├── sources_1 ├── imports │ ├── release1 │ │ ├── rx │ │ │ ├── decode.v │ │ │ ├── chnlbond.v │ │ │ ├── decodeb.v │ │ │ ├── decodeg.v │ │ │ ├── decoder.v │ │ │ ├── dvi_decoder.v │ │ │ ├── phsaligner.v │ │ │ ├── decode_terc4.v │ │ │ └── serdes_1_to_5_diff_data.v │ │ ├── tx │ │ │ ├── encode.v │ │ │ ├── encodeb.v │ │ │ ├── encodeg.v │ │ │ ├── encoder.v │ │ │ ├── serdes_n_to_1.v │ │ │ ├── dvi_encoder_top.v │ │ │ ├── encode_terc4.v │ │ │ ├── gbgen.v │ │ │ └── convert_30to15_fifo.v │ │ └── hdcp │ │ │ ├── diff_network.v │ │ │ ├── shuffle_network.v │ │ │ ├── fa_crypt8.v │ │ │ ├── alpha_scale.v │ │ │ ├── alpha_blend.v │ │ │ ├── fa_crypt.v │ │ │ ├── hdcp_lfsr.v │ │ │ └── hdcp_cipher.v │ └── common │ │ ├── DRAM16XN.v │ │ ├── sync_reset.v │ │ ├── pwm.v │ │ ├── data_island.v │ │ ├── boxtiming.v │ │ ├── i2c_slave_tb.v │ │ ├── i2c_snoop_tb.v │ │ ├── timing_detector.v │ │ ├── i2c_squash_tb.v │ │ └── i2c_snoop_edid.v └── ip │ ├── license.txt │ ├── clk_wiz_v3_1_0 │ ├── clkgendcm_720p60hz.v │ └── clkgendcm_720p60hz.xco │ └── fifo_generator_v7_2_0 │ ├── fifo_2kx18.xco │ └── fifo_2kx18.v ├── README └── constrs_1 └── imports └── release1 └── release1.ucf /sources_1/imports/release1/rx/decode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bunnie/netv-fpga/HEAD/sources_1/imports/release1/rx/decode.v -------------------------------------------------------------------------------- /sources_1/imports/release1/tx/encode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bunnie/netv-fpga/HEAD/sources_1/imports/release1/tx/encode.v -------------------------------------------------------------------------------- /sources_1/imports/release1/rx/chnlbond.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/bunnie/netv-fpga/HEAD/sources_1/imports/release1/rx/chnlbond.v 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/bunnie/netv-fpga/HEAD/sources_1/imports/release1/tx/dvi_encoder_top.v -------------------------------------------------------------------------------- /sources_1/ip/license.txt: -------------------------------------------------------------------------------- 1 | The files in this directory tree are auto-generated by the Xilinx IP Core 2 | Generator System. 3 | 4 | The configuration of the IP embodied in these files is the expression of 5 | Andrew "bunnie" Huang's thoughts and these thoughts are licensed in a 6 | CC-BY-SA 2.0 fashion. The copyright notice is located here instead of 7 | in the file, since the configuration files are stored in a machine- 8 | manipulated format that is not suitable for insertion of copyright notices. 9 | 10 | The generation of the IP from these configurations is guided by the requirements 11 | of Xilinx's IP Core Generator System. 12 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | Verilog code for the NeTV FPGA. Andrew "bunnie" Huang. 2 | 3 | Please pay attention to the version number embedded inside hdmi_overlay.v. This, along with the version notes, will inform you as to the latest status of the code. 4 | 5 | The code as checked-in is structured according to how the Xilinx ISE tools placed my code when using the PlanAhead flow. 6 | 7 | This was most recently compiled using ISE Design Suite 13.3 (as of May 2012). 8 | 9 | All of the code in here is licensed under a BSD license. Functional elements are licensed under an XL-1.0 license (patents awarded that use this code in any way are automatically irrevocably cross-licensed to me without limitation, and through that license I grant all parties that may use this code an automatic cross-license; likewise, any patents I may hold or be awarded on this code are automatically cross-licensed to you). Note there is no warranty for this code, express or implied. 10 | 11 | -------------------------------------------------------------------------------- /sources_1/imports/common/DRAM16XN.v: -------------------------------------------------------------------------------- 1 | // 2 | // Module: DRAM16XN 3 | // 4 | // Description: Distributed SelectRAM example 5 | // Dual Port 16 x N-bit 6 | // 7 | // Device: Spartan-3 Family 8 | //--------------------------------------------------------------------------------------- 9 | 10 | module DRAM16XN #(parameter data_width = 20) 11 | ( 12 | DATA_IN, 13 | ADDRESS, 14 | ADDRESS_DP, 15 | WRITE_EN, 16 | CLK, 17 | O_DATA_OUT, 18 | O_DATA_OUT_DP); 19 | 20 | input [data_width-1:0]DATA_IN; 21 | input [3:0] ADDRESS; 22 | input [3:0] ADDRESS_DP; 23 | input WRITE_EN; 24 | input CLK; 25 | 26 | output [data_width-1:0]O_DATA_OUT_DP; 27 | output [data_width-1:0]O_DATA_OUT; 28 | 29 | genvar i; 30 | generate 31 | for(i = 0 ; i < data_width ; i = i + 1) begin : dram16s 32 | RAM16X1D i_RAM16X1D_U( 33 | .D(DATA_IN[i]), //insert input signal 34 | .WE(WRITE_EN), //insert Write Enable signal 35 | .WCLK(CLK), //insert Write Clock signal 36 | .A0(ADDRESS[0]), //insert Address 0 signal port SPO 37 | .A1(ADDRESS[1]), //insert Address 1 signal port SPO 38 | .A2(ADDRESS[2]), //insert Address 2 signal port SPO 39 | .A3(ADDRESS[3]), //insert Address 3 signal port SPO 40 | .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO 41 | .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO 42 | .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO 43 | .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO 44 | .SPO(O_DATA_OUT[i]), //insert output signal SPO 45 | .DPO(O_DATA_OUT_DP[i]) //insert output signal DPO 46 | ); 47 | end 48 | endgenerate 49 | 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/diff_network.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | 27 | module diff_network ( 28 | input wire [6:0] i, 29 | output wire [6:0] o, 30 | input wire [6:0] k 31 | ); 32 | 33 | assign o[0] = k[0] ^ ^ i[1] ^ i[2] ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 34 | assign o[1] = k[1] ^ i[0] ^ ^ i[2] ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 35 | assign o[2] = k[2] ^ i[0] ^ i[1] ^ ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 36 | assign o[3] = k[3] ^ i[0] ^ i[1] ^ i[2] ^ ^ i[4] ^ i[5] ^ i[6]; 37 | assign o[4] = k[4] ^ i[0] ^ i[1] ^ i[2] ^ i[3] ^ ^ i[5] ^ i[6]; 38 | assign o[5] = k[5] ^ i[0] ^ i[1] ^ i[2] ^ i[3] ^ i[4] ^ ^ i[6]; 39 | assign o[6] = k[6] ^ i[0] ^ i[1] ^ i[2] ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 40 | 41 | endmodule // diff_network 42 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/shuffle_network.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | 27 | module shuffle_network ( 28 | input wire clk, 29 | input wire reset, 30 | input wire din, 31 | input wire sel, 32 | input wire advance, 33 | input wire init_iv, 34 | output wire dout 35 | ); 36 | 37 | reg a, b; 38 | 39 | always @(posedge clk or posedge reset) begin 40 | if( reset == 1 ) begin 41 | a <= 1'b0; 42 | b <= 1'b1; 43 | end else begin 44 | if( init_iv ) begin 45 | a <= 1'b0; 46 | b <= 1'b1; 47 | end else if( advance ) begin 48 | a <= sel ? din : b; 49 | b <= sel ? a : din; 50 | end else begin 51 | a <= a; 52 | b <= b; 53 | end 54 | end // else: !if( reset == 1 ) 55 | end // always @ (posedge clk or posedge reset) 56 | 57 | assign dout = sel ? b : a; 58 | 59 | endmodule // shuffle_network 60 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/fa_crypt8.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module fa_crypt8 ( 29 | input wire [7:0] key, // key bit 30 | input wire [7:0] hd, // hdmi data 31 | input wire [7:0] ld, // lcd data 32 | output wire [7:0] s, // sum out 33 | output wire ovf 34 | ); 35 | 36 | wire [7:0] carry; 37 | 38 | fa_crypt fa0 (.key(key[0]), .ci(1'b0), .hd(hd[0]), .ld(ld[0]), .co(carry[0]), .s(s[0]) ); 39 | fa_crypt fa1 (.key(key[1]), .ci(carry[0]), .hd(hd[1]), .ld(ld[1]), .co(carry[1]), .s(s[1]) ); 40 | fa_crypt fa2 (.key(key[2]), .ci(carry[1]), .hd(hd[2]), .ld(ld[2]), .co(carry[2]), .s(s[2]) ); 41 | fa_crypt fa3 (.key(key[3]), .ci(carry[2]), .hd(hd[3]), .ld(ld[3]), .co(carry[3]), .s(s[3]) ); 42 | fa_crypt fa4 (.key(key[4]), .ci(carry[3]), .hd(hd[4]), .ld(ld[4]), .co(carry[4]), .s(s[4]) ); 43 | fa_crypt fa5 (.key(key[5]), .ci(carry[4]), .hd(hd[5]), .ld(ld[5]), .co(carry[5]), .s(s[5]) ); 44 | fa_crypt fa6 (.key(key[6]), .ci(carry[5]), .hd(hd[6]), .ld(ld[6]), .co(carry[6]), .s(s[6]) ); 45 | fa_crypt fa7 (.key(key[7]), .ci(carry[6]), .hd(hd[7]), .ld(ld[7]), .co(carry[7]), .s(s[7]) ); 46 | 47 | assign ovf = carry[7]; 48 | 49 | endmodule // fa_crypt8 50 | 51 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/alpha_scale.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module alpha_scale ( 29 | input wire clk, 30 | input wire reset, 31 | input wire [2:0] code, 32 | input wire [7:0] din, 33 | output wire [7:0] dout 34 | ); 35 | 36 | reg [7:0] coef; 37 | wire [15:0] multval; 38 | 39 | // should be multiply by 1-alpha_vid value.... 40 | // setting 41 | // 000 1.0000000 42 | // 001 0.1000000 43 | // 010 0.1100000 44 | // 011 0.1110000 45 | // 100 0.1111000 46 | // 101 0.1111100 47 | // 110 0.1111110 48 | // 111 0.1111111 49 | 50 | always @(code) begin 51 | case(code) 52 | 3'b000: begin 53 | coef <= 8'h80; 54 | end 55 | 3'b001: begin 56 | coef <= 8'h40; 57 | end 58 | 3'b010: begin 59 | coef <= 8'h60; 60 | end 61 | 3'b011: begin 62 | coef <= 8'h70; 63 | end 64 | 3'b100: begin 65 | coef <= 8'h78; 66 | end 67 | 3'b101: begin 68 | coef <= 8'h7c; 69 | end 70 | 3'b110: begin 71 | coef <= 8'h7e; 72 | end 73 | 3'b111: begin 74 | coef <= 8'h7f; 75 | end 76 | endcase // case (code) 77 | end // always @ (code) 78 | 79 | assign multval = coef * din; 80 | 81 | assign dout[7:0] = multval[14:0] >> 7; 82 | 83 | endmodule // alpha_scale 84 | -------------------------------------------------------------------------------- /sources_1/imports/common/sync_reset.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////// 2 | // Copyright (c) 2012, Andrew "bunnie" Huang 3 | // (bunnie _aht_ bunniestudios "dote" com) 4 | // All rights reserved. 5 | // 6 | // Redistribution and use in source and binary forms, with or without 7 | // modification, are permitted provided that the following conditions are 8 | // met: 9 | // 10 | // Redistributions of source code must retain the above copyright 11 | // notice, this list of conditions and the following disclaimer. 12 | // Redistributions in binary form must reproduce the above copyright 13 | // notice, this list of conditions and the following disclaimer in 14 | // the documentation and/or other materials provided with the 15 | // distribution. 16 | // 17 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | // HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | //////////////////////////////////////////////// 29 | 30 | /// according to Xilinx WP272, all flip flops are reset to a "known value" 31 | /// by GSR. You're supposed to trust that. Of course, this "known value" 32 | /// isn't very explicitly stated, searching through the xilinx manuals 33 | /// it seems everything defaults to 0 except for stuff that's presetable. 34 | 35 | /// anyways, this module generates a local, synchronized reset based upon 36 | /// a global reset. The idea is to instantiate one of these near every 37 | /// terminal reset sink, so as to avoid loading down a global reset network. 38 | 39 | /// this should optimize utilization and speed a bit, and also allow the 40 | /// synthesizer to get more aggressive about using larger primitives 41 | 42 | ////////// 43 | // the input is the asychronous reset of interest 44 | // and the clock to synchronize it to 45 | // the output is a synchronized reset that is at least four clock cycles wide 46 | module sync_reset ( 47 | input wire glbl_reset, // async reset 48 | input wire clk, 49 | output wire reset 50 | ); 51 | 52 | wire [3:0] reschain; 53 | 54 | FDPE fdres0( .Q(reschain[0]), .C(clk), .CE(1'b1), .D(1'b0), .PRE(glbl_reset) ); 55 | FDPE fdres1( .Q(reschain[1]), .C(clk), .CE(1'b1), .D(reschain[0]), .PRE(glbl_reset) ); 56 | FDPE fdres2( .Q(reschain[2]), .C(clk), .CE(1'b1), .D(reschain[1]), .PRE(glbl_reset) ); 57 | FDPE fdres3( .Q(reschain[3]), .C(clk), .CE(1'b1), .D(reschain[2]), .PRE(glbl_reset) ); 58 | 59 | assign reset = reschain[3]; 60 | 61 | endmodule // sync_reset 62 | -------------------------------------------------------------------------------- /sources_1/imports/release1/rx/decode_terc4.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | 27 | `timescale 1 ps / 1ps 28 | 29 | module decode_terc4 ( 30 | input clkin, // pixel clock input 31 | input rstin, // async. reset input (active high) 32 | input [9:0] din, // data inputs: expect registered 33 | output reg [3:0] dout // data outputs 34 | ); 35 | reg [9:0] din_r; 36 | 37 | always @(posedge clkin or posedge rstin) begin 38 | if( rstin ) begin 39 | dout[3:0] <= 4'h0; 40 | din_r <= 10'b0; 41 | end else begin 42 | din_r <= din; 43 | case (din_r[9:0]) 44 | 10'b1010011100: dout[3:0] <= 4'b0000; 45 | 10'b1001100011: dout[3:0] <= 4'b0001; 46 | 10'b1011100100: dout[3:0] <= 4'b0010; 47 | 10'b1011100010: dout[3:0] <= 4'b0011; 48 | 10'b0101110001: dout[3:0] <= 4'b0100; 49 | 10'b0100011110: dout[3:0] <= 4'b0101; 50 | 10'b0110001110: dout[3:0] <= 4'b0110; 51 | 10'b0100111100: dout[3:0] <= 4'b0111; 52 | 10'b1011001100: dout[3:0] <= 4'b1000; 53 | 10'b0100111001: dout[3:0] <= 4'b1001; 54 | 10'b0110011100: dout[3:0] <= 4'b1010; 55 | 10'b1011000110: dout[3:0] <= 4'b1011; 56 | 10'b1010001110: dout[3:0] <= 4'b1100; 57 | 10'b1001110001: dout[3:0] <= 4'b1101; 58 | 10'b0101100011: dout[3:0] <= 4'b1110; 59 | 10'b1011000011: dout[3:0] <= 4'b1111; 60 | // no default to allow for maximum coding flexibility... 61 | endcase // case (din_q) 62 | end // else: !if( rstin ) 63 | end // always @ (posedge clkin or posedge rstin) 64 | 65 | endmodule // decode_terc4 66 | 67 | -------------------------------------------------------------------------------- /sources_1/imports/common/pwm.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | // this module does simple PWM modulation to create the "breathing" LED effect 27 | // 28 | 29 | `timescale 1 ns / 1 ps 30 | 31 | module pwm( 32 | input wire clk812k, // use clock from device DNA block, 812.5kHz 33 | input wire reset, 34 | output reg pwmout, 35 | input wire [11:0] bright, 36 | input wire [11:0] dim 37 | ); 38 | 39 | reg [9:0] pwm_count; 40 | reg pwmreg; 41 | reg [11:0] interpolate; 42 | reg countdn; 43 | wire [9:0] interp; 44 | 45 | always @(posedge clk812k) begin 46 | if( reset ) begin 47 | pwm_count <= 0; 48 | interpolate[11:0] <= dim[11:0]; 49 | countdn <= 0; 50 | end else begin 51 | if( interpolate[11:0] >= bright[11:0] ) begin 52 | countdn <= 1; 53 | end else if( interpolate[11:0] <= dim[11:0] ) begin 54 | countdn <= 0; 55 | end else begin 56 | countdn <= countdn; 57 | end 58 | 59 | if( pwm_count[9:0] == 10'h0 ) begin 60 | if( countdn == 1'b1 ) begin 61 | interpolate[11:0] <= interpolate[11:0] - 12'b1; 62 | end else begin 63 | interpolate[11:0] <= interpolate[11:0] + 12'b1; 64 | end 65 | end else begin 66 | interpolate[11:0] <= interpolate[11:0]; 67 | end 68 | 69 | pwm_count[9:0] <= pwm_count[9:0] + 10'b1; 70 | end 71 | 72 | pwmreg <= (pwm_count[9:0] < interp[9:0]); 73 | 74 | end // always @ (posedge clk812k or posedge reset) 75 | 76 | assign interp[9:0] = interpolate[11:2]; 77 | 78 | always @(posedge clk812k) begin 79 | // make it registered to ease up routing congestion to the edge 80 | pwmout <= !pwmreg; 81 | end 82 | 83 | endmodule // pwm 84 | -------------------------------------------------------------------------------- /sources_1/imports/common/data_island.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | 27 | // 28 | // data packet consists of 7 x 4 = 28 bytes + 4 bytes of parity 29 | // data header consists of 3 bytes + 1 byte of parity 30 | 31 | `timescale 1 ns / 1 ps 32 | 33 | module data_island ( 34 | input wire pclk; 35 | input wire reset; 36 | 37 | input wire [3:0] data_ch2; 38 | input wire [3:0] data_ch1; 39 | input wire data_header_ch0; 40 | input wire data_gb; 41 | input wire video_gb; 42 | 43 | output wire [7:0] packet_type; 44 | output wire [15:0] header_data; 45 | output wire [7:0] packet_data; // this is an 8 entry, 8-bit wide RAM 46 | input wire [2:0] packet_index; 47 | ); 48 | 49 | parameter RAM_WIDTH = ; 50 | parameter RAM_ADDR_BITS = ; 51 | 52 | (* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *) 53 | reg [RAM_WIDTH-1:0] [(2**RAM_ADDR_BITS)-1:0]; 54 | reg [RAM_WIDTH-1:0] , ; 55 | 56 | [RAM_ADDR_BITS-1:0] , ; 57 | [RAM_WIDTH-1:0] ; 58 | 59 | // The following code is only necessary if you wish to initialize the RAM 60 | // contents via an external file (use $readmemb for binary data) 61 | initial 62 | $readmemh("", , , ); 63 | 64 | always @(posedge ) begin 65 | if () begin 66 | if () 67 | [] <= ; 68 | <= []; 69 | end 70 | if () 71 | <= []; 72 | end 73 | 74 | endmodule // data_island 75 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/alpha_blend.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module alpha_blend( 29 | input wire clk, 30 | input wire reset, 31 | input wire [7:0] enc_b, 32 | input wire [7:0] enc_r, 33 | input wire [7:0] enc_g, 34 | input wire [2:0] alpha_vid, 35 | input wire alpha_en, 36 | input wire [7:0] lcd_b, 37 | input wire [7:0] lcd_r, 38 | input wire [7:0] lcd_g, 39 | input wire [23:0] cipher_stream, 40 | output wire [7:0] alpha_enc_b, 41 | output wire [7:0] alpha_enc_r, 42 | output wire [7:0] alpha_enc_g 43 | ); 44 | 45 | 46 | wire [7:0] enc_b_scaled; 47 | wire [7:0] enc_r_scaled; 48 | wire [7:0] enc_g_scaled; 49 | 50 | wire [7:0] enc_b_summed; 51 | wire [7:0] enc_r_summed; 52 | wire [7:0] enc_g_summed; 53 | 54 | assign enc_b_scaled = (enc_b >> alpha_vid) ^ (cipher_stream[7:0] ^ (cipher_stream[7:0] >> alpha_vid)); 55 | assign enc_g_scaled = (enc_g >> alpha_vid) ^ (cipher_stream[15:8] ^ (cipher_stream[15:8] >> alpha_vid)); 56 | assign enc_r_scaled = (enc_r >> alpha_vid) ^ (cipher_stream[23:16] ^ (cipher_stream[23:16] >> alpha_vid)); 57 | 58 | fa_crypt8 bCryptAdd( .key(cipher_stream[7:0]), .hd(enc_b_scaled), .ld(lcd_b), .s(enc_b_summed) ); 59 | fa_crypt8 gCryptAdd( .key(cipher_stream[15:8]), .hd(enc_g_scaled), .ld(lcd_g), .s(enc_g_summed) ); 60 | fa_crypt8 rCryptAdd( .key(cipher_stream[23:16]), .hd(enc_r_scaled), .ld(lcd_r), .s(enc_r_summed) ); 61 | 62 | assign alpha_enc_b = alpha_en ? enc_b_summed : (lcd_b ^ cipher_stream[7:0]); 63 | assign alpha_enc_g = alpha_en ? enc_g_summed : (lcd_g ^ cipher_stream[15:8]); 64 | assign alpha_enc_r = alpha_en ? enc_r_summed : (lcd_r ^ cipher_stream[23:16]); 65 | 66 | // temporary hack to just pass through, this will be replaced 67 | // assign alpha_enc_b = cipher_stream[7:0] ^ lcd_b[7:0]; 68 | // assign alpha_enc_g = cipher_stream[15:8] ^ lcd_g[7:0]; 69 | // assign alpha_enc_r = cipher_stream[23:16] ^ lcd_r[7:0]; 70 | 71 | endmodule // alpha_blend 72 | 73 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/fa_crypt.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module fa_crypt ( 29 | input wire key, // key bit 30 | input wire ci, // carry in 31 | input wire hd, // hdmi data 32 | input wire ld, // lcd data 33 | output reg co, // carry out 34 | output reg s // sum out 35 | ); 36 | 37 | always @(key or ci or hd or ld) begin 38 | case({key,ci,hd,ld}) 39 | 4'b0000: begin 40 | co = 0; 41 | s = 0; 42 | end 43 | 4'b0001: begin 44 | co = 0; 45 | s = 1; 46 | end 47 | 4'b0010: begin 48 | co = 0; 49 | s = 1; 50 | end 51 | 4'b0011: begin 52 | co = 1; 53 | s = 0; 54 | end 55 | 4'b0100: begin 56 | co = 0; 57 | s = 1; 58 | end 59 | 4'b0101: begin 60 | co = 1; 61 | s = 0; 62 | end 63 | 4'b0110: begin 64 | co = 1; 65 | s = 0; 66 | end 67 | 4'b0111: begin 68 | co = 1; 69 | s = 1; 70 | end 71 | 4'b1000: begin 72 | co = 0; 73 | s = 0; 74 | end 75 | 4'b1001: begin 76 | co = 1; 77 | s = 1; 78 | end 79 | 4'b1010: begin 80 | co = 0; 81 | s = 1; 82 | end 83 | 4'b1011: begin 84 | co = 0; 85 | s = 0; 86 | end 87 | 4'b1100: begin 88 | co = 1; 89 | s = 1; 90 | end 91 | 4'b1101: begin 92 | co = 1; 93 | s = 0; 94 | end 95 | 4'b1110: begin 96 | co = 0; 97 | s = 0; 98 | end 99 | 4'b1111: begin 100 | co = 1; 101 | s = 1; 102 | end 103 | endcase // case ({key,ci,hd,ld}) 104 | end // always @ (key or ci or hd or ld) 105 | 106 | endmodule // fa_crypt 107 | 108 | `ifdef NONEXISTENT_FOO 109 | K = key 110 | C = Carry In 111 | S = Source Data 112 | D = Output Data 113 | 114 | K C S D C O 115 | 116 | 0 0 0 0 0 0 117 | 0 0 0 1 0 1 118 | 0 0 1 0 0 1 119 | 0 0 1 1 1 0 120 | 121 | 0 1 0 0 0 1 122 | 0 1 0 1 1 0 123 | 0 1 1 0 1 0 124 | 0 1 1 1 1 1 125 | 126 | 1 0 0 0 0 0 127 | 1 0 0 1 1 1 128 | 1 0 1 0 0 1 129 | 1 0 1 1 0 0 130 | 131 | 1 1 0 0 1 1 132 | 1 1 0 1 1 0 133 | 1 1 1 0 0 0 134 | 1 1 1 1 1 1 135 | 136 | Co:MUX = (K ^ S ^ D)#O6# ? Ci : (K ^ S & D)#O5# 137 | `endif 138 | -------------------------------------------------------------------------------- /sources_1/imports/release1/tx/encode_terc4.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | `timescale 1 ps / 1ps 27 | 28 | module encode_terc4 ( 29 | input clkin, // pixel clock input 30 | input rstin, // async. reset input (active high) 31 | input [3:0] din, // data inputs: expect registered 32 | output reg [9:0] dout, // data outputs 33 | input dat_gb 34 | ); 35 | 36 | reg [3:0] din_q; // extra stages to match pipeline delays 37 | reg [9:0] q_m_reg; // extra stages to match pipeline delays 38 | 39 | reg dat_gb_q, dat_gb_reg; 40 | 41 | always @(posedge clkin or posedge rstin) begin 42 | if(rstin) begin 43 | din_q <= 4'b0; 44 | dout <= 10'b0; 45 | dat_gb_q <= 1'b0; 46 | dat_gb_reg <= 1'b0; 47 | end else begin 48 | din_q <= din; 49 | dat_gb_q <= dat_gb; 50 | dat_gb_reg <= dat_gb_q; 51 | 52 | if( dat_gb_reg ) begin 53 | dout <= 10'b0100110011; 54 | end else begin 55 | dout <= q_m_reg; 56 | end 57 | end // else: !if(rstin) 58 | end // always @ (posedge clkin or posedge rstin) 59 | 60 | always @(posedge clkin or posedge rstin) begin 61 | if( rstin ) begin 62 | q_m_reg[9:0] <= 10'h0; 63 | end else begin 64 | case ({din_q[3], din_q[2], din_q[1], din_q[0]}) 65 | 4'b0000: q_m_reg[9:0] <= 10'b1010011100; 66 | 4'b0001: q_m_reg[9:0] <= 10'b1001100011; 67 | 4'b0010: q_m_reg[9:0] <= 10'b1011100100; 68 | 4'b0011: q_m_reg[9:0] <= 10'b1011100010; 69 | 4'b0100: q_m_reg[9:0] <= 10'b0101110001; 70 | 4'b0101: q_m_reg[9:0] <= 10'b0100011110; 71 | 4'b0110: q_m_reg[9:0] <= 10'b0110001110; 72 | 4'b0111: q_m_reg[9:0] <= 10'b0100111100; 73 | 4'b1000: q_m_reg[9:0] <= 10'b1011001100; 74 | 4'b1001: q_m_reg[9:0] <= 10'b0100111001; 75 | 4'b1010: q_m_reg[9:0] <= 10'b0110011100; 76 | 4'b1011: q_m_reg[9:0] <= 10'b1011000110; 77 | 4'b1100: q_m_reg[9:0] <= 10'b1010001110; 78 | 4'b1101: q_m_reg[9:0] <= 10'b1001110001; 79 | 4'b1110: q_m_reg[9:0] <= 10'b0101100011; 80 | 4'b1111: q_m_reg[9:0] <= 10'b1011000011; 81 | // no default since all cases are covered in this ROM. 82 | endcase // case ({din_q[3], din_q[2], din_q[1], din_q[0]}) 83 | end // else: !if( rstin ) 84 | end // always @ (posedge clkin or posedge rstin) 85 | 86 | endmodule // encode_terc4 87 | -------------------------------------------------------------------------------- /sources_1/imports/release1/tx/gbgen.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | module gbgen ( 27 | input pclk, 28 | input rstin, 29 | input vsync, 30 | input hsync, 31 | input sync_pol, 32 | input de, 33 | 34 | output gb, 35 | output [3:0] code 36 | ); 37 | 38 | reg [11:0] hpixel; 39 | wire [11:0] papos; 40 | reg [11:0] depos; 41 | 42 | reg hsync_v; // active when high 43 | reg hsync_v2; 44 | reg vsync_v; 45 | reg vsync_v2; 46 | reg de_d; 47 | 48 | wire hsync_rising; 49 | wire vsync_rising; 50 | 51 | wire pa; 52 | 53 | always @(posedge pclk) begin 54 | if( rstin ) begin 55 | hpixel <= 0; 56 | depos <= 0; 57 | end else begin 58 | if( hsync_rising ) begin 59 | hpixel <= 0; 60 | end else begin 61 | hpixel <= hpixel + 12'b1; 62 | end 63 | 64 | if( de && !de_d ) begin // de is rising 65 | depos <= hpixel; 66 | end else begin 67 | depos <= depos; 68 | end 69 | end // else: !if( rstin ) 70 | end // always @ (posedge pclk) 71 | 72 | assign papos = depos - 12'd10; // note: decimal 10, not binary 10 73 | // 0 1 2 3 4 5 6 7 74 | // | | | | | | | | 75 | // ct pa gb gb v v v v 76 | // 77 | // depos = 4 78 | // gbpos = 2 79 | 80 | assign gb = (hpixel >= (depos - 12'd2)) && (hpixel < depos); 81 | assign pa = (hpixel >= papos) && (hpixel < depos); 82 | 83 | assign code[3:1] = 3'b0; // these never change 84 | assign code[0] = pa; // this is the only bit that changes on pre-amble 85 | 86 | always @(posedge pclk or posedge rstin) begin 87 | if( rstin ) begin 88 | hsync_v <= 0; 89 | vsync_v <= 0; 90 | 91 | hsync_v2 <= 0; 92 | vsync_v2 <= 0; 93 | de_d <= 0; 94 | end else begin 95 | hsync_v <= hsync ^ !sync_pol; 96 | vsync_v <= vsync ^ !sync_pol; 97 | 98 | de_d <= de; 99 | hsync_v2 <= hsync_v; // just a delayed version 100 | vsync_v2 <= vsync_v; 101 | end // else: !if( rstin ) 102 | end // always @ (posedge pclk or posedge rstin) 103 | assign hsync_rising = hsync_v & !hsync_v2; 104 | assign vsync_rising = vsync_v & !vsync_v2; 105 | 106 | endmodule // gbgen 107 | -------------------------------------------------------------------------------- /sources_1/imports/common/boxtiming.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | `timescale 1 ns / 1ps 27 | 28 | module boxtiming ( 29 | input wire pclk, 30 | input wire rstin, 31 | input wire vsync, 32 | input wire hsync, 33 | input wire sync_pol, // 0 means active 0, 1 means active 1 34 | input wire de, 35 | input wire cv, 36 | input wire [11:0] hpos, 37 | input wire [11:0] hsize, 38 | input wire [11:0] vpos, 39 | input wire [11:0] vsize, 40 | output reg box_active 41 | ); 42 | 43 | reg [11:0] hcount; 44 | reg [11:0] vcount; 45 | 46 | reg hsync_v; // active when high 47 | reg hsync_v2; 48 | reg vsync_v; 49 | reg vsync_v2; 50 | reg de_d; 51 | 52 | reg active; 53 | 54 | wire hsync_rising; 55 | wire vsync_rising; 56 | wire de_rising; 57 | wire de_falling; 58 | 59 | always @(posedge pclk or posedge rstin) begin 60 | if( rstin ) begin 61 | hsync_v <= 0; 62 | vsync_v <= 0; 63 | 64 | hsync_v2 <= 0; 65 | vsync_v2 <= 0; 66 | 67 | de_d <= 0; 68 | end else begin 69 | de_d <= de; 70 | 71 | if( cv ) begin 72 | hsync_v <= hsync ^ !sync_pol; 73 | vsync_v <= vsync ^ !sync_pol; 74 | end else begin 75 | hsync_v <= hsync_v; 76 | vsync_v <= vsync_v; 77 | end 78 | 79 | hsync_v2 <= hsync_v; // just a delayed version 80 | vsync_v2 <= vsync_v; 81 | end // else: !if( rstin ) 82 | end // always @ (posedge pclk or posedge rstin) 83 | assign hsync_rising = hsync_v & !hsync_v2; 84 | assign vsync_rising = vsync_v & !vsync_v2; 85 | assign de_rising = de & !de_d; 86 | assign de_falling = !de & de_d; 87 | 88 | always @(posedge pclk or posedge rstin) begin 89 | if( rstin ) begin 90 | hcount <= 0; 91 | end else begin 92 | if( de_rising ) begin 93 | hcount <= 12'b0000_0000_0000; 94 | end else begin 95 | if( de ) begin 96 | hcount <= hcount + 12'b0000_0000_0001; 97 | end else begin 98 | hcount <= hcount; 99 | end 100 | end 101 | end // else: !if( rstin ) 102 | end // always @ (posedge pclk or posedge rstin) 103 | 104 | always @(posedge pclk or posedge rstin) begin 105 | if( rstin ) begin 106 | vcount <= 0; 107 | end else begin 108 | if( vsync_rising ) begin 109 | vcount <= 12'b0000_0000_0000; 110 | end else begin 111 | if( de_falling ) begin // this may be a bug but I think it's worked around elsewhere 112 | vcount <= vcount + 12'b0000_0000_0001; 113 | end else begin 114 | vcount <= vcount; 115 | end 116 | end 117 | end // else: !if( rstin ) 118 | end // always @ (posedge pclk or posedge rstin) 119 | 120 | always @(posedge pclk or posedge rstin) begin 121 | if( rstin ) begin 122 | active <= 0; 123 | end else begin 124 | if( (hcount >= hpos) && (hcount < (hpos + hsize)) && 125 | (vcount >= vpos) && (vcount < (vpos + vsize)) ) begin 126 | active <= 1'b1; 127 | end else begin 128 | active <= 1'b0; 129 | end 130 | end 131 | 132 | box_active <= active; 133 | end // always @ (posedge pclk or posedge rstin) 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /sources_1/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v: -------------------------------------------------------------------------------- 1 | // file: clkgendcm_720p60hz.v 2 | // 3 | // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // 720p60hzclocksource 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // CLK_OUT1 74.287 0.000 N/A 200.000 N/A 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Input Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // primary 26 0.010 64 | 65 | `timescale 1ps/1ps 66 | 67 | (* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *) 68 | module clkgendcm_720p60hz 69 | (// Clock in ports 70 | input CLK_IN1, 71 | // Clock out ports 72 | output CLK_OUT1, 73 | // Status and control signals 74 | input RESET, 75 | output LOCKED 76 | ); 77 | 78 | // Input buffering 79 | //------------------------------------ 80 | assign clkin1 = CLK_IN1; 81 | 82 | 83 | // Clocking primitive 84 | //------------------------------------ 85 | // Instantiation of the DCM primitive 86 | // * Unused inputs are tied off 87 | // * Unused outputs are labeled unused 88 | wire psdone_unused; 89 | wire locked_int; 90 | wire [2:1] status_int; 91 | wire clkfx; 92 | wire clkfx180_unused; 93 | wire clkfxdv_unused; 94 | 95 | DCM_CLKGEN 96 | #(.CLKFXDV_DIVIDE (2), 97 | .CLKFX_DIVIDE (7), 98 | .CLKFX_MULTIPLY (20), 99 | .SPREAD_SPECTRUM ("NONE"), 100 | .STARTUP_WAIT ("FALSE"), 101 | .CLKIN_PERIOD (38.461), 102 | .CLKFX_MD_MAX (2.8571)) 103 | dcm_clkgen_inst 104 | // Input clock 105 | (.CLKIN (clkin1), 106 | // Output clocks 107 | .CLKFX (clkfx), 108 | .CLKFX180 (clkfx180_unused), 109 | .CLKFXDV (clkfxdv_unused), 110 | // Ports for dynamic reconfiguration 111 | .PROGCLK (1'b0), 112 | .PROGDATA (PROGDATA), 113 | .PROGEN (PROGEN), 114 | .PROGDONE (progdone_unused), 115 | // Other control and status signals 116 | .FREEZEDCM (1'b0), 117 | .LOCKED (locked_int), 118 | .STATUS (status_int), 119 | .RST (RESET)); 120 | 121 | assign LOCKED = locked_int; 122 | 123 | // Output buffering 124 | //----------------------------------- 125 | 126 | BUFG clkout1_buf 127 | (.O (CLK_OUT1), 128 | .I (clkfx)); 129 | 130 | 131 | 132 | 133 | endmodule 134 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/hdcp_lfsr.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | // lfsr module for hdcp cipher 30 | module hdcp_lfsr( 31 | input wire clk, 32 | input wire reset, // this is just a low-level reset 33 | 34 | input wire [55:0] iv, // initial values 35 | 36 | input wire init_iv, // load initial values 37 | input wire advance, // advance state one cycle 38 | output wire onebit // my one-bit output 39 | ); 40 | 41 | reg [12:0] lfsr0; 42 | reg [13:0] lfsr1; 43 | reg [15:0] lfsr2; 44 | reg [16:0] lfsr3; 45 | 46 | wire [3:0] comb_tap0; 47 | wire [3:0] comb_tap1; 48 | wire [3:0] comb_tap2; 49 | 50 | always @(posedge clk or posedge reset) begin 51 | if( reset == 1 ) begin 52 | lfsr0 <= 13'b0; 53 | lfsr1 <= 14'b0; 54 | lfsr2 <= 16'b0; 55 | lfsr3 <= 17'b0; 56 | end else begin 57 | if( init_iv ) begin 58 | // assume bit-offsets start from 0 59 | lfsr0[12:0] <= {~iv[6],iv[11:0]}; 60 | lfsr1[13:0] <= {~iv[18],iv[24:12]}; 61 | lfsr2[15:0] <= {~iv[32],iv[39:25]}; 62 | lfsr3[16:0] <= {~iv[47],iv[55:40]}; 63 | end else if( advance ) begin 64 | // 13 11 9 5 65 | // 12 10 8 4 66 | lfsr0[0 ] <= lfsr0[4] ^ lfsr0[8] ^ lfsr0[10] ^ lfsr0[12]; 67 | lfsr0[1 ] <= lfsr0[0 ]; 68 | lfsr0[2 ] <= lfsr0[1 ]; 69 | lfsr0[3 ] <= lfsr0[2 ]; 70 | lfsr0[4 ] <= lfsr0[3 ]; 71 | lfsr0[5 ] <= lfsr0[4 ]; 72 | lfsr0[6 ] <= lfsr0[5 ]; 73 | lfsr0[7 ] <= lfsr0[6 ]; 74 | lfsr0[8 ] <= lfsr0[7 ]; 75 | lfsr0[9 ] <= lfsr0[8 ]; 76 | lfsr0[10] <= lfsr0[9 ]; 77 | lfsr0[11] <= lfsr0[10]; 78 | lfsr0[12] <= lfsr0[11]; 79 | 80 | //4 6 7 10 11 14 81 | //3 5 6 9 10 13 82 | lfsr1[0 ] <= lfsr1[3] ^ lfsr1[5] ^ lfsr1[6] ^ lfsr1[9] ^ lfsr1[10] ^ lfsr1[13]; 83 | lfsr1[1 ] <= lfsr1[0 ]; 84 | lfsr1[2 ] <= lfsr1[1 ]; 85 | lfsr1[3 ] <= lfsr1[2 ]; 86 | lfsr1[4 ] <= lfsr1[3 ]; 87 | lfsr1[5 ] <= lfsr1[4 ]; 88 | lfsr1[6 ] <= lfsr1[5 ]; 89 | lfsr1[7 ] <= lfsr1[6 ]; 90 | lfsr1[8 ] <= lfsr1[7 ]; 91 | lfsr1[9 ] <= lfsr1[8 ]; 92 | lfsr1[10] <= lfsr1[9 ]; 93 | lfsr1[11] <= lfsr1[10]; 94 | lfsr1[12] <= lfsr1[11]; 95 | lfsr1[13] <= lfsr1[12]; 96 | 97 | //5 7 8 12 15 16 98 | //4 6 7 11 14 15 99 | lfsr2[0 ] <= lfsr2[4] ^ lfsr2[6] ^ lfsr2[7] ^ lfsr2[11] ^ lfsr2[14] ^ lfsr2[15]; 100 | lfsr2[1 ] <= lfsr2[0 ]; 101 | lfsr2[2 ] <= lfsr2[1 ]; 102 | lfsr2[3 ] <= lfsr2[2 ]; 103 | lfsr2[4 ] <= lfsr2[3 ]; 104 | lfsr2[5 ] <= lfsr2[4 ]; 105 | lfsr2[6 ] <= lfsr2[5 ]; 106 | lfsr2[7 ] <= lfsr2[6 ]; 107 | lfsr2[8 ] <= lfsr2[7 ]; 108 | lfsr2[9 ] <= lfsr2[8 ]; 109 | lfsr2[10] <= lfsr2[9 ]; 110 | lfsr2[11] <= lfsr2[10]; 111 | lfsr2[12] <= lfsr2[11]; 112 | lfsr2[13] <= lfsr2[12]; 113 | lfsr2[14] <= lfsr2[13]; 114 | lfsr2[15] <= lfsr2[14]; 115 | 116 | //5 11 15 17 117 | //4 10 14 16 118 | lfsr3[0 ] <= lfsr3[4] ^ lfsr3[10] ^ lfsr3[14] ^ lfsr3[16]; 119 | lfsr3[1 ] <= lfsr3[0 ]; 120 | lfsr3[2 ] <= lfsr3[1 ]; 121 | lfsr3[3 ] <= lfsr3[2 ]; 122 | lfsr3[4 ] <= lfsr3[3 ]; 123 | lfsr3[5 ] <= lfsr3[4 ]; 124 | lfsr3[6 ] <= lfsr3[5 ]; 125 | lfsr3[7 ] <= lfsr3[6 ]; 126 | lfsr3[8 ] <= lfsr3[7 ]; 127 | lfsr3[9 ] <= lfsr3[8 ]; 128 | lfsr3[10] <= lfsr3[9 ]; 129 | lfsr3[11] <= lfsr3[10]; 130 | lfsr3[12] <= lfsr3[11]; 131 | lfsr3[13] <= lfsr3[12]; 132 | lfsr3[14] <= lfsr3[13]; 133 | lfsr3[15] <= lfsr3[14]; 134 | lfsr3[16] <= lfsr3[15]; 135 | end else begin 136 | // hold state 137 | lfsr0 <= lfsr0; 138 | lfsr1 <= lfsr1; 139 | lfsr2 <= lfsr2; 140 | lfsr3 <= lfsr3; 141 | end 142 | end // else: !if( reset == 1 ) 143 | end // always @ (posedge clk or posedge reset) 144 | 145 | assign comb_tap0[0] = lfsr0[3]; 146 | assign comb_tap0[1] = lfsr1[4]; 147 | assign comb_tap0[2] = lfsr2[5]; 148 | assign comb_tap0[3] = lfsr3[5]; 149 | 150 | assign comb_tap1[0] = lfsr0[7]; 151 | assign comb_tap1[1] = lfsr1[8]; 152 | assign comb_tap1[2] = lfsr2[9]; 153 | assign comb_tap1[3] = lfsr3[11]; 154 | 155 | assign comb_tap2[0] = lfsr0[12]; 156 | assign comb_tap2[1] = lfsr1[13]; 157 | assign comb_tap2[2] = lfsr2[15]; 158 | assign comb_tap2[3] = lfsr3[16]; 159 | 160 | wire [3:0] sh_dout; 161 | shuffle_network sh0 ( .clk(clk), .reset(reset), 162 | .din(comb_tap0[0] ^ comb_tap0[1] ^ comb_tap0[2] ^ comb_tap0[3]), 163 | .sel(comb_tap1[0]), 164 | .advance(advance), 165 | .init_iv(init_iv), 166 | .dout(sh_dout[0]) 167 | ); 168 | 169 | shuffle_network sh1 ( .clk(clk), .reset(reset), 170 | .din(sh_dout[0]), 171 | .sel(comb_tap1[1]), 172 | .advance(advance), 173 | .init_iv(init_iv), 174 | .dout(sh_dout[1]) 175 | ); 176 | 177 | shuffle_network sh2 ( .clk(clk), .reset(reset), 178 | .din(sh_dout[1]), 179 | .sel(comb_tap1[2]), 180 | .advance(advance), 181 | .init_iv(init_iv), 182 | .dout(sh_dout[2]) 183 | ); 184 | 185 | shuffle_network sh3 ( .clk(clk), .reset(reset), 186 | .din(sh_dout[2]), 187 | .sel(comb_tap1[3]), 188 | .advance(advance), 189 | .init_iv(init_iv), 190 | .dout(sh_dout[3]) 191 | ); 192 | 193 | assign onebit = sh_dout[3] ^ comb_tap2[0] ^ comb_tap2[1] ^ comb_tap2[2] ^ comb_tap2[3]; 194 | 195 | endmodule // hdcp_lfsr 196 | 197 | -------------------------------------------------------------------------------- /sources_1/imports/release1/tx/convert_30to15_fifo.v: -------------------------------------------------------------------------------- 1 | module convert_30to15_fifo( 2 | input wire rst, // reset 3 | input wire clk, // clock input 4 | input wire clkx2, // 2x clock input 5 | input wire [29:0] datain, // input data for 2:1 serialisation 6 | output wire [14:0] dataout); // 5-bit data out 7 | 8 | //////////////////////////////////////////////////// 9 | // Here we instantiate a 16x10 Dual Port RAM 10 | // and fill first it with data aligned to 11 | // clk domain 12 | //////////////////////////////////////////////////// 13 | wire [3:0] wa; // RAM read address 14 | reg [3:0] wa_d; // RAM read address 15 | wire [3:0] ra; // RAM read address 16 | reg [3:0] ra_d; // RAM read address 17 | wire [29:0] dataint; // RAM output 18 | 19 | parameter ADDR0 = 4'b0000; 20 | parameter ADDR1 = 4'b0001; 21 | parameter ADDR2 = 4'b0010; 22 | parameter ADDR3 = 4'b0011; 23 | parameter ADDR4 = 4'b0100; 24 | parameter ADDR5 = 4'b0101; 25 | parameter ADDR6 = 4'b0110; 26 | parameter ADDR7 = 4'b0111; 27 | parameter ADDR8 = 4'b1000; 28 | parameter ADDR9 = 4'b1001; 29 | parameter ADDR10 = 4'b1010; 30 | parameter ADDR11 = 4'b1011; 31 | parameter ADDR12 = 4'b1100; 32 | parameter ADDR13 = 4'b1101; 33 | parameter ADDR14 = 4'b1110; 34 | parameter ADDR15 = 4'b1111; 35 | 36 | always@(wa) begin 37 | case (wa) 38 | ADDR0 : wa_d = ADDR1 ; 39 | ADDR1 : wa_d = ADDR2 ; 40 | ADDR2 : wa_d = ADDR3 ; 41 | ADDR3 : wa_d = ADDR4 ; 42 | ADDR4 : wa_d = ADDR5 ; 43 | ADDR5 : wa_d = ADDR6 ; 44 | ADDR6 : wa_d = ADDR7 ; 45 | ADDR7 : wa_d = ADDR8 ; 46 | ADDR8 : wa_d = ADDR9 ; 47 | ADDR9 : wa_d = ADDR10; 48 | ADDR10 : wa_d = ADDR11; 49 | ADDR11 : wa_d = ADDR12; 50 | ADDR12 : wa_d = ADDR13; 51 | ADDR13 : wa_d = ADDR14; 52 | ADDR14 : wa_d = ADDR15; 53 | default : wa_d = ADDR0; 54 | endcase 55 | end 56 | 57 | FDC fdc_wa0 (.C(clk), .D(wa_d[0]), .CLR(rst), .Q(wa[0])); 58 | FDC fdc_wa1 (.C(clk), .D(wa_d[1]), .CLR(rst), .Q(wa[1])); 59 | FDC fdc_wa2 (.C(clk), .D(wa_d[2]), .CLR(rst), .Q(wa[2])); 60 | FDC fdc_wa3 (.C(clk), .D(wa_d[3]), .CLR(rst), .Q(wa[3])); 61 | 62 | //Dual Port fifo to bridge data from clk to clkx2 63 | DRAM16XN #(.data_width(30)) 64 | fifo_u ( 65 | .DATA_IN(datain), 66 | .ADDRESS(wa), 67 | .ADDRESS_DP(ra), 68 | .WRITE_EN(1'b1), 69 | .CLK(clk), 70 | .O_DATA_OUT(), 71 | .O_DATA_OUT_DP(dataint)); 72 | 73 | ///////////////////////////////////////////////////////////////// 74 | // Here starts clk2x domain for fifo read out 75 | // FIFO read is set to be once every 2 cycles of clk2x in order 76 | // to keep up pace with the fifo write speed 77 | // Also FIFO read reset is delayed a bit in order to avoid 78 | // underflow. 79 | ///////////////////////////////////////////////////////////////// 80 | 81 | always@(ra) begin 82 | case (ra) 83 | ADDR0 : ra_d = ADDR1 ; 84 | ADDR1 : ra_d = ADDR2 ; 85 | ADDR2 : ra_d = ADDR3 ; 86 | ADDR3 : ra_d = ADDR4 ; 87 | ADDR4 : ra_d = ADDR5 ; 88 | ADDR5 : ra_d = ADDR6 ; 89 | ADDR6 : ra_d = ADDR7 ; 90 | ADDR7 : ra_d = ADDR8 ; 91 | ADDR8 : ra_d = ADDR9 ; 92 | ADDR9 : ra_d = ADDR10; 93 | ADDR10 : ra_d = ADDR11; 94 | ADDR11 : ra_d = ADDR12; 95 | ADDR12 : ra_d = ADDR13; 96 | ADDR13 : ra_d = ADDR14; 97 | ADDR14 : ra_d = ADDR15; 98 | default : ra_d = ADDR0; 99 | endcase 100 | end 101 | 102 | wire rstsync, rstsync_q, rstp; 103 | (* ASYNC_REG = "TRUE" *) FDP fdp_rst (.C(clkx2), .D(rst), .PRE(rst), .Q(rstsync)); 104 | 105 | FD fd_rstsync (.C(clkx2), .D(rstsync), .Q(rstsync_q)); 106 | FD fd_rstp (.C(clkx2), .D(rstsync_q), .Q(rstp)); 107 | 108 | wire sync; 109 | FDR sync_gen (.Q (sync), .C (clkx2), .R(rstp), .D(~sync)); 110 | 111 | FDRE fdc_ra0 (.C(clkx2), .D(ra_d[0]), .R(rstp), .CE(sync), .Q(ra[0])); 112 | FDRE fdc_ra1 (.C(clkx2), .D(ra_d[1]), .R(rstp), .CE(sync), .Q(ra[1])); 113 | FDRE fdc_ra2 (.C(clkx2), .D(ra_d[2]), .R(rstp), .CE(sync), .Q(ra[2])); 114 | FDRE fdc_ra3 (.C(clkx2), .D(ra_d[3]), .R(rstp), .CE(sync), .Q(ra[3])); 115 | 116 | wire [29:0] db; 117 | 118 | FDE fd_db0 (.C(clkx2), .D(dataint[0]), .CE(sync), .Q(db[0])); 119 | FDE fd_db1 (.C(clkx2), .D(dataint[1]), .CE(sync), .Q(db[1])); 120 | FDE fd_db2 (.C(clkx2), .D(dataint[2]), .CE(sync), .Q(db[2])); 121 | FDE fd_db3 (.C(clkx2), .D(dataint[3]), .CE(sync), .Q(db[3])); 122 | FDE fd_db4 (.C(clkx2), .D(dataint[4]), .CE(sync), .Q(db[4])); 123 | FDE fd_db5 (.C(clkx2), .D(dataint[5]), .CE(sync), .Q(db[5])); 124 | FDE fd_db6 (.C(clkx2), .D(dataint[6]), .CE(sync), .Q(db[6])); 125 | FDE fd_db7 (.C(clkx2), .D(dataint[7]), .CE(sync), .Q(db[7])); 126 | FDE fd_db8 (.C(clkx2), .D(dataint[8]), .CE(sync), .Q(db[8])); 127 | FDE fd_db9 (.C(clkx2), .D(dataint[9]), .CE(sync), .Q(db[9])); 128 | FDE fd_db10 (.C(clkx2), .D(dataint[10]), .CE(sync), .Q(db[10])); 129 | FDE fd_db11 (.C(clkx2), .D(dataint[11]), .CE(sync), .Q(db[11])); 130 | FDE fd_db12 (.C(clkx2), .D(dataint[12]), .CE(sync), .Q(db[12])); 131 | FDE fd_db13 (.C(clkx2), .D(dataint[13]), .CE(sync), .Q(db[13])); 132 | FDE fd_db14 (.C(clkx2), .D(dataint[14]), .CE(sync), .Q(db[14])); 133 | FDE fd_db15 (.C(clkx2), .D(dataint[15]), .CE(sync), .Q(db[15])); 134 | FDE fd_db16 (.C(clkx2), .D(dataint[16]), .CE(sync), .Q(db[16])); 135 | FDE fd_db17 (.C(clkx2), .D(dataint[17]), .CE(sync), .Q(db[17])); 136 | FDE fd_db18 (.C(clkx2), .D(dataint[18]), .CE(sync), .Q(db[18])); 137 | FDE fd_db19 (.C(clkx2), .D(dataint[19]), .CE(sync), .Q(db[19])); 138 | FDE fd_db20 (.C(clkx2), .D(dataint[20]), .CE(sync), .Q(db[20])); 139 | FDE fd_db21 (.C(clkx2), .D(dataint[21]), .CE(sync), .Q(db[21])); 140 | FDE fd_db22 (.C(clkx2), .D(dataint[22]), .CE(sync), .Q(db[22])); 141 | FDE fd_db23 (.C(clkx2), .D(dataint[23]), .CE(sync), .Q(db[23])); 142 | FDE fd_db24 (.C(clkx2), .D(dataint[24]), .CE(sync), .Q(db[24])); 143 | FDE fd_db25 (.C(clkx2), .D(dataint[25]), .CE(sync), .Q(db[25])); 144 | FDE fd_db26 (.C(clkx2), .D(dataint[26]), .CE(sync), .Q(db[26])); 145 | FDE fd_db27 (.C(clkx2), .D(dataint[27]), .CE(sync), .Q(db[27])); 146 | FDE fd_db28 (.C(clkx2), .D(dataint[28]), .CE(sync), .Q(db[28])); 147 | FDE fd_db29 (.C(clkx2), .D(dataint[29]), .CE(sync), .Q(db[29])); 148 | 149 | wire [14:0] mux; 150 | assign mux = (~sync) ? db[14:0] : db[29:15]; 151 | 152 | FD fd_out0 (.C(clkx2), .D(mux[0]), .Q(dataout[0])); 153 | FD fd_out1 (.C(clkx2), .D(mux[1]), .Q(dataout[1])); 154 | FD fd_out2 (.C(clkx2), .D(mux[2]), .Q(dataout[2])); 155 | FD fd_out3 (.C(clkx2), .D(mux[3]), .Q(dataout[3])); 156 | FD fd_out4 (.C(clkx2), .D(mux[4]), .Q(dataout[4])); 157 | FD fd_out5 (.C(clkx2), .D(mux[5]), .Q(dataout[5])); 158 | FD fd_out6 (.C(clkx2), .D(mux[6]), .Q(dataout[6])); 159 | FD fd_out7 (.C(clkx2), .D(mux[7]), .Q(dataout[7])); 160 | FD fd_out8 (.C(clkx2), .D(mux[8]), .Q(dataout[8])); 161 | FD fd_out9 (.C(clkx2), .D(mux[9]), .Q(dataout[9])); 162 | FD fd_out10 (.C(clkx2), .D(mux[10]), .Q(dataout[10])); 163 | FD fd_out11 (.C(clkx2), .D(mux[11]), .Q(dataout[11])); 164 | FD fd_out12 (.C(clkx2), .D(mux[12]), .Q(dataout[12])); 165 | FD fd_out13 (.C(clkx2), .D(mux[13]), .Q(dataout[13])); 166 | FD fd_out14 (.C(clkx2), .D(mux[14]), .Q(dataout[14])); 167 | 168 | endmodule 169 | -------------------------------------------------------------------------------- /sources_1/ip/fifo_generator_v7_2_0/fifo_2kx18.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.1 4 | # Date: Tue Aug 09 21:46:42 2011 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = false 17 | SET asysymbol = true 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = false 20 | SET designentry = Verilog 21 | SET device = xc6slx9 22 | SET devicefamily = spartan6 23 | SET flowvendor = Foundation_ISE 24 | SET formalverification = false 25 | SET foundationsym = false 26 | SET implementationfiletype = Ngc 27 | SET package = tqg144 28 | SET removerpms = false 29 | SET simulationfiles = Behavioral 30 | SET speedgrade = -2 31 | SET verilogsim = true 32 | SET vhdlsim = false 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Fifo_Generator family Xilinx,_Inc. 7.2 36 | # END Select 37 | # BEGIN Parameters 38 | CSET add_ngc_constraint_axi=false 39 | CSET almost_empty_flag=false 40 | CSET almost_full_flag=false 41 | CSET aruser_width=1 42 | CSET awuser_width=1 43 | CSET axi_address_width=32 44 | CSET axi_data_width=64 45 | CSET axi_type=AXI4_Stream 46 | CSET axis_type=FIFO 47 | CSET buser_width=1 48 | CSET clock_enable_type=Slave_Interface_Clock_Enable 49 | CSET clock_type_axi=Common_Clock 50 | CSET component_name=fifo_2kx18 51 | CSET data_count=false 52 | CSET data_count_width=11 53 | CSET disable_timing_violations=false 54 | CSET disable_timing_violations_axi=false 55 | CSET dout_reset_value=0 56 | CSET empty_threshold_assert_value=2 57 | CSET empty_threshold_assert_value_axis=1022 58 | CSET empty_threshold_assert_value_rach=1022 59 | CSET empty_threshold_assert_value_rdch=1022 60 | CSET empty_threshold_assert_value_wach=1022 61 | CSET empty_threshold_assert_value_wdch=1022 62 | CSET empty_threshold_assert_value_wrch=1022 63 | CSET empty_threshold_negate_value=3 64 | CSET enable_aruser=false 65 | CSET enable_awuser=false 66 | CSET enable_buser=false 67 | CSET enable_common_overflow=false 68 | CSET enable_common_underflow=false 69 | CSET enable_data_counts_axis=false 70 | CSET enable_data_counts_rach=false 71 | CSET enable_data_counts_rdch=false 72 | CSET enable_data_counts_wach=false 73 | CSET enable_data_counts_wdch=false 74 | CSET enable_data_counts_wrch=false 75 | CSET enable_ecc=false 76 | CSET enable_ecc_axis=false 77 | CSET enable_ecc_rach=false 78 | CSET enable_ecc_rdch=false 79 | CSET enable_ecc_wach=false 80 | CSET enable_ecc_wdch=false 81 | CSET enable_ecc_wrch=false 82 | CSET enable_handshake_flag_options_axis=false 83 | CSET enable_handshake_flag_options_rach=false 84 | CSET enable_handshake_flag_options_rdch=false 85 | CSET enable_handshake_flag_options_wach=false 86 | CSET enable_handshake_flag_options_wdch=false 87 | CSET enable_handshake_flag_options_wrch=false 88 | CSET enable_read_channel=false 89 | CSET enable_reset_synchronization=true 90 | CSET enable_ruser=false 91 | CSET enable_tdata=false 92 | CSET enable_tdest=false 93 | CSET enable_tid=false 94 | CSET enable_tkeep=false 95 | CSET enable_tlast=false 96 | CSET enable_tready=true 97 | CSET enable_tstrobe=false 98 | CSET enable_tuser=false 99 | CSET enable_write_channel=false 100 | CSET enable_wuser=false 101 | CSET fifo_application_type_axis=Data_FIFO 102 | CSET fifo_application_type_rach=Data_FIFO 103 | CSET fifo_application_type_rdch=Data_FIFO 104 | CSET fifo_application_type_wach=Data_FIFO 105 | CSET fifo_application_type_wdch=Data_FIFO 106 | CSET fifo_application_type_wrch=Data_FIFO 107 | CSET fifo_implementation=Independent_Clocks_Block_RAM 108 | CSET fifo_implementation_axis=Common_Clock_Block_RAM 109 | CSET fifo_implementation_rach=Common_Clock_Block_RAM 110 | CSET fifo_implementation_rdch=Common_Clock_Block_RAM 111 | CSET fifo_implementation_wach=Common_Clock_Block_RAM 112 | CSET fifo_implementation_wdch=Common_Clock_Block_RAM 113 | CSET fifo_implementation_wrch=Common_Clock_Block_RAM 114 | CSET full_flags_reset_value=1 115 | CSET full_threshold_assert_value=2045 116 | CSET full_threshold_assert_value_axis=1023 117 | CSET full_threshold_assert_value_rach=1023 118 | CSET full_threshold_assert_value_rdch=1023 119 | CSET full_threshold_assert_value_wach=1023 120 | CSET full_threshold_assert_value_wdch=1023 121 | CSET full_threshold_assert_value_wrch=1023 122 | CSET full_threshold_negate_value=2044 123 | CSET id_width=4 124 | CSET inject_dbit_error=false 125 | CSET inject_dbit_error_axis=false 126 | CSET inject_dbit_error_rach=false 127 | CSET inject_dbit_error_rdch=false 128 | CSET inject_dbit_error_wach=false 129 | CSET inject_dbit_error_wdch=false 130 | CSET inject_dbit_error_wrch=false 131 | CSET inject_sbit_error=false 132 | CSET inject_sbit_error_axis=false 133 | CSET inject_sbit_error_rach=false 134 | CSET inject_sbit_error_rdch=false 135 | CSET inject_sbit_error_wach=false 136 | CSET inject_sbit_error_wdch=false 137 | CSET inject_sbit_error_wrch=false 138 | CSET input_data_width=18 139 | CSET input_depth=2048 140 | CSET input_depth_axis=1024 141 | CSET input_depth_rach=16 142 | CSET input_depth_rdch=1024 143 | CSET input_depth_wach=16 144 | CSET input_depth_wdch=1024 145 | CSET input_depth_wrch=16 146 | CSET interface_type=Native 147 | CSET output_data_width=18 148 | CSET output_depth=2048 149 | CSET overflow_flag=false 150 | CSET overflow_flag_axi=false 151 | CSET overflow_sense=Active_High 152 | CSET overflow_sense_axi=Active_High 153 | CSET performance_options=Standard_FIFO 154 | CSET programmable_empty_type=No_Programmable_Empty_Threshold 155 | CSET programmable_empty_type_axis=Empty 156 | CSET programmable_empty_type_rach=Empty 157 | CSET programmable_empty_type_rdch=Empty 158 | CSET programmable_empty_type_wach=Empty 159 | CSET programmable_empty_type_wdch=Empty 160 | CSET programmable_empty_type_wrch=Empty 161 | CSET programmable_full_type=No_Programmable_Full_Threshold 162 | CSET programmable_full_type_axis=Full 163 | CSET programmable_full_type_rach=Full 164 | CSET programmable_full_type_rdch=Full 165 | CSET programmable_full_type_wach=Full 166 | CSET programmable_full_type_wdch=Full 167 | CSET programmable_full_type_wrch=Full 168 | CSET rach_type=FIFO 169 | CSET rdch_type=FIFO 170 | CSET read_clock_frequency=1 171 | CSET read_data_count=false 172 | CSET read_data_count_width=11 173 | CSET reset_pin=true 174 | CSET reset_type=Asynchronous_Reset 175 | CSET ruser_width=1 176 | CSET tdata_width=64 177 | CSET tdest_width=4 178 | CSET tid_width=8 179 | CSET tkeep_width=4 180 | CSET tstrb_width=4 181 | CSET tuser_width=4 182 | CSET underflow_flag=false 183 | CSET underflow_flag_axi=false 184 | CSET underflow_sense=Active_High 185 | CSET underflow_sense_axi=Active_High 186 | CSET use_clock_enable=false 187 | CSET use_dout_reset=false 188 | CSET use_embedded_registers=false 189 | CSET use_extra_logic=false 190 | CSET valid_flag=false 191 | CSET valid_sense=Active_High 192 | CSET wach_type=FIFO 193 | CSET wdch_type=FIFO 194 | CSET wrch_type=FIFO 195 | CSET write_acknowledge_flag=false 196 | CSET write_acknowledge_sense=Active_High 197 | CSET write_clock_frequency=1 198 | CSET write_data_count=false 199 | CSET write_data_count_width=11 200 | CSET wuser_width=1 201 | # END Parameters 202 | GENERATE 203 | # CRC: 5a428ec2 204 | -------------------------------------------------------------------------------- /sources_1/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.1 4 | # Date: Tue Aug 09 21:40:17 2011 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = false 17 | SET asysymbol = true 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = false 20 | SET designentry = Verilog 21 | SET device = xc6slx9 22 | SET devicefamily = spartan6 23 | SET flowvendor = Other 24 | SET formalverification = false 25 | SET foundationsym = false 26 | SET implementationfiletype = Ngc 27 | SET package = tqg144 28 | SET removerpms = false 29 | SET simulationfiles = Behavioral 30 | SET speedgrade = -2 31 | SET verilogsim = true 32 | SET vhdlsim = false 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Clocking_Wizard family Xilinx,_Inc. 3.1 36 | # END Select 37 | # BEGIN Parameters 38 | CSET calc_done=DONE 39 | CSET clk_in_sel_port=CLK_IN_SEL 40 | CSET clk_out1_port=CLK_OUT1 41 | CSET clk_out1_use_fine_ps_gui=false 42 | CSET clk_out2_port=CLK_OUT2 43 | CSET clk_out2_use_fine_ps_gui=false 44 | CSET clk_out3_port=CLK_OUT3 45 | CSET clk_out3_use_fine_ps_gui=false 46 | CSET clk_out4_port=CLK_OUT4 47 | CSET clk_out4_use_fine_ps_gui=false 48 | CSET clk_out5_port=CLK_OUT5 49 | CSET clk_out5_use_fine_ps_gui=false 50 | CSET clk_out6_port=CLK_OUT6 51 | CSET clk_out6_use_fine_ps_gui=false 52 | CSET clk_out7_port=CLK_OUT7 53 | CSET clk_out7_use_fine_ps_gui=false 54 | CSET clk_valid_port=CLK_VALID 55 | CSET clkfb_in_n_port=CLKFB_IN_N 56 | CSET clkfb_in_p_port=CLKFB_IN_P 57 | CSET clkfb_in_port=CLKFB_IN 58 | CSET clkfb_in_signaling=SINGLE 59 | CSET clkfb_out_n_port=CLKFB_OUT_N 60 | CSET clkfb_out_p_port=CLKFB_OUT_P 61 | CSET clkfb_out_port=CLKFB_OUT 62 | CSET clkin1_jitter_ps=384.61 63 | CSET clkin1_ui_jitter=0.010 64 | CSET clkin2_jitter_ps=100.0 65 | CSET clkin2_ui_jitter=0.010 66 | CSET clkout1_drives=BUFG 67 | CSET clkout1_requested_duty_cycle=50.0 68 | CSET clkout1_requested_out_freq=74.285 69 | CSET clkout1_requested_phase=0.000 70 | CSET clkout2_drives=BUFG 71 | CSET clkout2_requested_duty_cycle=50.0 72 | CSET clkout2_requested_out_freq=100.000 73 | CSET clkout2_requested_phase=0.000 74 | CSET clkout2_used=false 75 | CSET clkout3_drives=BUFG 76 | CSET clkout3_requested_duty_cycle=50.0 77 | CSET clkout3_requested_out_freq=100.000 78 | CSET clkout3_requested_phase=0.000 79 | CSET clkout3_used=false 80 | CSET clkout4_drives=BUFG 81 | CSET clkout4_requested_duty_cycle=50.0 82 | CSET clkout4_requested_out_freq=100.000 83 | CSET clkout4_requested_phase=0.000 84 | CSET clkout4_used=false 85 | CSET clkout5_drives=BUFG 86 | CSET clkout5_requested_duty_cycle=50.0 87 | CSET clkout5_requested_out_freq=100.000 88 | CSET clkout5_requested_phase=0.000 89 | CSET clkout5_used=false 90 | CSET clkout6_drives=BUFG 91 | CSET clkout6_requested_duty_cycle=50.0 92 | CSET clkout6_requested_out_freq=100.000 93 | CSET clkout6_requested_phase=0.000 94 | CSET clkout6_used=false 95 | CSET clkout7_drives=BUFG 96 | CSET clkout7_requested_duty_cycle=50.0 97 | CSET clkout7_requested_out_freq=100.000 98 | CSET clkout7_requested_phase=0.000 99 | CSET clkout7_used=false 100 | CSET clock_mgr_type=MANUAL 101 | CSET component_name=clkgendcm_720p60hz 102 | CSET daddr_port=DADDR 103 | CSET dclk_port=DCLK 104 | CSET dcm_clk_feedback=1X 105 | CSET dcm_clk_out1_port=CLK0 106 | CSET dcm_clk_out2_port=CLK0 107 | CSET dcm_clk_out3_port=CLK0 108 | CSET dcm_clk_out4_port=CLK0 109 | CSET dcm_clk_out5_port=CLK0 110 | CSET dcm_clk_out6_port=CLK0 111 | CSET dcm_clkdv_divide=2.0 112 | CSET dcm_clkfx_divide=1 113 | CSET dcm_clkfx_multiply=4 114 | CSET dcm_clkgen_clk_out1_port=CLKFX 115 | CSET dcm_clkgen_clk_out2_port=CLKFX 116 | CSET dcm_clkgen_clk_out3_port=CLKFX 117 | CSET dcm_clkgen_clkfx_divide=7 118 | CSET dcm_clkgen_clkfx_md_max=0 119 | CSET dcm_clkgen_clkfx_multiply=20 120 | CSET dcm_clkgen_clkfxdv_divide=2 121 | CSET dcm_clkgen_clkin_period=38.461 122 | CSET dcm_clkgen_notes=720p60hzclocksource 123 | CSET dcm_clkgen_spread_spectrum=NONE 124 | CSET dcm_clkgen_startup_wait=false 125 | CSET dcm_clkin_divide_by_2=false 126 | CSET dcm_clkin_period=10.000 127 | CSET dcm_clkout_phase_shift=NONE 128 | CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS 129 | CSET dcm_notes=None 130 | CSET dcm_phase_shift=0 131 | CSET dcm_pll_cascade=NONE 132 | CSET dcm_startup_wait=false 133 | CSET den_port=DEN 134 | CSET din_port=DIN 135 | CSET dout_port=DOUT 136 | CSET drdy_port=DRDY 137 | CSET dwe_port=DWE 138 | CSET feedback_source=FDBK_AUTO 139 | CSET in_freq_units=Units_MHz 140 | CSET in_jitter_units=Units_UI 141 | CSET input_clk_stopped_port=INPUT_CLK_STOPPED 142 | CSET jitter_options=UI 143 | CSET jitter_sel=No_Jitter 144 | CSET locked_port=LOCKED 145 | CSET mmcm_bandwidth=OPTIMIZED 146 | CSET mmcm_clkfbout_mult_f=4.000 147 | CSET mmcm_clkfbout_phase=0.000 148 | CSET mmcm_clkfbout_use_fine_ps=false 149 | CSET mmcm_clkin1_period=10.000 150 | CSET mmcm_clkin2_period=10.000 151 | CSET mmcm_clkout0_divide_f=4.000 152 | CSET mmcm_clkout0_duty_cycle=0.500 153 | CSET mmcm_clkout0_phase=0.000 154 | CSET mmcm_clkout0_use_fine_ps=false 155 | CSET mmcm_clkout1_divide=1 156 | CSET mmcm_clkout1_duty_cycle=0.500 157 | CSET mmcm_clkout1_phase=0.000 158 | CSET mmcm_clkout1_use_fine_ps=false 159 | CSET mmcm_clkout2_divide=1 160 | CSET mmcm_clkout2_duty_cycle=0.500 161 | CSET mmcm_clkout2_phase=0.000 162 | CSET mmcm_clkout2_use_fine_ps=false 163 | CSET mmcm_clkout3_divide=1 164 | CSET mmcm_clkout3_duty_cycle=0.500 165 | CSET mmcm_clkout3_phase=0.000 166 | CSET mmcm_clkout3_use_fine_ps=false 167 | CSET mmcm_clkout4_cascade=false 168 | CSET mmcm_clkout4_divide=1 169 | CSET mmcm_clkout4_duty_cycle=0.500 170 | CSET mmcm_clkout4_phase=0.000 171 | CSET mmcm_clkout4_use_fine_ps=false 172 | CSET mmcm_clkout5_divide=1 173 | CSET mmcm_clkout5_duty_cycle=0.500 174 | CSET mmcm_clkout5_phase=0.000 175 | CSET mmcm_clkout5_use_fine_ps=false 176 | CSET mmcm_clkout6_divide=1 177 | CSET mmcm_clkout6_duty_cycle=0.500 178 | CSET mmcm_clkout6_phase=0.000 179 | CSET mmcm_clkout6_use_fine_ps=false 180 | CSET mmcm_clock_hold=false 181 | CSET mmcm_compensation=ZHOLD 182 | CSET mmcm_divclk_divide=1 183 | CSET mmcm_notes=None 184 | CSET mmcm_ref_jitter1=0.010 185 | CSET mmcm_ref_jitter2=0.010 186 | CSET mmcm_startup_wait=false 187 | CSET num_out_clks=1 188 | CSET override_dcm=false 189 | CSET override_dcm_clkgen=true 190 | CSET override_mmcm=false 191 | CSET override_pll=false 192 | CSET platform=nt64 193 | CSET pll_bandwidth=OPTIMIZED 194 | CSET pll_clk_feedback=CLKFBOUT 195 | CSET pll_clkfbout_mult=4 196 | CSET pll_clkfbout_phase=0.000 197 | CSET pll_clkin_period=10.000 198 | CSET pll_clkout0_divide=1 199 | CSET pll_clkout0_duty_cycle=0.500 200 | CSET pll_clkout0_phase=0.000 201 | CSET pll_clkout1_divide=1 202 | CSET pll_clkout1_duty_cycle=0.500 203 | CSET pll_clkout1_phase=0.000 204 | CSET pll_clkout2_divide=1 205 | CSET pll_clkout2_duty_cycle=0.500 206 | CSET pll_clkout2_phase=0.000 207 | CSET pll_clkout3_divide=1 208 | CSET pll_clkout3_duty_cycle=0.500 209 | CSET pll_clkout3_phase=0.000 210 | CSET pll_clkout4_divide=1 211 | CSET pll_clkout4_duty_cycle=0.500 212 | CSET pll_clkout4_phase=0.000 213 | CSET pll_clkout5_divide=1 214 | CSET pll_clkout5_duty_cycle=0.500 215 | CSET pll_clkout5_phase=0.000 216 | CSET pll_compensation=INTERNAL 217 | CSET pll_divclk_divide=1 218 | CSET pll_notes=None 219 | CSET pll_ref_jitter=0.010 220 | CSET power_down_port=POWER_DOWN 221 | CSET prim_in_freq=26 222 | CSET prim_in_jitter=0.010 223 | CSET prim_source=No_buffer 224 | CSET primary_port=CLK_IN1 225 | CSET primtype_sel=DCM_CLKGEN 226 | CSET psclk_port=PSCLK 227 | CSET psdone_port=PSDONE 228 | CSET psen_port=PSEN 229 | CSET psincdec_port=PSINCDEC 230 | CSET relative_inclk=REL_PRIMARY 231 | CSET reset_port=RESET 232 | CSET secondary_in_freq=100.000 233 | CSET secondary_in_jitter=0.010 234 | CSET secondary_port=CLK_IN2 235 | CSET secondary_source=Single_ended_clock_capable_pin 236 | CSET status_port=STATUS 237 | CSET summary_strings=empty 238 | CSET use_clk_valid=false 239 | CSET use_dyn_phase_shift=false 240 | CSET use_dyn_reconfig=false 241 | CSET use_freeze=false 242 | CSET use_freq_synth=true 243 | CSET use_inclk_stopped=false 244 | CSET use_inclk_switchover=false 245 | CSET use_locked=true 246 | CSET use_max_i_jitter=false 247 | CSET use_min_o_jitter=false 248 | CSET use_min_power=false 249 | CSET use_phase_alignment=false 250 | CSET use_power_down=false 251 | CSET use_reset=true 252 | CSET use_spread_spectrum=false 253 | CSET use_status=false 254 | # END Parameters 255 | GENERATE 256 | # CRC: fcd26fcc 257 | -------------------------------------------------------------------------------- /sources_1/imports/common/i2c_slave_tb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | `timescale 1ns / 1ps 27 | 28 | //////////////////////////////////////////////////////////////////////////////// 29 | // Company: 30 | // Engineer: 31 | // 32 | // Create Date: 12:30:45 04/05/2011 33 | // Design Name: i2c_slave 34 | // Module Name: C:/largework/fpga/hdmi/impl4/common/i2c_slave_tb.v 35 | // Project Name: impl4 36 | // Target Device: 37 | // Tool versions: 38 | // Description: 39 | // 40 | // Verilog Test Fixture created by ISE for module: i2c_slave 41 | // 42 | // Dependencies: 43 | // 44 | // Revision: 45 | // Revision 0.01 - File Created 46 | // Additional Comments: 47 | // 48 | //////////////////////////////////////////////////////////////////////////////// 49 | 50 | module i2c_slave_tb; 51 | 52 | reg SDA; // physical wire state 53 | reg SCL; 54 | 55 | // Inputs 56 | reg clk; 57 | reg reset; 58 | reg [7:0] i2c_device_addr; 59 | reg [7:0] reg_addr; 60 | reg wr_stb; 61 | reg [7:0] reg_data_in; 62 | 63 | // Outputs 64 | wire SCL_pd; 65 | wire SDA_pd; 66 | wire SDA_pu; 67 | wire [7:0] reg_a0; 68 | wire [7:0] reg_a1; 69 | wire [7:0] reg_a2; 70 | wire [7:0] reg_a3; 71 | 72 | // Instantiate the Unit Under Test (UUT) 73 | i2c_slave uut ( 74 | .SCL(SCL), 75 | .SCL_pd(SCL_pd), 76 | .SDA(SDA), 77 | .SDA_pd(SDA_pd), 78 | .SDA_pu(SDA_pu), 79 | .clk(clk), 80 | .reset(reset), 81 | .i2c_device_addr(i2c_device_addr), 82 | .reg_addr(reg_addr), 83 | .wr_stb(wr_stb), 84 | .reg_data_in(reg_data_in), 85 | .reg_0(reg_a0), 86 | .reg_1(reg_a1), 87 | .reg_2(reg_a2), 88 | .reg_3(reg_a3) 89 | ); 90 | 91 | reg sda_host; // what the host is driving to 92 | reg scl_host; 93 | reg ack; // what the ack state is 94 | reg [7:0] readdata; 95 | 96 | // always @(SCL_pd, SDA_pd, SDA_pu, sda_host, scl_host) begin 97 | always @(*) begin // lazy 98 | // scl equations 99 | case( {SCL_pd, scl_host} ) 100 | 2'b00: SCL <= 1'b0; 101 | 2'b01: SCL <= 1'b1; 102 | 2'b10: SCL <= 1'b0; 103 | // conflict case 104 | 2'b11: SCL <= 1'bX; 105 | // handle tristate case 106 | 2'b0Z: SCL <= 1'b1; 107 | 2'b1Z: SCL <= 1'b0; 108 | default: SCL <= 1'bX; 109 | endcase // case ( {SCL_pd, scl_host} ) 110 | 111 | case( {SDA_pd, SDA_pu, sda_host} ) 112 | 3'b000: SDA <= 1'b0; 113 | 3'b001: SDA <= 1'b1; 114 | 3'b010: SDA <= 1'bX; // change to 1'b1 for override 115 | 3'b011: SDA <= 1'b1; 116 | 3'b100: SDA <= 1'b0; 117 | 3'b101: SDA <= 1'bX; // change to 1'b0 for override 118 | 3'b110: SDA <= 1'bX; 119 | 3'b111: SDA <= 1'bX; 120 | 121 | // tristate case 122 | 3'b00Z: SDA <= 1'b1; 123 | 3'b01Z: SDA <= 1'b1; 124 | 3'b10Z: SDA <= 1'b0; 125 | 3'b11Z: SDA <= 1'bX; 126 | endcase // case ( {SDA_pd, SDA_pu, sda_host} ) 127 | end 128 | 129 | parameter PERIOD = 16'd40; // 25 MHz 130 | parameter I2C_PD = 16'd2464; // make it odd to try and catch non-phase synced issues 131 | parameter I2C_TH = 16'd114; 132 | parameter I2C_TS = 16'd217; 133 | 134 | always begin 135 | clk = 1'b0; 136 | #(PERIOD/2) clk = 1'b1; 137 | #(PERIOD/2); 138 | end 139 | 140 | task I2C_idle; 141 | begin 142 | scl_host = 1'bZ; 143 | sda_host = 1'bZ; 144 | #I2C_PD; 145 | end 146 | endtask // I2C_idle 147 | 148 | task I2C_start; 149 | begin 150 | scl_host = 1'bZ; 151 | sda_host = 1'bZ; 152 | #(I2C_PD/2); 153 | scl_host = 1'bZ; 154 | sda_host = 1'b0; 155 | #(I2C_PD/2); 156 | end 157 | endtask // I2C_start 158 | 159 | task I2C_stop; 160 | begin 161 | scl_host = 1'bZ; 162 | sda_host = 1'b0; 163 | #(I2C_PD/2); 164 | scl_host = 1'bZ; 165 | sda_host = 1'bZ; 166 | #(I2C_PD/2); 167 | end 168 | endtask // I2C_start 169 | 170 | task I2C_tx_bit; // tx from host ( from testbench ) 171 | input bitval; 172 | 173 | begin 174 | scl_host = 1'b0; 175 | #I2C_TH; 176 | sda_host = bitval; 177 | #(I2C_PD/2); 178 | scl_host = 1'bZ; 179 | sda_host = bitval; 180 | #(I2C_PD/2); 181 | end 182 | endtask // I2C_tx_bit 183 | 184 | task I2C_rx_bit; // rx to host ( to testbench ) 185 | output bitval; 186 | 187 | begin 188 | scl_host = 1'b0; 189 | #(I2C_TH/2); 190 | sda_host = 1'bz; 191 | #(I2C_PD/2); 192 | scl_host = 1'bZ; 193 | sda_host = 1'bz; 194 | #1; 195 | bitval = SDA; 196 | #(I2C_PD/2); 197 | end 198 | endtask // I2C_start 199 | 200 | task I2C_ack_low; 201 | begin 202 | scl_host = 1'b0; 203 | #(I2C_PD/2); 204 | end 205 | endtask // I2C_ack_low 206 | 207 | 208 | task I2C_tx_daddr; 209 | input [7:0] daddr; 210 | output rack; 211 | 212 | begin 213 | I2C_tx_bit( daddr[7] ); 214 | I2C_tx_bit( daddr[6] ); 215 | I2C_tx_bit( daddr[5] ); 216 | I2C_tx_bit( daddr[4] ); 217 | I2C_tx_bit( daddr[3] ); 218 | I2C_tx_bit( daddr[2] ); 219 | I2C_tx_bit( daddr[1] ); 220 | I2C_tx_bit( daddr[0] ); 221 | I2C_rx_bit(rack); 222 | I2C_ack_low(); 223 | end 224 | endtask // I2C_TX_DADDR 225 | 226 | task I2C_rx_daddr; 227 | output [7:0] daddr; 228 | input nack; 229 | 230 | begin 231 | I2C_rx_bit(daddr[7]); 232 | I2C_rx_bit(daddr[6]); 233 | I2C_rx_bit(daddr[5]); 234 | I2C_rx_bit(daddr[4]); 235 | I2C_rx_bit(daddr[3]); 236 | I2C_rx_bit(daddr[2]); 237 | I2C_rx_bit(daddr[1]); 238 | I2C_rx_bit(daddr[0]); 239 | I2C_tx_bit( nack ); 240 | I2C_ack_low(); 241 | end 242 | endtask // I2C_RX_DADDR 243 | 244 | initial begin 245 | // Initialize Inputs 246 | clk = 0; 247 | reset = 0; 248 | i2c_device_addr = 8'h72; 249 | reg_addr = 0; 250 | wr_stb = 0; 251 | reg_data_in = 0; 252 | 253 | $stop; 254 | 255 | I2C_idle(); 256 | // run an actual reset cycle 257 | #(PERIOD*4); 258 | reset = 1; 259 | #(PERIOD*4); 260 | reset = 0; 261 | #(PERIOD*4); 262 | 263 | // now pre-set a few I2C registers 264 | reg_addr = 0; 265 | wr_stb = 1; 266 | reg_data_in = 8'hDE; 267 | #(PERIOD*4); 268 | 269 | wr_stb = 0; 270 | #(PERIOD*1); 271 | 272 | reg_addr = 1; 273 | wr_stb = 1; 274 | reg_data_in = 8'hAD; 275 | #(PERIOD*2); 276 | 277 | wr_stb = 0; 278 | #(PERIOD*1); 279 | 280 | reg_addr = 2; 281 | wr_stb = 1; 282 | reg_data_in = 8'hBE; 283 | #(PERIOD*2); 284 | 285 | wr_stb = 0; 286 | #(PERIOD*1); 287 | 288 | reg_addr = 3; 289 | wr_stb = 1; 290 | reg_data_in = 8'hEF; 291 | #(PERIOD*2); 292 | 293 | 294 | // let it soak for a bit for good measure 295 | #(PERIOD*10); 296 | 297 | // now the real sim starts 298 | I2C_idle(); 299 | 300 | // write some data 301 | I2C_start(); 302 | I2C_tx_daddr(8'h72, ack); // write to device 72 303 | I2C_tx_daddr(8'h01, ack); // address 01 304 | I2C_tx_daddr(8'h33, ack); // data 55 305 | I2C_stop(); 306 | #(I2C_PD*5); 307 | 308 | // do a multi-cycle read 309 | I2C_start(); 310 | I2C_tx_daddr(8'h72, ack); // dummy write to 72 311 | I2C_tx_daddr(8'h00, ack); // address 00 312 | I2C_start(); 313 | I2C_tx_daddr(8'h73, ack); // read from 72 314 | // #(I2C_PD*3); 315 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 316 | // #(I2C_PD*3); 317 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 318 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 319 | I2C_rx_daddr(readdata, 1'bz); // data @ address 0 320 | I2C_stop(); 321 | #(I2C_PD*5); 322 | 323 | // do a multi-cycle write 324 | I2C_start(); 325 | I2C_tx_daddr(8'h72, ack); // write to device 70 326 | I2C_tx_daddr(8'h01, ack); // address 01 327 | I2C_tx_daddr(8'hFA, ack); 328 | I2C_tx_daddr(8'hCE, ack); 329 | I2C_tx_daddr(8'h69, ack); 330 | I2C_stop(); 331 | #(I2C_PD*5); 332 | 333 | // read back one address at a time 334 | I2C_start(); 335 | I2C_tx_daddr(8'h72, ack); // dummy write to 72 336 | I2C_tx_daddr(8'h00, ack); // address 00 337 | 338 | #(I2C_PD*5); 339 | I2C_start(); 340 | I2C_tx_daddr(8'h73, ack); // read from 72 341 | I2C_rx_daddr(readdata, 1'bz); // one read 342 | I2C_stop(); 343 | 344 | // this is the only questionable vector 345 | // if you do an isolated read, should the address have 346 | // incremeted from the previous read, or 347 | // should it be the same. I have implemented it so 348 | // that it increments. 349 | I2C_start(); 350 | I2C_tx_daddr(8'h73, ack); // read from 72 351 | I2C_rx_daddr(readdata, 1'bz); // one read 352 | I2C_stop(); 353 | 354 | #(I2C_PD*5); 355 | 356 | I2C_start(); 357 | I2C_tx_daddr(8'h73, ack); // read from 72 358 | I2C_rx_daddr(readdata, 1'b0); // one read 359 | I2C_rx_daddr(readdata, 1'bz); // one read 360 | I2C_stop(); 361 | 362 | 363 | // write to another device not us 364 | I2C_start(); 365 | I2C_tx_daddr(8'hA0, ack); // write to device a0 366 | I2C_tx_daddr(8'h01, ack); // address 01 367 | I2C_tx_daddr(8'h55, ack); // data 55 -- this should be ignored 368 | I2C_stop(); 369 | 370 | #I2C_PD; 371 | #I2C_PD; 372 | end 373 | 374 | endmodule 375 | 376 | -------------------------------------------------------------------------------- /sources_1/imports/common/i2c_snoop_tb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | `timescale 1ns / 1ps 27 | 28 | //////////////////////////////////////////////////////////////////////////////// 29 | // Company: 30 | // Engineer: 31 | // 32 | // Create Date: 12:30:45 04/05/2011 33 | // Design Name: i2c_slave 34 | // Module Name: C:/largework/fpga/hdmi/impl4/common/i2c_slave_tb.v 35 | // Project Name: impl4 36 | // Target Device: 37 | // Tool versions: 38 | // Description: 39 | // 40 | // Verilog Test Fixture created by ISE for module: i2c_slave 41 | // 42 | // Dependencies: 43 | // 44 | // Revision: 45 | // Revision 0.01 - File Created 46 | // Additional Comments: 47 | // 48 | //////////////////////////////////////////////////////////////////////////////// 49 | 50 | module i2c_snoop_tb; 51 | 52 | reg SDA; // physical wire state 53 | reg SCL; 54 | 55 | // Inputs 56 | reg clk; 57 | reg reset; 58 | reg [7:0] i2c_device_addr; 59 | reg [7:0] reg_addr; 60 | reg wr_stb; 61 | reg [7:0] reg_data_in; 62 | 63 | // Outputs 64 | wire SCL_pd; 65 | wire SDA_pd; 66 | wire SDA_pu; 67 | wire [7:0] reg_a0; 68 | wire [7:0] reg_a1; 69 | wire [7:0] reg_a2; 70 | wire [7:0] reg_a3; 71 | 72 | reg [7:0] snoop_addr; 73 | wire [7:0] snoop_data; 74 | 75 | // Instantiate the Unit Under Test (UUT) 76 | i2c_snoop uut ( 77 | .SCL(SCL), 78 | .SDA(SDA), 79 | .clk(clk), 80 | .reset(reset), 81 | .i2c_snoop_addr(8'h74), 82 | .reg_addr(snoop_addr), 83 | .reg_dout(snoop_data) 84 | ); 85 | 86 | // Instantiate the Unit Under Test (UUT) 87 | i2c_slave target ( 88 | .SCL(SCL), 89 | .SCL_pd(SCL_pd), 90 | .SDA(SDA), 91 | .SDA_pd(SDA_pd), 92 | .SDA_pu(SDA_pu), 93 | .clk(clk), 94 | .reset(reset), 95 | .i2c_device_addr(i2c_device_addr), 96 | .reg_addr(reg_addr), 97 | .wr_stb(wr_stb), 98 | .reg_data_in(reg_data_in), 99 | .reg_0(reg_a0), 100 | .reg_1(reg_a1), 101 | .reg_2(reg_a2), 102 | .reg_3(reg_a3) 103 | ); 104 | 105 | reg sda_host; // what the host is driving to 106 | reg scl_host; 107 | reg ack; // what the ack state is 108 | reg [7:0] readdata; 109 | 110 | // always @(SCL_pd, SDA_pd, SDA_pu, sda_host, scl_host) begin 111 | always @(*) begin // lazy 112 | // scl equations 113 | case( {SCL_pd, scl_host} ) 114 | 2'b00: SCL <= 1'b0; 115 | 2'b01: SCL <= 1'b1; 116 | 2'b10: SCL <= 1'b0; 117 | // conflict case 118 | 2'b11: SCL <= 1'bX; 119 | // handle tristate case 120 | 2'b0Z: SCL <= 1'b1; 121 | 2'b1Z: SCL <= 1'b0; 122 | default: SCL <= 1'bX; 123 | endcase // case ( {SCL_pd, scl_host} ) 124 | 125 | case( {SDA_pd, SDA_pu, sda_host} ) 126 | 3'b000: SDA <= 1'b0; 127 | 3'b001: SDA <= 1'b1; 128 | 3'b010: SDA <= 1'bX; // change to 1'b1 for override 129 | 3'b011: SDA <= 1'b1; 130 | 3'b100: SDA <= 1'b0; 131 | 3'b101: SDA <= 1'bX; // change to 1'b0 for override 132 | 3'b110: SDA <= 1'bX; 133 | 3'b111: SDA <= 1'bX; 134 | 135 | // tristate case 136 | 3'b00Z: SDA <= 1'b1; 137 | 3'b01Z: SDA <= 1'b1; 138 | 3'b10Z: SDA <= 1'b0; 139 | 3'b11Z: SDA <= 1'bX; 140 | endcase // case ( {SDA_pd, SDA_pu, sda_host} ) 141 | end 142 | 143 | parameter PERIOD = 16'd40; // 25 MHz 144 | parameter I2C_PD = 16'd2464; // make it odd to try and catch non-phase synced issues 145 | parameter I2C_TH = 16'd114; 146 | parameter I2C_TS = 16'd217; 147 | 148 | always begin 149 | clk = 1'b0; 150 | #(PERIOD/2) clk = 1'b1; 151 | #(PERIOD/2); 152 | end 153 | 154 | task I2C_idle; 155 | begin 156 | scl_host = 1'bZ; 157 | sda_host = 1'bZ; 158 | #I2C_PD; 159 | end 160 | endtask // I2C_idle 161 | 162 | task I2C_start; 163 | begin 164 | scl_host = 1'bZ; 165 | sda_host = 1'bZ; 166 | #(I2C_PD/2); 167 | scl_host = 1'bZ; 168 | sda_host = 1'b0; 169 | #(I2C_PD/2); 170 | end 171 | endtask // I2C_start 172 | 173 | task I2C_stop; 174 | begin 175 | scl_host = 1'bZ; 176 | sda_host = 1'b0; 177 | #(I2C_PD/2); 178 | scl_host = 1'bZ; 179 | sda_host = 1'bZ; 180 | #(I2C_PD/2); 181 | end 182 | endtask // I2C_start 183 | 184 | task I2C_tx_bit; // tx from host ( from testbench ) 185 | input bitval; 186 | 187 | begin 188 | scl_host = 1'b0; 189 | #I2C_TH; 190 | sda_host = bitval; 191 | #(I2C_PD/2); 192 | scl_host = 1'bZ; 193 | sda_host = bitval; 194 | #(I2C_PD/2); 195 | end 196 | endtask // I2C_tx_bit 197 | 198 | task I2C_rx_bit; // rx to host ( to testbench ) 199 | output bitval; 200 | 201 | begin 202 | scl_host = 1'b0; 203 | #(I2C_TH/2); 204 | sda_host = 1'bz; 205 | #(I2C_PD/2); 206 | scl_host = 1'bZ; 207 | sda_host = 1'bz; 208 | #1; 209 | bitval = SDA; 210 | #(I2C_PD/2); 211 | end 212 | endtask // I2C_start 213 | 214 | task I2C_ack_low; 215 | begin 216 | scl_host = 1'b0; 217 | #(I2C_PD/2); 218 | end 219 | endtask // I2C_ack_low 220 | 221 | 222 | task I2C_tx_daddr; 223 | input [7:0] daddr; 224 | output rack; 225 | 226 | begin 227 | I2C_tx_bit( daddr[7] ); 228 | I2C_tx_bit( daddr[6] ); 229 | I2C_tx_bit( daddr[5] ); 230 | I2C_tx_bit( daddr[4] ); 231 | I2C_tx_bit( daddr[3] ); 232 | I2C_tx_bit( daddr[2] ); 233 | I2C_tx_bit( daddr[1] ); 234 | I2C_tx_bit( daddr[0] ); 235 | I2C_rx_bit(rack); 236 | I2C_ack_low(); 237 | end 238 | endtask // I2C_TX_DADDR 239 | 240 | task I2C_rx_daddr; 241 | output [7:0] daddr; 242 | input nack; 243 | 244 | begin 245 | I2C_rx_bit(daddr[7]); 246 | I2C_rx_bit(daddr[6]); 247 | I2C_rx_bit(daddr[5]); 248 | I2C_rx_bit(daddr[4]); 249 | I2C_rx_bit(daddr[3]); 250 | I2C_rx_bit(daddr[2]); 251 | I2C_rx_bit(daddr[1]); 252 | I2C_rx_bit(daddr[0]); 253 | I2C_tx_bit( nack ); 254 | I2C_ack_low(); 255 | end 256 | endtask // I2C_RX_DADDR 257 | 258 | initial begin 259 | // Initialize Inputs 260 | clk = 0; 261 | reset = 0; 262 | i2c_device_addr = 8'h74; 263 | reg_addr = 0; 264 | wr_stb = 0; 265 | reg_data_in = 0; 266 | snoop_addr = 0; 267 | 268 | $stop; 269 | 270 | I2C_idle(); 271 | // run an actual reset cycle 272 | #(PERIOD*4); 273 | reset = 1; 274 | #(PERIOD*4); 275 | reset = 0; 276 | #(PERIOD*4); 277 | 278 | // now pre-set a few I2C registers 279 | reg_addr = 0; 280 | wr_stb = 1; 281 | reg_data_in = 8'hDE; 282 | #(PERIOD*4); 283 | 284 | wr_stb = 0; 285 | #(PERIOD*1); 286 | 287 | reg_addr = 1; 288 | wr_stb = 1; 289 | reg_data_in = 8'hAD; 290 | #(PERIOD*2); 291 | 292 | wr_stb = 0; 293 | #(PERIOD*1); 294 | 295 | reg_addr = 2; 296 | wr_stb = 1; 297 | reg_data_in = 8'hBE; 298 | #(PERIOD*2); 299 | 300 | wr_stb = 0; 301 | #(PERIOD*1); 302 | 303 | reg_addr = 3; 304 | wr_stb = 1; 305 | reg_data_in = 8'hEF; 306 | #(PERIOD*2); 307 | 308 | 309 | // let it soak for a bit for good measure 310 | #(PERIOD*10); 311 | 312 | // now the real sim starts 313 | I2C_idle(); 314 | 315 | // write some data 316 | I2C_start(); 317 | I2C_tx_daddr(8'h74, ack); // write to device 72 318 | I2C_tx_daddr(8'h01, ack); // address 01 319 | I2C_tx_daddr(8'h33, ack); // data 55 320 | I2C_stop(); 321 | #(I2C_PD*5); 322 | 323 | // do a multi-cycle read 324 | I2C_start(); 325 | I2C_tx_daddr(8'h74, ack); // dummy write to 72 326 | I2C_tx_daddr(8'h00, ack); // address 00 327 | I2C_start(); 328 | I2C_tx_daddr(8'h75, ack); // read from 72 329 | // #(I2C_PD*3); 330 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 331 | // #(I2C_PD*3); 332 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 333 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 334 | I2C_rx_daddr(readdata, 1'bz); // data @ address 0 335 | I2C_stop(); 336 | #(I2C_PD*5); 337 | 338 | // do a multi-cycle write 339 | I2C_start(); 340 | I2C_tx_daddr(8'h74, ack); // write to device 70 341 | I2C_tx_daddr(8'h01, ack); // address 01 342 | I2C_tx_daddr(8'hFA, ack); 343 | I2C_tx_daddr(8'hCE, ack); 344 | I2C_tx_daddr(8'h69, ack); 345 | I2C_stop(); 346 | #(I2C_PD*5); 347 | 348 | #I2C_PD; 349 | #I2C_PD; 350 | snoop_addr = 8'h01; 351 | #I2C_PD; 352 | snoop_addr = 8'h02; 353 | #I2C_PD; 354 | snoop_addr = 8'h03; 355 | #I2C_PD; 356 | snoop_addr = 8'h04; 357 | #I2C_PD; 358 | snoop_addr = 8'h05; 359 | #I2C_PD; 360 | #I2C_PD; 361 | 362 | // read back one address at a time 363 | I2C_start(); 364 | I2C_tx_daddr(8'h74, ack); // dummy write to 72 365 | I2C_tx_daddr(8'h00, ack); // address 00 366 | 367 | #(I2C_PD*5); 368 | I2C_start(); 369 | I2C_tx_daddr(8'h75, ack); // read from 72 370 | I2C_rx_daddr(readdata, 1'bz); // one read 371 | I2C_stop(); 372 | 373 | // this is the only questionable vector 374 | // if you do an isolated read, should the address have 375 | // incremeted from the previous read, or 376 | // should it be the same. I have implemented it so 377 | // that it increments. 378 | I2C_start(); 379 | I2C_tx_daddr(8'h75, ack); // read from 72 380 | I2C_rx_daddr(readdata, 1'bz); // one read 381 | I2C_stop(); 382 | 383 | #(I2C_PD*5); 384 | 385 | I2C_start(); 386 | I2C_tx_daddr(8'h75, ack); // read from 72 387 | I2C_rx_daddr(readdata, 1'b0); // one read 388 | I2C_rx_daddr(readdata, 1'bz); // one read 389 | I2C_stop(); 390 | 391 | 392 | // write to another device not us 393 | I2C_start(); 394 | I2C_tx_daddr(8'hA0, ack); // write to device a0 395 | I2C_tx_daddr(8'h01, ack); // address 01 396 | I2C_tx_daddr(8'h55, ack); // data 55 -- this should be ignored 397 | I2C_stop(); 398 | 399 | #I2C_PD; 400 | #I2C_PD; 401 | snoop_addr = 8'h01; 402 | #I2C_PD; 403 | snoop_addr = 8'h02; 404 | #I2C_PD; 405 | snoop_addr = 8'h03; 406 | #I2C_PD; 407 | snoop_addr = 8'h04; 408 | #I2C_PD; 409 | snoop_addr = 8'h05; 410 | #I2C_PD; 411 | #I2C_PD; 412 | #I2C_PD; 413 | #I2C_PD; 414 | 415 | end 416 | 417 | endmodule 418 | 419 | -------------------------------------------------------------------------------- /sources_1/imports/common/timing_detector.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | `timescale 1 ns / 1ps 27 | 28 | module timing_detector ( 29 | input wire pclk, 30 | input wire rstin, // asynchronous, as it is asserted during no-clock condition 31 | input wire vsync, // assume positive-polarity sync on input 32 | input wire hsync, // assume positive-polarity sync on input 33 | input wire de, 34 | input wire refclk, 35 | input wire lcd_de, 36 | input wire lcd_vsync, 37 | 38 | output reg [11:0] hactive, // in pixels 39 | output reg [11:0] vactive, // in lines 40 | output reg [11:0] htotal, // in pixels 41 | output reg [23:0] vtotal, // ** in PIXELS ** must divide by htotal in software 42 | output reg [7:0] h_frontporch, // in pixels 43 | output reg [7:0] h_backporch, // in pixels 44 | output reg [23:0] v_frontporch, // ** in PIXELS ** 45 | output reg [23:0] v_backporch, // ** in PIXELS ** 46 | output reg [7:0] hsync_width, // in pixels 47 | output reg [23:0] vsync_width, // ** in PIXELS ** 48 | output reg [11:0] lcd_de_latency, // in lines 49 | output reg [11:0] lcd_vsync_latency, // in lines 50 | 51 | output reg [23:0] refclkcnt // number of refclocks in a field 52 | ); 53 | 54 | reg vsync_d; 55 | reg hsync_d; 56 | reg de_d; 57 | 58 | wire vsync_rising; 59 | wire hsync_rising; 60 | wire de_rising; 61 | 62 | wire vsync_falling; 63 | wire hsync_falling; 64 | wire de_falling; 65 | 66 | reg [11:0] hcount; 67 | reg [7:0] hsync_width_cnt; 68 | reg [23:0] vcount; 69 | reg [11:0] de_count; 70 | reg [11:0] vactive_count; 71 | reg [7:0] h_fp_count; 72 | reg [7:0] h_bp_count; 73 | reg [23:0] v_fp_count; 74 | reg [23:0] v_bp_count; 75 | 76 | reg vsync_refclk; 77 | reg vsync__refclk; 78 | reg vsync___refclk; 79 | reg vsync____refclk; 80 | wire vsync_refclk_rising; 81 | reg [23:0] refclkcounter; 82 | 83 | reg lcd_de_pclk; 84 | reg lcd_de_1pclk; 85 | reg lcd_de_2pclk; 86 | 87 | reg lcd_vsync_pclk; 88 | reg lcd_vsync_1pclk; 89 | reg lcd_vsync_2pclk; 90 | 91 | reg first_de_rising; 92 | reg first_lcd_de_rising; 93 | 94 | //// vertical front/back porch machine 95 | always @(posedge pclk or posedge rstin) begin 96 | if( rstin ) begin 97 | v_fp_count <= 0; 98 | v_bp_count <= 0; 99 | v_frontporch <= 0; 100 | v_backporch <= 0; 101 | first_de_rising <= 1; 102 | end else begin 103 | if( vsync_falling ) begin 104 | v_fp_count <= 0; 105 | first_de_rising <= 1; 106 | end else begin 107 | if( v_fp_count == 24'hFF_FFFF ) begin 108 | v_fp_count <= v_fp_count; 109 | end else begin 110 | v_fp_count <= v_fp_count + 24'b1; // counting in pixels 111 | end 112 | 113 | if( de_rising ) begin 114 | first_de_rising <= 0; 115 | end else begin 116 | first_de_rising <= first_de_rising; 117 | end 118 | end 119 | 120 | if( de_rising && first_de_rising ) begin 121 | v_frontporch <= v_fp_count; 122 | end else begin 123 | v_frontporch <= v_frontporch; 124 | end 125 | 126 | if( de_falling ) begin 127 | v_bp_count <= 0; 128 | end else begin 129 | if( v_bp_count == 24'hFF_FFFF ) begin 130 | v_bp_count <= v_bp_count; 131 | end else begin 132 | v_bp_count <= v_bp_count + 24'b1; // counting in pixels 133 | end 134 | end 135 | 136 | if( vsync_rising ) begin 137 | v_backporch <= v_bp_count; 138 | end else begin 139 | v_backporch <= v_backporch; 140 | end 141 | end // else: !if( rstin ) 142 | end // always @ (posedge pclk) 143 | 144 | //// horizonal front/back porch machine 145 | always @(posedge pclk or posedge rstin) begin 146 | if( rstin ) begin 147 | h_fp_count <= 0; 148 | h_bp_count <= 0; 149 | h_frontporch <= 0; 150 | h_backporch <= 0; 151 | end else begin 152 | if( hsync_falling ) begin 153 | h_fp_count <= 8'b0; 154 | end else begin 155 | if( h_fp_count == 8'b1111_1111 ) begin 156 | h_fp_count <= h_fp_count; // saturate to catch de-only timings 157 | end else begin 158 | h_fp_count <= h_fp_count + 8'b1; 159 | end 160 | end 161 | 162 | if( de_rising ) begin 163 | h_frontporch <= h_fp_count + 8'b10; // this is a bit of a hack, why is one pixel missing? 164 | end else begin 165 | h_frontporch <= h_frontporch; 166 | end 167 | 168 | if( de_falling ) begin 169 | h_bp_count <= 0; 170 | end else begin 171 | if( h_bp_count == 8'b1111_1111 ) begin 172 | h_bp_count <= h_bp_count; 173 | end else begin 174 | h_bp_count <= h_bp_count + 8'b1; 175 | end 176 | end 177 | 178 | if( hsync_rising ) begin 179 | h_backporch <= h_bp_count; 180 | end else begin 181 | h_backporch <= h_backporch; 182 | end 183 | end // else: !if( rstin ) 184 | end // always @ (posedge pclk) 185 | 186 | //// vsync_width machine 187 | always @(posedge pclk or posedge rstin) begin 188 | if( rstin ) begin 189 | vsync_width <= 0; 190 | end else begin 191 | if( vsync_rising ) begin 192 | vsync_width <= vsync_width; 193 | // vcount is reset on vsync_rising as well 194 | end else begin 195 | if( vsync_falling ) begin 196 | vsync_width[23:0] <= vcount[23:0]; // counting in pixels 197 | end else begin 198 | vsync_width <= vsync_width; 199 | end 200 | end 201 | end 202 | end // always @ (posedge pclk) 203 | 204 | //// hsync_width machine 205 | always @(posedge pclk or posedge rstin) begin 206 | if( rstin ) begin 207 | hsync_width <= 0; 208 | hsync_width_cnt <= 8'b0; 209 | end else begin 210 | if( hsync_rising ) begin 211 | hsync_width <= hsync_width; 212 | hsync_width_cnt <= 8'b1; 213 | end else begin 214 | if( hsync_falling ) begin 215 | hsync_width <= hsync_width_cnt; 216 | end else begin 217 | hsync_width <= hsync_width; 218 | end 219 | hsync_width_cnt <= hsync_width_cnt + 8'b1; 220 | end 221 | end 222 | end // always @ (posedge pclk) 223 | 224 | //// vactive machine 225 | //// add detectors for lcd_de_latency and lcd_vsync_latency 226 | always @(posedge pclk or posedge rstin) begin 227 | if( rstin ) begin 228 | vactive <= 0; 229 | vactive_count <= 0; 230 | 231 | lcd_de_latency <= 0; 232 | lcd_vsync_latency <= 0; 233 | 234 | lcd_de_pclk <= 0; 235 | lcd_de_1pclk <= 0; 236 | lcd_de_2pclk <= 0; 237 | 238 | lcd_vsync_pclk <= 0; 239 | lcd_vsync_1pclk <= 0; 240 | lcd_vsync_2pclk <= 0; 241 | 242 | first_lcd_de_rising <= 1; 243 | end else begin // if ( rstin ) 244 | if( vsync_rising ) begin 245 | vactive <= vactive_count; 246 | vactive_count <= 0; 247 | end else begin 248 | if( de_rising ) begin // counting in lines 249 | vactive_count <= vactive_count + 12'b1; 250 | end else begin 251 | vactive_count <= vactive_count; 252 | end 253 | vactive <= vactive; 254 | end // else: !if( vsync_rising ) 255 | 256 | lcd_de_2pclk <= lcd_de; 257 | lcd_de_1pclk <= lcd_de_2pclk; 258 | lcd_de_pclk <= lcd_de_1pclk; 259 | 260 | lcd_vsync_2pclk <= lcd_vsync; 261 | lcd_vsync_1pclk <= lcd_vsync_2pclk; 262 | lcd_vsync_pclk <= lcd_vsync_1pclk; 263 | 264 | if( vsync_rising ) begin 265 | first_lcd_de_rising <= 1; 266 | end else begin 267 | if( !lcd_de_pclk & lcd_de_1pclk ) begin // rising edge 268 | first_lcd_de_rising <= 0; 269 | end else begin 270 | first_lcd_de_rising <= first_lcd_de_rising; 271 | end 272 | end 273 | 274 | // look for the rising edge 275 | if( !lcd_de_pclk & lcd_de_1pclk & first_lcd_de_rising ) begin 276 | lcd_de_latency <= vactive_count; 277 | end else begin 278 | lcd_de_latency <= lcd_de_latency; 279 | end 280 | 281 | // look for the rising edge 282 | if( !lcd_vsync_pclk & lcd_vsync_1pclk ) begin 283 | lcd_vsync_latency <= vactive_count; 284 | end else begin 285 | lcd_vsync_latency <= lcd_vsync_latency; 286 | end 287 | end // else: !if( rstin ) 288 | end // always @ (posedge pclk) 289 | 290 | //// hactive mcahine 291 | always @(posedge pclk or posedge rstin) begin 292 | if( rstin ) begin 293 | de_count <= 0; 294 | hactive <= 0; 295 | end else begin 296 | if( de_rising ) begin 297 | de_count <= 12'b1; // first pixel counts 298 | end else if( de ) begin 299 | de_count <= de_count + 12'b1; 300 | end else begin 301 | de_count <= de_count; 302 | end 303 | 304 | if( de_falling ) begin 305 | hactive <= de_count; 306 | end else begin 307 | hactive <= hactive; 308 | end 309 | end // else: !if( rstin ) 310 | end // always @ (posedge pclk) 311 | 312 | //// htotal, vtotal machine 313 | always @(posedge pclk or posedge rstin) begin 314 | if( rstin ) begin 315 | hcount <= 0; 316 | vcount <= 0; 317 | 318 | htotal <= 0; 319 | vtotal <= 0; 320 | end else begin 321 | if( vsync_rising ) begin 322 | vtotal <= vcount; 323 | vcount <= 24'b1; 324 | end else begin 325 | vcount <= vcount + 24'b1; /// counting in pixels 326 | vtotal <= vtotal; 327 | end 328 | 329 | if( de_rising ) begin 330 | htotal <= hcount; 331 | hcount <= 12'b1; 332 | end else begin 333 | hcount <= hcount + 12'b1; 334 | htotal <= htotal; 335 | end 336 | end // else: !if( rstin ) 337 | end // always @ (posedge pclk) 338 | 339 | //// refclock machine 340 | //// lots of cross-domain madness that might break things. 341 | always @(posedge refclk or posedge rstin) begin 342 | if( rstin ) begin 343 | refclkcnt <= 0; 344 | refclkcounter <= 0; 345 | 346 | vsync____refclk <= 0; 347 | vsync___refclk <= 0; 348 | vsync__refclk <= 0; 349 | vsync_refclk <= 0; 350 | end else begin 351 | vsync_refclk <= vsync__refclk; 352 | vsync__refclk <= vsync___refclk; 353 | vsync___refclk <= vsync____refclk; 354 | vsync____refclk <= vsync; 355 | 356 | if( vsync_refclk_rising ) begin 357 | refclkcnt <= refclkcounter; 358 | refclkcounter <= 24'b1; 359 | end else begin 360 | refclkcnt <= refclkcnt; 361 | refclkcounter <= refclkcounter + 24'b01; 362 | end 363 | 364 | end // else: !if( rstin ) 365 | end // always @ (posedge refclk or posedge rstin) 366 | assign vsync_refclk_rising = !vsync_refclk & vsync__refclk; 367 | 368 | 369 | //// rising/falling edge extraction machine 370 | always @(posedge pclk or posedge rstin) begin 371 | if(rstin) begin 372 | vsync_d <= 0; 373 | hsync_d <= 0; 374 | de_d <= 0; 375 | end else begin 376 | vsync_d <= vsync; 377 | hsync_d <= hsync; 378 | de_d <= de; 379 | end 380 | end // always @ (posedge pclk) 381 | 382 | assign vsync_rising = vsync & !vsync_d; 383 | assign hsync_rising = hsync & !hsync_d; 384 | assign de_rising = de & !de_d; 385 | 386 | assign vsync_falling = !vsync & vsync_d; 387 | assign hsync_falling = !hsync & hsync_d; 388 | assign de_falling = !de & de_d; 389 | 390 | endmodule // timing_detector 391 | -------------------------------------------------------------------------------- /sources_1/imports/common/i2c_squash_tb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | `timescale 1ns / 1ps 27 | 28 | //////////////////////////////////////////////////////////////////////////////// 29 | // Company: 30 | // Engineer: 31 | // 32 | // Create Date: 12:30:45 04/05/2011 33 | // Design Name: i2c_slave 34 | // Module Name: C:/largework/fpga/hdmi/impl4/common/i2c_slave_tb.v 35 | // Project Name: impl4 36 | // Target Device: 37 | // Tool versions: 38 | // Description: 39 | // 40 | // Verilog Test Fixture created by ISE for module: i2c_slave 41 | // 42 | // Dependencies: 43 | // 44 | // Revision: 45 | // Revision 0.01 - File Created 46 | // Additional Comments: 47 | // 48 | //////////////////////////////////////////////////////////////////////////////// 49 | 50 | module i2c_squash_tb; 51 | 52 | reg SDA; // physical wire state 53 | reg SCL; 54 | 55 | // Inputs 56 | reg clk; 57 | reg reset; 58 | reg [7:0] i2c_device_addr; 59 | reg [7:0] reg_addr; 60 | reg wr_stb; 61 | reg [7:0] reg_data_in; 62 | 63 | // Outputs 64 | wire SCL_pd; 65 | wire SDA_pd; 66 | wire SDA_pu; 67 | wire [7:0] reg_a0; 68 | wire [7:0] reg_a1; 69 | wire [7:0] reg_a2; 70 | wire [7:0] reg_a3; 71 | 72 | reg [7:0] snoop_addr; 73 | wire [7:0] snoop_data; 74 | 75 | wire DDC_SDA_pu; 76 | wire DDC_SDA_pd; 77 | wire [63:0] An; 78 | wire Aksv14_write; 79 | 80 | //`define FOO 81 | `ifdef FOO 82 | // Instantiate the Unit Under Test (UUT) 83 | i2c_snoop supa_snoopa ( 84 | .SCL(SCL), 85 | .SDA(SDA), 86 | .clk(clk), 87 | .reset(reset), 88 | .i2c_snoop_addr(8'h74), 89 | .reg_addr(snoop_addr), 90 | .reg_dout(snoop_data), 91 | .An(An), 92 | .Aksv14_write(Aksv14_write) 93 | ); 94 | `endif 95 | 96 | // Instantiate the Unit Under Test (UUT) 97 | i2c_slave target ( 98 | .SCL(SCL), 99 | .SCL_pd(SCL_pd), 100 | .SDA(SDA), 101 | .SDA_pd(SDA_pd_comb), 102 | .SDA_pu(SDA_pu_comb), 103 | .clk(clk), 104 | .reset(reset), 105 | .i2c_device_addr(i2c_device_addr), 106 | .reg_addr(reg_addr), 107 | .wr_stb(wr_stb), 108 | .reg_data_in(reg_data_in), 109 | .reg_0(reg_a0), 110 | .reg_1(reg_a1), 111 | .reg_2(reg_a2), 112 | .reg_3(reg_a3) 113 | ); 114 | i2c_squash_edid ddc_edid_squash ( 115 | .SCL(SCL), 116 | .SDA(SDA), 117 | .clk(clk), 118 | .reset(reset), 119 | 120 | .SDA_pu(DDC_SDA_pu), 121 | .SDA_pd(DDC_SDA_pd), 122 | 123 | .i2c_snoop_addr(8'h74) // EDID address 124 | ); 125 | 126 | reg sda_host; // what the host is driving to 127 | reg scl_host; 128 | reg ack; // what the ack state is 129 | reg [7:0] readdata; 130 | 131 | wire SDA_pu_comb; 132 | wire SDA_pd_comb; 133 | 134 | assign SDA_pu = SDA_pu_comb | DDC_SDA_pu; 135 | assign SDA_pd = SDA_pd_comb | DDC_SDA_pd; 136 | 137 | // always @(SCL_pd, SDA_pd, SDA_pu, sda_host, scl_host) begin 138 | always @(*) begin // lazy 139 | // scl equations 140 | case( {SCL_pd, scl_host} ) 141 | 2'b00: SCL <= 1'b0; 142 | 2'b01: SCL <= 1'b1; 143 | 2'b10: SCL <= 1'b0; 144 | // conflict case 145 | 2'b11: SCL <= 1'bX; 146 | // handle tristate case 147 | 2'b0Z: SCL <= 1'b1; 148 | 2'b1Z: SCL <= 1'b0; 149 | default: SCL <= 1'bX; 150 | endcase // case ( {SCL_pd, scl_host} ) 151 | 152 | case( {SDA_pd, SDA_pu, sda_host} ) 153 | 3'b000: SDA <= 1'b0; 154 | 3'b001: SDA <= 1'b1; 155 | 3'b010: SDA <= 1'bX; // change to 1'b1 for override 156 | 3'b011: SDA <= 1'b1; 157 | 3'b100: SDA <= 1'b0; 158 | 3'b101: SDA <= 1'bX; // change to 1'b0 for override 159 | 3'b110: SDA <= 1'bX; 160 | 3'b111: SDA <= 1'bX; 161 | 162 | // tristate case 163 | 3'b00Z: SDA <= 1'b1; 164 | 3'b01Z: SDA <= 1'b1; 165 | 3'b10Z: SDA <= 1'b0; 166 | 3'b11Z: SDA <= 1'bX; 167 | endcase // case ( {SDA_pd, SDA_pu, sda_host} ) 168 | end 169 | 170 | parameter PERIOD = 16'd40; // 25 MHz 171 | parameter I2C_PD = 16'd2464; // make it odd to try and catch non-phase synced issues 172 | parameter I2C_TH = 16'd114; 173 | parameter I2C_TS = 16'd217; 174 | 175 | always begin 176 | clk = 1'b0; 177 | #(PERIOD/2) clk = 1'b1; 178 | #(PERIOD/2); 179 | end 180 | 181 | task I2C_idle; 182 | begin 183 | scl_host = 1'bZ; 184 | sda_host = 1'bZ; 185 | #I2C_PD; 186 | end 187 | endtask // I2C_idle 188 | 189 | task I2C_start; 190 | begin 191 | scl_host = 1'bZ; 192 | sda_host = 1'bZ; 193 | #(I2C_PD/2); 194 | scl_host = 1'bZ; 195 | sda_host = 1'b0; 196 | #(I2C_PD/2); 197 | end 198 | endtask // I2C_start 199 | 200 | task I2C_stop; 201 | begin 202 | scl_host = 1'bZ; 203 | sda_host = 1'b0; 204 | #(I2C_PD/2); 205 | scl_host = 1'bZ; 206 | sda_host = 1'bZ; 207 | #(I2C_PD/2); 208 | end 209 | endtask // I2C_start 210 | 211 | task I2C_tx_bit; // tx from host ( from testbench ) 212 | input bitval; 213 | 214 | begin 215 | scl_host = 1'b0; 216 | #I2C_TH; 217 | sda_host = bitval; 218 | #(I2C_PD/2); 219 | scl_host = 1'bZ; 220 | sda_host = bitval; 221 | #(I2C_PD/2); 222 | end 223 | endtask // I2C_tx_bit 224 | 225 | task I2C_rx_bit; // rx to host ( to testbench ) 226 | output bitval; 227 | 228 | begin 229 | scl_host = 1'b0; 230 | #(I2C_TH/2); 231 | sda_host = 1'bz; 232 | #(I2C_PD/2); 233 | scl_host = 1'bZ; 234 | sda_host = 1'bz; 235 | #1; 236 | bitval = SDA; 237 | #(I2C_PD/2); 238 | end 239 | endtask // I2C_start 240 | 241 | task I2C_ack_low; 242 | begin 243 | scl_host = 1'b0; 244 | #(I2C_PD/2); 245 | end 246 | endtask // I2C_ack_low 247 | 248 | 249 | task I2C_tx_daddr; 250 | input [7:0] daddr; 251 | output rack; 252 | 253 | begin 254 | I2C_tx_bit( daddr[7] ); 255 | I2C_tx_bit( daddr[6] ); 256 | I2C_tx_bit( daddr[5] ); 257 | I2C_tx_bit( daddr[4] ); 258 | I2C_tx_bit( daddr[3] ); 259 | I2C_tx_bit( daddr[2] ); 260 | I2C_tx_bit( daddr[1] ); 261 | I2C_tx_bit( daddr[0] ); 262 | I2C_rx_bit(rack); 263 | I2C_ack_low(); 264 | end 265 | endtask // I2C_TX_DADDR 266 | 267 | task I2C_rx_daddr; 268 | output [7:0] daddr; 269 | input nack; 270 | 271 | begin 272 | I2C_rx_bit(daddr[7]); 273 | I2C_rx_bit(daddr[6]); 274 | I2C_rx_bit(daddr[5]); 275 | I2C_rx_bit(daddr[4]); 276 | I2C_rx_bit(daddr[3]); 277 | I2C_rx_bit(daddr[2]); 278 | I2C_rx_bit(daddr[1]); 279 | I2C_rx_bit(daddr[0]); 280 | I2C_tx_bit( nack ); 281 | I2C_ack_low(); 282 | end 283 | endtask // I2C_RX_DADDR 284 | 285 | initial begin 286 | // Initialize Inputs 287 | clk = 0; 288 | reset = 0; 289 | i2c_device_addr = 8'h74; 290 | reg_addr = 0; 291 | wr_stb = 0; 292 | reg_data_in = 0; 293 | snoop_addr = 0; 294 | 295 | $stop; 296 | 297 | I2C_idle(); 298 | // run an actual reset cycle 299 | #(PERIOD*4); 300 | reset = 1; 301 | #(PERIOD*4); 302 | reset = 0; 303 | #(PERIOD*4); 304 | 305 | // now pre-set a few I2C registers 306 | reg_addr = 0; 307 | wr_stb = 1; 308 | reg_data_in = 8'hDE; 309 | #(PERIOD*4); 310 | 311 | wr_stb = 0; 312 | #(PERIOD*1); 313 | 314 | reg_addr = 1; 315 | wr_stb = 1; 316 | reg_data_in = 8'hAD; 317 | #(PERIOD*2); 318 | 319 | wr_stb = 0; 320 | #(PERIOD*1); 321 | 322 | reg_addr = 2; 323 | wr_stb = 1; 324 | reg_data_in = 8'hBE; 325 | #(PERIOD*2); 326 | 327 | wr_stb = 0; 328 | #(PERIOD*1); 329 | 330 | reg_addr = 3; 331 | wr_stb = 1; 332 | reg_data_in = 8'hEF; 333 | #(PERIOD*2); 334 | 335 | 336 | // let it soak for a bit for good measure 337 | #(PERIOD*10); 338 | 339 | // now the real sim starts 340 | I2C_idle(); 341 | 342 | // write some data 343 | I2C_start(); 344 | I2C_tx_daddr(8'h74, ack); // write to device 72 345 | I2C_tx_daddr(8'h01, ack); // address 01 346 | I2C_tx_daddr(8'h33, ack); // data 55 347 | I2C_stop(); 348 | #(I2C_PD*5); 349 | 350 | // do a multi-cycle read 351 | I2C_start(); 352 | I2C_tx_daddr(8'h74, ack); // dummy write to 72 353 | I2C_tx_daddr(8'h00, ack); // address 00 354 | I2C_start(); 355 | I2C_tx_daddr(8'h75, ack); // read from 72 356 | // #(I2C_PD*3); 357 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 358 | // #(I2C_PD*3); 359 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 360 | I2C_rx_daddr(readdata, 1'b0); // data @ address 0 361 | I2C_rx_daddr(readdata, 1'bz); // data @ address 0 362 | I2C_stop(); 363 | #(I2C_PD*5); 364 | 365 | // do a multi-cycle write 366 | I2C_start(); 367 | I2C_tx_daddr(8'h74, ack); // write to device 70 368 | I2C_tx_daddr(8'h01, ack); // address 01 369 | I2C_tx_daddr(8'hFA, ack); 370 | I2C_tx_daddr(8'hCE, ack); 371 | I2C_tx_daddr(8'h69, ack); 372 | I2C_stop(); 373 | #(I2C_PD*5); 374 | 375 | #I2C_PD; 376 | #I2C_PD; 377 | snoop_addr = 8'h01; 378 | #I2C_PD; 379 | snoop_addr = 8'h02; 380 | #I2C_PD; 381 | snoop_addr = 8'h03; 382 | #I2C_PD; 383 | snoop_addr = 8'h04; 384 | #I2C_PD; 385 | snoop_addr = 8'h05; 386 | #I2C_PD; 387 | #I2C_PD; 388 | 389 | // read back one address at a time 390 | I2C_start(); 391 | I2C_tx_daddr(8'h74, ack); // dummy write to 72 392 | I2C_tx_daddr(8'h00, ack); // address 00 393 | 394 | #(I2C_PD*5); 395 | I2C_start(); 396 | I2C_tx_daddr(8'h75, ack); // read from 72 397 | I2C_rx_daddr(readdata, 1'bz); // one read 398 | I2C_stop(); 399 | 400 | // this is the only questionable vector 401 | // if you do an isolated read, should the address have 402 | // incremeted from the previous read, or 403 | // should it be the same. I have implemented it so 404 | // that it increments. 405 | I2C_start(); 406 | I2C_tx_daddr(8'h75, ack); // read from 72 407 | I2C_rx_daddr(readdata, 1'bz); // one read 408 | I2C_stop(); 409 | 410 | #(I2C_PD*5); 411 | 412 | I2C_start(); 413 | I2C_tx_daddr(8'h75, ack); // read from 72 414 | I2C_rx_daddr(readdata, 1'b0); // one read 415 | I2C_rx_daddr(readdata, 1'bz); // one read 416 | I2C_stop(); 417 | 418 | 419 | // write to another device not us 420 | I2C_start(); 421 | I2C_tx_daddr(8'hA0, ack); // write to device a0 422 | I2C_tx_daddr(8'h01, ack); // address 01 423 | I2C_tx_daddr(8'h55, ack); // data 55 -- this should be ignored 424 | I2C_stop(); 425 | 426 | #I2C_PD; 427 | #I2C_PD; 428 | snoop_addr = 8'h01; 429 | #I2C_PD; 430 | snoop_addr = 8'h02; 431 | #I2C_PD; 432 | snoop_addr = 8'h03; 433 | #I2C_PD; 434 | snoop_addr = 8'h04; 435 | #I2C_PD; 436 | snoop_addr = 8'h05; 437 | #I2C_PD; 438 | #I2C_PD; 439 | #I2C_PD; 440 | #I2C_PD; 441 | 442 | end 443 | 444 | endmodule // i2c_squash_tb 445 | 446 | -------------------------------------------------------------------------------- /constrs_1/imports/release1/release1.ucf: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | ## Copyright (c) 2011, Andrew "bunnie" Huang 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without modification, 6 | ## are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, 9 | ## this list of conditions and the following disclaimer. 10 | ## * Redistributions in binary form must reproduce the above copyright notice, 11 | ## this list of conditions and the following disclaimer in the documentation and/or 12 | ## other materials provided with the distribution. 13 | ## 14 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | ## EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | ## OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | ## SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | ## INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | ## LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | ## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | ## WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | ## POSSIBILITY OF SUCH DAMAGE. 24 | ## 25 | ############################################################################## 26 | 27 | ########################################### 28 | # Setting VCCAUX for Spartan 6 TMDS 29 | ########################################### 30 | CONFIG VCCAUX = 3.3; 31 | 32 | # 33 | # Constraint for RX0 34 | # 35 | #NET "dvi_rx0/rxclk" TNM_NET = "DVI_CLOCK0"; 36 | #TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 155 MHz HIGH 50%; 37 | # 38 | # Multi-cycle paths for TX0 39 | # 40 | TIMEGRP bramgrp_0 = RAMS("dvi_tx0/pixel2x/dataint[*]"); 41 | TIMEGRP fddbgrp_0 = FFS("dvi_tx0/pixel2x/db[*]"); 42 | TIMEGRP bramra_0 = FFS("dvi_tx0/pixel2x/ra[*]"); 43 | 44 | TIMESPEC TS_ramdo_0 = FROM "bramgrp_0" TO "fddbgrp_0" TS_pixclocks ; 45 | TIMESPEC TS_ramra_0 = FROM "bramra_0" TO "fddbgrp_0" TS_pixclocks ; 46 | 47 | ############################################################################## 48 | # SYSCLK Input 49 | ############################################################################## 50 | NET "clk26" IOSTANDARD = LVCMOS33; 51 | NET "clk26" LOC = P21; 52 | #NET "clk26" TNM_NET = "clk26"; 53 | #TIMESPEC TS_clk26_ = PERIOD "clk26" 26 MHz HIGH 50 % PRIORITY 255; 54 | 55 | ############################################ 56 | # TMDS pairs for output 57 | ############################################ 58 | # Clock 59 | NET "TX0_TMDS[3]" IOSTANDARD = TMDS_33; 60 | NET "TX0_TMDSB[3]" IOSTANDARD = TMDS_33; 61 | #INST "dvi_tx0/clkout/oserdes_s" LOC = OLOGIC_X6Y0; 62 | INST "dvi_tx0/TMDS3" LOC = P51; 63 | #INST "dvi_tx0/clkout/oserdes_m" LOC = OLOGIC_X6Y1; 64 | NET "dvi_tx0/TMDS[3]" LOC = P51; 65 | NET "dvi_tx0/TMDSB[3]" LOC = P50; 66 | # Red 67 | NET "TX0_TMDS[2]" IOSTANDARD = TMDS_33; 68 | NET "TX0_TMDSB[2]" IOSTANDARD = TMDS_33; 69 | INST "dvi_tx0/TMDS2" LOC = P62; 70 | #INST "dvi_tx0/oserdes2/oserdes_s" LOC = OLOGIC_X10Y2; 71 | #INST "dvi_tx0/oserdes2/oserdes_m" LOC = OLOGIC_X10Y3; 72 | NET "dvi_tx0/TMDS[2]" LOC = P62; 73 | NET "dvi_tx0/TMDSB[2]" LOC = P61; 74 | # Green 75 | NET "TX0_TMDS[1]" IOSTANDARD = TMDS_33; 76 | NET "TX0_TMDSB[1]" IOSTANDARD = TMDS_33; 77 | #INST "dvi_tx0/oserdes1/oserdes_s" LOC = OLOGIC_X9Y2; 78 | INST "dvi_tx0/TMDS1" LOC = P58; 79 | #INST "dvi_tx0/oserdes1/oserdes_m" LOC = OLOGIC_X9Y3; 80 | NET "dvi_tx0/TMDS[1]" LOC = P58; 81 | NET "dvi_tx0/TMDSB[1]" LOC = P57; 82 | # Blue 83 | NET "TX0_TMDS[0]" IOSTANDARD = TMDS_33; 84 | NET "TX0_TMDSB[0]" IOSTANDARD = TMDS_33; 85 | #INST "dvi_tx0/oserdes0/oserdes_s" LOC = OLOGIC_X7Y2; 86 | INST "dvi_tx0/TMDS0" LOC = P56; 87 | #INST "dvi_tx0/oserdes0/oserdes_m" LOC = OLOGIC_X7Y3; 88 | NET "dvi_tx0/TMDS[0]" LOC = P56; 89 | NET "dvi_tx0/TMDSB[0]" LOC = P55; 90 | 91 | ############################################## 92 | # TMDS pairs for input 93 | ############################################## 94 | # CLK 95 | NET "RX0_TMDS[3]" IOSTANDARD = TMDS_33; 96 | NET "dvi_rx0/tmdsclk_p" LOC = P124; 97 | NET "RX0_TMDSB[3]" IOSTANDARD = TMDS_33; 98 | NET "dvi_rx0/tmdsclk_n" LOC = P123; 99 | # Red 100 | NET "RX0_TMDS[2]" IOSTANDARD = TMDS_33; 101 | NET "dvi_rx0/dec_r/des_0/datain_p" LOC = P134; 102 | NET "RX0_TMDSB[2]" IOSTANDARD = TMDS_33; 103 | NET "dvi_rx0/dec_r/des_0/datain_n" LOC = P133; 104 | # Green 105 | NET "RX0_TMDS[1]" IOSTANDARD = TMDS_33; 106 | NET "dvi_rx0/dec_g/des_0/datain_p" LOC = P132; 107 | NET "RX0_TMDSB[1]" IOSTANDARD = TMDS_33; 108 | NET "dvi_rx0/dec_g/des_0/datain_n" LOC = P131; 109 | # Blue 110 | NET "RX0_TMDS[0]" IOSTANDARD = TMDS_33; 111 | NET "dvi_rx0/dec_b/des_0/datain_p" LOC = P127; 112 | NET "RX0_TMDSB[0]" IOSTANDARD = TMDS_33; 113 | NET "dvi_rx0/dec_b/des_0/datain_n" LOC = P126; 114 | 115 | ######## 116 | # video in 117 | ######## 118 | #R0 119 | NET "LCD_R[2]" IOSTANDARD = LVCMOS33; 120 | NET "LCD_R[2]" LOC = P38; 121 | #R1 122 | NET "LCD_R[3]" IOSTANDARD = LVCMOS33; 123 | NET "LCD_R[3]" LOC = P27; 124 | #R2 125 | NET "LCD_R[4]" IOSTANDARD = LVCMOS33; 126 | NET "LCD_R[4]" LOC = P16; 127 | #R3 128 | NET "LCD_R[5]" IOSTANDARD = LVCMOS33; 129 | NET "LCD_R[5]" LOC = P23; 130 | #R4 131 | NET "LCD_R[6]" IOSTANDARD = LVCMOS33; 132 | NET "LCD_R[6]" LOC = P22; 133 | #R5 134 | NET "LCD_R[7]" IOSTANDARD = LVCMOS33; 135 | NET "LCD_R[7]" LOC = P15; 136 | #G0 137 | NET "LCD_G[2]" IOSTANDARD = LVCMOS33; 138 | NET "LCD_G[2]" LOC = P29; 139 | #G1 140 | NET "LCD_G[3]" IOSTANDARD = LVCMOS33; 141 | NET "LCD_G[3]" LOC = P34; 142 | #G2 143 | NET "LCD_G[4]" IOSTANDARD = LVCMOS33; 144 | NET "LCD_G[4]" LOC = P14; 145 | #G3 146 | NET "LCD_G[5]" IOSTANDARD = LVCMOS33; 147 | NET "LCD_G[5]" LOC = P12; 148 | #G4 149 | NET "LCD_G[6]" IOSTANDARD = LVCMOS33; 150 | NET "LCD_G[6]" LOC = P26; 151 | #G5 152 | NET "LCD_G[7]" IOSTANDARD = LVCMOS33; 153 | NET "LCD_G[7]" LOC = P30; 154 | NET "LCDO_DCLK" IOSTANDARD = LVCMOS33; 155 | NET "LCDO_DCLK" SLEW = SLOW; 156 | NET "LCDO_DCLK" LOC = P17; 157 | NET "LCDO_DCLK" DRIVE = 4; 158 | NET "LCD_DE" IOSTANDARD = LVCMOS33; 159 | NET "LCD_DE" LOC = P24; 160 | NET "LCD_HSYNC" IOSTANDARD = LVCMOS33; 161 | NET "LCD_HSYNC" LOC = P33; 162 | NET "LCD_VSYNC" IOSTANDARD = LVCMOS33; 163 | NET "LCD_VSYNC" LOC = P35; 164 | #B0 165 | NET "LCD_B[2]" IOSTANDARD = LVCMOS33; 166 | NET "LCD_B[2]" LOC = P11; 167 | #B1 168 | NET "LCD_B[3]" IOSTANDARD = LVCMOS33; 169 | NET "LCD_B[3]" LOC = P10; 170 | #B2 171 | NET "LCD_B[4]" IOSTANDARD = LVCMOS33; 172 | NET "LCD_B[4]" LOC = P32; 173 | #B3 174 | NET "LCD_B[5]" IOSTANDARD = LVCMOS33; 175 | NET "LCD_B[5]" LOC = P40; 176 | #B4 177 | NET "LCD_B[6]" IOSTANDARD = LVCMOS33; 178 | NET "LCD_B[6]" LOC = P9; 179 | #B5 180 | NET "LCD_B[7]" IOSTANDARD = LVCMOS33; 181 | NET "LCD_B[7]" LOC = P8; 182 | 183 | NET "VSYNC_STB" IOSTANDARD = LVCMOS33; 184 | NET "VSYNC_STB" LOC = P41; 185 | NET "HPD_NOTIFY" IOSTANDARD = LVCMOS33; 186 | NET "HPD_NOTIFY" LOC = P7; 187 | NET "HDCP_AKSV" IOSTANDARD = LVCMOS33; 188 | NET "HDCP_AKSV" LOC = P5; 189 | NET "LOWVOLT_NOTIFY" IOSTANDARD = LVCMOS33; 190 | NET "LOWVOLT_NOTIFY" LOC = P1; 191 | NET "SOURCE_NOTIFY" IOSTANDARD = LVCMOS33; 192 | NET "SOURCE_NOTIFY" LOC = P140; 193 | 194 | NET "SDA" LOC = P105; 195 | NET "SDA" IOSTANDARD = LVCMOS33; 196 | NET "SCL" IOSTANDARD = LVCMOS33; 197 | NET "SCL" LOC = P104; 198 | 199 | NET "DDC_SCL" IOSTANDARD = LVCMOS33; 200 | NET "DDC_SCL" LOC = P99; 201 | NET "DDC_SDA" IOSTANDARD = LVCMOS33; 202 | NET "DDC_SDA" LOC = P100; 203 | NET "HPD_N" IOSTANDARD = LVCMOS33; 204 | NET "HPD_N" LOC = P98; 205 | NET "HPD_OVERRIDE" IOSTANDARD = LVCMOS33; 206 | NET "HPD_OVERRIDE" LOC = P111; 207 | 208 | NET "DDC_SDA_PU" IOSTANDARD = LVCMOS33; 209 | NET "DDC_SDA_PU" LOC = P66; 210 | NET "DDC_SDA_PD" IOSTANDARD = LVCMOS33; 211 | NET "DDC_SDA_PD" LOC = P67; 212 | 213 | ######################################## 214 | # Reset button and LEDs and Mechanical Switches (SW) 215 | ######################################## 216 | 217 | # nonsense pin for now 218 | # add a pull-up, and check it happens in synthesis 219 | NET "rstbtn_n" IOSTANDARD = LVCMOS33; 220 | NET "rstbtn_n" PULLUP; 221 | NET "rstbtn_n" LOC = P115; 222 | NET "LED0" IOSTANDARD = LVCMOS33; 223 | NET "LED0" LOC = P138; 224 | NET "LED1" IOSTANDARD = LVCMOS33; 225 | NET "LED1" LOC = P137; 226 | 227 | NET "CEC" LOC = P47; 228 | NET "CEC" IOSTANDARD = LVCMOS33; 229 | 230 | NET "CHUMBY_BEND" LOC = P2; 231 | NET "CHUMBY_BEND" IOSTANDARD = LVCMOS33; 232 | 233 | NET "LOWVOLT_N" IOSTANDARD = LVCMOS33; 234 | NET "LOWVOLT_N" LOC = P44; 235 | NET "LOWVOLT_N" PULLUP; 236 | 237 | ################################## 238 | ## timing constraints 239 | ################################## 240 | 241 | ###### 26 mhz clock period constraint 242 | NET "clk26" TNM_NET = "clk26_pin"; 243 | TIMESPEC TS_26mpin = PERIOD "clk26_pin" 26 MHz HIGH 50%; 244 | NET "clk26buf" TNM_NET = "clk26_tnm"; 245 | TIMESPEC TS_26m = PERIOD "clk26_tnm" 26 MHz HIGH 50%; 246 | 247 | ###### clock period spec 248 | NET "RX0_TMDS[3]" TNM_NET = "RXCLK_PIN"; 249 | TIMESPEC TS_RXCLK_PIN = PERIOD "RXCLK_PIN" 74.25 MHz HIGH 50% PRIORITY -1; 250 | 251 | NET "RX0_TMDSB[3]" TNM_NET = "RXCLKB_PIN"; 252 | TIMESPEC TS_RXCLKB_PIN = PERIOD "RXCLKB_PIN" 74.25 MHz HIGH 50% PRIORITY -1; 253 | 254 | # manually propagated constraint 255 | NET "dvi_rx0/pclk" TNM = "pixclocks"; 256 | TIMESPEC TS_pixclocks = PERIOD "pixclocks" 74.25 MHz; 257 | 258 | NET "dvi_rx0/pclkx2" TNM_NET = "pclkx2"; 259 | TIMESPEC TS_pclkx2 = PERIOD "pclkx2" 148.5 MHz; 260 | 261 | NET "dvi_rx0/pclkx10" TNM_NET = "pclkx10"; 262 | TIMESPEC TS_pclkx10 = PERIOD "pclkx10" 742.5 MHz; 263 | 264 | NET "dvi_rx0/rxclk" TNM_NET = "rxclk_to_dcm"; 265 | TIMESPEC TS_rxclk_to_dcm = PERIOD "rxclk_to_dcm" 74.25 MHz; 266 | 267 | NET "tx0_pclk" TNM_NET = "tx0_pclk_net"; 268 | TIMESPEC TS_tx0_pclk = PERIOD "tx0_pclk_net" 74.25 MHz; 269 | 270 | NET "selfclockgen/clkfx" TNM_NET = "self_clk"; 271 | TIMESPEC TS_selfclk = PERIOD "self_clk" 74.285 MHz; 272 | 273 | NET "clk2M" TNM_NET = "clk2M_net"; 274 | TIMESPEC TS_clk2M = PERIOD "clk2M_net" 815 kHz; 275 | 276 | ######## input pad timing constraints 277 | NET "LCD_*" TNM = PADS(LCD_*) "lcd_pads"; 278 | OFFSET = IN 5 ns BEFORE "tx0_pclk" TIMEGRP "lcd_pads"; 279 | 280 | ######## TIG constraints 281 | NET "clk26buf" TNM_NET = FFS "I2C_REGS"; 282 | NET "dvi_rx0/pclk" TNM_NET = FFS "rx_REGS"; 283 | NET "tx0_pclk" TNM_NET = FFS "tx_REGS"; 284 | NET "rx0_pllclk1" TNM_NET = FFS "td_REGS"; # used by timing detector in some versions 285 | NET "tx0_pclk" TNM_NET = RAMS "tx_RAMS"; 286 | NET "tx0_pclk" TNM_NET = BRAMS_PORTA "tx_RAMSA"; 287 | NET "tx0_pclk" TNM_NET = BRAMS_PORTB "tx_RAMSB"; 288 | NET "selfclockgen/clkfx" TNM_NET = FFS "self_REGS"; 289 | TIMEGRP "tx0_syncgrp" = "tx_REGS" "tx_RAMS" "tx_RAMSA" "tx_RAMSB"; 290 | 291 | # I2C programming TIGs 292 | NET "host_i2c/I2C_reg_update" TNM = I2C_reg_exception; 293 | NET "ddc_hdcp_snoop/I2C_reg_update" TNM = I2C_reg_exception; 294 | NET "ddc_hdcp_snoop/Aksv14_write_rstpot" TNM = I2C_REG_exception; 295 | TIMESPEC TS_false_txw = FROM "I2C_reg_exception" TO "tx_REGS" TIG ; 296 | TIMESPEC TS_false_txr = FROM "tx_REGS" TO "I2C_reg_exception" TIG ; 297 | TIMESPEC TS_false_txd = FROM "td_REGS" TO "I2C_REGS" TIG ; 298 | 299 | TIMESPEC TS_false_rxw = FROM "I2C_reg_exception" TO "rx_REGS" TIG ; # there are none of these btw 300 | TIMESPEC TS_false_rxr = FROM "rx_REGS" TO "I2C_reg_exception" TIG ; 301 | 302 | TIMESPEC TS_false_self = FROM "I2C_reg_exception" TO "self_REGS" TIG ; 303 | 304 | # reset TIGs 305 | NET "tx0_reset" TIG; 306 | 307 | # self-clock TIGs 308 | NET "selfclockgen/clkfx" TNM_NET = "self_REGS"; 309 | TIMESPEC TS_false_self_tx = FROM "self_REGS" TO "tx_REGS" TIG ; 310 | TIMESPEC TS_false_self_i2c = FROM "self_REGS" TO "I2C_REGS" TIG ; 311 | 312 | ######## fix-up constraints 313 | TIMESPEC TS_TX_SYNC = FROM "tx0_syncgrp" TO "tx0_syncgrp" 74.25MHz; 314 | #TIMESPEC TS_DP_FFS = FROM "tx_REGS" TO "tx_REGS" 74.25MHz; 315 | #TIMESPEC TS_RAMS_FFS = FROM "tx_RAMS" TO "tx_REGS" 74.25MHz; 316 | #TIMESPEC TS_FFS_RAMS = FROM "tx_REGS" TO "tx_RAMS" 74.25MHz; 317 | 318 | TIMESPEC TS_RX0_FFS = FROM "rx_REGS" TO "rx_REGS" 74.25MHz; 319 | TIMESPEC TS_RXTX_FFS = FROM "rx_REGS" TO "tx_REGS" 74.25MHz; 320 | 321 | 322 | ### comment out during self-timed mode 323 | NET "dvi_rx0/bufpll_lock" TIG; 324 | 325 | ### remove comment during self-timed mode 326 | #NET "clk26" CLOCK_DEDICATED_ROUTE = FALSE; 327 | #NET "comp_ctl[6]" TIG; 328 | 329 | 330 | #################### LEGACY ##################### 331 | 332 | #Created by Constraints Editor (xc6slx9-tqg144-2) - 2011/03/16 333 | #NET "RX0_TMDS[3]" TNM_NET = "RX0_TMDS<3>"; 334 | # limited by ADVPLL spec 335 | #TIMESPEC TS_RX0_TMDS_3_ = PERIOD "RX0_TMDS<3>" 95 MHz HIGH 50 % PRIORITY 1; 336 | #TIMESPEC TS_RX0_TMDS_3_ = PERIOD "RX0_TMDS<3>" 35.34 ns HIGH 50%; # 480p/60 337 | #TIMESPEC TS_RX0_TMDS_3_ = PERIOD "RX0_TMDS<3>" 13.48 ns HIGH 50%; # 720p/60 338 | 339 | #NET "RX0_TMDSB[3]" TNM_NET = "RX0_TMDSB<3>"; 340 | #TIMESPEC TS_RX0_TMDSB_3_ = PERIOD "RX0_TMDSB<3>" 95 MHz HIGH 50 % PRIORITY 1; 341 | #TIMESPEC TS_RX0_TMDS_3_ = PERIOD "RX0_TMDSB<3>" 35.34 ns HIGH 50%; # 480p/60 342 | #TIMESPEC TS_RX0_TMDS_3_ = PERIOD "RX0_TMDSB<3>" 13.48 ns HIGH 50%; # 720p/60 343 | 344 | #NET "tx0_pclk" TNM_NET = "tx0_pclk"; 345 | #TIMESPEC TS_tx0_pclk = PERIOD "tx0_pclk" 74.25 MHz HIGH 50 % PRIORITY 2; 346 | 347 | #TIMESPEC TS_LCD_DCLK = PERIOD "LCD_DCLK" 74.25 MHz PRIORITY 200; 348 | #TIMESPEC TS_rx_clk = PERIOD "rx_clk" 74.25 MHz PRIORITY 1; 349 | #NET "LCD_DCLK" TNM_NET = "LCD_DCLK"; 350 | #NET "dvi_rx0/rxclk" TNM_NET = "rx_clk"; 351 | 352 | #TIMESPEC TS_rxclk_main = PERIOD "rxclk_main" 74.25 MHz PRIORITY 1; 353 | 354 | #NET "RX0_TMDS[3]" TNM_NET = "rxclk_main"; 355 | #TIMESPEC TS_rxclk_main_b = PERIOD "rxclk_main_b" 74.25 MHz PRIORITY 1; 356 | #NET "RX0_TMDSB[3]" TNM_NET = "rxclk_main_b"; 357 | #NET "clk26buf_BUFG" TNM = "clk26_tnm"; 358 | -------------------------------------------------------------------------------- /sources_1/imports/release1/hdcp/hdcp_cipher.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | // generates a stream of hdcp cipher data 30 | module hdcp_cipher( 31 | input wire clk, 32 | input reset, 33 | 34 | input [55:0] Km, // shared secret value 35 | input [63:0] An, // session random number 36 | 37 | input hdcpBlockCipher_init, // pulsed only one cycle 38 | input authentication, // pulsed one cycle same time as above 39 | input hdcpRekeyCipher, // pulsed one cycle to initiate rekey 40 | input hdcpStreamCipher,// advance cipher state one clock 41 | output [23:0] pr_data, // pseudorandom data output 42 | output reg stream_ready // asserted when stream is ready (after init seq) 43 | ); 44 | 45 | wire lfsr_out; 46 | wire [23:0] ostream; 47 | wire [83:0] Bo_wire; 48 | 49 | parameter INIT = 12'b1 << 0; 50 | parameter BLOCK_1 = 12'b1 << 1; 51 | parameter BLOCK_2 = 12'b1 << 2; 52 | parameter BLOCK_3 = 12'b1 << 3; 53 | parameter BLOCK_4 = 12'b1 << 4; 54 | parameter BLOCK_5 = 12'b1 << 5; 55 | parameter BLOCK_6 = 12'b1 << 6; 56 | parameter BLOCK_7 = 12'b1 << 7; 57 | parameter BLOCK_8 = 12'b1 << 8; 58 | parameter BLOCK_9 = 12'b1 << 9; 59 | parameter GET_M = 12'b1 << 10; 60 | parameter STREAM = 12'b1 << 11; 61 | parameter REKEY = 12'b1 << 12; 62 | parameter nSTATES = 13; 63 | 64 | reg [(nSTATES-1):0] cstate = {{(nSTATES-1){1'b0}},1'b1}; 65 | reg [(nSTATES-1):0] nstate; 66 | 67 | // `define SIMULATION 1 68 | `ifdef SIMULATION 69 | // synthesis translate_off 70 | reg [8*20:1] state_ascii = "INIT "; 71 | always @(cstate) begin 72 | if (cstate == INIT ) state_ascii <= "INIT "; 73 | else if (cstate == BLOCK_1 ) state_ascii <= "BLOCK_1 "; 74 | else if (cstate == BLOCK_2 ) state_ascii <= "BLOCK_2 "; 75 | else if (cstate == BLOCK_3 ) state_ascii <= "BLOCK_3 "; 76 | else if (cstate == BLOCK_4 ) state_ascii <= "BLOCK_4 "; 77 | else if (cstate == BLOCK_5 ) state_ascii <= "BLOCK_5 "; 78 | else if (cstate == BLOCK_6 ) state_ascii <= "BLOCK_6 "; 79 | else if (cstate == BLOCK_7 ) state_ascii <= "BLOCK_7 "; 80 | else if (cstate == BLOCK_8 ) state_ascii <= "BLOCK_8 "; 81 | else if (cstate == BLOCK_9 ) state_ascii <= "BLOCK_9 "; 82 | else if (cstate == GET_M ) state_ascii <= "GET_M "; 83 | else if (cstate == STREAM ) state_ascii <= "STREAM "; 84 | else if (cstate == REKEY ) state_ascii <= "REKEY "; 85 | else state_ascii <= "WTF "; 86 | end 87 | // synthesis translate_on 88 | `endif // `ifdef SIMULATION 89 | 90 | reg [5:0] statecnt; 91 | reg rekey; 92 | reg load_block; 93 | reg load_56; // load 56 or 80 bits... 94 | reg load_lfsr; 95 | reg advance_lfsr; 96 | reg advance_block; 97 | reg [83:0] Ks; 98 | reg [83:0] Ki; 99 | reg [63:0] Mi; 100 | reg load_ks; 101 | reg auth_mode; 102 | reg [83:0] Kmod; 103 | 104 | always @ (posedge clk or posedge reset) begin 105 | if (reset) 106 | cstate <= INIT; 107 | else 108 | cstate <=#1 nstate; 109 | end 110 | 111 | hdcp_lfsr lfsr( .clk(clk), .reset(reset), 112 | .iv(auth_mode ? Ks[55:0] : Ki[55:0]), 113 | .init_iv(load_lfsr), 114 | .advance(advance_lfsr), 115 | .onebit(lfsr_out)); 116 | 117 | hdcp_block block( .clk(clk), .reset(reset), 118 | 119 | .load(load_block), 120 | .B(auth_mode ? {20'b0,An} : {20'b0,Mi}), 121 | .K(Kmod), 122 | .Bo(Bo_wire), 123 | .rekey(rekey), 124 | .lfsr_in(lfsr_out), 125 | .ostream(ostream), 126 | .advance(advance_block)); 127 | assign pr_data = ostream; 128 | 129 | always @ (*) begin 130 | case ({auth_mode,load_56}) //synthesis parallel_case full_case 131 | 2'b00: begin // not auth mode, load 84 bits 132 | Kmod = Ki; 133 | end 134 | 2'b01: begin // not auth mode, but load 56 bits only 135 | Kmod = {28'b0,Ks[55:0]}; 136 | end 137 | 2'b10: begin // auth mode, load 84 bits 138 | Kmod = Ks; 139 | end 140 | 2'b11: begin // auth mode, load only 56 bits 141 | Kmod = {28'b0,Km[55:0]}; 142 | end 143 | endcase // case ({auth_mode,load_56}) 144 | end // always @ (*) 145 | 146 | 147 | always @ (*) begin 148 | case (cstate) //synthesis parallel_case full_case 149 | INIT: begin 150 | nstate = hdcpBlockCipher_init ? BLOCK_1 : INIT; 151 | end 152 | BLOCK_1: begin 153 | nstate = BLOCK_2; 154 | end 155 | BLOCK_2: begin 156 | nstate = (statecnt >= 6'd47) ? BLOCK_3: BLOCK_2; 157 | end 158 | BLOCK_3: begin 159 | nstate = BLOCK_4; 160 | end 161 | BLOCK_4: begin 162 | nstate = BLOCK_5; 163 | end 164 | BLOCK_5: begin 165 | nstate = BLOCK_6; 166 | end 167 | BLOCK_6: begin 168 | nstate = BLOCK_7; 169 | end 170 | BLOCK_7: begin 171 | nstate = BLOCK_8; 172 | end 173 | BLOCK_8: begin 174 | nstate = (statecnt >= 6'd55) ? BLOCK_9: BLOCK_8; 175 | end 176 | BLOCK_9: begin 177 | nstate = GET_M; 178 | end 179 | GET_M: begin 180 | nstate = STREAM; 181 | end 182 | STREAM: begin 183 | if( hdcpBlockCipher_init ) begin 184 | nstate = BLOCK_1; 185 | end else if( hdcpRekeyCipher ) begin 186 | nstate = REKEY; 187 | end else begin 188 | nstate = STREAM; 189 | end 190 | end 191 | REKEY: begin 192 | if( hdcpBlockCipher_init ) begin 193 | nstate = BLOCK_1; 194 | end else begin 195 | nstate = (statecnt >= 6'd55) ? STREAM : REKEY; 196 | end 197 | end 198 | endcase // case (cstate) 199 | end 200 | 201 | always @ (posedge clk or posedge reset) begin 202 | if( reset ) begin 203 | statecnt <=#1 6'b0; 204 | rekey <=#1 1'b0; 205 | load_block <=#1 1'b0; 206 | advance_lfsr <=#1 1'b0; 207 | advance_block <=#1 1'b0; 208 | load_ks <=#1 1'b0; 209 | auth_mode <=#1 1'b0; 210 | stream_ready <=#1 1'b0; 211 | load_56 <=#1 1'b0; 212 | end else begin 213 | case (cstate) // synthesis parallel_case full_case 214 | INIT: begin 215 | statecnt <=#1 6'b0; 216 | rekey <=#1 1'b0; 217 | load_block <=#1 1'b0; 218 | advance_lfsr <=#1 1'b0; 219 | advance_block <=#1 1'b0; 220 | load_ks <=#1 1'b0; 221 | auth_mode <=#1 authentication; 222 | load_lfsr <=#1 1'b0; 223 | stream_ready <=#1 1'b0; 224 | load_56 <=#1 1'b0; 225 | end 226 | BLOCK_1: begin 227 | statecnt <=#1 6'b0; 228 | rekey <=#1 1'b0; 229 | load_block <=#1 1'b1; // load B & K regs of block module 230 | advance_lfsr <=#1 1'b0; 231 | advance_block <=#1 1'b0; 232 | load_ks <=#1 1'b0; 233 | auth_mode <=#1 auth_mode; 234 | load_lfsr <=#1 1'b0; 235 | stream_ready <=#1 1'b0; 236 | load_56 <=#1 1'b1; 237 | end 238 | BLOCK_2: begin 239 | statecnt <=#1 statecnt + 1; // 48 clocks 240 | rekey <=#1 1'b0; 241 | load_block <=#1 1'b0; 242 | advance_lfsr <=#1 1'b0; 243 | advance_block <=#1 1'b1; 244 | load_ks <=#1 1'b0; 245 | auth_mode <=#1 auth_mode; 246 | load_lfsr <=#1 1'b0; 247 | stream_ready <=#1 1'b0; 248 | load_56 <=#1 1'b0; 249 | end 250 | BLOCK_3: begin 251 | statecnt <=#1 0; 252 | rekey <=#1 1'b0; 253 | load_block <=#1 1'b0; 254 | advance_lfsr <=#1 1'b0; 255 | advance_block <=#1 1'b0; 256 | load_ks <=#1 1'b1; // save Ks, Ki, and B=>K 257 | auth_mode <=#1 auth_mode; 258 | load_lfsr <=#1 1'b0; 259 | stream_ready <=#1 1'b0; 260 | load_56 <=#1 1'b0; 261 | end 262 | BLOCK_4: begin 263 | statecnt <=#1 0; 264 | rekey <=#1 1'b0; 265 | load_block <=#1 1'b0; 266 | advance_lfsr <=#1 1'b0; 267 | advance_block <=#1 1'b0; 268 | load_ks <=#1 1'b1; // dup of above 269 | auth_mode <=#1 auth_mode; 270 | load_lfsr <=#1 1'b0; 271 | stream_ready <=#1 1'b0; 272 | load_56 <=#1 1'b0; 273 | end 274 | BLOCK_5: begin 275 | statecnt <=#1 0; 276 | rekey <=#1 1'b0; 277 | load_block <=#1 1'b1; // reload block cipher 278 | advance_lfsr <=#1 1'b0; 279 | advance_block <=#1 1'b0; 280 | load_ks <=#1 1'b0; 281 | auth_mode <=#1 auth_mode; 282 | load_lfsr <=#1 1'b0; 283 | stream_ready <=#1 1'b0; 284 | load_56 <=#1 1'b0; 285 | end 286 | BLOCK_6: begin 287 | statecnt <=#1 0; 288 | rekey <=#1 1'b0; 289 | load_block <=#1 1'b0; 290 | advance_lfsr <=#1 1'b0; 291 | advance_block <=#1 1'b0; 292 | load_ks <=#1 1'b0; 293 | auth_mode <=#1 auth_mode; 294 | load_lfsr <=#1 1'b1; // init lfsr 295 | stream_ready <=#1 1'b0; 296 | load_56 <=#1 1'b0; 297 | end 298 | BLOCK_7: begin 299 | statecnt <=#1 0; 300 | rekey <=#1 1'b1; // assert rekey 301 | load_block <=#1 1'b0; 302 | advance_lfsr <=#1 1'b0; 303 | advance_block <=#1 1'b0; 304 | load_ks <=#1 1'b0; 305 | auth_mode <=#1 auth_mode; 306 | load_lfsr <=#1 1'b0; 307 | stream_ready <=#1 1'b0; 308 | load_56 <=#1 1'b0; 309 | end 310 | BLOCK_8: begin 311 | statecnt <=#1 statecnt + 1; // 56 clocks 312 | rekey <=#1 1'b1; 313 | load_block <=#1 1'b0; 314 | advance_lfsr <=#1 1'b1; 315 | advance_block <=#1 1'b1; 316 | load_ks <=#1 1'b0; 317 | auth_mode <=#1 auth_mode; 318 | load_lfsr <=#1 1'b0; 319 | stream_ready <=#1 1'b0; 320 | load_56 <=#1 1'b0; 321 | end 322 | BLOCK_9: begin 323 | statecnt <=#1 0; 324 | rekey <=#1 1'b0; // de-assert rekey 325 | load_block <=#1 1'b0; 326 | advance_lfsr <=#1 1'b0; 327 | advance_block <=#1 1'b0; 328 | load_ks <=#1 1'b0; 329 | auth_mode <=#1 auth_mode; 330 | load_lfsr <=#1 1'b0; 331 | stream_ready <=#1 1'b0; 332 | load_56 <=#1 1'b0; 333 | end // case: BLOCK_9 334 | GET_M: begin // one cycle wait to get M register loaded properly 335 | statecnt <=#1 0; 336 | rekey <=#1 1'b0; 337 | load_block <=#1 1'b0; 338 | advance_lfsr <=#1 1'b0; 339 | advance_block <=#1 1'b0; 340 | load_ks <=#1 1'b0; 341 | auth_mode <=#1 1'b0; 342 | load_lfsr <=#1 1'b0; 343 | stream_ready <=#1 1'b0; 344 | load_56 <=#1 1'b0; 345 | end 346 | STREAM: begin 347 | statecnt <=#1 0; 348 | rekey <=#1 1'b0; 349 | load_block <=#1 1'b0; 350 | advance_lfsr <=#1 hdcpStreamCipher; 351 | advance_block <=#1 hdcpStreamCipher; 352 | load_ks <=#1 1'b0; 353 | auth_mode <=#1 authentication; 354 | load_lfsr <=#1 1'b0; 355 | stream_ready <=#1 1'b1; 356 | load_56 <=#1 1'b0; 357 | end 358 | REKEY: begin 359 | statecnt <=#1 statecnt + 1; 360 | rekey <=#1 1'b1; 361 | load_block <=#1 1'b0; 362 | advance_lfsr <=#1 1'b1; 363 | advance_block <=#1 1'b1; 364 | load_ks <=#1 1'b0; 365 | auth_mode <=#1 auth_mode; 366 | load_lfsr <=#1 1'b0; 367 | stream_ready <=#1 1'b0; 368 | load_56 <=#1 1'b0; 369 | end 370 | endcase // case (cstate) 371 | end 372 | end // always @ (posedge clk or posedge reset) 373 | 374 | always @(posedge clk or posedge reset) begin 375 | if( reset ) begin 376 | Ks <= 80'b0; 377 | Ki <= 80'b0; 378 | end else begin 379 | // if( hdcpBlockCipher_init ) begin 380 | // Ks <= (authentication | auth_mode) ? {28'b0,Km} : Ks; 381 | // Ki <= 80'b0; 382 | // end else if( load_ks && auth_mode ) begin 383 | if( load_ks && auth_mode ) begin 384 | Ks <= Bo_wire; 385 | Ki <= 80'b0; 386 | end else if( load_ks && !auth_mode ) begin 387 | Ks <= Ks; 388 | Ki <= Bo_wire; 389 | end else begin 390 | Ks <= Ks; 391 | Ki <= Ki; 392 | end 393 | end 394 | end // always @ (posedge clk or posedge reset) 395 | 396 | always @(posedge clk or posedge reset) begin 397 | if( reset ) begin 398 | Mi <= 80'b0; 399 | end else begin 400 | if( (cstate == BLOCK_8) || (cstate == BLOCK_9) || (cstate == GET_M) ) begin 401 | Mi[15:0] <= ostream[15:0]; 402 | Mi[31:16] <= Mi[15:0]; 403 | Mi[47:32] <= Mi[31:16]; 404 | Mi[63:48] <= Mi[47:32]; 405 | end else begin 406 | Mi <= Mi; 407 | end 408 | end // else: !if( reset ) 409 | end // always @ (posedge clk or posedge reset) 410 | 411 | endmodule // hdcp_cipher 412 | -------------------------------------------------------------------------------- /sources_1/imports/release1/rx/serdes_1_to_5_diff_data.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Xilinx, Inc. 2010 www.xilinx.com 4 | // 5 | // XAPP xxx - 1:5 Differential Data De-serializer 6 | // 7 | ////////////////////////////////////////////////////////////////////////////// 8 | // 9 | // File name : serdes_1_to_5_diff_data.v 10 | // 11 | // Description : This module instantiates IODELAY2 and ISERDES2 primitives 12 | // to receive TMDS differential data in 1:5 format 13 | // 14 | // Note: 15 | // 16 | // Author : Bob Feng 17 | ////////////////////////////////////////////////////////////////////////////// 18 | // 19 | // Disclaimer: 20 | // 21 | // This disclaimer is not a license and does not grant any rights to the materials 22 | // distributed herewith. Except as otherwise provided in a valid license issued to you 23 | // by Xilinx, and to the maximum extent permitted by applicable law: 24 | // (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 25 | // AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 26 | // INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 27 | // FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 28 | // or tort, including negligence, or under any other theory of liability) for any loss or damage 29 | // of any kind or nature related to, arising under or in connection with these materials, 30 | // including for any direct, or any indirect, special, incidental, or consequential loss 31 | // or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 32 | // as a result of any action brought by a third party) even if such damage or loss was 33 | // reasonably foreseeable or Xilinx had been advised of the possibility of the same. 34 | // 35 | // Critical Applications: 36 | // 37 | // Xilinx products are not designed or intended to be fail-safe, or for use in any application 38 | // requiring fail-safe performance, such as life-support or safety devices or systems, 39 | // Class III medical devices, nuclear facilities, applications related to the deployment of airbags, 40 | // or any other applications that could lead to death, personal injury, or severe property or 41 | // environmental damage (individually and collectively, "Critical Applications"). Customer assumes 42 | // the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 43 | // to applicable laws and regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 46 | // 47 | ////////////////////////////////////////////////////////////////////////////// 48 | 49 | `timescale 1ps/1ps 50 | 51 | module serdes_1_to_5_diff_data # ( 52 | parameter DIFF_TERM = "TRUE", 53 | parameter SIM_TAP_DELAY = 49, 54 | parameter BITSLIP_ENABLE = "FALSE" 55 | )( 56 | input wire use_phase_detector, // '1' enables the phase detector logic 57 | input wire datain_p, // Input from LVDS receiver pin 58 | input wire datain_n, // Input from LVDS receiver pin 59 | input wire rxioclk, // IO Clock network 60 | input wire rxserdesstrobe, // Parallel data capture strobe 61 | input wire reset, // Reset line 62 | input wire gclk, // Global clock 63 | input wire bitslip, // Bitslip control line 64 | output wire [4:0] data_out // Output data 65 | ); 66 | 67 | wire ddly_m; 68 | wire ddly_s; 69 | wire busys; 70 | wire rx_data_in; 71 | wire cascade; 72 | wire pd_edge; 73 | reg [8:0] counter; 74 | reg [3:0] state; 75 | reg cal_data_sint; 76 | wire busy_data; 77 | reg busy_data_d; 78 | wire cal_data_slave; 79 | reg enable; 80 | reg cal_data_master; 81 | reg rst_data; 82 | reg inc_data_int; 83 | wire inc_data; 84 | reg ce_data; 85 | reg valid_data_d; 86 | reg incdec_data_d; 87 | reg [4:0] pdcounter; 88 | wire valid_data; 89 | wire incdec_data; 90 | reg flag; 91 | reg mux; 92 | reg ce_data_inta ; 93 | wire [1:0] incdec_data_or; 94 | wire incdec_data_im; 95 | wire [1:0] valid_data_or; 96 | wire valid_data_im; 97 | wire [1:0] busy_data_or; 98 | wire all_ce; 99 | 100 | wire [1:0] debug_in = 2'b00; 101 | 102 | assign busy_data = busys ; 103 | 104 | assign cal_data_slave = cal_data_sint ; 105 | 106 | ///////////////////////////////////////////////// 107 | // 108 | // IDELAY Calibration FSM 109 | // 110 | ///////////////////////////////////////////////// 111 | always @ (posedge gclk or posedge reset) 112 | begin 113 | if (reset == 1'b1) begin 114 | state <= 0 ; 115 | cal_data_master <= 1'b0 ; 116 | cal_data_sint <= 1'b0 ; 117 | counter <= 9'h000 ; 118 | enable <= 1'b0 ; 119 | mux <= 1'h1 ; 120 | end 121 | else begin 122 | counter <= counter + 9'h001 ; 123 | if (counter[8] == 1'b1) begin 124 | counter <= 9'h000 ; 125 | end 126 | if (counter[5] == 1'b1) begin 127 | enable <= 1'b1 ; 128 | end 129 | if (state == 0 && enable == 1'b1) begin // Wait for IODELAY to be available 130 | cal_data_master <= 1'b0 ; 131 | cal_data_sint <= 1'b0 ; 132 | rst_data <= 1'b0 ; 133 | if (busy_data_d == 1'b0) begin 134 | state <= 1 ; 135 | end 136 | end 137 | else if (state == 1) begin // Issue calibrate command to both master and slave, needed for simulation, not for the silicon 138 | cal_data_master <= 1'b1 ; 139 | cal_data_sint <= 1'b1 ; 140 | if (busy_data_d == 1'b1) begin // and wait for command to be accepted 141 | state <= 2 ; 142 | end 143 | end 144 | else if (state == 2) begin // Now RST master and slave IODELAYs needed for simulation, not for the silicon 145 | cal_data_master <= 1'b0 ; 146 | cal_data_sint <= 1'b0 ; 147 | if (busy_data_d == 1'b0) begin 148 | rst_data <= 1'b1 ; 149 | state <= 3 ; 150 | end 151 | end 152 | else if (state == 3) begin // Wait for IODELAY to be available 153 | rst_data <= 1'b0 ; 154 | if (busy_data_d == 1'b0) begin 155 | state <= 4 ; 156 | end 157 | end 158 | else if (state == 4) begin // Wait for occasional enable 159 | if (counter[8] == 1'b1) begin 160 | state <= 5 ; 161 | end 162 | end 163 | else if (state == 5) begin // Calibrate slave only 164 | if (busy_data_d == 1'b0) begin 165 | cal_data_sint <= 1'b1 ; 166 | state <= 6 ; 167 | end 168 | end 169 | else if (state == 6) begin // Wait for command to be accepted 170 | cal_data_sint <= 1'b0 ; 171 | if (busy_data_d == 1'b1) begin 172 | state <= 7 ; 173 | end 174 | end 175 | else if (state == 7) begin // Wait for all IODELAYs to be available, ie CAL command finished 176 | cal_data_sint <= 1'b0 ; 177 | if (busy_data_d == 1'b0) begin 178 | state <= 4 ; 179 | end 180 | end 181 | end 182 | end 183 | 184 | always @ (posedge gclk or posedge reset) // Per-bit phase detection state machine 185 | begin 186 | if (reset == 1'b1) begin 187 | pdcounter <= 5'b1000 ; 188 | ce_data_inta <= 1'b0 ; 189 | flag <= 1'b0 ; // flag is there to only allow one inc or dec per cal (test) 190 | end 191 | else begin 192 | busy_data_d <= busy_data_or[1] ; 193 | if (use_phase_detector == 1'b1) begin // decide whther pd is used 194 | incdec_data_d <= incdec_data_or[1] ; 195 | valid_data_d <= valid_data_or[1] ; 196 | if (ce_data_inta == 1'b1) begin 197 | ce_data = mux ; 198 | end 199 | else begin 200 | ce_data = 64'h0000000000000000 ; 201 | end 202 | if (state == 7) begin 203 | flag <= 1'b0 ; 204 | end 205 | else if (state != 4 || busy_data_d == 1'b1) begin // Reset filter if state machine issues a cal command or unit is busy 206 | pdcounter <= 5'b10000 ; 207 | ce_data_inta <= 1'b0 ; 208 | end 209 | else if (pdcounter == 5'b11111 && flag == 1'b0) begin // Filter has reached positive max - increment the tap count 210 | ce_data_inta <= 1'b1 ; 211 | inc_data_int <= 1'b1 ; 212 | pdcounter <= 5'b10000 ; 213 | flag <= 1'b1 ; 214 | end 215 | else if (pdcounter == 5'b00000 && flag == 1'b0) begin // Filter has reached negative max - decrement the tap count 216 | ce_data_inta <= 1'b1 ; 217 | inc_data_int <= 1'b0 ; 218 | pdcounter <= 5'b10000 ; 219 | flag <= 1'b1 ; 220 | end 221 | else if (valid_data_d == 1'b1) begin // increment filter 222 | ce_data_inta <= 1'b0 ; 223 | if (incdec_data_d == 1'b1 && pdcounter != 5'b11111) begin 224 | pdcounter <= pdcounter + 5'b00001 ; 225 | end 226 | else if (incdec_data_d == 1'b0 && pdcounter != 5'b00000) begin // decrement filter 227 | pdcounter <= pdcounter + 5'b11111 ; 228 | end 229 | end 230 | else begin 231 | ce_data_inta <= 1'b0 ; 232 | end 233 | end 234 | else begin 235 | ce_data = all_ce ; 236 | inc_data_int <= debug_in[1] ; 237 | end 238 | end 239 | end 240 | 241 | assign inc_data = inc_data_int ; 242 | 243 | assign incdec_data_or[0] = 1'b0 ; // Input Mux - Initialise generate loop OR gates 244 | assign valid_data_or[0] = 1'b0 ; 245 | assign busy_data_or[0] = 1'b0 ; 246 | 247 | assign incdec_data_im = incdec_data & mux; // Input muxes 248 | assign incdec_data_or[1] = incdec_data_im | incdec_data_or; // AND gates to allow just one signal through at a tome 249 | assign valid_data_im = valid_data & mux; // followed by an OR 250 | assign valid_data_or[1] = valid_data_im | valid_data_or; // for the three inputs from each PD 251 | assign busy_data_or[1] = busy_data | busy_data_or; // The busy signals just need an OR gate 252 | 253 | assign all_ce = debug_in[0] ; 254 | 255 | IBUFDS #( 256 | .DIFF_TERM (DIFF_TERM)) 257 | data_in ( 258 | .I (datain_p), 259 | .IB (datain_n), 260 | .O (rx_data_in) 261 | ); 262 | 263 | // 264 | // Master IDELAY 265 | // 266 | IODELAY2 #( 267 | .DATA_RATE ("SDR"), 268 | .IDELAY_VALUE (0), 269 | .IDELAY2_VALUE (0), 270 | .IDELAY_MODE ("NORMAL" ), 271 | .ODELAY_VALUE (0), 272 | .IDELAY_TYPE ("DIFF_PHASE_DETECTOR"), 273 | .COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), //("WRAPAROUND"), // this setting is for implementation 274 | // .COUNTER_WRAPAROUND ("WRAPAROUND"), // this setting is for simulation 275 | .DELAY_SRC ("IDATAIN"), 276 | .SERDES_MODE ("MASTER"), 277 | .SIM_TAPDELAY_VALUE (SIM_TAP_DELAY) 278 | ) iodelay_m ( 279 | .IDATAIN (rx_data_in), // data from IBUFDS 280 | .TOUT (), // tri-state signal to IOB 281 | .DOUT (), // output data to IOB 282 | .T (1'b1), // tri-state control from OLOGIC/OSERDES2 283 | .ODATAIN (1'b0), // data from OLOGIC/OSERDES2 284 | .DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2 285 | .DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2 286 | .IOCLK0 (rxioclk), // High speed clock for calibration 287 | .IOCLK1 (1'b0), // High speed clock for calibration 288 | .CLK (gclk), // Fabric clock (GCLK) for control signals 289 | .CAL (cal_data_master), // Calibrate control signal 290 | .INC (inc_data), // Increment counter 291 | .CE (ce_data), // Clock Enable 292 | .RST (rst_data), // Reset delay line 293 | .BUSY () // output signal indicating sync circuit has finished / calibration has finished 294 | ); 295 | 296 | // 297 | // Slave IDELAY 298 | // 299 | IODELAY2 #( 300 | .DATA_RATE ("SDR"), 301 | .IDELAY_VALUE (0), 302 | .IDELAY2_VALUE (0), 303 | .IDELAY_MODE ("NORMAL" ), 304 | .ODELAY_VALUE (0), 305 | .IDELAY_TYPE ("DIFF_PHASE_DETECTOR"), 306 | .COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // this lacked the note about impl/sim 307 | // .COUNTER_WRAPAROUND ("WRAPAROUND"), 308 | .DELAY_SRC ("IDATAIN"), 309 | .SERDES_MODE ("SLAVE"), 310 | .SIM_TAPDELAY_VALUE (SIM_TAP_DELAY) 311 | ) iodelay_s ( 312 | .IDATAIN (rx_data_in), // data from IBUFDS 313 | .TOUT (), // tri-state signal to IOB 314 | .DOUT (), // output data to IOB 315 | .T (1'b1), // tri-state control from OLOGIC/OSERDES2 316 | .ODATAIN (1'b0), // data from OLOGIC/OSERDES2 317 | .DATAOUT (ddly_s), // Slave output data to ILOGIC/ISERDES2 318 | .DATAOUT2 (), // 319 | .IOCLK0 (rxioclk), // High speed IO clock for calibration 320 | .IOCLK1 (1'b0), 321 | .CLK (gclk), // Fabric clock (GCLK) for control signals 322 | .CAL (cal_data_slave), // Calibrate control signal 323 | .INC (inc_data), // Increment counter 324 | .CE (ce_data), // Clock Enable 325 | .RST (rst_data), // Reset delay line 326 | .BUSY (busys) // output signal indicating sync circuit has finished / calibration has finished 327 | ); 328 | 329 | // 330 | // Master ISERDES 331 | // 332 | 333 | ISERDES2 #( 334 | .DATA_WIDTH (5), 335 | .DATA_RATE ("SDR"), 336 | .BITSLIP_ENABLE (BITSLIP_ENABLE), 337 | .SERDES_MODE ("MASTER"), 338 | .INTERFACE_TYPE ("RETIMED")) 339 | iserdes_m ( 340 | .D (ddly_m), 341 | .CE0 (1'b1), 342 | .CLK0 (rxioclk), 343 | .CLK1 (1'b0), 344 | .IOCE (rxserdesstrobe), 345 | .RST (reset), 346 | .CLKDIV (gclk), 347 | .SHIFTIN (pd_edge), 348 | .BITSLIP (bitslip), 349 | .FABRICOUT (), 350 | .Q4 (data_out[4]), 351 | .Q3 (data_out[3]), 352 | .Q2 (data_out[2]), 353 | .Q1 (data_out[1]), 354 | .DFB (), 355 | .CFB0 (), 356 | .CFB1 (), 357 | .VALID (valid_data), 358 | .INCDEC (incdec_data), 359 | .SHIFTOUT (cascade)); 360 | 361 | // 362 | // Slave ISERDES 363 | // 364 | 365 | ISERDES2 #( 366 | .DATA_WIDTH (5), 367 | .DATA_RATE ("SDR"), 368 | .BITSLIP_ENABLE (BITSLIP_ENABLE), 369 | .SERDES_MODE ("SLAVE"), 370 | .INTERFACE_TYPE ("RETIMED") 371 | ) iserdes_s ( 372 | .D (ddly_s), 373 | .CE0 (1'b1), 374 | .CLK0 (rxioclk), 375 | .CLK1 (1'b0), 376 | .IOCE (rxserdesstrobe), 377 | .RST (reset), 378 | .CLKDIV (gclk), 379 | .SHIFTIN (cascade), 380 | .BITSLIP (bitslip), 381 | .FABRICOUT (), 382 | .Q4 (data_out[0]), 383 | .Q3 (), 384 | .Q2 (), 385 | .Q1 (), 386 | .DFB (), 387 | .CFB0 (), 388 | .CFB1 (), 389 | .VALID (), 390 | .INCDEC (), 391 | .SHIFTOUT (pd_edge)); 392 | 393 | 394 | reg [7:0] rxpdcntr = 8'h7f; 395 | always @ (posedge gclk or posedge reset) begin 396 | if (reset) 397 | rxpdcntr <= 8'h7f; 398 | else if (ce_data) 399 | if (inc_data) 400 | rxpdcntr <= rxpdcntr + 1'b1; 401 | else 402 | rxpdcntr <= rxpdcntr - 1'b1; 403 | end 404 | 405 | endmodule 406 | -------------------------------------------------------------------------------- /sources_1/ip/fifo_generator_v7_2_0/fifo_2kx18.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * 3 | * * 4 | * This file contains confidential and proprietary information * 5 | * of Xilinx, Inc. and is protected under U.S. and * 6 | * international copyright and other intellectual property * 7 | * laws. * 8 | * * 9 | * DISCLAIMER * 10 | * This disclaimer is not a license and does not grant any * 11 | * rights to the materials distributed herewith. Except as * 12 | * otherwise provided in a valid license issued to you by * 13 | * Xilinx, and to the maximum extent permitted by applicable * 14 | * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * 15 | * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * 16 | * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * 17 | * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * 18 | * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * 19 | * (2) Xilinx shall not be liable (whether in contract or tort, * 20 | * including negligence, or under any other theory of * 21 | * liability) for any loss or damage of any kind or nature * 22 | * related to, arising under or in connection with these * 23 | * materials, including for any direct, or any indirect, * 24 | * special, incidental, or consequential loss or damage * 25 | * (including loss of data, profits, goodwill, or any type of * 26 | * loss or damage suffered as a result of any action brought * 27 | * by a third party) even if such damage or loss was * 28 | * reasonably foreseeable or Xilinx had been advised of the * 29 | * possibility of the same. * 30 | * * 31 | * CRITICAL APPLICATIONS * 32 | * Xilinx products are not designed or intended to be fail- * 33 | * safe, or for use in any application requiring fail-safe * 34 | * performance, such as life-support or safety devices or * 35 | * systems, Class III medical devices, nuclear facilities, * 36 | * applications related to the deployment of airbags, or any * 37 | * other applications that could lead to death, personal * 38 | * injury, or severe property or environmental damage * 39 | * (individually and collectively, "Critical * 40 | * Applications"). Customer assumes the sole risk and * 41 | * liability of any use of Xilinx products in Critical * 42 | * Applications, subject only to applicable laws and * 43 | * regulations governing limitations on product liability. * 44 | * * 45 | * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * 46 | * PART OF THIS FILE AT ALL TIMES. * 47 | *******************************************************************************/ 48 | // The synthesis directives "translate_off/translate_on" specified below are 49 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 50 | // tools. Ensure they are correct for your synthesis tool(s). 51 | 52 | // You must compile the wrapper file fifo_2kx18.v when simulating 53 | // the core, fifo_2kx18. When compiling the wrapper file, be sure to 54 | // reference the XilinxCoreLib Verilog simulation library. For detailed 55 | // instructions, please refer to the "CORE Generator Help". 56 | 57 | `timescale 1ns/1ps 58 | 59 | module fifo_2kx18( 60 | rst, 61 | wr_clk, 62 | rd_clk, 63 | din, 64 | wr_en, 65 | rd_en, 66 | dout, 67 | full, 68 | empty); 69 | 70 | 71 | input rst; 72 | input wr_clk; 73 | input rd_clk; 74 | input [17 : 0] din; 75 | input wr_en; 76 | input rd_en; 77 | output [17 : 0] dout; 78 | output full; 79 | output empty; 80 | 81 | // synthesis translate_off 82 | 83 | FIFO_GENERATOR_V7_2 #( 84 | .C_ADD_NGC_CONSTRAINT(0), 85 | .C_APPLICATION_TYPE_AXIS(0), 86 | .C_APPLICATION_TYPE_RACH(0), 87 | .C_APPLICATION_TYPE_RDCH(0), 88 | .C_APPLICATION_TYPE_WACH(0), 89 | .C_APPLICATION_TYPE_WDCH(0), 90 | .C_APPLICATION_TYPE_WRCH(0), 91 | .C_AXIS_TDATA_WIDTH(64), 92 | .C_AXIS_TDEST_WIDTH(4), 93 | .C_AXIS_TID_WIDTH(8), 94 | .C_AXIS_TKEEP_WIDTH(4), 95 | .C_AXIS_TSTRB_WIDTH(4), 96 | .C_AXIS_TUSER_WIDTH(4), 97 | .C_AXIS_TYPE(0), 98 | .C_AXI_ADDR_WIDTH(32), 99 | .C_AXI_ARUSER_WIDTH(1), 100 | .C_AXI_AWUSER_WIDTH(1), 101 | .C_AXI_BUSER_WIDTH(1), 102 | .C_AXI_DATA_WIDTH(64), 103 | .C_AXI_ID_WIDTH(4), 104 | .C_AXI_RUSER_WIDTH(1), 105 | .C_AXI_TYPE(0), 106 | .C_AXI_WUSER_WIDTH(1), 107 | .C_COMMON_CLOCK(0), 108 | .C_COUNT_TYPE(0), 109 | .C_DATA_COUNT_WIDTH(11), 110 | .C_DEFAULT_VALUE("BlankString"), 111 | .C_DIN_WIDTH(18), 112 | .C_DIN_WIDTH_AXIS(1), 113 | .C_DIN_WIDTH_RACH(32), 114 | .C_DIN_WIDTH_RDCH(64), 115 | .C_DIN_WIDTH_WACH(32), 116 | .C_DIN_WIDTH_WDCH(64), 117 | .C_DIN_WIDTH_WRCH(2), 118 | .C_DOUT_RST_VAL("0"), 119 | .C_DOUT_WIDTH(18), 120 | .C_ENABLE_RLOCS(0), 121 | .C_ENABLE_RST_SYNC(1), 122 | .C_ERROR_INJECTION_TYPE(0), 123 | .C_ERROR_INJECTION_TYPE_AXIS(0), 124 | .C_ERROR_INJECTION_TYPE_RACH(0), 125 | .C_ERROR_INJECTION_TYPE_RDCH(0), 126 | .C_ERROR_INJECTION_TYPE_WACH(0), 127 | .C_ERROR_INJECTION_TYPE_WDCH(0), 128 | .C_ERROR_INJECTION_TYPE_WRCH(0), 129 | .C_FAMILY("spartan6"), 130 | .C_FULL_FLAGS_RST_VAL(1), 131 | .C_HAS_ALMOST_EMPTY(0), 132 | .C_HAS_ALMOST_FULL(0), 133 | .C_HAS_AXIS_TDATA(0), 134 | .C_HAS_AXIS_TDEST(0), 135 | .C_HAS_AXIS_TID(0), 136 | .C_HAS_AXIS_TKEEP(0), 137 | .C_HAS_AXIS_TLAST(0), 138 | .C_HAS_AXIS_TREADY(1), 139 | .C_HAS_AXIS_TSTRB(0), 140 | .C_HAS_AXIS_TUSER(0), 141 | .C_HAS_AXI_ARUSER(0), 142 | .C_HAS_AXI_AWUSER(0), 143 | .C_HAS_AXI_BUSER(0), 144 | .C_HAS_AXI_RD_CHANNEL(0), 145 | .C_HAS_AXI_RUSER(0), 146 | .C_HAS_AXI_WR_CHANNEL(0), 147 | .C_HAS_AXI_WUSER(0), 148 | .C_HAS_BACKUP(0), 149 | .C_HAS_DATA_COUNT(0), 150 | .C_HAS_DATA_COUNTS_AXIS(0), 151 | .C_HAS_DATA_COUNTS_RACH(0), 152 | .C_HAS_DATA_COUNTS_RDCH(0), 153 | .C_HAS_DATA_COUNTS_WACH(0), 154 | .C_HAS_DATA_COUNTS_WDCH(0), 155 | .C_HAS_DATA_COUNTS_WRCH(0), 156 | .C_HAS_INT_CLK(0), 157 | .C_HAS_MASTER_CE(0), 158 | .C_HAS_MEMINIT_FILE(0), 159 | .C_HAS_OVERFLOW(0), 160 | .C_HAS_PROG_FLAGS_AXIS(0), 161 | .C_HAS_PROG_FLAGS_RACH(0), 162 | .C_HAS_PROG_FLAGS_RDCH(0), 163 | .C_HAS_PROG_FLAGS_WACH(0), 164 | .C_HAS_PROG_FLAGS_WDCH(0), 165 | .C_HAS_PROG_FLAGS_WRCH(0), 166 | .C_HAS_RD_DATA_COUNT(0), 167 | .C_HAS_RD_RST(0), 168 | .C_HAS_RST(1), 169 | .C_HAS_SLAVE_CE(0), 170 | .C_HAS_SRST(0), 171 | .C_HAS_UNDERFLOW(0), 172 | .C_HAS_VALID(0), 173 | .C_HAS_WR_ACK(0), 174 | .C_HAS_WR_DATA_COUNT(0), 175 | .C_HAS_WR_RST(0), 176 | .C_IMPLEMENTATION_TYPE(2), 177 | .C_IMPLEMENTATION_TYPE_AXIS(1), 178 | .C_IMPLEMENTATION_TYPE_RACH(1), 179 | .C_IMPLEMENTATION_TYPE_RDCH(1), 180 | .C_IMPLEMENTATION_TYPE_WACH(1), 181 | .C_IMPLEMENTATION_TYPE_WDCH(1), 182 | .C_IMPLEMENTATION_TYPE_WRCH(1), 183 | .C_INIT_WR_PNTR_VAL(0), 184 | .C_INTERFACE_TYPE(0), 185 | .C_MEMORY_TYPE(1), 186 | .C_MIF_FILE_NAME("BlankString"), 187 | .C_MSGON_VAL(1), 188 | .C_OPTIMIZATION_MODE(0), 189 | .C_OVERFLOW_LOW(0), 190 | .C_PRELOAD_LATENCY(1), 191 | .C_PRELOAD_REGS(0), 192 | .C_PRIM_FIFO_TYPE("2kx18"), 193 | .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), 194 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), 195 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), 196 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), 197 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), 198 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), 199 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), 200 | .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), 201 | .C_PROG_EMPTY_TYPE(0), 202 | .C_PROG_EMPTY_TYPE_AXIS(5), 203 | .C_PROG_EMPTY_TYPE_RACH(5), 204 | .C_PROG_EMPTY_TYPE_RDCH(5), 205 | .C_PROG_EMPTY_TYPE_WACH(5), 206 | .C_PROG_EMPTY_TYPE_WDCH(5), 207 | .C_PROG_EMPTY_TYPE_WRCH(5), 208 | .C_PROG_FULL_THRESH_ASSERT_VAL(2045), 209 | .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), 210 | .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), 211 | .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), 212 | .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), 213 | .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), 214 | .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), 215 | .C_PROG_FULL_THRESH_NEGATE_VAL(2044), 216 | .C_PROG_FULL_TYPE(0), 217 | .C_PROG_FULL_TYPE_AXIS(5), 218 | .C_PROG_FULL_TYPE_RACH(5), 219 | .C_PROG_FULL_TYPE_RDCH(5), 220 | .C_PROG_FULL_TYPE_WACH(5), 221 | .C_PROG_FULL_TYPE_WDCH(5), 222 | .C_PROG_FULL_TYPE_WRCH(5), 223 | .C_RACH_TYPE(0), 224 | .C_RDCH_TYPE(0), 225 | .C_RD_DATA_COUNT_WIDTH(11), 226 | .C_RD_DEPTH(2048), 227 | .C_RD_FREQ(1), 228 | .C_RD_PNTR_WIDTH(11), 229 | .C_REG_SLICE_MODE_AXIS(0), 230 | .C_REG_SLICE_MODE_RACH(0), 231 | .C_REG_SLICE_MODE_RDCH(0), 232 | .C_REG_SLICE_MODE_WACH(0), 233 | .C_REG_SLICE_MODE_WDCH(0), 234 | .C_REG_SLICE_MODE_WRCH(0), 235 | .C_UNDERFLOW_LOW(0), 236 | .C_USE_COMMON_OVERFLOW(0), 237 | .C_USE_COMMON_UNDERFLOW(0), 238 | .C_USE_DEFAULT_SETTINGS(0), 239 | .C_USE_DOUT_RST(0), 240 | .C_USE_ECC(0), 241 | .C_USE_ECC_AXIS(0), 242 | .C_USE_ECC_RACH(0), 243 | .C_USE_ECC_RDCH(0), 244 | .C_USE_ECC_WACH(0), 245 | .C_USE_ECC_WDCH(0), 246 | .C_USE_ECC_WRCH(0), 247 | .C_USE_EMBEDDED_REG(0), 248 | .C_USE_FIFO16_FLAGS(0), 249 | .C_USE_FWFT_DATA_COUNT(0), 250 | .C_VALID_LOW(0), 251 | .C_WACH_TYPE(0), 252 | .C_WDCH_TYPE(0), 253 | .C_WRCH_TYPE(0), 254 | .C_WR_ACK_LOW(0), 255 | .C_WR_DATA_COUNT_WIDTH(11), 256 | .C_WR_DEPTH(2048), 257 | .C_WR_DEPTH_AXIS(1024), 258 | .C_WR_DEPTH_RACH(16), 259 | .C_WR_DEPTH_RDCH(1024), 260 | .C_WR_DEPTH_WACH(16), 261 | .C_WR_DEPTH_WDCH(1024), 262 | .C_WR_DEPTH_WRCH(16), 263 | .C_WR_FREQ(1), 264 | .C_WR_PNTR_WIDTH(11), 265 | .C_WR_PNTR_WIDTH_AXIS(10), 266 | .C_WR_PNTR_WIDTH_RACH(4), 267 | .C_WR_PNTR_WIDTH_RDCH(10), 268 | .C_WR_PNTR_WIDTH_WACH(4), 269 | .C_WR_PNTR_WIDTH_WDCH(10), 270 | .C_WR_PNTR_WIDTH_WRCH(4), 271 | .C_WR_RESPONSE_LATENCY(1)) 272 | inst ( 273 | .RST(rst), 274 | .WR_CLK(wr_clk), 275 | .RD_CLK(rd_clk), 276 | .DIN(din), 277 | .WR_EN(wr_en), 278 | .RD_EN(rd_en), 279 | .DOUT(dout), 280 | .FULL(full), 281 | .EMPTY(empty), 282 | .BACKUP(), 283 | .BACKUP_MARKER(), 284 | .CLK(), 285 | .SRST(), 286 | .WR_RST(), 287 | .RD_RST(), 288 | .PROG_EMPTY_THRESH(), 289 | .PROG_EMPTY_THRESH_ASSERT(), 290 | .PROG_EMPTY_THRESH_NEGATE(), 291 | .PROG_FULL_THRESH(), 292 | .PROG_FULL_THRESH_ASSERT(), 293 | .PROG_FULL_THRESH_NEGATE(), 294 | .INT_CLK(), 295 | .INJECTDBITERR(), 296 | .INJECTSBITERR(), 297 | .ALMOST_FULL(), 298 | .WR_ACK(), 299 | .OVERFLOW(), 300 | .ALMOST_EMPTY(), 301 | .VALID(), 302 | .UNDERFLOW(), 303 | .DATA_COUNT(), 304 | .RD_DATA_COUNT(), 305 | .WR_DATA_COUNT(), 306 | .PROG_FULL(), 307 | .PROG_EMPTY(), 308 | .SBITERR(), 309 | .DBITERR(), 310 | .M_ACLK(), 311 | .S_ACLK(), 312 | .S_ARESETN(), 313 | .M_ACLK_EN(), 314 | .S_ACLK_EN(), 315 | .S_AXI_AWID(), 316 | .S_AXI_AWADDR(), 317 | .S_AXI_AWLEN(), 318 | .S_AXI_AWSIZE(), 319 | .S_AXI_AWBURST(), 320 | .S_AXI_AWLOCK(), 321 | .S_AXI_AWCACHE(), 322 | .S_AXI_AWPROT(), 323 | .S_AXI_AWQOS(), 324 | .S_AXI_AWREGION(), 325 | .S_AXI_AWUSER(), 326 | .S_AXI_AWVALID(), 327 | .S_AXI_AWREADY(), 328 | .S_AXI_WID(), 329 | .S_AXI_WDATA(), 330 | .S_AXI_WSTRB(), 331 | .S_AXI_WLAST(), 332 | .S_AXI_WUSER(), 333 | .S_AXI_WVALID(), 334 | .S_AXI_WREADY(), 335 | .S_AXI_BID(), 336 | .S_AXI_BRESP(), 337 | .S_AXI_BUSER(), 338 | .S_AXI_BVALID(), 339 | .S_AXI_BREADY(), 340 | .M_AXI_AWID(), 341 | .M_AXI_AWADDR(), 342 | .M_AXI_AWLEN(), 343 | .M_AXI_AWSIZE(), 344 | .M_AXI_AWBURST(), 345 | .M_AXI_AWLOCK(), 346 | .M_AXI_AWCACHE(), 347 | .M_AXI_AWPROT(), 348 | .M_AXI_AWQOS(), 349 | .M_AXI_AWREGION(), 350 | .M_AXI_AWUSER(), 351 | .M_AXI_AWVALID(), 352 | .M_AXI_AWREADY(), 353 | .M_AXI_WID(), 354 | .M_AXI_WDATA(), 355 | .M_AXI_WSTRB(), 356 | .M_AXI_WLAST(), 357 | .M_AXI_WUSER(), 358 | .M_AXI_WVALID(), 359 | .M_AXI_WREADY(), 360 | .M_AXI_BID(), 361 | .M_AXI_BRESP(), 362 | .M_AXI_BUSER(), 363 | .M_AXI_BVALID(), 364 | .M_AXI_BREADY(), 365 | .S_AXI_ARID(), 366 | .S_AXI_ARADDR(), 367 | .S_AXI_ARLEN(), 368 | .S_AXI_ARSIZE(), 369 | .S_AXI_ARBURST(), 370 | .S_AXI_ARLOCK(), 371 | .S_AXI_ARCACHE(), 372 | .S_AXI_ARPROT(), 373 | .S_AXI_ARQOS(), 374 | .S_AXI_ARREGION(), 375 | .S_AXI_ARUSER(), 376 | .S_AXI_ARVALID(), 377 | .S_AXI_ARREADY(), 378 | .S_AXI_RID(), 379 | .S_AXI_RDATA(), 380 | .S_AXI_RRESP(), 381 | .S_AXI_RLAST(), 382 | .S_AXI_RUSER(), 383 | .S_AXI_RVALID(), 384 | .S_AXI_RREADY(), 385 | .M_AXI_ARID(), 386 | .M_AXI_ARADDR(), 387 | .M_AXI_ARLEN(), 388 | .M_AXI_ARSIZE(), 389 | .M_AXI_ARBURST(), 390 | .M_AXI_ARLOCK(), 391 | .M_AXI_ARCACHE(), 392 | .M_AXI_ARPROT(), 393 | .M_AXI_ARQOS(), 394 | .M_AXI_ARREGION(), 395 | .M_AXI_ARUSER(), 396 | .M_AXI_ARVALID(), 397 | .M_AXI_ARREADY(), 398 | .M_AXI_RID(), 399 | .M_AXI_RDATA(), 400 | .M_AXI_RRESP(), 401 | .M_AXI_RLAST(), 402 | .M_AXI_RUSER(), 403 | .M_AXI_RVALID(), 404 | .M_AXI_RREADY(), 405 | .S_AXIS_TVALID(), 406 | .S_AXIS_TREADY(), 407 | .S_AXIS_TDATA(), 408 | .S_AXIS_TSTRB(), 409 | .S_AXIS_TKEEP(), 410 | .S_AXIS_TLAST(), 411 | .S_AXIS_TID(), 412 | .S_AXIS_TDEST(), 413 | .S_AXIS_TUSER(), 414 | .M_AXIS_TVALID(), 415 | .M_AXIS_TREADY(), 416 | .M_AXIS_TDATA(), 417 | .M_AXIS_TSTRB(), 418 | .M_AXIS_TKEEP(), 419 | .M_AXIS_TLAST(), 420 | .M_AXIS_TID(), 421 | .M_AXIS_TDEST(), 422 | .M_AXIS_TUSER(), 423 | .AXI_AW_INJECTSBITERR(), 424 | .AXI_AW_INJECTDBITERR(), 425 | .AXI_AW_PROG_FULL_THRESH(), 426 | .AXI_AW_PROG_EMPTY_THRESH(), 427 | .AXI_AW_DATA_COUNT(), 428 | .AXI_AW_WR_DATA_COUNT(), 429 | .AXI_AW_RD_DATA_COUNT(), 430 | .AXI_AW_SBITERR(), 431 | .AXI_AW_DBITERR(), 432 | .AXI_AW_OVERFLOW(), 433 | .AXI_AW_UNDERFLOW(), 434 | .AXI_W_INJECTSBITERR(), 435 | .AXI_W_INJECTDBITERR(), 436 | .AXI_W_PROG_FULL_THRESH(), 437 | .AXI_W_PROG_EMPTY_THRESH(), 438 | .AXI_W_DATA_COUNT(), 439 | .AXI_W_WR_DATA_COUNT(), 440 | .AXI_W_RD_DATA_COUNT(), 441 | .AXI_W_SBITERR(), 442 | .AXI_W_DBITERR(), 443 | .AXI_W_OVERFLOW(), 444 | .AXI_W_UNDERFLOW(), 445 | .AXI_B_INJECTSBITERR(), 446 | .AXI_B_INJECTDBITERR(), 447 | .AXI_B_PROG_FULL_THRESH(), 448 | .AXI_B_PROG_EMPTY_THRESH(), 449 | .AXI_B_DATA_COUNT(), 450 | .AXI_B_WR_DATA_COUNT(), 451 | .AXI_B_RD_DATA_COUNT(), 452 | .AXI_B_SBITERR(), 453 | .AXI_B_DBITERR(), 454 | .AXI_B_OVERFLOW(), 455 | .AXI_B_UNDERFLOW(), 456 | .AXI_AR_INJECTSBITERR(), 457 | .AXI_AR_INJECTDBITERR(), 458 | .AXI_AR_PROG_FULL_THRESH(), 459 | .AXI_AR_PROG_EMPTY_THRESH(), 460 | .AXI_AR_DATA_COUNT(), 461 | .AXI_AR_WR_DATA_COUNT(), 462 | .AXI_AR_RD_DATA_COUNT(), 463 | .AXI_AR_SBITERR(), 464 | .AXI_AR_DBITERR(), 465 | .AXI_AR_OVERFLOW(), 466 | .AXI_AR_UNDERFLOW(), 467 | .AXI_R_INJECTSBITERR(), 468 | .AXI_R_INJECTDBITERR(), 469 | .AXI_R_PROG_FULL_THRESH(), 470 | .AXI_R_PROG_EMPTY_THRESH(), 471 | .AXI_R_DATA_COUNT(), 472 | .AXI_R_WR_DATA_COUNT(), 473 | .AXI_R_RD_DATA_COUNT(), 474 | .AXI_R_SBITERR(), 475 | .AXI_R_DBITERR(), 476 | .AXI_R_OVERFLOW(), 477 | .AXI_R_UNDERFLOW(), 478 | .AXIS_INJECTSBITERR(), 479 | .AXIS_INJECTDBITERR(), 480 | .AXIS_PROG_FULL_THRESH(), 481 | .AXIS_PROG_EMPTY_THRESH(), 482 | .AXIS_DATA_COUNT(), 483 | .AXIS_WR_DATA_COUNT(), 484 | .AXIS_RD_DATA_COUNT(), 485 | .AXIS_SBITERR(), 486 | .AXIS_DBITERR(), 487 | .AXIS_OVERFLOW(), 488 | .AXIS_UNDERFLOW()); 489 | 490 | 491 | // synthesis translate_on 492 | 493 | // XST black box declaration 494 | // box_type "black_box" 495 | // synthesis attribute box_type of fifo_2kx18 is "black_box" 496 | 497 | endmodule 498 | 499 | -------------------------------------------------------------------------------- /sources_1/imports/common/i2c_snoop_edid.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011, Andrew "bunnie" Huang 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without modification, 6 | // are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, 9 | // this list of conditions and the following disclaimer. 10 | // * Redistributions in binary form must reproduce the above copyright notice, 11 | // this list of conditions and the following disclaimer in the documentation and/or 12 | // other materials provided with the distribution. 13 | // 14 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 15 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 17 | // SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 18 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 19 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 22 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 23 | // POSSIBILITY OF SUCH DAMAGE. 24 | // 25 | ////////////////////////////////////////////////////////////////////////////// 26 | // An I2C bus snooper implementation. Oversampled for robustness. 27 | // 28 | // There are two versions, the EDID snooper and the HDCP snooper 29 | // 30 | // It's split because EDID records can be very large and the compiler should 31 | // infer a block ram for the large records. However, the nature of the HDCP 32 | // registers would cause the compiler to infer slice registers. Thus, this code 33 | // is identical to the HDCP snoop with the exception that the HDCP read ports 34 | // are removed which will allow the compiler to properly infer a LUT RAM. 35 | /////////// 36 | `timescale 1 ns / 1 ps 37 | 38 | module i2c_snoop_edid ( 39 | // external host interface 40 | input wire SCL, // the SCL pin state 41 | input wire SDA, 42 | 43 | input wire clk, // internal FPGA clock 44 | input wire reset, // internal FPGA reset 45 | // i2c configuration 46 | input wire [7:0] i2c_snoop_addr, 47 | 48 | // internal slave interface to read snooped register 49 | input wire [7:0] reg_addr, 50 | output wire [7:0] reg_dout 51 | 52 | ); 53 | 54 | /////// I2C physical layer components 55 | /// SDA is stable when SCL is high. 56 | /// If SDA moves while SCL is high, this is considered a start or stop condition. 57 | /// 58 | /// Otherwise, SDA can move around when SCL is low (this is where we suppress bits or 59 | /// overdrive as needed). SDA is a wired-AND bus, so you only "drive" zero. 60 | /// 61 | /// In an oversampled implementation, a rising and falling edge de-glitcher is needed 62 | /// for SCL and SDA. 63 | /// 64 | 65 | // rise fall time cycles computation: 66 | // At 400kHz operation, 2.5us is a cycle. "chatter" from transition should be about 67 | // 5% of total cycle time max (just rule of thumb), so 0.125us should be the equiv 68 | // number of cycles. 69 | // For the demo board, a 25 MHz clock is provided, and 0.125us ~ 4 cycles 70 | // At 100kHz operation, 10us is a cycle, so 0.5us ~ 12 cycles 71 | parameter TRF_CYCLES = 5'd4; // number of cycles for rise/fall time 72 | 73 | // just some tie-offs for future functionality not yet implemented... 74 | assign SDA_pu = 1'b0; 75 | assign SCL_pd = 1'b0; 76 | 77 | //////////////// 78 | ///// protocol-level state machine 79 | //////////////// 80 | parameter I2C_START = 14'b1 << 0; // should only pass through this state for one cycle 81 | parameter I2C_RESTART = 14'b1 << 1; 82 | parameter I2C_DADDR = 14'b1 << 2; 83 | parameter I2C_ACK_DADDR = 14'b1 << 3; 84 | parameter I2C_ADDR = 14'b1 << 4; 85 | parameter I2C_ACK_ADDR = 14'b1 << 5; 86 | parameter I2C_WR_DATA = 14'b1 << 6; 87 | parameter I2C_ACK_WR = 14'b1 << 7; 88 | parameter I2C_END_WR = 14'b1 << 8; 89 | parameter I2C_RD_DATA = 14'b1 << 9; 90 | parameter I2C_ACK_RD = 14'b1 << 10; 91 | parameter I2C_END_RD = 14'b1 << 11; 92 | parameter I2C_END_RD2 = 14'b1 << 12; 93 | parameter I2C_WAITSTOP = 14'b1 << 13; 94 | 95 | parameter I2C_nSTATES = 14; 96 | 97 | reg [(I2C_nSTATES-1):0] I2C_cstate = {{(I2C_nSTATES-1){1'b0}}, 1'b1}; //current and next states 98 | reg [(I2C_nSTATES-1):0] I2C_nstate; 99 | 100 | //`define SIMULATION 101 | `ifdef SIMULATION 102 | // synthesis translate_off 103 | reg [8*20:1] I2C_state_ascii = "I2C_START "; 104 | always @(I2C_cstate) begin 105 | if (I2C_cstate == I2C_START) I2C_state_ascii <= "I2C_START "; 106 | else if (I2C_cstate == I2C_RESTART) I2C_state_ascii <= "I2C_RESTART "; 107 | else if (I2C_cstate == I2C_DADDR) I2C_state_ascii <= "I2C_DADDR "; 108 | else if (I2C_cstate == I2C_ACK_DADDR) I2C_state_ascii <= "I2C_ACK_DADDR "; 109 | else if (I2C_cstate == I2C_ADDR) I2C_state_ascii <= "I2C_ADDR "; 110 | else if (I2C_cstate == I2C_ACK_ADDR) I2C_state_ascii <= "I2C_ACK_ADDR "; 111 | else if (I2C_cstate == I2C_WR_DATA) I2C_state_ascii <= "I2C_WR_DATA "; 112 | else if (I2C_cstate == I2C_ACK_WR) I2C_state_ascii <= "I2C_ACK_WR "; 113 | else if (I2C_cstate == I2C_END_WR) I2C_state_ascii <= "I2C_END_WR "; 114 | else if (I2C_cstate == I2C_RD_DATA) I2C_state_ascii <= "I2C_RD_DATA "; 115 | else if (I2C_cstate == I2C_ACK_RD) I2C_state_ascii <= "I2C_ACK_RD "; 116 | else if (I2C_cstate == I2C_END_RD) I2C_state_ascii <= "I2C_END_RD "; 117 | else if (I2C_cstate == I2C_END_RD2) I2C_state_ascii <= "I2C_END_RD2 "; 118 | else if (I2C_cstate == I2C_WAITSTOP) I2C_state_ascii <= "I2C_WAITSTOP "; 119 | else I2C_state_ascii <= "WTF "; 120 | end 121 | // synthesis translate_on 122 | `endif 123 | 124 | reg [3:0] I2C_bitcnt; 125 | reg [7:0] I2C_addr; 126 | reg [7:0] I2C_daddr; 127 | reg [7:0] I2C_wdata; 128 | reg [7:0] I2C_rdata; 129 | reg I2C_reg_update; 130 | 131 | always @ (posedge clk) begin 132 | if (reset || ((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) // stop condition always resets 133 | I2C_cstate <= I2C_START; 134 | else 135 | I2C_cstate <=#1 I2C_nstate; 136 | end 137 | 138 | always @ (*) begin 139 | case (I2C_cstate) //synthesis parallel_case full_case 140 | I2C_START: begin // wait for the start condition 141 | I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_DADDR : I2C_START; 142 | end 143 | I2C_RESTART: begin // repeated start moves immediately to DADDR 144 | I2C_nstate = I2C_DADDR; 145 | end 146 | I2C_DADDR: begin // 8 bits to get the address 147 | I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_DADDR : I2C_DADDR; 148 | end 149 | I2C_ACK_DADDR: begin // depending upon W/R bit state, go to one of two branches 150 | I2C_nstate = (SCL_cstate == SCL_FALL) ? 151 | (I2C_daddr[7:1] != i2c_snoop_addr[7:1]) ? // get everything *but* HDCP 152 | (I2C_daddr[0] == 1'b0 ? I2C_ADDR : I2C_RD_DATA) : 153 | I2C_WAITSTOP : // !I2C_daddr match 154 | I2C_ACK_DADDR; // !SCL_FALL 155 | end 156 | 157 | // device address branch 158 | I2C_ADDR: begin 159 | I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_ADDR : I2C_ADDR; 160 | end 161 | I2C_ACK_ADDR: begin 162 | I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_WR_DATA : I2C_ACK_ADDR; 163 | end 164 | 165 | // write branch 166 | I2C_WR_DATA: begin // 8 bits to get the write data 167 | I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start 168 | ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_WR : I2C_WR_DATA; 169 | end 170 | I2C_ACK_WR: begin // trigger the ack response (pull SDA low until next falling edge) 171 | // and stay in this state until the next falling edge of SCL 172 | I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_END_WR : I2C_ACK_WR; 173 | end 174 | I2C_END_WR: begin // one-cycle state to update address+1, reset SDA pulldown 175 | I2C_nstate = I2C_WR_DATA; // SCL is now low 176 | end 177 | 178 | // read branch 179 | I2C_RD_DATA: begin // 8 bits to get the read data 180 | I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start 181 | ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_RD : I2C_RD_DATA; 182 | end 183 | I2C_ACK_RD: begin // wait for an (n)ack response 184 | // need to sample (n)ack on a rising edge 185 | I2C_nstate = (SCL_cstate == SCL_RISE) ? I2C_END_RD : I2C_ACK_RD; 186 | end 187 | I2C_END_RD: begin // if nack, just go to start state (don't explicitly check stop event) 188 | // single cycle state for adr+1 update 189 | I2C_nstate = (SDA_cstate == SDA_LOW) ? I2C_END_RD2 : I2C_START; 190 | end 191 | I2C_END_RD2: begin // before entering I2C_RD_DATA, we need to have seen a falling edge. 192 | I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_RD_DATA : I2C_END_RD2; 193 | end 194 | 195 | // we're not the addressed device, so we just idle until we see a stop 196 | I2C_WAITSTOP: begin 197 | I2C_nstate = (((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) ? // stop 198 | I2C_START : 199 | (((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_FALL))) ? // or start 200 | I2C_RESTART : 201 | I2C_WAITSTOP; 202 | end 203 | endcase // case (cstate) 204 | end 205 | 206 | always @ (posedge clk or posedge reset) begin 207 | if( reset ) begin 208 | I2C_bitcnt <=#1 4'b0; 209 | I2C_daddr <=#1 8'b0; 210 | I2C_wdata <=#1 8'b0; 211 | I2C_reg_update <=#1 1'b0; 212 | I2C_rdata <=#1 8'b0; 213 | I2C_addr <=#1 8'b0; // this persists across transactions 214 | end else begin 215 | case (I2C_cstate) // synthesis parallel_case full_case 216 | I2C_START: begin // everything in reset 217 | I2C_bitcnt <=#1 4'b0; 218 | I2C_daddr <=#1 8'b0; 219 | I2C_wdata <=#1 8'b0; 220 | I2C_rdata <=#1 8'b0; 221 | I2C_reg_update <=#1 1'b0; 222 | I2C_addr <=#1 I2C_addr; 223 | end 224 | 225 | I2C_RESTART: begin 226 | I2C_bitcnt <=#1 4'b0; 227 | I2C_daddr <=#1 8'b0; 228 | I2C_wdata <=#1 8'b0; 229 | I2C_rdata <=#1 8'b0; 230 | I2C_reg_update <=#1 1'b0; 231 | I2C_addr <=#1 I2C_addr; 232 | end 233 | 234 | // get my i2c device address (am I being talked to?) 235 | I2C_DADDR: begin // shift in the address on rising edges of clock 236 | if( SCL_cstate == SCL_RISE ) begin 237 | I2C_bitcnt <=#1 I2C_bitcnt + 4'b1; 238 | I2C_daddr[7] <=#1 I2C_daddr[6]; 239 | I2C_daddr[6] <=#1 I2C_daddr[5]; 240 | I2C_daddr[5] <=#1 I2C_daddr[4]; 241 | I2C_daddr[4] <=#1 I2C_daddr[3]; 242 | I2C_daddr[3] <=#1 I2C_daddr[2]; 243 | I2C_daddr[2] <=#1 I2C_daddr[1]; 244 | I2C_daddr[1] <=#1 I2C_daddr[0]; 245 | I2C_daddr[0] <=#1 (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0; 246 | end else begin // we're oversampled so we need a hold-state gutter 247 | I2C_bitcnt <=#1 I2C_bitcnt; 248 | I2C_daddr <=#1 I2C_daddr; 249 | end // else: !if( SCL_cstate == SCL_RISE ) 250 | I2C_wdata <=#1 8'b0; 251 | I2C_rdata <=#1 8'b0; 252 | I2C_reg_update <=#1 1'b0; 253 | I2C_addr <=#1 I2C_addr; 254 | end // case: I2C_DADDR 255 | I2C_ACK_DADDR: begin 256 | I2C_daddr <=#1 I2C_daddr; 257 | I2C_bitcnt <=#1 4'b0; 258 | I2C_wdata <=#1 8'b0; 259 | I2C_rdata <=#1 I2C_regread_async; 260 | I2C_reg_update <=#1 1'b0; 261 | I2C_addr <=#1 I2C_addr; 262 | end 263 | 264 | // get my i2c "write" address (what we want to access inside me) 265 | I2C_ADDR: begin 266 | if( SCL_cstate == SCL_RISE ) begin 267 | I2C_bitcnt <=#1 I2C_bitcnt + 4'b1; 268 | I2C_addr[7] <=#1 I2C_addr[6]; 269 | I2C_addr[6] <=#1 I2C_addr[5]; 270 | I2C_addr[5] <=#1 I2C_addr[4]; 271 | I2C_addr[4] <=#1 I2C_addr[3]; 272 | I2C_addr[3] <=#1 I2C_addr[2]; 273 | I2C_addr[2] <=#1 I2C_addr[1]; 274 | I2C_addr[1] <=#1 I2C_addr[0]; 275 | I2C_addr[0] <=#1 (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0; 276 | end else begin // we're oversampled so we need a hold-state gutter 277 | I2C_bitcnt <=#1 I2C_bitcnt; 278 | I2C_addr <=#1 I2C_addr; 279 | end // else: !if( SCL_cstate == SCL_RISE ) 280 | I2C_wdata <=#1 8'b0; 281 | I2C_rdata <=#1 8'b0; 282 | I2C_reg_update <=#1 1'b0; 283 | I2C_daddr <=#1 I2C_daddr; 284 | end // case: I2C_ADDR 285 | I2C_ACK_ADDR: begin 286 | I2C_daddr <=#1 I2C_daddr; 287 | I2C_bitcnt <=#1 4'b0; 288 | I2C_wdata <=#1 8'b0; 289 | I2C_rdata <=#1 I2C_regread_async; // update my read data here 290 | I2C_reg_update <=#1 1'b0; 291 | I2C_addr <=#1 I2C_addr; 292 | end 293 | 294 | 295 | // write branch 296 | I2C_WR_DATA: begin // shift in data on rising edges of clock 297 | if( SCL_cstate == SCL_RISE ) begin 298 | I2C_bitcnt <=#1 I2C_bitcnt + 4'b1; 299 | I2C_wdata[7] <=#1 I2C_wdata[6]; 300 | I2C_wdata[6] <=#1 I2C_wdata[5]; 301 | I2C_wdata[5] <=#1 I2C_wdata[4]; 302 | I2C_wdata[4] <=#1 I2C_wdata[3]; 303 | I2C_wdata[3] <=#1 I2C_wdata[2]; 304 | I2C_wdata[2] <=#1 I2C_wdata[1]; 305 | I2C_wdata[1] <=#1 I2C_wdata[0]; 306 | I2C_wdata[0] <=#1 (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0; 307 | end else begin 308 | I2C_bitcnt <=#1 I2C_bitcnt; // hold state gutter 309 | I2C_wdata <=#1 I2C_wdata; 310 | end // else: !if( SCL_cstate == SCL_RISE ) 311 | I2C_daddr <=#1 I2C_daddr; 312 | I2C_reg_update <=#1 1'b0; 313 | I2C_rdata <=#1 I2C_rdata; 314 | I2C_addr <=#1 I2C_addr; 315 | end // case: I2C_WR_DATA 316 | I2C_ACK_WR: begin 317 | I2C_daddr <=#1 I2C_daddr; 318 | I2C_bitcnt <=#1 4'b0; 319 | I2C_wdata <=#1 I2C_wdata; 320 | I2C_reg_update <=#1 1'b1; // write the data now (over and over again while in state) 321 | I2C_rdata <=#1 I2C_rdata; 322 | I2C_addr <=#1 I2C_addr; 323 | end 324 | I2C_END_WR: begin 325 | I2C_addr <=#1 I2C_addr + 8'b1; // this is a one-cycle state so this is safe 326 | I2C_bitcnt <=#1 4'b0; 327 | I2C_wdata <=#1 8'b0; 328 | I2C_rdata <=#1 I2C_rdata; 329 | I2C_reg_update <=#1 1'b0; 330 | I2C_daddr <=#1 I2C_daddr; 331 | end 332 | 333 | // read branch 334 | I2C_RD_DATA: begin // shift out data on falling edges of clock 335 | if( SCL_cstate == SCL_RISE ) begin 336 | I2C_bitcnt <=#1 I2C_bitcnt + 4'b1; 337 | 338 | I2C_rdata[7] <=#1 I2C_rdata[6]; 339 | I2C_rdata[6] <=#1 I2C_rdata[5]; 340 | I2C_rdata[5] <=#1 I2C_rdata[4]; 341 | I2C_rdata[4] <=#1 I2C_rdata[3]; 342 | I2C_rdata[3] <=#1 I2C_rdata[2]; 343 | I2C_rdata[2] <=#1 I2C_rdata[1]; 344 | I2C_rdata[1] <=#1 I2C_rdata[0]; 345 | I2C_rdata[0] <=#1 (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0; 346 | end else begin 347 | I2C_bitcnt <=#1 I2C_bitcnt; // hold state gutter 348 | I2C_rdata <=#1 I2C_rdata; 349 | end 350 | I2C_daddr <=#1 I2C_daddr; 351 | I2C_reg_update <=#1 1'b0; 352 | I2C_wdata <=#1 I2C_rdata; // push rdata to wdata 353 | I2C_addr <=#1 I2C_addr; 354 | end // case: I2C_RD_DATA 355 | I2C_ACK_RD: begin 356 | I2C_daddr <=#1 I2C_daddr; 357 | I2C_bitcnt <=#1 4'b0; 358 | I2C_rdata <=#1 I2C_rdata; 359 | I2C_reg_update <=#1 1'b1; // commit reads even to our internal bank 360 | I2C_wdata <=#1 I2C_rdata; // push rdata to wdata 361 | I2C_addr <=#1 I2C_addr; 362 | end 363 | I2C_END_RD: begin 364 | I2C_addr <=#1 I2C_addr + 8'b1; // this is a one-cycle state so this is safe 365 | I2C_bitcnt <=#1 4'b0; 366 | I2C_rdata <=#1 I2C_rdata; 367 | I2C_reg_update <=#1 1'b0; 368 | I2C_wdata <=#1 I2C_wdata; 369 | I2C_daddr <=#1 I2C_daddr; 370 | end 371 | I2C_END_RD2: begin 372 | I2C_daddr <=#1 8'b0; 373 | I2C_bitcnt <=#1 4'b0; 374 | I2C_rdata <=#1 I2C_rdata; 375 | I2C_reg_update <=#1 1'b0; 376 | I2C_wdata <=#1 I2C_wdata; 377 | I2C_addr <=#1 I2C_addr; 378 | end 379 | 380 | I2C_WAITSTOP: begin 381 | I2C_daddr <=#1 8'b0; 382 | I2C_bitcnt <=#1 4'b0; 383 | I2C_rdata <=#1 I2C_rdata; 384 | I2C_reg_update <=#1 1'b0; 385 | I2C_wdata <=#1 I2C_wdata; 386 | I2C_addr <=#1 I2C_addr; 387 | end 388 | endcase // case (cstate) 389 | end // else: !if( reset ) 390 | end // always @ (posedge clk or posedge reset) 391 | 392 | //////////////// 393 | ///// register bank management 394 | //////////////// 395 | parameter RAM_WIDTH = 8; 396 | parameter RAM_ADDR_BITS = 8; 397 | 398 | (* RAM_STYLE="{AUTO | DISTRIBUTED | PIPE_DISTRIBUTED}" *) 399 | reg [RAM_WIDTH-1:0] I2C_regblock [(2**RAM_ADDR_BITS)-1:0]; 400 | wire [RAM_WIDTH-1:0] I2C_regread_async; 401 | 402 | wire [RAM_ADDR_BITS-1:0] I2C_ramaddr; 403 | 404 | reg wr_stb_d; 405 | 406 | always @(posedge clk) begin 407 | if (I2C_reg_update) begin // this should be multiple cycles 408 | I2C_regblock[I2C_ramaddr] <= I2C_wdata; 409 | end 410 | end 411 | 412 | assign I2C_regread_async = I2C_regblock[I2C_ramaddr]; 413 | assign reg_dout = I2C_regblock[reg_addr[RAM_ADDR_BITS-1:0]]; 414 | 415 | assign I2C_ramaddr = I2C_addr[RAM_ADDR_BITS-1:0]; 416 | 417 | //////////////// 418 | ///// SCL low-level sampling state machine 419 | //////////////// 420 | parameter SCL_HIGH = 4'b1 << 0; // should only pass through this state for one cycle 421 | parameter SCL_FALL = 4'b1 << 1; 422 | parameter SCL_LOW = 4'b1 << 2; 423 | parameter SCL_RISE = 4'b1 << 3; 424 | parameter SCL_nSTATES = 4; 425 | 426 | reg [(SCL_nSTATES-1):0] SCL_cstate = {{(SCL_nSTATES-1){1'b0}}, 1'b1}; //current and next states 427 | reg [(SCL_nSTATES-1):0] SCL_nstate; 428 | 429 | //`define SIMULATION 430 | `ifdef SIMULATION 431 | // synthesis translate_off 432 | reg [8*20:1] SCL_state_ascii = "SCL_HIGH "; 433 | 434 | always @(SCL_cstate) begin 435 | if (SCL_cstate == SCL_HIGH) SCL_state_ascii <= "SCL_HIGH "; 436 | else if (SCL_cstate == SCL_FALL) SCL_state_ascii <= "SCL_FALL "; 437 | else if (SCL_cstate == SCL_LOW ) SCL_state_ascii <= "SCL_LOW "; 438 | else if (SCL_cstate == SCL_RISE) SCL_state_ascii <= "SCL_RISE "; 439 | else SCL_state_ascii <= "WTF "; 440 | end 441 | // synthesis translate_on 442 | `endif 443 | 444 | reg [4:0] SCL_rfcnt; 445 | reg SCL_s, SCL_sync; 446 | reg SDA_s, SDA_sync; 447 | 448 | always @ (posedge clk or posedge reset) begin 449 | if (reset) 450 | SCL_cstate <= SCL_HIGH; // always start here even if it's wrong -- easier to test 451 | else 452 | SCL_cstate <=#1 SCL_nstate; 453 | end 454 | 455 | always @ (*) begin 456 | case (SCL_cstate) //synthesis parallel_case full_case 457 | SCL_HIGH: begin 458 | SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b0)) ? SCL_FALL : SCL_HIGH; 459 | end 460 | SCL_FALL: begin 461 | SCL_nstate = SCL_LOW; 462 | end 463 | SCL_LOW: begin 464 | SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b1)) ? SCL_RISE : SCL_LOW; 465 | end 466 | SCL_RISE: begin 467 | SCL_nstate = SCL_HIGH; 468 | end 469 | endcase // case (cstate) 470 | end // always @ (*) 471 | 472 | always @ (posedge clk or posedge reset) begin 473 | if( reset ) begin 474 | SCL_rfcnt <=#1 5'b0; 475 | end else begin 476 | case (SCL_cstate) // synthesis parallel_case full_case 477 | SCL_HIGH: begin 478 | if( SCL_sync == 1'b1 ) begin 479 | SCL_rfcnt <=#1 5'b0; 480 | end else begin 481 | SCL_rfcnt <=#1 SCL_rfcnt + 5'b1; 482 | end 483 | end 484 | SCL_FALL: begin 485 | SCL_rfcnt <=#1 5'b0; 486 | end 487 | SCL_LOW: begin 488 | if( SCL_sync == 1'b0 ) begin 489 | SCL_rfcnt <=#1 5'b0; 490 | end else begin 491 | SCL_rfcnt <=#1 SCL_rfcnt + 5'b1; 492 | end 493 | end 494 | SCL_RISE: begin 495 | SCL_rfcnt <=#1 5'b0; 496 | end 497 | endcase // case (cstate) 498 | end // else: !if( reset ) 499 | end // always @ (posedge clk or posedge reset) 500 | 501 | 502 | //////////////// 503 | ///// SDA low-level sampling state machine 504 | //////////////// 505 | parameter SDA_HIGH = 4'b1 << 0; // should only pass through this state for one cycle 506 | parameter SDA_FALL = 4'b1 << 1; 507 | parameter SDA_LOW = 4'b1 << 2; 508 | parameter SDA_RISE = 4'b1 << 3; 509 | parameter SDA_nSTATES = 4; 510 | 511 | reg [(SDA_nSTATES-1):0] SDA_cstate = {{(SDA_nSTATES-1){1'b0}}, 1'b1}; //current and next states 512 | reg [(SDA_nSTATES-1):0] SDA_nstate; 513 | 514 | //`define SIMULATION 515 | `ifdef SIMULATION 516 | // synthesis translate_off 517 | reg [8*20:1] SDA_state_ascii = "SDA_HIGH "; 518 | 519 | always @(SDA_cstate) begin 520 | if (SDA_cstate == SDA_HIGH) SDA_state_ascii <= "SDA_HIGH "; 521 | else if (SDA_cstate == SDA_FALL) SDA_state_ascii <= "SDA_FALL "; 522 | else if (SDA_cstate == SDA_LOW ) SDA_state_ascii <= "SDA_LOW "; 523 | else if (SDA_cstate == SDA_RISE) SDA_state_ascii <= "SDA_RISE "; 524 | else SDA_state_ascii <= "WTF "; 525 | end 526 | // synthesis translate_on 527 | `endif 528 | 529 | reg [4:0] SDA_rfcnt; 530 | 531 | always @ (posedge clk or posedge reset) begin 532 | if (reset) 533 | SDA_cstate <= SDA_HIGH; // always start here even if it's wrong -- easier to test 534 | else 535 | SDA_cstate <=#1 SDA_nstate; 536 | end 537 | 538 | always @ (*) begin 539 | case (SDA_cstate) //synthesis parallel_case full_case 540 | SDA_HIGH: begin 541 | SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b0)) ? SDA_FALL : SDA_HIGH; 542 | end 543 | SDA_FALL: begin 544 | SDA_nstate = SDA_LOW; 545 | end 546 | SDA_LOW: begin 547 | SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b1)) ? SDA_RISE : SDA_LOW; 548 | end 549 | SDA_RISE: begin 550 | SDA_nstate = SDA_HIGH; 551 | end 552 | endcase // case (cstate) 553 | end // always @ (*) 554 | 555 | always @ (posedge clk or posedge reset) begin 556 | if( reset ) begin 557 | SDA_rfcnt <=#1 5'b0; 558 | end else begin 559 | case (SDA_cstate) // synthesis parallel_case full_case 560 | SDA_HIGH: begin 561 | if( SDA_sync == 1'b1 ) begin 562 | SDA_rfcnt <=#1 5'b0; 563 | end else begin 564 | SDA_rfcnt <=#1 SDA_rfcnt + 5'b1; 565 | end 566 | end 567 | SDA_FALL: begin 568 | SDA_rfcnt <=#1 5'b0; 569 | end 570 | SDA_LOW: begin 571 | if( SDA_sync == 1'b0 ) begin 572 | SDA_rfcnt <=#1 5'b0; 573 | end else begin 574 | SDA_rfcnt <=#1 SDA_rfcnt + 5'b1; 575 | end 576 | end 577 | SDA_RISE: begin 578 | SDA_rfcnt <=#1 5'b0; 579 | end 580 | endcase // case (cstate) 581 | end // else: !if( reset ) 582 | end // always @ (posedge clk or posedge reset) 583 | 584 | 585 | 586 | ///////////////////// 587 | /////// synchronizers 588 | ///////////////////// 589 | always @ (posedge clk or posedge reset) begin 590 | if (reset) begin 591 | SCL_s <= 0; 592 | SCL_sync <= 0; 593 | SDA_s <= 0; 594 | SDA_sync <= 0; 595 | end else begin 596 | SCL_s <= SCL; 597 | SCL_sync <= SCL_s; 598 | SDA_s <= SDA; 599 | SDA_sync <= SDA_s; 600 | end // else: !if(reset) 601 | end // always @ (posedge clk or posedge reset) 602 | 603 | endmodule // i2c_slave 604 | --------------------------------------------------------------------------------