├── .gitignore ├── LICENSE ├── README.md ├── hdcp_engine.srcs └── sources_1 │ └── imports │ └── srcs-origin │ ├── component.xml │ ├── diff_network.v │ ├── hdcp_block.v │ ├── hdcp_cipher.v │ ├── hdcp_engine.v │ ├── hdcp_lfsr.v │ ├── shuffle_network.v │ └── xgui │ ├── hdcp_engine_v1_0.tcl │ └── hdcp_engine_v1_1.tcl └── hdcp_engine.xpr /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # NeTV2 FPGA HDCP Engine 2 | 3 | Implements the chipher logic for HDCP. Needs key inputs 4 | provided by host, see https://github.com/bunnie/netv2-derive_km 5 | and https://github.com/bunnie/netv2-fpga-hdcp-snoop for 6 | related blocks. 7 | 8 | It's tested to work with Vivado 2016.1. 9 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/component.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | alphamaxmedia.com 4 | bunnie 5 | hdcp_engine 6 | 1.1 7 | 8 | 9 | reset 10 | 11 | 12 | 13 | 14 | 15 | 16 | RST 17 | 18 | 19 | reset 20 | 21 | 22 | 23 | 24 | 25 | clk 26 | 27 | 28 | 29 | 30 | 31 | 32 | CLK 33 | 34 | 35 | clk 36 | 37 | 38 | 39 | 40 | 41 | ASSOCIATED_RESET 42 | reset 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | xilinx_anylanguagesynthesis 51 | Synthesis 52 | :vivado.xilinx.com:synthesis 53 | Verilog 54 | hdcp_engine 55 | 56 | xilinx_anylanguagesynthesis_view_fileset 57 | 58 | 59 | 60 | viewChecksum 61 | dd1adaef 62 | 63 | 64 | 65 | 66 | xilinx_anylanguagebehavioralsimulation 67 | Simulation 68 | :vivado.xilinx.com:simulation 69 | Verilog 70 | hdcp_engine 71 | 72 | xilinx_anylanguagebehavioralsimulation_view_fileset 73 | 74 | 75 | 76 | viewChecksum 77 | dd1adaef 78 | 79 | 80 | 81 | 82 | xilinx_xpgui 83 | UI Layout 84 | :vivado.xilinx.com:xgui.ui 85 | 86 | xilinx_xpgui_view_fileset 87 | 88 | 89 | 90 | viewChecksum 91 | d04bca28 92 | 93 | 94 | 95 | 96 | 97 | 98 | clk 99 | 100 | in 101 | 102 | 103 | wire 104 | xilinx_anylanguagesynthesis 105 | xilinx_anylanguagebehavioralsimulation 106 | 107 | 108 | 109 | 110 | 111 | reset 112 | 113 | in 114 | 115 | 116 | std_logic 117 | xilinx_anylanguagesynthesis 118 | xilinx_anylanguagebehavioralsimulation 119 | 120 | 121 | 122 | 123 | 124 | hpd 125 | 126 | in 127 | 128 | 129 | std_logic 130 | xilinx_anylanguagesynthesis 131 | xilinx_anylanguagebehavioralsimulation 132 | 133 | 134 | 135 | 136 | 137 | ctl_code 138 | 139 | in 140 | 141 | 3 142 | 0 143 | 144 | 145 | 146 | std_logic_vector 147 | xilinx_anylanguagesynthesis 148 | xilinx_anylanguagebehavioralsimulation 149 | 150 | 151 | 152 | 153 | 154 | cv 155 | 156 | in 157 | 158 | 159 | std_logic 160 | xilinx_anylanguagesynthesis 161 | xilinx_anylanguagebehavioralsimulation 162 | 163 | 164 | 165 | 166 | 167 | de 168 | 169 | in 170 | 171 | 172 | std_logic 173 | xilinx_anylanguagesynthesis 174 | xilinx_anylanguagebehavioralsimulation 175 | 176 | 177 | 178 | 179 | 180 | line_end 181 | 182 | in 183 | 184 | 185 | std_logic 186 | xilinx_anylanguagesynthesis 187 | xilinx_anylanguagebehavioralsimulation 188 | 189 | 190 | 191 | 192 | 193 | hsync 194 | 195 | in 196 | 197 | 198 | std_logic 199 | xilinx_anylanguagesynthesis 200 | xilinx_anylanguagebehavioralsimulation 201 | 202 | 203 | 204 | 205 | 206 | vsync 207 | 208 | in 209 | 210 | 211 | std_logic 212 | xilinx_anylanguagesynthesis 213 | xilinx_anylanguagebehavioralsimulation 214 | 215 | 216 | 217 | 218 | 219 | hdcp_ena 220 | 221 | in 222 | 223 | 224 | std_logic 225 | xilinx_anylanguagesynthesis 226 | xilinx_anylanguagebehavioralsimulation 227 | 228 | 229 | 230 | 231 | 232 | Km_rdy 233 | 234 | in 235 | 236 | 237 | std_logic 238 | xilinx_anylanguagesynthesis 239 | xilinx_anylanguagebehavioralsimulation 240 | 241 | 242 | 243 | 244 | 245 | Km 246 | 247 | in 248 | 249 | 55 250 | 0 251 | 252 | 253 | 254 | std_logic_vector 255 | xilinx_anylanguagesynthesis 256 | xilinx_anylanguagebehavioralsimulation 257 | 258 | 259 | 260 | 261 | 262 | An_rdy 263 | 264 | in 265 | 266 | 267 | std_logic 268 | xilinx_anylanguagesynthesis 269 | xilinx_anylanguagebehavioralsimulation 270 | 271 | 272 | 273 | 274 | 275 | An 276 | 277 | in 278 | 279 | 63 280 | 0 281 | 282 | 283 | 284 | std_logic_vector 285 | xilinx_anylanguagesynthesis 286 | xilinx_anylanguagebehavioralsimulation 287 | 288 | 289 | 290 | 291 | 292 | cipher_stream 293 | 294 | out 295 | 296 | 23 297 | 0 298 | 299 | 300 | 301 | std_logic_vector 302 | xilinx_anylanguagesynthesis 303 | xilinx_anylanguagebehavioralsimulation 304 | 305 | 306 | 307 | 308 | 309 | hdcp_is_ready 310 | 311 | out 312 | 313 | 314 | std_logic 315 | xilinx_anylanguagesynthesis 316 | xilinx_anylanguagebehavioralsimulation 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | HDCP_UNPLUG 325 | Hdcp Unplug 326 | 1 327 | 328 | 329 | HDCP_WAIT_AKSV 330 | Hdcp Wait Aksv 331 | 2 332 | 333 | 334 | HDCP_AUTH_PULSE 335 | Hdcp Auth Pulse 336 | 4 337 | 338 | 339 | HDCP_AUTH 340 | Hdcp Auth 341 | 8 342 | 343 | 344 | HDCP_AUTH_WAIT 345 | Hdcp Auth Wait 346 | 16 347 | 348 | 349 | HDCP_AUTH_VSYNC_PULSE 350 | Hdcp Auth Vsync Pulse 351 | 32 352 | 353 | 354 | HDCP_AUTH_VSYNC 355 | Hdcp Auth Vsync 356 | 64 357 | 358 | 359 | HDCP_AUTH_VSYNC_WAIT 360 | Hdcp Auth Vsync Wait 361 | 128 362 | 363 | 364 | HDCP_WAIT_1001 365 | Hdcp Wait 1001 366 | 256 367 | 368 | 369 | HDCP_WAIT_1001_END 370 | Hdcp Wait 1001 End 371 | 512 372 | 373 | 374 | HDCP_VSYNC 375 | Hdcp Vsync 376 | 1024 377 | 378 | 379 | HDCP_VSYNC_PULSE 380 | Hdcp Vsync Pulse 381 | 2048 382 | 383 | 384 | HDCP_VSYNC_WAIT 385 | Hdcp Vsync Wait 386 | 4096 387 | 388 | 389 | HDCP_READY 390 | Hdcp Ready 391 | 8192 392 | 393 | 394 | HDCP_REKEY 395 | Hdcp Rekey 396 | 16384 397 | 398 | 399 | HDCP_REKEY_PULSE 400 | Hdcp Rekey Pulse 401 | 32768 402 | 403 | 404 | HDCP_REKEY_WAIT 405 | Hdcp Rekey Wait 406 | 65536 407 | 408 | 409 | HDCP_WAIT_KMRDY 410 | Hdcp Wait Kmrdy 411 | 131072 412 | 413 | 414 | HDCP_nSTATES 415 | Hdcp Nstates 416 | 18 417 | 418 | 419 | 420 | 421 | 422 | xilinx_anylanguagesynthesis_view_fileset 423 | 424 | shuffle_network.v 425 | verilogSource 426 | 427 | 428 | diff_network.v 429 | verilogSource 430 | 431 | 432 | hdcp_lfsr.v 433 | verilogSource 434 | 435 | 436 | hdcp_block.v 437 | verilogSource 438 | 439 | 440 | hdcp_cipher.v 441 | verilogSource 442 | 443 | 444 | hdcp_engine.v 445 | verilogSource 446 | CHECKSUM_b114f012 447 | 448 | 449 | 450 | xilinx_anylanguagebehavioralsimulation_view_fileset 451 | 452 | shuffle_network.v 453 | verilogSource 454 | 455 | 456 | diff_network.v 457 | verilogSource 458 | 459 | 460 | hdcp_lfsr.v 461 | verilogSource 462 | 463 | 464 | hdcp_block.v 465 | verilogSource 466 | 467 | 468 | hdcp_cipher.v 469 | verilogSource 470 | 471 | 472 | hdcp_engine.v 473 | verilogSource 474 | 475 | 476 | 477 | xilinx_xpgui_view_fileset 478 | 479 | xgui/hdcp_engine_v1_1.tcl 480 | tclSource 481 | CHECKSUM_f0a014b4 482 | XGUI_VERSION_2 483 | 484 | 485 | 486 | hdcp_engine_v1_1 487 | 488 | 489 | HDCP_UNPLUG 490 | Hdcp Unplug 491 | 1 492 | 493 | 494 | HDCP_WAIT_AKSV 495 | Hdcp Wait Aksv 496 | 2 497 | 498 | 499 | HDCP_AUTH_PULSE 500 | Hdcp Auth Pulse 501 | 4 502 | 503 | 504 | HDCP_AUTH 505 | Hdcp Auth 506 | 8 507 | 508 | 509 | HDCP_AUTH_WAIT 510 | Hdcp Auth Wait 511 | 16 512 | 513 | 514 | HDCP_AUTH_VSYNC_PULSE 515 | Hdcp Auth Vsync Pulse 516 | 32 517 | 518 | 519 | HDCP_AUTH_VSYNC 520 | Hdcp Auth Vsync 521 | 64 522 | 523 | 524 | HDCP_AUTH_VSYNC_WAIT 525 | Hdcp Auth Vsync Wait 526 | 128 527 | 528 | 529 | HDCP_WAIT_1001 530 | Hdcp Wait 1001 531 | 256 532 | 533 | 534 | HDCP_WAIT_1001_END 535 | Hdcp Wait 1001 End 536 | 512 537 | 538 | 539 | HDCP_VSYNC 540 | Hdcp Vsync 541 | 1024 542 | 543 | 544 | HDCP_VSYNC_PULSE 545 | Hdcp Vsync Pulse 546 | 2048 547 | 548 | 549 | HDCP_VSYNC_WAIT 550 | Hdcp Vsync Wait 551 | 4096 552 | 553 | 554 | HDCP_READY 555 | Hdcp Ready 556 | 8192 557 | 558 | 559 | HDCP_REKEY 560 | Hdcp Rekey 561 | 16384 562 | 563 | 564 | HDCP_REKEY_PULSE 565 | Hdcp Rekey Pulse 566 | 32768 567 | 568 | 569 | HDCP_REKEY_WAIT 570 | Hdcp Rekey Wait 571 | 65536 572 | 573 | 574 | HDCP_WAIT_KMRDY 575 | Hdcp Wait Kmrdy 576 | 131072 577 | 578 | 579 | HDCP_nSTATES 580 | Hdcp Nstates 581 | 18 582 | 583 | 584 | Component_Name 585 | hdcp_engine_v1_0 586 | 587 | 588 | 589 | 590 | 591 | artix7 592 | 593 | 594 | /UserIP 595 | 596 | hdcp_engine_v1_1 597 | package_project 598 | Alphamax LLC 599 | http://alphamaxmedia.com 600 | 3 601 | 2016-10-30T15:29:12Z 602 | 603 | F:/largework/fpga/netv2/hdcp_engine/hdcp_engine.srcs/sources_1/imports/srcs-origin 604 | F:/largework/fpga/netv2/hdcp_engine/hdcp_engine.srcs/sources_1/imports/srcs-origin 605 | F:/largework/fpga/netv2/hdcp_engine/hdcp_engine.srcs/sources_1/imports/srcs-origin 606 | F:/largework/fpga/netv2/hdcp_engine/hdcp_engine.srcs/sources_1/imports/srcs-origin 607 | 608 | 609 | 610 | 2016.1 611 | 612 | 613 | 614 | 615 | 616 | 617 | 618 | 619 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/diff_network.v: -------------------------------------------------------------------------------- 1 | /* 2 | This program is free software: you can redistribute it and/or modify 3 | it under the terms of the GNU General Public License as published by 4 | the Free Software Foundation, either version 3 of the License, or 5 | (at your option) any later version. 6 | 7 | This program is distributed in the hope that it will be useful, 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 | GNU General Public License for more details. 11 | 12 | You should have received a copy of the GNU General Public License 13 | along with this program. If not, see . 14 | 15 | 16 | Copyright 2016 Andrew 'bunnie' Huang, all rights reserved 17 | */ 18 | 19 | 20 | module diff_network ( 21 | input wire [6:0] i, 22 | output wire [6:0] o, 23 | input wire [6:0] k 24 | ); 25 | 26 | assign o[0] = k[0] ^ ^ i[1] ^ i[2] ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 27 | assign o[1] = k[1] ^ i[0] ^ ^ i[2] ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 28 | assign o[2] = k[2] ^ i[0] ^ i[1] ^ ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 29 | assign o[3] = k[3] ^ i[0] ^ i[1] ^ i[2] ^ ^ i[4] ^ i[5] ^ i[6]; 30 | assign o[4] = k[4] ^ i[0] ^ i[1] ^ i[2] ^ i[3] ^ ^ i[5] ^ i[6]; 31 | assign o[5] = k[5] ^ i[0] ^ i[1] ^ i[2] ^ i[3] ^ i[4] ^ ^ i[6]; 32 | assign o[6] = k[6] ^ i[0] ^ i[1] ^ i[2] ^ i[3] ^ i[4] ^ i[5] ^ i[6]; 33 | 34 | endmodule // diff_network 35 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_block.v: -------------------------------------------------------------------------------- 1 | /* 2 | This program is free software: you can redistribute it and/or modify 3 | it under the terms of the GNU General Public License as published by 4 | the Free Software Foundation, either version 3 of the License, or 5 | (at your option) any later version. 6 | 7 | This program is distributed in the hope that it will be useful, 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 | GNU General Public License for more details. 11 | 12 | You should have received a copy of the GNU General Public License 13 | along with this program. If not, see . 14 | 15 | 16 | Copyright 2016 Andrew 'bunnie' Huang, all rights reserved 17 | */ 18 | 19 | module hdcp_block ( 20 | input wire clk, 21 | input wire reset, 22 | 23 | input wire load, 24 | input wire [83:0] B, 25 | input wire [83:0] K, 26 | 27 | output wire [83:0] Bo, 28 | input wire rekey, 29 | input wire lfsr_in, 30 | 31 | output reg [23:0] ostream, 32 | 33 | input wire advance 34 | ); 35 | 36 | reg [27:0] Bx; 37 | reg [27:0] By; 38 | reg [27:0] Bz; 39 | wire [27:0] o_Bx; 40 | wire [27:0] o_By; 41 | wire [27:0] o_Bz; 42 | 43 | reg [27:0] Kx; 44 | reg [27:0] Ky; 45 | reg [27:0] Kz; 46 | wire [27:0] o_Kx; 47 | wire [27:0] o_Ky; 48 | wire o_Ky13; // bit 13 comes from lfsr_in when rekey is active 49 | wire [27:0] o_Kz; 50 | 51 | wire [23:0] ostream_r; 52 | 53 | // semi-auto generated with a perl script 54 | wire [3:0] SK0_in; 55 | wire [3:0] SK1_in; 56 | wire [3:0] SK2_in; 57 | wire [3:0] SK3_in; 58 | wire [3:0] SK4_in; 59 | wire [3:0] SK5_in; 60 | wire [3:0] SK6_in; 61 | 62 | reg [3:0] SK0; 63 | reg [3:0] SK1; 64 | reg [3:0] SK2; 65 | reg [3:0] SK3; 66 | reg [3:0] SK4; 67 | reg [3:0] SK5; 68 | reg [3:0] SK6; 69 | 70 | wire [3:0] SB0_in; 71 | wire [3:0] SB1_in; 72 | wire [3:0] SB2_in; 73 | wire [3:0] SB3_in; 74 | wire [3:0] SB4_in; 75 | wire [3:0] SB5_in; 76 | wire [3:0] SB6_in; 77 | 78 | reg [3:0] SB0; 79 | reg [3:0] SB1; 80 | reg [3:0] SB2; 81 | reg [3:0] SB3; 82 | reg [3:0] SB4; 83 | reg [3:0] SB5; 84 | reg [3:0] SB6; 85 | 86 | assign Bo = {Bz[27:0],By[27:0],Bx[27:0]}; 87 | always @(posedge clk) begin 88 | if( reset ) begin 89 | Bx <= 28'b0; 90 | By <= 28'b0; 91 | Bz <= 28'b0; 92 | Kx <= 28'b0; 93 | Ky <= 28'b0; 94 | Kz <= 28'b0; 95 | ostream <= 24'b0; 96 | end else begin 97 | if( load ) begin 98 | // Bz <= B[83:56]; 99 | Bz <= {19'b0,1'b0,B[63:56]}; // repeater is fixed to zero 100 | By <= B[55:28]; 101 | Bx <= B[27:0]; 102 | 103 | Kz <= K[83:56]; 104 | Ky <= K[55:28]; 105 | Kx <= K[27:0]; 106 | ostream <= 24'b0; 107 | end else if( advance ) begin 108 | Bx <= o_Bx; 109 | By <= o_By; 110 | Bz <= o_Bz; 111 | 112 | Kx <= o_Kx; 113 | Ky <= o_Ky; 114 | Kz <= o_Kz; 115 | ostream <= ostream_r; 116 | end else begin 117 | Bx <= Bx; 118 | By <= By; 119 | Bz <= Bz; 120 | 121 | Kx <= Kx; 122 | Ky <= Ky; 123 | Kz <= Kz; 124 | ostream <= ostream; 125 | end 126 | end // else: !if( reset ) 127 | end // always @ (posedge clk or posedge reset) 128 | 129 | 130 | //////////// 131 | // bround linear transformation 132 | // generated using perl script makebround.pl bround.csv > bround_code.txt 133 | //////////// 134 | diff_network bround1 ( .o({o_Bx[24],o_Bx[20],o_Bx[16],o_Bx[12],o_Bx[8],o_Bx[4],o_Bx[0]}), 135 | .k({Ky[6],Ky[5],Ky[4],Ky[3],Ky[2],Ky[1],Ky[0]}), 136 | .i({Bz[6],Bz[5],Bz[4],Bz[3],Bz[2],Bz[1],Bz[0]}) ); 137 | 138 | diff_network bround2 ( .o({o_By[24],o_By[20],o_By[16],o_By[12],o_By[8],o_By[4],o_By[0]}), 139 | .k({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 140 | .i({By[12],By[2],By[1],By[0],Bz[9],Bz[8],Bz[7]}) ); 141 | 142 | diff_network bround3 ( .o({o_By[25],o_By[21],o_By[17],o_By[13],o_By[9],o_By[5],o_By[1]}), 143 | .k({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 144 | .i({By[13],By[5],By[4],By[3],Bz[12],Bz[11],Bz[10]}) ); 145 | 146 | diff_network bround4 ( .o({o_By[26],o_By[22],o_By[18],o_By[14],o_By[10],o_By[6],o_By[2]}), 147 | .k({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 148 | .i({By[14],By[8],By[7],By[6],Bz[15],Bz[14],Bz[13]}) ); 149 | 150 | diff_network bround5 ( .o({o_By[27],o_By[23],o_By[19],o_By[15],o_By[11],o_By[7],o_By[3]}), 151 | .k({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 152 | .i({By[15],By[11],By[10],By[9],Bz[18],Bz[17],Bz[16]}) ); 153 | 154 | diff_network bround6 ( .o({o_Bx[25],o_Bx[21],o_Bx[17],o_Bx[13],o_Bx[9],o_Bx[5],o_Bx[1]}), 155 | .k({Ky[13],Ky[12],Ky[11],Ky[10],Ky[9],Ky[8],Ky[7]}), 156 | .i({Bz[21],Bz[20],Bz[19],By[19],By[18],By[17],By[16]}) ); 157 | 158 | diff_network bround7 ( .o({o_Bx[26],o_Bx[22],o_Bx[18],o_Bx[14],o_Bx[10],o_Bx[6],o_Bx[2]}), 159 | .k({Ky[20],Ky[19],Ky[18],Ky[17],Ky[16],Ky[15],Ky[14]}), 160 | .i({Bz[24],Bz[23],Bz[22],By[23],By[22],By[21],By[20]}) ); 161 | 162 | diff_network bround8 ( .o({o_Bx[27],o_Bx[23],o_Bx[19],o_Bx[15],o_Bx[11],o_Bx[7],o_Bx[3]}), 163 | .k({Ky[27],Ky[26],Ky[25],Ky[24],Ky[23],Ky[22],Ky[21]}), 164 | .i({Bz[27],Bz[26],Bz[25],By[27],By[26],By[25],By[24]}) ); 165 | 166 | 167 | //////////// 168 | // kround linear transform 169 | // generated using perl script makelinx.pl kround.csv > kround 170 | //////////// 171 | 172 | diff_network kround1 ( .o({o_Kx[24],o_Kx[20],o_Kx[16],o_Kx[12],o_Kx[8],o_Kx[4],o_Kx[0]}), 173 | .i({Kz[6],Kz[5],Kz[4],Kz[3],Kz[2],Kz[1],Kz[0]}), 174 | .k(7'b0) ); 175 | 176 | diff_network kround2 ( .o({o_Ky[24],o_Ky[20],o_Ky[16],o_Ky[12],o_Ky[8],o_Ky[4],o_Ky[0]}), 177 | .i({Ky[12],Ky[2],Ky[1],Ky[0],Kz[9],Kz[8],Kz[7]}), 178 | .k(7'b0) ); 179 | 180 | diff_network kround3 ( .o({o_Ky[25],o_Ky[21],o_Ky[17],o_Ky13,o_Ky[9],o_Ky[5],o_Ky[1]}), 181 | .i({Ky[13],Ky[5],Ky[4],Ky[3],Kz[12],Kz[11],Kz[10]}), 182 | .k(7'b0) ); 183 | assign o_Ky[13] = rekey ? lfsr_in : o_Ky13; 184 | 185 | diff_network kround4 ( .o({o_Ky[26],o_Ky[22],o_Ky[18],o_Ky[14],o_Ky[10],o_Ky[6],o_Ky[2]}), 186 | .i({Ky[14],Ky[8],Ky[7],Ky[6],Kz[15],Kz[14],Kz[13]}), 187 | .k(7'b0) ); 188 | 189 | diff_network kround5 ( .o({o_Ky[27],o_Ky[23],o_Ky[19],o_Ky[15],o_Ky[11],o_Ky[7],o_Ky[3]}), 190 | .i({Ky[15],Ky[11],Ky[10],Ky[9],Kz[18],Kz[17],Kz[16]}), 191 | .k(7'b0) ); 192 | 193 | diff_network kround6 ( .o({o_Kx[25],o_Kx[21],o_Kx[17],o_Kx[13],o_Kx[9],o_Kx[5],o_Kx[1]}), 194 | .i({Kz[21],Kz[20],Kz[19],Ky[19],Ky[18],Ky[17],Ky[16]}), 195 | .k(7'b0) ); 196 | 197 | diff_network kround7 ( .o({o_Kx[26],o_Kx[22],o_Kx[18],o_Kx[14],o_Kx[10],o_Kx[6],o_Kx[2]}), 198 | .i({Kz[24],Kz[23],Kz[22],Ky[23],Ky[22],Ky[21],Ky[20]}), 199 | .k(7'b0) ); 200 | 201 | diff_network kround8 ( .o({o_Kx[27],o_Kx[23],o_Kx[19],o_Kx[15],o_Kx[11],o_Kx[7],o_Kx[3]}), 202 | .i({Kz[27],Kz[26],Kz[25],Ky[27],Ky[26],Ky[25],Ky[24]}), 203 | .k(7'b0) ); 204 | 205 | ///////////// 206 | // sboxes 207 | // generated using script makeblock.pl sbox_src.txt > sbox_code.txt 208 | ///////////// 209 | always @(SK0_in[3:0]) begin 210 | case (SK0_in[3:0]) 211 | 4'h0: SK0 = 4'd8; 212 | 4'h1: SK0 = 4'd14; 213 | 4'h2: SK0 = 4'd5; 214 | 4'h3: SK0 = 4'd9; 215 | 4'h4: SK0 = 4'd3; 216 | 4'h5: SK0 = 4'd0; 217 | 4'h6: SK0 = 4'd12; 218 | 4'h7: SK0 = 4'd6; 219 | 4'h8: SK0 = 4'd1; 220 | 4'h9: SK0 = 4'd11; 221 | 4'hA: SK0 = 4'd15; 222 | 4'hB: SK0 = 4'd2; 223 | 4'hC: SK0 = 4'd4; 224 | 4'hD: SK0 = 4'd7; 225 | 4'hE: SK0 = 4'd10; 226 | 4'hF: SK0 = 4'd13; 227 | endcase // case (SK0_in[3:0]) 228 | end // always @ (SK0_in[3:0]) 229 | 230 | always @(SK0_in[3:0]) begin 231 | case (SK0_in[3:0]) 232 | 4'h0: SK0 = 4'd8; 233 | 4'h1: SK0 = 4'd14; 234 | 4'h2: SK0 = 4'd5; 235 | 4'h3: SK0 = 4'd9; 236 | 4'h4: SK0 = 4'd3; 237 | 4'h5: SK0 = 4'd0; 238 | 4'h6: SK0 = 4'd12; 239 | 4'h7: SK0 = 4'd6; 240 | 4'h8: SK0 = 4'd1; 241 | 4'h9: SK0 = 4'd11; 242 | 4'hA: SK0 = 4'd15; 243 | 4'hB: SK0 = 4'd2; 244 | 4'hC: SK0 = 4'd4; 245 | 4'hD: SK0 = 4'd7; 246 | 4'hE: SK0 = 4'd10; 247 | 4'hF: SK0 = 4'd13; 248 | endcase // case (SK0_in[3:0]) 249 | end // always @ (SK0_in[3:0]) 250 | 251 | always @(SK1_in[3:0]) begin 252 | case (SK1_in[3:0]) 253 | 4'h0: SK1 = 4'd1; 254 | 4'h1: SK1 = 4'd6; 255 | 4'h2: SK1 = 4'd4; 256 | 4'h3: SK1 = 4'd15; 257 | 4'h4: SK1 = 4'd8; 258 | 4'h5: SK1 = 4'd3; 259 | 4'h6: SK1 = 4'd11; 260 | 4'h7: SK1 = 4'd5; 261 | 4'h8: SK1 = 4'd10; 262 | 4'h9: SK1 = 4'd0; 263 | 4'hA: SK1 = 4'd9; 264 | 4'hB: SK1 = 4'd12; 265 | 4'hC: SK1 = 4'd7; 266 | 4'hD: SK1 = 4'd13; 267 | 4'hE: SK1 = 4'd14; 268 | 4'hF: SK1 = 4'd2; 269 | endcase // case (SK1_in[3:0]) 270 | end // always @ (SK1_in[3:0]) 271 | 272 | always @(SK2_in[3:0]) begin 273 | case (SK2_in[3:0]) 274 | 4'h0: SK2 = 4'd13; 275 | 4'h1: SK2 = 4'd11; 276 | 4'h2: SK2 = 4'd8; 277 | 4'h3: SK2 = 4'd6; 278 | 4'h4: SK2 = 4'd7; 279 | 4'h5: SK2 = 4'd4; 280 | 4'h6: SK2 = 4'd2; 281 | 4'h7: SK2 = 4'd15; 282 | 4'h8: SK2 = 4'd1; 283 | 4'h9: SK2 = 4'd12; 284 | 4'hA: SK2 = 4'd14; 285 | 4'hB: SK2 = 4'd0; 286 | 4'hC: SK2 = 4'd10; 287 | 4'hD: SK2 = 4'd3; 288 | 4'hE: SK2 = 4'd9; 289 | 4'hF: SK2 = 4'd5; 290 | endcase // case (SK2_in[3:0]) 291 | end // always @ (SK2_in[3:0]) 292 | 293 | always @(SK3_in[3:0]) begin 294 | case (SK3_in[3:0]) 295 | 4'h0: SK3 = 4'd0; 296 | 4'h1: SK3 = 4'd14; 297 | 4'h2: SK3 = 4'd11; 298 | 4'h3: SK3 = 4'd7; 299 | 4'h4: SK3 = 4'd12; 300 | 4'h5: SK3 = 4'd3; 301 | 4'h6: SK3 = 4'd2; 302 | 4'h7: SK3 = 4'd13; 303 | 4'h8: SK3 = 4'd15; 304 | 4'h9: SK3 = 4'd4; 305 | 4'hA: SK3 = 4'd8; 306 | 4'hB: SK3 = 4'd1; 307 | 4'hC: SK3 = 4'd9; 308 | 4'hD: SK3 = 4'd10; 309 | 4'hE: SK3 = 4'd5; 310 | 4'hF: SK3 = 4'd6; 311 | endcase // case (SK3_in[3:0]) 312 | end // always @ (SK3_in[3:0]) 313 | 314 | always @(SK4_in[3:0]) begin 315 | case (SK4_in[3:0]) 316 | 4'h0: SK4 = 4'd12; 317 | 4'h1: SK4 = 4'd7; 318 | 4'h2: SK4 = 4'd15; 319 | 4'h3: SK4 = 4'd8; 320 | 4'h4: SK4 = 4'd11; 321 | 4'h5: SK4 = 4'd14; 322 | 4'h6: SK4 = 4'd1; 323 | 4'h7: SK4 = 4'd4; 324 | 4'h8: SK4 = 4'd6; 325 | 4'h9: SK4 = 4'd10; 326 | 4'hA: SK4 = 4'd3; 327 | 4'hB: SK4 = 4'd5; 328 | 4'hC: SK4 = 4'd0; 329 | 4'hD: SK4 = 4'd9; 330 | 4'hE: SK4 = 4'd13; 331 | 4'hF: SK4 = 4'd2; 332 | endcase // case (SK4_in[3:0]) 333 | end // always @ (SK4_in[3:0]) 334 | 335 | always @(SK5_in[3:0]) begin 336 | case (SK5_in[3:0]) 337 | 4'h0: SK5 = 4'd1; 338 | 4'h1: SK5 = 4'd12; 339 | 4'h2: SK5 = 4'd7; 340 | 4'h3: SK5 = 4'd2; 341 | 4'h4: SK5 = 4'd8; 342 | 4'h5: SK5 = 4'd3; 343 | 4'h6: SK5 = 4'd4; 344 | 4'h7: SK5 = 4'd14; 345 | 4'h8: SK5 = 4'd11; 346 | 4'h9: SK5 = 4'd5; 347 | 4'hA: SK5 = 4'd0; 348 | 4'hB: SK5 = 4'd15; 349 | 4'hC: SK5 = 4'd13; 350 | 4'hD: SK5 = 4'd6; 351 | 4'hE: SK5 = 4'd10; 352 | 4'hF: SK5 = 4'd9; 353 | endcase // case (SK5_in[3:0]) 354 | end // always @ (SK5_in[3:0]) 355 | 356 | always @(SK6_in[3:0]) begin 357 | case (SK6_in[3:0]) 358 | 4'h0: SK6 = 4'd10; 359 | 4'h1: SK6 = 4'd7; 360 | 4'h2: SK6 = 4'd6; 361 | 4'h3: SK6 = 4'd1; 362 | 4'h4: SK6 = 4'd0; 363 | 4'h5: SK6 = 4'd14; 364 | 4'h6: SK6 = 4'd3; 365 | 4'h7: SK6 = 4'd13; 366 | 4'h8: SK6 = 4'd12; 367 | 4'h9: SK6 = 4'd9; 368 | 4'hA: SK6 = 4'd11; 369 | 4'hB: SK6 = 4'd2; 370 | 4'hC: SK6 = 4'd15; 371 | 4'hD: SK6 = 4'd5; 372 | 4'hE: SK6 = 4'd4; 373 | 4'hF: SK6 = 4'd8; 374 | endcase // case (SK6_in[3:0]) 375 | end // always @ (SK6_in[3:0]) 376 | 377 | always @(SB0_in[3:0]) begin 378 | case (SB0_in[3:0]) 379 | 4'h0: SB0 = 4'd12; 380 | 4'h1: SB0 = 4'd9; 381 | 4'h2: SB0 = 4'd3; 382 | 4'h3: SB0 = 4'd0; 383 | 4'h4: SB0 = 4'd11; 384 | 4'h5: SB0 = 4'd5; 385 | 4'h6: SB0 = 4'd13; 386 | 4'h7: SB0 = 4'd6; 387 | 4'h8: SB0 = 4'd2; 388 | 4'h9: SB0 = 4'd4; 389 | 4'hA: SB0 = 4'd14; 390 | 4'hB: SB0 = 4'd7; 391 | 4'hC: SB0 = 4'd8; 392 | 4'hD: SB0 = 4'd15; 393 | 4'hE: SB0 = 4'd1; 394 | 4'hF: SB0 = 4'd10; 395 | endcase // case (SB0_in[3:0]) 396 | end // always @ (SB0_in[3:0]) 397 | 398 | always @(SB1_in[3:0]) begin 399 | case (SB1_in[3:0]) 400 | 4'h0: SB1 = 4'd3; 401 | 4'h1: SB1 = 4'd8; 402 | 4'h2: SB1 = 4'd14; 403 | 4'h3: SB1 = 4'd1; 404 | 4'h4: SB1 = 4'd5; 405 | 4'h5: SB1 = 4'd2; 406 | 4'h6: SB1 = 4'd11; 407 | 4'h7: SB1 = 4'd13; 408 | 4'h8: SB1 = 4'd10; 409 | 4'h9: SB1 = 4'd4; 410 | 4'hA: SB1 = 4'd9; 411 | 4'hB: SB1 = 4'd7; 412 | 4'hC: SB1 = 4'd6; 413 | 4'hD: SB1 = 4'd15; 414 | 4'hE: SB1 = 4'd12; 415 | 4'hF: SB1 = 4'd0; 416 | endcase // case (SB1_in[3:0]) 417 | end // always @ (SB1_in[3:0]) 418 | 419 | always @(SB2_in[3:0]) begin 420 | case (SB2_in[3:0]) 421 | 4'h0: SB2 = 4'd7; 422 | 4'h1: SB2 = 4'd4; 423 | 4'h2: SB2 = 4'd1; 424 | 4'h3: SB2 = 4'd10; 425 | 4'h4: SB2 = 4'd11; 426 | 4'h5: SB2 = 4'd13; 427 | 4'h6: SB2 = 4'd14; 428 | 4'h7: SB2 = 4'd3; 429 | 4'h8: SB2 = 4'd12; 430 | 4'h9: SB2 = 4'd15; 431 | 4'hA: SB2 = 4'd6; 432 | 4'hB: SB2 = 4'd0; 433 | 4'hC: SB2 = 4'd2; 434 | 4'hD: SB2 = 4'd8; 435 | 4'hE: SB2 = 4'd9; 436 | 4'hF: SB2 = 4'd5; 437 | endcase // case (SB2_in[3:0]) 438 | end // always @ (SB2_in[3:0]) 439 | 440 | always @(SB3_in[3:0]) begin 441 | case (SB3_in[3:0]) 442 | 4'h0: SB3 = 4'd6; 443 | 4'h1: SB3 = 4'd3; 444 | 4'h2: SB3 = 4'd1; 445 | 4'h3: SB3 = 4'd4; 446 | 4'h4: SB3 = 4'd10; 447 | 4'h5: SB3 = 4'd12; 448 | 4'h6: SB3 = 4'd15; 449 | 4'h7: SB3 = 4'd2; 450 | 4'h8: SB3 = 4'd5; 451 | 4'h9: SB3 = 4'd14; 452 | 4'hA: SB3 = 4'd11; 453 | 4'hB: SB3 = 4'd8; 454 | 4'hC: SB3 = 4'd9; 455 | 4'hD: SB3 = 4'd7; 456 | 4'hE: SB3 = 4'd0; 457 | 4'hF: SB3 = 4'd13; 458 | endcase // case (SB3_in[3:0]) 459 | end // always @ (SB3_in[3:0]) 460 | 461 | always @(SB4_in[3:0]) begin 462 | case (SB4_in[3:0]) 463 | 4'h0: SB4 = 4'd3; 464 | 4'h1: SB4 = 4'd6; 465 | 4'h2: SB4 = 4'd15; 466 | 4'h3: SB4 = 4'd12; 467 | 4'h4: SB4 = 4'd4; 468 | 4'h5: SB4 = 4'd1; 469 | 4'h6: SB4 = 4'd9; 470 | 4'h7: SB4 = 4'd2; 471 | 4'h8: SB4 = 4'd5; 472 | 4'h9: SB4 = 4'd8; 473 | 4'hA: SB4 = 4'd10; 474 | 4'hB: SB4 = 4'd7; 475 | 4'hC: SB4 = 4'd11; 476 | 4'hD: SB4 = 4'd13; 477 | 4'hE: SB4 = 4'd0; 478 | 4'hF: SB4 = 4'd14; 479 | endcase // case (SB4_in[3:0]) 480 | end // always @ (SB4_in[3:0]) 481 | 482 | always @(SB5_in[3:0]) begin 483 | case (SB5_in[3:0]) 484 | 4'h0: SB5 = 4'd11; 485 | 4'h1: SB5 = 4'd14; 486 | 4'h2: SB5 = 4'd6; 487 | 4'h3: SB5 = 4'd8; 488 | 4'h4: SB5 = 4'd5; 489 | 4'h5: SB5 = 4'd2; 490 | 4'h6: SB5 = 4'd12; 491 | 4'h7: SB5 = 4'd7; 492 | 4'h8: SB5 = 4'd1; 493 | 4'h9: SB5 = 4'd4; 494 | 4'hA: SB5 = 4'd15; 495 | 4'hB: SB5 = 4'd3; 496 | 4'hC: SB5 = 4'd10; 497 | 4'hD: SB5 = 4'd13; 498 | 4'hE: SB5 = 4'd9; 499 | 4'hF: SB5 = 4'd0; 500 | endcase // case (SB5_in[3:0]) 501 | end // always @ (SB5_in[3:0]) 502 | 503 | always @(SB6_in[3:0]) begin 504 | case (SB6_in[3:0]) 505 | 4'h0: SB6 = 4'd1; 506 | 4'h1: SB6 = 4'd11; 507 | 4'h2: SB6 = 4'd7; 508 | 4'h3: SB6 = 4'd4; 509 | 4'h4: SB6 = 4'd2; 510 | 4'h5: SB6 = 4'd5; 511 | 4'h6: SB6 = 4'd12; 512 | 4'h7: SB6 = 4'd9; 513 | 4'h8: SB6 = 4'd13; 514 | 4'h9: SB6 = 4'd6; 515 | 4'hA: SB6 = 4'd8; 516 | 4'hB: SB6 = 4'd15; 517 | 4'hC: SB6 = 4'd14; 518 | 4'hD: SB6 = 4'd0; 519 | 4'hE: SB6 = 4'd3; 520 | 4'hF: SB6 = 4'd10; 521 | endcase // case (SB6_in[3:0]) 522 | end // always @ (SB6_in[3:0]) 523 | 524 | ////// 525 | /// Sbox wiring 526 | /// generated by perl script ./make_sboxwires.pl 527 | ////// 528 | assign SB0_in[0] = Bx[0]; 529 | assign SB0_in[1] = Bx[7]; 530 | assign SB0_in[2] = Bx[14]; 531 | assign SB0_in[3] = Bx[21]; 532 | 533 | assign SK0_in[0] = Kx[0]; 534 | assign SK0_in[1] = Kx[7]; 535 | assign SK0_in[2] = Kx[14]; 536 | assign SK0_in[3] = Kx[21]; 537 | 538 | assign o_Bz[0] = SB0[0]; 539 | assign o_Bz[7] = SB0[1]; 540 | assign o_Bz[14] = SB0[2]; 541 | assign o_Bz[21] = SB0[3]; 542 | 543 | assign o_Kz[0] = SK0[0]; 544 | assign o_Kz[7] = SK0[1]; 545 | assign o_Kz[14] = SK0[2]; 546 | assign o_Kz[21] = SK0[3]; 547 | 548 | assign SB1_in[0] = Bx[1]; 549 | assign SB1_in[1] = Bx[8]; 550 | assign SB1_in[2] = Bx[15]; 551 | assign SB1_in[3] = Bx[22]; 552 | 553 | assign SK1_in[0] = Kx[1]; 554 | assign SK1_in[1] = Kx[8]; 555 | assign SK1_in[2] = Kx[15]; 556 | assign SK1_in[3] = Kx[22]; 557 | 558 | assign o_Bz[1] = SB1[0]; 559 | assign o_Bz[8] = SB1[1]; 560 | assign o_Bz[15] = SB1[2]; 561 | assign o_Bz[22] = SB1[3]; 562 | 563 | assign o_Kz[1] = SK1[0]; 564 | assign o_Kz[8] = SK1[1]; 565 | assign o_Kz[15] = SK1[2]; 566 | assign o_Kz[22] = SK1[3]; 567 | 568 | assign SB2_in[0] = Bx[2]; 569 | assign SB2_in[1] = Bx[9]; 570 | assign SB2_in[2] = Bx[16]; 571 | assign SB2_in[3] = Bx[23]; 572 | 573 | assign SK2_in[0] = Kx[2]; 574 | assign SK2_in[1] = Kx[9]; 575 | assign SK2_in[2] = Kx[16]; 576 | assign SK2_in[3] = Kx[23]; 577 | 578 | assign o_Bz[2] = SB2[0]; 579 | assign o_Bz[9] = SB2[1]; 580 | assign o_Bz[16] = SB2[2]; 581 | assign o_Bz[23] = SB2[3]; 582 | 583 | assign o_Kz[2] = SK2[0]; 584 | assign o_Kz[9] = SK2[1]; 585 | assign o_Kz[16] = SK2[2]; 586 | assign o_Kz[23] = SK2[3]; 587 | 588 | assign SB3_in[0] = Bx[3]; 589 | assign SB3_in[1] = Bx[10]; 590 | assign SB3_in[2] = Bx[17]; 591 | assign SB3_in[3] = Bx[24]; 592 | 593 | assign SK3_in[0] = Kx[3]; 594 | assign SK3_in[1] = Kx[10]; 595 | assign SK3_in[2] = Kx[17]; 596 | assign SK3_in[3] = Kx[24]; 597 | 598 | assign o_Bz[3] = SB3[0]; 599 | assign o_Bz[10] = SB3[1]; 600 | assign o_Bz[17] = SB3[2]; 601 | assign o_Bz[24] = SB3[3]; 602 | 603 | assign o_Kz[3] = SK3[0]; 604 | assign o_Kz[10] = SK3[1]; 605 | assign o_Kz[17] = SK3[2]; 606 | assign o_Kz[24] = SK3[3]; 607 | 608 | assign SB4_in[0] = Bx[4]; 609 | assign SB4_in[1] = Bx[11]; 610 | assign SB4_in[2] = Bx[18]; 611 | assign SB4_in[3] = Bx[25]; 612 | 613 | assign SK4_in[0] = Kx[4]; 614 | assign SK4_in[1] = Kx[11]; 615 | assign SK4_in[2] = Kx[18]; 616 | assign SK4_in[3] = Kx[25]; 617 | 618 | assign o_Bz[4] = SB4[0]; 619 | assign o_Bz[11] = SB4[1]; 620 | assign o_Bz[18] = SB4[2]; 621 | assign o_Bz[25] = SB4[3]; 622 | 623 | assign o_Kz[4] = SK4[0]; 624 | assign o_Kz[11] = SK4[1]; 625 | assign o_Kz[18] = SK4[2]; 626 | assign o_Kz[25] = SK4[3]; 627 | 628 | assign SB5_in[0] = Bx[5]; 629 | assign SB5_in[1] = Bx[12]; 630 | assign SB5_in[2] = Bx[19]; 631 | assign SB5_in[3] = Bx[26]; 632 | 633 | assign SK5_in[0] = Kx[5]; 634 | assign SK5_in[1] = Kx[12]; 635 | assign SK5_in[2] = Kx[19]; 636 | assign SK5_in[3] = Kx[26]; 637 | 638 | assign o_Bz[5] = SB5[0]; 639 | assign o_Bz[12] = SB5[1]; 640 | assign o_Bz[19] = SB5[2]; 641 | assign o_Bz[26] = SB5[3]; 642 | 643 | assign o_Kz[5] = SK5[0]; 644 | assign o_Kz[12] = SK5[1]; 645 | assign o_Kz[19] = SK5[2]; 646 | assign o_Kz[26] = SK5[3]; 647 | 648 | assign SB6_in[0] = Bx[6]; 649 | assign SB6_in[1] = Bx[13]; 650 | assign SB6_in[2] = Bx[20]; 651 | assign SB6_in[3] = Bx[27]; 652 | 653 | assign SK6_in[0] = Kx[6]; 654 | assign SK6_in[1] = Kx[13]; 655 | assign SK6_in[2] = Kx[20]; 656 | assign SK6_in[3] = Kx[27]; 657 | 658 | assign o_Bz[6] = SB6[0]; 659 | assign o_Bz[13] = SB6[1]; 660 | assign o_Bz[20] = SB6[2]; 661 | assign o_Bz[27] = SB6[3]; 662 | 663 | assign o_Kz[6] = SK6[0]; 664 | assign o_Kz[13] = SK6[1]; 665 | assign o_Kz[20] = SK6[2]; 666 | assign o_Kz[27] = SK6[3]; 667 | 668 | ////// 669 | // output function 670 | // generated by perl script ./makeofunc.pl ofunc.txt > ostream_code.txt 671 | ////// 672 | assign ostream_r[0] = (Bz[17] & Kz[3]) ^ (Bz[26] & Kz[6]) ^ (Bz[22] & Kz[0]) ^ (Bz[27] & Kz[9]) ^ (Bz[21] & Kz[4]) ^ (Bz[18] & Kz[22]) ^ (Bz[2] & Kz[5]) ^ By[5] ^ Ky[10]; 673 | 674 | assign ostream_r[1] = (Bz[5] & Kz[20]) ^ (Bz[20] & Kz[18]) ^ (Bz[15] & Kz[7]) ^ (Bz[24] & Kz[23]) ^ (Bz[2] & Kz[15]) ^ (Bz[25] & Kz[5]) ^ (Bz[0] & Kz[3]) ^ By[16] ^ Ky[25]; 675 | 676 | assign ostream_r[2] = (Bz[22] & Kz[7]) ^ (Bz[5] & Kz[19]) ^ (Bz[14] & Kz[2]) ^ (Bz[16] & Kz[10]) ^ (Bz[25] & Kz[22]) ^ (Bz[17] & Kz[4]) ^ (Bz[20] & Kz[13]) ^ By[11] ^ Ky[21]; 677 | 678 | assign ostream_r[3] = (Bz[19] & Kz[6]) ^ (Bz[3] & Kz[14]) ^ (Bz[15] & Kz[9]) ^ (Bz[11] & Kz[8]) ^ (Bz[21] & Kz[17]) ^ (Bz[16] & Kz[18]) ^ (Bz[27] & Kz[12]) ^ By[1] ^ Ky[24]; 679 | 680 | assign ostream_r[4] = (Bz[19] & Kz[25]) ^ (Bz[6] & Kz[6]) ^ (Bz[17] & Kz[5]) ^ (Bz[18] & Kz[2]) ^ (Bz[22] & Kz[10]) ^ (Bz[7] & Kz[15]) ^ (Bz[9] & Kz[21]) ^ By[12] ^ Ky[8]; 681 | 682 | assign ostream_r[5] = (Bz[3] & Kz[27]) ^ (Bz[7] & Kz[14]) ^ (Bz[4] & Kz[2]) ^ (Bz[8] & Kz[4]) ^ (Bz[16] & Kz[24]) ^ (Bz[6] & Kz[19]) ^ (Bz[5] & Kz[1]) ^ By[17] ^ Ky[12]; 683 | 684 | assign ostream_r[6] = (Bz[8] & Kz[17]) ^ (Bz[21] & Kz[26]) ^ (Bz[27] & Kz[4]) ^ (Bz[2] & Kz[16]) ^ (Bz[11] & Kz[27]) ^ (Bz[24] & Kz[7]) ^ (Bz[12] & Kz[22]) ^ By[3] ^ Ky[11]; 685 | 686 | assign ostream_r[7] = (Bz[9] & Kz[9]) ^ (Bz[5] & Kz[10]) ^ (Bz[7] & Kz[19]) ^ (Bz[4] & Kz[11]) ^ (Bz[8] & Kz[7]) ^ (Bz[13] & Kz[6]) ^ (Bz[3] & Kz[8]) ^ By[15] ^ Ky[23]; 687 | 688 | assign ostream_r[8] = (Bz[26] & Kz[13]) ^ (Bz[13] & Kz[12]) ^ (Bz[23] & Kz[18]) ^ (Bz[10] & Kz[24]) ^ (Bz[11] & Kz[15]) ^ (Bz[7] & Kz[23]) ^ (Bz[15] & Kz[7]) ^ By[19] ^ Ky[16]; 689 | 690 | assign ostream_r[9] = (Bz[1] & Kz[0]) ^ (Bz[0] & Kz[5]) ^ (Bz[19] & Kz[20]) ^ (Bz[11] & Kz[25]) ^ (Bz[13] & Kz[1]) ^ (Bz[16] & Kz[24]) ^ (Bz[24] & Kz[9]) ^ By[18] ^ Ky[27]; 691 | 692 | assign ostream_r[10] = (Bz[26] & Kz[14]) ^ (Bz[13] & Kz[23]) ^ (Bz[9] & Kz[27]) ^ (Bz[14] & Kz[25]) ^ (Bz[10] & Kz[17]) ^ (Bz[4] & Kz[19]) ^ (Bz[1] & Kz[1]) ^ By[2] ^ Ky[22]; 693 | 694 | assign ostream_r[11] = (Bz[21] & Kz[6]) ^ (Bz[15] & Kz[21]) ^ (Bz[5] & Kz[17]) ^ (Bz[3] & Kz[15]) ^ (Bz[13] & Kz[26]) ^ (Bz[25] & Kz[11]) ^ (Bz[16] & Kz[16]) ^ By[27] ^ Ky[7]; 695 | 696 | assign ostream_r[12] = (Bz[20] & Kz[11]) ^ (Bz[7] & Kz[22]) ^ (Bz[18] & Kz[20]) ^ (Bz[12] & Kz[0]) ^ (Bz[17] & Kz[26]) ^ (Bz[1] & Kz[23]) ^ (Bz[16] & Kz[17]) ^ By[0] ^ Ky[2]; 697 | 698 | assign ostream_r[13] = (Bz[14] & Kz[8]) ^ (Bz[23] & Kz[4]) ^ (Bz[1] & Kz[3]) ^ (Bz[12] & Kz[14]) ^ (Bz[24] & Kz[20]) ^ (Bz[6] & Kz[26]) ^ (Bz[18] & Kz[23]) ^ By[9] ^ Ky[15]; 699 | 700 | assign ostream_r[14] = (Bz[19] & Kz[19]) ^ (Bz[6] & Kz[0]) ^ (Bz[21] & Kz[18]) ^ (Bz[25] & Kz[2]) ^ (Bz[23] & Kz[13]) ^ (Bz[1] & Kz[8]) ^ (Bz[10] & Kz[24]) ^ By[8] ^ Ky[14]; 701 | 702 | assign ostream_r[15] = (Bz[3] & Kz[16]) ^ (Bz[0] & Kz[21]) ^ (Bz[27] & Kz[24]) ^ (Bz[23] & Kz[25]) ^ (Bz[19] & Kz[12]) ^ (Bz[8] & Kz[27]) ^ (Bz[4] & Kz[15]) ^ By[7] ^ Ky[18]; 703 | 704 | assign ostream_r[16] = (Bz[6] & Kz[3]) ^ (Bz[5] & Kz[5]) ^ (Bz[14] & Kz[8]) ^ (Bz[22] & Kz[25]) ^ (Bz[24] & Kz[7]) ^ (Bz[18] & Kz[27]) ^ (Bz[2] & Kz[2]) ^ By[21] ^ Ky[26]; 705 | 706 | assign ostream_r[17] = (Bz[3] & Kz[11]) ^ (Bz[4] & Kz[14]) ^ (Bz[2] & Kz[23]) ^ (Bz[6] & Kz[17]) ^ (Bz[22] & Kz[22]) ^ (Bz[14] & Kz[13]) ^ (Bz[12] & Kz[19]) ^ By[26] ^ Ky[4]; 707 | 708 | assign ostream_r[18] = (Bz[25] & Kz[1]) ^ (Bz[21] & Kz[16]) ^ (Bz[19] & Kz[14]) ^ (Bz[9] & Kz[11]) ^ (Bz[10] & Kz[12]) ^ (Bz[15] & Kz[6]) ^ (Bz[13] & Kz[10]) ^ By[22] ^ Ky[19]; 709 | 710 | assign ostream_r[19] = (Bz[23] & Kz[21]) ^ (Bz[11] & Kz[1]) ^ (Bz[10] & Kz[10]) ^ (Bz[20] & Kz[20]) ^ (Bz[1] & Kz[18]) ^ (Bz[12] & Kz[26]) ^ (Bz[14] & Kz[9]) ^ By[4] ^ Ky[13]; 711 | 712 | assign ostream_r[20] = (Bz[11] & Kz[20]) ^ (Bz[26] & Kz[21]) ^ (Bz[20] & Kz[9]) ^ (Bz[17] & Kz[25]) ^ (Bz[8] & Kz[12]) ^ (Bz[23] & Kz[3]) ^ (Bz[0] & Kz[15]) ^ By[24] ^ Ky[0]; 713 | 714 | assign ostream_r[21] = (Bz[9] & Kz[18]) ^ (Bz[17] & Kz[12]) ^ (Bz[26] & Kz[21]) ^ (Bz[4] & Kz[27]) ^ (Bz[27] & Kz[1]) ^ (Bz[0] & Kz[16]) ^ (Bz[15] & Kz[24]) ^ By[6] ^ Ky[20]; 715 | 716 | assign ostream_r[22] = (Bz[22] & Kz[13]) ^ (Bz[12] & Kz[0]) ^ (Bz[2] & Kz[3]) ^ (Bz[10] & Kz[16]) ^ (Bz[7] & Kz[22]) ^ (Bz[20] & Kz[11]) ^ (Bz[25] & Kz[26]) ^ By[13] ^ Ky[9]; 717 | 718 | assign ostream_r[23] = (Bz[27] & Kz[2]) ^ (Bz[24] & Kz[0]) ^ (Bz[26] & Kz[13]) ^ (Bz[8] & Kz[5]) ^ (Bz[0] & Kz[4]) ^ (Bz[9] & Kz[8]) ^ (Bz[18] & Kz[10]) ^ By[23] ^ Ky[3]; 719 | 720 | endmodule // hdcp_block 721 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_cipher.v: -------------------------------------------------------------------------------- 1 | /* 2 | This program is free software: you can redistribute it and/or modify 3 | it under the terms of the GNU General Public License as published by 4 | the Free Software Foundation, either version 3 of the License, or 5 | (at your option) any later version. 6 | 7 | This program is distributed in the hope that it will be useful, 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 | GNU General Public License for more details. 11 | 12 | You should have received a copy of the GNU General Public License 13 | along with this program. If not, see . 14 | 15 | 16 | Copyright 2016 Andrew 'bunnie' Huang, all rights reserved 17 | */ 18 | 19 | 20 | `timescale 1 ns / 1 ps 21 | 22 | // generates a stream of hdcp cipher data 23 | module hdcp_cipher( 24 | input wire clk, 25 | input reset, 26 | 27 | input [55:0] Km, // shared secret value 28 | input [63:0] An, // session random number 29 | 30 | input hdcpBlockCipher_init, // pulsed only one cycle 31 | input authentication, // pulsed one cycle same time as above 32 | input hdcpRekeyCipher, // pulsed one cycle to initiate rekey 33 | input hdcpStreamCipher,// advance cipher state one clock 34 | output [23:0] pr_data, // pseudorandom data output 35 | output reg stream_ready // asserted when stream is ready (after init seq) 36 | ); 37 | 38 | wire lfsr_out; 39 | wire [23:0] ostream; 40 | wire [83:0] Bo_wire; 41 | 42 | parameter INIT = 12'b1 << 0; 43 | parameter BLOCK_1 = 12'b1 << 1; 44 | parameter BLOCK_2 = 12'b1 << 2; 45 | parameter BLOCK_3 = 12'b1 << 3; 46 | parameter BLOCK_4 = 12'b1 << 4; 47 | parameter BLOCK_5 = 12'b1 << 5; 48 | parameter BLOCK_6 = 12'b1 << 6; 49 | parameter BLOCK_7 = 12'b1 << 7; 50 | parameter BLOCK_8 = 12'b1 << 8; 51 | parameter BLOCK_9 = 12'b1 << 9; 52 | parameter GET_M = 12'b1 << 10; 53 | parameter STREAM = 12'b1 << 11; 54 | parameter REKEY = 12'b1 << 12; 55 | parameter nSTATES = 13; 56 | 57 | reg [(nSTATES-1):0] cstate = {{(nSTATES-1){1'b0}},1'b1}; 58 | reg [(nSTATES-1):0] nstate; 59 | 60 | // `define SIMULATION 1 61 | `ifdef SIMULATION 62 | // synthesis translate_off 63 | reg [8*20:1] state_ascii = "INIT "; 64 | always @(cstate) begin 65 | if (cstate == INIT ) state_ascii <= "INIT "; 66 | else if (cstate == BLOCK_1 ) state_ascii <= "BLOCK_1 "; 67 | else if (cstate == BLOCK_2 ) state_ascii <= "BLOCK_2 "; 68 | else if (cstate == BLOCK_3 ) state_ascii <= "BLOCK_3 "; 69 | else if (cstate == BLOCK_4 ) state_ascii <= "BLOCK_4 "; 70 | else if (cstate == BLOCK_5 ) state_ascii <= "BLOCK_5 "; 71 | else if (cstate == BLOCK_6 ) state_ascii <= "BLOCK_6 "; 72 | else if (cstate == BLOCK_7 ) state_ascii <= "BLOCK_7 "; 73 | else if (cstate == BLOCK_8 ) state_ascii <= "BLOCK_8 "; 74 | else if (cstate == BLOCK_9 ) state_ascii <= "BLOCK_9 "; 75 | else if (cstate == GET_M ) state_ascii <= "GET_M "; 76 | else if (cstate == STREAM ) state_ascii <= "STREAM "; 77 | else if (cstate == REKEY ) state_ascii <= "REKEY "; 78 | else state_ascii <= "WTF "; 79 | end 80 | // synthesis translate_on 81 | `endif // `ifdef SIMULATION 82 | 83 | reg [5:0] statecnt; 84 | reg rekey; 85 | reg load_block; 86 | reg load_56; // load 56 or 80 bits... 87 | reg load_lfsr; 88 | reg advance_lfsr; 89 | reg advance_block; 90 | reg [83:0] Ks; 91 | reg [83:0] Ki; 92 | reg [63:0] Mi; 93 | reg load_ks; 94 | reg auth_mode; 95 | reg [83:0] Kmod; 96 | 97 | always @ (posedge clk) begin 98 | if (reset) 99 | cstate <= INIT; 100 | else 101 | cstate <=#1 nstate; 102 | end 103 | 104 | hdcp_lfsr lfsr( .clk(clk), .reset(reset), 105 | .iv(auth_mode ? Ks[55:0] : Ki[55:0]), 106 | .init_iv(load_lfsr), 107 | .advance(advance_lfsr), 108 | .onebit(lfsr_out)); 109 | 110 | hdcp_block block( .clk(clk), .reset(reset), 111 | 112 | .load(load_block), 113 | .B(auth_mode ? {20'b0,An} : {20'b0,Mi}), 114 | .K(Kmod), 115 | .Bo(Bo_wire), 116 | .rekey(rekey), 117 | .lfsr_in(lfsr_out), 118 | .ostream(ostream), 119 | .advance(advance_block)); 120 | assign pr_data = ostream; 121 | 122 | always @ (*) begin 123 | case ({auth_mode,load_56}) //synthesis parallel_case full_case 124 | 2'b00: begin // not auth mode, load 84 bits 125 | Kmod = Ki; 126 | end 127 | 2'b01: begin // not auth mode, but load 56 bits only 128 | Kmod = {28'b0,Ks[55:0]}; 129 | end 130 | 2'b10: begin // auth mode, load 84 bits 131 | Kmod = Ks; 132 | end 133 | 2'b11: begin // auth mode, load only 56 bits 134 | Kmod = {28'b0,Km[55:0]}; 135 | end 136 | endcase // case ({auth_mode,load_56}) 137 | end // always @ (*) 138 | 139 | 140 | always @ (*) begin 141 | case (cstate) //synthesis parallel_case full_case 142 | INIT: begin 143 | nstate = hdcpBlockCipher_init ? BLOCK_1 : INIT; 144 | end 145 | BLOCK_1: begin 146 | nstate = BLOCK_2; 147 | end 148 | BLOCK_2: begin 149 | nstate = (statecnt >= 6'd47) ? BLOCK_3: BLOCK_2; 150 | end 151 | BLOCK_3: begin 152 | nstate = BLOCK_4; 153 | end 154 | BLOCK_4: begin 155 | nstate = BLOCK_5; 156 | end 157 | BLOCK_5: begin 158 | nstate = BLOCK_6; 159 | end 160 | BLOCK_6: begin 161 | nstate = BLOCK_7; 162 | end 163 | BLOCK_7: begin 164 | nstate = BLOCK_8; 165 | end 166 | BLOCK_8: begin 167 | nstate = (statecnt >= 6'd55) ? BLOCK_9: BLOCK_8; 168 | end 169 | BLOCK_9: begin 170 | nstate = GET_M; 171 | end 172 | GET_M: begin 173 | nstate = STREAM; 174 | end 175 | STREAM: begin 176 | if( hdcpBlockCipher_init ) begin 177 | nstate = BLOCK_1; 178 | end else if( hdcpRekeyCipher ) begin 179 | nstate = REKEY; 180 | end else begin 181 | nstate = STREAM; 182 | end 183 | end 184 | REKEY: begin 185 | if( hdcpBlockCipher_init ) begin 186 | nstate = BLOCK_1; 187 | end else begin 188 | nstate = (statecnt >= 6'd55) ? STREAM : REKEY; 189 | end 190 | end 191 | endcase // case (cstate) 192 | end 193 | 194 | always @ (posedge clk) begin 195 | if( reset ) begin 196 | statecnt <=#1 6'b0; 197 | rekey <=#1 1'b0; 198 | load_block <=#1 1'b0; 199 | advance_lfsr <=#1 1'b0; 200 | advance_block <=#1 1'b0; 201 | load_ks <=#1 1'b0; 202 | auth_mode <=#1 1'b0; 203 | stream_ready <=#1 1'b0; 204 | load_56 <=#1 1'b0; 205 | end else begin 206 | case (cstate) // synthesis parallel_case full_case 207 | INIT: begin 208 | statecnt <=#1 6'b0; 209 | rekey <=#1 1'b0; 210 | load_block <=#1 1'b0; 211 | advance_lfsr <=#1 1'b0; 212 | advance_block <=#1 1'b0; 213 | load_ks <=#1 1'b0; 214 | auth_mode <=#1 authentication; 215 | load_lfsr <=#1 1'b0; 216 | stream_ready <=#1 1'b0; 217 | load_56 <=#1 1'b0; 218 | end 219 | BLOCK_1: begin 220 | statecnt <=#1 6'b0; 221 | rekey <=#1 1'b0; 222 | load_block <=#1 1'b1; // load B & K regs of block module 223 | advance_lfsr <=#1 1'b0; 224 | advance_block <=#1 1'b0; 225 | load_ks <=#1 1'b0; 226 | auth_mode <=#1 auth_mode; 227 | load_lfsr <=#1 1'b0; 228 | stream_ready <=#1 1'b0; 229 | load_56 <=#1 1'b1; 230 | end 231 | BLOCK_2: begin 232 | statecnt <=#1 statecnt + 1; // 48 clocks 233 | rekey <=#1 1'b0; 234 | load_block <=#1 1'b0; 235 | advance_lfsr <=#1 1'b0; 236 | advance_block <=#1 1'b1; 237 | load_ks <=#1 1'b0; 238 | auth_mode <=#1 auth_mode; 239 | load_lfsr <=#1 1'b0; 240 | stream_ready <=#1 1'b0; 241 | load_56 <=#1 1'b0; 242 | end 243 | BLOCK_3: begin 244 | statecnt <=#1 0; 245 | rekey <=#1 1'b0; 246 | load_block <=#1 1'b0; 247 | advance_lfsr <=#1 1'b0; 248 | advance_block <=#1 1'b0; 249 | load_ks <=#1 1'b1; // save Ks, Ki, and B=>K 250 | auth_mode <=#1 auth_mode; 251 | load_lfsr <=#1 1'b0; 252 | stream_ready <=#1 1'b0; 253 | load_56 <=#1 1'b0; 254 | end 255 | BLOCK_4: begin 256 | statecnt <=#1 0; 257 | rekey <=#1 1'b0; 258 | load_block <=#1 1'b0; 259 | advance_lfsr <=#1 1'b0; 260 | advance_block <=#1 1'b0; 261 | load_ks <=#1 1'b1; // dup of above 262 | auth_mode <=#1 auth_mode; 263 | load_lfsr <=#1 1'b0; 264 | stream_ready <=#1 1'b0; 265 | load_56 <=#1 1'b0; 266 | end 267 | BLOCK_5: begin 268 | statecnt <=#1 0; 269 | rekey <=#1 1'b0; 270 | load_block <=#1 1'b1; // reload block cipher 271 | advance_lfsr <=#1 1'b0; 272 | advance_block <=#1 1'b0; 273 | load_ks <=#1 1'b0; 274 | auth_mode <=#1 auth_mode; 275 | load_lfsr <=#1 1'b0; 276 | stream_ready <=#1 1'b0; 277 | load_56 <=#1 1'b0; 278 | end 279 | BLOCK_6: begin 280 | statecnt <=#1 0; 281 | rekey <=#1 1'b0; 282 | load_block <=#1 1'b0; 283 | advance_lfsr <=#1 1'b0; 284 | advance_block <=#1 1'b0; 285 | load_ks <=#1 1'b0; 286 | auth_mode <=#1 auth_mode; 287 | load_lfsr <=#1 1'b1; // init lfsr 288 | stream_ready <=#1 1'b0; 289 | load_56 <=#1 1'b0; 290 | end 291 | BLOCK_7: begin 292 | statecnt <=#1 0; 293 | rekey <=#1 1'b1; // assert rekey 294 | load_block <=#1 1'b0; 295 | advance_lfsr <=#1 1'b0; 296 | advance_block <=#1 1'b0; 297 | load_ks <=#1 1'b0; 298 | auth_mode <=#1 auth_mode; 299 | load_lfsr <=#1 1'b0; 300 | stream_ready <=#1 1'b0; 301 | load_56 <=#1 1'b0; 302 | end 303 | BLOCK_8: begin 304 | statecnt <=#1 statecnt + 1; // 56 clocks 305 | rekey <=#1 1'b1; 306 | load_block <=#1 1'b0; 307 | advance_lfsr <=#1 1'b1; 308 | advance_block <=#1 1'b1; 309 | load_ks <=#1 1'b0; 310 | auth_mode <=#1 auth_mode; 311 | load_lfsr <=#1 1'b0; 312 | stream_ready <=#1 1'b0; 313 | load_56 <=#1 1'b0; 314 | end 315 | BLOCK_9: begin 316 | statecnt <=#1 0; 317 | rekey <=#1 1'b0; // de-assert rekey 318 | load_block <=#1 1'b0; 319 | advance_lfsr <=#1 1'b0; 320 | advance_block <=#1 1'b0; 321 | load_ks <=#1 1'b0; 322 | auth_mode <=#1 auth_mode; 323 | load_lfsr <=#1 1'b0; 324 | stream_ready <=#1 1'b0; 325 | load_56 <=#1 1'b0; 326 | end // case: BLOCK_9 327 | GET_M: begin // one cycle wait to get M register loaded properly 328 | statecnt <=#1 0; 329 | rekey <=#1 1'b0; 330 | load_block <=#1 1'b0; 331 | advance_lfsr <=#1 1'b0; 332 | advance_block <=#1 1'b0; 333 | load_ks <=#1 1'b0; 334 | auth_mode <=#1 1'b0; 335 | load_lfsr <=#1 1'b0; 336 | stream_ready <=#1 1'b0; 337 | load_56 <=#1 1'b0; 338 | end 339 | STREAM: begin 340 | statecnt <=#1 0; 341 | rekey <=#1 1'b0; 342 | load_block <=#1 1'b0; 343 | advance_lfsr <=#1 hdcpStreamCipher; 344 | advance_block <=#1 hdcpStreamCipher; 345 | load_ks <=#1 1'b0; 346 | auth_mode <=#1 authentication; 347 | load_lfsr <=#1 1'b0; 348 | stream_ready <=#1 1'b1; 349 | load_56 <=#1 1'b0; 350 | end 351 | REKEY: begin 352 | statecnt <=#1 statecnt + 1; 353 | rekey <=#1 1'b1; 354 | load_block <=#1 1'b0; 355 | advance_lfsr <=#1 1'b1; 356 | advance_block <=#1 1'b1; 357 | load_ks <=#1 1'b0; 358 | auth_mode <=#1 auth_mode; 359 | load_lfsr <=#1 1'b0; 360 | stream_ready <=#1 1'b0; 361 | load_56 <=#1 1'b0; 362 | end 363 | endcase // case (cstate) 364 | end 365 | end // always @ (posedge clk or posedge reset) 366 | 367 | always @(posedge clk) begin 368 | if( reset ) begin 369 | Ks <= 80'b0; 370 | Ki <= 80'b0; 371 | end else begin 372 | // if( hdcpBlockCipher_init ) begin 373 | // Ks <= (authentication | auth_mode) ? {28'b0,Km} : Ks; 374 | // Ki <= 80'b0; 375 | // end else if( load_ks && auth_mode ) begin 376 | if( load_ks && auth_mode ) begin 377 | Ks <= Bo_wire; 378 | Ki <= 80'b0; 379 | end else if( load_ks && !auth_mode ) begin 380 | Ks <= Ks; 381 | Ki <= Bo_wire; 382 | end else begin 383 | Ks <= Ks; 384 | Ki <= Ki; 385 | end 386 | end 387 | end // always @ (posedge clk or posedge reset) 388 | 389 | always @(posedge clk) begin 390 | if( reset ) begin 391 | Mi <= 80'b0; 392 | end else begin 393 | if( (cstate == BLOCK_8) || (cstate == BLOCK_9) || (cstate == GET_M) ) begin 394 | Mi[15:0] <= ostream[15:0]; 395 | Mi[31:16] <= Mi[15:0]; 396 | Mi[47:32] <= Mi[31:16]; 397 | Mi[63:48] <= Mi[47:32]; 398 | end else begin 399 | Mi <= Mi; 400 | end 401 | end // else: !if( reset ) 402 | end // always @ (posedge clk or posedge reset) 403 | 404 | endmodule // hdcp_cipher 405 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_engine.v: -------------------------------------------------------------------------------- 1 | /* 2 | This program is free software: you can redistribute it and/or modify 3 | it under the terms of the GNU General Public License as published by 4 | the Free Software Foundation, either version 3 of the License, or 5 | (at your option) any later version. 6 | 7 | This program is distributed in the hope that it will be useful, 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 | GNU General Public License for more details. 11 | 12 | You should have received a copy of the GNU General Public License 13 | along with this program. If not, see . 14 | 15 | 16 | Copyright 2016 Andrew 'bunnie' Huang, all rights reserved 17 | */ 18 | 19 | module hdcp_engine ( 20 | input wire clk, 21 | input reset, 22 | 23 | // this comes directly from the HPD input 24 | input hpd, 25 | 26 | // these come from the input decoder 27 | input [3:0] ctl_code, 28 | input cv, 29 | input de, 30 | input line_end, 31 | input hsync, 32 | input vsync, 33 | input hdcp_ena, 34 | 35 | // this is computed by the host via fancy linear algebra and session keys 36 | input Km_rdy, 37 | input [55:0] Km, // shared secret value 38 | 39 | // directly from i2c_snoop block watching address 0x74 40 | input An_rdy, 41 | input [63:0] An, // session random number 42 | 43 | // cipher stream output 44 | output [23:0] cipher_stream, 45 | output hdcp_is_ready 46 | ); 47 | 48 | wire Aksv14_write; 49 | assign Aksv14_write = An_rdy; 50 | 51 | reg hpd_n; 52 | always @(posedge clk) begin 53 | // retime and invert HPD 54 | hpd_n <= !hpd; 55 | end 56 | 57 | // autodetect sync polarity 58 | reg hdmi_vsync_pol; 59 | reg hdmi_hsync_pol; 60 | reg vsync_v_raw, hsync_v_raw; 61 | reg hdmi_de_d; 62 | wire hdmi_de_rising; 63 | 64 | assign hdmi_de_rising = !hdmi_de_d & de; 65 | // hdmi sync polarity detector 66 | always @(posedge clk) begin 67 | if(reset) begin 68 | hdmi_vsync_pol <= 0; 69 | hdmi_hsync_pol <= 0; 70 | vsync_v_raw <= 0; 71 | hsync_v_raw <= 0; 72 | end else begin 73 | hdmi_de_d <= de; 74 | 75 | if(cv) begin 76 | vsync_v_raw <= vsync; 77 | hsync_v_raw <= hsync; 78 | end else begin 79 | vsync_v_raw <= vsync_v_raw; 80 | hsync_v_raw <= hsync_v_raw; 81 | end 82 | // the theory goes that de is always active high so use this to adjust sync polarities 83 | if( hdmi_de_rising ) begin 84 | hdmi_vsync_pol <= !vsync_v_raw; 85 | hdmi_hsync_pol <= !hsync_v_raw; 86 | end else begin 87 | hdmi_vsync_pol <= hdmi_vsync_pol; 88 | hdmi_hsync_pol <= hdmi_hsync_pol; 89 | end 90 | end 91 | end // always @ (posedge clk) 92 | 93 | reg vsync_v; 94 | reg hsync_v; 95 | reg hsync_v2; 96 | reg vsync_v2; 97 | 98 | always @(posedge clk) begin 99 | if( reset == 1'b1 ) begin 100 | vsync_v <= 0; 101 | hsync_v <= 0; 102 | hsync_v2 <= 0; 103 | vsync_v2 <= 0; 104 | end else begin 105 | hsync_v2 <= hsync_v; 106 | vsync_v2 <= vsync_v; 107 | if(cv) begin 108 | vsync_v <= vsync ^ !hdmi_vsync_pol; 109 | hsync_v <= hsync ^ !hdmi_hsync_pol; 110 | end else begin 111 | vsync_v <= vsync_v; 112 | hsync_v <= hsync_v; 113 | end 114 | end // else: !if( reset == 1'b1 ) 115 | end // always @ (posedge clk) 116 | assign vsync_rising = vsync_v & !vsync_v2; 117 | 118 | /////// 119 | // HDCP 120 | /////// 121 | // HDCP initialization procedure 122 | // 123 | // 1. Sniff An, KSV going across the wire 124 | // 2. Generate private key table for one of the KSV's 125 | // 3. Perform the Km computation using derived private key table 126 | // 4. Enter An, Km into the register for the HDCP cipher 127 | // 5. Initiate the authentication (pulse hdcpBlockCipher_init and 128 | // authentication high one cycle simultaneously) 129 | // 6. Wait until stream_ready is high 130 | // 131 | // Now begins the main loop: 132 | // There is an ambiguity in the spec. Either a rekey operation happens immediately 133 | // (since this happens during vertical retrace), or not. Either way, this is roughly 134 | // what happens. 135 | // 136 | // 1. If hdcp_ena activates (or of de and data island enable), advance cipher 137 | // 2. If vertical sync happens, pulse hdcpBlockCipher_init one cycle and wait 138 | // until stream_ready; return to 1 139 | // 3. If horizontal sync happens, pulse hdcpRekeyCipher once cycle, wait until 140 | // stream_ready; return to 1 141 | // 142 | // That's it. So the only question is if vsync "happens" immediately after an authentication. 143 | // The test vectors would suggest this is the case but I can't find it in the state machine 144 | // diagrams, so perhaps good to try both options...? 145 | parameter HDCP_UNPLUG = 18'b1 << 0; 146 | parameter HDCP_WAIT_AKSV = 18'b1 << 1; 147 | parameter HDCP_AUTH_PULSE = 18'b1 << 2; 148 | parameter HDCP_AUTH = 18'b1 << 3; 149 | parameter HDCP_AUTH_WAIT = 18'b1 << 4; 150 | parameter HDCP_AUTH_VSYNC_PULSE = 18'b1 << 5; 151 | parameter HDCP_AUTH_VSYNC = 18'b1 << 6; 152 | parameter HDCP_AUTH_VSYNC_WAIT = 18'b1 << 7; 153 | parameter HDCP_WAIT_1001 = 18'b1 << 8; 154 | parameter HDCP_WAIT_1001_END = 18'b1 << 9; 155 | parameter HDCP_VSYNC = 18'b1 << 10; 156 | parameter HDCP_VSYNC_PULSE = 18'b1 << 11; 157 | parameter HDCP_VSYNC_WAIT = 18'b1 << 12; 158 | parameter HDCP_READY = 18'b1 << 13; 159 | parameter HDCP_REKEY = 18'b1 << 14; 160 | parameter HDCP_REKEY_PULSE = 18'b1 << 15; 161 | parameter HDCP_REKEY_WAIT = 18'b1 << 16; 162 | parameter HDCP_WAIT_KMRDY = 18'b1 << 17; 163 | 164 | parameter HDCP_nSTATES = 18; 165 | 166 | wire stream_ready; // asserted when stream is ready (after init seq) 167 | reg [(HDCP_nSTATES-1):0] HDCP_cstate = {{(HDCP_nSTATES-1){1'b0}}, 1'b1}; 168 | reg [(HDCP_nSTATES-1):0] HDCP_nstate; 169 | 170 | reg auth_mode; 171 | reg hdcp_init; 172 | reg hdcp_rekey; 173 | wire hdcp_stream_ena; 174 | 175 | reg active_line; 176 | reg hdcp_rekey_2; 177 | reg hdcp_rekey_1; 178 | 179 | reg appleTV2_bug; 180 | 181 | reg Km_rdy0; 182 | reg Km_rdy1; 183 | reg Km_rdy2; 184 | wire Km_ready; 185 | reg hdcp_requested; 186 | 187 | // Apple TV version 2 has a bug where the 1001 EESS happens by far too early in the window of oppty 188 | // spec is a window 512 cycles after vsync start, in practice ATV2 is a window about 94 clocks after vsync 189 | always @ (posedge clk) begin 190 | if( reset == 1'b1 ) begin 191 | appleTV2_bug <= 0; 192 | end else begin 193 | if( (HDCP_cstate == HDCP_VSYNC_WAIT) && (ctl_code[3:0] == 4'b1001) ) begin 194 | appleTV2_bug <= 1; 195 | end else if( (HDCP_cstate == HDCP_READY) ) begin 196 | appleTV2_bug <= 0; 197 | end else begin 198 | appleTV2_bug <= appleTV2_bug; 199 | end 200 | end // else: !if( reset == 1'b1 ) 201 | end // always @ (posedge clk or posedge reset) 202 | 203 | assign hdcp_is_ready = (HDCP_cstate == HDCP_READY); 204 | 205 | // compute active_line. This tells you if the last line had active data 206 | // in it or not. Reset the computation on falling edge of hsync 207 | always @ (posedge clk) begin 208 | if( reset == 1'b1 ) begin 209 | active_line <= 1'b0; 210 | hdcp_rekey_2 <= 1'b0; 211 | hdcp_rekey_1 <= 1'b0; 212 | end else begin 213 | hdcp_rekey_2 <= hdcp_rekey_1; 214 | hdcp_rekey_1 <= hdcp_rekey || 215 | (line_end && (HDCP_cstate == HDCP_READY) && de); 216 | if( de ) begin 217 | active_line <= 1'b1; 218 | end else if( !hsync_v & hsync_v2 ) begin // hsync falling 219 | active_line <= 1'b0; 220 | end 221 | end 222 | end 223 | 224 | always @ (posedge clk) begin 225 | if ( reset | hpd_n ) 226 | HDCP_cstate <= HDCP_UNPLUG; 227 | else 228 | if( Aksv14_write ) begin 229 | HDCP_cstate <= HDCP_AUTH_PULSE; // hack for tivo series 3 230 | end else begin 231 | HDCP_cstate <=#1 HDCP_nstate; 232 | end 233 | end 234 | 235 | always @ (*) begin 236 | case (HDCP_cstate) //synthesis parallel_case full_case 237 | HDCP_UNPLUG: begin 238 | HDCP_nstate = hpd_n ? HDCP_UNPLUG : HDCP_WAIT_AKSV; 239 | end 240 | HDCP_WAIT_AKSV: begin 241 | // wait until the 14th byte is written to the HDCP register set 242 | // this is the MSB of AKsv, and this triggers an authentication event 243 | HDCP_nstate = Aksv14_write ? HDCP_AUTH_PULSE : HDCP_WAIT_AKSV; 244 | // HDCP_nstate = Aksv14_write ? HDCP_WAIT_KMRDY : HDCP_WAIT_AKSV; 245 | // in this implementation, skip the HDCP_WAIT_KMRDY state 246 | end 247 | 248 | // this state is unreachable 249 | HDCP_WAIT_KMRDY: begin 250 | HDCP_nstate = Km_ready ? HDCP_AUTH_PULSE : HDCP_WAIT_KMRDY; 251 | end 252 | 253 | //////// 254 | // maybe put a state here to wait for Km to become ready 255 | // but for now, we assume host has pre-loaded Km. Km is fixed for every Tx/Rx HDMI pair. 256 | // So once you have computed it, it can be pre-loaded even before the transaction happens. 257 | // One way around this is to snag AKsv, Bksv; and if they are a new pair, compute Km 258 | // and load it; and then override hpd_n high for a second to force a re-key *only* if 259 | // this is new pair. Thus, the first time you plug in a new device you *might* see it 260 | // flicker once, but it would never happen again, but I think typically you would 261 | // not notice because the screen would stay dark the entire time. 262 | // 263 | // --> above is the wait KMRDY state. The way this should work now is: 264 | // 1. Aksv is written, byte 14 triggers an interrupt to the CPU. 265 | // 2. CPU derives Km, writes Km, sets Km ready 266 | // 3. state machine then moves on to initiate auth pulse 267 | // 268 | //////// 269 | HDCP_AUTH_PULSE: begin 270 | HDCP_nstate = HDCP_AUTH; 271 | end 272 | HDCP_AUTH: begin 273 | HDCP_nstate = stream_ready? HDCP_AUTH : HDCP_AUTH_WAIT; 274 | end 275 | HDCP_AUTH_WAIT: begin 276 | HDCP_nstate = stream_ready ? HDCP_AUTH_VSYNC_PULSE : HDCP_AUTH_WAIT; 277 | end 278 | 279 | // this is a special vsync-update state just for after auth 280 | // because I don't know if there is more than 1 vsync period between 281 | // the conclusion of auth and the first 1001 assertion 282 | // if there is, then we end up unsynchronized on the Mi state 283 | HDCP_AUTH_VSYNC_PULSE: begin 284 | HDCP_nstate = HDCP_AUTH_VSYNC; 285 | end 286 | HDCP_AUTH_VSYNC: begin 287 | HDCP_nstate = stream_ready ? HDCP_AUTH_VSYNC : HDCP_AUTH_VSYNC_WAIT; 288 | end 289 | HDCP_AUTH_VSYNC_WAIT: begin 290 | HDCP_nstate = stream_ready ? HDCP_WAIT_1001 : HDCP_AUTH_VSYNC_WAIT; 291 | end 292 | 293 | // our primary wait state 294 | HDCP_WAIT_1001: begin 295 | HDCP_nstate = ((vsync_v && (ctl_code[3:0] == 4'b1001)) || appleTV2_bug) ? 296 | HDCP_WAIT_1001_END : HDCP_WAIT_1001; 297 | end 298 | HDCP_WAIT_1001_END: begin 299 | HDCP_nstate = (vsync_v && (ctl_code[3:0] == 4'b1001)) ? 300 | HDCP_WAIT_1001_END : HDCP_READY; 301 | end 302 | 303 | 304 | HDCP_VSYNC_PULSE: begin 305 | HDCP_nstate = HDCP_VSYNC; 306 | end 307 | HDCP_VSYNC: begin 308 | HDCP_nstate = stream_ready ? HDCP_VSYNC : HDCP_VSYNC_WAIT; 309 | end 310 | HDCP_VSYNC_WAIT: begin 311 | HDCP_nstate = stream_ready ? HDCP_WAIT_1001 : HDCP_VSYNC_WAIT; 312 | end 313 | 314 | // our primary cipher state 315 | HDCP_READY: begin 316 | // i've now got a signal banging rekey outside this state machine 317 | // it's unclean, but necessary to get rekey to happen early enough 318 | // to meet hdcp spec requirement for rekey time. 319 | // Core assumption: the only way stream becomes un-ready during 320 | // HDCP_READY is due to the external rekey event. vsync_rising 321 | // will never result in this triggering because it itself must 322 | // transition this state machine to a new state before stream_ready 323 | // changes; and furthermore, stream_ready is guaranteed to be high 324 | // upon return to this state. 325 | HDCP_nstate = (stream_ready == 1'b0) ? HDCP_REKEY_WAIT : 326 | vsync_rising ? HDCP_VSYNC_PULSE : 327 | HDCP_READY; 328 | end 329 | 330 | HDCP_REKEY_PULSE: begin 331 | HDCP_nstate = HDCP_REKEY; 332 | end 333 | HDCP_REKEY: begin 334 | HDCP_nstate = stream_ready ? HDCP_REKEY : HDCP_REKEY_WAIT; 335 | end 336 | HDCP_REKEY_WAIT: begin 337 | HDCP_nstate = stream_ready ? HDCP_READY : HDCP_REKEY_WAIT; 338 | end 339 | endcase // case (HDCP_cstate) 340 | end 341 | 342 | // assign Km_ready = !Km_rdy2 & Km_rdy1; // rising edge pulse 343 | assign Km_ready = Km_rdy2; // for now make it level triggered ("cheezy mode") 344 | 345 | always @ (posedge clk) begin 346 | if( reset | hpd_n ) begin 347 | auth_mode <=#1 1'b0; 348 | hdcp_init <=#1 1'b0; 349 | hdcp_rekey <=#1 1'b0; 350 | hdcp_requested <=#1 1'b0; 351 | 352 | Km_rdy0 <= 1'b0; 353 | Km_rdy1 <= 1'b0; 354 | Km_rdy2 <= 1'b0; 355 | end else begin 356 | Km_rdy0 <= Km_rdy; 357 | Km_rdy1 <= Km_rdy0; 358 | Km_rdy2 <= Km_rdy1; 359 | 360 | case (HDCP_cstate) //synthesis parallel_case full_case 361 | HDCP_UNPLUG: begin 362 | auth_mode <=#1 1'b0; 363 | hdcp_init <=#1 1'b0; 364 | hdcp_rekey <=#1 1'b0; 365 | hdcp_requested <=#1 1'b0; 366 | end 367 | HDCP_WAIT_AKSV: begin 368 | auth_mode <=#1 1'b0; 369 | hdcp_init <=#1 1'b0; 370 | hdcp_rekey <=#1 1'b0; 371 | hdcp_requested <=#1 1'b0; 372 | end 373 | 374 | HDCP_WAIT_KMRDY: begin 375 | auth_mode <=#1 1'b0; 376 | hdcp_init <=#1 1'b0; 377 | hdcp_rekey <=#1 1'b0; 378 | hdcp_requested <=#1 1'b0; 379 | end 380 | 381 | HDCP_AUTH_PULSE: begin 382 | auth_mode <=#1 1'b1; 383 | hdcp_init <=#1 1'b1; // pulse just one cycle 384 | hdcp_rekey <=#1 1'b0; 385 | hdcp_requested <=#1 1'b0; 386 | end 387 | HDCP_AUTH: begin 388 | auth_mode <=#1 1'b0; 389 | hdcp_init <=#1 1'b0; 390 | hdcp_rekey <=#1 1'b0; 391 | hdcp_requested <=#1 1'b0; 392 | end 393 | HDCP_AUTH_WAIT: begin 394 | auth_mode <=#1 1'b0; 395 | hdcp_init <=#1 1'b0; 396 | hdcp_rekey <=#1 1'b0; 397 | hdcp_requested <=#1 1'b0; 398 | end 399 | 400 | HDCP_AUTH_VSYNC_PULSE: begin 401 | auth_mode <=#1 1'b0; 402 | hdcp_init <=#1 1'b1; // pulse init, but not with auth_mode 403 | hdcp_rekey <=#1 1'b0; 404 | hdcp_requested <=#1 1'b0; 405 | end 406 | HDCP_AUTH_VSYNC: begin 407 | auth_mode <=#1 1'b0; 408 | hdcp_init <=#1 1'b0; 409 | hdcp_rekey <=#1 1'b0; 410 | hdcp_requested <=#1 1'b0; 411 | end 412 | HDCP_AUTH_VSYNC_WAIT: begin 413 | auth_mode <=#1 1'b0; 414 | hdcp_init <=#1 1'b0; 415 | hdcp_rekey <=#1 1'b0; 416 | hdcp_requested <=#1 1'b0; 417 | end 418 | 419 | HDCP_WAIT_1001: begin 420 | auth_mode <=#1 1'b0; 421 | hdcp_init <=#1 1'b0; 422 | hdcp_rekey <=#1 1'b0; 423 | hdcp_requested <=#1 1'b0; 424 | end 425 | HDCP_WAIT_1001_END: begin 426 | auth_mode <=#1 1'b0; 427 | hdcp_init <=#1 1'b0; 428 | hdcp_rekey <=#1 1'b0; 429 | hdcp_requested <=#1 1'b0; 430 | end 431 | 432 | HDCP_VSYNC_PULSE: begin 433 | auth_mode <=#1 1'b0; 434 | hdcp_init <=#1 1'b1; // pulse init, but not with auth_mode 435 | hdcp_rekey <=#1 1'b0; 436 | hdcp_requested <=#1 1'b1; 437 | end 438 | HDCP_VSYNC: begin 439 | auth_mode <=#1 1'b0; 440 | hdcp_init <=#1 1'b0; 441 | hdcp_rekey <=#1 1'b0; 442 | hdcp_requested <=#1 1'b1; 443 | end 444 | HDCP_VSYNC_WAIT: begin 445 | auth_mode <=#1 1'b0; 446 | hdcp_init <=#1 1'b0; 447 | hdcp_rekey <=#1 1'b0; 448 | hdcp_requested <=#1 1'b1; 449 | end 450 | 451 | HDCP_READY: begin 452 | auth_mode <=#1 1'b0; 453 | hdcp_init <=#1 1'b0; 454 | hdcp_rekey <=#1 1'b0; 455 | hdcp_requested <=#1 1'b1; 456 | end 457 | 458 | HDCP_REKEY_PULSE: begin 459 | auth_mode <=#1 1'b0; 460 | hdcp_init <=#1 1'b0; 461 | // hdcp_rekey <=#1 1'b1; // pulse rekey 462 | hdcp_rekey <=#1 1'b0; // we're going to do this asychronously to save some cycles 463 | // yes, it means hdcp_rekey gets optimized out 464 | // but structurally this helps me remember what the code was intended to do 465 | hdcp_requested <=#1 1'b1; 466 | end 467 | HDCP_REKEY: begin 468 | auth_mode <=#1 1'b0; 469 | hdcp_init <=#1 1'b0; 470 | hdcp_rekey <=#1 1'b0; 471 | hdcp_requested <=#1 1'b1; 472 | end 473 | HDCP_REKEY_WAIT: begin 474 | auth_mode <=#1 1'b0; 475 | hdcp_init <=#1 1'b0; 476 | hdcp_rekey <=#1 1'b0; 477 | hdcp_requested <=#1 1'b1; 478 | end 479 | endcase // case (HDCP_cstate) 480 | end // else: !if( reset ) 481 | end // always @ (posedge clk) 482 | 483 | hdcp_cipher cipher ( 484 | .clk(clk), 485 | .reset(reset), 486 | .Km(Km), 487 | .An(An), 488 | .hdcpBlockCipher_init(hdcp_init), 489 | .authentication(auth_mode), 490 | .hdcpRekeyCipher(hdcp_rekey_2), 491 | .hdcpStreamCipher(hdcp_ena && (HDCP_cstate == HDCP_READY)), 492 | .pr_data(cipher_stream), 493 | .stream_ready(stream_ready) 494 | ); 495 | 496 | 497 | endmodule // hdcp_engine 498 | 499 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_lfsr.v: -------------------------------------------------------------------------------- 1 | /* 2 | This program is free software: you can redistribute it and/or modify 3 | it under the terms of the GNU General Public License as published by 4 | the Free Software Foundation, either version 3 of the License, or 5 | (at your option) any later version. 6 | 7 | This program is distributed in the hope that it will be useful, 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 | GNU General Public License for more details. 11 | 12 | You should have received a copy of the GNU General Public License 13 | along with this program. If not, see . 14 | 15 | 16 | Copyright 2016 Andrew 'bunnie' Huang, all rights reserved 17 | */ 18 | 19 | 20 | `timescale 1 ns / 1 ps 21 | 22 | // lfsr module for hdcp cipher 23 | module hdcp_lfsr( 24 | input wire clk, 25 | input wire reset, // this is just a low-level reset 26 | 27 | input wire [55:0] iv, // initial values 28 | 29 | input wire init_iv, // load initial values 30 | input wire advance, // advance state one cycle 31 | output wire onebit // my one-bit output 32 | ); 33 | 34 | reg [12:0] lfsr0; 35 | reg [13:0] lfsr1; 36 | reg [15:0] lfsr2; 37 | reg [16:0] lfsr3; 38 | 39 | wire [3:0] comb_tap0; 40 | wire [3:0] comb_tap1; 41 | wire [3:0] comb_tap2; 42 | 43 | always @(posedge clk) begin 44 | if( reset == 1 ) begin 45 | lfsr0 <= 13'b0; 46 | lfsr1 <= 14'b0; 47 | lfsr2 <= 16'b0; 48 | lfsr3 <= 17'b0; 49 | end else begin 50 | if( init_iv ) begin 51 | // assume bit-offsets start from 0 52 | lfsr0[12:0] <= {~iv[6],iv[11:0]}; 53 | lfsr1[13:0] <= {~iv[18],iv[24:12]}; 54 | lfsr2[15:0] <= {~iv[32],iv[39:25]}; 55 | lfsr3[16:0] <= {~iv[47],iv[55:40]}; 56 | end else if( advance ) begin 57 | // 13 11 9 5 58 | // 12 10 8 4 59 | lfsr0[0 ] <= lfsr0[4] ^ lfsr0[8] ^ lfsr0[10] ^ lfsr0[12]; 60 | lfsr0[1 ] <= lfsr0[0 ]; 61 | lfsr0[2 ] <= lfsr0[1 ]; 62 | lfsr0[3 ] <= lfsr0[2 ]; 63 | lfsr0[4 ] <= lfsr0[3 ]; 64 | lfsr0[5 ] <= lfsr0[4 ]; 65 | lfsr0[6 ] <= lfsr0[5 ]; 66 | lfsr0[7 ] <= lfsr0[6 ]; 67 | lfsr0[8 ] <= lfsr0[7 ]; 68 | lfsr0[9 ] <= lfsr0[8 ]; 69 | lfsr0[10] <= lfsr0[9 ]; 70 | lfsr0[11] <= lfsr0[10]; 71 | lfsr0[12] <= lfsr0[11]; 72 | 73 | //4 6 7 10 11 14 74 | //3 5 6 9 10 13 75 | lfsr1[0 ] <= lfsr1[3] ^ lfsr1[5] ^ lfsr1[6] ^ lfsr1[9] ^ lfsr1[10] ^ lfsr1[13]; 76 | lfsr1[1 ] <= lfsr1[0 ]; 77 | lfsr1[2 ] <= lfsr1[1 ]; 78 | lfsr1[3 ] <= lfsr1[2 ]; 79 | lfsr1[4 ] <= lfsr1[3 ]; 80 | lfsr1[5 ] <= lfsr1[4 ]; 81 | lfsr1[6 ] <= lfsr1[5 ]; 82 | lfsr1[7 ] <= lfsr1[6 ]; 83 | lfsr1[8 ] <= lfsr1[7 ]; 84 | lfsr1[9 ] <= lfsr1[8 ]; 85 | lfsr1[10] <= lfsr1[9 ]; 86 | lfsr1[11] <= lfsr1[10]; 87 | lfsr1[12] <= lfsr1[11]; 88 | lfsr1[13] <= lfsr1[12]; 89 | 90 | //5 7 8 12 15 16 91 | //4 6 7 11 14 15 92 | lfsr2[0 ] <= lfsr2[4] ^ lfsr2[6] ^ lfsr2[7] ^ lfsr2[11] ^ lfsr2[14] ^ lfsr2[15]; 93 | lfsr2[1 ] <= lfsr2[0 ]; 94 | lfsr2[2 ] <= lfsr2[1 ]; 95 | lfsr2[3 ] <= lfsr2[2 ]; 96 | lfsr2[4 ] <= lfsr2[3 ]; 97 | lfsr2[5 ] <= lfsr2[4 ]; 98 | lfsr2[6 ] <= lfsr2[5 ]; 99 | lfsr2[7 ] <= lfsr2[6 ]; 100 | lfsr2[8 ] <= lfsr2[7 ]; 101 | lfsr2[9 ] <= lfsr2[8 ]; 102 | lfsr2[10] <= lfsr2[9 ]; 103 | lfsr2[11] <= lfsr2[10]; 104 | lfsr2[12] <= lfsr2[11]; 105 | lfsr2[13] <= lfsr2[12]; 106 | lfsr2[14] <= lfsr2[13]; 107 | lfsr2[15] <= lfsr2[14]; 108 | 109 | //5 11 15 17 110 | //4 10 14 16 111 | lfsr3[0 ] <= lfsr3[4] ^ lfsr3[10] ^ lfsr3[14] ^ lfsr3[16]; 112 | lfsr3[1 ] <= lfsr3[0 ]; 113 | lfsr3[2 ] <= lfsr3[1 ]; 114 | lfsr3[3 ] <= lfsr3[2 ]; 115 | lfsr3[4 ] <= lfsr3[3 ]; 116 | lfsr3[5 ] <= lfsr3[4 ]; 117 | lfsr3[6 ] <= lfsr3[5 ]; 118 | lfsr3[7 ] <= lfsr3[6 ]; 119 | lfsr3[8 ] <= lfsr3[7 ]; 120 | lfsr3[9 ] <= lfsr3[8 ]; 121 | lfsr3[10] <= lfsr3[9 ]; 122 | lfsr3[11] <= lfsr3[10]; 123 | lfsr3[12] <= lfsr3[11]; 124 | lfsr3[13] <= lfsr3[12]; 125 | lfsr3[14] <= lfsr3[13]; 126 | lfsr3[15] <= lfsr3[14]; 127 | lfsr3[16] <= lfsr3[15]; 128 | end else begin 129 | // hold state 130 | lfsr0 <= lfsr0; 131 | lfsr1 <= lfsr1; 132 | lfsr2 <= lfsr2; 133 | lfsr3 <= lfsr3; 134 | end 135 | end // else: !if( reset == 1 ) 136 | end // always @ (posedge clk or posedge reset) 137 | 138 | assign comb_tap0[0] = lfsr0[3]; 139 | assign comb_tap0[1] = lfsr1[4]; 140 | assign comb_tap0[2] = lfsr2[5]; 141 | assign comb_tap0[3] = lfsr3[5]; 142 | 143 | assign comb_tap1[0] = lfsr0[7]; 144 | assign comb_tap1[1] = lfsr1[8]; 145 | assign comb_tap1[2] = lfsr2[9]; 146 | assign comb_tap1[3] = lfsr3[11]; 147 | 148 | assign comb_tap2[0] = lfsr0[12]; 149 | assign comb_tap2[1] = lfsr1[13]; 150 | assign comb_tap2[2] = lfsr2[15]; 151 | assign comb_tap2[3] = lfsr3[16]; 152 | 153 | wire [3:0] sh_dout; 154 | shuffle_network sh0 ( .clk(clk), .reset(reset), 155 | .din(comb_tap0[0] ^ comb_tap0[1] ^ comb_tap0[2] ^ comb_tap0[3]), 156 | .sel(comb_tap1[0]), 157 | .advance(advance), 158 | .init_iv(init_iv), 159 | .dout(sh_dout[0]) 160 | ); 161 | 162 | shuffle_network sh1 ( .clk(clk), .reset(reset), 163 | .din(sh_dout[0]), 164 | .sel(comb_tap1[1]), 165 | .advance(advance), 166 | .init_iv(init_iv), 167 | .dout(sh_dout[1]) 168 | ); 169 | 170 | shuffle_network sh2 ( .clk(clk), .reset(reset), 171 | .din(sh_dout[1]), 172 | .sel(comb_tap1[2]), 173 | .advance(advance), 174 | .init_iv(init_iv), 175 | .dout(sh_dout[2]) 176 | ); 177 | 178 | shuffle_network sh3 ( .clk(clk), .reset(reset), 179 | .din(sh_dout[2]), 180 | .sel(comb_tap1[3]), 181 | .advance(advance), 182 | .init_iv(init_iv), 183 | .dout(sh_dout[3]) 184 | ); 185 | 186 | assign onebit = sh_dout[3] ^ comb_tap2[0] ^ comb_tap2[1] ^ comb_tap2[2] ^ comb_tap2[3]; 187 | 188 | endmodule // hdcp_lfsr 189 | 190 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/shuffle_network.v: -------------------------------------------------------------------------------- 1 | /* 2 | This program is free software: you can redistribute it and/or modify 3 | it under the terms of the GNU General Public License as published by 4 | the Free Software Foundation, either version 3 of the License, or 5 | (at your option) any later version. 6 | 7 | This program is distributed in the hope that it will be useful, 8 | but WITHOUT ANY WARRANTY; without even the implied warranty of 9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 | GNU General Public License for more details. 11 | 12 | You should have received a copy of the GNU General Public License 13 | along with this program. If not, see . 14 | 15 | 16 | Copyright 2016 Andrew 'bunnie' Huang, all rights reserved 17 | */ 18 | 19 | 20 | module shuffle_network ( 21 | input wire clk, 22 | input wire reset, 23 | input wire din, 24 | input wire sel, 25 | input wire advance, 26 | input wire init_iv, 27 | output wire dout 28 | ); 29 | 30 | reg a, b; 31 | 32 | always @(posedge clk) begin 33 | if( reset == 1 ) begin 34 | a <= 1'b0; 35 | b <= 1'b1; 36 | end else begin 37 | if( init_iv ) begin 38 | a <= 1'b0; 39 | b <= 1'b1; 40 | end else if( advance ) begin 41 | a <= sel ? din : b; 42 | b <= sel ? a : din; 43 | end else begin 44 | a <= a; 45 | b <= b; 46 | end 47 | end // else: !if( reset == 1 ) 48 | end // always @ (posedge clk or posedge reset) 49 | 50 | assign dout = sel ? b : a; 51 | 52 | endmodule // shuffle_network 53 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/xgui/hdcp_engine_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "HDCP_AUTH" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "HDCP_AUTH_PULSE" -parent ${Page_0} 8 | ipgui::add_param $IPINST -name "HDCP_AUTH_VSYNC" -parent ${Page_0} 9 | ipgui::add_param $IPINST -name "HDCP_AUTH_VSYNC_PULSE" -parent ${Page_0} 10 | ipgui::add_param $IPINST -name "HDCP_AUTH_VSYNC_WAIT" -parent ${Page_0} 11 | ipgui::add_param $IPINST -name "HDCP_AUTH_WAIT" -parent ${Page_0} 12 | ipgui::add_param $IPINST -name "HDCP_READY" -parent ${Page_0} 13 | ipgui::add_param $IPINST -name "HDCP_REKEY" -parent ${Page_0} 14 | ipgui::add_param $IPINST -name "HDCP_REKEY_PULSE" -parent ${Page_0} 15 | ipgui::add_param $IPINST -name "HDCP_REKEY_WAIT" -parent ${Page_0} 16 | ipgui::add_param $IPINST -name "HDCP_UNPLUG" -parent ${Page_0} 17 | ipgui::add_param $IPINST -name "HDCP_VSYNC" -parent ${Page_0} 18 | ipgui::add_param $IPINST -name "HDCP_VSYNC_PULSE" -parent ${Page_0} 19 | ipgui::add_param $IPINST -name "HDCP_VSYNC_WAIT" -parent ${Page_0} 20 | ipgui::add_param $IPINST -name "HDCP_WAIT_1001" -parent ${Page_0} 21 | ipgui::add_param $IPINST -name "HDCP_WAIT_1001_END" -parent ${Page_0} 22 | ipgui::add_param $IPINST -name "HDCP_WAIT_AKSV" -parent ${Page_0} 23 | ipgui::add_param $IPINST -name "HDCP_WAIT_KMRDY" -parent ${Page_0} 24 | ipgui::add_param $IPINST -name "HDCP_nSTATES" -parent ${Page_0} 25 | 26 | 27 | } 28 | 29 | proc update_PARAM_VALUE.HDCP_AUTH { PARAM_VALUE.HDCP_AUTH } { 30 | # Procedure called to update HDCP_AUTH when any of the dependent parameters in the arguments change 31 | } 32 | 33 | proc validate_PARAM_VALUE.HDCP_AUTH { PARAM_VALUE.HDCP_AUTH } { 34 | # Procedure called to validate HDCP_AUTH 35 | return true 36 | } 37 | 38 | proc update_PARAM_VALUE.HDCP_AUTH_PULSE { PARAM_VALUE.HDCP_AUTH_PULSE } { 39 | # Procedure called to update HDCP_AUTH_PULSE when any of the dependent parameters in the arguments change 40 | } 41 | 42 | proc validate_PARAM_VALUE.HDCP_AUTH_PULSE { PARAM_VALUE.HDCP_AUTH_PULSE } { 43 | # Procedure called to validate HDCP_AUTH_PULSE 44 | return true 45 | } 46 | 47 | proc update_PARAM_VALUE.HDCP_AUTH_VSYNC { PARAM_VALUE.HDCP_AUTH_VSYNC } { 48 | # Procedure called to update HDCP_AUTH_VSYNC when any of the dependent parameters in the arguments change 49 | } 50 | 51 | proc validate_PARAM_VALUE.HDCP_AUTH_VSYNC { PARAM_VALUE.HDCP_AUTH_VSYNC } { 52 | # Procedure called to validate HDCP_AUTH_VSYNC 53 | return true 54 | } 55 | 56 | proc update_PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE { PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE } { 57 | # Procedure called to update HDCP_AUTH_VSYNC_PULSE when any of the dependent parameters in the arguments change 58 | } 59 | 60 | proc validate_PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE { PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE } { 61 | # Procedure called to validate HDCP_AUTH_VSYNC_PULSE 62 | return true 63 | } 64 | 65 | proc update_PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT { PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT } { 66 | # Procedure called to update HDCP_AUTH_VSYNC_WAIT when any of the dependent parameters in the arguments change 67 | } 68 | 69 | proc validate_PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT { PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT } { 70 | # Procedure called to validate HDCP_AUTH_VSYNC_WAIT 71 | return true 72 | } 73 | 74 | proc update_PARAM_VALUE.HDCP_AUTH_WAIT { PARAM_VALUE.HDCP_AUTH_WAIT } { 75 | # Procedure called to update HDCP_AUTH_WAIT when any of the dependent parameters in the arguments change 76 | } 77 | 78 | proc validate_PARAM_VALUE.HDCP_AUTH_WAIT { PARAM_VALUE.HDCP_AUTH_WAIT } { 79 | # Procedure called to validate HDCP_AUTH_WAIT 80 | return true 81 | } 82 | 83 | proc update_PARAM_VALUE.HDCP_READY { PARAM_VALUE.HDCP_READY } { 84 | # Procedure called to update HDCP_READY when any of the dependent parameters in the arguments change 85 | } 86 | 87 | proc validate_PARAM_VALUE.HDCP_READY { PARAM_VALUE.HDCP_READY } { 88 | # Procedure called to validate HDCP_READY 89 | return true 90 | } 91 | 92 | proc update_PARAM_VALUE.HDCP_REKEY { PARAM_VALUE.HDCP_REKEY } { 93 | # Procedure called to update HDCP_REKEY when any of the dependent parameters in the arguments change 94 | } 95 | 96 | proc validate_PARAM_VALUE.HDCP_REKEY { PARAM_VALUE.HDCP_REKEY } { 97 | # Procedure called to validate HDCP_REKEY 98 | return true 99 | } 100 | 101 | proc update_PARAM_VALUE.HDCP_REKEY_PULSE { PARAM_VALUE.HDCP_REKEY_PULSE } { 102 | # Procedure called to update HDCP_REKEY_PULSE when any of the dependent parameters in the arguments change 103 | } 104 | 105 | proc validate_PARAM_VALUE.HDCP_REKEY_PULSE { PARAM_VALUE.HDCP_REKEY_PULSE } { 106 | # Procedure called to validate HDCP_REKEY_PULSE 107 | return true 108 | } 109 | 110 | proc update_PARAM_VALUE.HDCP_REKEY_WAIT { PARAM_VALUE.HDCP_REKEY_WAIT } { 111 | # Procedure called to update HDCP_REKEY_WAIT when any of the dependent parameters in the arguments change 112 | } 113 | 114 | proc validate_PARAM_VALUE.HDCP_REKEY_WAIT { PARAM_VALUE.HDCP_REKEY_WAIT } { 115 | # Procedure called to validate HDCP_REKEY_WAIT 116 | return true 117 | } 118 | 119 | proc update_PARAM_VALUE.HDCP_UNPLUG { PARAM_VALUE.HDCP_UNPLUG } { 120 | # Procedure called to update HDCP_UNPLUG when any of the dependent parameters in the arguments change 121 | } 122 | 123 | proc validate_PARAM_VALUE.HDCP_UNPLUG { PARAM_VALUE.HDCP_UNPLUG } { 124 | # Procedure called to validate HDCP_UNPLUG 125 | return true 126 | } 127 | 128 | proc update_PARAM_VALUE.HDCP_VSYNC { PARAM_VALUE.HDCP_VSYNC } { 129 | # Procedure called to update HDCP_VSYNC when any of the dependent parameters in the arguments change 130 | } 131 | 132 | proc validate_PARAM_VALUE.HDCP_VSYNC { PARAM_VALUE.HDCP_VSYNC } { 133 | # Procedure called to validate HDCP_VSYNC 134 | return true 135 | } 136 | 137 | proc update_PARAM_VALUE.HDCP_VSYNC_PULSE { PARAM_VALUE.HDCP_VSYNC_PULSE } { 138 | # Procedure called to update HDCP_VSYNC_PULSE when any of the dependent parameters in the arguments change 139 | } 140 | 141 | proc validate_PARAM_VALUE.HDCP_VSYNC_PULSE { PARAM_VALUE.HDCP_VSYNC_PULSE } { 142 | # Procedure called to validate HDCP_VSYNC_PULSE 143 | return true 144 | } 145 | 146 | proc update_PARAM_VALUE.HDCP_VSYNC_WAIT { PARAM_VALUE.HDCP_VSYNC_WAIT } { 147 | # Procedure called to update HDCP_VSYNC_WAIT when any of the dependent parameters in the arguments change 148 | } 149 | 150 | proc validate_PARAM_VALUE.HDCP_VSYNC_WAIT { PARAM_VALUE.HDCP_VSYNC_WAIT } { 151 | # Procedure called to validate HDCP_VSYNC_WAIT 152 | return true 153 | } 154 | 155 | proc update_PARAM_VALUE.HDCP_WAIT_1001 { PARAM_VALUE.HDCP_WAIT_1001 } { 156 | # Procedure called to update HDCP_WAIT_1001 when any of the dependent parameters in the arguments change 157 | } 158 | 159 | proc validate_PARAM_VALUE.HDCP_WAIT_1001 { PARAM_VALUE.HDCP_WAIT_1001 } { 160 | # Procedure called to validate HDCP_WAIT_1001 161 | return true 162 | } 163 | 164 | proc update_PARAM_VALUE.HDCP_WAIT_1001_END { PARAM_VALUE.HDCP_WAIT_1001_END } { 165 | # Procedure called to update HDCP_WAIT_1001_END when any of the dependent parameters in the arguments change 166 | } 167 | 168 | proc validate_PARAM_VALUE.HDCP_WAIT_1001_END { PARAM_VALUE.HDCP_WAIT_1001_END } { 169 | # Procedure called to validate HDCP_WAIT_1001_END 170 | return true 171 | } 172 | 173 | proc update_PARAM_VALUE.HDCP_WAIT_AKSV { PARAM_VALUE.HDCP_WAIT_AKSV } { 174 | # Procedure called to update HDCP_WAIT_AKSV when any of the dependent parameters in the arguments change 175 | } 176 | 177 | proc validate_PARAM_VALUE.HDCP_WAIT_AKSV { PARAM_VALUE.HDCP_WAIT_AKSV } { 178 | # Procedure called to validate HDCP_WAIT_AKSV 179 | return true 180 | } 181 | 182 | proc update_PARAM_VALUE.HDCP_WAIT_KMRDY { PARAM_VALUE.HDCP_WAIT_KMRDY } { 183 | # Procedure called to update HDCP_WAIT_KMRDY when any of the dependent parameters in the arguments change 184 | } 185 | 186 | proc validate_PARAM_VALUE.HDCP_WAIT_KMRDY { PARAM_VALUE.HDCP_WAIT_KMRDY } { 187 | # Procedure called to validate HDCP_WAIT_KMRDY 188 | return true 189 | } 190 | 191 | proc update_PARAM_VALUE.HDCP_nSTATES { PARAM_VALUE.HDCP_nSTATES } { 192 | # Procedure called to update HDCP_nSTATES when any of the dependent parameters in the arguments change 193 | } 194 | 195 | proc validate_PARAM_VALUE.HDCP_nSTATES { PARAM_VALUE.HDCP_nSTATES } { 196 | # Procedure called to validate HDCP_nSTATES 197 | return true 198 | } 199 | 200 | 201 | proc update_MODELPARAM_VALUE.HDCP_UNPLUG { MODELPARAM_VALUE.HDCP_UNPLUG PARAM_VALUE.HDCP_UNPLUG } { 202 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 203 | set_property value [get_property value ${PARAM_VALUE.HDCP_UNPLUG}] ${MODELPARAM_VALUE.HDCP_UNPLUG} 204 | } 205 | 206 | proc update_MODELPARAM_VALUE.HDCP_WAIT_AKSV { MODELPARAM_VALUE.HDCP_WAIT_AKSV PARAM_VALUE.HDCP_WAIT_AKSV } { 207 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 208 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_AKSV}] ${MODELPARAM_VALUE.HDCP_WAIT_AKSV} 209 | } 210 | 211 | proc update_MODELPARAM_VALUE.HDCP_AUTH_PULSE { MODELPARAM_VALUE.HDCP_AUTH_PULSE PARAM_VALUE.HDCP_AUTH_PULSE } { 212 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 213 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_PULSE}] ${MODELPARAM_VALUE.HDCP_AUTH_PULSE} 214 | } 215 | 216 | proc update_MODELPARAM_VALUE.HDCP_AUTH { MODELPARAM_VALUE.HDCP_AUTH PARAM_VALUE.HDCP_AUTH } { 217 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 218 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH}] ${MODELPARAM_VALUE.HDCP_AUTH} 219 | } 220 | 221 | proc update_MODELPARAM_VALUE.HDCP_AUTH_WAIT { MODELPARAM_VALUE.HDCP_AUTH_WAIT PARAM_VALUE.HDCP_AUTH_WAIT } { 222 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 223 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_WAIT}] ${MODELPARAM_VALUE.HDCP_AUTH_WAIT} 224 | } 225 | 226 | proc update_MODELPARAM_VALUE.HDCP_AUTH_VSYNC_PULSE { MODELPARAM_VALUE.HDCP_AUTH_VSYNC_PULSE PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE } { 227 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 228 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE}] ${MODELPARAM_VALUE.HDCP_AUTH_VSYNC_PULSE} 229 | } 230 | 231 | proc update_MODELPARAM_VALUE.HDCP_AUTH_VSYNC { MODELPARAM_VALUE.HDCP_AUTH_VSYNC PARAM_VALUE.HDCP_AUTH_VSYNC } { 232 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 233 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_VSYNC}] ${MODELPARAM_VALUE.HDCP_AUTH_VSYNC} 234 | } 235 | 236 | proc update_MODELPARAM_VALUE.HDCP_AUTH_VSYNC_WAIT { MODELPARAM_VALUE.HDCP_AUTH_VSYNC_WAIT PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT } { 237 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 238 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT}] ${MODELPARAM_VALUE.HDCP_AUTH_VSYNC_WAIT} 239 | } 240 | 241 | proc update_MODELPARAM_VALUE.HDCP_WAIT_1001 { MODELPARAM_VALUE.HDCP_WAIT_1001 PARAM_VALUE.HDCP_WAIT_1001 } { 242 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 243 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_1001}] ${MODELPARAM_VALUE.HDCP_WAIT_1001} 244 | } 245 | 246 | proc update_MODELPARAM_VALUE.HDCP_WAIT_1001_END { MODELPARAM_VALUE.HDCP_WAIT_1001_END PARAM_VALUE.HDCP_WAIT_1001_END } { 247 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 248 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_1001_END}] ${MODELPARAM_VALUE.HDCP_WAIT_1001_END} 249 | } 250 | 251 | proc update_MODELPARAM_VALUE.HDCP_VSYNC { MODELPARAM_VALUE.HDCP_VSYNC PARAM_VALUE.HDCP_VSYNC } { 252 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 253 | set_property value [get_property value ${PARAM_VALUE.HDCP_VSYNC}] ${MODELPARAM_VALUE.HDCP_VSYNC} 254 | } 255 | 256 | proc update_MODELPARAM_VALUE.HDCP_VSYNC_PULSE { MODELPARAM_VALUE.HDCP_VSYNC_PULSE PARAM_VALUE.HDCP_VSYNC_PULSE } { 257 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 258 | set_property value [get_property value ${PARAM_VALUE.HDCP_VSYNC_PULSE}] ${MODELPARAM_VALUE.HDCP_VSYNC_PULSE} 259 | } 260 | 261 | proc update_MODELPARAM_VALUE.HDCP_VSYNC_WAIT { MODELPARAM_VALUE.HDCP_VSYNC_WAIT PARAM_VALUE.HDCP_VSYNC_WAIT } { 262 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 263 | set_property value [get_property value ${PARAM_VALUE.HDCP_VSYNC_WAIT}] ${MODELPARAM_VALUE.HDCP_VSYNC_WAIT} 264 | } 265 | 266 | proc update_MODELPARAM_VALUE.HDCP_READY { MODELPARAM_VALUE.HDCP_READY PARAM_VALUE.HDCP_READY } { 267 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 268 | set_property value [get_property value ${PARAM_VALUE.HDCP_READY}] ${MODELPARAM_VALUE.HDCP_READY} 269 | } 270 | 271 | proc update_MODELPARAM_VALUE.HDCP_REKEY { MODELPARAM_VALUE.HDCP_REKEY PARAM_VALUE.HDCP_REKEY } { 272 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 273 | set_property value [get_property value ${PARAM_VALUE.HDCP_REKEY}] ${MODELPARAM_VALUE.HDCP_REKEY} 274 | } 275 | 276 | proc update_MODELPARAM_VALUE.HDCP_REKEY_PULSE { MODELPARAM_VALUE.HDCP_REKEY_PULSE PARAM_VALUE.HDCP_REKEY_PULSE } { 277 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 278 | set_property value [get_property value ${PARAM_VALUE.HDCP_REKEY_PULSE}] ${MODELPARAM_VALUE.HDCP_REKEY_PULSE} 279 | } 280 | 281 | proc update_MODELPARAM_VALUE.HDCP_REKEY_WAIT { MODELPARAM_VALUE.HDCP_REKEY_WAIT PARAM_VALUE.HDCP_REKEY_WAIT } { 282 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 283 | set_property value [get_property value ${PARAM_VALUE.HDCP_REKEY_WAIT}] ${MODELPARAM_VALUE.HDCP_REKEY_WAIT} 284 | } 285 | 286 | proc update_MODELPARAM_VALUE.HDCP_WAIT_KMRDY { MODELPARAM_VALUE.HDCP_WAIT_KMRDY PARAM_VALUE.HDCP_WAIT_KMRDY } { 287 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 288 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_KMRDY}] ${MODELPARAM_VALUE.HDCP_WAIT_KMRDY} 289 | } 290 | 291 | proc update_MODELPARAM_VALUE.HDCP_nSTATES { MODELPARAM_VALUE.HDCP_nSTATES PARAM_VALUE.HDCP_nSTATES } { 292 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 293 | set_property value [get_property value ${PARAM_VALUE.HDCP_nSTATES}] ${MODELPARAM_VALUE.HDCP_nSTATES} 294 | } 295 | 296 | -------------------------------------------------------------------------------- /hdcp_engine.srcs/sources_1/imports/srcs-origin/xgui/hdcp_engine_v1_1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "HDCP_AUTH" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "HDCP_AUTH_PULSE" -parent ${Page_0} 8 | ipgui::add_param $IPINST -name "HDCP_AUTH_VSYNC" -parent ${Page_0} 9 | ipgui::add_param $IPINST -name "HDCP_AUTH_VSYNC_PULSE" -parent ${Page_0} 10 | ipgui::add_param $IPINST -name "HDCP_AUTH_VSYNC_WAIT" -parent ${Page_0} 11 | ipgui::add_param $IPINST -name "HDCP_AUTH_WAIT" -parent ${Page_0} 12 | ipgui::add_param $IPINST -name "HDCP_READY" -parent ${Page_0} 13 | ipgui::add_param $IPINST -name "HDCP_REKEY" -parent ${Page_0} 14 | ipgui::add_param $IPINST -name "HDCP_REKEY_PULSE" -parent ${Page_0} 15 | ipgui::add_param $IPINST -name "HDCP_REKEY_WAIT" -parent ${Page_0} 16 | ipgui::add_param $IPINST -name "HDCP_UNPLUG" -parent ${Page_0} 17 | ipgui::add_param $IPINST -name "HDCP_VSYNC" -parent ${Page_0} 18 | ipgui::add_param $IPINST -name "HDCP_VSYNC_PULSE" -parent ${Page_0} 19 | ipgui::add_param $IPINST -name "HDCP_VSYNC_WAIT" -parent ${Page_0} 20 | ipgui::add_param $IPINST -name "HDCP_WAIT_1001" -parent ${Page_0} 21 | ipgui::add_param $IPINST -name "HDCP_WAIT_1001_END" -parent ${Page_0} 22 | ipgui::add_param $IPINST -name "HDCP_WAIT_AKSV" -parent ${Page_0} 23 | ipgui::add_param $IPINST -name "HDCP_WAIT_KMRDY" -parent ${Page_0} 24 | ipgui::add_param $IPINST -name "HDCP_nSTATES" -parent ${Page_0} 25 | 26 | 27 | } 28 | 29 | proc update_PARAM_VALUE.HDCP_AUTH { PARAM_VALUE.HDCP_AUTH } { 30 | # Procedure called to update HDCP_AUTH when any of the dependent parameters in the arguments change 31 | } 32 | 33 | proc validate_PARAM_VALUE.HDCP_AUTH { PARAM_VALUE.HDCP_AUTH } { 34 | # Procedure called to validate HDCP_AUTH 35 | return true 36 | } 37 | 38 | proc update_PARAM_VALUE.HDCP_AUTH_PULSE { PARAM_VALUE.HDCP_AUTH_PULSE } { 39 | # Procedure called to update HDCP_AUTH_PULSE when any of the dependent parameters in the arguments change 40 | } 41 | 42 | proc validate_PARAM_VALUE.HDCP_AUTH_PULSE { PARAM_VALUE.HDCP_AUTH_PULSE } { 43 | # Procedure called to validate HDCP_AUTH_PULSE 44 | return true 45 | } 46 | 47 | proc update_PARAM_VALUE.HDCP_AUTH_VSYNC { PARAM_VALUE.HDCP_AUTH_VSYNC } { 48 | # Procedure called to update HDCP_AUTH_VSYNC when any of the dependent parameters in the arguments change 49 | } 50 | 51 | proc validate_PARAM_VALUE.HDCP_AUTH_VSYNC { PARAM_VALUE.HDCP_AUTH_VSYNC } { 52 | # Procedure called to validate HDCP_AUTH_VSYNC 53 | return true 54 | } 55 | 56 | proc update_PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE { PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE } { 57 | # Procedure called to update HDCP_AUTH_VSYNC_PULSE when any of the dependent parameters in the arguments change 58 | } 59 | 60 | proc validate_PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE { PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE } { 61 | # Procedure called to validate HDCP_AUTH_VSYNC_PULSE 62 | return true 63 | } 64 | 65 | proc update_PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT { PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT } { 66 | # Procedure called to update HDCP_AUTH_VSYNC_WAIT when any of the dependent parameters in the arguments change 67 | } 68 | 69 | proc validate_PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT { PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT } { 70 | # Procedure called to validate HDCP_AUTH_VSYNC_WAIT 71 | return true 72 | } 73 | 74 | proc update_PARAM_VALUE.HDCP_AUTH_WAIT { PARAM_VALUE.HDCP_AUTH_WAIT } { 75 | # Procedure called to update HDCP_AUTH_WAIT when any of the dependent parameters in the arguments change 76 | } 77 | 78 | proc validate_PARAM_VALUE.HDCP_AUTH_WAIT { PARAM_VALUE.HDCP_AUTH_WAIT } { 79 | # Procedure called to validate HDCP_AUTH_WAIT 80 | return true 81 | } 82 | 83 | proc update_PARAM_VALUE.HDCP_READY { PARAM_VALUE.HDCP_READY } { 84 | # Procedure called to update HDCP_READY when any of the dependent parameters in the arguments change 85 | } 86 | 87 | proc validate_PARAM_VALUE.HDCP_READY { PARAM_VALUE.HDCP_READY } { 88 | # Procedure called to validate HDCP_READY 89 | return true 90 | } 91 | 92 | proc update_PARAM_VALUE.HDCP_REKEY { PARAM_VALUE.HDCP_REKEY } { 93 | # Procedure called to update HDCP_REKEY when any of the dependent parameters in the arguments change 94 | } 95 | 96 | proc validate_PARAM_VALUE.HDCP_REKEY { PARAM_VALUE.HDCP_REKEY } { 97 | # Procedure called to validate HDCP_REKEY 98 | return true 99 | } 100 | 101 | proc update_PARAM_VALUE.HDCP_REKEY_PULSE { PARAM_VALUE.HDCP_REKEY_PULSE } { 102 | # Procedure called to update HDCP_REKEY_PULSE when any of the dependent parameters in the arguments change 103 | } 104 | 105 | proc validate_PARAM_VALUE.HDCP_REKEY_PULSE { PARAM_VALUE.HDCP_REKEY_PULSE } { 106 | # Procedure called to validate HDCP_REKEY_PULSE 107 | return true 108 | } 109 | 110 | proc update_PARAM_VALUE.HDCP_REKEY_WAIT { PARAM_VALUE.HDCP_REKEY_WAIT } { 111 | # Procedure called to update HDCP_REKEY_WAIT when any of the dependent parameters in the arguments change 112 | } 113 | 114 | proc validate_PARAM_VALUE.HDCP_REKEY_WAIT { PARAM_VALUE.HDCP_REKEY_WAIT } { 115 | # Procedure called to validate HDCP_REKEY_WAIT 116 | return true 117 | } 118 | 119 | proc update_PARAM_VALUE.HDCP_UNPLUG { PARAM_VALUE.HDCP_UNPLUG } { 120 | # Procedure called to update HDCP_UNPLUG when any of the dependent parameters in the arguments change 121 | } 122 | 123 | proc validate_PARAM_VALUE.HDCP_UNPLUG { PARAM_VALUE.HDCP_UNPLUG } { 124 | # Procedure called to validate HDCP_UNPLUG 125 | return true 126 | } 127 | 128 | proc update_PARAM_VALUE.HDCP_VSYNC { PARAM_VALUE.HDCP_VSYNC } { 129 | # Procedure called to update HDCP_VSYNC when any of the dependent parameters in the arguments change 130 | } 131 | 132 | proc validate_PARAM_VALUE.HDCP_VSYNC { PARAM_VALUE.HDCP_VSYNC } { 133 | # Procedure called to validate HDCP_VSYNC 134 | return true 135 | } 136 | 137 | proc update_PARAM_VALUE.HDCP_VSYNC_PULSE { PARAM_VALUE.HDCP_VSYNC_PULSE } { 138 | # Procedure called to update HDCP_VSYNC_PULSE when any of the dependent parameters in the arguments change 139 | } 140 | 141 | proc validate_PARAM_VALUE.HDCP_VSYNC_PULSE { PARAM_VALUE.HDCP_VSYNC_PULSE } { 142 | # Procedure called to validate HDCP_VSYNC_PULSE 143 | return true 144 | } 145 | 146 | proc update_PARAM_VALUE.HDCP_VSYNC_WAIT { PARAM_VALUE.HDCP_VSYNC_WAIT } { 147 | # Procedure called to update HDCP_VSYNC_WAIT when any of the dependent parameters in the arguments change 148 | } 149 | 150 | proc validate_PARAM_VALUE.HDCP_VSYNC_WAIT { PARAM_VALUE.HDCP_VSYNC_WAIT } { 151 | # Procedure called to validate HDCP_VSYNC_WAIT 152 | return true 153 | } 154 | 155 | proc update_PARAM_VALUE.HDCP_WAIT_1001 { PARAM_VALUE.HDCP_WAIT_1001 } { 156 | # Procedure called to update HDCP_WAIT_1001 when any of the dependent parameters in the arguments change 157 | } 158 | 159 | proc validate_PARAM_VALUE.HDCP_WAIT_1001 { PARAM_VALUE.HDCP_WAIT_1001 } { 160 | # Procedure called to validate HDCP_WAIT_1001 161 | return true 162 | } 163 | 164 | proc update_PARAM_VALUE.HDCP_WAIT_1001_END { PARAM_VALUE.HDCP_WAIT_1001_END } { 165 | # Procedure called to update HDCP_WAIT_1001_END when any of the dependent parameters in the arguments change 166 | } 167 | 168 | proc validate_PARAM_VALUE.HDCP_WAIT_1001_END { PARAM_VALUE.HDCP_WAIT_1001_END } { 169 | # Procedure called to validate HDCP_WAIT_1001_END 170 | return true 171 | } 172 | 173 | proc update_PARAM_VALUE.HDCP_WAIT_AKSV { PARAM_VALUE.HDCP_WAIT_AKSV } { 174 | # Procedure called to update HDCP_WAIT_AKSV when any of the dependent parameters in the arguments change 175 | } 176 | 177 | proc validate_PARAM_VALUE.HDCP_WAIT_AKSV { PARAM_VALUE.HDCP_WAIT_AKSV } { 178 | # Procedure called to validate HDCP_WAIT_AKSV 179 | return true 180 | } 181 | 182 | proc update_PARAM_VALUE.HDCP_WAIT_KMRDY { PARAM_VALUE.HDCP_WAIT_KMRDY } { 183 | # Procedure called to update HDCP_WAIT_KMRDY when any of the dependent parameters in the arguments change 184 | } 185 | 186 | proc validate_PARAM_VALUE.HDCP_WAIT_KMRDY { PARAM_VALUE.HDCP_WAIT_KMRDY } { 187 | # Procedure called to validate HDCP_WAIT_KMRDY 188 | return true 189 | } 190 | 191 | proc update_PARAM_VALUE.HDCP_nSTATES { PARAM_VALUE.HDCP_nSTATES } { 192 | # Procedure called to update HDCP_nSTATES when any of the dependent parameters in the arguments change 193 | } 194 | 195 | proc validate_PARAM_VALUE.HDCP_nSTATES { PARAM_VALUE.HDCP_nSTATES } { 196 | # Procedure called to validate HDCP_nSTATES 197 | return true 198 | } 199 | 200 | 201 | proc update_MODELPARAM_VALUE.HDCP_UNPLUG { MODELPARAM_VALUE.HDCP_UNPLUG PARAM_VALUE.HDCP_UNPLUG } { 202 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 203 | set_property value [get_property value ${PARAM_VALUE.HDCP_UNPLUG}] ${MODELPARAM_VALUE.HDCP_UNPLUG} 204 | } 205 | 206 | proc update_MODELPARAM_VALUE.HDCP_WAIT_AKSV { MODELPARAM_VALUE.HDCP_WAIT_AKSV PARAM_VALUE.HDCP_WAIT_AKSV } { 207 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 208 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_AKSV}] ${MODELPARAM_VALUE.HDCP_WAIT_AKSV} 209 | } 210 | 211 | proc update_MODELPARAM_VALUE.HDCP_AUTH_PULSE { MODELPARAM_VALUE.HDCP_AUTH_PULSE PARAM_VALUE.HDCP_AUTH_PULSE } { 212 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 213 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_PULSE}] ${MODELPARAM_VALUE.HDCP_AUTH_PULSE} 214 | } 215 | 216 | proc update_MODELPARAM_VALUE.HDCP_AUTH { MODELPARAM_VALUE.HDCP_AUTH PARAM_VALUE.HDCP_AUTH } { 217 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 218 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH}] ${MODELPARAM_VALUE.HDCP_AUTH} 219 | } 220 | 221 | proc update_MODELPARAM_VALUE.HDCP_AUTH_WAIT { MODELPARAM_VALUE.HDCP_AUTH_WAIT PARAM_VALUE.HDCP_AUTH_WAIT } { 222 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 223 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_WAIT}] ${MODELPARAM_VALUE.HDCP_AUTH_WAIT} 224 | } 225 | 226 | proc update_MODELPARAM_VALUE.HDCP_AUTH_VSYNC_PULSE { MODELPARAM_VALUE.HDCP_AUTH_VSYNC_PULSE PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE } { 227 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 228 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_VSYNC_PULSE}] ${MODELPARAM_VALUE.HDCP_AUTH_VSYNC_PULSE} 229 | } 230 | 231 | proc update_MODELPARAM_VALUE.HDCP_AUTH_VSYNC { MODELPARAM_VALUE.HDCP_AUTH_VSYNC PARAM_VALUE.HDCP_AUTH_VSYNC } { 232 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 233 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_VSYNC}] ${MODELPARAM_VALUE.HDCP_AUTH_VSYNC} 234 | } 235 | 236 | proc update_MODELPARAM_VALUE.HDCP_AUTH_VSYNC_WAIT { MODELPARAM_VALUE.HDCP_AUTH_VSYNC_WAIT PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT } { 237 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 238 | set_property value [get_property value ${PARAM_VALUE.HDCP_AUTH_VSYNC_WAIT}] ${MODELPARAM_VALUE.HDCP_AUTH_VSYNC_WAIT} 239 | } 240 | 241 | proc update_MODELPARAM_VALUE.HDCP_WAIT_1001 { MODELPARAM_VALUE.HDCP_WAIT_1001 PARAM_VALUE.HDCP_WAIT_1001 } { 242 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 243 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_1001}] ${MODELPARAM_VALUE.HDCP_WAIT_1001} 244 | } 245 | 246 | proc update_MODELPARAM_VALUE.HDCP_WAIT_1001_END { MODELPARAM_VALUE.HDCP_WAIT_1001_END PARAM_VALUE.HDCP_WAIT_1001_END } { 247 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 248 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_1001_END}] ${MODELPARAM_VALUE.HDCP_WAIT_1001_END} 249 | } 250 | 251 | proc update_MODELPARAM_VALUE.HDCP_VSYNC { MODELPARAM_VALUE.HDCP_VSYNC PARAM_VALUE.HDCP_VSYNC } { 252 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 253 | set_property value [get_property value ${PARAM_VALUE.HDCP_VSYNC}] ${MODELPARAM_VALUE.HDCP_VSYNC} 254 | } 255 | 256 | proc update_MODELPARAM_VALUE.HDCP_VSYNC_PULSE { MODELPARAM_VALUE.HDCP_VSYNC_PULSE PARAM_VALUE.HDCP_VSYNC_PULSE } { 257 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 258 | set_property value [get_property value ${PARAM_VALUE.HDCP_VSYNC_PULSE}] ${MODELPARAM_VALUE.HDCP_VSYNC_PULSE} 259 | } 260 | 261 | proc update_MODELPARAM_VALUE.HDCP_VSYNC_WAIT { MODELPARAM_VALUE.HDCP_VSYNC_WAIT PARAM_VALUE.HDCP_VSYNC_WAIT } { 262 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 263 | set_property value [get_property value ${PARAM_VALUE.HDCP_VSYNC_WAIT}] ${MODELPARAM_VALUE.HDCP_VSYNC_WAIT} 264 | } 265 | 266 | proc update_MODELPARAM_VALUE.HDCP_READY { MODELPARAM_VALUE.HDCP_READY PARAM_VALUE.HDCP_READY } { 267 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 268 | set_property value [get_property value ${PARAM_VALUE.HDCP_READY}] ${MODELPARAM_VALUE.HDCP_READY} 269 | } 270 | 271 | proc update_MODELPARAM_VALUE.HDCP_REKEY { MODELPARAM_VALUE.HDCP_REKEY PARAM_VALUE.HDCP_REKEY } { 272 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 273 | set_property value [get_property value ${PARAM_VALUE.HDCP_REKEY}] ${MODELPARAM_VALUE.HDCP_REKEY} 274 | } 275 | 276 | proc update_MODELPARAM_VALUE.HDCP_REKEY_PULSE { MODELPARAM_VALUE.HDCP_REKEY_PULSE PARAM_VALUE.HDCP_REKEY_PULSE } { 277 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 278 | set_property value [get_property value ${PARAM_VALUE.HDCP_REKEY_PULSE}] ${MODELPARAM_VALUE.HDCP_REKEY_PULSE} 279 | } 280 | 281 | proc update_MODELPARAM_VALUE.HDCP_REKEY_WAIT { MODELPARAM_VALUE.HDCP_REKEY_WAIT PARAM_VALUE.HDCP_REKEY_WAIT } { 282 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 283 | set_property value [get_property value ${PARAM_VALUE.HDCP_REKEY_WAIT}] ${MODELPARAM_VALUE.HDCP_REKEY_WAIT} 284 | } 285 | 286 | proc update_MODELPARAM_VALUE.HDCP_WAIT_KMRDY { MODELPARAM_VALUE.HDCP_WAIT_KMRDY PARAM_VALUE.HDCP_WAIT_KMRDY } { 287 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 288 | set_property value [get_property value ${PARAM_VALUE.HDCP_WAIT_KMRDY}] ${MODELPARAM_VALUE.HDCP_WAIT_KMRDY} 289 | } 290 | 291 | proc update_MODELPARAM_VALUE.HDCP_nSTATES { MODELPARAM_VALUE.HDCP_nSTATES PARAM_VALUE.HDCP_nSTATES } { 292 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 293 | set_property value [get_property value ${PARAM_VALUE.HDCP_nSTATES}] ${MODELPARAM_VALUE.HDCP_nSTATES} 294 | } 295 | 296 | -------------------------------------------------------------------------------- /hdcp_engine.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 109 | 110 | 111 | 112 | 113 | 115 | 116 | 117 | 118 | 119 | 127 | 128 | 129 | 130 | 131 | 134 | 135 | 137 | 138 | 140 | 141 | 143 | 144 | 146 | 147 | 149 | 150 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | --------------------------------------------------------------------------------