├── .gitattributes ├── .gitignore ├── LICENCE ├── README.md ├── atarimod ├── README.md ├── board │ ├── atarimod-cache.lib │ ├── atarimod-rescue.lib │ ├── atarimod.bak │ ├── atarimod.kicad_pcb │ ├── atarimod.kicad_pcb-bak │ ├── atarimod.net │ ├── atarimod.pro │ ├── atarimod.sch │ ├── atarimod.xml │ ├── components.bak │ ├── components.bck │ ├── components.dcm │ ├── components.lib │ ├── footprints.pretty │ │ └── socket_embedded_40pin.kicad_mod │ ├── fp-lib-table │ └── sym-lib-table ├── doc │ ├── COLORBAR.BAS │ ├── atarimod.pdf │ ├── bill_of_materials.txt │ ├── gerber.zip │ ├── modboards.jpg │ ├── overview.jpg │ └── pin_assignment.txt ├── firmware │ ├── atari_lumacode_1_0.pof │ ├── atari_lumacode_1_1.pof │ ├── atarimod_1_1.pof │ ├── atarimod_1_2.pof │ └── atarimod_1_3.pof ├── palette │ ├── Altirra Default NTSC.pal │ ├── Altirra Default NTSC.png │ ├── Altirra Default PAL.pal │ ├── Altirra Default PAL.png │ ├── Atari_800_NTSC.bin │ └── Atari_800_PAL.bin └── quartus │ ├── AtariMod.vhd │ ├── AtariMod.vhd.bak │ ├── AtariModLumacode.vhd │ ├── AtariModLumacode.vhd.bak │ ├── ClockMultiplier.vhd │ ├── ClockMultiplier.vhd.bak │ ├── ClockMultiplier6.vhd │ ├── ClockMultiplier6.vhd.bak │ ├── GTIA2YPbPr.vhd │ ├── GTIA2YPbPr.vhd.bak │ ├── GTIAEmulator.vhd │ ├── GTIAEmulator.vhd.bak │ ├── PLL171.cmp │ ├── PLL171.ppf │ ├── PLL171.qip │ ├── PLL171.vhd │ ├── PLL227.cmp │ ├── PLL227.ppf │ ├── PLL227.qip │ ├── PLL227.vhd │ ├── PLL228.cmp │ ├── PLL228.ppf │ ├── PLL228.qip │ ├── PLL228.vhd │ ├── Prog.cdf │ ├── Run.cdf │ ├── VideoRAM.cmp │ ├── VideoRAM.qip │ ├── VideoRAM.vhd │ ├── atarimod.qpf │ ├── atarimod.qsf │ ├── atarimod.qws │ ├── atarimod.sdc │ ├── atarimod.sdc.bak │ ├── atarimod_assignment_defaults.qdf │ └── greybox_tmp │ └── cbx_args.txt ├── board ├── board-cache.lib ├── board.bak ├── board.kicad_pcb ├── board.kicad_pcb-bak ├── board.net ├── board.pro ├── board.sch ├── board.xml ├── components.bak ├── components.bck ├── components.dcm ├── components.lib ├── footprints.pretty │ ├── FCI_10029449-11-5B13-5DRLF.kicad_mod │ ├── QFP_144_GND.kicad_mod │ ├── RCA_JACK.kicad_mod │ └── TrippleRCA.kicad_mod ├── fp-lib-table └── gerber │ ├── board-B.Cu.gbl │ ├── board-B.Mask.gbs │ ├── board-B.SilkS.gbo │ ├── board-Edge.Cuts.gm1 │ ├── board-F.Cu.gtl │ ├── board-F.Mask.gts │ ├── board-F.SilkS.gto │ ├── board.drl │ └── gerber.zip ├── c64mod ├── README.md ├── c128board │ ├── README.md │ ├── c128adapter_bom.ods │ ├── c128board-backups │ │ └── c128board-2023-06-27_154036.zip │ ├── c128board-cache.lib │ ├── c128board.bak │ ├── c128board.kicad_pcb │ ├── c128board.kicad_pcb-bak │ ├── c128board.kicad_prl │ ├── c128board.kicad_pro │ ├── c128board.net │ ├── c128board.pdf │ ├── c128board.pro │ ├── c128board.sch │ ├── footprints.pretty │ │ ├── socket_embedded_40pin.kicad_mod │ │ └── socket_embedded_48pin.kicad_mod │ ├── fp-lib-table │ ├── gerber.zip │ ├── parts.dcm │ ├── parts.lib │ └── sym-lib-table ├── c64board │ ├── c64board-backups │ │ └── c64board-2023-06-01_132559.zip │ ├── c64board-cache.lib │ ├── c64board.bak │ ├── c64board.kicad_pcb │ ├── c64board.kicad_pcb-bak │ ├── c64board.kicad_prl │ ├── c64board.kicad_pro │ ├── c64board.net │ ├── c64board.pro │ ├── c64board.sch │ ├── footprints.pretty │ │ └── socket_embedded_40pin.kicad_mod │ ├── fp-lib-table │ ├── parts.bck │ ├── parts.dcm │ ├── parts.lib │ └── sym-lib-table ├── doc │ ├── C64C_Service_Manual.pdf │ ├── adapterboard.jpg │ ├── adapterboard_bom.ods │ ├── c64board.pdf │ ├── connectors.jpg │ ├── dramrefreshpattern.txt │ ├── gerber.zip │ ├── modboards.jpg │ ├── mode_288p.jpg │ ├── mode_576p.jpg │ ├── mode_576p_scanlines.jpg │ └── vic-ii.txt ├── firmware │ ├── C64mod_2_10_beta1.pof │ ├── C64mod_2_10_beta2.pof │ ├── C64mod_2_10_beta3.pof │ ├── C64mod_2_11_LC.pof │ ├── C64mod_2_11_beta1.pof │ ├── C64mod_2_12.pof │ ├── C64mod_2_7.pof │ ├── C64mod_2_8_beta1.pof │ ├── C64mod_2_8_beta2.pof │ ├── C64mod_2_8_beta3.pof │ ├── C64mod_2_8_beta4.pof │ ├── C64mod_2_9.pof │ ├── C64mod_2_9_beta1.pof │ ├── C64mod_2_9_beta2.pof │ ├── C64mod_2_9_beta3.pof │ ├── C64mod_2_9_beta4.pof │ ├── C64mod_2_9_beta5.pof │ └── C64mod_2_9_beta6.pof ├── quartus │ ├── .qsys_edit │ │ ├── SETTINGSFLASH.xml │ │ ├── SETTINGSFLASH_schematic.nlv │ │ ├── filters.xml │ │ └── preferences.xml │ ├── C64mod.cdf │ ├── C64mod.ipregen.rpt │ ├── C64mod.qpf │ ├── C64mod.qsf │ ├── C64mod.qws │ ├── C64mod.vhd │ ├── C64mod.vhd.bak │ ├── C64modLumacode.vhd │ ├── C64modLumacode.vhd.bak │ ├── C64mod_assignment_defaults.qdf │ ├── ClockMultiplier.vhd │ ├── ClockMultiplier.vhd.bak │ ├── PLL252.cmp │ ├── PLL252.mif │ ├── PLL252.ppf │ ├── PLL252.qip │ ├── PLL252.vhd │ ├── PLL262.cmp │ ├── PLL262.mif │ ├── PLL262.ppf │ ├── PLL262.qip │ ├── PLL262.vhd │ ├── Prog.cdf │ ├── RSFlipFlop.vhd │ ├── RSFlipFlop.vhd.bak │ ├── Run.cdf │ ├── SETTINGSFLASH.BAK.qsys │ ├── SETTINGSFLASH.qsys │ ├── SETTINGSFLASH.sopcinfo │ ├── SETTINGSFLASH │ │ ├── SETTINGSFLASH.bsf │ │ ├── SETTINGSFLASH.cmp │ │ ├── SETTINGSFLASH.csv │ │ ├── SETTINGSFLASH.html │ │ ├── SETTINGSFLASH.ppf │ │ ├── SETTINGSFLASH.spd │ │ ├── SETTINGSFLASH.xml │ │ ├── SETTINGSFLASH_bb.v │ │ ├── SETTINGSFLASH_generation.rpt │ │ ├── SETTINGSFLASH_generation_previous.rpt │ │ ├── SETTINGSFLASH_inst.v │ │ ├── SETTINGSFLASH_inst.vhd │ │ ├── simulation │ │ │ ├── SETTINGSFLASH.sip │ │ │ ├── SETTINGSFLASH.vhd │ │ │ ├── aldec │ │ │ │ └── rivierapro_setup.tcl │ │ │ ├── cadence │ │ │ │ ├── cds.lib │ │ │ │ ├── cds_libs │ │ │ │ │ └── onchip_flash_0.cds.lib │ │ │ │ ├── hdl.var │ │ │ │ └── ncsim_setup.sh │ │ │ ├── mentor │ │ │ │ └── msim_setup.tcl │ │ │ ├── submodules │ │ │ │ ├── altera_onchip_flash.v │ │ │ │ ├── altera_onchip_flash_avmm_csr_controller.v │ │ │ │ ├── altera_onchip_flash_avmm_data_controller.v │ │ │ │ └── altera_onchip_flash_util.v │ │ │ └── synopsys │ │ │ │ └── vcsmx │ │ │ │ ├── synopsys_sim.setup │ │ │ │ └── vcsmx_setup.sh │ │ └── synthesis │ │ │ ├── SETTINGSFLASH.debuginfo │ │ │ ├── SETTINGSFLASH.qip │ │ │ ├── SETTINGSFLASH.vhd │ │ │ ├── SETTINGSFLASH.vhd.bak │ │ │ └── submodules │ │ │ ├── altera_onchip_flash.sdc │ │ │ ├── altera_onchip_flash.v │ │ │ ├── altera_onchip_flash_avmm_csr_controller.v │ │ │ ├── altera_onchip_flash_avmm_data_controller.v │ │ │ ├── altera_onchip_flash_util.v │ │ │ └── rtl │ │ │ └── altera_onchip_flash_block.v │ ├── Settings.vhd │ ├── Settings.vhd.bak │ ├── VIC2Emulation.vhd │ ├── VIC2Emulation.vhd.bak │ ├── VICTypes.vhd │ ├── VICTypes.vhd.bak │ ├── c64mod.sdc │ ├── c64mod.sdc.bak │ ├── defaultsettings.hex │ ├── greybox_tmp │ │ └── cbx_args.txt │ ├── ip_upgrade_port_diff_reports │ │ └── settingsflash.18_1.no_port_diff.rpt │ ├── ram_dual.vhd │ └── ram_dual.vhd.bak └── testsignal │ ├── Prog.cdf │ ├── README.md │ ├── box.jpg │ ├── testsignal.qpf │ ├── testsignal.qsf │ ├── testsignal.qws │ ├── testsignal.sdc │ ├── testsignal.sdc.bak │ ├── testsignal.vhd │ └── testsignal.vhd.bak ├── doc ├── backside.jpg ├── bill_of_materials.txt ├── frontside.jpg ├── pin_assignment.txt ├── resistors.ods ├── schematics.pdf └── videotimings.txt ├── quartus ├── PLL7_31.cmp ├── PLL7_31.ppf ├── PLL7_31.qip ├── PLL7_31.vhd ├── PLL8.cmp ├── PLL8.ppf ├── PLL8.qip ├── PLL8.vhd ├── PLL_14_387.cmp ├── PLL_14_387.ppf ├── PLL_14_387.qip ├── PLL_14_387.v ├── PLL_14_411.cmp ├── PLL_14_411.ppf ├── PLL_14_411.qip ├── PLL_14_411.v ├── PLL_14_625.cmp ├── PLL_14_625.ppf ├── PLL_14_625.qip ├── PLL_14_625.vhd ├── Program.cdf ├── Run.cdf ├── TestPattern.qws ├── TestPattern.vhd ├── TestPattern.vhd.bak ├── avideoboard.ipregen.rpt ├── avideoboard.qpf ├── avideoboard.qsf ├── avideoboard.qws ├── avideoboard.sdc └── avideoboard_assignment_defaults.qdf └── zxspectrummod ├── README.md ├── board ├── board-cache.lib ├── board.bak ├── board.kicad_pcb ├── board.kicad_pcb-bak ├── board.net ├── board.pro ├── board.sch ├── components.bak ├── components.bck ├── components.dcm ├── components.lib ├── fp-lib-table └── gerber │ ├── board-B.Cu.gbr │ ├── board-B.Mask.gbr │ ├── board-B.SilkS.gbr │ ├── board-Edge.Cuts.gbr │ ├── board-F.Cu.gbr │ ├── board-F.Mask.gbr │ ├── board-F.SilkS.gbr │ ├── board.drl │ └── gerber.zip ├── doc ├── assembly.jpg ├── board.pdf ├── closeup.jpg ├── closeup288p.jpg ├── connectors.jpg ├── game.jpg ├── game288p.jpg ├── modboard.jpg └── pin_assignment.txt ├── firmware └── zxspectrum_1_1.pof └── quartus ├── PLL4PHASES.cmp ├── PLL4PHASES.ppf ├── PLL4PHASES.qip ├── PLL4PHASES.vhd ├── Program.cdf ├── Run.cdf ├── ULA2YPbPr.vhd ├── ULA2YPbPr.vhd.bak ├── ZXVideoRAM.cmp ├── ZXVideoRAM.qip ├── ZXVideoRAM.vhd ├── greybox_tmp └── cbx_args.txt ├── zxspectrum.ipregen.rpt ├── zxspectrum.qpf ├── zxspectrum.qsf ├── zxspectrum.qws ├── zxspectrum.sdc ├── zxspectrum.sdc.bak └── zxspectrum_assignment_defaults.qdf /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Logs 2 | logs 3 | *.log 4 | npm-debug.log* 5 | 6 | # Runtime data 7 | pids 8 | *.pid 9 | *.seed 10 | 11 | # Directory for instrumented libs generated by jscoverage/JSCover 12 | lib-cov 13 | 14 | # Coverage directory used by tools like istanbul 15 | coverage 16 | 17 | # Grunt intermediate storage (http://gruntjs.com/creating-plugins#storing-task-files) 18 | .grunt 19 | 20 | # node-waf configuration 21 | .lock-wscript 22 | 23 | # Compiled binary addons (http://nodejs.org/api/addons.html) 24 | build/Release 25 | 26 | # Dependency directories 27 | node_modules 28 | jspm_packages 29 | 30 | # Optional npm cache directory 31 | .npm 32 | 33 | # Optional REPL history 34 | .node_repl_history 35 | 36 | # ========================= 37 | # Operating System Files 38 | # ========================= 39 | 40 | # OSX 41 | # ========================= 42 | 43 | .DS_Store 44 | .AppleDouble 45 | .LSOverride 46 | 47 | # Thumbnails 48 | ._* 49 | 50 | # Files that might appear in the root of a volume 51 | .DocumentRevisions-V100 52 | .fseventsd 53 | .Spotlight-V100 54 | .TemporaryItems 55 | .Trashes 56 | .VolumeIcon.icns 57 | 58 | # Directories potentially created on remote AFP share 59 | .AppleDB 60 | .AppleDesktop 61 | Network Trash Folder 62 | Temporary Items 63 | .apdisk 64 | 65 | # Windows 66 | # ========================= 67 | 68 | # Windows image file caches 69 | Thumbs.db 70 | ehthumbs.db 71 | 72 | # Folder config file 73 | Desktop.ini 74 | 75 | # Recycle Bin used on file shares 76 | $RECYCLE.BIN/ 77 | 78 | # Windows Installer files 79 | *.cab 80 | *.msi 81 | *.msm 82 | *.msp 83 | 84 | # Windows shortcuts 85 | *.lnk 86 | 87 | # Quartus II intermediate files 88 | */db 89 | */*/db 90 | */.qsys_edit 91 | */devkits 92 | */greybox_tmp 93 | */*/incremental_db 94 | */incremental_db 95 | */*/output_files 96 | */output_files 97 | */*/output_file.map 98 | 99 | **/rescue-backup -------------------------------------------------------------------------------- /LICENCE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2019 Reinhard Grafl 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 4 | 5 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # A-Video Board 2 | 3 | A small FPGA board with a component video interface to directly drive 4 | an analog monitor or TV input. 5 | Its main purpose is to create component video / RGB mods of vintage 6 | home computers and consoles or to provide video output for hobby projects. 7 | 8 | It consists of the purest minimum parts necessary to have a multi-purpose 9 | FPGA combined with a simple way to generate a YPbPr signal. After much research 10 | I finally settled on a cheap MAX 10 device in a TQFP-144 package which I can 11 | solder by hand (barely). The rest of the parts are pretty cheap and quite easy to solder. 12 | 13 | To interface any of the vintage systems to the A-Video Board, level shifters 14 | are necessary to translate the 5 volt to 3.3 volt for the FPGA input pins. These level 15 | shifters can be implemented in a system specific daughter board that can be stacked 16 | on top of the A-Video board. Any such interface board can probably be implemented in a 17 | simple single-sided wide-pitch PCB that can be even home-etched with some experience. 18 | 19 | Currently I have built applications of the A-Video board for 20 | * [Commodore 64](/c64mod) 21 | * [Atari 8 bit machines](/atarimod) 22 | * [ZX Spectrum](/zxspectrummod) 23 | 24 | ## Images 25 | ![alt text](doc/frontside.jpg "A-Video Board front") 26 | ![alt text](doc/backside.jpg "A-Video Board back") 27 | 28 | ## Board design 29 | 30 | The board has these main parts 31 | 32 | * 10M02SCE144: fairly cheap FPGA of the MAX10 series 33 | * LM1117IMPX-3.3: linear voltage regulator 34 | * LFSPX0024957: 25Mhz clock generator 35 | * THS7316: video output amplifier 36 | * R1-R19: three 5-bit DACs made from transistors 37 | 38 | and various supporting passive components, mainly decoupling, filtering and pull-ups. 39 | 40 | It has the following connectors: 41 | * GPIO1 20-pin header that directly connects to FPGA pins 42 | * GPIO2 10-pin header with two pins providing GND and +3.3V, the remaining 8 connect to the FPGA. 43 | * JTAG 10-pin header for programming the FPGA (via an USB-Blaster or compatible device) 44 | * 3 RCA sockets to output the video signal (normally YPbPr, but other formats could be produced as well). 45 | Note that in the schematics these sockets are denoted as BNC, but are actually RCA connectors of type 46 | RCJ-046 (green), RCJ-042 (red), RCJ-045 (blue). 47 | * GND, VIN Provide between 4.5V and 9V as supply voltage. The board consumes about 80mA. 48 | 49 | ## Contact 50 | If you plan to use an A-Video board, feel free to contact me for assistance: 51 | reinhard.grafl (at) aon.at 52 | Maybe I will either have some spare PCBs I could send you to populate yourself, 53 | or even provide you with a fully assembled board for the cost of the parts and shipping. 54 | -------------------------------------------------------------------------------- /atarimod/README.md: -------------------------------------------------------------------------------- 1 | # Atari RGB Mod 2 | 3 | Built on the A-Video board, this is a modification usable for Atari 8-bit 4 | computers that generate YPbPr signal in either 288p or 576p to display on 5 | modern displays. 6 | 7 | ## Motivation 8 | 9 | These old Atari computers generate the colour output signal directly in the weird way that was 10 | necessary to construct a PAL or NTSC signal. The technique is called "quadrature amplitude modulation" and has the 11 | disadvantage of not being completely reversible, so the original colours can not be reconstructed from this 12 | signal. 13 | Even worse, the XL line of machines does not even provide this signal directly on the video output, but 14 | only already combined with the luminance signal as composite video. There are simple ways to provide 15 | separate luminance and colour, but even then the quality is pretty bad. 16 | This was not such a problem on cathode ray tube (CRT) displays, but on modern LCD TVs this signal looks totally 17 | unusable. 18 | 19 | So, no matter how I tried, I could not reliably re-construct the original colours from the colour signal output. 20 | The only way to really solve the issue was to intercept the necessary information in digital form to 21 | create a perfectly sharp and clear analog video signal by my own circuitry. 22 | 23 | ## Theory of Operation 24 | 25 | The FPGA chip passively listens to all relevant pins of the GTIA graphics chip and re-implements the 26 | relevant logic of the GTIA in its logic fabric, effectively providing a second GTIA (parts of it). 27 | To sniff the signals from the GTIA, a specific adapter board is needed that sits between the 28 | GTIA and its socket. Revision 3 of the adapter is now pretty small and should fit in all Atari models. 29 | From this adapter, a 20-pin ribbon cable (either mounted permanently to the adapter or using a plug) 30 | leads to the FPGA board. 31 | This FPGA board can either be the generic A-Video board or a re-purposed C64 Video Enhancement Board. 32 | Both boards are firmeware-compatible, but differ in their size and connector options. You should 33 | also be able to fairly easily change these connectivity options anyway. 34 | 35 | 36 | ## Adapter building details (Rev. 3) 37 | 38 | In the doc folder, there are schematics, gerber files and a bill of material to build the adapter. 39 | Ideally you need a 0.8mm PCB (a slighly thicker boards will also work) and assemble everything except 40 | the P1 socket. This specific socket is meant to be put into the big holes, so the extra-long solder tails 41 | will stick out pretty far on the bottom side. These will then fit into the IC socket on the Atari. 42 | Take care not to get any solder onto these thin tails when soldering the ticker barrels into the 43 | adapter board (this can become tricky, but with a 0.8mm board it should not be too hard). 44 | Before actually soldering the socket you have to cut away one of the plastic cross-beams so it 45 | will not conflict with the ICs. 46 | 47 | For attaching the 20-pin ribbon cable to P2, you have several options. I used an angled 48 | pin-header with a standard ribbon cable connector to keep a low profile. If there is space 49 | in your device you can as well use a straight pain-header. An even more sophisticated option 50 | is a permantent PCB-to-ribbon-cable header which can be found with quite a low profile. 51 | You can even solder the ribbon cable wires direcly into the board or whatever you fancy. 52 | 53 | 54 | ## FPGA Details 55 | 56 | The FPGA on the A-Video board is programmed in VHDL, using the free version of the Quartus II development suite. 57 | This chip has an on-board non-volatile program memory, so no external flash is needed and the chip has 58 | a very short start-up time. There is a PLL built in which I use to generate a 228Mhz clock from the 25Mhz reference. 59 | With this 228Mhz and some advanced programming I can multiply the Atari pixel clock to a pretty clean (below 1 ns jitter) 14,1875 MHz clock to drive the whole circuit and create a nice output signal. 60 | 61 | On non-PAL machines the Atari pixel clock runs at a slightly different speed. There the clock multiplier circuit will actually produce an internal clock that has variations in their clock cycle length. This will lead 62 | to a slightly different length of every other pixel in 240p mode, and of every 4th pixel in 480p mode. 63 | 64 | 65 | ## Output 66 | 67 | The mod can be used to create three different output formats: 68 | * 240p/288p (default) 69 | * 480p/576p 70 | * 480p/576p with scanline effect 71 | 72 | Selecting the output can be done by jumper connectors or an external switch (already provided 73 | in the C64 Video Enhancement): 74 | * Connect GPIO2_4 to GND: 480p/576p 75 | * Connect GPIO2_5 or GPIO2_6 to GND: 480p/576p with scanline effect 76 | 77 | ## Images 78 | ![alt text](doc/modboards.jpg "Installation of the two mod boards (Adapter Rev.2)") 79 | ![alt text](doc/overview.jpg "Overview over the whole system") 80 | 81 | -------------------------------------------------------------------------------- /atarimod/board/atarimod.pro: -------------------------------------------------------------------------------- 1 | update=15.09.2020 15:54:31 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [general] 27 | version=1 28 | [eeschema] 29 | version=1 30 | LibDir= 31 | [schematic_editor] 32 | version=1 33 | PageLayoutDescrFile= 34 | PlotDirectoryName=../doc/ 35 | SubpartIdSeparator=0 36 | SubpartFirstId=65 37 | NetFmtName=Pcbnew 38 | SpiceAjustPassiveValues=0 39 | LabSize=60 40 | ERC_TestSimilarLabels=1 41 | -------------------------------------------------------------------------------- /atarimod/board/components.bak: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # 74HC14D 5 | # 6 | DEF 74HC14D IC 0 40 Y Y 1 F N 7 | F0 "IC" -50 50 60 H V C CNN 8 | F1 "74HC14D" 50 -50 60 H V C CNN 9 | F2 "" 50 0 60 H I C CNN 10 | F3 "" 50 0 60 H I C CNN 11 | DRAW 12 | S -200 -100 300 -800 0 1 0 N 13 | X 1A 1 -400 -250 200 R 50 50 1 1 I 14 | X 1Y 2 500 -250 200 L 50 50 1 1 O 15 | X 2A 3 -400 -350 200 R 50 50 1 1 I 16 | X 2Y 4 500 -350 200 L 50 50 1 1 O 17 | X 3A 5 -400 -450 200 R 50 50 1 1 I 18 | X 3Y 6 500 -450 200 L 50 50 1 1 O 19 | X GND 7 -400 -150 200 R 50 50 1 1 W 20 | X 4Y 8 500 -550 200 L 50 50 1 1 O 21 | X 4A 9 -400 -550 200 R 50 50 1 1 I 22 | X 5Y 10 500 -650 200 L 50 50 1 1 O 23 | X 5A 11 -400 -650 200 R 50 50 1 1 I 24 | X 6Y 12 500 -750 200 L 50 50 1 1 O 25 | X 6A 13 -400 -750 200 R 50 50 1 1 I 26 | X VCC 14 500 -150 200 L 50 50 1 1 W 27 | ENDDRAW 28 | ENDDEF 29 | # 30 | # GTIA 31 | # 32 | DEF GTIA U 0 40 Y Y 1 F N 33 | F0 "U" -100 -200 60 H V C CNN 34 | F1 "GTIA" 200 -200 60 H V C CNN 35 | F2 "" -100 -200 60 H I C CNN 36 | F3 "" -100 -200 60 H I C CNN 37 | DRAW 38 | S -200 -250 400 -2250 0 1 0 N 39 | X A1 1 -400 -300 200 R 50 50 1 1 O 40 | X A0 2 -400 -400 200 R 50 50 1 1 O 41 | X GND 3 -400 -500 200 R 50 50 1 1 W 42 | X D3 4 -400 -600 200 R 50 50 1 1 B 43 | X D2 5 -400 -700 200 R 50 50 1 1 B 44 | X D1 6 -400 -800 200 R 50 50 1 1 B 45 | X D0 7 -400 -900 200 R 50 50 1 1 B 46 | X T0 8 -400 -1000 200 R 50 50 1 1 I 47 | X T1 9 -400 -1100 200 R 50 50 1 1 I 48 | X T2 10 -400 -1200 200 R 50 50 1 1 I 49 | X AN2 20 -400 -2200 200 R 50 50 1 1 O 50 | X PHI2 30 600 -1300 200 L 50 50 1 1 O 51 | X A2 40 600 -300 200 L 50 50 1 1 O 52 | X T3 11 -400 -1300 200 R 50 50 1 1 I 53 | X COLOR 21 600 -2200 200 L 50 50 1 1 O 54 | X LUM0 31 600 -1200 200 L 50 50 1 1 O 55 | X S0 12 -400 -1400 200 R 50 50 1 1 I 56 | X LUM1 22 600 -2100 200 L 50 50 1 1 O 57 | X CS 32 600 -1100 200 L 50 50 1 1 O 58 | X S1 13 -400 -1500 200 R 50 50 1 1 I 59 | X LUM2 23 600 -2000 200 L 50 50 1 1 O 60 | X R/W 33 600 -1000 200 L 50 50 1 1 O 61 | X S2 14 -400 -1600 200 R 50 50 1 1 I 62 | X LUM3 24 600 -1900 200 L 50 50 1 1 I 63 | X D7 34 600 -900 200 L 50 50 1 1 B 64 | X S3 15 -400 -1700 200 R 50 50 1 1 I 65 | X CSYNC 25 600 -1800 200 L 50 50 1 1 O 66 | X D6 35 600 -800 200 L 50 50 1 1 B 67 | X PAL 16 -400 -1800 200 R 50 50 1 1 O 68 | X HALT 26 600 -1700 200 L 50 50 1 1 O 69 | X D5 36 600 -700 200 L 50 50 1 1 B 70 | X CAD3 17 -400 -1900 200 R 50 50 1 1 I 71 | X 5V 27 600 -1600 200 L 50 50 1 1 W 72 | X D4 37 600 -600 200 L 50 50 1 1 B 73 | X AN0 18 -400 -2000 200 R 50 50 1 1 O 74 | X OSC 28 600 -1500 200 L 50 50 1 1 I 75 | X A4 38 600 -500 200 L 50 50 1 1 O 76 | X AN1 19 -400 -2100 200 R 50 50 1 1 O 77 | X FOO 29 600 -1400 200 L 50 50 1 1 I 78 | X A3 39 600 -400 200 L 50 50 1 1 O 79 | ENDDRAW 80 | ENDDEF 81 | # 82 | #End Library 83 | -------------------------------------------------------------------------------- /atarimod/board/components.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /atarimod/board/components.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /atarimod/board/components.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # 74HC14D 5 | # 6 | DEF 74HC14D IC 0 40 Y Y 1 F N 7 | F0 "IC" -50 50 60 H V C CNN 8 | F1 "74HC14D" 50 -50 60 H V C CNN 9 | F2 "" 50 0 60 H I C CNN 10 | F3 "" 50 0 60 H I C CNN 11 | DRAW 12 | S -200 -100 300 -800 0 1 0 N 13 | X 1A 1 -400 -150 200 R 50 50 1 1 I 14 | X 1Y 2 -400 -250 200 R 50 50 1 1 O 15 | X 2A 3 -400 -350 200 R 50 50 1 1 I 16 | X 2Y 4 -400 -450 200 R 50 50 1 1 O 17 | X 3A 5 -400 -550 200 R 50 50 1 1 I 18 | X 3Y 6 -400 -650 200 R 50 50 1 1 O 19 | X GND 7 -400 -750 200 R 50 50 1 1 W 20 | X 4Y 8 500 -750 200 L 50 50 1 1 O 21 | X 4A 9 500 -650 200 L 50 50 1 1 I 22 | X 5Y 10 500 -550 200 L 50 50 1 1 O 23 | X 5A 11 500 -450 200 L 50 50 1 1 I 24 | X 6Y 12 500 -350 200 L 50 50 1 1 O 25 | X 6A 13 500 -250 200 L 50 50 1 1 I 26 | X VCC 14 500 -150 200 L 50 50 1 1 W 27 | ENDDRAW 28 | ENDDEF 29 | # 30 | # GTIA 31 | # 32 | DEF GTIA U 0 40 Y Y 1 F N 33 | F0 "U" -100 -200 60 H V C CNN 34 | F1 "GTIA" 200 -200 60 H V C CNN 35 | F2 "" -100 -200 60 H I C CNN 36 | F3 "" -100 -200 60 H I C CNN 37 | DRAW 38 | S -200 -250 400 -2250 0 1 0 N 39 | X A1 1 -400 -300 200 R 50 50 1 1 O 40 | X A0 2 -400 -400 200 R 50 50 1 1 O 41 | X GND 3 -400 -500 200 R 50 50 1 1 W 42 | X D3 4 -400 -600 200 R 50 50 1 1 B 43 | X D2 5 -400 -700 200 R 50 50 1 1 B 44 | X D1 6 -400 -800 200 R 50 50 1 1 B 45 | X D0 7 -400 -900 200 R 50 50 1 1 B 46 | X T0 8 -400 -1000 200 R 50 50 1 1 I 47 | X T1 9 -400 -1100 200 R 50 50 1 1 I 48 | X T2 10 -400 -1200 200 R 50 50 1 1 I 49 | X AN2 20 -400 -2200 200 R 50 50 1 1 O 50 | X PHI2 30 600 -1300 200 L 50 50 1 1 O 51 | X A2 40 600 -300 200 L 50 50 1 1 O 52 | X T3 11 -400 -1300 200 R 50 50 1 1 I 53 | X COLOR 21 600 -2200 200 L 50 50 1 1 O 54 | X LUM0 31 600 -1200 200 L 50 50 1 1 O 55 | X S0 12 -400 -1400 200 R 50 50 1 1 I 56 | X LUM1 22 600 -2100 200 L 50 50 1 1 O 57 | X CS 32 600 -1100 200 L 50 50 1 1 O 58 | X S1 13 -400 -1500 200 R 50 50 1 1 I 59 | X LUM2 23 600 -2000 200 L 50 50 1 1 O 60 | X R/W 33 600 -1000 200 L 50 50 1 1 O 61 | X S2 14 -400 -1600 200 R 50 50 1 1 I 62 | X LUM3 24 600 -1900 200 L 50 50 1 1 I 63 | X D7 34 600 -900 200 L 50 50 1 1 B 64 | X S3 15 -400 -1700 200 R 50 50 1 1 I 65 | X CSYNC 25 600 -1800 200 L 50 50 1 1 O 66 | X D6 35 600 -800 200 L 50 50 1 1 B 67 | X PAL 16 -400 -1800 200 R 50 50 1 1 O 68 | X HALT 26 600 -1700 200 L 50 50 1 1 O 69 | X D5 36 600 -700 200 L 50 50 1 1 B 70 | X CAD3 17 -400 -1900 200 R 50 50 1 1 I 71 | X 5V 27 600 -1600 200 L 50 50 1 1 W 72 | X D4 37 600 -600 200 L 50 50 1 1 B 73 | X AN0 18 -400 -2000 200 R 50 50 1 1 O 74 | X OSC 28 600 -1500 200 L 50 50 1 1 I 75 | X A4 38 600 -500 200 L 50 50 1 1 O 76 | X AN1 19 -400 -2100 200 R 50 50 1 1 O 77 | X FOO 29 600 -1400 200 L 50 50 1 1 I 78 | X A3 39 600 -400 200 L 50 50 1 1 O 79 | ENDDRAW 80 | ENDDEF 81 | # 82 | #End Library 83 | -------------------------------------------------------------------------------- /atarimod/board/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | ) 3 | -------------------------------------------------------------------------------- /atarimod/board/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name atarimod-rescue)(type Legacy)(uri ${KIPRJMOD}/atarimod-rescue.lib)(options "")(descr "")) 3 | (lib (name components)(type Legacy)(uri ${KIPRJMOD}/components.lib)(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /atarimod/doc/COLORBAR.BAS: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/doc/COLORBAR.BAS -------------------------------------------------------------------------------- /atarimod/doc/atarimod.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/doc/atarimod.pdf -------------------------------------------------------------------------------- /atarimod/doc/bill_of_materials.txt: -------------------------------------------------------------------------------- 1 | References Type Value/Part Number Size 2 | 3 | C1,C2 Ceramic Capacitor 1 uF 2012 metric 4 | C3,C4,C5,C6 Ceramic Capacitor 100 nF 1608 metric 5 | IC1,IC2,IC3,IC4 Schmitt-Trigger Inverter SN74LVC14ADBR SSOP-14 6 | P1 40-pin IC precision socket with long solder tails 111-93-640-41-001000 DIP 40 7 | P2 Pinheader/Ribbon cable connector any 2x20, 2.54mm 8 | R10 SMD Resistor 100 ohm 2012 metric 9 | U2 LDO Voltage Regulator 3.3V MIC5504-3.3YM5 SOT-23-5 10 | -------------------------------------------------------------------------------- /atarimod/doc/gerber.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/doc/gerber.zip -------------------------------------------------------------------------------- /atarimod/doc/modboards.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/doc/modboards.jpg -------------------------------------------------------------------------------- /atarimod/doc/overview.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/doc/overview.jpg -------------------------------------------------------------------------------- /atarimod/doc/pin_assignment.txt: -------------------------------------------------------------------------------- 1 | Pin assignments for the Atari mod 2 | 3 | GTIA pin Mod board out A-Video board MAX 10 pin 4 | A1 P2 1 GPIO1 1 74 5 | A2 P2 2 GPIO1 2 75 6 | A0 P2 3 GPIO1 3 76 7 | A3 P2 4 GPIO1 4 77 8 | D3 P2 5 GPIO1 5 78 9 | A4 P2 6 GPIO1 6 79 10 | D2 P2 7 GPIO1 7 80 11 | D4 P2 8 GPIO1 8 81 12 | D1 P2 9 GPIO1 9 87 13 | D5 P2 10 GPIO1 10 88 14 | D0 P2 11 GPIO1 11 91 15 | D6 P2 12 GPIO1 12 92 16 | AN0 P2 13 GPIO1 13 97 17 | D7 P2 14 GPIO1 14 98 18 | AN1 P2 15 GPIO1 15 99 19 | RW P2 16 GPIO1 16 100 20 | AN2 P2 17 GPIO1 17 101 21 | CS P2 18 GPIO1 18 103 22 | PHI2 P2 19 GPIO1 19 105 23 | HALT P2 20 GPIO1 20 106 24 | 25 | -------------------------------------------------------------------------------- /atarimod/firmware/atari_lumacode_1_0.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/firmware/atari_lumacode_1_0.pof -------------------------------------------------------------------------------- /atarimod/firmware/atari_lumacode_1_1.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/firmware/atari_lumacode_1_1.pof -------------------------------------------------------------------------------- /atarimod/firmware/atarimod_1_1.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/firmware/atarimod_1_1.pof -------------------------------------------------------------------------------- /atarimod/firmware/atarimod_1_2.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/firmware/atarimod_1_2.pof -------------------------------------------------------------------------------- /atarimod/firmware/atarimod_1_3.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/firmware/atarimod_1_3.pof -------------------------------------------------------------------------------- /atarimod/palette/Altirra Default NTSC.pal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/palette/Altirra Default NTSC.pal -------------------------------------------------------------------------------- /atarimod/palette/Altirra Default NTSC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/palette/Altirra Default NTSC.png -------------------------------------------------------------------------------- /atarimod/palette/Altirra Default PAL.pal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/palette/Altirra Default PAL.pal -------------------------------------------------------------------------------- /atarimod/palette/Altirra Default PAL.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/palette/Altirra Default PAL.png -------------------------------------------------------------------------------- /atarimod/palette/Atari_800_NTSC.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/palette/Atari_800_NTSC.bin -------------------------------------------------------------------------------- /atarimod/palette/Atari_800_PAL.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/palette/Atari_800_PAL.bin -------------------------------------------------------------------------------- /atarimod/quartus/ClockMultiplier.vhd: -------------------------------------------------------------------------------- 1 | 2 | 3 | library ieee; 4 | use ieee.numeric_std.all; 5 | use ieee.std_logic_1164.all; 6 | 7 | entity ClockMultiplier is 8 | port ( 9 | -- reference clock 10 | CLK25: in std_logic; 11 | -- atari pixel clock 12 | F0O: in std_logic; 13 | 14 | -- x4 times output clock 15 | CLK: out std_logic 16 | ); 17 | end entity; 18 | 19 | 20 | architecture immediate of ClockMultiplier is 21 | -- high-speed clock to generate synchronous clock from. this is done 22 | -- with 4 coupled signals that are 0,45,90,135 degree phase shifted to give 23 | -- 8 usable edges. 24 | signal CLK228A : std_logic; 25 | signal CLK228B : std_logic; 26 | signal CLK228C : std_logic; 27 | signal CLK228D : std_logic; 28 | 29 | component PLL228 is 30 | PORT 31 | ( 32 | inclk0 : IN STD_LOGIC ; 33 | c0 : OUT STD_LOGIC ; 34 | c1 : OUT STD_LOGIC ; 35 | c2 : OUT STD_LOGIC ; 36 | c3 : OUT STD_LOGIC 37 | ); 38 | end component; 39 | 40 | begin 41 | subdividerpll: PLL228 port map ( CLK25, CLK228A, CLK228B, CLK228C, CLK228D ); 42 | 43 | process (F0O, CLK228A, CLK228B, CLK228C, CLK228D) 44 | -- having 8 versions of the circuit running slightly 45 | -- time-shifted 46 | variable counter0 : integer range 0 to 15 := 0; 47 | variable counter1 : integer range 0 to 15 := 0; 48 | variable counter2 : integer range 0 to 15 := 0; 49 | variable counter3 : integer range 0 to 15 := 0; 50 | variable counter4 : integer range 0 to 15 := 0; 51 | variable counter5 : integer range 0 to 15 := 0; 52 | variable counter6 : integer range 0 to 15 := 0; 53 | variable counter7 : integer range 0 to 15 := 0; 54 | variable in0_clk : std_logic := '0'; 55 | variable in1_clk : std_logic := '0'; 56 | variable in2_clk : std_logic := '0'; 57 | variable in3_clk : std_logic := '0'; 58 | variable in4_clk : std_logic := '0'; 59 | variable in5_clk : std_logic := '0'; 60 | variable in6_clk : std_logic := '0'; 61 | variable in7_clk : std_logic := '0'; 62 | variable prev0_clk : std_logic := '0'; 63 | variable prev1_clk : std_logic := '0'; 64 | variable prev2_clk : std_logic := '0'; 65 | variable prev3_clk : std_logic := '0'; 66 | variable prev4_clk : std_logic := '0'; 67 | variable prev5_clk : std_logic := '0'; 68 | variable prev6_clk : std_logic := '0'; 69 | variable prev7_clk : std_logic := '0'; 70 | 71 | variable bits : std_logic_vector(3 downto 0); 72 | constant reset: integer := 4; 73 | begin 74 | 75 | if rising_edge(CLK228A) then 76 | if in0_clk='0' and prev0_clk='1' then 77 | counter0 := reset; 78 | else 79 | counter0 := counter0+1; 80 | end if; 81 | prev0_clk := in0_clk; 82 | in0_clk := F0O; 83 | end if; 84 | if rising_edge(CLK228B) then 85 | if in1_clk='0' and prev1_clk='1' then 86 | counter1 := reset; 87 | else 88 | counter1 := counter1+1; 89 | end if; 90 | prev1_clk := in1_clk; 91 | in1_clk := F0O; 92 | end if; 93 | if rising_edge(CLK228C) then 94 | if in2_clk='0' and prev2_clk='1' then 95 | counter2 := reset; 96 | else 97 | counter2 := counter2+1; 98 | end if; 99 | prev2_clk := in2_clk; 100 | in2_clk := F0O; 101 | end if; 102 | if rising_edge(CLK228D) then 103 | if in3_clk='0' and prev3_clk='1' then 104 | counter3 := reset; 105 | else 106 | counter3 := counter3+1; 107 | end if; 108 | prev3_clk := in3_clk; 109 | in3_clk := F0O; 110 | end if; 111 | if falling_edge(CLK228A) then 112 | if in4_clk='0' and prev4_clk='1' then 113 | counter4 := reset; 114 | else 115 | counter4 := counter4+1; 116 | end if; 117 | prev4_clk := in4_clk; 118 | in4_clk := F0O; 119 | end if; 120 | if falling_edge(CLK228B) then 121 | if in5_clk='0' and prev5_clk='1' then 122 | counter5 := reset; 123 | else 124 | counter5 := counter5+1; 125 | end if; 126 | prev5_clk := in5_clk; 127 | in5_clk := F0O; 128 | end if; 129 | if falling_edge(CLK228C) then 130 | if in6_clk='0' and prev6_clk='1' then 131 | counter6 := reset; 132 | else 133 | counter6 := counter6+1; 134 | end if; 135 | prev6_clk := in6_clk; 136 | in6_clk := F0O; 137 | end if; 138 | if falling_edge(CLK228D) then 139 | if in7_clk='0' and prev7_clk='1' then 140 | counter7 := reset; 141 | else 142 | counter7 := counter7+1; 143 | end if; 144 | prev7_clk := in7_clk; 145 | in7_clk := F0O; 146 | end if; 147 | 148 | -- merge clock counters asynchronously 149 | bits:= std_logic_vector 150 | ( to_unsigned(counter0,4) 151 | or to_unsigned(counter1,4) 152 | or to_unsigned(counter2,4) 153 | or to_unsigned(counter3,4) 154 | or to_unsigned(counter4,4) 155 | or to_unsigned(counter5,4) 156 | or to_unsigned(counter6,4) 157 | or to_unsigned(counter7,4) 158 | ); 159 | 160 | CLK <= bits(3); 161 | end process; 162 | 163 | end immediate; 164 | 165 | -------------------------------------------------------------------------------- /atarimod/quartus/ClockMultiplier6.vhd.bak: -------------------------------------------------------------------------------- 1 | 2 | 3 | library ieee; 4 | use ieee.numeric_std.all; 5 | use ieee.std_logic_1164.all; 6 | 7 | entity ClockMultiplier is 8 | port ( 9 | -- reference clock 10 | CLK25: in std_logic; 11 | -- atari pixel clock 12 | F0O: in std_logic; 13 | 14 | -- x4 times output clock 15 | CLK: out std_logic 16 | ); 17 | end entity; 18 | 19 | 20 | architecture immediate of ClockMultiplier is 21 | -- high-speed clock to generate synchronous clock from. this is done 22 | -- with 4 coupled signals that are 0,45,90,135 degree phase shifted to give 23 | -- 8 usable edges. 24 | signal CLK228A : std_logic; 25 | signal CLK228B : std_logic; 26 | signal CLK228C : std_logic; 27 | signal CLK228D : std_logic; 28 | 29 | component PLL228 is 30 | PORT 31 | ( 32 | inclk0 : IN STD_LOGIC ; 33 | c0 : OUT STD_LOGIC ; 34 | c1 : OUT STD_LOGIC ; 35 | c2 : OUT STD_LOGIC ; 36 | c3 : OUT STD_LOGIC 37 | ); 38 | end component; 39 | 40 | begin 41 | subdividerpll: PLL228 port map ( CLK25, CLK228A, CLK228B, CLK228C, CLK228D ); 42 | 43 | process (F0O, CLK228A, CLK228B, CLK228C, CLK228D) 44 | -- having 8 versions of the circuit running slightly 45 | -- time-shifted 46 | variable counter0 : integer range 0 to 15 := 0; 47 | variable counter1 : integer range 0 to 15 := 0; 48 | variable counter2 : integer range 0 to 15 := 0; 49 | variable counter3 : integer range 0 to 15 := 0; 50 | variable counter4 : integer range 0 to 15 := 0; 51 | variable counter5 : integer range 0 to 15 := 0; 52 | variable counter6 : integer range 0 to 15 := 0; 53 | variable counter7 : integer range 0 to 15 := 0; 54 | variable in0_clk : std_logic := '0'; 55 | variable in1_clk : std_logic := '0'; 56 | variable in2_clk : std_logic := '0'; 57 | variable in3_clk : std_logic := '0'; 58 | variable in4_clk : std_logic := '0'; 59 | variable in5_clk : std_logic := '0'; 60 | variable in6_clk : std_logic := '0'; 61 | variable in7_clk : std_logic := '0'; 62 | variable prev0_clk : std_logic := '0'; 63 | variable prev1_clk : std_logic := '0'; 64 | variable prev2_clk : std_logic := '0'; 65 | variable prev3_clk : std_logic := '0'; 66 | variable prev4_clk : std_logic := '0'; 67 | variable prev5_clk : std_logic := '0'; 68 | variable prev6_clk : std_logic := '0'; 69 | variable prev7_clk : std_logic := '0'; 70 | 71 | variable bits : std_logic_vector(3 downto 0); 72 | constant reset: integer := 4; 73 | begin 74 | 75 | if rising_edge(CLK228A) then 76 | if in0_clk='0' and prev0_clk='1' then 77 | counter0 := reset; 78 | else 79 | counter0 := counter0+1; 80 | end if; 81 | prev0_clk := in0_clk; 82 | in0_clk := F0O; 83 | end if; 84 | if rising_edge(CLK228B) then 85 | if in1_clk='0' and prev1_clk='1' then 86 | counter1 := reset; 87 | else 88 | counter1 := counter1+1; 89 | end if; 90 | prev1_clk := in1_clk; 91 | in1_clk := F0O; 92 | end if; 93 | if rising_edge(CLK228C) then 94 | if in2_clk='0' and prev2_clk='1' then 95 | counter2 := reset; 96 | else 97 | counter2 := counter2+1; 98 | end if; 99 | prev2_clk := in2_clk; 100 | in2_clk := F0O; 101 | end if; 102 | if rising_edge(CLK228D) then 103 | if in3_clk='0' and prev3_clk='1' then 104 | counter3 := reset; 105 | else 106 | counter3 := counter3+1; 107 | end if; 108 | prev3_clk := in3_clk; 109 | in3_clk := F0O; 110 | end if; 111 | if falling_edge(CLK228A) then 112 | if in4_clk='0' and prev4_clk='1' then 113 | counter4 := reset; 114 | else 115 | counter4 := counter4+1; 116 | end if; 117 | prev4_clk := in4_clk; 118 | in4_clk := F0O; 119 | end if; 120 | if falling_edge(CLK228B) then 121 | if in5_clk='0' and prev5_clk='1' then 122 | counter5 := reset; 123 | else 124 | counter5 := counter5+1; 125 | end if; 126 | prev5_clk := in5_clk; 127 | in5_clk := F0O; 128 | end if; 129 | if falling_edge(CLK228C) then 130 | if in6_clk='0' and prev6_clk='1' then 131 | counter6 := reset; 132 | else 133 | counter6 := counter6+1; 134 | end if; 135 | prev6_clk := in6_clk; 136 | in6_clk := F0O; 137 | end if; 138 | if falling_edge(CLK228D) then 139 | if in7_clk='0' and prev7_clk='1' then 140 | counter7 := reset; 141 | else 142 | counter7 := counter7+1; 143 | end if; 144 | prev7_clk := in7_clk; 145 | in7_clk := F0O; 146 | end if; 147 | 148 | -- merge clock counters asynchronously 149 | bits:= std_logic_vector 150 | ( to_unsigned(counter0,4) 151 | or to_unsigned(counter1,4) 152 | or to_unsigned(counter2,4) 153 | or to_unsigned(counter3,4) 154 | or to_unsigned(counter4,4) 155 | or to_unsigned(counter5,4) 156 | or to_unsigned(counter6,4) 157 | or to_unsigned(counter7,4) 158 | ); 159 | 160 | CLK <= bits(3); 161 | end process; 162 | 163 | end immediate; 164 | 165 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL171.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL171 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC ; 21 | c1 : OUT STD_LOGIC ; 22 | c2 : OUT STD_LOGIC ; 23 | c3 : OUT STD_LOGIC 24 | ); 25 | end component; 26 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL171.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL171.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL171.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL171.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL171.ppf"] 7 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL227.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, the Altera Quartus Prime License Agreement, 9 | --the Altera MegaCore Function License Agreement, or other 10 | --applicable license agreement, including, without limitation, 11 | --that your use is for the sole purpose of programming logic 12 | --devices manufactured by Altera and sold by Altera or its 13 | --authorized distributors. Please refer to the applicable 14 | --agreement for further details. 15 | 16 | 17 | component PLL227 18 | PORT 19 | ( 20 | inclk0 : IN STD_LOGIC := '0'; 21 | c0 : OUT STD_LOGIC ; 22 | c1 : OUT STD_LOGIC 23 | ); 24 | end component; 25 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL227.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL227.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "16.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL227.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL227.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL227.ppf"] 7 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL228.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL228 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC ; 21 | c1 : OUT STD_LOGIC ; 22 | c2 : OUT STD_LOGIC ; 23 | c3 : OUT STD_LOGIC 24 | ); 25 | end component; 26 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL228.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /atarimod/quartus/PLL228.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL228.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL228.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL228.ppf"] 7 | -------------------------------------------------------------------------------- /atarimod/quartus/Prog.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/atarimod/quartus/output_files/") File("atarimod.pof") MfrSpec(OpMask(3) Child_OpMask(2 3 3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /atarimod/quartus/Run.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/atarimod/quartus/output_files/") File("atarimod.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /atarimod/quartus/VideoRAM.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component VideoRAM 17 | PORT 18 | ( 19 | clock : IN STD_LOGIC := '1'; 20 | data : IN STD_LOGIC_VECTOR (14 DOWNTO 0); 21 | rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 22 | wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 23 | wren : IN STD_LOGIC := '0'; 24 | q : OUT STD_LOGIC_VECTOR (14 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /atarimod/quartus/VideoRAM.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "VideoRAM.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "VideoRAM.cmp"] 6 | -------------------------------------------------------------------------------- /atarimod/quartus/atarimod.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 22:46:18 February 07, 2018 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.0" 27 | DATE = "22:46:18 February 07, 2018" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "atarimod" 32 | -------------------------------------------------------------------------------- /atarimod/quartus/atarimod.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/atarimod/quartus/atarimod.qws -------------------------------------------------------------------------------- /atarimod/quartus/atarimod.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 40.000 -name clk25 [get_ports {CLK25}] 2 | create_clock -period 70.000 -name clksync [get_registers {ClockMultiplier:multi|counter0[3]}] 3 | derive_pll_clocks 4 | 5 | -------------------------------------------------------------------------------- /atarimod/quartus/atarimod.sdc.bak: -------------------------------------------------------------------------------- 1 | create_clock -period 100.000 -name clkatari [get_ports {GPIO1(2)}] 2 | derive_pll_clocks 3 | -------------------------------------------------------------------------------- /atarimod/quartus/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | BANDWIDTH_TYPE=AUTO 2 | CLK0_DIVIDE_BY=25 3 | CLK0_DUTY_CYCLE=50 4 | CLK0_MULTIPLY_BY=171 5 | CLK0_PHASE_SHIFT=0 6 | CLK1_DIVIDE_BY=25 7 | CLK1_DUTY_CYCLE=50 8 | CLK1_MULTIPLY_BY=171 9 | CLK1_PHASE_SHIFT=731 10 | CLK2_DIVIDE_BY=25 11 | CLK2_DUTY_CYCLE=50 12 | CLK2_MULTIPLY_BY=171 13 | CLK2_PHASE_SHIFT=1462 14 | CLK3_DIVIDE_BY=25 15 | CLK3_DUTY_CYCLE=50 16 | CLK3_MULTIPLY_BY=171 17 | CLK3_PHASE_SHIFT=2193 18 | COMPENSATE_CLOCK=CLK0 19 | INCLK0_INPUT_FREQUENCY=40000 20 | INTENDED_DEVICE_FAMILY="MAX 10" 21 | LPM_TYPE=altpll 22 | OPERATION_MODE=NORMAL 23 | PLL_TYPE=AUTO 24 | PORT_ACTIVECLOCK=PORT_UNUSED 25 | PORT_ARESET=PORT_UNUSED 26 | PORT_CLKBAD0=PORT_UNUSED 27 | PORT_CLKBAD1=PORT_UNUSED 28 | PORT_CLKLOSS=PORT_UNUSED 29 | PORT_CLKSWITCH=PORT_UNUSED 30 | PORT_CONFIGUPDATE=PORT_UNUSED 31 | PORT_FBIN=PORT_UNUSED 32 | PORT_INCLK0=PORT_USED 33 | PORT_INCLK1=PORT_UNUSED 34 | PORT_LOCKED=PORT_UNUSED 35 | PORT_PFDENA=PORT_UNUSED 36 | PORT_PHASECOUNTERSELECT=PORT_UNUSED 37 | PORT_PHASEDONE=PORT_UNUSED 38 | PORT_PHASESTEP=PORT_UNUSED 39 | PORT_PHASEUPDOWN=PORT_UNUSED 40 | PORT_PLLENA=PORT_UNUSED 41 | PORT_SCANACLR=PORT_UNUSED 42 | PORT_SCANCLK=PORT_UNUSED 43 | PORT_SCANCLKENA=PORT_UNUSED 44 | PORT_SCANDATA=PORT_UNUSED 45 | PORT_SCANDATAOUT=PORT_UNUSED 46 | PORT_SCANDONE=PORT_UNUSED 47 | PORT_SCANREAD=PORT_UNUSED 48 | PORT_SCANWRITE=PORT_UNUSED 49 | PORT_clk0=PORT_USED 50 | PORT_clk1=PORT_USED 51 | PORT_clk2=PORT_USED 52 | PORT_clk3=PORT_USED 53 | PORT_clk4=PORT_UNUSED 54 | PORT_clk5=PORT_UNUSED 55 | PORT_clkena0=PORT_UNUSED 56 | PORT_clkena1=PORT_UNUSED 57 | PORT_clkena2=PORT_UNUSED 58 | PORT_clkena3=PORT_UNUSED 59 | PORT_clkena4=PORT_UNUSED 60 | PORT_clkena5=PORT_UNUSED 61 | PORT_extclk0=PORT_UNUSED 62 | PORT_extclk1=PORT_UNUSED 63 | PORT_extclk2=PORT_UNUSED 64 | PORT_extclk3=PORT_UNUSED 65 | WIDTH_CLOCK=5 66 | DEVICE_FAMILY="MAX 10" 67 | CBX_AUTO_BLACKBOX=ALL 68 | inclk 69 | inclk 70 | clk 71 | clk 72 | clk 73 | clk 74 | -------------------------------------------------------------------------------- /board/board.pro: -------------------------------------------------------------------------------- 1 | update=03/03/2017 15:27:49 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [general] 27 | version=1 28 | [eeschema] 29 | version=1 30 | LibDir=../dvideoboard 31 | [eeschema/libraries] 32 | LibName1=power 33 | LibName2=device 34 | LibName3=transistors 35 | LibName4=conn 36 | LibName5=linear 37 | LibName6=regul 38 | LibName7=74xx 39 | LibName8=cmos4000 40 | LibName9=adc-dac 41 | LibName10=memory 42 | LibName11=xilinx 43 | LibName12=microcontrollers 44 | LibName13=dsp 45 | LibName14=microchip 46 | LibName15=analog_switches 47 | LibName16=motorola 48 | LibName17=texas 49 | LibName18=intel 50 | LibName19=audio 51 | LibName20=interface 52 | LibName21=digital-audio 53 | LibName22=philips 54 | LibName23=display 55 | LibName24=cypress 56 | LibName25=siliconi 57 | LibName26=opto 58 | LibName27=atmel 59 | LibName28=contrib 60 | LibName29=valves 61 | LibName30=components 62 | [schematic_editor] 63 | version=1 64 | PageLayoutDescrFile= 65 | PlotDirectoryName= 66 | SubpartIdSeparator=0 67 | SubpartFirstId=65 68 | NetFmtName=Pcbnew 69 | SpiceForceRefPrefix=0 70 | SpiceUseNetNumbers=0 71 | LabSize=60 72 | -------------------------------------------------------------------------------- /board/components.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /board/components.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /board/footprints.pretty/FCI_10029449-11-5B13-5DRLF.kicad_mod: -------------------------------------------------------------------------------- 1 | (module FCI_10029449-11-5B13-5DRLF (layer F.Cu) (tedit 58BAC508) 2 | (fp_text reference FCI_10029449-11[13]RLF (at 0 0) (layer F.SilkS) 3 | (effects (font (size 1.5 1.5) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0 0) (layer F.SilkS) 6 | (effects (font (size 1.5 1.5) (thickness 0.15))) 7 | ) 8 | (fp_line (start -7.5 8.47) (end -7.5 6.3) (layer F.SilkS) (width 0.2032)) 9 | (fp_line (start 7.5 8.47) (end 7.5 6.3) (layer F.SilkS) (width 0.2032)) 10 | (fp_line (start 7.5 8.47) (end -7.5 8.47) (layer F.SilkS) (width 0.2032)) 11 | (pad SHLD thru_hole circle (at -7.85 4.95) (size 2 2) (drill 1.3) (layers *.Cu *.SilkS *.Mask)) 12 | (pad SHLD thru_hole circle (at 7.85 4.95) (size 2 2) (drill 1.3) (layers *.Cu *.SilkS *.Mask)) 13 | (pad SHLD thru_hole circle (at -7.25 0) (size 2 2) (drill 1.3) (layers *.Cu *.SilkS *.Mask)) 14 | (pad SHLD thru_hole circle (at 7.25 0) (size 2 2) (drill 1.3) (layers *.Cu *.SilkS *.Mask)) 15 | (pad 1 smd rect (at 4.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at 4.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 17 | (pad 3 smd rect (at 3.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 18 | (pad 4 smd rect (at 3.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 19 | (pad 5 smd rect (at 2.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 20 | (pad 6 smd rect (at 2.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 21 | (pad 7 smd rect (at 1.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 22 | (pad 8 smd rect (at 1.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 23 | (pad 9 smd rect (at 0.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 24 | (pad 10 smd rect (at 0.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 25 | (pad 11 smd rect (at -0.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 26 | (pad 12 smd rect (at -0.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 27 | (pad 13 smd rect (at -1.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 28 | (pad 14 smd rect (at -1.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 29 | (pad 15 smd rect (at -2.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 30 | (pad 16 smd rect (at -2.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 31 | (pad 17 smd rect (at -3.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 32 | (pad 18 smd rect (at -3.75 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 33 | (pad 19 smd rect (at -4.25 -0.9) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 34 | ) 35 | -------------------------------------------------------------------------------- /board/footprints.pretty/RCA_JACK.kicad_mod: -------------------------------------------------------------------------------- 1 | (module RCA_JACK (layer F.Cu) (tedit 5A1B2110) 2 | (fp_text reference REF** (at -5 2) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value RCA_JACK (at -5 -2) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start 0 5.1) (end -1.7 5.1) (layer F.SilkS) (width 0.1)) 9 | (fp_line (start -1.7 5.1) (end -1.7 3.4) (layer F.SilkS) (width 0.1)) 10 | (fp_line (start -1.7 3.4) (end 0 3.4) (layer F.SilkS) (width 0.1)) 11 | (fp_line (start 0 -5.1) (end -1.7 -5.1) (layer F.SilkS) (width 0.1)) 12 | (fp_line (start -1.7 -5.1) (end -1.7 -3.4) (layer F.SilkS) (width 0.1)) 13 | (fp_line (start -1.7 -3.4) (end 0 -3.4) (layer F.SilkS) (width 0.1)) 14 | (fp_line (start -1.7 -5) (end -1.7 -4.1) (layer F.SilkS) (width 0.1)) 15 | (fp_line (start 0 0) (end 0 -5) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start 0 -5) (end -10 -5) (layer F.SilkS) (width 0.15)) 17 | (fp_line (start -10 -5) (end -10 5) (layer F.SilkS) (width 0.15)) 18 | (fp_line (start -10 5) (end 0 5) (layer F.SilkS) (width 0.15)) 19 | (fp_line (start 0 5) (end 0 0) (layer F.SilkS) (width 0.15)) 20 | (pad 2 thru_hole oval (at -4 0) (size 1.9 4) (drill oval 1.3 3.4) (layers *.Cu *.Mask)) 21 | (pad 1 thru_hole oval (at -8.5 0) (size 2.9 1.6) (drill oval 2.3 1) (layers *.Cu *.Mask)) 22 | ) 23 | -------------------------------------------------------------------------------- /board/footprints.pretty/TrippleRCA.kicad_mod: -------------------------------------------------------------------------------- 1 | (module TrippleRCA (layer F.Cu) (tedit 59EA5391) 2 | (fp_text reference REF** (at 3 1.75) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value TrippleRCA (at -5.5 1.75) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start 9 0) (end 9 -8) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 9 -8) (end 19 -8) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 19 -8) (end 19 0) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -9 0) (end -9 -8) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -9 -8) (end -19 -8) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -19 -8) (end -19 0) (layer F.SilkS) (width 0.15)) 14 | (fp_line (start 5 0) (end 5 -8) (layer F.SilkS) (width 0.15)) 15 | (fp_line (start 5 -8) (end -5 -8) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start -5 -8) (end -5 0) (layer F.SilkS) (width 0.15)) 17 | (fp_line (start -21 0) (end -21 12.5) (layer F.SilkS) (width 0.15)) 18 | (fp_line (start -21 12.5) (end 21 12.5) (layer F.SilkS) (width 0.15)) 19 | (fp_line (start 21 12.5) (end 21 0) (layer F.SilkS) (width 0.15)) 20 | (fp_line (start 21 0) (end -21 0) (layer F.SilkS) (width 0.15)) 21 | (fp_line (start -5.25 0) (end 6 0) (layer F.SilkS) (width 0.15)) 22 | (pad "" np_thru_hole circle (at -20.6 8.875) (size 4 4) (drill 3.5) (layers *.Cu *.Mask)) 23 | (pad "" np_thru_hole circle (at 20.6 8.875) (size 4 4) (drill 3.5) (layers *.Cu *.Mask)) 24 | (pad 3 thru_hole circle (at 3.75 12.5) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) 25 | (pad 4 thru_hole circle (at 3.75 5.25) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) 26 | (pad 5 thru_hole circle (at 17.75 12.5) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) 27 | (pad 6 thru_hole circle (at 17.75 5.25) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) 28 | (pad 1 thru_hole circle (at -10.25 12.5) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) 29 | (pad 2 thru_hole circle (at -10.25 5.25) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) 30 | ) 31 | -------------------------------------------------------------------------------- /board/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name footprints)(type KiCad)(uri ${KIPRJMOD}/footprints.pretty)(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /board/gerber/board-Edge.Cuts.gm1: -------------------------------------------------------------------------------- 1 | G04 #@! TF.FileFunction,Profile,NP* 2 | %FSLAX46Y46*% 3 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 4 | G04 Created by KiCad (PCBNEW 4.0.4-stable) date 12/09/17 18:10:45* 5 | %MOMM*% 6 | %LPD*% 7 | G01* 8 | G04 APERTURE LIST* 9 | %ADD10C,0.100000*% 10 | %ADD11C,0.150000*% 11 | G04 APERTURE END LIST* 12 | D10* 13 | D11* 14 | X157480000Y-93726000D02* 15 | X157480000Y-93472000D01* 16 | X157480000Y-81026000D02* 17 | X157480000Y-80772000D01* 18 | X157480000Y-89408000D02* 19 | X157480000Y-89154000D01* 20 | X157480000Y-102108000D02* 21 | X157480000Y-101854000D01* 22 | X157480000Y-106426000D02* 23 | X157480000Y-106172000D01* 24 | X157480000Y-114554000D02* 25 | X157480000Y-114808000D01* 26 | X157480000Y-114808000D02* 27 | G75* 28 | G03X158242000Y-115570000I762000J0D01* 29 | G01* 30 | X158242000Y-113792000D02* 31 | G75* 32 | G03X157480000Y-114554000I0J-762000D01* 33 | G01* 34 | X157480000Y-106426000D02* 35 | G75* 36 | G03X158242000Y-107188000I762000J0D01* 37 | G01* 38 | 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/board/gerber/gerber.zip -------------------------------------------------------------------------------- /c64mod/README.md: -------------------------------------------------------------------------------- 1 | # C64 RGB Mod 2 | 3 | Built on the A-Video board, this is a modification usable for the Commodore 64 computer 4 | that generates a YPbPr signal in either 288p or 576p to display on modern displays. 5 | 6 | ## Motivation 7 | 8 | I wanted to get the most perfect display from an original C64 computer. After many failed attempts to 9 | reconstruct a digitally perfect pixel-by-pixel display from the S-Video output, I finally came back 10 | to my original idea to emulate the inner workings of the VIC-II chip. 11 | So, as for the atari 8-bit line and the ZX Spectrum, I applied my trusty A-Video board. 12 | 13 | ## Building details 14 | 15 | The FPGA chip passively listens to all relevant pins of the VIC graphics chip and re-implements the 16 | relevant logic of the GTIA in its logic fabric, effectively providing a second VIC (parts of it). 17 | The mod board consists of two parts: A small adapter board that sits under the VIC and sniffs all relevant 18 | pins, and the A-Video board that does the actual processing. The 5 volt signals from the C64 are 19 | level-shifted by the adapter board down to 3.3 volts for use by the FPGA. 20 | Since the adapter board only listens to the signals (with very high-impedience input pins), it 21 | will not influence the working of the VIC or any other part of the system in any way. The FPGA implementation 22 | may have some glitches, but this should only affect the visual output. 23 | Note that the mod consumes an additional 100mA of current from the 5 volt rail, 24 | so make sure that your power supply can handle this. 25 | 26 | ## Assembling the VIC adapter board 27 | 28 | If you want to build your own adapter board, you need to have a PCB manufactured with 0.8mm thickness 29 | (use the gerber.zip for ordering). After soldering the ICs and passives, you need to fit a 40-pin 30 | IC socket into the big holes. Use the socket type with round pins (the more expensive ones). 31 | Solder from below and remove as much excess solder as possible. Then install the ribbon cable connector. 32 | Take special care when installing the voltage regulator, as this small package always gave me the most trouble. 33 | For your convenience, I have set up a [BOM](doc/adapterboard_bom.ods) and a parts list at 34 | [mouser](https://www.mouser.com/ProjectManager/ProjectDetail.aspx?AccessID=2b75b16750) 35 | containing everything to build the board. 36 | 37 | ## Connectors 38 | 39 | In my current build, the A-Video port is just screwed on top of the existing RF modulator. 40 | This saved me the trouble of removing the modulator first (which would need additional circuitry to 41 | keep the A/V output working). But this comes at the cost that the back of the computer case 42 | now has a rather large and ugly hole. I am pretty sure there are good solutions available to get rid of 43 | this big modulator box while keeping the A/V functionality. Then the YPbPr connectors would be located 44 | much lower and would look more natural. 45 | If you even want a totally reversible mod you could probably place the A-Video board somewhere inside the 46 | case and bring out the YPbPr cable through the user port opening. 47 | 48 | ## Output 49 | 50 | The mod can be used to create three different output formats: 51 | * 288p (default) 52 | * 576p 53 | * 576p with scanline effect 54 | 55 | Selecting the output can be done by jumper connectors or an external switch: 56 | * Connect GPIO2_4 to GPIO2_2 (GND): 576p 57 | * Connect GPIO2_6 to GPIO2_2 (GND): 576p with scanline effect 58 | 59 | ## Images 60 | ![alt text](doc/adapterboard.jpg "VIC-II adapter board") 61 | ![alt text](doc/modboards.jpg "Installation of the two mod boards") 62 | ![alt text](doc/connectors.jpg "Backside connectors") 63 | ![alt text](doc/mode_288p.jpg "Display with standard definition (crappy upscaler)") 64 | ![alt text](doc/mode_576p.jpg "Display with doubled scanlines") 65 | ![alt text](doc/mode_576p_scanlines.jpg "Display with doubled scanlines and visual scanline effect") 66 | 67 | -------------------------------------------------------------------------------- /c64mod/c128board/README.md: -------------------------------------------------------------------------------- 1 | # C128 adapter 2 | 3 | This is an adapater to be plugged between the VIC-IIe and its socket in a Commodore 128. 4 | Using this the, C64 Video Enchancement Board should in theory be able to work for the 40 columns mode 5 | display of the C128. 6 | 7 | ## Building 8 | 9 | Use the provided gerber files (gerber.zip) to have a the PCB manufactured. Use the provided 10 | bill of material (c218adapter_bom.ods) to order the necessary parts and solder everything 11 | according to the silk-screen placement markings. Be careful to get the orientation of 12 | the various ICs right. Pin 1 is always marked specifically. 13 | 14 | ## IC socket 15 | 16 | The VIC-IIe has 48 pins, so a 48-pin socket would be needed. Unluckily, there are no such sockets 17 | to be found anywhere that have those long solder tails needed to perfectly fit the IC socket in 18 | the C128 board. So I made the design to use one 40-pin socket together with one 8-pin socket. 19 | To make things more complicated still, the 8-pin socket is of the narrow variant, so you 20 | have so split it to halves before mounting. 21 | 22 | ## Installation into the C128 23 | The adapter board should directly fit under the VIC-IIe without relocating any components 24 | (it was quite difficult to design the board in this way). 25 | 26 | Installing the FPGA board will be pretty difficult, because it does not really fit into the space 27 | of the removed RF modulator. You will have to remove parts of the metal can of 28 | the graphics chips and also some small parts of the DIN connector. 29 | As the original mod was designed with only the C64 in mind, you are pretty much 30 | on your own here. Good luck! 31 | -------------------------------------------------------------------------------- /c64mod/c128board/c128adapter_bom.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/c128board/c128adapter_bom.ods -------------------------------------------------------------------------------- /c64mod/c128board/c128board-backups/c128board-2023-06-27_154036.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/c128board/c128board-backups/c128board-2023-06-27_154036.zip -------------------------------------------------------------------------------- /c64mod/c128board/c128board.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 0, 4 | "active_layer_preset": "", 5 | "auto_track_width": true, 6 | "hidden_nets": [], 7 | "high_contrast_mode": 0, 8 | "net_color_mode": 1, 9 | "opacity": { 10 | "pads": 1.0, 11 | "tracks": 1.0, 12 | "vias": 1.0, 13 | "zones": 0.6 14 | }, 15 | "ratsnest_display_mode": 0, 16 | "selection_filter": { 17 | "dimensions": true, 18 | "footprints": true, 19 | "graphics": true, 20 | "keepouts": true, 21 | "lockedItems": true, 22 | "otherItems": true, 23 | "pads": true, 24 | "text": true, 25 | "tracks": true, 26 | "vias": true, 27 | "zones": true 28 | }, 29 | "visible_items": [ 30 | 0, 31 | 1, 32 | 2, 33 | 3, 34 | 4, 35 | 5, 36 | 6, 37 | 7, 38 | 8, 39 | 9, 40 | 10, 41 | 11, 42 | 12, 43 | 13, 44 | 14, 45 | 15, 46 | 16, 47 | 17, 48 | 18, 49 | 19, 50 | 20, 51 | 21, 52 | 22, 53 | 23, 54 | 24, 55 | 25, 56 | 26, 57 | 27, 58 | 28, 59 | 29, 60 | 30, 61 | 32, 62 | 33, 63 | 34, 64 | 35, 65 | 36 66 | ], 67 | "visible_layers": "fffffff_ffffffff", 68 | "zone_display_mode": 0 69 | }, 70 | "meta": { 71 | "filename": "c128board.kicad_prl", 72 | "version": 3 73 | }, 74 | "project": { 75 | "files": [] 76 | } 77 | } 78 | -------------------------------------------------------------------------------- /c64mod/c128board/c128board.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/c128board/c128board.pdf -------------------------------------------------------------------------------- /c64mod/c128board/c128board.pro: -------------------------------------------------------------------------------- 1 | update=31.01.2020 21:09:28 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [pcbnew] 9 | version=1 10 | LastNetListRead= 11 | UseCmpFile=1 12 | PadDrill=0.600000000000 13 | PadDrillOvalY=0.600000000000 14 | PadSizeH=1.500000000000 15 | PadSizeV=1.500000000000 16 | PcbTextSizeV=1.500000000000 17 | PcbTextSizeH=1.500000000000 18 | PcbTextThickness=0.300000000000 19 | ModuleTextSizeV=1.000000000000 20 | ModuleTextSizeH=1.000000000000 21 | ModuleTextSizeThickness=0.150000000000 22 | SolderMaskClearance=0.000000000000 23 | SolderMaskMinWidth=0.000000000000 24 | DrawSegmentWidth=0.200000000000 25 | BoardOutlineThickness=0.100000000000 26 | ModuleOutlineThickness=0.150000000000 27 | [cvpcb] 28 | version=1 29 | NetIExt=net 30 | [eeschema] 31 | version=1 32 | LibDir= 33 | [eeschema/libraries] 34 | [schematic_editor] 35 | version=1 36 | PageLayoutDescrFile= 37 | PlotDirectoryName=./ 38 | SubpartIdSeparator=0 39 | SubpartFirstId=65 40 | NetFmtName= 41 | SpiceAjustPassiveValues=0 42 | LabSize=50 43 | ERC_TestSimilarLabels=1 44 | -------------------------------------------------------------------------------- /c64mod/c128board/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name footprints)(type KiCad)(uri ${KIPRJMOD}/footprints.pretty)(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /c64mod/c128board/gerber.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/c128board/gerber.zip -------------------------------------------------------------------------------- /c64mod/c128board/parts.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /c64mod/c128board/parts.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # LVC245 5 | # 6 | DEF LVC245 U 0 40 Y Y 1 F N 7 | F0 "U" -50 100 50 H V C CNN 8 | F1 "LVC245" 0 0 50 H V C CNN 9 | F2 "" 0 0 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | DRAW 12 | S -250 -100 200 -1100 0 1 0 N 13 | X DIR 1 -350 -150 100 R 50 50 1 1 I 14 | X GND 10 -350 -1050 100 R 50 50 1 1 W 15 | X B8 11 300 -1050 100 L 50 50 1 1 O 16 | X B7 12 300 -950 100 L 50 50 1 1 O 17 | X B6 13 300 -850 100 L 50 50 1 1 O 18 | X B5 14 300 -750 100 L 50 50 1 1 O 19 | X B4 15 300 -650 100 L 50 50 1 1 O 20 | X B3 16 300 -550 100 L 50 50 1 1 O 21 | X B2 17 300 -450 100 L 50 50 1 1 O 22 | X B1 18 300 -350 100 L 50 50 1 1 O 23 | X OE 19 300 -250 100 L 50 50 1 1 I 24 | X A1 2 -350 -250 100 R 50 50 1 1 I 25 | X VCC 20 300 -150 100 L 50 50 1 1 W 26 | X A2 3 -350 -350 100 R 50 50 1 1 I 27 | X A3 4 -350 -450 100 R 50 50 1 1 I 28 | X A4 5 -350 -550 100 R 50 50 1 1 I 29 | X A5 6 -350 -650 100 R 50 50 1 1 I 30 | X A6 7 -350 -750 100 R 50 50 1 1 I 31 | X A7 8 -350 -850 100 R 50 50 1 1 I 32 | X A8 9 -350 -950 100 R 50 50 1 1 I 33 | ENDDRAW 34 | ENDDEF 35 | # 36 | # LVC257 37 | # 38 | DEF LVC257 U 0 40 Y Y 1 F N 39 | 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DB4 3 -400 -350 100 R 50 50 1 1 O 96 | X A6 30 450 -1150 100 L 50 50 1 1 O 97 | X A7 31 450 -1050 100 L 50 50 1 1 O 98 | X A8 32 450 -950 100 L 50 50 1 1 O 99 | X A9 33 450 -850 100 L 50 50 1 1 O 100 | X A10 34 450 -750 100 L 50 50 1 1 O 101 | X DB11 35 450 -650 100 L 50 50 1 1 O 102 | X DB10 36 450 -550 100 L 50 50 1 1 O 103 | X DB9 37 450 -450 100 L 50 50 1 1 O 104 | X DB8 38 450 -350 100 L 50 50 1 1 O 105 | X DB7 39 450 -250 100 L 50 50 1 1 O 106 | X DB3 4 -400 -450 100 R 50 50 1 1 O 107 | X VCC 40 450 -150 100 L 50 50 1 1 w 108 | X DB2 5 -400 -550 100 R 50 50 1 1 O 109 | X DB1 6 -400 -650 100 R 50 50 1 1 O 110 | X DB0 7 -400 -750 100 R 50 50 1 1 O 111 | X IRQ 8 -400 -850 100 R 50 50 1 1 O 112 | X LP 9 -400 -950 100 R 50 50 1 1 O 113 | ENDDRAW 114 | ENDDEF 115 | # 116 | #End Library 117 | -------------------------------------------------------------------------------- /c64mod/c128board/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name parts)(type Legacy)(uri C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/c64board/parts.lib)(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /c64mod/c64board/c64board-backups/c64board-2023-06-01_132559.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/c64board/c64board-backups/c64board-2023-06-01_132559.zip -------------------------------------------------------------------------------- /c64mod/c64board/c64board.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 0, 4 | "active_layer_preset": "", 5 | "auto_track_width": true, 6 | "hidden_nets": [], 7 | "high_contrast_mode": 0, 8 | "net_color_mode": 1, 9 | "opacity": { 10 | "pads": 1.0, 11 | "tracks": 1.0, 12 | "vias": 1.0, 13 | "zones": 0.6 14 | }, 15 | "ratsnest_display_mode": 0, 16 | "selection_filter": { 17 | "dimensions": true, 18 | "footprints": true, 19 | "graphics": true, 20 | "keepouts": true, 21 | "lockedItems": true, 22 | "otherItems": true, 23 | "pads": true, 24 | "text": true, 25 | "tracks": true, 26 | "vias": true, 27 | "zones": true 28 | }, 29 | "visible_items": [ 30 | 0, 31 | 1, 32 | 2, 33 | 3, 34 | 4, 35 | 5, 36 | 6, 37 | 7, 38 | 8, 39 | 9, 40 | 10, 41 | 11, 42 | 12, 43 | 13, 44 | 14, 45 | 15, 46 | 16, 47 | 18, 48 | 19, 49 | 20, 50 | 21, 51 | 22, 52 | 23, 53 | 24, 54 | 25, 55 | 26, 56 | 27, 57 | 28, 58 | 29, 59 | 30, 60 | 32, 61 | 33, 62 | 34, 63 | 35, 64 | 36 65 | ], 66 | "visible_layers": "003ffff_00000000", 67 | "zone_display_mode": 0 68 | }, 69 | "meta": { 70 | "filename": "c64board.kicad_prl", 71 | "version": 3 72 | }, 73 | "project": { 74 | "files": [] 75 | } 76 | } 77 | -------------------------------------------------------------------------------- /c64mod/c64board/c64board.pro: -------------------------------------------------------------------------------- 1 | update=29.10.2018 19:26:11 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [pcbnew] 9 | version=1 10 | LastNetListRead= 11 | UseCmpFile=1 12 | PadDrill=0.600000000000 13 | PadDrillOvalY=0.600000000000 14 | PadSizeH=1.500000000000 15 | PadSizeV=1.500000000000 16 | PcbTextSizeV=1.500000000000 17 | PcbTextSizeH=1.500000000000 18 | PcbTextThickness=0.300000000000 19 | ModuleTextSizeV=1.000000000000 20 | ModuleTextSizeH=1.000000000000 21 | ModuleTextSizeThickness=0.150000000000 22 | SolderMaskClearance=0.000000000000 23 | SolderMaskMinWidth=0.000000000000 24 | DrawSegmentWidth=0.200000000000 25 | BoardOutlineThickness=0.100000000000 26 | ModuleOutlineThickness=0.150000000000 27 | [cvpcb] 28 | version=1 29 | NetIExt=net 30 | [eeschema] 31 | version=1 32 | LibDir= 33 | [eeschema/libraries] 34 | [schematic_editor] 35 | version=1 36 | PageLayoutDescrFile= 37 | PlotDirectoryName=./ 38 | SubpartIdSeparator=0 39 | SubpartFirstId=65 40 | NetFmtName= 41 | SpiceAjustPassiveValues=0 42 | LabSize=50 43 | ERC_TestSimilarLabels=1 44 | -------------------------------------------------------------------------------- /c64mod/c64board/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name footprints)(type KiCad)(uri ${KIPRJMOD}/footprints.pretty)(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /c64mod/c64board/parts.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /c64mod/c64board/parts.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | 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EXPORTunsaved(SLAVE)unsaved.csr,(SLAVE)onchip_flash_0.csr) 1 0 1 NJ 6 | preplace netloc EXPORTunsaved(SLAVE)onchip_flash_0.clk,(SLAVE)unsaved.clk) 1 0 1 NJ 7 | preplace netloc EXPORTunsaved(SLAVE)onchip_flash_0.nreset,(SLAVE)unsaved.nreset) 1 0 1 NJ 8 | preplace netloc EXPORTunsaved(SLAVE)unsaved.data,(SLAVE)onchip_flash_0.data) 1 0 1 NJ 9 | levelinfo -pg 1 0 50 210 10 | levelinfo -hier unsaved 60 100 200 11 | -------------------------------------------------------------------------------- /c64mod/quartus/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /c64mod/quartus/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /c64mod/quartus/C64mod.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/firmware/") File("C64mod_2_7.pof") MfrSpec(OpMask(3) Child_OpMask(2 3 3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /c64mod/quartus/C64mod.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 21 | # Date created = 11:27:19 September 21, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "11:27:19 September 21, 2018" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "C64mod" 31 | -------------------------------------------------------------------------------- /c64mod/quartus/C64mod.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/quartus/C64mod.qws -------------------------------------------------------------------------------- /c64mod/quartus/C64modLumacode.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | use work.VICTypes.all; 5 | 6 | entity C64ModLumacode is 7 | port ( 8 | -- reference clock 9 | CLK25: in std_logic; 10 | 11 | -- digital YPbPr output 12 | Y: out std_logic_vector(5 downto 0); 13 | Pb: out std_logic_vector(4 downto 0); 14 | Pr: out std_logic_vector(4 downto 0); 15 | 16 | -- sniffing VIC-II pins comming to the GPIO1 17 | GPIO1: in std_logic_vector(20 downto 1); 18 | 19 | -- read output mode settings 20 | GPIO2_4: in std_logic; 21 | GPIO2_5: in std_logic; 22 | GPIO2_6: in std_logic; 23 | 24 | -- multi-purpose use for the JTAG signals (a bit dangerous, but should work) 25 | TMS : in std_logic; -- external jumper to support the 6567R56A 26 | TCK : in std_logic; -- keep the pin working so JTAG is possible 27 | TDI : in std_logic; -- external jumper to force high-contrast palette 28 | TDO : out std_logic; -- keep the pin working so JTAG is possible 29 | 30 | -- pixel clock output to drive the VIC if necessary 31 | AUXPIXELCLOCK : out std_logic 32 | ); 33 | end entity; 34 | 35 | 36 | architecture immediate of C64ModLumacode is 37 | component C64Mod is 38 | generic 39 | ( 40 | lumacode: boolean := false 41 | ); 42 | port ( 43 | -- reference clock 44 | CLK25: in std_logic; 45 | 46 | -- digital YPbPr output 47 | Y: out std_logic_vector(5 downto 0); 48 | Pb: out std_logic_vector(4 downto 0); 49 | Pr: out std_logic_vector(4 downto 0); 50 | 51 | -- sniffing VIC-II pins comming to the GPIO1 52 | GPIO1: in std_logic_vector(20 downto 1); 53 | 54 | -- read output mode settings 55 | GPIO2_4: in std_logic; 56 | GPIO2_5: in std_logic; 57 | GPIO2_6: in std_logic; 58 | 59 | -- multi-purpose use for the JTAG signals (a bit dangerous, but should work) 60 | TMS : in std_logic; -- external jumper to support the 6567R56A 61 | TCK : in std_logic; -- keep the pin working so JTAG is possible 62 | TDI : in std_logic; -- external jumper to force high-contrast palette 63 | TDO : out std_logic; -- keep the pin working so JTAG is possible 64 | 65 | -- pixel clock output to drive the VIC if necessary 66 | AUXPIXELCLOCK : out std_logic 67 | ); 68 | end component; 69 | 70 | begin 71 | c64: C64Mod generic map(lumacode => true) 72 | port map ( 73 | CLK25, 74 | Y, 75 | Pb, 76 | Pr, 77 | GPIO1, 78 | GPIO2_4, 79 | GPIO2_5, 80 | GPIO2_6, 81 | TMS, 82 | TCK, 83 | TDI, 84 | TDO, 85 | AUXPIXELCLOCK 86 | ); 87 | end immediate; 88 | 89 | -------------------------------------------------------------------------------- /c64mod/quartus/PLL252.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL252 17 | PORT 18 | ( 19 | configupdate : IN STD_LOGIC := '0'; 20 | inclk0 : IN STD_LOGIC := '0'; 21 | scanclk : IN STD_LOGIC := '1'; 22 | scanclkena : IN STD_LOGIC := '0'; 23 | scandata : IN STD_LOGIC := '0'; 24 | c0 : OUT STD_LOGIC ; 25 | c1 : OUT STD_LOGIC ; 26 | c2 : OUT STD_LOGIC ; 27 | c3 : OUT STD_LOGIC ; 28 | scandataout : OUT STD_LOGIC ; 29 | scandone : OUT STD_LOGIC 30 | ); 31 | end component; 32 | -------------------------------------------------------------------------------- /c64mod/quartus/PLL252.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /c64mod/quartus/PLL252.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL252.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL252.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL252.ppf"] 7 | -------------------------------------------------------------------------------- /c64mod/quartus/PLL262.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL262 17 | PORT 18 | ( 19 | configupdate : IN STD_LOGIC := '0'; 20 | inclk0 : IN STD_LOGIC := '0'; 21 | scanclk : IN STD_LOGIC := '1'; 22 | scanclkena : IN STD_LOGIC := '0'; 23 | scandata : IN STD_LOGIC := '0'; 24 | c0 : OUT STD_LOGIC ; 25 | c1 : OUT STD_LOGIC ; 26 | c2 : OUT STD_LOGIC ; 27 | c3 : OUT STD_LOGIC ; 28 | scandataout : OUT STD_LOGIC ; 29 | scandone : OUT STD_LOGIC 30 | ); 31 | end component; 32 | -------------------------------------------------------------------------------- /c64mod/quartus/PLL262.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /c64mod/quartus/PLL262.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL262.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL262.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL262.ppf"] 7 | -------------------------------------------------------------------------------- /c64mod/quartus/Prog.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/output_files/") File("C64mod.pof") MfrSpec(OpMask(3) Child_OpMask(2 3 3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /c64mod/quartus/RSFlipFlop.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | 5 | entity RSFlipFlop is 6 | port ( 7 | R: in std_logic; 8 | S: in std_logic; 9 | Q: out std_logic 10 | ); 11 | end entity; 12 | 13 | 14 | architecture immediate of RSFlipFlop is 15 | begin 16 | process (R,S) 17 | begin 18 | if R='0' then 19 | Q <= '0'; 20 | elsif S='0' then 21 | Q <= '1'; 22 | end if; 23 | end process; 24 | end immediate; 25 | -------------------------------------------------------------------------------- /c64mod/quartus/RSFlipFlop.vhd.bak: -------------------------------------------------------------------------------- 1 | ibrary ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | 5 | entity RSFlipFlop is 6 | port ( 7 | R: in std_logic; 8 | S: in std_logic; 9 | Q: out std_logic 10 | ); 11 | end entity; 12 | 13 | 14 | architecture immediate of RSFlipFlop is 15 | process (R,S) 16 | begin 17 | if R='0' then 18 | Q <= '0'; 19 | elsif S='0' then 20 | Q <= '1'; 21 | end if; 22 | end process; 23 | 24 | end immediate; 25 | -------------------------------------------------------------------------------- /c64mod/quartus/Run.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/output_files/") File("C64mod.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH.BAK.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 70 | 71 | 72 | Single Uncompressed Image 73 | Internal Configuration 74 | 75 | 76 | 77 | 78 | 79 | Read and write,Read and write,Read only,Hidden,Hidden 80 | $${FILENAME}_onchip_flash_0 81 | 82 | 83 | altera_onchip_flash.dat 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 70 | 71 | 72 | Single Uncompressed Image 73 | Internal Configuration 74 | 75 | 76 | 77 | 78 | 79 | Read and write,Read and write,Read only,Hidden,Hidden 80 | $${FILENAME}_onchip_flash_0 81 | 82 | 83 | altera_onchip_flash.dat 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH.cmp: -------------------------------------------------------------------------------- 1 | component SETTINGSFLASH is 2 | port ( 3 | clock : in std_logic := 'X'; -- clk 4 | avmm_csr_addr : in std_logic := 'X'; -- address 5 | avmm_csr_read : in std_logic := 'X'; -- read 6 | avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 7 | avmm_csr_write : in std_logic := 'X'; -- write 8 | avmm_csr_readdata : out std_logic_vector(31 downto 0); -- readdata 9 | avmm_data_addr : in std_logic_vector(11 downto 0) := (others => 'X'); -- address 10 | avmm_data_read : in std_logic := 'X'; -- read 11 | avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 12 | avmm_data_write : in std_logic := 'X'; -- write 13 | avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata 14 | avmm_data_waitrequest : out std_logic; -- waitrequest 15 | avmm_data_readdatavalid : out std_logic; -- readdatavalid 16 | avmm_data_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount 17 | reset_n : in std_logic := 'X' -- reset_n 18 | ); 19 | end component SETTINGSFLASH; 20 | 21 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH.csv: -------------------------------------------------------------------------------- 1 | # system info SETTINGSFLASH on 2019.06.10.22:04:48 2 | system_info: 3 | name,value 4 | DEVICE,10M02SCE144C8G 5 | DEVICE_FAMILY,MAX 10 6 | GENERATION_ID,1560197085 7 | # 8 | # 9 | # Files generated for SETTINGSFLASH on 2019.06.10.22:04:48 10 | files: 11 | filepath,kind,attributes,module,is_top 12 | simulation/SETTINGSFLASH.vhd,VHDL,,SETTINGSFLASH,true 13 | simulation/submodules/altera_onchip_flash_util.v,VERILOG,,altera_onchip_flash,false 14 | simulation/submodules/altera_onchip_flash.v,VERILOG,,altera_onchip_flash,false 15 | simulation/submodules/altera_onchip_flash_avmm_data_controller.v,VERILOG,,altera_onchip_flash,false 16 | simulation/submodules/altera_onchip_flash_avmm_csr_controller.v,VERILOG,,altera_onchip_flash,false 17 | # 18 | # Map from instance-path to kind of module 19 | instances: 20 | instancePath,module 21 | SETTINGSFLASH.onchip_flash_0,altera_onchip_flash 22 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 7 | 11 | 15 | 19 | 20 | 21 | 22 | 25 | 26 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module SETTINGSFLASH ( 3 | clock, 4 | reset_n, 5 | avmm_data_addr, 6 | avmm_data_read, 7 | avmm_data_writedata, 8 | avmm_data_write, 9 | avmm_data_readdata, 10 | avmm_data_waitrequest, 11 | avmm_data_readdatavalid, 12 | avmm_data_burstcount, 13 | avmm_csr_addr, 14 | avmm_csr_read, 15 | avmm_csr_writedata, 16 | avmm_csr_write, 17 | avmm_csr_readdata); 18 | 19 | input clock; 20 | input reset_n; 21 | input [11:0] avmm_data_addr; 22 | input avmm_data_read; 23 | input [31:0] avmm_data_writedata; 24 | input avmm_data_write; 25 | output [31:0] avmm_data_readdata; 26 | output avmm_data_waitrequest; 27 | output avmm_data_readdatavalid; 28 | input [1:0] avmm_data_burstcount; 29 | input avmm_csr_addr; 30 | input avmm_csr_read; 31 | input [31:0] avmm_csr_writedata; 32 | input avmm_csr_write; 33 | output [31:0] avmm_csr_readdata; 34 | endmodule 35 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH_generation.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create simulation model 2 | Info: qsys-generate C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH\simulation --family="MAX 10" --part=10M02SCE144C8G 3 | Progress: Loading quartus/SETTINGSFLASH.qsys 4 | Progress: Reading input file 5 | Progress: Adding onchip_flash_0 [altera_onchip_flash 18.1] 6 | Progress: Parameterizing module onchip_flash_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | Info: SETTINGSFLASH: Generating SETTINGSFLASH "SETTINGSFLASH" for SIM_VHDL 12 | Info: onchip_flash_0: "SETTINGSFLASH" instantiated altera_onchip_flash "onchip_flash_0" 13 | Info: SETTINGSFLASH: Done "SETTINGSFLASH" with 2 modules, 5 files 14 | Info: qsys-generate succeeded. 15 | Info: Finished: Create simulation model 16 | Info: Starting: Create Modelsim Project. 17 | Info: sim-script-gen --spd=C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH\SETTINGSFLASH.spd --output-directory=C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/ --use-relative-paths=true 18 | Info: Doing: ip-make-simscript --spd=C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH\SETTINGSFLASH.spd --output-directory=C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/ --use-relative-paths=true 19 | Info: Generating the following file(s) for MODELSIM simulator in C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/ directory: 20 | Info: mentor/msim_setup.tcl 21 | Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation 22 | Info: Generating the following file(s) for VCSMX simulator in C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/ directory: 23 | Info: synopsys/vcsmx/synopsys_sim.setup 24 | Info: synopsys/vcsmx/vcsmx_setup.sh 25 | Info: Generating the following file(s) for NCSIM simulator in C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/ directory: 26 | Info: cadence/cds.lib 27 | Info: cadence/hdl.var 28 | Info: cadence/ncsim_setup.sh 29 | Info: 1 .cds.lib files in cadence/cds_libs/ directory 30 | Info: Generating the following file(s) for RIVIERA simulator in C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/ directory: 31 | Info: aldec/rivierapro_setup.tcl 32 | Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/quartus/SETTINGSFLASH/simulation/. 33 | Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 34 | Info: Finished: Create Modelsim Project. 35 | Info: Starting: Create block symbol file (.bsf) 36 | Info: qsys-generate C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH.qsys --block-symbol-file --output-directory=C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH --family="MAX 10" --part=10M02SCE144C8G 37 | Progress: Loading quartus/SETTINGSFLASH.qsys 38 | Progress: Reading input file 39 | Progress: Adding onchip_flash_0 [altera_onchip_flash 18.1] 40 | Progress: Parameterizing module onchip_flash_0 41 | Progress: Building connections 42 | Progress: Parameterizing connections 43 | Progress: Validating 44 | Progress: Done reading input file 45 | Info: qsys-generate succeeded. 46 | Info: Finished: Create block symbol file (.bsf) 47 | Info: 48 | Info: Starting: Create HDL design files for synthesis 49 | Info: qsys-generate C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH.qsys --synthesis=VHDL --output-directory=C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH\synthesis --family="MAX 10" --part=10M02SCE144C8G 50 | Progress: Loading quartus/SETTINGSFLASH.qsys 51 | Progress: Reading input file 52 | Progress: Adding onchip_flash_0 [altera_onchip_flash 18.1] 53 | Progress: Parameterizing module onchip_flash_0 54 | Progress: Building connections 55 | Progress: Parameterizing connections 56 | Progress: Validating 57 | Progress: Done reading input file 58 | Info: SETTINGSFLASH: Generating SETTINGSFLASH "SETTINGSFLASH" for QUARTUS_SYNTH 59 | Info: onchip_flash_0: Generating top-level entity altera_onchip_flash 60 | Info: onchip_flash_0: "SETTINGSFLASH" instantiated altera_onchip_flash "onchip_flash_0" 61 | Info: SETTINGSFLASH: Done "SETTINGSFLASH" with 2 modules, 7 files 62 | Info: qsys-generate succeeded. 63 | Info: Finished: Create HDL design files for synthesis 64 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH_generation_previous.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create HDL design files for synthesis 2 | Info: qsys-generate C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH.qsys --synthesis=VHDL --output-directory=C:\Users\Reinhard\Documents\GitHub\A-VideoBoard\c64mod\quartus\SETTINGSFLASH\synthesis --family="MAX 10" --part=10M02SCE144C8G 3 | Progress: Loading quartus/SETTINGSFLASH.qsys 4 | Progress: Reading input file 5 | Progress: Adding onchip_flash_0 [altera_onchip_flash 18.0] 6 | Progress: Parameterizing module onchip_flash_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | Info: SETTINGSFLASH: Generating SETTINGSFLASH "SETTINGSFLASH" for QUARTUS_SYNTH 12 | Info: onchip_flash_0: Generating top-level entity altera_onchip_flash 13 | Info: onchip_flash_0: "SETTINGSFLASH" instantiated altera_onchip_flash "onchip_flash_0" 14 | Info: SETTINGSFLASH: Done "SETTINGSFLASH" with 2 modules, 7 files 15 | Info: qsys-generate succeeded. 16 | Info: Finished: Create HDL design files for synthesis 17 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH_inst.v: -------------------------------------------------------------------------------- 1 | SETTINGSFLASH u0 ( 2 | .clock (), // clk.clk 3 | .reset_n (), // nreset.reset_n 4 | .avmm_data_addr (), // data.address 5 | .avmm_data_read (), // .read 6 | .avmm_data_writedata (), // .writedata 7 | .avmm_data_write (), // .write 8 | .avmm_data_readdata (), // .readdata 9 | .avmm_data_waitrequest (), // .waitrequest 10 | .avmm_data_readdatavalid (), // .readdatavalid 11 | .avmm_data_burstcount (), // .burstcount 12 | .avmm_csr_addr (), // csr.address 13 | .avmm_csr_read (), // .read 14 | .avmm_csr_writedata (), // .writedata 15 | .avmm_csr_write (), // .write 16 | .avmm_csr_readdata () // .readdata 17 | ); 18 | 19 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/SETTINGSFLASH_inst.vhd: -------------------------------------------------------------------------------- 1 | component SETTINGSFLASH is 2 | port ( 3 | clock : in std_logic := 'X'; -- clk 4 | reset_n : in std_logic := 'X'; -- reset_n 5 | avmm_data_addr : in std_logic_vector(11 downto 0) := (others => 'X'); -- address 6 | avmm_data_read : in std_logic := 'X'; -- read 7 | avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 8 | avmm_data_write : in std_logic := 'X'; -- write 9 | avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata 10 | avmm_data_waitrequest : out std_logic; -- waitrequest 11 | avmm_data_readdatavalid : out std_logic; -- readdatavalid 12 | avmm_data_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount 13 | avmm_csr_addr : in std_logic := 'X'; -- address 14 | avmm_csr_read : in std_logic := 'X'; -- read 15 | avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata 16 | avmm_csr_write : in std_logic := 'X'; -- write 17 | avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata 18 | ); 19 | end component SETTINGSFLASH; 20 | 21 | u0 : component SETTINGSFLASH 22 | port map ( 23 | clock => CONNECTED_TO_clock, -- clk.clk 24 | reset_n => CONNECTED_TO_reset_n, -- nreset.reset_n 25 | avmm_data_addr => CONNECTED_TO_avmm_data_addr, -- data.address 26 | avmm_data_read => CONNECTED_TO_avmm_data_read, -- .read 27 | avmm_data_writedata => CONNECTED_TO_avmm_data_writedata, -- .writedata 28 | avmm_data_write => CONNECTED_TO_avmm_data_write, -- .write 29 | avmm_data_readdata => CONNECTED_TO_avmm_data_readdata, -- .readdata 30 | avmm_data_waitrequest => CONNECTED_TO_avmm_data_waitrequest, -- .waitrequest 31 | avmm_data_readdatavalid => CONNECTED_TO_avmm_data_readdatavalid, -- .readdatavalid 32 | avmm_data_burstcount => CONNECTED_TO_avmm_data_burstcount, -- .burstcount 33 | avmm_csr_addr => CONNECTED_TO_avmm_csr_addr, -- csr.address 34 | avmm_csr_read => CONNECTED_TO_avmm_csr_read, -- .read 35 | avmm_csr_writedata => CONNECTED_TO_avmm_csr_writedata, -- .writedata 36 | avmm_csr_write => CONNECTED_TO_avmm_csr_write, -- .write 37 | avmm_csr_readdata => CONNECTED_TO_avmm_csr_readdata -- .readdata 38 | ); 39 | 40 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/simulation/SETTINGSFLASH.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "SETTINGSFLASH" -library "lib_SETTINGSFLASH" -name IP_TOOL_NAME "Qsys" 2 | set_global_assignment -entity "SETTINGSFLASH" -library "lib_SETTINGSFLASH" -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -entity "SETTINGSFLASH" -library "lib_SETTINGSFLASH" -name IP_TOOL_ENV "Qsys" 4 | set_global_assignment -library "lib_SETTINGSFLASH" -name SPD_FILE [file join $::quartus(sip_path) "../SETTINGSFLASH.spd"] 5 | set_global_assignment -library "lib_SETTINGSFLASH" -name MISC_FILE [file join $::quartus(sip_path) "../../SETTINGSFLASH.qsys"] 6 | 7 | set_global_assignment -library "lib_SETTINGSFLASH" -name MISC_FILE [file join $::quartus(sip_path) "SETTINGSFLASH.vhd"] 8 | set_global_assignment -library "lib_SETTINGSFLASH" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash_util.v"] 9 | set_global_assignment -library "lib_SETTINGSFLASH" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash.v"] 10 | set_global_assignment -library "lib_SETTINGSFLASH" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash_avmm_data_controller.v"] 11 | set_global_assignment -library "lib_SETTINGSFLASH" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash_avmm_csr_controller.v"] 12 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/simulation/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE onchip_flash_0 ./libraries/onchip_flash_0/ 13 | DEFINE altera_ver ./libraries/altera_ver/ 14 | DEFINE lpm_ver ./libraries/lpm_ver/ 15 | DEFINE sgate_ver ./libraries/sgate_ver/ 16 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 17 | DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/ 18 | DEFINE altera ./libraries/altera/ 19 | DEFINE lpm ./libraries/lpm/ 20 | DEFINE sgate ./libraries/sgate/ 21 | DEFINE altera_mf ./libraries/altera_mf/ 22 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 23 | DEFINE fiftyfivenm ./libraries/fiftyfivenm/ 24 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/simulation/cadence/cds_libs/onchip_flash_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/ 17 | DEFINE altera ./../libraries/altera/ 18 | DEFINE lpm ./../libraries/lpm/ 19 | DEFINE sgate ./../libraries/sgate/ 20 | DEFINE altera_mf ./../libraries/altera_mf/ 21 | DEFINE altera_lnsim ./../libraries/altera_lnsim/ 22 | DEFINE fiftyfivenm ./../libraries/fiftyfivenm/ 23 | DEFINE onchip_flash_0 ./../libraries/onchip_flash_0/ 24 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/simulation/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/simulation/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | onchip_flash_0: ./libraries/onchip_flash_0/ 6 | altera_ver: ./libraries/altera_ver/ 7 | lpm_ver: ./libraries/lpm_ver/ 8 | sgate_ver: ./libraries/sgate_ver/ 9 | altera_mf_ver: ./libraries/altera_mf_ver/ 10 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 11 | fiftyfivenm_ver: ./libraries/fiftyfivenm_ver/ 12 | altera: ./libraries/altera/ 13 | lpm: ./libraries/lpm/ 14 | sgate: ./libraries/sgate/ 15 | altera_mf: ./libraries/altera_mf/ 16 | altera_lnsim: ./libraries/altera_lnsim/ 17 | fiftyfivenm: ./libraries/fiftyfivenm/ 18 | LIBRARY_SCAN = TRUE 19 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/synthesis/submodules/altera_onchip_flash.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2018 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | 15 | #************************************************************** 16 | # Time Information 17 | #************************************************************** 18 | 19 | 20 | 21 | #************************************************************** 22 | # Create Clock 23 | #************************************************************** 24 | 25 | 26 | 27 | #************************************************************** 28 | # Create Generated Clock 29 | #************************************************************** 30 | 31 | 32 | 33 | #************************************************************** 34 | # Set Clock Latency 35 | #************************************************************** 36 | 37 | 38 | 39 | #************************************************************** 40 | # Set Clock Uncertainty 41 | #************************************************************** 42 | 43 | 44 | 45 | #************************************************************** 46 | # Set Input Delay 47 | #************************************************************** 48 | 49 | 50 | 51 | #************************************************************** 52 | # Set Output Delay 53 | #************************************************************** 54 | 55 | 56 | 57 | #************************************************************** 58 | # Set Clock Groups 59 | #************************************************************** 60 | 61 | 62 | 63 | #************************************************************** 64 | # Set False Path 65 | #************************************************************** 66 | 67 | set_false_path -to [get_registers {*|flash_busy_reg}] 68 | set_false_path -to [get_registers {*|flash_busy_clear_reg}] 69 | 70 | 71 | #************************************************************** 72 | # Set Multicycle Path 73 | #************************************************************** 74 | 75 | 76 | 77 | #************************************************************** 78 | # Set Maximum Delay 79 | #************************************************************** 80 | 81 | 82 | 83 | #************************************************************** 84 | # Set Minimum Delay 85 | #************************************************************** 86 | 87 | 88 | 89 | #************************************************************** 90 | # Set Input Transition 91 | #************************************************************** 92 | 93 | -------------------------------------------------------------------------------- /c64mod/quartus/SETTINGSFLASH/synthesis/submodules/rtl/altera_onchip_flash_block.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/quartus/SETTINGSFLASH/synthesis/submodules/rtl/altera_onchip_flash_block.v -------------------------------------------------------------------------------- /c64mod/quartus/VICTypes.vhd: -------------------------------------------------------------------------------- 1 | package VICTypes is -- untested... 2 | 3 | type t_VICType is (CLOCKS63, CLOCKS64, CLOCKS65); 4 | 5 | end VICTypes; 6 | -------------------------------------------------------------------------------- /c64mod/quartus/VICTypes.vhd.bak: -------------------------------------------------------------------------------- 1 | package VICTypes is -- untested... 2 | 3 | type t_VICType is (CLOCK63, CLOCK64, CLOCK65); 4 | 5 | -- (optional) useful tools 6 | function to_slv (e : my_enum_type) return std_logic_vector; 7 | function to_enum (s : std_logic_vector(my_enum'length downto 0)) 8 | return my_enum_type; 9 | 10 | end VICTypes; 11 | 12 | package body VICTypes is 13 | -- subprogram bodies here 14 | end VICTypes; -------------------------------------------------------------------------------- /c64mod/quartus/c64mod.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 40.00 -name clkref [get_ports {CLK25}] 2 | create_clock -period 120.000 -name clksync [get_registers {clkmulti|counter0[3]}] 3 | derive_pll_clocks 4 | 5 | -------------------------------------------------------------------------------- /c64mod/quartus/c64mod.sdc.bak: -------------------------------------------------------------------------------- 1 | create_clock -period 40.00 -name clkref [get_ports {CLK25}] 2 | create_clock -period 10.50 -name clk12th [get_registers {counter[1]}] 3 | create_clock -period 125.0 -name clkpixel [get_registers {out_clkpixel}] 4 | derive_pll_clocks 5 | -------------------------------------------------------------------------------- /c64mod/quartus/defaultsettings.hex: -------------------------------------------------------------------------------- 1 | :4000000010020000100200001002000010020000100200001002000010020000100200001002000010020000100200001002000010020000100200001002000010020000a0 2 | :40004000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000a0 3 | :40008000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b829000030 4 | :4000c0000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e000070 5 | :40010000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b63200003f 6 | :40014000844100008441000084410000844100008441000084410000844100008441000084410000844100008441000084410000844100008441000084410000844100002f 7 | :400180004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300002f 8 | :4001c000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d00001f 9 | :40020000753100007531000075310000753100007531000075310000753100007531000075310000753100007531000075310000753100007531000075310000753100005e 10 | :40024000722100007221000072210000722100007221000072210000722100007221000072210000722100007221000072210000722100007221000072210000722100004e 11 | :40028000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000ae 12 | :4002c000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a00005e 13 | :40030000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000dd 14 | :400340000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d0000ed 15 | :40038000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000ed 16 | :4003c000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e00001d 17 | :40040000100200001002000010020000100200001002000010020000100200001002000010020000100200001002000010020000100200001002000010020000100200009c 18 | :40044000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e0000107e00009c 19 | :40048000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b8290000b82900002c 20 | :4004c0000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00000b4e00006c 21 | :40050000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b6320000b63200003b 22 | :40054000844100008441000084410000844100008441000084410000844100008441000084410000844100008441000084410000844100008441000084410000844100002b 23 | :400580004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300004e2300002b 24 | :4005c000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d0000115d00001b 25 | :40060000753100007531000075310000753100007531000075310000753100007531000075310000753100007531000075310000753100007531000075310000753100005a 26 | :40064000722100007221000072210000722100007221000072210000722100007221000072210000722100007221000072210000722100007221000072210000722100004a 27 | :40068000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000b8410000aa 28 | :4006c000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a0000102a00005a 29 | :40070000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000103e0000d9 30 | :400740000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d00000c5d0000e9 31 | :40078000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000463f0000e9 32 | :4007c000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e0000104e000019 33 | :00000001FF 34 | -------------------------------------------------------------------------------- /c64mod/quartus/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | BANDWIDTH_TYPE=AUTO 2 | CLK0_DIVIDE_BY=1 3 | CLK0_DUTY_CYCLE=50 4 | CLK0_MULTIPLY_BY=10 5 | CLK0_PHASE_SHIFT=0 6 | CLK1_DIVIDE_BY=1 7 | CLK1_DUTY_CYCLE=50 8 | CLK1_MULTIPLY_BY=20 9 | CLK1_PHASE_SHIFT=0 10 | COMPENSATE_CLOCK=CLK0 11 | INCLK0_INPUT_FREQUENCY=67340 12 | INTENDED_DEVICE_FAMILY="MAX 10" 13 | LPM_TYPE=altpll 14 | OPERATION_MODE=NORMAL 15 | PLL_TYPE=AUTO 16 | PORT_ACTIVECLOCK=PORT_UNUSED 17 | PORT_ARESET=PORT_USED 18 | PORT_CLKBAD0=PORT_UNUSED 19 | PORT_CLKBAD1=PORT_UNUSED 20 | PORT_CLKLOSS=PORT_UNUSED 21 | PORT_CLKSWITCH=PORT_UNUSED 22 | PORT_CONFIGUPDATE=PORT_UNUSED 23 | PORT_FBIN=PORT_UNUSED 24 | PORT_INCLK0=PORT_USED 25 | PORT_INCLK1=PORT_UNUSED 26 | PORT_LOCKED=PORT_USED 27 | PORT_PFDENA=PORT_UNUSED 28 | PORT_PHASECOUNTERSELECT=PORT_UNUSED 29 | PORT_PHASEDONE=PORT_UNUSED 30 | PORT_PHASESTEP=PORT_UNUSED 31 | PORT_PHASEUPDOWN=PORT_UNUSED 32 | PORT_PLLENA=PORT_UNUSED 33 | PORT_SCANACLR=PORT_UNUSED 34 | PORT_SCANCLK=PORT_UNUSED 35 | PORT_SCANCLKENA=PORT_UNUSED 36 | PORT_SCANDATA=PORT_UNUSED 37 | PORT_SCANDATAOUT=PORT_UNUSED 38 | PORT_SCANDONE=PORT_UNUSED 39 | PORT_SCANREAD=PORT_UNUSED 40 | PORT_SCANWRITE=PORT_UNUSED 41 | PORT_clk0=PORT_USED 42 | PORT_clk1=PORT_USED 43 | PORT_clk2=PORT_UNUSED 44 | PORT_clk3=PORT_UNUSED 45 | PORT_clk4=PORT_UNUSED 46 | PORT_clk5=PORT_UNUSED 47 | PORT_clkena0=PORT_UNUSED 48 | PORT_clkena1=PORT_UNUSED 49 | PORT_clkena2=PORT_UNUSED 50 | PORT_clkena3=PORT_UNUSED 51 | PORT_clkena4=PORT_UNUSED 52 | PORT_clkena5=PORT_UNUSED 53 | PORT_extclk0=PORT_UNUSED 54 | PORT_extclk1=PORT_UNUSED 55 | PORT_extclk2=PORT_UNUSED 56 | PORT_extclk3=PORT_UNUSED 57 | SELF_RESET_ON_LOSS_LOCK=OFF 58 | WIDTH_CLOCK=5 59 | DEVICE_FAMILY="MAX 10" 60 | CBX_AUTO_BLACKBOX=ALL 61 | areset 62 | inclk 63 | inclk 64 | clk 65 | clk 66 | locked 67 | -------------------------------------------------------------------------------- /c64mod/quartus/ip_upgrade_port_diff_reports/settingsflash.18_1.no_port_diff.rpt: -------------------------------------------------------------------------------- 1 | IP Ports Diff Report for settingsflash 2 | Mon Jun 10 22:05:10 2019 3 | Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. IP Information 10 | 11 | 12 | 13 | +------------------------------------------------------------------+ 14 | ; IP Information ; 15 | +----------------------+-------------------------------------------+ 16 | ; IP Variation Name ; settingsflash ; 17 | ; Prior Version ; 18.0 ; 18 | ; New Version ; 18.1 ; 19 | ; New File ; SETTINGSFLASH/synthesis/SETTINGSFLASH.vhd ; 20 | ; Has Port Differences ; No ; 21 | +----------------------+-------------------------------------------+ 22 | 23 | 24 | -------------------------------------------------------------------------------- /c64mod/quartus/ram_dual.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity ram_dual is 6 | generic 7 | ( 8 | data_width : integer := 8; 9 | addr_width : integer := 16 10 | ); 11 | port 12 | ( 13 | data : in std_logic_vector(data_width-1 downto 0); 14 | raddr : in std_logic_vector(addr_width-1 downto 0); 15 | waddr : in std_logic_vector(addr_width-1 downto 0); 16 | we : in std_logic := '1'; 17 | rclk : in std_logic; 18 | wclk : in std_logic; 19 | q : out std_logic_vector(data_width-1 downto 0) 20 | ); 21 | end ram_dual; 22 | 23 | architecture rtl of ram_dual is 24 | 25 | -- Build a 2-D array type for the RAM 26 | subtype word_t is std_logic_vector(data_width-1 downto 0); 27 | type memory_t is array((2**addr_width)-1 downto 0) of word_t; 28 | 29 | -- Declare the RAM signal. 30 | signal ram : memory_t; 31 | 32 | begin 33 | 34 | process(wclk) 35 | begin 36 | if(rising_edge(wclk)) then 37 | if(we = '1') then 38 | ram(to_integer(unsigned(waddr))) <= data; 39 | end if; 40 | end if; 41 | end process; 42 | 43 | process(rclk) 44 | begin 45 | if(rising_edge(rclk)) then 46 | q <= ram(to_integer(unsigned(raddr))); 47 | end if; 48 | end process; 49 | 50 | end rtl; 51 | -------------------------------------------------------------------------------- /c64mod/quartus/ram_dual.vhd.bak: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity ram_dual is 5 | port 6 | ( 7 | data : in std_logic_vector(7 downto 0); 8 | raddr : in natural range 0 to 63; 9 | waddr : in natural range 0 to 63; 10 | we : in std_logic := '1'; 11 | rclk : in std_logic; 12 | wclk : in std_logic; 13 | q : out std_logic_vector(7 downto 0) 14 | ); 15 | 16 | end ram_dual; 17 | 18 | architecture rtl of ram_dual is 19 | 20 | -- Build a 2-D array type for the RAM 21 | subtype word_t is std_logic_vector(7 downto 0); 22 | type memory_t is array(63 downto 0) of word_t; 23 | 24 | -- Declare the RAM signal. 25 | signal ram : memory_t; 26 | 27 | begin 28 | 29 | process(wclk) 30 | begin 31 | if(rising_edge(wclk)) then 32 | if(we = '1') then 33 | ram(waddr) <= data; 34 | end if; 35 | end if; 36 | end process; 37 | 38 | process(rclk) 39 | begin 40 | if(rising_edge(rclk)) then 41 | q <= ram(raddr); 42 | end if; 43 | end process; 44 | 45 | end rtl; 46 | -------------------------------------------------------------------------------- /c64mod/testsignal/Prog.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5M570ZT100) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/c64mod/testsignal/output_files/") File("testsignal.pof") MfrSpec(OpMask(3) SEC_Device(5M570ZT100) Child_OpMask(2 3 3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /c64mod/testsignal/README.md: -------------------------------------------------------------------------------- 1 | ![alt text](box.jpg "Everything needed in a nice box") 2 | -------------------------------------------------------------------------------- /c64mod/testsignal/box.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/c64mod/testsignal/box.jpg -------------------------------------------------------------------------------- /c64mod/testsignal/testsignal.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 21 | # Date created = 13:15:36 September 27, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.1" 26 | DATE = "13:15:36 September 27, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "testsignal" 31 | -------------------------------------------------------------------------------- /c64mod/testsignal/testsignal.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 21 | # Date created = 13:15:36 September 27, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # testsignal_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "MAX V" 40 | set_global_assignment -name DEVICE 5M570ZT100C5 41 | set_global_assignment -name TOP_LEVEL_ENTITY testsignal 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:15:36 SEPTEMBER 27, 2019" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" 49 | set_global_assignment -name ENABLE_OCT_DONE OFF 50 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 51 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" 53 | set_location_assignment PIN_12 -to CLK100 54 | set_location_assignment PIN_54 -to DB[7] 55 | set_location_assignment PIN_56 -to DB[8] 56 | set_location_assignment PIN_58 -to DB[9] 57 | set_location_assignment PIN_66 -to DB[10] 58 | set_location_assignment PIN_68 -to DB[11] 59 | set_location_assignment PIN_82 -to A[5] 60 | set_location_assignment PIN_84 -to A[4] 61 | set_location_assignment PIN_86 -to A[3] 62 | set_location_assignment PIN_98 -to A[2] 63 | set_location_assignment PIN_92 -to A[0] 64 | set_location_assignment PIN_53 -to DB[6] 65 | set_location_assignment PIN_55 -to DB[5] 66 | set_location_assignment PIN_57 -to DB[4] 67 | set_location_assignment PIN_61 -to DB[3] 68 | set_location_assignment PIN_67 -to DB[2] 69 | set_location_assignment PIN_69 -to DB[1] 70 | set_location_assignment PIN_71 -to DB[0] 71 | set_location_assignment PIN_77 -to CS 72 | set_location_assignment PIN_81 -to RW 73 | set_location_assignment PIN_83 -to BA 74 | set_location_assignment PIN_91 -to AEC 75 | set_location_assignment PIN_97 -to PHI0 76 | set_location_assignment PIN_96 -to A[1] 77 | set_global_assignment -name SDC_FILE testsignal.sdc 78 | set_global_assignment -name VHDL_FILE testsignal.vhd 79 | set_global_assignment -name CDF_FILE Prog.cdf -------------------------------------------------------------------------------- /c64mod/testsignal/testsignal.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /c64mod/testsignal/testsignal.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.00 -name clkref [get_ports {CLK100}] 2 | create_clock -period 125.0 -name pixelclock [get_registers {out_clock}] 3 | 4 | 5 | -------------------------------------------------------------------------------- /c64mod/testsignal/testsignal.sdc.bak: -------------------------------------------------------------------------------- 1 | create_clock -period 40.00 -name clkref [get_ports {CLK25}] 2 | create_clock -period 120.000 -name clksync [get_registers {clkmulti|counter0[3]}] 3 | derive_pll_clocks 4 | 5 | -------------------------------------------------------------------------------- /c64mod/testsignal/testsignal.vhd.bak: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | 5 | -- Test circuit to simulate the signals of a VIC in the C64 to drive 6 | -- and test a C64 video enhancement board in PAL mode. 7 | 8 | 9 | entity TestSignal is 10 | port ( 11 | -- reference clock 12 | CLK100: in std_logic; 13 | 14 | -- generated signals 15 | DB: out std_logic_vector(11 downto 0); 16 | A: out std_logic_vector(5 downto 0); 17 | CS: out std_logic; 18 | RW: out std_logic; 19 | BA: out std_logic; 20 | AEC: out std_logic; 21 | PHI0: out std_logic; 22 | ); 23 | end entity; 24 | 25 | 26 | architecture immediate of TestSignal is 27 | begin 28 | process 29 | begin 30 | DB <= "000000000000"; 31 | A <= "000000"; 32 | CS <= '1'; 33 | RW <= '1'; 34 | BA <= '1'; 35 | AEC <= '1'; 36 | end process; 37 | 38 | process (CLK100) 39 | variable displayline : integer range 0 to 311 := 0; 40 | variable cycle : integer range 1 to 63 := 0; 41 | variable tick : integer range 0 to 127; 42 | begin 43 | if rising_edge(CLK100) then 44 | -- generate output signal depending on counter positions 45 | if counter<50 then 46 | PHI0 <= '1'; 47 | else 48 | PHI1 <= '0'; 49 | end if; 50 | 51 | -- progress the counters 52 | if tick<101 then 53 | tick := tick+1; 54 | else 55 | tick := 1; 56 | 57 | if cycle<63 then 58 | cycle := cycle+1; 59 | else 60 | cycle := 0; 61 | if displayline<311 then 62 | displayline := displayline +1; 63 | else 64 | displayline := 0; 65 | end if; 66 | end if; 67 | end if; 68 | end if; 69 | end process; 70 | end immediate; 71 | -------------------------------------------------------------------------------- /doc/backside.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/doc/backside.jpg -------------------------------------------------------------------------------- /doc/bill_of_materials.txt: -------------------------------------------------------------------------------- 1 | Reference, Value, Footprint, Datasheet 2 | POWER1,CONM_01x02,Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm, 3 | C6,100nF,Capacitors_SMD:C_0603_HandSoldering, 4 | C15,100nF,Capacitors_SMD:C_0603_HandSoldering, 5 | C16,100nF,Capacitors_SMD:C_0603_HandSoldering, 6 | C17,100nF,Capacitors_SMD:C_0603_HandSoldering, 7 | C14,100nF,Capacitors_SMD:C_0603_HandSoldering, 8 | C13,100nF,Capacitors_SMD:C_0603_HandSoldering, 9 | C12,100nF,Capacitors_SMD:C_0603_HandSoldering, 10 | C11,100nF,Capacitors_SMD:C_0603_HandSoldering, 11 | C18,100nF,Capacitors_SMD:C_0603_HandSoldering, 12 | C19,100nF,Capacitors_SMD:C_0603_HandSoldering, 13 | C20,100nF,Capacitors_SMD:C_0603_HandSoldering, 14 | C21,100nF,Capacitors_SMD:C_0603_HandSoldering, 15 | C22,100nF,Capacitors_SMD:C_0603_HandSoldering, 16 | C23,100nF,Capacitors_SMD:C_0603_HandSoldering, 17 | C24,100nF,Capacitors_SMD:C_0603_HandSoldering, 18 | C33,100nF,Capacitors_SMD:C_0603_HandSoldering, 19 | C32,100nF,Capacitors_SMD:C_0603_HandSoldering, 20 | C31,100nF,Capacitors_SMD:C_0603_HandSoldering, 21 | C34,100nF,Capacitors_SMD:C_0603_HandSoldering, 22 | C25,100nF,Capacitors_SMD:C_0603_HandSoldering, 23 | U2,10M02SCE144,footprints:QFP_144_GND, 24 | JTAG1,CONN_02X05,Pin_Headers:Pin_Header_Straight_2x05_Pitch2.54mm, 25 | R23,10k,Resistors_SMD:R_0805_HandSoldering, 26 | R21,10k,Resistors_SMD:R_0805_HandSoldering, 27 | R20,10k,Resistors_SMD:R_0805_HandSoldering, 28 | R22,10k,Resistors_SMD:R_0805_HandSoldering, 29 | R24,10k,Resistors_SMD:R_0805_HandSoldering, 30 | R26,10k,Resistors_SMD:R_0805_HandSoldering, 31 | R25,10k,Resistors_SMD:R_0805_HandSoldering, 32 | C1,10uF,Capacitors_SMD:C_0805_HandSoldering, 33 | C2,10uF,Capacitors_SMD:C_0805_HandSoldering, 34 | L2,10uH,Capacitors_SMD:C_0805_HandSoldering, 35 | L1,10uH,Capacitors_SMD:C_0805_HandSoldering, 36 | C3,10uF,Capacitors_SMD:C_0805_HandSoldering, 37 | C4,10uF,Capacitors_SMD:C_0805_HandSoldering, 38 | AMP1,THS7316,Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm, 39 | R29,75,Resistors_SMD:R_0805_HandSoldering, 40 | R28,75,Resistors_SMD:R_0805_HandSoldering, 41 | R27,75,Resistors_SMD:R_0805_HandSoldering, 42 | C7,100nF,Capacitors_SMD:C_0603_HandSoldering, 43 | R16,16k,Resistors_SMD:R_0805_HandSoldering, 44 | R15,8k,Resistors_SMD:R_0805_HandSoldering, 45 | R14,4k,Resistors_SMD:R_0805_HandSoldering, 46 | R13,2k,Resistors_SMD:R_0805_HandSoldering, 47 | R12,1k,Resistors_SMD:R_0805_HandSoldering, 48 | R19,150,Resistors_SMD:R_0805_HandSoldering, 49 | R11,16k,Resistors_SMD:R_0805_HandSoldering, 50 | R10,8k,Resistors_SMD:R_0805_HandSoldering, 51 | R9,4k,Resistors_SMD:R_0805_HandSoldering, 52 | R8,2k,Resistors_SMD:R_0805_HandSoldering, 53 | R7,1k,Resistors_SMD:R_0805_HandSoldering, 54 | R18,150,Resistors_SMD:R_0805_HandSoldering, 55 | R6,16k,Resistors_SMD:R_0805_HandSoldering, 56 | R5,8k,Resistors_SMD:R_0805_HandSoldering, 57 | R4,4k,Resistors_SMD:R_0805_HandSoldering, 58 | R3,2k,Resistors_SMD:R_0805_HandSoldering, 59 | R2,1k,Resistors_SMD:R_0805_HandSoldering, 60 | R17,150,Resistors_SMD:R_0805_HandSoldering, 61 | R1,1k1,Resistors_SMD:R_0805_HandSoldering, 62 | REG1,LM1117IMPX-3.3,TO_SOT_Packages_SMD:SOT-223, 63 | GPIO2,CONN_02X05,Pin_Headers:Pin_Header_Straight_2x05_Pitch2.54mm, 64 | C26,100nF,Capacitors_SMD:C_0603_HandSoldering, 65 | C27,100nF,Capacitors_SMD:C_0603_HandSoldering, 66 | POWER2,CONN_02X01,Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm, 67 | Y1,BNC,footprints:RCA_JACK, 68 | PB1,BNC,footprints:RCA_JACK, 69 | PR1,BNC,footprints:RCA_JACK, 70 | GPIO1,CONN_02X10,Pin_Headers:Pin_Header_Straight_2x10_Pitch2.54mm, 71 | OSC1,LFSPXO024957,Oscillators:Oscillator_SMD_EuroQuartz_XO53-4pin_5.0x3.2mm_HandSoldering, 72 | L3,10uH,Capacitors_SMD:C_0805_HandSoldering, 73 | C5,10uF,Capacitors_SMD:C_0805_HandSoldering, 74 | -------------------------------------------------------------------------------- /doc/frontside.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/doc/frontside.jpg -------------------------------------------------------------------------------- /doc/pin_assignment.txt: -------------------------------------------------------------------------------- 1 | Pin assignments for the A-Video Board (Rev.2) 2 | 3 | 25Mhz Reference clock: MAX 10 pin 25 4 | 5 | 20-pin GPIO-header GPIO1 6 | Connector pin MAX 10 pin 7 | GPIO1 1 74 8 | GPIO1 2 75 9 | GPIO1 3 76 10 | GPIO1 4 77 11 | GPIO1 5 78 12 | GPIO1 6 79 13 | GPIO1 7 80 14 | GPIO1 8 81 15 | GPIO1 9 87 16 | GPIO1 10 88 17 | GPIO1 11 91 18 | GPIO1 12 92 19 | GPIO1 13 97 20 | GPIO1 14 98 21 | GPIO1 15 99 22 | GPIO1 16 100 23 | GPIO1 17 101 24 | GPIO1 18 103 25 | GPIO1 19 105 26 | GPIO1 20 106 27 | 28 | 10-pin GPIO-header GPIO2 29 | Connector pin MAX 10 pin 30 | GPIO2 1 3.3V 31 | GPIO2 2 GND 32 | GPIO2 3 41 33 | GPIO2 4 40 34 | GPIO2 5 39 35 | GPIO2 6 33 36 | GPIO2 7 32 37 | GPIO2 8 31 38 | GPIO2 9 28 (can drive PLL) 39 | GPIO2 10 27 (can drive PLL) 40 | 41 | 42 | In-board wiring of the MAX 10 to the DAC 43 | MAX 10 pin 44 | Y(5) = SYNC 46 45 | Y(4) 47 46 | Y(3) 48 47 | Y(2) 49 48 | Y(1) 50 49 | Y(0) 51 50 | PB(4) 52 51 | PB(3) 53 52 | PB(2) 59 53 | PB(1) 60 54 | PB(0) 61 55 | PR(4) 63 56 | PR(3) 65 57 | PR(2) 67 58 | PR(1) 69 59 | PR(0) 70 60 | 61 | -------------------------------------------------------------------------------- /doc/resistors.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/doc/resistors.ods -------------------------------------------------------------------------------- /doc/schematics.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/doc/schematics.pdf -------------------------------------------------------------------------------- /doc/videotimings.txt: -------------------------------------------------------------------------------- 1 | Structure of a 288p video signal 2 | -------------------------------- 3 | 4 | The A-Video board is designed to generate a YPbPr signal that consists of three separate channels: 5 | The Y signal carries the luminance information together with frame and line sync. 6 | The Pb and Pr signals carry additional colour information (the blue differential and red differential). 7 | Each of the three channels is controled by a simple 5-bit DAC (5 bit plus sync in case of the Y signal) 8 | made from resistors and that feed into a video amplifier to drive the outgoing line. 9 | 10 | The voltage range of the signals is 0 to 700mV for the Pb and Pr channel and 0,300-1000mV for the Y channel 11 | (everything is DC coupled). 12 | By using a different firmware in the FPGA it would also be possible to generate a RGsB signal since this uses 13 | the same voltage ranges. 14 | 15 | Since 288p was never a real standard, but more a kind of hack many computers and consoles of the time used, 16 | I wanted to create a signal that would be most largely supported. Therefore I will try to reproduce the 17 | signal that is generated by the original Sony Playstation as accurately as possible. 18 | 19 | Vertical: 20 | 8 lines frame start sync pattern 21 | 17 lines black 22 | 288 lines video content (270 visible on my TV) 23 | 312 Total 24 | 25 | Synchronization pulses always start at either the line begin 26 | or exactly in the middle of a line (32 us after line start). 27 | The sync pattern is as follows: 28 | 29 | Line 0 | 4.70us | 2.35us | 30 | Line 1 | 2.35us | 2.35us | 31 | Line 2 | 2.35us | 2.35us | 32 | Line 3 | 27.30us | 27.30us | 33 | Line 4 | 27.30us | 27.30us | 34 | Line 5 | 27.30us | 2.35us | 35 | Line 6 | 2.35us | 2.35us | 36 | Line 7 | 2.35us | 2.35us | 37 | Line 8 | 4.70us | 38 | ... 39 | 40 | 41 | To get square pixels on my test TV (set to 4:3), the pixel clock needs to be 7.31 Mhz. 42 | As a comparision the following devices use these slightly different timings: 43 | ZX Spectrum: 7 MHz 44 | Atari 800 (PAL): 7.08 MHz 45 | Commodore 64 (PAL): 7.88 Mhz 46 | -------------------------------------------------------------------------------- /quartus/PLL7_31.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL7_31 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC 21 | ); 22 | end component; 23 | -------------------------------------------------------------------------------- /quartus/PLL7_31.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /quartus/PLL7_31.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL7_31.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL7_31.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL7_31.ppf"] 7 | -------------------------------------------------------------------------------- /quartus/PLL8.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, the Altera Quartus Prime License Agreement, 9 | --the Altera MegaCore Function License Agreement, or other 10 | --applicable license agreement, including, without limitation, 11 | --that your use is for the sole purpose of programming logic 12 | --devices manufactured by Altera and sold by Altera or its 13 | --authorized distributors. Please refer to the applicable 14 | --agreement for further details. 15 | 16 | 17 | component PLL8 18 | PORT 19 | ( 20 | inclk0 : IN STD_LOGIC := '0'; 21 | c0 : OUT STD_LOGIC 22 | ); 23 | end component; 24 | -------------------------------------------------------------------------------- /quartus/PLL8.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /quartus/PLL8.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "16.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL8.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL8.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL8.ppf"] 7 | -------------------------------------------------------------------------------- /quartus/PLL_14_387.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL_14_387 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC 21 | ); 22 | end component; 23 | -------------------------------------------------------------------------------- /quartus/PLL_14_387.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /quartus/PLL_14_387.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL_14_387.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_14_387.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_14_387.ppf"] 7 | -------------------------------------------------------------------------------- /quartus/PLL_14_411.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL_14_411 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC 21 | ); 22 | end component; 23 | -------------------------------------------------------------------------------- /quartus/PLL_14_411.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /quartus/PLL_14_411.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL_14_411.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_14_411.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_14_411.ppf"] 7 | -------------------------------------------------------------------------------- /quartus/PLL_14_625.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL_14_625 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC 21 | ); 22 | end component; 23 | -------------------------------------------------------------------------------- /quartus/PLL_14_625.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /quartus/PLL_14_625.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL_14_625.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_14_625.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_14_625.ppf"] 7 | -------------------------------------------------------------------------------- /quartus/Program.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/quartus/output_files/") File("avideoboard.pof") MfrSpec(OpMask(3) Child_OpMask(2 3 3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /quartus/Run.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/quartus/output_files/") File("avideoboard.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /quartus/TestPattern.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/quartus/TestPattern.qws -------------------------------------------------------------------------------- /quartus/avideoboard.ipregen.rpt: -------------------------------------------------------------------------------- 1 | IP Upgrade report for avideoboard 2 | Wed Jul 22 15:04:43 2020 3 | Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. IP Upgrade Summary 11 | 3. Successfully Upgraded IP Components 12 | 4. IP Upgrade Messages 13 | 14 | 15 | 16 | ---------------- 17 | ; Legal Notice ; 18 | ---------------- 19 | Copyright (C) 2018 Intel Corporation. All rights reserved. 20 | Your use of Intel Corporation's design tools, logic functions 21 | and other software and tools, and its AMPP partner logic 22 | functions, and any output files from any of the foregoing 23 | (including device programming or simulation files), and any 24 | associated documentation or information are expressly subject 25 | to the terms and conditions of the Intel Program License 26 | Subscription Agreement, the Intel Quartus Prime License Agreement, 27 | the Intel FPGA IP License Agreement, or other applicable license 28 | agreement, including, without limitation, that your use is for 29 | the sole purpose of programming logic devices manufactured by 30 | Intel and sold by Intel or its authorized distributors. Please 31 | refer to the applicable agreement for further details. 32 | 33 | 34 | 35 | +----------------------------------------------------------------------------+ 36 | ; IP Upgrade Summary ; 37 | +------------------------------+---------------------------------------------+ 38 | ; IP Components Upgrade Status ; Passed - Wed Jul 22 15:04:43 2020 ; 39 | ; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; 40 | ; Revision Name ; avideoboard ; 41 | ; Top-level Entity Name ; TestPattern ; 42 | ; Family ; MAX 10 ; 43 | +------------------------------+---------------------------------------------+ 44 | 45 | 46 | +------------------------------------------------------------------------------------------------------------------+ 47 | ; Successfully Upgraded IP Components ; 48 | +-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ 49 | ; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; 50 | +-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ 51 | ; PLL_14_625 ; ALTPLL ; 18.0 ; PLL_14_625.qip ; PLL_14_625.vhd ; PLL_14_625.qip ; ; 52 | ; PLL_14_411 ; ALTPLL ; 18.0 ; PLL_14_411.qip ; PLL_14_411.v ; PLL_14_411.qip ; ; 53 | ; PLL_14_387 ; ALTPLL ; 18.0 ; PLL_14_387.qip ; PLL_14_387.v ; PLL_14_387.qip ; ; 54 | +-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ 55 | 56 | 57 | +---------------------+ 58 | ; IP Upgrade Messages ; 59 | +---------------------+ 60 | Info (11902): Backing up file "PLL_14_625.vhd" to "PLL_14_625.BAK.vhd" 61 | Info (11837): Started upgrading IP component ALTPLL with file "PLL_14_625.vhd" 62 | Info (11902): Backing up file "PLL_14_411.v" to "PLL_14_411.BAK.v" 63 | Info (11837): Started upgrading IP component ALTPLL with file "PLL_14_411.v" 64 | Info (11902): Backing up file "PLL_14_387.v" to "PLL_14_387.BAK.v" 65 | Info (11837): Started upgrading IP component ALTPLL with file "PLL_14_387.v" 66 | Info (11131): Completed upgrading IP component ALTPLL with file "PLL_14_625.vhd" 67 | Info (11131): Completed upgrading IP component ALTPLL with file "PLL_14_411.v" 68 | Info (11131): Completed upgrading IP component ALTPLL with file "PLL_14_387.v" 69 | Info (23030): Evaluation of Tcl script c:/intelfpga_lite/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful 70 | Info: Quartus Prime Shell was successful. 0 errors, 0 warnings 71 | Info: Peak virtual memory: 4859 megabytes 72 | Info: Processing ended: Wed Jul 22 15:04:43 2020 73 | Info: Elapsed time: 00:01:16 74 | Info: Total CPU time (on all processors): 00:01:41 75 | 76 | 77 | -------------------------------------------------------------------------------- /quartus/avideoboard.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 14:44:52 November 01, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.0" 27 | DATE = "14:44:52 November 01, 2017" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "avideoboard" 32 | -------------------------------------------------------------------------------- /quartus/avideoboard.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/quartus/avideoboard.qws -------------------------------------------------------------------------------- /quartus/avideoboard.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 40.000 -name clkref [get_ports {CLKREF}] 2 | derive_pll_clocks 3 | -------------------------------------------------------------------------------- /zxspectrummod/README.md: -------------------------------------------------------------------------------- 1 | # ZXSpectrum Mod 2 | 3 | Built on the A-Video board, this is a modification usable for the 4 | ZX Spectrum 16K/48K versions (li'l old Speccy) that generates a 5 | YPbPr signal in either 288p or 576p to display on modern displays. 6 | 7 | ## Motivation 8 | 9 | As many home computers of the era, the ZX Spectrum (16K,48K) generates its 10 | video output in the form of a composite signal that was of notoriously 11 | bad quality, even if viewed on an analogue cathode ray tube. With 12 | modern LCD screens that do some digital preprocessing of the signal, 13 | the result is even more horrible. 14 | Even though the graphics chip (the ULA) outputs the video signal 15 | as a kind of RGB signal (YUV for these who know their colour formats), this 16 | signal is still very noisy and there is a lot of digital processing 17 | that shows up in the image. 18 | So this machine was also a good candidate for improvement with 19 | my A-Video board. 20 | 21 | ## Building 22 | 23 | The construction uses the A-Video board with a small daughter board for shifting 24 | the logic levels from 5V to 3.3V. 25 | To avoid soldering leads directly to the ULA, I took the 26 | signals from various via points on the board - basically wherever I could 27 | find one. In a few instances I soldered the leads to some other pins of 28 | various parts - but never to the ULA itself. 29 | 30 | You may notice that the mod just fits into the tiny space that is 31 | left in the ZX Spectrum after removing the RF modulator. That is no coincidence. 32 | The design of the A-Video board itself was totally driven by this exact space 33 | constraint. 34 | 35 | As a side note I want to mention that I have replaced the original 36 | voltage regulator with its huge heat sink with a modern buck converter 37 | that generates nearly no heat at all. This will probably reduce the stress on the 38 | power supply (the original one) as well reduce the temperature in the cramped 39 | computer case. 40 | 41 | ## Implementation details 42 | 43 | The FPGA chip passively listens to all relevant pins of the ULA and tries to make 44 | sense of what is going on. 45 | This was not so easy as it may seem, because I was not able to directly extract the pixel 46 | clock. There are no pins on the ULA that would directly provide this. The connection to the 47 | oscillator quartz is very sensitive to any added load and I could not reliably connect anything 48 | to it without rendering the system unstable. I could also not use the clock output to the CPU 49 | because the ULA turns this on and off in a totally unpredictable pattern to disable CPU 50 | access to the bus. 51 | 52 | I figured out that it is possible to listen to the CAS line which is driven by the ULA to fetch 53 | image data from the memory. All ULA accesses have a very distinct timing pattern and can be well 54 | separated from the accesses that are done on behalf of the CPU. For every 8 pixels that are drawn 55 | on the screen, the ULA fetches two bytes from the same memory row without re-sending the row 56 | address. The FPGA always monitors these bytes and can re-construct the contents of the 57 | video RAM. 58 | 59 | With a kind of custom PLL-circuit done in the FPGA, I can generate a video output signal that 60 | is in sync with the incoming stream of video data. 61 | 62 | 63 | ## Output 64 | 65 | The mod can be used to create three different output formats: 66 | * 288p (default) 67 | * 576p 68 | * 576p with scanlines 69 | 70 | Selecting the output can be done by jumper connectors or an external switch: 71 | * Connect GPIO1_18 to GPIO1_17 (or GND): 576p without scanlines 72 | * Connect GPIO1_15 to GPIO1_17 (or GND): 576p with scanlines 73 | 74 | ## Images 75 | ![alt text](doc/assembly.jpg "Overview over the whole system") 76 | ![alt text](doc/modboard.jpg "Installation of A-Video with daughter board") 77 | ![alt text](doc/connectors.jpg "Closed machine with YPbPr sockets") 78 | ![alt text](doc/game.jpg "576p video output on my TV") 79 | ![alt text](doc/closeup.jpg "Closeup of video output") 80 | -------------------------------------------------------------------------------- /zxspectrummod/board/board-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # +3V3 5 | # 6 | DEF +3V3 #PWR 0 0 Y Y 1 F P 7 | F0 "#PWR" 0 -150 50 H I C CNN 8 | F1 "+3V3" 0 140 50 H V C CNN 9 | F2 "" 0 0 50 H V C CNN 10 | F3 "" 0 0 50 H V C CNN 11 | ALIAS +3.3V 12 | DRAW 13 | P 2 0 1 0 -30 50 0 100 N 14 | P 2 0 1 0 0 0 0 100 N 15 | P 2 0 1 0 0 100 30 50 N 16 | X +3V3 1 0 0 0 U 50 50 1 1 W N 17 | ENDDRAW 18 | ENDDEF 19 | # 20 | # CONN_01X07 21 | # 22 | DEF CONN_01X07 P 0 40 Y N 1 F N 23 | F0 "P" 0 400 50 H V C CNN 24 | F1 "CONN_01X07" 100 0 50 V V C CNN 25 | F2 "" 0 0 50 H V C CNN 26 | F3 "" 0 0 50 H V C CNN 27 | $FPLIST 28 | Pin_Header_Straight_1X07 29 | Pin_Header_Angled_1X07 30 | Socket_Strip_Straight_1X07 31 | Socket_Strip_Angled_1X07 32 | $ENDFPLIST 33 | DRAW 34 | S -50 -350 50 350 0 1 0 N 35 | S -50 -295 10 -305 0 1 0 N 36 | S -50 -195 10 -205 0 1 0 N 37 | S -50 -95 10 -105 0 1 0 N 38 | S -50 5 10 -5 0 1 0 N 39 | S -50 105 10 95 0 1 0 N 40 | S -50 205 10 195 0 1 0 N 41 | S -50 305 10 295 0 1 0 N 42 | X P1 1 -200 300 150 R 50 50 1 1 P 43 | X P2 2 -200 200 150 R 50 50 1 1 P 44 | X P3 3 -200 100 150 R 50 50 1 1 P 45 | X P4 4 -200 0 150 R 50 50 1 1 P 46 | X P5 5 -200 -100 150 R 50 50 1 1 P 47 | X P6 6 -200 -200 150 R 50 50 1 1 P 48 | X P7 7 -200 -300 150 R 50 50 1 1 P 49 | ENDDRAW 50 | ENDDEF 51 | # 52 | # CONN_01X11 53 | # 54 | DEF CONN_01X11 P 0 40 Y N 1 F N 55 | F0 "P" 0 600 50 H V C CNN 56 | F1 "CONN_01X11" 100 0 50 V V C CNN 57 | F2 "" 0 0 50 H V C CNN 58 | F3 "" 0 0 50 H V C CNN 59 | $FPLIST 60 | Pin_Header_Straight_1X11 61 | Pin_Header_Angled_1X11 62 | Socket_Strip_Straight_1X11 63 | Socket_Strip_Angled_1X11 64 | $ENDFPLIST 65 | DRAW 66 | S -50 -495 10 -505 0 1 0 N 67 | S -50 -395 10 -405 0 1 0 N 68 | S -50 -295 10 -305 0 1 0 N 69 | S -50 -195 10 -205 0 1 0 N 70 | S -50 -95 10 -105 0 1 0 N 71 | S -50 5 10 -5 0 1 0 N 72 | S -50 105 10 95 0 1 0 N 73 | S -50 205 10 195 0 1 0 N 74 | S -50 305 10 295 0 1 0 N 75 | S -50 405 10 395 0 1 0 N 76 | S -50 505 10 495 0 1 0 N 77 | S -50 550 50 -550 0 1 0 N 78 | X P1 1 -200 500 150 R 50 50 1 1 P 79 | X P2 2 -200 400 150 R 50 50 1 1 P 80 | X P3 3 -200 300 150 R 50 50 1 1 P 81 | X P4 4 -200 200 150 R 50 50 1 1 P 82 | X P5 5 -200 100 150 R 50 50 1 1 P 83 | X P6 6 -200 0 150 R 50 50 1 1 P 84 | X P7 7 -200 -100 150 R 50 50 1 1 P 85 | X P8 8 -200 -200 150 R 50 50 1 1 P 86 | X P9 9 -200 -300 150 R 50 50 1 1 P 87 | X P10 10 -200 -400 150 R 50 50 1 1 P 88 | X P11 11 -200 -500 150 R 50 50 1 1 P 89 | ENDDRAW 90 | ENDDEF 91 | # 92 | # C_Small 93 | # 94 | DEF C_Small C 0 10 N N 1 F N 95 | F0 "C" 10 70 50 H V L CNN 96 | F1 "C_Small" 10 -80 50 H V L CNN 97 | F2 "" 0 0 50 H V C CNN 98 | F3 "" 0 0 50 H V C CNN 99 | $FPLIST 100 | C? 101 | C_????_* 102 | C_???? 103 | SMD*_c 104 | Capacitor* 105 | $ENDFPLIST 106 | DRAW 107 | P 2 0 1 13 -60 -20 60 -20 N 108 | P 2 0 1 12 -60 20 60 20 N 109 | X ~ 1 0 100 75 D 40 40 1 1 P 110 | X ~ 2 0 -100 80 U 40 40 1 1 P 111 | ENDDRAW 112 | ENDDEF 113 | # 114 | # GND 115 | # 116 | DEF GND #PWR 0 0 Y Y 1 F P 117 | F0 "#PWR" 0 -250 50 H I C CNN 118 | F1 "GND" 0 -150 50 H V C CNN 119 | F2 "" 0 0 50 H V C CNN 120 | F3 "" 0 0 50 H V C CNN 121 | DRAW 122 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 123 | X GND 1 0 0 0 D 50 50 1 1 W N 124 | ENDDRAW 125 | ENDDEF 126 | # 127 | # LVC245A 128 | # 129 | DEF LVC245A IC 0 40 Y Y 1 F N 130 | F0 "IC" -50 50 60 H V C CNN 131 | F1 "LVC245A" 50 -50 60 H V C CNN 132 | F2 "" 50 0 60 H I C CNN 133 | F3 "" 50 0 60 H I C CNN 134 | DRAW 135 | S -200 -100 300 -1100 0 1 0 N 136 | X DIR 1 -400 -150 200 R 50 50 1 1 I 137 | X A1 2 -400 -250 200 R 50 50 1 1 B 138 | X A2 3 -400 -350 200 R 50 50 1 1 B 139 | X A3 4 -400 -450 200 R 50 50 1 1 B 140 | X A4 5 -400 -550 200 R 50 50 1 1 B 141 | X A5 6 -400 -650 200 R 50 50 1 1 B 142 | X A6 7 -400 -750 200 R 50 50 1 1 B 143 | X A7 8 -400 -850 200 R 50 50 1 1 B 144 | X A8 9 -400 -950 200 R 50 50 1 1 B 145 | X GND 10 -400 -1050 200 R 50 50 1 1 W 146 | X VCC 20 500 -150 200 L 50 50 1 1 W 147 | X B8 11 500 -1050 200 L 50 50 1 1 B 148 | X B7 12 500 -950 200 L 50 50 1 1 B 149 | X B6 13 500 -850 200 L 50 50 1 1 B 150 | X B5 14 500 -750 200 L 50 50 1 1 B 151 | X B4 15 500 -650 200 L 50 50 1 1 B 152 | X B3 16 500 -550 200 L 50 50 1 1 B 153 | X B2 17 500 -450 200 L 50 50 1 1 B 154 | X B1 18 500 -350 200 L 50 50 1 1 B 155 | X OE 19 500 -250 200 L 50 50 1 1 I I 156 | ENDDRAW 157 | ENDDEF 158 | # 159 | # PWR_FLAG 160 | # 161 | DEF PWR_FLAG #FLG 0 0 N N 1 F P 162 | F0 "#FLG" 0 95 50 H I C CNN 163 | F1 "PWR_FLAG" 0 180 50 H V C CNN 164 | F2 "" 0 0 50 H V C CNN 165 | F3 "" 0 0 50 H V C CNN 166 | DRAW 167 | X pwr 1 0 0 0 U 50 50 0 0 w 168 | P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N 169 | ENDDRAW 170 | ENDDEF 171 | # 172 | #End Library 173 | -------------------------------------------------------------------------------- /zxspectrummod/board/board.pro: -------------------------------------------------------------------------------- 1 | update=27/10/2017 14:50:15 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [general] 27 | version=1 28 | [eeschema] 29 | version=1 30 | LibDir=../dvideoboard 31 | [eeschema/libraries] 32 | LibName1=power 33 | LibName2=device 34 | LibName3=transistors 35 | LibName4=conn 36 | LibName5=linear 37 | LibName6=regul 38 | LibName7=74xx 39 | LibName8=cmos4000 40 | LibName9=adc-dac 41 | LibName10=memory 42 | LibName11=xilinx 43 | LibName12=microcontrollers 44 | LibName13=dsp 45 | LibName14=microchip 46 | LibName15=analog_switches 47 | LibName16=motorola 48 | LibName17=texas 49 | LibName18=intel 50 | LibName19=audio 51 | LibName20=interface 52 | LibName21=digital-audio 53 | LibName22=philips 54 | LibName23=display 55 | LibName24=cypress 56 | LibName25=siliconi 57 | LibName26=opto 58 | LibName27=atmel 59 | LibName28=contrib 60 | LibName29=valves 61 | LibName30=components 62 | [schematic_editor] 63 | version=1 64 | PageLayoutDescrFile= 65 | PlotDirectoryName= 66 | SubpartIdSeparator=0 67 | SubpartFirstId=65 68 | NetFmtName=Pcbnew 69 | SpiceForceRefPrefix=0 70 | SpiceUseNetNumbers=0 71 | LabSize=60 72 | -------------------------------------------------------------------------------- /zxspectrummod/board/components.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /zxspectrummod/board/components.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /zxspectrummod/board/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name footprints)(type KiCad)(uri ${KIPRJMOD}/footprints.pretty)(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /zxspectrummod/board/gerber/board-Edge.Cuts.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.FileFunction,Profile,NP* 2 | %FSLAX46Y46*% 3 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 4 | G04 Created by KiCad (PCBNEW 4.0.4-stable) date 12/09/17 21:43:03* 5 | %MOMM*% 6 | %LPD*% 7 | G01* 8 | G04 APERTURE LIST* 9 | %ADD10C,0.100000*% 10 | %ADD11C,0.150000*% 11 | G04 APERTURE END LIST* 12 | D10* 13 | D11* 14 | X114935000Y-88265000D02* 15 | X114935000Y-69215000D01* 16 | X161925000Y-88265000D02* 17 | X114935000Y-88265000D01* 18 | X161925000Y-69215000D02* 19 | X161925000Y-88265000D01* 20 | X114935000Y-69215000D02* 21 | X161925000Y-69215000D01* 22 | M02* 23 | -------------------------------------------------------------------------------- /zxspectrummod/board/gerber/board.drl: -------------------------------------------------------------------------------- 1 | M48 2 | METRIC,TZ 3 | T1C0.400 4 | T2C1.000 5 | % 6 | G90 7 | G05 8 | T1 9 | X124968Y-71882 10 | X127000Y-82042 11 | X127254Y-79248 12 | X128524Y-76708 13 | X129286Y-78232 14 | X129286Y-82042 15 | X131826Y-83566 16 | X138430Y-71120 17 | X141224Y-72390 18 | X147828Y-71882 19 | X147828Y-74168 20 | X147828Y-76454 21 | X147828Y-79248 22 | X147828Y-81788 23 | X151638Y-82042 24 | X151892Y-71882 25 | X157226Y-82296 26 | T2 27 | X116840Y-71120 28 | X116840Y-73660 29 | X116840Y-76200 30 | X116840Y-78740 31 | X116840Y-81280 32 | X116840Y-83820 33 | X116840Y-86360 34 | X124460Y-86360 35 | X127000Y-86360 36 | X129540Y-86360 37 | X132080Y-86360 38 | X134620Y-86360 39 | X137160Y-86360 40 | X139700Y-86360 41 | X142240Y-86360 42 | X144780Y-86360 43 | X147320Y-86360 44 | X149860Y-86360 45 | X160020Y-71120 46 | X160020Y-73660 47 | X160020Y-76200 48 | X160020Y-78740 49 | X160020Y-81280 50 | X160020Y-83820 51 | X160020Y-86360 52 | T0 53 | M30 54 | -------------------------------------------------------------------------------- /zxspectrummod/board/gerber/gerber.zip: -------------------------------------------------------------------------------- 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assignments for the ZX-Spectrum mod (Rev.2) 2 | 3 | Mod board in Mod board out A-Video board MAX 10 pin 4 | D7 OUT1 1 GPIO1 14 98 5 | D6 OUT1 2 GPIO1 12 92 6 | D5 OUT1 3 GPIO1 10 88 7 | D4 OUT1 4 GPIO1 8 81 8 | D3 OUT1 5 GPIO1 6 79 9 | D2 OUT1 6 GPIO1 4 77 10 | D1 OUT1 7 GPIO1 2 75 11 | D0 OUT2 2 GPIO2 3 41 12 | CAS OUT2 3 GPIO2 5 39 13 | IOREQ OUT2 4 GPIO2 7 32 14 | WR OUT2 5 GPIO2 9 28 15 | -------------------------------------------------------------------------------- /zxspectrummod/firmware/zxspectrum_1_1.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/zxspectrummod/firmware/zxspectrum_1_1.pof -------------------------------------------------------------------------------- /zxspectrummod/quartus/PLL4PHASES.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component PLL4PHASES 17 | PORT 18 | ( 19 | inclk0 : IN STD_LOGIC := '0'; 20 | c0 : OUT STD_LOGIC ; 21 | c1 : OUT STD_LOGIC ; 22 | c2 : OUT STD_LOGIC ; 23 | c3 : OUT STD_LOGIC 24 | ); 25 | end component; 26 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/PLL4PHASES.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/PLL4PHASES.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL4PHASES.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL4PHASES.cmp"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL4PHASES.ppf"] 7 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/Program.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/zxspectrummod/quartus/output_files/") File("zxspectrum.pof") MfrSpec(OpMask(3) Child_OpMask(2 3 3)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/Run.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M02SCE144) Path("C:/Users/Reinhard/Documents/GitHub/A-VideoBoard/zxspectrummod/quartus/output_files/") File("zxspectrum.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/ZXVideoRAM.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, the Altera Quartus Prime License Agreement, 9 | --the Altera MegaCore Function License Agreement, or other 10 | --applicable license agreement, including, without limitation, 11 | --that your use is for the sole purpose of programming logic 12 | --devices manufactured by Altera and sold by Altera or its 13 | --authorized distributors. Please refer to the applicable 14 | --agreement for further details. 15 | 16 | 17 | component ZXVideoRAM 18 | PORT 19 | ( 20 | data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 21 | rdaddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0); 22 | rdclock : IN STD_LOGIC ; 23 | wraddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0); 24 | wrclock : IN STD_LOGIC := '1'; 25 | wren : IN STD_LOGIC := '0'; 26 | q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) 27 | ); 28 | end component; 29 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/ZXVideoRAM.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "16.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ZXVideoRAM.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ZXVideoRAM.cmp"] 6 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | BANDWIDTH_TYPE=AUTO 2 | CLK0_DIVIDE_BY=25 3 | CLK0_DUTY_CYCLE=50 4 | CLK0_MULTIPLY_BY=112 5 | CLK0_PHASE_SHIFT=0 6 | CLK1_DIVIDE_BY=25 7 | CLK1_DUTY_CYCLE=50 8 | CLK1_MULTIPLY_BY=112 9 | CLK1_PHASE_SHIFT=1116 10 | CLK2_DIVIDE_BY=25 11 | CLK2_DUTY_CYCLE=50 12 | CLK2_MULTIPLY_BY=112 13 | CLK2_PHASE_SHIFT=2232 14 | CLK3_DIVIDE_BY=25 15 | CLK3_DUTY_CYCLE=50 16 | CLK3_MULTIPLY_BY=112 17 | CLK3_PHASE_SHIFT=3348 18 | COMPENSATE_CLOCK=CLK0 19 | INCLK0_INPUT_FREQUENCY=40000 20 | INTENDED_DEVICE_FAMILY="MAX 10" 21 | LPM_TYPE=altpll 22 | OPERATION_MODE=NORMAL 23 | PLL_TYPE=AUTO 24 | PORT_ACTIVECLOCK=PORT_UNUSED 25 | PORT_ARESET=PORT_UNUSED 26 | PORT_CLKBAD0=PORT_UNUSED 27 | PORT_CLKBAD1=PORT_UNUSED 28 | PORT_CLKLOSS=PORT_UNUSED 29 | PORT_CLKSWITCH=PORT_UNUSED 30 | PORT_CONFIGUPDATE=PORT_UNUSED 31 | PORT_FBIN=PORT_UNUSED 32 | PORT_INCLK0=PORT_USED 33 | PORT_INCLK1=PORT_UNUSED 34 | PORT_LOCKED=PORT_UNUSED 35 | PORT_PFDENA=PORT_UNUSED 36 | PORT_PHASECOUNTERSELECT=PORT_UNUSED 37 | PORT_PHASEDONE=PORT_UNUSED 38 | PORT_PHASESTEP=PORT_UNUSED 39 | PORT_PHASEUPDOWN=PORT_UNUSED 40 | PORT_PLLENA=PORT_UNUSED 41 | PORT_SCANACLR=PORT_UNUSED 42 | PORT_SCANCLK=PORT_UNUSED 43 | PORT_SCANCLKENA=PORT_UNUSED 44 | PORT_SCANDATA=PORT_UNUSED 45 | PORT_SCANDATAOUT=PORT_UNUSED 46 | PORT_SCANDONE=PORT_UNUSED 47 | PORT_SCANREAD=PORT_UNUSED 48 | PORT_SCANWRITE=PORT_UNUSED 49 | PORT_clk0=PORT_USED 50 | PORT_clk1=PORT_USED 51 | PORT_clk2=PORT_USED 52 | PORT_clk3=PORT_USED 53 | PORT_clk4=PORT_UNUSED 54 | PORT_clk5=PORT_UNUSED 55 | PORT_clkena0=PORT_UNUSED 56 | PORT_clkena1=PORT_UNUSED 57 | PORT_clkena2=PORT_UNUSED 58 | PORT_clkena3=PORT_UNUSED 59 | PORT_clkena4=PORT_UNUSED 60 | PORT_clkena5=PORT_UNUSED 61 | PORT_extclk0=PORT_UNUSED 62 | PORT_extclk1=PORT_UNUSED 63 | PORT_extclk2=PORT_UNUSED 64 | PORT_extclk3=PORT_UNUSED 65 | WIDTH_CLOCK=5 66 | DEVICE_FAMILY="MAX 10" 67 | CBX_AUTO_BLACKBOX=ALL 68 | inclk 69 | inclk 70 | clk 71 | clk 72 | clk 73 | clk 74 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/zxspectrum.ipregen.rpt: -------------------------------------------------------------------------------- 1 | IP Upgrade report for zxspectrum 2 | Sun Sep 22 12:29:09 2019 3 | Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. IP Upgrade Summary 11 | 3. Successfully Upgraded IP Components 12 | 4. IP Upgrade Messages 13 | 14 | 15 | 16 | ---------------- 17 | ; Legal Notice ; 18 | ---------------- 19 | Copyright (C) 2018 Intel Corporation. All rights reserved. 20 | Your use of Intel Corporation's design tools, logic functions 21 | and other software and tools, and its AMPP partner logic 22 | functions, and any output files from any of the foregoing 23 | (including device programming or simulation files), and any 24 | associated documentation or information are expressly subject 25 | to the terms and conditions of the Intel Program License 26 | Subscription Agreement, the Intel Quartus Prime License Agreement, 27 | the Intel FPGA IP License Agreement, or other applicable license 28 | agreement, including, without limitation, that your use is for 29 | the sole purpose of programming logic devices manufactured by 30 | Intel and sold by Intel or its authorized distributors. Please 31 | refer to the applicable agreement for further details. 32 | 33 | 34 | 35 | +----------------------------------------------------------------------------+ 36 | ; IP Upgrade Summary ; 37 | +------------------------------+---------------------------------------------+ 38 | ; IP Components Upgrade Status ; Passed - Sun Sep 22 12:29:09 2019 ; 39 | ; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; 40 | ; Revision Name ; zxspectrum ; 41 | ; Top-level Entity Name ; ULA2YPbPr ; 42 | ; Family ; MAX 10 ; 43 | +------------------------------+---------------------------------------------+ 44 | 45 | 46 | +------------------------------------------------------------------------------------------------------------------+ 47 | ; Successfully Upgraded IP Components ; 48 | +-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ 49 | ; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; 50 | +-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ 51 | ; PLL4PHASES ; ALTPLL ; 16.0 ; PLL4PHASES.qip ; PLL4PHASES.vhd ; PLL4PHASES.qip ; ; 52 | +-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ 53 | 54 | 55 | +---------------------+ 56 | ; IP Upgrade Messages ; 57 | +---------------------+ 58 | Info (11902): Backing up file "PLL4PHASES.vhd" to "PLL4PHASES.BAK.vhd" 59 | Info (11837): Started upgrading IP component ALTPLL with file "PLL4PHASES.vhd" 60 | Info (11131): Completed upgrading IP component ALTPLL with file "PLL4PHASES.vhd" 61 | Info (23030): Evaluation of Tcl script c:/intelfpga_lite/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful 62 | Info: Quartus Prime Shell was successful. 0 errors, 0 warnings 63 | Info: Peak virtual memory: 4899 megabytes 64 | Info: Processing ended: Sun Sep 22 12:29:09 2019 65 | Info: Elapsed time: 00:00:41 66 | Info: Total CPU time (on all processors): 00:01:10 67 | 68 | 69 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/zxspectrum.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 13:22:20 October 07, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.0" 27 | DATE = "13:22:20 October 07, 2017" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "zxspectrum" 32 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/zxspectrum.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/c0pperdragon/A-VideoBoard/cdc04b6049de80b1d2bf97a422622d0b9c220317/zxspectrummod/quartus/zxspectrum.qws -------------------------------------------------------------------------------- /zxspectrummod/quartus/zxspectrum.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 40.000 -name clk25 [get_ports {CLKREF}] 2 | derive_pll_clocks 3 | -------------------------------------------------------------------------------- /zxspectrummod/quartus/zxspectrum.sdc.bak: -------------------------------------------------------------------------------- 1 | create_clock -period 20.000 -name clk50 [get_ports {CLKREF}] 2 | derive_pll_clocks 3 | --------------------------------------------------------------------------------