├── .gitignore
├── 270p
├── Lumacode270p50.txt
├── Lumacode270p_specs.txt
├── convertimage.py
├── example_270p
│ ├── example_270p.ino
│ └── picture.h
└── lumacode_logo.bmp
├── README.md
├── cabletester
├── DIN_connector_pinout.svg.png
├── atari_st_pinouts.gif
├── diamond
│ ├── .run_manager.ini
│ ├── .spread_sheet.ini
│ ├── .spreadsheet_view.ini
│ ├── CableTester.ccl
│ ├── CableTester.ldf
│ ├── CableTester.lpf
│ ├── CableTester1.sty
│ ├── PLL_57.edn
│ ├── PLL_57.ipx
│ ├── PLL_57.jhd
│ ├── PLL_57.lpc
│ ├── PLL_57.naf
│ ├── PLL_57.sort
│ ├── PLL_57.srp
│ ├── PLL_57.sym
│ ├── PLL_57.vhd
│ ├── PLL_57_generate.log
│ ├── PLL_57_tmpl.vhd
│ ├── _math_real.vhd
│ ├── generate_core.tcl
│ ├── generate_ngd.tcl
│ ├── msg_file.log
│ ├── promote.xml
│ ├── reportview.xml
│ └── source
│ │ └── EGA.vhd
└── pinouts.txt
├── misc
├── VICIIdizer_R56A.jed
├── lumacode_logo.png
├── lumacode_logo_blackwhite.png
└── productplan.txt
├── signalgenerator
├── README.md
├── board
│ ├── Library.bak
│ ├── Library.kicad_sym
│ ├── board-backups
│ │ ├── board-2023-06-22_194020.zip
│ │ ├── board-2023-06-22_195446.zip
│ │ ├── board-2023-06-22_202431.zip
│ │ ├── board-2023-06-23_121358.zip
│ │ └── board-2023-06-29_160753.zip
│ ├── board.kicad_pcb
│ ├── board.kicad_prl
│ ├── board.kicad_pro
│ ├── board.kicad_sch
│ ├── board.pdf
│ ├── footprints.pretty
│ │ └── RCA_JACK.kicad_mod
│ ├── fp-info-cache
│ ├── fp-lib-table
│ └── sym-lib-table
├── diamond
│ ├── .run_manager.ini
│ ├── .setting.ini
│ ├── .spread_sheet.ini
│ ├── .spreadsheet_view.ini
│ ├── EFB_FOR_PLL.edn
│ ├── EFB_FOR_PLL.ipx
│ ├── EFB_FOR_PLL.jhd
│ ├── EFB_FOR_PLL.lpc
│ ├── EFB_FOR_PLL.naf
│ ├── EFB_FOR_PLL.sort
│ ├── EFB_FOR_PLL.srp
│ ├── EFB_FOR_PLL.sym
│ ├── EFB_FOR_PLL.vhd
│ ├── EFB_FOR_PLL_generate.log
│ ├── EFB_FOR_PLL_tmpl.vhd
│ ├── EFB_generate.log
│ ├── EFB_tmpl.vhd
│ ├── PLL_24.edn
│ ├── PLL_24.ipx
│ ├── PLL_24.jhd
│ ├── PLL_24.lpc
│ ├── PLL_24.naf
│ ├── PLL_24.sort
│ ├── PLL_24.srp
│ ├── PLL_24.sym
│ ├── PLL_24.vhd
│ ├── PLL_24_generate.log
│ ├── PLL_24_tmpl.vhd
│ ├── SignalGenerator.ccl
│ ├── SignalGenerator.ldf
│ ├── SignalGenerator.lpf
│ ├── SignalGenerator1.sty
│ ├── TITLES.edn
│ ├── TITLES.ipx
│ ├── TITLES.jhd
│ ├── TITLES.lpc
│ ├── TITLES.naf
│ ├── TITLES.sort
│ ├── TITLES.srp
│ ├── TITLES.sym
│ ├── TITLES.vhd
│ ├── TITLES_generate.log
│ ├── TITLES_tmpl.vhd
│ ├── _math_real.vhd
│ ├── generate_core.tcl
│ ├── generate_ngd.tcl
│ ├── msg_file.log
│ ├── promote.xml
│ ├── reportview.xml
│ ├── source
│ │ ├── ClockGenerator.vhd
│ │ ├── Frequencies.vhd
│ │ ├── SignalGenerator.vhd
│ │ └── titles.mem
│ └── tb_TITLES_tmpl.vhd
└── doc
│ ├── AtariST400p72.txt
│ ├── Lumacode270p50.txt
│ ├── Lumacode270p_specs.txt
│ ├── calc720p.py
│ ├── calcpll.py
│ ├── signalgenerator.jpg
│ └── switches.txt
└── testrig
├── 100mhz
├── .run_manager.ini
├── .spread_sheet.ini
├── .spreadsheet_view.ini
├── Generate100MHz.ccl
├── Generate100MHz.ldf
├── Generate100MHz.lpf
├── Generate100MHz.sdc
├── Generate100MHz1.sty
├── PLL200.edn
├── PLL200.ipx
├── PLL200.jhd
├── PLL200.lpc
├── PLL200.naf
├── PLL200.sort
├── PLL200.srp
├── PLL200.sym
├── PLL200.vhd
├── PLL200_generate.log
├── PLL200_tmpl.vhd
├── _math_real.vhd
├── generate_core.tcl
├── generate_ngd.tcl
├── msg_file.log
├── promote.xml
├── reportview.xml
└── source
│ └── Generate100MHz.vhd
├── 14_3mhz
├── .run_manager.ini
├── .spread_sheet.ini
├── .spreadsheet_view.ini
├── Generate14_3Mhz.ccl
├── Generate14_3Mhz.ldf
├── Generate14_3Mhz.lpf
├── Generate14_3Mhz1.sty
├── PLL28_6.edn
├── PLL28_6.ipx
├── PLL28_6.jhd
├── PLL28_6.lpc
├── PLL28_6.naf
├── PLL28_6.sort
├── PLL28_6.srp
├── PLL28_6.sym
├── PLL28_6.vhd
├── PLL28_6_generate.log
├── PLL28_6_tmpl.vhd
├── _math_real.vhd
├── generate_core.tcl
├── generate_ngd.tcl
├── msg_file.log
├── promote.xml
├── reportview.xml
└── source
│ └── Generate14_3MHz.vhd
├── amigaboost
├── .run_manager.ini
├── .spread_sheet.ini
├── .spreadsheet_view.ini
├── AmigaBoost.ccl
├── AmigaBoost.ldf
├── AmigaBoost.lpf
├── AmigaBoost1.sty
├── PLL_56_81.edn
├── PLL_56_81.ipx
├── PLL_56_81.jhd
├── PLL_56_81.lpc
├── PLL_56_81.naf
├── PLL_56_81.sort
├── PLL_56_81.srp
├── PLL_56_81.sym
├── PLL_56_81.vhd
├── PLL_56_81_generate.log
├── PLL_56_81_tmpl.vhd
├── PLL_56_94.edn
├── PLL_56_94.ipx
├── PLL_56_94.jhd
├── PLL_56_94.lpc
├── PLL_56_94.naf
├── PLL_56_94.sort
├── PLL_56_94.srp
├── PLL_56_94.sym
├── PLL_56_94.vhd
├── PLL_56_94_generate.log
├── PLL_56_94_tmpl.vhd
├── _math_real.vhd
├── generate_core.tcl
├── generate_ngd.tcl
├── msg_file.log
├── promote.xml
├── reportview.xml
└── source
│ └── AmigaBoost.vhd
├── board
├── Library.bak
├── Library.kicad_sym
├── board.kicad_prl
├── board.kicad_pro
├── board.kicad_sch
├── board.pdf
├── board.plt
└── sym-lib-table
├── calcpll.py
└── ledanimation
├── .run_manager.ini
├── .spread_sheet.ini
├── .spreadsheet_view.ini
├── LEDAnimation.ccl
├── LEDAnimation.ldf
├── LEDAnimation.lpf
├── LEDAnimation1.sty
├── promote.xml
├── reportview.xml
└── source
└── LEDAnimation.vhd
/.gitignore:
--------------------------------------------------------------------------------
1 |
2 | **/*-backups
3 | **/impl1
4 | **/*_tcr.dir
5 | **/*_tcl.html
6 |
7 | **/Lumacode270p
--------------------------------------------------------------------------------
/270p/Lumacode270p50.txt:
--------------------------------------------------------------------------------
1 | sampling=6,6,6,6,6,6,6,1,1,0,3,1,0,0,0,2,0,2,1,0,58,40,256,256,10,26,256,256
2 | geometry=4,36,480,270,480,270,2,2,3,2,24000000,1539,4000,312,4,0,0
3 | palette=RGB6(Lumacode)
4 | palette_control=10
5 |
--------------------------------------------------------------------------------
/270p/Lumacode270p_specs.txt:
--------------------------------------------------------------------------------
1 | 1080p-scaleable SD signal (16:9)
2 |
3 | Input 50Hz:
4 | v sync 3 lines
5 | v back porch 37 lines
6 | v visible 270 lines
7 | v front porch 2 lines
8 | v total 312 lines
9 |
10 | h sync 24 pixels (3 us)
11 | h back porch 6 pixels (0.75 us)
12 | h visible 480 pixels (60 us)
13 | h front porch 3 pixels (0.375 us)
14 | h total 513 pixels (64.125 us)
15 |
16 | pixel rate 8 MHz
17 | frame rate 49.9825 Hz
18 |
--------------------------------------------------------------------------------
/270p/convertimage.py:
--------------------------------------------------------------------------------
1 | import math
2 |
3 | def conv(source, target):
4 | file1 = open(source,"rb")
5 | file1.read(54);
6 | data = file1.read(3*192*256)
7 | file1.close()
8 |
9 | file2 = open(target,'w')
10 | for y in range(256):
11 | accu=0
12 | for x in range(192):
13 | bit = x % 4;
14 | i = 3*((191-x)+192*(255-y))
15 | l = math.floor( (data[i] + data[i+1] + data[i+2]) / (3*64))
16 | accu = (accu<<2) | l
17 | if bit==3:
18 | print(accu,end="",file=file2)
19 | if y<255 or x<191:
20 | print(",",end="",file=file2)
21 | accu=0
22 | print(file=file2)
23 | file2.close()
24 |
25 | conv("lumacode_logo.bmp", "example_270p/picture.h")
26 |
--------------------------------------------------------------------------------
/270p/lumacode_logo.bmp:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/270p/lumacode_logo.bmp
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # LumaCode
2 | Definition of the "LumaCode" signal standard and documentation of various implementations.
3 |
4 | * [Documentation wiki](https://github.com/c0pperdragon/LumaCode/wiki)
5 | * [Issue tracking](https://github.com/c0pperdragon/LumaCode/issues)
6 | * [Reference implementation](signalgenerator)
7 |
--------------------------------------------------------------------------------
/cabletester/DIN_connector_pinout.svg.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/cabletester/DIN_connector_pinout.svg.png
--------------------------------------------------------------------------------
/cabletester/atari_st_pinouts.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/cabletester/atari_st_pinouts.gif
--------------------------------------------------------------------------------
/cabletester/diamond/.run_manager.ini:
--------------------------------------------------------------------------------
1 | [Runmanager]
2 | Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xdc\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
3 | windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4 | headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
5 |
6 | [impl1%3CStrategy1%3E]
7 | isChecked=false
8 | isHidden=false
9 | isExpanded=false
10 |
--------------------------------------------------------------------------------
/cabletester/diamond/.spread_sheet.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | COLUMN_POS_INFO_NAME_-1_0=Prioritize
3 | COLUMN_POS_INFO_NAME_-1_1=PIO Register
4 |
--------------------------------------------------------------------------------
/cabletester/diamond/.spreadsheet_view.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | pin_sort_type=0
3 | pin_sort_ascending=true
4 | sig_sort_type=0
5 | sig_sort_ascending=true
6 | active_Sheet=Port Assignments
7 |
8 | [Port%20Assignments]
9 | Name="171,0"
10 | Group%20By="83,1"
11 | Pin="53,2"
12 | BANK="66,3"
13 | BANK_VCC="93,4"
14 | VREF="63,5"
15 | IO_TYPE="185,6"
16 | PULLMODE="127,7"
17 | DRIVE="70,8"
18 | SLEWRATE="121,9"
19 | CLAMP="89,10"
20 | OPENDRAIN="100,11"
21 | DIFFRESISTOR="114,12"
22 | DIFFDRIVE="95,13"
23 | HYSTERESIS="125,14"
24 | Outload%20%28pF%29="101,15"
25 | MaxSkew="86,16"
26 | Clock%20Load%20Only="118,17"
27 | SwitchingID="98,18"
28 | Ground%20plane%20PCB%20noise%20%28mV%29="185,19"
29 | Power%20plane%20PCB%20noise%20%28mV%29="182,20"
30 | SSO%20Allowance%28%25%29="134,21"
31 | sort_columns="Name,Ascending"
32 |
33 | [Pin%20Assignments]
34 | Pin="95,0"
35 | Pad%20Name="94,1"
36 | Dual%20Function="205,2"
37 | Polarity="77,3"
38 | BANK="0,4"
39 | BANK_VCC="93,5"
40 | IO_TYPE="104,6"
41 | Signal%20Name="98,7"
42 | Signal%20Type="95,8"
43 | sort_columns="Pin,Ascending"
44 |
45 | [Clock%20Resource]
46 | Clock%20Type="100,ELLIPSIS"
47 | Clock%20Name="100,ELLIPSIS"
48 | Selection="100,ELLIPSIS"
49 |
50 | [Global%20Preferences]
51 | Preference%20Name="288,ELLIPSIS"
52 | Preference%20Value="268,ELLIPSIS"
53 |
54 | [Cell%20Mapping]
55 | Type="100,ELLIPSIS"
56 | Name="100,ELLIPSIS"
57 | Din\Dout="100,ELLIPSIS"
58 | PIO%20Register="100,ELLIPSIS"
59 |
60 | [Route%20Priority]
61 | Type="100,ELLIPSIS"
62 | Name="100,ELLIPSIS"
63 | Prioritize="100,ELLIPSIS"
64 |
65 | [Timing%20Preferences]
66 | Preference%20Name="183,ELLIPSIS"
67 | Preference%20Value="128,ELLIPSIS"
68 | Preference%20Unit="121,ELLIPSIS"
69 |
70 | [Group]
71 | Group%20Type\Name="160,ELLIPSIS"
72 | Value="48,ELLIPSIS"
73 |
74 | [Misc%20Preferences]
75 | Preference%20Name="147,ELLIPSIS"
76 | Preference%20Value="128,ELLIPSIS"
77 |
--------------------------------------------------------------------------------
/cabletester/diamond/CableTester.ccl:
--------------------------------------------------------------------------------
1 | VERSION=20110520
2 |
--------------------------------------------------------------------------------
/cabletester/diamond/CableTester.ldf:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
--------------------------------------------------------------------------------
/cabletester/diamond/CableTester.lpf:
--------------------------------------------------------------------------------
1 | BLOCK RESETPATHS ;
2 | BLOCK ASYNCPATHS ;
3 | LOCATE COMP "CLK25" SITE "21" ;
4 | LOCATE COMP "CP[0]" SITE "17" ;
5 | LOCATE COMP "CP[1]" SITE "16" ;
6 | LOCATE COMP "CP[2]" SITE "28" ;
7 | LOCATE COMP "CP[3]" SITE "27" ;
8 | LOCATE COMP "D[0]" SITE "13" ;
9 | LOCATE COMP "D[1]" SITE "12" ;
10 | LOCATE COMP "D[2]" SITE "11" ;
11 | LOCATE COMP "D[3]" SITE "10" ;
12 | LOCATE COMP "D[5]" SITE "8" ;
13 | LOCATE COMP "D[6]" SITE "5" ;
14 | LOCATE COMP "D[7]" SITE "4" ;
15 | LOCATE COMP "D[4]" SITE "9" ;
16 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.jhd:
--------------------------------------------------------------------------------
1 | MODULE PLL_57 DEFIN PLL_57.vhd
2 | SUBMODULE EHXPLLJ
3 | INSTANCE PLLInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-4SG32C
5 | SpeedGrade=4
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=PLL
15 | CoreRevision=5.8
16 | ModuleName=PLL_57
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=11/19/2024
20 | Time=23:41:16
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=None
28 | Order=None
29 | IO=0
30 | mode=Divider
31 | CLKI=25
32 | CLKI_DIV=2
33 | BW=1.146
34 | VCO=687.500
35 | fb_mode=CLKOP
36 | CLKFB_DIV=1
37 | FRACN_ENABLE=0
38 | FRACN_DIV=0
39 | DynamicPhase=STATIC
40 | ClkEnable=0
41 | Standby=0
42 | Enable_sel=0
43 | PLLRst=0
44 | PLLMRst=0
45 | ClkOS2Rst=0
46 | ClkOS3Rst=0
47 | LockSig=0
48 | LockStk=0
49 | WBProt=0
50 | OPBypass=0
51 | OPUseDiv=0
52 | CLKOP_DIV=55
53 | FREQ_PIN_CLKOP=100
54 | OP_Tol=0.0
55 | CLKOP_AFREQ=12.500000
56 | CLKOP_PHASEADJ=0
57 | CLKOP_TRIM_POL=Rising
58 | CLKOP_TRIM_DELAY=0
59 | EnCLKOS=1
60 | OSBypass=0
61 | OSUseDiv=0
62 | CLKOS_DIV=12
63 | FREQ_PIN_CLKOS=100
64 | OS_Tol=0.0
65 | CLKOS_AFREQ=57.291667
66 | CLKOS_PHASEADJ=0
67 | CLKOS_TRIM_POL=Rising
68 | CLKOS_TRIM_DELAY=0
69 | EnCLKOS2=0
70 | OS2Bypass=0
71 | OS2UseDiv=0
72 | CLKOS2_DIV=1
73 | FREQ_PIN_CLKOS2=100
74 | OS2_Tol=0.0
75 | CLKOS2_AFREQ=
76 | CLKOS2_PHASEADJ=0
77 | EnCLKOS3=0
78 | OS3Bypass=0
79 | OS3UseDiv=0
80 | CLKOS3_DIV=1
81 | FREQ_PIN_CLKOS3=100
82 | OS3_Tol=0.0
83 | CLKOS3_AFREQ=
84 | CLKOS3_PHASEADJ=0
85 |
86 | [Command]
87 | cmd_line= -w -n PLL_57 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 12 -phase_cntl STATIC -fb_mode 1
88 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.naf:
--------------------------------------------------------------------------------
1 | CLKI i
2 | CLKOP o
3 | CLKOS o
4 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.sort:
--------------------------------------------------------------------------------
1 | PLL_57.vhd
2 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Tue Nov 19 23:41:16 2024
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_57 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 12 -phase_cntl STATIC -fb_mode 1
11 | Circuit name : PLL_57
12 | Module type : pll
13 | Module Version : 5.7
14 | Ports :
15 | Inputs : CLKI
16 | Outputs : CLKOP, CLKOS
17 | I/O buffer : not inserted
18 | EDIF output : PLL_57.edn
19 | VHDL output : PLL_57.vhd
20 | VHDL template : PLL_57_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : PLL_57.srp
24 | Element Usage :
25 | EHXPLLJ : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/cabletester/diamond/PLL_57.sym
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | -- Module Version: 5.7
3 | --C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_57 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 12 -phase_cntl STATIC -fb_mode 1
4 |
5 | -- Tue Nov 19 23:41:16 2024
6 |
7 | library IEEE;
8 | use IEEE.std_logic_1164.all;
9 | -- synopsys translate_off
10 | library MACHXO2;
11 | use MACHXO2.components.all;
12 | -- synopsys translate_on
13 |
14 | entity PLL_57 is
15 | port (
16 | CLKI: in std_logic;
17 | CLKOP: out std_logic;
18 | CLKOS: out std_logic);
19 | end PLL_57;
20 |
21 | architecture Structure of PLL_57 is
22 |
23 | -- internal signal declarations
24 | signal LOCK: std_logic;
25 | signal CLKOS_t: std_logic;
26 | signal CLKOP_t: std_logic;
27 | signal scuba_vlo: std_logic;
28 |
29 | -- local component declarations
30 | component VLO
31 | port (Z: out std_logic);
32 | end component;
33 | component EHXPLLJ
34 | generic (INTFB_WAKE : in String; DDRST_ENA : in String;
35 | DCRST_ENA : in String; MRST_ENA : in String;
36 | PLLRST_ENA : in String; DPHASE_SOURCE : in String;
37 | STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
38 | OUTDIVIDER_MUXC2 : in String;
39 | OUTDIVIDER_MUXB2 : in String;
40 | OUTDIVIDER_MUXA2 : in String;
41 | PREDIVIDER_MUXD1 : in Integer;
42 | PREDIVIDER_MUXC1 : in Integer;
43 | PREDIVIDER_MUXB1 : in Integer;
44 | PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
45 | PLL_LOCK_MODE : in Integer;
46 | CLKOS_TRIM_DELAY : in Integer;
47 | CLKOS_TRIM_POL : in String;
48 | CLKOP_TRIM_DELAY : in Integer;
49 | CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
50 | FRACN_ENABLE : in String; FEEDBK_PATH : in String;
51 | CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
52 | CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
53 | CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
54 | CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
55 | VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
56 | VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
57 | CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
58 | CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
59 | CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
60 | CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
61 | CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
62 | port (CLKI: in std_logic; CLKFB: in std_logic;
63 | PHASESEL1: in std_logic; PHASESEL0: in std_logic;
64 | PHASEDIR: in std_logic; PHASESTEP: in std_logic;
65 | LOADREG: in std_logic; STDBY: in std_logic;
66 | PLLWAKESYNC: in std_logic; RST: in std_logic;
67 | RESETM: in std_logic; RESETC: in std_logic;
68 | RESETD: in std_logic; ENCLKOP: in std_logic;
69 | ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
70 | ENCLKOS3: in std_logic; PLLCLK: in std_logic;
71 | PLLRST: in std_logic; PLLSTB: in std_logic;
72 | PLLWE: in std_logic; PLLADDR4: in std_logic;
73 | PLLADDR3: in std_logic; PLLADDR2: in std_logic;
74 | PLLADDR1: in std_logic; PLLADDR0: in std_logic;
75 | PLLDATI7: in std_logic; PLLDATI6: in std_logic;
76 | PLLDATI5: in std_logic; PLLDATI4: in std_logic;
77 | PLLDATI3: in std_logic; PLLDATI2: in std_logic;
78 | PLLDATI1: in std_logic; PLLDATI0: in std_logic;
79 | CLKOP: out std_logic; CLKOS: out std_logic;
80 | CLKOS2: out std_logic; CLKOS3: out std_logic;
81 | LOCK: out std_logic; INTLOCK: out std_logic;
82 | REFCLK: out std_logic; CLKINTFB: out std_logic;
83 | DPHSRC: out std_logic; PLLACK: out std_logic;
84 | PLLDATO7: out std_logic; PLLDATO6: out std_logic;
85 | PLLDATO5: out std_logic; PLLDATO4: out std_logic;
86 | PLLDATO3: out std_logic; PLLDATO2: out std_logic;
87 | PLLDATO1: out std_logic; PLLDATO0: out std_logic);
88 | end component;
89 | attribute FREQUENCY_PIN_CLKOS : string;
90 | attribute FREQUENCY_PIN_CLKOP : string;
91 | attribute FREQUENCY_PIN_CLKI : string;
92 | attribute ICP_CURRENT : string;
93 | attribute LPF_RESISTOR : string;
94 | attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "57.291667";
95 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "12.500000";
96 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000";
97 | attribute ICP_CURRENT of PLLInst_0 : label is "10";
98 | attribute LPF_RESISTOR of PLLInst_0 : label is "8";
99 | attribute syn_keep : boolean;
100 | attribute NGD_DRC_MASK : integer;
101 | attribute NGD_DRC_MASK of Structure : architecture is 1;
102 |
103 | begin
104 | -- component instantiation statements
105 | scuba_vlo_inst: VLO
106 | port map (Z=>scuba_vlo);
107 |
108 | PLLInst_0: EHXPLLJ
109 | generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
110 | MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
111 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
112 | PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
113 | CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
114 | CLKOS_CPHASE=> 11, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 54,
115 | PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
116 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
117 | FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
118 | PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
119 | OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
120 | CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
121 | PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED",
122 | OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
123 | CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
124 | CLKOS_DIV=> 12, CLKOP_DIV=> 55, CLKFB_DIV=> 1, CLKI_DIV=> 2,
125 | FEEDBK_PATH=> "CLKOP")
126 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
127 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
128 | PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
129 | PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
130 | RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
131 | ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
132 | PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
133 | PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
134 | PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
135 | PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
136 | PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
137 | PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
138 | PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
139 | PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
140 | CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
141 | REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
142 | PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
143 | PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
144 | PLLDATO1=>open, PLLDATO0=>open);
145 |
146 | CLKOS <= CLKOS_t;
147 | CLKOP <= CLKOP_t;
148 | end Structure;
149 |
150 | -- synopsys translate_off
151 | library MACHXO2;
152 | configuration Structure_CON of PLL_57 is
153 | for Structure
154 | for all:VLO use entity MACHXO2.VLO(V); end for;
155 | for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
156 | end for;
157 | end Structure_CON;
158 |
159 | -- synopsys translate_on
160 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
6 | Tue Nov 19 23:41:16 2024
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_57 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 12 -phase_cntl STATIC -fb_mode 1
17 | Circuit name : PLL_57
18 | Module type : pll
19 | Module Version : 5.7
20 | Ports :
21 | Inputs : CLKI
22 | Outputs : CLKOP, CLKOS
23 | I/O buffer : not inserted
24 | EDIF output : PLL_57.edn
25 | VHDL output : PLL_57.vhd
26 | VHDL template : PLL_57_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : PLL_57.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: PLL_57.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/cabletester/diamond/PLL_57_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | -- Module Version: 5.7
3 | -- Tue Nov 19 23:41:16 2024
4 |
5 | -- parameterized module component declaration
6 | component PLL_57
7 | port (CLKI: in std_logic; CLKOP: out std_logic;
8 | CLKOS: out std_logic);
9 | end component;
10 |
11 | -- parameterized module component instance
12 | __ : PLL_57
13 | port map (CLKI=>__, CLKOP=>__, CLKOS=>__);
14 |
--------------------------------------------------------------------------------
/cabletester/diamond/generate_core.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | proc GetCmdLine {lpcfile} {
48 | global Para
49 |
50 | if [catch {open $lpcfile r} fileid] {
51 | puts "Cannot open $para_file file!"
52 | exit -1
53 | }
54 |
55 | seek $fileid 0 start
56 | set default_match 0
57 | while {[gets $fileid line] >= 0} {
58 | if {[string first "\[Command\]" $line] == 0} {
59 | set default_match 1
60 | continue
61 | }
62 | if {[string first "\[" $line] == 0} {
63 | set default_match 0
64 | }
65 | if {$default_match == 1} {
66 | if [regexp {([^=]*)=(.*)} $line match parameter value] {
67 | if [regexp {([ |\t]*;)} $parameter match] {continue}
68 | if [regexp {(.*)[ |\t]*;} $value match temp] {
69 | set Para($parameter) $temp
70 | } else {
71 | set Para($parameter) $value
72 | }
73 | }
74 | }
75 | }
76 | set default_match 0
77 | close $fileid
78 |
79 | return $Para(cmd_line)
80 | }
81 |
82 | set platformpath [GetPlatform]
83 | set Para(sbp_path) [file dirname [info script]]
84 | set Para(install_dir) $env(TOOLRTF)
85 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
86 |
87 | set scuba "$Para(FPGAPath)/scuba"
88 | set modulename "PLL_57"
89 | set lang "vhdl"
90 | set lpcfile "$Para(sbp_path)/$modulename.lpc"
91 | set arch "xo2c00"
92 | set cmd_line [GetCmdLine $lpcfile]
93 | set fdcfile "$Para(sbp_path)/$modulename.fdc"
94 | if {[file exists $fdcfile] == 0} {
95 | append scuba " " $cmd_line
96 | } else {
97 | append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
98 | }
99 | set Para(result) [catch {eval exec "$scuba"} msg]
100 | #puts $msg
101 |
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/cabletester/diamond/generate_ngd.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | set platformpath [GetPlatform]
48 | set Para(sbp_path) [file dirname [info script]]
49 | set Para(install_dir) $env(TOOLRTF)
50 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
51 | set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
52 |
53 | set Para(ModuleName) "PLL_57"
54 | set Para(Module) "PLL"
55 | set Para(libname) machxo2
56 | set Para(arch_name) xo2c00
57 | set Para(PartType) "LCMXO2-1200HC"
58 |
59 | set Para(tech_syn) machxo2
60 | set Para(tech_cae) machxo2
61 | set Para(Package) "QFN32"
62 | set Para(SpeedGrade) "4"
63 | set Para(FMax) "100"
64 | set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
65 |
66 | #create response file(*.cmd) for Synpwrap
67 | proc CreateCmdFile {} {
68 | global Para
69 |
70 | file mkdir "$Para(sbp_path)/syn_results"
71 | if [catch {open $Para(ModuleName).cmd w} rspFile] {
72 | puts "Cannot create response file $Para(ModuleName).cmd."
73 | exit -1
74 | } else {
75 | puts $rspFile "PROJECT: $Para(ModuleName)
76 | working_path: \"$Para(sbp_path)/syn_results\"
77 | module: $Para(ModuleName)
78 | verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\"
79 | vlog_std_v2001: true
80 | constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
81 | suffix_name: edn
82 | output_file_name: $Para(ModuleName)
83 | write_prf: true
84 | disable_io_insertion: true
85 | force_gsr: false
86 | frequency: $Para(FMax)
87 | fanout_limit: 50
88 | retiming: false
89 | pipe: false
90 | part: $Para(PartType)
91 | speed_grade: $Para(SpeedGrade)
92 | "
93 | close $rspFile
94 | }
95 | }
96 |
97 | #synpwrap
98 | CreateCmdFile
99 | set synpwrap "$Para(bin_dir)/synpwrap"
100 | if {[file exists $fdcfile] == 0} {
101 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
102 | } else {
103 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
104 | }
105 | #puts $msg
106 |
107 | #edif2ngd
108 | set edif2ngd "$Para(FPGAPath)/edif2ngd"
109 | set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
110 | #puts $msg
111 |
112 | #ngdbuild
113 | set ngdbuild "$Para(FPGAPath)/ngdbuild"
114 | set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
115 | #puts $msg
116 |
--------------------------------------------------------------------------------
/cabletester/diamond/msg_file.log:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Tue Nov 19 23:41:16 2024
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | BEGIN SCUBA Module Synthesis
11 |
12 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_57 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 12 -phase_cntl STATIC -fb_mode 1
13 | Circuit name : PLL_57
14 | Module type : pll
15 | Module Version : 5.7
16 | Ports :
17 | Inputs : CLKI
18 | Outputs : CLKOP, CLKOS
19 | I/O buffer : not inserted
20 | EDIF output : PLL_57.edn
21 | VHDL output : PLL_57.vhd
22 | VHDL template : PLL_57_tmpl.vhd
23 | VHDL purpose : for synthesis and simulation
24 | Bus notation : big endian
25 | Report output : PLL_57.srp
26 | Estimated Resource Usage:
27 |
28 | END SCUBA Module Synthesis
29 |
30 |
--------------------------------------------------------------------------------
/cabletester/diamond/promote.xml:
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1 |
2 |
3 |
4 |
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/cabletester/diamond/reportview.xml:
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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/cabletester/diamond/source/EGA.vhd:
--------------------------------------------------------------------------------
1 | library ieee;
2 | library machxo2;
3 | use ieee.numeric_std.all;
4 | use ieee.std_logic_1164.all;
5 | use machxo2.all;
6 |
7 | entity EGA is
8 | port (
9 | CLK25 : in std_logic;
10 | D : out std_logic_vector(7 downto 0);
11 | CP : out std_logic_vector(3 downto 0)
12 | );
13 | end entity;
14 |
15 |
16 | architecture immediate of EGA is
17 |
18 | component PLL_57 is
19 | port (
20 | CLKI: in std_logic;
21 | CLKOP: out std_logic;
22 | CLKOS: out std_logic);
23 | end component;
24 |
25 | signal CLK57: std_logic;
26 |
27 |
28 | begin
29 | pll : PLL_57 PORT MAP ( CLKI => CLK25, CLKOP => open, CLKOS => CLK57 );
30 |
31 | process (CLK57)
32 | type letter is array(0 to 9) of std_logic_vector(7 downto 0);
33 | constant letter_R:letter := (
34 | "00000000",
35 | "11111100",
36 | "11000110",
37 | "11000110",
38 | "11111100",
39 | "11001100",
40 | "11000110",
41 | "11000011",
42 | "00000000",
43 | "00000000"
44 | );
45 | constant letter_G:letter := (
46 | "00000000",
47 | "00111100",
48 | "01100110",
49 | "11000000",
50 | "11001111",
51 | "11000011",
52 | "01111110",
53 | "00000000",
54 | "00000000",
55 | "00000000"
56 | );
57 | constant letter_B:letter := (
58 | "00000000",
59 | "11111100",
60 | "11000011",
61 | "11000011",
62 | "11111100",
63 | "11000011",
64 | "11000011",
65 | "11111100",
66 | "00000000",
67 | "00000000"
68 | );
69 |
70 | variable phase:integer range 0 to 3;
71 | variable x:integer range 0 to 1023;
72 | variable y:integer range 0 to 511;
73 | variable top:integer := 38;
74 | variable left:integer := 230;
75 | variable R:std_logic_vector(3 downto 0);
76 | variable G:std_logic_vector(3 downto 0);
77 | variable B:std_logic_vector(3 downto 0);
78 | variable HS:std_logic;
79 | variable VS:std_logic;
80 | variable CS:std_logic;
81 | begin
82 | if rising_edge(CLK57) then
83 | R := "0000";
84 | G := "0000";
85 | B := "0000";
86 | HS := '0';
87 | VS := '0';
88 | CS := '1';
89 | if y<3 then
90 | VS := '1';
91 | end if;
92 | if x<67 then
93 | HS := '1';
94 | end if;
95 | if x<67 or (y<3 and x<912-67) then
96 | CS := '0';
97 | end if;
98 | if ((y=top or y=top+200-1) and x>=left and x=top and y=left+40 and x=top+20 and y=left+40 and x=top+160 and y=top+144 and letter_R(y-(top+160))(7-(x-(left+40))/2)='1' then
112 | R := "1111";
113 | end if;
114 | elsif x>=left+40 and x=top+170 and y=top+144 and letter_G(y-(top+170))(7-(x-(left+40))/2)='1' then
117 | G := "1111";
118 | end if;
119 | elsif x>=left+40 and x=top+180 and y=top+144 and letter_B(y-(top+180))(7-(x-(left+40))/2)='1' then
122 | B := "1111";
123 | end if;
124 | end if;
125 |
126 | if phase=0 or phase=1 then
127 | D <= B(3) & G(3) & R(3) & R(2) & R(1) & B(0) & G(0) & (not HS);
128 | elsif phase=2 then
129 | D <= VS & HS & B(2) & G(2) & B(1) & G(1) & R(0) & CS;
130 | else
131 | D <= (not VS) & CS & B(3) & B(2) & G(3) & G(2) & R(3) & R(2);
132 | end if;
133 |
134 | if phase<3 then
135 | phase:=phase+1;
136 | else
137 | phase:=0;
138 | if x<912-1 then
139 | x:=x+1;
140 | else
141 | x:=0;
142 | if y<262-1 then
143 | y:=y+1;
144 | else
145 | y:=0;
146 | end if;
147 | end if;
148 | end if;
149 | end if;
150 |
151 | if falling_edge(CLK57) then
152 | if phase=2 then
153 | CP <= "0011";
154 | elsif phase=3 then
155 | CP <= "0100";
156 | elsif phase=0 then
157 | CP <= "1000";
158 | else
159 | CP <= "0000";
160 | end if;
161 | end if;
162 | end process;
163 |
164 | end immediate;
165 |
--------------------------------------------------------------------------------
/cabletester/pinouts.txt:
--------------------------------------------------------------------------------
1 | Digital ports on cable tester
2 |
3 | Spectrum128 EGA Pin header
4 | (8way DIN) (DB9) (16 pin)
5 | -VS (1) CP3.D7 32
6 | -HS (5) CP0/1.D0 12/2
7 | CS 4 CP2.D0 29
8 | G0 1 CP0/1.D1 13/3
9 | R0 2 CP2.D1 28
10 | B0 3 CP0/1.D2 14/4
11 | G1 4 CP2.D2 27
12 | R1 5 CP0/1.D3 15/5
13 | B1 6 CP2.D3 26
14 | GND 2 1 7 any GND
15 | G2/I 3 6 8 CP2.D4 25
16 | R2 2 9 CP0/1.D4 16/6
17 | B2 7 10 CP2.D5 24
18 | R3 7 3 11 CP0/1.D5 17/7
19 | HS 8 12 CP2.D6 23
20 | G3 6 4 13 CP0/1.D6 18/8
21 | VS 9 14 CP2.D7 22
22 | B3 8 5 15 CP0/1.D7 19/9
23 | 16
24 |
25 |
26 | Analog port on cable tester
27 |
28 | CPC, BBC Micro
29 | (6way DIN)
30 | R 1 CP3.D0 (2k) 39
31 | + CP3.D1 (1k) 38
32 | G 2 CP3.D2 (2k) 37
33 | + CP3.D3 (1k) 36
34 | B 3 CP3.D4 (2k) 35
35 | + CP3.D5 (1k) 34
36 | CS 4 CP3.D6 33
37 | GND 5 GND 31
38 |
39 |
40 |
--------------------------------------------------------------------------------
/misc/lumacode_logo.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/misc/lumacode_logo.png
--------------------------------------------------------------------------------
/misc/lumacode_logo_blackwhite.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/misc/lumacode_logo_blackwhite.png
--------------------------------------------------------------------------------
/misc/productplan.txt:
--------------------------------------------------------------------------------
1 |
2 | RGBtoHDMI devices
3 | - Mono & Lumacode (RCA cable)
4 | - Pro (16 pin, 6 pin, 3.5mm audio) with case
5 | - Case für small RGBtoHDMI
6 |
7 | Lumacode sources
8 | - GTIAdigitizer
9 | - PPUdigitizer
10 | - STICdigitizer
11 | - TEDdigitizer
12 | - TIAdigitizer
13 | - TMSdigitizer
14 | - ULAdigitizer
15 | - VDPdigitizer
16 | - VIC20digitizer
17 | - VICIIdizer
18 | - VICIIdizer128
19 |
20 | Adapters
21 | - C128 VDC mono to RCA socket
22 |
23 | Digital cables (to 16-pin connector)
24 | - BBC micro (6 way DIN)
25 | - Spectrum 128/+2, Sinclair QL (8 way DIN)
26 | - EGA (DB9)
27 | - Atari ST monochrome
28 | - Amiga with digital hack (DB23)
29 |
30 | Analog cables (to 6-pin connector)
31 | - Lumacode and Mono (RCA)
32 | - Amstrad CPC, BBC micro (6 way DIN)
33 | - Spectrum +2A/3, Sinclair QL (8 way DIN)
34 |
35 |
36 | Modding:
37 | For some Apple II - machines, the user can add an 8-pin DIN port
38 | that is compatible with the cables for the Spectrum 128/+2
39 |
--------------------------------------------------------------------------------
/signalgenerator/README.md:
--------------------------------------------------------------------------------
1 | # Signal generator
2 |
3 | A small device intended to generate various LumaCode signal standards.
4 |
5 | 
6 |
--------------------------------------------------------------------------------
/signalgenerator/board/Library.bak:
--------------------------------------------------------------------------------
1 | (kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
2 | (symbol "74LVC04" (in_bom yes) (on_board yes)
3 | (property "Reference" "U" (id 0) (at 6.35 0 0)
4 | (effects (font (size 1.27 1.27)))
5 | )
6 | (property "Value" "74LVC04" (id 1) (at 0 0 0)
7 | (effects (font (size 1.27 1.27)))
8 | )
9 | (property "Footprint" "" (id 2) (at 0 0 0)
10 | (effects (font (size 1.27 1.27)) hide)
11 | )
12 | (property "Datasheet" "" (id 3) (at 0 0 0)
13 | (effects (font (size 1.27 1.27)) hide)
14 | )
15 | (symbol "74LVC04_0_1"
16 | (rectangle (start -8.89 5.08) (end 8.89 -5.08)
17 | (stroke (width 0) (type default) (color 0 0 0 0))
18 | (fill (type none))
19 | )
20 | )
21 | (symbol "74LVC04_1_1"
22 | (pin input line (at -7.62 -7.62 90) (length 2.54)
23 | (name "I1" (effects (font (size 1.27 1.27))))
24 | (number "1" (effects (font (size 1.27 1.27))))
25 | )
26 | (pin output line (at 2.54 7.62 270) (length 2.54)
27 | (name "O5" (effects (font (size 1.27 1.27))))
28 | (number "10" (effects (font (size 1.27 1.27))))
29 | )
30 | (pin input line (at 0 7.62 270) (length 2.54)
31 | (name "I5" (effects (font (size 1.27 1.27))))
32 | (number "11" (effects (font (size 1.27 1.27))))
33 | )
34 | (pin output line (at -2.54 7.62 270) (length 2.54)
35 | (name "O4" (effects (font (size 1.27 1.27))))
36 | (number "12" (effects (font (size 1.27 1.27))))
37 | )
38 | (pin input line (at -5.08 7.62 270) (length 2.54)
39 | (name "I4" (effects (font (size 1.27 1.27))))
40 | (number "13" (effects (font (size 1.27 1.27))))
41 | )
42 | (pin power_in line (at -7.62 7.62 270) (length 2.54)
43 | (name "VCC" (effects (font (size 1.27 1.27))))
44 | (number "14" (effects (font (size 1.27 1.27))))
45 | )
46 | (pin output line (at -5.08 -7.62 90) (length 2.54)
47 | (name "O1" (effects (font (size 1.27 1.27))))
48 | (number "2" (effects (font (size 1.27 1.27))))
49 | )
50 | (pin input line (at -2.54 -7.62 90) (length 2.54)
51 | (name "I2" (effects (font (size 1.27 1.27))))
52 | (number "3" (effects (font (size 1.27 1.27))))
53 | )
54 | (pin output line (at 0 -7.62 90) (length 2.54)
55 | (name "O2" (effects (font (size 1.27 1.27))))
56 | (number "4" (effects (font (size 1.27 1.27))))
57 | )
58 | (pin input line (at 2.54 -7.62 90) (length 2.54)
59 | (name "I3" (effects (font (size 1.27 1.27))))
60 | (number "5" (effects (font (size 1.27 1.27))))
61 | )
62 | (pin output line (at 5.08 -7.62 90) (length 2.54)
63 | (name "O3" (effects (font (size 1.27 1.27))))
64 | (number "6" (effects (font (size 1.27 1.27))))
65 | )
66 | (pin power_in line (at 7.62 -7.62 90) (length 2.54)
67 | (name "GND" (effects (font (size 1.27 1.27))))
68 | (number "7" (effects (font (size 1.27 1.27))))
69 | )
70 | (pin output line (at 7.62 7.62 270) (length 2.54)
71 | (name "O6" (effects (font (size 1.27 1.27))))
72 | (number "8" (effects (font (size 1.27 1.27))))
73 | )
74 | (pin input line (at 5.08 7.62 270) (length 2.54)
75 | (name "I6" (effects (font (size 1.27 1.27))))
76 | (number "9" (effects (font (size 1.27 1.27))))
77 | )
78 | )
79 | )
80 | (symbol "XO2-DIP20" (in_bom yes) (on_board yes)
81 | (property "Reference" "U" (id 0) (at 0 -2.54 0)
82 | (effects (font (size 1.27 1.27)))
83 | )
84 | (property "Value" "XO2-DIP20" (id 1) (at 0 0 0)
85 | (effects (font (size 1.27 1.27)))
86 | )
87 | (property "Footprint" "" (id 2) (at 0 0 0)
88 | (effects (font (size 1.27 1.27)) hide)
89 | )
90 | (property "Datasheet" "" (id 3) (at 0 0 0)
91 | (effects (font (size 1.27 1.27)) hide)
92 | )
93 | (symbol "XO2-DIP20_0_1"
94 | (rectangle (start -7.62 -5.08) (end 7.62 -33.02)
95 | (stroke (width 0) (type default) (color 0 0 0 0))
96 | (fill (type none))
97 | )
98 | )
99 | (symbol "XO2-DIP20_1_1"
100 | (pin power_in line (at -10.16 -7.62 0) (length 2.54)
101 | (name "GND" (effects (font (size 1.27 1.27))))
102 | (number "1" (effects (font (size 1.27 1.27))))
103 | )
104 | (pin bidirectional line (at -10.16 -30.48 0) (length 2.54)
105 | (name "" (effects (font (size 1.27 1.27))))
106 | (number "10" (effects (font (size 1.27 1.27))))
107 | )
108 | (pin bidirectional line (at 10.16 -30.48 180) (length 2.54)
109 | (name "" (effects (font (size 1.27 1.27))))
110 | (number "11" (effects (font (size 1.27 1.27))))
111 | )
112 | (pin bidirectional line (at 10.16 -27.94 180) (length 2.54)
113 | (name "" (effects (font (size 1.27 1.27))))
114 | (number "12" (effects (font (size 1.27 1.27))))
115 | )
116 | (pin bidirectional line (at 10.16 -25.4 180) (length 2.54)
117 | (name "" (effects (font (size 1.27 1.27))))
118 | (number "13" (effects (font (size 1.27 1.27))))
119 | )
120 | (pin bidirectional line (at 10.16 -22.86 180) (length 2.54)
121 | (name "" (effects (font (size 1.27 1.27))))
122 | (number "14" (effects (font (size 1.27 1.27))))
123 | )
124 | (pin bidirectional line (at 10.16 -20.32 180) (length 2.54)
125 | (name "" (effects (font (size 1.27 1.27))))
126 | (number "15" (effects (font (size 1.27 1.27))))
127 | )
128 | (pin bidirectional line (at 10.16 -17.78 180) (length 2.54)
129 | (name "" (effects (font (size 1.27 1.27))))
130 | (number "16" (effects (font (size 1.27 1.27))))
131 | )
132 | (pin bidirectional line (at 10.16 -15.24 180) (length 2.54)
133 | (name "" (effects (font (size 1.27 1.27))))
134 | (number "17" (effects (font (size 1.27 1.27))))
135 | )
136 | (pin bidirectional line (at 10.16 -12.7 180) (length 2.54)
137 | (name "" (effects (font (size 1.27 1.27))))
138 | (number "18" (effects (font (size 1.27 1.27))))
139 | )
140 | (pin bidirectional line (at 10.16 -10.16 180) (length 2.54)
141 | (name "" (effects (font (size 1.27 1.27))))
142 | (number "19" (effects (font (size 1.27 1.27))))
143 | )
144 | (pin bidirectional line (at -10.16 -10.16 0) (length 2.54)
145 | (name "" (effects (font (size 1.27 1.27))))
146 | (number "2" (effects (font (size 1.27 1.27))))
147 | )
148 | (pin power_in line (at 10.16 -7.62 180) (length 2.54)
149 | (name "VCC" (effects (font (size 1.27 1.27))))
150 | (number "20" (effects (font (size 1.27 1.27))))
151 | )
152 | (pin bidirectional line (at -10.16 -12.7 0) (length 2.54)
153 | (name "" (effects (font (size 1.27 1.27))))
154 | (number "3" (effects (font (size 1.27 1.27))))
155 | )
156 | (pin bidirectional line (at -10.16 -15.24 0) (length 2.54)
157 | (name "" (effects (font (size 1.27 1.27))))
158 | (number "4" (effects (font (size 1.27 1.27))))
159 | )
160 | (pin bidirectional line (at -10.16 -17.78 0) (length 2.54)
161 | (name "" (effects (font (size 1.27 1.27))))
162 | (number "5" (effects (font (size 1.27 1.27))))
163 | )
164 | (pin bidirectional line (at -10.16 -20.32 0) (length 2.54)
165 | (name "" (effects (font (size 1.27 1.27))))
166 | (number "6" (effects (font (size 1.27 1.27))))
167 | )
168 | (pin bidirectional line (at -10.16 -22.86 0) (length 2.54)
169 | (name "" (effects (font (size 1.27 1.27))))
170 | (number "7" (effects (font (size 1.27 1.27))))
171 | )
172 | (pin bidirectional line (at -10.16 -25.4 0) (length 2.54)
173 | (name "" (effects (font (size 1.27 1.27))))
174 | (number "8" (effects (font (size 1.27 1.27))))
175 | )
176 | (pin bidirectional line (at -10.16 -27.94 0) (length 2.54)
177 | (name "" (effects (font (size 1.27 1.27))))
178 | (number "9" (effects (font (size 1.27 1.27))))
179 | )
180 | )
181 | )
182 | )
183 |
--------------------------------------------------------------------------------
/signalgenerator/board/Library.kicad_sym:
--------------------------------------------------------------------------------
1 | (kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
2 | (symbol "74LVC04" (in_bom yes) (on_board yes)
3 | (property "Reference" "U" (id 0) (at 6.35 0 0)
4 | (effects (font (size 1.27 1.27)))
5 | )
6 | (property "Value" "74LVC04" (id 1) (at 0 0 0)
7 | (effects (font (size 1.27 1.27)))
8 | )
9 | (property "Footprint" "" (id 2) (at 0 0 0)
10 | (effects (font (size 1.27 1.27)) hide)
11 | )
12 | (property "Datasheet" "" (id 3) (at 0 0 0)
13 | (effects (font (size 1.27 1.27)) hide)
14 | )
15 | (symbol "74LVC04_0_1"
16 | (rectangle (start -8.89 5.08) (end 8.89 -5.08)
17 | (stroke (width 0) (type default) (color 0 0 0 0))
18 | (fill (type none))
19 | )
20 | )
21 | (symbol "74LVC04_1_1"
22 | (pin input line (at -7.62 -7.62 90) (length 2.54)
23 | (name "I1" (effects (font (size 1.27 1.27))))
24 | (number "1" (effects (font (size 1.27 1.27))))
25 | )
26 | (pin output line (at 2.54 7.62 270) (length 2.54)
27 | (name "O5" (effects (font (size 1.27 1.27))))
28 | (number "10" (effects (font (size 1.27 1.27))))
29 | )
30 | (pin input line (at 0 7.62 270) (length 2.54)
31 | (name "I5" (effects (font (size 1.27 1.27))))
32 | (number "11" (effects (font (size 1.27 1.27))))
33 | )
34 | (pin output line (at -2.54 7.62 270) (length 2.54)
35 | (name "O4" (effects (font (size 1.27 1.27))))
36 | (number "12" (effects (font (size 1.27 1.27))))
37 | )
38 | (pin input line (at -5.08 7.62 270) (length 2.54)
39 | (name "I4" (effects (font (size 1.27 1.27))))
40 | (number "13" (effects (font (size 1.27 1.27))))
41 | )
42 | (pin power_in line (at -7.62 7.62 270) (length 2.54)
43 | (name "VCC" (effects (font (size 1.27 1.27))))
44 | (number "14" (effects (font (size 1.27 1.27))))
45 | )
46 | (pin output line (at -5.08 -7.62 90) (length 2.54)
47 | (name "O1" (effects (font (size 1.27 1.27))))
48 | (number "2" (effects (font (size 1.27 1.27))))
49 | )
50 | (pin input line (at -2.54 -7.62 90) (length 2.54)
51 | (name "I2" (effects (font (size 1.27 1.27))))
52 | (number "3" (effects (font (size 1.27 1.27))))
53 | )
54 | (pin output line (at 0 -7.62 90) (length 2.54)
55 | (name "O2" (effects (font (size 1.27 1.27))))
56 | (number "4" (effects (font (size 1.27 1.27))))
57 | )
58 | (pin input line (at 2.54 -7.62 90) (length 2.54)
59 | (name "I3" (effects (font (size 1.27 1.27))))
60 | (number "5" (effects (font (size 1.27 1.27))))
61 | )
62 | (pin output line (at 5.08 -7.62 90) (length 2.54)
63 | (name "O3" (effects (font (size 1.27 1.27))))
64 | (number "6" (effects (font (size 1.27 1.27))))
65 | )
66 | (pin power_in line (at 7.62 -7.62 90) (length 2.54)
67 | (name "GND" (effects (font (size 1.27 1.27))))
68 | (number "7" (effects (font (size 1.27 1.27))))
69 | )
70 | (pin output line (at 7.62 7.62 270) (length 2.54)
71 | (name "O6" (effects (font (size 1.27 1.27))))
72 | (number "8" (effects (font (size 1.27 1.27))))
73 | )
74 | (pin input line (at 5.08 7.62 270) (length 2.54)
75 | (name "I6" (effects (font (size 1.27 1.27))))
76 | (number "9" (effects (font (size 1.27 1.27))))
77 | )
78 | )
79 | )
80 | (symbol "XO2-DIP20" (in_bom yes) (on_board yes)
81 | (property "Reference" "U" (id 0) (at 0 -2.54 0)
82 | (effects (font (size 1.27 1.27)))
83 | )
84 | (property "Value" "XO2-DIP20" (id 1) (at 0 0 0)
85 | (effects (font (size 1.27 1.27)))
86 | )
87 | (property "Footprint" "" (id 2) (at 0 0 0)
88 | (effects (font (size 1.27 1.27)) hide)
89 | )
90 | (property "Datasheet" "" (id 3) (at 0 0 0)
91 | (effects (font (size 1.27 1.27)) hide)
92 | )
93 | (symbol "XO2-DIP20_0_1"
94 | (rectangle (start -7.62 -5.08) (end 7.62 -33.02)
95 | (stroke (width 0) (type default) (color 0 0 0 0))
96 | (fill (type none))
97 | )
98 | )
99 | (symbol "XO2-DIP20_1_1"
100 | (pin power_in line (at -10.16 -7.62 0) (length 2.54)
101 | (name "GND" (effects (font (size 1.27 1.27))))
102 | (number "1" (effects (font (size 1.27 1.27))))
103 | )
104 | (pin bidirectional line (at -10.16 -30.48 0) (length 2.54)
105 | (name "PIN14" (effects (font (size 1.27 1.27))))
106 | (number "10" (effects (font (size 1.27 1.27))))
107 | )
108 | (pin bidirectional line (at 10.16 -30.48 180) (length 2.54)
109 | (name "PIN16" (effects (font (size 1.27 1.27))))
110 | (number "11" (effects (font (size 1.27 1.27))))
111 | )
112 | (pin bidirectional line (at 10.16 -27.94 180) (length 2.54)
113 | (name "PIN17" (effects (font (size 1.27 1.27))))
114 | (number "12" (effects (font (size 1.27 1.27))))
115 | )
116 | (pin bidirectional line (at 10.16 -25.4 180) (length 2.54)
117 | (name "PIN20" (effects (font (size 1.27 1.27))))
118 | (number "13" (effects (font (size 1.27 1.27))))
119 | )
120 | (pin bidirectional line (at 10.16 -22.86 180) (length 2.54)
121 | (name "PIN21" (effects (font (size 1.27 1.27))))
122 | (number "14" (effects (font (size 1.27 1.27))))
123 | )
124 | (pin bidirectional line (at 10.16 -20.32 180) (length 2.54)
125 | (name "PIN23" (effects (font (size 1.27 1.27))))
126 | (number "15" (effects (font (size 1.27 1.27))))
127 | )
128 | (pin bidirectional line (at 10.16 -17.78 180) (length 2.54)
129 | (name "PIN25" (effects (font (size 1.27 1.27))))
130 | (number "16" (effects (font (size 1.27 1.27))))
131 | )
132 | (pin bidirectional line (at 10.16 -15.24 180) (length 2.54)
133 | (name "PIN26" (effects (font (size 1.27 1.27))))
134 | (number "17" (effects (font (size 1.27 1.27))))
135 | )
136 | (pin bidirectional line (at 10.16 -12.7 180) (length 2.54)
137 | (name "PIN27" (effects (font (size 1.27 1.27))))
138 | (number "18" (effects (font (size 1.27 1.27))))
139 | )
140 | (pin bidirectional line (at 10.16 -10.16 180) (length 2.54)
141 | (name "PIN28" (effects (font (size 1.27 1.27))))
142 | (number "19" (effects (font (size 1.27 1.27))))
143 | )
144 | (pin bidirectional line (at -10.16 -10.16 0) (length 2.54)
145 | (name "PIN4" (effects (font (size 1.27 1.27))))
146 | (number "2" (effects (font (size 1.27 1.27))))
147 | )
148 | (pin power_in line (at 10.16 -7.62 180) (length 2.54)
149 | (name "VCC" (effects (font (size 1.27 1.27))))
150 | (number "20" (effects (font (size 1.27 1.27))))
151 | )
152 | (pin bidirectional line (at -10.16 -12.7 0) (length 2.54)
153 | (name "PIN5" (effects (font (size 1.27 1.27))))
154 | (number "3" (effects (font (size 1.27 1.27))))
155 | )
156 | (pin bidirectional line (at -10.16 -15.24 0) (length 2.54)
157 | (name "PIN8" (effects (font (size 1.27 1.27))))
158 | (number "4" (effects (font (size 1.27 1.27))))
159 | )
160 | (pin bidirectional line (at -10.16 -17.78 0) (length 2.54)
161 | (name "PIN9" (effects (font (size 1.27 1.27))))
162 | (number "5" (effects (font (size 1.27 1.27))))
163 | )
164 | (pin bidirectional line (at -10.16 -20.32 0) (length 2.54)
165 | (name "PIN10" (effects (font (size 1.27 1.27))))
166 | (number "6" (effects (font (size 1.27 1.27))))
167 | )
168 | (pin bidirectional line (at -10.16 -22.86 0) (length 2.54)
169 | (name "PIN11" (effects (font (size 1.27 1.27))))
170 | (number "7" (effects (font (size 1.27 1.27))))
171 | )
172 | (pin bidirectional line (at -10.16 -25.4 0) (length 2.54)
173 | (name "PIN12" (effects (font (size 1.27 1.27))))
174 | (number "8" (effects (font (size 1.27 1.27))))
175 | )
176 | (pin bidirectional line (at -10.16 -27.94 0) (length 2.54)
177 | (name "PIN13" (effects (font (size 1.27 1.27))))
178 | (number "9" (effects (font (size 1.27 1.27))))
179 | )
180 | )
181 | )
182 | )
183 |
--------------------------------------------------------------------------------
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/signalgenerator/board/board.kicad_prl:
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1 | {
2 | "board": {
3 | "active_layer": 0,
4 | "active_layer_preset": "",
5 | "auto_track_width": true,
6 | "hidden_netclasses": [],
7 | "hidden_nets": [],
8 | "high_contrast_mode": 0,
9 | "net_color_mode": 1,
10 | "opacity": {
11 | "images": 0.6,
12 | "pads": 1.0,
13 | "tracks": 1.0,
14 | "vias": 1.0,
15 | "zones": 0.6
16 | },
17 | "ratsnest_display_mode": 0,
18 | "selection_filter": {
19 | "dimensions": true,
20 | "footprints": true,
21 | "graphics": true,
22 | "keepouts": true,
23 | "lockedItems": true,
24 | "otherItems": true,
25 | "pads": true,
26 | "text": true,
27 | "tracks": true,
28 | "vias": true,
29 | "zones": true
30 | },
31 | "visible_items": [
32 | 0,
33 | 1,
34 | 2,
35 | 3,
36 | 4,
37 | 5,
38 | 6,
39 | 7,
40 | 8,
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43 | 11,
44 | 12,
45 | 13,
46 | 14,
47 | 15,
48 | 18,
49 | 19,
50 | 20,
51 | 21,
52 | 22,
53 | 23,
54 | 24,
55 | 25,
56 | 26,
57 | 27,
58 | 28,
59 | 29,
60 | 30,
61 | 32,
62 | 33,
63 | 34,
64 | 35,
65 | 36
66 | ],
67 | "visible_layers": "fffffff_fffffffe",
68 | "zone_display_mode": 0
69 | },
70 | "git": {
71 | "repo_password": "",
72 | "repo_type": "",
73 | "repo_username": "",
74 | "ssh_key": ""
75 | },
76 | "meta": {
77 | "filename": "board.kicad_prl",
78 | "version": 3
79 | },
80 | "project": {
81 | "files": []
82 | }
83 | }
84 |
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/signalgenerator/board/footprints.pretty/RCA_JACK.kicad_mod:
--------------------------------------------------------------------------------
1 | (footprint "RCA_JACK"
2 | (version 20240108)
3 | (generator "pcbnew")
4 | (generator_version "8.0")
5 | (layer "F.Cu")
6 | (property "Reference" "REF**"
7 | (at -5 2 0)
8 | (layer "F.SilkS")
9 | (uuid "5f3b24f2-0267-4564-9c21-cf3a3b1b7ab9")
10 | (effects
11 | (font
12 | (size 1 1)
13 | (thickness 0.15)
14 | )
15 | )
16 | )
17 | (property "Value" "RCA_JACK"
18 | (at -5 -2 0)
19 | (layer "F.Fab")
20 | (uuid "7d79ae8a-3544-4f93-a220-63c7a445fd2b")
21 | (effects
22 | (font
23 | (size 1 1)
24 | (thickness 0.15)
25 | )
26 | )
27 | )
28 | (property "Footprint" ""
29 | (at 0 0 0)
30 | (unlocked yes)
31 | (layer "F.Fab")
32 | (hide yes)
33 | (uuid "3902c19b-6400-48ee-838a-b84a3f8802d0")
34 | (effects
35 | (font
36 | (size 1.27 1.27)
37 | )
38 | )
39 | )
40 | (property "Datasheet" ""
41 | (at 0 0 0)
42 | (unlocked yes)
43 | (layer "F.Fab")
44 | (hide yes)
45 | (uuid "fe8ca051-ea95-4a46-ac93-2ecc5dbcae94")
46 | (effects
47 | (font
48 | (size 1.27 1.27)
49 | )
50 | )
51 | )
52 | (property "Description" ""
53 | (at 0 0 0)
54 | (unlocked yes)
55 | (layer "F.Fab")
56 | (hide yes)
57 | (uuid "d4bdee77-cd0f-43b5-ab40-c6bf898016c2")
58 | (effects
59 | (font
60 | (size 1.27 1.27)
61 | )
62 | )
63 | )
64 | (attr through_hole)
65 | (fp_line
66 | (start -10 -5)
67 | (end -10 -1)
68 | (stroke
69 | (width 0.1)
70 | (type default)
71 | )
72 | (layer "F.SilkS")
73 | (uuid "77400d39-9ff4-4122-ab84-3061dcaf1737")
74 | )
75 | (fp_line
76 | (start -10 5)
77 | (end -10 1)
78 | (stroke
79 | (width 0.1)
80 | (type default)
81 | )
82 | (layer "F.SilkS")
83 | (uuid "0b85cb9c-8433-49a5-a9c1-cbbe57ef3429")
84 | )
85 | (fp_line
86 | (start -10 5)
87 | (end 0 5)
88 | (stroke
89 | (width 0.15)
90 | (type solid)
91 | )
92 | (layer "F.SilkS")
93 | (uuid "487b57ec-3c56-49b9-93b3-f05679d82e26")
94 | )
95 | (fp_line
96 | (start -1.7 -5.1)
97 | (end -1.7 -3.4)
98 | (stroke
99 | (width 0.1)
100 | (type solid)
101 | )
102 | (layer "F.SilkS")
103 | (uuid "89d72e44-9864-4b8b-b80c-94abe96bf226")
104 | )
105 | (fp_line
106 | (start -1.7 -5)
107 | (end -1.7 -4.1)
108 | (stroke
109 | (width 0.1)
110 | (type solid)
111 | )
112 | (layer "F.SilkS")
113 | (uuid "f77d4632-e272-47a3-bd38-512d116dad03")
114 | )
115 | (fp_line
116 | (start -1.7 -3.4)
117 | (end 0 -3.4)
118 | (stroke
119 | (width 0.1)
120 | (type solid)
121 | )
122 | (layer "F.SilkS")
123 | (uuid "4e3c4a45-1049-403a-a5d9-79289e18cebd")
124 | )
125 | (fp_line
126 | (start -1.7 3.4)
127 | (end 0 3.4)
128 | (stroke
129 | (width 0.1)
130 | (type solid)
131 | )
132 | (layer "F.SilkS")
133 | (uuid "2bee226d-96e4-4eb1-9439-c36757a46fc2")
134 | )
135 | (fp_line
136 | (start -1.7 5.1)
137 | (end -1.7 3.4)
138 | (stroke
139 | (width 0.1)
140 | (type solid)
141 | )
142 | (layer "F.SilkS")
143 | (uuid "92ad6820-98ca-44d0-9834-6fd0e7faa1d5")
144 | )
145 | (fp_line
146 | (start 0 -5.1)
147 | (end -1.7 -5.1)
148 | (stroke
149 | (width 0.1)
150 | (type solid)
151 | )
152 | (layer "F.SilkS")
153 | (uuid "65fce26b-0ec1-4373-a66a-ae2294f94f82")
154 | )
155 | (fp_line
156 | (start 0 -5)
157 | (end -10 -5)
158 | (stroke
159 | (width 0.15)
160 | (type solid)
161 | )
162 | (layer "F.SilkS")
163 | (uuid "ba7611a4-3423-4810-8065-7544fed8c1bb")
164 | )
165 | (fp_line
166 | (start 0 0)
167 | (end 0 -5)
168 | (stroke
169 | (width 0.15)
170 | (type solid)
171 | )
172 | (layer "F.SilkS")
173 | (uuid "d0eb7de3-dced-4031-901c-bb72c43d9540")
174 | )
175 | (fp_line
176 | (start 0 5)
177 | (end 0 0)
178 | (stroke
179 | (width 0.15)
180 | (type solid)
181 | )
182 | (layer "F.SilkS")
183 | (uuid "c9007a37-bd0a-45b5-94c0-42f42846d5af")
184 | )
185 | (fp_line
186 | (start 0 5.1)
187 | (end -1.7 5.1)
188 | (stroke
189 | (width 0.1)
190 | (type solid)
191 | )
192 | (layer "F.SilkS")
193 | (uuid "db824140-b02e-4df7-bde5-42d848aa02dc")
194 | )
195 | (pad "1" thru_hole oval
196 | (at -8.5 0)
197 | (size 2.9 1.6)
198 | (drill oval 2.3 1)
199 | (layers "*.Cu" "*.Mask")
200 | (remove_unused_layers no)
201 | (uuid "33f505c0-188d-4479-b990-245f9a6d5e93")
202 | )
203 | (pad "2" thru_hole oval
204 | (at -4 0)
205 | (size 1.9 4)
206 | (drill oval 1.3 3.4)
207 | (layers "*.Cu" "*.Mask")
208 | (remove_unused_layers no)
209 | (uuid "9d3ca9a6-d3c6-41fd-ada7-25187a3eae31")
210 | )
211 | )
--------------------------------------------------------------------------------
/signalgenerator/board/fp-lib-table:
--------------------------------------------------------------------------------
1 | (fp_lib_table
2 | (version 7)
3 | (lib (name "Projectfootprints")(type "KiCad")(uri "${KIPRJMOD}/footprints.pretty")(options "")(descr ""))
4 | )
5 |
--------------------------------------------------------------------------------
/signalgenerator/board/sym-lib-table:
--------------------------------------------------------------------------------
1 | (sym_lib_table
2 | (lib (name "Library")(type "KiCad")(uri "${KIPRJMOD}/Library.kicad_sym")(options "")(descr ""))
3 | )
4 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/.run_manager.ini:
--------------------------------------------------------------------------------
1 | [Runmanager]
2 | Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xdc\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
3 | windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4 | headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
5 |
6 | [impl1%3CStrategy1%3E]
7 | isChecked=false
8 | isHidden=false
9 | isExpanded=false
10 |
11 | [Lumacode270p%3CArea%3E]
12 | isChecked=false
13 | isHidden=false
14 | isExpanded=false
15 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/.setting.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | PAR.auto_tasks=PARTrace
3 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/.spread_sheet.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | COLUMN_POS_INFO_NAME_-1_0=Prioritize
3 | COLUMN_POS_INFO_NAME_-1_1=PIO Register
4 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/.spreadsheet_view.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | pin_sort_type=0
3 | pin_sort_ascending=true
4 | sig_sort_type=0
5 | sig_sort_ascending=true
6 | active_Sheet=Port Assignments
7 |
8 | [Port%20Assignments]
9 | Name="223,0"
10 | Group%20By="83,1"
11 | Pin="53,2"
12 | BANK="66,3"
13 | BANK_VCC="93,4"
14 | VREF="63,5"
15 | IO_TYPE="94,6"
16 | PULLMODE="94,7"
17 | DRIVE="70,8"
18 | SLEWRATE="93,9"
19 | CLAMP="74,10"
20 | OPENDRAIN="100,11"
21 | DIFFRESISTOR="114,12"
22 | DIFFDRIVE="95,13"
23 | HYSTERESIS="101,14"
24 | Outload%20%28pF%29="101,15"
25 | MaxSkew="86,16"
26 | Clock%20Load%20Only="118,17"
27 | SwitchingID="98,18"
28 | Ground%20plane%20PCB%20noise%20%28mV%29="185,19"
29 | Power%20plane%20PCB%20noise%20%28mV%29="182,20"
30 | SSO%20Allowance%28%25%29="134,21"
31 | sort_columns="IO_TYPE,Ascending"
32 |
33 | [Pin%20Assignments]
34 | Pin="95,0"
35 | Pad%20Name="94,1"
36 | Dual%20Function="205,2"
37 | Polarity="77,3"
38 | BANK="0,4"
39 | BANK_VCC="93,5"
40 | IO_TYPE="94,6"
41 | Signal%20Name="123,7"
42 | Signal%20Type="95,8"
43 | sort_columns="Pin,Ascending"
44 |
45 | [Clock%20Resource]
46 | Clock%20Type="100,ELLIPSIS"
47 | Clock%20Name="211,ELLIPSIS"
48 | Selection="100,ELLIPSIS"
49 |
50 | [Global%20Preferences]
51 | Preference%20Name="288,ELLIPSIS"
52 | Preference%20Value="268,ELLIPSIS"
53 |
54 | [Cell%20Mapping]
55 | Type="100,ELLIPSIS"
56 | Name="100,ELLIPSIS"
57 | Din\Dout="100,ELLIPSIS"
58 | PIO%20Register="100,ELLIPSIS"
59 |
60 | [Route%20Priority]
61 | Type="100,ELLIPSIS"
62 | Name="100,ELLIPSIS"
63 | Prioritize="100,ELLIPSIS"
64 |
65 | [Timing%20Preferences]
66 | Preference%20Name="261,ELLIPSIS"
67 | Preference%20Value="128,ELLIPSIS"
68 | Preference%20Unit="121,ELLIPSIS"
69 |
70 | [Group]
71 | Group%20Type\Name="160,ELLIPSIS"
72 | Value="48,ELLIPSIS"
73 |
74 | [Misc%20Preferences]
75 | Preference%20Name="147,ELLIPSIS"
76 | Preference%20Value="128,ELLIPSIS"
77 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.jhd:
--------------------------------------------------------------------------------
1 | MODULE EFB_FOR_PLL DEFIN EFB_FOR_PLL.vhd
2 | SUBMODULE EFB
3 | INSTANCE EFBInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 | SUBMODULE VHI
7 | INSTANCE scuba_vhi_inst
8 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-5SG32C
5 | SpeedGrade=5
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=EFB
15 | CoreRevision=1.2
16 | ModuleName=EFB_FOR_PLL
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=07/02/2023
20 | Time=12:26:27
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=BusA(0 to 7)
28 | Order=Big Endian [MSB:LSB]
29 | IO=0
30 | freq=
31 | i2c1=0
32 | i2c1config=0
33 | i2c1_addr=7-Bit Addressing
34 | i2c1_ce=0
35 | i2c1_freq=100
36 | i2c1_sa=10000
37 | i2c1_we=0
38 | i2c2=0
39 | i2c2_addr=7-Bit Addressing
40 | i2c2_ce=0
41 | i2c2_freq=100
42 | i2c2_sa=10000
43 | i2c2_we=0
44 | ufm_addr=7-Bit Addressing
45 | ufm_sa=10000
46 | pll=1
47 | pll_cnt=1
48 | spi=0
49 | spi_clkinv=0
50 | spi_cs=1
51 | spi_en=0
52 | spi_freq=1
53 | spi_lsb=0
54 | spi_mode=Slave
55 | spi_ib=0
56 | spi_ph=0
57 | spi_hs=0
58 | spi_rxo=0
59 | spi_rxr=0
60 | spi_txo=0
61 | spi_txr=0
62 | spi_we=0
63 | static_tc=Static
64 | tc=0
65 | tc_clkinv=Positive
66 | tc_ctr=1
67 | tc_div=1
68 | tc_ipcap=0
69 | tc_mode=CTCM
70 | tc_ocr=32767
71 | tc_oflow=1
72 | tc_o=TOGGLE
73 | tc_opcomp=0
74 | tc_osc=0
75 | tc_sa_oflow=0
76 | tc_top=65535
77 | ufm=0
78 | ufm0=0
79 | ufm1=0
80 | ufm2=0
81 | ufm3=0
82 | ufm_cfg0=0
83 | ufm_cfg1=0
84 | wb_clk_freq=50
85 | ufm_usage=SHARED_EBR_TAG
86 | ufm_ebr=
87 | ufm_remain=
88 | mem_size=1
89 | ufm_start=
90 | ufm_init=0
91 | memfile=
92 | ufm_dt=hex
93 | ufm0_ebr=
94 | mem_size0=1
95 | ufm0_init=0
96 | memfile0=
97 | ufm0_dt=hex
98 | ufm1_ebr=
99 | mem_size1=1
100 | ufm1_init=0
101 | memfile1=
102 | ufm1_dt=hex
103 | ufm2_ebr=
104 | mem_size2=1
105 | ufm2_init=0
106 | memfile2=
107 | ufm2_dt=hex
108 | ufm3_ebr=
109 | mem_size3=1
110 | ufm3_init=0
111 | memfile3=
112 | ufm3_dt=hex
113 | ufm_cfg0_ebr=
114 | mem_size_cfg0=1
115 | ufm_cfg0_init=0
116 | memfile_cfg0=
117 | ufm_cfg0_dt=hex
118 | ufm_cfg1_ebr=
119 | mem_size_cfg1=1
120 | ufm_cfg1_init=0
121 | memfile_cfg1=
122 | ufm_cfg1_dt=hex
123 | wb=1
124 | boot_option=Internal
125 | efb_ufm=0
126 | boot_option_internal=Single Boot
127 | internal_ufm0=0
128 | internal_ufm1=0
129 | efb_ufm_boot=
130 | tamperdr=0
131 | t_pwd=0
132 | t_lockflash=0
133 | t_manmode=0
134 | t_jtagport=0
135 | t_sspiport=0
136 | t_sic2port=0
137 | t_wbport=0
138 | t_portlock=0
139 |
140 | [Command]
141 | cmd_line= -w -n EFB_FOR_PLL -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -pll1 -wb -dev 1200
142 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.naf:
--------------------------------------------------------------------------------
1 | wb_clk_i i
2 | wb_rst_i i
3 | wb_cyc_i i
4 | wb_stb_i i
5 | wb_we_i i
6 | wb_adr_i[7] i
7 | wb_adr_i[6] i
8 | wb_adr_i[5] i
9 | wb_adr_i[4] i
10 | wb_adr_i[3] i
11 | wb_adr_i[2] i
12 | wb_adr_i[1] i
13 | wb_adr_i[0] i
14 | wb_dat_i[7] i
15 | wb_dat_i[6] i
16 | wb_dat_i[5] i
17 | wb_dat_i[4] i
18 | wb_dat_i[3] i
19 | wb_dat_i[2] i
20 | wb_dat_i[1] i
21 | wb_dat_i[0] i
22 | wb_dat_o[7] o
23 | wb_dat_o[6] o
24 | wb_dat_o[5] o
25 | wb_dat_o[4] o
26 | wb_dat_o[3] o
27 | wb_dat_o[2] o
28 | wb_dat_o[1] o
29 | wb_dat_o[0] o
30 | wb_ack_o o
31 | pll0_bus_i[8] i
32 | pll0_bus_i[7] i
33 | pll0_bus_i[6] i
34 | pll0_bus_i[5] i
35 | pll0_bus_i[4] i
36 | pll0_bus_i[3] i
37 | pll0_bus_i[2] i
38 | pll0_bus_i[1] i
39 | pll0_bus_i[0] i
40 | pll0_bus_o[16] o
41 | pll0_bus_o[15] o
42 | pll0_bus_o[14] o
43 | pll0_bus_o[13] o
44 | pll0_bus_o[12] o
45 | pll0_bus_o[11] o
46 | pll0_bus_o[10] o
47 | pll0_bus_o[9] o
48 | pll0_bus_o[8] o
49 | pll0_bus_o[7] o
50 | pll0_bus_o[6] o
51 | pll0_bus_o[5] o
52 | pll0_bus_o[4] o
53 | pll0_bus_o[3] o
54 | pll0_bus_o[2] o
55 | pll0_bus_o[1] o
56 | pll0_bus_o[0] o
57 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.sort:
--------------------------------------------------------------------------------
1 | EFB_FOR_PLL.vhd
2 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.12.1.454
2 | Sun Jul 02 12:26:27 2023
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB_FOR_PLL -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -pll1 -wb -dev 1200
11 | Circuit name : EFB_FOR_PLL
12 | Module type : efb
13 | Module Version : 1.2
14 | Ports :
15 | Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0], pll0_bus_i[8:0]
16 | Outputs : wb_dat_o[7:0], wb_ack_o, pll0_bus_o[16:0]
17 | I/O buffer : not inserted
18 | EDIF output : EFB_FOR_PLL.edn
19 | VHDL output : EFB_FOR_PLL.vhd
20 | VHDL template : EFB_FOR_PLL_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : EFB_FOR_PLL.srp
24 | Element Usage :
25 | EFB : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/signalgenerator/diamond/EFB_FOR_PLL.sym
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.12.1.454
6 | Sun Jul 02 12:26:27 2023
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB_FOR_PLL -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -pll1 -wb -dev 1200
17 | Circuit name : EFB_FOR_PLL
18 | Module type : efb
19 | Module Version : 1.2
20 | Ports :
21 | Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0], pll0_bus_i[8:0]
22 | Outputs : wb_dat_o[7:0], wb_ack_o, pll0_bus_o[16:0]
23 | I/O buffer : not inserted
24 | EDIF output : EFB_FOR_PLL.edn
25 | VHDL output : EFB_FOR_PLL.vhd
26 | VHDL template : EFB_FOR_PLL_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : EFB_FOR_PLL.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: EFB_FOR_PLL.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_FOR_PLL_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.12.1.454
2 | -- Module Version: 1.2
3 | -- Sun Jul 02 12:26:27 2023
4 |
5 | -- parameterized module component declaration
6 | component EFB_FOR_PLL
7 | port (wb_clk_i: in std_logic; wb_rst_i: in std_logic;
8 | wb_cyc_i: in std_logic; wb_stb_i: in std_logic;
9 | wb_we_i: in std_logic;
10 | wb_adr_i: in std_logic_vector(7 downto 0);
11 | wb_dat_i: in std_logic_vector(7 downto 0);
12 | wb_dat_o: out std_logic_vector(7 downto 0);
13 | wb_ack_o: out std_logic;
14 | pll0_bus_i: in std_logic_vector(8 downto 0);
15 | pll0_bus_o: out std_logic_vector(16 downto 0));
16 | end component;
17 |
18 | -- parameterized module component instance
19 | __ : EFB_FOR_PLL
20 | port map (wb_clk_i=>__, wb_rst_i=>__, wb_cyc_i=>__, wb_stb_i=>__,
21 | wb_we_i=>__, wb_adr_i(7 downto 0)=>__, wb_dat_i(7 downto 0)=>__,
22 | wb_dat_o(7 downto 0)=>__, wb_ack_o=>__, pll0_bus_i(8 downto 0)=>__,
23 | pll0_bus_o(16 downto 0)=>__);
24 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.12.1.454
6 | Sun Jul 02 11:20:09 2023
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 10 -pll1 -wb -dev 1200
17 | Circuit name : EFB
18 | Module type : efb
19 | Module Version : 1.2
20 | Ports :
21 | Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0], pll0_bus_i[8:0]
22 | Outputs : wb_dat_o[7:0], wb_ack_o, pll0_bus_o[16:0]
23 | I/O buffer : not inserted
24 | EDIF output : EFB.edn
25 | VHDL output : EFB.vhd
26 | VHDL template : EFB_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : EFB.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: EFB.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/EFB_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.12.1.454
2 | -- Module Version: 1.2
3 | -- Sun Jul 02 11:20:09 2023
4 |
5 | -- parameterized module component declaration
6 | component EFB
7 | port (wb_clk_i: in std_logic; wb_rst_i: in std_logic;
8 | wb_cyc_i: in std_logic; wb_stb_i: in std_logic;
9 | wb_we_i: in std_logic;
10 | wb_adr_i: in std_logic_vector(7 downto 0);
11 | wb_dat_i: in std_logic_vector(7 downto 0);
12 | wb_dat_o: out std_logic_vector(7 downto 0);
13 | wb_ack_o: out std_logic;
14 | pll0_bus_i: in std_logic_vector(8 downto 0);
15 | pll0_bus_o: out std_logic_vector(16 downto 0));
16 | end component;
17 |
18 | -- parameterized module component instance
19 | __ : EFB
20 | port map (wb_clk_i=>__, wb_rst_i=>__, wb_cyc_i=>__, wb_stb_i=>__,
21 | wb_we_i=>__, wb_adr_i(7 downto 0)=>__, wb_dat_i(7 downto 0)=>__,
22 | wb_dat_o(7 downto 0)=>__, wb_ack_o=>__, pll0_bus_i(8 downto 0)=>__,
23 | pll0_bus_o(16 downto 0)=>__);
24 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.jhd:
--------------------------------------------------------------------------------
1 | MODULE PLL_24 DEFIN PLL_24.vhd
2 | SUBMODULE EHXPLLJ
3 | INSTANCE PLLInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-5SG32C
5 | SpeedGrade=5
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=PLL
15 | CoreRevision=5.8
16 | ModuleName=PLL_24
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=08/12/2024
20 | Time=16:18:30
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=None
28 | Order=None
29 | IO=0
30 | mode=Divider
31 | CLKI=24
32 | CLKI_DIV=3
33 | BW=0.786
34 | VCO=408.000
35 | fb_mode=CLKOP
36 | CLKFB_DIV=1
37 | FRACN_ENABLE=0
38 | FRACN_DIV=0
39 | DynamicPhase=STATIC
40 | ClkEnable=0
41 | Standby=0
42 | Enable_sel=0
43 | PLLRst=0
44 | PLLMRst=0
45 | ClkOS2Rst=0
46 | ClkOS3Rst=0
47 | LockSig=0
48 | LockStk=0
49 | WBProt=1
50 | OPBypass=0
51 | OPUseDiv=0
52 | CLKOP_DIV=51
53 | FREQ_PIN_CLKOP=100
54 | OP_Tol=0.0
55 | CLKOP_AFREQ=8.000000
56 | CLKOP_PHASEADJ=0
57 | CLKOP_TRIM_POL=Rising
58 | CLKOP_TRIM_DELAY=0
59 | EnCLKOS=1
60 | OSBypass=0
61 | OSUseDiv=0
62 | CLKOS_DIV=17
63 | FREQ_PIN_CLKOS=100
64 | OS_Tol=0.0
65 | CLKOS_AFREQ=24.000000
66 | CLKOS_PHASEADJ=0
67 | CLKOS_TRIM_POL=Rising
68 | CLKOS_TRIM_DELAY=0
69 | EnCLKOS2=0
70 | OS2Bypass=0
71 | OS2UseDiv=0
72 | CLKOS2_DIV=1
73 | FREQ_PIN_CLKOS2=100
74 | OS2_Tol=0.0
75 | CLKOS2_AFREQ=
76 | CLKOS2_PHASEADJ=0
77 | EnCLKOS3=0
78 | OS3Bypass=0
79 | OS3UseDiv=0
80 | CLKOS3_DIV=1
81 | FREQ_PIN_CLKOS3=100
82 | OS3_Tol=0.0
83 | CLKOS3_AFREQ=
84 | CLKOS3_PHASEADJ=0
85 |
86 | [Command]
87 | cmd_line= -w -n PLL_24 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 24 -mdiv 3 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 51 -trims 0 -phases 0 -trims_r -bdiv 17 -phase_cntl STATIC -fb_mode 1 -wb
88 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.naf:
--------------------------------------------------------------------------------
1 | CLKI i
2 | PLLCLK i
3 | PLLRST i
4 | PLLSTB i
5 | PLLWE i
6 | PLLDATI[7] i
7 | PLLDATI[6] i
8 | PLLDATI[5] i
9 | PLLDATI[4] i
10 | PLLDATI[3] i
11 | PLLDATI[2] i
12 | PLLDATI[1] i
13 | PLLDATI[0] i
14 | PLLADDR[4] i
15 | PLLADDR[3] i
16 | PLLADDR[2] i
17 | PLLADDR[1] i
18 | PLLADDR[0] i
19 | CLKOP o
20 | CLKOS o
21 | PLLDATO[7] o
22 | PLLDATO[6] o
23 | PLLDATO[5] o
24 | PLLDATO[4] o
25 | PLLDATO[3] o
26 | PLLDATO[2] o
27 | PLLDATO[1] o
28 | PLLDATO[0] o
29 | PLLACK o
30 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.sort:
--------------------------------------------------------------------------------
1 | PLL_24.vhd
2 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Mon Aug 12 16:18:30 2024
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_24 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 24 -mdiv 3 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 51 -trims 0 -phases 0 -trims_r -bdiv 17 -phase_cntl STATIC -fb_mode 1 -wb
11 | Circuit name : PLL_24
12 | Module type : pll
13 | Module Version : 5.7
14 | Ports :
15 | Inputs : CLKI, PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]
16 | Outputs : CLKOP, CLKOS, PLLDATO[7:0], PLLACK
17 | I/O buffer : not inserted
18 | EDIF output : PLL_24.edn
19 | VHDL output : PLL_24.vhd
20 | VHDL template : PLL_24_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : PLL_24.srp
24 | Element Usage :
25 | EHXPLLJ : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/signalgenerator/diamond/PLL_24.sym
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
6 | Mon Aug 12 16:18:30 2024
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_24 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 24 -mdiv 3 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 51 -trims 0 -phases 0 -trims_r -bdiv 17 -phase_cntl STATIC -fb_mode 1 -wb
17 | Circuit name : PLL_24
18 | Module type : pll
19 | Module Version : 5.7
20 | Ports :
21 | Inputs : CLKI, PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]
22 | Outputs : CLKOP, CLKOS, PLLDATO[7:0], PLLACK
23 | I/O buffer : not inserted
24 | EDIF output : PLL_24.edn
25 | VHDL output : PLL_24.vhd
26 | VHDL template : PLL_24_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : PLL_24.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: PLL_24.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/PLL_24_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | -- Module Version: 5.7
3 | -- Mon Aug 12 16:18:30 2024
4 |
5 | -- parameterized module component declaration
6 | component PLL_24
7 | port (CLKI: in std_logic; PLLCLK: in std_logic;
8 | PLLRST: in std_logic; PLLSTB: in std_logic;
9 | PLLWE: in std_logic; PLLDATI: in std_logic_vector(7 downto 0);
10 | PLLADDR: in std_logic_vector(4 downto 0); CLKOP: out std_logic;
11 | CLKOS: out std_logic;
12 | PLLDATO: out std_logic_vector(7 downto 0);
13 | PLLACK: out std_logic);
14 | end component;
15 |
16 | -- parameterized module component instance
17 | __ : PLL_24
18 | port map (CLKI=>__, PLLCLK=>__, PLLRST=>__, PLLSTB=>__, PLLWE=>__,
19 | PLLDATI(7 downto 0)=>__, PLLADDR(4 downto 0)=>__, CLKOP=>__,
20 | CLKOS=>__, PLLDATO(7 downto 0)=>__, PLLACK=>__);
21 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/SignalGenerator.ccl:
--------------------------------------------------------------------------------
1 | VERSION=20110520
2 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/SignalGenerator.ldf:
--------------------------------------------------------------------------------
1 |
2 |
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6 |
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8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
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46 |
47 |
48 |
49 |
50 |
51 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/SignalGenerator.lpf:
--------------------------------------------------------------------------------
1 | BLOCK RESETPATHS ;
2 | BLOCK ASYNCPATHS ;
3 | BANK 0 VCCIO 3.3 V;
4 | BANK 1 VCCIO 3.3 V;
5 | BANK 2 VCCIO 3.3 V;
6 | BANK 3 VCCIO 3.3 V;
7 | LOCATE COMP "INV_CSYNC" SITE "25" ;
8 | LOCATE COMP "INV_LUM0" SITE "26" ;
9 | LOCATE COMP "INV_LUM1" SITE "27" ;
10 | IOBUF PORT "INV_CSYNC" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
11 | IOBUF PORT "INV_LUM0" IO_TYPE=LVCMOS33 ;
12 | IOBUF PORT "INV_LUM1" IO_TYPE=LVCMOS33 ;
13 | LOCATE COMP "REFCLK" SITE "11" ;
14 | SYSCONFIG MCCLK_FREQ=2.08 CONFIG_SECURE=ON ;
15 | LOCATE COMP "SELECTION[3]" SITE "21" ;
16 | LOCATE COMP "SELECTION[2]" SITE "20" ;
17 | LOCATE COMP "SELECTION[1]" SITE "17" ;
18 | LOCATE COMP "SELECTION[0]" SITE "16" ;
19 | LOCATE COMP "SEL50HZ" SITE "23" ;
20 | IOBUF PORT "SEL50HZ" IO_TYPE=LVCMOS33 ;
21 | IOBUF PORT "SELECTION[0]" IO_TYPE=LVCMOS33 ;
22 | IOBUF PORT "SELECTION[1]" IO_TYPE=LVCMOS33 ;
23 | IOBUF PORT "SELECTION[2]" IO_TYPE=LVCMOS33 ;
24 | IOBUF PORT "SELECTION[3]" IO_TYPE=LVCMOS33 ;
25 | IOBUF PORT "REFCLK" IO_TYPE=LVCMOS33 ;
26 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.jhd:
--------------------------------------------------------------------------------
1 | MODULE TITLES DEFIN TITLES.vhd
2 | SUBMODULE DP8KC
3 | INSTANCE TITLES_0_5_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 | SUBMODULE VHI
7 | INSTANCE scuba_vhi_inst
8 | SUBMODULE DP8KC
9 | INSTANCE TITLES_0_4_1
10 | SUBMODULE DP8KC
11 | INSTANCE TITLES_0_3_2
12 | SUBMODULE DP8KC
13 | INSTANCE TITLES_0_2_3
14 | SUBMODULE DP8KC
15 | INSTANCE TITLES_0_1_4
16 | SUBMODULE DP8KC
17 | INSTANCE TITLES_0_0_5
18 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-5SG32C
5 | SpeedGrade=5
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=ROM
15 | CoreRevision=5.4
16 | ModuleName=TITLES
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=04/27/2025
20 | Time=12:51:50
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=BusA(0 to 7)
28 | Order=[MSB:LSB]
29 | IO=0
30 | Address=256
31 | Data=96
32 | enByte=0
33 | ByteSize=8
34 | OutputEn=1
35 | ClockEn=0
36 | Optimization=Speed
37 | Reset=Sync
38 | Reset1=Sync
39 | Init=0
40 | MemFile=c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem
41 | MemFormat=bin
42 | EnECC=0
43 | Pipeline=0
44 | Write=Normal
45 | init_data=0
46 | no_init=0
47 |
48 | [FilesGenerated]
49 | c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem=mem
50 |
51 | [Command]
52 | cmd_line= -w -n TITLES -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 8 -data_width 96 -num_words 256 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile "c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem" -memformat bin
53 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.naf:
--------------------------------------------------------------------------------
1 | Address[7] i
2 | Address[6] i
3 | Address[5] i
4 | Address[4] i
5 | Address[3] i
6 | Address[2] i
7 | Address[1] i
8 | Address[0] i
9 | OutClock i
10 | OutClockEn i
11 | Reset i
12 | Q[95] o
13 | Q[94] o
14 | Q[93] o
15 | Q[92] o
16 | Q[91] o
17 | Q[90] o
18 | Q[89] o
19 | Q[88] o
20 | Q[87] o
21 | Q[86] o
22 | Q[85] o
23 | Q[84] o
24 | Q[83] o
25 | Q[82] o
26 | Q[81] o
27 | Q[80] o
28 | Q[79] o
29 | Q[78] o
30 | Q[77] o
31 | Q[76] o
32 | Q[75] o
33 | Q[74] o
34 | Q[73] o
35 | Q[72] o
36 | Q[71] o
37 | Q[70] o
38 | Q[69] o
39 | Q[68] o
40 | Q[67] o
41 | Q[66] o
42 | Q[65] o
43 | Q[64] o
44 | Q[63] o
45 | Q[62] o
46 | Q[61] o
47 | Q[60] o
48 | Q[59] o
49 | Q[58] o
50 | Q[57] o
51 | Q[56] o
52 | Q[55] o
53 | Q[54] o
54 | Q[53] o
55 | Q[52] o
56 | Q[51] o
57 | Q[50] o
58 | Q[49] o
59 | Q[48] o
60 | Q[47] o
61 | Q[46] o
62 | Q[45] o
63 | Q[44] o
64 | Q[43] o
65 | Q[42] o
66 | Q[41] o
67 | Q[40] o
68 | Q[39] o
69 | Q[38] o
70 | Q[37] o
71 | Q[36] o
72 | Q[35] o
73 | Q[34] o
74 | Q[33] o
75 | Q[32] o
76 | Q[31] o
77 | Q[30] o
78 | Q[29] o
79 | Q[28] o
80 | Q[27] o
81 | Q[26] o
82 | Q[25] o
83 | Q[24] o
84 | Q[23] o
85 | Q[22] o
86 | Q[21] o
87 | Q[20] o
88 | Q[19] o
89 | Q[18] o
90 | Q[17] o
91 | Q[16] o
92 | Q[15] o
93 | Q[14] o
94 | Q[13] o
95 | Q[12] o
96 | Q[11] o
97 | Q[10] o
98 | Q[9] o
99 | Q[8] o
100 | Q[7] o
101 | Q[6] o
102 | Q[5] o
103 | Q[4] o
104 | Q[3] o
105 | Q[2] o
106 | Q[1] o
107 | Q[0] o
108 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.sort:
--------------------------------------------------------------------------------
1 | TITLES.vhd
2 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Sun Apr 27 12:51:50 2025
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n TITLES -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 8 -data_width 96 -num_words 256 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem -memformat bin
11 | Circuit name : TITLES
12 | Module type : EBR_ROM
13 | Module Version : 5.4
14 | Ports :
15 | Inputs : Address[7:0], OutClock, OutClockEn, Reset
16 | Outputs : Q[95:0]
17 | I/O buffer : not inserted
18 | Memory file : c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem
19 | EDIF output : TITLES.edn
20 | VHDL output : TITLES.vhd
21 | VHDL template : TITLES_tmpl.vhd
22 | VHDL testbench : tb_TITLES_tmpl.vhd
23 | VHDL purpose : for synthesis and simulation
24 | Bus notation : big endian
25 | Report output : TITLES.srp
26 | Element Usage :
27 | DP8KC : 6
28 | Estimated Resource Usage:
29 | EBR : 6
30 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/signalgenerator/diamond/TITLES.sym
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
6 | Sun Apr 27 12:51:50 2025
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n TITLES -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 8 -data_width 96 -num_words 256 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem -memformat bin
17 | Circuit name : TITLES
18 | Module type : EBR_ROM
19 | Module Version : 5.4
20 | Ports :
21 | Inputs : Address[7:0], OutClock, OutClockEn, Reset
22 | Outputs : Q[95:0]
23 | I/O buffer : not inserted
24 | Memory file : c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem
25 | EDIF output : TITLES.edn
26 | VHDL output : TITLES.vhd
27 | VHDL template : TITLES_tmpl.vhd
28 | VHDL testbench : tb_TITLES_tmpl.vhd
29 | VHDL purpose : for synthesis and simulation
30 | Bus notation : big endian
31 | Report output : TITLES.srp
32 | Estimated Resource Usage:
33 | EBR : 6
34 |
35 | END SCUBA Module Synthesis
36 |
37 | File: TITLES.lpc created.
38 |
39 |
40 | End process: completed successfully.
41 |
42 |
43 | Total Warnings: 0
44 |
45 | Total Errors: 0
46 |
47 |
48 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/TITLES_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | -- Module Version: 5.4
3 | -- Sun Apr 27 12:51:50 2025
4 |
5 | -- parameterized module component declaration
6 | component TITLES
7 | port (Address: in std_logic_vector(7 downto 0);
8 | OutClock: in std_logic; OutClockEn: in std_logic;
9 | Reset: in std_logic; Q: out std_logic_vector(95 downto 0));
10 | end component;
11 |
12 | -- parameterized module component instance
13 | __ : TITLES
14 | port map (Address(7 downto 0)=>__, OutClock=>__, OutClockEn=>__,
15 | Reset=>__, Q(95 downto 0)=>__);
16 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/generate_core.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | proc GetCmdLine {lpcfile} {
48 | global Para
49 |
50 | if [catch {open $lpcfile r} fileid] {
51 | puts "Cannot open $para_file file!"
52 | exit -1
53 | }
54 |
55 | seek $fileid 0 start
56 | set default_match 0
57 | while {[gets $fileid line] >= 0} {
58 | if {[string first "\[Command\]" $line] == 0} {
59 | set default_match 1
60 | continue
61 | }
62 | if {[string first "\[" $line] == 0} {
63 | set default_match 0
64 | }
65 | if {$default_match == 1} {
66 | if [regexp {([^=]*)=(.*)} $line match parameter value] {
67 | if [regexp {([ |\t]*;)} $parameter match] {continue}
68 | if [regexp {(.*)[ |\t]*;} $value match temp] {
69 | set Para($parameter) $temp
70 | } else {
71 | set Para($parameter) $value
72 | }
73 | }
74 | }
75 | }
76 | set default_match 0
77 | close $fileid
78 |
79 | return $Para(cmd_line)
80 | }
81 |
82 | set platformpath [GetPlatform]
83 | set Para(sbp_path) [file dirname [info script]]
84 | set Para(install_dir) $env(TOOLRTF)
85 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
86 |
87 | set scuba "$Para(FPGAPath)/scuba"
88 | set modulename "TITLES"
89 | set lang "vhdl"
90 | set lpcfile "$Para(sbp_path)/$modulename.lpc"
91 | set arch "xo2c00"
92 | set cmd_line [GetCmdLine $lpcfile]
93 | set fdcfile "$Para(sbp_path)/$modulename.fdc"
94 | if {[file exists $fdcfile] == 0} {
95 | append scuba " " $cmd_line
96 | } else {
97 | append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
98 | }
99 | set Para(result) [catch {eval exec "$scuba"} msg]
100 | #puts $msg
101 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/generate_ngd.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | set platformpath [GetPlatform]
48 | set Para(sbp_path) [file dirname [info script]]
49 | set Para(install_dir) $env(TOOLRTF)
50 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
51 | set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
52 |
53 | set Para(ModuleName) "TITLES"
54 | set Para(Module) "ROM"
55 | set Para(libname) machxo2
56 | set Para(arch_name) xo2c00
57 | set Para(PartType) "LCMXO2-1200HC"
58 |
59 | set Para(tech_syn) machxo2
60 | set Para(tech_cae) machxo2
61 | set Para(Package) "QFN32"
62 | set Para(SpeedGrade) "5"
63 | set Para(FMax) "100"
64 | set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
65 |
66 | #edif2ngd
67 | set edif2ngd "$Para(FPGAPath)/edif2ngd"
68 | set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
69 | #puts $msg
70 |
71 | #ngdbuild
72 | set ngdbuild "$Para(FPGAPath)/ngdbuild"
73 | set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
74 | #puts $msg
75 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/msg_file.log:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Sun Apr 27 12:51:50 2025
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | BEGIN SCUBA Module Synthesis
11 |
12 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n TITLES -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-1200HC -addr_width 8 -data_width 96 -num_words 256 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem -memformat bin
13 | Circuit name : TITLES
14 | Module type : EBR_ROM
15 | Module Version : 5.4
16 | Ports :
17 | Inputs : Address[7:0], OutClock, OutClockEn, Reset
18 | Outputs : Q[95:0]
19 | I/O buffer : not inserted
20 | Memory file : c:/users/reinhard/documents/github_lumacode/lumacode/signalgenerator/diamond/source/titles.mem
21 | EDIF output : TITLES.edn
22 | VHDL output : TITLES.vhd
23 | VHDL template : TITLES_tmpl.vhd
24 | VHDL testbench : tb_TITLES_tmpl.vhd
25 | VHDL purpose : for synthesis and simulation
26 | Bus notation : big endian
27 | Report output : TITLES.srp
28 | Estimated Resource Usage:
29 | EBR : 6
30 |
31 | END SCUBA Module Synthesis
32 |
33 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/promote.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/reportview.xml:
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/source/ClockGenerator.vhd:
--------------------------------------------------------------------------------
1 |
2 | library ieee;
3 | use ieee.numeric_std.all;
4 | use ieee.std_logic_1164.all;
5 | use work.Frequencies.all;
6 |
7 | entity ClockGenerator is
8 | port (
9 | -- reference oscillator input
10 | REFCLK : in std_logic;
11 | -- selected output frequency
12 | FREQUENCY : in t_Frequency;
13 | -- generated clock
14 | CLK : out std_logic
15 | );
16 | end entity;
17 |
18 | architecture immediate of ClockGenerator is
19 |
20 | component PLL_24
21 | port (
22 | CLKI: in std_logic;
23 | PLLCLK: in std_logic;
24 | PLLRST: in std_logic;
25 | PLLSTB: in std_logic;
26 | PLLWE: in std_logic;
27 | PLLDATI: in std_logic_vector(7 downto 0);
28 | PLLADDR: in std_logic_vector(4 downto 0);
29 | CLKOP: out std_logic;
30 | CLKOS: out std_logic;
31 | PLLDATO: out std_logic_vector(7 downto 0);
32 | PLLACK: out std_logic
33 | );
34 | end component;
35 |
36 | -- clock for wishbone programming
37 | COMPONENT OSCH
38 | GENERIC (NOM_FREQ: string);
39 | PORT (
40 | STDBY:IN std_logic;
41 | OSC:OUT std_logic;
42 | SEDSTDBY:OUT std_logic
43 | );
44 | END COMPONENT;
45 | -- wishbone interface
46 | component EFB_FOR_PLL
port (
47 | wb_clk_i: in std_logic;
48 | wb_rst_i: in std_logic;
49 | wb_cyc_i: in std_logic;
50 | wb_stb_i: in std_logic;
51 | wb_we_i: in std_logic;
52 | wb_adr_i: in std_logic_vector(7 downto 0);
53 | wb_dat_i: in std_logic_vector(7 downto 0);
54 | wb_dat_o: out std_logic_vector(7 downto 0);
55 | wb_ack_o: out std_logic;
56 | pll0_bus_i: in std_logic_vector(8 downto 0);
57 | pll0_bus_o: out std_logic_vector(16 downto 0)
58 | );
59 | end component;
60 |
61 | signal PLL_bus_i: std_logic_vector(8 downto 0);
62 | signal PLL_bus_o: std_logic_vector(16 downto 0);
63 | signal WB_clk : std_logic;
64 | signal WB_cyc : std_logic;
65 | signal WB_we : std_logic;
66 | signal WB_adr : std_logic_vector(7 downto 0);
67 | signal WB_dat_i : std_logic_vector(7 downto 0);
68 | signal WB_ack : std_logic;
69 |
70 | begin
71 | my_pll : PLL_24 PORT MAP (
72 | CLKI => REFCLK,
73 | CLKOP => open,
74 | CLKOS => CLK,
75 | PLLCLK => PLL_bus_o(16),
76 | PLLRST => PLL_bus_o(15),
77 | PLLSTB => PLL_bus_o(14),
78 | PLLWE => PLL_bus_o(13),
79 | PLLADDR => PLL_bus_o(12 downto 8),
80 | PLLDATI => PLL_bus_o(7 downto 0),
81 | PLLDATO => PLL_bus_i(8 downto 1),
82 | PLLACK => PLL_bus_i(0)
83 | );
84 |
85 | OSCInst0: OSCH
86 | GENERIC MAP( NOM_FREQ => "2.08" )
87 | PORT MAP ( STDBY=> '0', OSC => WB_clk, SEDSTDBY => open );
88 |
89 | my_efb : EFB_FOR_PLL PORT MAP (
90 | wb_clk_i => WB_clk,
91 | wb_rst_i => '0',
92 | wb_cyc_i => WB_cyc,
93 | wb_stb_i => '1',
94 | wb_we_i => WB_we,
95 | wb_adr_i => WB_adr,
96 | wb_dat_i => WB_dat_i,
97 | wb_dat_o => open,
98 | wb_ack_o => WB_ack,
99 | pll0_bus_i => PLL_bus_i,
100 | pll0_bus_o => PLL_bus_o
101 | );
102 |
103 | -- monitor the frequency input setting and adjust PLL accordingly
104 | process (WB_clk)
105 | variable startup : integer range 0 to 100000 := 100000;
106 | variable didinit : boolean := false;
107 | variable freq_set : t_Frequency := MHZ_15_763;
108 | variable freq_now : t_Frequency := MHZ_15_763;
109 | variable reconfiguring : integer range 0 to 3 := 0;
110 | variable diva: integer range 0 to 127;
111 | variable divb: integer range 0 to 127;
112 | begin
113 | if rising_edge(WB_clk) then
114 | if startup/=0 then
115 | WB_cyc <= '0';
116 | startup := startup-1;
117 | elsif reconfiguring=0 then
118 | if freq_set /= freq_now or not didinit then
119 | case freq_set is
120 | when MHZ_7_080 => diva:=77; divb:=87;
121 | when MHZ_7_159 => diva:=51; divb:=57;
122 | when MHZ_8_000 => diva:=50; divb:=50;
123 | when MHZ_8_181 => diva:=90; divb:=88;
124 | when MHZ_8_867 => diva:=92; divb:=83;
125 | when MHZ_10_738 => diva:=98; divb:=73;
126 | when MHZ_14_000 => diva:=56; divb:=32;
127 | when MHZ_14_110 => diva:=97; divb:=55;
128 | when MHZ_14_187 => diva:=94; divb:=53;
129 | when MHZ_14_318 => diva:=68; divb:=38;
130 | when MHZ_15_763 => diva:=67; divb:=34;
131 | when MHZ_15_961 => diva:=50; divb:=25;
132 | when MHZ_16_000 => diva:=50; divb:=25;
133 | when MHZ_16_108 => diva:=99; divb:=49;
134 | when MHZ_16_363 => diva:=90; divb:=44;
135 | when MHZ_21_281 => diva:=93; divb:=35;
136 | when MHZ_21_477 => diva:=51; divb:=19;
137 | when MHZ_24_000 => diva:=51; divb:=17;
138 | when MHZ_28_636 => diva:=68; divb:=19;
139 | when MHZ_31_922 => diva:=60; divb:=15;
140 | when MHZ_32_216 => diva:=97; divb:=24;
141 | when others => diva:=1; divb:=1;
142 | end case;
143 | WB_cyc <= '1'; -- start a cycle
144 | WB_we <= '1'; -- write
145 | WB_adr <= "00000110"; -- register 6: MC1_DIVA
146 | WB_dat_i <= std_logic_vector(to_unsigned(diva-1, 8));
147 | reconfiguring := 1;
148 | freq_now := freq_set;
149 | didinit := true;
150 | else
151 | WB_cyc <= '0';
152 | end if;
153 | elsif reconfiguring=1 then
154 | if WB_ack='1' then -- wait for ack and then end cycle
155 | WB_cyc <= '0';
156 | reconfiguring := 2;
157 | end if;
158 | elsif reconfiguring=2 then
159 | WB_cyc <= '1'; -- start a cycle
160 | WB_we <= '1'; -- write
161 | WB_adr <= "00000111"; -- register 7: MC1_DIVB
162 | WB_dat_i <= std_logic_vector(to_unsigned(divb-1, 8));
163 | reconfiguring := 3;
164 | elsif reconfiguring=3 then
165 | if WB_ack='1' then -- wait for ack and then end cycle
166 | WB_cyc <= '0';
167 | reconfiguring := 0;
168 | end if;
169 | end if;
170 |
171 | freq_set := frequency;
172 | end if;
173 | end process;
174 |
175 | end immediate;
176 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/source/Frequencies.vhd:
--------------------------------------------------------------------------------
1 | package Frequencies is
2 |
3 | type t_Frequency is (
4 | MHZ_7_080, -- G7000 2x pixel clock = 7.080000
5 | MHZ_7_159, -- NTSC Intellivion 2x pixel clock = 7.159088
6 | MHZ_8_000, -- PAL Intellivion 2x pixel clock = 8.000000
7 | MHZ_8_181, -- NTSC VIC 20 2x pixel clock = 8.181817
8 | MHZ_8_867, -- PAL VIC 20 2x pixel clock = 8.867236
9 | MHZ_10_738, -- PAL/NTSC TMS99xxA 2x pixel clock = 10.738635
10 | MHZ_14_000, -- PAL ZX Spectrum 2x pixel clock = 14.000000
11 | MHZ_14_110, -- NTSC ZX Spectrum 2x pixel clock = 14.110000
12 | MHZ_14_187, -- PAL Atari 2600 4x pixel clock = 14.18758
13 | MHZ_14_318, -- NTSC Atari 2600 4x pixel clock = 14.31818
14 | MHZ_15_763, -- PAL C64/C128 2x pixel clock = 15.763968
15 | MHZ_15_961, -- PAL Master System 3x pixel = 15.961023
16 | MHZ_16_000, -- C128 VDC
17 | MHZ_16_108, -- NTSC Master System 3x pixel = 16.1079525
18 | MHZ_16_363, -- NTSC C64 2x pixel clock = 16.363632
19 | MHZ_21_281, -- PAL Atari 8-bit 6x pixel clock = 21.28137
20 | MHZ_21_477, -- NTSC Atari 8-bit 6x pixel clock = 21.47727
21 | MHZ_24_000, -- Lumacode270p
22 | MHZ_28_636, -- Maria x4 pixel clock = 28.63636
23 | MHZ_31_922, -- PAL NES 6x pixel clock = 31.9220544
24 | MHZ_32_216 -- NTSC NES 6x pixel clock = 32.215908
25 | );
26 |
27 | end Frequencies;
28 |
--------------------------------------------------------------------------------
/signalgenerator/diamond/tb_TITLES_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | library IEEE;
3 | use IEEE.std_logic_1164.all;
4 | use IEEE.std_logic_unsigned.all;
5 |
6 | use IEEE.math_real.all;
7 |
8 | use IEEE.numeric_std.all;
9 |
10 | entity tb is
11 | end entity tb;
12 |
13 |
14 | architecture test of tb is
15 |
16 | component TITLES
17 | port (Address : in std_logic_vector(7 downto 0);
18 | OutClock: in std_logic; OutClockEn: in std_logic;
19 | Reset: in std_logic; Q : out std_logic_vector(95 downto 0)
20 | );
21 | end component;
22 |
23 | signal Address : std_logic_vector(7 downto 0) := (others => '0');
24 | signal OutClock: std_logic := '0';
25 | signal OutClockEn: std_logic := '0';
26 | signal Reset: std_logic := '0';
27 | signal Q : std_logic_vector(95 downto 0);
28 | begin
29 | u1 : TITLES
30 | port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn,
31 | Reset => Reset, Q => Q
32 | );
33 |
34 | process
35 |
36 | begin
37 | Address <= (others => '0') ;
38 | wait for 100 ns;
39 | wait until Reset = '0';
40 | for i in 0 to 259 loop
41 | wait until OutClock'event and OutClock = '1';
42 | Address <= Address + '1' after 1 ns;
43 | end loop;
44 | wait;
45 | end process;
46 |
47 | OutClock <= not OutClock after 5.00 ns;
48 |
49 | process
50 |
51 | begin
52 | OutClockEn <= '0' ;
53 | wait for 100 ns;
54 | wait until Reset = '0';
55 | OutClockEn <= '1' ;
56 | wait;
57 | end process;
58 |
59 | process
60 |
61 | begin
62 | Reset <= '1' ;
63 | wait for 100 ns;
64 | Reset <= '0' ;
65 | wait;
66 | end process;
67 |
68 | end architecture test;
69 |
--------------------------------------------------------------------------------
/signalgenerator/doc/AtariST400p72.txt:
--------------------------------------------------------------------------------
1 | sampling=2,2,2,2,2,2,2,0,0,0,7,1,0,0,0,0,0,8,0,0,84,256,256,256,20,256,256,256
2 | geometry=116,75,640,400,640,400,1,1,0,0,32000000,896,5000,501,4,0,0
3 | palette=Mono_(2_level)
4 | scanline_level=0
5 |
--------------------------------------------------------------------------------
/signalgenerator/doc/Lumacode270p50.txt:
--------------------------------------------------------------------------------
1 | sampling=6,6,6,6,6,6,6,1,1,0,3,1,0,0,0,2,0,2,1,0,58,40,256,256,10,26,256,256
2 | geometry=4,36,480,270,480,270,2,2,3,2,24000000,1539,4000,312,4,0,0
3 | palette=RGB6(Lumacode)
4 | palette_control=10
5 |
--------------------------------------------------------------------------------
/signalgenerator/doc/Lumacode270p_specs.txt:
--------------------------------------------------------------------------------
1 | 1080p-scaleable SD signal (16:9)
2 |
3 | Input 50Hz:
4 | v sync 3 lines
5 | v back porch 37 lines
6 | v visible 270 lines
7 | v front porch 2 lines
8 | v total 312 lines
9 |
10 | h sync 24 pixels (3 us)
11 | h back porch 6 pixels (0.75 us)
12 | h visible 480 pixels (60 us)
13 | h front porch 3 pixels (0.375 us)
14 | h total 513 pixels (64.125 us)
15 |
16 | pixel rate 8 MHz
17 | frame rate 49.9825 Hz
18 |
--------------------------------------------------------------------------------
/signalgenerator/doc/calc720p.py:
--------------------------------------------------------------------------------
1 | def calc(target):
2 | bestf = 0
3 | bestvco = 0
4 | bestd1 = 0
5 | bestdivider = 0
6 | for d1 in range(20,150,1):
7 | vco = 24*d1
8 | for divider in range(1,1290,1):
9 | f = vco/divider
10 | if abs(f-target) < abs(bestf-target):
11 | bestf = f
12 | bestvco = vco
13 | bestd1 = d1
14 | bestdivider = divider
15 | print ("best for ",target,": ",bestvco,"(",bestd1,") ","/",bestdivider,"=", bestvco/bestdivider);
16 | calc(115.024) # HDMI 1080p
17 |
--------------------------------------------------------------------------------
/signalgenerator/doc/calcpll.py:
--------------------------------------------------------------------------------
1 | def calc(target):
2 | bestf = 0
3 | bestvco = 0
4 | vestdivider = 0
5 | for multiplier in range(50,100,1):
6 | vco = 8*multiplier;
7 | for divider in range(15,100,1):
8 | f = vco/divider
9 | if abs(f-target) < abs(bestf-target):
10 | bestf = f
11 | bestvco = vco
12 | bestdivider = divider
13 | print ("best for ",target,": ",bestvco/8,":",bestdivider,"=", bestvco/bestdivider);
14 |
15 | calc(7.080000)
16 | calc(7.159088)
17 | calc(8.000000)
18 | calc(8.181817)
19 | calc(8.867236)
20 | calc(10.738635)
21 | calc(14.000000)
22 | calc(14.11000)
23 | calc(14.18758)
24 | calc(14.31818)
25 | calc(15.763968)
26 | calc(15.961023)
27 | calc(16.00000)
28 | calc(16.1079525)
29 | calc(16.363632)
30 | calc(21.28137)
31 | calc(21.47727)
32 | calc(24.0000)
33 | calc(28.63636)
34 | calc(31.9220544)
35 | calc(32.215908)
36 |
--------------------------------------------------------------------------------
/signalgenerator/doc/signalgenerator.jpg:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/signalgenerator/doc/signalgenerator.jpg
--------------------------------------------------------------------------------
/signalgenerator/doc/switches.txt:
--------------------------------------------------------------------------------
1 |
2 | DIP-switch settings for the lumacode signal generator
3 |
4 | 1 2 3 4
5 | OFF OFF OFF OFF C64/C128
6 | OFF OFF OFF ON C64 6567R56A (only 60Hz)
7 | OFF OFF ON OFF VIC 20
8 | OFF OFF ON ON C16, Plus/4
9 | OFF ON OFF OFF Atari 8-bit
10 | OFF ON OFF ON Atari 2600 PAL colors
11 | OFF ON ON OFF Atari 2600 NTSC colors
12 | OFF ON ON ON Atari 7800
13 | ON OFF OFF OFF TMS99xxA
14 | ON OFF OFF ON ZX Spectrum (only 50Hz)
15 | ON OFF ON OFF NES
16 | ON OFF ON ON Sega Master System
17 | ON ON OFF OFF Intellivision
18 | ON ON OFF ON G7000 or Odyssey II
19 | others Lumacode 720p (only 50Hz)
20 |
21 | When jumper set: 50Hz
22 | When not set: 60Hz
23 |
--------------------------------------------------------------------------------
/testrig/100mhz/.run_manager.ini:
--------------------------------------------------------------------------------
1 | [Runmanager]
2 | Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x2\x7f\0\0\x1\xdf\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
3 | windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4 | headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
5 |
6 | [impl1%3CStrategy1%3E]
7 | isChecked=false
8 | isHidden=false
9 | isExpanded=false
10 |
--------------------------------------------------------------------------------
/testrig/100mhz/.spread_sheet.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | COLUMN_POS_INFO_NAME_-1_0=Prioritize
3 | COLUMN_POS_INFO_NAME_-1_1=PIO Register
4 |
--------------------------------------------------------------------------------
/testrig/100mhz/.spreadsheet_view.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | pin_sort_type=0
3 | pin_sort_ascending=true
4 | sig_sort_type=0
5 | sig_sort_ascending=true
6 | active_Sheet=Port Assignments
7 |
8 | [Port%20Assignments]
9 | Name="171,0"
10 | Group%20By="83,1"
11 | Pin="55,2"
12 | BANK="66,3"
13 | BANK_VCC="93,4"
14 | VREF="63,5"
15 | IO_TYPE="185,6"
16 | PULLMODE="127,7"
17 | DRIVE="70,8"
18 | SLEWRATE="121,9"
19 | CLAMP="89,10"
20 | OPENDRAIN="100,11"
21 | DIFFRESISTOR="114,12"
22 | DIFFDRIVE="95,13"
23 | HYSTERESIS="125,14"
24 | Outload%20%28pF%29="101,15"
25 | MaxSkew="86,16"
26 | Clock%20Load%20Only="118,17"
27 | SwitchingID="98,18"
28 | Ground%20plane%20PCB%20noise%20%28mV%29="185,19"
29 | Power%20plane%20PCB%20noise%20%28mV%29="182,20"
30 | SSO%20Allowance%28%25%29="134,21"
31 | sort_columns="Name,Ascending"
32 |
33 | [Pin%20Assignments]
34 | Pin="95,0"
35 | Pad%20Name="94,1"
36 | Dual%20Function="205,2"
37 | Polarity="77,3"
38 | BANK="0,4"
39 | BANK_VCC="93,5"
40 | IO_TYPE="185,6"
41 | Signal%20Name="119,7"
42 | Signal%20Type="135,8"
43 | sort_columns="Pin,Ascending"
44 |
45 | [Clock%20Resource]
46 | Clock%20Type="100,ELLIPSIS"
47 | Clock%20Name="100,ELLIPSIS"
48 | Selection="100,ELLIPSIS"
49 |
50 | [Global%20Preferences]
51 | Preference%20Name="288,ELLIPSIS"
52 | Preference%20Value="268,ELLIPSIS"
53 |
54 | [Cell%20Mapping]
55 | Type="100,ELLIPSIS"
56 | Name="100,ELLIPSIS"
57 | Din\Dout="100,ELLIPSIS"
58 | PIO%20Register="100,ELLIPSIS"
59 |
60 | [Route%20Priority]
61 | Type="100,ELLIPSIS"
62 | Name="100,ELLIPSIS"
63 | Prioritize="100,ELLIPSIS"
64 |
65 | [Timing%20Preferences]
66 | Preference%20Name="177,ELLIPSIS"
67 | Preference%20Value="128,ELLIPSIS"
68 | Preference%20Unit="121,ELLIPSIS"
69 |
70 | [Group]
71 | Group%20Type\Name="160,ELLIPSIS"
72 | Value="48,ELLIPSIS"
73 |
74 | [Misc%20Preferences]
75 | Preference%20Name="147,ELLIPSIS"
76 | Preference%20Value="128,ELLIPSIS"
77 |
--------------------------------------------------------------------------------
/testrig/100mhz/Generate100MHz.ccl:
--------------------------------------------------------------------------------
1 | VERSION=20110520
2 |
--------------------------------------------------------------------------------
/testrig/100mhz/Generate100MHz.ldf:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
--------------------------------------------------------------------------------
/testrig/100mhz/Generate100MHz.lpf:
--------------------------------------------------------------------------------
1 | BLOCK RESETPATHS ;
2 | BLOCK ASYNCPATHS ;
3 | LOCATE COMP "CLK25" SITE "21" ;
4 | LOCATE COMP "CP[0]" SITE "17" ;
5 | LOCATE COMP "CP[1]" SITE "16" ;
6 | LOCATE COMP "CP[2]" SITE "28" ;
7 | LOCATE COMP "CP[3]" SITE "27" ;
8 | LOCATE COMP "D[0]" SITE "13" ;
9 | LOCATE COMP "D[1]" SITE "12" ;
10 | LOCATE COMP "D[2]" SITE "11" ;
11 | LOCATE COMP "D[3]" SITE "10" ;
12 | LOCATE COMP "D[4]" SITE "9" ;
13 | LOCATE COMP "D[5]" SITE "8" ;
14 | LOCATE COMP "D[6]" SITE "5" ;
15 | LOCATE COMP "D[7]" SITE "4" ;
16 |
--------------------------------------------------------------------------------
/testrig/100mhz/Generate100MHz.sdc:
--------------------------------------------------------------------------------
1 | create_clock -period 40 -name clk25 [get_ports CLK25]
2 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.jhd:
--------------------------------------------------------------------------------
1 | MODULE PLL200 DEFIN PLL200.vhd
2 | SUBMODULE EHXPLLJ
3 | INSTANCE PLLInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-5SG32C
5 | SpeedGrade=5
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=PLL
15 | CoreRevision=5.8
16 | ModuleName=PLL200
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=09/09/2023
20 | Time=16:17:18
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=None
28 | Order=None
29 | IO=0
30 | mode=Frequency
31 | CLKI=25
32 | CLKI_DIV=1
33 | BW=2.387
34 | VCO=600.000
35 | fb_mode=CLKOP
36 | CLKFB_DIV=8
37 | FRACN_ENABLE=0
38 | FRACN_DIV=0
39 | DynamicPhase=STATIC
40 | ClkEnable=0
41 | Standby=0
42 | Enable_sel=0
43 | PLLRst=0
44 | PLLMRst=0
45 | ClkOS2Rst=0
46 | ClkOS3Rst=0
47 | LockSig=0
48 | LockStk=0
49 | WBProt=0
50 | OPBypass=0
51 | OPUseDiv=0
52 | CLKOP_DIV=3
53 | FREQ_PIN_CLKOP=200
54 | OP_Tol=0.0
55 | CLKOP_AFREQ=200.000000
56 | CLKOP_PHASEADJ=0
57 | CLKOP_TRIM_POL=Rising
58 | CLKOP_TRIM_DELAY=0
59 | EnCLKOS=0
60 | OSBypass=0
61 | OSUseDiv=0
62 | CLKOS_DIV=1
63 | FREQ_PIN_CLKOS=100
64 | OS_Tol=0.0
65 | CLKOS_AFREQ=
66 | CLKOS_PHASEADJ=0
67 | CLKOS_TRIM_POL=Rising
68 | CLKOS_TRIM_DELAY=0
69 | EnCLKOS2=0
70 | OS2Bypass=0
71 | OS2UseDiv=0
72 | CLKOS2_DIV=1
73 | FREQ_PIN_CLKOS2=100
74 | OS2_Tol=0.0
75 | CLKOS2_AFREQ=
76 | CLKOS2_PHASEADJ=0
77 | EnCLKOS3=0
78 | OS3Bypass=0
79 | OS3UseDiv=0
80 | CLKOS3_DIV=1
81 | FREQ_PIN_CLKOS3=100
82 | OS3_Tol=0.0
83 | CLKOS3_AFREQ=
84 | CLKOS3_PHASEADJ=0
85 |
86 | [Command]
87 | cmd_line= -w -n PLL200 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 200 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
88 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.naf:
--------------------------------------------------------------------------------
1 | CLKI i
2 | CLKOP o
3 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.sort:
--------------------------------------------------------------------------------
1 | PLL200.vhd
2 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.12.1.454
2 | Sat Sep 09 16:17:18 2023
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL200 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 200 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
11 | Circuit name : PLL200
12 | Module type : pll
13 | Module Version : 5.7
14 | Ports :
15 | Inputs : CLKI
16 | Outputs : CLKOP
17 | I/O buffer : not inserted
18 | EDIF output : PLL200.edn
19 | VHDL output : PLL200.vhd
20 | VHDL template : PLL200_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : PLL200.srp
24 | Element Usage :
25 | EHXPLLJ : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/testrig/100mhz/PLL200.sym
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
2 | -- Module Version: 5.7
3 | --C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL200 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 200 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
4 |
5 | -- Sat Sep 09 16:17:18 2023
6 |
7 | library IEEE;
8 | use IEEE.std_logic_1164.all;
9 | -- synopsys translate_off
10 | library MACHXO2;
11 | use MACHXO2.components.all;
12 | -- synopsys translate_on
13 |
14 | entity PLL200 is
15 | port (
16 | CLKI: in std_logic;
17 | CLKOP: out std_logic);
18 | end PLL200;
19 |
20 | architecture Structure of PLL200 is
21 |
22 | -- internal signal declarations
23 | signal LOCK: std_logic;
24 | signal CLKOP_t: std_logic;
25 | signal scuba_vlo: std_logic;
26 |
27 | -- local component declarations
28 | component VLO
29 | port (Z: out std_logic);
30 | end component;
31 | component EHXPLLJ
32 | generic (INTFB_WAKE : in String; DDRST_ENA : in String;
33 | DCRST_ENA : in String; MRST_ENA : in String;
34 | PLLRST_ENA : in String; DPHASE_SOURCE : in String;
35 | STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
36 | OUTDIVIDER_MUXC2 : in String;
37 | OUTDIVIDER_MUXB2 : in String;
38 | OUTDIVIDER_MUXA2 : in String;
39 | PREDIVIDER_MUXD1 : in Integer;
40 | PREDIVIDER_MUXC1 : in Integer;
41 | PREDIVIDER_MUXB1 : in Integer;
42 | PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
43 | PLL_LOCK_MODE : in Integer;
44 | CLKOS_TRIM_DELAY : in Integer;
45 | CLKOS_TRIM_POL : in String;
46 | CLKOP_TRIM_DELAY : in Integer;
47 | CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
48 | FRACN_ENABLE : in String; FEEDBK_PATH : in String;
49 | CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
50 | CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
51 | CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
52 | CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
53 | VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
54 | VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
55 | CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
56 | CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
57 | CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
58 | CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
59 | CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
60 | port (CLKI: in std_logic; CLKFB: in std_logic;
61 | PHASESEL1: in std_logic; PHASESEL0: in std_logic;
62 | PHASEDIR: in std_logic; PHASESTEP: in std_logic;
63 | LOADREG: in std_logic; STDBY: in std_logic;
64 | PLLWAKESYNC: in std_logic; RST: in std_logic;
65 | RESETM: in std_logic; RESETC: in std_logic;
66 | RESETD: in std_logic; ENCLKOP: in std_logic;
67 | ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
68 | ENCLKOS3: in std_logic; PLLCLK: in std_logic;
69 | PLLRST: in std_logic; PLLSTB: in std_logic;
70 | PLLWE: in std_logic; PLLADDR4: in std_logic;
71 | PLLADDR3: in std_logic; PLLADDR2: in std_logic;
72 | PLLADDR1: in std_logic; PLLADDR0: in std_logic;
73 | PLLDATI7: in std_logic; PLLDATI6: in std_logic;
74 | PLLDATI5: in std_logic; PLLDATI4: in std_logic;
75 | PLLDATI3: in std_logic; PLLDATI2: in std_logic;
76 | PLLDATI1: in std_logic; PLLDATI0: in std_logic;
77 | CLKOP: out std_logic; CLKOS: out std_logic;
78 | CLKOS2: out std_logic; CLKOS3: out std_logic;
79 | LOCK: out std_logic; INTLOCK: out std_logic;
80 | REFCLK: out std_logic; CLKINTFB: out std_logic;
81 | DPHSRC: out std_logic; PLLACK: out std_logic;
82 | PLLDATO7: out std_logic; PLLDATO6: out std_logic;
83 | PLLDATO5: out std_logic; PLLDATO4: out std_logic;
84 | PLLDATO3: out std_logic; PLLDATO2: out std_logic;
85 | PLLDATO1: out std_logic; PLLDATO0: out std_logic);
86 | end component;
87 | attribute FREQUENCY_PIN_CLKOP : string;
88 | attribute FREQUENCY_PIN_CLKI : string;
89 | attribute ICP_CURRENT : string;
90 | attribute LPF_RESISTOR : string;
91 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000";
92 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000";
93 | attribute ICP_CURRENT of PLLInst_0 : label is "9";
94 | attribute LPF_RESISTOR of PLLInst_0 : label is "8";
95 | attribute syn_keep : boolean;
96 | attribute NGD_DRC_MASK : integer;
97 | attribute NGD_DRC_MASK of Structure : architecture is 1;
98 |
99 | begin
100 | -- component instantiation statements
101 | scuba_vlo_inst: VLO
102 | port map (Z=>scuba_vlo);
103 |
104 | PLLInst_0: EHXPLLJ
105 | generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
106 | MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
107 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
108 | PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
109 | CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
110 | CLKOS_CPHASE=> 0, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 2,
111 | PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
112 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
113 | FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
114 | PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
115 | OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
116 | CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
117 | PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED",
118 | OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
119 | CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
120 | CLKOS_DIV=> 1, CLKOP_DIV=> 3, CLKFB_DIV=> 8, CLKI_DIV=> 1,
121 | FEEDBK_PATH=> "CLKOP")
122 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
123 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
124 | PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
125 | PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
126 | RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
127 | ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
128 | PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
129 | PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
130 | PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
131 | PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
132 | PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
133 | PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
134 | PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
135 | PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
136 | CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
137 | REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
138 | PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
139 | PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
140 | PLLDATO1=>open, PLLDATO0=>open);
141 |
142 | CLKOP <= CLKOP_t;
143 | end Structure;
144 |
145 | -- synopsys translate_off
146 | library MACHXO2;
147 | configuration Structure_CON of PLL200 is
148 | for Structure
149 | for all:VLO use entity MACHXO2.VLO(V); end for;
150 | for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
151 | end for;
152 | end Structure_CON;
153 |
154 | -- synopsys translate_on
155 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.12.1.454
6 | Sat Sep 09 16:17:18 2023
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL200 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 200 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
17 | Circuit name : PLL200
18 | Module type : pll
19 | Module Version : 5.7
20 | Ports :
21 | Inputs : CLKI
22 | Outputs : CLKOP
23 | I/O buffer : not inserted
24 | EDIF output : PLL200.edn
25 | VHDL output : PLL200.vhd
26 | VHDL template : PLL200_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : PLL200.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: PLL200.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/testrig/100mhz/PLL200_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.12.1.454
2 | -- Module Version: 5.7
3 | -- Sat Sep 09 16:17:18 2023
4 |
5 | -- parameterized module component declaration
6 | component PLL200
7 | port (CLKI: in std_logic; CLKOP: out std_logic);
8 | end component;
9 |
10 | -- parameterized module component instance
11 | __ : PLL200
12 | port map (CLKI=>__, CLKOP=>__);
13 |
--------------------------------------------------------------------------------
/testrig/100mhz/generate_core.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | proc GetCmdLine {lpcfile} {
48 | global Para
49 |
50 | if [catch {open $lpcfile r} fileid] {
51 | puts "Cannot open $para_file file!"
52 | exit -1
53 | }
54 |
55 | seek $fileid 0 start
56 | set default_match 0
57 | while {[gets $fileid line] >= 0} {
58 | if {[string first "\[Command\]" $line] == 0} {
59 | set default_match 1
60 | continue
61 | }
62 | if {[string first "\[" $line] == 0} {
63 | set default_match 0
64 | }
65 | if {$default_match == 1} {
66 | if [regexp {([^=]*)=(.*)} $line match parameter value] {
67 | if [regexp {([ |\t]*;)} $parameter match] {continue}
68 | if [regexp {(.*)[ |\t]*;} $value match temp] {
69 | set Para($parameter) $temp
70 | } else {
71 | set Para($parameter) $value
72 | }
73 | }
74 | }
75 | }
76 | set default_match 0
77 | close $fileid
78 |
79 | return $Para(cmd_line)
80 | }
81 |
82 | set platformpath [GetPlatform]
83 | set Para(sbp_path) [file dirname [info script]]
84 | set Para(install_dir) $env(TOOLRTF)
85 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
86 |
87 | set scuba "$Para(FPGAPath)/scuba"
88 | set modulename "PLL200"
89 | set lang "vhdl"
90 | set lpcfile "$Para(sbp_path)/$modulename.lpc"
91 | set arch "xo2c00"
92 | set cmd_line [GetCmdLine $lpcfile]
93 | set fdcfile "$Para(sbp_path)/$modulename.fdc"
94 | if {[file exists $fdcfile] == 0} {
95 | append scuba " " $cmd_line
96 | } else {
97 | append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
98 | }
99 | set Para(result) [catch {eval exec "$scuba"} msg]
100 | #puts $msg
101 |
--------------------------------------------------------------------------------
/testrig/100mhz/generate_ngd.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | set platformpath [GetPlatform]
48 | set Para(sbp_path) [file dirname [info script]]
49 | set Para(install_dir) $env(TOOLRTF)
50 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
51 | set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
52 |
53 | set Para(ModuleName) "PLL200"
54 | set Para(Module) "PLL"
55 | set Para(libname) machxo2
56 | set Para(arch_name) xo2c00
57 | set Para(PartType) "LCMXO2-1200HC"
58 |
59 | set Para(tech_syn) machxo2
60 | set Para(tech_cae) machxo2
61 | set Para(Package) "QFN32"
62 | set Para(SpeedGrade) "5"
63 | set Para(FMax) "100"
64 | set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
65 |
66 | #create response file(*.cmd) for Synpwrap
67 | proc CreateCmdFile {} {
68 | global Para
69 |
70 | file mkdir "$Para(sbp_path)/syn_results"
71 | if [catch {open $Para(ModuleName).cmd w} rspFile] {
72 | puts "Cannot create response file $Para(ModuleName).cmd."
73 | exit -1
74 | } else {
75 | puts $rspFile "PROJECT: $Para(ModuleName)
76 | working_path: \"$Para(sbp_path)/syn_results\"
77 | module: $Para(ModuleName)
78 | verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\"
79 | vlog_std_v2001: true
80 | constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
81 | suffix_name: edn
82 | output_file_name: $Para(ModuleName)
83 | write_prf: true
84 | disable_io_insertion: true
85 | force_gsr: false
86 | frequency: $Para(FMax)
87 | fanout_limit: 50
88 | retiming: false
89 | pipe: false
90 | part: $Para(PartType)
91 | speed_grade: $Para(SpeedGrade)
92 | "
93 | close $rspFile
94 | }
95 | }
96 |
97 | #synpwrap
98 | CreateCmdFile
99 | set synpwrap "$Para(bin_dir)/synpwrap"
100 | if {[file exists $fdcfile] == 0} {
101 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
102 | } else {
103 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
104 | }
105 | #puts $msg
106 |
107 | #edif2ngd
108 | set edif2ngd "$Para(FPGAPath)/edif2ngd"
109 | set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
110 | #puts $msg
111 |
112 | #ngdbuild
113 | set ngdbuild "$Para(FPGAPath)/ngdbuild"
114 | set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
115 | #puts $msg
116 |
--------------------------------------------------------------------------------
/testrig/100mhz/msg_file.log:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.12.1.454
2 | Sat Sep 09 16:17:18 2023
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | BEGIN SCUBA Module Synthesis
11 |
12 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL200 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 200 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
13 | Circuit name : PLL200
14 | Module type : pll
15 | Module Version : 5.7
16 | Ports :
17 | Inputs : CLKI
18 | Outputs : CLKOP
19 | I/O buffer : not inserted
20 | EDIF output : PLL200.edn
21 | VHDL output : PLL200.vhd
22 | VHDL template : PLL200_tmpl.vhd
23 | VHDL purpose : for synthesis and simulation
24 | Bus notation : big endian
25 | Report output : PLL200.srp
26 | Estimated Resource Usage:
27 |
28 | END SCUBA Module Synthesis
29 |
30 |
--------------------------------------------------------------------------------
/testrig/100mhz/promote.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
--------------------------------------------------------------------------------
/testrig/100mhz/reportview.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
--------------------------------------------------------------------------------
/testrig/100mhz/source/Generate100MHz.vhd:
--------------------------------------------------------------------------------
1 | library ieee;
2 | library machxo2;
3 | use ieee.numeric_std.all;
4 | use ieee.std_logic_1164.all;
5 | use machxo2.all;
6 |
7 | entity Generate100MHz is
8 | port (
9 | CLK25 : in std_logic;
10 | D : out std_logic_vector(7 downto 0);
11 | CP : out std_logic_vector(3 downto 0)
12 | );
13 | end entity;
14 |
15 |
16 | architecture immediate of Generate100MHz is
17 |
18 | component PLL200 is
19 | port (
20 | CLKI: in std_logic;
21 | CLKOP: out std_logic);
22 | end component;
23 |
24 | signal CLK200: std_logic;
25 |
26 | begin
27 | pll : PLL200 PORT MAP ( CLKI => CLK25, CLKOP => CLK200 );
28 |
29 | process (CLK200)
30 | variable x:std_logic := '0';
31 | begin
32 | if falling_edge(CLK200) then
33 | x := not x;
34 | end if;
35 | CP <= CLK200 & "000";
36 | D <= "0000000" & x;
37 | end process;
38 |
39 | end immediate;
40 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/.run_manager.ini:
--------------------------------------------------------------------------------
1 | [Runmanager]
2 | Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xdc\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
3 | windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4 | headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
5 |
6 | [impl1%3CStrategy1%3E]
7 | isChecked=false
8 | isHidden=false
9 | isExpanded=false
10 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/.spread_sheet.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | COLUMN_POS_INFO_NAME_-1_0=Prioritize
3 | COLUMN_POS_INFO_NAME_-1_1=PIO Register
4 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/.spreadsheet_view.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | pin_sort_type=0
3 | pin_sort_ascending=true
4 | sig_sort_type=0
5 | sig_sort_ascending=true
6 | active_Sheet=Port Assignments
7 |
8 | [Port%20Assignments]
9 | Name="171,0"
10 | Group%20By="83,1"
11 | Pin="53,2"
12 | BANK="66,3"
13 | BANK_VCC="93,4"
14 | VREF="63,5"
15 | IO_TYPE="94,6"
16 | PULLMODE="94,7"
17 | DRIVE="70,8"
18 | SLEWRATE="93,9"
19 | CLAMP="74,10"
20 | OPENDRAIN="100,11"
21 | DIFFRESISTOR="114,12"
22 | DIFFDRIVE="95,13"
23 | HYSTERESIS="101,14"
24 | Outload%20%28pF%29="101,15"
25 | MaxSkew="86,16"
26 | Clock%20Load%20Only="118,17"
27 | SwitchingID="98,18"
28 | Ground%20plane%20PCB%20noise%20%28mV%29="185,19"
29 | Power%20plane%20PCB%20noise%20%28mV%29="182,20"
30 | SSO%20Allowance%28%25%29="134,21"
31 | sort_columns="Name,Ascending"
32 |
33 | [Pin%20Assignments]
34 | Pin="95,0"
35 | Pad%20Name="94,1"
36 | Dual%20Function="205,2"
37 | Polarity="77,3"
38 | BANK="0,4"
39 | BANK_VCC="93,5"
40 | IO_TYPE="83,6"
41 | Signal%20Name="98,7"
42 | Signal%20Type="95,8"
43 | sort_columns="Pin,Ascending"
44 |
45 | [Clock%20Resource]
46 | Clock%20Type="100,ELLIPSIS"
47 | Clock%20Name="100,ELLIPSIS"
48 | Selection="100,ELLIPSIS"
49 |
50 | [Global%20Preferences]
51 | Preference%20Name="288,ELLIPSIS"
52 | Preference%20Value="268,ELLIPSIS"
53 |
54 | [Cell%20Mapping]
55 | Type="100,ELLIPSIS"
56 | Name="100,ELLIPSIS"
57 | Din\Dout="100,ELLIPSIS"
58 | PIO%20Register="100,ELLIPSIS"
59 |
60 | [Route%20Priority]
61 | Type="100,ELLIPSIS"
62 | Name="100,ELLIPSIS"
63 | Prioritize="100,ELLIPSIS"
64 |
65 | [Timing%20Preferences]
66 | Preference%20Name="183,ELLIPSIS"
67 | Preference%20Value="128,ELLIPSIS"
68 | Preference%20Unit="121,ELLIPSIS"
69 |
70 | [Group]
71 | Group%20Type\Name="160,ELLIPSIS"
72 | Value="48,ELLIPSIS"
73 |
74 | [Misc%20Preferences]
75 | Preference%20Name="147,ELLIPSIS"
76 | Preference%20Value="128,ELLIPSIS"
77 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/Generate14_3Mhz.ccl:
--------------------------------------------------------------------------------
1 | VERSION=20110520
2 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/Generate14_3Mhz.ldf:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/Generate14_3Mhz.lpf:
--------------------------------------------------------------------------------
1 | BLOCK RESETPATHS ;
2 | BLOCK ASYNCPATHS ;
3 | LOCATE COMP "D[0]" SITE "13" ;
4 | LOCATE COMP "D[1]" SITE "12" ;
5 | LOCATE COMP "D[2]" SITE "11" ;
6 | LOCATE COMP "D[3]" SITE "10" ;
7 | LOCATE COMP "D[4]" SITE "9" ;
8 | LOCATE COMP "D[5]" SITE "8" ;
9 | LOCATE COMP "D[6]" SITE "5" ;
10 | LOCATE COMP "D[7]" SITE "4" ;
11 | LOCATE COMP "CP[0]" SITE "17" ;
12 | LOCATE COMP "CP[1]" SITE "16" ;
13 | LOCATE COMP "CP[2]" SITE "28" ;
14 | LOCATE COMP "CP[3]" SITE "27" ;
15 | SYSCONFIG MCCLK_FREQ=2.08 ;
16 | LOCATE COMP "CLK25" SITE "21" ;
17 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.jhd:
--------------------------------------------------------------------------------
1 | MODULE PLL28_6 DEFIN PLL28_6.vhd
2 | SUBMODULE EHXPLLJ
3 | INSTANCE PLLInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-5SG32C
5 | SpeedGrade=5
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=PLL
15 | CoreRevision=5.8
16 | ModuleName=PLL28_6
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=09/20/2023
20 | Time=11:46:52
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=None
28 | Order=None
29 | IO=0
30 | mode=Divider
31 | CLKI=25
32 | CLKI_DIV=2
33 | BW=1.146
34 | VCO=687.500
35 | fb_mode=CLKOP
36 | CLKFB_DIV=1
37 | FRACN_ENABLE=0
38 | FRACN_DIV=0
39 | DynamicPhase=STATIC
40 | ClkEnable=0
41 | Standby=0
42 | Enable_sel=0
43 | PLLRst=0
44 | PLLMRst=0
45 | ClkOS2Rst=0
46 | ClkOS3Rst=0
47 | LockSig=0
48 | LockStk=0
49 | WBProt=0
50 | OPBypass=0
51 | OPUseDiv=0
52 | CLKOP_DIV=55
53 | FREQ_PIN_CLKOP=100
54 | OP_Tol=0.0
55 | CLKOP_AFREQ=12.500000
56 | CLKOP_PHASEADJ=0
57 | CLKOP_TRIM_POL=Rising
58 | CLKOP_TRIM_DELAY=0
59 | EnCLKOS=1
60 | OSBypass=0
61 | OSUseDiv=0
62 | CLKOS_DIV=24
63 | FREQ_PIN_CLKOS=100
64 | OS_Tol=0.0
65 | CLKOS_AFREQ=28.645833
66 | CLKOS_PHASEADJ=0
67 | CLKOS_TRIM_POL=Rising
68 | CLKOS_TRIM_DELAY=0
69 | EnCLKOS2=0
70 | OS2Bypass=0
71 | OS2UseDiv=0
72 | CLKOS2_DIV=1
73 | FREQ_PIN_CLKOS2=100
74 | OS2_Tol=0.0
75 | CLKOS2_AFREQ=
76 | CLKOS2_PHASEADJ=0
77 | EnCLKOS3=0
78 | OS3Bypass=0
79 | OS3UseDiv=0
80 | CLKOS3_DIV=1
81 | FREQ_PIN_CLKOS3=100
82 | OS3_Tol=0.0
83 | CLKOS3_AFREQ=
84 | CLKOS3_PHASEADJ=0
85 |
86 | [Command]
87 | cmd_line= -w -n PLL28_6 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 24 -phase_cntl STATIC -fb_mode 1
88 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.naf:
--------------------------------------------------------------------------------
1 | CLKI i
2 | CLKOP o
3 | CLKOS o
4 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.sort:
--------------------------------------------------------------------------------
1 | PLL28_6.vhd
2 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.12.1.454
2 | Wed Sep 20 11:46:52 2023
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL28_6 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 24 -phase_cntl STATIC -fb_mode 1
11 | Circuit name : PLL28_6
12 | Module type : pll
13 | Module Version : 5.7
14 | Ports :
15 | Inputs : CLKI
16 | Outputs : CLKOP, CLKOS
17 | I/O buffer : not inserted
18 | EDIF output : PLL28_6.edn
19 | VHDL output : PLL28_6.vhd
20 | VHDL template : PLL28_6_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : PLL28_6.srp
24 | Element Usage :
25 | EHXPLLJ : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/testrig/14_3mhz/PLL28_6.sym
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.12.1.454
6 | Wed Sep 20 11:46:52 2023
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL28_6 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 24 -phase_cntl STATIC -fb_mode 1
17 | Circuit name : PLL28_6
18 | Module type : pll
19 | Module Version : 5.7
20 | Ports :
21 | Inputs : CLKI
22 | Outputs : CLKOP, CLKOS
23 | I/O buffer : not inserted
24 | EDIF output : PLL28_6.edn
25 | VHDL output : PLL28_6.vhd
26 | VHDL template : PLL28_6_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : PLL28_6.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: PLL28_6.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/PLL28_6_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.12.1.454
2 | -- Module Version: 5.7
3 | -- Wed Sep 20 11:46:52 2023
4 |
5 | -- parameterized module component declaration
6 | component PLL28_6
7 | port (CLKI: in std_logic; CLKOP: out std_logic;
8 | CLKOS: out std_logic);
9 | end component;
10 |
11 | -- parameterized module component instance
12 | __ : PLL28_6
13 | port map (CLKI=>__, CLKOP=>__, CLKOS=>__);
14 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/generate_core.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | proc GetCmdLine {lpcfile} {
48 | global Para
49 |
50 | if [catch {open $lpcfile r} fileid] {
51 | puts "Cannot open $para_file file!"
52 | exit -1
53 | }
54 |
55 | seek $fileid 0 start
56 | set default_match 0
57 | while {[gets $fileid line] >= 0} {
58 | if {[string first "\[Command\]" $line] == 0} {
59 | set default_match 1
60 | continue
61 | }
62 | if {[string first "\[" $line] == 0} {
63 | set default_match 0
64 | }
65 | if {$default_match == 1} {
66 | if [regexp {([^=]*)=(.*)} $line match parameter value] {
67 | if [regexp {([ |\t]*;)} $parameter match] {continue}
68 | if [regexp {(.*)[ |\t]*;} $value match temp] {
69 | set Para($parameter) $temp
70 | } else {
71 | set Para($parameter) $value
72 | }
73 | }
74 | }
75 | }
76 | set default_match 0
77 | close $fileid
78 |
79 | return $Para(cmd_line)
80 | }
81 |
82 | set platformpath [GetPlatform]
83 | set Para(sbp_path) [file dirname [info script]]
84 | set Para(install_dir) $env(TOOLRTF)
85 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
86 |
87 | set scuba "$Para(FPGAPath)/scuba"
88 | set modulename "PLL28_6"
89 | set lang "vhdl"
90 | set lpcfile "$Para(sbp_path)/$modulename.lpc"
91 | set arch "xo2c00"
92 | set cmd_line [GetCmdLine $lpcfile]
93 | set fdcfile "$Para(sbp_path)/$modulename.fdc"
94 | if {[file exists $fdcfile] == 0} {
95 | append scuba " " $cmd_line
96 | } else {
97 | append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
98 | }
99 | set Para(result) [catch {eval exec "$scuba"} msg]
100 | #puts $msg
101 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/generate_ngd.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | set platformpath [GetPlatform]
48 | set Para(sbp_path) [file dirname [info script]]
49 | set Para(install_dir) $env(TOOLRTF)
50 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
51 | set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
52 |
53 | set Para(ModuleName) "PLL28_6"
54 | set Para(Module) "PLL"
55 | set Para(libname) machxo2
56 | set Para(arch_name) xo2c00
57 | set Para(PartType) "LCMXO2-1200HC"
58 |
59 | set Para(tech_syn) machxo2
60 | set Para(tech_cae) machxo2
61 | set Para(Package) "QFN32"
62 | set Para(SpeedGrade) "5"
63 | set Para(FMax) "100"
64 | set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
65 |
66 | #create response file(*.cmd) for Synpwrap
67 | proc CreateCmdFile {} {
68 | global Para
69 |
70 | file mkdir "$Para(sbp_path)/syn_results"
71 | if [catch {open $Para(ModuleName).cmd w} rspFile] {
72 | puts "Cannot create response file $Para(ModuleName).cmd."
73 | exit -1
74 | } else {
75 | puts $rspFile "PROJECT: $Para(ModuleName)
76 | working_path: \"$Para(sbp_path)/syn_results\"
77 | module: $Para(ModuleName)
78 | verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\"
79 | vlog_std_v2001: true
80 | constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
81 | suffix_name: edn
82 | output_file_name: $Para(ModuleName)
83 | write_prf: true
84 | disable_io_insertion: true
85 | force_gsr: false
86 | frequency: $Para(FMax)
87 | fanout_limit: 50
88 | retiming: false
89 | pipe: false
90 | part: $Para(PartType)
91 | speed_grade: $Para(SpeedGrade)
92 | "
93 | close $rspFile
94 | }
95 | }
96 |
97 | #synpwrap
98 | CreateCmdFile
99 | set synpwrap "$Para(bin_dir)/synpwrap"
100 | if {[file exists $fdcfile] == 0} {
101 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
102 | } else {
103 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
104 | }
105 | #puts $msg
106 |
107 | #edif2ngd
108 | set edif2ngd "$Para(FPGAPath)/edif2ngd"
109 | set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
110 | #puts $msg
111 |
112 | #ngdbuild
113 | set ngdbuild "$Para(FPGAPath)/ngdbuild"
114 | set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
115 | #puts $msg
116 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/msg_file.log:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.12.1.454
2 | Wed Sep 20 11:46:52 2023
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | BEGIN SCUBA Module Synthesis
11 |
12 | Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL28_6 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 55 -trims 0 -phases 0 -trims_r -bdiv 24 -phase_cntl STATIC -fb_mode 1
13 | Circuit name : PLL28_6
14 | Module type : pll
15 | Module Version : 5.7
16 | Ports :
17 | Inputs : CLKI
18 | Outputs : CLKOP, CLKOS
19 | I/O buffer : not inserted
20 | EDIF output : PLL28_6.edn
21 | VHDL output : PLL28_6.vhd
22 | VHDL template : PLL28_6_tmpl.vhd
23 | VHDL purpose : for synthesis and simulation
24 | Bus notation : big endian
25 | Report output : PLL28_6.srp
26 | Estimated Resource Usage:
27 |
28 | END SCUBA Module Synthesis
29 |
30 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/promote.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/reportview.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
--------------------------------------------------------------------------------
/testrig/14_3mhz/source/Generate14_3MHz.vhd:
--------------------------------------------------------------------------------
1 | library ieee;
2 | library machxo2;
3 | use ieee.numeric_std.all;
4 | use ieee.std_logic_1164.all;
5 | use machxo2.all;
6 |
7 | entity Generate14_3MHz is
8 | port (
9 | CLK25 : in std_logic;
10 | D : out std_logic_vector(7 downto 0);
11 | CP : out std_logic_vector(3 downto 0)
12 | );
13 | end entity;
14 |
15 |
16 | architecture immediate of Generate14_3MHz is
17 |
18 | component PLL28_6 is
19 | port (
20 | CLKI: in std_logic;
21 | CLKOS: out std_logic;
22 | CLKOP: out std_logic
23 | );
24 | end component;
25 |
26 | signal CLK28_6: std_logic;
27 |
28 | begin
29 | pll : PLL28_6 PORT MAP ( CLKI => CLK25, CLKOP => open, CLKOS => CLK28_6 );
30 |
31 | process (CLK28_6)
32 | variable x:std_logic := '0';
33 | begin
34 | if falling_edge(CLK28_6) then
35 | x := not x;
36 | end if;
37 | CP <= "000" & CLK28_6;
38 | D <= "000000" & x & (not x);
39 | end process;
40 |
41 | end immediate;
42 |
--------------------------------------------------------------------------------
/testrig/amigaboost/.run_manager.ini:
--------------------------------------------------------------------------------
1 | [Runmanager]
2 | Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x2\x7f\0\0\x1\xdf\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
3 | windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4 | headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
5 |
6 | [impl1%3CStrategy1%3E]
7 | isChecked=false
8 | isHidden=false
9 | isExpanded=false
10 |
--------------------------------------------------------------------------------
/testrig/amigaboost/.spread_sheet.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | COLUMN_POS_INFO_NAME_-1_0=Prioritize
3 | COLUMN_POS_INFO_NAME_-1_1=PIO Register
4 |
--------------------------------------------------------------------------------
/testrig/amigaboost/.spreadsheet_view.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | pin_sort_type=0
3 | pin_sort_ascending=true
4 | sig_sort_type=0
5 | sig_sort_ascending=true
6 | active_Sheet=Port Assignments
7 |
8 | [Port%20Assignments]
9 | Name="171,0"
10 | Group%20By="83,1"
11 | Pin="55,2"
12 | BANK="66,3"
13 | BANK_VCC="93,4"
14 | VREF="63,5"
15 | IO_TYPE="185,6"
16 | PULLMODE="127,7"
17 | DRIVE="70,8"
18 | SLEWRATE="121,9"
19 | CLAMP="89,10"
20 | OPENDRAIN="100,11"
21 | DIFFRESISTOR="114,12"
22 | DIFFDRIVE="95,13"
23 | HYSTERESIS="125,14"
24 | Outload%20%28pF%29="101,15"
25 | MaxSkew="86,16"
26 | Clock%20Load%20Only="118,17"
27 | SwitchingID="98,18"
28 | Ground%20plane%20PCB%20noise%20%28mV%29="185,19"
29 | Power%20plane%20PCB%20noise%20%28mV%29="182,20"
30 | SSO%20Allowance%28%25%29="134,21"
31 | sort_columns="Name,Ascending"
32 |
33 | [Pin%20Assignments]
34 | Pin="95,0"
35 | Pad%20Name="94,1"
36 | Dual%20Function="205,2"
37 | Polarity="77,3"
38 | BANK="0,4"
39 | BANK_VCC="93,5"
40 | IO_TYPE="185,6"
41 | Signal%20Name="101,7"
42 | Signal%20Type="135,8"
43 | sort_columns="Pin,Ascending"
44 |
45 | [Clock%20Resource]
46 | Clock%20Type="100,ELLIPSIS"
47 | Clock%20Name="100,ELLIPSIS"
48 | Selection="100,ELLIPSIS"
49 |
50 | [Global%20Preferences]
51 | Preference%20Name="288,ELLIPSIS"
52 | Preference%20Value="268,ELLIPSIS"
53 |
54 | [Cell%20Mapping]
55 | Type="100,ELLIPSIS"
56 | Name="100,ELLIPSIS"
57 | Din\Dout="100,ELLIPSIS"
58 | PIO%20Register="100,ELLIPSIS"
59 |
60 | [Route%20Priority]
61 | Type="100,ELLIPSIS"
62 | Name="100,ELLIPSIS"
63 | Prioritize="100,ELLIPSIS"
64 |
65 | [Timing%20Preferences]
66 | Preference%20Name="183,ELLIPSIS"
67 | Preference%20Value="128,ELLIPSIS"
68 | Preference%20Unit="121,ELLIPSIS"
69 |
70 | [Group]
71 | Group%20Type\Name="160,ELLIPSIS"
72 | Value="48,ELLIPSIS"
73 |
74 | [Misc%20Preferences]
75 | Preference%20Name="147,ELLIPSIS"
76 | Preference%20Value="128,ELLIPSIS"
77 |
--------------------------------------------------------------------------------
/testrig/amigaboost/AmigaBoost.ccl:
--------------------------------------------------------------------------------
1 | VERSION=20110520
2 |
--------------------------------------------------------------------------------
/testrig/amigaboost/AmigaBoost.ldf:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
--------------------------------------------------------------------------------
/testrig/amigaboost/AmigaBoost.lpf:
--------------------------------------------------------------------------------
1 | BLOCK RESETPATHS ;
2 | BLOCK ASYNCPATHS ;
3 | LOCATE COMP "CLK" SITE "21" ;
4 | LOCATE COMP "CP[0]" SITE "17" ;
5 | LOCATE COMP "CP[1]" SITE "16" ;
6 | LOCATE COMP "CP[2]" SITE "28" ;
7 | LOCATE COMP "CP[3]" SITE "27" ;
8 | LOCATE COMP "D[0]" SITE "13" ;
9 | LOCATE COMP "D[1]" SITE "12" ;
10 | LOCATE COMP "D[2]" SITE "11" ;
11 | LOCATE COMP "D[3]" SITE "10" ;
12 | LOCATE COMP "D[4]" SITE "9" ;
13 | LOCATE COMP "D[5]" SITE "8" ;
14 | LOCATE COMP "D[6]" SITE "5" ;
15 | LOCATE COMP "D[7]" SITE "4" ;
16 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.jhd:
--------------------------------------------------------------------------------
1 | MODULE PLL_56_81 DEFIN PLL_56_81.vhd
2 | SUBMODULE EHXPLLJ
3 | INSTANCE PLLInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-4SG32C
5 | SpeedGrade=4
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=PLL
15 | CoreRevision=5.8
16 | ModuleName=PLL_56_81
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=11/09/2024
20 | Time=17:08:41
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=None
28 | Order=None
29 | IO=0
30 | mode=Divider
31 | CLKI=25
32 | CLKI_DIV=2
33 | BW=1.146
34 | VCO=625.000
35 | fb_mode=CLKOP
36 | CLKFB_DIV=1
37 | FRACN_ENABLE=0
38 | FRACN_DIV=0
39 | DynamicPhase=STATIC
40 | ClkEnable=0
41 | Standby=0
42 | Enable_sel=0
43 | PLLRst=0
44 | PLLMRst=0
45 | ClkOS2Rst=0
46 | ClkOS3Rst=0
47 | LockSig=0
48 | LockStk=0
49 | WBProt=0
50 | OPBypass=0
51 | OPUseDiv=0
52 | CLKOP_DIV=50
53 | FREQ_PIN_CLKOP=100
54 | OP_Tol=0.0
55 | CLKOP_AFREQ=12.500000
56 | CLKOP_PHASEADJ=0
57 | CLKOP_TRIM_POL=Rising
58 | CLKOP_TRIM_DELAY=0
59 | EnCLKOS=1
60 | OSBypass=0
61 | OSUseDiv=0
62 | CLKOS_DIV=11
63 | FREQ_PIN_CLKOS=100
64 | OS_Tol=0.0
65 | CLKOS_AFREQ=56.818182
66 | CLKOS_PHASEADJ=0
67 | CLKOS_TRIM_POL=Rising
68 | CLKOS_TRIM_DELAY=0
69 | EnCLKOS2=0
70 | OS2Bypass=0
71 | OS2UseDiv=0
72 | CLKOS2_DIV=1
73 | FREQ_PIN_CLKOS2=100
74 | OS2_Tol=0.0
75 | CLKOS2_AFREQ=
76 | CLKOS2_PHASEADJ=0
77 | EnCLKOS3=0
78 | OS3Bypass=0
79 | OS3UseDiv=0
80 | CLKOS3_DIV=1
81 | FREQ_PIN_CLKOS3=100
82 | OS3_Tol=0.0
83 | CLKOS3_AFREQ=
84 | CLKOS3_PHASEADJ=0
85 |
86 | [Command]
87 | cmd_line= -w -n PLL_56_81 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 50 -trims 0 -phases 0 -trims_r -bdiv 11 -phase_cntl STATIC -fb_mode 1
88 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.naf:
--------------------------------------------------------------------------------
1 | CLKI i
2 | CLKOP o
3 | CLKOS o
4 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.sort:
--------------------------------------------------------------------------------
1 | PLL_56_81.vhd
2 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Sat Nov 09 17:08:41 2024
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_56_81 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 50 -trims 0 -phases 0 -trims_r -bdiv 11 -phase_cntl STATIC -fb_mode 1
11 | Circuit name : PLL_56_81
12 | Module type : pll
13 | Module Version : 5.7
14 | Ports :
15 | Inputs : CLKI
16 | Outputs : CLKOP, CLKOS
17 | I/O buffer : not inserted
18 | EDIF output : PLL_56_81.edn
19 | VHDL output : PLL_56_81.vhd
20 | VHDL template : PLL_56_81_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : PLL_56_81.srp
24 | Element Usage :
25 | EHXPLLJ : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/testrig/amigaboost/PLL_56_81.sym
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
6 | Sat Nov 09 17:08:41 2024
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_56_81 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 50 -trims 0 -phases 0 -trims_r -bdiv 11 -phase_cntl STATIC -fb_mode 1
17 | Circuit name : PLL_56_81
18 | Module type : pll
19 | Module Version : 5.7
20 | Ports :
21 | Inputs : CLKI
22 | Outputs : CLKOP, CLKOS
23 | I/O buffer : not inserted
24 | EDIF output : PLL_56_81.edn
25 | VHDL output : PLL_56_81.vhd
26 | VHDL template : PLL_56_81_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : PLL_56_81.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: PLL_56_81.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_81_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | -- Module Version: 5.7
3 | -- Sat Nov 09 17:08:41 2024
4 |
5 | -- parameterized module component declaration
6 | component PLL_56_81
7 | port (CLKI: in std_logic; CLKOP: out std_logic;
8 | CLKOS: out std_logic);
9 | end component;
10 |
11 | -- parameterized module component instance
12 | __ : PLL_56_81
13 | port map (CLKI=>__, CLKOP=>__, CLKOS=>__);
14 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.ipx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.jhd:
--------------------------------------------------------------------------------
1 | MODULE PLL_56_94 DEFIN PLL_56_94.vhd
2 | SUBMODULE EHXPLLJ
3 | INSTANCE PLLInst_0
4 | SUBMODULE VLO
5 | INSTANCE scuba_vlo_inst
6 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.lpc:
--------------------------------------------------------------------------------
1 | [Device]
2 | Family=machxo2
3 | PartType=LCMXO2-1200HC
4 | PartName=LCMXO2-1200HC-4SG32C
5 | SpeedGrade=4
6 | Package=QFN32
7 | OperatingCondition=COM
8 | Status=S
9 |
10 | [IP]
11 | VendorName=Lattice Semiconductor Corporation
12 | CoreType=LPM
13 | CoreStatus=Demo
14 | CoreName=PLL
15 | CoreRevision=5.8
16 | ModuleName=PLL_56_94
17 | SourceFormat=VHDL
18 | ParameterFileVersion=1.0
19 | Date=11/09/2024
20 | Time=19:25:26
21 |
22 | [Parameters]
23 | Verilog=0
24 | VHDL=1
25 | EDIF=1
26 | Destination=Synplicity
27 | Expression=None
28 | Order=None
29 | IO=0
30 | mode=Divider
31 | CLKI=25
32 | CLKI_DIV=2
33 | BW=1.198
34 | VCO=512.500
35 | fb_mode=CLKOP
36 | CLKFB_DIV=1
37 | FRACN_ENABLE=0
38 | FRACN_DIV=0
39 | DynamicPhase=STATIC
40 | ClkEnable=0
41 | Standby=0
42 | Enable_sel=0
43 | PLLRst=0
44 | PLLMRst=0
45 | ClkOS2Rst=0
46 | ClkOS3Rst=0
47 | LockSig=0
48 | LockStk=0
49 | WBProt=0
50 | OPBypass=0
51 | OPUseDiv=0
52 | CLKOP_DIV=41
53 | FREQ_PIN_CLKOP=100
54 | OP_Tol=0.0
55 | CLKOP_AFREQ=12.500000
56 | CLKOP_PHASEADJ=0
57 | CLKOP_TRIM_POL=Rising
58 | CLKOP_TRIM_DELAY=0
59 | EnCLKOS=1
60 | OSBypass=0
61 | OSUseDiv=0
62 | CLKOS_DIV=9
63 | FREQ_PIN_CLKOS=100
64 | OS_Tol=0.0
65 | CLKOS_AFREQ=56.944444
66 | CLKOS_PHASEADJ=0
67 | CLKOS_TRIM_POL=Rising
68 | CLKOS_TRIM_DELAY=0
69 | EnCLKOS2=0
70 | OS2Bypass=0
71 | OS2UseDiv=0
72 | CLKOS2_DIV=1
73 | FREQ_PIN_CLKOS2=100
74 | OS2_Tol=0.0
75 | CLKOS2_AFREQ=
76 | CLKOS2_PHASEADJ=0
77 | EnCLKOS3=0
78 | OS3Bypass=0
79 | OS3UseDiv=0
80 | CLKOS3_DIV=1
81 | FREQ_PIN_CLKOS3=100
82 | OS3_Tol=0.0
83 | CLKOS3_AFREQ=
84 | CLKOS3_PHASEADJ=0
85 |
86 | [Command]
87 | cmd_line= -w -n PLL_56_94 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 41 -trims 0 -phases 0 -trims_r -bdiv 9 -phase_cntl STATIC -fb_mode 1
88 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.naf:
--------------------------------------------------------------------------------
1 | CLKI i
2 | CLKOP o
3 | CLKOS o
4 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.sort:
--------------------------------------------------------------------------------
1 | PLL_56_94.vhd
2 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.srp:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Sat Nov 09 19:25:26 2024
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_56_94 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 41 -trims 0 -phases 0 -trims_r -bdiv 9 -phase_cntl STATIC -fb_mode 1
11 | Circuit name : PLL_56_94
12 | Module type : pll
13 | Module Version : 5.7
14 | Ports :
15 | Inputs : CLKI
16 | Outputs : CLKOP, CLKOS
17 | I/O buffer : not inserted
18 | EDIF output : PLL_56_94.edn
19 | VHDL output : PLL_56_94.vhd
20 | VHDL template : PLL_56_94_tmpl.vhd
21 | VHDL purpose : for synthesis and simulation
22 | Bus notation : big endian
23 | Report output : PLL_56_94.srp
24 | Element Usage :
25 | EHXPLLJ : 1
26 | Estimated Resource Usage:
27 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94.sym:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/testrig/amigaboost/PLL_56_94.sym
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94_generate.log:
--------------------------------------------------------------------------------
1 | Starting process: Module
2 |
3 | Starting process:
4 |
5 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
6 | Sat Nov 09 19:25:26 2024
7 |
8 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
9 | Copyright (c) 1995 AT&T Corp. All rights reserved.
10 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
11 | Copyright (c) 2001 Agere Systems All rights reserved.
12 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
13 |
14 | BEGIN SCUBA Module Synthesis
15 |
16 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_56_94 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 41 -trims 0 -phases 0 -trims_r -bdiv 9 -phase_cntl STATIC -fb_mode 1
17 | Circuit name : PLL_56_94
18 | Module type : pll
19 | Module Version : 5.7
20 | Ports :
21 | Inputs : CLKI
22 | Outputs : CLKOP, CLKOS
23 | I/O buffer : not inserted
24 | EDIF output : PLL_56_94.edn
25 | VHDL output : PLL_56_94.vhd
26 | VHDL template : PLL_56_94_tmpl.vhd
27 | VHDL purpose : for synthesis and simulation
28 | Bus notation : big endian
29 | Report output : PLL_56_94.srp
30 | Estimated Resource Usage:
31 |
32 | END SCUBA Module Synthesis
33 |
34 | File: PLL_56_94.lpc created.
35 |
36 |
37 | End process: completed successfully.
38 |
39 |
40 | Total Warnings: 0
41 |
42 | Total Errors: 0
43 |
44 |
45 |
--------------------------------------------------------------------------------
/testrig/amigaboost/PLL_56_94_tmpl.vhd:
--------------------------------------------------------------------------------
1 | -- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.13.0.56.2
2 | -- Module Version: 5.7
3 | -- Sat Nov 09 19:25:26 2024
4 |
5 | -- parameterized module component declaration
6 | component PLL_56_94
7 | port (CLKI: in std_logic; CLKOP: out std_logic;
8 | CLKOS: out std_logic);
9 | end component;
10 |
11 | -- parameterized module component instance
12 | __ : PLL_56_94
13 | port map (CLKI=>__, CLKOP=>__, CLKOS=>__);
14 |
--------------------------------------------------------------------------------
/testrig/amigaboost/generate_core.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | proc GetCmdLine {lpcfile} {
48 | global Para
49 |
50 | if [catch {open $lpcfile r} fileid] {
51 | puts "Cannot open $para_file file!"
52 | exit -1
53 | }
54 |
55 | seek $fileid 0 start
56 | set default_match 0
57 | while {[gets $fileid line] >= 0} {
58 | if {[string first "\[Command\]" $line] == 0} {
59 | set default_match 1
60 | continue
61 | }
62 | if {[string first "\[" $line] == 0} {
63 | set default_match 0
64 | }
65 | if {$default_match == 1} {
66 | if [regexp {([^=]*)=(.*)} $line match parameter value] {
67 | if [regexp {([ |\t]*;)} $parameter match] {continue}
68 | if [regexp {(.*)[ |\t]*;} $value match temp] {
69 | set Para($parameter) $temp
70 | } else {
71 | set Para($parameter) $value
72 | }
73 | }
74 | }
75 | }
76 | set default_match 0
77 | close $fileid
78 |
79 | return $Para(cmd_line)
80 | }
81 |
82 | set platformpath [GetPlatform]
83 | set Para(sbp_path) [file dirname [info script]]
84 | set Para(install_dir) $env(TOOLRTF)
85 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
86 |
87 | set scuba "$Para(FPGAPath)/scuba"
88 | set modulename "PLL_56_94"
89 | set lang "vhdl"
90 | set lpcfile "$Para(sbp_path)/$modulename.lpc"
91 | set arch "xo2c00"
92 | set cmd_line [GetCmdLine $lpcfile]
93 | set fdcfile "$Para(sbp_path)/$modulename.fdc"
94 | if {[file exists $fdcfile] == 0} {
95 | append scuba " " $cmd_line
96 | } else {
97 | append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
98 | }
99 | set Para(result) [catch {eval exec "$scuba"} msg]
100 | #puts $msg
101 |
--------------------------------------------------------------------------------
/testrig/amigaboost/generate_ngd.tcl:
--------------------------------------------------------------------------------
1 | #!/usr/local/bin/wish
2 |
3 | proc GetPlatform {} {
4 | global tcl_platform
5 |
6 | set cpu $tcl_platform(machine)
7 |
8 | switch $cpu {
9 | intel -
10 | i*86* {
11 | set cpu ix86
12 | }
13 | x86_64 {
14 | if {$tcl_platform(wordSize) == 4} {
15 | set cpu ix86
16 | }
17 | }
18 | }
19 |
20 | switch $tcl_platform(platform) {
21 | windows {
22 | if {$cpu == "amd64"} {
23 | # Do not check wordSize, win32-x64 is an IL32P64 platform.
24 | set cpu x86_64
25 | }
26 | if {$cpu == "x86_64"} {
27 | return "nt64"
28 | } else {
29 | return "nt"
30 | }
31 | }
32 | unix {
33 | if {$tcl_platform(os) == "Linux"} {
34 | if {$cpu == "x86_64"} {
35 | return "lin64"
36 | } else {
37 | return "lin"
38 | }
39 | } else {
40 | return "sol"
41 | }
42 | }
43 | }
44 | return "nt"
45 | }
46 |
47 | set platformpath [GetPlatform]
48 | set Para(sbp_path) [file dirname [info script]]
49 | set Para(install_dir) $env(TOOLRTF)
50 | set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
51 | set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
52 |
53 | set Para(ModuleName) "PLL_56_94"
54 | set Para(Module) "PLL"
55 | set Para(libname) machxo2
56 | set Para(arch_name) xo2c00
57 | set Para(PartType) "LCMXO2-1200HC"
58 |
59 | set Para(tech_syn) machxo2
60 | set Para(tech_cae) machxo2
61 | set Para(Package) "QFN32"
62 | set Para(SpeedGrade) "4"
63 | set Para(FMax) "100"
64 | set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
65 |
66 | #create response file(*.cmd) for Synpwrap
67 | proc CreateCmdFile {} {
68 | global Para
69 |
70 | file mkdir "$Para(sbp_path)/syn_results"
71 | if [catch {open $Para(ModuleName).cmd w} rspFile] {
72 | puts "Cannot create response file $Para(ModuleName).cmd."
73 | exit -1
74 | } else {
75 | puts $rspFile "PROJECT: $Para(ModuleName)
76 | working_path: \"$Para(sbp_path)/syn_results\"
77 | module: $Para(ModuleName)
78 | verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\"
79 | vlog_std_v2001: true
80 | constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
81 | suffix_name: edn
82 | output_file_name: $Para(ModuleName)
83 | write_prf: true
84 | disable_io_insertion: true
85 | force_gsr: false
86 | frequency: $Para(FMax)
87 | fanout_limit: 50
88 | retiming: false
89 | pipe: false
90 | part: $Para(PartType)
91 | speed_grade: $Para(SpeedGrade)
92 | "
93 | close $rspFile
94 | }
95 | }
96 |
97 | #synpwrap
98 | CreateCmdFile
99 | set synpwrap "$Para(bin_dir)/synpwrap"
100 | if {[file exists $fdcfile] == 0} {
101 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
102 | } else {
103 | set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
104 | }
105 | #puts $msg
106 |
107 | #edif2ngd
108 | set edif2ngd "$Para(FPGAPath)/edif2ngd"
109 | set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
110 | #puts $msg
111 |
112 | #ngdbuild
113 | set ngdbuild "$Para(FPGAPath)/ngdbuild"
114 | set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
115 | #puts $msg
116 |
--------------------------------------------------------------------------------
/testrig/amigaboost/msg_file.log:
--------------------------------------------------------------------------------
1 | SCUBA, Version Diamond (64-bit) 3.13.0.56.2
2 | Sat Nov 09 19:25:26 2024
3 |
4 | Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
5 | Copyright (c) 1995 AT&T Corp. All rights reserved.
6 | Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
7 | Copyright (c) 2001 Agere Systems All rights reserved.
8 | Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
9 |
10 | BEGIN SCUBA Module Synthesis
11 |
12 | Issued command : C:\lscc\diamond\3.13\ispfpga\bin\nt64\scuba.exe -w -n PLL_56_94 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -mdiv 2 -ndiv 1 -trimp 0 -phasep 0 -trimp_r -adiv 41 -trims 0 -phases 0 -trims_r -bdiv 9 -phase_cntl STATIC -fb_mode 1
13 | Circuit name : PLL_56_94
14 | Module type : pll
15 | Module Version : 5.7
16 | Ports :
17 | Inputs : CLKI
18 | Outputs : CLKOP, CLKOS
19 | I/O buffer : not inserted
20 | EDIF output : PLL_56_94.edn
21 | VHDL output : PLL_56_94.vhd
22 | VHDL template : PLL_56_94_tmpl.vhd
23 | VHDL purpose : for synthesis and simulation
24 | Bus notation : big endian
25 | Report output : PLL_56_94.srp
26 | Estimated Resource Usage:
27 |
28 | END SCUBA Module Synthesis
29 |
30 |
--------------------------------------------------------------------------------
/testrig/amigaboost/promote.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
--------------------------------------------------------------------------------
/testrig/amigaboost/reportview.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
--------------------------------------------------------------------------------
/testrig/amigaboost/source/AmigaBoost.vhd:
--------------------------------------------------------------------------------
1 | library ieee;
2 | library machxo2;
3 | use ieee.numeric_std.all;
4 | use ieee.std_logic_1164.all;
5 | use machxo2.all;
6 |
7 | entity AmigaBoost is
8 | port (
9 | CLK : in std_logic;
10 | D : out std_logic_vector(7 downto 0);
11 | CP : out std_logic_vector(3 downto 0)
12 | );
13 | end entity;
14 |
15 |
16 | architecture immediate of AmigaBoost is
17 |
18 | component PLL_56_94 is
19 | port (
20 | CLKI: in std_logic;
21 | CLKOS: out std_logic;
22 | CLKOP: out std_logic
23 | );
24 | end component;
25 |
26 | signal CLK_56: std_logic;
27 |
28 | begin
29 | pll : PLL_56_94 PORT MAP ( CLKI => CLK, CLKOP => open, CLKOS => CLK_56 );
30 |
31 | process (CLK_56)
32 | variable x:std_logic := '0';
33 | begin
34 | if falling_edge(CLK_56) then
35 | x := not x;
36 | end if;
37 | CP <= CLK_56 & "000";
38 | D <= "0000000" & x;
39 | end process;
40 |
41 | end immediate;
42 |
--------------------------------------------------------------------------------
/testrig/board/Library.bak:
--------------------------------------------------------------------------------
1 | (kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
2 | (symbol "74LVC04" (in_bom yes) (on_board yes)
3 | (property "Reference" "U" (id 0) (at 6.35 0 0)
4 | (effects (font (size 1.27 1.27)))
5 | )
6 | (property "Value" "74LVC04" (id 1) (at 0 0 0)
7 | (effects (font (size 1.27 1.27)))
8 | )
9 | (property "Footprint" "" (id 2) (at 0 0 0)
10 | (effects (font (size 1.27 1.27)) hide)
11 | )
12 | (property "Datasheet" "" (id 3) (at 0 0 0)
13 | (effects (font (size 1.27 1.27)) hide)
14 | )
15 | (symbol "74LVC04_0_1"
16 | (rectangle (start -8.89 5.08) (end 8.89 -5.08)
17 | (stroke (width 0) (type default) (color 0 0 0 0))
18 | (fill (type none))
19 | )
20 | )
21 | (symbol "74LVC04_1_1"
22 | (pin input line (at -7.62 -7.62 90) (length 2.54)
23 | (name "I1" (effects (font (size 1.27 1.27))))
24 | (number "1" (effects (font (size 1.27 1.27))))
25 | )
26 | (pin output line (at 2.54 7.62 270) (length 2.54)
27 | (name "O5" (effects (font (size 1.27 1.27))))
28 | (number "10" (effects (font (size 1.27 1.27))))
29 | )
30 | (pin input line (at 0 7.62 270) (length 2.54)
31 | (name "I5" (effects (font (size 1.27 1.27))))
32 | (number "11" (effects (font (size 1.27 1.27))))
33 | )
34 | (pin output line (at -2.54 7.62 270) (length 2.54)
35 | (name "O4" (effects (font (size 1.27 1.27))))
36 | (number "12" (effects (font (size 1.27 1.27))))
37 | )
38 | (pin input line (at -5.08 7.62 270) (length 2.54)
39 | (name "I4" (effects (font (size 1.27 1.27))))
40 | (number "13" (effects (font (size 1.27 1.27))))
41 | )
42 | (pin power_in line (at -7.62 7.62 270) (length 2.54)
43 | (name "VCC" (effects (font (size 1.27 1.27))))
44 | (number "14" (effects (font (size 1.27 1.27))))
45 | )
46 | (pin output line (at -5.08 -7.62 90) (length 2.54)
47 | (name "O1" (effects (font (size 1.27 1.27))))
48 | (number "2" (effects (font (size 1.27 1.27))))
49 | )
50 | (pin input line (at -2.54 -7.62 90) (length 2.54)
51 | (name "I2" (effects (font (size 1.27 1.27))))
52 | (number "3" (effects (font (size 1.27 1.27))))
53 | )
54 | (pin output line (at 0 -7.62 90) (length 2.54)
55 | (name "O2" (effects (font (size 1.27 1.27))))
56 | (number "4" (effects (font (size 1.27 1.27))))
57 | )
58 | (pin input line (at 2.54 -7.62 90) (length 2.54)
59 | (name "I3" (effects (font (size 1.27 1.27))))
60 | (number "5" (effects (font (size 1.27 1.27))))
61 | )
62 | (pin output line (at 5.08 -7.62 90) (length 2.54)
63 | (name "O3" (effects (font (size 1.27 1.27))))
64 | (number "6" (effects (font (size 1.27 1.27))))
65 | )
66 | (pin power_in line (at 7.62 -7.62 90) (length 2.54)
67 | (name "GND" (effects (font (size 1.27 1.27))))
68 | (number "7" (effects (font (size 1.27 1.27))))
69 | )
70 | (pin output line (at 7.62 7.62 270) (length 2.54)
71 | (name "O6" (effects (font (size 1.27 1.27))))
72 | (number "8" (effects (font (size 1.27 1.27))))
73 | )
74 | (pin input line (at 5.08 7.62 270) (length 2.54)
75 | (name "I6" (effects (font (size 1.27 1.27))))
76 | (number "9" (effects (font (size 1.27 1.27))))
77 | )
78 | )
79 | )
80 | (symbol "XO2-DIP20" (in_bom yes) (on_board yes)
81 | (property "Reference" "U" (id 0) (at 0 -2.54 0)
82 | (effects (font (size 1.27 1.27)))
83 | )
84 | (property "Value" "XO2-DIP20" (id 1) (at 0 0 0)
85 | (effects (font (size 1.27 1.27)))
86 | )
87 | (property "Footprint" "" (id 2) (at 0 0 0)
88 | (effects (font (size 1.27 1.27)) hide)
89 | )
90 | (property "Datasheet" "" (id 3) (at 0 0 0)
91 | (effects (font (size 1.27 1.27)) hide)
92 | )
93 | (symbol "XO2-DIP20_0_1"
94 | (rectangle (start -7.62 -5.08) (end 7.62 -33.02)
95 | (stroke (width 0) (type default) (color 0 0 0 0))
96 | (fill (type none))
97 | )
98 | )
99 | (symbol "XO2-DIP20_1_1"
100 | (pin power_in line (at -10.16 -7.62 0) (length 2.54)
101 | (name "GND" (effects (font (size 1.27 1.27))))
102 | (number "1" (effects (font (size 1.27 1.27))))
103 | )
104 | (pin bidirectional line (at -10.16 -30.48 0) (length 2.54)
105 | (name "PIN14" (effects (font (size 1.27 1.27))))
106 | (number "10" (effects (font (size 1.27 1.27))))
107 | )
108 | (pin bidirectional line (at 10.16 -30.48 180) (length 2.54)
109 | (name "PIN16" (effects (font (size 1.27 1.27))))
110 | (number "11" (effects (font (size 1.27 1.27))))
111 | )
112 | (pin bidirectional line (at 10.16 -27.94 180) (length 2.54)
113 | (name "PIN17" (effects (font (size 1.27 1.27))))
114 | (number "12" (effects (font (size 1.27 1.27))))
115 | )
116 | (pin bidirectional line (at 10.16 -25.4 180) (length 2.54)
117 | (name "PIN20" (effects (font (size 1.27 1.27))))
118 | (number "13" (effects (font (size 1.27 1.27))))
119 | )
120 | (pin bidirectional line (at 10.16 -22.86 180) (length 2.54)
121 | (name "PIN21" (effects (font (size 1.27 1.27))))
122 | (number "14" (effects (font (size 1.27 1.27))))
123 | )
124 | (pin bidirectional line (at 10.16 -20.32 180) (length 2.54)
125 | (name "PIN23" (effects (font (size 1.27 1.27))))
126 | (number "15" (effects (font (size 1.27 1.27))))
127 | )
128 | (pin bidirectional line (at 10.16 -17.78 180) (length 2.54)
129 | (name "PIN25" (effects (font (size 1.27 1.27))))
130 | (number "16" (effects (font (size 1.27 1.27))))
131 | )
132 | (pin bidirectional line (at 10.16 -15.24 180) (length 2.54)
133 | (name "PIN26" (effects (font (size 1.27 1.27))))
134 | (number "17" (effects (font (size 1.27 1.27))))
135 | )
136 | (pin bidirectional line (at 10.16 -12.7 180) (length 2.54)
137 | (name "PIN27" (effects (font (size 1.27 1.27))))
138 | (number "18" (effects (font (size 1.27 1.27))))
139 | )
140 | (pin bidirectional line (at 10.16 -10.16 180) (length 2.54)
141 | (name "PIN28" (effects (font (size 1.27 1.27))))
142 | (number "19" (effects (font (size 1.27 1.27))))
143 | )
144 | (pin bidirectional line (at -10.16 -10.16 0) (length 2.54)
145 | (name "PIN4" (effects (font (size 1.27 1.27))))
146 | (number "2" (effects (font (size 1.27 1.27))))
147 | )
148 | (pin power_in line (at 10.16 -7.62 180) (length 2.54)
149 | (name "VCC" (effects (font (size 1.27 1.27))))
150 | (number "20" (effects (font (size 1.27 1.27))))
151 | )
152 | (pin bidirectional line (at -10.16 -12.7 0) (length 2.54)
153 | (name "PIN5" (effects (font (size 1.27 1.27))))
154 | (number "3" (effects (font (size 1.27 1.27))))
155 | )
156 | (pin bidirectional line (at -10.16 -15.24 0) (length 2.54)
157 | (name "PIN8" (effects (font (size 1.27 1.27))))
158 | (number "4" (effects (font (size 1.27 1.27))))
159 | )
160 | (pin bidirectional line (at -10.16 -17.78 0) (length 2.54)
161 | (name "PIN9" (effects (font (size 1.27 1.27))))
162 | (number "5" (effects (font (size 1.27 1.27))))
163 | )
164 | (pin bidirectional line (at -10.16 -20.32 0) (length 2.54)
165 | (name "PIN10" (effects (font (size 1.27 1.27))))
166 | (number "6" (effects (font (size 1.27 1.27))))
167 | )
168 | (pin bidirectional line (at -10.16 -22.86 0) (length 2.54)
169 | (name "PIN11" (effects (font (size 1.27 1.27))))
170 | (number "7" (effects (font (size 1.27 1.27))))
171 | )
172 | (pin bidirectional line (at -10.16 -25.4 0) (length 2.54)
173 | (name "PIN12" (effects (font (size 1.27 1.27))))
174 | (number "8" (effects (font (size 1.27 1.27))))
175 | )
176 | (pin bidirectional line (at -10.16 -27.94 0) (length 2.54)
177 | (name "PIN13" (effects (font (size 1.27 1.27))))
178 | (number "9" (effects (font (size 1.27 1.27))))
179 | )
180 | )
181 | )
182 | )
183 |
--------------------------------------------------------------------------------
/testrig/board/board.kicad_prl:
--------------------------------------------------------------------------------
1 | {
2 | "board": {
3 | "active_layer": 44,
4 | "active_layer_preset": "",
5 | "auto_track_width": true,
6 | "hidden_netclasses": [],
7 | "hidden_nets": [],
8 | "high_contrast_mode": 0,
9 | "net_color_mode": 1,
10 | "opacity": {
11 | "images": 0.6,
12 | "pads": 1.0,
13 | "tracks": 1.0,
14 | "vias": 1.0,
15 | "zones": 0.6
16 | },
17 | "ratsnest_display_mode": 0,
18 | "selection_filter": {
19 | "dimensions": true,
20 | "footprints": true,
21 | "graphics": true,
22 | "keepouts": true,
23 | "lockedItems": true,
24 | "otherItems": true,
25 | "pads": true,
26 | "text": true,
27 | "tracks": true,
28 | "vias": true,
29 | "zones": true
30 | },
31 | "visible_items": [
32 | 0,
33 | 1,
34 | 2,
35 | 3,
36 | 4,
37 | 5,
38 | 6,
39 | 7,
40 | 8,
41 | 9,
42 | 10,
43 | 11,
44 | 12,
45 | 13,
46 | 14,
47 | 15,
48 | 16,
49 | 18,
50 | 19,
51 | 20,
52 | 21,
53 | 22,
54 | 23,
55 | 24,
56 | 25,
57 | 26,
58 | 27,
59 | 28,
60 | 29,
61 | 30,
62 | 32,
63 | 33,
64 | 34,
65 | 35,
66 | 36
67 | ],
68 | "visible_layers": "003ffff_80000001",
69 | "zone_display_mode": 0
70 | },
71 | "git": {
72 | "repo_password": "",
73 | "repo_type": "",
74 | "repo_username": "",
75 | "ssh_key": ""
76 | },
77 | "meta": {
78 | "filename": "board.kicad_prl",
79 | "version": 3
80 | },
81 | "project": {
82 | "files": []
83 | }
84 | }
85 |
--------------------------------------------------------------------------------
/testrig/board/board.pdf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/c0pperdragon/LumaCode/b7e07dc5e4880d52ede0bd72d37bf442476c6d00/testrig/board/board.pdf
--------------------------------------------------------------------------------
/testrig/board/sym-lib-table:
--------------------------------------------------------------------------------
1 | (sym_lib_table
2 | (lib (name "Library")(type "KiCad")(uri "${KIPRJMOD}/Library.kicad_sym")(options "")(descr ""))
3 | )
4 |
--------------------------------------------------------------------------------
/testrig/calcpll.py:
--------------------------------------------------------------------------------
1 | def calc(target):
2 | bestf = 0
3 | bestvco = 0
4 | bestd1 = 0
5 | bestdivider = 0
6 | for d1 in range(24,65,1):
7 | vco = 12.5*d1
8 | for divider in range(1,129,1):
9 | f = vco/divider
10 | if abs(f-target) < abs(bestf-target):
11 | bestf = f
12 | bestvco = vco
13 | bestd1 = d1
14 | bestdivider = divider
15 | print ("best for ",target,": ",bestvco,"(",bestd1,") ","/",bestdivider,"=", bestvco/bestdivider);
16 | calc(71.5909) # Atari 8-bit/2600 NTSC
17 | calc(88.67236) # VIC20 PAL
18 | calc(28.63636) # 8xNTSC subcarrier (clock generator for VIC 20 PAL)
19 | calc(106.40685) # NES 4xPAL master clock
20 | calc(28.636352) # 2 times C16 master clock NTSC
21 | calc(57.272724) # 4 times AppleIIGS(NTSC) clock
22 | calc(7.080000) # 2 times G7000 clock
23 |
--------------------------------------------------------------------------------
/testrig/ledanimation/.run_manager.ini:
--------------------------------------------------------------------------------
1 | [Runmanager]
2 | Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xdc\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
3 | windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
4 | headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
5 |
6 | [impl1%3CStrategy1%3E]
7 | isChecked=false
8 | isHidden=false
9 | isExpanded=false
10 |
--------------------------------------------------------------------------------
/testrig/ledanimation/.spread_sheet.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | COLUMN_POS_INFO_NAME_-1_0=Prioritize
3 | COLUMN_POS_INFO_NAME_-1_1=PIO Register
4 |
--------------------------------------------------------------------------------
/testrig/ledanimation/.spreadsheet_view.ini:
--------------------------------------------------------------------------------
1 | [General]
2 | pin_sort_type=0
3 | pin_sort_ascending=true
4 | sig_sort_type=0
5 | sig_sort_ascending=true
6 | active_Sheet=Port Assignments
7 |
8 | [Port%20Assignments]
9 | Name="151,0"
10 | Group%20By="83,1"
11 | Pin="55,2"
12 | BANK="66,3"
13 | BANK_VCC="93,4"
14 | VREF="63,5"
15 | IO_TYPE="185,6"
16 | PULLMODE="127,7"
17 | DRIVE="70,8"
18 | SLEWRATE="121,9"
19 | CLAMP="89,10"
20 | OPENDRAIN="100,11"
21 | DIFFRESISTOR="114,12"
22 | DIFFDRIVE="95,13"
23 | HYSTERESIS="101,14"
24 | Outload%20%28pF%29="101,15"
25 | MaxSkew="86,16"
26 | Clock%20Load%20Only="118,17"
27 | SwitchingID="98,18"
28 | Ground%20plane%20PCB%20noise%20%28mV%29="185,19"
29 | Power%20plane%20PCB%20noise%20%28mV%29="182,20"
30 | SSO%20Allowance%28%25%29="134,21"
31 | sort_columns="Name,Ascending"
32 |
33 | [Pin%20Assignments]
34 | Pin="95,0"
35 | Pad%20Name="94,1"
36 | Dual%20Function="205,2"
37 | Polarity="77,3"
38 | BANK="0,4"
39 | BANK_VCC="93,5"
40 | IO_TYPE="185,6"
41 | Signal%20Name="101,7"
42 | Signal%20Type="135,8"
43 | sort_columns="Pin,Ascending"
44 |
45 | [Clock%20Resource]
46 | Clock%20Type="100,ELLIPSIS"
47 | Clock%20Name="100,ELLIPSIS"
48 | Selection="100,ELLIPSIS"
49 |
50 | [Global%20Preferences]
51 | Preference%20Name="288,ELLIPSIS"
52 | Preference%20Value="268,ELLIPSIS"
53 |
54 | [Cell%20Mapping]
55 | Type="100,ELLIPSIS"
56 | Name="100,ELLIPSIS"
57 | Din\Dout="100,ELLIPSIS"
58 | PIO%20Register="100,ELLIPSIS"
59 |
60 | [Route%20Priority]
61 | Type="100,ELLIPSIS"
62 | Name="100,ELLIPSIS"
63 | Prioritize="100,ELLIPSIS"
64 |
65 | [Timing%20Preferences]
66 | Preference%20Name="161,ELLIPSIS"
67 | Preference%20Value="128,ELLIPSIS"
68 | Preference%20Unit="121,ELLIPSIS"
69 |
70 | [Group]
71 | Group%20Type\Name="160,ELLIPSIS"
72 | Value="48,ELLIPSIS"
73 |
74 | [Misc%20Preferences]
75 | Preference%20Name="147,ELLIPSIS"
76 | Preference%20Value="128,ELLIPSIS"
77 |
--------------------------------------------------------------------------------
/testrig/ledanimation/LEDAnimation.ccl:
--------------------------------------------------------------------------------
1 | VERSION=20110520
2 |
--------------------------------------------------------------------------------
/testrig/ledanimation/LEDAnimation.ldf:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
--------------------------------------------------------------------------------
/testrig/ledanimation/LEDAnimation.lpf:
--------------------------------------------------------------------------------
1 | BLOCK RESETPATHS ;
2 | BLOCK ASYNCPATHS ;
3 | LOCATE COMP "CP[1]" SITE "16" ;
4 | LOCATE COMP "CP[3]" SITE "27" ;
5 | LOCATE COMP "D[0]" SITE "13" ;
6 | LOCATE COMP "D[1]" SITE "12" ;
7 | LOCATE COMP "D[2]" SITE "11" ;
8 | LOCATE COMP "D[3]" SITE "10" ;
9 | LOCATE COMP "D[4]" SITE "9" ;
10 | LOCATE COMP "D[5]" SITE "8" ;
11 | LOCATE COMP "D[6]" SITE "5" ;
12 | LOCATE COMP "D[7]" SITE "4" ;
13 | VOLTAGE 3.300 V;
14 | SYSCONFIG MCCLK_FREQ=88.67 ;
15 | LOCATE COMP "CP[0]" SITE "17" ;
16 | LOCATE COMP "CP[2]" SITE "28" ;
17 | LOCATE COMP "CLK" SITE "21" ;
18 |
--------------------------------------------------------------------------------
/testrig/ledanimation/promote.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
--------------------------------------------------------------------------------
/testrig/ledanimation/reportview.xml:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
--------------------------------------------------------------------------------
/testrig/ledanimation/source/LEDAnimation.vhd:
--------------------------------------------------------------------------------
1 | library ieee;
2 | library machxo2;
3 | use ieee.numeric_std.all;
4 | use ieee.std_logic_1164.all;
5 | use machxo2.all;
6 |
7 | entity LEDAnimation is
8 | port (
9 | CLK : in std_logic;
10 | D : out std_logic_vector(7 downto 0);
11 | CP : out std_logic_vector(3 downto 0)
12 | );
13 | end entity;
14 |
15 |
16 | architecture immediate of LEDAnimation is
17 |
18 | begin
19 | -- generate output led animation
20 | process (CLK)
21 |
22 | variable phase: integer range 0 to 7 := 0;
23 | variable led: std_logic_vector(31 downto 0);
24 | variable delay: integer range 0 to 32000000 := 0;
25 | variable anim: integer range 0 to 31 := 0;
26 |
27 | begin
28 | if rising_edge(CLK) then
29 | case phase is
30 | when 0 => CP <= "0000"; D <= led(7 downto 0);
31 | when 1 => CP <= "0001";
32 | when 2 => CP <= "0000"; D <= led(15 downto 8);
33 | when 3 => CP <= "0010";
34 | when 4 => CP <= "0000"; D <= led(16)&led(17)&led(18)&led(19)&led(20)&led(21)&led(22)&led(23);
35 | when 5 => CP <= "0100";
36 | when 6 => CP <= "0000"; D <= led(24)&led(25)&led(26)&led(27)&led(28)&led(29)&led(30)&led(31);
37 | when 7 => CP <= "1000";
38 | end case;
39 | phase := (phase+1) mod 8;
40 |
41 | for L in 0 to 31 loop
42 | if (anim<24 and L>=anim and L=24 and (L>=anim or L0 then
51 | delay:=delay-1;
52 | else
53 | delay := 25000000/2 - 1;
54 | anim := (anim+1) mod 32;
55 | end if;
56 | end if;
57 | end process;
58 |
59 | end immediate;
60 |
--------------------------------------------------------------------------------