├── .gitignore ├── .travis.yml ├── LICENSE.txt ├── Makefile ├── Makefile.connectal ├── Makefile.version ├── README.md ├── boardinfo ├── ac701.json ├── ac701_untethered.json ├── ac701g2.json ├── asic.json ├── awsf1.json ├── bluesim.json ├── cvc.json ├── de5.json ├── htg4.json ├── kc160g2.json ├── kc705.json ├── kc705_untethered.json ├── kc705g1.json ├── kc705g2.json ├── kcu105.json ├── miniitx100.json ├── ncverilog.json ├── nfsume.json ├── parallella.json ├── ultra96.json ├── v2000t.json ├── vc707.json ├── vc707g2.json ├── vc709.json ├── vcs.json ├── vcu108.json ├── vcu118.json ├── verilator.json ├── vsim.json ├── xsim.json ├── zc702.json ├── zc706.json ├── zc706_ubuntu.json ├── zcu102.json ├── zcu111.json ├── zedboard.json ├── zedboard_ubuntu.json ├── zybo.json └── zynq100.json ├── bsv ├── Adapter.bsv ├── AddressGenerator.bsv ├── AsicTop.bsv ├── AvalonBits.bsv ├── AvalonDdr3Controller.bsv ├── AvalonDma.bsv ├── AvalonGather.bsv ├── AvalonMasterSlave.bsv ├── AvalonSplitter.bsv ├── AwsF1Top.bsv ├── Axi4MasterSlave.bsv ├── AxiBits.bsv ├── AxiDdr3Controller.bsv ├── AxiDma.bsv ├── AxiGather.bsv ├── AxiMasterSlave.bsv ├── AxiStream.bsv ├── BpiFlash.bsv ├── BramMux.bsv ├── CnocPortal.bsv ├── ConnectableWithTrace.bsv ├── ConnectalAlteraCells.bsv ├── ConnectalBram.bsv ├── ConnectalBramFifo.bsv ├── ConnectalClocks.bsv ├── ConnectalCompletionBuffer.bsv ├── ConnectalConfig.bsv ├── ConnectalEHR.bsv ├── ConnectalFIFO.bsv ├── ConnectalMMU.bsv ├── ConnectalMemTypes.bsv ├── ConnectalMemUtils.bsv ├── ConnectalMemory.bsv ├── ConnectalMimo.bsv ├── ConnectalPrelude.bsv ├── ConnectalXilinxCells.bsv ├── CtrlMux.bsv ├── DisplayInd.bsv ├── Dsp48E1.bsv ├── GearboxGetPut.bsv ├── GetPutM.bsv ├── GetPutWithClocks.bsv ├── HostInterface.bsv ├── LinkerLib.bsv ├── MIFO.bsv ├── MemPipe.bsv ├── MemReadEngine.bsv ├── MemServer.bsv ├── MemServerInternal.bsv ├── MemServerPortal.bsv ├── MemToPcie.bsv ├── MemWriteEngine.bsv ├── OldEHR.bsv ├── PS4LIB.bsv ├── PS5LIB.bsv ├── PS7LIB.bsv ├── PS7Trace.bsv ├── PS8LIB.bsv ├── ParallellaTop.bsv ├── Pcie1EndpointX7.bsv ├── Pcie2EndpointX7.bsv ├── Pcie3EndpointX7.bsv ├── Pcie3RootPortX7.bsv ├── PcieCsr.bsv ├── PcieEndpointS5.bsv ├── PcieEndpointS5Test.bsv ├── PcieGearbox.bsv ├── PcieHost.bsv ├── PcieRootDevice.bsv ├── PcieRootPortX7.bsv ├── PcieSplitter.bsv ├── PcieStateChanges.bsv ├── PcieToMem.bsv ├── PcieTop.bsv ├── PcieTracer.bsv ├── PhysMemSlaveFromBram.bsv ├── Pipe.bsv ├── Platform.bsv ├── Portal.bsv ├── SimDma.bsv ├── SimLink.bsv ├── SyncAxisFifo32x8.bsv ├── SyncBits.bsv ├── Trace.bsv ├── TraceMemClient.bsv ├── UntetheredTop.bsv ├── XsimIF.bsv ├── XsimTop.bsv ├── ZynqTop.bsv └── ZynqUltraTop.bsv ├── constraints ├── altera │ ├── de5.qsf │ ├── de5.sdc │ ├── htg4.qsf │ └── htg4.sdc └── xilinx │ ├── Readme.md │ ├── ac701.xdc │ ├── awsf1.xdc │ ├── bluesim.xdc │ ├── bluesim_pcie.xdc │ ├── cdc.tcl │ ├── kc160g2.xdc │ ├── kc705-3.0.xdc │ ├── kc705-ddr3.prj │ ├── kc705.xdc │ ├── kc705g2.xdc │ ├── kcu105.xdc │ ├── miniitx100-axiddr3.prj │ ├── miniitx100.xdc │ ├── nfsume-axiddr3.prj │ ├── nfsume.xdc │ ├── ok │ ├── zc7z010clg400.xdc │ ├── zc7z020clg400.xdc │ ├── zc7z020clg484.xdc │ ├── zc7z045ffg900.xdc │ └── zc7z100ffg900.xdc │ ├── parallella.xdc │ ├── pcie-clocks.xdc │ ├── v2000t.xdc │ ├── vc707-axiddr3.prj │ ├── vc707-portal-pblock.xdc │ ├── vc707.xdc │ ├── vc707_aurora.xdc │ ├── vc707_ddr3.xdc │ ├── vc707_ddr3_pins.xdc │ ├── vc707g2-axiddr3.prj │ ├── vc707g2.xdc │ ├── vc709.xdc │ ├── vcu108.xdc │ ├── vcu118.xdc │ ├── verilator.xdc │ ├── xc7z010clg400.xdc │ ├── xc7z045ffg900.xdc │ ├── xc7z100ffg900.xdc │ ├── zc706-axiddr3.prj │ ├── zc706.xdc │ ├── zc706_pl_ddr3_pins.xdc │ ├── zc7z020clg400.xdc │ ├── zc7z020clg484.xdc │ ├── zcu102.xdc │ ├── zcu111.xdc │ ├── zybo.xdc │ └── zynq100.xdc ├── contrib ├── bluescope │ ├── Makefile │ ├── Memcpy.bsv │ ├── Top.bsv │ └── testbluescope.cpp ├── bluescopeevent │ ├── Makefile │ ├── SignalGen.bsv │ ├── Top.bsv │ └── testbluescopeevent.cpp ├── bluescopeeventpio │ ├── Makefile │ ├── SignalGen.bsv │ ├── Top.bsv │ └── testbluescopeeventpio.cpp ├── channelselect │ ├── ChannelSelect.bsv │ ├── ChannelSelectTest.bsv │ ├── ChannelSelectTestInterfaces.bsv │ ├── DDS.bsv │ ├── DDSTest.bsv │ ├── DDSTestInterfaces.bsv │ ├── FPCMult.bsv │ ├── Makefile │ ├── Readme.md │ ├── SDRTypes.bsv │ ├── Top.bsv │ ├── sinetable.c │ └── testchannelselecttest.cpp ├── fib │ ├── Fib.bsv │ ├── FibNarrow.bsv │ ├── Makefile │ ├── Readme.md │ └── testfib.cpp ├── flowcontrol │ ├── Makefile │ ├── Sink.bsv │ ├── Top.bsv │ └── test.cpp ├── importverilog │ ├── .gitignore │ ├── Main.bsv │ ├── Makefile │ ├── Readme.md │ ├── regfile.v │ ├── regfile_tb.v │ └── testmain.cpp ├── maxcommonsubseq │ ├── HirschA.bsv │ ├── HirschB.bsv │ ├── HirschC.bsv │ ├── MCSAlgorithm.bsv │ ├── Makefile │ ├── Maxcommonsubseq.bsv │ ├── Top.bsv │ ├── hirschberg.py │ └── testmaxcommonsubseq.cpp ├── noc │ ├── Makefile │ ├── Noc.bsv │ ├── NocNode.bsv │ ├── Readme.md │ ├── Top.bsv │ └── testnoc.cpp ├── noc2d │ ├── Makefile │ ├── Noc2d.bsv │ ├── NocNode.bsv │ ├── Readme.md │ ├── Top.bsv │ └── testnoc2d.cpp ├── parallella │ ├── ELink.bsv │ ├── Makefile │ ├── PParallellaLIB.bsv │ ├── ParallellaLib.bsv │ ├── ParallellaLibDefs.bsv │ ├── Top.bsv │ ├── notes.txt │ ├── parallella.v │ └── testmain.cpp ├── perf │ ├── Makefile │ ├── Perf.bsv │ ├── Top.bsv │ └── testperf.cpp ├── pipe_mul │ ├── Makefile │ ├── PipeMulTB.bsv │ ├── Top.bsv │ └── testpipe_mul.cpp ├── pipe_mul2 │ ├── Makefile │ ├── PipeMulTB.bsv │ ├── Top.bsv │ └── testpipe_mul.cpp ├── portalperf │ ├── Makefile │ ├── PortalPerf.bsv │ ├── Repeat.bsv │ ├── Top.bsv │ └── testportalperf.cpp ├── ptest │ ├── Makefile │ ├── PTest.bsv │ ├── PTest.bsv.bad │ └── PTest.bsv.good ├── serialconfig │ ├── Makefile │ ├── Readme.md │ ├── Serialconfig.bsv │ └── testserialconfig.cpp ├── smithwaterman │ ├── GotohB.bsv │ ├── GotohC.bsv │ ├── Makefile │ ├── Readme.md │ ├── Smithwaterman.bsv │ ├── Top.bsv │ ├── sw.py │ └── testsmithwaterman.cpp └── splice │ ├── Makefile │ ├── Splice.bsv │ ├── Top.bsv │ └── testsplice.cpp ├── cpp ├── BsimDma.cpp ├── DmaBuffer.cpp ├── DmaBuffer.h ├── MMUServer.h ├── TlpReplay.cpp ├── XsimTop.cpp ├── XsimTop.h ├── bluesim_main.cxx ├── bsim_relay.c ├── dmaManager.c ├── dmaManager.h ├── dmaSendFd.h ├── kernel_module.c ├── manualMMUIndication.h ├── monkit.h ├── platformMemory.cpp ├── poller.cpp ├── portal.c ├── portal.h ├── portalJson.c ├── portalKernel.h ├── portalPrintf.c ├── portalPython.cpp ├── runpython.cpp ├── sock_utils.c ├── sock_utils.h ├── timer.c ├── transportHardware.c ├── transportPortal.c ├── transportSerial.c ├── transportShared.c ├── transportSocket.c ├── transportWebSocket.c ├── transportXsim.c └── verilatortop.cpp ├── debian ├── changelog ├── compat ├── connectal-doc.docs ├── connectal-doc.install ├── connectal-zynqdrivers.install ├── connectal.dkms ├── connectal.install ├── connectal.udev ├── control ├── copyright ├── docs └── rules ├── doc ├── Makefile ├── ReadmePartialReconfiguration.md ├── SmithWaterman.md ├── android-sdk-screenshots │ ├── android-sdk-license.png │ ├── android-sdk-manager-log.png │ └── android-sdk-manager.png ├── axi_tracing.md ├── centos.md ├── generated │ └── html │ │ ├── indication-only.png │ │ ├── portal.html │ │ └── request-response-1.png ├── ifdef.md ├── library │ ├── Makefile │ └── source │ │ ├── bsv │ │ ├── addressgenerator.rst │ │ ├── arith.rst │ │ ├── axistream.rst │ │ ├── bsv.rst │ │ ├── ctrlmux.rst │ │ ├── hostinterface.rst │ │ ├── leds.rst │ │ ├── memportal.rst │ │ ├── memreadengine.rst │ │ ├── memtypes.rst │ │ ├── mmu.rst │ │ ├── pipe.rst │ │ └── portal.rst │ │ ├── bsvsphinx.py │ │ ├── c │ │ ├── c.rst │ │ └── portal.rst │ │ ├── conf.py │ │ ├── design │ │ ├── Makefile │ │ ├── abstract.rst │ │ ├── bs-related-papers.bib │ │ ├── conclusion.rst │ │ ├── connectal-framework.rst │ │ ├── design.rst │ │ ├── flowcontrol.rst │ │ ├── host_interface.rst │ │ ├── images │ │ │ ├── Makefile │ │ │ ├── MemreadEngine.pdf │ │ │ ├── MemreadEngine.pptx │ │ │ ├── PortalImpl0.pptx │ │ │ ├── data_accel_logical0.pdf │ │ │ ├── data_accel_logical0.pptx │ │ │ ├── data_accel_logical1.pdf │ │ │ ├── data_accel_logical1.pptx │ │ │ ├── data_accel_logical2.pdf │ │ │ ├── data_accel_logical2.pptx │ │ │ ├── data_accel_logical3.pdf │ │ │ ├── data_accel_logical3.pptx │ │ │ ├── data_accel_logical4.pdf │ │ │ ├── data_accel_logical4.pptx │ │ │ ├── msc0.pdf │ │ │ ├── msc0.pptx │ │ │ ├── msc1.pdf │ │ │ ├── msc1.pptx │ │ │ ├── msc2.pdf │ │ │ ├── msc2.pptx │ │ │ ├── platform.pdf │ │ │ ├── platform.pptx │ │ │ ├── platforms.pdf │ │ │ └── platforms.pptx │ │ ├── implementing-string-search.rst │ │ ├── interface_definitions.rst │ │ ├── introduction.rst │ │ ├── performance.rst │ │ ├── portal.rst │ │ ├── portalstructure.rst │ │ ├── references.bib │ │ ├── related-work.rst │ │ ├── string-search.rst │ │ └── toolchain.rst │ │ ├── devguide │ │ ├── clocks.rst │ │ ├── compilingproject.rst │ │ ├── connectalbuild.pdf │ │ ├── design.rst │ │ ├── devguide.rst │ │ └── projectstructure.rst │ │ ├── examples │ │ ├── index.rst │ │ └── simple.rst │ │ ├── index.rst │ │ ├── installation.rst │ │ ├── intro.rst │ │ ├── make.rst │ │ ├── makefile.connectal.build.rst │ │ ├── makefile.connectal.rst │ │ ├── themes │ │ └── connectal │ │ │ ├── layout.html │ │ │ ├── static │ │ │ └── tracking.js_t │ │ │ └── theme.conf │ │ └── tools │ │ ├── generate-constraints.rst │ │ ├── makefilegen.rst │ │ ├── pcieflat.rst │ │ ├── tools.rst │ │ └── topgen.rst ├── makefilegen.md ├── maxcommonsubseq.md ├── previous │ └── portal.asciidoc ├── server.md └── syntax.md ├── docker └── Dockerfile ├── drivers ├── awsf1portal │ ├── Makefile │ ├── Makefile.dkms │ ├── cdev_bypass.c │ ├── cdev_ctrl.c │ ├── cdev_ctrl.h │ ├── cdev_events.c │ ├── cdev_sgdma.c │ ├── cdev_sgdma.h │ ├── cdev_xvc.c │ ├── cdev_xvc.h │ ├── dkms.conf │ ├── driverversion.h │ ├── libxdma.c │ ├── libxdma.h │ ├── libxdma_api.h │ ├── linux │ │ └── dma-buf.h │ ├── pcieportal.h │ ├── portal.c │ ├── portal_internal.h │ ├── version.h │ ├── xdma_cdev.c │ ├── xdma_cdev.h │ ├── xdma_ioctl.h │ ├── xdma_mod.c │ └── xdma_mod.h ├── connectalsdhci │ ├── Makefile │ └── connectalsdhci.c ├── connectalspi │ ├── Makefile │ └── connectalspi.c ├── pcieportal │ ├── Makefile │ ├── Makefile.dkms │ ├── dkms.conf │ ├── driverversion.h │ ├── linux │ │ └── dma-buf.h │ ├── pcieportal.c │ └── pcieportal.h ├── portalmem │ ├── Makefile │ ├── portalmem.c │ └── portalmem.h └── zynqportal │ ├── Makefile │ ├── zynqportal.c │ └── zynqportal.h ├── etc ├── modules-load.d │ └── connectal.conf └── udev │ └── rules.d │ ├── 51-connectaltty.rules │ ├── 52-altera-usb.rules │ ├── 52-connectaltest.rules │ ├── 52-digilent-usb.rules │ └── 99-pcieportal.rules ├── examples ├── algo1_nandsim │ ├── Algo1NandSim.bsv │ ├── Makefile │ ├── nandsim.cpp │ ├── test.bin │ └── test.cpp ├── algo2_nandsim │ ├── Makefile │ ├── Top.bsv │ ├── jregexp.charMap │ ├── jregexp.stateMap │ ├── jregexp.stateTransitions │ ├── test.bin │ └── test.cpp ├── aurora │ ├── Aurora.bsv │ ├── BviAurora.bsv │ ├── Gtx.bsv │ ├── Makefile │ ├── Top.bsv │ ├── aurora-clocks.xdc │ ├── aurora.json │ ├── clock.tcl │ ├── synth-ip.tcl │ └── testaurora.cpp ├── bscan │ ├── BscanIF.bsv │ ├── Makefile │ └── testbscan.cpp ├── caffe │ ├── Conv.bsv │ ├── INSTALL │ ├── Makefile │ └── README.md ├── echo │ ├── Echo.bsv │ ├── Makefile │ └── testecho.cpp ├── echo2ind │ ├── Echo.bsv │ ├── Makefile │ └── testecho.cpp ├── echofast │ └── Makefile ├── echohost │ ├── Echo.bsv │ ├── Makefile │ ├── testecho.cpp │ └── vc707_floorplan.xdc ├── echoinvert │ ├── Echo.bsv │ ├── EchoInterface.bsv │ ├── Makefile │ └── testecho.cpp ├── echojson │ ├── Echo.bsv │ ├── Makefile │ ├── Swallow.bsv │ ├── daemon.cpp │ └── testecho.cpp ├── echojsonpy │ ├── Echo.bsv │ ├── Makefile │ ├── Swallow.bsv │ ├── daemon.cpp │ ├── old_testecho.py │ └── testecho.py ├── echomux │ ├── Echo.bsv │ ├── Makefile │ ├── Services.bsv │ ├── daemon.cpp │ └── testecho.cpp ├── echoproto │ ├── Echo.bsv │ ├── Makefile │ ├── echo.proto │ └── testecho.cpp ├── echopy │ ├── Echo.bsv │ ├── EchoInterface.bsv │ ├── Makefile │ ├── testecho.py │ └── ubuntu-python-dev.sh ├── echoshared │ ├── Echo.bsv │ ├── Makefile │ ├── daemon.cpp │ └── testecho.cpp ├── echoslow │ ├── Echo.bsv │ └── Makefile ├── echosoft │ ├── Echo.bsv │ ├── Makefile │ ├── Swallow.bsv │ ├── daemon.cpp │ └── testecho.cpp ├── echotrace │ ├── Echo.bsv │ ├── Makefile │ ├── testecho.cpp │ └── vc707_floorplan.xdc ├── echowebsocket │ ├── Echo.bsv │ ├── Makefile │ ├── Swallow.bsv │ ├── daemon.cpp │ └── testecho.cpp ├── fmcomms1 │ ├── ExtraXilinxCells.bsv │ ├── ExtraXilinxCells.bsv.pp │ ├── FMComms1.bsv │ ├── FMComms1ADC.bsv │ ├── FMComms1DAC.bsv │ ├── FMComms1Pins.bsv │ ├── Makefile │ ├── Top.bsv │ ├── clock.tcl │ ├── fmci2c.c │ ├── fmci2c.h │ ├── fmcomms1-fmc.json │ ├── i2c_zedboardandroid.c │ ├── i2c_zedboardandroid.h │ ├── readtrace.py │ ├── testfmcomms1.cpp │ └── testi2c.c ├── gyro_simple │ ├── Makefile │ ├── clock.tcl │ ├── gyro.h │ ├── gyroVisualize.py │ ├── gyro_simple.h │ ├── pinout.json │ ├── test_gyro.cpp │ └── test_gyro.py ├── gyrospi │ ├── Makefile │ ├── STest.bsv │ ├── gyro.h │ ├── pinout.json │ └── testspi.cpp ├── hbridge_simple │ ├── Makefile │ ├── hbridge_simple.h │ ├── pinout.json │ └── test_hbridge.cpp ├── hdmidisplay │ ├── BsimHdmi.cpp │ ├── HDMI16.bsv │ ├── Makefile │ ├── TestHdmi.pro │ ├── hdmi.json │ ├── hdmidisplay-bluesim.xdc │ ├── hdmidisplay-vc707.xdc │ ├── hdmidisplay-zc702.xdc │ ├── hdmidisplay-zedboard.xdc │ ├── i2c.json │ ├── qtmain.cpp │ ├── testhdmidisplay.cpp │ └── worker.h ├── imageon │ ├── ImageonCapture.bsv │ ├── ImageonCapturePins.bsv │ ├── Makefile │ ├── Makefile.dump │ ├── clock.tcl │ ├── dump_image.cpp │ ├── i2ccamera.h │ ├── imageon-clocks.xdc │ ├── imageon-fmc.json │ ├── imageon-zedboard.json │ └── testimagecapture.cpp ├── leds │ ├── LedController.bsv │ ├── Makefile │ ├── pinout.json │ └── testleds.cpp ├── linking │ ├── GetInverse.v │ ├── LinkerLib.bsv │ ├── Makefile │ ├── Processor.bsv │ ├── ProcessorTop.bsv │ └── Processor_Generated.bsv ├── matmul │ ├── Makefile │ ├── Makefile.mm │ ├── Makefile.mmif │ ├── clocks.tcl │ ├── design-vc707.tcl │ ├── design.tcl │ ├── mkZynqTop_flpn.xdc │ ├── perf.txt │ ├── synth-ip.tcl │ └── testmm.cpp ├── maxsonar_simple │ ├── Makefile │ ├── maxsonar_simple.h │ ├── pinout.json │ └── test_maxsonar.cpp ├── memcpy │ ├── Makefile │ ├── Memcpy.bsv │ └── testmemcpy.cpp ├── memcpyslow │ └── Makefile ├── memlatency │ ├── Makefile │ ├── Memlatency.bsv │ └── testmemlatency.cpp ├── memread │ ├── Makefile │ ├── ReadTest.bsv │ ├── design_vc707.tcl │ ├── testmemread.cpp │ └── vc707_floorplan.xdc ├── memread128 │ ├── Makefile │ └── vcu118 │ │ └── vivado.log ├── memread2 │ ├── Makefile │ ├── Memread2.bsv │ └── testmemread2.cpp ├── memread256 │ └── Makefile ├── memread_4m │ ├── Makefile │ └── ReadTest.bsv ├── memread_simple │ ├── Makefile │ ├── ReadTest.bsv │ ├── design_vc707.tcl │ ├── testmemread.cpp │ └── vc707_floorplan.xdc ├── memwrite │ ├── Makefile │ ├── Memwrite.bsv │ └── testmemwrite.cpp ├── memwrite128 │ └── Makefile ├── memwrite256 │ └── Makefile ├── memwrite_4m │ ├── Makefile │ └── Memwrite.bsv ├── nandsim │ ├── Makefile │ └── testnandsim.cpp ├── portal-synth-boundary │ ├── Makefile │ ├── Simple.bsv │ ├── Top.bsv │ └── testsimple.cpp ├── printf │ ├── Echo.bsv │ ├── Makefile │ ├── SwallowIF.bsv │ ├── Top.bsv │ └── testecho.cpp ├── rbm │ ├── LICENSE.txt │ ├── Makefile │ ├── Makefile.rbm │ ├── Readme.md │ ├── synth-ip.tcl │ └── testrbm.cpp ├── readbw │ ├── ReadBW.bsv │ └── testreadbw.cpp ├── regexp │ ├── Makefile │ ├── jregexp.charMap │ ├── jregexp.stateMap │ ├── jregexp.stateTransitions │ ├── test.bin │ └── testregexp.cpp ├── sdcard_spi │ ├── Makefile │ ├── SPI.bsv │ ├── SPITest.bsv │ ├── pin_translation.json │ ├── readme.txt │ └── sdcard_spi.cpp ├── simple │ ├── Makefile │ ├── Simple.bsv │ ├── boards │ │ ├── de5.json │ │ └── htg4.json │ ├── simple.h │ └── testsimple.cpp ├── simplemultibluesim │ ├── Link.bsv │ ├── LinkIF.bsv │ ├── Makefile │ ├── run.sh │ ├── testsimple.cpp │ └── xsimrun.sh ├── simplesharedhw │ ├── Makefile │ ├── Simple.bsv │ └── testsimple.cpp ├── strstr │ ├── Makefile │ ├── StrstrExample.bsv │ └── teststrstr.cpp ├── swmemcpy │ ├── Makefile │ ├── SWmemcpy.bsv │ └── testswmemcpy.cpp ├── vectoradd_hls │ ├── Makefile │ ├── README.md │ ├── bsv │ │ ├── Vadd.bsv │ │ └── VaddBvi.bsv │ ├── solution1 │ │ └── impl │ │ │ └── verilog │ │ │ └── vectoradd.v │ ├── src │ │ └── vectoradd.cpp │ └── testvadd.cpp ├── zedboard_robot │ ├── Controller.bsv │ ├── Makefile │ ├── pinout.json │ ├── sonarVisualize.py │ ├── test_zedboard_robot.cpp │ └── test_zedboard_robot.py └── zynqpcie │ ├── Makefile │ ├── SimpleIF.bsv │ ├── Top.bsv │ ├── ZynqPcieTestIF.bsv │ ├── synth-ip.tcl │ ├── testsimple.cpp │ ├── testzynqpcie.cpp │ └── zynqpcie.json ├── generated ├── altera │ ├── ALTERA_DDR3_WRAPPER.bsv │ ├── ALTERA_ETH_PMA_RECONFIG_WRAPPER.bsv │ ├── ALTERA_ETH_PMA_RESET_CONTROL_WRAPPER.bsv │ ├── ALTERA_ETH_PMA_WRAPPER.bsv │ ├── ALTERA_PCIE_ED_WRAPPER.bsv │ ├── ALTERA_PCIE_RECONFIG_DRIVER_WRAPPER.bsv │ ├── ALTERA_PCIE_SIV_WRAPPER.bsv │ ├── ALTERA_PCIE_SV_WRAPPER.bsv │ ├── ALTERA_PLL_WRAPPER.bsv │ └── ALTERA_XCVR_RECONFIG_WRAPPER.bsv ├── cpp │ ├── GeneratedTypes.h │ ├── MMURequest.c │ └── README ├── scripts │ ├── generate_altera_ddrbvi.sh │ ├── generate_altera_ethbvi.sh │ ├── generate_altera_macbvi.sh │ ├── generate_altera_pciebvi.sh │ ├── generate_bscane2.sh │ ├── generate_bufgcrtl.sh │ ├── generate_pcie2wrapper.sh │ ├── generate_pcie3.sh │ ├── generate_pcie3u.sh │ ├── generate_pcie3uplus.sh │ ├── generate_pcie_2_1.sh │ ├── generate_pciewrapper.sh │ ├── generate_pipeclock.sh │ ├── generate_pps7.sh │ ├── generate_pps7lib.sh │ ├── generate_zynq_mpsoc.sh │ └── importbvi.py └── xilinx │ ├── AxiDdr3Wrapper.bsv │ ├── AxiDmaBvi.bsv │ ├── AxiEth1000BaseX.bsv │ ├── AxiEthBvi.bsv │ ├── AxiIntcBvi.bsv │ ├── BscanE2.bsv │ ├── Bufgctrl.bsv │ ├── Ddr3Wrapper.bsv │ ├── PCIEWRAPPER.bsv │ ├── PCIEWRAPPER2.bsv │ ├── PCIEWRAPPER3.bsv │ ├── PCIEWRAPPER3u.bsv │ ├── PCIEWRAPPER3uplus.bsv │ ├── PCIE_2_1.bsv │ ├── PPS7LIB.bsv │ ├── PipeClock.bsv │ └── ZYNQ_ULTRA.bsv ├── gralloc ├── Android.mk ├── Makefile ├── README ├── bitset ├── gr.h ├── gralloc.cpp ├── gralloc_priv.h └── mapper.cpp ├── jtag ├── README ├── bsd │ ├── xc7k325t_ffg900.bsd │ ├── xc7vx485t_ffg1761.bsd │ ├── xc7vx690t_ffg1761.bsd │ └── xc7z020_clg484.bsd ├── digilent-hs1.cfg ├── digilent-hs2.cfg ├── dumptrace.py ├── kc705.cfg ├── kc705program.cfg ├── pcietrace.cfg ├── readll.py ├── run_jtag.sh ├── run_trace.sh ├── zedboard.cfg └── zedtrace.cfg ├── lib ├── bsv │ ├── Arith.bsv │ ├── BRAMFIFOFLevel.bsv │ ├── BlueScope.bsv │ ├── BlueScopeEvent.bsv │ ├── BlueScopeEventPIO.bsv │ ├── Bscan.bsv │ ├── ConfigCounter.bsv │ ├── ConnectalSpi.bsv │ ├── Dma2BRAM.bsv │ ├── FrequencyCounter.bsv │ ├── HDMI.bsv │ ├── HdmiDisplay.bsv │ ├── ImageonVita.bsv │ ├── IserdesDatadeser.bsv │ ├── IserdesDatadeserIF.bsv │ ├── Leds.bsv │ ├── PipeMul.bsv │ ├── SharedMemoryFifo.bsv │ ├── SharedMemoryPortal.bsv │ ├── SpiRoot.bsv │ ├── SpiTap.bsv │ ├── Stack.bsv │ ├── StackReg.bsv │ ├── XADC.bsv │ ├── XilinxVirtex7PCIE.bsv │ └── YUV.bsv ├── cpp │ ├── connectal_conv.cpp │ ├── connectal_conv.h │ ├── connectal_convmm.cpp │ ├── edid.h │ ├── i2chdmi.h │ ├── printfInd.h │ └── userReference.h ├── deprecated │ ├── BurstFunnel.bsv │ ├── DirectoryRF.bsv │ ├── DmaUtils.bsv │ ├── OldMemServer.bsv │ ├── RegFileA.bsv │ ├── SGListComb.bsv │ ├── bsv_Makefile │ ├── pcietestbench │ │ ├── Makefile │ │ ├── PcieTestBench.bsv │ │ ├── Top.bsv │ │ └── testpcie.cpp │ ├── pcietestbench_dma_io │ │ ├── Makefile │ │ ├── Memread.bsv │ │ ├── PcieTestBench.bsv │ │ ├── Top.bsv │ │ ├── memread_nobuff_io.tstlp │ │ └── testpcie.cpp │ └── pcietestbench_dma_oo │ │ ├── Makefile │ │ ├── Memread.bsv │ │ ├── PcieTestBench.bsv │ │ ├── Top.bsv │ │ ├── memread_nobuff_oo.tstlp │ │ └── testpcie.cpp ├── matmul │ ├── bar.m │ ├── bsv │ │ ├── DotProdServer.bsv │ │ ├── FloatOps.bsv │ │ ├── FpAdd.bsv │ │ ├── FpMac.bsv │ │ ├── FpMacTb.bsv │ │ ├── FpMul.bsv │ │ ├── MatrixNT.bsv │ │ └── MatrixTN.bsv │ └── cpp │ │ ├── cuda.cpp │ │ ├── portalmat.cpp │ │ └── portalmat.h ├── nandsim │ ├── bsv │ │ ├── NandSim.bsv │ │ └── NandSimNames.bsv │ └── cpp │ │ └── nandsim.h ├── nvme │ ├── bsv │ │ ├── AxiPcie3RootPort.bsv │ │ ├── AxiPcieRootPort.bsv │ │ ├── Nvme.bsv │ │ ├── NvmeIfc.bsv │ │ └── NvmePins.bsv │ ├── cpp │ │ ├── nvme.cpp │ │ └── nvme.h │ └── tcl │ │ └── package.tcl ├── qemu │ ├── fpgadev.cpp │ └── fpgadev.h ├── rbm │ ├── bsv │ │ ├── DmaVector.bsv │ │ ├── Rbm.bsv │ │ ├── RbmTypes.bsv │ │ ├── Sigmoid.bsv │ │ └── Timer.bsv │ └── cpp │ │ ├── mnist.h │ │ ├── rbm.cpp │ │ └── rbm.h ├── regexp │ ├── bsv │ │ ├── Regexp.bsv │ │ └── RegexpEngine.bsv │ └── cpp │ │ └── regexp_utils.h ├── strstr │ ├── bsv │ │ ├── MPEngine.bsv │ │ └── Strstr.bsv │ └── cpp │ │ ├── mp.h │ │ └── strstr.h └── zedboard_robot │ ├── bsv │ ├── GyroController.bsv │ ├── HBridgeController.bsv │ └── MaxSonarController.bsv │ └── cpp │ ├── read_buffer.cpp │ └── read_buffer.h ├── pcie ├── Makefile ├── pcieflat ├── testdata.dat └── tlp.py ├── scripts ├── AST.py ├── Doxyfile ├── Makefile.connectal.application ├── Makefile.connectal.build ├── adb │ ├── LICENSE │ ├── README.rst │ ├── __init__.py │ ├── adb_commands.py │ ├── adb_debug.py │ ├── adb_protocol.py │ ├── adb_test.py │ ├── common.py │ ├── common_cli.py │ ├── common_stub.py │ ├── fastboot.py │ ├── fastboot_debug.py │ ├── fastboot_protocol.txt │ ├── fastboot_test.py │ ├── filesync_protocol.py │ ├── filesync_protocol.txt │ └── usb_exceptions.py ├── aws │ ├── build.sh │ ├── create-fpga-image.sh │ ├── create_dcp_from_cl.tcl │ ├── describe-latest-fpga-image.sh │ ├── encrypt.tcl │ ├── notify_via_sns.py │ ├── run.awsf1 │ ├── synth_awsf1.tcl │ ├── upload.sh │ └── wait_for_afi.py ├── boardinfo.py ├── bsv.filter ├── bsvdepend.py ├── bsvdependencies.py ├── bsvgen.py ├── bsvpreprocess.py ├── cadb ├── check-timing.py ├── connectal-make ├── connectal-synth-avalonddr3.tcl ├── connectal-synth-axichecker.tcl ├── connectal-synth-axiddr3.tcl ├── connectal-synth-axidma.tcl ├── connectal-synth-axieth.tcl ├── connectal-synth-axiintc.tcl ├── connectal-synth-eth.tcl ├── connectal-synth-ila.tcl ├── connectal-synth-ip.tcl ├── connectal-synth-pcie-rp.tcl ├── connectal-synth-pcie.tcl ├── connectal-synth-pll.tcl ├── connectal-synth-zynq-mpsoc.tcl ├── cppgen.py ├── deprecated │ ├── mkpcietop-partial-reconfiguration.tcl │ ├── mkpcietop-synth.tcl │ ├── portaltop-impl.tcl │ └── portaltop-synth.tcl ├── discover_icmp.py ├── discover_tcp.py ├── driver_signature.sed ├── extract-bvi-schedule.py ├── generate-constraints.py ├── globalv.py ├── makefilegen.py ├── packagesource.py ├── parse_qsf.py ├── parse_xdc.py ├── portal.py ├── portalJson.py ├── power.py ├── preprocess_trace.py ├── reorderbytes.py ├── run.android ├── run.android.sh ├── run.parallella.sh ├── run.pcietest ├── run.pcietest.altera ├── run_on_daffodil ├── syntax.py ├── topgen.py └── util.py ├── tests ├── adapter │ ├── Makefile │ ├── Test.bsv │ └── test.cpp ├── aecho │ ├── Echo.orig.bsv │ ├── EchoReq.bsv │ ├── Makefile │ ├── generated │ │ ├── Echo.bsv │ │ ├── EchoVerilog.v │ │ ├── L_class_OC_Echo.bsv │ │ ├── L_class_OC_Fifo.bsv │ │ ├── L_class_OC_Fifo1.bsv │ │ ├── l_class_OC_Echo.cpp │ │ ├── l_class_OC_Echo.h │ │ ├── l_class_OC_Echo.v │ │ ├── l_class_OC_EchoIndication.cpp │ │ ├── l_class_OC_EchoIndication.h │ │ ├── l_class_OC_EchoRequest.cpp │ │ ├── l_class_OC_EchoRequest.h │ │ ├── l_class_OC_EchoTest.cpp │ │ ├── l_class_OC_EchoTest.h │ │ ├── l_class_OC_Fifo.cpp │ │ ├── l_class_OC_Fifo.h │ │ ├── l_class_OC_Fifo.v │ │ ├── l_class_OC_Fifo1.cpp │ │ ├── l_class_OC_Fifo1.h │ │ ├── l_class_OC_Fifo1.v │ │ ├── output.cpp │ │ └── output.h │ └── testecho.cpp ├── algo1_flashmodel │ ├── AuroraCommon.bsv │ ├── AuroraGearbox.bsv │ ├── AuroraImportFmc1.bsv │ ├── ChipscopeWrapper.bsv │ ├── ControllerTypes.bsv │ ├── FlashBusModel.bsv │ ├── FlashCtrlModel.bsv │ ├── FlashTop.bsv │ ├── Makefile │ ├── NandSimMod.bsv │ ├── NullResetN.bsv │ ├── PageBuffers.bsv │ ├── Top.bsv │ ├── TopPins.bsv │ ├── flashaccess.cpp │ └── test.cpp ├── algo1_nandsim_manual │ ├── Makefile │ ├── algo1.cpp │ ├── haystack.txt │ ├── kernel │ │ └── Makefile │ └── nandsim_manual.c ├── avalon_mm │ ├── AvalonBfmWrapper.bsv │ ├── Echo.bsv │ ├── Makefile │ ├── Readme.md │ ├── TestProgram.bsv │ ├── avlm_avls_1x1.qsys │ ├── testecho.cpp │ └── verilog │ │ ├── tb.sv │ │ └── test_program.v ├── axieth │ ├── AxiEth.bsv │ ├── EthPins.bsv │ ├── Makefile │ ├── axieth.h │ ├── axieth.json │ ├── axieth.xdc │ ├── testaxieth.cpp │ └── xsim_export.tcl ├── bluecheck-bram │ ├── Bram2Example.bsv │ ├── BramExample.bsv │ └── make.sh ├── bluecheck-sharedmemfifo │ ├── ConnectalProjectConfig.bsv │ ├── SharedMemoryFifoCheck.bsv │ └── make.sh ├── bluecheck_harness │ ├── Harness.bsv │ ├── Makefile │ └── harness.py ├── bpiflash │ ├── BpiFlashTest.bsv │ ├── I28F512P33.bsv │ ├── Makefile │ ├── bpiflash.h │ ├── bpiflash.json │ ├── i28f512p33.v │ └── testbpiflash.cpp ├── ddr3 │ ├── Ddr3Test.bsv │ ├── Makefile │ ├── synth-ip.tcl │ └── testddr3.cpp ├── ddr3_altera │ ├── Ddr3Test.bsv │ ├── Makefile │ ├── de5.json │ ├── synth-ip.tcl │ └── testddr3.cpp ├── ddr_minimal │ ├── Ddr3Test.bsv │ ├── Makefile │ ├── synth-ip.tcl │ └── testddr3.cpp ├── dma2bram │ ├── Makefile │ ├── Test.bsv │ └── test.cpp ├── dram_awsf1 │ ├── Axi4.bsv │ ├── DdrAws.bsv │ ├── Makefile │ └── testddr3.cpp ├── echosoft2 │ ├── EchoId.bsv │ ├── Makefile │ ├── daemon.cpp │ └── testecho.cpp ├── fastecho │ ├── FastEcho.bsv │ ├── Makefile │ ├── about_this_test.txt │ ├── synth-ip.tcl │ └── testfastecho.cpp ├── float │ ├── FloatTest.bsv │ ├── Makefile │ └── ftest.c ├── fp │ ├── BviFpAdd.bsv │ ├── FpOps.bsv │ ├── FpTest.bsv │ ├── Makefile │ ├── synth-ip.tcl │ └── testfp.cpp ├── guard │ ├── GuardTest.bsv │ ├── Makefile │ └── gtest.c ├── ipcperf │ ├── IpcTest.bsv │ ├── Makefile │ ├── testipctest.cpp │ └── vc707_floorplan.xdc ├── memcpy_manysglists │ ├── Makefile │ ├── Top.bsv │ └── testmemcpy.cpp ├── memread_err │ ├── Makefile │ ├── Memread.bsv │ └── testmemread.cpp ├── memread_manual │ ├── Makefile │ ├── ReadTest.bsv │ ├── design_vc707.tcl │ ├── kernel │ │ └── Makefile │ ├── memread_manual_manager.c │ └── vc707_floorplan.xdc ├── memread_manyclients │ ├── Makefile │ └── performance.txt ├── memread_manyclients128 │ └── Makefile ├── memread_manyengines │ ├── Makefile │ └── ReadTest.bsv ├── memserver_copy │ ├── Makefile │ ├── Memcopy.bsv │ └── testmemcopy.cpp ├── memserver_copy128 │ └── Makefile ├── memserver_copy_slow │ └── Makefile ├── memserver_write │ ├── Makefile │ ├── Memwrite.bsv │ └── testmemwrite.cpp ├── memserver_write128 │ └── Makefile ├── memtopcie_bluesim │ ├── Makefile │ └── Top.bsv ├── memwrite_acp │ ├── Makefile │ ├── Memwrite.bsv │ └── testmemwrite.cpp ├── memwrite_manyclients │ └── Makefile ├── memwrite_manyclients128 │ └── Makefile ├── memwrite_trivial │ ├── Makefile │ ├── Memwrite.bsv │ └── testmemwrite.cpp ├── memwriteengine_test │ ├── Makefile │ ├── MemWriteEngineTest.bsv │ ├── Memwrite.bsv │ └── testmemwrite.cpp ├── method │ ├── Makefile │ ├── Method.bsv │ └── mtest.cpp ├── mifo │ ├── Makefile │ ├── MifoTest.bsv │ └── testmifo.cpp ├── nandsim_manual │ ├── Makefile │ ├── kernel │ │ └── Makefile │ ├── nandsim_manual.c │ ├── testnandsim.cpp │ └── testnandsim_test.cpp ├── nvme_core │ └── string_search.cpp ├── nvme_strstr │ ├── Makefile │ ├── NvmeSearch.bsv │ ├── StringSearchIfc.bsv │ ├── fmc.json │ ├── main.cpp │ ├── nfsume.json │ ├── nvme.json │ ├── nvme.xdc │ ├── package100.tcl │ └── synth-ip.tcl ├── nvme_test │ ├── Makefile │ ├── NvmeTest.bsv │ ├── fmc.json │ ├── impl.tcl │ ├── main.cpp │ ├── miniitx100.json │ ├── nfsume.json │ ├── nfsume.xdc │ ├── nvme.xdc │ └── synth-ip.tcl ├── ov7670 │ ├── Makefile │ ├── Ov7670Controller.bsv │ ├── Ov7670Interface.bsv │ ├── SCCB.bsv │ ├── pinout.json │ └── testcam.cpp ├── partial │ ├── Bounce.bsv │ ├── Bounce1.bsv │ ├── Bounce2.bsv │ ├── Bounce3.bsv │ ├── Echo.bsv │ ├── Makefile │ ├── README │ ├── floorplan-zc702.xdc │ └── testecho.cpp ├── pcie-debug │ ├── Makefile │ ├── TestPins.bsv │ ├── TracePcie.bsv │ ├── pin_translation.json │ └── tracepcie.cpp ├── pciememcheck │ ├── CheckMPM.bsv │ ├── Makefile │ ├── PcieMemCheck.bsv │ └── pciememcheck.cpp ├── physmaster │ ├── Echo.bsv │ ├── Makefile │ ├── PhysReq.bsv │ ├── daemon.cpp │ └── testecho.cpp ├── qemuaccel │ ├── AccelIfcNames.bsv │ ├── AccelTop.bsv │ ├── BlockDev.bsv │ ├── Devices.bsv │ ├── Makefile │ ├── QemuAccel.bsv │ ├── QemuAccelIfc.bsv │ ├── Serial.bsv │ └── qemuaccel.cpp ├── rootport │ ├── AxiPcieRootPort.bsv │ ├── Makefile │ ├── RootPort.bsv │ ├── RootPortIfc.bsv │ ├── RootPortPins.bsv │ ├── gencores.tcl │ ├── rootport.cpp │ ├── rootport.json │ └── rootport.xdc ├── serialportal │ ├── Makefile │ ├── SerialPortalIfc.bsv │ ├── SerialPortalTest.bsv │ ├── rs232.json │ └── serialportal.cpp ├── simmethodtime │ ├── Makefile │ ├── Simm.bsv │ └── test.cpp ├── simple_manual │ ├── Makefile │ ├── Simple.bsv │ ├── kernel │ │ └── Makefile │ ├── simple_manual.c │ └── testsimple.cpp ├── spi │ ├── ConnectalProjectConfig.bsv │ ├── Makefile │ └── spitest.gtkw ├── spikehw │ ├── AxiEthBufferBvi.bsv │ ├── AxiEthSubsystem.bsv │ ├── AxiIic.bsv │ ├── AxiSpiBvi.bsv │ ├── AxiUart.bsv │ ├── GigEthPcsPmaBvi.bsv │ ├── Makefile │ ├── README.md │ ├── SpikeHw.bsv │ ├── SpikeHwIfc.bsv │ ├── SpikeHwPins.bsv │ ├── SyncAxisFifo32x1024.bsv │ ├── TriModeMacBvi.bsv │ ├── boot │ │ ├── Makefile │ │ ├── copybbl.c │ │ └── entry.S │ ├── bootromx4.hex │ ├── eth.json │ ├── flash.json │ ├── gencores.tcl │ ├── geneth.tcl │ ├── i2c-standard.json │ ├── nfsume.json │ ├── program.tcl │ ├── rtscts.json │ ├── spikehw-miniitx100.json │ ├── spikehw-vc707g2.json │ ├── spikehw-vc709.json │ ├── spikehw.cpp │ ├── spikehw.h │ ├── spikehw.json │ ├── spikehw.xdc │ ├── test-spikehw.cpp │ └── trace.tcl ├── test_pmod │ ├── Controller.bsv │ ├── Makefile │ ├── Top.bsv │ ├── pinout.json │ └── testpmod.cpp ├── test_sdio1 │ ├── Makefile │ ├── SDIO.bsv │ ├── Top.bsv │ ├── pinout.json │ └── test_sdio1.cpp ├── test_spi0 │ ├── Makefile │ ├── SPI.bsv │ ├── Top.bsv │ ├── foo.cpp │ └── test_spi0.cpp ├── testfpmul │ ├── Makefile │ ├── Top.bsv │ └── testfpmul.cpp ├── testldstrex │ ├── Makefile │ └── testldstrex.cpp ├── testmm16.16.2 │ ├── Makefile │ └── synth-ip.tcl ├── testmm16.16.4 │ ├── Makefile │ └── synth-ip.tcl ├── testmm2.4.2 │ ├── Makefile │ ├── synth-ip.tcl │ └── zc706_floorplan.xdc ├── testmm32.16.2 │ ├── Makefile │ └── synth-ip.tcl ├── testmm32.32.2 │ ├── Makefile │ └── synth-ip.tcl ├── testmm4.2.2 │ ├── Makefile │ └── synth-ip.tcl ├── testmm4.4.2 │ ├── Makefile │ └── synth-ip.tcl ├── testmm4.4.4 │ ├── Makefile │ └── synth-ip.tcl ├── testmm8.8.2 │ ├── Makefile │ ├── synth-ip.tcl │ └── zc706_floorplan.xdc ├── testmm8.8.4 │ ├── Makefile │ └── synth-ip.tcl ├── testmm_cuda_perf │ ├── Makefile │ ├── Readme.md │ ├── cuda_opencv_example │ │ ├── Makefile │ │ ├── image.jpg │ │ ├── main.cpp │ │ └── main.cu │ ├── run_exe │ ├── synth-ip.tcl │ └── zc706_floorplan.xdc ├── testrbm16.16.2 │ ├── Makefile │ └── synth-ip.tcl ├── testrbm8.8.2 │ ├── Makefile │ └── synth-ip.tcl └── yuv │ ├── Makefile │ ├── YuvIF.bsv │ └── testyuv.cpp └── verilog ├── CONNECTNET.v ├── CONNECTNET2.v ├── FpgaReset.v ├── GenBIBUF.v ├── LinkInverter.v ├── PositiveReset.v ├── PutInverter.v ├── SyncFIFO.v ├── SyncFIFO1.v ├── SyncReset.v ├── XsimDmaReadWrite.sv ├── XsimFinish.sv ├── XsimLink.sv ├── XsimSink.sv ├── XsimSource.sv ├── altera ├── BRAM1.v ├── BRAM1BE.v ├── BRAM2.v └── siv_gen2x8 │ └── siv_gen2x8.v ├── awsf1.sv ├── cl_id_defines.vh └── xsimtop.sv /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.pyc 3 | *.o 4 | lextab.py 5 | parselog.txt 6 | parser.out 7 | parsetab.py 8 | *.bo 9 | *.so 10 | *.ba 11 | *.cmd 12 | *.mod.c 13 | *.ko 14 | Module.symvers 15 | *.jou 16 | *.log 17 | .build 18 | mk*.cxx 19 | mk*.h 20 | *.bspec 21 | model_*.cxx 22 | model_*.h 23 | mk*.sched 24 | mk*.v 25 | modules.order 26 | xilinx/pcie_7x_v2_1 27 | examples/*/ac701 28 | examples/*/kc705 29 | examples/*/vc707 30 | examples/*/zc702 31 | examples/*/zc706 32 | examples/*/de5 33 | examples/*/htg4 34 | examples/*/zedboard 35 | examples/*/zybo 36 | generated/xilinx/* 37 | dkms.conf.out 38 | *.vcd 39 | bluesim 40 | xsim 41 | vc709 42 | vc707 43 | vc707g2 44 | usage_statistics_webtalk.* 45 | vivado_pid* 46 | nfsume 47 | .cache 48 | ubuntu.exe 49 | *signature_file.h 50 | .tmp_versions 51 | .Xil 52 | *.mcs 53 | verilator 54 | zc706 55 | *.png 56 | *.bit 57 | *.prm 58 | zedboard 59 | miniitx100 60 | *.pb 61 | kc705g2 62 | ac701g2 63 | *.ltx 64 | zedboard_ubuntu 65 | -------------------------------------------------------------------------------- /Makefile.version: -------------------------------------------------------------------------------- 1 | VERSION=22.05.23b 2 | -------------------------------------------------------------------------------- /boardinfo/ac701g2.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "bsvdefines" : ["XILINX=1", "Artix7", "PCIE", "PCIE2", "PcieHostInterface", "PhysAddrWidth=40", "PcieLanes=4", 4 | "CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit", "CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest"], 5 | "os" : "ubuntu", 6 | "partname" : "xc7a200tfbg676-2", 7 | "need_pcie" : "x7_gen2x8", 8 | "TOP" : "PcieTop", 9 | "constraints": ["constraints/xilinx/ac701.xdc", "constraints/xilinx/pcie-clocks.xdc"], 10 | "implconstraints": ["constraints/xilinx/ac701.xdc", "constraints/xilinx/pcie-clocks.xdc"], 11 | "runscript" : "run.pcietest", 12 | "CONNECTALFLAGS" : ["--mainclockperiod=4", "--derivedclockperiod=4", "--pcieclockperiod=4"], 13 | "rewireclockstring" : "" 14 | }, 15 | "fmc": { 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /boardinfo/asic.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "asic", 5 | "rewireclockstring" : "", 6 | "TOP" : "AsicTop", 7 | "bsvdefines": ["ASIC", "CnocTop", "XsimHostInterface", "PhysAddrWidth=32"], 8 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 9 | "need_pcie" : "unused" 10 | } 11 | } 12 | 13 | 14 | -------------------------------------------------------------------------------- /boardinfo/awsf1.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "bsvdefines" : ["XILINX=1", "VirtexUltrascale", "PhysAddrWidth=40", "DataBusWidth=512", "XsimHostInterface", "AWSF1=1", 4 | "MemTagSize=16", "MemServerTags=8", 5 | "DEFAULT_NOPROGRAM=1", 6 | "CONNECTAL_BITS_DEPENDENCES=build/checkpoints/to_aws/mkTop.SH_CL_routed.dcp", "CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.aws"], 7 | "os" : "ubuntu", 8 | "partname" : "xcvu9p-flgb2104-2-i", 9 | "TOP" : "AwsF1Top", 10 | "constraints": ["constraints/xilinx/awsf1.xdc"], 11 | "implconstraints": ["constraints/xilinx/awsf1.xdc"], 12 | "runscript" : "run.pcietest", 13 | "CONNECTALFLAGS" : ["--mainclockperiod=8", "--derivedclockperiod=8", "--pcieclockperiod=8"], 14 | "rewireclockstring" : "" 15 | }, 16 | "pins": { 17 | } 18 | } 19 | 20 | 21 | -------------------------------------------------------------------------------- /boardinfo/cvc.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "xc7z020clg484-1", 5 | "rewireclockstring" : "tclzynqrewireclock", 6 | "TOP" : "XsimTop", 7 | "bsvdefines": ["CnocTop", "XsimHostInterface", "PhysAddrWidth=40", "SIMULATION", "SVDPI", 8 | "CONNECTAL_BITS_DEPENDENCES=cvcsim"], 9 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 10 | "need_pcie" : "unused" 11 | } 12 | } 13 | 14 | 15 | -------------------------------------------------------------------------------- /boardinfo/kc160g2.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "bsvdefines" : ["XILINX=1", "Kintex7", "PCIE", "PCIE2", "PcieHostInterface", "PhysAddrWidth=40", "PcieLanes=8", 4 | "CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit", "CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest"], 5 | "os" : "ubuntu", 6 | "partname" : "xc7k160tffg676-2", 7 | "need_pcie" : "x7_gen2x8", 8 | "TOP" : "PcieTop", 9 | "constraints": [], 10 | "implconstraints": ["constraints/xilinx/kc160g2.xdc"], 11 | "runscript" : "run.pcietest", 12 | "CONNECTALFLAGS" : ["--mainclockperiod=4", "--derivedclockperiod=4", "--pcieclockperiod=4"], 13 | "rewireclockstring" : "" 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /boardinfo/ncverilog.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "xc7z020clg484-1", 5 | "TOP" : "XsimTop", 6 | "bsvdefines": ["CnocTop", "XsimHostInterface", "PhysAddrWidth=40", "SIMULATION", "SVDPI", 7 | "CONNECTAL_BITS_DEPENDENCES=ncverilogsim"], 8 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 9 | "need_pcie" : "unused" 10 | } 11 | } 12 | 13 | 14 | -------------------------------------------------------------------------------- /boardinfo/parallella.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "bsvdefines" : ["XILINX=1", "ZYNQ", "ZynqHostInterface", "PhysAddrWidth=32", 4 | "CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit", "CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android", 5 | "CONNECTAL_EXENAME=android.exe", "CONNECTAL_EXENAME2=android.exe2"], 6 | "os" : "ubuntu", 7 | "partname" : "xc7z020clg400-1", 8 | "constraints": [], 9 | "implconstraints": ["constraints/xilinx/zc7z020clg400.xdc", "constraints/xilinx/parallella.xdc"], 10 | "rewireclockstring" : "tclzynqrewireclock", 11 | "TOP" : "ZynqTop", 12 | "runscript" : "run.android", 13 | "CONNECTALFLAGS" : [], 14 | "need_pcie" : "unused" 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /boardinfo/v2000t.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "bsvdefines" : ["XILINX=1", "Virtex7", "PCIE", "PcieHostInterface", "PhysAddrWidth=40", 4 | "CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit", "CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest"], 5 | "os" : "ubuntu", 6 | "partname" : "xc7v2000tflg1925-2", 7 | "need_pcie" : "x7_gen1x8", 8 | "TOP" : "PcieTop", 9 | "constraints": [], 10 | "implconstraints": ["constraints/xilinx/v2000t.xdc"], 11 | "runscript" : "run.pcietest", 12 | "CONNECTALFLAGS" : [], 13 | "rewireclockstring" : "" 14 | }, 15 | "fmc": { 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /boardinfo/vcs.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "xc7z020clg484-1", 5 | "TOP" : "XsimTop", 6 | "bsvdefines": ["CnocTop", "XsimHostInterface", "PhysAddrWidth=40", "SIMULATION", "SVDPI", 7 | "CONNECTAL_BITS_DEPENDENCES=vcssim"], 8 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 9 | "need_pcie" : "unused" 10 | } 11 | } 12 | 13 | 14 | -------------------------------------------------------------------------------- /boardinfo/verilator.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "xc7z020clg484-1", 5 | "rewireclockstring" : "tclzynqrewireclock", 6 | "TOP" : "XsimTop", 7 | "bsvdefines": ["CnocTop", "XsimHostInterface", "PhysAddrWidth=40", "SIMULATION", "SVDPI", 8 | "CONNECTAL_BITS_DEPENDENCES=vlsim"], 9 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 10 | "need_pcie" : "unused" 11 | } 12 | } 13 | 14 | 15 | -------------------------------------------------------------------------------- /boardinfo/vsim.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "5SGXEA7N2F45C2", 5 | "rewireclockstring" : "tclzynqrewireclock", 6 | "TOP" : "XsimTop", 7 | "bsvdefines": ["MODELSIM=1", "CnocTop", "XsimHostInterface", "PhysAddrWidth=40", "XSIM", "SIMULATION", "SVDPI", "PcieLanes=8", 8 | "CONNECTAL_BITS_DEPENDENCES=vsim"], 9 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 10 | "need_pcie" : "unused" 11 | } 12 | } 13 | 14 | 15 | -------------------------------------------------------------------------------- /boardinfo/xsim.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "ubuntu", 4 | "partname" : "xc7z020clg484-1", 5 | "rewireclockstring" : "tclzynqrewireclock", 6 | "TOP" : "XsimTop", 7 | "bsvdefines": ["XILINX=1", "CnocTop", "XsimHostInterface", "PhysAddrWidth=40", "XSIM", "SIMULATION", "SVDPI", "PcieLanes=8", 8 | "CONNECTAL_BITS_DEPENDENCES=xsim"], 9 | "CONNECTALFLAGS" : ["--mainclockperiod=20", "--derivedclockperiod=10"], 10 | "need_pcie" : "unused" 11 | } 12 | } 13 | 14 | 15 | -------------------------------------------------------------------------------- /boardinfo/zynq100.json: -------------------------------------------------------------------------------- 1 | { 2 | "options": { 3 | "os" : "android", 4 | "partname" : "xc7z100ffg900-2", 5 | "rewireclockstring" : "tclzynqrewireclock", 6 | "constraints": [], 7 | "implconstraints": ["constraints/xilinx/xc7z045ffg900.xdc", "constraints/xilinx/zynq100.xdc", 8 | "CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit", "CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android", 9 | "CONNECTAL_EXENAME=android.exe", "CONNECTAL_EXENAME2=android.exe2"], 10 | "TOP" : "ZynqTop", 11 | "runscript" : "run.android", 12 | "bsvdefines" : ["XILINX=1", "ZYNQ", "ZynqHostInterface", "PhysAddrWidth=40"], 13 | "CONNECTALFLAGS" : [], 14 | "need_pcie" : "unused" 15 | }, 16 | "fmc": { 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /constraints/xilinx/awsf1.xdc: -------------------------------------------------------------------------------- 1 | # TBD 2 | -------------------------------------------------------------------------------- /constraints/xilinx/bluesim.xdc: -------------------------------------------------------------------------------- 1 | this file intentionally left blank 2 | -------------------------------------------------------------------------------- /constraints/xilinx/bluesim_pcie.xdc: -------------------------------------------------------------------------------- 1 | this file intentionally left blank 2 | -------------------------------------------------------------------------------- /constraints/xilinx/cdc.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## set properties to help out clock domain crossing analysis 3 | ## 4 | 5 | # set ASYNC_REG property on SyncReset and SyncFifo variants 6 | foreach pat {"reset_hold_reg[*]" "sGEnqPtr*_reg[*]" "dGDeqPtr*_reg[*]" "sSyncReg*_reg[*]" "dSyncReg*_reg[*]"} { 7 | set cells [get_cells -hier $pat] 8 | if {[llength $cells] > 0} { 9 | puts "ASYNC_REG $cells" 10 | set_property ASYNC_REG 1 $cells 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /constraints/xilinx/parallella.xdc: -------------------------------------------------------------------------------- 1 | # Nothing here, until the standard Parallella stuff gets defined 2 | -------------------------------------------------------------------------------- /constraints/xilinx/v2000t.xdc: -------------------------------------------------------------------------------- 1 | # constraints TBD 2 | -------------------------------------------------------------------------------- /constraints/xilinx/vc707-portal-pblock.xdc: -------------------------------------------------------------------------------- 1 | startgroup 2 | create_pblock pblock_portalTop 3 | resize_pblock pblock_portalTop -add {SLICE_X0Y0:SLICE_X105Y199 DSP48_X0Y0:DSP48_X8Y79 PCIE_X0Y0:PCIE_X0Y0 RAMB18_X0Y0:RAMB18_X6Y79 RAMB36_X0Y0:RAMB36_X6Y39} 4 | add_cells_to_pblock pblock_portalTop [get_cells top_portalTop] 5 | endgroup 6 | -------------------------------------------------------------------------------- /constraints/xilinx/verilator.xdc: -------------------------------------------------------------------------------- 1 | this file intentionally left blank 2 | -------------------------------------------------------------------------------- /constraints/xilinx/zcu102.xdc: -------------------------------------------------------------------------------- 1 | 2 | ## TBD 3 | 4 | -------------------------------------------------------------------------------- /constraints/xilinx/zcu111.xdc: -------------------------------------------------------------------------------- 1 | 2 | ## TBD 3 | 4 | -------------------------------------------------------------------------------- /constraints/xilinx/zybo.xdc: -------------------------------------------------------------------------------- 1 | set_property iostandard "LVCMOS25" [get_ports "GPIO_leds[0]"] 2 | set_property PACKAGE_PIN "M14" [get_ports "GPIO_leds[0]"] 3 | set_property slew "SLOW" [get_ports "GPIO_leds[0]"] 4 | set_property PIO_DIRECTION "OUTPUT" [get_ports "GPIO_leds[0]"] 5 | 6 | set_property iostandard "LVCMOS25" [get_ports "GPIO_leds[1]"] 7 | set_property PACKAGE_PIN "M15" [get_ports "GPIO_leds[1]"] 8 | set_property slew "SLOW" [get_ports "GPIO_leds[1]"] 9 | set_property PIO_DIRECTION "OUTPUT" [get_ports "GPIO_leds[1]"] 10 | 11 | set_property iostandard "LVCMOS25" [get_ports "GPIO_leds[2]"] 12 | set_property PACKAGE_PIN "G14" [get_ports "GPIO_leds[2]"] 13 | set_property slew "SLOW" [get_ports "GPIO_leds[2]"] 14 | set_property PIO_DIRECTION "OUTPUT" [get_ports "GPIO_leds[2]"] 15 | 16 | set_property iostandard "LVCMOS25" [get_ports "GPIO_leds[3]"] 17 | set_property PACKAGE_PIN "D18" [get_ports "GPIO_leds[3]"] 18 | set_property slew "SLOW" [get_ports "GPIO_leds[3]"] 19 | set_property PIO_DIRECTION "OUTPUT" [get_ports "GPIO_leds[3]"] 20 | -------------------------------------------------------------------------------- /contrib/bluescope/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = MemcpyRequest BlueScopeRequest MemcpyIndication BlueScopeIndication MemServerIndication 4 | BSVFILES = Memcpy.bsv $(CONNECTALDIR)/lib/bsv/BlueScope.bsv Top.bsv 5 | CPPFILES=testbluescope.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/bluescopeevent/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = SignalGenRequest SignalGenIndication \ 4 | BlueScopeEventRequest BlueScopeEventIndication 5 | BSVFILES = ../../lib/bsv/BlueScopeEvent.bsv SignalGen.bsv Top.bsv 6 | CPPFILES=testbluescopeevent.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /contrib/bluescopeeventpio/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = SignalGenRequest SignalGenIndication \ 3 | BlueScopeEventPIORequest BlueScopeEventPIOIndication 4 | 5 | BSVFILES = ../../lib/bsv/BlueScopeEventPIO.bsv SignalGen.bsv Top.bsv 6 | CPPFILES=testbluescopeeventpio.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /contrib/channelselect/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = ChannelSelectTestRequest DDSTestRequest ChannelSelectTestIndication DDSTestIndication 3 | 4 | BSVFILES = ChannelSelectTestInterfaces.bsv DDSTestInterfaces.bsv Top.bsv 5 | CPPFILES=testchannelselecttest.cpp 6 | 7 | gentarget:: sine.bin 8 | 9 | sine.bin: sinetable 10 | mkdir -p bluesim 11 | ./sinetable >sine.bin 12 | cp sine.bin bluesim 13 | 14 | sinetable: sinetable.c 15 | cc -o sinetable sinetable.c -lm 16 | 17 | include $(CONNECTALDIR)/Makefile.connectal 18 | -------------------------------------------------------------------------------- /contrib/fib/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = FibRequest:Fib.request 3 | H2S_INTERFACES = Fib:FibIndication 4 | 5 | BSVFILES = Fib.bsv 6 | CPPFILES=testfib.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /contrib/flowcontrol/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = SinkRequest SinkIndication 3 | 4 | BSVFILES = Sink.bsv Top.bsv 5 | CPPFILES=test.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/importverilog/.gitignore: -------------------------------------------------------------------------------- 1 | RegFile.bsv 2 | -------------------------------------------------------------------------------- /contrib/importverilog/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MainRequest:Main.request 3 | H2S_INTERFACES = Main:MainRequest 4 | 5 | BSVFILES = Main.bsv RegFile.bsv 6 | CPPFILES=testmain.cpp 7 | 8 | RegFile.bsv: regfile.v 9 | $(CONNECTALDIR)/generated/scripts/importbvi.py -o RegFile.bsv -I RegFile -P RF -c clock -r reset_n \ 10 | regfile.v 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /contrib/importverilog/Readme.md: -------------------------------------------------------------------------------- 1 | This example shows how to integrate a verilog module 2 | with Bluespec code. 3 | 4 | In the Makefile there is a target to build RefFile.bsv automatically 5 | from regfile.v. This creates a Bluespec wrapper for the verilog, 6 | allowing Bluespec code to send signals into the verilog and to get 7 | results back into Bluespec. 8 | -------------------------------------------------------------------------------- /contrib/maxcommonsubseq/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = MaxcommonsubseqRequest MaxcommonsubseqIndication 4 | BSVFILES = Maxcommonsubseq.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv 5 | CPPFILES=testmaxcommonsubseq.cpp 6 | CONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /contrib/noc/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = NocRequest NocIndication 3 | 4 | BSVFILES = Noc.bsv Top.bsv 5 | CPPFILES=testnoc.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/noc2d/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = NocRequest NocIndication 3 | 4 | BSVFILES = Noc2d.bsv Top.bsv 5 | CPPFILES=testnoc2d.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/perf/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = PerfRequest PerfIndication 4 | BSVFILES = Perf.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv 5 | CPPFILES=testperf.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/pipe_mul/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = PipeMulRequest PipeMulIndication 3 | 4 | BSVFILES = PipeMulTB.bsv Top.bsv 5 | CPPFILES=testpipe_mul.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/pipe_mul2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = PipeMulRequest PipeMulIndication 3 | 4 | BSVFILES = PipeMulTB.bsv Top.bsv 5 | CPPFILES=testpipe_mul.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/portalperf/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = PortalPerfRequest PortalPerfIndication 3 | 4 | BSVFILES = Repeat.bsv PortalPerf.bsv Top.bsv 5 | CPPFILES=testportalperf.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /contrib/ptest/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = PTestRequest PTestIndication 3 | 4 | BSVFILES = PTest.bsv 5 | 6 | include $(CONNECTALDIR)/Makefile.connectal 7 | -------------------------------------------------------------------------------- /contrib/serialconfig/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = SerialconfigRequest:Serialconfig.request 3 | H2S_INTERFACES = Serialconfig:SerialconfigIndication 4 | 5 | BSVFILES = Serialconfig.bsv 6 | CPPFILES=testserialconfig.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /contrib/smithwaterman/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = SmithwatermanRequest SmithwatermanIndication 4 | BSVFILES = Smithwaterman.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv 5 | CPPFILES=testsmithwaterman.cpp 6 | CONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /contrib/smithwaterman/Readme.md: -------------------------------------------------------------------------------- 1 | ## Smith-Waterman 2 | 3 | L. Stewart 4 | March17, 2014 5 | 6 | See connectal/doc/SmithWaterman.md 7 | -------------------------------------------------------------------------------- /contrib/splice/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = SpliceRequest SpliceIndication 4 | BSVFILES = Splice.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv 5 | CPPFILES=testsplice.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /debian/compat: -------------------------------------------------------------------------------- 1 | 8 2 | -------------------------------------------------------------------------------- /debian/connectal-doc.docs: -------------------------------------------------------------------------------- 1 | #DOCS# 2 | -------------------------------------------------------------------------------- /debian/connectal-doc.install: -------------------------------------------------------------------------------- 1 | #DOCS# 2 | -------------------------------------------------------------------------------- /debian/connectal-zynqdrivers.install: -------------------------------------------------------------------------------- 1 | /usr/share/connectal-zynqdrivers/*.ko 2 | -------------------------------------------------------------------------------- /debian/connectal.dkms: -------------------------------------------------------------------------------- 1 | drivers/pcieportal/dkms.conf.out 2 | -------------------------------------------------------------------------------- /debian/connectal.install: -------------------------------------------------------------------------------- 1 | /usr/bin/pcieflat 2 | /usr/share/connectal 3 | /usr/src/ 4 | -------------------------------------------------------------------------------- /debian/connectal.udev: -------------------------------------------------------------------------------- 1 | # UDev rules for setting up Bluespec emulation device drivers 2 | 3 | ACTION=="add",SUBSYSTEM=="pci",ATTR{vendor}=="0x1be7", ATTR{device}="0xb100", RUN+="/sbin/modprobe -ba pcieportal portalmem" 4 | KERNEL=="portal*",MODE="666" 5 | KERNEL=="portalmem",MODE="666" 6 | KERNEL=="connectal",MODE="666" 7 | -------------------------------------------------------------------------------- /debian/docs: -------------------------------------------------------------------------------- 1 | README.md 2 | -------------------------------------------------------------------------------- /debian/rules: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make -f 2 | # -*- makefile -*- 3 | # Sample debian/rules that uses debhelper. 4 | # 5 | # This file was originally written by Joey Hess and Craig Small. 6 | # As a special exception, when this file is copied by dh-make into a 7 | # dh-make output file, you may use that output file without restriction. 8 | # This special exception was added by Craig Small in version 0.37 of dh-make. 9 | # 10 | # Modified to make a template file for a multi-binary package with separated 11 | # build-arch and build-indep targets by Bill Allombert 2001 12 | 13 | # Uncomment this to turn on verbose mode. 14 | #export DH_VERBOSE=1 15 | 16 | # This has to be exported to make some magic below work. 17 | export DH_OPTIONS 18 | 19 | 20 | %: 21 | dh $@ --with dkms 22 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | all: 4 | make -C library html latexpdf 5 | -------------------------------------------------------------------------------- /doc/android-sdk-screenshots/android-sdk-license.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/doc/android-sdk-screenshots/android-sdk-license.png -------------------------------------------------------------------------------- /doc/android-sdk-screenshots/android-sdk-manager-log.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/doc/android-sdk-screenshots/android-sdk-manager-log.png -------------------------------------------------------------------------------- /doc/android-sdk-screenshots/android-sdk-manager.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/doc/android-sdk-screenshots/android-sdk-manager.png -------------------------------------------------------------------------------- /doc/generated/html/indication-only.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/doc/generated/html/indication-only.png -------------------------------------------------------------------------------- /doc/generated/html/request-response-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/doc/generated/html/request-response-1.png -------------------------------------------------------------------------------- /doc/ifdef.md: -------------------------------------------------------------------------------- 1 | --BSC 2 | 3 | ZYNQ is defined for the following platforms: [zc702,zedboard] 4 | PCIE is defined for the following platforms: [ac701, kc705, vc707] 5 | SIMULATION is defined for the following platforms: [bsim, bsim_pcie] 6 | 7 | --CPP 8 | 9 | ZYNQ is defined for the following platforms: [zedboard, zc702] 10 | -------------------------------------------------------------------------------- /doc/library/source/bsv/bsv.rst: -------------------------------------------------------------------------------- 1 | ======================= 2 | Connectal BSV Libraries 3 | ======================= 4 | 5 | .. toctree:: 6 | :maxdepth: 2 7 | :numbered: 8 | 9 | addressgenerator.rst 10 | arith.rst 11 | axistream.rst 12 | ctrlmux.rst 13 | hostinterface.rst 14 | leds.rst 15 | memportal.rst 16 | memreadengine.rst 17 | memtypes.rst 18 | mmu.rst 19 | pipe.rst 20 | portal.rst 21 | -------------------------------------------------------------------------------- /doc/library/source/bsv/ctrlmux.rst: -------------------------------------------------------------------------------- 1 | CtrlMux Package 2 | ===================== 3 | 4 | .. bsv:package:: CtrlMux 5 | 6 | .. bsv:module:: mkInterruptMux#(Vector#(numPortals,MemPortal#(aw,dataWidth)) portals)(ReadOnly#(Bool)) 7 | 8 | Used by BsimTop, PcieTop, and ZynqTop. Takes a vector of MemPortals and returns a boolean indicating whether any of the portals has indication method data available. 9 | 10 | .. bsv:module:: mkSlaveMux#(Vector#(numPortals,MemPortal#(aw,dataWidth)) portals)(PhysMemSlave#(addrWidth,dataWidth)) 11 | 12 | Takes a vector of MemPortals and returns a PhysMemSlave combining them. 13 | 14 | -------------------------------------------------------------------------------- /doc/library/source/bsv/leds.rst: -------------------------------------------------------------------------------- 1 | Leds Package 2 | ===================== 3 | 4 | .. bsv:package:: Leds 5 | 6 | .. bsv:interface:: LEDS 7 | 8 | .. bsv:typedef:: LedsWidth 9 | 10 | Defined to be the number of default LEDs on the FPGA board. 11 | 12 | The Zedboard has 8, Zc706 has 4, ... 13 | 14 | .. bsv:method:: Bit#(LedsWidth) leds() 15 | 16 | -------------------------------------------------------------------------------- /doc/library/source/bsv/memportal.rst: -------------------------------------------------------------------------------- 1 | MemPortal Package 2 | ================= 3 | 4 | .. bsv:package:: MemPortal 5 | 6 | 7 | mkMemPortal Module 8 | ------------------ 9 | 10 | .. bsv:module:: mkMemPortal#(Bit#(slaveDataWidth) ifcId, PipePortal#(numRequests, numIndications, slaveDataWidth) portal)(MemPortal#(slaveAddrWidth, slaveDataWidth)) 11 | 12 | Takes an interface identifier and a PipePortal and returns a MemPortal. 13 | 14 | -------------------------------------------------------------------------------- /doc/library/source/bsv/memreadengine.rst: -------------------------------------------------------------------------------- 1 | MemReadEngine Package 2 | ===================== 3 | 4 | .. bsv:package:: MemReadEngine 5 | 6 | .. bsv:module:: mkMemReadEngine(MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers)) 7 | 8 | Creates a MemReadEngine with default 256 bytes of buffer per server. 9 | 10 | .. bsv:module:: mkMemReadEngineBuff#(Integer bufferSizeBytes) (MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers)) 11 | 12 | Creates a MemReadEngine with the specified buffer size. 13 | 14 | -------------------------------------------------------------------------------- /doc/library/source/c/c.rst: -------------------------------------------------------------------------------- 1 | 2 | Connectal C/C++ Libraries 3 | ========================= 4 | 5 | .. toctree:: 6 | :maxdepth: 2 7 | :numbered: 8 | 9 | portal.rst 10 | -------------------------------------------------------------------------------- /doc/library/source/design/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: 3 | make -C images all 4 | -------------------------------------------------------------------------------- /doc/library/source/design/design.rst: -------------------------------------------------------------------------------- 1 | Connectal Design 2 | **************** 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | abstract.rst 8 | introduction.rst 9 | string-search.rst 10 | connectal-framework.rst 11 | implementing-string-search.rst 12 | toolchain.rst 13 | performance.rst 14 | related-work.rst 15 | conclusion.rst 16 | 17 | portalstructure.rst 18 | portal.rst 19 | interface_definitions.rst 20 | flowcontrol.rst 21 | host_interface.rst 22 | -------------------------------------------------------------------------------- /doc/library/source/design/flowcontrol.rst: -------------------------------------------------------------------------------- 1 | .. _flow_control: 2 | 3 | Flow Control 4 | ============ 5 | 6 | -------------------------------------------------------------------------------- /doc/library/source/design/host_interface.rst: -------------------------------------------------------------------------------- 1 | .. host_interface: 2 | 3 | Host Interface 4 | ============== 5 | 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-------------------------------------------------------------------------------- /doc/library/source/examples/simple.rst: -------------------------------------------------------------------------------- 1 | 2 | Simple Example 3 | ============== 4 | 5 | -------------------------------------------------------------------------------- /doc/library/source/index.rst: -------------------------------------------------------------------------------- 1 | .. connectal documentation master file, created by 2 | sphinx-quickstart on Tue Nov 25 12:27:26 2014. 3 | You can adapt this file completely to your liking, but it should at least 4 | contain the root `toctree` directive. 5 | 6 | ===================================== 7 | Welcome to connectal's documentation! 8 | ===================================== 9 | 10 | Contents 11 | -------- 12 | 13 | .. toctree:: 14 | :maxdepth: 2 15 | 16 | intro.rst 17 | installation.rst 18 | design/design.rst 19 | devguide/devguide.rst 20 | make.rst 21 | tools/tools.rst 22 | bsv/bsv.rst 23 | c/c.rst 24 | examples/index.rst 25 | 26 | Indices and tables 27 | ================== 28 | 29 | * :ref:`genindex` 30 | * :ref:`modindex` 31 | * :ref:`search` 32 | 33 | -------------------------------------------------------------------------------- /doc/library/source/intro.rst: -------------------------------------------------------------------------------- 1 | ============ 2 | Introduction 3 | ============ 4 | 5 | Introduction goes here. 6 | 7 | -------------------------------------------------------------------------------- /doc/library/source/make.rst: -------------------------------------------------------------------------------- 1 | ======================= 2 | Connectal Makefile Variables 3 | ======================= 4 | 5 | .. toctree:: 6 | :maxdepth: 2 7 | :numbered: 8 | 9 | makefile.connectal.rst 10 | makefile.connectal.build.rst 11 | -------------------------------------------------------------------------------- /doc/library/source/themes/connectal/layout.html: -------------------------------------------------------------------------------- 1 | {# 2 | connectal/layout.html 3 | ~~~~~~~~~~~~~~~~~~~ 4 | 5 | #} 6 | {%- extends "classic/layout.html" %} 7 | 8 | {% set script_files = script_files + ['_static/tracking.js'] %} 9 | -------------------------------------------------------------------------------- /doc/library/source/themes/connectal/static/tracking.js_t: -------------------------------------------------------------------------------- 1 | (function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){ 2 | (i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o), 3 | m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m) 4 | })(window,document,'script','//www.google-analytics.com/analytics.js','ga'); 5 | 6 | ga('create', 'UA-15845210-2', 'auto'); // Replace with your property ID. 7 | ga('send', 'pageview'); 8 | -------------------------------------------------------------------------------- /doc/library/source/themes/connectal/theme.conf: -------------------------------------------------------------------------------- 1 | [theme] 2 | inherit = classic 3 | 4 | -------------------------------------------------------------------------------- /doc/library/source/tools/generate-constraints.rst: -------------------------------------------------------------------------------- 1 | 2 | .. _invocation_generate-constraints.py 3 | 4 | Invocation of generate-constraints.py 5 | ======================= 6 | 7 | .. argparse:: 8 | :module: generate-constraints 9 | :func: newArgparser 10 | :prog: generate-constraints 11 | -------------------------------------------------------------------------------- /doc/library/source/tools/tools.rst: -------------------------------------------------------------------------------- 1 | ======================= 2 | Connectal Tools 3 | ======================= 4 | 5 | .. toctree:: 6 | :maxdepth: 2 7 | :numbered: 8 | 9 | makefilegen.rst 10 | generate-constraints.rst 11 | pcieflat.rst 12 | topgen.rst 13 | -------------------------------------------------------------------------------- /doc/library/source/tools/topgen.rst: -------------------------------------------------------------------------------- 1 | 2 | .. _invocation_topgen.py 3 | 4 | Invocation of topgen.py 5 | ======================= 6 | 7 | .. argparse:: 8 | :module: topgen 9 | :func: newArgparser 10 | :prog: topgen 11 | -------------------------------------------------------------------------------- /docker/Dockerfile: -------------------------------------------------------------------------------- 1 | FROM bsc-contrib:latest 2 | ADD . /build/ 3 | RUN apt update; apt-get -y install jq python python-ply rsync awscli 4 | ENV PATH /opt/bluespec/bin:$PATH 5 | ENV BLUESPECDIR /opt/bluespec/lib 6 | -------------------------------------------------------------------------------- /drivers/awsf1portal/Makefile.dkms: -------------------------------------------------------------------------------- 1 | obj-m += pcieportal.o 2 | obj-m += portalmem.o 3 | 4 | pcieportal-objs := portal.o libxdma.o xdma_cdev.o cdev_ctrl.o cdev_events.o cdev_sgdma.o cdev_xvc.o cdev_bypass.o xdma_mod.o 5 | pcieportal.ko: driverversion.h 6 | 7 | driverversion.h: 8 | echo "#define DRIVER_VERSION \"@VERSION@\"" > driverversion.h 9 | -------------------------------------------------------------------------------- /drivers/awsf1portal/dkms.conf: -------------------------------------------------------------------------------- 1 | PACKAGE_NAME="@PKG_NAME@" 2 | PACKAGE_VERSION="@VERSION@" 3 | BUILT_MODULE_NAME[0]="pcieportal" 4 | DEST_MODULE_LOCATION[0]="/extra/fpga" 5 | BUILT_MODULE_NAME[1]="portalmem" 6 | DEST_MODULE_LOCATION[1]="/extra/fpga" 7 | AUTOINSTALL="yes" 8 | -------------------------------------------------------------------------------- /drivers/awsf1portal/driverversion.h: -------------------------------------------------------------------------------- 1 | #define DRIVER_VERSION "" 2 | -------------------------------------------------------------------------------- /drivers/connectalsdhci/Makefile: -------------------------------------------------------------------------------- 1 | 2 | V?=0 3 | ifeq ($(V),0) 4 | Q=@ 5 | else 6 | Q= 7 | endif 8 | CONNECTALDIR ?= $(PWD)/../.. 9 | include $(CONNECTALDIR)/Makefile.version 10 | 11 | obj-m += connectalsdhci.o 12 | 13 | CROSS_COMPILE?=arm-linux-gnueabi- 14 | 15 | ccflags-y := -I$(src)/../portalmem -I$(src)/../../cpp -I$(PWD)/../.. -I$(src)/../../generated/cpp \ 16 | -DDRIVER_VERSION="KBUILD_STR($(VERSION))" 17 | 18 | connectalsdhci.ko: connectalsdhci.c 19 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) xilinx_zynq_portal_defconfig 20 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) oldconfig 21 | @$(MAKE) -j 8 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) zImage 22 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) modules 23 | 24 | clean: 25 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) clean 26 | -------------------------------------------------------------------------------- /drivers/connectalspi/Makefile: -------------------------------------------------------------------------------- 1 | 2 | V?=0 3 | ifeq ($(V),0) 4 | Q=@ 5 | else 6 | Q= 7 | endif 8 | CONNECTALDIR ?= $(PWD)/../.. 9 | include $(CONNECTALDIR)/Makefile.version 10 | 11 | obj-m += connectalspi.o 12 | 13 | CROSS_COMPILE?=arm-linux-gnueabi- 14 | 15 | ccflags-y := -I$(src)/../portalmem -I$(src)/../../cpp -I$(PWD)/../.. -I$(src)/../../generated/cpp \ 16 | -DDRIVER_VERSION="KBUILD_STR($(VERSION))" 17 | 18 | connectalspi.ko: connectalspi.c 19 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) xilinx_zynq_portal_defconfig 20 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) oldconfig 21 | @$(MAKE) -j 8 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) zImage 22 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) modules 23 | 24 | clean: 25 | @$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) clean 26 | -------------------------------------------------------------------------------- /drivers/pcieportal/Makefile.dkms: -------------------------------------------------------------------------------- 1 | obj-m += pcieportal.o 2 | obj-m += portalmem.o 3 | 4 | pcieportal.ko: driverversion.h 5 | 6 | driverversion.h: 7 | echo "#define DRIVER_VERSION \"@VERSION@\"" > driverversion.h 8 | -------------------------------------------------------------------------------- /drivers/pcieportal/dkms.conf: -------------------------------------------------------------------------------- 1 | PACKAGE_NAME="@PKG_NAME@" 2 | PACKAGE_VERSION="@VERSION@" 3 | BUILT_MODULE_NAME[0]="pcieportal" 4 | DEST_MODULE_LOCATION[0]="/extra/fpga" 5 | BUILT_MODULE_NAME[1]="portalmem" 6 | DEST_MODULE_LOCATION[1]="/extra/fpga" 7 | AUTOINSTALL="yes" 8 | -------------------------------------------------------------------------------- /drivers/pcieportal/driverversion.h: -------------------------------------------------------------------------------- 1 | #define DRIVER_VERSION "" 2 | -------------------------------------------------------------------------------- /etc/modules-load.d/connectal.conf: -------------------------------------------------------------------------------- 1 | portalmem 2 | -------------------------------------------------------------------------------- /etc/udev/rules.d/51-connectaltty.rules: -------------------------------------------------------------------------------- 1 | # For Ubuntu 12.04 2 | # zedboard 3 | SUBSYSTEM=="usb", ATTR{idVendor}=="04b4", ATTR{idProduct}=="0008", MODE="0666", OWNER="jenkins" 4 | KERNEL=="ttyACM*", ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="0008", MODE:="0666" 5 | # zc702 6 | SUBSYSTEM=="usb", ATTR{idVendor}=="10c4", ATTR{idProduct}=="ea60", MODE="0666", OWNER="jenkins" 7 | KERNEL=="ttyUSB*", ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea60", MODE:="0666" 8 | # zybo 9 | SUBSYSTEM=="usb", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE="0666", OWNER="jenkins" 10 | KERNEL=="ttyUSB*", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE:="0666" 11 | 12 | -------------------------------------------------------------------------------- /etc/udev/rules.d/52-altera-usb.rules: -------------------------------------------------------------------------------- 1 | 2 | # Allow users to access Altera Jtag device 3 | ACTION=="add", ATTR{idVendor}=="09fb", MODE:="666" 4 | -------------------------------------------------------------------------------- /etc/udev/rules.d/52-connectaltest.rules: -------------------------------------------------------------------------------- 1 | # 2 | # rule for connectal kernel test module 3 | # 4 | KERNEL=="connectaltest", MODE="0666" 5 | -------------------------------------------------------------------------------- /etc/udev/rules.d/99-pcieportal.rules: -------------------------------------------------------------------------------- 1 | # UDev rules for setting up Bluespec emulation device drivers 2 | 3 | ACTION=="add",SUBSYSTEM=="pci",ATTR{vendor}=="0x1be7", ATTR{device}="0xb100", RUN+="/sbin/modprobe -ba pcieportal portalmem" 4 | KERNEL=="portal*",MODE="666" 5 | KERNEL=="xdma*",MODE="666" 6 | KERNEL=="portalmem",MODE="666" 7 | KERNEL=="connectal",MODE="666" 8 | -------------------------------------------------------------------------------- /examples/algo1_nandsim/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | 4 | S2H_INTERFACES = NandCfgRequest:Algo1NandSim.nandCfgRequest MMURequest:Algo1NandSim.nandMMURequest MemServerRequest:Algo1NandSim.nandMemServerRequest StrstrRequest:Algo1NandSim.strstrRequest 5 | H2S_INTERFACES = Algo1NandSim:NandCfgIndication,MMUIndication,MemServerIndication,StrstrIndication 6 | MEM_READ_INTERFACES = lAlgo1NandSim.dmaReadClients 7 | MEM_WRITE_INTERFACES = lAlgo1NandSim.dmaWriteClients 8 | 9 | BSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv Algo1NandSim.bsv 10 | CPPFILES=test.cpp nandsim.cpp 11 | 12 | CONNECTALFLAGS += -D ALGO_NANDSIM 13 | CONNECTALFLAGS += -D DEGPAR=2 14 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/strstr/cpp 15 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp 16 | 17 | 18 | include $(CONNECTALDIR)/Makefile.connectal 19 | -------------------------------------------------------------------------------- /examples/algo1_nandsim/test.bin: -------------------------------------------------------------------------------- 1 | acabcabacababacababababababcacabcabacababacabababc 2 | 012345678912 3 | -------------------------------------------------------------------------------- /examples/algo2_nandsim/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = NandCfgRequest RegexpRequest NandCfgIndication RegexpIndication 4 | BSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv $(CONNECTALDIR)/lib/regexp/bsv/Regexp.bsv $(CONNECTALDIR)/lib/nandsim/bsv/NandSimNames.bsv Top.bsv 5 | CPPFILES=test.cpp 6 | CPPFILES2=../nandsim/testnandsim.cpp 7 | CONNECTALFLAGS += -D HAYSTACKREADCLIENTS=1 8 | CONNECTALFLAGS += -D DEGPAR=4 -D MAX_NUM_STATES=32 -D MAX_NUM_CHARS=32 9 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/regexp/cpp 10 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp 11 | CONNECTALFLAGS += -D ALGO_NANDSIM 12 | 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /examples/algo2_nandsim/jregexp.charMap: -------------------------------------------------------------------------------- 1 |   2 |   -------------------------------------------------------------------------------- /examples/algo2_nandsim/jregexp.stateMap: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/examples/algo2_nandsim/jregexp.stateMap -------------------------------------------------------------------------------- /examples/algo2_nandsim/jregexp.stateTransitions: -------------------------------------------------------------------------------- 1 |      2 |         -------------------------------------------------------------------------------- /examples/aurora/aurora-clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name user_clk -period "6.4" [get_ports "userClk_p"] 2 | create_clock -name mgtref_clk -period "6.4" [get_ports "mgtRefClk_p"] 3 | -------------------------------------------------------------------------------- /examples/aurora/aurora.json: -------------------------------------------------------------------------------- 1 | { 2 | "userClk_p": { 3 | "IOSTANDARD": "LVDS_25", 4 | "DIFF_TERM": "TRUE", 5 | "fmc": "userClk_p" 6 | }, 7 | "userClk_n": { 8 | "IOSTANDARD": "LVDS_25", 9 | "DIFF_TERM": "TRUE", 10 | "fmc": "userClk_n" 11 | }, 12 | "smaUserClk_p": { 13 | "IOSTANDARD": "LVDS_25", 14 | "DIFF_TERM": "TRUE", 15 | "fmc": "smaUserClk_p" 16 | }, 17 | "smaUserClk_n": { 18 | "IOSTANDARD": "LVDS_25", 19 | "DIFF_TERM": "TRUE", 20 | "fmc": "smaUserClk_n" 21 | }, 22 | "mgtRefClk_p": { 23 | "DIFF_TERM": "TRUE", 24 | "fmc": "mgtRefClk_p" 25 | }, 26 | "mgtRefClk_n": { 27 | "DIFF_TERM": "TRUE", 28 | "fmc": "mgtRefClk_n" 29 | }, 30 | "mgtRx_p": { 31 | "fmc": "mgtRx_p" 32 | }, 33 | "mgtRx_n": { 34 | "fmc": "mgtRx_n" 35 | }, 36 | "mgtTx_p": { 37 | "fmc": "mgtTx_p" 38 | }, 39 | "mgtTx_n": { 40 | "fmc": "mgtTx_n" 41 | } 42 | } -------------------------------------------------------------------------------- /examples/aurora/clock.tcl: -------------------------------------------------------------------------------- 1 | ## disconnect unused CLK and RST ports inserted by bsc 2 | foreach {pat} {CLK_GATE*} { 3 | puts $pat 4 | puts ports 5 | puts [get_ports $pat] 6 | puts nets 7 | puts [get_nets $pat] 8 | foreach {net} [get_nets $pat] { 9 | disconnect_net -net $net -objects [get_pins -of_objects $net] 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /examples/aurora/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source board.tcl 2 | source $connectaldir/scripts/connectal-synth-ip.tcl 3 | 4 | connectal_synth_ip aurora_64b66b 9.2 aurora_64b66b_0 [list CONFIG.interface_mode {Framing} CONFIG.C_GT_LOC_5 {1} CONFIG.C_GT_LOC_1 {X}] 5 | -------------------------------------------------------------------------------- /examples/bscan/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = BscanRequest:BscanIF.request:host 3 | H2S_INTERFACES = BscanIF:BscanIndication:host 4 | 5 | BSVFILES = BscanIF.bsv 6 | CPPFILES=testbscan.cpp 7 | CONNECTALFLAGS += -D IMPORT_HOSTIF 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | 11 | -------------------------------------------------------------------------------- /examples/caffe/INSTALL: -------------------------------------------------------------------------------- 1 | 2 | cmake 3 | libboost-all-dev 4 | libgoogle-glog-dev 5 | libprotobuf-dev protobuf-compiler 6 | libhdf5-dev 7 | liblmdb-dev 8 | libleveldb-dev 9 | libsnappy-dev 10 | libopencv-dev 11 | libatlas-dev 12 | libatlas-blas-dev 13 | libblas-dev 14 | libopenblas-dev 15 | libatlas-base-dev 16 | libpapi-dev 17 | -------------------------------------------------------------------------------- /examples/caffe/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ConvRequest:Conv.request 3 | H2S_INTERFACES = Conv:ConvIndication 4 | MEM_READ_INTERFACES = lConv.readDma 5 | MEM_WRITE_INTERFACES = lConv.writeDma 6 | 7 | # Direct convolution/gradient calculation version 8 | CPPFILES = $(CONNECTALDIR)/lib/cpp/connectal_conv.cpp 9 | BSVFILES = Conv.bsv 10 | CONNECTALFLAGS += --shared --bsvpath $(CONNECTALDIR)/lib/matmul/bsv 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /examples/caffe/README.md: -------------------------------------------------------------------------------- 1 | apt-get install libopencv-dev libopencv-core-dev 2 | apt-get install autoconf 3 | apt-get install libtool 4 | apt-get install gtkwave 5 | apt-get install cmake 6 | apt-get install boost 7 | apt-get install libboost-dev 8 | apt-get install libboost-system 9 | apt-get install libboost-system-dev libboost-thread-dev 10 | apt-get install libgoogle-glog-dev glib-dev 11 | apt-get install libgoogle-glog-dev 12 | apt-get install libhdf5-dev 13 | apt-get install liblmdb-dev 14 | apt-get install libleveldb-dev 15 | apt-get install libsnappy-dev 16 | apt-get install libatlas-dev 17 | apt-get install libopenblas-dev 18 | apt-get install libatlas-dev libblas-test libopenblas-dev libatlas-cpp-0.6-dev libatlas-base-dev 19 | apt-get install python-numpy 20 | apt-get install libboost-python-dev 21 | apt-get install python-numpy 22 | apt-get install gfortran 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /examples/echo/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv 6 | CPPFILES= testecho.cpp 7 | 8 | CONNECTALFLAGS += -D TRACE_PORTAL 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | 12 | -------------------------------------------------------------------------------- /examples/echo2ind/Makefile: -------------------------------------------------------------------------------- 1 | # Test program for multiple interfaces of same datatype 2 | CONNECTALDIR?=../.. 3 | S2H_INTERFACES = EchoRequest:Echo.request1,Echo.request2 4 | H2S_INTERFACES = Echo:EchoIndication,EchoIndication 5 | 6 | BSVFILES = Echo.bsv 7 | CPPFILES= testecho.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | 11 | -------------------------------------------------------------------------------- /examples/echofast/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALFLAGS += -D BSV_POSITIVE_RESET 2 | 3 | ifeq ($(BOARD),zedboard) 4 | MAIN_CLOCK_PERIOD=5.0 5 | DERIVED_CLOCK_PERIOD=10.0 6 | endif 7 | ifeq ($(BOARD),zc706) 8 | MAIN_CLOCK_PERIOD=2.0 9 | DERIVED_CLOCK_PERIOD=5.0 10 | endif 11 | 12 | include ../echo/Makefile 13 | -------------------------------------------------------------------------------- /examples/echohost/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request:host 3 | H2S_INTERFACES = Echo:EchoIndication:host 4 | 5 | BSVFILES = ../echo/Echo.bsv 6 | CPPFILES= ../echo/testecho.cpp 7 | ## for testing fpgamake: 8 | FPGAMAKE_CONNECTALFLAGS += -P mkEchoIndicationProxySynth -P mkEchoRequestWrapperMemPortalPipes 9 | PORTAL_DUMP_MAP = "EchoIndication:EchoRequest:SwallowRequest" 10 | CONNECTALFLAGS += -D IMPORT_HOSTIF 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /examples/echoinvert/EchoInterface.bsv: -------------------------------------------------------------------------------- 1 | 2 | interface EchoIndication; 3 | method Action heard(Bit#(32) v); 4 | method Action heard2(Bit#(16) a, Bit#(16) b); 5 | endinterface 6 | 7 | interface EchoRequest; 8 | method Action say(Bit#(32) v); 9 | method Action say2(Bit#(16) a, Bit#(16) b); 10 | method Action setLeds(Bit#(8) v); 11 | endinterface 12 | -------------------------------------------------------------------------------- /examples/echoinvert/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = !Echo:EchoIndication 4 | 5 | BSVFILES = EchoInterface.bsv 6 | CPPFILES= testecho.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | 10 | -------------------------------------------------------------------------------- /examples/echojson/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv Swallow.bsv 6 | CPPFILES=testecho.cpp 7 | CPPFILES2=daemon.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /examples/echojsonpy/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv Swallow.bsv 6 | CPPFILES=daemon.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /examples/echomux/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = EchoRequestSW EchoIndicationSW SecondRequest SecondIndication ThirdRequest ThirdIndication 3 | S2H_INTERFACES = EchoRequest:Echo.request 4 | H2S_INTERFACES = Echo:EchoIndication 5 | 6 | BSVFILES = Echo.bsv Services.bsv 7 | CPPFILES=testecho.cpp 8 | CPPFILES2=daemon.cpp 9 | AUTOTOP = --portname IfcNames_SecondRequest --portname IfcNames_SecondIndication --portname IfcNames_ThirdRequest --portname IfcNames_ThirdIndication 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/echoproto/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | CPPFILES=testecho.cpp 6 | #CONNECTALFLAGS += --protobuf interface.json 7 | CONNECTALFLAGS += --protobuf echo_pb.json 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | 11 | prebuild:: 12 | $(CONNECTALDIR)/../protobuf/src/protoc --cpp_out=. --bsv_out=. echo.proto 13 | -------------------------------------------------------------------------------- /examples/echoproto/echo.proto: -------------------------------------------------------------------------------- 1 | syntax = "proto2"; 2 | package echo; 3 | 4 | message EchoSay { 5 | required fixed32 v = 1; 6 | } 7 | message EchoSay2 { 8 | required fixed32 a = 1; 9 | required fixed32 b = 2; 10 | } 11 | message EchoLeds { 12 | required fixed32 v = 1; 13 | } 14 | message EchoHeard { 15 | required fixed32 v = 1; 16 | } 17 | message EchoHeard2 { 18 | required fixed32 a = 1; 19 | required fixed32 b = 2; 20 | } 21 | 22 | message Empty { 23 | } 24 | 25 | service EchoRequest { 26 | rpc say (EchoSay) returns (Empty); 27 | rpc say2 (EchoSay2) returns (Empty); 28 | rpc setLeds (EchoLeds) returns (Empty); 29 | } 30 | service EchoIndication { 31 | rpc heard (EchoHeard) returns (Empty); 32 | rpc heard2 (EchoHeard2) returns (Empty); 33 | } 34 | -------------------------------------------------------------------------------- /examples/echopy/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoResponse 4 | 5 | BSVFILES = EchoInterface.bsv 6 | PYFILES = testecho.py 7 | 8 | CONNECTALFLAGS += --run-args="$(PWD)/testecho.py $(CONNECTALDIR)/scripts/portal.py $(PWD)/$(BOARD)/bin/connectal.so" 9 | CONNECTALFLAGS += -D PYTHONPATH="$(CONNECTALDIR)/scripts:." -D CONNECTALDIR="$(CONNECTALDIR)" 10 | 11 | ifeq ($(BOARD),zedboard_ubuntu) 12 | prebuild:: 13 | ./ubuntu-python-dev.sh 14 | endif 15 | 16 | include $(CONNECTALDIR)/Makefile.connectal 17 | -------------------------------------------------------------------------------- /examples/echopy/ubuntu-python-dev.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | for path in p/python2.7/libpython2.7_2.7.11-7ubuntu1_armhf p/python2.7/libpython2.7-dev_2.7.11-7ubuntu1_armhf libj/libjsoncpp/libjsoncpp1_1.7.2-1_armhf libj/libjsoncpp/libjsoncpp-dev_1.7.2-1_armhf; do 4 | pkg=`basename $path` 5 | [ -f $pkg.deb ] || ( 6 | wget http://ports.ubuntu.com/ubuntu-ports/pool/main/$path.deb; 7 | ar x $pkg.deb; 8 | xzcat data.tar.xz | tar -xvf - 9 | ) 10 | done 11 | sed -i "s|#define _POSIX_C_SOURCE 200112L|/* _POSIX_C_SOURCE defined by features.h*/|" usr/include/arm-linux-gnueabihf/python2.7/pyconfig.h 12 | sed -i "s|#define _XOPEN_SOURCE 600|/* _XOPEN_SOURCE defined by features.h*/|" usr/include/arm-linux-gnueabihf/python2.7/pyconfig.h 13 | rm -f data.tar.xz control.tar.gz debian-binary 14 | -------------------------------------------------------------------------------- /examples/echoshared/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | INTERFACES = MMURequest MMUIndication MemServerRequest MemServerIndication 5 | 6 | BSVFILES = Echo.bsv $(CONNECTALDIR)/bsv/ConnectalMemory.bsv 7 | CPPFILES=testecho.cpp $(CONNECTALDIR)/cpp/transportShared.c $(CONNECTALDIR)/cpp/dmaManager.c 8 | CPPFILES2=daemon.cpp $(CONNECTALDIR)/cpp/transportShared.c $(CONNECTALDIR)/cpp/dmaManager.c 9 | AUTOTOP = --portname MMURequestS2H --portname MMUIndicationH2S 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/echoslow/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication:host.derivedClock,host.derivedReset 4 | 5 | BSVFILES = Echo.bsv 6 | CPPFILES= ../echo/testecho.cpp 7 | CONNECTALFLAGS += -D IMPORT_HOST_CLOCKS 8 | CONNECTALFLAGS += --derivedclockperiod=125 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/echosoft/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv Swallow.bsv 6 | CPPFILES=testecho.cpp 7 | CPPFILES2=daemon.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /examples/echotrace/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = MMURequest 3 | S2H_INTERFACES = EchoRequest:Echo.request 4 | H2S_INTERFACES = Echo:EchoIndication 5 | 6 | BSVFILES = Echo.bsv $(CONNECTALDIR)/bsv/ConnectalMemory.bsv 7 | CPPFILES=testecho.cpp $(CONNECTALDIR)/cpp/transportShared.c $(CONNECTALDIR)/cpp/dmaManager.c 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /examples/echowebsocket/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv Swallow.bsv 6 | CPPFILES=testecho.cpp $(CONNECTALDIR)/cpp/portalWebSocket.c 7 | CPPFILES2=daemon.cpp $(CONNECTALDIR)/cpp/portalWebSocket.c 8 | CONNECTALFLAGS += -lwebsockets 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/fmcomms1/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | INTERFACES = FMComms1Request FMComms1Indication \ 4 | BlueScopeEventPIORequest BlueScopeEventPIOIndication 5 | 6 | BSVFILES = ../../lib/bsv/BlueScopeEventPIO.bsv \ 7 | FMComms1ADC.bsv FMComms1DAC.bsv FMComms1.bsv \ 8 | Top.bsv 9 | CPPFILES=testfmcomms1.cpp fmci2c.c i2c_zedboardandroid.c 10 | CONNECTALFLAGS = -C fmcomms1-$(BOARD).xdc --tcl clock.tcl 11 | CONNECTALFLAGS += -D USE_FMC_I2C1 -D IMPORT_HOSTIF 12 | PIN_TYPE = FMComms1Pins 13 | PIN_TYPE_INCLUDE = FMComms1Pins 14 | 15 | ifeq ($(BOARD),zedboard) 16 | HAS_PS7=true 17 | #CONNECTALFLAGS += -D USE_I2C0 18 | endif 19 | ifeq ($(BOARD),zc702) 20 | HAS_PS7=true 21 | endif 22 | 23 | USER_PIN_BINDINGS ?= --pin-binding fmc:fmc1 24 | 25 | gentarget:: fmcomms1-$(BOARD).xdc 26 | 27 | fmcomms1-$(BOARD).xdc: fmcomms1-fmc.json $(CONNECTALDIR)/boardinfo/$(BOARD).json 28 | $(CONNECTALDIR)/scripts/generate-constraints.py $(USER_PIN_BINDINGS) -o fmcomms1-$(BOARD).xdc --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile fmcomms1-fmc.json 29 | 30 | include $(CONNECTALDIR)/Makefile.connectal 31 | -------------------------------------------------------------------------------- /examples/fmcomms1/clock.tcl: -------------------------------------------------------------------------------- 1 | ## disconnect unused CLK and RST ports inserted by bsc 2 | foreach {pat} {CLK_GATE_* CLK_pins_spi_clock} { 3 | foreach {net} [get_nets $pat] { 4 | disconnect_net -net $net -objects [get_pins -of_objects $net] 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /examples/fmcomms1/i2c_zedboardandroid.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file i2c_zedboardandroid.h 3 | * @brief ZYNQ Hardware I2C header file. 4 | * 5 | ******************************************************************************* 6 | * API copied from i2c_ps7.h 7 | * Copyright 2011(c) Analog Devices, Inc. 8 | */ 9 | 10 | #include 11 | 12 | uint32_t I2C_Init(const char * devfile, uint32_t i2cAddr); 13 | 14 | uint32_t I2C_Read(uint32_t i2cAddr, uint32_t regAddr, uint32_t rxSize, uint8_t* rxBuf); 15 | 16 | uint32_t I2C_Write(uint32_t i2cAddr, uint32_t regAddr, uint32_t txSize, uint8_t* txBuf); 17 | 18 | -------------------------------------------------------------------------------- /examples/gyro_simple/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | S2H_INTERFACES = GyroCtrlRequest:GyroController.req 3 | H2S_INTERFACES = GyroController:GyroCtrlIndication 4 | MEM_WRITE_INTERFACES = cons\(lGyroController.dmaClient,nil\) 5 | INTERFACES = GyroSampleStream 6 | 7 | AUTOTOP = --interface pins:GyroController.pins --portname IfcNames_GyroSampleStream 8 | ZBR = $(CONNECTALDIR)/lib/zedboard_robot 9 | BSVFILES = $(ZBR)/bsv/GyroController.bsv 10 | CPPFILES = test_gyro.cpp $(ZBR)/cpp/read_buffer.cpp 11 | 12 | PIN_TYPE = GyroSimplePins 13 | PIN_TYPE_INCLUDE = GyroController 14 | PINOUT_FILE = pinout.json 15 | PIN_BINDINGS = pmod:pmodd 16 | 17 | include $(CONNECTALDIR)/Makefile.connectal 18 | -------------------------------------------------------------------------------- /examples/gyro_simple/clock.tcl: -------------------------------------------------------------------------------- 1 | ## disconnect unused CLK and RST ports inserted by bsc 2 | foreach {pat} {CLK_GATE_* CLK_clock} { 3 | foreach {net} [get_nets $pat] { 4 | puts "disconnecting net $net" 5 | disconnect_net -net $net -objects [get_pins -of_objects $net] 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /examples/gyrospi/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | S2H_INTERFACES = STestRequest:STest.request 3 | H2S_INTERFACES = STest:STestIndication 4 | 5 | BSVFILES = STest.bsv 6 | CPPFILES = testspi.cpp 7 | 8 | PIN_TYPE = STestPins 9 | PIN_TYPE_INCLUDE = STest 10 | PINOUT_FILE = pinout.json 11 | PIN_BINDINGS = pmod:pmodd 12 | 13 | AUTOTOP = --interface pins:STest.pins 14 | 15 | include $(CONNECTALDIR)/Makefile.connectal 16 | -------------------------------------------------------------------------------- /examples/gyrospi/pinout.json: -------------------------------------------------------------------------------- 1 | { 2 | "spi_sel_n": { 3 | "PIO_DIRECTION": "OUTPUT", 4 | "pmod": "J1" 5 | }, 6 | "spi_mosi": { 7 | "PIO_DIRECTION": "OUTPUT", 8 | "pmod": "J2" 9 | }, 10 | "spi_miso_v": { 11 | "PIO_DIRECTION": "INPUT", 12 | "pmod": "J3" 13 | }, 14 | "CLK_spi_clock": { 15 | "PIO_DIRECTION": "OUTPUT", 16 | "pmod": "J4" 17 | } 18 | } 19 | 20 | 21 | -------------------------------------------------------------------------------- /examples/hbridge_simple/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | S2H_INTERFACES = HBridgeCtrlRequest:HBridgeController.req 3 | H2S_INTERFACES = HBridgeController:HBridgeCtrlIndication 4 | 5 | ZBLD = $(CONNECTALDIR)/lib/zedboard_robot/bsv 6 | BSVFILES = $(ZBLD)/HBridgeController.bsv 7 | CPPFILES= test_hbridge.cpp 8 | 9 | PIN_TYPE = HBridgeSimplePins 10 | PIN_TYPE_INCLUDE = HBridgeController 11 | PINOUT_FILE = pinout.json 12 | PIN_BINDINGS = pmod:pmodc 13 | AUTOTOP = --interface pins:HBridgeController.pins 14 | 15 | include $(CONNECTALDIR)/Makefile.connectal 16 | -------------------------------------------------------------------------------- /examples/hdmidisplay/TestHdmi.pro: -------------------------------------------------------------------------------- 1 | 2 | QT += core gui 3 | 4 | TARGET = Hdmi 5 | TEMPLATE = lib 6 | CONFIG += sharedlib 7 | 8 | HEADERS += worker.h 9 | SOURCES += qtmain.cpp 10 | -------------------------------------------------------------------------------- /examples/hdmidisplay/hdmi.json: -------------------------------------------------------------------------------- 1 | { 2 | "CLK_hdmi_clock_if": { 3 | "hdmi": "clock" 4 | }, 5 | "hdmi_hsync": { 6 | "hdmi": "hsync" 7 | }, 8 | "hdmi_vsync": { 9 | "hdmi": "vsync" 10 | }, 11 | "hdmi_de": { 12 | "hdmi": "de" 13 | }, 14 | "hdmi_data[0]": { "hdmi": "data[0]" }, 15 | "hdmi_data[1]": { "hdmi": "data[1]" }, 16 | "hdmi_data[2]": { "hdmi": "data[2]" }, 17 | "hdmi_data[3]": { "hdmi": "data[3]" }, 18 | "hdmi_data[4]": { "hdmi": "data[4]" }, 19 | "hdmi_data[5]": { "hdmi": "data[5]" }, 20 | "hdmi_data[6]": { "hdmi": "data[6]" }, 21 | "hdmi_data[7]": { "hdmi": "data[7]" }, 22 | "hdmi_data[8]": { "hdmi": "data[8]" }, 23 | "hdmi_data[9]": { "hdmi": "data[9]" }, 24 | "hdmi_data[10]": { "hdmi": "data[10]" }, 25 | "hdmi_data[11]": { "hdmi": "data[11]" }, 26 | "hdmi_data[12]": { "hdmi": "data[12]" }, 27 | "hdmi_data[13]": { "hdmi": "data[13]" }, 28 | "hdmi_data[14]": { "hdmi": "data[14]" }, 29 | "hdmi_data[15]": { "hdmi": "data[15]" } 30 | } 31 | -------------------------------------------------------------------------------- /examples/hdmidisplay/hdmidisplay-bluesim.xdc: -------------------------------------------------------------------------------- 1 | ## intentionally blank 2 | -------------------------------------------------------------------------------- /examples/hdmidisplay/hdmidisplay-vc707.xdc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /examples/hdmidisplay/i2c.json: -------------------------------------------------------------------------------- 1 | { 2 | "I2C0_scl": { 3 | "i2c0": "scl" 4 | }, 5 | "I2C0_sda": { 6 | "i2c0": "sda" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /examples/imageon/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ImageonSerdesRequest:ImageonCapture.serdes_request HdmiGeneratorRequest:ImageonCapture.hdmi_request ImageonCaptureRequest:ImageonCapture.capture_request 3 | H2S_INTERFACES = ImageonCapture:ImageonSerdesIndication,HdmiGeneratorIndication,ImageonCaptureIndication 4 | MEM_WRITE_INTERFACES = lImageonCapture.dmaClient 5 | 6 | BSVFILES = $(CONNECTALDIR)/lib/bsv/IserdesDatadeserIF.bsv $(CONNECTALDIR)/lib/bsv/HDMI.bsv ImageonCapture.bsv 7 | CPPFILES=testimagecapture.cpp 8 | CONNECTALFLAGS = -D USE_I2C1 9 | PINOUT_FILE += imageon-fmc.json 10 | PIN_TYPE = ImageonCapturePins 11 | PIN_TYPE_INCLUDE = ImageonCapturePins 12 | ifeq ($(BOARD),zedboard) 13 | CONNECTALFLAGS += -D USE_I2C0 14 | PINOUT_FILE += imageon-zedboard.json 15 | PIN_BINDINGS ?= fmc:fmc1 16 | else 17 | PIN_BINDINGS ?= fmc:fmc2 18 | endif 19 | CONNECTALFLAGS += -C imageon-clocks.xdc --tcl clock.tcl 20 | AUTOTOP = --interface pins:ImageonCapture.pins 21 | 22 | include $(CONNECTALDIR)/Makefile.connectal 23 | -------------------------------------------------------------------------------- /examples/imageon/Makefile.dump: -------------------------------------------------------------------------------- 1 | 2 | all: 3 | gcc -Wall -o dump_image dump_image.cpp 4 | 5 | fetchdata: 6 | adb -s 172.17.1.165:5555 pull /mnt/sdcard/tmp.outfile pixeldata.dat 7 | -------------------------------------------------------------------------------- /examples/imageon/clock.tcl: -------------------------------------------------------------------------------- 1 | ## disconnect unused CLK and RST ports inserted by bsc 2 | foreach {pat} {CLK_GATE_* CLK_pins_spi_clock} { 3 | foreach {net} [get_nets $pat] { 4 | puts "disconnecting net $net" 5 | disconnect_net -net $net -objects [get_pins -of_objects $net] 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /examples/imageon/imageon-clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name video_clk -period "10" [get_ports "fmc_video_clk1_v"] 2 | create_clock -name serpins_clk -period "10" [get_ports "serpins_io_vita_clk_p_v"] 3 | create_clock -name spi_clk -period "100" [get_pins "ts_0/lImageonCapture_spiController_clockDivider/cntr_reg[9]/Q"] 4 | 5 | -------------------------------------------------------------------------------- /examples/imageon/imageon-zedboard.json: -------------------------------------------------------------------------------- 1 | { 2 | "I2C0_scl": { 3 | "i2c0": "scl" 4 | }, 5 | "I2C0_sda": { 6 | "i2c0": "sda" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /examples/leds/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = LedControllerRequest:LedController.request 3 | 4 | BSVFILES = LedController.bsv 5 | CPPFILES= testleds.cpp 6 | 7 | PIN_TYPE = LedPins 8 | PIN_TYPE_INCLUDE = LedController 9 | PINOUT_FILE = pinout.json 10 | AUTOTOP = --interface pins:LedController.leds 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /examples/leds/pinout.json: -------------------------------------------------------------------------------- 1 | { 2 | "leds[0]" : { 3 | "PIO_DIRECTION": "OUTPUT", 4 | "leds" : "L0" 5 | }, 6 | "leds[1]" : { 7 | "PIO_DIRECTION": "OUTPUT", 8 | "leds" : "L1" 9 | }, 10 | "leds[2]" : { 11 | "PIO_DIRECTION": "OUTPUT", 12 | "leds" : "L2" 13 | }, 14 | "leds[3]" : { 15 | "PIO_DIRECTION": "OUTPUT", 16 | "leds" : "L3" 17 | }, 18 | "leds[4]" : { 19 | "PIO_DIRECTION": "OUTPUT", 20 | "leds" : "L4" 21 | }, 22 | "leds[5]" : { 23 | "PIO_DIRECTION": "OUTPUT", 24 | "leds" : "L5" 25 | }, 26 | "leds[6]" : { 27 | "PIO_DIRECTION": "OUTPUT", 28 | "leds" : "L6" 29 | }, 30 | "leds[7]" : { 31 | "PIO_DIRECTION": "OUTPUT", 32 | "leds" : "L7" 33 | } 34 | } 35 | 36 | 37 | -------------------------------------------------------------------------------- /examples/linking/GetInverse.v: -------------------------------------------------------------------------------- 1 | 2 | `ifdef BSV_ASSIGNMENT_DELAY 3 | `else 4 | `define BSV_ASSIGNMENT_DELAY 5 | `endif 6 | 7 | `ifdef BSV_POSITIVE_RESET 8 | `define BSV_RESET_VALUE 1'b1 9 | `define BSV_RESET_EDGE posedge 10 | `else 11 | `define BSV_RESET_VALUE 1'b0 12 | `define BSV_RESET_EDGE negedge 13 | `endif 14 | 15 | module GetInverse(CLK, 16 | RST, 17 | 18 | get, 19 | EN_get, 20 | RDY_get, 21 | 22 | put, 23 | EN_put, 24 | RDY_put 25 | ); 26 | parameter DATA_WIDTH = 1; 27 | 28 | input CLK; 29 | input RST; 30 | output [DATA_WIDTH-1,0] get; 31 | input [DATA_WIDTH-1,0] put; 32 | input EN_get; 33 | input EN_put; 34 | output RDY_get; 35 | output RDY_put; 36 | 37 | // will this work? 38 | assign get = put; 39 | assign RDY_get = EN_put; 40 | assign RDY_put = EN_get; 41 | 42 | endmodule // GetInverse 43 | -------------------------------------------------------------------------------- /examples/linking/Makefile: -------------------------------------------------------------------------------- 1 | clean: 2 | rm -f mk*.v *.b[iao] 3 | -------------------------------------------------------------------------------- /examples/linking/Processor.bsv: -------------------------------------------------------------------------------- 1 | interface Cache; 2 | interface Put#(CacheRequest) request; 3 | interface Get#(CacheResponse) response; 4 | endinterface 5 | 6 | // we want to be able to synthesize this, but it has interface parameters 7 | module mkProcessor#(Cache cache, Peripherals peripherals)(Processor); 8 | rule foo; 9 | cache.request.put(req); 10 | endrule 11 | rule bar; 12 | let response <- cache.response.get(); 13 | endrule 14 | endmodule 15 | 16 | // original top level 17 | module mkTopLevel(Pins); 18 | Memory memory <- mkMemory(); 19 | Cache cache <- mkCache(memory); // standard parameter use example 20 | 21 | Vector#(NumProcessors,Processor) processors <- replicateM(mkProcessor(cache)); // 22 | 23 | Vector#(NumCaches, Memory) mems <- replicateM(mkMemory); 24 | Vector#(NumCaches, Cache) caches <- mapM(mkCache, mems); 25 | 26 | interface pins = memory.pins; 27 | endmodule 28 | -------------------------------------------------------------------------------- /examples/linking/ProcessorTop.bsv: -------------------------------------------------------------------------------- 1 | import Processor_Generated::*; 2 | 3 | //==================================================================================================================== 4 | 5 | module mkProcessorTop(Pins); 6 | Memory memory <- mkMemory(); 7 | Cache cache <- mkCache(memory); // actually uses the wrapper from Processor_Generated.bsv 8 | 9 | Vector#(NumProcessors,Processor) processors <- replicateM(mkProcessor(cache)); // same here 10 | 11 | Vector#(NumCaches, Memory) mems <- replicateM(mkMemory); 12 | Vector#(NumCaches, Cache) caches <- mapM(mkCache, mems); // and here 13 | 14 | interface mod; 15 | interface Pins pins = memory.pins; 16 | endinterface 17 | endmodule 18 | -------------------------------------------------------------------------------- /examples/matmul/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 4 | 5 | MMDIR=../matmul 6 | RBMDIR=../rbm 7 | TESTCPPFILES=testmm.cpp 8 | CONNECTALFLAGS = -D J_VALUE=1 -D K_VALUE=1 -D N_VALUE=1 -D DataBusWidth=32 9 | 10 | include $(MMDIR)/Makefile.mm 11 | include $(MMDIR)/Makefile.mmif 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /examples/matmul/Makefile.mmif: -------------------------------------------------------------------------------- 1 | S2H_INTERFACES += MmRequestTN:MatrixTN.mmRequest:host TimerRequest:MatrixTN.timerRequest 2 | H2S_INTERFACES += MatrixTN\#\(TDiv\#\(DataBusWidth,32\)\):MmIndication,TimerIndication:host 3 | MEM_READ_INTERFACES = lMatrixTN.readClients 4 | MEM_WRITE_INTERFACES = lMatrixTN.writeClients 5 | 6 | -------------------------------------------------------------------------------- /examples/matmul/clocks.tcl: -------------------------------------------------------------------------------- 1 | 2 | foreach {pat} {CLK_GATE_hdmi_clock_if CLK_*deleteme_unused_clock* CLK_GATE_*deleteme_unused_clock* RST_N_*deleteme_unused_reset*} { 3 | foreach {net} [get_nets $pat] { 4 | disconnect_net -net $net -objects [get_pins -of_objects $net] 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /examples/matmul/mkZynqTop_flpn.xdc: -------------------------------------------------------------------------------- 1 | create_pblock mmtile_0 2 | resize_pblock mmtile_0 -add {SLICE_X96Y270:SLICE_X171Y335 DSP48_X4Y108:DSP48_X6Y133 RAMB18_X5Y108:RAMB18_X8Y133 RAMB36_X5Y54:RAMB36_X8Y66} 3 | endgroup 4 | add_cells_to_pblock mmtile_0 [get_cells [list top_top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs 5 | -------------------------------------------------------------------------------- /examples/matmul/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | connectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 5 | connectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 6 | -------------------------------------------------------------------------------- /examples/maxsonar_simple/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | S2H_INTERFACES = MaxSonarCtrlRequest:MaxSonarController.req 3 | H2S_INTERFACES = MaxSonarController:MaxSonarCtrlIndication 4 | 5 | ZBR = $(CONNECTALDIR)/lib/zedboard_robot 6 | BSVFILES = $(ZBR)/bsv/MaxSonarController.bsv 7 | CPPFILES= test_maxsonar.cpp $(ZBR)/cpp/read_buffer.cpp 8 | AUTOTOP = --interface pins:MaxSonarController.pins 9 | 10 | PIN_TYPE = MaxSonarSimplePins 11 | PIN_TYPE_INCLUDE = MaxSonarController 12 | PINOUT_FILE = pinout.json 13 | PIN_BINDINGS = pmod:pmodb 14 | 15 | include $(CONNECTALDIR)/Makefile.connectal 16 | -------------------------------------------------------------------------------- /examples/maxsonar_simple/pinout.json: -------------------------------------------------------------------------------- 1 | { 2 | "maxsonar_range_ctrl" : { 3 | "PIO_DIRECTION": "OUTPUT", 4 | "pmod" : "J2" 5 | }, 6 | "maxsonar_pulse_v" : { 7 | "PIO_DIRECTION": "INPUT", 8 | "pmod" : "J4" 9 | }, 10 | 11 | "leds_leds[0]" : { 12 | "PIO_DIRECTION": "OUTPUT", 13 | "leds" : "L0" 14 | }, 15 | "leds_leds[1]" : { 16 | "PIO_DIRECTION": "OUTPUT", 17 | "leds" : "L1" 18 | }, 19 | "leds_leds[2]" : { 20 | "PIO_DIRECTION": "OUTPUT", 21 | "leds" : "L2" 22 | }, 23 | "leds_leds[3]" : { 24 | "PIO_DIRECTION": "OUTPUT", 25 | "leds" : "L3" 26 | }, 27 | "leds_leds[4]" : { 28 | "PIO_DIRECTION": "OUTPUT", 29 | "leds" : "L4" 30 | }, 31 | "leds_leds[5]" : { 32 | "PIO_DIRECTION": "OUTPUT", 33 | "leds" : "L5" 34 | }, 35 | "leds_leds[6]" : { 36 | "PIO_DIRECTION": "OUTPUT", 37 | "leds" : "L6" 38 | }, 39 | "leds_leds[7]" : { 40 | "PIO_DIRECTION": "OUTPUT", 41 | "leds" : "L7" 42 | } 43 | } 44 | 45 | 46 | -------------------------------------------------------------------------------- /examples/memcpy/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemcpyRequest:Memcpy.request 3 | H2S_INTERFACES = Memcpy:MemcpyIndication 4 | MEM_READ_INTERFACES = lMemcpy.dmaReadClient 5 | MEM_WRITE_INTERFACES = lMemcpy.dmaWriteClient 6 | 7 | BSVFILES = ../memcpy/Memcpy.bsv 8 | CPPFILES= ../memcpy/testmemcpy.cpp 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/memcpyslow/Makefile: -------------------------------------------------------------------------------- 1 | include ../memcpy/Makefile 2 | 3 | CONNECTALFLAGS += --mainclockperiod=30 4 | 5 | -------------------------------------------------------------------------------- /examples/memlatency/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemlatencyRequest:Memlatency.request 3 | H2S_INTERFACES = Memlatency:MemlatencyIndication 4 | MEM_READ_INTERFACES = lMemlatency.dmaReadClient 5 | MEM_WRITE_INTERFACES = lMemlatency.dmaWriteClient 6 | 7 | BSVFILES = Memlatency.bsv 8 | CPPFILES = testmemlatency.cpp 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/memread/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 4 | H2S_INTERFACES = ReadTest:ReadTestIndication 5 | MEM_READ_INTERFACES = lReadTest.dmaClient 6 | BSVFILES = ReadTest.bsv 7 | CPPFILES=testmemread.cpp 8 | 9 | ifeq ($(BOARD),zedboard) 10 | CONNECTALFLAGS += -DBSV_POSITIVE_RESET 11 | endif 12 | ifeq ($(BOARD),xsim) 13 | CONNECTALFLAGS += -DBSV_POSITIVE_RESET 14 | endif 15 | 16 | #CONNECTALFLAGS += -DTLP32 17 | CONNECTALFLAGS += -DMEMENGINE_REQUEST_CYCLES 18 | 19 | include $(CONNECTALDIR)/Makefile.connectal 20 | -------------------------------------------------------------------------------- /examples/memread/vc707_floorplan.xdc: -------------------------------------------------------------------------------- 1 | startgroup 2 | create_pblock pblock_ep7 3 | resize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32} 4 | add_cells_to_pblock pblock_ep7 [get_cells [list ep7]] -clear_locs 5 | endgroup 6 | 7 | startgroup 8 | create_pblock pblock_pciehost 9 | resize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X171Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38 BUFGCTRL_X0Y16} 10 | add_cells_to_pblock pblock_pciehost [get_cells [list pciehost]] -clear_locs 11 | endgroup 12 | 13 | startgroup 14 | create_pblock pblock_portalTop 15 | resize_pblock pblock_portalTop -add {SLICE_X0Y25:SLICE_X101Y247 DSP48_X0Y10:DSP48_X7Y97 RAMB18_X0Y10:RAMB18_X6Y97 RAMB36_X0Y5:RAMB36_X6Y48} 16 | add_cells_to_pblock pblock_portalTop [get_cells [list portalTop]] -clear_locs 17 | endgroup 18 | -------------------------------------------------------------------------------- /examples/memread128/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 3 | H2S_INTERFACES = ReadTest:ReadTestIndication 4 | MEM_READ_INTERFACES = lReadTest.dmaClient 5 | 6 | BSVFILES = ../memread/ReadTest.bsv 7 | CPPFILES= ../memread/testmemread.cpp 8 | CONNECTALFLAGS += -D DataBusWidth=128 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/memread2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = Memread2Request:Memread2.request 3 | H2S_INTERFACES = Memread2:Memread2Indication 4 | MEM_READ_INTERFACES = lMemread2.dmaClients 5 | 6 | BSVFILES = Memread2.bsv 7 | CPPFILES=testmemread2.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /examples/memread256/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 3 | H2S_INTERFACES = ReadTest:ReadTestIndication 4 | MEM_READ_INTERFACES = lReadTest.dmaClient 5 | 6 | BSVFILES = ../memread/ReadTest.bsv 7 | CPPFILES= ../memread/testmemread.cpp 8 | CONNECTALFLAGS += -D DataBusWidth=256 9 | CONNECTALFLAGS += --mainclockperiod=8 -D USE_WIDE_WIDTH 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/memread_4m/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 3 | H2S_INTERFACES = ReadTest\#\(\`NumberOfMasters\):ReadTestIndication 4 | MEM_READ_INTERFACES = lReadTest.dmaClients 5 | 6 | BSVFILES = ReadTest.bsv 7 | CPPFILES=../memread/testmemread.cpp 8 | PLATFORM_NUMBER_OF_MASTERS =4 9 | #CONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/memread_simple/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 3 | H2S_INTERFACES = ReadTest:ReadTestIndication 4 | MEM_READ_INTERFACES = lReadTest.dmaClient 5 | 6 | BSVFILES = ReadTest.bsv 7 | CPPFILES=testmemread.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /examples/memread_simple/vc707_floorplan.xdc: -------------------------------------------------------------------------------- 1 | startgroup 2 | create_pblock pblock_ep7 3 | resize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32} 4 | add_cells_to_pblock pblock_ep7 [get_cells [list ep7]] -clear_locs 5 | endgroup 6 | 7 | startgroup 8 | create_pblock pblock_pciehost 9 | resize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X171Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38 BUFGCTRL_X0Y16} 10 | add_cells_to_pblock pblock_pciehost [get_cells [list pciehost]] -clear_locs 11 | endgroup 12 | 13 | startgroup 14 | create_pblock pblock_portalTop 15 | resize_pblock pblock_portalTop -add {SLICE_X0Y25:SLICE_X101Y247 DSP48_X0Y10:DSP48_X7Y97 RAMB18_X0Y10:RAMB18_X6Y97 RAMB36_X0Y5:RAMB36_X6Y48} 16 | add_cells_to_pblock pblock_portalTop [get_cells [list portalTop]] -clear_locs 17 | endgroup 18 | -------------------------------------------------------------------------------- /examples/memwrite/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 5 | 6 | BSVFILES = Memwrite.bsv 7 | CPPFILES=testmemwrite.cpp 8 | CONNECTALFLAGS += --bscflags " -show-schedule" 9 | CONNECTALFLAGS += -DMEMENGINE_REQUEST_CYCLES 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/memwrite128/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 5 | 6 | BSVFILES = ../memwrite/Memwrite.bsv 7 | CPPFILES=../memwrite/testmemwrite.cpp 8 | CONNECTALFLAGS += --bscflags " -show-schedule" 9 | CONNECTALFLAGS += -D DataBusWidth=128 10 | CONNECTALFLAGS += -D USE_ACP 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /examples/memwrite256/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 5 | 6 | BSVFILES = ../memwrite/Memwrite.bsv 7 | CPPFILES=../memwrite/testmemwrite.cpp 8 | CONNECTALFLAGS += --bscflags " -show-schedule" 9 | CONNECTALFLAGS += -D DataBusWidth=256 10 | CONNECTALFLAGS += -D USE_ACP 11 | # CONNECTALFLAGS += -D NumEngineServers=4 12 | CONNECTALFLAGS += --mainclockperiod=8 -D USE_WIDE_WIDTH 13 | 14 | include $(CONNECTALDIR)/Makefile.connectal 15 | -------------------------------------------------------------------------------- /examples/memwrite_4m/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite\#\(\`NumberOfMasters\):MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClients 5 | 6 | BSVFILES = Memwrite.bsv 7 | CPPFILES = ../memwrite/testmemwrite.cpp 8 | PLATFORM_NUMBER_OF_MASTERS =4 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/nandsim/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = NandCfgRequest:NandSim.request 3 | H2S_INTERFACES = NandSim:NandCfgIndication 4 | MEM_READ_INTERFACES = lNandSim.readClient 5 | MEM_WRITE_INTERFACES = lNandSim.writeClient 6 | 7 | BSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv 8 | CPPFILES=testnandsim.cpp 9 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/portal-synth-boundary/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = SimpleRequest SimpleIndication 3 | 4 | BSVFILES = Simple.bsv Top.bsv 5 | CPPFILES=testsimple.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /examples/printf/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = Swallow EchoRequest EchoIndication DisplayInd 3 | 4 | BSVFILES = Echo.bsv SwallowIF.bsv Top.bsv 5 | CPPFILES=testecho.cpp 6 | USE_PRINTF = 1 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /examples/rbm/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | CONNECTALFLAGS = -D J_VALUE=1 -D K_VALUE=1 -D N_VALUE=1 -D DataBusWidth=32 4 | 5 | MMDIR=../matmul 6 | RBMDIR=../rbm 7 | TESTCPPFILES= testrbm.cpp 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(RBMDIR)/Makefile.rbm 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /examples/rbm/Readme.md: -------------------------------------------------------------------------------- 1 | 2 | BSV implementation of Restricted Boltzmann Machine modeled on 3 | git://github.com/echen/restricted-boltzmann-machines 4 | 5 | MNIST numeric digit data from: 6 | http://yann.lecun.com/exdb/mnist/ 7 | -------------------------------------------------------------------------------- /examples/rbm/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /examples/regexp/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = RegexpRequest:Regexp.request 3 | H2S_INTERFACES = Regexp\#\(64\):RegexpIndication 4 | MEM_READ_INTERFACES = "append(lRegexp.config_read_client,lRegexp.haystack_read_client)" 5 | 6 | BSVFILES = $(CONNECTALDIR)/lib/regexp/bsv/Regexp.bsv 7 | CPPFILES=testregexp.cpp 8 | CONNECTALFLAGS = -D DEGPAR=4 -D MAX_NUM_STATES=32 -D MAX_NUM_CHARS=32 9 | CONNECTALFLAGS += --stl=gnustl_static 10 | RUN_ARGS = test.bin 11 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/regexp/cpp 12 | CONNECTALFLAGS += --run-args="$(addprefix $(PWD)/, jregexp.charMap jregexp.stateMap jregexp.stateTransitions test.bin)" 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /examples/regexp/jregexp.charMap: -------------------------------------------------------------------------------- 1 |   2 |   -------------------------------------------------------------------------------- /examples/regexp/jregexp.stateMap: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/examples/regexp/jregexp.stateMap -------------------------------------------------------------------------------- /examples/regexp/jregexp.stateTransitions: -------------------------------------------------------------------------------- 1 |      2 |         -------------------------------------------------------------------------------- /examples/sdcard_spi/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | 4 | BSVFILES = SPITest.bsv 5 | CPPFILES = sdcard_spi.cpp 6 | 7 | S2H_INTERFACES = SPIRequest:SPITest.spiRequest 8 | H2S_INTERFACES = SPITest:SPIIndication 9 | MEM_READ_INTERFACES = 10 | MEM_WRITE_INTERFACES = 11 | 12 | PINOUT_FILE += pin_translation.json 13 | PIN_TYPE = SPIMasterPins 14 | PIN_TYPE_INCLUDE = SPI 15 | AUTOTOP = --interface pins:SPITest.spiMasterPins 16 | 17 | include $(CONNECTALDIR)/Makefile.connectal 18 | 19 | -------------------------------------------------------------------------------- /examples/sdcard_spi/pin_translation.json: -------------------------------------------------------------------------------- 1 | { 2 | "spi_sclk": { 3 | "PIO_DIRECTION": "OUTPUT", 4 | "sdio": "clk" 5 | }, 6 | "spi_mosi": { 7 | "PIO_DIRECTION": "OUTPUT", 8 | "sdio": "cmd" 9 | }, 10 | "spi_miso": { 11 | "PIO_DIRECTION": "INPUT", 12 | "sdio": "dat0" 13 | }, 14 | "spi_ncs": { 15 | "PIO_DIRECTION": "OUTPUT", 16 | "sdio": "cd_dat3" 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /examples/sdcard_spi/readme.txt: -------------------------------------------------------------------------------- 1 | sdcard_spi example 2 | ------------------ 3 | 4 | This example uses SPI mode on an SD card to read the first block of data. 5 | This example was initially designed for the kc705g2 FPGA platform using an 6 | 8 GB SDHC card. Due to differences in initialization, this will not work on 7 | older, smaller SD cards, and it may not work on larger, newer SD* cards. 8 | 9 | The mkSPIMaster module in SPI.bsv has not been well tested. Currently this 10 | example is the only time it has been used. You may find bugs if you try to 11 | use it in a different situation (especially if SPI mode isn't 0). 12 | 13 | -------------------------------------------------------------------------------- /examples/simple/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = SimpleRequest:Simple.request 3 | H2S_INTERFACES = Simple:SimpleRequest 4 | 5 | BSVFILES = Simple.bsv 6 | CPPFILES = testsimple.cpp 7 | 8 | ifeq ($(BOARD), $(filter $(BOARD), de5 htg4)) 9 | PIN_BINDINGS?=PCIE:PCIE LED:LED OSC:OSC 10 | endif 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /examples/simplemultibluesim/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = LinkRequest:Link.linkRequest SimpleRequest:Link.simpleRequest 3 | H2S_INTERFACES = Link:SimpleRequest 4 | 5 | BSVFILES = ../simple/Simple.bsv LinkIF.bsv 6 | CPPFILES=testsimple.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /examples/simplemultibluesim/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd bluesim 4 | 5 | BLUESIM_SOCKET_NAME=socket1 ./bin/bsim & bsim1_pid=$! 6 | BLUESIM_SOCKET_NAME=socket2 ./bin/bsim & bsim2_pid=$! 7 | 8 | BLUESIM_SOCKET_NAME=socket1 ./bin/bsim_exe & bsimexe1_pid=$! 9 | BLUESIM_SOCKET_NAME=socket2 ./bin/bsim_exe & bsimexe2_pid=$! 10 | 11 | wait $bsimexe1_pid $bsimexe2_pid 12 | kill $bsim1_pid $bsim2_pid 13 | -------------------------------------------------------------------------------- /examples/simplemultibluesim/xsimrun.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd xsim 4 | 5 | SOFTWARE_SOCKET_NAME=node1. xsim -R work.xsimtop & xsim1_pid=$! 6 | SOFTWARE_SOCKET_NAME=node2. xsim -R work.xsimtop & xsim2_pid=$! 7 | 8 | sleep 10 9 | 10 | SOFTWARE_SOCKET_NAME=node1. ./bin/ubuntu.exe & xsimexe1_pid=$! 11 | SOFTWARE_SOCKET_NAME=node2. ./bin/ubuntu.exe & xsimexe2_pid=$! 12 | 13 | wait $xsimexe1_pid $xsimexe2_pid 14 | kill $xsim1_pid $xsim2_pid 15 | -------------------------------------------------------------------------------- /examples/simplesharedhw/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = SharedMemoryPortalConfig 3 | S2H_INTERFACES = /SimpleRequest:Simple.request 4 | H2S_INTERFACES = /Simple:SimpleRequest 5 | MEM_READ_INTERFACES = "cons(lSharereadEngine.dmaClient,nil)" 6 | MEM_WRITE_INTERFACES = "cons(lSharewriteEngine.dmaClient,nil)" 7 | 8 | CONNECTALFLAGS += -D USE_ACP -D USE_DUAL_CLOCK_FIFOF 9 | BSVFILES = Simple.bsv $(CONNECTALDIR)/bsv/Portal.bsv 10 | CPPFILES=testsimple.cpp 11 | CONNECTALFLAGS += -D USE_ACP 12 | AUTOTOP = --importfiles SharedMemoryPortal --importfiles SharedMemoryPortalConfig --importfiles MemTypes --importfiles MemReadEngine --importfiles MemWriteEngine 13 | 14 | include $(CONNECTALDIR)/Makefile.connectal 15 | -------------------------------------------------------------------------------- /examples/strstr/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = StrstrRequest:StrstrExample.request 3 | H2S_INTERFACES = StrstrExample:StrstrIndication 4 | MEM_READ_INTERFACES = lStrstrExample.readClients 5 | 6 | BSVFILES = $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv StrstrExample.bsv 7 | CPPFILES=teststrstr.cpp 8 | CONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/swmemcpy/Makefile: -------------------------------------------------------------------------------- 1 | BASEDIR = ../../ 2 | UTILDIR = ../../cpp/ 3 | 4 | testpa: 5 | g++ -I$(BASEDIR) testpa.cpp $(UTILDIR)/portal.c $(UTILDIR)/sock_utils.c -pthread 6 | 7 | clean: 8 | rm a.out 9 | -------------------------------------------------------------------------------- /examples/vectoradd_hls/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../../ 2 | S2H_INTERFACES = VaddRequest:Vadd.request 3 | H2S_INTERFACES = Vadd:VaddResponse 4 | 5 | BSVFILES = bsv/Vadd.bsv 6 | CPPFILES = testvadd.cpp 7 | 8 | CONNECTALFLAGS += -V solution1/impl/verilog 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /examples/vectoradd_hls/src/vectoradd.cpp: -------------------------------------------------------------------------------- 1 | 2 | 3 | void vectoradd(const int in0[64], const int in1[64], int out[64]) 4 | { 5 | #pragma HLS interface ap_hs port=in0 6 | #pragma HLS interface ap_hs port=in1 7 | #pragma HLS interface ap_hs port=out 8 | for (int i = 0; i < 64; i++) 9 | #pragma unroll 4 10 | out[i] = in0[i] + in1[i]; 11 | } 12 | -------------------------------------------------------------------------------- /generated/cpp/README: -------------------------------------------------------------------------------- 1 | 2 | GeneratedTypes.h and MMURequest.c in this directory are taken from tests/memread_manual/bluesim/jni, without modification. 3 | 4 | They are only used when compiling dmaSendFd.h for drivers/pcieportal/pcieportal.c and drivers/zynqportal/zynqportal.c 5 | 6 | 7 | -------------------------------------------------------------------------------- /generated/scripts/generate_altera_ddrbvi.sh: -------------------------------------------------------------------------------- 1 | # 2 | # 3 | set -x 4 | set -e 5 | ./importbvi.py -o ALTERA_DDR3_WRAPPER.bsv -I AvalonDdr3 -P AvalonDdr3 \ 6 | -c pll_ref_clk -r global_reset_n -r soft_reset_n -c afi_clk -c afi_half_clk -r afi_reset_n -r afi_reset_export_n \ 7 | -f mem -f avl -f local -f oct -f pll \ 8 | /home/hwang/dev/connectal/out/de5/synthesis/altera_mem_if_ddr3_emif_wrapper/altera_mem_if_ddr3_emif_wrapper.v 9 | -------------------------------------------------------------------------------- /generated/scripts/generate_altera_macbvi.sh: -------------------------------------------------------------------------------- 1 | # 2 | # 3 | set -x 4 | set -e 5 | ./importbvi.py -o ALTERA_MAC_WRAPPER.bsv -I MacWrap -P MacWrap \ 6 | -c p0_tx_clk_clk -c p1_tx_clk_clk -c p2_tx_clk_clk -c p3_tx_clk_clk \ 7 | -c p0_rx_clk_clk -c p1_rx_clk_clk -c p2_rx_clk_clk -c p3_rx_clk_clk \ 8 | -c mgmt_clk_clk \ 9 | -r mgmt_reset_reset_n -r jtag_reset_reset \ 10 | -r p0_tx_reset_reset_n -r p1_tx_reset_reset_n -r p2_tx_reset_reset_n -r p3_tx_reset_reset_n \ 11 | -r p0_rx_reset_reset_n -r p1_rx_reset_reset_n -r p2_rx_reset_reset_n -r p3_rx_reset_reset_n \ 12 | -f p0_tx -f p0_rx -f p1_tx -f p1_rx -f p2_tx -f p2_rx -f p3_tx -f p3_rx \ 13 | -f p0_xgmii -f p1_xgmii -f p2_xgmii -f p3_xgmii \ 14 | -f p0_link_fault -f p1_link_fault -f p2_link_fault -f p3_link_fault \ 15 | ../../out/de5/synthesis/altera_mac.v 16 | 17 | -------------------------------------------------------------------------------- /generated/scripts/generate_bscane2.sh: -------------------------------------------------------------------------------- 1 | # 2 | set -x 3 | set -e 4 | scripts/importbvi.py -o BscanE2.bsv -C BSCANE2 -I BscanE2 -P PPS7 -c DRCK -c TCK --param=JTAG_CHAIN \ 5 | ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib 6 | 7 | -------------------------------------------------------------------------------- /generated/scripts/generate_bufgcrtl.sh: -------------------------------------------------------------------------------- 1 | # 2 | set -x 3 | set -e 4 | scripts/importbvi.py -o Bufgctrl.bsv -C BUFGCTRL -I Bufgctrl -P Bufgctrl \ 5 | -c I0 -c I1 -c O \ 6 | ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib 7 | 8 | -------------------------------------------------------------------------------- /generated/scripts/generate_pciewrapper.sh: -------------------------------------------------------------------------------- 1 | # 2 | set -x 3 | set -e 4 | ../scripts/importbvi.py -o PCIEWRAPPER.bsv -I PcieWrap -P PcieWrap \ 5 | -n pl_link_partner_gen2_supported \ 6 | -n cfg_mgmt_wr_rw1c_as_rw \ 7 | -n pipe_gen3_out \ 8 | -n pipe_userclk1_in \ 9 | -n pipe_userclk2_in \ 10 | -n pl_link_gen2_cap \ 11 | -c user_clk_out -r user_reset_out \ 12 | -c sys_clk -r sys_rst_n \ 13 | -f cfg_aer -f cfg_ds -f cfg_err -f cfg_interrupt \ 14 | -f cfg_mgmt -f cfg_msg -f cfg_pmcsr -f cfg_pm \ 15 | -f cfg_root_control \ 16 | -f pipe -f pl_link -f pci_exp -f pcie_drp \ 17 | -p lanes \ 18 | ../../out/vc707/pcie_7x_0/synth/pcie_7x_0.v 19 | 20 | # xilinx/pcie_7x_v2_1/synth/pcie_7x_0.v 21 | -------------------------------------------------------------------------------- /generated/scripts/generate_pipeclock.sh: -------------------------------------------------------------------------------- 1 | # 2 | set -e 3 | set -x 4 | ./scripts/importbvi.py -o PipeClock.bsv -P pclk -I pclk -p pcie_lane \ 5 | xilinx/7x/pcie/source/pcie_7x_0_pipe_clock.v 6 | -------------------------------------------------------------------------------- /generated/scripts/generate_pps7lib.sh: -------------------------------------------------------------------------------- 1 | # 2 | set -x 3 | set -e 4 | scripts/importbvi.py -o PPS7LIB.bsv -C PS7 -I PPS7LIB -P PPS7 \ 5 | -f DDR -f FTMT -f FTMD -f IRQ \ 6 | -f EMIOGPIO -f EMIOPJTAG -f EMIOTRACE -f EMIOWDT -f EVENT -f PS -f SAXIACP \ 7 | -c MAXIGP0ACLK -c MAXIGP1ACLK -c SAXIACPACLK \ 8 | -c SAXIGP0ACLK -c SAXIGP1ACLK \ 9 | -c SAXIHP0ACLK -c SAXIHP1ACLK -c SAXIHP2ACLK -c SAXIHP3ACLK \ 10 | -i PS7EXTENDED:Pps7Emiocan:Pps7Emioenet:Pps7Emiopjtag:Pps7Emiosdio:Pps7Emiospi:Pps7Emiotrace:Pps7Emiottc:Pps7Emiouart:Pps7Emiousb:Pps7Emiowdt:Pps7Dma:Pps7Ftmd:Pps7Ftmt \ 11 | --notdef Pps7Maxigp --notdef Pps7Saxigp --notdef Pps7Saxihp --notdef Pps7Saxiacp \ 12 | ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib 13 | 14 | # -c DMA0ACLK -c DMA1ACLK -c DMA2ACLK -c DMA3ACLK \ 15 | # -c EMIOENET0GMIIRXCLK -c EMIOENET0GMIITXCLK \ 16 | # -c EMIOENET1GMIIRXCLK -c EMIOENET1GMIITXCLK \ 17 | # -c EMIOSDIO0CLKFB -c EMIOSDIO1CLKFB -c EMIOTRACECLK \ 18 | -------------------------------------------------------------------------------- /generated/scripts/generate_zynq_mpsoc.sh: -------------------------------------------------------------------------------- 1 | 2 | # -c pl_clk0 -c pl_clk1 -r pl_resetn0 3 | ../scripts/importbvi.py -c maxihpm0_fpd_aclk -c maxihpm0_fpd_aclk -c saxihpc0_fpd_aclk -c saxiacp_fpd_aclk -c saxi_lpd_aclk -c saxihp0_fpd_aclk -c saxihp1_fpd_aclk -c saxihp2_fpd_aclk -c saxihp3_fpd_aclk -c sacefpd_aclk -c maxihpm0_lpd_aclk -I PS8 -P PS8 -o ZYNQ_ULTRA.bsv ../../out/zcu102/zynq_ultra_ps_e_0/zynq_ultra_ps_e_0_stub.v 4 | 5 | sed -i 's/zynq_ultra_ps_e_0(maxihpm0_fpd_aclk,/zynq_ultra_ps_e_0/' ZYNQ_ULTRA.bsv 6 | sed -i 's/default_clock clk()/default_clock no_clock/' ZYNQ_ULTRA.bsv 7 | sed -i 's/default_reset rst()/default_reset no_reset/' ZYNQ_ULTRA.bsv 8 | sed -i 's/input_reset.*;//' ZYNQ_ULTRA.bsv 9 | sed -i 's/, Reset .*reset//' ZYNQ_ULTRA.bsv 10 | ##sed -i 's/method maxigp0[^;]*/& clocked_by (maxihpm0_lpd_aclk) reset_by (no_reset)/' ZYNQ_ULTRA.bsv 11 | sed -i 's/method [a-z][^;]*/& clocked_by (maxihpm0_lpd_aclk) reset_by (no_reset)/' ZYNQ_ULTRA.bsv 12 | -------------------------------------------------------------------------------- /gralloc/Android.mk: -------------------------------------------------------------------------------- 1 | LOCAL_PATH:= $(call my-dir) 2 | 3 | include $(CLEAR_VARS) 4 | 5 | LOCAL_MODULE_PATH := $(TARGET_OUT_SHARED_LIBRARIES)/hw 6 | LOCAL_SHARED_LIBRARIES := libcutils liblog 7 | 8 | HDMI_SRC_FILES = DmaConfigProxy.cpp DmaIndicationWrapper.cpp HdmiDisplayRequestProxy.cpp HdmiDisplayIndicationWrapper.cpp HdmiInternalRequestProxy.cpp HdmiInternalIndicationWrapper.cpp 9 | 10 | LOCAL_SRC_FILES := \ 11 | ../cpp/portal.cpp ../cpp/dmaManager.cpp \ 12 | $(addprefix ../examples/hdmidisplay/zedboard/jni/, $(HDMI_SRC_FILES)) \ 13 | gralloc.cpp mapper.cpp 14 | 15 | LOCAL_MODULE_TAGS = optional 16 | LOCAL_MODULE := gralloc.portal 17 | LOCAL_CFLAGS:= -DZYNQ -DLOG_TAG=\"gralloc\" -I$(LOCAL_PATH)/../cpp -I$(LOCAL_PATH)/../lib/cpp -I$(LOCAL_PATH)/.. -I$(LOCAL_PATH)/../examples/hdmidisplay/zedboard/jni -I$(LOCAL_PATH)/../drivers/zynqportal 18 | 19 | include $(BUILD_SHARED_LIBRARY) 20 | -------------------------------------------------------------------------------- /gralloc/Makefile: -------------------------------------------------------------------------------- 1 | ## 2 | ## Usage: make BOARD=[zedboard,zc702] ANDROID_TOP=/path/to/android 3 | ## 4 | 5 | all: gralloc.portal.so 6 | 7 | ../examples/hdmidisplay/$(BOARD)/jni/HdmiDisplayRequestProxy.h: ../lib/bsv/HdmiDisplay.bsv 8 | (cd ../examples/hdmidisplay; make gen.$(BOARD) build.$(BOARD)) 9 | cp -v ../examples/hdmidisplay/$(BOARD)/bin/*.bin* . 10 | 11 | gralloc.portal.so: gralloc.cpp mapper.cpp Android.mk ../lib/bsv/HdmiDisplay.bsv ../examples/hdmidisplay/$(BOARD)/jni/HdmiDisplayRequestProxy.h 12 | pushd $(ANDROID_TOP); . ./build/envsetup.sh; lunch zedboard-userdebug; popd; TOP=$(ANDROID_TOP) mm showcommands 13 | cp -v $(ANDROID_TOP)/out/target/product/zedboard/system/lib/hw/gralloc.portal.so gralloc.portal.so 14 | -------------------------------------------------------------------------------- /gralloc/README: -------------------------------------------------------------------------------- 1 | 2 | To compile the gralloc library: 3 | 4 | 1. cd 5 | (to build this tree, see: https://github.com/cambridgehackers/zynq-android4/wiki/ZynqAndroid4.1 ) 6 | 2. set environment variables from that build tree: 7 | source ./build/envsetup.sh; lunch zedboard-userdebug 8 | 3. cd mm 11 | (Note that this will place the resulting library into the android build tree output directory, 12 | probably in the file: out/target/product/zedboard/system/lib/hw/gralloc.portal.so ) 13 | 14 | NOTE: the xilinx GLIBCXX libraries conflict with the gcc system libraries used by the GCC 15 | cross compiler (xilinx versions are bad). 16 | Because of this, the xilinx 'source xxxx' lines cannot be executed prior to compiling android. 17 | -------------------------------------------------------------------------------- /jtag/digilent-hs1.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # Digilent HS1 3 | # 4 | # The Digilent HS1 is a high-speed FT2232H-based adapter, compliant with the 5 | # Xilinx JTAG 14-pin pinout. 6 | # It does not support ARM reset signals (SRST and TRST) but can still be used for 7 | # hardware debugging, with some limitations. 8 | # 9 | # http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,922&Prod=JTAG-HS1 10 | # 11 | 12 | interface ft2232 13 | ft2232_device_desc "Digilent Adept USB Device" 14 | ft2232_layout digilent-hs1 15 | ft2232_vid_pid 0x0403 0x6010 16 | adapter_khz 100 17 | -------------------------------------------------------------------------------- /jtag/digilent-hs2.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # high-speed FT232H-based adapter, compliant with the 3 | # Xilinx JTAG 14-pin pinout. 4 | # 5 | 6 | interface ft2232 7 | ft2232_layout digilent-hs1 8 | ft2232_vid_pid 0x0403 0x6014 9 | adapter_khz 100 10 | -------------------------------------------------------------------------------- /jtag/run_jtag.sh: -------------------------------------------------------------------------------- 1 | # 2 | set -e 3 | set -x 4 | #openocd -f kc705.cfg 5 | openocd -f zedboard.cfg 6 | -------------------------------------------------------------------------------- /jtag/run_trace.sh: -------------------------------------------------------------------------------- 1 | #/bin/bash 2 | set -x 3 | set -e 4 | openocd -f zedtrace.cfg 2>trace.xx.tempfile 5 | sed -e"s/\(.\)\(...\)\(....\)/\1 \2 \3 /" trace.log 9 | #rm -f trace.xx.tempfile 10 | -------------------------------------------------------------------------------- /jtag/zedtrace.cfg: -------------------------------------------------------------------------------- 1 | source digilent-hs2.cfg 2 | 3 | jtag newtap zed tap -irlen 6 -ircapture 0x01 -expected-id 0x03727093 4 | jtag newtap cortex tap -irlen 4 -ircapture 0x01 -expected-id 0x4ba00477 5 | 6 | # targets cortex_a 7 | 8 | verify_jtag 9 | 10 | init 11 | scan_chain 12 | 13 | # clear bscan.sel() by setting IR to a different register 14 | irscan zed.tap 9 15 | 16 | #echo [drscan zed.tap 64 0xffffffffffffffff] 17 | #echo [drscan zed.tap 64 0xffffffffffffffff] 18 | #echo [drscan zed.tap 64 0x0000000000000000] 19 | #echo [drscan zed.tap 64 0x0000000000000000] 20 | #echo [drscan zed.tap 64 0x00000000000000f0] 21 | for {set j 0} {$j < 4} {incr j} { 22 | # try reading out USER2 register 000011 23 | irscan zed.tap 3 24 | for {set i 0} {$i < 256 + 2} {incr i} { 25 | echo [drscan zed.tap 64 0xdeadbeefbeefdead] 26 | } 27 | sleep 1000 28 | } 29 | 30 | # clear bscan.sel() by setting IR to a different register 31 | irscan zed.tap 9 32 | 33 | shutdown 34 | 35 | -------------------------------------------------------------------------------- /lib/deprecated/bsv_Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | test: testspi testAdapter 4 | 5 | testspi: ConnectalSpi.bsv 6 | bsc -check-assert -sim -u -g mkSpiTestBench ConnectalSpi.bsv 7 | bsc -check-assert -sim -u -e mkSpiTestBench -o spiTestBench mkSpiTestBench.ba 8 | ./spiTestBench -V spi.vcd 9 | 10 | testgearbox: GearboxTb.bsv 11 | bsc -sim -u -g mkGearboxTb GearboxTb.bsv 12 | bsc -sim -u -e mkGearboxTb -o testGearbox mkGearboxTb.ba 13 | ./testGearbox 14 | 15 | mkGearboxTb.v: GearboxTb.bsv 16 | bsc -verilog -u -g mkGearboxTb GearboxTb.bsv 17 | 18 | testAdapter: Adapter.bsv 19 | bsc -p +:../lib/bsv -check-assert -sim -u -g mkAdapterTb Adapter.bsv 20 | bsc -check-assert -sim -u -e mkAdapterTb -o testAdapter mkAdapterTb.ba 21 | ./testAdapter 22 | 23 | testConnectalReadyQueue: ConnectalReadyQueue.bsv 24 | bsc -check-assert -sim -u -g mkRQTB ConnectalReadyQueue.bsv 25 | bsc -check-assert -sim -u -e mkRQTB -o testConnectalReadyQueue mkRQTB.ba 26 | ./testConnectalReadyQueue 27 | 28 | mkSPI20.v: ConnectalSpi.bsv 29 | bsc -verilog -u -g mkSPI20 ConnectalSpi.bsv 30 | -------------------------------------------------------------------------------- /lib/deprecated/pcietestbench/Makefile: -------------------------------------------------------------------------------- 1 | INTERFACES = PcieTestBenchRequest PcieTestBenchIndication 2 | 3 | BSVFILES = PcieTestBench.bsv Top.bsv 4 | CPPFILES=testpcie.cpp 5 | 6 | include ../../Makefile.common 7 | -------------------------------------------------------------------------------- /lib/deprecated/pcietestbench_dma_io/Makefile: -------------------------------------------------------------------------------- 1 | INTERFACES = PcieTestBenchRequest PcieTestBenchIndication 2 | 3 | BSVFILES = PcieTestBench.bsv Top.bsv 4 | CPPFILES=testpcie.cpp 5 | 6 | include ../../Makefile.common 7 | -------------------------------------------------------------------------------- /lib/deprecated/pcietestbench_dma_oo/Makefile: -------------------------------------------------------------------------------- 1 | 2 | INTERFACES = PcieTestBenchRequest PcieTestBenchIndication 3 | BSVFILES = PcieTestBench.bsv Top.bsv ../../lib/deprecated/DmaUtils.bsv 4 | CPPFILES=testpcie.cpp 5 | 6 | include ../../Makefile.common 7 | -------------------------------------------------------------------------------- /lib/matmul/bar.m: -------------------------------------------------------------------------------- 1 | source("foo.m"); 2 | 3 | om3 = m1*m2; 4 | 5 | max_error_m3 = 0.0; 6 | max_error_tm3 = 0.0; 7 | max_error_om3 = 0.0; 8 | 9 | #calculate a few dot products along the diagonal 10 | #see if the dot products agree with m3 and tm3 11 | for i = 1:size(m1)(1) 12 | printf("dp: %d\n", i); 13 | dp = m1(i,:)*m2(:,i); 14 | max_error_m3 = max(abs(m3(i,i)-dp),max_error_m3); 15 | max_error_tm3 = max(abs(tm3(i,i)-dp),max_error_tm3); 16 | max_error_om3 = max(abs(om3(i,i)-dp),max_error_om3); 17 | endfor 18 | 19 | 20 | max_error_m3 21 | max_error_tm3 22 | max_error_om3 23 | 24 | 25 | -------------------------------------------------------------------------------- /scripts/adb/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/scripts/adb/__init__.py -------------------------------------------------------------------------------- /scripts/adb/fastboot_protocol.txt: -------------------------------------------------------------------------------- 1 | Fastboot Protocol Documentation 2 | 3 | Fastboot's protocol is similar to ADB in only a few ways. However, to make the 4 | code simpler to be inside a bootloader, it basically was completely altered. 5 | 6 | Commands: 7 | getvar:%(variable)s 8 | download:%08x 9 | verify:%08x 10 | flash:%(partition)s 11 | erase:%(partition)s 12 | oem %(stuff)s 13 | boot 14 | continue 15 | reboot 16 | reboot-bootloader 17 | 18 | 19 | Responses: 20 | These are 4-64 bytes long. The first 4 bytes is the header, the rest is 21 | header-specific but only up to 60 bytes. 22 | 23 | INFO + data[0-60] 24 | Arbitrary data returned from the bootloader. 25 | OKAY + reason[0-60] 26 | Last response, says the command succeeded. 27 | FAIL + reason[0-60] 28 | Last response, says the command failed. 29 | DATA + size[8] 30 | Only in response to a download command, says the bootloader is ready to 31 | accept `size` amount of data. 32 | 33 | -------------------------------------------------------------------------------- /scripts/aws/create-fpga-image.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | name=$1 4 | timestamp=$2 5 | bucket="aws-fpga" 6 | 7 | if [ "$AWS_FPGA_BUCKET" != "" ]; then 8 | bucket="$AWS_FPGA_BUCKET" 9 | fi 10 | 11 | if [ "$name" == "" -o "$timestamp" == "" ]; then 12 | echo "usage: $0 [s3 bucket]" >&2 13 | exit -1 14 | fi 15 | 16 | if [ "$3" != "" ]; then 17 | bucket="$3" 18 | fi 19 | 20 | if [ -d "build/checkpoints" ]; then 21 | CHECKPOINTS_DIR="build/checkpoints" 22 | fi 23 | if [ -d "awsf1/build/checkpoints" ]; then 24 | CHECKPOINTS_DIR="awsf1/build/checkpoints" 25 | fi 26 | 27 | aws s3 cp $CHECKPOINTS_DIR/to_aws/$timestamp.Developer_CL.tar s3://$bucket/$name/ 28 | aws s3 cp $CHECKPOINTS_DIR/$timestamp.debug_probes.ltx s3://$bucket/$name/ 29 | aws ec2 create-fpga-image --name $name --description $timestamp --input-storage-location Bucket=$bucket,Key=$name/$timestamp.Developer_CL.tar --logs-storage-location Bucket=$bucket,Key=logs-folder | tee latest-fpga-image.json 30 | -------------------------------------------------------------------------------- /scripts/aws/describe-latest-fpga-image.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | if [ -f awsf1/latest-fpga-image.json ]; then 4 | aws ec2 describe-fpga-images --fpga-image-ids `jq -r .FpgaImageId < awsf1/latest-fpga-image.json` 5 | fi 6 | if [ -f latest-fpga-image.json ]; then 7 | aws ec2 describe-fpga-images --fpga-image-ids `jq -r .FpgaImageId < latest-fpga-image.json` 8 | fi 9 | 10 | -------------------------------------------------------------------------------- /scripts/aws/upload.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | filename=$1 4 | if [ "$filename" = "" ]; then 5 | echo Usage: $0 filename 6 | exit 1 7 | fi 8 | 9 | basename=`basename $filename .Developer_CL.tar` 10 | echo "basename=$basename" 11 | 12 | aws s3 cp ../checkpoints/to_aws/$filename s3://aws-fpga/simple/$filename 13 | aws s3 cp ../checkpoints.$basename.debug_probes.ltx s3://aws-fpga/simple/$filename 14 | aws ec2 create-fpga-image --name simple --description "$filename" --input-storage-location Bucket=aws-fpga,Key=simple/$filename --logs-storage-location Bucket=aws-fpga,Key=logs-folder 15 | -------------------------------------------------------------------------------- /scripts/connectal-make: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | make CONNECTALDIR=/usr/share/connectal $* 4 | 5 | -------------------------------------------------------------------------------- /scripts/connectal-synth-axiddr3.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | set prj_boardname $boardname 5 | if [string match "*g2" $boardname] {set prj_boardname [string trimright $boardname "g2"]} 6 | 7 | connectal_synth_ip mig_7series 4.0 axiddr3 [list CONFIG.XML_INPUT_FILE "$connectaldir/constraints/xilinx/$prj_boardname-axiddr3.prj" CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] 8 | -------------------------------------------------------------------------------- /scripts/connectal-synth-axidma.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | set prj_boardname $boardname 5 | if [string match "*g2" $boardname] {set prj_boardname [string trimright $boardname "g2"]} 6 | 7 | connectal_synth_ip axi_dma 7.1 axi_dma_0 [list CONFIG.c_sg_include_stscntrl_strm {1} CONFIG.c_m_axi_mm2s_data_width {32} CONFIG.c_m_axi_s2mm_data_width {32} CONFIG.c_mm2s_burst_size {8} CONFIG.c_s2mm_burst_size {8}] 8 | 9 | -------------------------------------------------------------------------------- /scripts/connectal-synth-axieth.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | set prj_boardname $boardname 5 | if [string match "*g2" $boardname] {set prj_boardname [string trimright $boardname "g2"]} 6 | 7 | connectal_synth_ip axi_ethernet 7.0 axi_ethernet_0 [list CONFIG.ETHERNET_BOARD_INTERFACE {sfp_sfp1} CONFIG.DIFFCLK_BOARD_INTERFACE {sfp_mgt_clk} CONFIG.axiliteclkrate {250.0} CONFIG.axisclkrate {250.0} CONFIG.PHY_TYPE {1000BaseX}] 8 | 9 | -------------------------------------------------------------------------------- /scripts/connectal-synth-axiintc.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | puts $boardname 5 | set prj_boardname $boardname 6 | if [string match "*g2" $boardname] {set prj_boardname [string trimright $boardname "g2"]} 7 | 8 | connectal_synth_ip axi_intc 4.1 axi_intc_0 [list CONFIG.C_NUM_INTR_INPUTS {16} CONFIG.C_S_AXI_ACLK_FREQ_MHZ {250.0} CONFIG.C_NUM_SW_INTR {0}] 9 | -------------------------------------------------------------------------------- /scripts/deprecated/mkpcietop-synth.tcl: -------------------------------------------------------------------------------- 1 | 2 | # NOTE: typical usage would be "vivado -mode tcl -source create_mkPcieTop_batch.tcl" 3 | # 4 | # STEP#0: define output directory area. 5 | # 6 | if [file exists {board.tcl}] { 7 | source {board.tcl} 8 | } else { 9 | set boardname vc707 10 | set partname {xc7vx485tffg1761-2} 11 | } 12 | 13 | set outputDir ./hw 14 | file mkdir $outputDir 15 | # 16 | # STEP#1: setup design sources and constraints 17 | # 18 | read_verilog [ glob {verilog/top/*.v} ] 19 | read_verilog [ glob $connectaldir/xilinx/pcie_7x_v2_1/pcie_7x_0/source/*.v ] 20 | read_verilog [ glob $connectaldir/xilinx/7x/pcie/source/*.v ] 21 | read_xdc constraints/$boardname.xdc 22 | 23 | # STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design 24 | # 25 | synth_design -name mkPcieTop -top mkPcieTop -part $partname -flatten rebuilt 26 | 27 | write_checkpoint -force $outputDir/mkpcietop_post_synth 28 | -------------------------------------------------------------------------------- /scripts/deprecated/portaltop-impl.tcl: -------------------------------------------------------------------------------- 1 | 2 | # NOTE: typical usage would be "vivado -mode tcl -source create_mkPcieTop_batch.tcl" 3 | # 4 | # STEP#0: define output directory area. 5 | # 6 | if [file exists {board.tcl}] { 7 | source {board.tcl} 8 | } else { 9 | set boardname vc707 10 | set partname {xc7vx485tffg1761-2} 11 | } 12 | 13 | set outputDir ./hw 14 | file mkdir $outputDir 15 | # 16 | # STEP#1: setup design sources and constraints 17 | # 18 | read_verilog [ glob {verilog/lib/*.v} ] 19 | read_verilog [ glob {verilog/portal/*.v} ] 20 | 21 | # STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design 22 | # 23 | synth_design -mode out_of_context -name mkConnectalTopForPcie -top mkConnectalTopForPcie -part $partname -flatten rebuilt 24 | 25 | write_checkpoint -force $outputDir/portaltop_post_synth 26 | 27 | read_xdc $connectaldir/constraints/$boardname-portal-pblock.xdc 28 | 29 | place_design 30 | route_design 31 | 32 | write_checkpoint -force $outputDir/portaltop_post_route 33 | -------------------------------------------------------------------------------- /scripts/deprecated/portaltop-synth.tcl: -------------------------------------------------------------------------------- 1 | 2 | # NOTE: typical usage would be "vivado -mode tcl -source create_mkPcieTop_batch.tcl" 3 | # 4 | # STEP#0: define output directory area. 5 | # 6 | if [file exists {board.tcl}] { 7 | source {board.tcl} 8 | } else { 9 | set boardname vc707 10 | set partname {xc7vx485tffg1761-2} 11 | } 12 | 13 | set outputDir ./hw 14 | file mkdir $outputDir 15 | # 16 | # STEP#1: setup design sources and constraints 17 | # 18 | read_verilog [ glob {verilog/top/*.v} ] 19 | read_verilog [ glob {verilog/portal/*.v} ] 20 | 21 | # STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design 22 | # 23 | synth_design -mode out_of_context -name mkSynthesizeableConnectalTop -top mkSynthesizeableConnectalTop -part $partname -flatten rebuilt 24 | 25 | write_checkpoint -force $outputDir/portaltop_post_synth 26 | -------------------------------------------------------------------------------- /scripts/driver_signature.sed: -------------------------------------------------------------------------------- 1 | s/ */ /g 2 | s/\(.*\) \(.*\)/{"\1", "\2"},/ 3 | s/ ".*\// "/ 4 | 5 | -------------------------------------------------------------------------------- /scripts/globalv.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | globaldecls = [] 4 | globalvars = {} 5 | 6 | def add_new(decl): 7 | if decl: 8 | globaldecls.append(decl) 9 | globalvars[decl.name] = decl 10 | -------------------------------------------------------------------------------- /scripts/run.pcietest.altera: -------------------------------------------------------------------------------- 1 | # 2 | set -x 3 | set -e 4 | export SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" 5 | echo "run.de5test parameters are:" $* 6 | SSHPARAM=" -o StrictHostKeyChecking=no" 7 | 8 | if [ "$SERIALNO" != "" ]; then 9 | BOARD_USB="-c $SERIALNO" 10 | else 11 | BOARD_USB="-c 1" 12 | fi 13 | if [ "$RUNTIMELIMIT" != "" ]; then 14 | TIMELIMIT=$RUNTIMELIMIT 15 | else 16 | TIMELIMIT=3m 17 | fi 18 | 19 | if [ "$RUNPARAM" != "" ]; then 20 | TEMPDIR=/tmp/`uname -n`-$PPID-pcie 21 | ssh $SSHPARAM $RUNPARAM "rm -rf $TEMPDIR; mkdir -p $TEMPDIR" 22 | scp $1 $2 $RUNPARAM:$TEMPDIR 23 | BINNAME=`basename $1` 24 | EXENAME=`basename $2` 25 | if [ "$NOPROGRAM" != "1" ]; then 26 | ssh $SSHPARAM $RUNPARAM "fpgajtag $BOARD_USB $TEMPDIR/$BINNAME" 27 | else 28 | echo "not programming $BOARD" 29 | fi 30 | else 31 | if [ "$NOPROGRAM" != "1" ]; then 32 | echo $1 33 | quartus_pgm $BOARD_USB -m jtag -o p\;$1 34 | sleep 1 35 | fi 36 | fi 37 | -------------------------------------------------------------------------------- /scripts/run_on_daffodil: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | ./run.android --buildbot-url=http://connectalbuild.qrclab.com/archive --project=connectal-simple/zedboard --build-number=10 --board-name=daffodil_zedboard 4 | -------------------------------------------------------------------------------- /tests/adapter/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = TestRequest:Test.request 3 | H2S_INTERFACES = Test:TestIndication 4 | 5 | BSVFILES = Test.bsv 6 | CPPFILES=test.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /tests/aecho/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | LTDIR = $(CONNECTALDIR)/../llvm-translate/ 6 | LLVMT = $(LTDIR)/Debug+Asserts/bin/llvm-translate 7 | ACCDIR = $(CONNECTALDIR)/../atomicc/examples/echo 8 | GENDIR = generated 9 | BSVFILES = EchoReq.bsv 10 | CPPFILES = testecho.cpp 11 | CONNECTALFLAGS += --verilog $(GENDIR) --bsvpath $(GENDIR) 12 | BSCFLAGS += -show-bvi 13 | AUTOTOP += --integratedIndication 14 | 15 | prebuild:: 16 | $(LLVMT) --odir=$(GENDIR) $(ACCDIR)/fifo.ll 17 | $(LLVMT) --odir=$(GENDIR) $(ACCDIR)/echo.ll $(ACCDIR)/atomicc.ll 18 | $(LTDIR)/linker.py --directory generated --output Echo l_class_OC_Echo 19 | 20 | include $(CONNECTALDIR)/Makefile.connectal 21 | -------------------------------------------------------------------------------- /tests/aecho/generated/L_class_OC_Echo.bsv: -------------------------------------------------------------------------------- 1 | interface L_class_OC_Echo; 2 | method Action respond_rule(); 3 | method Action say(Bit#(32) say_v); 4 | endinterface 5 | import "BVI" l_class_OC_Echo = 6 | module mkL_class_OC_Echo(L_class_OC_Echo); 7 | default_reset rst(nRST); 8 | default_clock clk(CLK); 9 | method respond_rule() enable(respond_rule__ENA) ready(respond_rule__RDY); 10 | method say(say_v) enable(say__ENA) ready(say__RDY); 11 | schedule (respond_rule, say) CF (respond_rule, say); 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/aecho/generated/L_class_OC_Fifo.bsv: -------------------------------------------------------------------------------- 1 | interface L_class_OC_Fifo; 2 | method Action in_enq(Bit#(32) in_enq_v); 3 | method Action out_deq(); 4 | method Bit#(32) out_first(); 5 | endinterface 6 | import "BVI" l_class_OC_Fifo = 7 | module mkL_class_OC_Fifo(L_class_OC_Fifo); 8 | default_reset rst(nRST); 9 | default_clock clk(CLK); 10 | method in_enq(in_enq_v) enable(in_enq__ENA) ready(in_enq__RDY); 11 | method out_deq() enable(out_deq__ENA) ready(out_deq__RDY); 12 | method out_first out_first() ready(out_first__RDY); 13 | schedule (in_enq, out_deq, out_first) CF (in_enq, out_deq, out_first); 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/aecho/generated/L_class_OC_Fifo1.bsv: -------------------------------------------------------------------------------- 1 | interface L_class_OC_Fifo1; 2 | method Action in_enq(Bit#(32) in_enq_v); 3 | method Action out_deq(); 4 | method Bit#(32) out_first(); 5 | endinterface 6 | import "BVI" l_class_OC_Fifo1 = 7 | module mkL_class_OC_Fifo1(L_class_OC_Fifo1); 8 | default_reset rst(nRST); 9 | default_clock clk(CLK); 10 | method in_enq(in_enq_v) enable(in_enq__ENA) ready(in_enq__RDY); 11 | method out_deq() enable(out_deq__ENA) ready(out_deq__RDY); 12 | method out_first out_first() ready(out_first__RDY); 13 | schedule (in_enq, out_deq, out_first) CF (in_enq, out_deq, out_first); 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Echo.cpp: -------------------------------------------------------------------------------- 1 | #include "l_class_OC_Echo.h" 2 | void l_class_OC_Echo::respond_rule(void) { 3 | unsigned int call = fifo.out_first(); 4 | fifo.out_deq(); 5 | ind->heard(call); 6 | } 7 | bool l_class_OC_Echo::respond_rule__RDY(void) { 8 | bool tmp__1 = fifo.out_first__RDY(); 9 | bool tmp__2 = fifo.out_deq__RDY(); 10 | bool tmp__3 = ind->heard__RDY(); 11 | return (tmp__1 & tmp__2) & tmp__3; 12 | } 13 | void l_class_OC_Echo::say(unsigned int say_v) { 14 | fifo.in_enq(say_v); 15 | } 16 | bool l_class_OC_Echo::say__RDY(void) { 17 | bool tmp__1 = fifo.in_enq__RDY(); 18 | return tmp__1; 19 | } 20 | void l_class_OC_Echo::run() 21 | { 22 | if (respond_rule__RDY()) respond_rule(); 23 | } 24 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Echo.h: -------------------------------------------------------------------------------- 1 | #ifndef __l_class_OC_Echo_H__ 2 | #define __l_class_OC_Echo_H__ 3 | #include "l_class_OC_Fifo1.h" 4 | #include "l_class_OC_EchoIndication.h" 5 | class l_class_OC_Echo { 6 | class l_class_OC_Fifo1 fifo; 7 | class l_class_OC_EchoIndication *ind; 8 | unsigned int pipetemp; 9 | public: 10 | void respond_rule(void); 11 | bool respond_rule__RDY(void); 12 | void say(unsigned int say_v); 13 | bool say__RDY(void); 14 | void run(); 15 | void setind(class l_class_OC_EchoIndication *v) { ind = v; } 16 | }; 17 | #endif // __l_class_OC_Echo_H__ 18 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_EchoIndication.cpp: -------------------------------------------------------------------------------- 1 | #include "l_class_OC_EchoIndication.h" 2 | void l_class_OC_EchoIndication::heard(unsigned int heard_v) { 3 | stop_main_program = 1; 4 | ("Heard an echo: %d\n")->(heard_v); 5 | } 6 | bool l_class_OC_EchoIndication::heard__RDY(void) { 7 | return 1; 8 | } 9 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_EchoIndication.h: -------------------------------------------------------------------------------- 1 | #ifndef __l_class_OC_EchoIndication_H__ 2 | #define __l_class_OC_EchoIndication_H__ 3 | class l_class_OC_EchoIndication { 4 | public: 5 | void heard(unsigned int heard_v); 6 | bool heard__RDY(void); 7 | }; 8 | #endif // __l_class_OC_EchoIndication_H__ 9 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_EchoRequest.cpp: -------------------------------------------------------------------------------- 1 | #include "l_class_OC_EchoRequest.h" 2 | void l_class_OC_EchoRequest::say(unsigned int say_v) { 3 | } 4 | bool l_class_OC_EchoRequest::say__RDY(void) { 5 | return 1; 6 | } 7 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_EchoRequest.h: -------------------------------------------------------------------------------- 1 | #ifndef __l_class_OC_EchoRequest_H__ 2 | #define __l_class_OC_EchoRequest_H__ 3 | class l_class_OC_EchoRequest { 4 | public: 5 | void say(unsigned int say_v); 6 | bool say__RDY(void); 7 | }; 8 | #endif // __l_class_OC_EchoRequest_H__ 9 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_EchoTest.cpp: -------------------------------------------------------------------------------- 1 | #include "l_class_OC_EchoTest.h" 2 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_EchoTest.h: -------------------------------------------------------------------------------- 1 | #ifndef __l_class_OC_EchoTest_H__ 2 | #define __l_class_OC_EchoTest_H__ 3 | #include "l_class_OC_Echo.h" 4 | class l_class_OC_EchoTest { 5 | class l_class_OC_Echo *echo; 6 | unsigned int x; 7 | public: 8 | void setecho(class l_class_OC_Echo *v) { echo = v; } 9 | }; 10 | #endif // __l_class_OC_EchoTest_H__ 11 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Fifo.cpp: -------------------------------------------------------------------------------- 1 | #include "l_class_OC_Fifo.h" 2 | void l_class_OC_Fifo::in_enq(unsigned int in_enq_v) { 3 | } 4 | bool l_class_OC_Fifo::in_enq__RDY(void) { 5 | return 0; 6 | } 7 | void l_class_OC_Fifo::out_deq(void) { 8 | } 9 | bool l_class_OC_Fifo::out_deq__RDY(void) { 10 | return 0; 11 | } 12 | unsigned int l_class_OC_Fifo::out_first(void) { 13 | return 0; 14 | } 15 | bool l_class_OC_Fifo::out_first__RDY(void) { 16 | return 0; 17 | } 18 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Fifo.h: -------------------------------------------------------------------------------- 1 | #ifndef __l_class_OC_Fifo_H__ 2 | #define __l_class_OC_Fifo_H__ 3 | class l_class_OC_Fifo { 4 | public: 5 | void in_enq(unsigned int in_enq_v); 6 | bool in_enq__RDY(void); 7 | void out_deq(void); 8 | bool out_deq__RDY(void); 9 | unsigned int out_first(void); 10 | bool out_first__RDY(void); 11 | }; 12 | #endif // __l_class_OC_Fifo_H__ 13 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Fifo.v: -------------------------------------------------------------------------------- 1 | module l_class_OC_Fifo ( 2 | input CLK, 3 | input nRST, 4 | input in_enq__ENA, 5 | input [31:0]in_enq_v, 6 | output in_enq__RDY, 7 | input out_deq__ENA, 8 | output out_deq__RDY, 9 | output [31:0]out_first, 10 | output out_first__RDY); 11 | wire in_enq__RDY_internal; 12 | wire in_enq__ENA_internal = in_enq__ENA && in_enq__RDY_internal; 13 | assign in_enq__RDY = in_enq__RDY_internal; 14 | wire out_deq__RDY_internal; 15 | wire out_deq__ENA_internal = out_deq__ENA && out_deq__RDY_internal; 16 | assign out_deq__RDY = out_deq__RDY_internal; 17 | assign in_enq__RDY_internal = 0; 18 | assign out_deq__RDY_internal = 0; 19 | assign out_first = 0; 20 | assign out_first__RDY_internal = 0; 21 | endmodule 22 | 23 | //METAGUARD; in_enq__RDY; 0; 24 | //METAGUARD; out_deq__RDY; 0; 25 | //METAGUARD; out_first__RDY; 0; 26 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Fifo1.cpp: -------------------------------------------------------------------------------- 1 | #include "l_class_OC_Fifo1.h" 2 | void l_class_OC_Fifo1::in_enq(unsigned int in_enq_v) { 3 | element = in_enq_v; 4 | full = 1; 5 | } 6 | bool l_class_OC_Fifo1::in_enq__RDY(void) { 7 | return full ^ 1; 8 | } 9 | void l_class_OC_Fifo1::out_deq(void) { 10 | full = 0; 11 | } 12 | bool l_class_OC_Fifo1::out_deq__RDY(void) { 13 | return full; 14 | } 15 | unsigned int l_class_OC_Fifo1::out_first(void) { 16 | return element; 17 | } 18 | bool l_class_OC_Fifo1::out_first__RDY(void) { 19 | return full; 20 | } 21 | -------------------------------------------------------------------------------- /tests/aecho/generated/l_class_OC_Fifo1.h: -------------------------------------------------------------------------------- 1 | #ifndef __l_class_OC_Fifo1_H__ 2 | #define __l_class_OC_Fifo1_H__ 3 | class l_class_OC_Fifo1 { 4 | unsigned int element; 5 | bool full; 6 | public: 7 | void in_enq(unsigned int in_enq_v); 8 | bool in_enq__RDY(void); 9 | void out_deq(void); 10 | bool out_deq__RDY(void); 11 | unsigned int out_first(void); 12 | bool out_first__RDY(void); 13 | }; 14 | #endif // __l_class_OC_Fifo1_H__ 15 | -------------------------------------------------------------------------------- /tests/aecho/generated/output.cpp: -------------------------------------------------------------------------------- 1 | void l_class_OC_Echo::respond_rule(void) { 2 | unsigned int call = fifo.first(); 3 | fifo.deq(); 4 | ind->heard(call); 5 | } 6 | bool l_class_OC_Echo::respond_rule__RDY(void) { 7 | bool tmp__1 = fifo.first__RDY(); 8 | bool tmp__2 = fifo.deq__RDY(); 9 | bool tmp__3 = ind->heard__RDY(); 10 | return (tmp__1 & tmp__2) & tmp__3; 11 | } 12 | void l_class_OC_Echo::say(unsigned int say_v) { 13 | fifo.enq(say_v); 14 | } 15 | bool l_class_OC_Echo::say__RDY(void) { 16 | bool tmp__1 = fifo.enq__RDY(); 17 | return tmp__1; 18 | } 19 | void l_class_OC_Echo::run() 20 | { 21 | if (respond_rule__RDY()) respond_rule(); 22 | } 23 | -------------------------------------------------------------------------------- /tests/aecho/generated/output.h: -------------------------------------------------------------------------------- 1 | class l_class_OC_EchoRequest { 2 | private: 3 | public: 4 | void say(unsigned int say_v); 5 | bool say__RDY(void); 6 | }; 7 | 8 | class l_class_OC_EchoIndication { 9 | private: 10 | public: 11 | void heard(unsigned int heard_v); 12 | bool heard__RDY(void); 13 | }; 14 | 15 | class l_class_OC_Echo { 16 | private: 17 | class l_class_OC_Fifo1 fifo; 18 | class l_class_OC_EchoIndication *ind; 19 | unsigned int pipetemp; 20 | public: 21 | void respond_rule(void); 22 | bool respond_rule__RDY(void); 23 | void say(unsigned int say_v); 24 | bool say__RDY(void); 25 | void run(); 26 | void setind(class l_class_OC_EchoIndication *v) { ind = v; } 27 | }; 28 | 29 | class l_class_OC_EchoTest { 30 | private: 31 | class l_class_OC_Echo *echo; 32 | unsigned int x; 33 | public: 34 | void setecho(class l_class_OC_Echo *v) { echo = v; } 35 | }; 36 | 37 | -------------------------------------------------------------------------------- /tests/algo1_flashmodel/NullResetN.bsv: -------------------------------------------------------------------------------- 1 | package NullResetN; 2 | 3 | interface NullResetNIfc; 4 | interface Reset rst_n; 5 | endinterface 6 | 7 | import "BVI" null_reset_n = 8 | module mkNullResetN (NullResetNIfc); 9 | default_clock no_clock; 10 | default_reset no_reset; 11 | 12 | output_reset rst_n(RESET_N); 13 | endmodule 14 | 15 | endpackage: NullResetN 16 | -------------------------------------------------------------------------------- /tests/algo1_nandsim_manual/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | INTERFACES = NandCfgRequest StrstrRequest NandCfgIndication StrstrIndication 4 | BSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv $(CONNECTALDIR)/examples/algo1_nandsim/Top.bsv $(CONNECTALDIR)/lib/nandsim/bsv/NandSimNames.bsv 5 | CPPFILES=algo1.cpp 6 | CPPFILES2=nandsim_manual.c 7 | CONNECTALFLAGS += -D2 NO_CPP_PORTAL_CODE -lm 8 | CONNECTALFLAGS += -D DEGPAR=2 9 | # -lblkid 10 | CONNECTALFLAGS += -I$(CONNECTALDIR)/lib/strstr/cpp 11 | CONNECTALFLAGS += -DNO_POLLER_SUPPORT 12 | 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /tests/algo1_nandsim_manual/haystack.txt: -------------------------------------------------------------------------------- 1 | acabcabacababacababababababcacabcabacababacabababc 2 | 012345678912 3 | -------------------------------------------------------------------------------- /tests/avalon_mm/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv 6 | CPPFILES= testecho.cpp 7 | 8 | CONNECTALFLAGS += --verilog verilog 9 | CONNECTALFLAGS += --systemverilog $(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1 10 | 11 | prebuild:: 12 | cd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) ip-generate \ 13 | --project-directory=$(IPDIR)/$(BOARD) \ 14 | --output-directory=$(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1 \ 15 | --report-file=spd \ 16 | --file-set=SIM_VERILOG \ 17 | ../avlm_avls_1x1.qsys; \ 18 | BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) ip-make-simscript \ 19 | --spd=$(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1/avlm_avls_1x1.spd \ 20 | --compile-to-work \ 21 | --output-directory=$(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1; 22 | 23 | include $(CONNECTALDIR)/Makefile.connectal 24 | 25 | -------------------------------------------------------------------------------- /tests/avalon_mm/TestProgram.bsv: -------------------------------------------------------------------------------- 1 | import Clocks::*; 2 | import DefaultValue::*; 3 | 4 | import "BVI" test_program = 5 | module mkTestProgram(Empty); 6 | default_clock clk(); 7 | default_reset rst(); 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/avalon_mm/verilog/tb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | 3 | module tb (); 4 | 5 | reg clk = 1'b0; 6 | reg reset = 1'b1; 7 | 8 | localparam CLOCK_PERIOD = 100; // Clock period in ps 9 | localparam INITIAL_RESET_CYCLES = 10; // Number of cycles to reset when simulation starts 10 | 11 | avlm_avls_1x1 dut( 12 | .clk_clk(clk), 13 | .reset_reset_n(~reset) 14 | ); 15 | 16 | test_program tp(); 17 | 18 | // Clock signal generator 19 | always begin 20 | #(CLOCK_PERIOD / 2); 21 | clk = ~clk; 22 | end 23 | 24 | // Initial reset 25 | initial begin 26 | repeat(INITIAL_RESET_CYCLES) @(posedge clk); 27 | reset = 1'b0; 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /tests/axieth/EthPins.bsv: -------------------------------------------------------------------------------- 1 | 2 | import AxiEthBvi::*; 3 | 4 | interface EthPins; 5 | interface AxiethbviSfp sfp; 6 | interface AxiethbviMgt mgt; 7 | interface Clock deleteme_unused_clock; 8 | interface Reset deleteme_unused_reset; 9 | endinterface 10 | 11 | (* always_ready, always_enabled *) 12 | interface AxiEthPins; 13 | interface EthPins eth; 14 | endinterface -------------------------------------------------------------------------------- /tests/axieth/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = AxiEthTestRequest:AxiEth.request 3 | H2S_INTERFACES = AxiEth:AxiEthTestIndication:host 4 | MEM_READ_INTERFACES = lAxiEth.dmaReadClient 5 | MEM_WRITE_INTERFACES = lAxiEth.dmaWriteClient 6 | 7 | CONNECTALFLAGS+= -P mkConnectalTop 8 | CONNECTALFLAGS+= --shared 9 | 10 | 11 | BSVFILES = AxiEth.bsv 12 | CPPFILES=testaxieth.cpp 13 | 14 | CONNECTALFLAGS+= -DDataBusWidth=32 15 | ## ethernet uses the 200MHz SYS clock 16 | CONNECTALFLAGS += -D XILINX_SYS_CLK -D IMPORT_HOSTIF 17 | CONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_intc_0/axi_intc_0.xci 18 | CONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_dma_0/axi_dma_0.xci 19 | CONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_ethernet_0/axi_ethernet_0.xci 20 | CONNECTALFLAGS += --constraint=axieth.xdc --implconstraint=axieth.xdc 21 | 22 | ifneq ($(BOARD),xsim) 23 | PINOUT_FILE += axieth.json 24 | endif 25 | PIN_TYPE = AxiEthPins 26 | PIN_TYPE_INCLUDE = EthPins 27 | AUTOTOP = --interface pins:AxiEth.pins 28 | 29 | include $(CONNECTALDIR)/Makefile.connectal 30 | -------------------------------------------------------------------------------- /tests/axieth/axieth.h: -------------------------------------------------------------------------------- 1 | #ifndef AXIETH_H 2 | #define AXIETH_H 3 | 4 | class AxiEthTestRequestProxy; 5 | class AxiEthTestIndication; 6 | class DmaManager; 7 | 8 | class AxiEth { 9 | public: 10 | AxiEth(); 11 | ~AxiEth(); 12 | int irq ( const uint8_t newLevel ); 13 | void status(); 14 | void setupDma( uint32_t memref ); 15 | void read(unsigned long offset, uint8_t *buf); 16 | void write(unsigned long offset, const uint8_t *buf); 17 | private: 18 | AxiEthTestRequestProxy *request; 19 | AxiEthTestIndication *indication; 20 | DmaManager *dmaManager; 21 | bool didReset; 22 | 23 | void maybeReset(); 24 | }; 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /tests/axieth/axieth.json: -------------------------------------------------------------------------------- 1 | { 2 | "eth_mgt_clk_clk_p_v": { 3 | "pins": "si5324_clk_p" 4 | }, 5 | "eth_mgt_clk_clk_n_v": { 6 | "pins": "si5324_clk_n" 7 | }, 8 | "eth_sfp_rxp_v": { 9 | "sfp1": "rxp" 10 | }, 11 | "eth_sfp_rxn_v": { 12 | "sfp1": "rxn" 13 | }, 14 | "eth_sfp_txp": { 15 | "sfp1": "txp" 16 | }, 17 | "eth_sfp_txn": { 18 | "sfp1": "txn" 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /tests/axieth/axieth.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name eth_mgt_clk_clk -period 8.000 [get_ports eth_mgt_clk_clk_p_v] 2 | -------------------------------------------------------------------------------- /tests/bluecheck-sharedmemfifo/ConnectalProjectConfig.bsv: -------------------------------------------------------------------------------- 1 | `define ConnectalVersion 15.10.3 2 | `define NumberOfMasters 1 3 | `define PinType Empty 4 | `define PinTypeInclude Misc 5 | `define NumberOfUserTiles 1 6 | `define SlaveDataBusWidth 32 7 | `define SlaveControlAddrWidth 5 8 | `define BurstLenSize 8 9 | `define project_dir $(DTOP) 10 | `define MainClockPeriod 20 11 | `define DerivedClockPeriod 10.000000 12 | `define BsimHostInterface 13 | `define PhysAddrWidth 40 14 | `define SIMULATION 15 | `define BOARD_bluesim 16 | -------------------------------------------------------------------------------- /tests/bluecheck_harness/Harness.bsv: -------------------------------------------------------------------------------- 1 | import AxiBits::*; 2 | 3 | 4 | interface HarnessRequest; 5 | method Action startTest(Bit#(16) v); 6 | endinterface 7 | interface HarnessResponse; 8 | method Action testStarted(Bit#(16) v); 9 | endinterface 10 | 11 | interface Harness; 12 | interface HarnessRequest request; 13 | endinterface 14 | 15 | module [Module] mkHarness#(HarnessResponse response)(Harness); 16 | let checker <- mkMkPhysMemSlaveChecker(); 17 | 18 | interface HarnessRequest request; 19 | method Action startTest(Bit#(16) v); 20 | $display("startTest %x is a no op", v); 21 | response.testStarted(v); 22 | endmethod 23 | endinterface 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests/bluecheck_harness/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = HarnessRequest:Harness.request 3 | H2S_INTERFACES = Harness:HarnessResponse 4 | 5 | BSVFILES = Harness.bsv 6 | PYFILES = physmemrequest.py 7 | 8 | CONNECTALFLAGS += -D BLUECHECK --bsvpath=$(CONNECTALDIR)/../bluecheck 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | 12 | -------------------------------------------------------------------------------- /tests/bpiflash/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = BpiFlashTestRequest:BpiFlashTest.request 3 | H2S_INTERFACES = BpiFlashTest:BpiFlashTestIndication 4 | 5 | CONNECTALFLAGS+= -P mkConnectalTop 6 | CONNECTALFLAGS+= --shared 7 | 8 | 9 | BSVFILES = BpiFlashTest.bsv 10 | CPPFILES=testbpiflash.cpp 11 | 12 | ifneq ($(BOARD),vc709) 13 | CONNECTALFLAGS+= --verilog=i28f512p33.v 14 | endif 15 | 16 | ifeq ($(BOARD),vc709) 17 | PINOUT_FILE += bpiflash.json 18 | PIN_TYPE = BpiPins 19 | PIN_TYPE_INCLUDE = BpiFlash 20 | AUTOTOP = --interface pins:BpiFlashTest.pins 21 | endif 22 | 23 | flash.mcs: flash.hex 24 | vivado -mode batch -source genmcs.tcl 25 | 26 | include $(CONNECTALDIR)/Makefile.connectal 27 | -------------------------------------------------------------------------------- /tests/bpiflash/bpiflash.h: -------------------------------------------------------------------------------- 1 | #ifndef BPIFLASH_H 2 | #define BPIFLASH_H 3 | 4 | class BpiFlashTestRequestProxy; 5 | class BpiFlashTestIndication; 6 | 7 | class BpiFlash { 8 | public: 9 | BpiFlash(); 10 | ~BpiFlash(); 11 | void read(unsigned long offset, uint8_t *buf); 12 | void write(unsigned long offset, const uint8_t *buf); 13 | private: 14 | BpiFlashTestRequestProxy *request; 15 | BpiFlashTestIndication *indication; 16 | bool didReset; 17 | 18 | void maybeReset(); 19 | }; 20 | 21 | #endif 22 | 23 | -------------------------------------------------------------------------------- /tests/ddr3/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = Ddr3TestRequest:Ddr3Test.request 3 | H2S_INTERFACES = Ddr3Test:Ddr3TestIndication:host 4 | MEM_READ_INTERFACES = lDdr3Test.readClient 5 | MEM_WRITE_INTERFACES = lDdr3Test.writeClient 6 | 7 | ifneq ($(BOARD),zc706) 8 | ifneq ($(BOARD),miniitx100) 9 | CONNECTALFLAGS += -D DataBusWidth=128 10 | endif 11 | endif 12 | CONNECTALFLAGS += -D IMPORT_HOSTIF -D XILINX_SYS_CLK 13 | CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/axiddr3/axiddr3.xci 14 | 15 | BSVFILES = Ddr3Test.bsv 16 | CPPFILES=testddr3.cpp 17 | 18 | PIN_TYPE = Ddr3Pins 19 | PIN_TYPE_INCLUDE = AxiDdr3Controller 20 | AUTOTOP = --interface pins:Ddr3Test.ddr3 21 | 22 | include $(CONNECTALDIR)/Makefile.connectal 23 | -------------------------------------------------------------------------------- /tests/ddr3/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source board.tcl 2 | source $connectaldir/scripts/connectal-synth-axiddr3.tcl 3 | -------------------------------------------------------------------------------- /tests/ddr3_altera/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = Ddr3TestRequest:Ddr3Test.request 3 | H2S_INTERFACES = Ddr3Test:Ddr3TestIndication:host 4 | MEM_READ_INTERFACES = lDdr3Test.readClient 5 | 6 | ifneq ($(BOARD),zc706) 7 | CONNECTALFLAGS += -D DataBusWidth=128 8 | endif 9 | CONNECTALFLAGS += -D IMPORT_HOSTIF -D XILINX_SYS_CLK 10 | CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/synthesis/altera_mem_if_ddr3_emif_wrapper/altera_mem_if_ddr3_emif_wrapper.qip 11 | 12 | BSVFILES = Ddr3Test.bsv 13 | CPPFILES=testddr3.cpp 14 | 15 | PIN_BINDINGS ?= DDR3B:DDR3B PCIE:PCIE OSC:OSC RZQ:RZQ 16 | PINOUT_FILE = de5.json 17 | 18 | PIN_TYPE = Ddr3Pins 19 | PIN_TYPE_INCLUDE = AvalonDdr3Controller 20 | AUTOTOP = --interface pins:Ddr3Test.pins 21 | 22 | prebuild:: 23 | (cd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) $(QUARTUS_SH) -t $(CONNECTALDIR)/scripts/connectal-synth-avalonddr3.tcl) 24 | 25 | include $(CONNECTALDIR)/Makefile.connectal 26 | -------------------------------------------------------------------------------- /tests/ddr3_altera/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source $connectaldir/scripts/connectal-synth-avalonddr3.tcl 2 | -------------------------------------------------------------------------------- /tests/ddr_minimal/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = Ddr3TestRequest:Ddr3Test.request 3 | H2S_INTERFACES = Ddr3Test:Ddr3TestIndication:host 4 | 5 | ifneq ($(BOARD),zc706) 6 | ifneq ($(BOARD),miniitx100) 7 | CONNECTALFLAGS += -D DataBusWidth=128 8 | endif 9 | endif 10 | CONNECTALFLAGS += -D IMPORT_HOSTIF -D XILINX_SYS_CLK 11 | CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/axiddr3/axiddr3.xci 12 | 13 | BSVFILES = Ddr3Test.bsv 14 | CPPFILES=testddr3.cpp 15 | 16 | PIN_TYPE = Ddr3Pins 17 | PIN_TYPE_INCLUDE = AxiDdr3Controller 18 | AUTOTOP = --interface pins:Ddr3Test.ddr3 19 | 20 | include $(CONNECTALDIR)/Makefile.connectal 21 | -------------------------------------------------------------------------------- /tests/ddr_minimal/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source board.tcl 2 | source $connectaldir/scripts/connectal-synth-axiddr3.tcl 3 | -------------------------------------------------------------------------------- /tests/dma2bram/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = TestRequest:Test.request 3 | H2S_INTERFACES = Test:TestIndication 4 | MEM_READ_INTERFACES = lTest.dmaClient 5 | 6 | BSVFILES = Test.bsv 7 | CPPFILES=test.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /tests/dram_awsf1/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = Ddr3TestRequest:DdrAws.request 3 | H2S_INTERFACES = DdrAws:Ddr3TestIndication 4 | 5 | BSVFILES= \ 6 | DdrAws.bsv\ 7 | Axi4.bsv 8 | 9 | CPPFILES= testddr3.cpp 10 | 11 | 12 | PIN_TYPE = Axi4 13 | PIN_TYPE_INCLUDE = Axi4 14 | AUTOTOP = --interface pins:DdrAws.ddr3 15 | 16 | CONNECTALFLAGS += -D AWSF1_DDR_A 17 | 18 | include $(CONNECTALDIR)/Makefile.connectal 19 | -------------------------------------------------------------------------------- /tests/echosoft2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:EchoId.request SwallowRequest:Swallow.request 3 | H2S_INTERFACES = EchoId:EchoIndication 4 | 5 | BSVFILES = EchoId.bsv ../../examples/echosoft/Swallow.bsv 6 | CPPFILES=testecho.cpp 7 | CPPFILES2=daemon.cpp 8 | AUTOTOP = --portname IfcNames_EchoIndication2H2S --portname IfcNames_EchoRequest2S2H 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/fastecho/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | S2H_INTERFACES = \ 4 | FastEchoRequestA:FastEcho.requestA \ 5 | FastEchoRequestB:FastEcho.requestB \ 6 | FastEchoRequestC:FastEcho.requestC \ 7 | FastEchoRequestD:FastEcho.requestD \ 8 | 9 | H2S_INTERFACES = \ 10 | FastEcho:FastEchoIndicationA \ 11 | FastEcho:FastEchoIndicationB \ 12 | FastEcho:FastEchoIndicationC \ 13 | FastEcho:FastEchoIndicationD \ 14 | 15 | BSVFILES = FastEcho.bsv 16 | CPPFILES = testfastecho.cpp 17 | 18 | # This matches the frequency of the original design where the bug was found 19 | CONNECTALFLAGS += --mainclockperiod=32 20 | CONNECTALFLAGS += -D GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO 21 | CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/dual_clock_axis_fifo_32x8/dual_clock_axis_fifo_32x8.xci 22 | 23 | include $(CONNECTALDIR)/Makefile.connectal 24 | 25 | -------------------------------------------------------------------------------- /tests/fastecho/about_this_test.txt: -------------------------------------------------------------------------------- 1 | This test reproduces the bug reported in issue #133 on github. 2 | https://github.com/cambridgehackers/connectal/issues/133 3 | 4 | When this design is built for kc705g2 and run on FPGA, it typically stalls 5 | after a few thousand requests and indications. 6 | -------------------------------------------------------------------------------- /tests/fastecho/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/../fpgamake/tcl/ipcore.tcl" 3 | 4 | if {[version -short] >= "2016.1"} { 5 | set dual_clock_axis_fifo_version 13.1 6 | } else { 7 | set dual_clock_axis_fifo_version 13.0 8 | } 9 | 10 | fpgamake_ipcore fifo_generator $dual_clock_axis_fifo_version dual_clock_axis_fifo_32x8 [list \ 11 | config.interface_type {axi_stream} \ 12 | config.clock_type_axi {independent_clock} \ 13 | config.tdata_num_bytes {4} \ 14 | config.tuser_width {0} \ 15 | config.enable_tlast {true} \ 16 | config.has_tkeep {true} \ 17 | config.fifo_application_type_axis {data_fifo} \ 18 | config.reset_type {asynchronous_reset} \ 19 | ] 20 | 21 | -------------------------------------------------------------------------------- /tests/float/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | run: floatTestBench 4 | ./floatTestBench 5 | 6 | ctest: 7 | gcc -o ftest ftest.c 8 | ./ftest 9 | rm -f ftest 10 | 11 | floatTestBench: FloatTest.bsv 12 | mkdir -p obj 13 | bsc --show-schedule -sim -info-dir obj -bdir obj -p +:$(CONNECTALDIR)/lib/bsv -g mkFloatTestBench -u $< 14 | bsc --show-schedule -sim -info-dir obj -bdir obj -e mkFloatTestBench -o floatTestBench 15 | 16 | clean: 17 | rm -rf floatTestBench* mkFloatTestBench.* model_mkFloatTestBench.* dump.vcd obj 18 | -------------------------------------------------------------------------------- /tests/float/ftest.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() 4 | { 5 | union { 6 | float f; 7 | unsigned int i; 8 | } dfloat; 9 | union { 10 | double f; 11 | unsigned long i; 12 | } ddouble; 13 | 14 | printf("[%s:%d] sizeof(float) %ld sizeof(double) %ld\n", __FUNCTION__, __LINE__, sizeof(float), sizeof(double)); 15 | dfloat.i = 0x3f60be97; 16 | printf("[%s:%d] f %f\n", __FUNCTION__, __LINE__, dfloat.f); 17 | printf("[%s:%d] i %x\n", __FUNCTION__, __LINE__, dfloat.i); 18 | dfloat.f = 3.14159; 19 | printf("[%s:%d] 2f %f\n", __FUNCTION__, __LINE__, dfloat.f); 20 | printf("[%s:%d] 2i %x\n", __FUNCTION__, __LINE__, dfloat.i); 21 | ddouble.f = 3.14159; 22 | printf("[%s:%d] 2f %f\n", __FUNCTION__, __LINE__, ddouble.f); 23 | printf("[%s:%d] 2i %lx\n", __FUNCTION__, __LINE__, ddouble.i); 24 | return 0; 25 | } 26 | -------------------------------------------------------------------------------- /tests/fp/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = FpRequest:FpTest.request 3 | H2S_INTERFACES = FpTest:FpIndication 4 | 5 | BSVFILES = FpTest.bsv 6 | CPPFILES=testfp.cpp 7 | CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/fp_add/fp_add.xci --xci=$(IPDIR)/$(BOARD)/fp_mul/fp_mul.xci 8 | 9 | FP_ADD_V = $(IPDIR)/$(BOARD)/fp_add/fp_add_stub.v 10 | 11 | ifeq ($(BOARD),bluesim) 12 | # not for bluesim 13 | else 14 | ## 15 | ## the prebuild target will be made after the project directory is generated, e.g., by make gen.zedboard 16 | ## 17 | prebuild:: $(FP_ADD_V) BviFpAdd.bsv 18 | 19 | $(FP_ADD_V): synth-ip.tcl 20 | (cd $(BOARD); vivado -mode batch -source ../synth-ip.tcl) 21 | endif 22 | 23 | ## 24 | ## Generate the import "BVI" from the generated stub for the core: fp_add_stub.v 25 | ## Then, hand-modified so it works 26 | BviFpAdd.bsv: 27 | $(CONNECTALDIR)/scripts/importbvi.py -o BviFpAdd.bsv -c aclk -f s_axis_a -f s_axis_b -f m_axis_result -I BviFpAdd -P BviFpAdd $(FP_ADD_V) 28 | 29 | include $(CONNECTALDIR)/Makefile.connectal 30 | -------------------------------------------------------------------------------- /tests/fp/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source board.tcl 2 | source $connectaldir/scripts/connectal-synth-ip.tcl 3 | 4 | connectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 5 | connectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 6 | -------------------------------------------------------------------------------- /tests/guard/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | run: guardTestBench 4 | #./guardTestBench 5 | 6 | guardTestBench: GuardTest.bsv 7 | mkdir -p obj 8 | bsc --show-schedule -aggressive-conditions \ 9 | -sim -info-dir obj -bdir obj -p +:$(CONNECTALDIR)/lib/bsv -g mkGuardTestBench -u $< 10 | bsc --show-schedule -sim -info-dir obj -bdir obj -e mkGuardTestBench -o guardTestBench 11 | 12 | clean: 13 | rm -rf guardTestBench* mkGuardTestBench.* model_mkGuardTestBench.* dump.vcd obj 14 | -------------------------------------------------------------------------------- /tests/guard/gtest.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() 4 | { 5 | return 0; 6 | } 7 | -------------------------------------------------------------------------------- /tests/ipcperf/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = IpcTestRequest:IpcTest.request 3 | H2S_INTERFACES = IpcTest:IpcTestIndication 4 | 5 | BSVFILES = IpcTest.bsv 6 | CPPFILES=testipctest.cpp 7 | ## for testing fpgamake: 8 | FPGAMAKE_CONNECTALFLAGS += -P mkIpcTestIndicationProxySynth -P mkIpcTestRequestWrapperMemPortalPipes 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/memcpy_manysglists/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | MEMCPYDIR=$(CONNECTALDIR)/examples/memcpy 4 | INTERFACES = MemcpyRequest MemcpyIndication 5 | BSVFILES = $(MEMCPYDIR)/Memcpy.bsv Top.bsv 6 | CPPFILES=testmemcpy.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /tests/memread_err/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | S2H_INTERFACES = MemreadRequest:Memread.request 3 | H2S_INTERFACES = Memread:MemreadIndication 4 | MEM_READ_INTERFACES = cons\(lMemread.dmaClient,nil\) 5 | 6 | BSVFILES = Memread.bsv 7 | CPPFILES=testmemread.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /tests/memread_manual/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 3 | H2S_INTERFACES = ReadTest:ReadTestIndication 4 | MEM_READ_INTERFACES = lReadTest.dmaClient 5 | 6 | BSVFILES = ReadTest.bsv 7 | CPPFILES=memread_manual_manager.c 8 | #CONNECTALFLAGS += -D NO_CPP_PORTAL_CODE -D NO_POLLER_SUPPORT 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/memread_manual/vc707_floorplan.xdc: -------------------------------------------------------------------------------- 1 | startgroup 2 | create_pblock pblock_ep7 3 | resize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32} 4 | add_cells_to_pblock pblock_ep7 [get_cells [list ep7]] -clear_locs 5 | endgroup 6 | 7 | startgroup 8 | create_pblock pblock_pciehost 9 | resize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X171Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38 BUFGCTRL_X0Y16} 10 | add_cells_to_pblock pblock_pciehost [get_cells [list pciehost]] -clear_locs 11 | endgroup 12 | 13 | startgroup 14 | create_pblock pblock_portalTop 15 | resize_pblock pblock_portalTop -add {SLICE_X0Y25:SLICE_X101Y247 DSP48_X0Y10:DSP48_X7Y97 RAMB18_X0Y10:RAMB18_X6Y97 RAMB36_X0Y5:RAMB36_X6Y48} 16 | add_cells_to_pblock pblock_portalTop [get_cells [list portalTop]] -clear_locs 17 | endgroup 18 | -------------------------------------------------------------------------------- /tests/memread_manyclients/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | MEMREADDIR=$(CONNECTALDIR)/examples/memread 3 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 4 | H2S_INTERFACES = ReadTest:ReadTestIndication 5 | MEM_READ_INTERFACES = lReadTest.dmaClient 6 | 7 | BSVFILES = $(MEMREADDIR)/ReadTest.bsv 8 | CPPFILES = $(MEMREADDIR)/testmemread.cpp 9 | CONNECTALFLAGS += -D NumEngineServers=16 10 | CONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /tests/memread_manyclients/performance.txt: -------------------------------------------------------------------------------- 1 | 2 | Memread Manyclients 3 | DataBusWidth | BufferSize | NumServers | NumRequests | Utilization | Bandwidth 4 | 64 | 256 | 16 | 2 | 0.944658 | 0.995 GB/s 5 | 128 | 256 | 16 | 2 | 0.559449 | 1.119 GB/s 6 | 128 | 256 | 16 | 4 | locks up 7 | 128 | 512 | 8 | 4 | locks up 8 | 128 | 512 | 8 | 2 | stalls 9 | 128 | 512 | 1 | 2 | 10 | -------------------------------------------------------------------------------- /tests/memread_manyclients128/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | MEMREADDIR=$(CONNECTALDIR)/examples/memread 3 | S2H_INTERFACES = MemreadRequest:Memread.request 4 | H2S_INTERFACES = Memread:MemreadIndication 5 | MEM_READ_INTERFACES = lMemread.dmaClient 6 | 7 | BSVFILES = $(MEMREADDIR)/Memread.bsv 8 | CPPFILES = $(MEMREADDIR)/testmemread.cpp 9 | CONNECTALFLAGS += -D NumEngineServers=8 -D DataBusWidth=128 10 | CONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread 11 | 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /tests/memread_manyengines/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = ReadTestRequest:ReadTest.request 3 | H2S_INTERFACES = ReadTest\#\(\`NumEngines\):ReadTestIndication 4 | MEM_READ_INTERFACES = lReadTest.dmaClients 5 | 6 | BSVFILES = ReadTest.bsv 7 | CPPFILES = ../../examples/memread/testmemread.cpp 8 | CONNECTALFLAGS += --bscflags " -D DataBusWidth=128 -D NumEngines=4" 9 | CONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | 13 | -------------------------------------------------------------------------------- /tests/memserver_copy/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemcopyRequest:Memcopy.request 3 | H2S_INTERFACES = Memcopy:MemcopyIndication 4 | MEM_READ_INTERFACES = lMemcopy.readClients 5 | MEM_WRITE_INTERFACES = lMemcopy.writeClients 6 | 7 | BSVFILES = ../memserver_copy/Memcopy.bsv 8 | CPPFILES = ../memserver_copy/testmemcopy.cpp 9 | CONNECTALFLAGS += -D USE_ACP -P mkConnectalTop 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/memserver_copy128/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemcopyRequest:Memcopy.request 3 | H2S_INTERFACES = Memcopy:MemcopyIndication 4 | MEM_READ_INTERFACES = lMemcopy.readClients 5 | MEM_WRITE_INTERFACES = lMemcopy.writeClients 6 | 7 | BSVFILES = ../memserver_copy/Memcopy.bsv 8 | CPPFILES = ../memserver_copy/testmemcopy.cpp 9 | CONNECTALFLAGS += -D USE_ACP -P mkConnectalTop -D DataBusWidth=128 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/memserver_copy_slow/Makefile: -------------------------------------------------------------------------------- 1 | include ../memserver_copy/Makefile 2 | 3 | CONNECTALFLAGS += --mainclockperiod=30 4 | -------------------------------------------------------------------------------- /tests/memserver_write/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClients 5 | 6 | BSVFILES = Memwrite.bsv 7 | CPPFILES = testmemwrite.cpp 8 | CONNECTALFLAGS += -D USE_ACP -P mkConnectalTop -D BYTE_ENABLES 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/memserver_write128/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | MSWDIR=../memserver_write/ 3 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 4 | H2S_INTERFACES = Memwrite:MemwriteIndication 5 | MEM_WRITE_INTERFACES = lMemwrite.dmaClients 6 | 7 | BSVFILES = $(MSWDIR)/Memwrite.bsv 8 | CPPFILES = $(MSWDIR)/testmemwrite.cpp 9 | CONNECTALFLAGS += -D USE_ACP -P mkConnectalTop -D DataBusWidth=128 -D BYTE_ENABLES 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/memtopcie_bluesim/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | MEMREADDIR=$(CONNECTALDIR)/examples/memread 4 | INTERFACES = MemreadRequest MemreadIndication 5 | BSVFILES = $(MEMREADDIR)/Memread.bsv Top.bsv 6 | CPPFILES = $(MEMREADDIR)/testmemread.cpp 7 | CONNECTALFLAGS += -D NumEngineServers=16 -D DataBusWidth=128 8 | CONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread 9 | #CONNECTALFLAGS += --bscflags " -show-schedule" 10 | 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/memwrite_acp/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 5 | 6 | BSVFILES = Memwrite.bsv 7 | CPPFILES = testmemwrite.cpp 8 | CONNECTALFLAGS += -D USE_ACP 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/memwrite_manyclients/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | MEMWRITEDIR=$(CONNECTALDIR)/examples/memwrite 3 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 4 | H2S_INTERFACES = Memwrite:MemwriteIndication 5 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 6 | 7 | BSVFILES = $(MEMWRITEDIR)/Memwrite.bsv 8 | CPPFILES = $(MEMWRITEDIR)/testmemwrite.cpp 9 | CONNECTALFLAGS += -D NumEngineServers=16 10 | CONNECTALFLAGS += --bscflags " -show-schedule" 11 | #CONNECTALFLAGS += --bscflags " -ddumpschedule" 12 | 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /tests/memwrite_manyclients128/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | MEMWRITEDIR=$(CONNECTALDIR)/examples/memwrite 3 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 4 | H2S_INTERFACES = Memwrite:MemwriteIndication 5 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 6 | 7 | BSVFILES = $(MEMWRITEDIR)/Memwrite.bsv 8 | CPPFILES = $(MEMWRITEDIR)/testmemwrite.cpp 9 | CONNECTALFLAGS += -D NumEngineServers=8 -D DataBusWidth=128 10 | CONNECTALFLAGS += --bscflags " -show-schedule" 11 | #CONNECTALFLAGS += --bscflags " -ddumpschedule" 12 | 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /tests/memwrite_trivial/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | MEM_WRITE_INTERFACES = lMemwrite.dmaClient 5 | 6 | BSVFILES = Memwrite.bsv 7 | CPPFILES = testmemwrite.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /tests/memwriteengine_test/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MemwriteRequest:Memwrite.request 3 | H2S_INTERFACES = Memwrite:MemwriteIndication 4 | #MEM_WRITE_INTERFACES = lMemwrite.dmaClients 5 | 6 | BSVFILES = Memwrite.bsv 7 | CPPFILES = testmemwrite.cpp 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /tests/method/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MethodRequest:Method.request 3 | 4 | BSVFILES = Method.bsv 5 | CPPFILES= mtest.cpp 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | 9 | -------------------------------------------------------------------------------- /tests/method/mtest.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() 4 | { 5 | return 0; 6 | } 7 | -------------------------------------------------------------------------------- /tests/mifo/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = MifoTestRequest:MifoTest.request 3 | H2S_INTERFACES = MifoTest:MifoTestIndication 4 | 5 | BSVFILES = MifoTest.bsv 6 | CPPFILES=testmifo.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /tests/nandsim_manual/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = NandCfgRequest:NandSim.request 3 | H2S_INTERFACES = NandSim:NandCfgIndication 4 | MEM_READ_INTERFACES = lNandSim.readClient 5 | MEM_WRITE_INTERFACES = lNandSim.writeClient 6 | 7 | NANDLIB = ../../lib/nandsim 8 | BSVFILES = $(NANDLIB)/bsv/NandSim.bsv 9 | CPPFILES=testnandsim_test.cpp 10 | #CPPFILES=testnandsim.cpp 11 | #CPPFILES=nandsim_manual.c 12 | 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /tests/nvme_strstr/fmc.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "FMC": "FMC_GBTCLK_P[00]" 4 | }, 5 | "pcie_refclk_n": { 6 | "FMC": "FMC_GBTCLK_N[00]" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "FMC": "FMC_LA_P[00]", 10 | "IOSTANDARD": "LVCMOS18", 11 | "PIO_DIRECTION": "OUTPUT" 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /tests/nvme_strstr/nfsume.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "FMC": "FMC_GBTCLK_P[00]" 4 | }, 5 | "pcie_refclk_n": { 6 | "FMC": "FMC_GBTCLK_N[00]" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "FMC": "FMC_LA_P[00]", 10 | "IOSTANDARD": "LVCMOS18", 11 | "PIO_DIRECTION": "OUTPUT" 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /tests/nvme_strstr/nvme.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "pcie": "sys_clk_p" 4 | }, 5 | "pcie_refclk_n": { 6 | "pcie": "sys_clk_n" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "pcie": "sys_reset_n" 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /tests/nvme_strstr/nvme.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name root_pci_refclk -period 10 [get_ports pcie_refclk_p] 2 | 3 | set_max_delay -from [get_clocks {userclk2}] -to [get_clocks {userclk1}] 4.0 -datapath_only 4 | set_max_delay -to [get_clocks {userclk2}] -from [get_clocks {userclk1}] 4.0 -datapath_only 5 | 6 | set_max_delay -from [get_clocks {userclk2}] -to [get_clocks {clk_125mhz_mux_*}] 4.0 -datapath_only 7 | set_max_delay -to [get_clocks {userclk2}] -from [get_clocks {clk_125mhz_mux_*}] 4.0 -datapath_only 8 | 9 | set_max_delay -from [get_clocks {userclk2}] -to [get_clocks {clk_250mhz_mux_*}] 4.0 -datapath_only 10 | set_max_delay -to [get_clocks {userclk2}] -from [get_clocks {clk_250mhz_mux_*}] 4.0 -datapath_only 11 | -------------------------------------------------------------------------------- /tests/nvme_test/fmc.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "FMC": "FMC_GBTCLK_P[00]" 4 | }, 5 | "pcie_refclk_n": { 6 | "FMC": "FMC_GBTCLK_N[00]" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "FMC": "FMC_LA_P[00]", 10 | "IOSTANDARD": "LVCMOS18", 11 | "PIO_DIRECTION": "OUTPUT" 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /tests/nvme_test/impl.tcl: -------------------------------------------------------------------------------- 1 | set dbgs [get_nets -hierarchical -filter {MARK_DEBUG}] 2 | if {[llength $dbgs] > 0} { 3 | set_property mark_debug false $dbgs 4 | } 5 | 6 | opt_design 7 | place_design 8 | phys_opt_design 9 | route_design 10 | write_bitstream -force debug.bit 11 | write_debug_probes -force debug.ltx 12 | report_timing_summary -file debug_timing_summary.txt 13 | -------------------------------------------------------------------------------- /tests/nvme_test/miniitx100.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "pcie": "sys_clk_p" 4 | }, 5 | "pcie_refclk_n": { 6 | "pcie": "sys_clk_n" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "pcie": "sys_reset_n" 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /tests/nvme_test/nfsume.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "FMC": "FMC_GBTCLK_P[00]" 4 | }, 5 | "pcie_refclk_n": { 6 | "FMC": "FMC_GBTCLK_N[00]" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "FMC": "FMC_LA_P[00]", 10 | "IOSTANDARD": "LVCMOS18", 11 | "PIO_DIRECTION": "OUTPUT" 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /tests/nvme_test/nfsume.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN "AT8" [get_ports "pcie_refclk_p"] 2 | set_property DIFF_TERM "TRUE" [get_ports "pcie_refclk_p"] 3 | set_property PACKAGE_PIN "AT7" [get_ports "pcie_refclk_n"] 4 | set_property DIFF_TERM "TRUE" [get_ports "pcie_refclk_n"] 5 | set_property PACKAGE_PIN "AU28" [get_ports "RST_N_pcie_sys_reset_n"] 6 | set_property IOSTANDARD "LVCMOS18" [get_ports "RST_N_pcie_sys_reset_n"] 7 | set_property PIO_DIRECTION "OUTPUT" [get_ports "RST_N_pcie_sys_reset_n"] 8 | 9 | -------------------------------------------------------------------------------- /tests/ov7670/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = Ov7670ControllerRequest:Ov7670Controller.request 3 | H2S_INTERFACES = Ov7670Controller:Ov7670ControllerIndication 4 | MEM_WRITE_INTERFACES = lOv7670Controller.dmaClient 5 | 6 | BSVFILES = Ov7670Interface.bsv 7 | CPPFILES= testcam.cpp 8 | 9 | PIN_TYPE = Ov7670Pins 10 | PIN_TYPE_INCLUDE = Ov7670Interface 11 | PINOUT_FILE = pinout.json 12 | AUTOTOP = --interface pins:Ov7670Controller.pins 13 | 14 | include $(CONNECTALDIR)/Makefile.connectal 15 | -------------------------------------------------------------------------------- /tests/partial/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:Echo.request 3 | H2S_INTERFACES = Echo:EchoIndication 4 | 5 | BSVFILES = Echo.bsv 6 | CPPFILES= testecho.cpp 7 | 8 | VARIANT?=1 9 | VARIANT_LIST = 2 3 10 | PARTIAL_MODULE = Bounce 11 | RECONFIG_MODULE = lEcho_bounce 12 | CONNECTALFLAGS += -P mk$(PARTIAL_MODULE) --implconstraint=floorplan-$(BOARD).xdc -DRedefInstance=$(PARTIAL_MODULE)$(VARIANT) 13 | 14 | include $(CONNECTALDIR)/Makefile.connectal 15 | -------------------------------------------------------------------------------- /tests/partial/README: -------------------------------------------------------------------------------- 1 | 2 | To program PR bitfile: 3 | 4 | echo 1 /sys/devices/amba.2/f8007000.devcfg/is_partial_bitstream 5 | cat variant2/Impl/ReTop/mkTop_pblock_lEcho_bounce_partial.bin >/dev/xdevcfg 6 | cat variant2/Impl/ReTop/mkTop_pblock_lEcho_bounce_partial.bin >/dev/xdevcfg 7 | ./android.exe 8 | 9 | Note: 10 | is_partial_bitstream is persistent 11 | -------------------------------------------------------------------------------- /tests/partial/floorplan-zc702.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_pblock pblock_lEcho_bounce 3 | add_cells_to_pblock [get_pblocks pblock_lEcho_bounce] [get_cells -quiet [list top/lEcho_bounce]] 4 | resize_pblock [get_pblocks pblock_lEcho_bounce] -add {SLICE_X34Y100:SLICE_X47Y149} 5 | resize_pblock [get_pblocks pblock_lEcho_bounce] -add {DSP48_X2Y40:DSP48_X2Y59} 6 | set_property SNAPPING_MODE ON [get_pblocks pblock_lEcho_bounce] 7 | -------------------------------------------------------------------------------- /tests/pcie-debug/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = EchoRequest:TracePcie.request ChangeRequest:TracePcie.changeRequest 3 | H2S_INTERFACES = TracePcie:ChangeIndication:host TracePcie:EchoIndication 4 | 5 | BSVFILES = TracePcie.bsv 6 | CPPFILES= tracepcie.cpp 7 | 8 | CONNECTALFLAGS += -D TRACE_PORTAL 9 | 10 | CONNECTALFLAGS += -D IMPORT_HOSTIF -D PCIE_CHANGES_HOSTIF -D TracePcieStateMachine 11 | CONNECTALFLAGS += -D PCIE_CHANGES_SERIAL 12 | CONNECTALFLAGS += -D PCIE_CHANGES_UART 13 | CONNECTALFLAGS += -D PCIE_ALT_BRAM_SERVER -D PCIE_TRACE_PORT 14 | PINOUT_FILE += pin_translation.json 15 | PIN_TYPE = TestPins 16 | PIN_TYPE_INCLUDE = TestPins 17 | AUTOTOP = --interface pins:TracePcie.pins 18 | 19 | include $(CONNECTALDIR)/Makefile.connectal 20 | 21 | -------------------------------------------------------------------------------- /tests/pcie-debug/TestPins.bsv: -------------------------------------------------------------------------------- 1 | import Clocks::*; 2 | 3 | (* always_ready, always_enabled *) 4 | interface UartPins; 5 | method Bit#(1) sout(); 6 | method Action sin(Bit#(1) v); 7 | interface Clock deleteme_unused_clock; 8 | endinterface 9 | interface TestPins; 10 | interface UartPins uart; 11 | endinterface 12 | -------------------------------------------------------------------------------- /tests/pcie-debug/pin_translation.json: -------------------------------------------------------------------------------- 1 | { 2 | "uart_sout": { 3 | "uart": "d_out" 4 | }, 5 | "uart_sin_v": { 6 | "uart": "d_in" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /tests/pciememcheck/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = PcieMemCheckRequest:PcieMemCheck.request 3 | H2S_INTERFACES = PcieMemCheck:PcieMemCheckIndication 4 | 5 | BSVFILES = PcieMemCheck.bsv 6 | CPPFILES = pciememcheck.cpp 7 | CONNECTALFLAGS += -D USE_ACP -P mkConnectalTop 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /tests/physmaster/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | INTERFACES = EchoRequest EchoIndication PhysMemMasterRequest PhysMemMasterIndication 3 | 4 | BSVFILES = Echo.bsv PhysReq.bsv 5 | CPPFILES=daemon.cpp 6 | CPPFILES2=testecho.cpp 7 | CONNECTALFLAGS += --nohardware 8 | AUTOTOP= --portname IfcNames_PhysMemMasterIndication --portname IfcNames_PhysMemMasterRequest 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/qemuaccel/AccelIfcNames.bsv: -------------------------------------------------------------------------------- 1 | 2 | typedef enum {AccelIfcNamesNone=0, 3 | PlatformAccelIfcNames_MemServerRequestS2H=1, 4 | PlatformAccelIfcNames_MMURequestS2H=2, 5 | PlatformAccelIfcNames_MemServerIndicationH2S=3, 6 | PlatformAccelIfcNames_MMUIndicationH2S=4, 7 | AccelIfcNames_SerialIndicationH2S=5, 8 | AccelIfcNames_SimpleRequestH2S=6, 9 | AccelIfcNames_BlockDevResponseH2S=7, 10 | AccelIfcNames_SerialRequestS2H=8, 11 | AccelIfcNames_SimpleRequestS2H=9, 12 | AccelIfcNames_BlockDevRequestS2H=10 13 | } AccelIfcNames deriving (Eq,Bits); 14 | -------------------------------------------------------------------------------- /tests/qemuaccel/Devices.bsv: -------------------------------------------------------------------------------- 1 | import BlockDev::*; 2 | import Serial::*; 3 | import Simple::*; 4 | 5 | interface DevicesPorts; 6 | interface SerialPort serial; 7 | interface Client#(BlockDevTransfer,Bit#(32)) blockDev; 8 | endinterface 9 | 10 | interface Devices; 11 | interface SimpleRequest simple; 12 | interface SerialPort serial; 13 | interface BlockDevPort blockDev; 14 | interface DevicesPorts ports; 15 | endinterface 16 | 17 | module mkDevices#(SimpleIndication simpleIndication, 18 | SerialIndication serialIndication, 19 | BlockDevResponse blockDevResponse)(Devices); 20 | let simple <- mksimple(simpleIndication); 21 | let serial <- mkSerial(serialIndication); 22 | let blockDev <- mkBlockDev(blockDevResponse); 23 | 24 | interface SimpleRequest simple= simple.request; 25 | interface SerialPort serial = serial.request; 26 | interface BlockDevPort blockDev = blockDev.request; 27 | 28 | interface DevicesPorts ports; 29 | interface SerialPort serial = serial.port; 30 | interface Client client = blockDev.client; 31 | endinterface 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/qemuaccel/qemuaccel.cpp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | int main(int argc, const char **argv) 5 | { 6 | return 0; 7 | } 8 | -------------------------------------------------------------------------------- /tests/rootport/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | S2H_INTERFACES = RootPortRequest:RootPort.request 4 | H2S_INTERFACES = RootPort:RootPortIndication,RootPortTrace:host 5 | 6 | MEM_READ_INTERFACES = lRootPort.dmaReadClient 7 | MEM_WRITE_INTERFACES = lRootPort.dmaWriteClient 8 | 9 | BSVFILES = RootPortIfc.bsv $(CONNECTALDIR)/bsv/ConnectalConfig.bsv 10 | CPPFILES= rootport.cpp 11 | 12 | PINOUT_FILE += rootport.json 13 | PIN_TYPE = RootPortPins 14 | PIN_TYPE_INCLUDE = RootPortPins 15 | AUTOTOP = --interface pins:RootPort.pins 16 | 17 | AUTOTOP += --portalclock=lRootPort.portalClockSource 18 | CONNECTALFLAGS += -D USE_ACP 19 | CONNECTALFLAGS += -D TOP_SOURCES_PORTAL_CLOCK --mainclockperiod=8 20 | 21 | CONNECTALFLAGS += -D IMPORT_HOSTIF --bsvpath=../spikehw 22 | CONNECTALFLAGS += --xci=cores/$(BOARD)/axi_pcie_rp/axi_pcie_rp.xci 23 | CONNECTALFLAGS += --implconstraint=rootport.xdc 24 | 25 | include $(CONNECTALDIR)/Makefile.connectal 26 | -------------------------------------------------------------------------------- /tests/rootport/rootport.json: -------------------------------------------------------------------------------- 1 | { 2 | "pcie_refclk_p": { 3 | "pcie": "sys_clk_p" 4 | }, 5 | "pcie_refclk_n": { 6 | "pcie": "sys_clk_n" 7 | }, 8 | "RST_N_pcie_sys_reset_n": { 9 | "pcie": "sys_reset_n" 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /tests/rootport/rootport.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name root_pci_refclk -period 10 [get_ports pcie_refclk_p] 2 | -------------------------------------------------------------------------------- /tests/serialportal/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = SerialPortalRequest:SerialPortalTest.request EchoIndication:SerialPortalTest.echoIndication SimpleRequest:SerialPortalTest.simpleRequest 3 | H2S_INTERFACES = SerialPortalTest:SerialPortalIndication,EchoRequest,SimpleRequest 4 | 5 | INTERFACES = EchoRequest EchoIndication 6 | 7 | BSVFILES = SerialPortalIfc.bsv $(CONNECTALDIR)/examples/echo/Echo.bsv $(CONNECTALDIR)/examples/simple/Simple.bsv 8 | CPPFILES= serialportal.cpp 9 | 10 | CONNECTALFLAGS += -I $(CONNECTALDIR)/examples/simple 11 | 12 | PINOUT_FILE += rs232.json 13 | PIN_TYPE = SerialPortalPins 14 | PIN_TYPE_INCLUDE = SerialPortalIfc 15 | AUTOTOP = --interface pins:SerialPortalTest.pins 16 | include $(CONNECTALDIR)/Makefile.connectal 17 | -------------------------------------------------------------------------------- /tests/serialportal/rs232.json: -------------------------------------------------------------------------------- 1 | { 2 | "uart_SOUT": { 3 | "uart": "d_out" 4 | }, 5 | "uart_SIN": { 6 | "uart": "d_in" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /tests/simmethodtime/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = SimmRequest:Simm.request 3 | H2S_INTERFACES = Simm:SimmIndication 4 | 5 | BSVFILES = Simm.bsv 6 | CPPFILES= test.cpp 7 | CONNECTALFLAGS += -lpapi 8 | 9 | include $(CONNECTALDIR)/Makefile.connectal 10 | -------------------------------------------------------------------------------- /tests/simple_manual/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = SimpleRequest:Simple.request 3 | H2S_INTERFACES = Simple:SimpleRequest 4 | 5 | BSVFILES = Simple.bsv 6 | #original user program CPPFILES=testsimple.cpp 7 | CPPFILES=simple_manual.c 8 | CONNECTALFLAGS += -D NO_CPP_PORTAL_CODE 9 | 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/spi/ConnectalProjectConfig.bsv: -------------------------------------------------------------------------------- 1 | `define ConnectalVersion 15.11.1 2 | `define NumberOfMasters 1 3 | `define PinType Empty 4 | `define PinTypeInclude Misc 5 | `define NumberOfUserTiles 1 6 | `define SlaveDataBusWidth 32 7 | `define SlaveControlAddrWidth 5 8 | `define BurstLenSize 10 9 | `define project_dir $(DTOP) 10 | `define MainClockPeriod 20 11 | `define DerivedClockPeriod 10.000000 12 | `define BsimHostInterface 13 | `define PhysAddrWidth 40 14 | `define SIMULATION 15 | `define BOARD_bluesim 16 | -------------------------------------------------------------------------------- /tests/spi/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | run: spiTestBench 4 | ./spiTestBench 5 | gtkwave dump.vcd spitest.gtkw 6 | 7 | spiTestBench: $(CONNECTALDIR)/lib/bsv/ConnectalSpi.bsv 8 | mkdir -p obj 9 | bsc --show-schedule -sim -info-dir obj -bdir obj -p +:$(CONNECTALDIR)/lib/bsv:$(CONNECTALDIR)/bsv -g mkSpiTestBench -u $(CONNECTALDIR)/lib/bsv/ConnectalSpi.bsv 10 | bsc --show-schedule -sim -info-dir obj -bdir obj -e mkSpiTestBench -o spiTestBench 11 | 12 | clean: 13 | rm -rf spiTestBench* mkSpiTestBench.* model_mkSpiTestBench.* dump.vcd obj 14 | -------------------------------------------------------------------------------- /tests/spi/spitest.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Wed Apr 1 15:21:05 2015 4 | [*] 5 | [dumpfile] "/scratch/jamey/connectal/tests/spi/dump.vcd" 6 | [dumpfile_mtime] "Wed Apr 1 15:19:07 2015" 7 | [dumpfile_size] 10945 8 | [savefile] "/scratch/jamey/connectal/tests/spi/spitest.gtkw" 9 | [timestart] 0 10 | [size] 1302 874 11 | [pos] -1 -1 12 | *-8.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] main. 14 | [sst_width] 224 15 | [signals_width] 150 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 248 18 | @28 19 | main.top.probeMiso$PROBE 20 | main.top.probeMosi$PROBE 21 | main.top.probeSelN$PROBE 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /tests/spikehw/boot/copybbl.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | #define DRAM_BASE 0 4 | #define DRAM_SIZE 64*1024*1024 5 | #define BOOT_SIZE 0x400 6 | #define BBL_BASE (DRAM_SIZE+BOOT_SIZE) 7 | #define BBL_LEN (64*1024) 8 | 9 | int copybbl() 10 | { 11 | volatile long *src = (long *)BBL_BASE; 12 | volatile long *dst = (long*)(DRAM_BASE+0x100); 13 | int i; 14 | for (i = 0; i < BBL_LEN/sizeof(*dst); i++) 15 | *dst++ = *src++; 16 | } 17 | -------------------------------------------------------------------------------- /tests/spikehw/boot/entry.S: -------------------------------------------------------------------------------- 1 | 2 | 3 | entry: 4 | lui sp,1 5 | jal copybbl 6 | li a0, 0x200 7 | jr a0 8 | stuck: j stuck 9 | copybbl: -------------------------------------------------------------------------------- /tests/spikehw/eth.json: -------------------------------------------------------------------------------- 1 | { 2 | "eth_sfp_rxp_v": { 3 | "sfp1": "rxp" 4 | }, 5 | "eth_sfp_rxn_v": { 6 | "sfp1": "rxn" 7 | }, 8 | "eth_sfp_txp": { 9 | "sfp1": "txp" 10 | }, 11 | "eth_sfp_txn": { 12 | "sfp1": "txn" 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /tests/spikehw/i2c-standard.json: -------------------------------------------------------------------------------- 1 | { 2 | "iic_gpo": { 3 | "pins": "si5324_rst_n" 4 | }, 5 | "iic_sda": { 6 | "iic_main": "sda" 7 | }, 8 | "iic_scl": { 9 | "iic_main": "scl" 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /tests/spikehw/program.tcl: -------------------------------------------------------------------------------- 1 | open_hw 2 | connect_hw_server 3 | open_hw_target 4 | current_hw_device [lindex [get_hw_devices] 0] 5 | set_property PROBES.FILE {/home/jamey/connectal.clean/tests/spikehw/debug.ltx} [lindex [get_hw_devices] 0] 6 | set_property PROGRAM.FILE {/home/jamey/connectal.clean/tests/spikehw/debug.bit} [lindex [get_hw_devices] 0] 7 | program_hw_devices [lindex [get_hw_devices] 0] 8 | quit 9 | -------------------------------------------------------------------------------- /tests/spikehw/rtscts.json: -------------------------------------------------------------------------------- 1 | { 2 | "uart_rts": { 3 | "uart": "rts" 4 | }, 5 | "uart_cts_x": { 6 | "uart": "cts" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /tests/spikehw/spikehw-miniitx100.json: -------------------------------------------------------------------------------- 1 | { 2 | "eth_rx_los_v": { 3 | "sfp1": "rx_los" 4 | }, 5 | "eth_tx_disable": { 6 | "sfp1": "tx_disable" 7 | }, 8 | "iic_sda": { 9 | "sfp1": "mod_def2", 10 | "PIO_DIRECTION": "BIDIR" 11 | }, 12 | "iic_scl": { 13 | "sfp1": "mod_def1", 14 | "PIO_DIRECTION": "BIDIR" 15 | }, 16 | "iic_mux_reset": { 17 | "sfp1": "mod_def0", 18 | "PIO_DIRECTION": "OUTPUT", 19 | "comment": "not connected" 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /tests/spikehw/spikehw-vc707g2.json: -------------------------------------------------------------------------------- 1 | { 2 | "eth_mgt_clk_clk_p_v": { 3 | "pins": "sgmii_clk_p" 4 | }, 5 | "eth_mgt_clk_clk_n_v": { 6 | "pins": "sgmii_clk_n" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /tests/spikehw/spikehw-vc709.json: -------------------------------------------------------------------------------- 1 | { 2 | "eth_mgt_clk_clk_p_v": { 3 | "pins": "si5324_clk_p" 4 | }, 5 | "eth_mgt_clk_clk_n_v": { 6 | "pins": "si5324_clk_n" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /tests/spikehw/spikehw.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name eth_mgt_clk_clk -period 8.000 [get_ports eth_mgt_clk_clk_p_v] 2 | -------------------------------------------------------------------------------- /tests/test_pmod/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | INTERFACES = PmodControllerRequest PmodControllerIndication 3 | 4 | BSVFILES = Controller.bsv Top.bsv 5 | CPPFILES= testpmod.cpp 6 | PIN_TYPE = PmodPins 7 | PIN_TYPE_INCLUDE = Controller 8 | CONNECTALFLAGS = -C $(BOARD)/sources/pinout-$(BOARD).xdc 9 | 10 | PIN_BINDING ?= -b pmod:pmoda 11 | 12 | gentarget:: $(BOARD)/sources/pinout-$(BOARD).xdc 13 | $(BOARD)/sources/pinout-$(BOARD).xdc: pinout.json $(CONNECTALDIR)/boardinfo/$(BOARD).json 14 | mkdir -p $(BOARD)/sources 15 | $(CONNECTALDIR)/scripts/generate-constraints.py $(PIN_BINDING) -o $(BOARD)/sources/pinout-$(BOARD).xdc --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile pinout.json 16 | 17 | include $(CONNECTALDIR)/Makefile.connectal 18 | -------------------------------------------------------------------------------- /tests/test_pmod/pinout.json: -------------------------------------------------------------------------------- 1 | { 2 | "pmod[0]" : { 3 | "PIO_DIRECTION": "OUTPUT", 4 | "pmod" : "J1" 5 | }, 6 | "pmod[1]" : { 7 | "PIO_DIRECTION": "OUTPUT", 8 | "pmod" : "J2" 9 | }, 10 | "pmod[2]" : { 11 | "PIO_DIRECTION": "OUTPUT", 12 | "pmod" : "J3" 13 | }, 14 | "pmod[3]" : { 15 | "PIO_DIRECTION": "OUTPUT", 16 | "pmod" : "J4" 17 | }, 18 | "pmod[4]" : { 19 | "PIO_DIRECTION": "OUTPUT", 20 | "pmod" : "J7" 21 | }, 22 | "pmod[5]" : { 23 | "PIO_DIRECTION": "OUTPUT", 24 | "pmod" : "J8" 25 | }, 26 | "pmod[6]" : { 27 | "PIO_DIRECTION": "OUTPUT", 28 | "pmod" : "J9" 29 | }, 30 | "pmod[7]" : { 31 | "PIO_DIRECTION": "OUTPUT", 32 | "pmod" : "J10" 33 | } 34 | } 35 | 36 | 37 | -------------------------------------------------------------------------------- /tests/test_pmod/testpmod.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include "PmodControllerRequest.h" 9 | #include "PmodControllerIndication.h" 10 | #include "GeneratedTypes.h" 11 | 12 | 13 | class PmodControllerIndication : public PmodControllerIndicationWrapper 14 | { 15 | public: 16 | PmodControllerIndication(int id) : PmodControllerIndicationWrapper(id) {} 17 | virtual void rst ( const uint32_t v ) { 18 | fprintf(stderr, "PmodControllerIndication::rst(%08x)\n", v); 19 | } 20 | }; 21 | 22 | 23 | int main(int argc, const char **argv) 24 | { 25 | PmodControllerIndication *ind = new PmodControllerIndication(IfcNames_ControllerIndication); 26 | PmodControllerRequestProxy *device = new PmodControllerRequestProxy(IfcNames_ControllerRequest); 27 | 28 | for(int i = 0; i < 10; i++) { 29 | device->rst(i); 30 | sleep(1); 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /tests/test_sdio1/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | INTERFACES = SDIORequest SDIOResponse 3 | 4 | BSVFILES = Top.bsv SDIO.bsv 5 | CPPFILES= test_sdio1.cpp 6 | CONNECTALFLAGS += -D PS7EXTENDED -D IMPORT_HOSTIF 7 | 8 | PIN_TYPE = TestSDIO1Pins 9 | PIN_TYPE_INCLUDE = SDIO 10 | PINOUT_FILE = pinout.json 11 | PIN_BINDINGS = pmod:pmodd 12 | 13 | include $(CONNECTALDIR)/Makefile.connectal 14 | -------------------------------------------------------------------------------- /tests/test_spi0/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR ?= ../.. 2 | INTERFACES = SPIRequest SPIResponse 3 | 4 | BSVFILES = Top.bsv SPI.bsv 5 | CPPFILES= test_spi0.cpp 6 | CONNECTALFLAGS += -D PS7EXTENDED -D IMPORT_HOSTIF 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | -------------------------------------------------------------------------------- /tests/testfpmul/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | MMDIR=../../examples/matmul 4 | TESTCPPFILES= testfpmul.cpp 5 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 6 | CONNECTALFLAGS = -D J_VALUE=2 -D K_VALUE=2 -D N_VALUE=2 7 | 8 | include $(MMDIR)/Makefile.mm 9 | include $(MMDIR)/Makefile.mmif 10 | include $(CONNECTALDIR)/Makefile.connectal 11 | -------------------------------------------------------------------------------- /tests/testldstrex/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | 3 | TOOLCHAIN ?= /afs/csail.mit.edu/group/csg/tools/tools_lx86/android-ndk-r9d/sources/cxx-stl/gnu-libstdc++/4.6 4 | CPPFILES= testldstrex.cpp 5 | CONNECTALFLAGS += -I $(TOOLCHAIN)/include -I $(TOOLCHAIN)/libs/armeabi-v7a/include 6 | 7 | include $(CONNECTALDIR)/Makefile.connectal 8 | -------------------------------------------------------------------------------- /tests/testmm16.16.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=16 -D K_VALUE=16 -D N_VALUE=2 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm16.16.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm16.16.4/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=16 -D K_VALUE=16 -D N_VALUE=4 -D DataBusWidth=128 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm16.16.4/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm2.4.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=2 -D K_VALUE=4 -D N_VALUE=2 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm2.4.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm2.4.2/zc706_floorplan.xdc: -------------------------------------------------------------------------------- 1 | create_pblock mmtile_0 2 | resize_pblock mmtile_0 -add {SLICE_X92Y150:SLICE_X96Y250 SLICE_X97Y150:SLICE_X161Y250 DSP48_X4Y62:DSP48_X6Y99 RAMB18_X5Y62:RAMB18_X7Y99 RAMB36_X5Y31:RAMB36_X7Y49} 3 | add_cells_to_pblock mmtile_0 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs 4 | set_property CONTAIN_ROUTING true [get_pblocks mmtile_0] 5 | set_property HD.PARTPIN_RANGE {SLICE_X92Y150:SLICE_X96Y250} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_0/*] 6 | 7 | create_pblock mmtile_1 8 | resize_pblock mmtile_1 -add {SLICE_X92Y52:SLICE_X96Y151 SLICE_X97Y52:SLICE_X159Y151 DSP48_X4Y22:DSP48_X6Y59 RAMB18_X4Y22:RAMB18_X7Y59 RAMB36_X4Y11:RAMB36_X7Y29} 9 | add_cells_to_pblock mmtile_1 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_1]] -clear_locs 10 | set_property CONTAIN_ROUTING true [get_pblocks mmtile_1] 11 | set_property HD.PARTPIN_RANGE {SLICE_X92Y52:SLICE_X96Y151} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_1/*] 12 | -------------------------------------------------------------------------------- /tests/testmm32.16.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES=$(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=32 -D K_VALUE=16 -D N_VALUE=2 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm32.16.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm32.32.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=32 -D K_VALUE=32 -D N_VALUE=2 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm32.32.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm4.2.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=4 -D K_VALUE=2 -D N_VALUE=2 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm4.2.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm4.4.2/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CONNECTALDIR?=../.. 3 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 4 | 5 | MMDIR=$(CONNECTALDIR)/examples/matmul 6 | RBMDIR=$(CONNECTALDIR)/examples/rbm 7 | TESTCPPFILES= $(MMDIR)/testmm.cpp 8 | CONNECTALFLAGS = -D J_VALUE=4 -D K_VALUE=4 -D N_VALUE=2 9 | 10 | include $(MMDIR)/Makefile.mm 11 | include $(MMDIR)/Makefile.mmif 12 | include $(CONNECTALDIR)/Makefile.connectal 13 | -------------------------------------------------------------------------------- /tests/testmm4.4.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm4.4.4/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=4 -D K_VALUE=4 -D N_VALUE=4 -D DataBusWidth=128 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm4.4.4/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm8.8.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=2 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm8.8.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm8.8.4/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(MMDIR)/testmm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=4 -D DataBusWidth=128 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(MMDIR)/Makefile.mmif 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testmm8.8.4/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | ../../examples/matmul/synth-ip.tcl -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | CUDA_PERF_TEST = 1 5 | 6 | MMDIR=$(CONNECTALDIR)/examples/matmul 7 | RBMDIR=$(CONNECTALDIR)/examples/rbm 8 | TESTCPPFILES= $(MMDIR)/testmm.cpp 9 | CONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=2 10 | CONNECTALFLAGS += -D CUDA_PERF_TEST=$(CUDA_PERF_TEST) 11 | 12 | include $(MMDIR)/Makefile.mm 13 | include $(MMDIR)/Makefile.mmif 14 | include $(CONNECTALDIR)/Makefile.connectal 15 | -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/Readme.md: -------------------------------------------------------------------------------- 1 | Running on vangogh: 2 | 3 | 1) download opencv 2.4.9 to /scratch/opencv-cuda/ 4 | 5 | http://downloads.sourceforge.net/project/opencvlibrary/opencv-unix/2.4.9/opencv-2.4.9.zip 6 | 7 | 2) install it using the following commands (I used cmake version 2.8.11.2): 8 | cd opencv-2.9.4 9 | mkdir install 10 | cmake -G 'Unix Makefiles' -D WITH_CUDA=ON -D CMAKE_BUILD_TYPE=DEBUG -D BUILD_SHARED_LIBS=NO -D WITH_CUBLAS=YES -D CMAKE_INSTALL_PREFIX=./install . 11 | make -j 8 12 | make install 13 | 14 | 15 | 3) nm -A *.a | c++filt | grep -w T 16 | 17 | -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/cuda_opencv_example/Makefile: -------------------------------------------------------------------------------- 1 | NVCC = /usr/local/cuda-5.5/bin/nvcc 2 | 3 | default: cuda_opencv_example 4 | 5 | main.o: main.cu 6 | $(NVCC) -I/usr/local/cuda-5.5/targets/x86_64-linux/include/ -I/scratch/opencv-cuda/opencv-2.4.9/install/include -c main.cu 7 | 8 | cuda_opencv_example: main.o main.cpp 9 | g++ -I/usr/local/cuda-5.5/targets/x86_64-linux/include/ -I/scratch/opencv-cuda/opencv-2.4.9/install/include -o cuda_opencv_example main.o main.cpp \ 10 | -L/scratch/opencv-cuda/opencv-2.4.9/install/lib -L/usr/local/cuda-5.5/lib64 \ 11 | -lcuda -lopencv_core -lopencv_gpu -lcudart -lopencv_core 12 | 13 | run: 14 | LD_LIBRARY_PATH=/usr/local/cuda-5.5/lib64 ./cuda_opencv_example 15 | 16 | clean: 17 | rm -f main.o cuda_opencv_example -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/cuda_opencv_example/image.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/connectal/f182656bfe21160b8b263f3261b041d708adafe8/tests/testmm_cuda_perf/cuda_opencv_example/image.jpg -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/run_exe: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -x 3 | LD_LIBRARY_PATH=/usr/local/cuda-5.5/lib64 ./bin/bsim_exe 4 | -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | connectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 5 | connectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 6 | -------------------------------------------------------------------------------- /tests/testmm_cuda_perf/zc706_floorplan.xdc: -------------------------------------------------------------------------------- 1 | create_pblock mmtile_0 2 | resize_pblock mmtile_0 -add {SLICE_X92Y150:SLICE_X96Y250 SLICE_X97Y150:SLICE_X161Y250 DSP48_X4Y62:DSP48_X6Y99 RAMB18_X5Y62:RAMB18_X7Y99 RAMB36_X5Y31:RAMB36_X7Y49} 3 | add_cells_to_pblock mmtile_0 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs 4 | set_property CONTAIN_ROUTING true [get_pblocks mmtile_0] 5 | set_property HD.PARTPIN_RANGE {SLICE_X92Y150:SLICE_X96Y250} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_0/*] 6 | 7 | create_pblock mmtile_1 8 | resize_pblock mmtile_1 -add {SLICE_X92Y52:SLICE_X96Y151 SLICE_X97Y52:SLICE_X159Y151 DSP48_X4Y22:DSP48_X6Y59 RAMB18_X4Y22:RAMB18_X7Y59 RAMB36_X4Y11:RAMB36_X7Y29} 9 | add_cells_to_pblock mmtile_1 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_1]] -clear_locs 10 | set_property CONTAIN_ROUTING true [get_pblocks mmtile_1] 11 | set_property HD.PARTPIN_RANGE {SLICE_X92Y52:SLICE_X96Y151} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_1/*] 12 | -------------------------------------------------------------------------------- /tests/testrbm16.16.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(RBMDIR)/testrbm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=16 -D K_VALUE=16 -D N_VALUE=2 -D DataBusWidth=64 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(RBMDIR)/Makefile.rbm 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | 13 | -------------------------------------------------------------------------------- /tests/testrbm16.16.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | connectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 5 | connectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 6 | -------------------------------------------------------------------------------- /tests/testrbm8.8.2/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | BSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib 3 | 4 | MMDIR=$(CONNECTALDIR)/examples/matmul 5 | RBMDIR=$(CONNECTALDIR)/examples/rbm 6 | TESTCPPFILES= $(RBMDIR)/testrbm.cpp 7 | CONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=2 -D DataBusWidth=64 8 | 9 | include $(MMDIR)/Makefile.mm 10 | include $(RBMDIR)/Makefile.rbm 11 | include $(CONNECTALDIR)/Makefile.connectal 12 | -------------------------------------------------------------------------------- /tests/testrbm8.8.2/synth-ip.tcl: -------------------------------------------------------------------------------- 1 | source "board.tcl" 2 | source "$connectaldir/scripts/connectal-synth-ip.tcl" 3 | 4 | connectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 5 | connectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}] 6 | -------------------------------------------------------------------------------- /tests/yuv/Makefile: -------------------------------------------------------------------------------- 1 | CONNECTALDIR?=../.. 2 | S2H_INTERFACES = YuvRequest:YuvIF.request 3 | H2S_INTERFACES = YuvIF:YuvIndication 4 | 5 | BSVFILES = YuvIF.bsv 6 | CPPFILES= testyuv.cpp 7 | 8 | include $(CONNECTALDIR)/Makefile.connectal 9 | --------------------------------------------------------------------------------