├── .gitignore ├── INSTALL ├── OSS-CVC-ARTISTIC-LICENSING-FAQ.pdf ├── OSS-CVC-MODIFIED-ARTISTIC-LIC.TXT ├── README ├── bin ├── README ├── checkcvc └── checkcvc32 ├── chkcvc.src.dir ├── README ├── checkcvc64 ├── chkcvc.c ├── chkcvc64.c ├── makefile.lnx └── makefile.lnx64 ├── doc ├── Changelog ├── README ├── cvc_help.txt ├── cvc_xpropagation.pdf ├── dbg_help.txt ├── how_to_use_new_toggle_coverage_feature.README ├── oss-cvc-quick-start-061014.pdf └── systemverilog.doc │ ├── how-to-use-some-systemverilog-features.README │ └── svimplemented.v ├── getting_started.README ├── pli_incs ├── acc_user.h ├── cv_acc_user.h ├── cv_veriuser.h ├── cv_vpi_user.h ├── svdpi.h ├── veriuser.h └── vpi_user.h ├── release_directory_structure.README ├── src ├── .CODEGEN.NOTES.swp ├── OSS-CVC-MOD-ARTISTIC-LIC.TXT ├── config.h ├── cvc.c ├── cvc_wrhelp.h ├── cvmacros.h ├── dig_main.c ├── exe_main.c ├── fastlz.c ├── fastlz.h ├── fstapi.c ├── fstapi.h ├── helpgen.inp ├── helpgen2.inp ├── helpgen3.inp ├── hexasm.c ├── igen.h ├── libz.a ├── lz4.c ├── lz4.h ├── makefile.cvc ├── makefile.cvc64 ├── systsks.h ├── v.h ├── v_acc.c ├── v_aslib.c ├── v_asmlnk.c ├── v_bbgen.c ├── v_bbgen2.c ├── v_bbgen3.c ├── v_bbopt.c ├── v_cnv.c ├── v_cvcms.c ├── v_cvcrt.c ├── v_cvr.c ├── v_dbg.c ├── v_dbg2.c ├── v_del.c ├── v_dpi.c ├── v_ex.c ├── v_ex2.c ├── v_ex3.c ├── v_ex4.c ├── v_fx.c ├── v_fx2.c ├── v_fx3.c ├── v_genfx.c ├── v_ms.c ├── v_prp.c ├── v_prp2.c ├── v_regasn.c ├── v_sdf.c ├── v_sim.c ├── v_src.c ├── v_src2.c ├── v_src3.c ├── v_tf.c ├── v_trch.c ├── v_vpi.c ├── v_vpi2.c ├── v_vpi3.c └── v_xprop.c ├── tests_and_examples ├── README ├── examples.acc │ ├── acc_nxtchld.c │ ├── acc_nxtchld.plg │ ├── acc_probe.c │ ├── acc_probe.plg │ ├── acc_prtchg.c │ ├── accxl_drvld.c │ ├── accxldrvtst.plg │ ├── accxldrvtst.v │ ├── clean.sh │ ├── inst_pli.sh │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── nc_fdsp.v │ ├── pchg_fdsp.plg │ ├── pchg_fdsp.v │ ├── probe.v │ ├── readme │ └── rmlic.pl ├── examples.dpi │ ├── README │ ├── chandle.c │ ├── chandle.plg │ ├── chandle.v │ ├── diffname.c │ ├── diffname.plg │ ├── diffname.v │ ├── dpi_tests.sh │ ├── export.c │ ├── export.plg │ ├── export.v │ ├── fourstate.c │ ├── fourstate.plg │ ├── fourstate.v │ ├── fourstate_array.c │ ├── fourstate_array.plg │ ├── fourstate_array.v │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── reals.c │ ├── reals.plg │ ├── reals.v │ ├── rmlic.pl │ ├── selects.c │ ├── selects.plg │ ├── selects.v │ ├── twostate_array.c │ ├── twostate_array.plg │ ├── twostate_array.v │ ├── twostate_functions.c │ ├── twostate_functions.plg │ ├── twostate_functions.v │ ├── twostate_tasks.c │ ├── twostate_tasks.plg │ └── twostate_tasks.v ├── examples.tf │ ├── README │ ├── clean.sh │ ├── inst_pli.sh │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── plimfil.c │ ├── plimfil.plg │ ├── plimfil.v │ ├── plimfil2.c │ ├── plimfil2.plg │ ├── plimfil2.v │ ├── probe.c │ ├── probe.plg │ ├── probe.v │ ├── rmlic.pl │ ├── testmem.dat │ ├── testmem2.dat │ ├── tfclk.c │ ├── tfclk.plg │ └── tfclk.v ├── examples.vpi │ ├── README │ ├── async.c │ ├── async.plg │ ├── async.v │ ├── cacatmd1.v │ ├── clean.sh │ ├── dfpsetd.c │ ├── dfpsetd.plg │ ├── dfpsetd.v │ ├── fdspec01.v │ ├── fff9 │ ├── fff9.exp │ ├── findcaus.c │ ├── findcaus.plg │ ├── inst_pli.sh │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── opt_vacbtst.inp │ ├── opt_vacbtst.plg │ ├── prtbg09.v │ ├── rmlic.pl │ ├── task10.v │ ├── timtst03.v │ ├── vacbtst.c │ ├── vacbtst.inp │ ├── vacbtst.plg │ ├── vchkprt1.c │ ├── vchkprt2.c │ ├── vconta1.c │ ├── vconta1.plg │ ├── vdrvld1.c │ ├── vdrvld1.plg │ ├── vdrvld2.c │ ├── vdrvld2.plg │ ├── vfopen1.c │ ├── vfopen1.plg │ ├── vfopen1.v │ ├── vfopen2.c │ ├── vfopen2.plg │ ├── vfopen2.v │ ├── vhelbad.c │ ├── vhelbad.plg │ ├── vhelbad.v │ ├── vhello1.c │ ├── vhello1.plg │ ├── vhello1.v │ ├── vhello2.c │ ├── vhello2.plg │ ├── vhello2.v │ ├── vpifout.fil │ ├── vpifout.xfl │ ├── vpiret.m01 │ ├── vpitout.fil │ ├── vpitout.xfl │ ├── vprtchg.c │ ├── vprtchg.plg │ ├── vprtchg2.c │ ├── vprtchg2.plg │ ├── vprtchg3.c │ ├── vprtchg3.plg │ ├── vprtdel2.c │ ├── vprtdel2.plg │ ├── vprtdels.c │ ├── vprtdels.plg │ ├── vsetdels.c │ ├── vsetdels.plg │ ├── vsetval1.c │ ├── vsetval1.plg │ ├── vsetval1.v │ ├── vsetval2.c │ ├── vsetval2.plg │ ├── vsetval2.v │ ├── vtimcbs.c │ └── vtimcbs.plg ├── examples.xprop │ ├── README │ ├── cvc.xprop │ ├── cvc.xprop.excluded │ ├── rmlic.pl │ ├── x.optconfig │ ├── xcase.plg │ ├── xcase.v │ ├── xconfig.plg │ ├── xconfig.v │ ├── xedges.plg │ ├── xedges.v │ ├── xexcluded.plg │ ├── xexcluded.v │ ├── xif.plg │ ├── xif.v │ ├── xnested.plg │ ├── xnested.v │ ├── xprop2.plg │ ├── xprop2.v │ ├── xprop_eval.plg │ ├── xprop_eval.v │ ├── xprop_test.sh │ ├── xtrace.plg │ └── xtrace.v ├── install.test │ ├── 2901alg.plg │ ├── 2901block.plg │ ├── 2901sim.v │ ├── JK_Q.v │ ├── JK_QBAR.v │ ├── README │ ├── alg.v │ ├── arms.plg │ ├── arms_sim.v │ ├── armscnt.v │ ├── aspike1.plg │ ├── aspike1.v │ ├── aspike1a.plg │ ├── aspike1b.plg │ ├── aspike1c.plg │ ├── aspike1d.plg │ ├── block.v │ ├── c880.plg │ ├── c880.v │ ├── cpurtl2.plg │ ├── cpurtl2.v │ ├── defsplt1.plg │ ├── defsplt1.v │ ├── dffn.plg │ ├── dffn.v │ ├── dfpsetd.plg │ ├── dfpsetd.v │ ├── dfpsetd.vc │ ├── dfpsetd1.sdf │ ├── dfpsetd2.sdf │ ├── force01.inp │ ├── force01.plg │ ├── force01.v │ ├── gatenots.plg │ ├── gatenots.v │ ├── gcd.plg │ ├── gcd.v │ ├── gcdsim.v │ ├── gn.mem │ ├── inst_test.sh │ ├── inst_test_interp.sh │ ├── instid.plg │ ├── instid.plg64 │ ├── instid.v │ ├── instpnd3.plg │ ├── instpnd3.v │ ├── jkff.v │ ├── mem.dat │ ├── minisim.plg │ ├── minisim.v │ ├── mipdnot1.plg │ ├── mipdnot1.sdf │ ├── mipdnot1.v │ ├── mipdnot1.vc │ ├── patt.mem │ ├── prog2.dat │ ├── rmlic.pl │ ├── sdfia04.plg │ ├── sdfia04.sdf │ ├── sdfia04.v │ ├── sdfia04.vc │ ├── smrd04.plg │ ├── smrd04.v │ ├── smrd04.vc │ ├── tasks.inc │ ├── testmem.dat │ ├── udpjkff.plg │ ├── udpjkff.v │ ├── uu │ ├── xplipnd.plg │ ├── xplipnd.plg64 │ ├── xplipnd.v │ ├── xx2bdel.plg │ ├── xx2bdel.v │ ├── xx2bpth.plg │ ├── xx2bpth.v │ ├── xx2bpth2.plg │ ├── xx2bpth2.v │ └── xxdel.tst ├── open_cores │ ├── README │ ├── ac97 │ │ ├── README │ │ ├── ac97_defines.v │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── ac97_codec_sin.v │ │ │ │ ├── ac97_codec_sout.v │ │ │ │ ├── ac97_codec_top.v │ │ │ │ ├── test_bench_top.v │ │ │ │ ├── tests.v │ │ │ │ ├── wb_mast_model.v │ │ │ │ └── wb_model_defines.v │ │ ├── cvc.log │ │ ├── doc │ │ │ ├── README.txt │ │ │ ├── STATUS.txt │ │ │ └── ac97_doc.pdf │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── ac97_cra.v │ │ │ │ ├── ac97_defines.v │ │ │ │ ├── ac97_dma_if.v │ │ │ │ ├── ac97_dma_req.v │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ ├── ac97_int.v │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ ├── ac97_prc.v │ │ │ │ ├── ac97_rf.v │ │ │ │ ├── ac97_rst.v │ │ │ │ ├── ac97_sin.v │ │ │ │ ├── ac97_soc.v │ │ │ │ ├── ac97_sout.v │ │ │ │ ├── ac97_top.v │ │ │ │ └── ac97_wb_if.v │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ │ └── run │ │ │ │ └── Makefile │ │ ├── syn │ │ │ └── bin │ │ │ │ ├── comp.dc │ │ │ │ ├── design_spec.dc │ │ │ │ ├── lib_spec.dc │ │ │ │ └── read.dc │ │ ├── tests.v │ │ └── wb_model_defines.v │ ├── ata │ │ ├── README │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── ata_device.v │ │ │ │ ├── test_bench_top.v │ │ │ │ ├── tests.v │ │ │ │ ├── wb_mast_model.v │ │ │ │ ├── wb_model_defines.v │ │ │ │ └── wb_slv_model.v │ │ ├── cvc.log │ │ ├── doc │ │ │ ├── preliminary_ata_core.pdf │ │ │ └── src │ │ │ │ └── ata_core.doc │ │ ├── rtl │ │ │ ├── verilog │ │ │ │ ├── ocidec-1 │ │ │ │ │ ├── atahost_controller.v │ │ │ │ │ ├── atahost_pio_tctrl.v │ │ │ │ │ ├── atahost_top.v │ │ │ │ │ ├── atahost_wb_slave.v │ │ │ │ │ ├── revision_history.txt │ │ │ │ │ ├── ro_cnt.v │ │ │ │ │ ├── timescale.v │ │ │ │ │ └── ud_cnt.v │ │ │ │ └── ocidec-2 │ │ │ │ │ ├── atahost_controller.v │ │ │ │ │ ├── atahost_pio_actrl.v │ │ │ │ │ ├── atahost_pio_tctrl.v │ │ │ │ │ ├── atahost_top.v │ │ │ │ │ ├── atahost_wb_slave.v │ │ │ │ │ ├── revision_history.txt │ │ │ │ │ ├── ro_cnt.v │ │ │ │ │ ├── timescale.v │ │ │ │ │ └── ud_cnt.v │ │ │ └── vhdl │ │ │ │ ├── ocidec1 │ │ │ │ ├── atahost_controller.vhd │ │ │ │ ├── atahost_pio_tctrl.vhd │ │ │ │ ├── atahost_top.vhd │ │ │ │ ├── atahost_wb_slave.vhd │ │ │ │ ├── revision_history.txt │ │ │ │ ├── ro_cnt.vhd │ │ │ │ └── ud_cnt.vhd │ │ │ │ ├── ocidec2 │ │ │ │ ├── atahost_controller.vhd │ │ │ │ ├── atahost_pio_actrl.vhd │ │ │ │ ├── atahost_pio_tctrl.vhd │ │ │ │ ├── atahost_top.vhd │ │ │ │ ├── atahost_wb_slave.vhd │ │ │ │ ├── revision_history.txt │ │ │ │ ├── ro_cnt.vhd │ │ │ │ └── ud_cnt.vhd │ │ │ │ └── ocidec3 │ │ │ │ ├── atahost_controller.vhd │ │ │ │ ├── atahost_dma_actrl.vhd │ │ │ │ ├── atahost_dma_tctrl.vhd │ │ │ │ ├── atahost_fifo.vhd │ │ │ │ ├── atahost_lfsr.vhd │ │ │ │ ├── atahost_pio_actrl.vhd │ │ │ │ ├── atahost_pio_controller.vhd │ │ │ │ ├── atahost_pio_tctrl.vhd │ │ │ │ ├── atahost_reg_buf.vhd │ │ │ │ ├── atahost_top.vhd │ │ │ │ ├── atahost_wb_slave.vhd │ │ │ │ ├── revision_history.txt │ │ │ │ ├── ro_cnt.vhd │ │ │ │ └── ud_cnt.vhd │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ └── bin │ │ │ │ └── Makefile │ │ ├── syn │ │ │ └── bin │ │ │ │ ├── comp.dc │ │ │ │ ├── design_spec.dc │ │ │ │ ├── lib_spec.dc │ │ │ │ └── read.dc │ │ ├── tests.v │ │ ├── timescale.v │ │ └── wb_model_defines.v │ ├── can │ │ ├── README │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── can_testbench.v │ │ │ │ ├── can_testbench_defines.v │ │ │ │ └── timescale.v │ │ ├── can_defines.v │ │ ├── can_testbench_defines.v │ │ ├── cvc.log │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── README.txt │ │ │ │ ├── can_acf.v │ │ │ │ ├── can_bsp.v │ │ │ │ ├── can_btl.v │ │ │ │ ├── can_crc.v │ │ │ │ ├── can_defines.v │ │ │ │ ├── can_fifo.v │ │ │ │ ├── can_ibo.v │ │ │ │ ├── can_register.v │ │ │ │ ├── can_register_asyn.v │ │ │ │ ├── can_register_asyn_syn.v │ │ │ │ ├── can_register_syn.v │ │ │ │ ├── can_registers.v │ │ │ │ └── can_top.v │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ ├── INCA_libs │ │ │ │ │ └── worklib │ │ │ │ │ │ └── dir_keeper │ │ │ │ ├── cds.lib │ │ │ │ ├── hdl.var │ │ │ │ ├── memory_file_list │ │ │ │ ├── rtl_file_list │ │ │ │ └── sim_file_list │ │ │ │ ├── log │ │ │ │ └── dir_keeper │ │ │ │ ├── out │ │ │ │ └── dir_keeper │ │ │ │ └── run │ │ │ │ ├── clean │ │ │ │ ├── run_sim.scr │ │ │ │ └── wave.do │ │ ├── syn │ │ │ ├── libero │ │ │ │ └── pinedit.gcf │ │ │ └── synplicity │ │ │ │ ├── can.prj │ │ │ │ └── rev_1 │ │ │ │ └── dir_keeper │ │ └── timescale.v │ ├── cvc-open-core-sim-times.pdf │ ├── ethernet │ │ ├── README │ │ ├── bench │ │ │ └── tb_ethernet.v │ │ ├── cvc.log │ │ ├── eth_defines.v │ │ ├── eth_host.log │ │ ├── eth_memory.log │ │ ├── eth_phy_defines.v │ │ ├── ethernet_rx.log │ │ ├── ethernet_tx.log │ │ ├── log │ │ │ ├── eth_tb.log │ │ │ ├── eth_tb_host.log │ │ │ ├── eth_tb_memory.log │ │ │ ├── eth_tb_phy.log │ │ │ ├── eth_tb_wb_m_mon.log │ │ │ └── eth_tb_wb_s_mon.log │ │ ├── rtl │ │ │ ├── eth_clockgen.v │ │ │ ├── eth_cop.v │ │ │ ├── eth_crc.v │ │ │ ├── eth_fifo.v │ │ │ ├── eth_host.log │ │ │ ├── eth_host.v │ │ │ ├── eth_maccontrol.v │ │ │ ├── eth_macstatus.v │ │ │ ├── eth_memory.log │ │ │ ├── eth_memory.v │ │ │ ├── eth_miim.v │ │ │ ├── eth_outputcontrol.v │ │ │ ├── eth_phy.v │ │ │ ├── eth_random.v │ │ │ ├── eth_receivecontrol.v │ │ │ ├── eth_register.v │ │ │ ├── eth_registers.v │ │ │ ├── eth_rxaddrcheck.v │ │ │ ├── eth_rxcounters.v │ │ │ ├── eth_rxethmac.v │ │ │ ├── eth_rxstatem.v │ │ │ ├── eth_shiftreg.v │ │ │ ├── eth_spram_256x32.v │ │ │ ├── eth_top.v │ │ │ ├── eth_transmitcontrol.v │ │ │ ├── eth_txcounters.v │ │ │ ├── eth_txethmac.v │ │ │ ├── eth_txstatem.v │ │ │ ├── eth_wishbone.v │ │ │ ├── ethernet_rx.log │ │ │ ├── ethernet_tx.log │ │ │ ├── ram16x1d.v │ │ │ ├── tb_cop.v │ │ │ ├── tb_ethernet_with_cop.v │ │ │ ├── wb_bus_mon.v │ │ │ ├── wb_master32.v │ │ │ ├── wb_master_behavioral.v │ │ │ ├── wb_slave_behavioral.v │ │ │ └── xilinx_dist_ram_16x32.v │ │ ├── run.flist │ │ ├── tb_eth_defines.v │ │ ├── tb_eth_top.vh │ │ ├── timescale.v │ │ └── wb_model_defines.v │ ├── generic_fifos │ │ ├── README │ │ ├── bench │ │ │ └── verilog │ │ │ │ └── test_bench_top.v │ │ ├── cvc.log │ │ ├── doc │ │ │ └── README.txt │ │ ├── generic_dpram.v │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── generic_fifo_dc.v │ │ │ │ ├── generic_fifo_dc_gray.v │ │ │ │ ├── generic_fifo_lfsr.v │ │ │ │ ├── generic_fifo_sc_a.v │ │ │ │ ├── generic_fifo_sc_b.v │ │ │ │ ├── lfsr.v │ │ │ │ └── timescale.v │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ │ └── run │ │ │ │ └── waves │ │ │ │ └── waves.do │ │ └── timescale.v │ ├── m68k │ │ ├── README │ │ ├── README_VERILATOR.txt │ │ ├── bench │ │ │ ├── bench.cpp │ │ │ ├── bench.v │ │ │ ├── k68_soc_test.v │ │ │ ├── k68_testram.v │ │ │ ├── k68_testrom.v │ │ │ └── test.s │ │ ├── cvc.log │ │ ├── input.vc │ │ ├── k68_defines.v │ │ ├── rtl │ │ │ ├── k68_adder.v │ │ │ ├── k68_appl.v │ │ │ ├── k68_arb.v │ │ │ ├── k68_asx.v │ │ │ ├── k68_b2d.v │ │ │ ├── k68_buni.v │ │ │ ├── k68_calc.v │ │ │ ├── k68_ccc.v │ │ │ ├── k68_clkgen.v │ │ │ ├── k68_cpu.v │ │ │ ├── k68_d2b.v │ │ │ ├── k68_decode.v │ │ │ ├── k68_defines.v │ │ │ ├── k68_dpmem.v │ │ │ ├── k68_execute.v │ │ │ ├── k68_fetch.v │ │ │ ├── k68_load.v │ │ │ ├── k68_lsx.v │ │ │ ├── k68_par_mul.v │ │ │ ├── k68_prims.v │ │ │ ├── k68_regbank.v │ │ │ ├── k68_rox.v │ │ │ ├── k68_roxx.v │ │ │ ├── k68_sasc.v │ │ │ ├── k68_soc.v │ │ │ ├── sasc_brg.v │ │ │ ├── sasc_fifo4.v │ │ │ ├── sasc_top.v │ │ │ └── timescale.v │ │ ├── run.flist │ │ ├── sim │ │ │ ├── DEBUG_oprofile │ │ │ └── Makefile │ │ ├── test.rom.vh │ │ └── timescale.v │ ├── sha1 │ │ ├── README │ │ ├── cvc.log │ │ ├── dffhr.v │ │ ├── run.flist │ │ ├── sha1_exec.v │ │ ├── sha1_readme_v01.txt │ │ ├── sha1_round.v │ │ └── sha1_testbench.v │ ├── usb11 │ │ ├── README │ │ ├── cvc.log │ │ ├── generic_fifos │ │ │ ├── common │ │ │ │ └── generic_memories │ │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ └── generic_dpram.v │ │ │ └── generic_fifos │ │ │ │ ├── doc │ │ │ │ └── readme.txt │ │ │ │ └── rtl │ │ │ │ └── verilog │ │ │ │ ├── generic_fifo_dc.v │ │ │ │ ├── generic_fifo_dc_gray.v │ │ │ │ ├── generic_fifo_lfsr.v │ │ │ │ ├── generic_fifo_sc_a.v │ │ │ │ ├── generic_fifo_sc_b.v │ │ │ │ ├── lfsr.v │ │ │ │ └── timescale.v │ │ ├── run.flist │ │ ├── tests.v │ │ ├── tests_lib.v │ │ ├── timescale.v │ │ ├── usb1_defines.v │ │ ├── usb1_funct │ │ │ ├── bench │ │ │ │ └── verilog │ │ │ │ │ ├── test_bench_top.v │ │ │ │ │ ├── tests.v │ │ │ │ │ ├── tests_lib.v │ │ │ │ │ └── timescale.v │ │ │ ├── doc │ │ │ │ ├── README.txt │ │ │ │ └── success_story.txt │ │ │ ├── rtl │ │ │ │ └── verilog │ │ │ │ │ ├── timescale.v │ │ │ │ │ ├── usb1_core.v │ │ │ │ │ ├── usb1_crc16.v │ │ │ │ │ ├── usb1_crc5.v │ │ │ │ │ ├── usb1_ctrl.v │ │ │ │ │ ├── usb1_defines.v │ │ │ │ │ ├── usb1_fifo2.v │ │ │ │ │ ├── usb1_idma.v │ │ │ │ │ ├── usb1_pa.v │ │ │ │ │ ├── usb1_pd.v │ │ │ │ │ ├── usb1_pe.v │ │ │ │ │ ├── usb1_pl.v │ │ │ │ │ ├── usb1_rom1.v │ │ │ │ │ └── usb1_utmi_if.v │ │ │ └── sim │ │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ │ └── run │ │ │ │ └── Makefile │ │ └── usb_phy │ │ │ ├── doc │ │ │ └── readme.txt │ │ │ └── rtl │ │ │ └── verilog │ │ │ ├── timescale.v │ │ │ ├── usb_phy.v │ │ │ ├── usb_rx_phy.v │ │ │ └── usb_tx_phy.v │ └── wb_dma │ │ ├── README │ │ ├── bench │ │ └── verilog │ │ │ ├── test_bench_top.v │ │ │ ├── tests.v │ │ │ ├── wb_mast_model.v │ │ │ ├── wb_model_defines.v │ │ │ └── wb_slv_model.v │ │ ├── cvc.log │ │ ├── doc │ │ ├── README.txt │ │ ├── STATUS.txt │ │ └── dma_doc.pdf │ │ ├── rtl │ │ └── verilog │ │ │ ├── wb_dma_ch_arb.v │ │ │ ├── wb_dma_ch_pri_enc.v │ │ │ ├── wb_dma_ch_rf.v │ │ │ ├── wb_dma_ch_sel.v │ │ │ ├── wb_dma_de.v │ │ │ ├── wb_dma_defines.v │ │ │ ├── wb_dma_inc30r.v │ │ │ ├── wb_dma_pri_enc_sub.v │ │ │ ├── wb_dma_rf.v │ │ │ ├── wb_dma_top.v │ │ │ ├── wb_dma_wb_if.v │ │ │ ├── wb_dma_wb_mast.v │ │ │ └── wb_dma_wb_slv.v │ │ ├── run.flist │ │ ├── sim │ │ └── rtl_sim │ │ │ └── bin │ │ │ └── Makefile │ │ ├── syn │ │ └── bin │ │ │ ├── comp.dc │ │ │ ├── design_spec.dc │ │ │ ├── lib_spec.dc │ │ │ └── read.dc │ │ ├── tests.v │ │ ├── wb_dma_defines.v │ │ └── wb_model_defines.v └── verilog_da_bnchmrks │ ├── README.DA-SOLUTIONS.ORIGINAL.1999 │ ├── das_cpu │ ├── README.CVC-FEATURES │ ├── README.DA-SOLUTIONS.ORIGINAL.1999 │ ├── cpu_mixed.v │ ├── cpu_rtl.v │ ├── expected.run_all_toggle │ ├── finish.inp │ ├── gen_untoggled_report_from_tgldat.vc │ ├── prog │ ├── run_all_toggle.vc │ ├── run_fst_dumpvars.vc │ ├── run_optcfg_bits_exclude.vc │ ├── run_optcfg_tree.vc │ ├── run_tgl_on_off.vc │ ├── run_xprop.vc │ ├── tasks │ ├── tgl_some.cfg │ └── tgl_tree.cfg │ ├── das_lfsr │ ├── README │ ├── lfsr.sdf │ ├── lfsr1000.v │ ├── lfsr1000.vc │ ├── lfsr1000_no_sdf.vc │ ├── lfsr1000_nosdf.vc │ ├── lfsr16000.v │ ├── lfsr16000.vc │ ├── lfsr2000.v │ ├── lfsr2000.vc │ ├── lfsr32000.v │ ├── lfsr32000.vc │ ├── lfsr4000.v │ ├── lfsr4000.vc │ ├── lfsr500.v │ ├── lfsr500.vc │ ├── lfsr500_nosdf.vc │ ├── lfsr500_udp.v │ ├── lfsr8000.v │ └── lfsr8000.vc │ ├── das_mult │ ├── README │ ├── mult_gate.v │ ├── mult_gate.vc │ ├── ref_in │ └── ref_out │ ├── libs │ ├── lca100kgate │ │ ├── AN2.v │ │ ├── AN3.v │ │ ├── AN4.v │ │ ├── AN5.v │ │ ├── BUF8A.v │ │ ├── EN.v │ │ ├── FA1A.v │ │ ├── FD2.v │ │ ├── FD2v.orig │ │ ├── OR2.v │ │ ├── OR3.v │ │ ├── OR4.v │ │ ├── OR5.v │ │ ├── ZERO.v │ │ └── fd2.fix │ ├── lca100kunit │ │ ├── FA1a.v.old │ │ ├── FD2.v.old │ │ ├── an2.v │ │ ├── an3.v │ │ ├── an4.v │ │ ├── an5.v │ │ ├── buf8a.v │ │ ├── en.v │ │ ├── fa1a.v │ │ ├── fd2.v │ │ ├── or2.v │ │ ├── or3.v │ │ ├── or4.v │ │ └── or5.v │ └── tgc1000gate │ │ ├── AN210.v │ │ ├── BF001.v │ │ ├── BF002.v │ │ ├── BF003.v │ │ ├── BF003.v.gate │ │ ├── BF006.v │ │ ├── BF051.v │ │ ├── BF052.v │ │ ├── BF053.v │ │ ├── BF056.v │ │ ├── EN210.v │ │ ├── EN2B0.v │ │ ├── EX210.v │ │ ├── EX2B0.v │ │ ├── IV110.v │ │ ├── NA210.v │ │ ├── NA310.v │ │ ├── NA311.v │ │ ├── NA410.v │ │ ├── NO210.v │ │ ├── OR210.v │ │ ├── OR310.v │ │ ├── TO010.v │ │ └── aoiudp.v │ └── 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