├── .gitignore ├── INSTALL ├── OSS-CVC-ARTISTIC-LICENSING-FAQ.pdf ├── OSS-CVC-MODIFIED-ARTISTIC-LIC.TXT ├── README ├── bin ├── README ├── checkcvc └── checkcvc32 ├── chkcvc.src.dir ├── README ├── checkcvc64 ├── chkcvc.c ├── chkcvc64.c ├── makefile.lnx └── makefile.lnx64 ├── doc ├── Changelog ├── README ├── cvc_help.txt ├── cvc_xpropagation.pdf ├── dbg_help.txt ├── how_to_use_new_toggle_coverage_feature.README ├── oss-cvc-quick-start-061014.pdf └── systemverilog.doc │ ├── how-to-use-some-systemverilog-features.README │ └── svimplemented.v ├── getting_started.README ├── pli_incs ├── acc_user.h ├── cv_acc_user.h ├── cv_veriuser.h ├── cv_vpi_user.h ├── svdpi.h ├── veriuser.h └── vpi_user.h ├── release_directory_structure.README ├── src ├── .CODEGEN.NOTES.swp ├── OSS-CVC-MOD-ARTISTIC-LIC.TXT ├── config.h ├── cvc.c ├── cvc_wrhelp.h ├── cvmacros.h ├── dig_main.c ├── exe_main.c ├── fastlz.c ├── fastlz.h ├── fstapi.c ├── fstapi.h ├── helpgen.inp ├── helpgen2.inp ├── helpgen3.inp ├── hexasm.c ├── igen.h ├── libz.a ├── lz4.c ├── lz4.h ├── makefile.cvc ├── makefile.cvc64 ├── systsks.h ├── v.h ├── v_acc.c ├── v_aslib.c ├── v_asmlnk.c ├── v_bbgen.c ├── v_bbgen2.c ├── v_bbgen3.c ├── v_bbopt.c ├── v_cnv.c ├── v_cvcms.c ├── v_cvcrt.c ├── v_cvr.c ├── v_dbg.c ├── v_dbg2.c ├── v_del.c ├── v_dpi.c ├── v_ex.c ├── v_ex2.c ├── v_ex3.c ├── v_ex4.c ├── v_fx.c ├── v_fx2.c ├── v_fx3.c ├── v_genfx.c ├── v_ms.c ├── v_prp.c ├── v_prp2.c ├── v_regasn.c ├── v_sdf.c ├── v_sim.c ├── v_src.c ├── v_src2.c ├── v_src3.c ├── v_tf.c ├── v_trch.c ├── v_vpi.c ├── v_vpi2.c ├── v_vpi3.c └── v_xprop.c ├── tests_and_examples ├── README ├── examples.acc │ ├── acc_nxtchld.c │ ├── acc_nxtchld.plg │ ├── acc_probe.c │ ├── acc_probe.plg │ ├── acc_prtchg.c │ ├── accxl_drvld.c │ ├── accxldrvtst.plg │ ├── accxldrvtst.v │ ├── clean.sh │ ├── inst_pli.sh │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── nc_fdsp.v │ ├── pchg_fdsp.plg │ ├── pchg_fdsp.v │ ├── probe.v │ ├── readme │ └── rmlic.pl ├── examples.dpi │ ├── README │ ├── chandle.c │ ├── chandle.plg │ ├── chandle.v │ ├── diffname.c │ ├── diffname.plg │ ├── diffname.v │ ├── dpi_tests.sh │ ├── export.c │ ├── export.plg │ ├── export.v │ ├── fourstate.c │ ├── fourstate.plg │ ├── fourstate.v │ ├── fourstate_array.c │ ├── fourstate_array.plg │ ├── fourstate_array.v │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── reals.c │ ├── reals.plg │ ├── reals.v │ ├── rmlic.pl │ ├── selects.c │ ├── selects.plg │ ├── selects.v │ ├── twostate_array.c │ ├── twostate_array.plg │ ├── twostate_array.v │ ├── twostate_functions.c │ ├── twostate_functions.plg │ ├── twostate_functions.v │ ├── twostate_tasks.c │ ├── twostate_tasks.plg │ └── twostate_tasks.v ├── examples.tf │ ├── README │ ├── clean.sh │ ├── inst_pli.sh │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── plimfil.c │ ├── plimfil.plg │ ├── plimfil.v │ ├── plimfil2.c │ ├── plimfil2.plg │ ├── plimfil2.v │ ├── probe.c │ ├── probe.plg │ ├── probe.v │ ├── rmlic.pl │ ├── testmem.dat │ ├── testmem2.dat │ ├── tfclk.c │ ├── tfclk.plg │ └── tfclk.v ├── examples.vpi │ ├── README │ ├── async.c │ ├── async.plg │ ├── async.v │ ├── cacatmd1.v │ ├── clean.sh │ ├── dfpsetd.c │ ├── dfpsetd.plg │ ├── dfpsetd.v │ ├── fdspec01.v │ ├── fff9 │ ├── fff9.exp │ ├── findcaus.c │ ├── findcaus.plg │ ├── inst_pli.sh │ ├── makefile.lnx32 │ ├── makefile.lnx64 │ ├── opt_vacbtst.inp │ ├── opt_vacbtst.plg │ ├── prtbg09.v │ ├── rmlic.pl │ ├── task10.v │ ├── timtst03.v │ ├── vacbtst.c │ ├── vacbtst.inp │ ├── vacbtst.plg │ ├── vchkprt1.c │ ├── vchkprt2.c │ ├── vconta1.c │ ├── vconta1.plg │ ├── vdrvld1.c │ ├── vdrvld1.plg │ ├── vdrvld2.c │ ├── vdrvld2.plg │ ├── vfopen1.c │ ├── vfopen1.plg │ ├── vfopen1.v │ ├── vfopen2.c │ ├── vfopen2.plg │ ├── vfopen2.v │ ├── vhelbad.c │ ├── vhelbad.plg │ ├── vhelbad.v │ ├── vhello1.c │ ├── vhello1.plg │ ├── vhello1.v │ ├── vhello2.c │ ├── vhello2.plg │ ├── vhello2.v │ ├── vpifout.fil │ ├── vpifout.xfl │ ├── vpiret.m01 │ ├── vpitout.fil │ ├── vpitout.xfl │ ├── vprtchg.c │ ├── vprtchg.plg │ ├── vprtchg2.c │ ├── vprtchg2.plg │ ├── vprtchg3.c │ ├── vprtchg3.plg │ ├── vprtdel2.c │ ├── vprtdel2.plg │ ├── vprtdels.c │ ├── vprtdels.plg │ ├── vsetdels.c │ ├── vsetdels.plg │ ├── vsetval1.c │ ├── vsetval1.plg │ ├── vsetval1.v │ ├── vsetval2.c │ ├── vsetval2.plg │ ├── vsetval2.v │ ├── vtimcbs.c │ └── vtimcbs.plg ├── examples.xprop │ ├── README │ ├── cvc.xprop │ ├── cvc.xprop.excluded │ ├── rmlic.pl │ ├── x.optconfig │ ├── xcase.plg │ ├── xcase.v │ ├── xconfig.plg │ ├── xconfig.v │ ├── xedges.plg │ ├── xedges.v │ ├── xexcluded.plg │ ├── xexcluded.v │ ├── xif.plg │ ├── xif.v │ ├── xnested.plg │ ├── xnested.v │ ├── xprop2.plg │ ├── xprop2.v │ ├── xprop_eval.plg │ ├── xprop_eval.v │ ├── xprop_test.sh │ ├── xtrace.plg │ └── xtrace.v ├── install.test │ ├── 2901alg.plg │ ├── 2901block.plg │ ├── 2901sim.v │ ├── JK_Q.v │ ├── JK_QBAR.v │ ├── README │ ├── alg.v │ ├── arms.plg │ ├── arms_sim.v │ ├── armscnt.v │ ├── aspike1.plg │ ├── aspike1.v │ ├── aspike1a.plg │ ├── aspike1b.plg │ ├── aspike1c.plg │ ├── aspike1d.plg │ ├── block.v │ ├── c880.plg │ ├── c880.v │ ├── cpurtl2.plg │ ├── cpurtl2.v │ ├── defsplt1.plg │ ├── defsplt1.v │ ├── dffn.plg │ ├── dffn.v │ ├── dfpsetd.plg │ ├── dfpsetd.v │ ├── dfpsetd.vc │ ├── dfpsetd1.sdf │ ├── dfpsetd2.sdf │ ├── force01.inp │ ├── force01.plg │ ├── force01.v │ ├── gatenots.plg │ ├── gatenots.v │ ├── gcd.plg │ ├── gcd.v │ ├── gcdsim.v │ ├── gn.mem │ ├── inst_test.sh │ ├── inst_test_interp.sh │ ├── instid.plg │ ├── instid.plg64 │ ├── instid.v │ ├── instpnd3.plg │ ├── instpnd3.v │ ├── jkff.v │ ├── mem.dat │ ├── minisim.plg │ ├── minisim.v │ ├── mipdnot1.plg │ ├── mipdnot1.sdf │ ├── mipdnot1.v │ ├── mipdnot1.vc │ ├── patt.mem │ ├── prog2.dat │ ├── rmlic.pl │ ├── sdfia04.plg │ ├── sdfia04.sdf │ ├── sdfia04.v │ ├── sdfia04.vc │ ├── smrd04.plg │ ├── smrd04.v │ ├── smrd04.vc │ ├── tasks.inc │ ├── testmem.dat │ ├── udpjkff.plg │ ├── udpjkff.v │ ├── uu │ ├── xplipnd.plg │ ├── xplipnd.plg64 │ ├── xplipnd.v │ ├── xx2bdel.plg │ ├── xx2bdel.v │ ├── xx2bpth.plg │ ├── xx2bpth.v │ ├── xx2bpth2.plg │ ├── xx2bpth2.v │ └── xxdel.tst ├── open_cores │ ├── README │ ├── ac97 │ │ ├── README │ │ ├── ac97_defines.v │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── ac97_codec_sin.v │ │ │ │ ├── ac97_codec_sout.v │ │ │ │ ├── ac97_codec_top.v │ │ │ │ ├── test_bench_top.v │ │ │ │ ├── tests.v │ │ │ │ ├── wb_mast_model.v │ │ │ │ └── wb_model_defines.v │ │ ├── cvc.log │ │ ├── doc │ │ │ ├── README.txt │ │ │ ├── STATUS.txt │ │ │ └── ac97_doc.pdf │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── ac97_cra.v │ │ │ │ ├── ac97_defines.v │ │ │ │ ├── ac97_dma_if.v │ │ │ │ ├── ac97_dma_req.v │ │ │ │ ├── ac97_fifo_ctrl.v │ │ │ │ ├── ac97_in_fifo.v │ │ │ │ ├── ac97_int.v │ │ │ │ ├── ac97_out_fifo.v │ │ │ │ ├── ac97_prc.v │ │ │ │ ├── ac97_rf.v │ │ │ │ ├── ac97_rst.v │ │ │ │ ├── ac97_sin.v │ │ │ │ ├── ac97_soc.v │ │ │ │ ├── ac97_sout.v │ │ │ │ ├── ac97_top.v │ │ │ │ └── ac97_wb_if.v │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ │ └── run │ │ │ │ └── Makefile │ │ ├── syn │ │ │ └── bin │ │ │ │ ├── comp.dc │ │ │ │ ├── design_spec.dc │ │ │ │ ├── lib_spec.dc │ │ │ │ └── read.dc │ │ ├── tests.v │ │ └── wb_model_defines.v │ ├── ata │ │ ├── README │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── ata_device.v │ │ │ │ ├── test_bench_top.v │ │ │ │ ├── tests.v │ │ │ │ ├── wb_mast_model.v │ │ │ │ ├── wb_model_defines.v │ │ │ │ └── wb_slv_model.v │ │ ├── cvc.log │ │ ├── doc │ │ │ ├── preliminary_ata_core.pdf │ │ │ └── src │ │ │ │ └── ata_core.doc │ │ ├── rtl │ │ │ ├── verilog │ │ │ │ ├── ocidec-1 │ │ │ │ │ ├── atahost_controller.v │ │ │ │ │ ├── atahost_pio_tctrl.v │ │ │ │ │ ├── atahost_top.v │ │ │ │ │ ├── atahost_wb_slave.v │ │ │ │ │ ├── revision_history.txt │ │ │ │ │ ├── ro_cnt.v │ │ │ │ │ ├── timescale.v │ │ │ │ │ └── ud_cnt.v │ │ │ │ └── ocidec-2 │ │ │ │ │ ├── atahost_controller.v │ │ │ │ │ ├── atahost_pio_actrl.v │ │ │ │ │ ├── atahost_pio_tctrl.v │ │ │ │ │ ├── atahost_top.v │ │ │ │ │ ├── atahost_wb_slave.v │ │ │ │ │ ├── revision_history.txt │ │ │ │ │ ├── ro_cnt.v │ │ │ │ │ ├── timescale.v │ │ │ │ │ └── ud_cnt.v │ │ │ └── vhdl │ │ │ │ ├── ocidec1 │ │ │ │ ├── atahost_controller.vhd │ │ │ │ ├── atahost_pio_tctrl.vhd │ │ │ │ ├── atahost_top.vhd │ │ │ │ ├── atahost_wb_slave.vhd │ │ │ │ ├── revision_history.txt │ │ │ │ ├── ro_cnt.vhd │ │ │ │ └── ud_cnt.vhd │ │ │ │ ├── ocidec2 │ │ │ │ ├── atahost_controller.vhd │ │ │ │ ├── atahost_pio_actrl.vhd │ │ │ │ ├── atahost_pio_tctrl.vhd │ │ │ │ ├── atahost_top.vhd │ │ │ │ ├── atahost_wb_slave.vhd │ │ │ │ ├── revision_history.txt │ │ │ │ ├── ro_cnt.vhd │ │ │ │ └── ud_cnt.vhd │ │ │ │ └── ocidec3 │ │ │ │ ├── atahost_controller.vhd │ │ │ │ ├── atahost_dma_actrl.vhd │ │ │ │ ├── atahost_dma_tctrl.vhd │ │ │ │ ├── atahost_fifo.vhd │ │ │ │ ├── atahost_lfsr.vhd │ │ │ │ ├── atahost_pio_actrl.vhd │ │ │ │ ├── atahost_pio_controller.vhd │ │ │ │ ├── atahost_pio_tctrl.vhd │ │ │ │ ├── atahost_reg_buf.vhd │ │ │ │ ├── atahost_top.vhd │ │ │ │ ├── atahost_wb_slave.vhd │ │ │ │ ├── revision_history.txt │ │ │ │ ├── ro_cnt.vhd │ │ │ │ └── ud_cnt.vhd │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ └── bin │ │ │ │ └── Makefile │ │ ├── syn │ │ │ └── bin │ │ │ │ ├── comp.dc │ │ │ │ ├── design_spec.dc │ │ │ │ ├── lib_spec.dc │ │ │ │ └── read.dc │ │ ├── tests.v │ │ ├── timescale.v │ │ └── wb_model_defines.v │ ├── can │ │ ├── README │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── can_testbench.v │ │ │ │ ├── can_testbench_defines.v │ │ │ │ └── timescale.v │ │ ├── can_defines.v │ │ ├── can_testbench_defines.v │ │ ├── cvc.log │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── README.txt │ │ │ │ ├── can_acf.v │ │ │ │ ├── can_bsp.v │ │ │ │ ├── can_btl.v │ │ │ │ ├── can_crc.v │ │ │ │ ├── can_defines.v │ │ │ │ ├── can_fifo.v │ │ │ │ ├── can_ibo.v │ │ │ │ ├── can_register.v │ │ │ │ ├── can_register_asyn.v │ │ │ │ ├── can_register_asyn_syn.v │ │ │ │ ├── can_register_syn.v │ │ │ │ ├── can_registers.v │ │ │ │ └── can_top.v │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ ├── INCA_libs │ │ │ │ │ └── worklib │ │ │ │ │ │ └── dir_keeper │ │ │ │ ├── cds.lib │ │ │ │ ├── hdl.var │ │ │ │ ├── memory_file_list │ │ │ │ ├── rtl_file_list │ │ │ │ └── sim_file_list │ │ │ │ ├── log │ │ │ │ └── dir_keeper │ │ │ │ ├── out │ │ │ │ └── dir_keeper │ │ │ │ └── run │ │ │ │ ├── clean │ │ │ │ ├── run_sim.scr │ │ │ │ └── wave.do │ │ ├── syn │ │ │ ├── libero │ │ │ │ └── pinedit.gcf │ │ │ └── synplicity │ │ │ │ ├── can.prj │ │ │ │ └── rev_1 │ │ │ │ └── dir_keeper │ │ └── timescale.v │ ├── cvc-open-core-sim-times.pdf │ ├── ethernet │ │ ├── README │ │ ├── bench │ │ │ └── tb_ethernet.v │ │ ├── cvc.log │ │ ├── eth_defines.v │ │ ├── eth_host.log │ │ ├── eth_memory.log │ │ ├── eth_phy_defines.v │ │ ├── ethernet_rx.log │ │ ├── ethernet_tx.log │ │ ├── log │ │ │ ├── eth_tb.log │ │ │ ├── eth_tb_host.log │ │ │ ├── eth_tb_memory.log │ │ │ ├── eth_tb_phy.log │ │ │ ├── eth_tb_wb_m_mon.log │ │ │ └── eth_tb_wb_s_mon.log │ │ ├── rtl │ │ │ ├── eth_clockgen.v │ │ │ ├── eth_cop.v │ │ │ ├── eth_crc.v │ │ │ ├── eth_fifo.v │ │ │ ├── eth_host.log │ │ │ ├── eth_host.v │ │ │ ├── eth_maccontrol.v │ │ │ ├── eth_macstatus.v │ │ │ ├── eth_memory.log │ │ │ ├── eth_memory.v │ │ │ ├── eth_miim.v │ │ │ ├── eth_outputcontrol.v │ │ │ ├── eth_phy.v │ │ │ ├── eth_random.v │ │ │ ├── eth_receivecontrol.v │ │ │ ├── eth_register.v │ │ │ ├── eth_registers.v │ │ │ ├── eth_rxaddrcheck.v │ │ │ ├── eth_rxcounters.v │ │ │ ├── eth_rxethmac.v │ │ │ ├── eth_rxstatem.v │ │ │ ├── eth_shiftreg.v │ │ │ ├── eth_spram_256x32.v │ │ │ ├── eth_top.v │ │ │ ├── eth_transmitcontrol.v │ │ │ ├── eth_txcounters.v │ │ │ ├── eth_txethmac.v │ │ │ ├── eth_txstatem.v │ │ │ ├── eth_wishbone.v │ │ │ ├── ethernet_rx.log │ │ │ ├── ethernet_tx.log │ │ │ ├── ram16x1d.v │ │ │ ├── tb_cop.v │ │ │ ├── tb_ethernet_with_cop.v │ │ │ ├── wb_bus_mon.v │ │ │ ├── wb_master32.v │ │ │ ├── wb_master_behavioral.v │ │ │ ├── wb_slave_behavioral.v │ │ │ └── xilinx_dist_ram_16x32.v │ │ ├── run.flist │ │ ├── tb_eth_defines.v │ │ ├── tb_eth_top.vh │ │ ├── timescale.v │ │ └── wb_model_defines.v │ ├── generic_fifos │ │ ├── README │ │ ├── bench │ │ │ └── verilog │ │ │ │ └── test_bench_top.v │ │ ├── cvc.log │ │ ├── doc │ │ │ └── README.txt │ │ ├── generic_dpram.v │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── generic_fifo_dc.v │ │ │ │ ├── generic_fifo_dc_gray.v │ │ │ │ ├── generic_fifo_lfsr.v │ │ │ │ ├── generic_fifo_sc_a.v │ │ │ │ ├── generic_fifo_sc_b.v │ │ │ │ ├── lfsr.v │ │ │ │ └── timescale.v │ │ ├── run.flist │ │ ├── sim │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ │ └── run │ │ │ │ └── waves │ │ │ │ └── waves.do │ │ └── timescale.v │ ├── m68k │ │ ├── README │ │ ├── README_VERILATOR.txt │ │ ├── bench │ │ │ ├── bench.cpp │ │ │ ├── bench.v │ │ │ ├── k68_soc_test.v │ │ │ ├── k68_testram.v │ │ │ ├── k68_testrom.v │ │ │ └── test.s │ │ ├── cvc.log │ │ ├── input.vc │ │ ├── k68_defines.v │ │ ├── rtl │ │ │ ├── k68_adder.v │ │ │ ├── k68_appl.v │ │ │ ├── k68_arb.v │ │ │ ├── k68_asx.v │ │ │ ├── k68_b2d.v │ │ │ ├── k68_buni.v │ │ │ ├── k68_calc.v │ │ │ ├── k68_ccc.v │ │ │ ├── k68_clkgen.v │ │ │ ├── k68_cpu.v │ │ │ ├── k68_d2b.v │ │ │ ├── k68_decode.v │ │ │ ├── k68_defines.v │ │ │ ├── k68_dpmem.v │ │ │ ├── k68_execute.v │ │ │ ├── k68_fetch.v │ │ │ ├── k68_load.v │ │ │ ├── k68_lsx.v │ │ │ ├── k68_par_mul.v │ │ │ ├── k68_prims.v │ │ │ ├── k68_regbank.v │ │ │ ├── k68_rox.v │ │ │ ├── k68_roxx.v │ │ │ ├── k68_sasc.v │ │ │ ├── k68_soc.v │ │ │ ├── sasc_brg.v │ │ │ ├── sasc_fifo4.v │ │ │ ├── sasc_top.v │ │ │ └── timescale.v │ │ ├── run.flist │ │ ├── sim │ │ │ ├── DEBUG_oprofile │ │ │ └── Makefile │ │ ├── test.rom.vh │ │ └── timescale.v │ ├── sha1 │ │ ├── README │ │ ├── cvc.log │ │ ├── dffhr.v │ │ ├── run.flist │ │ ├── sha1_exec.v │ │ ├── sha1_readme_v01.txt │ │ ├── sha1_round.v │ │ └── sha1_testbench.v │ ├── usb11 │ │ ├── README │ │ ├── cvc.log │ │ ├── generic_fifos │ │ │ ├── common │ │ │ │ └── generic_memories │ │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ └── generic_dpram.v │ │ │ └── generic_fifos │ │ │ │ ├── doc │ │ │ │ └── readme.txt │ │ │ │ └── rtl │ │ │ │ └── verilog │ │ │ │ ├── generic_fifo_dc.v │ │ │ │ ├── generic_fifo_dc_gray.v │ │ │ │ ├── generic_fifo_lfsr.v │ │ │ │ ├── generic_fifo_sc_a.v │ │ │ │ ├── generic_fifo_sc_b.v │ │ │ │ ├── lfsr.v │ │ │ │ └── timescale.v │ │ ├── run.flist │ │ ├── tests.v │ │ ├── tests_lib.v │ │ ├── timescale.v │ │ ├── usb1_defines.v │ │ ├── usb1_funct │ │ │ ├── bench │ │ │ │ └── verilog │ │ │ │ │ ├── test_bench_top.v │ │ │ │ │ ├── tests.v │ │ │ │ │ ├── tests_lib.v │ │ │ │ │ └── timescale.v │ │ │ ├── doc │ │ │ │ ├── README.txt │ │ │ │ └── success_story.txt │ │ │ ├── rtl │ │ │ │ └── verilog │ │ │ │ │ ├── timescale.v │ │ │ │ │ ├── usb1_core.v │ │ │ │ │ ├── usb1_crc16.v │ │ │ │ │ ├── usb1_crc5.v │ │ │ │ │ ├── usb1_ctrl.v │ │ │ │ │ ├── usb1_defines.v │ │ │ │ │ ├── usb1_fifo2.v │ │ │ │ │ ├── usb1_idma.v │ │ │ │ │ ├── usb1_pa.v │ │ │ │ │ ├── usb1_pd.v │ │ │ │ │ ├── usb1_pe.v │ │ │ │ │ ├── usb1_pl.v │ │ │ │ │ ├── usb1_rom1.v │ │ │ │ │ └── usb1_utmi_if.v │ │ │ └── sim │ │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ └── Makefile │ │ │ │ └── run │ │ │ │ └── Makefile │ │ └── usb_phy │ │ │ ├── doc │ │ │ └── readme.txt │ │ │ └── rtl │ │ │ └── verilog │ │ │ ├── timescale.v │ │ │ ├── usb_phy.v │ │ │ ├── usb_rx_phy.v │ │ │ └── usb_tx_phy.v │ └── wb_dma │ │ ├── README │ │ ├── bench │ │ └── verilog │ │ │ ├── test_bench_top.v │ │ │ ├── tests.v │ │ │ ├── wb_mast_model.v │ │ │ ├── wb_model_defines.v │ │ │ └── wb_slv_model.v │ │ ├── cvc.log │ │ ├── doc │ │ ├── README.txt │ │ ├── STATUS.txt │ │ └── dma_doc.pdf │ │ ├── rtl │ │ └── verilog │ │ │ ├── wb_dma_ch_arb.v │ │ │ ├── wb_dma_ch_pri_enc.v │ │ │ ├── wb_dma_ch_rf.v │ │ │ ├── wb_dma_ch_sel.v │ │ │ ├── wb_dma_de.v │ │ │ ├── wb_dma_defines.v │ │ │ ├── wb_dma_inc30r.v │ │ │ ├── wb_dma_pri_enc_sub.v │ │ │ ├── wb_dma_rf.v │ │ │ ├── wb_dma_top.v │ │ │ ├── wb_dma_wb_if.v │ │ │ ├── wb_dma_wb_mast.v │ │ │ └── wb_dma_wb_slv.v │ │ ├── run.flist │ │ ├── sim │ │ └── rtl_sim │ │ │ └── bin │ │ │ └── Makefile │ │ ├── syn │ │ └── bin │ │ │ ├── comp.dc │ │ │ ├── design_spec.dc │ │ │ ├── lib_spec.dc │ │ │ └── read.dc │ │ ├── tests.v │ │ ├── wb_dma_defines.v │ │ └── wb_model_defines.v └── verilog_da_bnchmrks │ ├── README.DA-SOLUTIONS.ORIGINAL.1999 │ ├── das_cpu │ ├── README.CVC-FEATURES │ ├── README.DA-SOLUTIONS.ORIGINAL.1999 │ ├── cpu_mixed.v │ ├── cpu_rtl.v │ ├── expected.run_all_toggle │ ├── finish.inp │ ├── gen_untoggled_report_from_tgldat.vc │ ├── prog │ ├── run_all_toggle.vc │ ├── run_fst_dumpvars.vc │ ├── run_optcfg_bits_exclude.vc │ ├── run_optcfg_tree.vc │ ├── run_tgl_on_off.vc │ ├── run_xprop.vc │ ├── tasks │ ├── tgl_some.cfg │ └── tgl_tree.cfg │ ├── das_lfsr │ ├── README │ ├── lfsr.sdf │ ├── lfsr1000.v │ ├── lfsr1000.vc │ ├── lfsr1000_no_sdf.vc │ ├── lfsr1000_nosdf.vc │ ├── lfsr16000.v │ ├── lfsr16000.vc │ ├── lfsr2000.v │ ├── lfsr2000.vc │ ├── lfsr32000.v │ ├── lfsr32000.vc │ ├── lfsr4000.v │ ├── lfsr4000.vc │ ├── lfsr500.v │ ├── lfsr500.vc │ ├── lfsr500_nosdf.vc │ ├── lfsr500_udp.v │ ├── lfsr8000.v │ └── lfsr8000.vc │ ├── das_mult │ ├── README │ ├── mult_gate.v │ ├── mult_gate.vc │ ├── ref_in │ └── ref_out │ ├── libs │ ├── lca100kgate │ │ ├── AN2.v │ │ ├── AN3.v │ │ ├── AN4.v │ │ ├── AN5.v │ │ ├── BUF8A.v │ │ ├── EN.v │ │ ├── FA1A.v │ │ ├── FD2.v │ │ ├── FD2v.orig │ │ ├── OR2.v │ │ ├── OR3.v │ │ ├── OR4.v │ │ ├── OR5.v │ │ ├── ZERO.v │ │ └── fd2.fix │ ├── lca100kunit │ │ ├── FA1a.v.old │ │ ├── FD2.v.old │ │ ├── an2.v │ │ ├── an3.v │ │ ├── an4.v │ │ ├── an5.v │ │ ├── buf8a.v │ │ ├── en.v │ │ ├── fa1a.v │ │ ├── fd2.v │ │ ├── or2.v │ │ ├── or3.v │ │ ├── or4.v │ │ └── or5.v │ └── tgc1000gate │ │ ├── AN210.v │ │ ├── BF001.v │ │ ├── BF002.v │ │ ├── BF003.v │ │ ├── BF003.v.gate │ │ ├── BF006.v │ │ ├── BF051.v │ │ ├── BF052.v │ │ ├── BF053.v │ │ ├── BF056.v │ │ ├── EN210.v │ │ ├── EN2B0.v │ │ ├── EX210.v │ │ ├── EX2B0.v │ │ ├── IV110.v │ │ ├── NA210.v │ │ ├── NA310.v │ │ ├── NA311.v │ │ ├── NA410.v │ │ ├── NO210.v │ │ ├── OR210.v │ │ ├── OR310.v │ │ ├── TO010.v │ │ └── aoiudp.v │ └── ti_mult │ ├── README │ ├── mult.aiv.v │ ├── mult.aiv.vc │ ├── mult.v │ ├── mult.vc │ ├── multgp.v │ ├── patterns │ ├── tb.v │ └── ti.v └── toggle_coverage ├── README.coverage.helper-programs ├── bin ├── chk_tgldat ├── tgldat_merge ├── tgldat_report └── tvcd_to_tgldat └── src ├── README ├── chk_tgldat.c ├── makefile.lnx ├── tgldat.h ├── tgldat_merge.c ├── tgldat_report.c ├── tgldat_srvc.c └── tvcd_to_tgldat.c /.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | verilog.log 3 | cvcsim 4 | hexasm 5 | *.s 6 | cvc64 7 | -------------------------------------------------------------------------------- /OSS-CVC-ARTISTIC-LICENSING-FAQ.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/OSS-CVC-ARTISTIC-LICENSING-FAQ.pdf -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | 2 | This is OSS CVC IEEE P1364 Verilog simulator package release. 3 | 4 | Before installing or using OSS CVC you must read and agree to the 5 | "oss cvc dual licensing modified artistic license". By installing 6 | or using OSS CVC Package, you are agreeing to the license. If you 7 | do not agree to the license, do not install OSS CVC. Read the 8 | "oss-cvc-artistic-licensing.faq" in this directory to learn about 9 | the various possibilities of dual open source and commercial licensing. 10 | 11 | INSTALLATION: 12 | 13 | Instructions for making CVC or for installing CVC pre-made binaries (if 14 | you are an Enterprise OSS CVC customer) are in the INSTALL file in this 15 | directory. 16 | 17 | ENTERPRISE OSS CVC: 18 | 19 | To purchase Enterprise OSS CVC with pre-made binaries and support send 20 | email to craigr@tachyon-da.com. 21 | 22 | Also send email to craigr@tachyon-da.com to purchase a commercial OSS 23 | CVC license that allows OSS CVC do be combined with closed source 24 | software. 25 | -------------------------------------------------------------------------------- /bin/README: -------------------------------------------------------------------------------- 1 | 2 | The CVC binaries are now released as a separate directory because the 3 | major release files usually change much less frequently than the CVC 4 | binaries. To run the install_test you must copy the version of cvc and cvc64 5 | that corresponds to your RHEL operating system version to somewhere on 6 | your OS executable PATH environment. 7 | 8 | The binaries alon with the Changlog will be in directory 9 | 10 | -cvc-binaries-.dir 11 | 12 | The binaries will be named cvc... 13 | or cvc64... for cvc64. 14 | 15 | If you use the PLI, the pli_incs directory in the files-release directory 16 | must be copied to somewher on your gcc include (-I?) path. 17 | -------------------------------------------------------------------------------- /bin/checkcvc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/bin/checkcvc -------------------------------------------------------------------------------- /bin/checkcvc32: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/bin/checkcvc32 -------------------------------------------------------------------------------- /chkcvc.src.dir/README: -------------------------------------------------------------------------------- 1 | The checkcvc and checkcvc64 binaries are in the release bin directory. 2 | You should just run those. The makefile.lnx and makefile.lnx64 can be 3 | used to make the binaries again if you need to. 4 | 5 | If you really want to run on an old 32 bit linux OS, you need to change 6 | makefile.lnx to not define __X86_64__. 7 | -------------------------------------------------------------------------------- /chkcvc.src.dir/checkcvc64: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/chkcvc.src.dir/checkcvc64 -------------------------------------------------------------------------------- /chkcvc.src.dir/makefile.lnx: -------------------------------------------------------------------------------- 1 | CC=gcc 2 | LIBS= -lm -ldl 3 | # if you really want to run cvc on an old 32 bit linux remove the define 4 | CFLAGS=-O2 -m32 -D__X86_64__ 5 | 6 | all: 7 | $(CC) $(CFLAGS) $(LIBS) chkcvc.c -o checkcvc 8 | -------------------------------------------------------------------------------- /chkcvc.src.dir/makefile.lnx64: -------------------------------------------------------------------------------- 1 | CC=gcc 2 | LIBS= -ldl 3 | CFLAGS=-O2 -D__X86_64__ 4 | 5 | all: 6 | $(CC) $(CFLAGS) chkcvc64.c -o checkcvc64 $(LIBS) 7 | -------------------------------------------------------------------------------- /doc/Changelog: -------------------------------------------------------------------------------- 1 | 2 | Mon Jun 9 11:14:22 PDT 2014 3 | RELEASE 7.00b 4 | 1. Initial OSS CVC release. 5 | 6 | Thu Jul 31 12:12:57 PDT 2014 7 | RELEASE 7.00c 8 | 1. Added latest Gtkwave library calls and interface from Tony Bybell 9 | 2. Removed old wrong quick start pdf file from doc directory. 10 | -------------------------------------------------------------------------------- /doc/cvc_xpropagation.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/doc/cvc_xpropagation.pdf -------------------------------------------------------------------------------- /doc/oss-cvc-quick-start-061014.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/doc/oss-cvc-quick-start-061014.pdf -------------------------------------------------------------------------------- /doc/systemverilog.doc/how-to-use-some-systemverilog-features.README: -------------------------------------------------------------------------------- 1 | ======================================== 2 | CVC CURRENT SUPPORT FOR SYSTEMVERILOG 3 | ======================================== 4 | 5 | To use the new SystemVerilog features (SV), you must use the -systemverilog 6 | or -sv option at compile time. This is neccessary for CVC to be backward 7 | compatible with regular Verilog. Most conflicts between Verilog and 8 | SystemVerilog are a result of commonly used variables names which are now 9 | keywords in SV (byte/int, etc). 10 | 11 | Currently supported SV features are illustrated in the 'svimplemented.v' 12 | located in this directory that can be run through CVC. 13 | 14 | 15 | Using the -sv_lib to use the dpi_ PLI interface also turns on -systemverilog 16 | (-sv) switch. 17 | 18 | Copyright (c) 2001-2014 Tachyon Design Automation 19 | -------------------------------------------------------------------------------- /getting_started.README: -------------------------------------------------------------------------------- 1 | 2 | - Read the 'cvc_quick_start.pdf' on getting started using CVC in the 3 | "doc" directory. 4 | 5 | - OSS CVC contains new X-propagation features to help find RTL X-bugs. See 6 | the CVC X-propagation guide (doc/cvc_xpropagation.pdf) for more 7 | information on how to use +xprop. 8 | 9 | - OSS CVC has new improved instance and net bit specific toggle coverage 10 | features with the new simplifed .tgldat cumulative toggle coverage 11 | reporting file format. 12 | 13 | - See the CVC coverage guide (doc/toggle_coverage_manual.txt) for instructons 14 | or type cvc -h for brief explanations of the new options. The 15 | '-optconfigfile [file]' option now allows extra control for setting 16 | coverage or PLI access levels for each instance tree location and 17 | each net bit in the untoggled concise report. 18 | 19 | - For making OSS CVC binaries see the readme in the src directory. 20 | 21 | Copyright (c) 2001-2014 Tachyon Design Automation 22 | -------------------------------------------------------------------------------- /pli_incs/cv_acc_user.h: -------------------------------------------------------------------------------- 1 | 2 | /****************************************************************************** 3 | * cv_acc_user.h 4 | * 5 | * Simulator specific acc_user.h (acc_ routines) include file 6 | * 7 | * This file contains the constant definitions, structure definitions 8 | * used in IEEE P1364 LRM but not defined in acc_user.h file in appendix. 9 | * 10 | * It must be included after acc_user.h 11 | * 12 | * 13 | * This file also contains the acc_ routines that are in common use but 14 | * not in the IEEE standard 15 | * 16 | * Copyright (c) 2011-2013 Tachyon Design Automation All rights reserved. 17 | * Copyright 1995, IEEE. All rights reserved. 18 | ******************************************************************************/ 19 | #ifndef CVACCUSER_H 20 | #define CVACCUSER_H 21 | 22 | /*---------------------------------------------------------------------------*/ 23 | /*--------------------------- routine definitions ---------------------------*/ 24 | /*---------------------------------------------------------------------------*/ 25 | #if defined(__STDC__) || defined(__cplusplus) 26 | 27 | #ifndef PROTO_PARAMS 28 | #define PROTO_PARAMS(params) params 29 | #define DEFINED_PROTO_PARAMS 30 | #endif 31 | #ifndef EXTERN 32 | #define EXTERN 33 | #define DEFINED_EXTERN 34 | #endif 35 | 36 | #else 37 | 38 | #ifndef PROTO_PARAMS 39 | #define PROTO_PARAMS(params) (/* nothing */) 40 | #define DEFINED_PROTO_PARAMS 41 | #endif 42 | #ifndef EXTERN 43 | #define EXTERN extern 44 | #define DEFINED_EXTERN 45 | #endif 46 | 47 | #endif /* __STDC__ */ 48 | 49 | /* added routine for dumping internal acc_ handle contents */ 50 | EXTERN int __acc_show_object PROTO_PARAMS((handle obj)); 51 | 52 | #ifdef DEFINED_PROTO_PARAMS 53 | #undef DEFINED_PROTO_PARAMS 54 | #undef PROTO_PARAMS 55 | #endif 56 | 57 | #ifdef DEFINED_EXTERN 58 | #undef DEFINED_EXTERN 59 | #undef EXTERN 60 | #endif 61 | 62 | #endif /* CV_ACC_USER_H */ 63 | -------------------------------------------------------------------------------- /src/.CODEGEN.NOTES.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/src/.CODEGEN.NOTES.swp -------------------------------------------------------------------------------- /src/helpgen.inp: -------------------------------------------------------------------------------- 1 | /* file to generate debugger help */ 2 | $nokeepcommands; 3 | :set nologecho 4 | :info logecho 5 | $display(".. printing basic help message"); 6 | :help 7 | $input("helpgen2.inp"); 8 | -------------------------------------------------------------------------------- /src/helpgen2.inp: -------------------------------------------------------------------------------- 1 | /* generate help message for debugger topics */ 2 | $display("\n... printing help topic messages"); 3 | :help debugging 4 | $write("\n"); 5 | :help compiling 6 | $write("\n"); 7 | :help tracing 8 | $write("\n"); 9 | :help differences 10 | $write("\n"); 11 | :help statements 12 | $write("\n"); 13 | :help data 14 | $write("\n"); 15 | :help source 16 | $write("\n"); 17 | :help scope 18 | $write("\n"); 19 | :help breakpoints 20 | $write("\n"); 21 | :help changes 22 | $write("\n"); 23 | :help history 24 | $write("\n"); 25 | :help info 26 | $write("\n"); 27 | :help tasks 28 | $write("\n"); 29 | :help commands 30 | $input("helpgen3.inp"); 31 | -------------------------------------------------------------------------------- /src/helpgen3.inp: -------------------------------------------------------------------------------- 1 | // generate help message for individual : debugger commands 2 | $display("\n... printing : debugger help command messages"); 3 | :help :help 4 | $write("\n"); 5 | :help :shell 6 | $write("\n"); 7 | :help :where 8 | $write("\n"); 9 | :help :quit 10 | $write("\n"); 11 | :help :print 12 | $write("\n"); 13 | :help :reset 14 | $write("\n"); 15 | :help :expris 16 | $write("\n"); 17 | :help :varis 18 | $write("\n"); 19 | :help :whatis 20 | $write("\n"); 21 | :help :list 22 | $write("\n"); 23 | :help :set 24 | $write("\n"); 25 | :help :info 26 | $write("\n"); 27 | :help :scope 28 | $write("\n"); 29 | :help :breakpoint 30 | $write("\n"); 31 | :help :ibreakpoint 32 | $write("\n"); 33 | :help :delete 34 | $write("\n"); 35 | :help :enable 36 | $write("\n"); 37 | :help :disabl 38 | $write("\n"); 39 | :help :step 40 | $write("\n"); 41 | :help :istep 42 | $write("\n"); 43 | :help :history 44 | $write("\n"); 45 | :help :emptyhistory 46 | $write("\n"); 47 | :help :display 48 | $write("\n"); 49 | :help :undisplay 50 | $write("\n"); 51 | :help :tbreakpoint 52 | $write("\n"); 53 | :help :tibreakpoint 54 | $write("\n"); 55 | :help :ignore 56 | $write("\n"); 57 | :help :cond 58 | $write("\n"); 59 | :help :snapshot 60 | $write("\n"); 61 | :help :nextb 62 | $write("\n"); 63 | $keepcommands; 64 | :set logecho 65 | $finish(2); 66 | -------------------------------------------------------------------------------- /src/libz.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/src/libz.a -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/accxldrvtst.v: -------------------------------------------------------------------------------- 1 | // specify test for fd clear/set flip flop 2 | module test; 3 | wire t_q; 4 | reg t_clk, t_clk0, t_clk1, t_clk2, t_d, t_clr, t_set; 5 | 6 | fd3noqn i1(t_q0, t_clk2, t_clk2, t_d0, t_clr0, t_set0); 7 | fd3noqn i2(t_q1, t_clk2, t_clk2, t_d1, t_clr1, t_set1); 8 | fd3noqn i3(t_q, t_clk, t_clk1, t_d, t_clr, t_set); 9 | 10 | initial 11 | begin 12 | $test; 13 | $monitor($stime,, "q=%b, clk=%b, data=%b, clr=%b, set=%b", 14 | t_q, t_clk, t_d, t_clr, t_set); 15 | end 16 | endmodule 17 | 18 | module fd3noqn(q, clk, clk1, d, clr, set); 19 | output q; 20 | input clk, clk1, d, clr, set; 21 | wire xxx; 22 | 23 | xl_fd3 #10 i0(xxx, d, clk, clr, set); 24 | buf i1(q, xxx); 25 | not i2(qn, xxx); 26 | endmodule 27 | 28 | primitive xl_fd3(q, d, clk, clr, set); 29 | output q; reg q; 30 | input d, clk, clr, set; 31 | 32 | table 33 | // d clk clr set : q : q 34 | // - --- --- --- - - - - 35 | // set/clear low assertion 36 | ? ? ? 0 : ? : 1 ; 37 | ? ? ? x : ? : x ; 38 | ? ? 0 1 : ? : 0 ; 39 | ? ? x 1 : ? : x ; 40 | 41 | 0 r 1 1 : ? : 0 ; 42 | 1 r 1 1 : ? : 1 ; 43 | x r 1 1 : ? : x ; 44 | 45 | ? f 1 1 : ? : - ; 46 | ? (x?) 1 1 : ? : - ; 47 | ? (?x) 1 1 : ? : - ; 48 | * ? 1 1 : ? : - ; 49 | ? ? r 1 : ? : - ; 50 | ? ? 1 r : ? : - ; 51 | endtable 52 | endprimitive 53 | -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/clean.sh: -------------------------------------------------------------------------------- 1 | rm -f acc_probe acc_nxtchild accxl_drvld acc_prtchg *.o 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/makefile.lnx32: -------------------------------------------------------------------------------- 1 | 2 | # could add to CFLAGS to turn on warnings if you are using gcc 3 | WARNS=-Wall 4 | 5 | # change path if not running test from installed directory location 6 | INCS=-I../../pli_incs 7 | # maybe want -O and/or -g, if you use -O use -m486 8 | CFLAGS= -fPIC -Wall -m32 $(INCS) 9 | LFLAGS= -G -shared -export-dynamic -melf_i386 10 | 11 | # change to your compiler 12 | CC=gcc 13 | 14 | acc_probe.o: acc_probe.c 15 | $(CC) $(CFLAGS) -c acc_probe.c 16 | 17 | acc_nxtchld.o: acc_nxtchld.c 18 | $(CC) $(CFLAGS) -c acc_nxtchld.c 19 | 20 | accxl_drvld.o: accxl_drvld.c 21 | $(CC) $(CFLAGS) -c accxl_drvld.c 22 | 23 | acc_prtchg.o: acc_prtchg.c 24 | $(CC) $(CFLAGS) -c acc_prtchg.c 25 | 26 | # make rules for dynamic libraries 27 | acc_probe.so: acc_probe.o 28 | $(LD) $(LFLAGS) acc_probe.o -o acc_probe.so 29 | 30 | acc_nxtchld.so: acc_nxtchld.o 31 | $(LD) $(LFLAGS) acc_nxtchld.o -o acc_nxtchld.so 32 | 33 | accxl_drvld.so: accxl_drvld.o 34 | $(LD) $(LFLAGS) accxl_drvld.o -o accxl_drvld.so 35 | 36 | acc_prtchg.so: acc_prtchg.o 37 | $(LD) $(LFLAGS) acc_prtchg.o -o acc_prtchg.so 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/makefile.lnx64: -------------------------------------------------------------------------------- 1 | 2 | # could add to CFLAGS to turn on warnings if you are using gcc 3 | WARNS=-Wall 4 | 5 | # change path if not running test from installed directory location 6 | INCS=-I../../pli_incs 7 | # maybe want -O and/or -g, if you use -O use -m486 8 | CFLAGS= -fPIC -Wall $(INCS) 9 | LFLAGS= -G -shared -export-dynamic 10 | 11 | # change to your compiler 12 | CC=gcc 13 | 14 | acc_probe.o: acc_probe.c 15 | $(CC) $(CFLAGS) -c acc_probe.c 16 | 17 | acc_nxtchld.o: acc_nxtchld.c 18 | $(CC) $(CFLAGS) -c acc_nxtchld.c 19 | 20 | accxl_drvld.o: accxl_drvld.c 21 | $(CC) $(CFLAGS) -c accxl_drvld.c 22 | 23 | acc_prtchg.o: acc_prtchg.c 24 | $(CC) $(CFLAGS) -c acc_prtchg.c 25 | 26 | # make rules for dynamic libraries 27 | acc_probe.so: acc_probe.o 28 | $(LD) $(LFLAGS) acc_probe.o -o acc_probe.so 29 | 30 | acc_nxtchld.so: acc_nxtchld.o 31 | $(LD) $(LFLAGS) acc_nxtchld.o -o acc_nxtchld.so 32 | 33 | accxl_drvld.so: accxl_drvld.o 34 | $(LD) $(LFLAGS) accxl_drvld.o -o accxl_drvld.so 35 | 36 | acc_prtchg.so: acc_prtchg.o 37 | $(LD) $(LFLAGS) acc_prtchg.o -o acc_prtchg.so 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/probe.v: -------------------------------------------------------------------------------- 1 | module probe; 2 | reg [31:0] a, b, c; 3 | 4 | initial 5 | begin 6 | $setup_values(a, b, c); 7 | #10 a = 3; c = 1; 8 | #10 b = 3; c = 2; 9 | #10 c = 3; 10 | #10 a = 33; c = 9; 11 | #10 b = 44; c = 22; 12 | #10 a = 30; 13 | #10 a = 50; b = 200; c = 0; 14 | #10 a = 50; c = 99; 15 | #10 b = 90; c = 99; 16 | #10 b = 11; c = 19; 17 | end 18 | // do the flash 19 | always @(c) $flash_values($stime/2); 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/readme: -------------------------------------------------------------------------------- 1 | To test PLI 1.0 acc_ interface: 2 | 3 | BEFORE STARTING: 4 | Make sure binary CVC is installed in bin directory 2 levels up 5 | (../../bin/cvc) and run the shell script in install.test directory to 6 | verify correct installation of CVC. 7 | 8 | When compiling a design for use with the PLI you may need to compile with 9 | +acc+[level] command. This option compiles with the following levels of 10 | PLI access: 11 | 12 | +acc+1 or +acc 13 | Enable all PLI capabilities except value change callbacks and 14 | delay annotation. 15 | +acc+2 16 | All features above plus value change callbacks. 17 | +acc+3 18 | All features above plus module path delay. 19 | +acc+4 20 | All features above plus gate delay annotation. 21 | 22 | We are working on VCS style .tab file for more specific access options to 23 | increase peformance when using the PLI. 24 | 25 | HOW TO RUN THE TEST SCRIPT 26 | 27 | 1) Run the shell script inst_pli.sh. Various compiler and Verilog 28 | output messages will be printed but there should be no diff command 29 | differences printed. 30 | 31 | The commands to run CVC with dynamically loaded user PLI library 32 | explicitly access the user .so library in this directory. For your 33 | PLI libraries, it is better to set the LD_LIBRARY_PATH environment 34 | variables so explicit "./" is not needed 35 | 36 | 2) After completing the test, you can run clean.sh to remove work files. 37 | The inst_pli.sh script removes each PLI library .so dynamic library after 38 | running the test that uses it so unless something went wrong, you 39 | do not need to run clean.sh. 40 | 41 | 3) Use makefile.lnx as a template for your PLI programs. 42 | -------------------------------------------------------------------------------- /tests_and_examples/examples.acc/rmlic.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | my $file; 4 | my $i; 5 | my $line; 6 | 7 | $file = 'verilog.log'; 8 | if (@ARGV == 1) 9 | { 10 | $file = $ARGV[0]; 11 | } 12 | 13 | open(FILE, $file) or die "Can't open $file\n"; 14 | open(TMP, '>tmp') or die "Can't open tmp file\n"; 15 | for($i = 0; $i < 3; $i++) 16 | { 17 | $line = ; 18 | } 19 | while() 20 | { 21 | print TMP $_; 22 | } 23 | close TMP; 24 | close FILE; 25 | rename 'tmp', $file; 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/README: -------------------------------------------------------------------------------- 1 | 2 | DPI ROUTINE EXAMPLES AND INSTALLATION TEST 3 | 4 | This directory contains examples to illustrate how to use the SystemVerilog 5 | Direct Programming Interface (DPI) with CVC. To test for correct installation 6 | run the dpi_test.sh script that compiles DPI programs into .so libraries which 7 | are linked at compile time using -sv_lib [.so lib name] CVC command line 8 | option. 9 | 10 | Tests are: 11 | 12 | 1) twostate_tasks - test passing of 2-state values as input/outputs to tasks. 13 | 2) twostate_functions - use of functions with 2-state values. 14 | 3) fourstate - passing/setting 4-state values in DPI. 15 | 4) export - using DPI export to call Verilog tasks from C. 16 | 5) twostate_array - use of 2-state arrays. 17 | 6) fourstate_array - use of 4-state arrays. 18 | 7) reals - using reals with the DPI. 19 | 8) selects - use built in sv* bit and part select calls. 20 | 9) chandle - using chandle types in Verilog to pass C pointers. 21 | 22 | 23 | Currently CVC supports the following built in SV calls from svdpi.h: 24 | 25 | svDpiVersion 26 | svGetBitselBit 27 | svGetBitselLogic 28 | svPutBitselBit 29 | svPutBitselLogic 30 | svGetPartselBit 31 | svGetPartselLogic 32 | svPutPartselBit 33 | svPutPartselLogic 34 | svGetScope 35 | svSetScope 36 | svGetNameFromScope 37 | svGetScopeFromName 38 | 39 | Not yet supported: 40 | 41 | 'void function' - these should just be declared as tasks. 42 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/chandle.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | char cstr1[] = "CHANDLE STRING 1"; 5 | char cstr2[] = "CHANDLE STRING 2"; 6 | 7 | char *get_address(int i) 8 | { 9 | char *cp; 10 | 11 | if (i == 1) cp = cstr1; 12 | else cp = cstr2; 13 | return(cp); 14 | } 15 | 16 | void print_str(char *str) 17 | { 18 | io_printf("PASSED STRING: %s\n", str); 19 | } 20 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/chandle.plg: -------------------------------------------------------------------------------- 1 | PASSED STRING: CHANDLE STRING 1 2 | PASSED STRING: CHANDLE STRING 2 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/chandle.v: -------------------------------------------------------------------------------- 1 | /* 2 | * simple chandle (C pointers) test 3 | */ 4 | module test_chandle; 5 | import "DPI-C" function chandle get_address(input int i); 6 | import "DPI-C" task print_str(input chandle c); 7 | chandle c1, c2; 8 | 9 | initial begin 10 | c1 = get_address(1); 11 | print_str(c1); 12 | c2 = get_address(2); 13 | print_str(c2); 14 | end 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/diffname.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void ctest(svLogic b, svLogic b2) 5 | { 6 | io_printf("scalar values %d %d\n", b, b2); 7 | } 8 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/diffname.plg: -------------------------------------------------------------------------------- 1 | scalar values 0 1 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/diffname.v: -------------------------------------------------------------------------------- 1 | /* 2 | * test to use different name in Verilog than the C lib 3 | */ 4 | module diffname_test; 5 | import "DPI-C" ctest = task scalar_value(input reg b, input reg b2); 6 | 7 | reg s, s2; 8 | 9 | initial begin 10 | s = 0; 11 | s2 = 1; 12 | scalar_value(s, s2); 13 | end 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/export.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void verilogtask(svLogic, svLogic, svLogic); 5 | 6 | void ctask(void) 7 | { 8 | svLogic s,s2, s3; 9 | io_printf("C Task\n"); 10 | s = 1; 11 | s2 = 0; 12 | s3 = 3; 13 | verilogtask(s, s2, s3); 14 | } 15 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/export.plg: -------------------------------------------------------------------------------- 1 | C Task 2 | Verilog Task r=1 r2=0 r3=x 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/export.v: -------------------------------------------------------------------------------- 1 | /* 2 | * test calling Verilog task from C using DPI export 3 | */ 4 | module test_export; 5 | import "DPI-C" task ctask; 6 | 7 | export "DPI-C" task verilogtask; 8 | 9 | 10 | initial begin 11 | ctask; 12 | end 13 | 14 | task verilogtask(input reg r, input reg r2, input reg r3); 15 | $display("Verilog Task r=%d r2=%d r3=%d", r, r2, r3); 16 | endtask 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/fourstate.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void reg_test(const svLogicVecVal *i) 5 | { 6 | io_printf("REG aval=%d bval=%d\n", i->aval, i->bval); 7 | } 8 | 9 | void reg_assign(svLogicVecVal *i) 10 | { 11 | io_printf("ASSIGN REG aval=%d bval=%d\n", i->aval, i->bval); 12 | i->aval = 12; 13 | } 14 | 15 | void reg_wide(svLogicVecVal *vp) 16 | { 17 | int a0, a1; 18 | svLogicVecVal *ip0, *ip1; 19 | 20 | io_printf("ASSIGNING WIDE\n"); 21 | ip0 = &(vp[0]); 22 | a0 = ip0->aval; 23 | ip1 = &(vp[1]); 24 | a1 = ip1->aval; 25 | io_printf("a0 =%x a1 = %x\n", a0, a1); 26 | ip0->aval = 0xbbbbbbbb; 27 | ip1->aval = 0xcccccccc; 28 | } 29 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/fourstate.plg: -------------------------------------------------------------------------------- 1 | REG aval=13 bval=0 2 | ri= 13 3 | rio= 11 4 | ASSIGN REG aval=11 bval=0 5 | after rio= 12 6 | w=ffffffffaaaaaaaa 7 | ASSIGNING WIDE 8 | a0 =aaaaaaaa a1 = ffffffff 9 | after w=ccccccccbbbbbbbb 10 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/fourstate.v: -------------------------------------------------------------------------------- 1 | /* 2 | * simple 4-state input/output test 3 | */ 4 | module test_fourstate; 5 | import "DPI-C" task reg_test(input reg [31:0] i); 6 | import "DPI-C" task reg_assign(inout reg [31:0] io); 7 | import "DPI-C" task reg_wide(inout reg [63:0] i); 8 | 9 | reg [31:0] ri, rio; 10 | reg [63:0] w; 11 | 12 | 13 | initial begin 14 | ri = 13; 15 | reg_test(ri); 16 | $display("ri=%d", ri); 17 | rio = 11; 18 | $display("rio=%d", rio); 19 | reg_assign(rio); 20 | $display("after rio=%d", rio); 21 | 22 | w = 64'hffffffff_aaaaaaaa; 23 | $display("w=%x", w); 24 | reg_wide(w); 25 | $display("after w=%x", w); 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/fourstate_array.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void array_test(svLogicVecVal data[31]) 5 | { 6 | io_printf("data[0].aval = %d\n", data[0].aval); 7 | io_printf("data[1].aval = %d\n", data[1].aval); 8 | data[0].aval = 1; 9 | data[0].bval = 0; 10 | data[1].aval = 2; 11 | data[1].bval = 0; 12 | } 13 | 14 | void wide_array_test(svLogicVecVal *data[2]) 15 | { 16 | svLogicVecVal *ip0, *ip1; 17 | svLogicVecVal *svp0, *svp1; 18 | 19 | ip0 = data[0]; 20 | svp0 = &(ip0[0]); 21 | svp1 = &(ip0[1]); 22 | io_printf("data[0].aval[0] = %x data[1].aval[1] = %x\n", svp0->aval, svp1->aval); 23 | svp0->aval = 0x11111111; 24 | svp1->aval = 0xeeeeeeee; 25 | 26 | ip1 = data[1]; 27 | svp0 = &(ip1[0]); 28 | svp1 = &(ip1[1]); 29 | io_printf("data[1].aval[0] = %x data[1].aval[1] = %x\n", svp0->aval, svp1->aval); 30 | svp0->aval = 0xdddddddd; 31 | svp1->aval = 0x22222222; 32 | } 33 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/fourstate_array.plg: -------------------------------------------------------------------------------- 1 | data[0].aval = 12 2 | data[1].aval = 13 3 | data[0].aval[0] = aaaaaaaa data[1].aval[1] = ffffffff 4 | data[1].aval[0] = cccccccc data[1].aval[1] = bbbbbbbb 5 | array[0] = 0000000c array[1] = 0000000d 6 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/fourstate_array.v: -------------------------------------------------------------------------------- 1 | /* 2 | * simple 4-state array test 3 | */ 4 | module test_fourstate_array; 5 | import "DPI-C" task array_test(input reg [31:0] a [1:0]); 6 | import "DPI-C" task wide_array_test(inout reg [63:0] a [1:0]); 7 | 8 | reg [31:0] array [1:0]; 9 | reg [63:0] wide_array [1:0]; 10 | 11 | initial begin 12 | array[0] = 12; 13 | array[1] = 13; 14 | array_test(array); 15 | 16 | /* now wide array */ 17 | wide_array[0] = 64'hffffffff_aaaaaaaa; 18 | wide_array[1] = 64'hbbbbbbbb_cccccccc; 19 | wide_array_test(wide_array); 20 | $display("array[0] = %x array[1] = %x", array[0], array[1]); 21 | end 22 | endmodule 23 | 24 | 25 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/reals.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void set_array_vals(double *data, int size) 5 | { 6 | int i; 7 | 8 | for (i = 0; i < size; i++) 9 | { 10 | data[i] = i + 0.123456; 11 | } 12 | } 13 | 14 | double mult_real(const double d) 15 | { 16 | return(2*d); 17 | } 18 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/reals.plg: -------------------------------------------------------------------------------- 1 | array[0]=0.246912 2 | array[1]=2.24691 3 | array[2]=4.24691 4 | array[3]=6.24691 5 | array[4]=8.24691 6 | array[5]=10.2469 7 | array[6]=12.2469 8 | array[7]=14.2469 9 | array[8]=16.2469 10 | array[9]=18.2469 11 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/reals.v: -------------------------------------------------------------------------------- 1 | /* 2 | * simple real and real array test 3 | */ 4 | `define SIZE 10 5 | module real_test; 6 | import "DPI-C" task set_array_vals(inout real a [`SIZE-1:0], input int s); 7 | import "DPI-C" function real mult_real(input real i); 8 | 9 | real array [`SIZE:0]; 10 | real twox; 11 | int i; 12 | 13 | initial begin 14 | set_array_vals(array, `SIZE); 15 | for (i = 0; i < `SIZE; i = i+1) 16 | begin 17 | twox = mult_real(array[i]); 18 | $display("array[%0d]=%g", i, twox); 19 | end 20 | end 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/rmlic.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | my $file; 4 | my $i; 5 | my $line; 6 | 7 | $file = 'verilog.log'; 8 | if (@ARGV == 1) 9 | { 10 | $file = $ARGV[0]; 11 | } 12 | 13 | open(FILE, $file) or die "Can't open $file\n"; 14 | open(TMP, '>tmp') or die "Can't open tmp file\n"; 15 | for($i = 0; $i < 3; $i++) 16 | { 17 | $line = ; 18 | } 19 | while() 20 | { 21 | print TMP $_; 22 | } 23 | close TMP; 24 | close FILE; 25 | rename 'tmp', $file; 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/selects.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | /* 5 | * 2-state bit selects 6 | */ 7 | void bitsel_2state_test(svBitVecVal *val, int bi) 8 | { 9 | svBit sb; 10 | 11 | sb = svGetBitselBit(val, bi); 12 | io_printf("2-state val[%d]=%d\n", bi, sb); 13 | /* now zero the bit */ 14 | svPutBitselBit(val, bi, 0); 15 | /* one some bits */ 16 | svPutBitselBit(val, 20, 1); 17 | svPutBitselBit(val, 35, 1); 18 | sb = svGetBitselBit(val, bi); 19 | io_printf("2-state val[%d]=%d\n", bi, sb); 20 | } 21 | 22 | /* 23 | * 4-state bit selects 24 | */ 25 | void bitsel_4state_test(svLogicVecVal *val, int bi) 26 | { 27 | svLogic slb; 28 | 29 | slb = svGetBitselLogic(val, bi); 30 | io_printf("4-state val[%d]=%d\n", bi, slb); 31 | /* now zero the bit */ 32 | svPutBitselLogic(val, bi, 0); 33 | /* one some bits */ 34 | svPutBitselLogic(val, 20, 1); 35 | svPutBitselLogic(val, 35, 1); 36 | slb = svGetBitselLogic(val, bi); 37 | io_printf("4-state val[%d]=%d\n", bi, slb); 38 | } 39 | 40 | /* 41 | * 2-state part selects 42 | */ 43 | void partsel_2state_test(svBitVecVal *val, svBitVecVal *in) 44 | { 45 | svBitVecVal val2; 46 | 47 | svGetPartselBit(val, in, 0, 16); 48 | val2 = 0xffffffff; 49 | svPutPartselBit(val, val2, 20, 8); 50 | } 51 | 52 | /* 53 | * 4-state part selects 54 | */ 55 | void partsel_4state_test(svLogicVecVal *val, svLogicVecVal *in) 56 | { 57 | svLogicVecVal val2; 58 | 59 | svGetPartselLogic(val, in, 0, 16); 60 | val2.aval = 0xffffffff; 61 | val2.bval = 0x0; 62 | svPutPartselLogic(val, val2, 20, 8); 63 | } 64 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/selects.plg: -------------------------------------------------------------------------------- 1 | 2-state val[12]=1 2 | 2-state val[12]=0 3 | bi=0000000000000000000000000000100000000000000100000000000000000000 4 | 2-state val[55]=1 5 | 2-state val[55]=0 6 | bi=0000000000000000000000000000100000000000000100000000000000000000 7 | 4-state val[12]=1 8 | 4-state val[12]=0 9 | ri=0000000000000000000000000000100000000000000100000000000000000000 10 | 4-state val[55]=3 11 | 4-state val[55]=0 12 | ri=0000000000000000000000000000100000000000000100000000000000000000 13 | bi=0000000000000000000000000000000000001111111100001111111111111111 14 | ri=0000000000000000000000000000000000001111111100001111111111111111 15 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/selects.v: -------------------------------------------------------------------------------- 1 | /* 2 | * test built in bit/part select routines 3 | */ 4 | module select_test; 5 | import "DPI-C" task bitsel_2state_test(inout bit [63:0] o, input int bi); 6 | import "DPI-C" task bitsel_4state_test(inout reg [63:0] o, input int bi); 7 | import "DPI-C" task partsel_2state_test(inout bit [63:0] o, input bit [63:0] in); 8 | import "DPI-C" task partsel_4state_test(inout reg [63:0] o, input reg [63:0] in); 9 | bit [63:0] bi, bi2; 10 | reg [63:0] ri, ri2; 11 | 12 | initial begin 13 | /* do 2-state bit selects */ 14 | bi[12] = 1; 15 | bitsel_2state_test(bi, 12); 16 | $display("bi=%b", bi); 17 | bi[55] = 1; 18 | bitsel_2state_test(bi, 55); 19 | $display("bi=%b", bi); 20 | 21 | /* do 4-state bit selects */ 22 | ri = 0; 23 | ri[12] = 1; 24 | bitsel_4state_test(ri, 12); 25 | $display("ri=%b", ri); 26 | ri[55] = 1'bx; 27 | bitsel_4state_test(ri, 55); 28 | $display("ri=%b", ri); 29 | 30 | /* do 2-state part selects */ 31 | bi = 64'h0; 32 | bi2 = 64'hffffffff_ffffffff; 33 | partsel_2state_test(bi, bi2); 34 | $display("bi=%b", bi); 35 | 36 | /* do 4-state part selects */ 37 | ri = 64'h0; 38 | ri2 = 64'hffffffff_ffffffff; 39 | partsel_4state_test(ri, ri2); 40 | $display("ri=%b", ri); 41 | end 42 | endmodule 43 | 44 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_array.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void mult_array(svBitVecVal *ap, int size) 5 | { 6 | int i; 7 | 8 | for (i = 0; i < size; i++) 9 | { 10 | ap[i] *= 10; 11 | } 12 | } 13 | 14 | void wide_array_test(svBitVecVal *data[2]) 15 | { 16 | svBitVecVal *ip0, *ip1; 17 | svBitVecVal *svp0, *svp1; 18 | 19 | ip0 = data[0]; 20 | svp0 = &(ip0[0]); 21 | svp1 = &(ip0[1]); 22 | io_printf("data[0] = %x data[1] = %x\n", *svp0, *svp1); 23 | *svp0 = 0x11111111; 24 | *svp1 = 0xeeeeeeee; 25 | 26 | ip1 = data[1]; 27 | svp0 = &(ip1[0]); 28 | svp1 = &(ip1[1]); 29 | io_printf("data[1] = %x data[1] = %x\n", *svp0, *svp1); 30 | *svp0 = 0xdddddddd; 31 | *svp1 = 0x22222222; 32 | } 33 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_array.plg: -------------------------------------------------------------------------------- 1 | array[0] = 0 2 | array[1] = 10 3 | array[2] = 20 4 | array[3] = 30 5 | array[4] = 40 6 | array[5] = 50 7 | array[6] = 60 8 | array[7] = 70 9 | array[8] = 80 10 | array[9] = 90 11 | data[0] = aaaaaaaa data[1] = ffffffff 12 | data[1] = cccccccc data[1] = bbbbbbbb 13 | array[0] = eeeeeeee11111111 array[1] = 22222222dddddddd 14 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_array.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 2-state array tests 3 | */ 4 | `define SIZE 10 5 | module twostate_array; 6 | import "DPI-C" task mult_array(inout int i[`SIZE-1:0], input int size); 7 | 8 | int array[`SIZE-1:0]; 9 | int i; 10 | 11 | initial begin 12 | 13 | for (i = 0; i < `SIZE; i = i + 1) 14 | begin 15 | array[i] = i; 16 | end 17 | 18 | mult_array(array, `SIZE); 19 | for (i = 0; i < `SIZE; i = i + 1) 20 | begin 21 | $display("array[%0d] = %0d", i, array[i]); 22 | end 23 | 24 | end 25 | endmodule 26 | 27 | 28 | module wide_twostate_array; 29 | import "DPI-C" task wide_array_test(inout bit [63:0] a [1:0]); 30 | 31 | bit [63:0] array [1:0]; 32 | 33 | initial begin 34 | array[0] = 64'hffffffff_aaaaaaaa; 35 | array[1] = 64'hbbbbbbbb_cccccccc; 36 | wide_array_test(array); 37 | $display("array[0] = %x array[1] = %x", array[0], array[1]); 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_functions.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | char byte_test(const char i) 5 | { 6 | io_printf("BYTE = %d\n", i); 7 | return(2*i); 8 | } 9 | 10 | short int shortint_test(const short int i) 11 | { 12 | io_printf("SHORT INT = %d\n", i); 13 | return(2*i); 14 | } 15 | 16 | int int_test(const int i) 17 | { 18 | io_printf("INT = %d\n", i); 19 | return(2*i); 20 | } 21 | 22 | double real_test(const double i) 23 | { 24 | io_printf("REAL = %g\n", i); 25 | return(2.123*i); 26 | } 27 | 28 | svBit bit_test(const svBit i) 29 | { 30 | io_printf("BIT = %d\n", i); 31 | return(0); 32 | } 33 | 34 | long long int longint_test(const long long int i) 35 | { 36 | io_printf("LONG LONG INT = %llx\n", i); 37 | return(0xccccccccddddddddULL); 38 | } 39 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_functions.plg: -------------------------------------------------------------------------------- 1 | BYTE = 10 2 | byte_i=10 byte_o=20 3 | SHORT INT = 11 4 | short_i=11 short_o=22 5 | INT = 22 6 | int_i=22 int_o=44 7 | REAL = 123.5 8 | real_i=123.5 real_o=262.191 9 | BIT = 1 10 | bit_i=1 bit_o=0 11 | LONG LONG INT = aaaaaaaabbbbbbbb 12 | long_i=aaaaaaaabbbbbbbb long_o=ccccccccdddddddd 13 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_functions.v: -------------------------------------------------------------------------------- 1 | /* 2 | * simple 2-state function assigns 3 | */ 4 | module test_2state_functions; 5 | //'void function' not yet supported - use tasks instead 6 | import "DPI-C" function byte byte_test(input byte i); 7 | import "DPI-C" function shortint shortint_test(input shortint i); 8 | import "DPI-C" function int int_test(input int i); 9 | import "DPI-C" function real real_test(input real i); 10 | import "DPI-C" function bit bit_test(input bit i); 11 | import "DPI-C" function longint longint_test(input longint i); 12 | 13 | byte byte_i, byte_o; 14 | shortint short_i, short_o; 15 | int int_i, int_o; 16 | real real_i, real_o; 17 | bit bit_i, bit_o; 18 | longint long_i, long_o; 19 | 20 | initial begin 21 | byte_i = 10; 22 | byte_o = byte_test(byte_i); 23 | $display("byte_i=%0d byte_o=%0d", byte_i, byte_o); 24 | 25 | short_i = 11; 26 | short_o = shortint_test(short_i); 27 | $display("short_i=%0d short_o=%0d", short_i, short_o); 28 | 29 | int_i = 22; 30 | int_o = int_test(int_i); 31 | $display("int_i=%0d int_o=%0d", int_i, int_o); 32 | 33 | real_i = 123.5; 34 | real_o = real_test(real_i); 35 | $display("real_i=%g real_o=%g", real_i, real_o); 36 | 37 | bit_i = 1; 38 | bit_o = bit_test(bit_i); 39 | $display("bit_i=%g bit_o=%g", bit_i, bit_o); 40 | 41 | long_i = 64'haaaaaaaa_bbbbbbbb; 42 | long_o = longint_test(long_i); 43 | $display("long_i=%0x long_o=%0x", long_i, long_o); 44 | end 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_tasks.c: -------------------------------------------------------------------------------- 1 | #include "svdpi.h" 2 | #include "veriuser.h" 3 | 4 | void byte_test(const char i, char *o) 5 | { 6 | io_printf("BYTE = %d\n", i); 7 | *o = 2*i; 8 | } 9 | 10 | void shortint_test(const short int i, short int *o) 11 | { 12 | io_printf("SHORT INT = %d\n", i); 13 | *o = 2*i; 14 | } 15 | 16 | void int_test(const int i, int *o) 17 | { 18 | io_printf("INT = %d\n", i); 19 | *o = 2*i; 20 | } 21 | 22 | void real_test(const double i, double *o) 23 | { 24 | io_printf("REAL = %g\n", i); 25 | *o = 2.123*i; 26 | } 27 | 28 | void bit_test(const svBit i, svBit *o) 29 | { 30 | io_printf("BIT = %d\n", i); 31 | *o = 0; 32 | } 33 | 34 | void bit_vec_test(const svBitVecVal *i, svBitVecVal *o) 35 | { 36 | io_printf("BIT VECTOR = %d\n", *i); 37 | *o = 2*(*i); 38 | } 39 | 40 | void bit_vec_wide_test(const svBitVecVal *i, svBitVecVal *o) 41 | { 42 | io_printf("BIT VECTOR WIDE = %x %x %x %x\n", i[3], i[2], i[1], i[0]); 43 | o[3] = 0xaaaaaaaa; 44 | o[2] = 0xbbbbbbbb; 45 | o[1] = 0xcccccccc; 46 | o[0] = 0xdddddddd; 47 | } 48 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_tasks.plg: -------------------------------------------------------------------------------- 1 | BYTE = 10 2 | byte_i=10 byte_o=20 3 | SHORT INT = 11 4 | short_i=11 short_o=22 5 | INT = 22 6 | int_i=22 int_o=44 7 | REAL = 123.5 8 | real_i=123.5 real_o=262.191 9 | BIT = 1 10 | bit_i=1 bit_o=0 11 | BIT VECTOR = 30 12 | bitv_i=30 bitv_o=60 13 | BIT VECTOR WIDE = 11111111 22222222 33333333 44444444 14 | bitvw_i=11111111222222223333333344444444 bitv_o=aaaaaaaabbbbbbbbccccccccdddddddd 15 | -------------------------------------------------------------------------------- /tests_and_examples/examples.dpi/twostate_tasks.v: -------------------------------------------------------------------------------- 1 | /* 2 | * simple 2-state tasks input/outputs 3 | */ 4 | module test_2state_tasks; 5 | import "DPI-C" task byte_test(input byte i, output byte o); 6 | import "DPI-C" task shortint_test(input shortint i, output shortint o); 7 | import "DPI-C" task int_test(input int i, output int o); 8 | import "DPI-C" task real_test(input real i, output real o); 9 | import "DPI-C" task bit_test(input bit i, output bit o); 10 | import "DPI-C" task bit_vec_test(input bit [7:0] i, output bit [7:0] o); 11 | import "DPI-C" task bit_vec_wide_test(input bit [127:0] i, output bit [127:0] o); 12 | 13 | byte byte_i, byte_o; 14 | shortint short_i, short_o; 15 | int int_i, int_o; 16 | real real_i, real_o; 17 | bit bit_i, bit_o; 18 | bit [7:0] bitv_i, bitv_o; 19 | bit [127:0] bitvw_i, bitvw_o; 20 | 21 | initial begin 22 | byte_i = 10; 23 | byte_test(byte_i, byte_o); 24 | $display("byte_i=%0d byte_o=%0d", byte_i, byte_o); 25 | 26 | short_i = 11; 27 | shortint_test(short_i, short_o); 28 | $display("short_i=%0d short_o=%0d", short_i, short_o); 29 | 30 | int_i = 22; 31 | int_test(int_i, int_o); 32 | $display("int_i=%0d int_o=%0d", int_i, int_o); 33 | 34 | real_i = 123.5; 35 | real_test(real_i, real_o); 36 | $display("real_i=%g real_o=%g", real_i, real_o); 37 | 38 | bit_i = 1; 39 | bit_test(bit_i, bit_o); 40 | $display("bit_i=%g bit_o=%g", bit_i, bit_o); 41 | 42 | bitv_i = 30; 43 | bit_vec_test(bitv_i, bitv_o); 44 | $display("bitv_i=%0d bitv_o=%0d", bitv_i, bitv_o); 45 | 46 | bitvw_i = 128'h11111111_22222222_33333333_44444444; 47 | bit_vec_wide_test(bitvw_i, bitvw_o); 48 | $display("bitvw_i=%x bitv_o=%x", bitvw_i, bitvw_o); 49 | end 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/README: -------------------------------------------------------------------------------- 1 | To test PLI 1.0 tf_ interface: 2 | 3 | BEFORE STARTING: 4 | Run the shell script in install.test directory to verify correct build. 5 | 6 | When compiling a design for use with the PLI you may need to compile with 7 | +acc+[level] command. This option compiles with the following levels of 8 | PLI access: 9 | 10 | +acc+1 or +acc 11 | Enable all PLI capabilities except value change callbacks and 12 | delay annotation. 13 | +acc+2 14 | All features above plus value change callbacks. 15 | +acc+3 16 | All features above plus module path delay. 17 | +acc+4 18 | All features above plus gate delay annotation. 19 | 20 | We are working on VCS style .tab file for more specific access options to 21 | increase peformance when using the PLI. 22 | 23 | HOW TO RUN THE TEST SCRIPT 24 | 25 | 1) Run the shell script inst_pli.sh. Various compiler and Verilog 26 | output messages will be printed but there should be no diff command 27 | differences printed. 28 | 29 | By convention makefile.lnx assumes this test is run in release 30 | directory tree with include files in pli_incs 2 directory levels up 31 | and CVC binary is in bin directory also 2 levels up. 32 | 33 | The commands to run CVC with dynamically loaded user PLI library 34 | explicitly access the user .so library in this directory. For your 35 | PLI libraries, it is better to set the LD_LIBRARY_PATH environment 36 | variables so explicit "./" is not needed 37 | 38 | 2) After completing the test, run clean.sh to remove work files. 39 | The inst_pli.sh script removes each PLI library .so dynamic library after 40 | running the test that uses it so unless something went wrong, you 41 | do not need to run clean.sh. 42 | 43 | 3) Use makefile.lnx as a template for your PLI models. 44 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/clean.sh: -------------------------------------------------------------------------------- 1 | rm probe tfclk plimfil plimfil2 *.o *.dylib verilog.log 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/makefile.lnx32: -------------------------------------------------------------------------------- 1 | 2 | # could add to CFLAGS to turn on warnings if you are using gcc 3 | WARNS=-Wall 4 | 5 | # change path if not running test from installed directory location 6 | INCS=-I../../pli_incs 7 | # maybe want -O and/or -g, if you use -O use -march= 8 | CFLAGS= -fPIC -Wall -m32 $(INCS) 9 | LFLAGS= -G -shared -export-dynamic -melf_i386 10 | 11 | # change to your compiler 12 | CC=gcc 13 | 14 | probe.o: probe.c 15 | $(CC) $(CFLAGS) -c probe.c 16 | 17 | tfclk.o: tfclk.c 18 | $(CC) $(CFLAGS) -c tfclk.c 19 | 20 | plimfil.o: plimfil.c 21 | $(CC) $(CFLAGS) -c plimfil.c 22 | 23 | plimfil2.o: plimfil2.c 24 | $(CC) $(CFLAGS) -c plimfil2.c 25 | 26 | # make rules for dynamic libaries 27 | probe.so: probe.o 28 | $(LD) $(LFLAGS) probe.o -o probe.so 29 | 30 | tfclk.so: tfclk.o 31 | $(LD) $(LFLAGS) tfclk.o $(LFLAGS) -o tfclk.so 32 | 33 | plimfil.so: plimfil.o 34 | $(LD) $(LFLAGS) plimfil.o $(LFLAGS) -o plimfil.so 35 | 36 | plimfil2.so: plimfil2.o 37 | $(LD) $(LFLAGS) plimfil2.o $(LFLAGS) -o plimfil2.so 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/makefile.lnx64: -------------------------------------------------------------------------------- 1 | 2 | # could add to CFLAGS to turn on warnings if you are using gcc 3 | WARNS=-Wall 4 | 5 | # change path if not running test from installed directory location 6 | INCS=-I../../pli_incs 7 | # maybe want -O and/or -g, if you use -O use -march= 8 | CFLAGS= -fPIC -Wall $(INCS) 9 | LFLAGS= -G -shared -export-dynamic 10 | 11 | # change to your compiler 12 | CC=gcc 13 | 14 | probe.o: probe.c 15 | $(CC) $(CFLAGS) -c probe.c 16 | 17 | tfclk.o: tfclk.c 18 | $(CC) $(CFLAGS) -c tfclk.c 19 | 20 | plimfil.o: plimfil.c 21 | $(CC) $(CFLAGS) -c plimfil.c 22 | 23 | plimfil2.o: plimfil2.c 24 | $(CC) $(CFLAGS) -c plimfil2.c 25 | 26 | # make rules for dynamic libaries 27 | probe.so: probe.o 28 | $(LD) $(LFLAGS) probe.o -o probe.so 29 | 30 | tfclk.so: tfclk.o 31 | $(LD) $(LFLAGS) tfclk.o $(LFLAGS) -o tfclk.so 32 | 33 | plimfil.so: plimfil.o 34 | $(LD) $(LFLAGS) plimfil.o $(LFLAGS) -o plimfil.so 35 | 36 | plimfil2.so: plimfil2.o 37 | $(LD) $(LFLAGS) plimfil2.o $(LFLAGS) -o plimfil2.so 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/plimfil.plg: -------------------------------------------------------------------------------- 1 | writing filled memory values: 2 | 1: 0000000000000000000000000000000000000000000000000000000000000000000 3 | 2: 1111111111111111111111111111111111111111111111111111111111111111111 4 | 3: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 5 | 4: zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz 6 | 5: 0101010101010101010101010101010101010101010101010101010101010101010 7 | 6: x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x 8 | 7: 1010101010101010101010101010101010101010101010101010101010101010101 9 | 8: 1100110011110011001111001100111100110011110011001111001100111100110 10 | 9: z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z1z 11 | 10: 01xz01xz0101xz01xz0101xz01xz0101xz01xz0101xz01xz0101xz01xz0101xz01x 12 | 13 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/plimfil.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | reg [66:0] mem1[1:10]; 3 | 4 | initial 5 | begin 6 | fillmem; 7 | $display("writing filled memory values:"); 8 | writemem; 9 | end 10 | 11 | task fillmem; 12 | integer i; 13 | begin 14 | if ($pli_setupmemfill(10, 67) == 0) $finish; 15 | for (i = 1; i <= 10; i = i + 1) 16 | begin 17 | if ($pli_memfill(mem1[i], i) == 0) $finish; 18 | // notice must delay after call because value of i cannot change 19 | // but if mem fill used extension tf_strputp routine not needed 20 | // if you do not need portability, tf_strputp is better 21 | #10; 22 | end 23 | end 24 | endtask 25 | 26 | task writemem; 27 | integer i; 28 | begin 29 | for (i = 1; i <= 10; i = i + 1) $display("%0d: %b", i, mem1[i]); 30 | $write("\n"); 31 | end 32 | endtask 33 | endmodule 34 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/plimfil2.plg: -------------------------------------------------------------------------------- 1 | ** WARN** [1404] PLI1 - passing memory (array) - to tf_nodeinfo (via $pli_memfil2) is inefficient better to use VPI or DPI instead. 2 | writing filled memory values: 3 | 1: 0 4 | 2: 1 5 | 3: 1024 6 | 4: 16383 7 | 5: 12345 8 | 9 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/plimfil2.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | reg [31:0] mem2[1:5]; 3 | 4 | initial 5 | begin 6 | fillmem; 7 | $display("writing filled memory values:"); 8 | writemem; 9 | end 10 | 11 | task fillmem; 12 | integer i; 13 | begin 14 | if ($pli_setupmemfil2(5, 32) == 0) $finish; 15 | // since propagatep assignment immediate evaluate of drivers 16 | // do not need delay here 17 | for (i = 1; i <= 5; i = i + 1) 18 | begin 19 | // only need 2nd index argument for checking */ 20 | if ($pli_memfil2(mem2[i], i) == 0) $finish; 21 | end 22 | end 23 | endtask 24 | 25 | task writemem; 26 | integer i; 27 | begin 28 | for (i = 1; i <= 5; i = i + 1) $display("%0d: %0d", i, mem2[i]); 29 | $write("\n"); 30 | end 31 | endtask 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/probe.v: -------------------------------------------------------------------------------- 1 | module probe; 2 | reg [31:0] a, b, c; 3 | 4 | initial 5 | begin 6 | $setup_values(a, b, c); 7 | #10 a = 3; c = 1; 8 | #10 b = 3; c = 2; 9 | #10 c = 3; 10 | #10 a = 33; c = 9; 11 | #10 b = 44; c = 22; 12 | #10 a = 30; 13 | #10 a = 50; b = 200; c = 0; 14 | #10 a = 50; c = 99; 15 | #10 b = 90; c = 99; 16 | #10 b = 11; c = 19; 17 | end 18 | // do the flash 19 | always @(c) $flash_values($stime/2); 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/rmlic.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | my $file; 4 | my $i; 5 | my $line; 6 | 7 | $file = 'verilog.log'; 8 | if (@ARGV == 1) 9 | { 10 | $file = $ARGV[0]; 11 | } 12 | 13 | open(FILE, $file) or die "Can't open $file\n"; 14 | open(TMP, '>tmp') or die "Can't open tmp file\n"; 15 | for($i = 0; $i < 3; $i++) 16 | { 17 | $line = ; 18 | } 19 | while() 20 | { 21 | print TMP $_; 22 | } 23 | close TMP; 24 | close FILE; 25 | rename 'tmp', $file; 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/testmem.dat: -------------------------------------------------------------------------------- 1 | 0000000000_0000000000_0000000000_0000000000_0000000000_0000000000_0000000 2 | 1111111111_1111111111_1111111111_1111111111_1111111111_1111111111_1111111 3 | xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxx 4 | zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzz 5 | 0101010101_0101010101_0101010101_0101010101_0101010101_0101010101_0101010 6 | x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x 7 | 1010101010_1010101010_1010101010_1010101010_1010101010_1010101010_1010101 8 | 1100110011_1100110011_1100110011_1100110011_1100110011_1100110011_1100110 9 | z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z 10 | 01xz01xz01_01xz01xz01_01xz01xz01_01xz01xz01_01xz01xz01_01xz01xz01_01xz01x 11 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/testmem2.dat: -------------------------------------------------------------------------------- 1 | 0 2 | 1 3 | 1024 4 | 16383 5 | 12345 6 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/tfclk.plg: -------------------------------------------------------------------------------- 1 | 0 x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 2 | 20 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 3 | 120 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 4 | 220 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 5 | 320 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 6 | 420 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 7 | 520 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 8 | 620 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 9 | 720 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 10 | 820 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 11 | 920 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 12 | clock turned off at 1020 13 | 1220 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx 14 | 1320 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx 15 | 1420 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx 16 | 1520 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx 17 | 1620 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx 18 | 1720 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx 19 | 1820 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx 20 | 1920 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx 21 | 2020 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx 22 | 2120 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx 23 | -------------------------------------------------------------------------------- /tests_and_examples/examples.tf/tfclk.v: -------------------------------------------------------------------------------- 1 | 2 | `define CLK_PER 100 3 | 4 | module top; 5 | setdel i1(); 6 | endmodule 7 | 8 | module setdel; 9 | reg clk; 10 | reg [31:0] clk2; 11 | time t; 12 | initial 13 | begin 14 | $monitor($time,, "%b %b", clk, clk2); 15 | #20 $tfclk(clk); 16 | #1000 t = $tfclkoff; 17 | $display("clock turned off at %t", t); 18 | #200 $tfclk(clk2[2]); 19 | #1000 $finish; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/async.plg: -------------------------------------------------------------------------------- 1 | 0 z=x, a=x 2 | 10 z=x, a=z 3 | 20 z=x, a=1 4 | 25 z=0, a=1 5 | 30 z=0, a=0 6 | 35 z=1, a=0 7 | 40 z=1, a=1 8 | 41 z=1, a=0 9 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/async.v: -------------------------------------------------------------------------------- 1 | /* 2 | * async driven not gate cpu PLI model .v file 3 | */ 4 | module top; 5 | wire z; 6 | reg a; 7 | initial 8 | begin 9 | $monitor($stime,, "z=%b, a=%b", z, a); 10 | $pli_not(z, a); 11 | end 12 | initial 13 | begin 14 | #10 a = 1'bz; 15 | #10 a = 1; 16 | #10 a = 0; 17 | #10 a = 1; 18 | // notice glitch that PLI model maybe should catch 19 | #1 a = 0; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/cacatmd1.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | wire [31:0] w; 3 | wire [15:0] a, b, c; 4 | reg [31:0] w_r; 5 | 6 | assign {a[7:2], b, c[9:3]} = w; 7 | assign w = w_r; 8 | assign w = 32'hzzzzzzzz; 9 | assign b[1] = w[9]; 10 | 11 | initial 12 | begin 13 | $monitor($stime,, "a=%b, b=%b, c=%b, w=%h", a, b, c, w); 14 | #10 w_r = 0; 15 | #10 w_r = 32'hffffffff; 16 | #10 w_r = 32'haaaaaaaa; 17 | #10 w_r = 32'h55555555; 18 | #10 w_r = 32'hffffffff; 19 | #10 w_r = 0; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/clean.sh: -------------------------------------------------------------------------------- 1 | rm *.o *.dylib verilog.log fff9 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/dfpsetd.plg: -------------------------------------------------------------------------------- 1 | ... PLI delay setting complete. 2 | 0 preset=x clear=x q=x qbar=x 3 | 100 preset=0 clear=1 q=x qbar=x 4 | 110 preset=0 clear=1 q=1 qbar=x 5 | 116 preset=0 clear=1 q=1 qbar=0 6 | 200 preset=1 clear=1 q=1 qbar=0 7 | 300 preset=1 clear=0 q=1 qbar=0 8 | 306 preset=1 clear=0 q=1 qbar=1 9 | 312 preset=1 clear=0 q=0 qbar=1 10 | 400 preset=1 clear=1 q=0 qbar=1 11 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/dfpsetd.v: -------------------------------------------------------------------------------- 1 | module ffnand_test; 2 | wire q, qbar; 3 | reg preset, clear; 4 | 5 | parameter d = 10; 6 | 7 | ffnand ff1(q, qbar, preset, clear); 8 | initial 9 | begin 10 | #d preset = 0; clear = 1; 11 | #d preset = 1; 12 | #d clear = 0; 13 | #d clear = 1; 14 | end 15 | initial $monitor($time,, "preset=%b clear=%b q=%b qbar=%b", 16 | preset, clear,q, qbar); 17 | endmodule 18 | 19 | module ffnand(ffq, ffqbar, ffpreset, ffclear); 20 | output ffq, ffqbar; 21 | input ffpreset, ffclear; 22 | 23 | nand #(1, 1) q1(ffq, ffqbar, ffpreset), q2(ffqbar, ffq, ffclear); 24 | specify 25 | specparam pr = 5; 26 | specparam pf = 5; 27 | // notice error because no path delay to ffqbar 28 | (ffpreset => ffq) = (pr, pf); 29 | (ffclear => ffq) = (pr, pf); 30 | endspecify 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/findcaus.plg: -------------------------------------------------------------------------------- 1 | module iterator has size 1. 2 | ... processing instance task10 3 | init/always iterator has size 4. 4 | ... processing initial 5 | ... processing 3 type. 6 | ... processing initial 7 | ... processing 4 type. 8 | block stmt iterator has size 18. 9 | ... processing 3 type. 10 | ... processing 11 type. 11 | ... processing 3 type. 12 | ... processing 3 type. 13 | ... processing 3 type. 14 | ... processing 3 type. 15 | ... processing 57 type. 16 | ... processing 60 type. 17 | ... processing 57 type. 18 | ... processing 3 type. 19 | ... processing 3 type. 20 | ... processing 14 type. 21 | ... processing 60 type. 22 | ... processing 57 type. 23 | ... processing 3 type. 24 | ... processing 3 type. 25 | ... processing 60 type. 26 | ... processing 57 type. 27 | ... processing initial 28 | ... processing 4 type. 29 | block stmt iterator has size 2. 30 | ... processing 13 type. 31 | ... processing 11 type. 32 | ...processing always 33 | ... processing 4 type. 34 | block stmt iterator has size 1. 35 | ... processing 13 type. 36 | There were 1 total cause statements in top modules. 37 | 10 start x: ffffffff y: 1 count: 0 38 | 10 t1 started 39 | 30 t1 finished 40 | 30 return x: 00000000 y: 0 count: 1 41 | 30 t1 started 42 | 35 return x: 00000000 y: 0 count: 1 43 | 35 t1 started 44 | 55 t1 finished 45 | 55 return x: 00000002 y: 0 count: 2 46 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/opt_vacbtst.inp: -------------------------------------------------------------------------------- 1 | // remove C[number]> prefixes and output messages from log file 2 | . 3 | $remove_all_actions; 4 | $reg_all_actions; 5 | $remove_all_actions; 6 | $reg_all_actions; 7 | $display("---> reset %d times.\n", $reset_count); 8 | if ($reset_count < 3) $reset; else; 9 | $remove_all_actions; 10 | $reg_all_actions; 11 | $remove_all_actions; 12 | $reg_all_actions; 13 | . 14 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/opt_vacbtst.plg: -------------------------------------------------------------------------------- 1 | *** at end of compilation callback *** 2 | *** entering interactive mode callback *** 3 | C1 > // remove C[number]> prefixes and output messages from log file 4 | C1 > . 5 | *** exiting interactive mode callback *** 6 | 10 start x: ffffffff y: 1 count: 0 7 | 10 t1 started 8 | 30 t1 finished 9 | 30 return x: 00000000 y: 0 count: 1 10 | 30 t1 started 11 | 35 return x: 00000000 y: 0 count: 1 12 | 35 t1 started 13 | 55 t1 finished 14 | 55 return x: 00000002 y: 0 count: 2 15 | *** at end of simulation callback *** 16 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/rmlic.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | my $file; 4 | my $i; 5 | my $line; 6 | 7 | $file = 'verilog.log'; 8 | if (@ARGV == 1) 9 | { 10 | $file = $ARGV[0]; 11 | } 12 | 13 | open(FILE, $file) or die "Can't open $file\n"; 14 | open(TMP, '>tmp') or die "Can't open tmp file\n"; 15 | for($i = 0; $i < 3; $i++) 16 | { 17 | $line = ; 18 | } 19 | while() 20 | { 21 | print TMP $_; 22 | } 23 | close TMP; 24 | close FILE; 25 | rename 'tmp', $file; 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/task10.v: -------------------------------------------------------------------------------- 1 | module task10; 2 | reg [31:0] aa, x; 3 | reg bb, y, nochg; 4 | integer count; 5 | initial count = 0; 6 | 7 | event e1; 8 | 9 | task t1; 10 | input [31:0] a; 11 | input b; 12 | output [31:0] c; 13 | output d; 14 | reg d; 15 | reg [31:0] c; 16 | begin 17 | $display($stime, " t1 started"); 18 | 19 | d = b; 20 | #10 c = a; 21 | #10 count = count + 1; 22 | $display($stime, " t1 finished"); 23 | 24 | end 25 | endtask 26 | 27 | initial begin 28 | x = 31'hxxxxxxxx; 29 | #10; 30 | aa = 0; 31 | bb = 0; 32 | x = -1; 33 | y = 1; 34 | $display($stime," start x: %x y: %x count: %0d", x, y, count); 35 | t1(aa, bb, x, y); 36 | $display($stime," return x: %x y: %x count: %0d", x, y, count); 37 | 38 | aa = aa + 1; 39 | bb = ~bb; 40 | ->e1; 41 | t1(aa, bb, x, y); 42 | $display($stime," return x: %x y: %x count: %0d", x, y, count); 43 | 44 | aa = aa + 1; 45 | bb = ~bb; 46 | t1(aa, bb, x, y); 47 | $display($stime," return x: %x y: %x count: %0d", x, y, count); 48 | 49 | end 50 | 51 | initial begin 52 | @e1 ; 53 | #5 disable t1; 54 | end 55 | 56 | always begin @nochg ; end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/timtst03.v: -------------------------------------------------------------------------------- 1 | `timescale 10 ns / 1 ns 2 | module test; 3 | reg set; 4 | wire a, b, c; 5 | parameter p = 1.55; 6 | 7 | and #p i1(a, b, c); 8 | 9 | initial 10 | begin 11 | $monitor($realtime,,"set=", set); 12 | #p set = 0; 13 | #p set = 1; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vacbtst.inp: -------------------------------------------------------------------------------- 1 | // remove C[number]> prefixes and output messages from log file 2 | , 3 | $remove_all_actions; 4 | , 5 | $reg_all_actions; 6 | , 7 | $remove_all_actions; 8 | , 9 | $reg_all_actions; 10 | $display("---> reset %d times.\n", $reset_count); 11 | if ($reset_count < 3) $reset; else; 12 | , 13 | $remove_all_actions; 14 | , 15 | $reg_all_actions; 16 | , 17 | $remove_all_actions; 18 | , 19 | $reg_all_actions; 20 | . 21 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vconta1.plg: -------------------------------------------------------------------------------- 1 | There are 1 top level modules. 2 | --- processing a concatenate: 3 | Part select xx.a index 7 processed. 4 | Part select xx.a index 6 processed. 5 | Part select xx.a index 5 processed. 6 | Part select xx.a index 4 processed. 7 | Part select xx.a index 3 processed. 8 | Part select xx.a index 2 processed. 9 | Variable xx.b processed. 10 | Part select xx.c index 9 processed. 11 | Part select xx.c index 8 processed. 12 | Part select xx.c index 7 processed. 13 | Part select xx.c index 6 processed. 14 | Part select xx.c index 5 processed. 15 | Part select xx.c index 4 processed. 16 | Part select xx.c index 3 processed. 17 | === end of concatenate 18 | Variable xx.w processed. 19 | Variable xx.w processed. 20 | Variable xx.w_r processed. 21 | Variable xx.w processed. 22 | Bit select xx.b index 1 processed. 23 | Bit select xx.w index 9 processed. 24 | >>> All instances processed - continuing with simulation. 25 | 0 a=zzzzzzzzxxxxxxzz, b=xxxxxxxxxxxxxxxx, c=zzzzzzxxxxxxxzzz, w=xxxxxxxx 26 | 10 a=zzzzzzzz000000zz, b=0000000000000000, c=zzzzzz0000000zzz, w=00000000 27 | 20 a=zzzzzzzz111111zz, b=1111111111111111, c=zzzzzz1111111zzz, w=ffffffff 28 | 30 a=zzzzzzzz010101zz, b=01010101010101x1, c=zzzzzz0101010zzz, w=aaaaaaaa 29 | 40 a=zzzzzzzz101010zz, b=10101010101010x0, c=zzzzzz1010101zzz, w=55555555 30 | 50 a=zzzzzzzz111111zz, b=1111111111111111, c=zzzzzz1111111zzz, w=ffffffff 31 | 60 a=zzzzzzzz000000zz, b=0000000000000000, c=zzzzzz0000000zzz, w=00000000 32 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vfopen1.plg: -------------------------------------------------------------------------------- 1 | ... writing to file vpifout.fil. 2 | tmp_channel 4 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vfopen1.v: -------------------------------------------------------------------------------- 1 | module test; 2 | 3 | reg clk; 4 | 5 | integer tmp_channel; 6 | initial 7 | begin 8 | clk = 0; 9 | 10 | #2000 tmp_channel = $vpi_fopen("vpifout.fil"); 11 | $display("... writing to file vpifout.fil."); 12 | $fdisplay(tmp_channel | 5,"tmp_channel %d",tmp_channel); 13 | $fclose(tmp_channel); 14 | 15 | #4000 $finish; 16 | 17 | end 18 | 19 | always 20 | begin 21 | #1000 clk = ~clk; 22 | end 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vfopen2.plg: -------------------------------------------------------------------------------- 1 | writing to vpitout.fil. 2 | tmp_channel 4 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vfopen2.v: -------------------------------------------------------------------------------- 1 | module test; 2 | 3 | reg clk; 4 | 5 | integer tmp_channel; 6 | initial 7 | begin 8 | clk = 0; 9 | 10 | #2000 $vpi_fopen_task("vpitout.fil", tmp_channel); 11 | $display("writing to vpitout.fil."); 12 | $fdisplay(tmp_channel | 5,"tmp_channel %d",tmp_channel); 13 | $fclose(tmp_channel); 14 | 15 | #4000 $finish; 16 | 17 | end 18 | 19 | always 20 | begin 21 | #1000 clk = ~clk; 22 | end 23 | 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vhelbad.plg: -------------------------------------------------------------------------------- 1 | ... executing vpi_ systf compiletf routine. 2 | ... executing EndOfCompile callback for checking. 3 | ** ERR: $hello PLI 2.0 can not access systf call handle 4 | 1840: vpiPLI error (level 3) at ***none*(0): 5 | vpi_handle with vpiSysTfCall not called from inside vpi_ systf callback 6 | ** ERR: vpi_iterate error: 7 | 1854: vpiPLI error (level 3) at ***none*(0): 8 | vpi_iterate type vpiArgument passed illegal NULL handle 9 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vhelbad.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | integer i; 3 | real r; 4 | 5 | initial 6 | begin 7 | $hello(3); 8 | i = $stime; 9 | /* r = $realfhello; */ 10 | $display("done with PLI 2.0 calls returned i=%0d and r=%0g", i, r); 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vhello1.plg: -------------------------------------------------------------------------------- 1 | hello world 2 | **ERR: $hello PLI 2.0 task called with 1 arguments but none allowed 3 | done with PLI 2.0 calls returned i=0 and r=0 4 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vhello1.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | integer i; 3 | real r; 4 | 5 | initial 6 | begin 7 | $hello; 8 | i = $stime; 9 | $hello(i); 10 | $display("done with PLI 2.0 calls returned i=%0d and r=%0g", i, r); 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vhello2.plg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | vpi_ system task $hello registered. 3 | vpi_ system function $realfhello (ret. type 2) registered. 4 | -------------------------------------------------------------- 5 | hello world 6 | hello world 7 | done with PLI 2.0 calls returned i=0 and r=19 8 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vhello2.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | integer i; 3 | real r; 4 | 5 | initial 6 | begin 7 | $hello; 8 | r = $realfhello; 9 | i = $stime; 10 | $display("done with PLI 2.0 calls returned i=%0d and r=%0g", i, r); 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vpifout.fil: -------------------------------------------------------------------------------- 1 | tmp_channel 4 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vpifout.xfl: -------------------------------------------------------------------------------- 1 | tmp_channel 4 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vpiret.m01: -------------------------------------------------------------------------------- 1 | 2 | Why do vpi_ do call back registered functions return 'int' instead of 'void' 3 | 4 | It seems to me the vpi_ simulation related registered call back function 5 | in the s_cb_data type (LRM section 23.34, p. 584) and system task or 6 | function call back routines in s_vpi_systf_data (LRM section 23.25, p. 589) 7 | should have type "void returning function" instead of "int returning 8 | function". And in fact the example on page 588 is code this way and 9 | I think wrong since a void returning call back function 'get_current_cputime' 10 | is registered in the example. 11 | 12 | I discovered this trying to run some vpi_ code through a lint program. 13 | In order to take advantage of the checking ability of ansii C, registered 14 | functions must be declared as int returning and must explicitly return 15 | some kind of dummy value (probably 0). 16 | 17 | In addition to the advantage of allowing lint warning checking changing 18 | the fields to void returning allows optimizing C compilers to 19 | produce much better code. 20 | 21 | The s_vpi_vlog_info type defined in vpi_user.h for defining start up 22 | call back routines does require void returning routines. 23 | 24 | I could not find any use for either s_cb_data call back or s_vpi_systf_data 25 | routine int return value in the LRM. Is there something I am missing on 26 | this? Since the s_vpi_time type is already being changed, now might be 27 | a good time to also change the cb_rtn declarations. 28 | /Steve 29 | 30 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vpitout.fil: -------------------------------------------------------------------------------- 1 | tmp_channel 4 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vpitout.xfl: -------------------------------------------------------------------------------- 1 | tmp_channel 4 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vprtchg.plg: -------------------------------------------------------------------------------- 1 | There are 1 top level modules. 2 | >>> All instances processed - continuing with simulation. 3 | --> now 0: task10.count=00000000000000000000000000000000. 4 | --> now 0: task10.x=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx. 5 | --> now 10: task10.aa=00000000000000000000000000000000. 6 | --> now 10: task10.bb=0. 7 | --> now 10: task10.x=11111111111111111111111111111111. 8 | --> now 10: task10.y=1. 9 | 10 start x: ffffffff y: 1 count: 0 10 | --> now 10: task10.t1.a=00000000000000000000000000000000. 11 | --> now 10: task10.t1.b=0. 12 | 10 t1 started 13 | --> now 10: task10.t1.d=0. 14 | --> now 20: task10.t1.c=00000000000000000000000000000000. 15 | --> now 30: task10.count=00000000000000000000000000000001. 16 | 30 t1 finished 17 | --> now 30: task10.x=00000000000000000000000000000000. 18 | --> now 30: task10.y=0. 19 | 30 return x: 00000000 y: 0 count: 1 20 | --> now 30: task10.aa=00000000000000000000000000000001. 21 | --> now 30: task10.bb=1. 22 | --> now 30: task10.t1.a=00000000000000000000000000000001. 23 | --> now 30: task10.t1.b=1. 24 | 30 t1 started 25 | --> now 30: task10.t1.d=1. 26 | 35 return x: 00000000 y: 0 count: 1 27 | --> now 35: task10.aa=00000000000000000000000000000010. 28 | --> now 35: task10.bb=0. 29 | --> now 35: task10.t1.a=00000000000000000000000000000010. 30 | --> now 35: task10.t1.b=0. 31 | 35 t1 started 32 | --> now 35: task10.t1.d=0. 33 | --> now 45: task10.t1.c=00000000000000000000000000000010. 34 | --> now 55: task10.count=00000000000000000000000000000010. 35 | 55 t1 finished 36 | --> now 55: task10.x=00000000000000000000000000000010. 37 | 55 return x: 00000002 y: 0 count: 2 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vprtchg2.plg: -------------------------------------------------------------------------------- 1 | There are 1 top level modules. 2 | >>> All instances processed - continuing with simulation. 3 | --> now 0: task10.count changed to 0. 4 | --> now 0: task10.x changed to (av=7fffffff,bv=7fffffff). 5 | --> now 10: task10.aa changed to (av=0,bv=0). 6 | --> now 10: task10.bb changed to 0. 7 | --> now 10: task10.x changed to (av=ffffffff,bv=0). 8 | --> now 10: task10.y changed to 1. 9 | 10 start x: ffffffff y: 1 count: 0 10 | --> now 10: task10.t1.a changed to (av=0,bv=0). 11 | --> now 10: task10.t1.b changed to 0. 12 | 10 t1 started 13 | --> now 10: task10.t1.d changed to 0. 14 | --> now 20: task10.t1.c changed to (av=0,bv=0). 15 | --> now 30: task10.count changed to 1. 16 | 30 t1 finished 17 | --> now 30: task10.x changed to (av=0,bv=0). 18 | --> now 30: task10.y changed to 0. 19 | 30 return x: 00000000 y: 0 count: 1 20 | --> now 30: task10.aa changed to (av=1,bv=0). 21 | --> now 30: task10.bb changed to 1. 22 | --> now 30: task10.t1.a changed to (av=1,bv=0). 23 | --> now 30: task10.t1.b changed to 1. 24 | 30 t1 started 25 | --> now 30: task10.t1.d changed to 1. 26 | 35 return x: 00000000 y: 0 count: 1 27 | --> now 35: task10.aa changed to (av=2,bv=0). 28 | --> now 35: task10.bb changed to 0. 29 | --> now 35: task10.t1.a changed to (av=2,bv=0). 30 | --> now 35: task10.t1.b changed to 0. 31 | 35 t1 started 32 | --> now 35: task10.t1.d changed to 0. 33 | --> now 45: task10.t1.c changed to (av=2,bv=0). 34 | --> now 55: task10.count changed to 2. 35 | 55 t1 finished 36 | --> now 55: task10.x changed to (av=2,bv=0). 37 | 55 return x: 00000002 y: 0 count: 2 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vprtdel2.plg: -------------------------------------------------------------------------------- 1 | There are 1 top level modules (timescale -9 / -9). 2 | and gate test.i1 has delay #(1.6, 1.6). 3 | There are 0 instances in test (timescale: -8 / -9). 4 | All instances processed. 5 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vsetval1.plg: -------------------------------------------------------------------------------- 1 | 0 a=0000, w=0 (rw=0), wa=00000000000000000000000000000000 (rwa=00000000000000000000000000000000) 2 | 25 a=0020, w=0 (rw=0), wa=00000000000000000000000000000000 (rwa=00000000000000000000000000000000) 3 | 190 a=55aa, w=0 (rw=0), wa=00000000000000000000000000000000 (rwa=00000000000000000000000000000000) 4 | 290 a=55aa, w=x (rw=0), wa=00000000000000000000000000000000 (rwa=00000000000000000000000000000000) 5 | 420 a=55aa, w=1 (rw=z), wa=00000000000000000000000000000000 (rwa=00000000000000000000000000000000) 6 | 500 a=55aa, w=x (rw=z), wa=00000000000000000000000000000000 (rwa=00000000000000000000000000000000) 7 | 1125 a=55aa, w=x (rw=z), wa=00000000000000000000000000x00000 (rwa=00000000000000000000000000000000) 8 | 1300 a=55aa, w=x (rw=z), wa=zzzzzzzzzzzzzzzzzzzzzzzzzzxzzzzz (rwa=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) 9 | 1310 a=55aa, w=x (rw=z), wa=11111111111111111111111111111111 (rwa=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) 10 | 1320 a=55aa, w=x (rw=z), wa=zzzzzzzzzzzzzzzzzzzzzzzzzzxzzzzz (rwa=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) 11 | 1390 a=55aa, w=x (rw=z), wa=00000000000001011010101001x10101 (rwa=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) 12 | 1480 a=55aa, w=x (rw=z), wa=000000000000xxxxxxxxxxxxxxxxxxxx (rwa=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) 13 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vsetval2.plg: -------------------------------------------------------------------------------- 1 | 0 a=0000000000000000 2 | 125 a=0000000000100000 3 | 225 a=0000000000000000 4 | 325 a=0000000000100000 5 | 425 a=0000000000000000 6 | 525 a=0000000000100000 7 | 625 a=0000000000000000 8 | 725 a=0000000000100000 9 | 825 a=0000000000000000 10 | 925 a=0000000000100000 11 | -------------------------------------------------------------------------------- /tests_and_examples/examples.vpi/vsetval2.v: -------------------------------------------------------------------------------- 1 | // 2 | // test of strdelputp - copy from input system task to output then 3 | // compare results to make same 4 | // 5 | 6 | module top; 7 | xx i1(); 8 | endmodule 9 | 10 | module xx; 11 | integer i; 12 | reg [31:0] rwa; 13 | reg rw; 14 | reg [15:0] a, b; 15 | wire w; 16 | wire [31:0] wa; 17 | parameter d = 500; 18 | 19 | assign wa = rwa; 20 | assign w = rw; 21 | 22 | initial 23 | begin 24 | $monitor($stime,, "a=%b", a); 25 | a = 0; rwa = 0; 26 | for (i = 0; i < 1000; i = i + 100) 27 | begin 28 | $vsetval(a[5], rwa, i + 25, "vpiPureTransportDelay"); 29 | rwa[0] = ~rwa[0]; 30 | end 31 | #2000; 32 | end 33 | endmodule 34 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/README: -------------------------------------------------------------------------------- 1 | 2 | RUNNING CVC X-PROPAGATION TESTS 3 | 4 | This directory contains simple examples to illustrate how CVC X-propagation 5 | works along with the associated options to invoke CVC X-propagation. For a 6 | complete explanation of CVC X-propagation see doc/cvc_xpropagation.pdf from 7 | the top level directory. 8 | 9 | These examples are simple and mostly used 'initial' blocks to show 10 | X-propagation handling. To run all examples use the 'xprop_test.sh' script. 11 | 12 | 13 | The examples in this directory are used to illustrates the following 14 | functionality: 15 | 16 | xif.v - run with +xprop to show the Verilog semantic handling changes for 17 | if statements with X-propagation. 18 | 19 | xcase.v - run with +xprop to show the Verilog semantic handling changes for 20 | case statements with X-propagation. 21 | 22 | xnested.v - run with +xprop. Shows some combinations for if/case statements. 23 | 24 | xtrace.v - run with +xprop +xtrace. Used to show +xtrace capabilities 25 | when used along with +xprop/+xprop2 will trace each time and 26 | location that an if('bx) or case('bx) occurs causing X-progation 27 | to be entered. 28 | 29 | xprop2.v - run with +xprop2 to illustrate alternative X-propagation feature. 30 | 31 | xprop_eval.v - +xprop_eval to show X preservation across certain Verilog 32 | operators. 33 | 34 | xexcluded.v - +xprop +xprop_excluded. The +xprop_exlcuded option creates 35 | a file called 'cvc.xprop.excluded' that includes all statements 36 | that are not eligible for X-propagation along with the reason. 37 | 38 | xconfig.v - run with '-optconfigfile x.optconfig'. Example show how CVC's 39 | '-optconfigile' can be used to only turn on X-propagation for 40 | specific modules. 41 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/cvc.xprop: -------------------------------------------------------------------------------- 1 | 2 | ************************************************ 3 | ** ** 4 | ** CVC - Verilog X-propagation Report ** 5 | ** ** 6 | ** Generated : Sun Nov 17 20:41:00 2013 ** 7 | ************************************************ 8 | 9 | 10 | ########## X if condition ############ 11 | Time 0 12 | if (a) => 'bx1 13 | Location xtrace.v : 9 14 | Instance : xtrace 15 | ######################################### 16 | 17 | 18 | ########## X case condition ############ 19 | Time 0 20 | case (a) => 'b1xx 21 | Location xtrace.v : 15 22 | Instance : xtrace 23 | ######################################### 24 | 25 | 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/cvc.xprop.excluded: -------------------------------------------------------------------------------- 1 | 2 | ************************************************ 3 | ** ** 4 | ** X-propagation Not Eligible Statements ** 5 | ** ** 6 | ** Generated : Sun Nov 17 20:41:00 2013 ** 7 | ************************************************ 8 | 9 | 10 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/rmlic.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | my $file; 4 | my $i; 5 | my $line; 6 | 7 | $file = 'verilog.log'; 8 | if (@ARGV == 1) 9 | { 10 | $file = $ARGV[0]; 11 | } 12 | 13 | open(FILE, $file) or die "Can't open $file\n"; 14 | open(TMP, '>tmp') or die "Can't open tmp file\n"; 15 | for($i = 0; $i < 3; $i++) 16 | { 17 | $line = ; 18 | } 19 | while() 20 | { 21 | print TMP $_; 22 | } 23 | close TMP; 24 | close FILE; 25 | rename 'tmp', $file; 26 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/x.optconfig: -------------------------------------------------------------------------------- 1 | //only turn of X-propagation for module named 'dut' 2 | module {dut} {xprop}; 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xcase.plg: -------------------------------------------------------------------------------- 1 | case1 b = 0xx0 2 | case2 b = 0xx0 3 | case3 b = xxx0 4 | case4 b = 0xx0 c = 1100 5 | case5 b = 0xx0 c = xxxx 6 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xconfig.plg: -------------------------------------------------------------------------------- 1 | o=x 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xconfig.v: -------------------------------------------------------------------------------- 1 | //use CVC -optconfigfile option to only turn on X-propagation for module 2 | //named 'dut' not the testbench itself 3 | module testbench; 4 | reg clk, rst, i; 5 | wire o; 6 | 7 | dut i1(clk, rst, i, o); 8 | 9 | initial begin 10 | rst = 1'bx; 11 | i = 1'b0; 12 | clk = 1'b0; 13 | //xprop turned off for this module so it will not combine 14 | if (o) i = 1'b0; 15 | else i = 1'b1; 16 | 17 | clk = 1'b1; 18 | #1 ; 19 | clk = 1'b0; 20 | #1 ; 21 | $display("o=%b", o); 22 | end 23 | endmodule 24 | 25 | //include this module for x-propagation 26 | module dut(clk, rst, ival, oval); 27 | input clk; 28 | input rst; 29 | input ival; 30 | output reg oval; 31 | 32 | always @(clk) 33 | begin 34 | if (rst) oval = 1'b0; 35 | else oval = ival; 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xedges.plg: -------------------------------------------------------------------------------- 1 | test_scalar 2 | v=x 3 | test_scalar_negedge 4 | v=x 5 | test_vector 6 | v=xx 7 | test_vector_nonx_change 8 | v=00 9 | test_vector_negedge c[0]=x 10 | v=xx 11 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xedges.v: -------------------------------------------------------------------------------- 1 | //scalar (one-bit) change on 0->X 2 | module test_scalar; 3 | reg c, v; 4 | 5 | always @(c) v = 1'b0; 6 | 7 | initial begin 8 | v = 1'b1; 9 | c = 1'b0; 10 | #1 ; 11 | c = 1'bx; 12 | #1 ; 13 | $display("%m"); 14 | $display("v=%b", v); 15 | end 16 | 17 | endmodule 18 | 19 | //one bit scalar with 'negedge' 20 | module test_scalar_negedge; 21 | reg c,v; 22 | 23 | always @(negedge c) v = 1'b0; 24 | 25 | initial begin 26 | v = 1'b1; 27 | c = 1'b0; 28 | #1 ; 29 | c = 1'bx; 30 | #1 ; 31 | $display("%m"); 32 | $display("v=%b", v); 33 | end 34 | 35 | endmodule 36 | 37 | //two bit vectored with no 'real' 1/0 bits changed 00->XX 38 | module test_vector; 39 | reg [1:0] c,v; 40 | 41 | always @(c) v = 2'b00; 42 | 43 | initial begin 44 | v = 2'b11; 45 | c = 2'b00; 46 | #1 ; 47 | c = 2'bxx; 48 | #1 ; 49 | $display("%m"); 50 | $display("v=%b", v); 51 | end 52 | 53 | endmodule 54 | 55 | //two bit vectored with 'real' 1/0 bits changed 00->1X 56 | //handle as a real bit change 57 | module test_vector_nonx_change; 58 | reg [1:0] c,v; 59 | 60 | always @(c) v = 2'b00; 61 | 62 | initial begin 63 | v = 2'b11; 64 | c = 2'b00; 65 | #1 ; 66 | c = 2'b1x; 67 | #1 ; 68 | $display("%m"); 69 | $display("v=%b", v); 70 | end 71 | endmodule 72 | 73 | //two bit vectored with 'negedge' 74 | module test_vector_negedge; 75 | reg [1:0] c,v; 76 | 77 | always @(negedge c[0]) v = 2'b00; 78 | 79 | initial begin 80 | v = 2'b11; 81 | c = 2'b00; 82 | #1 ; 83 | c = 2'b1x; 84 | #1 ; 85 | $display("%m c[0]=%b", v[0]); 86 | $display("v=%b", v); 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xexcluded.plg: -------------------------------------------------------------------------------- 1 | b=0011 2 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xexcluded.v: -------------------------------------------------------------------------------- 1 | module xexcluded; 2 | reg [3:0] a, b; 3 | 4 | 5 | initial begin 6 | 7 | //only blocks containing if/case/lhs assings (=/<=/<= #const) are eligible 8 | //this if statement will be treated like regular Verilog since it 9 | //contains a delay the +xprop_exlude option will create a file called 10 | //'cvc.xprop.excluded' which are not eligible along with the reason 11 | a = 4'b000x; 12 | if (a) 13 | begin 14 | b = 4'b0000; 15 | #1; //contains delay - cannot be used in xprop 16 | end 17 | else 18 | begin 19 | b = 4'b0011; 20 | end 21 | $display("b=%b", b); 22 | end 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xif.plg: -------------------------------------------------------------------------------- 1 | test1 b=0001 2 | test2 b=x01x 3 | test3 b=11xx 4 | test4 b=x01x c=xxxx 5 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xif.v: -------------------------------------------------------------------------------- 1 | module xif; 2 | reg [3:0] a, b, c; 3 | 4 | initial begin 5 | /* TEST1 */ 6 | //if selector contains no Xs just handle as normal if 7 | a = 4'b0001; 8 | if (a) b = 1; 9 | else b = 0; 10 | //b=0001 11 | $display("test1 b=%b", b); 12 | 13 | 14 | /* TEST2 */ 15 | //if selector contains an X, combine the then/else sections using the ?: 16 | //rules, (0,0) = 0, (1,1) = 1, otherwise x 17 | a = 4'bxxxx; 18 | if (a) b = 4'bx010; 19 | else b = 4'bx011; 20 | //b=x01x 21 | $display("test2 b=%b", b); 22 | 23 | 24 | /* TEST3 */ 25 | //no else so combined with value on entry 26 | a = 4'b00x1; 27 | b = 4'b1100; 28 | if (a) b = 4'b1111; 29 | //b=11xx 30 | $display("test3 b=%b", b); 31 | 32 | /* TEST4 */ 33 | //X contains a select but 'c' is not set in else case will be assigned 'bx 34 | a = 4'b00x1; 35 | if (a) 36 | begin 37 | b = 4'bx010; 38 | c = 4'b1111; //c is assigned here not not is else case will be 4'bxxxx; 39 | end 40 | else b = 4'bx011; 41 | 42 | //b=x01x c = xxxx 43 | $display("test4 b=%b c=%b", b, c); 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xnested.plg: -------------------------------------------------------------------------------- 1 | test1 b = 1001 2 | test2 b = xx0x 3 | test3 b = 000x 4 | test4 b = xx00 5 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xprop2.plg: -------------------------------------------------------------------------------- 1 | b=xxxx 2 | case1 b = xxxx 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xprop2.v: -------------------------------------------------------------------------------- 1 | module xprop2; 2 | reg [3:0] a, b, c; 3 | 4 | initial begin 5 | //for +xprop2 - if value has an X does no combining will just set to x 6 | a = 4'b00x1; 7 | if (a) b = 4'bx010; 8 | else b = 4'bx011; 9 | //b=xxxx 10 | $display("b=%b", b); 11 | 12 | //same for +xprop2 case if selector contains an X no combining just set to X 13 | a = 4'b01xx; 14 | b = 0; 15 | case(a) 16 | 4'b0000: b = 4'b0000; 17 | 4'b1100: b = 4'b1100; 18 | 4'b0101: b = 4'b0010; 19 | 4'b0111: b = 4'b0100; 20 | endcase 21 | //just assigne b=xxxx 22 | $display("case1 b = %b", b); 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xprop_eval.plg: -------------------------------------------------------------------------------- 1 | and c = 1x1x 2 | or c = 1x1x 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xprop_eval.v: -------------------------------------------------------------------------------- 1 | module xprop_eval; 2 | reg [3:0] a, b, c; 3 | 4 | initial begin 5 | a = 4'b1011; 6 | b = 4'b1x1x; 7 | c = a & b; 8 | //normal Verilog c = 101x, with +xprop_eval c = 4'b1x1x 9 | $display("and c = %b", c); 10 | 11 | a = 4'b1011; 12 | b = 4'b1x1x; 13 | c = a | b; 14 | //normal Verilog c = 1x11, with +xprop_eval c = 4'b1x1x 15 | $display("or c = %b", c); 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xtrace.plg: -------------------------------------------------------------------------------- 1 | b = x01x 2 | b = 0xx0 3 | -------------------------------------------------------------------------------- /tests_and_examples/examples.xprop/xtrace.v: -------------------------------------------------------------------------------- 1 | module xtrace; 2 | reg [3:0] a, b, c; 3 | 4 | initial begin 5 | // the +xtrace feature along with +xprop or +xprop2 will record all times 6 | // and places during simulation where x-propagation occurs, run this 7 | // example with +xtrace and see the 'cvc.xprop' file it creates 8 | a = 4'b00x1; 9 | if (a) b = 4'bx010; 10 | else b = 4'bx011; 11 | $display("b = %b", b); 12 | 13 | a = 4'b01xx; 14 | b = 0; 15 | case(a) 16 | 4'b0000: b = 4'b0000; 17 | 4'b1100: b = 4'b1100; 18 | 4'b0101: b = 4'b0010; 19 | 4'b0111: b = 4'b0100; 20 | 4'b0100: b = 4'b0100; 21 | 4'b0110: b = 4'b0100; 22 | endcase 23 | $display("b = %b", b); 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/2901alg.plg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/install.test/2901alg.plg -------------------------------------------------------------------------------- /tests_and_examples/install.test/2901block.plg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/install.test/2901block.plg -------------------------------------------------------------------------------- /tests_and_examples/install.test/README: -------------------------------------------------------------------------------- 1 | 2 | RUNNING THE CVC INSTALLATION TEST 3 | 4 | *** BEWARE cvc and/or cvc64 must now be installed before running these 5 | *** scripts either somewhere on your shell PATH or in /tmp 6 | 7 | First run CVC without any arguments to make sure CVC binary is 8 | installed. The first line output CVC version number must match the version 9 | of your release directory. If the version number does not match, you probably 10 | have your shell PATH environment variable set to execute an old version of CVC. 11 | 12 | Run the shell command script to insure correct 32 bit installation by typing: 13 | 14 | inst_test.sh 15 | 16 | Correct installation is indicated by the following message with no diff 17 | command output lines before the message: 18 | 19 | >>>> Install test completed (this should be only printed message). 20 | 21 | To test 64 bit installation, type: "inst_test.sh cvc64". 22 | 23 | To test correct interpreter installation run the inst_test_interp.sh script. 24 | It can also take the cvc64 argument. 25 | 26 | By convention the expected output files end with .plg (and .plg64) suffixes. 27 | 28 | ------------------------------------------------------------------------- 29 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/arms.plg: -------------------------------------------------------------------------------- 1 | 2580 COUT !== 4'b0000 2 | 7230 COUT !== 4'b0000 3 | 11880 COUT !== 4'b0000 4 | 16530 COUT !== 4'b0000 5 | 21180 COUT !== 4'b0000 6 | 25830 COUT !== 4'b0000 7 | 30480 COUT !== 4'b0000 8 | 35130 COUT !== 4'b0000 9 | 39780 COUT !== 4'b0000 10 | 44430 COUT !== 4'b0000 11 | 49080 COUT !== 4'b0000 12 | 53730 COUT !== 4'b0000 13 | 58380 COUT !== 4'b0000 14 | 63030 COUT !== 4'b0000 15 | 67680 COUT !== 4'b0000 16 | 72330 COUT !== 4'b0000 17 | 76980 COUT !== 4'b0000 18 | 81630 COUT !== 4'b0000 19 | 86280 COUT !== 4'b0000 20 | 90930 COUT !== 4'b0000 21 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/aspike1.plg: -------------------------------------------------------------------------------- 1 | 0 out=x,in=0,w1=x,w2=x 2 | 2 out=x,in=0,w1=0,w2=x 3 | 5 out=z,in=0,w1=0,w2=1 4 | 100 out=z,in=1,w1=0,w2=1 5 | 101 out=z,in=1,w1=1,w2=1 6 | 105 out=1,in=1,w1=1,w2=0 7 | 111 out=0,in=1,w1=1,w2=0 8 | 200 out=0,in=x,w1=1,w2=0 9 | 201 out=0,in=x,w1=x,w2=0 10 | 204 out=0,in=x,w1=x,w2=x 11 | 209 out=x,in=x,w1=x,w2=x 12 | 300 out=x,in=z,w1=x,w2=x 13 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/aspike1.v: -------------------------------------------------------------------------------- 1 | module test; 2 | reg in; 3 | wire w1,w2,out; 4 | 5 | buf #(1,2) (w1,in); 6 | not #(3,4) (w2,w1); 7 | 8 | bufif1 #(5,6) (out,w2,in); 9 | 10 | initial begin 11 | $monitor($stime,, "out=%b,in=%b,w1=%b,w2=%b", out, in, w1, w2); 12 | #0 in=1'b0; 13 | #100 in=1'b1; 14 | #100 in=1'bx; 15 | #100 in=1'bz; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/aspike1a.plg: -------------------------------------------------------------------------------- 1 | 0 out=x,in=0,w1=x,w2=x 2 | 2 out=x,in=0,w1=0,w2=x 3 | 5 out=z,in=0,w1=0,w2=1 4 | 100 out=z,in=1,w1=0,w2=1 5 | 101 out=z,in=1,w1=1,w2=1 6 | 105 out=1,in=1,w1=1,w2=0 7 | 111 out=0,in=1,w1=1,w2=0 8 | 200 out=0,in=x,w1=1,w2=0 9 | 201 out=0,in=x,w1=x,w2=0 10 | **aspike1.v(8) WARN** now 204 [592] bufif1 gate test.__gate$$3 unstable (edge at 205 replaced by new at 209) - old St0, scheduled StL, new StX 11 | 204 out=0,in=x,w1=x,w2=x 12 | 209 out=x,in=x,w1=x,w2=x 13 | 300 out=x,in=z,w1=x,w2=x 14 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/aspike1b.plg: -------------------------------------------------------------------------------- 1 | 0 out=x,in=0,w1=x,w2=x 2 | 2 out=x,in=0,w1=0,w2=x 3 | 5 out=z,in=0,w1=0,w2=1 4 | 100 out=z,in=1,w1=0,w2=1 5 | 101 out=z,in=1,w1=1,w2=1 6 | 105 out=1,in=1,w1=1,w2=0 7 | 111 out=0,in=1,w1=1,w2=0 8 | 200 out=0,in=x,w1=1,w2=0 9 | 201 out=0,in=x,w1=x,w2=0 10 | 204 out=0,in=x,w1=x,w2=x 11 | 205 out=x,in=x,w1=x,w2=x 12 | 300 out=x,in=z,w1=x,w2=x 13 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/aspike1c.plg: -------------------------------------------------------------------------------- 1 | 0 out=x,in=0,w1=x,w2=x 2 | 2 out=x,in=0,w1=0,w2=x 3 | 5 out=z,in=0,w1=0,w2=1 4 | 100 out=z,in=1,w1=0,w2=1 5 | 101 out=z,in=1,w1=1,w2=1 6 | 105 out=1,in=1,w1=1,w2=0 7 | 111 out=0,in=1,w1=1,w2=0 8 | 200 out=0,in=x,w1=1,w2=0 9 | 201 out=0,in=x,w1=x,w2=0 10 | 204 out=x,in=x,w1=x,w2=x 11 | 300 out=x,in=z,w1=x,w2=x 12 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/aspike1d.plg: -------------------------------------------------------------------------------- 1 | 0 out=x,in=0,w1=x,w2=x 2 | 2 out=x,in=0,w1=0,w2=x 3 | 5 out=z,in=0,w1=0,w2=1 4 | 100 out=z,in=1,w1=0,w2=1 5 | 101 out=z,in=1,w1=1,w2=1 6 | 105 out=1,in=1,w1=1,w2=0 7 | 111 out=0,in=1,w1=1,w2=0 8 | 200 out=0,in=x,w1=1,w2=0 9 | 201 out=0,in=x,w1=x,w2=0 10 | 204 out=0,in=x,w1=x,w2=x 11 | 209 out=x,in=x,w1=x,w2=x 12 | 300 out=x,in=z,w1=x,w2=x 13 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/c880.plg: -------------------------------------------------------------------------------- 1 | 0 00000111101000000000000000 2 | 1 11111100010111100111111111 3 | 2 xxxxxxxxxxxxxxxxxxxxxxxxxx 4 | 4 10000111101000111101011111 5 | 5 1xxxxxxxxxxxxx1xx1x1x11111 6 | 6 00000110111100011110100101 7 | 7 00000111101100100111101111 8 | 8 xxxxxxxxxxxxxxxxxxxxxxxxxx 9 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/cpurtl2.plg: -------------------------------------------------------------------------------- 1 | 100000 accumulator = 168086735545728337 2 | 200000 accumulator = 2305843009213693953 3 | 300000 accumulator = 103706419654586480 4 | 400000 accumulator = 9160321642071588864 5 | 500000 accumulator = 180427117971047299 6 | 600000 accumulator = 36311929895191427 7 | 700000 accumulator = 36311929895191427 8 | 800000 accumulator = 78839485241497624 9 | 900000 accumulator = 155694798661118289 10 | 1000000 accumulator = 108369523933119360 11 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/defsplt1.plg: -------------------------------------------------------------------------------- 1 | ** WARN** [614] no pending statements or events after initialization - nothing to do 2 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/defsplt1.v: -------------------------------------------------------------------------------- 1 | 2 | module complex_mul; 3 | defparam UMLP.N=12; 4 | defparam UMLP.M=13; 5 | Mult0 UMLP (); //end of Mult0 UMLP 6 | 7 | defparam UMLR.N=12; 8 | defparam UMLR.M=13; 9 | Mult0 UMLR (); //end of Mult0 UMLR 10 | 11 | endmodule 12 | 13 | module Mult0 ; 14 | parameter N=12; 15 | parameter M=12; 16 | parameter Q=N+M; 17 | reg [M:0] datab; 18 | 19 | defparam U_MULT00.MULT_N=N-1; 20 | defparam U_MULT00.MULT_M=M-1; 21 | mult U_MULT00 ( 22 | .b(datab[M-1:0]), 23 | .r(aXb) 24 | ); 25 | 26 | endmodule 27 | 28 | module mult ( 29 | b, 30 | r 31 | ); 32 | parameter MULT_N =8; 33 | parameter MULT_M =8; 34 | parameter MULT_NM=MULT_M + MULT_N + 2; 35 | input [MULT_M :0] b; 36 | output [MULT_NM:0] r; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/dffn.v: -------------------------------------------------------------------------------- 1 | // pipeline model from LRM section 7.1.6 2 | module DFF(q, d, clk); 3 | output q; 4 | input d, clk; 5 | reg q; 6 | 7 | always @(posedge clk) 8 | begin 9 | $display($stime,, "-- %m: positive clock edge old q=%b d=%b", q, d); 10 | q = d; 11 | end 12 | endmodule 13 | 14 | module dffn(q, d, clk); 15 | parameter bits = 1; 16 | 17 | input [bits-1:0] d; 18 | output [bits-1:0] q; 19 | input clk; 20 | 21 | DFF dff[bits-1:0] (q, d, clk); 22 | endmodule 23 | 24 | module MxN_pipeline(in, out, clk); 25 | parameter M = 3, N = 4; 26 | 27 | input [M-1:0] in; 28 | output [M-1:0] out; 29 | input clk; 30 | 31 | wire [M*(N-1):1] t; 32 | 33 | dffn #(M) p[1:N] ({out, t}, {t, in}, clk); 34 | endmodule 35 | 36 | module top; 37 | reg [M-1:0] in; 38 | reg clk; 39 | wire [M-1:0] out; 40 | parameter M = 3, N = 4; 41 | 42 | MxN_pipeline #(M, N) pipe1(in, out, clk); 43 | 44 | initial 45 | begin 46 | $monitor($stime,, "in=%b, out=%b, clk=%b", in, out, clk); 47 | #10 in = 3'b0; 48 | #10 clk = 0; 49 | #10 clk = 1; 50 | #10 clk = 1'bx; 51 | #10 clk = 0; 52 | 53 | #10 in = 3'b111; 54 | #10 clk = 0; 55 | #10 clk = 1; 56 | #10 clk = 1'bx; 57 | #10 clk = 0; 58 | 59 | #10 in = 3'b0; 60 | #10 clk = 0; 61 | #10 clk = 111; 62 | #10 clk = 1'bx; 63 | #10 clk = 0; 64 | 65 | // notice values do not propagate through pipeline until here 66 | #10 in = 3'b111; 67 | #10 clk = 0; 68 | #10 clk = 1; 69 | #10 clk = 1'bx; 70 | #10 clk = 0; 71 | end 72 | endmodule 73 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/dfpsetd.plg: -------------------------------------------------------------------------------- 1 | **dfpsetd1.sdf(6) WARN** [2304] (LABEL form back annotation to parameter d non standard - will need to change to module scope specparam for Verilog 2000 2 | 0 preset=x clear=x q=x qbar=x 3 | 100 preset=0 clear=1 q=x qbar=x 4 | 110 preset=0 clear=1 q=1 qbar=x 5 | 116 preset=0 clear=1 q=1 qbar=0 6 | 200 preset=1 clear=1 q=1 qbar=0 7 | 300 preset=1 clear=0 q=1 qbar=0 8 | 306 preset=1 clear=0 q=1 qbar=1 9 | 312 preset=1 clear=0 q=0 qbar=1 10 | 400 preset=1 clear=1 q=0 qbar=1 11 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/dfpsetd.v: -------------------------------------------------------------------------------- 1 | module ffnand_test; 2 | wire q, qbar; 3 | reg preset, clear; 4 | 5 | parameter d = 10; 6 | 7 | ffnand ff1(q, qbar, preset, clear); 8 | initial 9 | begin 10 | #d preset = 0; clear = 1; 11 | #d preset = 1; 12 | #d clear = 0; 13 | #d clear = 1; 14 | end 15 | initial $monitor($time,, "preset=%b clear=%b q=%b qbar=%b", 16 | preset, clear,q, qbar); 17 | endmodule 18 | 19 | module ffnand(ffq, ffqbar, ffpreset, ffclear); 20 | output ffq, ffqbar; 21 | input ffpreset, ffclear; 22 | 23 | nand #(1, 1) q1(ffq, ffqbar, ffpreset), q2(ffqbar, ffq, ffclear); 24 | specify 25 | specparam pr = 5; 26 | specparam pf = 5; 27 | // notice error because no path delay to ffqbar 28 | (ffpreset => ffq) = (pr, pf); 29 | (ffclear => ffq) = (pr, pf); 30 | endspecify 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/dfpsetd.vc: -------------------------------------------------------------------------------- 1 | // use this option to determine SDF delay setting sequence 2 | // +sdfverbose 3 | dfpsetd.v 4 | // two different files on showing no context paths and one with context paths 5 | +sdfannotate dfpsetd1.sdf 6 | +sdfannotate dfpsetd2.sdf+ffnand_test 7 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/dfpsetd1.sdf: -------------------------------------------------------------------------------- 1 | (DELAYFILE 2 | (SDFVERSION "3.0") 3 | (CELL 4 | (CELLTYPE "ffnand_test" ) 5 | (INSTANCE ffnand_test) 6 | (LABEL (ABSOLUTE (d 100))) 7 | ) 8 | ) 9 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/dfpsetd2.sdf: -------------------------------------------------------------------------------- 1 | // context here [+] is ffnand_test 2 | (DELAYFILE 3 | (SDFVERSION "3.0") 4 | (CELL 5 | (CELLTYPE "ffnand" ) 6 | (INSTANCE ff1) 7 | (LABEL (ABSOLUTE (pr 10) (pf 10))) 8 | ) 9 | (CELL 10 | (CELLTYPE "nand" ) 11 | (INSTANCE ff1.q1) 12 | // since source has 2 delays (3rd toz computed), need 3 for increment 13 | (DELAY (INCREMENT (DEVICE (5) (5)))) 14 | ) 15 | (CELL 16 | (CELLTYPE "nand" ) 17 | (INSTANCE ff1.q2) 18 | (DELAY (INCREMENT (DEVICE (5) (5)))) 19 | ) 20 | ) 21 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/force01.inp: -------------------------------------------------------------------------------- 1 | // also test input from $input(); 2 | force d = (a | b | c); 3 | force e = (a | b | c); 4 | #10 $stop; 5 | . 6 | release d; 7 | release e; 8 | c = 0; 9 | #10 $finish; 10 | . 11 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/force01.plg: -------------------------------------------------------------------------------- 1 | d=0,e=0 2 | C1 > // also test input from $input(); 3 | C1 > force d = (a | b | c); 4 | C2 > force e = (a | b | c); 5 | C3 > #10 $stop; 6 | C4 > . 7 | d=1,e=1 8 | C4 > release d; 9 | C5 > release e; 10 | C6 > c = 0; 11 | C7 > #10 $finish; 12 | C8 > . 13 | d=0,e=0 14 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/force01.v: -------------------------------------------------------------------------------- 1 | module test; 2 | reg a, // = 1'hx, x 3 | b, // = 1'hx, x 4 | c, // = 1'hx, x 5 | d; // = 1'hx, x 6 | wire e; // = StX 7 | and and1(e, a, b, c); 8 | 9 | initial 10 | begin 11 | // $list; 12 | $monitor("d=%b,e=%b", d, e); 13 | a = 1; 14 | b = 0; 15 | c = 1; 16 | assign d = a & b & c; 17 | #10 ; 18 | $stop; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/gatenots.plg: -------------------------------------------------------------------------------- 1 | 0 input 0000000000000 outputs(m0) xxxxxxxxxxxxx 2 | 56 input 0000000000000 outputs(m0) 0000000000000 3 | 200 input 3ffffffffffff outputs(m1) 0000000000000 4 | 256 input 3ffffffffffff outputs(m1) 3ffffffffffff 5 | 400 input xxxxxxxxxxxxx outputs(m2) 3ffffffffffff 6 | 442 input xxxxxxxxxxxxx outputs(m2) xxxxxxxxxxxxx 7 | 600 input zzzzzzzzzzzzz outputs(m3) xxxxxxxxxxxxx 8 | 800 input 1555555555555 outputs(m4) xxxxxxxxxxxxx 9 | 856 input 1555555555555 outputs(m4) 1555555555555 10 | 1000 input XXXXXXXXXXXXX outputs(m5) 1555555555555 11 | 1042 input XXXXXXXXXXXXX outputs(m5) XXXXXXXXXXXXX 12 | 1200 input 2aaaaaaaaaaaa outputs(m6) XXXXXXXXXXXXX 13 | 1256 input 2aaaaaaaaaaaa outputs(m6) 2aaaaaaaaaaaa 14 | 1400 input 333ccf33ccf33 outputs(m7) 2aaaaaaaaaaaa 15 | 1456 input 333ccf33ccf33 outputs(m7) 333ccf33ccf33 16 | 1600 input 0000000000000 outputs(m8) 333ccf33ccf33 17 | 1656 input 0000000000000 outputs(m8) 0000000000000 18 | 1800 input 3ffffffffffff outputs(m9) 0000000000000 19 | 1856 input 3ffffffffffff outputs(m9) 3ffffffffffff 20 | 2000 input xxxxxxxxxxxxx outputs(m9) 3ffffffffffff 21 | 2042 input xxxxxxxxxxxxx outputs(m9) xxxxxxxxxxxxx 22 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/gcd.plg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/install.test/gcd.plg -------------------------------------------------------------------------------- /tests_and_examples/install.test/gn.mem: -------------------------------------------------------------------------------- 1 | 0000000000_0000000000_0000000000_0000000000_0000000000 2 | 1111111111_1111111111_1111111111_1111111111_1111111111 3 | xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx 4 | zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz 5 | 0101010101_0101010101_0101010101_0101010101_0101010101 6 | x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1 7 | 1010101010_1010101010_1010101010_1010101010_1010101010 8 | 1100110011_1100110011_1100110011_1100110011_1100110011 9 | 10 | 0000000000_0000000000_0000000000_0000000000_0000000000 11 | 1111111111_1111111111_1111111111_1111111111_1111111111 12 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/instid.plg: -------------------------------------------------------------------------------- 1 | i=0,p1=1,p2=0 2 | i=1,p1=2,p2=0 3 | i=2,p1=3,p2=0 4 | i=3,p1=4,p2=0 5 | i=6,p1=5,p2=0 6 | i=7,p1=6,p2=0 7 | i=8,p1=7,p2=0 8 | i=9,p1=8,p2=0 9 | i=24,p1=9,p2=0 10 | i=25,p1=10,p2=0 11 | i=26,p1=11,p2=0 12 | i=27,p1=12,p2=0 13 | i=30,p1=13,p2=0 14 | i=31,p1=14,p2=0 15 | i=32,p1=15,p2=0 16 | i=33,p1=16,p2=0 17 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/instid.plg64: -------------------------------------------------------------------------------- 1 | **instid.v(15) WARN** [602] x1(level1$$1) input port i (line **instid.v(3)) width 32 mismatch with 2 * i width 64 2 | **instid.v(16) WARN** [602] x2(level1) input port i (line **instid.v(3)) width 32 mismatch with (2 * i) + 1 width 64 3 | **instid.v(22) WARN** [602] x1(level2) input port i (line **instid.v(12)) width 32 mismatch with 3 * i width 64 4 | **instid.v(23) WARN** [602] x2(level2) input port i (line **instid.v(12)) width 32 mismatch with (3 * i) + 1 width 64 5 | **instid.v(29) WARN** [602] x1(level3) input port i (line **instid.v(19)) width 32 mismatch with 4 * i width 64 6 | **instid.v(30) WARN** [602] x2(level3) input port i (line **instid.v(19)) width 32 mismatch with (4 * i) + 1 width 64 7 | **instid.v(36) WARN** [602] x1(level4) input port i (line **instid.v(26)) width 32 mismatch with 4 * i width 64 8 | **instid.v(37) WARN** [602] x2(level4) input port i (line **instid.v(26)) width 32 mismatch with (4 * i) + 1 width 64 9 | i=0,p1=1,p2=0 10 | i=1,p1=2,p2=0 11 | i=2,p1=3,p2=0 12 | i=3,p1=4,p2=0 13 | i=6,p1=5,p2=0 14 | i=7,p1=6,p2=0 15 | i=8,p1=7,p2=0 16 | i=9,p1=8,p2=0 17 | i=24,p1=9,p2=0 18 | i=25,p1=10,p2=0 19 | i=26,p1=11,p2=0 20 | i=27,p1=12,p2=0 21 | i=30,p1=13,p2=0 22 | i=31,p1=14,p2=0 23 | i=32,p1=15,p2=0 24 | i=33,p1=16,p2=0 25 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/instid.v: -------------------------------------------------------------------------------- 1 | // instance identity test 2 | 3 | module level1(i); 4 | input [31:0] i; 5 | parameter p1 = 0, p2 = 0; 6 | initial 7 | begin 8 | #1 $display("i=%0d,p1=%0d,p2=%0d", i, p1, p2); 9 | end 10 | endmodule 11 | 12 | module level2(i); 13 | input [31:0] i; 14 | parameter p1 = 0, p2 = 0; 15 | level1 x1(2*i); 16 | level1 x2(2*i + 1); 17 | endmodule 18 | 19 | module level3(i); 20 | input [31:0] i; 21 | parameter p1 = 0, p2 = 0; 22 | level2 x1(3*i); 23 | level2 x2(3*i + 1); 24 | endmodule 25 | 26 | module level4(i); 27 | input [31:0] i; 28 | parameter p1 = 0, p2 = 0; 29 | level3 x1(4*i); 30 | level3 x2(4*i + 1); 31 | endmodule 32 | 33 | module level5(i); 34 | input [31:0] i; 35 | parameter p1 = 0, p2 = 0; 36 | level4 x1(4*i); 37 | level4 x2(4*i + 1); 38 | endmodule 39 | 40 | module top; 41 | integer i; 42 | 43 | initial i = 0; 44 | level5 t1(i); 45 | defparam t1.x1.x1.x1.x1.p1 = 1; 46 | defparam t1.x1.x1.x1.x2.p1 = 2; 47 | defparam t1.x1.x1.x2.x1.p1 = 3; 48 | defparam t1.x1.x1.x2.x2.p1 = 4; 49 | 50 | defparam t1.x1.x2.x1.x1.p1 = 5; 51 | defparam t1.x1.x2.x1.x2.p1 = 6; 52 | defparam t1.x1.x2.x2.x1.p1 = 7; 53 | defparam t1.x1.x2.x2.x2.p1 = 8; 54 | 55 | defparam t1.x2.x1.x1.x1.p1 = 9; 56 | defparam t1.x2.x1.x1.x2.p1 = 10; 57 | defparam t1.x2.x1.x2.x1.p1 = 11; 58 | defparam t1.x2.x1.x2.x2.p1 = 12; 59 | 60 | defparam t1.x2.x2.x1.x1.p1 = 13; 61 | defparam t1.x2.x2.x1.x2.p1 = 14; 62 | defparam t1.x2.x2.x2.x1.p1 = 15; 63 | defparam t1.x2.x2.x2.x2.p1 = 16; 64 | endmodule 65 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/instpnd3.plg: -------------------------------------------------------------------------------- 1 | i=0,h=31,p1=1,p2=0 2 | i=1,h=2,p1=2,p2=0 3 | i=2,h=3,p1=3,p2=0 4 | i=3,h=4,p1=4,p2=0 5 | i=6,h=5,p1=5,p2=0 6 | i=7,h=6,p1=6,p2=0 7 | i=8,h=7,p1=7,p2=0 8 | i=9,h=8,p1=8,p2=0 9 | i=24,h=9,p1=9,p2=0 10 | i=25,h=10,p1=10,p2=0 11 | i=26,h=11,p1=11,p2=0 12 | i=27,h=12,p1=12,p2=0 13 | i=30,h=13,p1=13,p2=0 14 | i=31,h=14,p1=14,p2=0 15 | i=32,h=15,p1=15,p2=0 16 | i=33,h=16,p1=16,p2=0 17 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/jkff.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************/ 2 | 3 | module jkff (t, tbar, j, k, ck, s, r); 4 | 5 | parameter rise = 0, fall = 0; 6 | 7 | input j, k, ck, s, r; // J, K, clock, s, clear 8 | output t, tbar; // data outputs 9 | 10 | JK_Q #(rise, fall) (t, j, k, ck, s, r); 11 | JK_QBAR #(rise, fall) (tbar, j, k, ck, s, r); 12 | 13 | endmodule // jkff 14 | 15 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/mem.dat: -------------------------------------------------------------------------------- 1 | 00000_00000 2 | 11111_11111 3 | xxxxx_xxxxx 4 | zzzzz_zzzzz 5 | 01010_10101 6 | x1x1x_1x1x1 7 | 10101_01010 8 | 11001_10011 9 | // 00110_01100 10 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/mipdnot1.plg: -------------------------------------------------------------------------------- 1 | 0 w1=x, r1=x, w2=x, r2=x 2 | 100 w1=x, r1=0, w2=x, r2=x 3 | 110 w1=1, r1=0, w2=x, r2=x 4 | 200 w1=1, r1=0, w2=x, r2=0 5 | 208 w1=1, r1=0, w2=1, r2=0 6 | 300 w1=1, r1=1, w2=1, r2=0 7 | 315 w1=0, r1=1, w2=1, r2=0 8 | 400 w1=0, r1=1, w2=1, r2=1 9 | 412 w1=0, r1=1, w2=0, r2=1 10 | 500 w1=0, r1=0, w2=0, r2=1 11 | 510 w1=1, r1=0, w2=0, r2=1 12 | 600 w1=1, r1=0, w2=0, r2=0 13 | 608 w1=1, r1=0, w2=1, r2=0 14 | 700 w1=1, r1=x, w2=1, r2=0 15 | 705 w1=x, r1=x, w2=1, r2=0 16 | 800 w1=x, r1=x, w2=1, r2=x 17 | 804 w1=x, r1=x, w2=x, r2=x 18 | 900 w1=x, r1=0, w2=x, r2=x 19 | 910 w1=1, r1=0, w2=x, r2=x 20 | 1000 w1=1, r1=0, w2=x, r2=0 21 | 1008 w1=1, r1=0, w2=1, r2=0 22 | 1100 w1=1, r1=z, w2=1, r2=0 23 | 1105 w1=x, r1=z, w2=1, r2=0 24 | 1200 w1=x, r1=z, w2=1, r2=z 25 | 1204 w1=x, r1=z, w2=x, r2=z 26 | 1300 w1=x, r1=1, w2=x, r2=z 27 | 1315 w1=0, r1=1, w2=x, r2=z 28 | 1400 w1=0, r1=1, w2=x, r2=1 29 | 1412 w1=0, r1=1, w2=0, r2=1 30 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/mipdnot1.sdf: -------------------------------------------------------------------------------- 1 | (DELAYFILE 2 | (SDFVERSION "3.0") 3 | (CELL 4 | (CELLTYPE "xx" ) 5 | (INSTANCE xx) 6 | (DELAY (ABSOLUTE (PORT i1.a (15) (10) (5)))) 7 | (DELAY (ABSOLUTE (PORT i2.a (12) (8) (4)))) 8 | ) 9 | ) 10 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/mipdnot1.v: -------------------------------------------------------------------------------- 1 | module xx; 2 | wire w1, w2; 3 | reg r1, r2; 4 | 5 | modnot i1(w1, r1); 6 | modnot i2(w2, r2); 7 | 8 | initial 9 | begin 10 | $monitor($stime,, "w1=%b, r1=%b, w2=%b, r2=%b", w1, r1, w2, r2); 11 | #100 r1 = 0; 12 | #100 r2 = 0; 13 | 14 | #100 r1 = 1; 15 | #100 r2 = 1; 16 | 17 | #100 r1 = 0; 18 | #100 r2 = 0; 19 | 20 | #100 r1 = 1'bx; 21 | #100 r2 = 1'bx; 22 | 23 | #100 r1 = 0; 24 | #100 r2 = 0; 25 | 26 | #100 r1 = 1'bz; 27 | #100 r2 = 1'bz; 28 | 29 | #100 r1 = 1; 30 | #100 r2 = 1; 31 | end 32 | endmodule 33 | 34 | module modnot(out, a); 35 | output out; 36 | input a; 37 | 38 | not (out, a); 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/mipdnot1.vc: -------------------------------------------------------------------------------- 1 | mipdnot1.v 2 | +sdfannotate mipdnot1.sdf 3 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/patt.mem: -------------------------------------------------------------------------------- 1 | 00000_00000_00000_00000_00000_00000_00000_00000_00000_00000_00000_00000 2 | 11111_11111_11111_11111_11111_11111_11111_11111_11111_11111_11111_11111 3 | xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx_xxxxx 4 | zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz_zzzzz 5 | 01010_10101_01010_10101_01010_10101_01010_10101_01010_10101_01010_10101 6 | x1x1x_1x1x1_x1x1x_1x1x1_x1x1x_1x1x1_x1x1x_1x1x1_x1x1x_1x1x1_x1x1x_1x1x1 7 | 10101_01010_10101_01010_10101_01010_10101_01010_10101_01010_10101_01010 8 | 11001_10011_11001_10011_11001_10011_11001_10011_11001_10011_11001_10011 9 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/rmlic.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | my $file; 4 | my $i; 5 | my $line; 6 | 7 | $file = 'verilog.log'; 8 | if (@ARGV == 1) 9 | { 10 | $file = $ARGV[0]; 11 | } 12 | 13 | open(FILE, $file) or die "Can't open $file\n"; 14 | open(TMP, '>tmp') or die "Can't open tmp file\n"; 15 | for($i = 0; $i < 3; $i++) 16 | { 17 | $line = ; 18 | } 19 | while() 20 | { 21 | print TMP $_; 22 | } 23 | close TMP; 24 | close FILE; 25 | rename 'tmp', $file; 26 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/sdfia04.plg: -------------------------------------------------------------------------------- 1 | 0 preset[1]=x clear[1]=x q[18]=x qbar[18]=x 2 | 10 preset[1]=0 clear[1]=1 q[18]=x qbar[18]=x 3 | 13 preset[1]=0 clear[1]=1 q[18]=1 qbar[18]=x 4 | 16 preset[1]=0 clear[1]=1 q[18]=1 qbar[18]=0 5 | 20 preset[1]=1 clear[1]=1 q[18]=1 qbar[18]=0 6 | 30 preset[1]=1 clear[1]=0 q[18]=1 qbar[18]=0 7 | 31 preset[1]=1 clear[1]=0 q[18]=1 qbar[18]=x 8 | 32 preset[1]=1 clear[1]=0 q[18]=x qbar[18]=x 9 | 33 preset[1]=1 clear[1]=0 q[18]=x qbar[18]=1 10 | 36 preset[1]=1 clear[1]=0 q[18]=0 qbar[18]=1 11 | 40 preset[1]=1 clear[1]=1 q[18]=0 qbar[18]=1 12 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/sdfia04.sdf: -------------------------------------------------------------------------------- 1 | (DELAYFILE 2 | (SDFVERSION "3.0") 3 | (CELL 4 | (CELLTYPE "and" ) 5 | (INSTANCE q1[18]) 6 | (DELAY (INCREMENT (DEVICE (:2:1)))) 7 | ) 8 | (CELL 9 | (CELLTYPE "and" ) 10 | (INSTANCE q2[18]) 11 | (DELAY (INCREMENT (DEVICE (1:2:)))) 12 | ) 13 | ) 14 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/sdfia04.v: -------------------------------------------------------------------------------- 1 | module ffnand_test; 2 | wire [1:18] q, qbar; 3 | reg [18:1] preset, clear; 4 | 5 | parameter d = 10; 6 | 7 | ffnand #(.wide(17)) ff1[1:18](q, qbar, preset, clear); 8 | initial 9 | begin 10 | #d preset[1] = 0; clear[1] = 1; 11 | #d preset[1] = 1; 12 | #d clear[1] = 0; 13 | #d clear[1] = 1; 14 | end 15 | initial $monitor($time,, "preset[1]=%b clear[1]=%b q[18]=%b qbar[18]=%b", 16 | preset[1], clear[1], q[18], qbar[18]); 17 | endmodule 18 | 19 | module ffnand(ffq, ffqbar, ffpreset, ffclear); 20 | output [1:wide + 1] ffq, ffqbar; 21 | input [wide + 1:1] ffpreset, ffclear; 22 | parameter wide = 1; 23 | 24 | nand #1 q1[1:wide + 1] (ffq, ffqbar, ffpreset), 25 | q2[1:wide + 1] (ffqbar, ffq, ffclear); 26 | endmodule 27 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/sdfia04.vc: -------------------------------------------------------------------------------- 1 | +sdfannotate sdfia04.sdf+ffnand_test.ff1[18] 2 | sdfia04.v 3 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/smrd04.plg: -------------------------------------------------------------------------------- 1 | idprom[1]=0010011011 2 | idprom[2]=0000001111 3 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/smrd04.v: -------------------------------------------------------------------------------- 1 | module top; 2 | parameter idprom_width = 10, idprom_depth = 2, step = 20; 3 | reg [8*idprom_width:1] s1, s2; 4 | integer index; 5 | 6 | reg [idprom_width:1] idprom[1:idprom_depth]; 7 | 8 | initial 9 | begin 10 | // probably should do some checking here 11 | if ($scan$plusargs("idprom1=", s1) == 0 12 | || $scan$plusargs("idprom2=", s2) == 0) 13 | begin 14 | $display("missing or bad idprom option(s)"); 15 | $finish; 16 | end 17 | $sreadmemb(idprom,,, s1, s2); 18 | for (index = 0; index < idprom_depth; index = index + 1) #step; 19 | for (index = 1; index <= idprom_depth; index = index + 1) 20 | $display("idprom[%0d]=%b", index, idprom[index]); 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/smrd04.vc: -------------------------------------------------------------------------------- 1 | +idprom1=0010011011 2 | +idprom2=00001111 3 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/testmem.dat: -------------------------------------------------------------------------------- 1 | 0000000000_0000000000_0000000000_0000000000_0000000000_0000000000_0000000 2 | 1111111111_1111111111_1111111111_1111111111_1111111111_1111111111_1111111 3 | xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxxxxx_xxxxxxx 4 | zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzzzzz_zzzzzzz 5 | 0101010101_0101010101_0101010101_0101010101_0101010101_0101010101_0101010 6 | x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x1x1_x1x1x1x 7 | 1010101010_1010101010_1010101010_1010101010_1010101010_1010101010_1010101 8 | 1100110011_1100110011_1100110011_1100110011_1100110011_1100110011_1100110 9 | z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z1z1_z1z1z1z 10 | 01xz01xz01_01xz01xz01_01xz01xz01_01xz01xz01_01xz01xz01_01xz01xz01_01xz01x 11 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/udpjkff.v: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | reg r_clock,j,k,s,r; 4 | assign clock = r_clock; 5 | 6 | jkff inst1 (t, tbar, j, k, clock, s, r); 7 | 8 | initial begin 9 | $monitor ($time,,"t=%b,tbar=%b,j=%b,k=%b,clock= %b,s=%b,r=%b", 10 | t, tbar, j, k, clock, s, r); 11 | j = 0; 12 | k = 0; 13 | s = 1; 14 | r = 1; 15 | end 16 | 17 | initial begin 18 | 19 | #10 s = 0; 20 | #10 r = 1; 21 | #10 r = 0; 22 | #10 r = 1; 23 | #10 j = 0; k = 0; 24 | #10 r_clock = 0; 25 | #10 r_clock = 1; 26 | #10 j = 0; k = 1; 27 | #10 r_clock = 0; 28 | #10 r_clock = 1; 29 | #10 j = 1; k = 0; 30 | #10 r_clock = 0; 31 | #10 r_clock = 1; 32 | #10 j = 1; k = 1; 33 | #10 r_clock = 0; 34 | #10 r_clock = 1; 35 | #10 j = 0; k = 1; 36 | #10 r_clock = 0; 37 | #10 r_clock = 1; 38 | #10 j = 0; k = 0; 39 | #10 r_clock = 0; 40 | #10 r_clock = 1; 41 | #10 r = 0; 42 | #10 r_clock = 0; 43 | #10 r_clock = 1; 44 | #10 r = 0; 45 | #10 s = 1; 46 | #10 r_clock = 0; 47 | #10 r_clock = 1; 48 | #10 r = 1; 49 | #10 s = 0; r = 1; 50 | #10 s = 1; r = 0; 51 | #10 s = 1; r = 1; 52 | #10 s = 0; r = 0; 53 | #10 s = 1; r = 0; 54 | #10 s = 0; r = 1; 55 | end 56 | endmodule 57 | 58 | // jk flip flop from valid SIM library 59 | module jkff (t, tbar, j, k, ck, s, r); 60 | 61 | parameter rise = 0, fall = 0; 62 | 63 | input j, k, ck, s, r; // J, K, clock, s, clear 64 | output t, tbar; // data outputs 65 | 66 | JK_Q #(rise, fall) (t, j, k, ck, s, r); 67 | JK_QBAR #(rise, fall) (tbar, j, k, ck, s, r); 68 | 69 | endmodule // jkff 70 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/uu: -------------------------------------------------------------------------------- 1 | 1a2,13 2 | > C1 > // also test input from $input(); 3 | > C1 > force d = (a | b | c); 4 | > C2 > force e = (a | b | c); 5 | > C3 > #10 $stop; 6 | > C4 > . 7 | > d=1,e=1 8 | > C4 > release d; 9 | > C5 > release e; 10 | > C6 > c = 0; 11 | > C7 > #10 $finish; 12 | > C8 > . 13 | > d=0,e=0 14 | >>>> Install +interp test completed (this should be only message printed). 15 | 16 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/xplipnd.plg: -------------------------------------------------------------------------------- 1 | i=0,p1=500,p2=501 2 | i=1,p1=502,p2=503 3 | i=2,p1=500,p2=501 4 | i=3,p1=502,p2=503 5 | i=6,p1=500,p2=501 6 | i=7,p1=502,p2=503 7 | i=8,p1=500,p2=501 8 | i=9,p1=502,p2=503 9 | i=24,p1=500,p2=501 10 | i=25,p1=502,p2=503 11 | i=26,p1=500,p2=501 12 | i=27,p1=502,p2=503 13 | i=30,p1=500,p2=501 14 | i=31,p1=502,p2=503 15 | i=32,p1=500,p2=501 16 | i=33,p1=502,p2=503 17 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/xplipnd.plg64: -------------------------------------------------------------------------------- 1 | **xplipnd.v(15) WARN** [602] x1(level1) input port i (line **xplipnd.v(3)) width 32 mismatch with 2 * i width 64 2 | **xplipnd.v(16) WARN** [602] x2(level1) input port i (line **xplipnd.v(3)) width 32 mismatch with (2 * i) + 1 width 64 3 | **xplipnd.v(22) WARN** [602] x1(level2) input port i (line **xplipnd.v(12)) width 32 mismatch with 3 * i width 64 4 | **xplipnd.v(23) WARN** [602] x2(level2) input port i (line **xplipnd.v(12)) width 32 mismatch with (3 * i) + 1 width 64 5 | **xplipnd.v(29) WARN** [602] x1(level3) input port i (line **xplipnd.v(19)) width 32 mismatch with 4 * i width 64 6 | **xplipnd.v(30) WARN** [602] x2(level3) input port i (line **xplipnd.v(19)) width 32 mismatch with (4 * i) + 1 width 64 7 | **xplipnd.v(36) WARN** [602] x1(level4) input port i (line **xplipnd.v(26)) width 32 mismatch with 4 * i width 64 8 | **xplipnd.v(37) WARN** [602] x2(level4) input port i (line **xplipnd.v(26)) width 32 mismatch with (4 * i) + 1 width 64 9 | i=0,p1=500,p2=501 10 | i=1,p1=502,p2=503 11 | i=2,p1=500,p2=501 12 | i=3,p1=502,p2=503 13 | i=6,p1=500,p2=501 14 | i=7,p1=502,p2=503 15 | i=8,p1=500,p2=501 16 | i=9,p1=502,p2=503 17 | i=24,p1=500,p2=501 18 | i=25,p1=502,p2=503 19 | i=26,p1=500,p2=501 20 | i=27,p1=502,p2=503 21 | i=30,p1=500,p2=501 22 | i=31,p1=502,p2=503 23 | i=32,p1=500,p2=501 24 | i=33,p1=502,p2=503 25 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/xplipnd.v: -------------------------------------------------------------------------------- 1 | // instance identity test 2 | 3 | module level1(i); 4 | input [31:0] i; 5 | parameter p1 = 0, p2 = 0; 6 | initial 7 | begin 8 | #1 $display("i=%0d,p1=%0d,p2=%0d", i, p1, p2); 9 | end 10 | endmodule 11 | 12 | module level2(i); 13 | input [31:0] i; 14 | parameter p1 = 0, p2 = 0; 15 | level1 #(.p1(500), .p2(501)) x1(2*i); 16 | level1 #(.p1(502), .p2(503)) x2(2*i + 1); 17 | endmodule 18 | 19 | module level3(i); 20 | input [31:0] i; 21 | parameter p1 = 0, p2 = 0; 22 | level2 #(.p1(400), .p2(401)) x1(3*i); 23 | level2 #(.p2(403), .p1(402)) x2(3*i + 1); 24 | endmodule 25 | 26 | module level4(i); 27 | input [31:0] i; 28 | parameter p1 = 0, p2 = 0; 29 | level3 #(.p1(300), .p2(301)) x1(4*i); 30 | level3 #(.p1(302), .p2(303)) x2(4*i + 1); 31 | endmodule 32 | 33 | module level5(i); 34 | input [31:0] i; 35 | parameter p1 = 0, p2 = 0; 36 | level4 #(.p1(200), .p2(201)) x1(4*i); 37 | level4 #(.p1(202), .p2(203)) x2(4*i + 1); 38 | endmodule 39 | 40 | module top; 41 | integer i; 42 | 43 | initial i = 0; 44 | level5 #(100,101) t1(i); 45 | /* -- 46 | defparam t1.x1.x1.x1.x1.p1 = 1'h1; 47 | defparam t1.x1.x1.x1.x2.p1 = 2'h2; 48 | defparam t1.x1.x1.x2.x1.p1 = 3'h3; 49 | defparam t1.x1.x1.x2.x2.p1 = 4'h4; 50 | 51 | defparam t1.x1.x2.x1.x1.p1 = 5'h5; 52 | defparam t1.x1.x2.x1.x2.p1 = 6'h6; 53 | defparam t1.x1.x2.x2.x1.p1 = 7'h7; 54 | defparam t1.x1.x2.x2.x2.p1 = 8'h8; 55 | 56 | defparam t1.x2.x1.x1.x1.p1 = 9'h9; 57 | defparam t1.x2.x1.x1.x2.p1 = 10'ha; 58 | defparam t1.x2.x1.x2.x1.p1 = 11'hb; 59 | defparam t1.x2.x1.x2.x2.p1 = 12'hc; 60 | 61 | defparam t1.x2.x2.x1.x1.p1 = 13'hd; 62 | defparam t1.x2.x2.x1.x2.p1 = 14'he; 63 | defparam t1.x2.x2.x2.x1.p1 = 15'hf; 64 | defparam t1.x2.x2.x2.x2.p1 = 16'h10; 65 | defparam t1.x2.x2.x2.x2.p2 = 93'h3f01; 66 | -- */ 67 | endmodule 68 | -------------------------------------------------------------------------------- /tests_and_examples/install.test/xxdel.tst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/install.test/xxdel.tst -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/README: -------------------------------------------------------------------------------- 1 | 2 | To run this test, type: 3 | 4 | %cvc +verbose -f run.flist 5 | 6 | 7 | You may need to make minor changes to 'run.flist' to get it to run in your 8 | simulation environment or pass in the file list using the proper option 9 | for your simulator. The +verbose option is needed by CVC to cause 10 | progress messages and simulation times to be printed. To inhibit messages, 11 | use the -q flag. 12 | 13 | All source code provided here is owned by their respective owners. See 14 | licensing details in Verilog source or www.opencores.com for more information 15 | or to download the original design source. 16 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/doc/README.txt: -------------------------------------------------------------------------------- 1 | 2 | The WISHBONE AC97 Controller Project Page is: 3 | http://www.opencores.org/cores/ac97/ 4 | 5 | To find out more about me (Rudolf Usselmann), please visit: 6 | http://www.asics.ws 7 | 8 | Directory Structure 9 | ------------------- 10 | [core_root] 11 | | 12 | +-doc Documentation 13 | | 14 | +-bench--+ Test Bench 15 | | +- verilog Verilog Sources 16 | | +-vhdl VHDL Sources 17 | | 18 | +-rtl----+ Core RTL Sources 19 | | +-verilog Verilog Sources 20 | | +-vhdl VHDL Sources 21 | | 22 | +-sim----+ 23 | | +-rtl_sim---+ Functional verification Directory 24 | | | +-bin Makefiles/Run Scripts 25 | | | +-run Working Directory 26 | | | 27 | | +-gate_sim--+ Functional & Timing Gate Level 28 | | | Verification Directory 29 | | +-bin Makefiles/Run Scripts 30 | | +-run Working Directory 31 | | 32 | +-lint--+ Lint Directory Tree 33 | | +-bin Makefiles/Run Scripts 34 | | +-run Working Directory 35 | | +-log Linter log & result files 36 | | 37 | +-syn---+ Synthesis Directory Tree 38 | | +-bin Synthesis Scripts 39 | | +-run Working Directory 40 | | +-log Synthesis log files 41 | | +-out Synthesis Output 42 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/doc/STATUS.txt: -------------------------------------------------------------------------------- 1 | This file describes the current status of the checked in HDL code. 2 | Please submit all bugs/comments/suggestions regarding the AC97 Controller 3 | core to: cores@opencores.org 4 | 5 | STATUS 6 | ====== 7 | 8 | Update (19/9/2002) 9 | ----------------- 10 | - Core successfully tested in hardware 11 | 12 | Update (8/2/2001) 13 | ----------------- 14 | - Changed Directory structure 15 | 16 | Initial Release (19/5/2001) 17 | --------------------------- 18 | - This is the very first release of the core 19 | - There might be still many bugs ! Only little testing has been done ! 20 | - Things that are not implemented yet, or are known not to work yet: 21 | - No Support for AC97 Modem Codecs (This is an optional item in AC97) 22 | 23 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/doc/ac97_doc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ac97/doc/ac97_doc.pdf -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/run.flist: -------------------------------------------------------------------------------- 1 | bench/verilog/ac97_codec_sin.v 2 | bench/verilog/ac97_codec_sout.v 3 | bench/verilog/ac97_codec_top.v 4 | bench/verilog/test_bench_top.v 5 | bench/verilog/wb_mast_model.v 6 | rtl/verilog/ac97_cra.v 7 | rtl/verilog/ac97_dma_if.v 8 | rtl/verilog/ac97_dma_req.v 9 | rtl/verilog/ac97_fifo_ctrl.v 10 | rtl/verilog/ac97_in_fifo.v 11 | rtl/verilog/ac97_int.v 12 | rtl/verilog/ac97_out_fifo.v 13 | rtl/verilog/ac97_prc.v 14 | rtl/verilog/ac97_rf.v 15 | rtl/verilog/ac97_rst.v 16 | rtl/verilog/ac97_sin.v 17 | rtl/verilog/ac97_soc.v 18 | rtl/verilog/ac97_sout.v 19 | rtl/verilog/ac97_top.v 20 | rtl/verilog/ac97_wb_if.v 21 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/syn/bin/design_spec.dc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Design Specification 4 | # 5 | # Author: Rudolf Usselmann 6 | # rudi@asics.ws 7 | # 8 | # Revision: 9 | # 3/7/01 RU Initial Sript 10 | # 11 | # 12 | ############################################################################### 13 | 14 | # ============================================== 15 | # Setup Design Parameters 16 | 17 | set design_files {ac97_fifo_ctrl ac97_dma_req ac97_cra ac97_prc ac97_soc ac97_in_fifo ac97_rf ac97_sout ac97_dma_if ac97_int ac97_rst ac97_out_fifo ac97_sin ac97_wb_if ac97_top} 18 | 19 | set design_name ac97_top 20 | set active_design ac97_top 21 | 22 | # Next Statement defines all clocks and resets in the design 23 | set special_net {rst clk bit_clk} 24 | 25 | set hdl_src_dir ../../rtl/verilog/ 26 | 27 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ac97/syn/bin/lib_spec.dc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Library Specification 4 | # 5 | # Author: Rudolf Usselmann 6 | # rudi@asics.ws 7 | # 8 | # Revision: 9 | # 3/7/01 RU Initial Sript 10 | # 11 | # 12 | ############################################################################### 13 | 14 | # ============================================== 15 | # Setup Libraries 16 | 17 | set search_path [list $search_path . \ 18 | /tools/dc_libraries/umc/umc_0.18/UMCL18U250D2_2.1/design_compiler/ \ 19 | $hdl_src_dir] 20 | 21 | set snps [getenv "SYNOPSYS"] 22 | 23 | set synthetic_library "" 24 | append synthetic_library $snps "/libraries/syn/dw01.sldb " 25 | append synthetic_library $snps "/libraries/syn/dw02.sldb " 26 | append synthetic_library $snps "/libraries/syn/dw03.sldb " 27 | append synthetic_library $snps "/libraries/syn/dw04.sldb " 28 | append synthetic_library $snps "/libraries/syn/dw05.sldb " 29 | append synthetic_library $snps "/libraries/syn/dw06.sldb " 30 | append synthetic_library $snps "/libraries/syn/dw07.sldb " 31 | 32 | set target_library { umcl18u250t2_typ.db } 33 | set link_library "" 34 | append link_library $target_library " " $synthetic_library 35 | set symbol_library { umcl18u250t2.sdb } 36 | 37 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/doc/preliminary_ata_core.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ata/doc/preliminary_ata_core.pdf -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/doc/src/ata_core.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ata/doc/src/ata_core.doc -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/rtl/verilog/ocidec-1/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/rtl/verilog/ocidec-2/revision_history.txt: -------------------------------------------------------------------------------- 1 | ----------------------------- 2 | Revision: 1.0 3 | Date: februar 18th, 2002 4 | Author: Richard Herveille 5 | - initial Verilog release 6 | ----------------------------- 7 | 8 | ----------------------------- 9 | Revision: 1.1 10 | Date: May 19th, 2002. 11 | Author: Richard Herveille 12 | - Fixed a potential bug that forced the core into an unknown state 13 | when an asynchronous reset was given without a running clock 14 | ----------------------------- 15 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/rtl/verilog/ocidec-2/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/rtl/vhdl/ocidec3/revision_history.txt: -------------------------------------------------------------------------------- 1 | ----------------------------- 2 | Revision: 1.0 3 | Date: march 22nd, 2001 4 | Author: Richard Herveille 5 | - initial release 6 | ----------------------------- 7 | 8 | ----------------------------- 9 | Revision: 1.0a 10 | Date: april 12th, 2001 11 | Author: Richard Herveille 12 | - removed records.vhd 13 | - removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools 14 | - fixed a minor bug where core didn't respond to IDEen bit. 15 | ----------------------------- 16 | 17 | ----------------------------- 18 | Revision: 1.1 19 | Date: june 18th, 2001 20 | Author: Richard Herveille 21 | - Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) 22 | ----------------------------- 23 | 24 | ----------------------------- 25 | Revision: 1.1a 26 | Date: june 19th, 2001 27 | Author: Richard Herveille 28 | - Simplified DAT_O output multiplexor 29 | ----------------------------- 30 | 31 | ----------------------------- 32 | Revision: 1.3 33 | Date: July 11th, 2001 34 | Author: Richard Herveille 35 | - renamed 'ata.vhd' to 'atahost.vhd' 36 | - Changed 'go' & 'igo' generation (pio_tctrl.vhdl). 37 | ----------------------------- 38 | 39 | ----------------------------- 40 | Revision: 1.4 41 | Date: Februar 17th, 2002 42 | Author: Richard Herveille 43 | - renamed all files to 'atahost_***.vhd' 44 | - broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' 45 | - changed resD input to generic RESD in ud_cnt.vhd 46 | - changed ID input to generic ID in ro_cnt.vhd 47 | - changed core to reflect changes in ro_cnt.vhd 48 | - removed references to 'count' library 49 | - changed IO names 50 | - added disclaimer 51 | - added CVS log 52 | - moved registers and wishbone signals into 'atahost_wb_slave.vhd' 53 | ----------------------------- 54 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/run.flist: -------------------------------------------------------------------------------- 1 | bench/verilog/ata_device.v 2 | bench/verilog/test_bench_top.v 3 | bench/verilog/wb_mast_model.v 4 | rtl/verilog/ocidec-1/atahost_controller.v 5 | rtl/verilog/ocidec-1/atahost_pio_tctrl.v 6 | rtl/verilog/ocidec-1/atahost_top.v 7 | rtl/verilog/ocidec-1/atahost_wb_slave.v 8 | rtl/verilog/ocidec-1/ro_cnt.v 9 | rtl/verilog/ocidec-1/ud_cnt.v 10 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/syn/bin/design_spec.dc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Design Specification 4 | # 5 | # Author: Rudolf Usselmann 6 | # rudi@asics.ws 7 | # 8 | # Revision: 9 | # 3/7/01 RU Initial Sript 10 | # 11 | # 12 | ############################################################################### 13 | 14 | # ============================================== 15 | # Setup Design Parameters 16 | 17 | set design_files {ud_cnt ro_cnt atahost_pio_tctrl atahost_controller atahost_top} 18 | 19 | set design_name atahost_top 20 | set active_design atahost_top 21 | 22 | # Next Statement defines all clocks and resets in the design 23 | set special_net {wb_rst_i rst_nreset_i wb_clk_i} 24 | 25 | set hdl_src_dir ../../rtl/verilog/ocidec-1/ 26 | 27 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/syn/bin/lib_spec.dc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Library Specification 4 | # 5 | # Author: Rudolf Usselmann 6 | # rudi@asics.ws 7 | # 8 | # Revision: 9 | # 3/7/01 RU Initial Sript 10 | # 11 | # 12 | ############################################################################### 13 | 14 | # ============================================== 15 | # Setup Libraries 16 | 17 | set search_path [list $search_path . \ 18 | /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ 19 | $hdl_src_dir] 20 | 21 | set snps [getenv "SYNOPSYS"] 22 | 23 | set synthetic_library "" 24 | append synthetic_library $snps "/libraries/syn/dw01.sldb " 25 | append synthetic_library $snps "/libraries/syn/dw02.sldb " 26 | append synthetic_library $snps "/libraries/syn/dw03.sldb " 27 | append synthetic_library $snps "/libraries/syn/dw04.sldb " 28 | append synthetic_library $snps "/libraries/syn/dw05.sldb " 29 | append synthetic_library $snps "/libraries/syn/dw06.sldb " 30 | append synthetic_library $snps "/libraries/syn/dw07.sldb " 31 | 32 | set target_library { umcl18u250t2_typ.db } 33 | set link_library "" 34 | append link_library $target_library " " $synthetic_library 35 | set symbol_library { umcl18u250t2.sdb } 36 | 37 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ata/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/run.flist: -------------------------------------------------------------------------------- 1 | bench/verilog/can_testbench.v 2 | rtl/verilog/can_acf.v 3 | rtl/verilog/can_bsp.v 4 | rtl/verilog/can_btl.v 5 | rtl/verilog/can_crc.v 6 | rtl/verilog/can_fifo.v 7 | rtl/verilog/can_ibo.v 8 | rtl/verilog/can_register_asyn_syn.v 9 | rtl/verilog/can_registers.v 10 | rtl/verilog/can_register_asyn.v 11 | rtl/verilog/can_register.v 12 | rtl/verilog/can_top.v 13 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/can/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/bin/cds.lib: -------------------------------------------------------------------------------- 1 | # 2 | # cds.lib: Defines the locations of compiled libraries. 3 | # Created by ncprep on Tue Jul 3 11:40:44 2001 4 | # 5 | 6 | define worklib ./INCA_libs/worklib 7 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/bin/hdl.var: -------------------------------------------------------------------------------- 1 | # 2 | # hdl.var: Defines variables used by the INCA tools. 3 | # Created by ncprep on Tue Jul 3 11:40:44 2001 4 | # 5 | 6 | softinclude $CDS_INST_DIR/tools/inca/files/hdl.var 7 | 8 | define LIB_MAP ( $LIB_MAP, + => worklib ) 9 | define VIEW_MAP ( $VIEW_MAP, .v => v) 10 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/bin/memory_file_list: -------------------------------------------------------------------------------- 1 | art_hstp_64x4_bist.v 2 | art_hstp_64x8_bist.v 3 | art_hsdp_64x8/art_hsdp_64x8.v 4 | art_hsdp_64x4/art_hsdp_64x4.v 5 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/bin/rtl_file_list: -------------------------------------------------------------------------------- 1 | can_btl.v 2 | can_registers.v 3 | can_register.v 4 | can_register_asyn.v 5 | can_register_syn.v 6 | can_register_asyn_syn.v 7 | can_top.v 8 | can_bsp.v 9 | can_crc.v 10 | can_acf.v 11 | can_fifo.v 12 | can_ibo.v 13 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/bin/sim_file_list: -------------------------------------------------------------------------------- 1 | timescale.v 2 | can_testbench_defines.v 3 | can_testbench.v 4 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/log/dir_keeper: -------------------------------------------------------------------------------- 1 | Only keeper of empty directories 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/out/dir_keeper: -------------------------------------------------------------------------------- 1 | Only keeper of empty directories 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/sim/rtl_sim/run/clean: -------------------------------------------------------------------------------- 1 | rm ../bin/INCA_libs/worklib/* 2 | rm ../bin/INCA_libs/worklib/.* 3 | rm ../log/*.log 4 | rm -rf ../out/*.shm 5 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/syn/libero/pinedit.gcf: -------------------------------------------------------------------------------- 1 | set_io "H5" "clkout_o"; 2 | set_io "M2" "tx_o"; 3 | set_io "J1" "wb_rst_i"; 4 | set_io "M3" "rx_i"; 5 | set_io "H1" "clk_i"; 6 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/can/syn/synplicity/rev_1/dir_keeper: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/can/syn/synplicity/rev_1/dir_keeper -------------------------------------------------------------------------------- /tests_and_examples/open_cores/cvc-open-core-sim-times.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/cvc-open-core-sim-times.pdf -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/ethernet_rx.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ethernet/ethernet_rx.log -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/ethernet_tx.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ethernet/ethernet_tx.log -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/log/eth_tb_host.log: -------------------------------------------------------------------------------- 1 | ================ HOST Module Testbench access log ================ 2 | 3 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/log/eth_tb_memory.log: -------------------------------------------------------------------------------- 1 | =============== MEMORY Module Testbench access log =============== 2 | 3 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/log/eth_tb_phy.log: -------------------------------------------------------------------------------- 1 | ================ PHY Module Testbench access log ================ 2 | 3 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/log/eth_tb_wb_m_mon.log: -------------------------------------------------------------------------------- 1 | ============= WISHBONE Master Bus Monitor error log ============= 2 | 3 | Only ERRONEOUS conditions are logged ! 4 | 5 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/log/eth_tb_wb_s_mon.log: -------------------------------------------------------------------------------- 1 | ============== WISHBONE Slave Bus Monitor error log ============== 2 | 3 | Only ERRONEOUS conditions are logged ! 4 | 5 | Time: 8071935 6 | tb_ethernet.wb_eth_slave_bus_mon.message_out, Slave provided invalid data during read and qualified it with ACK_I 7 | Byte select value: SEL_O = 1111, Data bus value: DAT_I = 0000zzzz 8 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/rtl/ethernet_rx.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ethernet/rtl/ethernet_rx.log -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/rtl/ethernet_tx.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/ethernet/rtl/ethernet_tx.log -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/rtl/ram16x1d.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/s/RAM16X1D.v,v 1.7.18.1 2002/11/04 23:31:33 patrickp Exp $ 2 | 3 | /* 4 | 5 | FUNCTION : 16x1 Dual Port Static RAM with synchronous write capability 6 | 7 | */ 8 | 9 | `timescale 100 ps / 10 ps 10 | 11 | 12 | module RAM16X1D (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE); 13 | 14 | parameter INIT = 16'h0000; 15 | 16 | output DPO, SPO; 17 | 18 | input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE; 19 | 20 | reg mem [15:0]; 21 | reg [4:0] count; 22 | wire [3:0] adr; 23 | wire [3:0] dpr_adr; 24 | wire d_in, wclk_in, we_in; 25 | 26 | buf b_d (d_in, D); 27 | buf b_wclk (wclk_in, WCLK); 28 | buf b_we (we_in, WE); 29 | 30 | buf b_a3 (adr[3], A3); 31 | buf b_a2 (adr[2], A2); 32 | buf b_a1 (adr[1], A1); 33 | buf b_a0 (adr[0], A0); 34 | 35 | buf b_d3 (dpr_adr[3], DPRA3); 36 | buf b_d2 (dpr_adr[2], DPRA2); 37 | buf b_d1 (dpr_adr[1], DPRA1); 38 | buf b_d0 (dpr_adr[0], DPRA0); 39 | 40 | buf b_spo (SPO, spo_int); 41 | buf b_dpo (DPO, dpo_int); 42 | 43 | buf b_spo_int (spo_int, mem[adr]); 44 | buf b_dpo_int (dpo_int, mem[dpr_adr]); 45 | 46 | initial 47 | begin 48 | for (count = 0; count < 16; count = count + 1) 49 | mem[count] <= INIT[count]; 50 | 51 | end 52 | 53 | always @(posedge wclk_in) 54 | begin 55 | if (we_in == 1'b1) 56 | mem[adr] <= d_in; 57 | end 58 | 59 | specify 60 | if (WE) 61 | (WCLK => SPO) = (1, 1); 62 | if (WE) 63 | (WCLK => DPO) = (1, 1); 64 | 65 | (A3 => SPO) = (1, 1); 66 | (A2 => SPO) = (1, 1); 67 | (A1 => SPO) = (1, 1); 68 | (A0 => SPO) = (1, 1); 69 | 70 | (DPRA3 => DPO) = (1, 1); 71 | (DPRA2 => DPO) = (1, 1); 72 | (DPRA1 => DPO) = (1, 1); 73 | (DPRA0 => DPO) = (1, 1); 74 | endspecify 75 | 76 | endmodule 77 | 78 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/ethernet/run.flist: -------------------------------------------------------------------------------- 1 | bench/tb_ethernet.v 2 | rtl/eth_clockgen.v 3 | rtl/eth_crc.v 4 | rtl/eth_fifo.v 5 | rtl/eth_maccontrol.v 6 | rtl/eth_macstatus.v 7 | rtl/eth_miim.v 8 | rtl/eth_outputcontrol.v 9 | rtl/eth_phy.v 10 | rtl/eth_random.v 11 | rtl/eth_receivecontrol.v 12 | rtl/eth_registers.v 13 | rtl/eth_register.v 14 | rtl/eth_rxaddrcheck.v 15 | rtl/eth_rxcounters.v 16 | rtl/eth_rxethmac.v 17 | rtl/eth_rxstatem.v 18 | rtl/eth_shiftreg.v 19 | rtl/eth_spram_256x32.v 20 | rtl/eth_top.v 21 | rtl/eth_transmitcontrol.v 22 | rtl/eth_txcounters.v 23 | rtl/eth_txethmac.v 24 | rtl/eth_txstatem.v 25 | rtl/eth_wishbone.v 26 | rtl/wb_bus_mon.v 27 | rtl/wb_master32.v 28 | rtl/wb_master_behavioral.v 29 | rtl/wb_slave_behavioral.v 30 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/generic_fifos/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/generic_fifos/rtl/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/generic_fifos/run.flist: -------------------------------------------------------------------------------- 1 | bench/verilog/test_bench_top.v 2 | rtl/verilog/generic_fifo_dc.v 3 | rtl/verilog/generic_fifo_sc_b.v 4 | rtl/verilog/timescale.v 5 | generic_dpram.v 6 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/generic_fifos/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/README_VERILATOR.txt: -------------------------------------------------------------------------------- 1 | This example was used to generate 2 | 3 | http://www.veripool.com/verilog_sim_benchmarks.html 4 | 5 | The code herein was from http://www.opencores.org 6 | 7 | To run the benchmarks 8 | 9 | cd sim 10 | make (simulator-name) 11 | 12 | You'll need to do several runs to avoid startup effects, and run another 13 | test with 0 simulation cycles so you can subtract off initialization 14 | effects. 15 | 16 | 17 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/cvc.log: -------------------------------------------------------------------------------- 1 | Highest level modules: 2 | bench 3 | Begin compiled design load: 4 | Begin simulation: 5 | 6 | 7 | Halted at location **bench/bench.v(58) time 100000040000 ps from call to $finish. 8 | Times (in sec.): Translate 0.0, load/optimize 0.1, simulation 10.3. 9 | There were 0 error(s), 0 warning(s), and 265 inform(s). 10 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/input.vc: -------------------------------------------------------------------------------- 1 | +librescan +libext+.v 2 | -y ../bench 3 | -y ../rtl 4 | +incdir+../bench 5 | +incdir+../rtl 6 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/rtl/k68_sasc.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module k68_sasc (/*AUTOARG*/ 4 | // Outputs 5 | tx_o, rts_o, dat_o, 6 | // Inputs 7 | clk_i, rst_i, cts_i, rx_i, dat_i, cs_i, we_i 8 | ) ; 9 | 10 | // Change these to set the baud rate for the SASC 11 | parameter div0 = 8'd1; 12 | parameter div1 = 8'd217; 13 | 14 | input clk_i,rst_i; 15 | 16 | // IO 17 | output tx_o, rts_o; 18 | input cts_i, rx_i; 19 | 20 | // Mem 21 | //input add_i; 22 | input [23:0] dat_i; 23 | input cs_i, we_i; 24 | output [9:0] dat_o; 25 | //reg [7:0] dat_o; 26 | 27 | wire [7:0] din; 28 | wire [7:0] dout; 29 | 30 | wire empty_o,full_o,sio_ce,sio_ce_x4; 31 | //reg we,wen; 32 | wire nrst; 33 | wire [7:0] brg0,brg1; 34 | wire re; 35 | 36 | assign re = cs_i & !we_i; 37 | 38 | assign {brg1,brg0,din} = dat_i; 39 | assign dat_o = {full_o,empty_o,dout}; 40 | assign nrst = ~rst_i; 41 | 42 | sasc_top sasc_top0( 43 | .rxd_i(rx_i), 44 | .txd_o(tx_o), 45 | .cts_i(cts_i), 46 | .rts_o(rts_o), 47 | 48 | .sio_ce(sio_ce), 49 | .sio_ce_x4(sio_ce_x4), 50 | 51 | .din_i(din), 52 | .dout_o(dout), 53 | 54 | .re_i(re), 55 | .we_i(we_i), 56 | 57 | .full_o(full_o), 58 | .empty_o(empty_o), 59 | 60 | .clk(clk_i),.rst(nrst) 61 | ); 62 | 63 | sasc_brg sasc_brg0( 64 | .sio_ce(sio_ce), 65 | .sio_ce_x4(sio_ce_x4), 66 | .div0(brg0), 67 | .div1(brg1), 68 | .clk(clk_i), .rst(nrst) 69 | ); 70 | 71 | 72 | endmodule // k68_sasc 73 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/rtl/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/run.flist: -------------------------------------------------------------------------------- 1 | bench/bench.v 2 | bench/k68_soc_test.v 3 | bench/k68_testram.v 4 | bench/k68_testrom.v 5 | rtl/k68_arb.v 6 | rtl/k68_b2d.v 7 | rtl/k68_buni.v 8 | rtl/k68_calc.v 9 | rtl/k68_ccc.v 10 | rtl/k68_clkgen.v 11 | rtl/k68_cpu.v 12 | rtl/k68_d2b.v 13 | rtl/k68_decode.v 14 | rtl/k68_dpmem.v 15 | rtl/k68_execute.v 16 | rtl/k68_fetch.v 17 | rtl/k68_load.v 18 | rtl/k68_regbank.v 19 | rtl/k68_rox.v 20 | rtl/k68_sasc.v 21 | rtl/k68_soc.v 22 | rtl/sasc_brg.v 23 | rtl/sasc_fifo4.v 24 | rtl/sasc_top.v 25 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/sim/DEBUG_oprofile: -------------------------------------------------------------------------------- 1 | opreport -g -d -d --symbols obj_dir/m68 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/m68k/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/sha1/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/sha1/dffhr.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////// 2 | // dffhr.v version 0.1 3 | // 4 | // Standard parameterizable synchronous reset D-type flipflop 5 | // 6 | // Paul Hartke, phartke@stanford.edu, Copyright (c)2002 7 | // 8 | // The information and description contained herein is the 9 | // property of Paul Hartke. 10 | // 11 | // Permission is granted for any reuse of this information 12 | // and description as long as this copyright notice is 13 | // preserved. Modifications may be made as long as this 14 | // notice is preserved. 15 | // This code is made available "as is". There is no warranty, 16 | // so use it at your own risk. 17 | // Documentation? "Use the source, Luke!" 18 | /////////////////////////////////////////////////////////////// 19 | 20 | module dffhr (d, r, clk, q); 21 | parameter WIDTH = 1; 22 | input r; 23 | input clk; 24 | input [WIDTH-1:0] d; 25 | output [WIDTH-1:0] q; 26 | reg [WIDTH-1:0] q; 27 | wire [WIDTH-1:0] d_d; 28 | assign #0 d_d=d; 29 | 30 | always @ (posedge clk) 31 | if ( r ) 32 | q <= {WIDTH{1'b1}}; 33 | else 34 | q <= d_d; 35 | 36 | endmodule // dffhr 37 | 38 | 39 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/sha1/run.flist: -------------------------------------------------------------------------------- 1 | dffhr.v 2 | sha1_exec.v 3 | sha1_round.v 4 | sha1_testbench.v 5 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/sha1/sha1_readme_v01.txt: -------------------------------------------------------------------------------- 1 | // Paul Hartke, phartke@stanford.edu, Copyright (c)2002 2 | // 3 | // The information and description contained herein is the 4 | // property of Paul Hartke. 5 | // 6 | // Permission is granted for any reuse of this information 7 | // and description as long as this copyright notice is 8 | // preserved. Modifications may be made as long as this 9 | // notice is preserved. 10 | // This code is made available "as is". There is no warranty, 11 | // so use it at your own risk. 12 | // Documentation? "Use the source, Luke!" 13 | 14 | sha1_readme.txt version 0.1 15 | Paul Hartke 16 | phartke@stanford.edu 17 | September 28, 2002 18 | 19 | SHA-1 is defined in NIST FIPS 180-2, Secure Hash Standard 20 | (SHS), August 2002. However, William Stalling's 21 | "Cryptography and Network Security, Principles and Practice, 22 | 2nd Ed." has a very through description and is an all 23 | around great crypto book. 24 | 25 | Files included in this distribution are: 26 | sha1_testbench.v 27 | -- Testbench with vectors from NIST FIPS 180-2 28 | sha1_exec.v 29 | -- Top level sha1 module 30 | sha1_round.v 31 | -- primitive sha1 round 32 | dffhr.v 33 | -- generic parameterizable D-flip flop library 34 | 35 | Performance Analysis 36 | Performance equation of core is 37 | frequency in MHz * (512bits/block) / (81 rounds/block). The 38 | cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7 39 | FPGA which results in 700 Mbps processing rate. 40 | Note: This calculation ignores the effect of a partially full 41 | last block 42 | 43 | Finally, Padding, HMAC, and bus interface functionality is not 44 | provided. These will vary with the particular system design. 45 | 46 | The core size is about 800 Xilinx Virtex II FPGA Family Slices. 47 | 48 | I welcome feedback on any aspects of this design. 49 | 50 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/generic_fifos/generic_fifos/rtl/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/run.flist: -------------------------------------------------------------------------------- 1 | usb1_funct/rtl/verilog/usb1_utmi_if.v 2 | usb1_funct/rtl/verilog/usb1_core.v 3 | usb1_funct/rtl/verilog/usb1_crc16.v 4 | usb1_funct/rtl/verilog/usb1_crc5.v 5 | usb1_funct/rtl/verilog/usb1_ctrl.v 6 | usb1_funct/rtl/verilog/usb1_fifo2.v 7 | usb1_funct/rtl/verilog/usb1_idma.v 8 | usb1_funct/rtl/verilog/usb1_pa.v 9 | usb1_funct/rtl/verilog/usb1_pd.v 10 | usb1_funct/rtl/verilog/usb1_pe.v 11 | usb1_funct/rtl/verilog/usb1_pl.v 12 | usb1_funct/rtl/verilog/usb1_rom1.v 13 | usb1_funct/bench/verilog/test_bench_top.v 14 | usb_phy/rtl/verilog/usb_tx_phy.v 15 | usb_phy/rtl/verilog/usb_phy.v 16 | usb_phy/rtl/verilog/usb_rx_phy.v 17 | generic_fifos/generic_fifos/rtl/verilog/generic_fifo_sc_a.v 18 | generic_fifos/common/generic_memories/rtl/verilog/generic_dpram.v 19 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/usb1_funct/bench/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/usb1_funct/doc/success_story.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/usb11/usb1_funct/doc/success_story.txt -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/usb1_funct/rtl/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/usb11/usb_phy/rtl/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/wb_dma/README: -------------------------------------------------------------------------------- 1 | 2 | This package was downloaded from 3 | 4 | www.tachyon-da.com/verilog_benchmarks.htm 5 | 6 | It is used for Verilog simulator benchmarking. To run your Verilog simulator 7 | just pass the file list. For CVC, you would type: 8 | 9 | %cvc +verbose -f run.flist 10 | 11 | You may need to make minor changes to 'run.flist' to get it to run in your 12 | simulation environment or pass in the file list using the proper option 13 | for your simulator. The +verbose option is needed by CVC to cause 14 | progress messages and simulation times to be printed. To inhibit messages, 15 | use the -q flag. 16 | 17 | All source code provided here is owned by their respective owners. See 18 | licensing details in Verilog source or www.opencores.com for more information 19 | or to download the original design source. 20 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/wb_dma/doc/README.txt: -------------------------------------------------------------------------------- 1 | 2 | The WISHBONE DMA/Bridge Project Page is: 3 | http://www.opencores.org/cores/wb_dma/ 4 | 5 | To find out more about me (Rudolf Usselmann), please visit: 6 | http://www.asics.ws 7 | 8 | Directory Structure 9 | ------------------- 10 | [core_root] 11 | | 12 | +-doc Documentation 13 | | 14 | +-bench--+ Test Bench 15 | | +- verilog Verilog Sources 16 | | +-vhdl VHDL Sources 17 | | 18 | +-rtl----+ Core RTL Sources 19 | | +-verilog Verilog Sources 20 | | +-vhdl VHDL Sources 21 | | 22 | +-sim----+ 23 | | +-rtl_sim---+ Functional verification Directory 24 | | | +-bin Makefiles/Run Scripts 25 | | | +-run Working Directory 26 | | | 27 | | +-gate_sim--+ Functional & Timing Gate Level 28 | | | Verification Directory 29 | | +-bin Makefiles/Run Scripts 30 | | +-run Working Directory 31 | | 32 | +-lint--+ Lint Directory Tree 33 | | +-bin Makefiles/Run Scripts 34 | | +-run Working Directory 35 | | +-log Linter log & result files 36 | | 37 | +-syn---+ Synthesis Directory Tree 38 | | +-bin Synthesis Scripts 39 | | +-run Working Directory 40 | | +-log Synthesis log files 41 | | +-out Synthesis Output 42 | 43 | 44 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/wb_dma/doc/dma_doc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/tests_and_examples/open_cores/wb_dma/doc/dma_doc.pdf -------------------------------------------------------------------------------- /tests_and_examples/open_cores/wb_dma/run.flist: -------------------------------------------------------------------------------- 1 | bench/verilog/test_bench_top.v 2 | bench/verilog/wb_mast_model.v 3 | bench/verilog/wb_slv_model.v 4 | rtl/verilog/wb_dma_ch_arb.v 5 | rtl/verilog/wb_dma_ch_pri_enc.v 6 | rtl/verilog/wb_dma_ch_rf.v 7 | rtl/verilog/wb_dma_ch_sel.v 8 | rtl/verilog/wb_dma_de.v 9 | rtl/verilog/wb_dma_inc30r.v 10 | rtl/verilog/wb_dma_pri_enc_sub.v 11 | rtl/verilog/wb_dma_rf.v 12 | rtl/verilog/wb_dma_top.v 13 | rtl/verilog/wb_dma_wb_if.v 14 | rtl/verilog/wb_dma_wb_mast.v 15 | rtl/verilog/wb_dma_wb_slv.v 16 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/wb_dma/syn/bin/design_spec.dc: -------------------------------------------------------------------------------- 1 | ################################################################################# 2 | # 3 | # Design Specification 4 | # 5 | # Author: Rudolf Usselmann 6 | # rudi@asics.ws 7 | # 8 | # Revision: 9 | # 3/7/01 RU Initial Sript 10 | # 11 | # 12 | ################################################################################# 13 | 14 | # ============================================== 15 | # Setup Design Parameters 16 | 17 | set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top } 18 | 19 | set design_name wb_dma_top 20 | set active_design wb_dma_top 21 | 22 | # Next Statement defines all clocks and resets in the design 23 | set special_net {rst clk} 24 | 25 | set hdl_src_dir ../../rtl/verilog/ 26 | 27 | -------------------------------------------------------------------------------- /tests_and_examples/open_cores/wb_dma/syn/bin/lib_spec.dc: -------------------------------------------------------------------------------- 1 | ################################################################################# 2 | # 3 | # Library Specification 4 | # 5 | # Author: Rudolf Usselmann 6 | # rudi@asics.ws 7 | # 8 | # Revision: 9 | # 3/7/01 RU Initial Sript 10 | # 11 | # 12 | ################################################################################# 13 | 14 | # ============================================== 15 | # Setup Libraries 16 | 17 | set search_path [list $search_path . \ 18 | /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ 19 | $hdl_src_dir] 20 | 21 | set snps [getenv "SYNOPSYS"] 22 | 23 | set synthetic_library "" 24 | append synthetic_library $snps "/libraries/syn/dw01.sldb " 25 | append synthetic_library $snps "/libraries/syn/dw02.sldb " 26 | append synthetic_library $snps "/libraries/syn/dw03.sldb " 27 | append synthetic_library $snps "/libraries/syn/dw04.sldb " 28 | append synthetic_library $snps "/libraries/syn/dw05.sldb " 29 | append synthetic_library $snps "/libraries/syn/dw06.sldb " 30 | append synthetic_library $snps "/libraries/syn/dw07.sldb " 31 | 32 | set target_library { umcl18u250t2_wc.db } 33 | set link_library "" 34 | append link_library $target_library " " $synthetic_library 35 | set symbol_library { umcl18u250t2.sdb } 36 | 37 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/README.DA-SOLUTIONS.ORIGINAL.1999: -------------------------------------------------------------------------------- 1 | 2 | This directory contains the public domain Verilog test circuits from the 3 | DA Solutions Ltd. benchmark library used in DA Solutions commercial 4 | benchmark program back in the late 1990s. Since DA Solutions no longer 5 | is active, John Hillawi has kindly allowed us to make them available. 6 | 7 | Here is contents of John's original README file: 8 | 9 | -- This library was created by DA Solutions for the purposes 10 | -- of benchmarking Verilog simulation products. 11 | -- This directory contains the public domain portion of the DA 12 | -- Solutions library. Other proprietary circuits, provided by 13 | -- end users were also used in the evaluation, but these remain 14 | -- confidential to the end users and DA Solutions and are not 15 | -- included in this release. 16 | -- 17 | -- 18 | -- The circuits are: 19 | -- DA Solutions CPU circuit (das_cpu) 20 | -- DA Solutions Multiplier circuit (das_mult) 21 | -- DA Solutions LFSR circuit (das_lfsr) 22 | -- TI Multiplier circuit (ti_mult) 23 | -- 24 | -- Simple gate level libraries are also provided in the libs 25 | -- directory. However, the user is recommended to obtain fully 26 | -- functional libraries from the ASIC Manufacturers. with full 27 | -- functional coding, and full timing parameters, in order to 28 | -- exactly replicate the DA Solutions 1994 results. DA Solutions 29 | -- has no authority to ship such libraries with this tape. 30 | 31 | We have added a -f file to simplify execution and slightly modified 32 | the README file for each circuit. Otherwise the tests are exactly 33 | as DA Solutions released them. 34 | 35 | We have put them on our web site as a public service, and because we 36 | are in process of publishing papers on our new byte code virtual 37 | machine interpreter (selected using -O option) that use the 38 | benchmark circuits for measurements. 39 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/finish.inp: -------------------------------------------------------------------------------- 1 | $finish; 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/gen_untoggled_report_from_tgldat.vc: -------------------------------------------------------------------------------- 1 | // toggle test - run after run_all_toggle.vc 2 | 3 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 4 | +verbose 5 | 6 | -toggle 7 | -untoggled_report_concise 8 | // -mark_driven_const_wires_toggled 9 | // driven const report only needs to be output once 10 | // -driven_const_report_concise 11 | 12 | -set_toggled_from_file all-dascpu.tgldat 13 | 14 | // many .tgldat files from different runs could be combined into one report 15 | // by including additional -set_toggled_from_file options here 16 | 17 | // write reand .tgldat to new file so can diff - no sim so just read-write 18 | -write_toggle_data_file all-dascpu2.tgldat 19 | 20 | // this causes cvc64 to enter debug mode before starting simulation 21 | // this only works when +interp is chosen - but since there is no simulation 22 | // the compiler is not needed 23 | +interp -s 24 | // this file just contains "$finish;" to stop simulation before any toggling 25 | -i finish.inp 26 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/run_all_toggle.vc: -------------------------------------------------------------------------------- 1 | 2 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 3 | +verbose 4 | 5 | // various options to see how new CVC toggle processing works 6 | // das_cpu is interesting because nearly every signal is toggled 7 | // uncomment all 5 lines to see the full new toggle capabilities 8 | -toggle 9 | -untoggled_report_concise 10 | -mark_driven_const_wires_toggled 11 | -driven_const_report_concise 12 | -write_toggle_data_file all-dascpu.tgldat 13 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/run_fst_dumpvars.vc: -------------------------------------------------------------------------------- 1 | //**GTKWAVE**// 2 | 3 | //Mandatory for all testing 4 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 5 | +verbose 6 | 7 | //enables these to see FST dumping for gtkwave plus various parallel dumping 8 | //options to speed up FST processing 9 | +fstvars 10 | +fst+parallel2=on 11 | // +fst+parallel=on 12 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/run_optcfg_bits_exclude.vc: -------------------------------------------------------------------------------- 1 | //**CVC TOGGLE PROCESSING**// 2 | 3 | //Mandatory for all testing 4 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 5 | +verbose 6 | 7 | -optconfigfile tgl_tree.cfg 8 | -mark_driven_const_wires_toggled 9 | -untoggled_report_concise 10 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/run_optcfg_tree.vc: -------------------------------------------------------------------------------- 1 | //**CVC TOGGLE PROCESSING**// 2 | 3 | // +define+TGL_ON_AFTER_INIT+ 4 | // +define+TGL_OFF_NEGEDGE_CYCLE+ 5 | 6 | //Mandatory for all testing 7 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 8 | +verbose 9 | 10 | // must not use -toggle here because the tgl_some.cfg file includes the 11 | // cpu part of das_cpu (omits the test bench part) then exlcudes instances 12 | // one by one. This illustrates the toggle coverage verification approach 13 | // where once an instance is known to have good toggle coverage, it is 14 | // excluded from future testing 15 | -optconfigfile tgl_some.cfg 16 | -mark_driven_const_wires_toggled 17 | -untoggled_report_concise 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/run_tgl_on_off.vc: -------------------------------------------------------------------------------- 1 | 2 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 3 | +verbose 4 | // define to not record during initializaton - see cpu_mixed.v source 5 | +define+TGL_ON_AFTER_INIT+ 6 | // define to only record from when clk=1 and not record when clk=0 7 | +define+TGL_OFF_NEGEDGE_CYCLE+ 8 | 9 | // various options to see how new CVC toggle processing works 10 | // das_cpu is interesting because nearly every signal is toggled 11 | // uncomment all 5 lines to see the full new toggle capabilities 12 | -toggle 13 | -untoggled_report_concise 14 | // if const nets are marked, they will always be treated as "toggled" 15 | // -mark_driven_const_wires_toggled 16 | // -driven_const_report_concise 17 | -write_toggle_data_file all-dascpu.tgldat 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/run_xprop.vc: -------------------------------------------------------------------------------- 1 | //**XPROP**// 2 | 3 | //Mandatory for all testing 4 | cpu_mixed.v -y ../libs/lca100kgate +libext+.v 5 | +verbose 6 | 7 | //das_cpu is an old style design that will not run with +xprop 8 | //design does not initialize with new +xprop more pessimistic x feature 9 | +xprop 10 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_cpu/tgl_tree.cfg: -------------------------------------------------------------------------------- 1 | // turn on toggle coverage for the cpu 2 | tree (-1) {cpu} {cover_toggle}; 3 | // this exclude the design tree under fp_unit. fp_unit as a module works 4 | // because there is only one in the design 5 | tree_exclude (-1) {fp_unit} {cover_toggle}; 6 | // instance exclude is for both instances and nets 7 | // include all from toggle coverage except bit 5 - opcode will not be 8 | // in report because only bit 5 does not toggle but it is excluded 9 | instance_exclude {testbench.c1.o1.opcode[5]} {cover_toggle}; 10 | // uncomment this line to add fp_unit back into toggle covera part of design 11 | // tree (-1) {fp_unit} {cover_toggle}; 12 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr.sdf: -------------------------------------------------------------------------------- 1 | (DELAYFILE 2 | (SDFVERSION "3.0") 3 | (TIMESCALE 10ns) 4 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_2) 5 | (DELAY (ABSOLUTE (DEVICE (:0.1:))))) 6 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_3) 7 | (DELAY (ABSOLUTE (DEVICE (:0.1:))))) 8 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_7) 9 | (DELAY (ABSOLUTE (DEVICE (:0.1:))))) 10 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_1) 11 | (DELAY (ABSOLUTE (DEVICE (:0.2:))))) 12 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_4) 13 | (DELAY (ABSOLUTE (DEVICE (:0.1:))))) 14 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_5) 15 | (DELAY (ABSOLUTE (DEVICE (:0:))))) 16 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_6) 17 | (DELAY (ABSOLUTE (DEVICE (:0:))))) 18 | (CELL (CELLTYPE "FD2" ) (INSTANCE * nand_8) 19 | (DELAY (ABSOLUTE (DEVICE (:0:))))) 20 | (CELL (CELLTYPE "FD2" ) (INSTANCE * inv_1) 21 | (DELAY (ABSOLUTE (DEVICE (:0:))))) 22 | (CELL (CELLTYPE "FD2" ) (INSTANCE * inv_2) 23 | (DELAY (ABSOLUTE (DEVICE (:0:))))) 24 | ) 25 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr1000.vc: -------------------------------------------------------------------------------- 1 | lfsr1000.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr1000_no_sdf.vc: -------------------------------------------------------------------------------- 1 | lfsr1000.v -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr1000_nosdf.vc: -------------------------------------------------------------------------------- 1 | lfsr1000.v -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr16000.vc: -------------------------------------------------------------------------------- 1 | lfsr16000.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr2000.vc: -------------------------------------------------------------------------------- 1 | lfsr2000.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr32000.vc: -------------------------------------------------------------------------------- 1 | lfsr32000.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr4000.vc: -------------------------------------------------------------------------------- 1 | lfsr4000.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr500.vc: -------------------------------------------------------------------------------- 1 | lfsr500.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr500_nosdf.vc: -------------------------------------------------------------------------------- 1 | lfsr500.v -y ../libs/lca100kgate +libext+.v 2 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_lfsr/lfsr8000.vc: -------------------------------------------------------------------------------- 1 | lfsr8000.v +sdfannotate lfsr.sdf -y ../libs/lca100kgate +libext+.v 2 | -toggle 3 | -mark_driven_const_wires_toggled 4 | -driven_const_report_concise 5 | -untoggled_report_concise 6 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_mult/README: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- These source files may be used and distributed without 4 | -- restriction. 5 | -- 6 | -------------------------------------------------------------------- 7 | -- 8 | -- Author John Hillawi 9 | -- Names mult_gate.v 10 | -- ref_in 11 | ref_out 12 | -- Purpose This circuit was created for the purpose of 13 | -- comparing simulation performance at Gate 14 | -- Level. It has been placed in the 15 | -- public domain to act as an ongoing metric 16 | -- for comparing performance. 17 | -- 18 | -------------------------------------------------------------------- 19 | -- 20 | -- This circuit is a gate level model of a 56 x 56 bit 21 | -- multiplier matrix. The gate count is approximately 22 | -- 25,000 gates. 23 | -- 24 | -------------------------------------------------------------------- 25 | -- 26 | -- As a guide to running, a typical script (in this case 27 | -- Pragmatic C Software Cver) would be: 28 | -- 29 | -- cver -f mult_gate.vc 30 | -- 31 | -- To directly execute mult_gate.v, type this: 32 | -- 33 | -- cver mult_gate.v -y ../libs/lca100kgate +libext+.v 34 | -- 35 | -------------------------------------------------------------------- 36 | -- 37 | -- The simulation testbench reads pairs of 56 bit floating 38 | -- point numbers from a file (ref_in) and presents them 39 | -- to the multiplier matrix. The output is sampled and compared 40 | -- with reference outputs in the file ref_out. The file supplied is 41 | -- sufficient to run for 774100 ns. 42 | -- 43 | -------------------------------------------------------------------- 44 | 45 | 46 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/das_mult/mult_gate.vc: -------------------------------------------------------------------------------- 1 | mult_gate.v -y ../libs/lca100kgate +libext+.v 2 | // -mark_driven_const_wires_toggled 3 | // -driven_const_report_concise 4 | // -toggle 5 | // -untoggled_report_concise 6 | +fstvars 7 | +verbose 8 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/AN2.v: -------------------------------------------------------------------------------- 1 | module AN2(a, b, z); 2 | 3 | input a, b; 4 | output z; 5 | 6 | and #1 g1(z, a, b); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/AN3.v: -------------------------------------------------------------------------------- 1 | module AN3(a, b, c, z); 2 | 3 | input a, b, c; 4 | output z; 5 | 6 | and #1 g1(z, a, b, c); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/AN4.v: -------------------------------------------------------------------------------- 1 | module AN4(a, b, c, d, z); 2 | 3 | input a, b, c, d; 4 | output z; 5 | 6 | and #1 g1(z, a, b, c, d); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/AN5.v: -------------------------------------------------------------------------------- 1 | module AN5(a, b, c, d, e, z); 2 | 3 | input a, b, c, d, e; 4 | output z; 5 | 6 | and #1 g1(z, a, b, c, d, e); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/BUF8A.v: -------------------------------------------------------------------------------- 1 | module BUF8A(a, z); 2 | 3 | input a; 4 | output z; 5 | 6 | buf #1 g1(z, a); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/EN.v: -------------------------------------------------------------------------------- 1 | module EN (a, b, z); 2 | 3 | input a, b; 4 | output z; 5 | 6 | xnor #1 g1(z, a, b); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/FA1A.v: -------------------------------------------------------------------------------- 1 | module FA1A( ci, a, b, s, co ); 2 | 3 | input ci, a, b; 4 | output s, co; 5 | 6 | xor #1 l1(s, ci, a, b); 7 | and l2(x1, ci, a ); 8 | and l3(x2, ci, b ); 9 | and l4(x3, a, b ); 10 | or #1 l5(co, x1, x2, x3); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/FD2.v: -------------------------------------------------------------------------------- 1 | module FD2 (d, cp, cd, q, qn); 2 | 3 | input d, cp, cd; 4 | output q, qn; 5 | 6 | nand #1 nand_2 (n2, d_, cp_), 7 | nand_3 (n3, n1, n4), 8 | nand_7 (q, n5, qn); 9 | 10 | // SJM nand #0 nand_1 (n1, d, cp_, cd), 11 | nand nand_1 (n1, d, cp_, cd), 12 | nand_4 (n4, n2, n3, cd), 13 | nand_5 (n5, n3, cp), 14 | nand_6 (n6, n4, cp), 15 | nand_8 (qn, n6, cd, q); 16 | 17 | // SJM not #0 inv_1 (cp_, cp), 18 | not inv_1 (cp_, cp), 19 | inv_2 (d_, d); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/FD2v.orig: -------------------------------------------------------------------------------- 1 | module FD2 (d, cp, cd, q, qn); 2 | 3 | input d, cp, cd; 4 | output q, qn; 5 | 6 | nand #1 nand_2 (n2, d_, cp_), 7 | nand_3 (n3, n1, n4), 8 | nand_7 (q, n5, qn); 9 | 10 | nand #0 nand_1 (n1, d, cp_, cd), 11 | nand_4 (n4, n2, n3, cd), 12 | nand_5 (n5, n3, cp), 13 | nand_6 (n6, n4, cp), 14 | nand_8 (qn, n6, cd, q); 15 | 16 | not #0 inv_1 (cp_, cp), 17 | inv_2 (d_, d); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/OR2.v: -------------------------------------------------------------------------------- 1 | module OR2(a, b, z); 2 | 3 | input a, b; 4 | output z; 5 | 6 | or #1 g1(z, a, b); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/OR3.v: -------------------------------------------------------------------------------- 1 | module OR3(a, b, c, z); 2 | 3 | input a, b, c; 4 | output z; 5 | 6 | or #1 g1(z, a, b, c); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/OR4.v: -------------------------------------------------------------------------------- 1 | module OR4(a, b, c, d, z); 2 | 3 | input a, b, c, d; 4 | output z; 5 | 6 | or #1 g1(z, a, b, c, d); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/OR5.v: -------------------------------------------------------------------------------- 1 | module OR5(a, b, c, d, e, z); 2 | 3 | input a, b, c, d, e; 4 | output z; 5 | 6 | or #1 g1(z, a, b, c, d, e); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/ZERO.v: -------------------------------------------------------------------------------- 1 | module zero ( LO ); 2 | 3 | // Verilog Port Declaration section 4 | 5 | output LO; 6 | 7 | 8 | // Verilog Structure section (in terms of gate prims) 9 | 10 | 11 | buf #1 ( LO , 1'b0 ) ; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kgate/fd2.fix: -------------------------------------------------------------------------------- 1 | module dflop (d, cp, cd, q); 2 | 3 | input d, cp, cd; 4 | output q, qn; 5 | 6 | nand n1(a, d, cp), 7 | n2(b, cp, cd), 8 | n3(c, d, cd); 9 | 10 | 11 | nand n4(e, d, cp), 12 | n5(f, cp, cd), 13 | n6(g, d, cd); 14 | 15 | nand n7(h, a, b, c), 16 | n8(g, e, f, g); 17 | 18 | not n9(q, h); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/FA1a.v.old: -------------------------------------------------------------------------------- 1 | module FA1A( ci, a, b, s, co ); 2 | 3 | input ci, a, b; 4 | output s, co; 5 | reg s, co; 6 | 7 | always 8 | begin 9 | #1 s = a != b != ci; 10 | co = (a && b) || (a&&ci) || (b&&ci); 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/FD2.v.old: -------------------------------------------------------------------------------- 1 | module FD2 (D, CP, CD, Q, QN); 2 | 3 | 4 | input D, CP, CD; 5 | output Q, QN; 6 | 7 | reg Q; 8 | 9 | always @(posedge CP or negedge CD) 10 | 11 | if (!CD) 12 | Q = #1 0; 13 | else 14 | Q = #1 D; 15 | 16 | assign QN = ~Q; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/an2.v: -------------------------------------------------------------------------------- 1 | module AN2(a, b, z); 2 | 3 | input a, b; 4 | output z; 5 | 6 | and #1 g1(z, a, b); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/an3.v: -------------------------------------------------------------------------------- 1 | module AN3(a, b, c, z); 2 | 3 | input a, b, c; 4 | output z; 5 | 6 | and #1 g1(z, a, b, c); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/an4.v: -------------------------------------------------------------------------------- 1 | module AN4(a, b, c, d, z); 2 | 3 | input a, b, c, d; 4 | output z; 5 | 6 | and #1 g1(z, a, b, c, d); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/an5.v: -------------------------------------------------------------------------------- 1 | module AN5(a, b, c, d, e, z); 2 | 3 | input a, b, c, d, e; 4 | output z; 5 | 6 | and #1 g1(z, a, b, c, d, e); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/buf8a.v: -------------------------------------------------------------------------------- 1 | module BUF8A(a, z); 2 | 3 | input a; 4 | output z; 5 | 6 | buf #1 g1(z, a); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/en.v: -------------------------------------------------------------------------------- 1 | module EN (a, b, z); 2 | 3 | input a, b; 4 | output z; 5 | 6 | xnor #1 g1(z, a, b); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/fa1a.v: -------------------------------------------------------------------------------- 1 | module FA1A(CI, A, B, S, CO); 2 | output 3 | S, 4 | CO; 5 | input 6 | CI, 7 | A, 8 | B; 9 | or 10 | #1 (CO, w1, w2, w3); 11 | and 12 | (w1, A, B); 13 | and 14 | (w2, CI, dd_net_11); 15 | and 16 | (w3, CI, dd_net_13); 17 | xor 18 | #1 (S, CI, dd_net_11, dd_net_13); 19 | buf 20 | (dd_net_11, A); 21 | buf 22 | (dd_net_13, B); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/fd2.v: -------------------------------------------------------------------------------- 1 | module FD2 (D, CP, CD, Q, QN); 2 | 3 | 4 | input D, CP, CD; 5 | output Q, QN; 6 | 7 | reg QI; 8 | 9 | always @(posedge CP or negedge CD) 10 | 11 | if (!CD) 12 | QI = #1 0; 13 | else 14 | QI = #1 D; 15 | 16 | assign QN = ~QI; 17 | assign Q = QI; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/or2.v: -------------------------------------------------------------------------------- 1 | module OR2(a, b, z); 2 | 3 | input a, b; 4 | output z; 5 | 6 | or #1 g1(z, a, b); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/or3.v: -------------------------------------------------------------------------------- 1 | module OR3(a, b, c, z); 2 | 3 | input a, b, c; 4 | output z; 5 | 6 | or #1 g1(z, a, b, c); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/or4.v: -------------------------------------------------------------------------------- 1 | module OR4(a, b, c, d, z); 2 | 3 | input a, b, c, d; 4 | output z; 5 | 6 | or #1 g1(z, a, b, c, d); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/lca100kunit/or5.v: -------------------------------------------------------------------------------- 1 | module OR5(a, b, c, d, e, z); 2 | 3 | input a, b, c, d, e; 4 | output z; 5 | 6 | or #1 g1(z, a, b, c, d, e); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/AN210.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module AN210 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | and #1 ( Y , A , B ) ; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF001.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF001 ( A1 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input B1; 9 | input B2; 10 | output Y; 11 | 12 | 13 | // Verilog Structure section (in terms of gate prims) 14 | 15 | and ( E2EG_5923 , B1 , B2 ) ; 16 | 17 | nor #1 ( Y , A1 , E2EG_5923 ) ; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF002.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF002 ( A1 , B1 , B2 , B3 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input B1; 9 | input B2; 10 | input B3; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | and ( E2EG_5924 , B3 , B1 , B2 ) ; 17 | 18 | nor #1 ( Y , A1 , E2EG_5924 ) ; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF003.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF003 ( A1 , A2 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input A2; 9 | input B1; 10 | input B2; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | 17 | aoiudp #1 ( Y , B1 , B2 , A1 , A2 ) ; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF003.v.gate: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF003 ( A1 , A2 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input A2; 9 | input B1; 10 | input B2; 11 | output Y; 12 | wire Y1, Y2, A1_, A2_, B1_, B2_; 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | 17 | // aoiudp ( Y , B1 , B2 , A1 , A2 ) ; 18 | 19 | not g1 (B1_,B1), g2 (B2_,B2), g3 (A1_,A1), g4 (A2_,A2); 20 | or g5 (Y1, B1_, B2_), g6 (Y2, A1_,A2_); 21 | and g7 (Y, Y1, Y2); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF006.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF006 ( A1 , A2 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input A2; 9 | input B1; 10 | input B2; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | and ( E2EG_5924 , B1 , B2 ) ; 17 | 18 | nor #1 ( Y , E2EG_5924 , A1 , A2 ) ; 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF051.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF051 ( A1 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input B1; 9 | input B2; 10 | output Y; 11 | 12 | 13 | // Verilog Structure section (in terms of gate prims) 14 | 15 | or ( E2EG_5937 , B1 , B2 ) ; 16 | 17 | nand #1 ( Y , E2EG_5937 , A1 ) ; 18 | 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF052.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF052 ( A1 , B1 , B2 , B3 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input B1; 9 | input B2; 10 | input B3; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | or ( E2EG_5942 , B3 , B1 , B2 ) ; 17 | 18 | nand #1 ( Y , E2EG_5942 , A1 ) ; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF053.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF053 ( A1 , A2 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input A2; 9 | input B1; 10 | input B2; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | or ( E2EG_5940 , B1 , B2 ) ; 17 | or ( E2EG_5942 , A1 , A2 ) ; 18 | 19 | nand #1 ( Y , E2EG_5940 , E2EG_5942 ) ; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/BF056.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module BF056 ( A1 , A2 , B1 , B2 , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A1; 8 | input A2; 9 | input B1; 10 | input B2; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | or ( E2EG_5944 , B1 , B2 ) ; 17 | 18 | nand #1 ( Y , A1 , E2EG_5944 , A2 ) ; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/EN210.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module EN210 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | xnor #1 ( Y , A , B ) ; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/EN2B0.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module EN2B0 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | xnor #1 ( Y , A , B ) ; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/EX210.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module EX210 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | xor #1 ( Y , B , A ) ; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/EX2B0.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module EX2B0 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | xor #1 ( Y , B , A ) ; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/IV110.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module IV110 ( A , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | output Y; 9 | 10 | 11 | // Verilog Structure section (in terms of gate prims) 12 | 13 | 14 | not #1 ( Y , A ) ; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/NA210.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module NA210 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | nand #1 ( Y , A , B ) ; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/NA310.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module NA310 ( A , B , C , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | input C; 10 | output Y; 11 | 12 | 13 | // Verilog Structure section (in terms of gate prims) 14 | 15 | 16 | nand #1 ( Y , C , A , B ) ; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/NA311.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module NA311 ( A , B , C , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | input C; 10 | output Y; 11 | 12 | 13 | // Verilog Structure section (in terms of gate prims) 14 | 15 | not ( IINVnet1 , A ) ; 16 | 17 | nand #1 ( Y , C , IINVnet1 , B ) ; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/NA410.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module NA410 ( A , B , C , D , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | input C; 10 | input D; 11 | output Y; 12 | 13 | 14 | // Verilog Structure section (in terms of gate prims) 15 | 16 | 17 | nand #1 ( Y , A , B , C , D ) ; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/NO210.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module NO210 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | nor #1 ( Y , A , B ) ; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/OR210.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module OR210 ( A , B , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | output Y; 10 | 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | or #1 ( Y , A , B ) ; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/OR310.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module OR310 ( A , B , C , Y ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | input A; 8 | input B; 9 | input C; 10 | output Y; 11 | 12 | 13 | // Verilog Structure section (in terms of gate prims) 14 | 15 | 16 | or #1 ( Y , C , A , B ) ; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/TO010.v: -------------------------------------------------------------------------------- 1 | // Verilog Interface section 2 | 3 | module TO010 ( HI , LO ); 4 | 5 | // Verilog Port Declaration section 6 | 7 | output HI; 8 | output LO; 9 | supply0 GROUND; 10 | supply1 POWER; 11 | 12 | // Verilog Structure section (in terms of gate prims) 13 | 14 | 15 | buf #1 ( HI , POWER ) ; 16 | buf #1 ( LO , GROUND ) ; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/libs/tgc1000gate/aoiudp.v: -------------------------------------------------------------------------------- 1 | primitive aoiudp 2 | (out, in1, in2, in3, in4); 3 | input in1, in2, in3, in4; 4 | output out; 5 | table 6 | // in1 in2 in3 in4 : out ; 7 | 0 ? 0 ? : 1 ; 8 | 0 ? ? 0 : 1 ; 9 | ? 0 0 ? : 1 ; 10 | ? 0 ? 0 : 1 ; 11 | 1 1 ? ? : 0 ; 12 | ? ? 1 1 : 0 ; 13 | endtable 14 | endprimitive 15 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/ti_mult/README: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- These source files may be used and distributed without 4 | -- restriction. 5 | -- 6 | -------------------------------------------------------------------- 7 | -- 8 | -- Author John Hillawi 9 | -- Names mult.v 10 | -- patterns 11 | -- Purpose This circuit was created for the purpose of 12 | -- measuring store size parameters for a variety 13 | of different sized circuits. 14 | -------------------------------------------------------------------- 15 | -- 16 | -- The circuit is a matrix multiplier unit supplied by Texas 17 | -- Instruments as public domain code. 18 | -- 19 | -------------------------------------------------------------------- 20 | -- 21 | -- As a guide to running, a typical script (in this case 22 | -- Pragmatic C Software Cver) would be: 23 | -- 24 | -- cver -f mult.vc 25 | -- 26 | -- To directly execute mult_gate.v, type this: 27 | -- 28 | -- cver mult.v -y ../libs/tgc1000gate +libext+.v 29 | -- 30 | -- Each line of the pattern file provides the pattern vectors 31 | -- for input1, input2, and the output reference vector. The 32 | -- model samples the output, and checks against the pattern file. 33 | -------------------------------------------------------------------- 34 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/ti_mult/mult.aiv.vc: -------------------------------------------------------------------------------- 1 | mult.aiv.v -y ../libs/tgc1000gate +libext+.v 2 | +change_port_type 3 | -------------------------------------------------------------------------------- /tests_and_examples/verilog_da_bnchmrks/ti_mult/mult.vc: -------------------------------------------------------------------------------- 1 | mult.v -y ../libs/tgc1000gate +libext+.v 2 | +change_port_type 3 | -------------------------------------------------------------------------------- /toggle_coverage/bin/chk_tgldat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/toggle_coverage/bin/chk_tgldat -------------------------------------------------------------------------------- /toggle_coverage/bin/tgldat_merge: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/toggle_coverage/bin/tgldat_merge -------------------------------------------------------------------------------- /toggle_coverage/bin/tgldat_report: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/toggle_coverage/bin/tgldat_report -------------------------------------------------------------------------------- /toggle_coverage/bin/tvcd_to_tgldat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cambridgehackers/open-src-cvc/b3e7fded6d4d79491886de40aec3a780efdd9d4e/toggle_coverage/bin/tvcd_to_tgldat -------------------------------------------------------------------------------- /toggle_coverage/src/README: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | CVC COVERAGE HELPER PROGRAMS - SOURCE FILES 3 | /////////////////////////////////////////////////////////////////////////// 4 | 5 | - see the '../README.coverage.helper-programs' on level up for more 6 | information on these files. 7 | 8 | - these helper programs are pre-compiled in ../bin, but are available if you 9 | desire to change them: 10 | 11 | - edit the makefile.lnx to choose 64 bit, 32 bit and whether you want -g on 12 | makefile -f maefile.lnx 13 | 14 | - there are some extern procs for reading, building the toggle dat netlist 15 | and other operations in the file tgldat_srvc.c (services) if you want to 16 | write your own analysis program. 17 | -------------------------------------------------------------------------------- /toggle_coverage/src/makefile.lnx: -------------------------------------------------------------------------------- 1 | # only 32-bit versions released use these - remove -m32 for 64 make 2 | # tgldat srvc has service procs for basic .tgldat net list manipulation 3 | CC=gcc 4 | LIBS= 5 | ARCHFLGS= 6 | 7 | ## optimized 8 | # CFLAGS= $(ARCHFLGS) -O2 -Wall -m32 9 | ## 64 bit 10 | CFLAGS= $(ARCHFLGS) -O2 -Wall 11 | #debug with -g 12 | ## 32 bit 13 | # CFLAGS= $(ARCHFLGS) -m32 -g -Wall 14 | ## 64 bit 15 | # CFLAGS= $(ARCHFLGS) -g -Wall 16 | 17 | tvcd_to_tgldat: tvcd_to_tgldat.o tgldat_srvc.o 18 | $(CC) $(CFLAGS) tvcd_to_tgldat.o tgldat_srvc.o $(LIBS) \ 19 | -o tvcd_to_tgldat 20 | 21 | tvcd_to_tgldat.o: tvcd_to_tgldat.c tgldat.h 22 | $(CC) $(CFLAGS) -c tvcd_to_tgldat.c 23 | 24 | chk_tgldat: chk_tgldat.o tgldat_srvc.o 25 | $(CC) $(CFLAGS) chk_tgldat.o tgldat_srvc.o $(LIBS) -o chk_tgldat 26 | 27 | chk_tgldat.o: chk_tgldat.c tgldat.h 28 | $(CC) $(CFLAGS) -c chk_tgldat.c 29 | 30 | tgldat_report: tgldat_report.o tgldat_srvc.o 31 | $(CC) $(CFLAGS) tgldat_report.o tgldat_srvc.o $(LIBS) -o tgldat_report 32 | 33 | tgldat_report.o: tgldat_report.c tgldat.h 34 | $(CC) $(CFLAGS) -c tgldat_report.c 35 | 36 | tgldat_merge: tgldat_merge.o tgldat_srvc.o 37 | $(CC) $(CFLAGS) tgldat_merge.o tgldat_srvc.o $(LIBS) -o tgldat_merge 38 | 39 | tgldat_merge.o: tgldat_merge.c tgldat.h 40 | $(CC) $(CFLAGS) -c tgldat_merge.c 41 | 42 | tgldat_srvc.o: tgldat_srvc.c tgldat.h 43 | $(CC) $(CFLAGS) -c tgldat_srvc.c 44 | 45 | all: tvcd_to_tgldat chk_tgldat tgldat_report tgldat_merge 46 | 47 | clean: 48 | rm tvcd_to_tgldat.o tvcd_to_tgldat chk_tgldat.o chk_tgldat \ 49 | tgldat_report.o tgldat_report tgldat_merge.o tgldat_merge \ 50 | tgldat_srvc.o 51 | --------------------------------------------------------------------------------