├── CACHE ├── sources_1 │ └── new │ │ ├── Cache_identification.v │ │ ├── Cache_output_set_select.v │ │ ├── L1_data_tgv.v │ │ ├── Cache_SET_L1_data.v │ │ ├── Cache_SET_L1_instr.v │ │ ├── L1_instr_dat.v │ │ ├── L1_instr_tgv.v │ │ ├── L2_tgv.v │ │ ├── Cache_SET_L2.v │ │ ├── L2_dat.v │ │ ├── Cache_replacement_instr.v │ │ ├── L1_data_dat.v │ │ ├── Cache_instruction_decode.v │ │ ├── Cache_replacement_data.v │ │ ├── Cache_LOAD_L1_data.v │ │ ├── simpleuart.v │ │ ├── Cache_replacement_L2.v │ │ ├── Cache_MEM_L1_data.v │ │ ├── Cache_MEM_L1_instr.v │ │ ├── Cache_TOP.v │ │ ├── Cache_MEM_L2.v │ │ ├── teknofest_ram.v │ │ ├── Cache_STORE_L1_data.v │ │ └── Cache_controller.v └── sim_1 │ └── new │ ├── Cache_MEM_L1_data_tb.v │ ├── Cache_MEM_L1_instr_tb.v │ ├── Cache_MEM_L2_tb.v │ ├── Cache_TOP_tb.v │ └── tekno_example.hex └── README.md /CACHE/sources_1/new/Cache_identification.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_identification#(parameter tag_size = 9)( 3 | input [tag_size-1:0] tag_i, 4 | input valid_mem, 5 | input [tag_size-1:0] tag_mem, 6 | output reg hit_o 7 | ); 8 | always @* begin 9 | if(valid_mem == 1'b1) begin // if valid_mem is 1 10 | if(tag_mem == tag_i) begin // if tag mem & tag input is equal it is hit 11 | hit_o = 1'b1; 12 | end 13 | else begin // if not it is not hit 14 | hit_o = 1'b0; 15 | end 16 | end 17 | else begin // if mem is not valid then it is not hit 18 | hit_o = 1'b0; 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_output_set_select.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_output_set_select#( // Whether set0 output or set1 output to cache output, the module that chooses accordingly 3 | parameter block_size = 128 4 | ) 5 | ( 6 | input hit_i, 7 | input cache_set_output_select_i, 8 | input [block_size-1:0] data_out_s2_i, 9 | input [block_size-1:0] data_out_s1_i, 10 | output reg [block_size-1:0] data_block_o 11 | ); 12 | always @(*) begin 13 | if(cache_set_output_select_i & (hit_i)) begin // If cache_set_output_select is 1, we will get output from set2 14 | data_block_o = data_out_s2_i; 15 | end 16 | else if(~cache_set_output_select_i & (hit_i)) begin // If cache_set_output_select is 0, we will get output from set1 17 | data_block_o = data_out_s1_i; 18 | end 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/L1_data_tgv.v: -------------------------------------------------------------------------------- 1 | // OpenRAM SRAM model 2 | // Words: 64 3 | // Word size: 128 4 | 5 | module L1_data_tgv#( 6 | parameter DATA_WIDTH = 10, // tag size (9 bits) + valid bit (1 bit) 7 | parameter ADDR_WIDTH = 6, // idx size (6 bits), log2(64) = 6 (64 = block no) 8 | parameter RAM_DEPTH = 1 << ADDR_WIDTH // 2^6 = 64 (depth) 9 | ) 10 | ( 11 | input clk_i, // clock input 12 | input we_i, // write enable input 13 | input [ADDR_WIDTH-1:0] addr_i, // address input 14 | input [DATA_WIDTH-1:0] data_i, // data input 15 | output reg [DATA_WIDTH-1:0] data_o // data output 16 | ); 17 | // Core Memory 18 | (* ram_style = "block" *) reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; // memory delete attribute for ASIC design 19 | // Port-1 Operation Read First 20 | always @ (posedge clk_i) begin : MEM_WRITE 21 | if (we_i) begin 22 | mem[addr_i][DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; 23 | end 24 | data_o <= mem[addr_i]; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_SET_L1_data.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_SET_L1_data#( 3 | parameter block_size = 128, 4 | parameter tag_size = 9, 5 | parameter idx_size = 6 6 | ) 7 | ( 8 | input clk_i, 9 | input [block_size-1:0] block_i, 10 | input [tag_size + idx_size-1:0] tag_and_idx_i, 11 | input we_i, 12 | input [15:0] byte_enable_i, 13 | output [block_size-1:0] block_o, 14 | output valid_o, 15 | output [tag_size -1:0] tag_o 16 | ); 17 | 18 | L1_data_dat L1_data_data_inst( // module that holds data bits L1 (1 kB) (128*64 bits) 19 | .clk_i(clk_i), 20 | .we_i(we_i), 21 | .byte_enable_i(byte_enable_i), 22 | .addr_i(tag_and_idx_i[idx_size-1:0]), 23 | .data_i(block_i), 24 | .data_o(block_o) 25 | ); 26 | 27 | L1_data_tgv L1_data_valid_tag_inst( // module that holds the valid & data bits (10*64 bits) 28 | .clk_i(clk_i), 29 | .we_i(we_i), 30 | .addr_i(tag_and_idx_i[idx_size-1:0]), 31 | .data_i({1'b1, tag_and_idx_i[tag_size + idx_size - 1:idx_size]}), 32 | .data_o({valid_o,tag_o}) 33 | ); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_SET_L1_instr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_SET_L1_instr#( 3 | parameter block_size = 128, 4 | parameter tag_size = 9, 5 | parameter idx_size = 6, 6 | parameter block_no = 64 7 | ) 8 | ( 9 | input clk_i, 10 | input [block_size-1:0] block_i, 11 | input [tag_size + idx_size-1:0] tag_and_idx_i, 12 | input we_i, 13 | input we_next_i, 14 | output [block_size-1:0] block_o, 15 | output valid_o, 16 | output [tag_size -1:0] tag_o, 17 | output [15:0] block_next_o, 18 | output valid_next_o, 19 | output [tag_size -1:0] tag_next_o 20 | ); 21 | 22 | L1_instr_dat L1_instr_data_inst( // module that holds data bits L1 (1 kB) (128*64 bits) 23 | .clk_i(clk_i), 24 | .we_i(we_i), 25 | .we_next_i(we_next_i), 26 | .addr_i(tag_and_idx_i[idx_size-1:0]), 27 | .data_i(block_i), 28 | .data_o(block_o), 29 | .data_next_o(block_next_o) 30 | ); 31 | 32 | L1_instr_tgv L1_instr_valid_tag_inst( // module that holds the valid & data bits (10*64 bits) 33 | .clk_i(clk_i), 34 | .we_i(we_i), 35 | .we_next_i(we_next_i), 36 | .addr_i(tag_and_idx_i[idx_size-1:0]), 37 | .data_i({1'b1, tag_and_idx_i[tag_size + idx_size - 1:idx_size]}), 38 | .data_o({valid_o,tag_o}), 39 | .data_next_o({valid_next_o,tag_next_o}) 40 | ); 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/L1_instr_dat.v: -------------------------------------------------------------------------------- 1 | // OpenRAM SRAM model 2 | // Words: 64 3 | // Word size: 128 4 | 5 | module L1_instr_dat#( 6 | parameter DATA_WIDTH = 128, // data size 128 bit = LINE SIZE 7 | parameter ADDR_WIDTH = 6, // idx size (6 bits), log2(64) = 6 (64 = block no) 8 | parameter RAM_DEPTH = 1 << ADDR_WIDTH // 2^6 = 64 (depth) 9 | ) 10 | ( 11 | input clk_i, // clock input 12 | input we_i, // write enable input 13 | input we_next_i, // write enable input for next idx 14 | input [ADDR_WIDTH-1:0] addr_i, // address input 15 | input [DATA_WIDTH-1:0] data_i, // data input 16 | output reg [DATA_WIDTH-1:0] data_o, // data output 17 | output reg [15:0] data_next_o // next data output 18 | ); 19 | // Core Memory 20 | (* ram_style = "block" *) reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; // memory delete attribute for ASIC design 21 | // Port-1 Operation Current Address Read First 22 | always @ (posedge clk_i) begin : MEM_WRITE 23 | if (we_i & ~(we_next_i)) begin // if write enable & not write next 24 | mem[addr_i][DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; 25 | end 26 | data_o <= mem[addr_i]; 27 | end 28 | always @(posedge clk_i) begin: MEM_WRITE_NEXT 29 | if(we_i & we_next_i) begin // if write enable & write next 30 | mem[addr_i+1'b1][DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; 31 | end 32 | data_next_o <= mem[addr_i + 6'd1][15:0]; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/L1_instr_tgv.v: -------------------------------------------------------------------------------- 1 | // OpenRAM SRAM model 2 | // Words: 64 3 | // Word size: 128 4 | 5 | module L1_instr_tgv#( 6 | parameter DATA_WIDTH = 10,// tag size (9 bits) + valid bit (1 bit) 7 | parameter ADDR_WIDTH = 6, // idx size (6 bits) log2(64) = 6 (64 = block no) 8 | parameter RAM_DEPTH = 1 << ADDR_WIDTH // 2^6 = 64 (depth) 9 | ) 10 | ( 11 | input clk_i, // clock input 12 | input we_i, // write enable input 13 | input we_next_i, // write enable input for next idx 14 | input [ADDR_WIDTH-1:0] addr_i, // address input 15 | input [DATA_WIDTH-1:0] data_i, // data input 16 | output reg [DATA_WIDTH-1:0] data_o, // data output 17 | output reg [DATA_WIDTH-1:0] data_next_o // next data output 18 | ); 19 | 20 | // Core Memory 21 | (* ram_style = "block" *) reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; // memory delete attribute for ASIC design 22 | // Port-1 Operation Current Address Read First 23 | always @ (posedge clk_i) begin : MEM_WRITE 24 | if (we_i & ~(we_next_i)) begin // if write enable & not write next 25 | mem[addr_i][DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; 26 | end 27 | data_o <= mem[addr_i]; 28 | end 29 | // Port-1 Operation Next idx Address Read First 30 | always @(posedge clk_i) begin: MEM_WRITE_NEXT 31 | if(we_i & we_next_i) begin // if write enable & write next 32 | mem[addr_i+1'b1][DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; 33 | end 34 | data_next_o <= mem[addr_i + 6'd1]; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/L2_tgv.v: -------------------------------------------------------------------------------- 1 | // True-Dual-Port BRAM with Byte-wide Write Enable 2 | module L2_tgv#( 3 | parameter NUM_COL = 1, // no byte enables 4 | parameter COL_WIDTH = 8, // tag size (7 bits) + valid bit (1 bit) 5 | parameter ADDR_WIDTH = 8, // idx size = 8, log2(256) = 8 (256 = block no) 6 | // Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth 7 | parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits 8 | ) 9 | ( 10 | input clk_i, // clock input 11 | input we_p1_i, // port 1 write enable signal (data cache) 12 | input we_p2_i, // port 2 write enable signal (instruction cache) 13 | input [ADDR_WIDTH-1:0] addr_p1_i, // port 1 address 14 | input [ADDR_WIDTH-1:0] addr_p2_i, // port 2 address 15 | input [DATA_WIDTH-1:0] data_p1_i, // port 1 data in 16 | input [DATA_WIDTH-1:0] data_p2_i, // port 2 data in 17 | output reg [DATA_WIDTH-1:0] data_p1_o, // data out port 1 18 | output reg [DATA_WIDTH-1:0] data_p2_o // data out port 2 19 | ); 20 | 21 | // Core Memory 22 | (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; // memory delete attribute for ASIC design 23 | // Port-1 Operation Read First 24 | always @ (posedge clk_i) begin 25 | if(we_p1_i) begin 26 | ram_block[addr_p1_i][DATA_WIDTH-1:0] <= data_p1_i[DATA_WIDTH-1:0]; 27 | end 28 | data_p1_o <= ram_block[addr_p1_i]; 29 | end 30 | // Port-2 Operation Read First 31 | always @ (posedge clk_i) begin 32 | if(we_p2_i) begin 33 | ram_block[addr_p2_i][DATA_WIDTH-1:0] <= data_p2_i[DATA_WIDTH-1:0]; 34 | end 35 | data_p2_o <= ram_block[addr_p2_i]; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_SET_L2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_SET_L2#( 3 | parameter block_size = 128, 4 | parameter tag_size = 7, 5 | parameter idx_size = 8 6 | ) 7 | ( 8 | input clk_i, 9 | input [block_size-1:0] block_p1_i, 10 | input [block_size-1:0] block_p2_i, 11 | input [tag_size + idx_size-1:0] tag_and_idx_p1_i, 12 | input [tag_size + idx_size-1:0] tag_and_idx_p2_i, 13 | input we_p1_i, 14 | input we_p2_i, 15 | input [15:0] byte_enable_p1_i, 16 | input [15:0] byte_enable_p2_i, 17 | output [block_size-1:0] block_p1_o, 18 | output [block_size-1:0] block_p2_o, 19 | output valid_p1_o, 20 | output valid_p2_o, 21 | output [tag_size -1:0] tag_p1_o, 22 | output [tag_size -1:0] tag_p2_o 23 | ); 24 | 25 | 26 | L2_dat L2_data_inst( // module that holds data bits L2 (4 kB) (128*256 bits) 27 | .clk_i(clk_i), 28 | .we_p1_i(we_p1_i), 29 | .we_p2_i(we_p2_i), 30 | .byte_enable_p1_i(byte_enable_p1_i), 31 | .byte_enable_p2_i(byte_enable_p2_i), 32 | .addr_p1_i(tag_and_idx_p1_i[idx_size-1:0]), 33 | .addr_p2_i(tag_and_idx_p2_i[idx_size-1:0]), 34 | .data_p1_i(block_p1_i), 35 | .data_p2_i(block_p2_i), 36 | .data_p1_o(block_p1_o), 37 | .data_p2_o(block_p2_o) 38 | ); 39 | 40 | L2_tgv L2_valid_tag_inst( // module that holds the valid & data bits (10*256 bits) 41 | .clk_i(clk_i), 42 | .we_p1_i(we_p1_i), 43 | .we_p2_i(we_p2_i), 44 | .addr_p1_i(tag_and_idx_p1_i[idx_size-1:0]), 45 | .addr_p2_i(tag_and_idx_p2_i[idx_size-1:0]), 46 | .data_p1_i({1'b1,tag_and_idx_p1_i[tag_size+idx_size-1:idx_size]}), 47 | .data_p2_i({1'b1,tag_and_idx_p2_i[tag_size+idx_size-1:idx_size]}), 48 | .data_p1_o({valid_p1_o,tag_p1_o}), 49 | .data_p2_o({valid_p2_o,tag_p2_o}) 50 | ); 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/L2_dat.v: -------------------------------------------------------------------------------- 1 | // True-Dual-Port BRAM with Byte-wide Write Enable 2 | module L2_dat#( 3 | parameter NUM_COL = 16,// no byte enables 4 | parameter COL_WIDTH = 8, // 1 byte = 8 bits 5 | parameter ADDR_WIDTH = 8, // idx size = 8, log2(256) = 8 (256 = block no) 6 | // Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth 7 | parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits = 1 byte * 16 = 16 byte = 128 bits ==> LINE SIZE 8 | ) 9 | ( 10 | input clk_i,// clock input 11 | input we_p1_i,// port 1 write enable signal (data cache) 12 | input we_p2_i,// port 2 write enable signal (instruction cache) 13 | input [NUM_COL-1:0] byte_enable_p1_i, // byte enable signals for port 1 14 | input [NUM_COL-1:0] byte_enable_p2_i, // byte enable signals for port 2 15 | input [ADDR_WIDTH-1:0] addr_p1_i, // port 1 address 16 | input [ADDR_WIDTH-1:0] addr_p2_i, // port 2 address 17 | input [DATA_WIDTH-1:0] data_p1_i, // port 1 data in 18 | input [DATA_WIDTH-1:0] data_p2_i, // port 2 data in 19 | output reg [DATA_WIDTH-1:0] data_p1_o, // data out port 1 20 | output reg [DATA_WIDTH-1:0] data_p2_o // data out port 2 21 | ); 22 | 23 | // Core Memory 24 | (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; // memory delete attribute for ASIC design 25 | integer i; 26 | // Port-1 Operation - Read First 27 | always @ (posedge clk_i) begin 28 | if(we_p1_i) begin 29 | for(i=0;i 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module simpleuart #(parameter integer DEFAULT_DIV = 1) ( 21 | input clk, 22 | input resetn, 23 | 24 | output ser_tx, 25 | input ser_rx, 26 | 27 | input [3:0] reg_div_we, 28 | input [31:0] reg_div_di, 29 | output [31:0] reg_div_do, 30 | 31 | input reg_dat_we, 32 | input reg_dat_re, 33 | input [31:0] reg_dat_di, 34 | output [31:0] reg_dat_do, 35 | output reg_dat_wait 36 | ); 37 | reg [31:0] cfg_divider; 38 | 39 | reg [3:0] recv_state; 40 | reg [31:0] recv_divcnt; 41 | reg [7:0] recv_pattern; 42 | reg [7:0] recv_buf_data; 43 | reg recv_buf_valid; 44 | 45 | reg [9:0] send_pattern; 46 | reg [3:0] send_bitcnt; 47 | reg [31:0] send_divcnt; 48 | reg send_dummy; 49 | 50 | assign reg_div_do = cfg_divider; 51 | 52 | assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); 53 | assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; 54 | 55 | always @(posedge clk) begin 56 | if (!resetn) begin 57 | cfg_divider <= DEFAULT_DIV; 58 | end else begin 59 | if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0]; 60 | if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8]; 61 | if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16]; 62 | if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24]; 63 | end 64 | end 65 | 66 | always @(posedge clk) begin 67 | if (!resetn) begin 68 | recv_state <= 0; 69 | recv_divcnt <= 0; 70 | recv_pattern <= 0; 71 | recv_buf_data <= 0; 72 | recv_buf_valid <= 0; 73 | end else begin 74 | recv_divcnt <= recv_divcnt + 1; 75 | if (reg_dat_re) 76 | recv_buf_valid <= 0; 77 | case (recv_state) 78 | 0: begin 79 | if (!ser_rx) 80 | recv_state <= 1; 81 | recv_divcnt <= 0; 82 | end 83 | 1: begin 84 | if (2*recv_divcnt > cfg_divider) begin 85 | recv_state <= 2; 86 | recv_divcnt <= 0; 87 | end 88 | end 89 | 10: begin 90 | if (recv_divcnt > cfg_divider) begin 91 | recv_buf_data <= recv_pattern; 92 | recv_buf_valid <= 1; 93 | recv_state <= 0; 94 | end 95 | end 96 | default: begin 97 | if (recv_divcnt > cfg_divider) begin 98 | recv_pattern <= {ser_rx, recv_pattern[7:1]}; 99 | recv_state <= recv_state + 1; 100 | recv_divcnt <= 0; 101 | end 102 | end 103 | endcase 104 | end 105 | end 106 | 107 | assign ser_tx = send_pattern[0]; 108 | 109 | always @(posedge clk) begin 110 | if (reg_div_we) 111 | send_dummy <= 1; 112 | send_divcnt <= send_divcnt + 1; 113 | if (!resetn) begin 114 | send_pattern <= ~0; 115 | send_bitcnt <= 0; 116 | send_divcnt <= 0; 117 | send_dummy <= 1; 118 | end else begin 119 | if (send_dummy && !send_bitcnt) begin 120 | send_pattern <= ~0; 121 | send_bitcnt <= 15; 122 | send_divcnt <= 0; 123 | send_dummy <= 0; 124 | end else 125 | if (reg_dat_we && !send_bitcnt) begin 126 | send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; 127 | send_bitcnt <= 10; 128 | send_divcnt <= 0; 129 | end else 130 | if (send_divcnt > cfg_divider && send_bitcnt) begin 131 | send_pattern <= {1'b1, send_pattern[9:1]}; 132 | send_bitcnt <= send_bitcnt - 1; 133 | send_divcnt <= 0; 134 | end 135 | end 136 | end 137 | endmodule 138 | -------------------------------------------------------------------------------- /CACHE/sim_1/new/Cache_MEM_L1_data_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_MEM_L1_data_tb(); 3 | parameter block_size = 128; 4 | parameter tag_size = 9; 5 | parameter idx_size = 6; 6 | parameter word_size = 2; 7 | parameter offset_size = 2; 8 | reg cpu_clk; 9 | reg clk_i; 10 | reg rst_i; 11 | reg read_i; 12 | reg write_i; 13 | reg [2:0] read_instruction_i; 14 | reg [2:0] write_instruction_i; 15 | reg write_L2_i; 16 | wire [tag_size+idx_size+word_size+offset_size-1:0] addr_i; 17 | reg [63:0] data_core_i; 18 | reg [block_size-1:0] data_L2_i; 19 | wire [block_size-1:0] data_block_o; 20 | wire [63:0] data_o; 21 | wire hit_o; 22 | 23 | reg [tag_size-1:0] tag; 24 | reg [idx_size-1:0] idx; 25 | reg [word_size-1:0] word; 26 | reg [offset_size-1:0] offset; 27 | assign addr_i = {tag, idx, word, offset}; 28 | 29 | parameter SB = 3'b000, 30 | SH = 3'b001, 31 | SW = 3'b010, 32 | SD = 3'b011; 33 | parameter LBU = 3'b100, 34 | LB = 3'b000, 35 | LHU = 3'b101, 36 | LH = 3'b001, 37 | LWU = 3'b110, 38 | LW = 3'b010, 39 | LD = 3'b011; 40 | 41 | Cache_MEM_L1_data#( 42 | .block_size(128), 43 | .tag_size(tag_size), 44 | .idx_size(idx_size), 45 | .block_no(64), 46 | .word_size(word_size), 47 | .offset_size(offset_size) 48 | ) 49 | Cache_MEMORY_L1_data_inst( 50 | .clk_i(clk_i), 51 | .rst_i(rst_i), 52 | .read_i(read_i), 53 | .write_i(write_i), 54 | .read_instruction_i(read_instruction_i), 55 | .write_instruction_i(write_instruction_i), 56 | .write_L2_i(write_L2_i), 57 | .addr_i(addr_i), 58 | .data_core_i(data_core_i), 59 | .data_L2_i(data_L2_i), 60 | .data_block_o(data_block_o), 61 | .data_o(data_o), 62 | .hit_o(hit_o) 63 | ); 64 | 65 | always #4 clk_i = ~clk_i; 66 | always #10 cpu_clk =~cpu_clk; 67 | initial begin 68 | cpu_clk = 0; 69 | clk_i = 0; 70 | reset_mem; 71 | write_from_L2(128'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0,6'd0,9'd0,2'd0,2'd0); 72 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LHU); // F0F0 73 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LBU); // F0 74 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LD); // F0F0F0F0F0F0F0F0 75 | write_from_L2(128'h0000AAAA,6'd0,9'd5,2'd0,2'd0); 76 | read_L1_data(6'd0,9'd5,2'd0,2'd0,LBU); // 00aa 77 | read_L1_data(6'd0,9'd5,2'd0,2'd0,LD); // aaaa 78 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LHU); // F0F0 79 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LBU); // F0 80 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LD); // F0F0F0F0F0F0F0F0 81 | #500; 82 | write_core(64'hABCD_EFFF_0000_00BB,6'd0,9'd0,2'd0,2'd2,SD); 83 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LBU); // 00BB 84 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LHU); // 0000_00BB 85 | //read_L1_data(6'd0,9'd5,2'd0,2'd1,LD); 86 | //read_L1_data(6'd0,9'd5,2'd0,2'd1,LD); 87 | write_from_L2(128'hDDDDDDDD,6'd0,9'd10,2'd0,2'd0); 88 | read_L1_data(6'd0,9'd0,2'd0,2'd0,LD); // abcdefff000000bb 89 | read_L1_data(6'd0,9'd10,2'd0,2'd0,LD); // DDDDDDDD 90 | #20; 91 | $finish; 92 | end 93 | 94 | task reset_mem(); 95 | begin 96 | rst_i = 1'b1; 97 | #100; 98 | rst_i = 1'b0; 99 | end 100 | endtask 101 | task write_core( 102 | input [63:0] data, 103 | input [idx_size-1:0] idx_i, 104 | input [tag_size-1:0] tag_i, 105 | input [word_size-1:0] word_i, 106 | input [offset_size-1:0] offset_i, 107 | input [2:0] write_instr); 108 | begin 109 | @(posedge cpu_clk); 110 | write_instruction_i = write_instr; 111 | idx = idx_i; 112 | tag = tag_i; 113 | word = word_i; 114 | offset = offset_i; 115 | data_core_i = data; 116 | #3; 117 | write_i = 1'b1; 118 | @(posedge cpu_clk); 119 | write_i = 1'b0; 120 | end 121 | endtask 122 | task write_from_L2( 123 | input [block_size-1:0] data, 124 | input [idx_size-1:0] idx_i, 125 | input [tag_size-1:0] tag_i, 126 | input[word_size-1:0] word_i, 127 | input[offset_size-1:0] offset_i); 128 | begin 129 | write_L2_i <= 1'b1; 130 | @(posedge cpu_clk); 131 | idx = idx_i; 132 | tag = tag_i; 133 | word = word_i; 134 | offset = offset_i; 135 | data_L2_i = data; 136 | #3; 137 | write_i = 1'b1; 138 | #5; 139 | @(posedge cpu_clk); 140 | write_i = 1'b0; 141 | write_L2_i <= 1'b0; 142 | end 143 | endtask 144 | task read_L1_data( 145 | input [idx_size-1:0] idx_i, 146 | input [tag_size-1:0] tag_i, 147 | input[word_size-1:0] word_i, 148 | input[offset_size-1:0] offset_i, 149 | input [2:0] read_instr); 150 | begin 151 | @(posedge cpu_clk); 152 | read_instruction_i = read_instr; 153 | idx = idx_i; 154 | tag = tag_i; 155 | word = word_i; 156 | offset = offset_i; 157 | #3; 158 | read_i = 1'b1; 159 | #5; 160 | @(posedge cpu_clk); 161 | read_i = 1'b0; 162 | end 163 | endtask 164 | endmodule 165 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_replacement_L2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_replacement_L2#( 3 | parameter idx_size = 6, 4 | parameter block_no = 64 5 | ) 6 | ( 7 | input rst_i, 8 | input read_p1_i, 9 | input read_p2_i, 10 | input write_p1_i, 11 | input write_p2_i, 12 | input [idx_size -1 :0] idx_p1_i, 13 | input [idx_size -1 :0] idx_p2_i, 14 | input hit_s1_p1_i, 15 | input hit_s2_p1_i, 16 | input hit_s1_p2_i, 17 | input hit_s2_p2_i, 18 | input valid_out_s1_p1_i, 19 | input valid_out_s2_p1_i, 20 | input valid_out_s1_p2_i, 21 | input valid_out_s2_p2_i, 22 | input ram_write_start_i, 23 | input write_through_i, 24 | output reg we_s1_p1_o, // set1 write signal port 1 25 | output reg we_s2_p1_o, // set2 write signal port 1 26 | output reg we_s1_p2_o, // set1 write signal port 2 27 | output reg we_s2_p2_o // set2 write signal port 2 28 | ); 29 | 30 | reg [block_no-1:0] lru_holder_s2; // holding the LRU (either LRU or not) for each block on set 2 31 | // if lru_holder_s2 is 0 means set 1 was last read, if it is 1 means set 2 was last read 32 | always @ (*) begin 33 | if(rst_i) begin 34 | lru_holder_s2[block_no-1:0] = 1'b0; 35 | end 36 | else if (~(read_p2_i & read_p1_i && (idx_p1_i == idx_p2_i))) begin // Do not update if reading from addresses with the same index 37 | if (hit_s1_p1_i & read_p1_i) begin // if hit port 1 set 1 and read port 1 update lru holder idx_p1 to 0 38 | lru_holder_s2[idx_p1_i] = 1'b0; 39 | end 40 | else if(hit_s2_p1_i & read_p1_i) begin // if hit port 1 set 2 and read port 1 update lru holder idx_p1 to 1 41 | lru_holder_s2[idx_p1_i] = 1'b1; 42 | end 43 | if (hit_s1_p2_i & read_p2_i) begin // if hit port 2 set 1 and read port 2 update lru holder idx_p2 to 0 44 | lru_holder_s2[idx_p2_i] = 1'b0; 45 | end 46 | else if(hit_s2_p2_i & read_p2_i) begin // if hit port 2 set2 and read port 2 update lru holder idx_p2 to 1 47 | lru_holder_s2[idx_p2_i] = 1'b1; 48 | end 49 | end 50 | end 51 | 52 | always@ (*) begin 53 | if(rst_i) begin 54 | we_s2_p1_o = 0; 55 | we_s1_p1_o = 0; 56 | we_s2_p2_o = 0; 57 | we_s1_p2_o = 0; 58 | end 59 | else if(ram_write_start_i) begin // start only if first data is being transferred to not corrupt write enable signals 60 | if ((write_p1_i & write_p2_i) && (idx_p1_i == idx_p2_i)) begin // if writing into same indexes 61 | if(hit_s1_p1_i & write_through_i) begin // if there is write_through look for hit in port 1 if there is a hit in set 1 then write into set1 62 | we_s1_p1_o = 1'b1; 63 | we_s2_p1_o = 1'b0; 64 | we_s1_p2_o = 1'b0; 65 | we_s2_p2_o = 1'b1; 66 | end 67 | else if(hit_s2_p1_i & write_through_i) begin // if there is write_through look for hit in port 1 if there is a hit in set 2 then write into set2 68 | we_s1_p1_o = 1'b0; 69 | we_s2_p1_o = 1'b1; 70 | we_s1_p2_o = 1'b1; 71 | we_s2_p2_o = 1'b0; 72 | end 73 | else begin // if not both than port 1 will be always written to set 1, port 2 will be written to set 2 74 | we_s2_p1_o = 1'b0; 75 | we_s1_p1_o = 1'b1; 76 | we_s2_p2_o = 1'b1; 77 | we_s1_p2_o = 1'b0; 78 | end 79 | end 80 | else begin 81 | if(write_p1_i) begin // if write port 1 82 | if(hit_s1_p1_i & write_through_i) begin // if there is write_through look for hit in port 1 if there is a hit in set 1 then write into set1 83 | we_s1_p1_o = 1'b1; 84 | we_s2_p1_o = 1'b0; 85 | end 86 | else if (hit_s2_p1_i & write_through_i) begin // if there is write_through look for hit in port 1 if there is a hit in set 2 then write into set2 87 | we_s2_p1_o = 1'b1; 88 | we_s1_p1_o = 1'b0; 89 | end 90 | else if(valid_out_s1_p1_i & valid_out_s2_p1_i) begin // if both sets are written (valid bits indicate that) 91 | we_s2_p1_o = ~lru_holder_s2[idx_p1_i]; // logical not value of lru holder decide we signal (because it holds lastly used) 92 | we_s1_p1_o = lru_holder_s2[idx_p1_i]; // value of lru holder decide we signal (because it holds lastly used) 93 | end 94 | else if(valid_out_s1_p1_i) begin // if only set 1 is written than write into set 2 95 | we_s2_p1_o = 1; 96 | we_s1_p1_o = 0; 97 | end 98 | else begin // if written for first time always write to set 1 first 99 | we_s2_p1_o = 0; 100 | we_s1_p1_o = 1; 101 | end 102 | end 103 | if(write_p2_i) begin // if write port 1 104 | if(valid_out_s1_p2_i & valid_out_s2_p2_i) begin // if both sets are written (valid bits indicate that) 105 | we_s2_p2_o = ~lru_holder_s2[idx_p2_i]; // logical not value of lru holder decide we signal (because it holds lastly used) 106 | we_s1_p2_o = lru_holder_s2[idx_p2_i]; // value of lru holder decide we signal (because it holds lastly used) 107 | end 108 | else if(valid_out_s1_p2_i) begin // if only set 1 is written than write into set 2 109 | we_s2_p2_o = 1; 110 | we_s1_p2_o = 0; 111 | end 112 | else begin // if written for first time always write to set 1 first 113 | we_s2_p2_o = 0; 114 | we_s1_p2_o = 1; 115 | end 116 | end 117 | end 118 | end 119 | end 120 | endmodule 121 | 122 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_MEM_L1_data.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Cache_MEM_L1_data#( // L1 data cache top module 4 | parameter block_size = 128, 5 | parameter tag_size = 9, 6 | parameter idx_size = 6, 7 | parameter block_no = 64, 8 | parameter word_size = 2, 9 | parameter offset_size = 2 10 | ) 11 | ( 12 | input clk_i, 13 | input rst_i, 14 | input read_i, 15 | input write_i, 16 | input [2:0] read_instruction_i, //load : 000 => LBU, 001 => LB, 010 => LHU, 011 => LH, 100 => LWU, 101 => LW, 110 => LD 17 | input [2:0] write_instruction_i, //store: 00 => SB, 01 => SH, 10 => SW, 11 => SD 18 | input write_L2_i, 19 | input write_through_i, 20 | input [tag_size+idx_size+word_size+offset_size-1:0] addr_i, 21 | input [63:0] data_core_i, 22 | input [block_size-1:0] data_L2_i, 23 | output [block_size-1:0] data_block_o, 24 | output [63:0] data_o, 25 | output hit_o 26 | ); 27 | // wires 28 | wire [block_size-1:0] data_in_write; 29 | wire [7:0] byte_enable_l; 30 | wire [7:0] byte_enable_h; 31 | wire [tag_size -1:0] tag_input; 32 | wire [idx_size -1:0] idx_input; 33 | wire [word_size-1:0] word_input; 34 | wire [offset_size-1:0] offset_input; 35 | wire cache_set_output_select; 36 | wire [block_size -1:0] data_out_s1; 37 | wire [block_size -1:0] data_out_s2; 38 | wire [tag_size -1:0] tag_out_s1; 39 | wire [tag_size -1:0] tag_out_s2; 40 | wire valid_out_s1; // valid bits with addressing 41 | wire valid_out_s2; // valid bits with addressing 42 | wire we_s1; 43 | wire we_s2; 44 | wire hit_s1; 45 | wire hit_s2; 46 | wire we_set1; 47 | wire we_set2; 48 | 49 | assign tag_input = addr_i[tag_size + idx_size + word_size + offset_size - 1:idx_size + word_size + offset_size]; 50 | assign idx_input = addr_i[idx_size + word_size + offset_size - 1:word_size+offset_size]; 51 | assign word_input = addr_i[word_size+offset_size -1 :offset_size]; 52 | assign offset_input = addr_i[offset_size-1:0]; 53 | 54 | assign we_set2 = write_i & we_s2; 55 | assign we_set1 = write_i & we_s1; 56 | assign hit_o = ((read_i | write_i) & (hit_s1 | hit_s2)) & (~rst_i); 57 | assign cache_set_output_select = ((read_i | write_i) & (hit_s2 & (~hit_s1))); 58 | 59 | Cache_SET_L1_data#( // SET1 60 | .block_size(block_size), 61 | .tag_size(tag_size), 62 | .idx_size(idx_size) 63 | ) 64 | cache_set_0( 65 | .clk_i(clk_i), 66 | .block_i(data_in_write), 67 | .tag_and_idx_i({tag_input,idx_input}), 68 | .we_i(we_set1), 69 | .byte_enable_i({byte_enable_h,byte_enable_l}), 70 | .block_o(data_out_s1), 71 | .valid_o(valid_out_s1), 72 | .tag_o(tag_out_s1) 73 | ); 74 | 75 | Cache_SET_L1_data#( // SET2 76 | .block_size(block_size), 77 | .tag_size(tag_size), 78 | .idx_size(idx_size) 79 | ) 80 | cache_set_1( 81 | .clk_i(clk_i), 82 | .block_i(data_in_write), 83 | .tag_and_idx_i({tag_input,idx_input}), 84 | .we_i(we_set2), 85 | .byte_enable_i({byte_enable_h,byte_enable_l}), 86 | .block_o(data_out_s2), 87 | .valid_o(valid_out_s2), 88 | .tag_o(tag_out_s2) 89 | ); 90 | 91 | Cache_identification#( // IDENTIFICATION FOR SET1 92 | .tag_size(tag_size) 93 | ) 94 | cache_identification_set_0( 95 | .tag_i(tag_input), 96 | .valid_mem(valid_out_s1), 97 | .tag_mem(tag_out_s1), 98 | .hit_o(hit_s1) 99 | ); 100 | 101 | Cache_identification#( // IDENTIFICATION FOR SET2 102 | .tag_size(tag_size) 103 | ) 104 | cache_identification_set_1( 105 | .tag_i(tag_input), 106 | .valid_mem(valid_out_s2), 107 | .tag_mem(tag_out_s2), 108 | .hit_o(hit_s2) 109 | ); 110 | 111 | Cache_replacement_data#( 112 | .idx_size(idx_size), 113 | .block_no(block_no) 114 | ) 115 | cache_replacement_inst( 116 | .rst_i(rst_i), 117 | .read_i(read_i), 118 | .write_i(write_i), 119 | .idx_i(idx_input), 120 | .hit_s1_i(hit_s1), 121 | .hit_s2_i(hit_s2), 122 | .write_L2_i(write_L2_i), 123 | .write_through_i(write_through_i), 124 | .valid_out_s1_i(valid_out_s1), 125 | .valid_out_s2_i(valid_out_s2), 126 | .we_s1_o(we_s1), 127 | .we_s2_o(we_s2) 128 | ); 129 | 130 | Cache_output_set_select #( 131 | .block_size(block_size) 132 | ) 133 | Cache_output_set_select_inst( 134 | .hit_i(hit_o), 135 | .cache_set_output_select_i(cache_set_output_select), 136 | .data_out_s2_i(data_out_s2), 137 | .data_out_s1_i(data_out_s1), 138 | .data_block_o(data_block_o) 139 | ); 140 | 141 | Cache_LOAD_L1_data #( // MODULE THAT DOES THE NECESSARY WORKS FOR LOAD OPERATIONS FROM CORE 142 | .offset_size(offset_size), 143 | .word_size(word_size) 144 | ) 145 | Cache_LOAD_L1_data_inst( 146 | .data_block_i(data_block_o), 147 | .offset_i(offset_input), 148 | .word_i(word_input), 149 | .read_instruction_i(read_instruction_i), 150 | .data_o(data_o) 151 | ); 152 | 153 | Cache_STORE_L1_data#( // MODULE THAT DOES THE NECESSARY WORKS FOR STORE OPERATIONS FROM CORE AND IN CASE OF WRITING FROM L2 154 | .offset_size(offset_size), 155 | .word_size(word_size), 156 | .block_size(block_size) 157 | ) 158 | Cache_STORE_L1_data_inst( 159 | .write_L2_i(write_L2_i), 160 | .data_L2_i(data_L2_i), 161 | .data_core_i(data_core_i), 162 | .offset_i(offset_input), 163 | .word_i(word_input), 164 | .write_instruction_i(write_instruction_i), 165 | .byte_enable_h_o(byte_enable_h), 166 | .byte_enable_l_o(byte_enable_l), 167 | .data_in_write_o(data_in_write) 168 | ); 169 | endmodule 170 | 171 | -------------------------------------------------------------------------------- /CACHE/sim_1/new/Cache_MEM_L1_instr_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_MEM_L1_instr_tb(); 3 | parameter block_size = 128; 4 | parameter tag_size = 9; 5 | parameter idx_size = 6; 6 | parameter word_size = 2; 7 | parameter offset_size = 2; 8 | //reg flag_done_i; 9 | reg cpu_clk; 10 | 11 | reg clk_i; 12 | reg rst_i; 13 | reg read_i; 14 | reg write_i; 15 | wire [tag_size+idx_size+word_size+offset_size-1:0] addr_i; 16 | reg [block_size-1:0] data_L2_i; 17 | wire [31:0] data_o; 18 | wire hit_o; 19 | wire miss_next_o; 20 | reg [tag_size-1:0] tag; 21 | reg [idx_size-1:0] idx; 22 | reg [word_size-1:0] word; 23 | reg [offset_size-1:0] offset; 24 | reg write_next_i; 25 | assign addr_i = {tag, idx, word, offset}; 26 | Cache_MEM_L1_instr#( // L1 instr cache top module 27 | .block_size(block_size), 28 | .tag_size(tag_size), 29 | .word_size(word_size), 30 | .offset_size(offset_size) 31 | ) 32 | Cache_Memory_L1_instr_inst( 33 | .clk_i(clk_i), 34 | .rst_i(rst_i), 35 | .read_i(read_i), // disaridan gelen read sinyali 36 | .write_i(write_i), // disaridan gelen write sinyali 37 | .write_next_i(write_next_i), 38 | .addr_i(addr_i), // 32 bitlik address 39 | .data_L2_i(data_L2_i), // L2'den gelecek block_size'lik data. 40 | //.flag_done_i(flag_done_i), // there was a miss in next address and it is written correctly, read address is now next address 41 | .data_o(data_o), // Core'a gidicek 32 bitlik data (Compressed ise lsb 16 okusun.) 42 | .hit_o(hit_o), // set1 veya set0 da hit var sinyali. 43 | .miss_next_o(miss_next_o) // compressed instruction gelmis onceden 1 kere ve PC+2'den okuma yapiliyor, ve son word'un son offset'inden okuma yapiyorsun yani kayma olmus. Ve sonraki address miss. 44 | ); 45 | 46 | always #4 clk_i = ~clk_i; 47 | always #20 cpu_clk = ~cpu_clk; 48 | initial begin 49 | cpu_clk = 1'b0; 50 | clk_i = 1'b0; 51 | write_next_i = 1'b0; 52 | reset_mem; 53 | /*write_from_L2( 54 | { 55 | 14'b101, 2'b11, 56 | 14'b101, 2'b00, 57 | 14'b100, 2'b10, 58 | 14'b111, 2'b11, 59 | 14'b010, 2'b11, 60 | 14'b001, 2'b00, 61 | 14'b111, 2'b10, 62 | 14'b1111_1111_1111_11, 2'b11 63 | },6'd1,9'd0,2'd0,2'd0 64 | ); 65 | read_L1_instr(6'd1,9'd0,2'd0,2'd0); // 001eFFFF 66 | write_from_L2( 67 | 128'b0,6'd1,9'd1,2'd0,2'd0 68 | ); 69 | read_L1_instr(6'd1,9'd1,2'd0,2'd0); // 0000_0000 70 | read_L1_instr(6'd1,9'd0,2'd0,2'd0); // 001eFFFF 71 | write_from_L2( 72 | 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF,6'd1,9'd2,2'd0,2'd0 73 | ); 74 | read_L1_instr(6'd1,9'd0,2'd0,2'd0); // 001EFFFF 75 | read_L1_instr(6'd1,9'd1,2'd0,2'd0); // miss 76 | read_L1_instr(6'd1,9'd2,2'd0,2'd0); // FFFF 77 | */ 78 | write_from_L2( 79 | { 80 | 14'b101, 2'b11, // nc5 81 | 14'b101, 2'b00, // c4 82 | 14'b100, 2'b10, // c3 83 | 14'b111, 2'b11, 84 | 14'b010, 2'b11, // nc2 85 | 14'b001, 2'b00, // c1 86 | 14'b111, 2'b10, 87 | 14'b000, 2'b11 // nc0 88 | },6'd0,9'd0,2'd0,2'd0); 89 | read_L1_instr(6'd0,9'd0,2'd0,2'd0); //nc0 001e0003 90 | read_L1_instr(6'd0,9'd0,2'd1,2'd0); //c1 0004 91 | read_L1_instr(6'd0,9'd0,2'd1,2'd2); //nc2 001f000b 92 | read_L1_instr(6'd0,9'd0,2'd2,2'd2); //c3 0012 93 | read_L1_instr(6'd0,9'd0,2'd3,2'd0); //c4 0014 94 | read_L1_instr(6'd0,9'd0,2'd3,2'd2); //nc5 if commented out miss_next, else ffff0017 95 | read_i = 1'b1; 96 | #20; 97 | write_next_i = 1'b1; 98 | //read_L1_instr(6'd1,9'd0,2'd3,2'd2); //miss next 99 | data_L2_i = { 100 | 14'b101, 2'b11, 101 | 14'b101, 2'b00, 102 | 14'b100, 2'b10, 103 | 14'b111, 2'b11, 104 | 14'b010, 2'b11, 105 | 14'b001, 2'b00, 106 | 14'b111, 2'b10, 107 | 14'b1111_1111_1111_11, 2'b11 108 | }; 109 | write_i = 1'b1; 110 | #20; 111 | read_i = 1'b0; 112 | write_i = 1'b0; 113 | 114 | read_L1_instr(6'd0,9'd0,2'd3,2'd2); //nc5 if commented out miss_next, else ffff0017 115 | 116 | /*write_from_L2( 117 | { 118 | 14'b101, 2'b11, 119 | 14'b101, 2'b00, 120 | 14'b100, 2'b10, 121 | 14'b111, 2'b11, 122 | 14'b010, 2'b11, 123 | 14'b001, 2'b00, 124 | 14'b111, 2'b10, 125 | 14'b1111_1111_1111_11, 2'b11 126 | },6'd1,9'd0,2'd0,2'd0 127 | );*/ 128 | //read_L1_instr(6'd0,9'd0,2'd3,2'd2); //nc5 ffff0017 129 | #10; 130 | $finish; 131 | end 132 | 133 | task reset_mem(); 134 | begin 135 | rst_i = 1'b1; 136 | #100; 137 | rst_i = 1'b0; 138 | end 139 | endtask 140 | task write_from_L2( 141 | input [block_size-1:0] data, 142 | input [idx_size-1:0] idx_i, 143 | input [tag_size-1:0] tag_i, 144 | input[word_size-1:0] word_i, 145 | input[offset_size-1:0] offset_i 146 | ); 147 | begin 148 | @(posedge cpu_clk); 149 | idx = idx_i; 150 | tag = tag_i; 151 | word = word_i; 152 | offset = offset_i; 153 | data_L2_i = data; 154 | write_i = 1'b1; 155 | #5; 156 | repeat(1)@(posedge cpu_clk); 157 | write_i = 1'b0; 158 | end 159 | endtask 160 | task read_L1_instr( 161 | input [idx_size-1:0] idx_i, 162 | input [tag_size-1:0] tag_i, 163 | input[word_size-1:0] word_i, 164 | input[offset_size-1:0] offset_i 165 | ); 166 | begin 167 | @(posedge cpu_clk); 168 | idx = idx_i; 169 | tag = tag_i; 170 | word = word_i; 171 | offset = offset_i; 172 | read_i = 1'b1; 173 | #5; 174 | repeat(1)@(posedge cpu_clk); 175 | read_i = 1'b0; 176 | end 177 | endtask 178 | endmodule 179 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_MEM_L1_instr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_MEM_L1_instr#( // L1 instr cache top module 3 | parameter block_size = 128, 4 | parameter tag_size = 9, 5 | parameter idx_size = 6, 6 | parameter word_size = 2, 7 | parameter offset_size = 1 // normally it is 2 but lsb bit offset is not being used 8 | ) 9 | ( 10 | input clk_i, 11 | input rst_i, 12 | input read_i, 13 | input instr_write_start_i, 14 | input write_i, 15 | input write_next_i, 16 | input [tag_size+idx_size+word_size+offset_size-1:0] addr_i, 17 | input [block_size-1:0] data_L2_i, 18 | output [31:0] data_o, 19 | output hit_o, 20 | output miss_next_o // Compressed instruction came once before and read from PC+2, and you are reading from the last offset of the last word, so there is slippage. And next address miss. 21 | ); 22 | 23 | wire [block_size -1:0] data_out_s1; 24 | wire [block_size -1:0] data_out_s2; 25 | 26 | wire [15:0] data_out_s1_next; 27 | wire [15:0] data_out_s2_next; 28 | 29 | wire [tag_size-1:0] tag_out_s1; 30 | wire [tag_size-1:0] tag_out_s2; 31 | 32 | wire [tag_size-1:0] tag_out_s1_next; 33 | wire [tag_size-1:0] tag_out_s2_next; 34 | 35 | wire valid_out_s1; 36 | wire valid_out_s2; 37 | 38 | wire valid_out_s1_next; 39 | wire valid_out_s2_next; 40 | 41 | wire [block_size-1:0] data_block_o; 42 | wire [15:0] data_block_o_next; 43 | 44 | wire [tag_size -1:0] tag_input; 45 | wire [idx_size -1:0] idx_input; 46 | wire [word_size-1:0] word_input; 47 | wire offset_input; 48 | 49 | wire cache_set_output_select; 50 | wire cache_set_output_select_next; 51 | 52 | wire we_s1; 53 | wire we_s2; 54 | 55 | wire hit_s1; 56 | wire hit_s2; 57 | 58 | wire hit_s1_next; 59 | wire hit_s2_next; 60 | 61 | wire we_set1; 62 | wire we_set2; 63 | 64 | assign tag_input = addr_i[tag_size + idx_size + word_size + offset_size - 1:idx_size + word_size + offset_size]; 65 | assign idx_input = addr_i[idx_size + word_size + offset_size - 1:word_size+offset_size]; 66 | assign word_input = addr_i[word_size+offset_size -1 :offset_size]; 67 | assign offset_input = addr_i[0]; 68 | 69 | assign we_set2 = write_i & we_s2; 70 | assign we_set1 = write_i & we_s1; 71 | 72 | assign hit_o = ((read_i | write_i) & (hit_s1 | hit_s2)) & (~rst_i); 73 | assign hit_o_next = ((read_i | write_i) & (hit_s1_next | hit_s2_next)) & (~rst_i); 74 | 75 | assign cache_set_output_select = ((read_i | write_i) & (hit_s2 & (~hit_s1))); 76 | assign cache_set_output_select_next = ((read_i | write_i) & (hit_s2_next & (~hit_s1_next))); 77 | 78 | Cache_SET_L1_instr cache_set_1( // SET1 79 | .clk_i(clk_i), 80 | .block_i(data_L2_i), 81 | .tag_and_idx_i({tag_input,idx_input}), 82 | .we_i(we_set1), 83 | .we_next_i(write_next_i), 84 | .block_o(data_out_s1), 85 | .valid_o(valid_out_s1), 86 | .tag_o(tag_out_s1), 87 | .block_next_o(data_out_s1_next), 88 | .valid_next_o(valid_out_s1_next), 89 | .tag_next_o(tag_out_s1_next) 90 | ); 91 | 92 | Cache_SET_L1_instr cache_set_2( // SET2 93 | .clk_i(clk_i), 94 | .block_i(data_L2_i), 95 | .tag_and_idx_i({tag_input,idx_input}), 96 | .we_i(we_set2), 97 | .we_next_i(write_next_i), 98 | .block_o(data_out_s2), 99 | .valid_o(valid_out_s2), 100 | .tag_o(tag_out_s2), 101 | .block_next_o(data_out_s2_next), 102 | .valid_next_o(valid_out_s2_next), 103 | .tag_next_o(tag_out_s2_next) 104 | ); 105 | 106 | Cache_identification cache_identification_set_0( // IDENTIFICATION FOR SET1 107 | .tag_i(tag_input), 108 | .valid_mem(valid_out_s1), 109 | .tag_mem(tag_out_s1), 110 | .hit_o(hit_s1) 111 | ); 112 | 113 | Cache_identification cache_identification_set_0_next( // IDENTIFICATION FOR SET1 NEXT 114 | .tag_i(tag_input), 115 | .valid_mem(valid_out_s1_next), 116 | .tag_mem(tag_out_s1_next), 117 | .hit_o(hit_s1_next) 118 | ); 119 | 120 | Cache_identification cache_identification_set_1( // IDENTIFICATION FOR SET2 121 | .tag_i(tag_input), 122 | .valid_mem(valid_out_s2), 123 | .tag_mem(tag_out_s2), 124 | .hit_o(hit_s2) 125 | ); 126 | 127 | Cache_identification cache_identification_set_1_next( // IDENTIFICATION FOR SET2 NEXT 128 | .tag_i(tag_input), 129 | .valid_mem(valid_out_s2_next), 130 | .tag_mem(tag_out_s2_next), 131 | .hit_o(hit_s2_next) 132 | ); 133 | 134 | Cache_replacement_instr cache_replacement_instr_inst( 135 | .rst_i(rst_i), 136 | .read_i(read_i), 137 | .instr_write_start_i(instr_write_start_i), 138 | .write_i(write_i), 139 | .idx_i(idx_input), 140 | .hit_s1_i(hit_s1), 141 | .hit_s2_i(hit_s2), 142 | .hit_s1_next_i(hit_s1_next), 143 | .hit_s2_next_i(hit_s2_next), 144 | .valid_out_s1_i(valid_out_s1), 145 | .valid_out_s2_i(valid_out_s2), 146 | .we_s1_o(we_s1), 147 | .we_s2_o(we_s2) 148 | ); 149 | 150 | Cache_output_set_select Cache_output_set_select_inst( 151 | .hit_i(hit_o), 152 | .cache_set_output_select_i(cache_set_output_select), 153 | .data_out_s2_i(data_out_s2), 154 | .data_out_s1_i(data_out_s1), 155 | .data_block_o(data_block_o) 156 | ); 157 | 158 | Cache_output_set_select#( 159 | .block_size(16) 160 | ) 161 | Cache_output_set_select_inst_next( 162 | .hit_i(hit_o_next), 163 | .cache_set_output_select_i(cache_set_output_select_next), 164 | .data_out_s2_i(data_out_s2_next), 165 | .data_out_s1_i(data_out_s1_next), 166 | .data_block_o(data_block_o_next) 167 | ); 168 | 169 | Cache_instruction_decode Cache_instruction_decoder_inst( 170 | .read_i(read_i), 171 | .hit_next_i(hit_o_next), 172 | .word_i(word_input), 173 | .offset_i(offset_input), 174 | .data_block_i(data_block_o), 175 | .data_block_next_i(data_block_o_next), 176 | .data_core_o(data_o), 177 | .flag_o(miss_next_o) 178 | ); 179 | 180 | endmodule -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_TOP( 3 | input clk_i, // cache clock 4 | input mem_clk_i, // main mem clock if it is different from cache clock 5 | input rst_i, // active high reset signal 6 | input read_instr_i, // coming from core! read instruction signal 7 | input read_data_i, // coming from core! read data signal 8 | input write_data_i, // coming from core! write data signal 9 | input [18:0] L1_instr_addr_i, // coming from core ! instruction address 10 | input [18:0] L1_data_addr_i, // coming from core ! data address 11 | input [2:0] DATA_read_instruction_i, // coming from core ! what kind of read in data cache (LB, LWU, LH, LD...) 12 | input [2:0] DATA_write_instruction_i, // coming from core ! what kind of read in data cache (SB, SW, SH, SD...) 13 | input [63:0] core_data_i, // coming from core ! data input from core 64 bits 14 | input [31:0] ram_data_i, // data output from ram 15 | output [31:0] core_instr_o, // goes to the core instruction output 16 | output [63:0] core_data_o, // goes to the core data output 17 | output [31:0] ram_data_o, // data input to the ram 18 | output [31:0] ram_read_addr_o, // ram read addr 19 | output [31:0] ram_write_addr_o, // ram write addr 20 | output ram_read_o, // ram read signal 21 | output miss_o, // output miss signal 22 | output [3:0] wr_strb_o, // write strobe output 23 | output write_data_o // data cache is writing to main memory 24 | ); 25 | wire write_through_o; // write through signal indicating that there is will be a write through in L2 and L1 data cache 26 | // L2 wires 27 | wire [127:0] L2_data_block_p1_o; 28 | wire [127:0] L2_data_block_p2_o; 29 | wire [127:0] L2_data_block_p1_i; 30 | wire [18:0] L2_p2_addr; //miss_next varsa sonraki adres olcak 31 | wire [15:0] L2_byte_enable_p1_i; 32 | wire [15:0] L2_byte_enable_p2_i; 33 | wire L2_read_p1; 34 | wire L2_read_p2; 35 | wire L2_write_p1; 36 | wire L2_write_p2; 37 | wire L2_p1_hit; 38 | wire L2_p2_hit; 39 | wire ram_write_start_o; // first write will be done on L2 cache (to not corrupt replacement algorithm) 40 | // L1_instr wires 41 | wire L1_instr_hit; 42 | wire L1_instr_write; 43 | wire L1_miss_next; // miss in next idx and (only given if data is needed from next idx) 44 | wire read_instr_o; // read instruction command coming from controller in case of miss 45 | wire instr_write_start_o; // write start on instruction cache (because of block rams it is being done in 2 clock period) 46 | wire write_next_i; 47 | // L1_data wires 48 | wire write_L2; // write from L2 to the L1 cache 49 | wire read_data_o; // read data command coming from controller in case of miss 50 | wire L1_data_hit; 51 | wire [127:0] L1_data_block_o; 52 | assign L2_data_block_p1_i = (ram_read_o == 1) ? {4{ram_data_i}} : L1_data_block_o; // if there is a ram_read then data port 1 must be ram data input else it is coming from L1 data cache 53 | 54 | Cache_MEM_L1_data Cache_L1_DATA_INST( 55 | .clk_i(clk_i), 56 | .rst_i(rst_i), 57 | .read_i(read_data_o | read_data_i), 58 | .write_i(write_L2 | write_data_o), 59 | .read_instruction_i(DATA_read_instruction_i), 60 | .write_instruction_i(DATA_write_instruction_i), 61 | .write_L2_i(write_L2), 62 | .write_through_i(write_through_o), 63 | .addr_i(L1_data_addr_i), 64 | .data_core_i(core_data_i), 65 | .data_L2_i(L2_data_block_p1_o), 66 | .data_block_o(L1_data_block_o), // buna gerek yok core_data_o'dan yola cikilarak ta yapilabilir? 67 | .data_o(core_data_o), 68 | .hit_o(L1_data_hit) 69 | ); 70 | 71 | Cache_MEM_L1_instr Cache_L1_INSTR( 72 | .clk_i(clk_i), 73 | .rst_i(rst_i), 74 | .read_i(read_instr_o | read_instr_i), //| read_instr_reg_o 75 | .instr_write_start_i(instr_write_start_o), 76 | .write_i(L1_instr_write), 77 | .write_next_i(write_next_i), 78 | .addr_i(L1_instr_addr_i[18:1]), // 79 | .data_L2_i(L2_data_block_p2_o), 80 | .data_o(core_instr_o), 81 | .hit_o(L1_instr_hit), 82 | .miss_next_o(L1_miss_next) 83 | ); 84 | 85 | Cache_MEM_L2 Cache_L2_inst( 86 | .clk_i(clk_i), 87 | .rst_i(rst_i), 88 | .read_p1_i(L2_read_p1), 89 | .read_p2_i(L2_read_p2), 90 | .write_p1_i(L2_write_p1), 91 | .write_p2_i(L2_write_p2), 92 | .data_block_p1_i(L2_data_block_p1_i), 93 | .data_block_p2_i({4{ram_data_i}}), 94 | .byte_enable_p1_i(L2_byte_enable_p1_i), 95 | .byte_enable_p2_i(L2_byte_enable_p2_i), 96 | .addr_p1_i(L1_data_addr_i[14:0]), // word and offset bits do not matter for L2 cache 97 | .addr_p2_i(L2_p2_addr[14:0]), // word and offset bits do not matter for L2 cache 98 | .ram_write_start_i(ram_write_start_o), 99 | .write_through_i(write_through_o), 100 | .data_block_p1_o(L2_data_block_p1_o), 101 | .data_block_p2_o(L2_data_block_p2_o), 102 | .hit_p1_o(L2_p1_hit), 103 | .hit_p2_o(L2_p2_hit) 104 | ); 105 | 106 | Cache_controller Cache_controller_inst( 107 | .clk_i(clk_i), 108 | .mem_clk_i(mem_clk_i), 109 | .rst_i(rst_i), 110 | .L2_data_block_p1_i(L2_data_block_p1_o), 111 | .L1_data_addr_i(L1_data_addr_i), 112 | .L1_instr_addr_i(L1_instr_addr_i), 113 | .L2_p1_hit_i(L2_p1_hit), 114 | .L2_p2_hit_i(L2_p2_hit), 115 | .L1_data_hit_i(L1_data_hit), 116 | .L1_instr_hit_i(L1_instr_hit), 117 | .L1_miss_next_i(L1_miss_next), 118 | .read_instr_i(read_instr_i), 119 | .read_data_i(read_data_i), 120 | .write_data_i(write_data_i), 121 | .DATA_write_instruction_i(DATA_write_instruction_i), 122 | .write_L2_o(write_L2), 123 | .L1_instr_write_o(L1_instr_write), 124 | .L2_read_p1_o(L2_read_p1), 125 | .L2_read_p2_o(L2_read_p2), 126 | .L2_write_p1_o(L2_write_p1), 127 | .L2_write_p2_o(L2_write_p2), 128 | .L2_byte_enable_p1_o(L2_byte_enable_p1_i), 129 | .L2_byte_enable_p2_o(L2_byte_enable_p2_i), 130 | .L2_p2_addr_o(L2_p2_addr), 131 | .ram_data_o(ram_data_o), 132 | .ram_read_addr_o(ram_read_addr_o), 133 | .ram_write_addr_o(ram_write_addr_o), 134 | .ram_read_o(ram_read_o), 135 | .miss_o(miss_o), 136 | .ram_write_start_o(ram_write_start_o), 137 | .write_next_o(write_next_i), 138 | .wr_strb_o(wr_strb_o), 139 | .read_data_o(read_data_o), 140 | .read_instr_o(read_instr_o), 141 | .write_data_o(write_data_o), 142 | .write_through_o(write_through_o), 143 | .instr_write_start_o(instr_write_start_o) 144 | ); 145 | 146 | endmodule 147 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_MEM_L2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_MEM_L2#( // L2 cache 3 | parameter block_size = 128, 4 | parameter tag_size = 7, 5 | parameter idx_size = 8, 6 | parameter block_no = 256 7 | ) 8 | ( 9 | input clk_i, 10 | input rst_i, 11 | input read_p1_i, 12 | input read_p2_i, 13 | input write_p1_i, 14 | input write_p2_i, 15 | input [block_size-1:0] data_block_p1_i, 16 | input [block_size-1:0] data_block_p2_i, 17 | input [15:0] byte_enable_p1_i, 18 | input [15:0] byte_enable_p2_i, 19 | input [tag_size+idx_size-1:0] addr_p1_i, 20 | input [tag_size+idx_size-1:0] addr_p2_i, 21 | input ram_write_start_i, 22 | input write_through_i, 23 | output [block_size-1:0] data_block_p1_o, // data out read port 1 (data cache & main memory write) 24 | output [block_size-1:0] data_block_p2_o, // data out read port 2 (instr cache write) 25 | output hit_p1_o, 26 | output hit_p2_o 27 | ); 28 | // wires 29 | wire valid_out_s1_p1; // valid bits with addressing 30 | wire valid_out_s2_p1; // valid bits with addressing 31 | wire valid_out_s1_p2; 32 | wire valid_out_s2_p2; 33 | 34 | wire [tag_size-1:0] tag_out_s1_p1; 35 | wire [tag_size-1:0] tag_out_s2_p1; 36 | wire [tag_size-1:0] tag_out_s1_p2; 37 | wire [tag_size-1:0] tag_out_s2_p2; 38 | 39 | 40 | wire [tag_size -1:0] tag_input_p1; 41 | wire [idx_size -1:0] idx_input_p1; 42 | wire [tag_size -1:0] tag_input_p2; 43 | wire [idx_size -1:0] idx_input_p2; 44 | 45 | wire cache_set_output_select_p1; 46 | wire cache_set_output_select_p2; 47 | 48 | wire [block_size -1:0] data_out_s1_p1; 49 | wire [block_size -1:0] data_out_s2_p1; 50 | wire [block_size -1:0] data_out_s1_p2; 51 | wire [block_size -1:0] data_out_s2_p2; 52 | 53 | wire we_s1_p1_o; 54 | wire we_s2_p1_o; 55 | wire we_s1_p2_o; 56 | wire we_s2_p2_o; 57 | 58 | wire hit_s1_p1; 59 | wire hit_s2_p1; 60 | wire hit_s1_p2; 61 | wire hit_s2_p2; 62 | 63 | wire we_set1_p1; 64 | wire we_set2_p1; 65 | wire we_set1_p2; 66 | wire we_set2_p2; 67 | 68 | assign tag_input_p2 = addr_p2_i[tag_size + idx_size - 1:idx_size]; 69 | assign idx_input_p2 = addr_p2_i[idx_size - 1:0]; 70 | 71 | assign tag_input_p1 = addr_p1_i[tag_size + idx_size - 1:idx_size]; 72 | assign idx_input_p1 = addr_p1_i[idx_size - 1:0]; 73 | 74 | 75 | assign we_set2_p1 = write_p1_i & we_s2_p1_o; 76 | assign we_set1_p1 = write_p1_i & we_s1_p1_o; 77 | assign we_set2_p2 = write_p2_i & we_s2_p2_o; 78 | assign we_set1_p2 = write_p2_i & we_s1_p2_o; 79 | 80 | assign hit_p1_o = ((read_p1_i) & (hit_s1_p1 | hit_s2_p1)) & (~rst_i); 81 | assign hit_p2_o = ((read_p2_i) & (hit_s1_p2 | hit_s2_p2)) & (~rst_i); 82 | 83 | assign cache_set_output_select_p1 = ((read_p1_i) & (hit_s2_p1 & (~hit_s1_p1))); 84 | assign cache_set_output_select_p2 = ((read_p2_i) & (hit_s2_p2 & (~hit_s1_p2))); 85 | 86 | Cache_SET_L2 Cache_L2_set1( 87 | .clk_i(clk_i), 88 | .block_p1_i(data_block_p1_i), 89 | .block_p2_i(data_block_p2_i), 90 | .tag_and_idx_p1_i({tag_input_p1,idx_input_p1}), 91 | .tag_and_idx_p2_i({tag_input_p2,idx_input_p2}), 92 | .we_p1_i(we_set1_p1), 93 | .we_p2_i(we_set1_p2), 94 | .byte_enable_p1_i(byte_enable_p1_i), 95 | .byte_enable_p2_i(byte_enable_p2_i), 96 | .block_p1_o(data_out_s1_p1), 97 | .block_p2_o(data_out_s1_p2), 98 | .valid_p1_o(valid_out_s1_p1), 99 | .valid_p2_o(valid_out_s1_p2), 100 | .tag_p1_o(tag_out_s1_p1), 101 | .tag_p2_o(tag_out_s1_p2) 102 | ); 103 | 104 | Cache_SET_L2 Cache_L2_set2( 105 | .clk_i(clk_i), 106 | .block_p1_i(data_block_p1_i), 107 | .block_p2_i(data_block_p2_i), 108 | .tag_and_idx_p1_i({tag_input_p1,idx_input_p1}), 109 | .tag_and_idx_p2_i({tag_input_p2,idx_input_p2}), 110 | .we_p1_i(we_set2_p1), 111 | .we_p2_i(we_set2_p2), 112 | .byte_enable_p1_i(byte_enable_p1_i), 113 | .byte_enable_p2_i(byte_enable_p2_i), 114 | .block_p1_o(data_out_s2_p1), 115 | .block_p2_o(data_out_s2_p2), 116 | .valid_p1_o(valid_out_s2_p1), 117 | .valid_p2_o(valid_out_s2_p2), 118 | .tag_p1_o(tag_out_s2_p1), 119 | .tag_p2_o(tag_out_s2_p2) 120 | ); 121 | 122 | Cache_identification#( // IDENTIFICATION FOR SET1 READ PORT 1 123 | .tag_size(tag_size) 124 | ) 125 | cache_identification_set_1_r1( 126 | .tag_i(tag_input_p1), 127 | .valid_mem(valid_out_s1_p1), 128 | .tag_mem(tag_out_s1_p1), 129 | .hit_o(hit_s1_p1) 130 | ); 131 | 132 | Cache_identification#( // IDENTIFICATION FOR SET1 READ PORT 2 133 | .tag_size(tag_size) 134 | ) 135 | cache_identification_set_1_r2( 136 | .tag_i(tag_input_p2), 137 | .valid_mem(valid_out_s1_p2), 138 | .tag_mem(tag_out_s1_p2), 139 | .hit_o(hit_s1_p2) 140 | ); 141 | 142 | Cache_identification#( // IDENTIFICATION FOR SET2 READ PORT 1 143 | .tag_size(tag_size) 144 | ) 145 | cache_identification_set_2_r1( 146 | .tag_i(tag_input_p1), 147 | .valid_mem(valid_out_s2_p1), 148 | .tag_mem(tag_out_s2_p1), 149 | .hit_o(hit_s2_p1) 150 | ); 151 | 152 | Cache_identification#( // IDENTIFICATION FOR SET2 READ PORT 2 153 | .tag_size(tag_size) 154 | ) 155 | cache_identification_set_2_r2( 156 | .tag_i(tag_input_p2), 157 | .valid_mem(valid_out_s2_p2), 158 | .tag_mem(tag_out_s2_p2), 159 | .hit_o(hit_s2_p2) 160 | ); 161 | 162 | Cache_replacement_L2#( // REPLACEMENT ALGORITMASI 163 | .idx_size(idx_size), 164 | .block_no(block_no) 165 | ) 166 | cache_replacement_L2_inst( 167 | .rst_i(rst_i), 168 | .read_p1_i(read_p1_i), 169 | .read_p2_i(read_p2_i), 170 | .write_p1_i(write_p1_i), 171 | .write_p2_i(write_p2_i), 172 | .idx_p1_i(idx_input_p1), 173 | .idx_p2_i(idx_input_p2), 174 | .hit_s1_p1_i(hit_s1_p1), 175 | .hit_s2_p1_i(hit_s2_p1), 176 | .hit_s1_p2_i(hit_s1_p2), 177 | .hit_s2_p2_i(hit_s2_p2), 178 | .valid_out_s1_p1_i(valid_out_s1_p1), 179 | .valid_out_s2_p1_i(valid_out_s2_p1), 180 | .valid_out_s1_p2_i(valid_out_s1_p2), 181 | .valid_out_s2_p2_i(valid_out_s2_p2), 182 | .ram_write_start_i(ram_write_start_i), 183 | .write_through_i(write_through_i), 184 | .we_s1_p1_o(we_s1_p1_o), 185 | .we_s2_p1_o(we_s2_p1_o), 186 | .we_s1_p2_o(we_s1_p2_o), 187 | .we_s2_p2_o(we_s2_p2_o) 188 | ); 189 | 190 | Cache_output_set_select #( 191 | .block_size(block_size) 192 | ) 193 | Cache_output_set_select_inst_P1( 194 | .hit_i(hit_p1_o | write_through_i), 195 | .cache_set_output_select_i(cache_set_output_select_p1), 196 | .data_out_s2_i(data_out_s2_p1), 197 | .data_out_s1_i(data_out_s1_p1), 198 | .data_block_o(data_block_p1_o) 199 | ); 200 | 201 | Cache_output_set_select #( 202 | .block_size(block_size) 203 | ) 204 | Cache_output_set_select_inst_P2( 205 | .hit_i(hit_p2_o), 206 | .cache_set_output_select_i(cache_set_output_select_p2), 207 | .data_out_s2_i(data_out_s2_p2), 208 | .data_out_s1_i(data_out_s1_p2), 209 | .data_block_o(data_block_p2_o) 210 | ); 211 | 212 | endmodule -------------------------------------------------------------------------------- /CACHE/sim_1/new/Cache_MEM_L2_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_MEM_L2_tb(); 3 | parameter block_size = 128; 4 | parameter tag_size = 7; 5 | parameter idx_size = 8; 6 | parameter word_size = 2; 7 | parameter offset_size = 2; 8 | 9 | reg clk_i; 10 | reg rst_i; 11 | reg read_p1_i; // disaridan gelen read sinyali port 1 12 | reg read_p2_i; // disaridan gelen read sinyali port 2 13 | reg write_p1_i; // disaridan gelen write sinyali port 1 14 | reg write_p2_i; // disaridan gelen write sinyali port 2 15 | reg [block_size-1:0] data_block_p1_i;// 128 bitlik gelen input data port 1 16 | reg [block_size-1:0] data_block_p2_i;// 128 bitlik gelen input data port 2 17 | reg [3:0] word_enable_p1_i; // disaridan gelen write icin word enable sinyali port 1 18 | reg [3:0] word_enable_p2_i; // disaridan gelen write icin word enable sinyali port 2 19 | wire [tag_size+idx_size+word_size+offset_size-1:0] addr_p1_i; 20 | wire [tag_size+idx_size+word_size+offset_size-1:0] addr_p2_i; 21 | wire [block_size-1:0] data_block_p1_o; // data out read port 1 (data cache & main memory write) 22 | wire [block_size-1:0] data_block_p2_o; // data out read port 2 (instr cache write) 23 | wire hit_p1_o; // read-port 1 hit 24 | wire hit_p2_o; // read-port 2 hit 25 | 26 | reg cpu_clk; 27 | reg [tag_size-1:0] tag_p1; 28 | reg [idx_size-1:0] idx_p1; 29 | reg [word_size-1:0] word_p1; 30 | reg [offset_size-1:0] offset_p1; 31 | assign addr_p1_i = {tag_p1, idx_p1, word_p1, offset_p1}; 32 | 33 | reg [tag_size-1:0] tag_p2; 34 | reg [idx_size-1:0] idx_p2; 35 | reg [word_size-1:0] word_p2; 36 | reg [offset_size-1:0] offset_p2; 37 | assign addr_p2_i = {tag_p2, idx_p2, word_p2, offset_p2}; 38 | 39 | 40 | Cache_MEM_L2 Cache_MEM_L2_inst( 41 | .clk_i(clk_i), 42 | .rst_i(rst_i), 43 | .read_p1_i(read_p1_i), // disaridan gelen read sinyali port 1 44 | .read_p2_i(read_p2_i), // disaridan gelen read sinyali port 2 45 | .write_p1_i(write_p1_i), // disaridan gelen write sinyali port 1 46 | .write_p2_i(write_p2_i), // disaridan gelen write sinyali port 2 47 | .data_block_p1_i(data_block_p1_i), // 128 bitlik gelen input data port 1 48 | .data_block_p2_i(data_block_p2_i), // 128 bitlik gelen input data port 2 49 | .byte_enable_p1_i(16'hFFFF), // disaridan gelen write icin word enable sinyali port 1 50 | .byte_enable_p2_i(16'hFFFF), // disaridan gelen write icin word enable sinyali port 2 51 | .addr_p1_i(addr_p1_i), // 32 bitlik address read port 1 52 | .addr_p2_i(addr_p2_i), // 32 bitlik address read port 2 53 | .data_block_p1_o(data_block_p1_o), // data out read port 1 (data cache & main memory write) 54 | .data_block_p2_o(data_block_p2_o), // data out read port 2 (instr cache write) 55 | .hit_p1_o(hit_p1_o), // read-port 1 hit 56 | .hit_p2_o(hit_p2_o) // read-port 2 hit 57 | ); 58 | 59 | always #5 clk_i = ~clk_i; 60 | always #20 cpu_clk =~cpu_clk; 61 | initial begin 62 | cpu_clk = 0; 63 | clk_i = 0; 64 | reset_mem; 65 | write_port1_port2(128'd15,8'd1,7'd5,2'd0,2'd0,4'b1111,128'd20,8'd1,7'd6,2'd0,2'd0,4'b1111); 66 | read_port1(8'd1,7'd5,2'd0,2'd0); // read 15 port 1 67 | read_port1(8'd1,7'd6,2'd0,2'd0); // read 20 port 1 68 | read_port2(8'd1,7'd5,2'd0,2'd0); // read 15 port 2 69 | read_port2(8'd1,7'd6,2'd0,2'd0); // read 20 port 2 70 | read_port1_port2(8'd1,7'd5,2'd0,2'd0,8'd1,7'd6,2'd0,2'd0); // read 15 port 1 - read 20 port 2 71 | 72 | write_port1_port2(128'd10,8'd1,7'd9,2'd0,2'd0,4'b1111,128'd30,8'd6,7'd6,2'd0,2'd0,4'b1111); 73 | read_port1_port2(8'd1,7'd9,2'd0,2'd0,8'd1,7'd6,2'd0,2'd0); // read 10 port 1 - read 20 port 2 74 | read_port1(8'd6,7'd6,2'd0,2'd0); // read 30 port 1 75 | read_port2(8'd1,7'd6,2'd0,2'd0); // read 20 port 2 76 | write_port2(128'd40,8'd0,7'd5,2'd0,2'd0,4'b1111); 77 | read_port1_port2(8'd0,7'd5,2'd0,2'd0,8'd6,7'd6,2'd0,2'd0); // read 40 port 1 - read 30 port 2 78 | read_port1(8'd0,7'd5,2'd0,2'd0); // read 40 port 1 79 | write_port2(128'd10,8'd0,7'd1,2'd0,2'd0,4'b1111); 80 | read_port1_port2(8'd0,7'd1,2'd0,2'd0,8'd0,7'd5,2'd0,2'd0); // read 10 port 1 - read 40 port 2 81 | read_port1(8'd0,7'd5,2'd0,2'd0); // read 40 port 1 82 | read_port1(8'd0,7'd1,2'd0,2'd0); // read 10 port 1 83 | read_port2(8'd0,7'd1,2'd0,2'd0); // read 10 port 2 84 | read_port2(8'd0,7'd5,2'd0,2'd0); // read 40 port 2 85 | $finish; 86 | end 87 | 88 | 89 | task reset_mem(); 90 | begin 91 | rst_i = 1'b1; 92 | #100; 93 | rst_i = 1'b0; 94 | #100; 95 | end 96 | endtask 97 | 98 | task read_port1_port2( 99 | input [idx_size-1:0] idx_i, 100 | input [tag_size-1:0] tag_i, 101 | input [word_size-1:0] word_i, 102 | input [offset_size-1:0] offset_i, 103 | input [idx_size-1:0] idx_i2, 104 | input [tag_size-1:0] tag_i2, 105 | input [word_size-1:0] word_i2, 106 | input [offset_size-1:0] offset_i2 107 | ); 108 | begin 109 | @(posedge cpu_clk); 110 | idx_p1 = idx_i; 111 | tag_p1 = tag_i; 112 | word_p1 = word_i; 113 | offset_p1 = offset_i; 114 | idx_p2 = idx_i2; 115 | tag_p2 = tag_i2; 116 | word_p2 = word_i2; 117 | offset_p2 = offset_i2; 118 | read_p1_i = 1'b1; 119 | read_p2_i = 1'b1; 120 | #5; 121 | @(posedge cpu_clk); 122 | read_p1_i = 1'b0; 123 | read_p2_i = 1'b0; 124 | end 125 | endtask 126 | task write_port1_port2( 127 | input [block_size-1:0] data, 128 | input [idx_size-1:0] idx_i, 129 | input [tag_size-1:0] tag_i, 130 | input [word_size-1:0] word_i, 131 | input [offset_size-1:0] offset_i, 132 | input [3:0] word_enable, 133 | input [block_size-1:0] data2, 134 | input [idx_size-1:0] idx_i2, 135 | input [tag_size-1:0] tag_i2, 136 | input [word_size-1:0] word_i2, 137 | input [offset_size-1:0] offset_i2, 138 | input [3:0] word_enable2 139 | ); 140 | begin 141 | @(posedge cpu_clk); 142 | idx_p1 = idx_i; 143 | tag_p1 = tag_i; 144 | word_p1 = word_i; 145 | offset_p1 = offset_i; 146 | word_enable_p1_i = word_enable; 147 | data_block_p1_i = data; 148 | idx_p2 = idx_i2; 149 | tag_p2 = tag_i2; 150 | word_p2 = word_i2; 151 | offset_p2 = offset_i2; 152 | word_enable_p2_i = word_enable2; 153 | data_block_p2_i = data2; 154 | write_p1_i = 1'b1; 155 | write_p2_i = 1'b1; 156 | #5; 157 | @(posedge cpu_clk); 158 | write_p1_i = 1'b0; 159 | write_p2_i = 1'b0; 160 | end 161 | endtask 162 | task write_port1( 163 | input [block_size-1:0] data, 164 | input [idx_size-1:0] idx_i, 165 | input [tag_size-1:0] tag_i, 166 | input [word_size-1:0] word_i, 167 | input [offset_size-1:0] offset_i, 168 | input [3:0] word_enable 169 | ); 170 | begin 171 | @(posedge cpu_clk); 172 | idx_p1 = idx_i; 173 | tag_p1 = tag_i; 174 | word_p1 = word_i; 175 | offset_p1 = offset_i; 176 | word_enable_p1_i = word_enable; 177 | data_block_p1_i = data; 178 | write_p1_i = 1'b1; 179 | #5; 180 | @(posedge cpu_clk); 181 | write_p1_i = 1'b0; 182 | end 183 | endtask 184 | 185 | task write_port2( 186 | input [block_size-1:0] data, 187 | input [idx_size-1:0] idx_i, 188 | input [tag_size-1:0] tag_i, 189 | input [word_size-1:0] word_i, 190 | input [offset_size-1:0] offset_i, 191 | input [3:0] word_enable 192 | ); 193 | begin 194 | @(posedge cpu_clk); 195 | idx_p2 = idx_i; 196 | tag_p2 = tag_i; 197 | word_p2 = word_i; 198 | offset_p2 = offset_i; 199 | word_enable_p2_i = word_enable; 200 | data_block_p2_i = data; 201 | write_p2_i = 1'b1; 202 | #5; 203 | @(posedge cpu_clk); 204 | write_p2_i = 1'b0; 205 | end 206 | endtask 207 | 208 | task read_port1( 209 | input [idx_size-1:0] idx_i, 210 | input [tag_size-1:0] tag_i, 211 | input [word_size-1:0] word_i, 212 | input [offset_size-1:0] offset_i 213 | ); 214 | begin 215 | @(posedge cpu_clk); 216 | idx_p1 = idx_i; 217 | tag_p1 = tag_i; 218 | word_p1 = word_i; 219 | offset_p1 = offset_i; 220 | read_p1_i = 1'b1; 221 | #5; 222 | @(posedge cpu_clk); 223 | read_p1_i = 1'b0; 224 | end 225 | endtask 226 | 227 | task read_port2( 228 | input [idx_size-1:0] idx_i, 229 | input [tag_size-1:0] tag_i, 230 | input [word_size-1:0] word_i, 231 | input [offset_size-1:0] offset_i 232 | ); 233 | begin 234 | @(posedge cpu_clk); 235 | idx_p2 = idx_i; 236 | tag_p2 = tag_i; 237 | word_p2 = word_i; 238 | offset_p2 = offset_i; 239 | read_p2_i = 1'b1; 240 | #5; 241 | @(posedge cpu_clk); 242 | read_p2_i = 1'b0; 243 | end 244 | endtask 245 | endmodule 246 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/teknofest_ram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: TUBITAK TUTEL 4 | // Engineer: 5 | // 6 | // Create Date: 27.04.2022 10:41:19 7 | // Design Name: TEKNOFEST 8 | // Module Name: teknofest_ram 9 | // Project Name: TEKNOFEST 10 | // Target Devices: Nexys A7 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module teknofest_ram #( 24 | parameter NB_COL = 4, 25 | parameter COL_WIDTH = 8, 26 | parameter RAM_DEPTH = 131072, 27 | parameter INIT_FILE = "C:/Users/TUTEL/Desktop/TEKNOFEST/tekno_sw/outputs/hex/uart_test.hex" 28 | ) 29 | ( 30 | input clk_i, 31 | input rst_ni, 32 | 33 | input [clogb2(RAM_DEPTH-1)-1:0] wr_addr, 34 | input [clogb2(RAM_DEPTH-1)-1:0] rd_addr, 35 | input [(NB_COL*COL_WIDTH)-1:0] wr_data, 36 | input [NB_COL-1:0] wr_strb, 37 | output [(NB_COL*COL_WIDTH)-1:0] rd_data, 38 | 39 | input rd_en, 40 | input ram_prog_rx_i, 41 | output system_reset_o, 42 | output prog_mode_led_o 43 | ); 44 | 45 | localparam CPU_CLK = 100_000_000; //Default CPU frequency on FPGA 46 | localparam BAUD_RATE = 9600; //Default Baud rate for programming on the run via UART 47 | 48 | reg [(NB_COL*COL_WIDTH)-1:0] ram [RAM_DEPTH-1:0]; 49 | reg [(NB_COL*COL_WIDTH)-1:0] ram_data; 50 | 51 | wire [31:0] ram_prog_data; 52 | wire ram_prog_data_valid; 53 | 54 | reg [clogb2(RAM_DEPTH-1)-1:0] prog_addr; 55 | wire [clogb2(RAM_DEPTH-1)-1:0] wr_addr_ram; 56 | wire [(NB_COL*COL_WIDTH)-1:0] wr_data_ram; 57 | 58 | assign wr_addr_ram = (prog_mode_led_o && ram_prog_data_valid) ? prog_addr : wr_addr; 59 | assign wr_data_ram = (prog_mode_led_o && ram_prog_data_valid) ? ram_prog_data : wr_data; 60 | 61 | generate 62 | if (INIT_FILE != "") begin: use_init_file 63 | initial 64 | $readmemh(INIT_FILE, ram, 0, RAM_DEPTH-1); 65 | end else begin: init_bram_to_zero 66 | integer ram_index; 67 | initial 68 | for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) 69 | ram[ram_index] = {(NB_COL*COL_WIDTH){1'b0}}; 70 | end 71 | endgenerate 72 | 73 | always @(posedge clk_i) 74 | if (rd_en) 75 | ram_data <= ram[rd_addr]; 76 | 77 | generate 78 | genvar i; 79 | for (i = 0; i < NB_COL; i = i+1) begin: byte_write 80 | always @(posedge clk_i) 81 | if (wr_strb[i] || (prog_mode_led_o && ram_prog_data_valid)) 82 | ram[wr_addr_ram][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= wr_data_ram[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; 83 | end 84 | endgenerate 85 | 86 | always @(posedge clk_i) begin 87 | if (!(rst_ni && system_reset_o)) begin 88 | prog_addr <= 'h0; 89 | end else begin 90 | if (prog_mode_led_o && ram_prog_data_valid) begin 91 | prog_addr <= prog_addr + 1'b1; 92 | end 93 | end 94 | end 95 | 96 | assign rd_data = ram_data; 97 | 98 | // The following function calculates the address width based on specified RAM depth 99 | function integer clogb2; 100 | input integer depth; 101 | for (clogb2=0; depth>0; clogb2=clogb2+1) 102 | depth = depth >> 1; 103 | endfunction 104 | 105 | // programmer program_ram( 106 | // .clock(clk_i), 107 | // .reset(rst_ni), 108 | // .rx(ram_prog_rx_i), 109 | // .ReceivedInstruction(ram_prog_data), 110 | // .ReceivedInstructionValid(ram_prog_data_valid), 111 | // .SystemReset(system_reset_o), 112 | // .ProbRx(ProbRx), 113 | // .ProgMode(prog_mode_led_o) 114 | // ); 115 | 116 | localparam PROGRAM_SEQUENCE = "TEKNOFEST"; 117 | localparam PROG_SEQ_LENGTH = 9 ; 118 | localparam SEQ_BREAK_THRESHOLD = 32'd1000000; 119 | 120 | reg [PROG_SEQ_LENGTH*8-1:0] received_sequence; 121 | reg [3:0] rcv_seq_ctr; 122 | 123 | reg [31:0] sequence_break_ctr; 124 | wire sequence_break; 125 | wire [31:0] prog_uart_do; 126 | 127 | localparam SequenceWait = 3'b000; 128 | localparam SequenceReceive = 3'b001; 129 | localparam SequenceCheck = 3'b011; 130 | localparam SequenceLengthCalc = 3'b010; 131 | localparam SequenceProgram = 3'b110; 132 | localparam SequenceFinish = 3'b100; 133 | 134 | reg [2:0] state_prog; 135 | reg [2:0] state_prog_next; 136 | reg [1:0] instruction_byte_ctr; 137 | reg [31:0] prog_instruction; 138 | reg [31:0] prog_intr_number; 139 | reg [31:0] prog_intr_ctr; 140 | 141 | reg prog_inst_valid; 142 | reg prog_sys_rst_n; 143 | wire ram_prog_rd_en; 144 | 145 | assign ram_prog_data = prog_instruction; 146 | assign ram_prog_data_valid = prog_inst_valid; 147 | assign system_reset_o = prog_sys_rst_n; 148 | assign ram_prog_rd_en = (state_prog != SequenceFinish); 149 | assign prog_mode_led_o = (state_prog == SequenceProgram); 150 | assign sequence_break = sequence_break_ctr == SEQ_BREAK_THRESHOLD; 151 | 152 | always @(posedge clk_i) begin 153 | if (!rst_ni) begin 154 | state_prog <= SequenceWait; 155 | end else begin 156 | state_prog <= state_prog_next; 157 | end 158 | end 159 | 160 | always @(*) begin 161 | state_prog_next = state_prog; 162 | case (state_prog) 163 | SequenceWait: begin 164 | if (prog_uart_do != ~0) begin 165 | state_prog_next = SequenceReceive; 166 | end 167 | end 168 | SequenceReceive: begin 169 | if (prog_uart_do != ~0) begin 170 | if (rcv_seq_ctr == PROG_SEQ_LENGTH-1) begin 171 | state_prog_next = SequenceCheck; 172 | end 173 | end else if (sequence_break) begin 174 | state_prog_next = SequenceWait; 175 | end 176 | end 177 | SequenceCheck: begin 178 | if (received_sequence == PROGRAM_SEQUENCE) begin 179 | state_prog_next = SequenceLengthCalc; 180 | end else begin 181 | state_prog_next = SequenceWait; 182 | end 183 | end 184 | SequenceLengthCalc: begin 185 | if ((prog_uart_do != ~0) && &instruction_byte_ctr) begin 186 | state_prog_next = SequenceProgram; 187 | end 188 | end 189 | SequenceProgram: begin 190 | if (prog_intr_ctr == prog_intr_number) begin 191 | state_prog_next = SequenceFinish; 192 | end 193 | end 194 | SequenceFinish: begin 195 | state_prog_next = SequenceWait; 196 | end 197 | endcase 198 | end 199 | 200 | always @(posedge clk_i) begin 201 | if (!rst_ni) begin 202 | instruction_byte_ctr <= 2'b0; 203 | prog_instruction <= 32'h0; 204 | prog_intr_number <= 32'h0; 205 | prog_intr_ctr <= 32'h0; 206 | sequence_break_ctr <= 32'h0; 207 | received_sequence <= 72'h0; 208 | rcv_seq_ctr <= 4'h0; 209 | prog_inst_valid <= 1'b0; 210 | prog_sys_rst_n <= 1'b1; 211 | end else begin 212 | case (state_prog) 213 | SequenceWait: begin 214 | instruction_byte_ctr <= 2'b0; 215 | prog_instruction <= 32'h0; 216 | prog_intr_number <= 32'h0; 217 | prog_intr_ctr <= 32'h0; 218 | sequence_break_ctr <= 32'h0; 219 | received_sequence <= 72'h0; 220 | rcv_seq_ctr <= 4'h0; 221 | prog_inst_valid <= 1'b0; 222 | prog_sys_rst_n <= 1'b1; 223 | if (prog_uart_do != ~0) begin 224 | rcv_seq_ctr <= rcv_seq_ctr + 4'h1; 225 | received_sequence <= {received_sequence[PROG_SEQ_LENGTH*8-9:0],prog_uart_do[7:0]}; 226 | end 227 | end 228 | SequenceReceive: begin 229 | if (prog_uart_do != ~0) begin 230 | received_sequence <= {received_sequence[PROG_SEQ_LENGTH*8-9:0],prog_uart_do[7:0]}; 231 | if (rcv_seq_ctr == PROG_SEQ_LENGTH-1) begin 232 | rcv_seq_ctr <= 4'h0; 233 | end else begin 234 | rcv_seq_ctr <= rcv_seq_ctr + 4'h1; 235 | end 236 | end else begin 237 | if (sequence_break) begin 238 | sequence_break_ctr <= 32'h0; 239 | rcv_seq_ctr <= 4'h0; 240 | end else begin 241 | sequence_break_ctr <= sequence_break_ctr + 32'h1; 242 | end 243 | end 244 | end 245 | SequenceCheck: begin 246 | instruction_byte_ctr <= 2'b0; 247 | end 248 | SequenceLengthCalc: begin 249 | prog_intr_ctr <= 32'h0; 250 | if (prog_uart_do != ~0) begin 251 | prog_intr_number <= {prog_intr_number[3*8-1:0],prog_uart_do[7:0]}; 252 | if (&instruction_byte_ctr) begin 253 | instruction_byte_ctr <= 2'b0; 254 | end else begin 255 | instruction_byte_ctr <= instruction_byte_ctr + 2'b1; 256 | end 257 | end 258 | end 259 | SequenceProgram: begin 260 | if (prog_uart_do != ~0) begin 261 | prog_instruction <= {prog_instruction[3*8-1:0],prog_uart_do[7:0]}; 262 | if (&instruction_byte_ctr) begin 263 | instruction_byte_ctr <= 2'b0; 264 | prog_inst_valid <= 1'b1; 265 | prog_intr_ctr <= prog_intr_ctr + 32'h1; 266 | end else begin 267 | instruction_byte_ctr <= instruction_byte_ctr + 2'b1; 268 | prog_inst_valid <= 1'b0; 269 | end 270 | end else begin 271 | prog_inst_valid <= 1'b0; 272 | end 273 | end 274 | SequenceFinish: begin 275 | prog_sys_rst_n <= 1'b0; 276 | end 277 | endcase 278 | end 279 | end 280 | 281 | simpleuart #( 282 | .DEFAULT_DIV(CPU_CLK/BAUD_RATE) 283 | ) 284 | simpleuart ( 285 | .clk (clk_i), 286 | .resetn (rst_ni), 287 | 288 | .ser_tx (), 289 | .ser_rx (ram_prog_rx_i), 290 | 291 | .reg_div_we (4'h0), 292 | .reg_div_di (4'h0), 293 | .reg_div_do (), 294 | 295 | .reg_dat_we (1'b0), 296 | .reg_dat_re (ram_prog_rd_en), 297 | .reg_dat_di (32'h0), 298 | .reg_dat_do (prog_uart_do), 299 | .reg_dat_wait() 300 | ); 301 | 302 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Cache 2 | ## L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC 3 | 4 | In the cache design, as specified in the specification, the instruction and data memory is separated at the 1st level, and a unified design has been made at the 2nd level. The block diagram showing the connections of the cache with the memory unit (RAM) located outside the core and the chip and the connections within the cache itself can be seen below. The reset input is not shown in the block diagram due to the large number of cables. Each level cache and controller also have reset inputs. The cache controller was written as a single module in the design, but it is shown here as two modules, because it makes the block diagram more readable. 5 | 6 | ![q](https://user-images.githubusercontent.com/81713653/185472909-7442a3be-75b6-40bb-a718-2c6bccf4df05.jpg) 7 | 8 |
9 | Figure 1: Cache Block Diagram 10 |
11 | 12 | 13 | 14 | In the 1st level cache designs, there is a single address entry since the write and read operations cannot be done from different addresses at the same time. In the 2nd level cache design, there are two write and two read inputs, so there are separate addresses for these ports (2 address entries in total). The reason for choosing two read inputs is to ensure that both level 1 caches can be read simultaneously from level 2 cache without waiting for each other. Even if the 1st level instruction cache will not write directly to the 2nd level cache, if there is a miss situation in the 2nd level cache's instruction read input, there will be a write from the external memory and 2 write entries have been selected since it is possible to perform a write operation from the data cache at the same time. In the 2nd level cache design, being able to read and write from 2 different inputs increased the performance, but made the design process more difficult and increased the space usage. SRAM technology was primarily intended to be used in the design of memory blocks. With the help of SRAM technology, 6 transistors, 2 capacitors and a sense amplifier, a one-bit memory can be created. On the contrary, in registers (D-Flip Flop) made with NAND logic gates, a total of 8 NAND gates are used. Since the NAND gate consists of 4 transistors, there are 32 transistors in total. Although the space usage in the one-bit memory design made with D-FF is higher than that of SRAM technology, it remains much slower in terms of speed compared to the design made with D-FF due to the use of a sense amplifier in SRAM technology. During the design process, it was aimed to create caches in SRAM technology with the help of OpenRAM. Although OpenRAM supports Sky130 technology, caches could not be created with SRAM technology due to errors in synthesis stages and problems in the library files of memory units to be created for multi-input writing/reading purposes. A design made with D-FFs is in focus. In the design made with D-FF, a more flexible design could be made since the memory design was entirely in the hands of the designer. 15 | 16 | In all level caches, 2-level set associativity is preferred in the block placement stage. The most important reasons for this preference are the small size of the cache, the reduction of the miss rate when switching from direct mapped to the 2-level set associative compared to other levels, and minimizing the hit time in caches. The long-term effect of increasing the level of set association on different memory sizes can be seen in Figure 2. 17 | 18 | 19 | ![image](https://user-images.githubusercontent.com/81713653/185473947-39952eec-367d-4cab-931a-a85598cef1fd.png) 20 | 21 | Figure 2: Effect of Set Associativity Level on Hit Rate for Different Memory Sizes [1] 22 | 23 | 24 | 25 | The cache line size has been chosen as 128-bit. For ease of design, the cache line size has been kept the same at all levels. 128-bit selection of line size, 2-bit byte selection, 2-bit word selection (in-block word number), 7-bit tag, and 8-bit index when address range is 19-bit as specified in the 2nd level caches. an addressing has been made. For the 1st level caches, unlike the 2nd level, the index is 6-bit and the tag is 9-bit. The reason for this change is due to the fact that the 1st level caches are 2 KB and the 2nd level cache is 8 KB. Since the set associativity is selected, the tag bits in the accessed index number will be checked in parallel for both sets while performing the block diagnosis. Level 1 cache has 64 blocks for both sets, while level 2 cache has 256 blocks. Associative selection with a 2-level set reduced the miss rate, but required the use of extra space as it required the storage of the tag bits, the use of a replacement algorithm, and the comparison of the stored tag bits with the tag bits at the incoming address. In the replacement phase, the LRU (Least Recently Used) algorithm is used. Since the set associativity level is chosen as 2, the LRU algorithm is implemented with the help of a 64-bit register in the 1st level caches (separately for the instruction and data caches), and with the help of a 256-bit register in the 2nd level cache. While reading from an address in the algorithm, if a hit occurs, the LRU bit of the set with that index is updated. In the case of write, if there are valid bits in both sets of the address to be written, writing is made to the set with the last unread index number. On the other hand, if only one of the sets has a valid bit while writing, the other set will be the one to write. If both have no valid bits (first-time writes), writes are always made to the first set. 26 | 27 | In the replacement algorithm, some additions have been made since the core will write to the 1st level data cache. If there is a hit at the address written by the core, the data should be written to the hit set, not to the set selected by the LRU. In the 2nd level cache, some changes have been made in the replacement algorithm because there are 2 read and 2 write entries. If it is desired to read from 2 entries with the same index but different addresses at the same time, the LRU bit in that index is not updated. If the 2 write entries have the same index but want to write to different addresses, the LRU algorithm is ignored and the first and second cluster are written to, respectively. 28 | 29 | Write-through was chosen as the writing policy. Although write-through takes longer than later write-back, which is another write policy, such a preference has been made due to the small cache sizes and the fact that peripherals have access to memory. Other factors in choosing a write-through policy are that in the case of a post-write, one dirty bit must be kept for each block, so controlling them increases the latency, and the design of direct-write is simpler than write-back. Write-throughs are only the result of a write operation by the core to the level 1 data cache. This write operation is controlled by the cache controller. 30 | 31 | The communication of the cache with the memory unit located outside the chip is provided with the help of the cache controller. Necessary write and read signals are sent to the outside. Since the external memory unit can read and write 32-bit and can only read from one input at a time, if a 128-bit read is to be made, the address is sent and the least meaningless 2nd bit of the address is 1 A row transfer is provided by increasing each. If the core writes to the data cache, the necessary bits of the write_strobe signal in the memory unit are activated according to the size of this write. Since the external memory unit will be 64-bit at most, the write operation is done twice and the least meaningless 2nd bit of the address is incremented by one at the end of the first write operation. If the 2nd level cache misses on both read inputs, the miss problem of the data cache is always taken care of first, then the miss problem of the instruction cache is solved, since a simultaneous write operation can be made from the external memory unit. 32 | 33 | In the top-level cache design, the processor waits for the instruction cache read signal and address information by the core, and sends the read data to the core. On the load side of the data cache, in addition to these, the read operation is a byte-addressable data, and additionally asks for information on how to read, and this information is included in the funct3 signal in the 32-bit decoded instruction. For the store side of the data cache, the write signal and the data to be written are expected. As with reading, knowledge of the funct3 signal is required. If it misses any of the caches, this signal is transmitted to the core and the core delays itself until there is a hit signal from the cache. 34 | 35 | Since the data always comes to the most meaningless bits in the write operation (storage) coming to the data cache at the 1st level, as a result of decoding the 32-bit instruction, with the help of funct3 bits, the bits coming from the core are shifted as necessary and then the decoded instruction is written as a result. On the read (load) side, the most meaningless bits should always be output. 36 | 37 | In the 1st level instruction cache, since compressed (16-bit) and normal (32-bit) instructions coexist, the data to go to the core should be selected accordingly. This selection means that if the last two bits of the data at the given address are "11", it is normal, otherwise it is a compressed instruction. After reading one compressed instruction, the alignment in the cache shifts until another compressed instruction is read, so extra processing is required when reading the instructions. Finally, if the word at the end of the line is wanted to be read after the compressed command is read once, since reading should be done from the address with the next index, the interior design always looks at the data coming from the address with the index. In such a case, if there is a miss at the next address, a write is made here from the higher-level cache. If there is a hit, the output is given data directly and the LRU bit of the set containing the data with the next index is also updated. 38 | 39 | ## REFERENCES: 40 | 41 | 1- Asanovic, K., & Stojanovic, V. (n.d.). Great Ideas in Computer Architecture (Machine Structures) Caches Part 2. Retrieved July 9, 2022, from https://inst.eecs.berkeley.edu/~cs61c/sp15/lec/15/2015Sp-CS61C-L15-kavs-Caches2-6up.pdf 42 | 43 | 44 | -------------------------------------------------------------------------------- /CACHE/sim_1/new/Cache_TOP_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_TOP_tb(); 3 | parameter block_size = 128; 4 | parameter tag_size = 9; 5 | parameter idx_size = 6; 6 | parameter word_size = 2; 7 | parameter offset_size = 2; 8 | parameter RAM_DEPTH = 131072; 9 | reg mem_clk_i; 10 | reg cpu_clk; 11 | reg clk_i; 12 | reg rst_i; 13 | reg read_instr_i; // coming from core! 14 | reg read_data_i; // coming from core! 15 | reg write_data_i; // coming from core! 16 | wire [18:0] L1_instr_addr_i; // coming from core ! 17 | wire [18:0] L1_data_addr_i; // coming from core ! 18 | reg [2:0] DATA_read_instruction_i; // coming from core ! 19 | reg [2:0] DATA_write_instruction_i; // coming from core ! 20 | reg [63:0] core_data_i; // coming from core ! 21 | wire [31:0] ram_data_i; // data that will read from RAM 22 | wire [31:0] core_instr_o; // goes to the core 23 | wire [63:0] core_data_o; // goes to the core 24 | wire [31:0] ram_data_o; // data that will be written to RAM 25 | wire [31:0] ram_read_addr_o; 26 | wire [31:0] ram_write_addr_o; 27 | wire ram_read_o; 28 | wire miss_o; 29 | wire [3:0] wr_strb_o; 30 | //wire write_data_o; 31 | reg ram_prog_rx_i; 32 | wire system_reset_o; 33 | wire prog_mode_led_o; 34 | 35 | reg [tag_size-1:0] tag_instr; 36 | reg [idx_size-1:0] idx_instr; 37 | reg [word_size-1:0] word_instr; 38 | reg [offset_size-1:0] offset_instr; 39 | 40 | assign L1_instr_addr_i = {tag_instr,idx_instr,word_instr,offset_instr}; 41 | 42 | reg [tag_size-1:0] tag_data; 43 | reg [idx_size-1:0] idx_data; 44 | reg [word_size-1:0] word_data; 45 | reg [offset_size-1:0] offset_data; 46 | 47 | assign L1_data_addr_i = {tag_data,idx_data,word_data,offset_data}; 48 | 49 | parameter SB = 3'b000, 50 | SH = 3'b001, 51 | SW = 3'b010, 52 | SD = 3'b011; 53 | parameter LBU = 3'b100, 54 | LB = 3'b000, 55 | LHU = 3'b101, 56 | LH = 3'b001, 57 | LWU = 3'b110, 58 | LW = 3'b010, 59 | LD = 3'b011; 60 | teknofest_ram #( 61 | .NB_COL(4), 62 | .COL_WIDTH(8), 63 | .RAM_DEPTH(RAM_DEPTH), 64 | .INIT_FILE("tekno_example.hex") // Location of the init file 65 | ) main_memory 66 | ( 67 | .clk_i (mem_clk_i ), 68 | .rst_ni (~rst_i), 69 | .wr_addr (ram_write_addr_o[18:2]), 70 | .rd_addr (ram_read_addr_o[18:2]), 71 | .wr_data (ram_data_o), 72 | 73 | .wr_strb (wr_strb_o ), 74 | .rd_data (ram_data_i ), 75 | .rd_en (ram_read_o ), 76 | .ram_prog_rx_i (ram_prog_rx_i ), 77 | .system_reset_o (system_reset_o), 78 | .prog_mode_led_o (prog_mode_led_o ) 79 | ); 80 | 81 | Cache_TOP Cache_top_inst( 82 | .clk_i(clk_i), 83 | .mem_clk_i(mem_clk_i), 84 | .rst_i(rst_i), 85 | .read_instr_i(read_instr_i), 86 | .read_data_i(read_data_i), 87 | .write_data_i(write_data_i),// 88 | .L1_instr_addr_i(L1_instr_addr_i), 89 | .L1_data_addr_i(L1_data_addr_i), // 90 | .DATA_read_instruction_i(DATA_read_instruction_i),// 91 | .DATA_write_instruction_i(DATA_write_instruction_i), // 92 | .core_data_i(core_data_i), 93 | .ram_data_i(ram_data_i), 94 | .core_instr_o(core_instr_o), 95 | .core_data_o(core_data_o), 96 | .ram_data_o(ram_data_o), 97 | .ram_read_addr_o(ram_read_addr_o), 98 | .ram_write_addr_o(ram_write_addr_o), 99 | .ram_read_o(ram_read_o), 100 | .miss_o(miss_o), 101 | .wr_strb_o(wr_strb_o), 102 | .write_data_o(write_data_o) 103 | ); 104 | 105 | always #6.25 clk_i = ~clk_i; 106 | always #6.25 cpu_clk = ~cpu_clk; 107 | always #6.25 mem_clk_i =~mem_clk_i; 108 | initial begin // initiliaze and reset 109 | read_instr_i = 1'b0; 110 | read_data_i = 1'b0; 111 | write_data_i = 1'b0; 112 | DATA_read_instruction_i = 3'b0; 113 | DATA_write_instruction_i = 3'b0; 114 | core_data_i = 64'b0; 115 | ram_prog_rx_i = 1'b0; 116 | mem_clk_i = 1'b1; 117 | clk_i = 1'b1; 118 | cpu_clk = 1'b1; 119 | #100; 120 | reset_mem(); 121 | #2000; 122 | //$finish; 123 | end 124 | 125 | /* 126 | initial begin // test instruction 127 | #100; 128 | ram_data_i = 32'd50; 129 | read_instr(0,0,0,0); // miss L1 & L2, then read 50 130 | ram_data_i = 32'd40; 131 | read_instr(0,1,0,0); // miss L1 & L2, then read 40 132 | ram_data_i = 32'b1111_1111_1111_1111_1111_1111_1111_1111; 133 | read_instr(0,2,0,0); // miss L1 & L2, then read 80 134 | read_instr(0,0,0,0); // miss L1, then read 50 135 | ram_data_i = 32'd100; 136 | read_instr(1,2,0,0); // write 100 to next ix 137 | read_instr(0,2,3,3); // miss next. 138 | #100; 139 | end 140 | */ 141 | 142 | initial begin // test finalized 143 | #2500; 144 | read_data(5,0,0,0,LD); // 00000b9300000b13 -miss L1 data,L2 unified 145 | read_data(5,0,1,0,LD); // 00000c1300000b93 -hit 146 | read_data(5,0,2,0,LD); // 00000c9300000c13 -hit 147 | read_data(9,0,0,0,LW); // 00000093 -Miss L1 data, L2 unified 148 | read_data(9,0,1,0,LW); // 7850006f -hit 149 | read_data(9,0,2,0,LW); // 00001797 -hit 150 | read_data(9,0,3,0,LW); // 4c878793 -hit 151 | write_data(64'b100,0,0,0,0,SB); // store 4 to address 0 -write Miss will occur 152 | read_data(0,0,0,0,LW); // 0000000000000004 -hit 153 | read_data(0,0,1,0,LW); // 0000000000001100 -hit 154 | read_data(0,0,2,0,LW); // 0000000000000002 -hit 155 | read_data(0,0,3,0,LW); // 0000000000000003 -hit 156 | write_data(64'B1111,0,0,2,0,SB); // store 1111 to address 2 -write 157 | read_data(0,0,2,0,LD); // 000000030000000f -hit 158 | read_data(1,0,0,1,LBU); // 00000000000000ba -miss L1 data, L2 unified 159 | read_instr(0,0,0,0); // 00000004 -miss L1 instr 160 | read_instr(2,0,0,0);// 00000513 -miss L1 instr, L2 unified 161 | read_instr(2,0,3,2);// 07130593 -miss L1 instr, L2 unified (next idx) 162 | read_instr(2,1,0,0);// 0016f693 -miss L1 instr, L2 unified 163 | read_instr(2,0,0,0);// 00000513 -hit 164 | read_instr(2,1,0,0);// 0016f693 -hit 165 | read_instr(2,2,0,0);// 00812e23 -miss L1 instr, L2 unified 166 | read_instr(2,1,0,0);// 0016f693 -hitt 167 | read_instr(2,0,0,0);// 00000513 -miss L1 instr, L2 unified 168 | read_data(0,0,0,0,LW); // 0000000000000004 -hit 169 | read_instr(0,0,1,0); // 00001100 - hit 170 | read_instr(1,0,0,0); // 0000ba98 - hit 171 | read_data_instr(0,0,1,0_,0,0,0,0,LD); // data: 0000110000000004, instr: 00001100 -- hit 172 | read_data_instr(5,0,1,0_,6,0,0,0,LD); // data: 00000d9300000d13, instr: 00000b93 -- miss L1 instr & data, miss L2 173 | #500; 174 | $finish; 175 | 176 | end 177 | 178 | task reset_mem(); 179 | begin 180 | rst_i = 1'b1; 181 | #1000; 182 | rst_i = 1'b0; 183 | end 184 | endtask 185 | 186 | task read_instr( 187 | input [idx_size-1:0] idx_i, 188 | input [tag_size-1:0] tag_i, 189 | input[word_size-1:0] word_i, 190 | input[offset_size-1:0] offset_i 191 | ); 192 | begin 193 | #4; 194 | idx_instr = idx_i; 195 | tag_instr = tag_i; 196 | word_instr = word_i; 197 | offset_instr = offset_i; 198 | read_instr_i = 1'b1; 199 | repeat(2)@(posedge cpu_clk); 200 | read_instr_i = 1'b0; 201 | #2; 202 | @(posedge cpu_clk); 203 | while(miss_o) 204 | @(posedge cpu_clk); 205 | end 206 | endtask 207 | 208 | task read_data( 209 | input [idx_size-1:0] idx_i, 210 | input [tag_size-1:0] tag_i, 211 | input[word_size-1:0] word_i, 212 | input[offset_size-1:0] offset_i, 213 | input [2:0] read_instr); 214 | begin 215 | #4; 216 | DATA_read_instruction_i = read_instr; 217 | idx_data = idx_i; 218 | tag_data = tag_i; 219 | word_data = word_i; 220 | offset_data = offset_i; 221 | read_data_i = 1'b1; 222 | repeat(2)@(posedge cpu_clk); 223 | read_data_i = 1'b0; 224 | #2; 225 | @(posedge cpu_clk); 226 | 227 | while(miss_o) 228 | @(posedge cpu_clk); 229 | 230 | 231 | end 232 | endtask 233 | 234 | task write_data( 235 | input [63:0] data, 236 | input [idx_size-1:0] idx_i, 237 | input [tag_size-1:0] tag_i, 238 | input [word_size-1:0] word_i, 239 | input [offset_size-1:0] offset_i, 240 | input [2:0] write_instr); 241 | begin 242 | #4; 243 | DATA_write_instruction_i = write_instr; 244 | idx_data = idx_i; 245 | tag_data = tag_i; 246 | word_data = word_i; 247 | offset_data = offset_i; 248 | core_data_i = data; 249 | write_data_i = 1'b1; 250 | repeat(2)@(posedge cpu_clk); 251 | write_data_i = 1'b0; 252 | #2; 253 | repeat(2)@(posedge cpu_clk); 254 | #2; 255 | while(miss_o | write_data_o == 1'b1) 256 | @(posedge cpu_clk); 257 | 258 | end 259 | 260 | endtask 261 | 262 | task read_data_instr( 263 | input [idx_size-1:0] idx_instr_i, 264 | input [tag_size-1:0] tag_instr_i, 265 | input[word_size-1:0] word_instr_i, 266 | input[offset_size-1:0] offset_instr_i, 267 | input [idx_size-1:0] idx_data_i, 268 | input [tag_size-1:0] tag_data_i, 269 | input[word_size-1:0] word_data_i, 270 | input[offset_size-1:0] offset_data_i, 271 | input [2:0] read_instr 272 | ); 273 | begin 274 | #4; 275 | idx_instr = idx_instr_i; 276 | tag_instr = tag_instr_i; 277 | word_instr = word_instr_i; 278 | offset_instr = offset_instr_i; 279 | idx_data = idx_data_i; 280 | tag_data = tag_data_i; 281 | word_data = word_data_i; 282 | offset_data = offset_data_i; 283 | DATA_read_instruction_i = read_instr; 284 | read_data_i = 1'b1; 285 | read_instr_i = 1'b1; 286 | repeat(2)@(posedge cpu_clk); 287 | read_data_i = 1'b0; 288 | read_instr_i = 1'b0; 289 | #2; 290 | while(miss_o == 1'b1) 291 | @(posedge cpu_clk); 292 | end 293 | endtask 294 | endmodule 295 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_STORE_L1_data.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Cache_STORE_L1_data#(parameter offset_size = 2, parameter word_size = 2, parameter block_size = 128)( 3 | input write_L2_i, // write from L2 4 | input [block_size-1:0] data_L2_i, // input from L2 cahe 5 | input [63:0] data_core_i, // input from core 6 | input [offset_size-1:0] offset_i, 7 | input [word_size-1:0] word_i, 8 | input [2:0] write_instruction_i, 9 | output reg [7:0] byte_enable_h_o, // high indexed byte enable signals 10 | output reg [7:0] byte_enable_l_o, // low indexed byte enable signals 11 | output reg [block_size-1:0] data_in_write_o // which data will be written into L1 data cache 12 | ); 13 | 14 | parameter SB = 3'b000, // parametric STORE signals (according to RISC-V FUNCT3) 15 | SH = 3'b001, 16 | SW = 3'b010, 17 | SD = 3'b011; 18 | 19 | always @(*) begin 20 | if(write_L2_i) begin // If write from L2 all byte enables are 1 21 | data_in_write_o = data_L2_i; 22 | byte_enable_h_o = 8'b1111_1111; 23 | byte_enable_l_o = 8'b1111_1111; 24 | end 25 | else begin 26 | case(write_instruction_i) // Here, actually byte_enables are manipulated and controlled according to the word and offsets. At the same time, data_in_write should be changed in the same way so that the written data is compatible with the byte_enable signals there. 27 | SB: begin 28 | data_in_write_o = {16{data_core_i[7:0]}}; // Since LSB will be written in 8 bits, we will copy it to all bits so that there is no error. 29 | if(word_i == 2'b11) begin 30 | byte_enable_l_o = 8'b0000_0000; //word_i [1] == 1 so byte_enable_l_o = 0 31 | if (offset_i == 2'b00) begin 32 | byte_enable_h_o = 8'b0001_0000; // the most meaningless byte_enable of the high word of the high side 1 33 | end 34 | else if(offset_i == 2'b01) begin 35 | byte_enable_h_o = 8'b0010_0000; // byte_enable of the 1st byte of the high word of the high side is 1 36 | end 37 | else if(offset_i == 2'b10) begin 38 | byte_enable_h_o = 8'b0100_0000; // byte_enable of the 2nd byte of the high word of the high side is 1 39 | end 40 | else begin 41 | byte_enable_h_o = 8'b1000_0000; // byte_enable of the 3rd byte of the high word of the high side is 1 42 | end 43 | end 44 | else if (word_i == 2'b10) begin 45 | byte_enable_l_o = 8'b0000_0000; //word_i [1] == 1 so byte_enable_l_o = 0 46 | if (offset_i == 2'b00) begin 47 | byte_enable_h_o = 8'b0000_0001; // the most meaningless byte_enable of the low word of the high side is 1 48 | end 49 | else if(offset_i == 2'b01) begin 50 | byte_enable_h_o = 8'b0000_0010; // byte_enable of the 1st byte of the low word of the high side is 1 51 | end 52 | else if(offset_i == 2'b10) begin 53 | byte_enable_h_o = 8'b0000_0100; // byte_enable of the 2nd byte of the low word of the high side is 1 54 | end 55 | else begin 56 | byte_enable_h_o = 8'b0000_1000; // byte_enable of the 3rd byte of the low word of the high side is 1 57 | end 58 | end 59 | else if (word_i == 2'b01) begin 60 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 so byte_enable_h_o = 0 61 | if (offset_i == 2'b00) begin 62 | byte_enable_l_o = 8'b0001_0000; // the most meaningless byte_enable of the high word of the low side is 1 63 | end 64 | else if(offset_i == 2'b01) begin 65 | byte_enable_l_o = 8'b0010_0000; // byte_enable of the 1st byte of the high word of the low side is 1 66 | end 67 | else if(offset_i == 2'b10) begin 68 | byte_enable_l_o = 8'b0100_0000; // byte_enable of the 2nd byte of the high word of the low side is 1 69 | end 70 | else begin 71 | byte_enable_l_o = 8'b1000_0000; // byte_enable of the 3rd byte of the high word of the low side is 1 72 | end 73 | end 74 | else begin 75 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 so byte_enable_h_o = 0 76 | if (offset_i == 2'b00) begin 77 | byte_enable_l_o = 8'b0000_0001; // the most meaningless byte_enable of the low word of the low side is 1 78 | end 79 | else if(offset_i == 2'b01) begin 80 | byte_enable_l_o = 8'b0000_0010; // byte_enable of 1st byte of low word of low side is 1 81 | end 82 | else if(offset_i == 2'b10) begin 83 | byte_enable_l_o = 8'b0000_0100; // byte_enable of 2nd byte of low word of low side is 1 84 | end 85 | else begin 86 | byte_enable_l_o = 8'b0000_1000; // byte_enable of 3rd byte of low word of low side is 1 87 | end 88 | end 89 | end 90 | SH: begin 91 | if(word_i == 2'b11) begin 92 | byte_enable_l_o = 8'b0000_0000; //word_i [1] == 1 so byte_enable_l_o = 0 93 | if (offset_i == 2'b00) begin 94 | byte_enable_h_o = 8'b0011_0000; // byte_enable of the 2 most meaningless bytes of the high word of the high side is 1 95 | data_in_write_o = {16'b0,data_core_i[15:0],32'b0,64'b0}; // data is aligned to the same place as the byte_enable signals 96 | end 97 | else if(offset_i == 2'b01) begin 98 | byte_enable_h_o = 8'b0110_0000; // 2nd and 3rd byte of high word of high side byte_enable is 1 99 | data_in_write_o = {8'b0,data_core_i[15:0],8'b0,32'b0,64'b0}; // data is aligned to the same place as the byte_enable signals 100 | end 101 | else if(offset_i == 2'b10) begin 102 | byte_enable_h_o = 8'b1100_0000; // 3rd and 4th byte of high word of high side byte_enable is 1 103 | data_in_write_o = {data_core_i[15:0],16'b0,32'b0,64'b0}; // data is aligned to the same place as the byte_enable signals 104 | end 105 | else begin // Logic ERROR. Reading is made from non-Word. Algorithmic continuation can also be done here, but it is non-logical. 106 | byte_enable_h_o = 8'b0000_0000; 107 | data_in_write_o = {128'b0}; 108 | end 109 | end 110 | else if(word_i == 2'b10) begin 111 | byte_enable_l_o = 8'b0000_0000; //word_i [1] == 1 so byte_enable_l_o = 0 112 | if (offset_i == 2'b00) begin 113 | byte_enable_h_o = 8'b0000_0011; // byte_enable of the 2 most meaningless bytes of the low word of the high side is 1 114 | data_in_write_o = {48'b0,data_core_i[15:0],64'b0}; // data is aligned to the same place as the byte_enable signals 115 | end 116 | else if(offset_i == 2'b01) begin 117 | byte_enable_h_o = 8'b0000_0110; // 2nd and 3rd byte of low word of high side byte_enable is 1 118 | data_in_write_o = {40'b0,data_core_i[15:0],8'b0,64'b0}; // data is aligned to the same place as the byte_enable signals 119 | end 120 | else if(offset_i == 2'b10) begin 121 | byte_enable_h_o = 8'b0000_1100; // 3rd and 4th byte of low word of high side byte_enable is 1 122 | data_in_write_o = {32'b0,data_core_i[15:0],16'b0,64'b0}; // data is aligned to the same place as the byte_enable signals 123 | end 124 | else begin // Logic ERROR. Reading is made from non-Word. Algorithmic continuation can also be done here, but it is non-logical. 125 | byte_enable_h_o = 8'b0000_0000; 126 | data_in_write_o = {128'b0}; 127 | end 128 | end 129 | else if(word_i == 2'b01) begin 130 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 so byte_enable_h_o = 0 131 | if (offset_i == 2'b00) begin 132 | byte_enable_l_o = 8'b0011_0000; // byte_enable of the 2 most meaningless bytes of the high word of the low side is 1 133 | data_in_write_o = {64'b0,16'b0,data_core_i[15:0],32'b0}; // data is aligned to the same place as the byte_enable signals 134 | end 135 | else if(offset_i == 2'b01) begin 136 | byte_enable_l_o = 8'b0110_0000; // 2nd and 3rd byte of high word of low side byte_enable is 1 137 | data_in_write_o = {64'b0,8'b0,data_core_i[15:0],8'b0,32'b0}; // data is aligned to the same place as the byte_enable signals 138 | end 139 | else if(offset_i == 2'b10) begin 140 | byte_enable_l_o = 8'b1100_0000; // 3rd and 4th byte of high word of low side byte_enable is 1 141 | data_in_write_o = {64'b0,data_core_i[15:0],16'b0,32'b0}; // data is aligned to the same place as the byte_enable signals 142 | end 143 | else begin // Logic ERROR. Reading is made from non-Word. Algorithmic continuation can also be done here, but it is non-logical. 144 | byte_enable_l_o = 8'b0000_0000; 145 | data_in_write_o = {128'b0}; 146 | end 147 | end 148 | else begin 149 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 oldugundan byte_enable_h_o = 0 olacak 150 | if (offset_i == 2'b00) begin 151 | byte_enable_l_o = 8'b0000_0011; // byte_enable of the 2 most meaningless bytes of the low word of the low side is 1 152 | data_in_write_o = {64'b0,48'b0,data_core_i[15:0]}; // data is aligned to the same place as the byte_enable signals 153 | end 154 | else if(offset_i == 2'b01) begin 155 | byte_enable_l_o = 8'b0000_0110; // 2nd and 3rd byte of low word of low side byte_enable is 1 156 | data_in_write_o = {64'b0,40'b0,data_core_i[15:0],8'b0}; // data is aligned to the same place as the byte_enable signals 157 | end 158 | else if(offset_i == 2'b10) begin 159 | byte_enable_l_o = 8'b0000_1100; // 3rd and 4th byte of low word of low side byte_enable is 1 160 | data_in_write_o = {64'b0,32'b0,data_core_i[15:0],16'b0}; // data is aligned to the same place as the byte_enable signals 161 | end 162 | else begin // Logic ERROR. Reading is made from non-Word. Algorithmic continuation can also be done here, but it is non-logical. 163 | byte_enable_l_o = 8'b0000_0000; 164 | data_in_write_o = {128'b0}; 165 | end 166 | end 167 | end 168 | SW: begin 169 | data_in_write_o = {4{data_core_i[31:0]}}; // Since LSB will be written in 32 bits, we will copy it to all bits so that there is no error. 170 | if(word_i == 2'b11) begin 171 | byte_enable_l_o = 8'b0000_0000; //word_i [1] == 1 so byte_enable_l_o = 0 172 | byte_enable_h_o = 8'b1111_0000; // Since word_i == 2'b11, the byte enable of the high word of the high side is 1 173 | end 174 | else if(word_i == 2'b10) begin 175 | byte_enable_l_o = 8'b0000_0000; //Since word_i [1] == 1, so byte_enable_l_o = 0 176 | byte_enable_h_o = 8'b0000_1111; // Since word_i == 2'b10, the byte enable of the low word of the high side is 1 177 | end 178 | else if(word_i == 2'b01) begin 179 | byte_enable_l_o = 8'b1111_0000; // Since word i == 2'b01, byte enable of high word of low side is 1 180 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 so byte_enable_h_o = 0 181 | end 182 | else begin 183 | byte_enable_l_o = 8'b0000_1111; // Since word i == 2'b00, byte enable of low word of low side is 1 184 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 so byte_enable_h_o = 0 185 | end 186 | end 187 | SD: begin 188 | data_in_write_o = {2{data_core_i[63:0]}}; // Since LSB 64 bit is written, we will copy it to all bits so that there is no error. 189 | if(word_i[1] == 1'b1) begin 190 | byte_enable_h_o = 8'b1111_1111; // Since the store will be made into a double word and word_i is [1] == 1, all byte_enable_h_o will be 1 191 | byte_enable_l_o = 8'b0000_0000; //word_i [1] == 1 so byte_enable_l_o = 0 192 | end 193 | else begin 194 | byte_enable_h_o = 8'b0000_0000; //word_i [1] == 0 so byte_enable_h_o = 0 195 | byte_enable_l_o = 8'b1111_1111; // Since the store will be made into a double word and word_i is [1] == 0, all byte_enable_l_o will be 1 196 | end 197 | end 198 | default: begin 199 | byte_enable_h_o = 8'b0000_0000; 200 | byte_enable_l_o = 8'b0000_0000; 201 | data_in_write_o = 128'b0; 202 | end 203 | endcase 204 | end 205 | end 206 | endmodule 207 | -------------------------------------------------------------------------------- /CACHE/sim_1/new/tekno_example.hex: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00001100 3 | 00000002 4 | 00000003 5 | FEDCBA98 6 | 00000393 7 | 00000413 8 | 00000493 9 | 00000513 10 | 05930592 11 | 00000613 12 | 05930693 13 | 00000713 14 | 00000793 15 | 00000813 16 | 00000893 17 | 00000913 18 | 00000993 19 | 00000a13 20 | 00000a93 21 | 00000b13 22 | 00000b93 23 | 00000c13 24 | 00000c93 25 | 00000d13 26 | 00000d93 27 | 00000e13 28 | 00000e93 29 | 00000f13 30 | 00000f93 31 | 00002197 32 | f8818193 33 | 00000093 34 | 200010b7 35 | 00109093 36 | ffc08113 37 | 00000093 38 | 7850006f 39 | 00001797 40 | 4c878793 41 | 0007a783 42 | 0007a503 43 | 00157513 44 | 00008067 45 | 00001797 46 | 4b078793 47 | 0007a783 48 | ff010113 49 | 00812423 50 | 0007a783 51 | 00112623 52 | 00050413 53 | 0017f793 54 | 00079063 55 | 00a00793 56 | 02f40263 57 | 00001797 58 | 47878793 59 | 0007a783 60 | 00c12083 61 | 0087a023 62 | 00812403 63 | 01010113 64 | 00008067 65 | 00d00513 66 | fadff0ef 67 | 00001797 68 | 45078793 69 | 0007a783 70 | 00c12083 71 | 0087a023 72 | 00812403 73 | 01010113 74 | 00008067 75 | 00054703 76 | 04070263 77 | 00001797 78 | 43078793 79 | 0007a803 80 | 00001797 81 | 41c78793 82 | 0007a583 83 | 00a00613 84 | 00082783 85 | 00150513 86 | 0017f793 87 | 0ff7f693 88 | 00069063 89 | 00c70a63 90 | 00e5a023 91 | 00054703 92 | fe0710e3 93 | 00008067 94 | 0ff7f793 95 | fe0786e3 96 | fe079ee3 97 | fe5ff06f 98 | fa010113 99 | 02812e23 100 | 02912c23 101 | 03212a23 102 | 03312823 103 | 03412623 104 | 03512423 105 | 00054303 106 | 04f12a23 107 | 04410793 108 | 04b12223 109 | 04c12423 110 | 04d12623 111 | 04e12823 112 | 05012c23 113 | 05112e23 114 | 00f12423 115 | 0c030063 116 | 00150513 117 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1358 | 2d2d2d2d 1359 | 2d2d2d2d 1360 | 2d2d2d2d 1361 | 000a2d2d 1362 | 20010010 1363 | 2001000c 1364 | 20010008 1365 | 20010004 1366 | 20010000 1367 | 2000000c 1368 | 20000008 1369 | 20000004 1370 | 20000000 1371 | -------------------------------------------------------------------------------- /CACHE/sources_1/new/Cache_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Cache_controller#( 4 | parameter block_size = 128 5 | ) 6 | ( 7 | input clk_i, 8 | input mem_clk_i, 9 | input rst_i, 10 | input [127:0] L2_data_block_p1_i, 11 | input [18:0] L1_data_addr_i, 12 | input [18:0] L1_instr_addr_i, 13 | input L2_p1_hit_i, 14 | input L2_p2_hit_i, 15 | input L1_data_hit_i, 16 | input L1_instr_hit_i, 17 | input L1_miss_next_i, 18 | input read_instr_i, 19 | input read_data_i, 20 | input write_data_i, 21 | input [2:0] DATA_write_instruction_i, 22 | output reg write_L2_o, 23 | output reg L1_instr_write_o, 24 | output reg L2_read_p1_o, 25 | output reg L2_read_p2_o, 26 | output reg L2_write_p1_o, 27 | output reg L2_write_p2_o, 28 | output reg [15:0] L2_byte_enable_p1_o, 29 | output reg [15:0] L2_byte_enable_p2_o, 30 | output [18:0] L2_p2_addr_o, 31 | output [31:0] ram_data_o, 32 | output [31:0] ram_read_addr_o, 33 | output [31:0] ram_write_addr_o, 34 | output ram_read_o, 35 | output miss_o, 36 | output ram_write_start_o, 37 | output reg write_next_o, 38 | output reg [3:0] wr_strb_o, 39 | output reg read_data_o, 40 | output reg read_instr_o, 41 | output reg write_data_o, 42 | output reg write_through_o, 43 | output reg instr_write_start_o 44 | ); 45 | // State for Instruction Cache Control 46 | reg [3:0] state_instr; 47 | parameter state_instr_idle = 4'd0, // idle state waiting for read instruction input, if there is a read go into state_instr_read 48 | state_instr_read = 4'd1, // read state decides if there is a hit or there is a miss and read L2, if there is a hit go state_data_idle else go state_instr_miss_L2_step0 49 | state_instr_miss_L1_step0 = 4'd2, // read L2 signal will be read on next state, this is delay state, go into state state_instr_miss_L1_step0 50 | state_instr_miss_L1_step1 = 4'd3, // read L2 signal and decides if there is a hit or start main memory transfer, if L1 hit go into state_instr_hit_L2_step0 if not go into state_instr_miss_L2_s 51 | state_instr_hit_L2_step0 = 4'd4, // there is a hit in L2, start writing into L1 instr cache, blockram will write 64 bits at once max step0, go into state_instr_hit_L2_step1 52 | state_instr_hit_L2_step1 = 4'd5, // there is a hit in L2, start writing into L1 instr cache, blockram will write 64 bits at once max step1, if L1 hit go into state_instr_idle 53 | state_instr_miss_L2_step0 = 4'd6, // main memory transfer [31:0],wait for memory done signals if instr is using memory and done signal then go into state_instr_miss_L2_step0 54 | state_instr_miss_L2_step1 = 4'd7, // main memory transfer [63:32], wait for memory done signals if instr is using memory and done signal then go into state_instr_miss_L2_step1 55 | state_instr_miss_L2_step2 = 4'd8, // main memory transfer [95:64], wait for memory done signals if instr is using memory and done signal then go into state_instr_miss_L2_step2 56 | state_instr_miss_L2_step3 = 4'd9, // main memory transfer [127:96], wait for memory done signals if instr is using memory and done signal then go into state_instr_miss_L2_done_step0 57 | state_instr_miss_L2_done_step0 = 4'd10, // main memory transfer is done, start writing into L1 instr cache, blockram will write 64 bits at once max step0, go into state_instr_miss_L2_done_step1 58 | state_instr_miss_L2_done_step1 = 4'd11; // main memory transfer is done, start writing into L1 instr cache, blockram will write 64 bits at once max step1, if hit go into state_instr_idle 59 | reg miss_L1_instr; // indicates that there is a miss in L1_instr (output from FSM) 60 | reg main_mem_transfer_instr; // indicates that main memory will be used for instruction cache 61 | reg transfer_instr_step1; // step 1 for instruction transfer is done 62 | reg transfer_instr_step2; // step 2 for instruction transfer is done 63 | reg transfer_instr_step3; // step 3 for instruction transfer is done 64 | reg ram_write_start_instr_o; // First write signal for L2 cache from instruction, for replacement algorithm 65 | 66 | // State for Data Cache Control & Registers 67 | reg [4:0] state_data; 68 | parameter state_data_idle = 5'd0, // idle state looking for read or write instruction, if read go into state_data_read, if write go into state_data_write_step0 69 | state_data_read = 5'd1, // data read state looking if there is a hit or not if there is a hit go into state_data_idle, if not go into state_data_miss_L1_step0 and look into L2 cache 70 | state_data_miss_L1_step0 = 5'd2, // read L2 signal will be read on next state, this is delay state, go into state state_data_miss_L1_step1 71 | state_data_miss_L1_step1 = 5'd3, // if there is a hit go into state state_data_hit_L2_step0 if there is not go into state_data_miss_L2_step0 72 | state_data_hit_L2_step0 = 5'd4, // there is a hit in L2, start writing into L1 data cache, blockram will write 64 bits at once max step0, go into state_data_hit_L2_step1 73 | state_data_hit_L2_step1 = 5'd5, // there is a hit in L2, start writing into L1 data cache, blockram will write 64 bits at once max step1, if L1 hit go into state_data_idle 74 | state_data_miss_L2_step = 5'd6, // wait before memory transfer in case instruction is trying to read and do not conflict go into state state_data_miss_L2_step0 75 | state_data_miss_L2_step0 = 5'd7, // main memory transfer [31:0],wait for memory done signals if data is using memory and done signal then go into state_data_miss_L2_step0 76 | state_data_miss_L2_step1 = 5'd8, // main memory transfer [63:32], wait for memory done signals if data is using memory and done signal then go into state_data_miss_L2_step1 77 | state_data_miss_L2_step2 = 5'd9, // main memory transfer [95:64], wait for memory done signals if data is using memory and done signal then go into state_data_miss_L2_step2 78 | state_data_miss_L2_step3 = 5'd10,// main memory transfer [127:96], wait for memory done signals if data is using memory and done signal then go into state_data_miss_L2_done_step0 79 | state_data_miss_L2_done_step0 = 5'd11, // main memory transfer is done, start writing into L1 instr cache, blockram will write 64 bits at once max step0, go into state_data_miss_L2_done_step1 80 | state_data_miss_L2_done_step1 = 5'd12, // main memory transfer is done, start writing into L1 instr cache, blockram will write 64 bits at once max step1, if hit go into state_data_idle 81 | state_data_write_step0 = 5'd13, // state to stabilize reading to decide write on which set go into state_data_write_step1 82 | state_data_write_step1 = 5'd14, // state to decide if written address is read before in L1 if it is not after write to main memory is done it will be read back, enable write signals go into state_data_writethrough_step0 83 | state_data_writethrough_step0 = 5'd15, // because blockram is being used 2 states for data transfer go into state_data_writethrough_step1 84 | state_data_writethrough_step1 = 5'd16, // because blockram is being used 2 states for data transfer, data written into L1 data, go into state_data_writethrough_step2 85 | state_data_writethrough_step2 = 5'd17, // write data into L2 cache from L1 data first 64 bit go inot state_data_writethrough_step3 86 | state_data_writethrough_step3 = 5'd18, // write data into L2 cache from L1 data last 64 bit go into state_data_writethrough_step4 87 | state_data_writethrough_step4 = 5'd19, // read data from L2, go into state state_data_writethrough_step5 88 | state_data_writethrough_step5 = 5'd20, // stabilise read data from L2 if it is not done on step4, go into state_data_writethrough_step6 89 | state_data_writethrough_step6 = 5'd21, // start writing data and give output signals to main memory, if instruction is SD go into state_data_writethrough_SD, if not go into state_data_writethrough_done 90 | state_data_writethrough_SD = 5'd22, // if instrution is SD (Store Data Word), because main memory can be written 32 bit once, transfer last 32 bits, wait for transfer done signal and if it is done go into state state_data_writethrough_done 91 | state_data_writethrough_done = 5'd23; // wait for transfer done if it is done and if there were miss in state state_data_write_step1 then go into state_data_miss_L1_step1 if not then go into state_data_idle 92 | parameter SB = 3'b000, // Store byte instruction 93 | SH = 3'b001, // Store half-word instruction 94 | SW = 3'b010, // Store word instruction 95 | SD = 3'b011; // Store double-word instruction 96 | reg miss_L1_data; // indicates that there is a miss in L1_data (output from FSM) 97 | reg main_mem_transfer_data; // indicates that main memory will be used for data cache 98 | reg transfer_data_step1; // step 1 for data transfer is done// 99 | reg transfer_data_step2; // step 2 for data transfer is done 100 | reg transfer_data_step3; // step 3 for data transfer is done 101 | reg ram_write_start_data_o; // First write signal for L2 cache from data, for replacement algorithm 102 | reg write_through_miss; // write through miss occurs when writing into an address that does not exist in L1 data cache 103 | reg start_write_transfer; // start write transfer 104 | reg start_write_transfer2; // start write transfer2 if instruction was SD first 32 bits been transferred now transfer other 32 bits 105 | // State for Main Memory Transfer (While Reading instruction or data) 106 | reg [2:0] state_main_mem; 107 | parameter state_main_mem_idle = 3'd0, // idle waiting for instruction or data transfer 108 | state_main_mem_transfer_0 = 3'd1, // main memory transfer [31:0], wait for done signals from instruction or data cache controller 109 | state_main_mem_transfer_1 = 3'd2, // main memory transfer [63:32], wait for done signals from instruction or data cache controller 110 | state_main_mem_transfer_2 = 3'd3, // main memory transfer [95:64], wait for done signals from instruction or data cache controller 111 | state_main_mem_transfer_3 = 3'd4; // main memory transfer [127:96], wait for done signals from instruction or data cache controller 112 | reg main_mem_done; // memory transfer is done 113 | reg main_mem_done_step0; // memory transfer transfer 0 is done 114 | reg main_mem_done_step1; // memory transfer transfer 1 is done 115 | reg main_mem_done_step2; // memory transfer transfer 2 is done 116 | // State for Main Memory Usage Control (Because only one read port on main memory) 117 | reg [1:0] state_main_mem_usage; 118 | parameter state_main_mem_usage_idle = 2'd0, // wait for instruction or data transfer 119 | state_main_mem_usage_instr = 2'd1, // instruction is being used state 120 | state_main_mem_usage_data = 2'd2; // data is being used state 121 | reg transfer_data; // data transfer is being done by main memory 122 | reg transfer_instr; // instruction transfer is being done by main memory 123 | // State for Main Memory Write Control 124 | reg [1:0] state_main_mem_write; 125 | parameter state_main_mem_write_idle = 2'd0, // waiting for write transfer signal 126 | state_main_mem_write_transfer_SD = 2'd1, // SD is instruction transfer MSB 32 bits 127 | state_main_mem_write_transfer_done = 2'd2; // write transfer is done 128 | reg main_mem_write_step1_done; // if instruction is SD and first 32 bit write is done 129 | reg main_mem_write_done; // write transfer is done 130 | // Registers for L2 131 | reg [18:0] ram_addr_L2_instr; // L2 instr address port 132 | reg [18:0] ram_addr_L2_data; // L2 data address port 133 | reg [18:0] ram_addr_L2_data_write; // ram write address 134 | // 135 | assign ram_data_o = (ram_write_addr_o[3:2] == 2'b11) ? L2_data_block_p1_i[127:96] : 136 | ((ram_write_addr_o[3:2] == 2'b10) ? L2_data_block_p1_i[95:64] : 137 | ((ram_write_addr_o[3:2] == 2'b01) ? L2_data_block_p1_i[63:32] : L2_data_block_p1_i[31:0])); 138 | assign ram_read_o = main_mem_transfer_instr | main_mem_transfer_data; 139 | assign ram_write_addr_o = {13'b0100_0000_0000_0,ram_addr_L2_data_write}; // from specification ram address is being arranged 140 | assign ram_read_addr_o = transfer_instr == 1 ? {13'b0100_0000_0000_0,ram_addr_L2_instr} : {13'b0100_0000_0000_0,ram_addr_L2_data}; // decide on which address will be used for ram 141 | assign miss_o = miss_L1_instr | miss_L1_data | (~L1_data_hit_i & (read_data_i | read_data_o)) | (~L1_instr_hit_i & (read_instr_i | read_instr_o)); // miss output 142 | assign L2_p2_addr_o = ((L1_instr_hit_i & L1_miss_next_i)) == 1'b1 ? (L1_instr_addr_i + 2'b10) : L1_instr_addr_i; // L2 address being decided if there is a miss next it will be next idx address 143 | assign ram_write_start_o = ram_write_start_instr_o | ram_write_start_data_o; 144 | // 145 | 146 | 147 | always @(posedge clk_i) begin // main memoryden okuma sirasini belirlemek icin yapilan state machine 148 | if(rst_i) begin 149 | transfer_instr <= 1'b0; 150 | transfer_data <= 1'b0; 151 | state_main_mem_usage <= state_main_mem_usage_idle; 152 | end 153 | else begin 154 | case(state_main_mem_usage) 155 | state_main_mem_usage_idle: begin 156 | if(main_mem_transfer_instr) begin 157 | transfer_instr <= 1'b1; 158 | transfer_data <= 1'b0; 159 | state_main_mem_usage <= state_main_mem_usage_instr; 160 | end 161 | else if(main_mem_transfer_data) begin 162 | transfer_data <= 1'b1; 163 | transfer_instr <= 1'b0; 164 | state_main_mem_usage <= state_main_mem_usage_data; 165 | end 166 | end 167 | 168 | state_main_mem_usage_instr: begin 169 | if(main_mem_transfer_instr) begin 170 | transfer_instr <= 1'b1; 171 | transfer_data <= 1'b0; 172 | state_main_mem_usage <= state_main_mem_usage_instr; 173 | end 174 | else begin 175 | transfer_data <= 1'b0; 176 | transfer_instr <= 1'b0; 177 | state_main_mem_usage <= state_main_mem_usage_idle; 178 | end 179 | end 180 | 181 | state_main_mem_usage_data: begin 182 | if(main_mem_transfer_data) begin 183 | transfer_data <= 1'b1; 184 | transfer_instr <= 1'b0; 185 | state_main_mem_usage <= state_main_mem_usage_data; 186 | end 187 | else begin 188 | transfer_data <= 1'b0; 189 | transfer_instr <= 1'b0; 190 | state_main_mem_usage <= state_main_mem_usage_idle; 191 | end 192 | end 193 | default: state_main_mem_usage <= state_main_mem_usage_idle; 194 | endcase 195 | end 196 | end 197 | 198 | always @(posedge clk_i) begin // instruction cache control 199 | if(rst_i) begin 200 | read_instr_o <= 1'b0; 201 | L2_read_p2_o <= 1'b0; 202 | miss_L1_instr <= 1'b0; 203 | write_next_o <= 1'b0; 204 | L1_instr_write_o <= 1'b0; 205 | transfer_instr_step1 <= 1'b0; 206 | transfer_instr_step2 <= 1'b0; 207 | transfer_instr_step3 <= 1'b0; 208 | ram_write_start_instr_o <= 1'b0; 209 | main_mem_transfer_instr <= 1'b0; 210 | L2_write_p2_o <= 1'b0; 211 | state_instr <= state_instr_idle; 212 | end 213 | else begin 214 | case(state_instr) 215 | state_instr_idle: begin // idle state read var mi diye bakiyor surekli 216 | if(read_instr_i) begin // read_instr_reg_o 217 | read_instr_o <= 1'b1; 218 | state_instr <= state_instr_read; 219 | end 220 | else begin 221 | read_instr_o <= 1'b0; 222 | L2_read_p2_o <= 1'b0; 223 | miss_L1_instr <= 1'b0; 224 | write_next_o <= 1'b0; 225 | L1_instr_write_o <= 1'b0; 226 | main_mem_transfer_instr <= 1'b0; 227 | L2_write_p2_o <= 1'b0; 228 | ram_write_start_instr_o <= 1'b0; 229 | state_instr <= state_instr_idle; 230 | end 231 | end 232 | 233 | 234 | state_instr_read: begin // read varsa buraya geliyor. 235 | if(L1_instr_hit_i & ~L1_miss_next_i) begin // basarili sekilde okundu 236 | miss_L1_instr <= 1'b0; 237 | state_instr <= state_instr_idle; 238 | read_instr_o <= 1'b0; 239 | end 240 | else begin // L1_instr cache'de miss 241 | if(L1_instr_hit_i & L1_miss_next_i) begin // Eger ki miss_next ise write_next_o'yu 1'e cek sonraki adrese yazilsin. (L1_instr_hit_i eklendi cunku bir turlu jump 242 | // ile o kosul olusturulursa hata olucak normal adresste miss olmasina ragmen yine sonraki adrese yazilacak.) 243 | write_next_o <= 1'b1; 244 | end 245 | read_instr_o <= 1'b1; 246 | miss_L1_instr <= 1'b1; 247 | L2_read_p2_o <= 1'b1; 248 | state_instr <= state_instr_miss_L1_step0; 249 | end 250 | end 251 | 252 | state_instr_miss_L1_step0: begin // 1 clock cycle gecikme ile datayi daha stabil hale getirmek icin 253 | state_instr <= state_instr_miss_L1_step1; 254 | end 255 | 256 | state_instr_miss_L1_step1: begin // L1_instr cache'de miss olmus. 257 | if(L2_p2_hit_i) begin // data L2'de var. L2'den L1'e yazma yapilacak. 258 | L1_instr_write_o <= 1'b1; 259 | instr_write_start_o <= 1'b1; 260 | state_instr <= state_instr_hit_L2_step0; 261 | end 262 | else if(~transfer_data) begin // L2'de de miss, Eger ki Data cache'de de onceden miss varsa ve main memory'yi kullaniyorsa girme bekle. 263 | main_mem_transfer_instr <= 1'b1; // instruction'dan main memory'ye transfer yapilacagini belirtir. 264 | L2_write_p2_o <= 1'b1; // L2'nin 2.portunun yazma sinyalini ac. 265 | L2_byte_enable_p2_o <= 16'h000F; 266 | ram_write_start_instr_o <= 1'b1; 267 | ram_addr_L2_instr <= L2_p2_addr_o & 19'b111_1111_1111_1111_0000; 268 | state_instr <= state_instr_miss_L2_step0; 269 | end 270 | end 271 | 272 | state_instr_hit_L2_step0: begin 273 | instr_write_start_o <= 1'b0; 274 | state_instr <= state_instr_hit_L2_step1; 275 | end 276 | 277 | state_instr_hit_L2_step1: begin 278 | L1_instr_write_o <= 1'b0; 279 | instr_write_start_o <= 1'b0; 280 | if(L1_instr_hit_i) begin 281 | miss_L1_instr <= 1'b0; 282 | write_next_o <= 1'b0; 283 | read_instr_o <= 1'b0; 284 | state_instr <= state_instr_idle; 285 | end 286 | end 287 | 288 | state_instr_miss_L2_step0: begin 289 | ram_write_start_instr_o <= 1'b0; 290 | if(main_mem_done_step0 & transfer_instr) begin 291 | ram_addr_L2_instr <= ram_addr_L2_instr + 3'b100; 292 | L2_byte_enable_p2_o <= 16'h00F0; 293 | transfer_instr_step1 <= 1'b1; 294 | state_instr <= state_instr_miss_L2_step1; 295 | end 296 | end 297 | 298 | state_instr_miss_L2_step1: begin 299 | if(main_mem_done_step1 & transfer_instr) begin 300 | ram_addr_L2_instr <= ram_addr_L2_instr + 3'b100; 301 | L2_byte_enable_p2_o <= 16'h0F00; 302 | transfer_instr_step1 <= 1'b0; 303 | transfer_instr_step2 <= 1'b1; 304 | state_instr <= state_instr_miss_L2_step2; 305 | end 306 | end 307 | 308 | state_instr_miss_L2_step2: begin 309 | if(main_mem_done_step2 & transfer_instr) begin 310 | ram_addr_L2_instr <= ram_addr_L2_instr + 3'b100; 311 | L2_byte_enable_p2_o <= 16'hF000; 312 | transfer_instr_step2 <= 1'b0; 313 | transfer_instr_step3 <= 1'b1; 314 | state_instr <= state_instr_miss_L2_step3; 315 | end 316 | end 317 | 318 | state_instr_miss_L2_step3: begin 319 | if(main_mem_done & transfer_instr) begin 320 | ram_addr_L2_instr <= L1_instr_addr_i; 321 | L2_write_p2_o <= 1'b0; 322 | main_mem_transfer_instr <= 1'b0; 323 | transfer_instr_step3 <= 1'b0; 324 | L2_byte_enable_p2_o <= 16'h0000; 325 | L1_instr_write_o <= 1'b1; 326 | instr_write_start_o <= 1'b1; 327 | 328 | state_instr <= state_instr_miss_L2_done_step0; 329 | end 330 | end 331 | 332 | state_instr_miss_L2_done_step0: begin 333 | instr_write_start_o <= 1'b0; 334 | state_instr <= state_instr_miss_L2_done_step1; 335 | end 336 | 337 | state_instr_miss_L2_done_step1: begin 338 | L1_instr_write_o <= 1'b0; 339 | instr_write_start_o <= 1'b0; 340 | if(L1_instr_hit_i & ~L1_miss_next_i) begin 341 | miss_L1_instr <= 1'b0; 342 | read_instr_o <= 1'b0; 343 | write_next_o <= 1'b0; 344 | state_instr <= state_instr_idle; 345 | end 346 | end 347 | 348 | default: state_instr <= state_instr_idle; 349 | endcase 350 | end 351 | end 352 | 353 | always @(posedge mem_clk_i) begin // main memory okuma yaparken senkronizasyon amacli state machine 354 | if(rst_i) begin 355 | state_main_mem <= state_main_mem_idle; 356 | main_mem_done <= 1'b0; 357 | main_mem_done_step0 <= 1'b0; 358 | main_mem_done_step1 <= 1'b0; 359 | main_mem_done_step2 <= 1'b0; 360 | end 361 | else begin 362 | case(state_main_mem) 363 | state_main_mem_idle: begin 364 | main_mem_done <= 1'b0; 365 | main_mem_done_step0 <= 1'b0; 366 | main_mem_done_step1 <= 1'b0; 367 | main_mem_done_step2 <= 1'b0; 368 | if(main_mem_transfer_instr | main_mem_transfer_data) begin 369 | state_main_mem <= state_main_mem_transfer_0; 370 | end 371 | end 372 | 373 | state_main_mem_transfer_0: begin 374 | main_mem_done_step0 <= 1'b1; 375 | if(transfer_data_step1 | transfer_instr_step1) begin 376 | state_main_mem <= state_main_mem_transfer_1; 377 | end 378 | end 379 | 380 | state_main_mem_transfer_1: begin 381 | main_mem_done_step0 <= 1'b0; 382 | main_mem_done_step1 <= 1'b1; 383 | if(transfer_data_step2 | transfer_instr_step2) begin 384 | state_main_mem <= state_main_mem_transfer_2; 385 | end 386 | end 387 | 388 | state_main_mem_transfer_2: begin 389 | main_mem_done_step1 <= 1'b0; 390 | main_mem_done_step2 <= 1'b1; 391 | if(transfer_data_step3 | transfer_instr_step3) begin 392 | state_main_mem <= state_main_mem_transfer_3; 393 | end 394 | 395 | end 396 | 397 | state_main_mem_transfer_3: begin 398 | if(main_mem_done) begin 399 | state_main_mem <= state_main_mem_idle; 400 | end 401 | main_mem_done_step2 <= 1'b0; 402 | main_mem_done <= 1'b1; 403 | //state_main_mem <= state_main_mem_idle; 404 | end 405 | 406 | default: state_main_mem <= state_main_mem_idle; 407 | endcase 408 | end 409 | end 410 | 411 | always @(posedge mem_clk_i) begin // main memory yazma yaparken senkronizasyon amacli state machine 412 | if(rst_i) begin 413 | state_main_mem_write <= state_main_mem_write_idle; 414 | main_mem_write_done <= 1'b0; 415 | end 416 | else begin 417 | case(state_main_mem_write) 418 | state_main_mem_write_idle: begin 419 | main_mem_write_done <= 1'b0; 420 | if(start_write_transfer) begin 421 | if(DATA_write_instruction_i == SD) begin 422 | state_main_mem_write <= state_main_mem_write_transfer_SD; 423 | end 424 | else begin 425 | state_main_mem_write <= state_main_mem_write_transfer_done; 426 | end 427 | end 428 | end 429 | state_main_mem_write_transfer_SD: begin 430 | main_mem_write_step1_done <= 1'b1; 431 | if(start_write_transfer2) begin 432 | state_main_mem_write <= state_main_mem_write_transfer_done; 433 | end 434 | end 435 | state_main_mem_write_transfer_done: begin 436 | state_main_mem_write <= state_main_mem_write_idle; 437 | main_mem_write_step1_done <= 1'b0; 438 | main_mem_write_done <= 1'b1; 439 | end 440 | default: state_main_mem_write <= state_main_mem_write_idle; 441 | endcase 442 | end 443 | end 444 | 445 | always @(posedge clk_i) begin // data cache control 446 | if(rst_i) begin 447 | write_through_miss <= 1'b0; 448 | read_data_o <= 1'b0; 449 | L2_read_p1_o <= 1'b0; 450 | miss_L1_data <= 1'b0; 451 | write_L2_o <= 1'b0; 452 | write_through_o <= 1'b0; 453 | L2_byte_enable_p1_o <= 16'b0; 454 | main_mem_transfer_data <= 1'b0; 455 | L2_write_p1_o <= 1'b0; 456 | wr_strb_o <= 4'b0; 457 | start_write_transfer <= 1'b0; 458 | start_write_transfer2 <= 1'b0; 459 | transfer_data_step1 <= 1'b0; 460 | transfer_data_step2 <= 1'b0; 461 | transfer_data_step3 <= 1'b0; 462 | ram_write_start_data_o <= 1'b0; 463 | state_data <= state_data_idle; 464 | end 465 | else begin 466 | case(state_data) 467 | state_data_idle: begin 468 | if(read_data_i) begin // read_data_reg_o 469 | //miss_L1_data <= 1'b1; 470 | read_data_o <= 1'b1; 471 | state_data <= state_data_read; // eger cpu yavas olcaksa direk state_data_read'e gitmeli 472 | end 473 | else if(write_data_i) begin 474 | read_data_o <= 1'b1; 475 | state_data <= state_data_write_step0; 476 | end 477 | else begin 478 | write_through_miss <= 1'b0; 479 | read_data_o <= 1'b0; 480 | L2_read_p1_o <= 1'b0; 481 | miss_L1_data <= 1'b0; 482 | write_L2_o <= 1'b0; 483 | write_through_o <= 1'b0; 484 | L2_byte_enable_p1_o <= 16'b0; 485 | main_mem_transfer_data <= 1'b0; 486 | L2_write_p1_o <= 1'b0; 487 | wr_strb_o <= 4'b0; 488 | start_write_transfer <= 1'b0; 489 | start_write_transfer2 <= 1'b0; 490 | transfer_data_step1 <= 1'b0; 491 | transfer_data_step2 <= 1'b0; 492 | transfer_data_step3 <= 1'b0; 493 | ram_write_start_data_o <= 1'b0; 494 | state_data <= state_data_idle; 495 | end 496 | end 497 | 498 | 499 | state_data_read: begin 500 | if(L1_data_hit_i) begin 501 | miss_L1_data <= 1'b0; 502 | read_data_o <= 1'b0; 503 | state_data <= state_data_idle; 504 | end 505 | else begin 506 | L2_read_p1_o <= 1'b1; 507 | read_data_o <= 1'b1; 508 | miss_L1_data <= 1'b1; 509 | state_data <= state_data_miss_L1_step0; 510 | end 511 | end 512 | 513 | state_data_miss_L1_step0: begin 514 | state_data <= state_data_miss_L1_step1; 515 | end 516 | 517 | state_data_miss_L1_step1: begin 518 | if(L2_p1_hit_i & ~write_through_miss) begin // ~write_through miss, yazma yapilmis ve daha once o adres cache'lerde bulunmuyorsa yapilacak bir sey. 519 | write_L2_o <= 1'b1; 520 | state_data <= state_data_hit_L2_step0; 521 | end 522 | else if(~transfer_instr & ~((state_instr == state_instr_miss_L1_step1) & ~L2_p2_hit_i))begin // L2'de de miss var. L1 instr cache main memory'yi kullanmiyorsa ve su anda kullanmiyacaksa buraya gir. 523 | 524 | L2_write_p1_o <= 1'b1; 525 | L2_byte_enable_p1_o <= 16'h000F; 526 | ram_write_start_data_o <= 1'b1; 527 | ram_addr_L2_data <= L1_data_addr_i & 19'b111_1111_1111_1111_0000; // 528 | state_data <= state_data_miss_L2_step; 529 | end 530 | end 531 | 532 | state_data_hit_L2_step0: begin 533 | state_data <= state_data_hit_L2_step1; 534 | end 535 | 536 | state_data_hit_L2_step1: begin 537 | if(L1_data_hit_i) begin 538 | write_L2_o <= 1'b0; 539 | miss_L1_data <= 1'b0; 540 | read_data_o <= 1'b0; 541 | state_data <= state_data_idle; 542 | end 543 | end 544 | state_data_miss_L2_step: begin 545 | ram_write_start_data_o <= 1'b0; 546 | if(~transfer_instr & ~((state_instr == state_instr_miss_L1_step1) & ~L2_p2_hit_i)) begin 547 | main_mem_transfer_data <= 1'b1; 548 | state_data <= state_data_miss_L2_step0; 549 | end 550 | 551 | end 552 | state_data_miss_L2_step0: begin 553 | ram_write_start_data_o <= 1'b0; 554 | if(main_mem_done_step0 & transfer_data) begin 555 | ram_addr_L2_data <= ram_addr_L2_data + 3'b100; 556 | L2_byte_enable_p1_o <= 16'h00F0; 557 | transfer_data_step1 <= 1'b1; 558 | state_data <= state_data_miss_L2_step1; 559 | end 560 | end 561 | 562 | state_data_miss_L2_step1: begin 563 | if(main_mem_done_step1 & transfer_data) begin 564 | ram_addr_L2_data <= ram_addr_L2_data + 3'b100; 565 | L2_byte_enable_p1_o <= 16'h0F00; 566 | transfer_data_step2 <= 1'b1; 567 | transfer_data_step1 <= 1'b0; 568 | state_data <= state_data_miss_L2_step2; 569 | end 570 | end 571 | 572 | state_data_miss_L2_step2: begin 573 | if(main_mem_done_step2 & transfer_data) begin 574 | ram_addr_L2_data <= ram_addr_L2_data + 3'b100; 575 | L2_byte_enable_p1_o <= 16'hF000; 576 | transfer_data_step3 <= 1'b1; 577 | transfer_data_step2 <= 1'b0; 578 | state_data <= state_data_miss_L2_step3; 579 | end 580 | end 581 | 582 | state_data_miss_L2_step3: begin 583 | if(main_mem_done & transfer_data) begin 584 | ram_addr_L2_data <= L1_data_addr_i & 19'b111_1111_1111_1111_0000; 585 | transfer_data_step3 <= 1'b0; 586 | main_mem_transfer_data <= 1'b0; 587 | L2_byte_enable_p1_o <= 16'b0; 588 | L2_write_p1_o <= 1'b0; 589 | write_L2_o <= 1'b1; 590 | state_data <= state_data_miss_L2_done_step0; 591 | end 592 | end 593 | 594 | state_data_miss_L2_done_step0: begin 595 | state_data <= state_data_miss_L2_done_step1; 596 | end 597 | 598 | state_data_miss_L2_done_step1: begin 599 | write_L2_o <= 1'b0; 600 | if(L1_data_hit_i) begin 601 | miss_L1_data <= 1'b0; 602 | read_data_o <= 1'b0; 603 | write_through_o <= 1'b0; 604 | write_through_miss <= 1'b0; 605 | state_data <= state_data_idle; 606 | end 607 | end 608 | 609 | state_data_write_step0: begin // read'i stable hale getirmek icin olan state 610 | state_data <= state_data_write_step1; 611 | end 612 | 613 | state_data_write_step1: begin 614 | if(~L1_data_hit_i) begin 615 | write_through_miss <= 1'b1; 616 | miss_L1_data <= 1'b1; 617 | end 618 | write_through_o <= 1'b1; 619 | write_data_o <= 1'b1; 620 | state_data <= state_data_writethrough_step0; 621 | end 622 | 623 | state_data_writethrough_step0: begin 624 | state_data <= state_data_writethrough_step1; 625 | end 626 | 627 | state_data_writethrough_step1: begin 628 | state_data <= state_data_writethrough_step2; 629 | end 630 | 631 | state_data_writethrough_step2: begin 632 | L2_write_p1_o <= 1'b1; 633 | ram_write_start_data_o <= 1'b1; 634 | L2_byte_enable_p1_o <= 16'hFFFF; 635 | state_data <= state_data_writethrough_step3; 636 | end 637 | 638 | state_data_writethrough_step3: begin 639 | ram_write_start_data_o <= 1'b0; 640 | state_data <= state_data_writethrough_step4; 641 | end 642 | 643 | state_data_writethrough_step4: begin 644 | ram_write_start_data_o <= 1'b0; 645 | L2_write_p1_o <= 1'b0; 646 | L2_byte_enable_p1_o <= 16'h0000; 647 | L2_read_p1_o <= 1'b1; 648 | state_data <= state_data_writethrough_step5; 649 | end 650 | 651 | state_data_writethrough_step5: begin 652 | state_data <= state_data_writethrough_step6; 653 | end 654 | 655 | state_data_writethrough_step6: begin // L2'den okuma yapildi. 656 | start_write_transfer <= 1'b1; 657 | ram_addr_L2_data_write <= L1_data_addr_i; 658 | if(DATA_write_instruction_i == SD) begin 659 | wr_strb_o <= 4'b1111; 660 | state_data <= state_data_writethrough_SD; 661 | end 662 | else if(DATA_write_instruction_i == SW) begin 663 | wr_strb_o <= 4'b1111; 664 | state_data <= state_data_writethrough_done; 665 | end 666 | else if(DATA_write_instruction_i == SH) begin 667 | if(L1_data_addr_i[1:0] == 2'b00) begin 668 | wr_strb_o <= 4'b0011; 669 | end 670 | else if(L1_data_addr_i[1:0] == 2'b01) begin 671 | wr_strb_o <= 4'b0110; 672 | end 673 | else if(L1_data_addr_i[1:0] == 2'b10) begin 674 | wr_strb_o <= 4'b1100; 675 | end 676 | //else if(L1_data_addr_i[1:0] == 2'b11) begin 677 | // wr_strb_o <= 4'b1000; 678 | //end 679 | 680 | state_data <= state_data_writethrough_done; 681 | end 682 | else if(DATA_write_instruction_i == SB) begin 683 | if(L1_data_addr_i[1:0] == 2'b00) begin 684 | wr_strb_o <= 4'b0001; 685 | end 686 | else if(L1_data_addr_i[1:0] == 2'b01) begin 687 | wr_strb_o <= 4'b0010; 688 | end 689 | else if(L1_data_addr_i[1:0] == 2'b10) begin 690 | wr_strb_o <= 4'b0100; 691 | end 692 | else if(L1_data_addr_i[1:0] == 2'b11) begin 693 | wr_strb_o <= 4'b1000; 694 | end 695 | state_data <= state_data_writethrough_done; 696 | end 697 | end 698 | 699 | state_data_writethrough_SD: begin // 1 kere daha transfer yapilacagi icin SD yapilirken 700 | if(main_mem_write_step1_done) begin 701 | start_write_transfer <= 1'b0; 702 | ram_addr_L2_data_write <= ram_addr_L2_data_write + 3'b100; 703 | start_write_transfer2 <= 1'b1; 704 | state_data <= state_data_writethrough_done; 705 | end 706 | end 707 | 708 | state_data_writethrough_done: begin 709 | if(main_mem_write_done) begin 710 | wr_strb_o <= 4'b0; 711 | ram_addr_L2_data_write <= L1_data_addr_i; 712 | start_write_transfer <= 1'b0; 713 | start_write_transfer2 <= 1'b0; 714 | write_data_o <= 1'b0; 715 | if(write_through_miss) begin 716 | state_data <= state_data_miss_L1_step1; 717 | end 718 | else begin 719 | L2_read_p1_o <= 1'b0; 720 | read_data_o <= 1'b0; 721 | write_through_o <= 1'b0; 722 | state_data <= state_data_idle; 723 | end 724 | end 725 | end 726 | 727 | default: state_data <= state_data_idle; 728 | endcase 729 | end 730 | end 731 | 732 | endmodule 733 | --------------------------------------------------------------------------------