├── bindings ├── vb6 │ ├── Form1.frx │ ├── CX86Operand.cls │ ├── screenshot.png │ └── Project1.vbw ├── java │ ├── capstone │ │ └── .gitignore │ └── .gitignore ├── python │ ├── prebuilt │ │ └── .gitkeep │ ├── pyproject.toml │ ├── .gitignore │ ├── capstone │ │ ├── arm64.py │ │ └── evm.py │ ├── cstest_py │ │ ├── README.md │ │ └── pyproject.toml │ └── MANIFEST.in └── powershell │ └── Capstone │ └── Lib │ └── Capstone │ └── .gitignore ├── packages ├── rpm │ └── postinstall.sh ├── deb │ └── triggers └── freebsd │ └── ports │ └── devel │ └── capstone │ └── pkg-plist ├── suite ├── cstest │ ├── test │ │ ├── empty_test_file.yaml │ │ ├── README.md │ │ ├── missing_madatory_field.yaml │ │ └── invalid_test_file.yaml │ └── README.md ├── auto-sync │ ├── src │ │ └── autosync │ │ │ ├── cpptranslator │ │ │ ├── patches │ │ │ │ └── __init__.py │ │ │ └── Tests │ │ │ │ ├── Differ │ │ │ │ ├── output │ │ │ │ │ └── README.md │ │ │ │ └── old_src │ │ │ │ │ └── diff_test_file_patching_new.c │ │ │ │ └── Patches │ │ │ │ └── template_src.c │ │ │ ├── Tests │ │ │ ├── MCUpdaterTests │ │ │ │ ├── cps.s │ │ │ │ ├── cps.s.cs │ │ │ │ ├── expected │ │ │ │ │ ├── fuzz │ │ │ │ │ │ └── test_b.txt.cs │ │ │ │ │ ├── merged │ │ │ │ │ │ └── unified │ │ │ │ │ │ │ └── test_b.txt.yaml │ │ │ │ │ └── multi │ │ │ │ │ │ └── unified │ │ │ │ │ │ └── test_b_arm64.txt.yaml │ │ │ │ └── Disassembler │ │ │ │ │ └── ARCH │ │ │ │ │ └── test_b.txt │ │ │ ├── test_include.inc │ │ │ └── test_header.h │ │ │ └── lit_config │ │ │ └── README.md │ ├── format_py.sh │ └── vendor │ │ └── README.md ├── fuzz │ ├── fuzz_disasm.options │ └── README ├── MC │ ├── Mips │ │ ├── mips-jump-instructions.s.cs │ │ ├── hilo-addressing.s.cs │ │ ├── set-at-directive.s.cs │ │ ├── micromips-jump-instructions-EB.s.cs │ │ ├── micromips-multiply-instructions.s.cs │ │ ├── mips64-instructions.s.cs │ │ ├── micromips-jump-instructions.s.cs │ │ ├── micromips-loadstore-unaligned.s.cs │ │ ├── micromips-movcond-instructions.s.cs │ │ ├── micromips-multiply-instructions-EB.s.cs │ │ ├── micromips-loadstore-unaligned-EB.s.cs │ │ ├── micromips-movcond-instructions-EB.s.cs │ │ ├── test_elm_insert.s.cs │ │ ├── micromips-loadstore-instructions.s.cs │ │ ├── micromips-shift-instructions.s.cs │ │ ├── micromips-loadstore-instructions-EB.s.cs │ │ ├── test_i10.s.cs │ │ ├── test_elm_insve.s.cs │ │ ├── micromips-shift-instructions-EB.s.cs │ │ └── test_lsa.s.cs │ ├── X86 │ │ ├── x86_64-sse4a.s.cs │ │ ├── x86_64-rtm-encoding.s.cs │ │ └── address-size.s.cs │ ├── Sparc │ │ ├── sparcv9-instructions.s.cs │ │ ├── sparc-vis.s.cs │ │ ├── sparcv8-instructions.s.cs │ │ ├── sparc-atomic-instructions.s.cs │ │ └── sparc-ctrl-instructions.s.cs │ ├── ARM │ │ ├── cde-integer.s.cs │ │ ├── udf-thumb.s.cs │ │ ├── armv8.5a-sb.s.cs │ │ ├── basic-thumb2-instructions-v8.s.cs │ │ ├── udf-arm.s.cs │ │ ├── thumb2-bxj.s.cs │ │ ├── arm-it-block.s.cs │ │ ├── thumb2-pldw.s.cs │ │ ├── bfloat16-a32.s.cs │ │ ├── thumb2-b.w-encodingT4.s.cs │ │ ├── thumb2-bxj-v8.s.cs │ │ ├── udf-thumb-2.s.cs │ │ ├── arm-thumb-trustzone.s.cs │ │ ├── arm-trustzone.s.cs │ │ ├── dot-req.s.cs │ │ ├── cde-vec-pred.s.cs │ │ ├── idiv.s.cs │ │ ├── neon-vswp.s.cs │ │ ├── idiv-thumb.s.cs │ │ ├── cps.s.cs │ │ ├── thumb2-ldrexd-strexd.s.cs │ │ ├── bfloat16-t32.s.cs │ │ ├── mve-vmov-pair.s.cs │ │ ├── arm-branches.s.cs │ │ ├── vmovhr.s.cs │ │ ├── armv8.1m-pacbti.s.cs │ │ ├── gas-compl-copr-reg.s.cs │ │ ├── mve-vpt.s.cs │ │ ├── arm-aliases.s.cs │ │ ├── thumb-mov.s.cs │ │ ├── crc32.s.cs │ │ ├── crc32-thumb.s.cs │ │ ├── thumbv7m.s.cs │ │ ├── thumb-hints.s.cs │ │ ├── ldrd-strd-gnu-arm.s.cs │ │ ├── basic-arm-instructions-v8.s.cs │ │ ├── clrm-asm.s.cs │ │ ├── implicit-it-generation.s.cs │ │ ├── arm_addrmode3.s.cs │ │ ├── thumbv7em.s.cs │ │ ├── armv8.2a-dotprod-a32.s.cs │ │ ├── armv8.2a-dotprod-t32.s.cs │ │ ├── armv8a-fpmul.s.cs │ │ ├── mve-reductions-fp.s.cs │ │ └── fconst.s.cs │ ├── AArch64 │ │ ├── arm64e.s.cs │ │ ├── armv8.4a-flagm.s.cs │ │ ├── armv8.5a-sb.s.cs │ │ ├── armv8.9a-clrbhb.txt.cs │ │ ├── armv8r-inst.s.cs │ │ ├── armv8.3a-pauth.s.cs │ │ ├── armv8.3a-js.s.cs │ │ ├── armv8.3a-js.txt.cs │ │ ├── armv8.9a-specres2.txt.cs │ │ ├── armv8.9a-rasv2.s.cs │ │ ├── a64-ignored-fields.txt.cs │ │ ├── armv8.2a-persistent-memory.s.cs │ │ ├── armv8.2a-mmfr2.txt.cs │ │ ├── armv8.2a-persistent-memory.txt.cs │ │ ├── armv8.3a-ID_ISAR6_EL1.s.cs │ │ ├── armv8.5a-persistent-memory.s.cs │ │ ├── armv8.5a-persistent-memory.txt.cs │ │ ├── arm64-target-specific-sysreg.s.cs │ │ ├── armv8.5a-altnzcv.s.cs │ │ ├── armv8.7a-wfxt.s.cs │ │ ├── armv8.5a-rand.txt.cs │ │ ├── armv8.7a-wfxt.txt.cs │ │ ├── armv8.2a-at.txt.cs │ │ ├── armv8.5a-rand.s.cs │ │ ├── armv8.4a-vncr.txt.cs │ │ ├── armv8.7a-hcx.s.cs │ │ ├── armv8.9a-specres2.s.cs │ │ ├── armv8.2a-at.s.cs │ │ ├── armv8.4a-vncr.s.cs │ │ ├── armv8.7a-hcx.txt.cs │ │ ├── neon-scalar-add-sub.s.cs │ │ ├── udf.txt.cs │ │ ├── armv8.9a-rasv2.txt.cs │ │ ├── neon-scalar-shift.s.cs │ │ ├── spe.s.cs │ │ ├── ldr.s.cs │ │ ├── speculation-barriers.txt.cs │ │ ├── str.s.cs │ │ ├── udf.s.cs │ │ ├── neon-scalar-rounding-shift.s.cs │ │ ├── speculation-barriers.s.cs │ │ ├── armv8.4a-dit.txt.cs │ │ ├── armv8.4a-dit.s.cs │ │ ├── armv8.5a-predres.s.cs │ │ ├── armv8.9a-clrbhb.s.cs │ │ ├── neon-extract.s.cs │ │ ├── armv9.4a-ebep.s.cs │ │ ├── tme.s.cs │ │ ├── arm64-vector-lists.s.cs │ │ ├── armv8.4a-flag.txt.cs │ │ ├── armv8.5a-ssbs.s.cs │ │ ├── bfcvt.s.cs │ │ ├── fcvtl.s.cs │ │ ├── bfcvtn.s.cs │ │ ├── armv8.1a-pan.s.cs │ │ ├── armv9.4a-ebep.txt.cs │ │ ├── st1q.s.cs │ │ ├── arm64-adr.s.cs │ │ ├── armv8r-unsupported-inst.s.cs │ │ ├── armv9.5a-spmu2.s.cs │ │ ├── case-insen-reg-names.s.cs │ │ ├── ld1q.s.cs │ │ ├── armv8.2a-uao.s.cs │ │ ├── armv8.3a-rcpc.txt.cs │ │ ├── armv9.5a-spmu2.txt.cs │ │ ├── tme.txt.cs │ │ ├── ldp-offset-predictable.txt.cs │ │ ├── arm64-invalid-logical.txt.cs │ │ ├── mopa.s.cs │ │ ├── arm64-nv-cond.s.cs │ │ ├── extq.s.cs │ │ ├── neon-scalar-reduce-pairwise.s.cs │ │ ├── armv8.2a-uao.txt.cs │ │ ├── armv8.3a-ID_ISAR6_EL1.txt.cs │ │ ├── lut.s.cs │ │ ├── neon-scalar-neg.s.cs │ │ ├── armv9.5a-fgwte3.s.cs │ │ ├── armv9.5a-fgwte3.txt.cs │ │ ├── armv9.4a-chk.txt.cs │ │ ├── armv9.5a-step2.s.cs │ │ ├── armv9.5a-step2.txt.cs │ │ ├── armv8.8a-nmi.s.cs │ │ ├── armv8.9a-ats1a.s.cs │ │ ├── armv8.9a-ats1a.txt.cs │ │ ├── colored.txt.cs │ │ ├── arm64-spsel-sysreg.s.cs │ │ ├── armv8.3a-rcpc.s.cs │ │ ├── armv9.4a-chk.s.cs │ │ ├── armv8.5a-bti.s.cs │ │ ├── armv8.8a-nmi.txt.cs │ │ ├── armv8.4a-flag.s.cs │ │ ├── armv8r-unsupported-sysreg.s.cs │ │ ├── ldp-postind.predictable.txt.cs │ │ ├── armv8.4a-trace.txt.cs │ │ ├── armv8.5a-ssbs.txt.cs │ │ ├── armv9.5a-e3dse.s.cs │ │ ├── ldp-preind.predictable.txt.cs │ │ ├── neon-sxtl.s.cs │ │ ├── neon-uxtl.s.cs │ │ ├── armv9.5a-e3dse.txt.cs │ │ ├── armv9a-rme.txt.cs │ │ ├── movt.s.cs │ │ ├── arm64-compact-unwind-fallback.s.cs │ │ ├── arm64-leaf-compact-unwind.s.cs │ │ ├── armv9.5a-hdbss.s.cs │ │ ├── armv9.5a-hdbss.txt.cs │ │ ├── armv8.4a-trace.s.cs │ │ ├── armv9.5a-hacdbs.s.cs │ │ ├── armv9.5a-hacdbs.txt.cs │ │ ├── arm64-optional-hash.s.cs │ │ ├── armv8.1a-pan.txt.cs │ │ ├── basic-a64-unpredictable.txt.cs │ │ ├── armv8.9a-prfm-slc.s.cs │ │ ├── neon-scalar-abs.s.cs │ │ ├── armv8.9a-pfar.s.cs │ │ ├── armv8.9a-pfar.txt.cs │ │ ├── st2q.s.cs │ │ ├── ld2q.s.cs │ │ ├── bfmlslb.s.cs │ │ ├── bfmlslt.s.cs │ │ ├── fcvtzs.s.cs │ │ ├── fcvtzu.s.cs │ │ ├── neon-scalar-saturating-shift.s.cs │ │ ├── scvtf.s.cs │ │ ├── ucvtf.s.cs │ │ ├── ld1w_q.s.cs │ │ ├── frinta.s.cs │ │ ├── frintm.s.cs │ │ ├── frintn.s.cs │ │ ├── frintp.s.cs │ │ ├── ptrue.s.cs │ │ ├── neon-scalar-extract-narrow.s.cs │ │ ├── armv8.9a-prfm-slc.txt.cs │ │ ├── neon-scalar-saturating-rounding-shift.s.cs │ │ ├── st3q.s.cs │ │ ├── arm64-basic-a64-instructions.s.cs │ │ ├── dot-req.s.cs │ │ ├── ld3q.s.cs │ │ ├── faddqv.s.cs │ │ ├── fmaxqv.s.cs │ │ ├── fminqv.s.cs │ │ ├── fmaxnmqv.s.cs │ │ ├── fminnmqv.s.cs │ │ ├── armv9a-rme.s.cs │ │ └── armv8.4a-ras.s.cs │ ├── TriCore │ │ ├── debug.s.cs │ │ ├── handwrite.s.cs │ │ ├── csfr.s.cs │ │ ├── extr_u.s.cs │ │ └── rr_insn.s.cs │ ├── LoongArch │ │ ├── arm-jump.s.cs │ │ ├── d-branch.s.cs │ │ ├── and.s.cs │ │ ├── andi.s.cs │ │ ├── andn.s.cs │ │ ├── bsll.s.cs │ │ ├── bsrl.s.cs │ │ ├── mskgez.s.cs │ │ ├── msknz.s.cs │ │ ├── nor.s.cs │ │ ├── nori.s.cs │ │ ├── or.s.cs │ │ ├── ori.s.cs │ │ ├── orn.s.cs │ │ ├── xor.s.cs │ │ ├── xori.s.cs │ │ ├── perm.s.cs │ │ ├── bitseli.s.cs │ │ ├── barrier.s.cs │ │ ├── bitsel.s.cs │ │ ├── pseudos.s.cs │ │ ├── f-branch.s.cs │ │ ├── flogb.s.cs │ │ ├── fsqrt.s.cs │ │ ├── ld.s.cs │ │ ├── set.s.cs │ │ ├── st.s.cs │ │ ├── extl.s.cs │ │ ├── fclass.s.cs │ │ ├── fcvth.s.cs │ │ ├── fcvtl.s.cs │ │ ├── fadd.s.cs │ │ ├── fdiv.s.cs │ │ ├── fmax.s.cs │ │ ├── fmin.s.cs │ │ ├── fmul.s.cs │ │ ├── fsub.s.cs │ │ ├── insve0.s.cs │ │ ├── pickve.s.cs │ │ ├── fcvt.s.cs │ │ ├── fmaxa.s.cs │ │ ├── fmina.s.cs │ │ ├── insgr2vr.s.cs │ │ ├── fmadd.s.cs │ │ ├── fmsub.s.cs │ │ ├── fnmadd.s.cs │ │ ├── fnmsub.s.cs │ │ ├── x86-jump.s.cs │ │ ├── d-move.s.cs │ │ ├── permi.s.cs │ │ ├── scr.s.cs │ │ ├── sran.s.cs │ │ ├── srln.s.cs │ │ ├── srarn.s.cs │ │ ├── srlrn.s.cs │ │ ├── atomic.s.cs │ │ ├── clz.s.cs │ │ ├── clo.s.cs │ │ ├── neg.s.cs │ │ ├── pcnt.s.cs │ │ ├── f-memory.s.cs │ │ ├── lvz.s.cs │ │ ├── frecip.s.cs │ │ ├── frsqrt.s.cs │ │ ├── mskltz.s.cs │ │ ├── addi.s.cs │ │ ├── f-bound-check.s.cs │ │ ├── misc.s.cs │ │ ├── replgr2vr.s.cs │ │ ├── madd.s.cs │ │ ├── mul.s.cs │ │ ├── replvei.s.cs │ │ ├── subi.s.cs │ │ ├── adda.s.cs │ │ ├── arm-mov.s.cs │ │ ├── msub.s.cs │ │ ├── replve.s.cs │ │ ├── setallnez.s.cs │ │ ├── setanyeqz.s.cs │ │ ├── frstp.s.cs │ │ ├── ldrepl.s.cs │ │ ├── pickve2gr.s.cs │ │ ├── shuf4i.s.cs │ │ ├── srani.s.cs │ │ ├── srlni.s.cs │ │ ├── shuf.s.cs │ │ ├── srarni.s.cs │ │ ├── stelm.s.cs │ │ ├── extrins.s.cs │ │ ├── repl128vei.s.cs │ │ ├── signcov.s.cs │ │ ├── srlrni.s.cs │ │ ├── d-memory.s.cs │ │ ├── d-bound-check.s.cs │ │ ├── replve0.s.cs │ │ ├── add.s.cs │ │ ├── sub.s.cs │ │ ├── f-conv.s.cs │ │ ├── sllwil.s.cs │ │ ├── ssrln.s.cs │ │ ├── ssran.s.cs │ │ ├── ssrarn.s.cs │ │ ├── ssrlrn.s.cs │ │ ├── ffint.s.cs │ │ ├── x86-misc.s.cs │ │ ├── arm-alu.s.cs │ │ ├── bit-shift.s.cs │ │ ├── sat.s.cs │ │ ├── crc.s.cs │ │ ├── exth.s.cs │ │ ├── seq.s.cs │ │ ├── sra.s.cs │ │ ├── srl.s.cs │ │ ├── arm-shift.s.cs │ │ ├── memory.s.cs │ │ ├── sll.s.cs │ │ ├── avg.s.cs │ │ └── div.s.cs │ ├── Xtensa │ │ ├── memorder.s.cs │ │ ├── call-jump.s.cs │ │ ├── move.s.cs │ │ ├── memory.s.cs │ │ └── shift.s.cs │ ├── HPPA │ │ ├── longimm20.s.cs │ │ ├── sfu11.s.cs │ │ └── branch11.s.cs │ ├── RISCV │ │ └── insn-riscv64.s.cs │ ├── ARC │ │ └── br_arc.s.cs │ ├── README.md │ └── BPF │ │ └── classic-be.cs └── run_clang_format.sh ├── tests ├── unit │ ├── README.md │ └── CMakeLists.txt ├── details │ └── README.md ├── integration │ └── compat_header │ │ ├── README.md │ │ ├── include │ │ └── compat.h │ │ └── src │ │ └── main.c └── MC │ ├── Sparc │ ├── sparc-vis.s.yaml │ ├── sparc_misc_instructions_big_endian.txt.yaml │ ├── sparc_misc_instructions_v9_big_endian.txt.yaml │ ├── sparc_vis_v9_niagara_big_endian.txt.yaml │ └── sparc_little_endian_sparcel_linux_gnu_big_endian.txt.yaml │ ├── ARM │ ├── udf-thumb.s.yaml │ ├── cde-integer.s.yaml │ ├── armv8.5a-sb.s.yaml │ ├── udf-arm.s.yaml │ ├── thumb2-bxj.s.yaml │ ├── arm-it-block.s.yaml │ ├── bfloat16-a32.s.yaml │ ├── thumb2-pldw.s.yaml │ ├── thumb2-b.w-encodingT4.s.yaml │ ├── thumb2-bxj-v8.s.yaml │ ├── cde-vec-pred.s.yaml │ ├── udf-thumb-2.s.yaml │ ├── arm-thumb-trustzone.s.yaml │ ├── arm-trustzone.s.yaml │ ├── dot-req.s.yaml │ ├── idiv.s.yaml │ ├── neon-vswp.s.yaml │ ├── idiv-thumb.s.yaml │ ├── thumb2-ldrexd-strexd.s.yaml │ ├── cps.s.yaml │ ├── mve-vmov-pair.s.yaml │ └── bfloat16-t32.s.yaml │ ├── TriCore │ ├── debug.s.yaml │ └── handwrite.s.yaml │ ├── LoongArch │ ├── arm-jump.s.yaml │ ├── d-branch.s.yaml │ ├── and.s.yaml │ ├── andi.s.yaml │ ├── andn.s.yaml │ ├── bsll.s.yaml │ ├── bsrl.s.yaml │ ├── mskgez.s.yaml │ ├── msknz.s.yaml │ ├── nor.s.yaml │ ├── nori.s.yaml │ ├── or.s.yaml │ ├── ori.s.yaml │ ├── orn.s.yaml │ ├── xor.s.yaml │ ├── xori.s.yaml │ ├── perm.s.yaml │ ├── bitseli.s.yaml │ └── bitsel.s.yaml │ ├── Mips │ ├── hilo-addressing.s.yaml │ ├── invalid.txt.yaml │ ├── test_2r_msa64.txt.yaml │ ├── test_elm_msa64.txt.yaml │ ├── test_elm_insert_msa64.txt.yaml │ └── valid-micromips32r3.txt.yaml │ ├── AArch64 │ ├── SVE │ │ ├── setffr.s.yaml │ │ ├── dot-req.s.yaml │ │ └── matrix-multiply-fp32.s.yaml │ ├── arm64e.s.yaml │ ├── armv8r-inst.s.yaml │ ├── SME2 │ │ ├── zero.s.yaml │ │ └── feature-sme2-implies-sme.s.yaml │ ├── armv9.5a-spmu2.s.yaml │ ├── SVE2 │ │ ├── aesd.s.yaml │ │ ├── aese.s.yaml │ │ ├── sm4e.s.yaml │ │ ├── histseg.s.yaml │ │ ├── rax1.s.yaml │ │ ├── pmullb-128.s.yaml │ │ ├── pmullt-128.s.yaml │ │ └── sm4ekey.s.yaml │ ├── armv8.3a-pauth.s.yaml │ ├── SME │ │ ├── streaming-mode-neon-bf16.s.yaml │ │ └── fa64-implies-sve2.s.yaml │ ├── arm64-target-specific-sysreg.s.yaml │ ├── armv8.3a-ID_ISAR6_EL1.s.yaml │ └── SVE2p1 │ │ └── feature-sve2p1-implies-sve2.s.yaml │ ├── PowerPC │ └── ppc64_encoding_p9vector_only_offset_branch_syntax_noregname_little_endian_64_pwr9.txt.yaml │ └── Xtensa │ └── memorder.s.yaml ├── ext_patches └── README.md ├── windows └── README ├── docs ├── capstone-logo.png └── BHUSA2014-capstone.pdf ├── .gitattributes ├── xcode ├── CapstoneFramework │ └── module.modulemap └── Capstone.xcodeproj │ └── project.xcworkspace │ └── contents.xcworkspacedata ├── .gitmodules ├── contrib ├── cs_driver │ └── README ├── README └── m68k_instruction_tbl_gen │ └── Makefile ├── cross_configs └── README.md ├── windowsce └── .gitignore ├── capstone-config.cmake.in ├── arch ├── EVM │ ├── EVMMapping.h │ ├── EVMModule.h │ ├── EVMDisassembler.h │ └── EVMInstPrinter.h ├── SH │ └── SHModule.h ├── Xtensa │ ├── XtensaModule.h │ └── XtensaDisassembler.h ├── TriCore │ └── TriCoreModule.h ├── WASM │ ├── WASMModule.h │ ├── WASMMapping.h │ ├── WASMDisassembler.h │ └── WASMInstPrinter.h ├── ARC │ └── ARCModule.h ├── ARM │ └── ARMModule.h ├── X86 │ └── X86Module.h ├── BPF │ ├── BPFModule.h │ └── BPFInstPrinter.h ├── M68K │ └── M68KModule.h ├── HPPA │ ├── HPPAModule.h │ └── HPPADisassembler.h ├── M680X │ └── M680XModule.h ├── PowerPC │ └── PPCModule.h ├── Sparc │ ├── SparcModule.h │ ├── SparcDisassemblerExtension.c │ └── SparcDisassemblerExtension.h ├── XCore │ └── XCoreModule.h ├── RISCV │ └── RISCVModule.h ├── AArch64 │ └── AArch64Module.h ├── MOS65XX │ ├── MOS65XXModule.h │ └── MOS65XXDisassemblerInternals.h ├── SystemZ │ ├── SystemZModule.h │ └── SystemZDisassemblerExtension.h ├── Mips │ ├── MipsModule.h │ └── MipsDisassembler.h ├── TMS320C64x │ └── TMS320C64xModule.h ├── Alpha │ └── AlphaModule.h └── LoongArch │ └── LoongArchModule.h ├── .dockerignore ├── .appveyor.yml ├── .reuse └── templates │ └── license-template.jinja2 ├── MCDisassembler.h ├── pkgconfig.mk ├── functions.mk ├── include └── windowsce │ └── intrin.h ├── .editorconfig └── cstool └── getopt.h /bindings/vb6/Form1.frx: -------------------------------------------------------------------------------- 1 | Text1 -------------------------------------------------------------------------------- /bindings/java/capstone/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bindings/python/prebuilt/.gitkeep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /packages/rpm/postinstall.sh: -------------------------------------------------------------------------------- 1 | ldconfig -------------------------------------------------------------------------------- /suite/cstest/test/empty_test_file.yaml: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bindings/java/.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | tags 3 | -------------------------------------------------------------------------------- /bindings/powershell/Capstone/Lib/Capstone/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /tests/unit/README.md: -------------------------------------------------------------------------------- 1 | Nothing in here yet :( 2 | 3 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/cpptranslator/patches/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /suite/cstest/test/README.md: -------------------------------------------------------------------------------- 1 | Integration tests of cstest 2 | -------------------------------------------------------------------------------- /ext_patches/README.md: -------------------------------------------------------------------------------- 1 | Patches for external build dependencies. 2 | -------------------------------------------------------------------------------- /suite/fuzz/fuzz_disasm.options: -------------------------------------------------------------------------------- 1 | [libfuzzer] 2 | max_len = 4096 3 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips-jump-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | -------------------------------------------------------------------------------- /suite/MC/X86/x86_64-sse4a.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | -------------------------------------------------------------------------------- /windows/README: -------------------------------------------------------------------------------- 1 | This directory contains code specific to Windows platforms. 2 | -------------------------------------------------------------------------------- /packages/deb/triggers: -------------------------------------------------------------------------------- 1 | # Trigger ldconfig after install 2 | activate-noawait ldconfig 3 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparcv9-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | -------------------------------------------------------------------------------- /suite/auto-sync/format_py.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/bash 2 | 3 | python3 -m black src/autosync 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/cde-integer.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x06,0xbf = itte eq 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/udf-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x00,0xde = udf #0 3 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64e.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x20,0x00,0xc1,0xda = pacia x0, x1 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/armv8.5a-sb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x70,0xf0,0x7f,0xf5 = sb 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/basic-thumb2-instructions-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | -------------------------------------------------------------------------------- /suite/MC/ARM/udf-arm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xf0,0x00,0xf0,0xe7 = udf #0 3 | -------------------------------------------------------------------------------- /suite/auto-sync/vendor/README.md: -------------------------------------------------------------------------------- 1 | Directory for Capstone external auto-sync dependencies. 2 | 3 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-flagm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x1f,0x40,0x00,0xd5 = cfinv 3 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-sb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xff,0x30,0x03,0xd5 == sb 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-clrbhb.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0xdf,0x22,0x03,0xd5 = clrbhb 3 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8r-inst.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x9f,0x3c,0x03,0xd5 == dfb 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-bxj.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xc2,0xf3,0x00,0x8f = bxj r2 3 | -------------------------------------------------------------------------------- /docs/capstone-logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/capstone-engine/capstone/HEAD/docs/capstone-logo.png -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-pauth.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x3f,0x23,0x03,0xd5 == paciasp 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-it-block.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x03,0x20,0xa0,0x01 = moveq r2, r3 3 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/MCUpdaterTests/cps.s: -------------------------------------------------------------------------------- 1 | [0x00,0x0a,0x31,0xd5] 2 | #CHECK: mrs x0, TRCRSR 3 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-js.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x00,0x7e,0x1e == fjcvtzs w0, d0 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-js.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x00,0x7e,0x1e == fjcvtzs w0, d0 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-specres2.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0xc0,0x73,0x0b,0xd5 = cosp rctx, x0 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-pldw.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xb0,0xf8,0x01,0xf1 = pldw [r0, #0x101] 3 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-vis.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xbf,0xb0,0x0c,0x20 = fzeros %f31 3 | -------------------------------------------------------------------------------- /bindings/vb6/CX86Operand.cls: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/capstone-engine/capstone/HEAD/bindings/vb6/CX86Operand.cls -------------------------------------------------------------------------------- /bindings/vb6/screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/capstone-engine/capstone/HEAD/bindings/vb6/screenshot.png -------------------------------------------------------------------------------- /docs/BHUSA2014-capstone.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/capstone-engine/capstone/HEAD/docs/BHUSA2014-capstone.pdf -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-rasv2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x40,0x53,0x38,0xd5 == mrs x0, ERXGSR_EL1 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/bfloat16-a32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x05,0x3d,0x04,0xfc = vdot.bf16 d3, d4, d5 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-b.w-encodingT4.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x36,0xf0,0x06,0xbc = b.w #0x3680c 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-bxj-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xcd,0xf3,0x00,0x8f = bxj sp 3 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | /arch/**/*.inc linguist-language=C 2 | 3 | # Ensure shell scripts have LF line endings 4 | *.sh text eol=lf -------------------------------------------------------------------------------- /suite/MC/AArch64/a64-ignored-fields.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xe8,0x23,0x20,0x1e == fcmp s31, #0.0 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-persistent-memory.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x27,0x7c,0x0b,0xd5 == dc cvap, x7 4 | -------------------------------------------------------------------------------- /suite/MC/TriCore/debug.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None 2 | 0x4b, 0x00, 0x00, 0x00 = cmp.f d0, d0, d0 3 | -------------------------------------------------------------------------------- /suite/fuzz/README: -------------------------------------------------------------------------------- 1 | This directory contains a fuzz testing harness for Capstone. 2 | Run "make" to compile this code. 3 | -------------------------------------------------------------------------------- /xcode/CapstoneFramework/module.modulemap: -------------------------------------------------------------------------------- 1 | module capstone { 2 | header "Headers/capstone.h" 3 | export * 4 | } 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-mmfr2.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x43,0x07,0x38,0xd5 == mrs x3, ID_AA64MMFR2_EL1 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-persistent-memory.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x27,0x7c,0x0b,0xd5 == dc cvap, x7 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xe0,0x02,0x38,0xd5 == mrs x0, ID_ISAR6_EL1 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-persistent-memory.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x27,0x7d,0x0b,0xd5 == dc cvadp, x7 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-persistent-memory.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x27,0x7d,0x0b,0xd5 == dc cvadp, x7 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/udf-thumb-2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x00,0xde = udf #0 3 | 0xf0,0xf7,0x00,0xa0 = udf.w #0 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/arm-jump.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x04,0xc4,0x36,0x00 = setarmj $a0, 1 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/d-branch.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xc0,0x0c,0x00,0x48 = bceqz $fcc6, 0xc 3 | -------------------------------------------------------------------------------- /suite/MC/TriCore/handwrite.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None 2 | 0x8f,0xff,0x83,0x81 = xor d8, d15, #0x3f 3 | -------------------------------------------------------------------------------- /bindings/python/pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools", "build"] 3 | build-backend = "setuptools.build_meta" 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-target-specific-sysreg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x00,0xf2,0x1f,0xd5 = msr CPM_IOACC_CTL_EL3, x0 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-thumb-trustzone.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xff,0xf7,0x00,0x80 = smc #15 3 | 0x0c,0xbf = ite eq 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/and.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xee,0x4e,0x26,0x75 = xvand.v $xr14, $xr23, $xr19 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/andi.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xeb,0x08,0xd1,0x77 = xvandi.b $xr11, $xr7, 0x42 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/andn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xe3,0x0d,0x28,0x75 = xvandn.v $xr3, $xr15, $xr3 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/bsll.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xae,0x52,0x8e,0x76 = xvbsll.v $xr14, $xr21, 0x14 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/bsrl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa4,0xf4,0x8e,0x76 = xvbsrl.v $xr4, $xr5, 0x1d 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/mskgez.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xbe,0x50,0x9c,0x76 = xvmskgez.b $xr30, $xr5 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/msknz.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xd6,0x62,0x9c,0x76 = xvmsknz.b $xr22, $xr22 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/nor.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xe4,0x8e,0x27,0x75 = xvnor.v $xr4, $xr23, $xr3 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/nori.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x27,0x44,0xdf,0x77 = xvnori.b $xr7, $xr1, 0xd1 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/or.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa6,0xd7,0x26,0x75 = xvor.v $xr6, $xr29, $xr21 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ori.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x46,0xbc,0xd7,0x77 = xvori.b $xr6, $xr2, 0xef 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/orn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xb1,0x97,0x28,0x75 = xvorn.v $xr17, $xr29, $xr5 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/xor.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x4e,0x2b,0x27,0x75 = xvxor.v $xr14, $xr26, $xr10 3 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/xori.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x1a,0x55,0xda,0x77 = xvxori.b $xr26, $xr8, 0x95 3 | -------------------------------------------------------------------------------- /suite/MC/Xtensa/memorder.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN, None 2 | 0xd0,0x20,0x0 = extw 3 | 0xc0,0x20,0x0 = memw 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-trustzone.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x7f,0x00,0x60,0xe1 = smc #15 3 | 0x70,0x00,0x60,0x01 = smceq #0 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/dot-req.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x05,0xb0,0xa0,0xe1 = mov r11, r5 3 | 0x06,0x10,0xa0,0xe1 = mov r1, r6 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/perm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf8,0x42,0x7d,0x75 = xvperm.w $xr24, $xr23, $xr16 3 | -------------------------------------------------------------------------------- /bindings/python/.gitignore: -------------------------------------------------------------------------------- 1 | MANIFEST 2 | dist/ 3 | capstone/lib 4 | capstone/include 5 | pyx/lib 6 | pyx/include 7 | pyx/*.c 8 | pyx/*.pyx 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-altnzcv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x3f,0x40,0x00,0xd5 == xaflag 4 | 0x5f,0x40,0x00,0xd5 == axflag 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.7a-wfxt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x11,0x10,0x03,0xd5 == wfet x17 4 | 0x23,0x10,0x03,0xd5 == wfit x3 5 | -------------------------------------------------------------------------------- /suite/MC/ARM/cde-vec-pred.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None 2 | 0x41,0xfe,0x00,0xef = vptete.i8 eq, q0, q0 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/idiv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3 3 | 0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-vswp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x02,0x10,0xb2,0xf3 = vswp d1, d2 3 | 0x44,0x20,0xb2,0xf3 = vswp q1, q2 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/bitseli.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xad,0xe6,0xc5,0x77 = xvbitseli.b $xr13, $xr21, 0x79 3 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-rand.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x00,0x24,0x3b,0xd5 = mrs x0, RNDR 3 | 0x21,0x24,0x3b,0xd5 = mrs x1, RNDRRS 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.7a-wfxt.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x11,0x10,0x03,0xd5 == wfet x17 4 | 0x23,0x10,0x03,0xd5 == wfit x3 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/barrier.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x00,0x00,0x72,0x38 = dbar 0 3 | 0x00,0x80,0x72,0x38 = ibar 0 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/bitsel.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xb2,0xbf,0x2a,0x0d = xvbitsel.v $xr18, $xr29, $xr15, $xr21 3 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/MCUpdaterTests/cps.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 3 | 0x00,0x0a,0x31,0xd5 == mrs x0, TRCRSR 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-at.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x01,0x79,0x08,0xd5 == at s1e1rp, x1 4 | 0x22,0x79,0x08,0xd5 == at s1e1wp, x2 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-rand.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x24,0x3b,0xd5 == mrs x0, RNDR 4 | 0x21,0x24,0x3b,0xd5 == mrs x1, RNDRRS 5 | -------------------------------------------------------------------------------- /suite/MC/ARM/idiv-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3 3 | 0xb4,0xfb,0xf5,0xf3 = udiv r3, r4, r5 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/pseudos.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x00,0x00,0x40,0x03 = nop 3 | 0x28,0x01,0x15,0x00 = move $a4, $a5 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-vncr.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x00,0x22,0x3c,0xd5 = mrs x0, VNCR_EL2 3 | 0x00,0x22,0x1c,0xd5 = msr VNCR_EL2, x0 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.7a-hcx.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x42,0x12,0x3c,0xd5 == mrs x2, HCRX_EL2 4 | 0x43,0x12,0x1c,0xd5 == msr HCRX_EL2, x3 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-specres2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xc0,0x73,0x0b,0xd5 == cosp rctx, x0 4 | 0xc0,0x73,0x0b,0xd5 == cosp rctx, x0 5 | -------------------------------------------------------------------------------- /suite/MC/ARM/cps.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x61,0xb6 = cpsie f 3 | 0xaf,0xf3,0x43,0x85 = cpsie i, #3 4 | 0xaf,0xf3,0x00,0x81 = cps #0 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-at.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x01,0x79,0x08,0xd5 == at s1e1rp, x1 4 | 0x22,0x79,0x08,0xd5 == at s1e1wp, x2 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-vncr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x22,0x3c,0xd5 == mrs x0, VNCR_EL2 4 | 0x00,0x22,0x1c,0xd5 == msr VNCR_EL2, x0 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.7a-hcx.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x42,0x12,0x3c,0xd5 == mrs x2, HCRX_EL2 4 | 0x43,0x12,0x1c,0xd5 == msr HCRX_EL2, x3 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-add-sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x1f,0x84,0xf0,0x5e == add d31, d0, d16 4 | 0xe1,0x84,0xe8,0x7e == sub d1, d7, d8 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/udf.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x00,0x00,0x00,0x00 = udf #0 3 | 0x01,0x02,0x00,0x00 = udf #513 4 | 0xff,0xff,0x00,0x00 = udf #65535 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-rasv2.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x40,0x53,0x38,0xd5 == mrs x0, ERXGSR_EL1 4 | 0x40,0x53,0x18,0xd5 == msr S3_0_C5_C3_2, x0 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xf1,0x47,0xe8,0x5e == sshl d17, d31, d8 4 | 0xf1,0x47,0xe8,0x7e == ushl d17, d31, d8 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/spe.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0x99,0x18,0xd5 == msr PMSNEVFR_EL1, x0 4 | 0x21,0x99,0x38,0xd5 == mrs x1, PMSNEVFR_EL1 5 | -------------------------------------------------------------------------------- /suite/MC/TriCore/csfr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None 2 | 0xcd, 0x41, 0xe0, 0x0f = mtcr #-0x1fc, d1 3 | 0x4d, 0x40, 0xe0, 0x2f = mfcr d2, #0xfe04 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ldr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xe11f8000 == zt0, [x0] 3 | 0xe11f8140 == zt0, [x10] 4 | 0xe11f81a0 == zt0, [x13] 5 | 0xe11f83e0 == zt0, [sp] 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/speculation-barriers.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x9f,0x22,0x03,0xd5 = csdb 3 | 0x9f,0x30,0x03,0xd5 = ssbb 4 | 0x9f,0x34,0x03,0xd5 = pssbb 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/str.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xe13f8000 == zt0, [x0] 3 | 0xe13f8140 == zt0, [x10] 4 | 0xe13f81a0 == zt0, [x13] 5 | 0xe13f83e0 == zt0, [sp] 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/udf.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x00,0x00,0x00 == udf #0 4 | 0x01,0x02,0x00,0x00 == udf #513 5 | 0xff,0xff,0x00,0x00 == udf #65535 6 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-ldrexd-strexd.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xd2,0xe8,0x7f,0x01 = ldrexd r0, r1, [r2] 3 | 0xc6,0xe8,0x73,0x45 = strexd r3, r4, r5, [r6] 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/f-branch.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xc0,0x0c,0x00,0x48 = bceqz $fcc6, 0xc 3 | 0xc0,0x49,0x00,0x48 = bcnez $fcc6, 0x48 4 | -------------------------------------------------------------------------------- /suite/MC/TriCore/extr_u.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None 2 | 0x17, 0x01, 0x40, 0x02 = extr d0, d1, e2 3 | 0x17, 0x01, 0x60, 0x02 = extr.u d0, d1, e2 4 | -------------------------------------------------------------------------------- /suite/MC/X86/x86_64-rtm-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x0f,0x01,0xd5 = xend 3 | 0x0f,0x01,0xd6 = xtest 4 | 0xc6,0xf8,0x0d = xabort $13 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xf1,0x57,0xe8,0x5e == srshl d17, d31, d8 4 | 0xf1,0x57,0xe8,0x7e == urshl d17, d31, d8 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/speculation-barriers.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x9f,0x22,0x03,0xd5 == csdb 4 | 0x9f,0x30,0x03,0xd5 == ssbb 5 | 0x9f,0x34,0x03,0xd5 == pssbb 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/flogb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x91,0xc5,0x9c,0x76 = xvflogb.s $xr17, $xr12 3 | 0x3a,0xc8,0x9c,0x76 = xvflogb.d $xr26, $xr1 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fsqrt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x64,0xe7,0x9c,0x76 = xvfsqrt.s $xr4, $xr27 3 | 0x5a,0xe8,0x9c,0x76 = xvfsqrt.d $xr26, $xr2 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ld.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x63,0xb8,0xb5,0x2c = xvld $xr3, $sp, -0x292 3 | 0x37,0x39,0x48,0x38 = xvldx $xr23, $a5, $t2 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/set.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x27,0x98,0x9c,0x76 = xvseteqz.v $fcc7, $xr1 3 | 0xa7,0x9d,0x9c,0x76 = xvsetnez.v $fcc7, $xr13 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/st.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x8e,0xbd,0xce,0x2c = xvst $xr14, $t0, 0x3af 3 | 0x27,0x55,0x4c,0x38 = xvstx $xr7, $a5, $r21 4 | -------------------------------------------------------------------------------- /suite/cstest/test/missing_madatory_field.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | arch: "arm" 5 | expected: 6 | insns: 7 | - 8 | op_str: "mov r11, r5" 9 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "suite/auto-sync/vendor/tree-sitter-cpp"] 2 | path = suite/auto-sync/vendor/tree-sitter-cpp 3 | url = https://github.com/tree-sitter/tree-sitter-cpp.git 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-dit.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x5f,0x41,0x03,0xd5 = msr DIT, #1 3 | 0xa0,0x42,0x1b,0xd5 = msr DIT, x0 4 | 0xa0,0x42,0x3b,0xd5 = mrs x0, DIT 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/extl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x9d,0x01,0x09,0x77 = xvextl.q.d $xr29, $xr12 3 | 0x9b,0x02,0x0d,0x77 = xvextl.qu.du $xr27, $xr20 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fclass.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xe3,0xd4,0x9c,0x76 = xvfclass.s $xr3, $xr7 3 | 0x56,0xd9,0x9c,0x76 = xvfclass.d $xr22, $xr10 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fcvth.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x29,0xef,0x9d,0x76 = xvfcvth.s.h $xr9, $xr25 3 | 0x3d,0xf6,0x9d,0x76 = xvfcvth.d.s $xr29, $xr17 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fcvtl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xd0,0xe9,0x9d,0x76 = xvfcvtl.s.h $xr16, $xr14 3 | 0xb8,0xf0,0x9d,0x76 = xvfcvtl.d.s $xr24, $xr5 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-dit.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x5f,0x41,0x03,0xd5 == msr DIT, #1 4 | 0xa0,0x42,0x1b,0xd5 == msr DIT, x0 5 | 0xa0,0x42,0x3b,0xd5 == mrs x0, DIT 6 | -------------------------------------------------------------------------------- /suite/MC/ARM/bfloat16-t32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xb6,0xff,0x46,0x16 = vcvt.bf16.f32 d1, q3 3 | 0x18,0xbf = it ne 4 | 0xf3,0xee,0xe1,0x09 = vcvtt.bf16.f32 s1, s3 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fadd.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa6,0xbe,0x30,0x75 = xvfadd.s $xr6, $xr21, $xr15 3 | 0x1b,0x05,0x31,0x75 = xvfadd.d $xr27, $xr8, $xr1 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fdiv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xbd,0xb0,0x3a,0x75 = xvfdiv.s $xr29, $xr5, $xr12 3 | 0x5f,0x79,0x3b,0x75 = xvfdiv.d $xr31, $xr10, $xr30 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmax.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x1d,0xa3,0x3c,0x75 = xvfmax.s $xr29, $xr24, $xr8 3 | 0x3f,0x5f,0x3d,0x75 = xvfmax.d $xr31, $xr25, $xr23 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmin.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xbf,0xc0,0x3e,0x75 = xvfmin.s $xr31, $xr5, $xr16 3 | 0xcd,0x67,0x3f,0x75 = xvfmin.d $xr13, $xr30, $xr25 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xc9,0xf9,0x38,0x75 = xvfmul.s $xr9, $xr14, $xr30 3 | 0x5c,0x4f,0x39,0x75 = xvfmul.d $xr28, $xr26, $xr19 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fsub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x16,0x8c,0x32,0x75 = xvfsub.s $xr22, $xr0, $xr3 3 | 0x24,0x3f,0x33,0x75 = xvfsub.d $xr4, $xr25, $xr15 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/insve0.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x26,0xdc,0xff,0x76 = xvinsve0.w $xr6, $xr1, 7 3 | 0x3c,0xe0,0xff,0x76 = xvinsve0.d $xr28, $xr1, 0 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/pickve.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x99,0xc7,0x03,0x77 = xvpickve.w $xr25, $xr28, 1 3 | 0x2d,0xe0,0x03,0x77 = xvpickve.d $xr13, $xr1, 0 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fcvt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x29,0x5e,0x46,0x75 = xvfcvt.h.s $xr9, $xr17, $xr23 3 | 0x5b,0xf5,0x46,0x75 = xvfcvt.s.d $xr27, $xr10, $xr29 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmaxa.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x4f,0x96,0x40,0x75 = xvfmaxa.s $xr15, $xr18, $xr5 3 | 0x82,0x76,0x41,0x75 = xvfmaxa.d $xr2, $xr20, $xr29 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmina.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x7d,0xc7,0x42,0x75 = xvfmina.s $xr29, $xr27, $xr17 3 | 0x8c,0x4a,0x43,0x75 = xvfmina.d $xr12, $xr20, $xr18 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/insgr2vr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xd9,0xdf,0xeb,0x76 = xvinsgr2vr.w $xr25, $s7, 7 3 | 0xbb,0xe6,0xeb,0x76 = xvinsgr2vr.d $xr27, $r21, 1 4 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/fuzz/test_b.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARCH, 0, None 2 | 0x00,0x0a,0x31,0xd5 == mrs x0, TRCRSR 3 | 0x80,0x08,0x31,0xd5 == mrs x0, TRCEXTINSELR -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-predres.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x80,0x73,0x0b,0xd5 == cfp rctx, x0 4 | 0xa1,0x73,0x0b,0xd5 == dvp rctx, x1 5 | 0xe2,0x73,0x0b,0xd5 == cpp rctx, x2 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-clrbhb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0xdf,0x22,0x03,0xd5 = clrbhb 3 | 0xdf,0x22,0x03,0xd5 = clrbhb 4 | 0xdf,0x22,0x03,0xd5 = clrbhb 5 | 0xdf,0x22,0x03,0xd5 = clrbhb 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-extract.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0x18,0x02,0x2e == ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} 4 | 0x20,0x18,0x02,0x6e == ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} 5 | -------------------------------------------------------------------------------- /suite/MC/ARM/mve-vmov-pair.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None 2 | 0x07,0xec,0x0e,0x8f = vmov lr, r7, q4[2], q4[0] 3 | 0x11,0xec,0x14,0x6f = vmov q3[3], q3[1], r4, r1 4 | -------------------------------------------------------------------------------- /tests/details/README.md: -------------------------------------------------------------------------------- 1 | ## Test instruction details 2 | 3 | This directory contains test cases for the `cs_detail` struct. 4 | Test files are consumed by the `cstest` tool (see: `suite/cstest`). 5 | -------------------------------------------------------------------------------- /tests/integration/compat_header/README.md: -------------------------------------------------------------------------------- 1 | 5 | 6 | Compilation tests for the generated source code. 7 | -------------------------------------------------------------------------------- /bindings/python/capstone/arm64.py: -------------------------------------------------------------------------------- 1 | # Copyright © 2024 Peace-Maker 2 | # SPDX-License-Identifier: BSD-3 3 | # Compatibility header with pre v6 API 4 | from .arm64_const import * 5 | -------------------------------------------------------------------------------- /bindings/python/cstest_py/README.md: -------------------------------------------------------------------------------- 1 | ## Python cstest 2 | 3 | This is the equivalent testing tool to `suite/cstest/`. It consumes the `yaml` test files 4 | in `/tests/` and reports the results. 5 | -------------------------------------------------------------------------------- /contrib/cs_driver/README: -------------------------------------------------------------------------------- 1 | This directory contains a sample project for using Capstone from a Windows 2 | driver. Open cs_driver.sln with Visual Studio 2013 or newer and see cs_driver.c 3 | for details. 4 | -------------------------------------------------------------------------------- /cross_configs/README.md: -------------------------------------------------------------------------------- 1 | # Cross Compilation Configs 2 | 3 | This directory holds example cross compilation configs for cmake. 4 | 5 | Files are named like: `__.cmake` 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.4a-ebep.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x22,0x43,0x38,0xd5 == mrs x2, {{pm|PM}} 4 | 0x23,0x43,0x18,0xd5 == msr {{pm|PM}}, x3 5 | 0x1f,0x43,0x01,0xd5 == msr {{pm|PM}}, #1 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmadd.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xe5,0xff,0x1d,0x0a = xvfmadd.s $xr5, $xr31, $xr31, $xr27 3 | 0x09,0xfe,0x2c,0x0a = xvfmadd.d $xr9, $xr16, $xr31, $xr25 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fmsub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x71,0x8c,0x5b,0x0a = xvfmsub.s $xr17, $xr3, $xr3, $xr23 3 | 0xfe,0x41,0x67,0x0a = xvfmsub.d $xr30, $xr15, $xr16, $xr14 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fnmadd.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xce,0x5e,0x9c,0x0a = xvfnmadd.s $xr14, $xr22, $xr23, $xr24 3 | 0xc1,0x5f,0xa6,0x0a = xvfnmadd.d $xr1, $xr30, $xr23, $xr12 4 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/fnmsub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xb6,0x90,0xd5,0x0a = xvfnmsub.s $xr22, $xr5, $xr4, $xr11 3 | 0x08,0x74,0xee,0x0a = xvfnmsub.d $xr8, $xr0, $xr29, $xr28 4 | -------------------------------------------------------------------------------- /suite/run_clang_format.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | set -ex 4 | 5 | find -name "*.[ch]" | grep -vE "autosync" > files_to_format.txt 6 | clang-format-17 --files=files_to_format.txt --dry-run --Werror --verbose 7 | -------------------------------------------------------------------------------- /tests/integration/compat_header/include/compat.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2024 Rot127 2 | // SPDX-License-Identifier: BSD-3.0-Clause 3 | 4 | int arm64(void); 5 | int sysz(void); 6 | -------------------------------------------------------------------------------- /windowsce/.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.obj 3 | 4 | # Libraries 5 | *.lib 6 | 7 | # Shared objects (inc. Windows DLLs) 8 | *.dll 9 | 10 | # VisualStudio 11 | *.exp 12 | *.map 13 | *.pdb 14 | -------------------------------------------------------------------------------- /suite/MC/AArch64/tme.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x63,0x30,0x23,0xd5 == tstart x3 4 | 0x64,0x31,0x23,0xd5 == ttest x4 5 | 0x7f,0x30,0x03,0xd5 == tcommit 6 | 0x80,0x46,0x62,0xd4 == tcancel #0x1234 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-vector-lists.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x00,0x00,0x0c == st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] 4 | 0x00,0x04,0x00,0x0c == st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-flag.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x1f,0x40,0x00,0xd5 = cfinv 3 | 0x2d,0x08,0x00,0x3a = setf8 w1 4 | 0x2d,0x48,0x00,0x3a = setf16 w1 5 | 0x2f,0x84,0x1f,0xba = rmif x1, #63, #15 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-ssbs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xc2,0x42,0x3b,0xd5 == mrs x2, {{ssbs|SSBS}} 4 | 0xc3,0x42,0x1b,0xd5 == msr {{ssbs|SSBS}}, x3 5 | 0x3f,0x41,0x03,0xd5 == msr {{ssbs|SSBS}}, #1 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/bfcvt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc160e000 == z0.h, {z0.s, z1.s} 3 | 0xc160e155 == z21.h, {z10.s, z11.s} 4 | 0xc160e197 == z23.h, {z12.s, z13.s} 5 | 0xc160e3df == z31.h, {z30.s, z31.s} 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fcvtl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc1a0e001 == {z0.s, z1.s}, z0.h 3 | 0xc1a0e155 == {z20.s, z21.s}, z10.h 4 | 0xc1a0e1b7 == {z22.s, z23.s}, z13.h 5 | 0xc1a0e3ff == {z30.s, z31.s}, z31.h 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/bfcvtn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc160e020 == z0.h, {z0.s, z1.s} 3 | 0xc160e175 == z21.h, {z10.s, z11.s} 4 | 0xc160e1b7 == z23.h, {z12.s, z13.s} 5 | 0xc160e3ff == z31.h, {z30.s, z31.s} 6 | -------------------------------------------------------------------------------- /suite/MC/HPPA/longimm20.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None 2 | 0x34,0x22,0x3f,0xf1 = ldo -8(r1),rp 3 | 0x23,0x98,0xc5,0x4f = ldil -0x55810000,ret0 4 | 0x2b,0x98,0xc5,0x4f = addil -0x55810000,ret0 -------------------------------------------------------------------------------- /suite/MC/LoongArch/x86-jump.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x04,0x84,0x36,0x00 = setx86j $a0, 1 3 | 0xa4,0x78,0x00,0x00 = setx86loope $a0, $a1 4 | 0xa4,0x7c,0x00,0x00 = setx86loopne $a0, $a1 5 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/output/README.md: -------------------------------------------------------------------------------- 1 | 5 | 6 | Output directory for patched files. 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.1a-pan.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x9f,0x40,0x00,0xd5 == msr PAN, #0 4 | 0x9f,0x41,0x00,0xd5 == msr PAN, #1 5 | 0x65,0x42,0x18,0xd5 == msr PAN, x5 6 | 0x6d,0x42,0x38,0xd5 == mrs x13, PAN 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.4a-ebep.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x23,0x43,0x38,0xd5 == mrs x3, PM 4 | 0x26,0x43,0x18,0xd5 == msr PM, x6 5 | 0x1f,0x42,0x01,0xd5 == msr PM, #0 6 | 0x1f,0x43,0x01,0xd5 == msr PM, #1 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/st1q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xe4202000 == {z0.q}, p0, [z0.d, x0] 3 | 0xe4353555 == {z21.q}, p5, [z10.d, x21] 4 | 0xe4282db7 == {z23.q}, p3, [z13.d, x8] 5 | 0xe43f3fff == {z31.q}, p7, [z31.d] 6 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-branches.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x01,0x00,0x00,0xea = b #4 3 | 0x01,0x00,0x00,0xeb = bl #4 4 | 0x01,0x00,0x00,0x0a = beq #4 5 | 0x00,0x00,0x00,0xfb = blx #2 6 | 0x01,0x00,0x00,0xea = b #4 7 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/d-move.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xed,0x96,0x14,0x01 = fmov.s $ft5, $ft15 3 | 0x3e,0x99,0x14,0x01 = fmov.d $fs6, $ft1 4 | 0x92,0x56,0x02,0x0d = fsel $ft10, $ft12, $ft13, $fcc4 5 | -------------------------------------------------------------------------------- /suite/MC/Mips/hilo-addressing.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | // 0x3c,0x04,0xde,0xae = lui $a0, %hi(addr) 3 | 0x03,0xe0,0x00,0x08 = jr $ra 4 | // 0x80,0x82,0xbe,0xef = lb $v0, %lo(addr)($a0) 5 | -------------------------------------------------------------------------------- /suite/MC/Xtensa/call-jump.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN, None 2 | 0x5,0x0,0x0 = call0 LBL0 3 | 0xc0,0x1,0x0 = callx0 a1 4 | 0x6,0x0,0x0 = j LBL0 5 | 0x0,0x2,0x0 = jx a2 6 | 0x80,0x0,0x0 = ret 7 | -------------------------------------------------------------------------------- /suite/cstest/README.md: -------------------------------------------------------------------------------- 1 | 5 | 6 | ## Testing cstest 7 | 8 | Files to test `cstest` itself are located in `suite/cstest/test`. 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-adr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0x00,0x00,0x10 == adr x0, #0 4 | 0x00,0x00,0x00,0x30 == adr x0, #1 5 | 0x00,0x00,0x00,0x90 == adrp x0, #0 6 | 0x00,0x00,0x00,0xb0 == adrp x0, #4096 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8r-unsupported-inst.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x03,0x00,0xa0,0xd4 == dcps3 4 | 0x83,0x00,0xa0,0xd4 == encoding: [0x83,0x00,0xa0,0xd4] 5 | 0xe3,0x00,0x00,0xd4 == encoding: [0xe3,0x00,0x00,0xd4] 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-spmu2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x80,0x9c,0x13,0xd5 == msr SPMZR_EL0, x0 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/case-insen-reg-names.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xa0,0xd4,0x66,0x4e == fadd v0.2d, v5.2d, v6.2d 4 | 0xa0,0xd4,0x66,0x4e == fadd v0.2d, v5.2d, v6.2d 5 | 0xa0,0xd4,0x66,0x4e == fadd v0.2d, v5.2d, v6.2d 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ld1q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc400a000 == {z0.q}, p0/z, [z0.d, x0] 3 | 0xc415b555 == {z21.q}, p5/z, [z10.d, x21] 4 | 0xc408adb7 == {z23.q}, p3/z, [z13.d, x8] 5 | 0xc41fbfff == {z31.q}, p7/z, [z31.d] 6 | -------------------------------------------------------------------------------- /bindings/python/MANIFEST.in: -------------------------------------------------------------------------------- 1 | recursive-include src * 2 | recursive-include prebuilt * 3 | include BUILDING.md 4 | graft capstone/lib 5 | graft capstone/include 6 | global-include *.dll 7 | global-include *.dylib 8 | global-include *.so.* 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-uao.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x7f,0x40,0x00,0xd5 == msr UAO, #0 4 | 0x7f,0x41,0x00,0xd5 == msr UAO, #1 5 | 0x81,0x42,0x18,0xd5 == msr UAO, x1 6 | 0x82,0x42,0x38,0xd5 == mrs x2, UAO 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-rcpc.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0xc0,0xbf,0x38 == ldaprb w0, [x0] 4 | 0x00,0xc0,0xbf,0x78 == ldaprh w0, [x0] 5 | 0x00,0xc0,0xbf,0xb8 == ldapr w0, [x0] 6 | 0x00,0xc0,0xbf,0xf8 == ldapr x0, [x0] 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-spmu2.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x80,0x9c,0x13,0xd5 == msr SPMZR_EL0, x0 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/permi.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x87,0x95,0xe5,0x77 = xvpermi.w $xr7, $xr12, 0x65 3 | 0xd1,0x0c,0xea,0x77 = xvpermi.d $xr17, $xr6, 0x83 4 | 0xea,0xe1,0xee,0x77 = xvpermi.q $xr10, $xr15, 0xb8 5 | -------------------------------------------------------------------------------- /suite/MC/Mips/set-at-directive.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x08,0x00,0x60,0x00 = jr $v1 3 | 0x08,0x00,0x80,0x03 = jr $gp 4 | 0x08,0x00,0xc0,0x03 = jr $fp 5 | 0x08,0x00,0xa0,0x03 = jr $sp 6 | 0x08,0x00,0xe0,0x03 = jr $ra 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/tme.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x63,0x30,0x23,0xd5 = tstart x3 3 | 0x64,0x31,0x23,0xd5 = ttest x4 4 | 0x7f,0x30,0x03,0xd5 = tcommit 5 | 0x80,0x46,0x62,0xd4 = tcancel #0x1234 6 | 0x80,0x46,0x62,0xd4 = tcancel #0x1234 7 | -------------------------------------------------------------------------------- /suite/MC/ARM/vmovhr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0x16,0xee,0x90,0x09 = vmov.f16 r0, s13 3 | 0x0a,0xee,0x90,0x19 = vmov.f16 s21, r1 4 | 0x01,0xee,0x10,0xd9 = vmov.f16 s2, sp 5 | 0x12,0xee,0x90,0xd9 = vmov.f16 sp, s5 6 | -------------------------------------------------------------------------------- /suite/MC/HPPA/sfu11.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None 2 | 0x10,0x00,0x00,0xa3 = spop0,2,3,n 3 | 0x10,0x00,0x1a,0xa1 = spop1,2,3,n r1 4 | 0x10,0x20,0x04,0xa3 = spop2,2,3,n r1 5 | 0x10,0x41,0x06,0xa3 = spop3,2,3,n r1,rp -------------------------------------------------------------------------------- /suite/MC/LoongArch/scr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa0,0x08,0x00,0x00 = movgr2scr $scr0, $a1 3 | 0x24,0x0c,0x00,0x00 = movscr2gr $a0, $scr1 4 | 0x00,0x66,0x00,0x48 = jiscr0 0x64 5 | 0x00,0x67,0x00,0x48 = jiscr1 0x64 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/sran.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xbe,0x8d,0xf6,0x74 = xvsran.b.h $xr30, $xr13, $xr3 3 | 0x52,0x13,0xf7,0x74 = xvsran.h.w $xr18, $xr26, $xr4 4 | 0x7b,0xd6,0xf7,0x74 = xvsran.w.d $xr27, $xr19, $xr21 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srln.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa7,0x95,0xf4,0x74 = xvsrln.b.h $xr7, $xr13, $xr5 3 | 0x46,0x16,0xf5,0x74 = xvsrln.h.w $xr6, $xr18, $xr5 4 | 0x8c,0xf1,0xf5,0x74 = xvsrln.w.d $xr12, $xr12, $xr28 5 | -------------------------------------------------------------------------------- /suite/MC/X86/address-size.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) 3 | 0xc6,0x06,0x00 = movb $0x0, (%rsi) 4 | 0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) 5 | 0xc6,0x06,0x00 = movb $0x0, (%rsi) 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ldp-offset-predictable.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0xe0 0x83 0x00 0xa9 == stp x0, x0, [sp, #8] 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srarn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x92,0xbe,0xfa,0x74 = xvsrarn.b.h $xr18, $xr20, $xr15 3 | 0x2c,0x10,0xfb,0x74 = xvsrarn.h.w $xr12, $xr1, $xr4 4 | 0x49,0xea,0xfb,0x74 = xvsrarn.w.d $xr9, $xr18, $xr26 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srlrn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x24,0xeb,0xf8,0x74 = xvsrlrn.b.h $xr4, $xr25, $xr26 3 | 0xb1,0x04,0xf9,0x74 = xvsrlrn.h.w $xr17, $xr5, $xr1 4 | 0x3d,0xc4,0xf9,0x74 = xvsrlrn.w.d $xr29, $xr1, $xr17 5 | -------------------------------------------------------------------------------- /xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata: -------------------------------------------------------------------------------- 1 | 2 | 4 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-invalid-logical.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x7b 0xbf 0x25 0x72 == invalid instruction encoding 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/mopa.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x80a00008 == za0.h, p0/m, p0/m, z0.b, z0.b 3 | 0x80bfffe9 == za1.h, p7/m, p7/m, z31.b, z31.b 4 | 0x80a00000 == za0.s, p0/m, p0/m, z0.b, z0.b 5 | 0x80bfffe3 == za3.s, p7/m, p7/m, z31.b, z31.b 6 | -------------------------------------------------------------------------------- /contrib/README: -------------------------------------------------------------------------------- 1 | This directory contains contributions that do not belong to the core engine. 2 | Code here might be helpful for those who want to integrate Capstone into 3 | their own projects. 4 | 5 | The license of these code was defined by their authors. 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-nv-cond.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xfc,0xff,0x7f,0x1e == fcsel d28, d31, d31, nv 4 | 0x00,0xf0,0x80,0x9a == csel x0, x0, x0, nv 5 | 0x00,0xf0,0x40,0xfa == ccmp x0, x0, #0, nv 6 | 0x0f,0x00,0x00,0x54 == b.nv #0 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/extq.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x56825b7 == z23.b, z23.b, z13.b, #8 3 | 0x5602400 == z0.b, z0.b, z0.b, #0 4 | 0x5652555 == z21.b, z21.b, z10.b, #5 5 | 0x56825b7 == z23.b, z23.b, z13.b, #8 6 | 0x56f27ff == z31.b, z31.b, z31.b, #15 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0xb8,0xf1,0x5e == addp d0, v1.2d 4 | 0x72,0xd8,0x30,0x5e == faddp h18, v3.2h 5 | 0x53,0xd8,0x30,0x7e == faddp s19, v2.2s 6 | 0x34,0xd8,0x70,0x7e == faddp d20, v1.2d 7 | -------------------------------------------------------------------------------- /suite/MC/ARM/armv8.1m-pacbti.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xaf,0xf3,0x2d,0x80 = aut r12, lr, sp 3 | 0xaf,0xf3,0x0f,0x80 = bti 4 | 0xaf,0xf3,0x0f,0x80 = bti 5 | 0xaf,0xf3,0x1d,0x80 = pac r12, lr, sp 6 | 0xaf,0xf3,0x0d,0x80 = pacbti r12, lr, sp 7 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/atomic.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x62,0xdf,0x00,0x20 = ll.w $tp, $s4, 0xdc 3 | 0xd3,0x39,0x00,0x21 = sc.w $t7, $t2, 0x38 4 | 0xcd,0x81,0x57,0x38 = llacq.w $t1, $t2 5 | 0xcd,0x85,0x57,0x38 = screl.w $t1, $t2 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/clz.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xc5,0x10,0x9c,0x76 = xvclz.b $xr5, $xr6 3 | 0xe4,0x14,0x9c,0x76 = xvclz.h $xr4, $xr7 4 | 0x0c,0x18,0x9c,0x76 = xvclz.w $xr12, $xr0 5 | 0x01,0x1c,0x9c,0x76 = xvclz.d $xr1, $xr0 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-jump-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0xd4,0x00,0x02,0x98 = j 1328 3 | 0xf4,0x00,0x02,0x98 = jal 1328 4 | // 0x03,0xe6,0x0f,0x3c = jalr $a2 5 | 0x00,0x07,0x0f,0x3c = jr $a3 6 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/template_src.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2024 Rot127 2 | // SPDX-License-Identifier: BSD-3 3 | 4 | int main() { 5 | tfunction(); 6 | tfunction(); 7 | } 8 | -------------------------------------------------------------------------------- /capstone-config.cmake.in: -------------------------------------------------------------------------------- 1 | @PACKAGE_INIT@ 2 | 3 | set_and_check(capstone_INCLUDE_DIR "@CAPSTONE_CMAKE_INSTALL_INCLUDEDIR@") 4 | set_and_check(capstone_LIB_DIR "@CAPSTONE_CMAKE_INSTALL_LIBDIR@") 5 | 6 | include("${CMAKE_CURRENT_LIST_DIR}/capstone-targets.cmake") 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.2a-uao.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x7f,0x40,0x00,0xd5 == msr UAO, #0 4 | 0x7f,0x41,0x00,0xd5 == msr UAO, #1 5 | 0x7f,0x4f,0x00,0xd5 == msr UAO, #15 6 | 0x81,0x42,0x18,0xd5 == msr UAO, x1 7 | 0x82,0x42,0x38,0xd5 == mrs x2, UAO 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-ID_ISAR6_EL1.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+v8.3a'] 4 | 0xe0,0x02,0x38,0xd5 == mrs x0, ID_ISAR6_EL1 5 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/clo.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x89,0x01,0x9c,0x76 = xvclo.b $xr9, $xr12 3 | 0xd0,0x05,0x9c,0x76 = xvclo.h $xr16, $xr14 4 | 0x5e,0x0a,0x9c,0x76 = xvclo.w $xr30, $xr18 5 | 0xbf,0x0c,0x9c,0x76 = xvclo.d $xr31, $xr5 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/neg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x97,0x30,0x9c,0x76 = xvneg.b $xr23, $xr4 3 | 0xc8,0x35,0x9c,0x76 = xvneg.h $xr8, $xr14 4 | 0xd7,0x39,0x9c,0x76 = xvneg.w $xr23, $xr14 5 | 0x34,0x3e,0x9c,0x76 = xvneg.d $xr20, $xr17 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-multiply-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa4,0x00,0x3c,0xcb = madd $a0, $a1 3 | 0xa4,0x00,0x3c,0xdb = maddu $a0, $a1 4 | 0xa4,0x00,0x3c,0xeb = msub $a0, $a1 5 | 0xa4,0x00,0x3c,0xfb = msubu $a0, $a1 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips64-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64, None 2 | 3 | 0x81,0x00,0x42,0x4d == ldxc1 $f2, $2($10) # encoding: [0x81,0x00,0x42,0x4d] 4 | 0x09,0x40,0x24,0x4f == sdxc1 $f8, $4($25) # encoding: [0x09,0x40,0x24,0x4f] 5 | -------------------------------------------------------------------------------- /suite/MC/Xtensa/move.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN, None 2 | 0x40,0x23,0x83 = moveqz a2, a3, a4 3 | 0xc0,0x3b,0xb3 = movgez a3, a11, a12 4 | 0x12,0x8,0x0 = movi a1, -2048 5 | 0x90,0x78,0x3 = movltz a7, a8, a9 6 | 0xc0,0xb,0x93 = movnez a10, a11, a12 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/lut.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc08b0000 == {z0.b-z3.b}, zt0, {z0-z1} 3 | 0xc08b03dc == {z28.b-z31.b}, zt0, {z30-z31} 4 | 0xc09b0000 == {z0.b, z4.b, z8.b, z12.b}, zt0, {z0-z1} 5 | 0xc09b03d3 == {z19.b, z23.b, z27.b, z31.b}, zt0, {z30-z31} 6 | -------------------------------------------------------------------------------- /suite/MC/ARM/gas-compl-copr-reg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4] 3 | 0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0] 4 | 0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4] 5 | 0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0] 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/pcnt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x68,0x23,0x9c,0x76 = xvpcnt.b $xr8, $xr27 3 | 0x8c,0x24,0x9c,0x76 = xvpcnt.h $xr12, $xr4 4 | 0xff,0x2a,0x9c,0x76 = xvpcnt.w $xr31, $xr23 5 | 0x9a,0x2d,0x9c,0x76 = xvpcnt.d $xr26, $xr12 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-jump-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x00,0xd4,0x98,0x02 = j 1328 3 | 0x00,0xf4,0x98,0x02 = jal 1328 4 | // 0xe6,0x03,0x3c,0x0f = jalr $a2 5 | 0x07,0x00,0x3c,0x0f = jr $a3 6 | 0x07,0x00,0x3c,0x0f = jr $a3 7 | -------------------------------------------------------------------------------- /suite/cstest/test/invalid_test_file.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ] 5 | arch: "arm" 6 | options: ["arm"] 7 | expected: 8 | insns: 9 | - 10 | op_str: "mov r11, r5" 11 | # Invisble tab 12 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/f-memory.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf7,0xe9,0x03,0x2b = fld.s $ft15, $t3, 0xfa 3 | 0x7e,0x9a,0x43,0x2b = fst.s $fs6, $t7, 0xe6 4 | 0xe1,0x4d,0x30,0x38 = fldx.s $fa1, $t3, $t7 5 | 0x7a,0x58,0x38,0x38 = fstx.s $fs2, $sp, $fp 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/lvz.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x04,0x04,0x00,0x05 = gcsrrd $a0, 1 3 | 0x24,0x04,0x00,0x05 = gcsrwr $a0, 1 4 | 0xa4,0x04,0x00,0x05 = gcsrxchg $a0, $a1, 1 5 | 0x01,0x24,0x48,0x06 = gtlbflush 6 | 0x01,0x80,0x2b,0x00 = hvcl 1 7 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-unaligned.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x85,0x60,0x10,0x00 = lwl $a0, 16($a1) 3 | 0x85,0x60,0x10,0x10 = lwr $a0, 16($a1) 4 | 0x85,0x60,0x10,0x80 = swl $a0, 16($a1) 5 | 0x85,0x60,0x10,0x90 = swr $a0, 16($a1) 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-neg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x1d,0xbb,0xe0,0x7e == neg d29, d24 4 | 0xd3,0x79,0x20,0x7e == sqneg b19, b14 5 | 0xf5,0x79,0x60,0x7e == sqneg h21, h15 6 | 0x94,0x79,0xa0,0x7e == sqneg s20, s12 7 | 0x92,0x79,0xe0,0x7e == sqneg d18, d12 8 | -------------------------------------------------------------------------------- /suite/MC/ARM/mve-vpt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None 2 | 0x41,0xfe,0x02,0x2f = vpteee.i8 eq, q0, q1 3 | 0x21,0xfe,0x03,0x3f = vptttt.s32 gt, q0, q1 4 | 0x71,0xfe,0x82,0xef = vptete.f16 ne, q0, q1 5 | 0x1c,0xff,0x54,0x2f = vmaxnmt.f16 q1, q6, q2 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/frecip.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x03,0xf6,0x9c,0x76 = xvfrecip.s $xr3, $xr16 3 | 0x11,0xfb,0x9c,0x76 = xvfrecip.d $xr17, $xr24 4 | 0x03,0x16,0x9d,0x76 = xvfrecipe.s $xr3, $xr16 5 | 0x11,0x1b,0x9d,0x76 = xvfrecipe.d $xr17, $xr24 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/frsqrt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x3f,0x07,0x9d,0x76 = xvfrsqrt.s $xr31, $xr25 3 | 0xce,0x0a,0x9d,0x76 = xvfrsqrt.d $xr14, $xr22 4 | 0x3f,0x27,0x9d,0x76 = xvfrsqrte.s $xr31, $xr25 5 | 0xce,0x2a,0x9d,0x76 = xvfrsqrte.d $xr14, $xr22 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/mskltz.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xae,0x40,0x9c,0x76 = xvmskltz.b $xr14, $xr5 3 | 0x2b,0x47,0x9c,0x76 = xvmskltz.h $xr11, $xr25 4 | 0x6e,0x4b,0x9c,0x76 = xvmskltz.w $xr14, $xr27 5 | 0xe7,0x4e,0x9c,0x76 = xvmskltz.d $xr7, $xr23 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-fgwte3.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0xa0,0x11,0x3e,0xd5 == mrs x0, FGWTE3_EL3 5 | 0xa0,0x11,0x1e,0xd5 == msr FGWTE3_EL3, x0 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-fgwte3.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0xa0,0x11,0x3e,0xd5 == mrs x0, FGWTE3_EL3 5 | 0xa0,0x11,0x1e,0xd5 == msr FGWTE3_EL3, x0 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/addi.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xc1,0x0a,0x8a,0x76 = xvaddi.bu $xr1, $xr22, 2 3 | 0x43,0xf5,0x8a,0x76 = xvaddi.hu $xr3, $xr10, 0x1d 4 | 0x65,0x0d,0x8b,0x76 = xvaddi.wu $xr5, $xr11, 3 5 | 0x06,0x9c,0x8b,0x76 = xvaddi.du $xr6, $xr0, 7 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/f-bound-check.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x63,0x37,0x74,0x38 = fldgt.s $fa3, $s4, $t1 3 | 0xb8,0x47,0x75,0x38 = fldle.s $fs0, $s6, $t5 4 | 0xbf,0x79,0x76,0x38 = fstgt.s $fs7, $t1, $s7 5 | 0xad,0x1d,0x77,0x38 = fstle.s $ft5, $t1, $a3 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/misc.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x64,0x00,0x2b,0x00 = syscall 0x64 3 | 0xc7,0x00,0x2a,0x00 = break 0xc7 4 | 0x98,0x60,0x00,0x00 = rdtimel.w $s1, $a0 5 | 0xab,0x64,0x00,0x00 = rdtimeh.w $a7, $a1 6 | 0x03,0x6d,0x00,0x00 = cpucfg $sp, $a4 7 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/replgr2vr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x10,0x02,0x9f,0x76 = xvreplgr2vr.b $xr16, $t4 3 | 0xc7,0x06,0x9f,0x76 = xvreplgr2vr.h $xr7, $fp 4 | 0xe4,0x09,0x9f,0x76 = xvreplgr2vr.w $xr4, $t3 5 | 0x10,0x0f,0x9f,0x76 = xvreplgr2vr.d $xr16, $s1 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-movcond-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xe6,0x00,0x58,0x48 = movz $t1, $a2, $a3 3 | 0xe6,0x00,0x18,0x48 = movn $t1, $a2, $a3 4 | 0x26,0x55,0x7b,0x09 = movt $t1, $a2, $fcc0 5 | 0x26,0x55,0x7b,0x01 = movf $t1, $a2, $fcc0 6 | -------------------------------------------------------------------------------- /suite/MC/TriCore/rr_insn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None 2 | 0x0b, 0x20, 0xc0, 0x01 = abs d0, d2 3 | 0x0b, 0x60, 0xc0, 0x05 = abs.b d0, d6 4 | 0x0b, 0x40, 0xc0, 0x27 = abs.h d2, d4 5 | 0x0b, 0x10, 0xd0, 0x01 = abss d0, d1 6 | 0x0b, 0x10, 0xd0, 0x07 = abss.h d0, d1 7 | -------------------------------------------------------------------------------- /tests/MC/Sparc/sparc-vis.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xbf, 0xb0, 0x0c, 0x20 ] 5 | arch: "CS_ARCH_SPARC" 6 | options: [ "CS_MODE_BIG_ENDIAN" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "fzeros %f31" 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.4a-chk.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+v8.9a', 'mattr=+v9.4a', 'mattr=+chk', 'mattr=+v8a'] 4 | 0x1f,0x25,0x03,0xd5 == chkfeat x16 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-step2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x40,0x05,0x30,0xd5 == mrs x0, MDSTEPOP_EL1 5 | 0x40,0x05,0x10,0xd5 == msr MDSTEPOP_EL1, x0 6 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-step2.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x40,0x05,0x30,0xd5 == mrs x0, MDSTEPOP_EL1 5 | 0x40,0x05,0x10,0xd5 == msr MDSTEPOP_EL1, x0 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/madd.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xe5,0x23,0xa8,0x74 = xvmadd.b $xr5, $xr31, $xr8 3 | 0x04,0xf0,0xa8,0x74 = xvmadd.h $xr4, $xr0, $xr28 4 | 0xa2,0x61,0xa9,0x74 = xvmadd.w $xr2, $xr13, $xr24 5 | 0x13,0xc9,0xa9,0x74 = xvmadd.d $xr19, $xr8, $xr18 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf2,0x6c,0x84,0x74 = xvmul.b $xr18, $xr7, $xr27 3 | 0xe9,0xca,0x84,0x74 = xvmul.h $xr9, $xr23, $xr18 4 | 0x15,0x6d,0x85,0x74 = xvmul.w $xr21, $xr8, $xr27 5 | 0xe0,0xa1,0x85,0x74 = xvmul.d $xr0, $xr15, $xr8 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/replvei.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x77,0x8c,0xf7,0x72 = vreplvei.b $vr23, $vr3, 3 3 | 0x1b,0xc2,0xf7,0x72 = vreplvei.h $vr27, $vr16, 0 4 | 0xf2,0xee,0xf7,0x72 = vreplvei.w $vr18, $vr23, 3 5 | 0x8f,0xf5,0xf7,0x72 = vreplvei.d $vr15, $vr12, 1 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/subi.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x72,0x07,0x8c,0x76 = xvsubi.bu $xr18, $xr27, 1 3 | 0xe6,0xce,0x8c,0x76 = xvsubi.hu $xr6, $xr23, 0x13 4 | 0x6d,0x14,0x8d,0x76 = xvsubi.wu $xr13, $xr3, 5 5 | 0x9a,0xbb,0x8d,0x76 = xvsubi.du $xr26, $xr28, 0xe 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-multiply-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0xa4,0xcb,0x3c = madd $a0, $a1 3 | 0x00,0xa4,0xdb,0x3c = maddu $a0, $a1 4 | 0x00,0xa4,0xeb,0x3c = msub $a0, $a1 5 | 0x00,0xa4,0xfb,0x3c = msubu $a0, $a1 6 | -------------------------------------------------------------------------------- /tests/MC/ARM/udf-thumb.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0xde ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "udf #0" 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.8a-nmi.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x02,0x43,0x38,0xd5 == mrs x2, {{allint|ALLINT}} 4 | 0x03,0x43,0x18,0xd5 == msr {{allint|ALLINT}}, x3 5 | 0x1f,0x41,0x01,0xd5 == msr {{allint|ALLINT}}, #1 6 | 0xa7,0xc9,0x38,0xd5 == mrs x7, {{icc_nmiar1_el1|ICC_NMIAR1_EL1}} 7 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/adda.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x0a,0x6f,0x5c,0x74 = xvadda.b $xr10, $xr24, $xr27 3 | 0x80,0xf7,0x5c,0x74 = xvadda.h $xr0, $xr28, $xr29 4 | 0x3f,0x25,0x5d,0x74 = xvadda.w $xr31, $xr9, $xr9 5 | 0x2a,0xe4,0x5d,0x74 = xvadda.d $xr10, $xr1, $xr25 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/arm-mov.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa4,0x44,0x36,0x00 = armmove $a0, $a1, 1 3 | 0x9d,0xc4,0x3f,0x00 = armmov.w $a0, 1 4 | 0x9e,0xc4,0x3f,0x00 = armmov.d $a0, 1 5 | 0x44,0x04,0x5c,0x00 = armmfflag $a0, 1 6 | 0x64,0x04,0x5c,0x00 = armmtflag $a0, 1 7 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/msub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x96,0x1e,0xaa,0x74 = xvmsub.b $xr22, $xr20, $xr7 3 | 0x40,0xb2,0xaa,0x74 = xvmsub.h $xr0, $xr18, $xr12 4 | 0xc3,0x76,0xab,0x74 = xvmsub.w $xr3, $xr22, $xr29 5 | 0x4b,0x8b,0xab,0x74 = xvmsub.d $xr11, $xr26, $xr2 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/replve.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x14,0x2e,0x22,0x75 = xvreplve.b $xr20, $xr16, $a7 3 | 0xa0,0xe2,0x22,0x75 = xvreplve.h $xr0, $xr21, $s1 4 | 0x54,0x4a,0x23,0x75 = xvreplve.w $xr20, $xr18, $t6 5 | 0x64,0xdc,0x23,0x75 = xvreplve.d $xr4, $xr3, $s0 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/setallnez.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa5,0xb3,0x9c,0x76 = xvsetallnez.b $fcc5, $xr29 3 | 0x85,0xb4,0x9c,0x76 = xvsetallnez.h $fcc5, $xr4 4 | 0xa4,0xb8,0x9c,0x76 = xvsetallnez.w $fcc4, $xr5 5 | 0x87,0xbe,0x9c,0x76 = xvsetallnez.d $fcc7, $xr20 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/setanyeqz.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x05,0xa1,0x9c,0x76 = xvsetanyeqz.b $fcc5, $xr8 3 | 0x85,0xa6,0x9c,0x76 = xvsetanyeqz.h $fcc5, $xr20 4 | 0xc7,0xa8,0x9c,0x76 = xvsetanyeqz.w $fcc7, $xr6 5 | 0x26,0xae,0x9c,0x76 = xvsetanyeqz.d $fcc6, $xr17 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x60,0x85,0x00,0x10 = lwl $a0, 16($a1) 3 | 0x60,0x85,0x10,0x10 = lwr $a0, 16($a1) 4 | 0x60,0x85,0x80,0x10 = swl $a0, 16($a1) 5 | 0x60,0x85,0x90,0x10 = swr $a0, 16($a1) 6 | -------------------------------------------------------------------------------- /tests/MC/ARM/cde-integer.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x06, 0xbf ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "itte eq" 11 | -------------------------------------------------------------------------------- /tests/MC/TriCore/debug.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x4b, 0x00, 0x01, 0x00 ] 5 | arch: "CS_ARCH_TRICORE" 6 | options: [ "CS_MODE_TRICORE_131" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "cmp.f d0, d0, d0" 11 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/frstp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x57,0x4a,0x2b,0x75 = xvfrstp.b $xr23, $xr18, $xr18 3 | 0xcd,0x9b,0x2b,0x75 = xvfrstp.h $xr13, $xr30, $xr6 4 | 0x98,0x7f,0x9a,0x76 = xvfrstpi.b $xr24, $xr28, 0x1f 5 | 0x16,0xcb,0x9a,0x76 = xvfrstpi.h $xr22, $xr24, 0x12 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ldrepl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xb3,0x92,0x9d,0x32 = xvldrepl.b $xr19, $r21, 0x764 3 | 0x20,0xc6,0x4d,0x32 = xvldrepl.h $xr0, $t5, 0x6e2 4 | 0x4b,0x0f,0x2a,0x32 = xvldrepl.w $xr11, $s3, -0x5f4 5 | 0x9c,0xdd,0x13,0x32 = xvldrepl.d $xr28, $t0, 0x7b8 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/pickve2gr.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x6e,0xd9,0xef,0x76 = xvpickve2gr.w $t2, $xr11, 6 3 | 0xc8,0xe0,0xef,0x76 = xvpickve2gr.d $a4, $xr6, 0 4 | 0x2c,0xd0,0xf3,0x76 = xvpickve2gr.wu $t0, $xr1, 4 5 | 0x0a,0xe1,0xf3,0x76 = xvpickve2gr.du $a6, $xr8, 0 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/shuf4i.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x95,0xa3,0x92,0x77 = xvshuf4i.b $xr21, $xr28, 0xa8 3 | 0x72,0x58,0x94,0x77 = xvshuf4i.h $xr18, $xr3, 0x16 4 | 0x20,0x4b,0x99,0x77 = xvshuf4i.w $xr0, $xr25, 0x52 5 | 0x98,0x8c,0x9d,0x77 = xvshuf4i.d $xr24, $xr4, 0x63 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srani.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xee,0x7e,0x58,0x77 = xvsrani.b.h $xr14, $xr23, 0xf 3 | 0x02,0x95,0x58,0x77 = xvsrani.h.w $xr2, $xr8, 5 4 | 0x65,0x39,0x59,0x77 = xvsrani.w.d $xr5, $xr11, 0xe 5 | 0xf1,0xc4,0x5b,0x77 = xvsrani.d.q $xr17, $xr7, 0x71 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srlni.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x05,0x49,0x40,0x77 = xvsrlni.b.h $xr5, $xr8, 2 3 | 0x87,0xd0,0x40,0x77 = xvsrlni.h.w $xr7, $xr4, 0x14 4 | 0xfe,0x45,0x41,0x77 = xvsrlni.w.d $xr30, $xr15, 0x11 5 | 0x8f,0x7f,0x43,0x77 = xvsrlni.d.q $xr15, $xr28, 0x5f 6 | -------------------------------------------------------------------------------- /tests/MC/ARM/armv8.5a-sb.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x70, 0xf0, 0x7f, 0xf5 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "sb" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/udf-arm.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xf0, 0x00, 0xf0, 0xe7 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "udf #0" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/arm-jump.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x04, 0xc4, 0x36, 0x00 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "setarmj $a0, 1" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/d-branch.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xc0, 0x0c, 0x00, 0x48 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "bceqz $fcc6, 0xc" 11 | -------------------------------------------------------------------------------- /tests/MC/TriCore/handwrite.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x8f, 0xff, 0x83, 0x81 ] 5 | arch: "CS_ARCH_TRICORE" 6 | options: [ "CS_MODE_TRICORE_162" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xor d8, d15, #0x3f" 11 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/shuf.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xd4,0xac,0x67,0x0d = xvshuf.b $xr20, $xr6, $xr11, $xr15 3 | 0x1d,0x87,0x7a,0x75 = xvshuf.h $xr29, $xr24, $xr1 4 | 0x0f,0x77,0x7b,0x75 = xvshuf.w $xr15, $xr24, $xr29 5 | 0x5b,0xbe,0x7b,0x75 = xvshuf.d $xr27, $xr18, $xr15 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srarni.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf5,0x7f,0x5c,0x77 = xvsrarni.b.h $xr21, $xr31, 0xf 3 | 0xc4,0xe6,0x5c,0x77 = xvsrarni.h.w $xr4, $xr22, 0x19 4 | 0x18,0xa5,0x5d,0x77 = xvsrarni.w.d $xr24, $xr8, 0x29 5 | 0xa7,0x1c,0x5e,0x77 = xvsrarni.d.q $xr7, $xr5, 7 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/stelm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x54,0x5c,0xaa,0x33 = xvstelm.b $xr20, $tp, -0x69, 0xa 3 | 0x28,0x40,0x51,0x33 = xvstelm.h $xr8, $ra, 0xa0, 4 4 | 0x53,0x9e,0x21,0x33 = xvstelm.w $xr19, $t6, 0x19c, 0 5 | 0xd6,0xe3,0x1d,0x33 = xvstelm.d $xr22, $s7, 0x3c0, 3 6 | -------------------------------------------------------------------------------- /tests/MC/ARM/thumb2-bxj.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xc2, 0xf3, 0x00, 0x8f ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "bxj r2" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/and.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xee, 0x4e, 0x26, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvand.v $xr14, $xr23, $xr19" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/andi.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xeb, 0x08, 0xd1, 0x77 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvandi.b $xr11, $xr7, 0x42" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/andn.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xe3, 0x0d, 0x28, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvandn.v $xr3, $xr15, $xr3" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/bsll.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xae, 0x52, 0x8e, 0x76 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvbsll.v $xr14, $xr21, 0x14" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/bsrl.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xa4, 0xf4, 0x8e, 0x76 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvbsrl.v $xr4, $xr5, 0x1d" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/mskgez.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xbe, 0x50, 0x9c, 0x76 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvmskgez.b $xr30, $xr5" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/msknz.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xd6, 0x62, 0x9c, 0x76 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvmsknz.b $xr22, $xr22" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/nor.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xe4, 0x8e, 0x27, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvnor.v $xr4, $xr23, $xr3" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/nori.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x27, 0x44, 0xdf, 0x77 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvnori.b $xr7, $xr1, 0xd1" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/or.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xa6, 0xd7, 0x26, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvor.v $xr6, $xr29, $xr21" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/ori.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x46, 0xbc, 0xd7, 0x77 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvori.b $xr6, $xr2, 0xef" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/orn.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xb1, 0x97, 0x28, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvorn.v $xr17, $xr29, $xr5" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/xor.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x4e, 0x2b, 0x27, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvxor.v $xr14, $xr26, $xr10" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/xori.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x1a, 0x55, 0xda, 0x77 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvxori.b $xr26, $xr8, 0x95" 11 | -------------------------------------------------------------------------------- /tests/MC/Mips/hilo-addressing.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x03, 0xe0, 0x00, 0x08 ] 5 | arch: "CS_ARCH_MIPS" 6 | options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "jr $ra" 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-ats1a.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x41,0x79,0x08,0xd5 == at s1e1a, x1 5 | 0x41,0x79,0x0c,0xd5 == at s1e2a, x1 6 | 0x41,0x79,0x0e,0xd5 == at s1e3a, x1 7 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-aliases.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x03,0x10,0x82,0xe0 = add r1, r2, r3 3 | 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 4 | 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 5 | 0x03,0x10,0x82,0xe1 = orr r1, r2, r3 6 | 0x03,0x10,0x02,0xe0 = and r1, r2, r3 7 | 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/extrins.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xfe,0xf2,0x8f,0x77 = xvextrins.b $xr30, $xr23, 0xfc 3 | 0xa0,0x21,0x8b,0x77 = xvextrins.h $xr0, $xr13, 0xc8 4 | 0xae,0x62,0x86,0x77 = xvextrins.w $xr14, $xr21, 0x98 5 | 0xdf,0x1f,0x82,0x77 = xvextrins.d $xr31, $xr30, 0x87 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/repl128vei.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x6a,0x8a,0xf7,0x76 = xvrepl128vei.b $xr10, $xr19, 2 3 | 0x66,0xca,0xf7,0x76 = xvrepl128vei.h $xr6, $xr19, 2 4 | 0xab,0xe5,0xf7,0x76 = xvrepl128vei.w $xr11, $xr13, 1 5 | 0xff,0xf2,0xf7,0x76 = xvrepl128vei.d $xr31, $xr23, 0 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/signcov.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x01,0x37,0x2e,0x75 = xvsigncov.b $xr1, $xr24, $xr13 3 | 0xe8,0xba,0x2e,0x75 = xvsigncov.h $xr8, $xr23, $xr14 4 | 0x23,0x2b,0x2f,0x75 = xvsigncov.w $xr3, $xr25, $xr10 5 | 0x3a,0xfe,0x2f,0x75 = xvsigncov.d $xr26, $xr17, $xr31 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srlrni.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x2a,0x72,0x44,0x77 = xvsrlrni.b.h $xr10, $xr17, 0xc 3 | 0xf6,0xb6,0x44,0x77 = xvsrlrni.h.w $xr22, $xr23, 0xd 4 | 0xd2,0xea,0x45,0x77 = xvsrlrni.w.d $xr18, $xr22, 0x3a 5 | 0x19,0xa9,0x46,0x77 = xvsrlrni.d.q $xr25, $xr8, 0x2a 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-movcond-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0xe6,0x48,0x58 = movz $t1, $a2, $a3 3 | 0x00,0xe6,0x48,0x18 = movn $t1, $a2, $a3 4 | 0x55,0x26,0x09,0x7b = movt $t1, $a2, $fcc0 5 | 0x55,0x26,0x01,0x7b = movf $t1, $a2, $fcc0 6 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file_patching_new.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2024 Rot127 2 | // SPDX-License-Identifier: BSD-3 3 | 4 | void function_a(int x) { 5 | return; 6 | } 7 | 8 | void function_b(int x) { 9 | return; 10 | } 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE/setffr.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x90, 0x2c, 0x25 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "setffr" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/arm64e.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0x00, 0xc1, 0xda ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "arm64e--" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "pacia x0, x1" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/armv8r-inst.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x9f, 0x3c, 0x03, 0xd5 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "v8r" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "dfb" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/arm-it-block.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x03, 0x20, 0xa0, 0x01 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "moveq r2, r3" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/perm.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xf8, 0x42, 0x7d, 0x75 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvperm.w $xr24, $xr23, $xr16" 11 | -------------------------------------------------------------------------------- /tests/MC/Sparc/sparc_misc_instructions_big_endian.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x00, 0x00, 0x00 ] 5 | arch: "CS_ARCH_SPARC" 6 | options: [ "CS_MODE_BIG_ENDIAN" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "unimp 0" 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-ats1a.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x41,0x79,0x08,0xd5 == at s1e1a, x1 5 | 0x41,0x79,0x0c,0xd5 == at s1e2a, x1 6 | 0x41,0x79,0x0e,0xd5 == at s1e3a, x1 7 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb-mov.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x85,0x46 = mov sp, r0 3 | 0x68,0x46 = mov r0, sp 4 | 0xed,0x46 = mov sp, sp 5 | 0x87,0x46 = mov pc, r0 6 | 0x78,0x46 = mov r0, pc 7 | 0xff,0x46 = mov pc, pc 8 | 0x4f,0xea,0x00,0x0d = mov.w sp, r0 9 | 0x4f,0xea,0x0d,0x00 = mov.w r0, sp 10 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt: -------------------------------------------------------------------------------- 1 | # The RUN line parsing 2 | # RUN: llvm-mc --disassemble -triple=arm64 < %s | FileCheck %s 3 | 4 | 5 | [0x00,0x0a,0x31,0xd5] 6 | # CHECK: mrs x0, TRCRSR 7 | 8 | [0x80,0x08,0x31,0xd5] 9 | # CHECK: mrs x0, TRCEXTINSELR 10 | -------------------------------------------------------------------------------- /tests/MC/ARM/bfloat16-a32.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x05, 0x3d, 0x04, 0xfc ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "vdot.bf16 d3, d4, d5" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/thumb2-pldw.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xb0, 0xf8, 0x01, 0xf1 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "pldw [r0, #0x101]" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/bitseli.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xad, 0xe6, 0xc5, 0x77 ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvbitseli.b $xr13, $xr21, 0x79" 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/colored.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+all'] 4 | 0xa1 0x00 0x00 0x54 == b.ne #20 5 | 0x00 0x7c 0x00 0x13 == asr w0, w0, #0 6 | -------------------------------------------------------------------------------- /suite/MC/Xtensa/memory.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN, None 2 | 0x22,0x1,0x3 = l8ui a2, a1, 3 3 | 0x32,0x91,0x2 = l16si a3, a1, 4 4 | 0x42,0x11,0x3 = l16ui a4, a1, 6 5 | 0x52,0x21,0x2 = l32i a5, a1, 8 6 | 0x22,0x41,0x3 = s8i a2, a1, 3 7 | 0x32,0x51,0x2 = s16i a3, a1, 4 8 | 0x52,0x61,0x2 = s32i a5, a1, 8 9 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SME2/zero.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x01, 0x00, 0x48, 0xc0 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme2" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "zero { zt0 }" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/armv9.5a-spmu2.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x80, 0x9c, 0x13, 0xd5 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "msr SPMZR_EL0, x0" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x36, 0xf0, 0x06, 0xbc ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "b.w #0x3680c" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/thumb2-bxj-v8.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xcd, 0xf3, 0x00, 0x8f ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_V8", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "bxj sp" 11 | -------------------------------------------------------------------------------- /tests/MC/LoongArch/bitsel.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xb2, 0xbf, 0x2a, 0x0d ] 5 | arch: "CS_ARCH_LOONGARCH" 6 | options: [ "CS_MODE_LOONGARCH64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "xvbitsel.v $xr18, $xr29, $xr15, $xr21" 11 | -------------------------------------------------------------------------------- /tests/MC/Mips/invalid.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x00, 0x00, 0x00 ] 5 | arch: "CS_ARCH_MIPS" 6 | options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "nop" 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-spsel-sysreg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xbf,0x40,0x00,0xd5 == msr SPSel, #0 4 | 0x00,0x42,0x18,0xd5 == msr SPSel, x0 5 | 0xdf,0x40,0x03,0xd5 == msr DAIFSet, #0 6 | 0x00,0x52,0x18,0xd5 == msr ESR_EL1, x0 7 | 0x00,0x42,0x38,0xd5 == mrs x0, SPSel 8 | 0x00,0x52,0x38,0xd5 == mrs x0, ESR_EL1 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.3a-rcpc.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x00,0xc0,0xbf,0x38 == ldaprb w0, [x0] 4 | 0x20,0xc2,0xbf,0x78 == ldaprh w0, [x17] 5 | 0x20,0xc0,0xbf,0xb8 == ldapr w0, [x1] 6 | 0x00,0xc0,0xbf,0xf8 == ldapr x0, [x0] 7 | 0x12,0xc0,0xbf,0xb8 == ldapr w18, [x0] 8 | 0x0f,0xc0,0xbf,0xf8 == ldapr x15, [x0] 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.4a-chk.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+chk', 'mattr=+v8.9a', 'mattr=+v9.4a', 'mattr=+v8a'] 4 | 0x1f,0x25,0x03,0xd5 == chkfeat x16 5 | 0x1f,0x25,0x03,0xd5 == chkfeat x16 6 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/d-memory.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf7,0xe9,0x03,0x2b = fld.s $ft15, $t3, 0xfa 3 | 0x36,0xca,0x81,0x2b = fld.d $ft14, $t5, 0x72 4 | 0xfc,0x18,0xc3,0x2b = fst.d $fs4, $a3, 0xc6 5 | 0xbb,0x7d,0x34,0x38 = fldx.d $fs3, $t1, $s8 6 | 0xe6,0x45,0x3c,0x38 = fstx.d $fa6, $t3, $t5 7 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/test_include.inc: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2024 Rot127 2 | // SPDX-License-Identifier: BSD-3 3 | 4 | #ifdef GUARD 5 | #undef GUARD 6 | 7 | Partial include of something 8 | 9 | #endif 10 | 11 | This part should be included if the whole file is included. 12 | -------------------------------------------------------------------------------- /tests/MC/Sparc/sparc_misc_instructions_v9_big_endian.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x00, 0x00, 0x00 ] 5 | arch: "CS_ARCH_SPARC" 6 | options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "unimp 0" 11 | -------------------------------------------------------------------------------- /arch/EVM/EVMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #include 5 | 6 | void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 7 | const char *EVM_insn_name(csh handle, unsigned int id); 8 | const char *EVM_group_name(csh handle, unsigned int id); 9 | -------------------------------------------------------------------------------- /arch/SH/SHModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Yoshinori Sato, 2022 */ 3 | 4 | #ifndef CS_SH_MODULE_H 5 | #define CS_SH_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err SH_global_init(cs_struct *ud); 10 | cs_err SH_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/aesd.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xe0, 0xe7, 0x22, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-aes" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "aesd z0.b, z0.b, z31.b" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/aese.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xe0, 0xe3, 0x22, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-aes" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "aese z0.b, z0.b, z31.b" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/sm4e.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xe0, 0xe3, 0x23, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-sm4" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "sm4e z0.s, z0.s, z31.s" 11 | -------------------------------------------------------------------------------- /arch/Xtensa/XtensaModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By billow , 2024 */ 3 | 4 | #ifndef CS_XTENSA_MODULE_H 5 | #define CS_XTENSA_MODULE_H 6 | 7 | cs_err Xtensa_global_init(cs_struct *ud); 8 | cs_err Xtensa_option(cs_struct *handle, cs_opt_type type, size_t value); 9 | 10 | #endif 11 | -------------------------------------------------------------------------------- /suite/MC/ARM/crc32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x42,0x00,0x01,0xe1 = crc32b r0, r1, r2 3 | 0x42,0x00,0x21,0xe1 = crc32h r0, r1, r2 4 | 0x42,0x00,0x41,0xe1 = crc32w r0, r1, r2 5 | 0x42,0x02,0x01,0xe1 = crc32cb r0, r1, r2 6 | 0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2 7 | 0x42,0x02,0x41,0xe1 = crc32cw r0, r1, r2 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/d-bound-check.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x63,0x37,0x74,0x38 = fldgt.s $fa3, $s4, $t1 3 | 0xba,0xfc,0x74,0x38 = fldgt.d $fs2, $a1, $s8 4 | 0xe3,0xd9,0x75,0x38 = fldle.d $fa3, $t3, $fp 5 | 0x6d,0xe9,0x76,0x38 = fstgt.d $ft5, $a7, $s3 6 | 0x32,0xb5,0x77,0x38 = fstle.d $ft10, $a5, $t1 7 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/replve0.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x8b,0x02,0x07,0x77 = xvreplve0.b $xr11, $xr20 3 | 0x4d,0x83,0x07,0x77 = xvreplve0.h $xr13, $xr26 4 | 0x88,0xc1,0x07,0x77 = xvreplve0.w $xr8, $xr12 5 | 0x94,0xe0,0x07,0x77 = xvreplve0.d $xr20, $xr4 6 | 0x91,0xf2,0x07,0x77 = xvreplve0.q $xr17, $xr20 7 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparcv8-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x81,0xa8,0x0a,0x24 = fcmps %f0, %f4 3 | 0x81,0xa8,0x0a,0x44 = fcmpd %f0, %f4 4 | 0x81,0xa8,0x0a,0x64 = fcmpq %f0, %f4 5 | 0x81,0xa8,0x0a,0xa4 = fcmpes %f0, %f4 6 | 0x81,0xa8,0x0a,0xc4 = fcmped %f0, %f4 7 | 0x81,0xa8,0x0a,0xe4 = fcmpeq %f0, %f4 8 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/histseg.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0xa0, 0x3f, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "histseg z0.b, z1.b, z31.b" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/rax1.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0xf4, 0x3f, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-sha3" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "rax1 z0.d, z1.d, z31.d" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/armv8.3a-pauth.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x3f, 0x23, 0x03, 0xd5 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64-none-linux-gnu", "pauth" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "paciasp" 11 | -------------------------------------------------------------------------------- /tests/MC/Sparc/sparc_vis_v9_niagara_big_endian.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xbf, 0xb0, 0x0c, 0x20 ] 5 | arch: "CS_ARCH_SPARC" 6 | options: [ "CS_MODE_V9", "niagara", "CS_MODE_BIG_ENDIAN" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "fzeros %f31" 11 | -------------------------------------------------------------------------------- /arch/TriCore/TriCoreModule.h: -------------------------------------------------------------------------------- 1 | // 2 | // Created by aya on 3/4/23. 3 | // 4 | 5 | #ifndef CAPSTONE_TRICODEMODULE_H 6 | #define CAPSTONE_TRICODEMODULE_H 7 | 8 | cs_err TRICORE_global_init(cs_struct *ud); 9 | cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value); 10 | 11 | #endif // CAPSTONE_TRICODEMODULE_H 12 | -------------------------------------------------------------------------------- /arch/WASM/WASMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifndef CS_WASM_MODULE_H 5 | #define CS_WASM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err WASM_global_init(cs_struct *ud); 10 | cs_err WASM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-bti.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x1f,0x24,0x03,0xd5 == bti 4 | 0x5f,0x24,0x03,0xd5 == bti c 5 | 0x9f,0x24,0x03,0xd5 == bti j 6 | 0xdf,0x24,0x03,0xd5 == bti jc 7 | 0x1f,0x24,0x03,0xd5 == bti 8 | 0x5f,0x24,0x03,0xd5 == bti c 9 | 0x9f,0x24,0x03,0xd5 == bti j 10 | 0xdf,0x24,0x03,0xd5 == bti jc 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.8a-nmi.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x03,0x43,0x38,0xd5 == mrs x3, ALLINT 4 | 0x06,0x43,0x18,0xd5 == msr ALLINT, x6 5 | 0x1f,0x40,0x01,0xd5 == msr ALLINT, #0 6 | 0x1f,0x41,0x01,0xd5 == msr ALLINT, #1 7 | 0xbf,0x51,0x00,0xd5 == msr S0_0_C5_C1_5, xzr 8 | 0xa7,0xc9,0x38,0xd5 == mrs x7, ICC_NMIAR1_EL1 9 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/add.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x74,0x16,0x0a,0x74 = xvadd.b $xr20, $xr19, $xr5 3 | 0xf8,0xb8,0x0a,0x74 = xvadd.h $xr24, $xr7, $xr14 4 | 0x33,0x54,0x0b,0x74 = xvadd.w $xr19, $xr1, $xr21 5 | 0xd3,0xb4,0x0b,0x74 = xvadd.d $xr19, $xr6, $xr13 6 | 0x84,0x1b,0x2d,0x75 = xvadd.q $xr4, $xr28, $xr6 7 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE/dot-req.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0x00, 0xa2, 0x04 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64-none-linux-gnu", "sve" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "add z0.s, z1.s, z2.s" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/pmullb-128.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xdd, 0x6b, 0x1f, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-aes" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "pmullb z29.q, z30.d, z31.d" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/pmullt-128.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xdd, 0x6f, 0x1f, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-aes" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "pmullt z29.q, z30.d, z31.d" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2/sm4ekey.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0xf0, 0x3f, 0x45 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2-sm4" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "sm4ekey z0.s, z1.s, z31.s" 11 | -------------------------------------------------------------------------------- /tests/MC/Mips/test_2r_msa64.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x7b, 0x03, 0x4e, 0xde ] 5 | arch: "CS_ARCH_MIPS" 6 | options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "fill.d $w27, $9" 11 | -------------------------------------------------------------------------------- /tests/MC/Sparc/sparc_little_endian_sparcel_linux_gnu_big_endian.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x40, 0xc0, 0x9f ] 5 | arch: "CS_ARCH_SPARC" 6 | options: [ "CS_MODE_V9", "CS_MODE_LITTLE_ENDIAN" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "call %g1" 11 | -------------------------------------------------------------------------------- /.dockerignore: -------------------------------------------------------------------------------- 1 | # Ignore source control directories 2 | .git 3 | .svn 4 | 5 | # Ignore build directories 6 | build 7 | dist 8 | 9 | # Ignore dependency directories 10 | node_modules 11 | vendor 12 | 13 | # Ignore temporary files 14 | *.log 15 | *.tmp 16 | 17 | # Ignore environment files 18 | .env 19 | 20 | # Ignore tests 21 | tests -------------------------------------------------------------------------------- /suite/MC/ARM/crc32-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xc1,0xfa,0x82,0xf0 = crc32b r0, r1, r2 3 | 0xc1,0xfa,0x92,0xf0 = crc32h r0, r1, r2 4 | 0xc1,0xfa,0xa2,0xf0 = crc32w r0, r1, r2 5 | 0xd1,0xfa,0x82,0xf0 = crc32cb r0, r1, r2 6 | 0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2 7 | 0xd1,0xfa,0xa2,0xf0 = crc32cw r0, r1, r2 8 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumbv7m.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None 2 | 0xef,0xf3,0x11,0x80 = mrs r0, basepri 3 | 0xef,0xf3,0x12,0x80 = mrs r0, basepri_max 4 | 0xef,0xf3,0x13,0x80 = mrs r0, faultmask 5 | 0x80,0xf3,0x11,0x88 = msr basepri, r0 6 | 0x80,0xf3,0x12,0x88 = msr basepri_max, r0 7 | 0x80,0xf3,0x13,0x88 = msr faultmask, r0 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x8b,0x43,0x0c,0x74 = xvsub.b $xr11, $xr28, $xr16 3 | 0x6b,0xe0,0x0c,0x74 = xvsub.h $xr11, $xr3, $xr24 4 | 0xee,0x1a,0x0d,0x74 = xvsub.w $xr14, $xr23, $xr6 5 | 0xa5,0x9d,0x0d,0x74 = xvsub.d $xr5, $xr13, $xr7 6 | 0x4d,0xff,0x2d,0x75 = xvsub.q $xr13, $xr26, $xr31 7 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-atomic-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x81,0x43,0xe0,0x0f = membar 15 3 | 0x81,0x43,0xc0,0x00 = stbar 4 | 0xd4,0x7e,0x00,0x16 = swap [%i0+%l6], %o2 5 | 0xd4,0x7e,0x20,0x20 = swap [%i0+32], %o2 6 | 0xd5,0xe6,0x10,0x16 = cas [%i0], %l6, %o2 7 | 0xd5,0xf6,0x10,0x16 = casx [%i0], %l6, %o2 8 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x65, 0x40, 0x63, 0x1e ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "-neon", "+sme" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "bfcvt h5, s3" 11 | -------------------------------------------------------------------------------- /.appveyor.yml: -------------------------------------------------------------------------------- 1 | version: 4.0-{build} 2 | 3 | os: 4 | - Visual Studio 2015 5 | 6 | before_build: 7 | - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 8 | 9 | build_script: 10 | - mkdir build 11 | - cd build 12 | - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. 13 | - nmake 14 | 15 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-flag.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x1f,0x40,0x00,0xd5 == cfinv 4 | 0x2d,0x08,0x00,0x3a == setf8 w1 5 | 0xed,0x0b,0x00,0x3a == setf8 wzr 6 | 0x2d,0x48,0x00,0x3a == setf16 w1 7 | 0xed,0x4b,0x00,0x3a == setf16 wzr 8 | 0x2f,0x84,0x1f,0xba == rmif x1, #63, #15 9 | 0xef,0x87,0x1f,0xba == rmif xzr, #63, #15 10 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0xe4, 0xa2, 0x64 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve", "+f32mm" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "fmmla z0.s, z1.s, z2.s" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0xf2, 0x1f, 0xd5 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "arm64", "cyclone" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "msr CPM_IOACC_CTL_EL3, x0" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/cde-vec-pred.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x41, 0xfe, 0x00, 0xef ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "vptete.i8 eq, q0, q0" 11 | -------------------------------------------------------------------------------- /tests/MC/Mips/test_elm_msa64.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x78, 0xb8, 0xfc, 0xd9 ] 5 | arch: "CS_ARCH_MIPS" 6 | options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "copy_s.d $19, $w31[0]" 11 | -------------------------------------------------------------------------------- /arch/ARC/ARCModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dmitry Sibirtsev , 2024 */ 3 | 4 | #ifndef CS_ARC_MODULE_H 5 | #define CS_ARC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err ARC_global_init(cs_struct *ud); 10 | cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8r-unsupported-sysreg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x03,0x20,0x1c,0xd5 == msr TTBR0_EL2, x3 4 | 0x03,0x20,0x3c,0xd5 == mrs x3, TTBR0_EL2 5 | 0x03,0x21,0x1c,0xd5 == msr VTTBR_EL2, x3 6 | 0x03,0x21,0x3c,0xd5 == mrs x3, VTTBR_EL2 7 | 0x03,0x26,0x1c,0xd5 == msr VSTTBR_EL2, x3 8 | 0x03,0x26,0x3c,0xd5 == mrs x3, VSTTBR_EL2 9 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x00, 0x90, 0xc0 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sme2" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "addha za0.s, p0/m, p0/m, z0.s" 11 | -------------------------------------------------------------------------------- /tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xe0, 0x02, 0x38, 0xd5 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64-none-linux-gnu", "v8.3a" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "mrs x0, ID_ISAR6_EL1" 11 | -------------------------------------------------------------------------------- /tests/MC/Mips/test_elm_insert_msa64.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x79, 0x39, 0xe8, 0x59 ] 5 | arch: "CS_ARCH_MIPS" 6 | options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "insert.d $w1[1], $sp" 11 | -------------------------------------------------------------------------------- /arch/ARM/ARMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_ARM_MODULE_H 5 | #define CS_ARM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err ARM_global_init(cs_struct *ud); 10 | cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/EVM/EVMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_EVM_MODULE_H 5 | #define CS_EVM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err EVM_global_init(cs_struct *ud); 10 | cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/X86/X86Module.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_X86_MODULE_H 5 | #define CS_X86_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err X86_global_init(cs_struct *ud); 10 | cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/RISCV/insn-riscv64.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_RISCV, CS_MODE_RISCV64, None 2 | 0x13,0x04,0xa8,0x7a = addi s0, a6, 0x7aa 3 | 0x1b,0x8e,0xaa,0x2a = addiw t3, s5, 0x2aa 4 | 0x2f,0xbe,0xaa,0x0a = amoswap.d.rl t3, a0, (s5) 5 | 0x3b,0x00,0x31,0x02 = mulw zero, sp, gp 6 | 0x53,0xa0,0x31,0xd0 = fcvt.s.lu ft0, gp, rdn 7 | 0x53,0x81,0x01,0xf2 = fmv.d.x ft2, gp 8 | 9 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0x20, 0x02, 0x44 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64", "sve2p1" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "cmla z0.b, z1.b, z2.b, #0" 11 | -------------------------------------------------------------------------------- /tests/MC/Mips/valid-micromips32r3.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x43, 0x60, 0x00, 0xad ] 5 | arch: "CS_ARCH_MIPS" 6 | options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3", "CS_MODE_MICRO" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "bposge32 350" 11 | -------------------------------------------------------------------------------- /.reuse/templates/license-template.jinja2: -------------------------------------------------------------------------------- 1 | {% for copyright_line in copyright_lines %} 2 | {{ copyright_line }} 3 | {% endfor %} 4 | {% for contributor_line in contributor_lines %} 5 | SPDX-FileContributor: {{ contributor_line }} 6 | {% endfor %} 7 | {% for expression in spdx_expressions %} 8 | SPDX-License-Identifier: {{ expression }} 9 | {% endfor %} 10 | -------------------------------------------------------------------------------- /MCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_MCDISASSEMBLER_H 5 | #define CS_MCDISASSEMBLER_H 6 | 7 | typedef enum DecodeStatus { 8 | MCDisassembler_Fail = 0, 9 | MCDisassembler_SoftFail = 1, 10 | MCDisassembler_Success = 3, 11 | } DecodeStatus; 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /arch/BPF/BPFModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CS_BPF_MODULE_H 5 | #define CS_BPF_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err BPF_global_init(cs_struct *ud); 10 | cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/M68K/M68KModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_M68K_MODULE_H 5 | #define CS_M68K_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err M68K_global_init(cs_struct *ud); 10 | cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ldp-postind.predictable.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+fp-armv8'] 4 | 0xe3 0x0f 0x80 0xa8 == stp x3, x3, [sp], #0 5 | 0xa5 0x98 0xc1 0x6c == ldp d5, d6, [x5], #24 6 | 0xff 0xff 0x80 0xa8 == stp xzr, xzr, [sp], #8 7 | -------------------------------------------------------------------------------- /tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x20, 0x80, 0x9f, 0x84 ] 5 | arch: "CS_ARCH_AARCH64" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "aarch64-none-linux-gnu", "sme-fa64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]" 11 | -------------------------------------------------------------------------------- /tests/MC/ARM/udf-thumb-2.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0xde, 0xf0, 0xf7, 0x00, 0xa0 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "udf #0" 11 | - 12 | asm_text: "udf.w #0" 13 | -------------------------------------------------------------------------------- /arch/HPPA/HPPAModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dmitry Sibirtsev , 2023 */ 3 | 4 | #ifndef CS_HPPA_MODULE_H 5 | #define CS_HPPA_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err HPPA_global_init(cs_struct *ud); 10 | cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /contrib/m68k_instruction_tbl_gen/Makefile: -------------------------------------------------------------------------------- 1 | CC=gcc 2 | ODIR=obj 3 | TBL_GEN=tbl_gen 4 | INC_FILE=../../arch/M68K/M68KInstructionTable.inc 5 | 6 | gen_inc: $(TBL_GEN) 7 | ./$(TBL_GEN) > $(INC_FILE) 8 | 9 | tbl_gen: M68KInstructionTblGen.c 10 | $(CC) -O3 M68KInstructionTblGen.c -o $(TBL_GEN) 11 | 12 | .PHONY: clean 13 | 14 | clean: 15 | rm $(TBL_GEN) 16 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-trace.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0x20,0x12,0x18,0xd5 = msr TRFCR_EL1, x0 3 | 0x20,0x12,0x1c,0xd5 = msr TRFCR_EL2, x0 4 | 0x20,0x12,0x1d,0xd5 = msr TRFCR_EL12, x0 5 | 0x20,0x12,0x38,0xd5 = mrs x0, TRFCR_EL1 6 | 0x20,0x12,0x3c,0xd5 = mrs x0, TRFCR_EL2 7 | 0x20,0x12,0x3d,0xd5 = mrs x0, TRFCR_EL12 8 | 0x5f,0x22,0x03,0xd5 = tsb csync 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.5a-ssbs.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+ssbs', 'mattr=+v8.5a', 'mattr=+v8r', 'mattr=-ssbs'] 4 | 0x3f 0x41 0x03 0xd5 == msr SSBS, #1 5 | 0xc3 0x42 0x1b 0xd5 == msr SSBS, x3 6 | 0xc2 0x42 0x3b 0xd5 == mrs x2, SSBS 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-e3dse.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x20,0xc1,0x3e,0xd5 == mrs x0, VDISR_EL3 5 | 0x20,0xc1,0x1e,0xd5 == msr VDISR_EL3, x0 6 | 0x60,0x52,0x3e,0xd5 == mrs x0, VSESR_EL3 7 | 0x60,0x52,0x1e,0xd5 == msr VSESR_EL3, x0 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ldp-preind.predictable.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+fp-armv8'] 4 | 0xe3 0x0f 0x80 0xa9 == stp x3, x3, [sp, #0]! 5 | 0xa5 0x98 0xc1 0x6d == ldp d5, d6, [x5, #24]! 6 | 0xff 0xff 0x80 0xa9 == stp xzr, xzr, [sp, #8]! 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-sxtl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0xa4,0x08,0x0f == sshll v0.8h, v1.8b, #0 4 | 0x20,0xa4,0x10,0x0f == sshll v0.4s, v1.4h, #0 5 | 0x20,0xa4,0x20,0x0f == sshll v0.2d, v1.2s, #0 6 | 0x20,0xa4,0x08,0x4f == sshll2 v0.8h, v1.16b, #0 7 | 0x20,0xa4,0x10,0x4f == sshll2 v0.4s, v1.8h, #0 8 | 0x20,0xa4,0x20,0x4f == sshll2 v0.2d, v1.4s, #0 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-uxtl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0xa4,0x08,0x2f == ushll v0.8h, v1.8b, #0 4 | 0x20,0xa4,0x10,0x2f == ushll v0.4s, v1.4h, #0 5 | 0x20,0xa4,0x20,0x2f == ushll v0.2d, v1.2s, #0 6 | 0x20,0xa4,0x08,0x6f == ushll2 v0.8h, v1.16b, #0 7 | 0x20,0xa4,0x10,0x6f == ushll2 v0.4s, v1.8h, #0 8 | 0x20,0xa4,0x20,0x6f == ushll2 v0.2d, v1.4s, #0 9 | -------------------------------------------------------------------------------- /arch/M680X/M680XModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_M680X_MODULE_H 5 | #define CS_M680X_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err M680X_global_init(cs_struct *ud); 10 | cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/PowerPC/PPCModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_POWERPC_MODULE_H 5 | #define CS_POWERPC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err PPC_global_init(cs_struct *ud); 10 | cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/Sparc/SparcModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_SPARC_MODULE_H 5 | #define CS_SPARC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err Sparc_global_init(cs_struct *ud); 10 | cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/XCore/XCoreModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_XCORE_MODULE_H 5 | #define CS_XCORE_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err XCore_global_init(cs_struct *ud); 10 | cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /pkgconfig.mk: -------------------------------------------------------------------------------- 1 | # Package version of Capstone for Makefile. 2 | # To be used to generate capstone.pc for pkg-config 3 | 4 | # version major & minor 5 | PKG_MAJOR = 6 6 | PKG_MINOR = 0 7 | 8 | # version bugfix level. Example: PKG_EXTRA = 1 9 | PKG_EXTRA = 0 10 | 11 | # version tag. Examples: rc1, b2, post1 - or just comment out for no tag 12 | PKG_TAG = alpha5 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-e3dse.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x20,0xc1,0x3e,0xd5 == mrs x0, VDISR_EL3 5 | 0x20,0xc1,0x1e,0xd5 == msr VDISR_EL3, x0 6 | 0x60,0x52,0x3e,0xd5 == mrs x0, VSESR_EL3 7 | 0x60,0x52,0x1e,0xd5 == msr VSESR_EL3, x0 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9a-rme.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xa0,0x60,0x3e,0xd5 == mrs x0, MFAR_EL3 4 | 0xc0,0x21,0x3e,0xd5 == mrs x0, GPCCR_EL3 5 | 0x80,0x21,0x3e,0xd5 == mrs x0, GPTBR_EL3 6 | 0x60,0x84,0x0e,0xd5 == tlbi rpaos, x0 7 | 0xe0,0x84,0x0e,0xd5 == tlbi rpalos, x0 8 | 0x9f,0x81,0x0e,0xd5 == tlbi paallos 9 | 0x9f,0x87,0x0e,0xd5 == tlbi paall 10 | -------------------------------------------------------------------------------- /tests/MC/ARM/arm-thumb-trustzone.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xff, 0xf7, 0x00, 0x80, 0x0c, 0xbf ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "smc #15" 11 | - 12 | asm_text: "ite eq" 13 | -------------------------------------------------------------------------------- /arch/RISCV/RISCVModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Shawn Chang , HardenedLinux@2018 */ 3 | 4 | #ifndef CS_RISCV_MODULE_H 5 | #define CS_RISCV_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err RISCV_global_init(cs_struct *ud); 10 | cs_err RISCV_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /functions.mk: -------------------------------------------------------------------------------- 1 | # Capstone Disassembly Engine 2 | # Common functions used by Makefile & tests/Makefile 3 | 4 | define compile 5 | $(ifeq ($(MACOS_UNIVERSAL),no), 6 | @$(CC) -MM -MP -MT $@ -MT $(@:.o=.d) $(CFLAGS) $< > $(@:.o=.d) 7 | ) 8 | ${CC} ${CFLAGS} -c $< -o $@ 9 | endef 10 | 11 | 12 | define log 13 | @printf " %-7s %s\n" "$(1)" "$(2)" 14 | endef 15 | 16 | -------------------------------------------------------------------------------- /suite/MC/AArch64/movt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc04f03e0 == zt0, z0 3 | 0xc04f33ff == zt0[3, mul vl], z31 4 | 0xc04c03e0 == x0, zt0[0] 5 | 0xc04c53f5 == x21, zt0[40] 6 | 0xc04c63f7 == x23, zt0[48] 7 | 0xc04c73ff == xzr, zt0[56] 8 | 0xc04e03e0 == zt0[0], x0 9 | 0xc04e53f5 == zt0[40], x21 10 | 0xc04e63f7 == zt0[48], x23 11 | 0xc04e73ff == zt0[56], xzr 12 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb-hints.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x00,0xbf = nop 3 | 0x10,0xbf = yield 4 | 0x20,0xbf = wfe 5 | 0x30,0xbf = wfi 6 | 0x40,0xbf = sev 7 | 0xbf,0xf3,0x5f,0x8f = dmb sy 8 | 0xbf,0xf3,0x5f,0x8f = dmb sy 9 | 0xbf,0xf3,0x4f,0x8f = dsb sy 10 | 0xbf,0xf3,0x4f,0x8f = dsb sy 11 | 0xbf,0xf3,0x6f,0x8f = isb sy 12 | 0xbf,0xf3,0x6f,0x8f = isb sy 13 | -------------------------------------------------------------------------------- /tests/MC/ARM/arm-trustzone.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x7f, 0x00, 0x60, 0xe1, 0x70, 0x00, 0x60, 0x01 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "smc #15" 11 | - 12 | asm_text: "smceq #0" 13 | -------------------------------------------------------------------------------- /tests/MC/ARM/dot-req.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x05, 0xb0, 0xa0, 0xe1, 0x06, 0x10, 0xa0, 0xe1 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "mov r11, r5" 11 | - 12 | asm_text: "mov r1, r6" 13 | -------------------------------------------------------------------------------- /arch/AArch64/AArch64Module.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_AARCH64_MODULE_H 5 | #define CS_AARCH64_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err AArch64_global_init(cs_struct *ud); 10 | cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/MOS65XX/MOS65XXModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Sebastian Macke , 2018 */ 3 | 4 | #ifndef CS_MOS65XX_MODULE_H 5 | #define CS_MOS65XX_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err MOS65XX_global_init(cs_struct *ud); 10 | cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/SystemZ/SystemZModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_SYSTEMZ_MODULE_H 5 | #define CS_SYSTEMZ_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err SystemZ_global_init(cs_struct *ud); 10 | cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-compact-unwind-fallback.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x03 == compact encoding: 0x03000000 5 | 0x03 == compact encoding: 0x03000000 6 | 0x03 == compact encoding: 0x03000000 7 | 0x03 == compact encoding: 0x03000000 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-leaf-compact-unwind.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x02 == compact encoding: 0x02000000 5 | 0x02 == compact encoding: 0x02009000 6 | 0x02 == compact encoding: 0x0200400f 7 | 0x02 == compact encoding: 0x02021010 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-hdbss.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x40,0x23,0x3c,0xd5 == mrs x0, HDBSSBR_EL2 5 | 0x40,0x23,0x1c,0xd5 == msr HDBSSBR_EL2, x0 6 | 0x60,0x23,0x3c,0xd5 == mrs x0, HDBSSPROD_EL2 7 | 0x60,0x23,0x1c,0xd5 == msr HDBSSPROD_EL2, x0 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-hdbss.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x40,0x23,0x3c,0xd5 == mrs x0, HDBSSBR_EL2 5 | 0x40,0x23,0x1c,0xd5 == msr HDBSSBR_EL2, x0 6 | 0x60,0x23,0x3c,0xd5 == mrs x0, HDBSSPROD_EL2 7 | 0x60,0x23,0x1c,0xd5 == msr HDBSSPROD_EL2, x0 8 | -------------------------------------------------------------------------------- /suite/MC/ARM/ldrd-strd-gnu-arm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xd0,0x02,0xea,0xe1 = ldrd r0, r1, [r10, #0x20]! 3 | 0xd0,0x02,0xca,0xe0 = ldrd r0, r1, [r10], #0x20 4 | 0xd0,0x02,0xca,0xe1 = ldrd r0, r1, [r10, #0x20] 5 | 0xf0,0x02,0xea,0xe1 = strd r0, r1, [r10, #0x20]! 6 | 0xf0,0x02,0xca,0xe0 = strd r0, r1, [r10], #0x20 7 | 0xf0,0x02,0xca,0xe1 = strd r0, r1, [r10, #0x20] 8 | -------------------------------------------------------------------------------- /tests/MC/ARM/idiv.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x12, 0xf3, 0x11, 0xe7, 0x14, 0xf5, 0x33, 0xe7 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "sdiv r1, r2, r3" 11 | - 12 | asm_text: "udiv r3, r4, r5" 13 | -------------------------------------------------------------------------------- /tests/MC/ARM/neon-vswp.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x02, 0x10, 0xb2, 0xf3, 0x44, 0x20, 0xb2, 0xf3 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_ARM" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "vswp d1, d2" 11 | - 12 | asm_text: "vswp q1, q2" 13 | -------------------------------------------------------------------------------- /arch/EVM/EVMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_EVMDISASSEMBLER_H 5 | #define CS_EVMDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, 11 | void *info); 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /arch/WASM/WASMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #include 5 | 6 | void WASM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 7 | const char *WASM_insn_name(csh handle, unsigned int id); 8 | const char *WASM_group_name(csh handle, unsigned int id); 9 | const char *WASM_kind_name(unsigned int id); 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-trace.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0x12,0x18,0xd5 == msr TRFCR_EL1, x0 4 | 0x20,0x12,0x1c,0xd5 == msr TRFCR_EL2, x0 5 | 0x20,0x12,0x1d,0xd5 == msr TRFCR_EL12, x0 6 | 0x20,0x12,0x38,0xd5 == mrs x0, TRFCR_EL1 7 | 0x20,0x12,0x3c,0xd5 == mrs x0, TRFCR_EL2 8 | 0x20,0x12,0x3d,0xd5 == mrs x0, TRFCR_EL12 9 | 0x5f,0x22,0x03,0xd5 == tsb csync 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-hacdbs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x80,0x23,0x3c,0xd5 == mrs x0, HACDBSBR_EL2 5 | 0x80,0x23,0x1c,0xd5 == msr HACDBSBR_EL2, x0 6 | 0xa0,0x23,0x3c,0xd5 == mrs x0, HACDBSCONS_EL2 7 | 0xa0,0x23,0x1c,0xd5 == msr HACDBSCONS_EL2, x0 8 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9.5a-hacdbs.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = [] 4 | 0x80,0x23,0x3c,0xd5 == mrs x0, HACDBSBR_EL2 5 | 0x80,0x23,0x1c,0xd5 == msr HACDBSBR_EL2, x0 6 | 0xa0,0x23,0x3c,0xd5 == mrs x0, HACDBSCONS_EL2 7 | 0xa0,0x23,0x1c,0xd5 == msr HACDBSCONS_EL2, x0 8 | -------------------------------------------------------------------------------- /arch/WASM/WASMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifndef CS_WASMDISASSEMBLER_H 5 | #define CS_WASMDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool WASM_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, 11 | void *info); 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /tests/MC/ARM/idiv-thumb.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x92, 0xfb, 0xf3, 0xf1, 0xb4, 0xfb, 0xf5, 0xf3 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "sdiv r1, r2, r3" 11 | - 12 | asm_text: "udiv r3, r4, r5" 13 | -------------------------------------------------------------------------------- /arch/Mips/MipsModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Giovanni Dante Grazioli, deroad , 2024 */ 3 | 4 | #ifndef CS_MIPS_MODULE_H 5 | #define CS_MIPS_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err Mips_global_init(cs_struct *ud); 10 | cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif // CS_MIPS_MODULE_H 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-optional-hash.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 0xff,0x83,0x00,0x91 = add sp, sp, #32 3 | 0x83,0x00,0x50,0xb1 = adds x3, x4, #1024, lsl #12 4 | 0x5f,0x60,0x23,0x8b = add sp, x2, x3 5 | 0x01,0x10,0x28,0x1e = fmov s1, #0.12500000 6 | 0xbf,0x33,0x03,0xd5 = dmb osh 7 | 0xe3,0x09,0x42,0x28 = ldnp w3, w2, [x15, #16] 8 | 0x95,0x78,0xa5,0xf8 = prfm pstl3strm, [x4, x5, lsl #3] 9 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_elm_insert.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 3 | 0x79,0x03,0xed,0xd9 == insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9] 4 | 0x79,0x22,0x2d,0x19 == insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19] 5 | 0x79,0x32,0x7a,0x19 == insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19] 6 | -------------------------------------------------------------------------------- /arch/Sparc/SparcDisassemblerExtension.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Rot127 , 2025 */ 3 | 4 | #include "SparcDisassemblerExtension.h" 5 | #include "SparcMCTargetDesc.h" 6 | 7 | bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature) 8 | { 9 | if (feature == Sparc_FeatureV9) { 10 | return mode & CS_MODE_V9; 11 | } 12 | return true; 13 | } 14 | -------------------------------------------------------------------------------- /arch/Sparc/SparcDisassemblerExtension.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Rot127 , 2025 */ 3 | 4 | #ifndef CS_SPARC_DISASSEMBLER_EXTENSION_H 5 | #define CS_SPARC_DISASSEMBLER_EXTENSION_H 6 | 7 | #include 8 | 9 | bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature); 10 | 11 | #endif // CS_SPARC_DISASSEMBLER_EXTENSION_H 12 | -------------------------------------------------------------------------------- /arch/TMS320C64x/TMS320C64xModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_TMS320C64X_MODULE_H 5 | #define CS_TMS320C64X_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err TMS320C64x_global_init(cs_struct *ud); 10 | cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.1a-pan.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+v8.1a'] 4 | 0x9f,0x40,0x00,0xd5 == msr PAN, #0 5 | 0x9f,0x41,0x00,0xd5 == msr PAN, #1 6 | 0x9f,0x4f,0x00,0xd5 == msr PAN, #15 7 | 0x65,0x42,0x18,0xd5 == msr PAN, x5 8 | 0x6d,0x42,0x38,0xd5 == mrs x13, PAN 9 | -------------------------------------------------------------------------------- /suite/MC/AArch64/basic-a64-unpredictable.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | # This regression test file is new. The option flags could not be determined. 3 | # LLVM uses the following mattr = ['mattr=+fp-armv8'] 4 | 0xe3 0x0f 0x40 0xa9 == ^ 5 | 0xe2 0x8b 0x41 0x69 == ^ 6 | 0x82 0x88 0x40 0x2d == ^ 7 | 0xe3 0x0f 0xc0 0xa8 == ^ 8 | 0xe2 0x8b 0xc1 0x68 == ^ 9 | 0x82 0x88 0xc0 0x2c == ^ 10 | -------------------------------------------------------------------------------- /arch/Alpha/AlphaModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dmitry Sibirtsev , 2023 */ 3 | 4 | #ifndef CAPSTONE_ALPHAMODULE_H 5 | #define CAPSTONE_ALPHAMODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err ALPHA_global_init(cs_struct *ud); 10 | cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif // CAPSTONE_ALPHAMODULE_H 13 | -------------------------------------------------------------------------------- /include/windowsce/intrin.h: -------------------------------------------------------------------------------- 1 | 2 | #if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && \ 3 | !defined(__INTRIN_H_) && !defined(_INTRIN) 4 | #define _STDINT 5 | 6 | #ifdef _M_ARM 7 | #include 8 | #if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) 9 | #include 10 | #endif 11 | #endif // _M_ARM 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/basic-arm-instructions-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x59,0xf0,0x7f,0xf5 = dmb ishld 3 | 0x51,0xf0,0x7f,0xf5 = dmb oshld 4 | 0x55,0xf0,0x7f,0xf5 = dmb nshld 5 | 0x5d,0xf0,0x7f,0xf5 = dmb ld 6 | 0x49,0xf0,0x7f,0xf5 = dsb ishld 7 | 0x41,0xf0,0x7f,0xf5 = dsb oshld 8 | 0x45,0xf0,0x7f,0xf5 = dsb nshld 9 | 0x4d,0xf0,0x7f,0xf5 = dsb ld 10 | 0x05,0xf0,0x20,0xe3 = sevl 11 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/f-conv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xbe,0x10,0x1d,0x01 = ffint.s.w $fs6, $fa5 3 | 0xb5,0x05,0x1b,0x01 = ftint.w.s $ft13, $ft5 4 | 0x10,0x06,0x1a,0x01 = ftintrm.w.s $ft8, $ft8 5 | 0xee,0x47,0x1a,0x01 = ftintrp.w.s $ft6, $fs7 6 | 0xa4,0x87,0x1a,0x01 = ftintrz.w.s $fa4, $fs5 7 | 0x24,0xc6,0x1a,0x01 = ftintrne.w.s $fa4, $ft9 8 | 0x25,0x46,0x1e,0x01 = frint.s $fa5, $ft9 9 | -------------------------------------------------------------------------------- /tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xd2, 0xe8, 0x7f, 0x01, 0xc6, 0xe8, 0x73, 0x45 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "ldrexd r0, r1, [r2]" 11 | - 12 | asm_text: "strexd r3, r4, r5, [r6]" 13 | -------------------------------------------------------------------------------- /arch/HPPA/HPPADisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dmitry Sibirtsev , 2023 */ 3 | 4 | #ifndef CS_HPPA_DISASSEMBLER_H 5 | #define CS_HPPA_DISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, 11 | void *info); 12 | 13 | #endif -------------------------------------------------------------------------------- /arch/SystemZ/SystemZDisassemblerExtension.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Rot127 , 2022-2023 */ 3 | 4 | #ifndef CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H 5 | #define CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H 6 | 7 | #include 8 | 9 | bool SystemZ_getFeatureBits(unsigned int mode, unsigned int feature); 10 | 11 | #endif // CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H 12 | -------------------------------------------------------------------------------- /arch/Xtensa/XtensaDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By billow , 2024 */ 3 | 4 | #ifndef XTENSA_DISASSEMBLER_H 5 | #define XTENSA_DISASSEMBLER_H 6 | 7 | #include "../../MCDisassembler.h" 8 | 9 | DecodeStatus Xtensa_LLVM_getInstruction(MCInst *MI, uint16_t *Size, 10 | const uint8_t *Bytes, 11 | unsigned BytesSize, uint64_t Address); 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/clrm-asm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0x9f,0xe8,0x0f,0x00 = clrm {r0, r1, r2, r3} 3 | 0x9f,0xe8,0x1e,0x00 = clrm {r1, r2, r3, r4} 4 | 0x9f,0xe8,0xff,0xdf = clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr} 5 | 0x9f,0xe8,0x00,0xc0 = clrm {lr, apsr} 6 | 0x9f,0xe8,0x03,0x80 = clrm {r0, r1, apsr} 7 | 0x9f,0xe8,0x1f,0xc0 = clrm {r0, r1, r2, r3, r4, lr, apsr} 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/sllwil.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xad,0x3a,0x08,0x77 = xvsllwil.h.b $xr13, $xr21, 6 3 | 0xb4,0x43,0x08,0x77 = xvsllwil.w.h $xr20, $xr29, 0 4 | 0x83,0xe2,0x08,0x77 = xvsllwil.d.w $xr3, $xr20, 0x18 5 | 0xef,0x39,0x0c,0x77 = xvsllwil.hu.bu $xr15, $xr15, 6 6 | 0xb6,0x43,0x0c,0x77 = xvsllwil.wu.hu $xr22, $xr29, 0 7 | 0xa3,0xfc,0x0c,0x77 = xvsllwil.du.wu $xr3, $xr5, 0x1f 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ssrln.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x98,0x90,0xfc,0x74 = xvssrln.b.h $xr24, $xr4, $xr4 3 | 0xe5,0x01,0xfd,0x74 = xvssrln.h.w $xr5, $xr15, $xr0 4 | 0x20,0xfb,0xfd,0x74 = xvssrln.w.d $xr0, $xr25, $xr30 5 | 0x3a,0xe9,0x04,0x75 = xvssrln.bu.h $xr26, $xr9, $xr26 6 | 0x87,0x06,0x05,0x75 = xvssrln.hu.w $xr7, $xr20, $xr1 7 | 0xaf,0xd1,0x05,0x75 = xvssrln.wu.d $xr15, $xr13, $xr20 8 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x0a, 0x31, 0xd5, 0x80, 0x08, 0x31, 0xd5 ] 5 | arch: "CS_ARCH_ARCH" 6 | options: [ "arm64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "mrs x0, TRCRSR" 11 | - 12 | asm_text: "mrs x0, TRCEXTINSELR" 13 | -------------------------------------------------------------------------------- /.editorconfig: -------------------------------------------------------------------------------- 1 | root = true 2 | 3 | [*] 4 | end_of_line = lf 5 | insert_final_newline = true 6 | 7 | [*.{py,pyx,pxd}] 8 | indent_style = space 9 | indent_size = 4 10 | 11 | # Follow Linux kernel coding style 12 | [*.{c,h,cpp,hpp,inc}] 13 | indent_style = tab 14 | indent_size = 8 15 | 16 | # OCaml bindings 17 | [*.ml] 18 | indent_style = tab 19 | indent_size = 4 20 | 21 | [Makefile] 22 | indent_style = tab 23 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ssran.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x91,0x84,0xfe,0x74 = xvssran.b.h $xr17, $xr4, $xr1 3 | 0x9c,0x37,0xff,0x74 = xvssran.h.w $xr28, $xr28, $xr13 4 | 0x35,0xfc,0xff,0x74 = xvssran.w.d $xr21, $xr1, $xr31 5 | 0x83,0xe1,0x06,0x75 = xvssran.bu.h $xr3, $xr12, $xr24 6 | 0x19,0x07,0x07,0x75 = xvssran.hu.w $xr25, $xr24, $xr1 7 | 0xde,0xa9,0x07,0x75 = xvssran.wu.d $xr30, $xr14, $xr10 8 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x00, 0x0a, 0x31, 0xd5, 0x80, 0x08, 0x31, 0xd5 ] 5 | arch: "CS_ARCH_ARCH" 6 | options: [ "arm64" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "mrs x0, TRCRSR" 11 | - 12 | asm_text: "mrs x0, TRCEXTINSELR" 13 | -------------------------------------------------------------------------------- /arch/BPF/BPFInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CS_BPFINSTPRINTER_H 5 | #define CS_BPFINSTPRINTER_H 6 | 7 | #include 8 | 9 | #include "../../MCInst.h" 10 | #include "../../SStream.h" 11 | 12 | struct SStream; 13 | 14 | void BPF_printInst(MCInst *MI, struct SStream *O, void *Info); 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /arch/EVM/EVMInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_EVMINSTPRINTER_H 5 | #define CS_EVMINSTPRINTER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCInst.h" 9 | #include "../../SStream.h" 10 | #include "../../cs_priv.h" 11 | 12 | struct SStream; 13 | 14 | void EVM_printInst(MCInst *MI, struct SStream *O, void *Info); 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-prfm-slc.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x66,0x00,0x80,0xf9 == prfm pldslckeep, [x3] 4 | 0x67,0x00,0x80,0xf9 == prfm pldslcstrm, [x3] 5 | 0x6e,0x00,0x80,0xf9 == prfm plislckeep, [x3] 6 | 0x6f,0x00,0x80,0xf9 == prfm plislcstrm, [x3] 7 | 0x76,0x00,0x80,0xf9 == prfm pstslckeep, [x3] 8 | 0x77,0x00,0x80,0xf9 == prfm pstslcstrm, [x3] 9 | 0x66,0x68,0xa5,0xf8 == prfm pldslckeep, [x3, x5] 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-abs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x1d,0xbb,0xe0,0x5e == abs d29, d24 4 | 0x1d,0x17,0xd4,0x7e == fabd h29, h24, h20 5 | 0x1d,0xd7,0xb4,0x7e == fabd s29, s24, s20 6 | 0x1d,0xd7,0xf4,0x7e == fabd d29, d24, d20 7 | 0xd3,0x79,0x20,0x5e == sqabs b19, b14 8 | 0xf5,0x79,0x60,0x5e == sqabs h21, h15 9 | 0x94,0x79,0xa0,0x5e == sqabs s20, s12 10 | 0x92,0x79,0xe0,0x5e == sqabs d18, d12 11 | -------------------------------------------------------------------------------- /suite/MC/ARM/implicit-it-generation.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x01,0x30 = adds r0, #1 3 | 0x10,0xf1,0x01,0x00 = adds.w r0, r0, #1 4 | 0x80,0xe0 = b #0x100 5 | 0x00,0xf0,0x00,0xbc = b.w #0x800 6 | 0x02,0xd0 = beq #4 7 | 0x00,0xf0,0x80,0x80 = beq.w #0x100 8 | 0x02,0xe0 = b #4 9 | 0x80,0xe0 = b #0x100 10 | 0x00,0xf0,0x00,0xbc = b.w #0x800 11 | 0x02,0xdc = bgt #4 12 | 0x00,0xf3,0x80,0x80 = bgt.w #0x100 13 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ssrarn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa7,0x81,0x02,0x75 = xvssrarn.b.h $xr7, $xr13, $xr0 3 | 0x56,0x38,0x03,0x75 = xvssrarn.h.w $xr22, $xr2, $xr14 4 | 0xed,0xc0,0x03,0x75 = xvssrarn.w.d $xr13, $xr7, $xr16 5 | 0x84,0x89,0x0a,0x75 = xvssrarn.bu.h $xr4, $xr12, $xr2 6 | 0x0f,0x0f,0x0b,0x75 = xvssrarn.hu.w $xr15, $xr24, $xr3 7 | 0x3e,0xa1,0x0b,0x75 = xvssrarn.wu.d $xr30, $xr9, $xr8 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/ssrlrn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x88,0xca,0x00,0x75 = xvssrlrn.b.h $xr8, $xr20, $xr18 3 | 0xa2,0x4d,0x01,0x75 = xvssrlrn.h.w $xr2, $xr13, $xr19 4 | 0xf8,0x94,0x01,0x75 = xvssrlrn.w.d $xr24, $xr7, $xr5 5 | 0xef,0xca,0x08,0x75 = xvssrlrn.bu.h $xr15, $xr23, $xr18 6 | 0xd6,0x41,0x09,0x75 = xvssrlrn.hu.w $xr22, $xr14, $xr16 7 | 0x94,0x97,0x09,0x75 = xvssrlrn.wu.d $xr20, $xr28, $xr5 8 | -------------------------------------------------------------------------------- /bindings/vb6/Project1.vbw: -------------------------------------------------------------------------------- 1 | Form1 = 110, 110, 1233, 906, , 88, 88, 1116, 749, C 2 | mCapStone = 22, 22, 1050, 683, 3 | mx86 = 88, 88, 1040, 757, 4 | mMisc = 66, 66, 1094, 727, 5 | CInstruction = 182, 182, 1070, 558, 6 | CInstDetails = 132, 132, 1084, 801, 7 | CDisassembler = 44, 44, 1229, 809, 8 | CX86Inst = 154, 154, 1106, 823, 9 | CX86Operand = 176, 176, 1128, 845, 10 | CX86OpMem = 198, 198, 1150, 867, 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-pfar.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xa0,0x60,0x38,0xd5 == mrs x0, PFAR_EL1 4 | 0xa0,0x60,0x18,0xd5 == msr PFAR_EL1, x0 5 | 0xa0,0x60,0x3c,0xd5 == mrs x0, PFAR_EL2 6 | 0xa0,0x60,0x1c,0xd5 == msr PFAR_EL2, x0 7 | 0xa0,0x60,0x3d,0xd5 == mrs x0, PFAR_EL12 8 | 0xa0,0x60,0x1d,0xd5 == msr PFAR_EL12, x0 9 | 0xa0,0x60,0x3e,0xd5 == mrs x0, MFAR_EL3 10 | 0xa0,0x60,0x1e,0xd5 == msr MFAR_EL3, x0 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-pfar.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xa0,0x60,0x38,0xd5 == mrs x0, PFAR_EL1 4 | 0xa0,0x60,0x18,0xd5 == msr PFAR_EL1, x0 5 | 0xa0,0x60,0x3c,0xd5 == mrs x0, PFAR_EL2 6 | 0xa0,0x60,0x1c,0xd5 == msr PFAR_EL2, x0 7 | 0xa0,0x60,0x3d,0xd5 == mrs x0, PFAR_EL12 8 | 0xa0,0x60,0x1d,0xd5 == msr PFAR_EL12, x0 9 | 0xa0,0x60,0x3e,0xd5 == mrs x0, MFAR_EL3 10 | 0xa0,0x60,0x1e,0xd5 == msr MFAR_EL3, x0 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/st2q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xe4600000 == {z0.q, z1.q}, p0, [x0, x0, lsl #4] 3 | 0xe4751555 == {z21.q, z22.q}, p5, [x10, x21, lsl #4] 4 | 0xe4680db7 == {z23.q, z24.q}, p3, [x13, x8, lsl #4] 5 | 0xe4400000 == {z0.q, z1.q}, p0, [x0] 6 | 0xe4451555 == {z21.q, z22.q}, p5, [x10, #10, mul vl] 7 | 0xe4480db7 == {z23.q, z24.q}, p3, [x13, #-16, mul vl] 8 | 0xe44f1fff == {z31.q, z0.q}, p7, [sp, #-2, mul vl] 9 | -------------------------------------------------------------------------------- /tests/MC/ARM/cps.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x61, 0xb6, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x00, 0x81 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "cpsie f" 11 | - 12 | asm_text: "cpsie i, #3" 13 | - 14 | asm_text: "cps #0" 15 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm_addrmode3.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 3 | 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 4 | 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 5 | 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 6 | 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 7 | 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 8 | 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 9 | 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4 10 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumbv7em.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None 2 | 0x80,0xf3,0x00,0x84 = msr apsr_g, r0 3 | 0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0 4 | 0x80,0xf3,0x01,0x84 = msr iapsr_g, r0 5 | 0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0 6 | 0x80,0xf3,0x02,0x84 = msr eapsr_g, r0 7 | 0x80,0xf3,0x02,0x8c = msr eapsr_nzcvqg, r0 8 | 0x80,0xf3,0x03,0x84 = msr xpsr_g, r0 9 | 0x80,0xf3,0x03,0x8c = msr xpsr_nzcvqg, r0 10 | -------------------------------------------------------------------------------- /suite/MC/HPPA/branch11.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None 2 | 0xe8,0x3f,0x1f,0x75 = bl 0xffffffffffffffc0,r1 3 | 0xe8,0x3f,0x1f,0x6f = bl,n 0xffffffffffffffbc,r1 4 | 0xe8,0x41,0x40,0x00 = blr r1,rp 5 | 0xe8,0x41,0x40,0x02 = blr,n r1,rp 6 | 0xe8,0x41,0xc0,0x00 = bv r1(rp) 7 | 0xe8,0x41,0xc0,0x02 = bv,n r1(rp) 8 | 0xe8,0x5f,0x3f,0x45 = gate 0xffffffffffffffa8,rp 9 | 0xe8,0x5f,0x3f,0x3f = gate,n 0xffffffffffffffa4,rp -------------------------------------------------------------------------------- /suite/MC/LoongArch/ffint.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa3,0x00,0x9e,0x76 = xvffint.s.w $xr3, $xr5 3 | 0x65,0x0a,0x9e,0x76 = xvffint.d.l $xr5, $xr19 4 | 0x83,0x07,0x9e,0x76 = xvffint.s.wu $xr3, $xr28 5 | 0xbf,0x0f,0x9e,0x76 = xvffint.d.lu $xr31, $xr29 6 | 0xe2,0x10,0x9e,0x76 = xvffintl.d.w $xr2, $xr7 7 | 0x87,0x17,0x9e,0x76 = xvffinth.d.w $xr7, $xr28 8 | 0x6a,0x0f,0x48,0x75 = xvffint.s.l $xr10, $xr27, $xr3 9 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/lit_config/README.md: -------------------------------------------------------------------------------- 1 | 5 | 6 | lit configurations for MC regression test generation. 7 | As an introduction see: https://medium.com/@mshockwave/using-llvm-lit-out-of-tree-5cddada85a78 ([archived](https://web.archive.org/web/20240421091240/https://medium.com/@mshockwave/using-llvm-lit-out-of-tree-5cddada85a78)) 8 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/x86-misc.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x04,0x04,0x5c,0x00 = x86mfflag $a0, 1 3 | 0x24,0x04,0x5c,0x00 = x86mtflag $a0, 1 4 | 0x04,0x74,0x00,0x00 = x86mftop $a0 5 | 0x20,0x70,0x00,0x00 = x86mttop 1 6 | 0x09,0x80,0x00,0x00 = x86inctop 7 | 0x29,0x80,0x00,0x00 = x86dectop 8 | 0x08,0x80,0x00,0x00 = x86settm 9 | 0x28,0x80,0x00,0x00 = x86clrtm 10 | 0x24,0x04,0x58,0x00 = x86settag $a0, 1, 1 11 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa4,0x1c,0x08,0x00 = lb $a1, 8($a0) 3 | 0xc4,0x14,0x08,0x00 = lbu $a2, 8($a0) 4 | 0x44,0x3c,0x08,0x00 = lh $v0, 8($a0) 5 | 0x82,0x34,0x08,0x00 = lhu $a0, 8($v0) 6 | 0xc5,0xfc,0x04,0x00 = lw $a2, 4($a1) 7 | 0xa4,0x18,0x08,0x00 = sb $a1, 8($a0) 8 | 0x44,0x38,0x08,0x00 = sh $v0, 8($a0) 9 | 0xa6,0xf8,0x04,0x00 = sw $a1, 4($a2) 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ld2q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xa4a08000 == {z0.q, z1.q}, p0/z, [x0, x0, lsl #4] 3 | 0xa4b59555 == {z21.q, z22.q}, p5/z, [x10, x21, lsl #4] 4 | 0xa4a88db7 == {z23.q, z24.q}, p3/z, [x13, x8, lsl #4] 5 | 0xa490e000 == {z0.q, z1.q}, p0/z, [x0] 6 | 0xa495f555 == {z21.q, z22.q}, p5/z, [x10, #10, mul vl] 7 | 0xa498edb7 == {z23.q, z24.q}, p3/z, [x13, #-16, mul vl] 8 | 0xa49fffff == {z31.q, z0.q}, p7/z, [sp, #-2, mul vl] 9 | -------------------------------------------------------------------------------- /suite/MC/ARC/br_arc.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None 2 | 3 | 0x3d,0xa,0x12,0x0 = brlt %r2, 0, 60 4 | 0x91,0xa,0x4,0x91 = brlo %r10, %r4, -112 5 | 0x2d,0xa,0x40,0x0 = breq %r2, %r1, 44 6 | 0xf1,0x8,0x11,0x80 = brne %r0, 0, -16 7 | 0x27,0xa,0x5,0x2 = brhs %r2, %r8, 38 8 | 0x30,0x1,0x2,0x0 = bne 304 9 | 0xc,0x1,0x1,0x0 = beq 268 10 | 0xa0,0x1,0xd,0x0 = bhi 416 11 | 0xbd,0x7,0xcf,0xff = b -68 12 | 0x0,0x0,0x9e,0x0 = b 4096 13 | -------------------------------------------------------------------------------- /tests/MC/ARM/mve-vmov-pair.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x07, 0xec, 0x0e, 0x8f, 0x11, 0xec, 0x14, 0x6f ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "vmov lr, r7, q4[2], q4[0]" 11 | - 12 | asm_text: "vmov q3[3], q3[1], r4, r1" 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/bfmlslb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64e8a1b7 == z23.s, z13.h, z8.h 3 | 0x64e0a000 == z0.s, z0.h, z0.h 4 | 0x64f5a155 == z21.s, z10.h, z21.h 5 | 0x64e8a1b7 == z23.s, z13.h, z8.h 6 | 0x64ffa3ff == z31.s, z31.h, z31.h 7 | 0x64e869b7 == z23.s, z13.h, z0.h[3] 8 | 0x64e06000 == z0.s, z0.h, z0.h[0] 9 | 0x64f56155 == z21.s, z10.h, z5.h[4] 10 | 0x64e869b7 == z23.s, z13.h, z0.h[3] 11 | 0x64ff6bff == z31.s, z31.h, z7.h[7] 12 | -------------------------------------------------------------------------------- /suite/MC/AArch64/bfmlslt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64e8a5b7 == z23.s, z13.h, z8.h 3 | 0x64e0a400 == z0.s, z0.h, z0.h 4 | 0x64f5a555 == z21.s, z10.h, z21.h 5 | 0x64e8a5b7 == z23.s, z13.h, z8.h 6 | 0x64ffa7ff == z31.s, z31.h, z31.h 7 | 0x64e86db7 == z23.s, z13.h, z0.h[3] 8 | 0x64e06400 == z0.s, z0.h, z0.h[0] 9 | 0x64f56555 == z21.s, z10.h, z5.h[4] 10 | 0x64e86db7 == z23.s, z13.h, z0.h[3] 11 | 0x64ff6fff == z31.s, z31.h, z7.h[7] 12 | -------------------------------------------------------------------------------- /tests/MC/PowerPC/ppc64_encoding_p9vector_only_offset_branch_syntax_noregname_little_endian_64_pwr9.txt.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0x66, 0x1b, 0xc0, 0x7c ] 5 | arch: "CS_ARCH_PPC" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PWR9" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "mtvsrdd 6, 0, 3" 11 | -------------------------------------------------------------------------------- /arch/LoongArch/LoongArchModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Jiajie Chen , 2024 */ 3 | /* Yanglin Xun <1109673069@qq.com>, 2024 */ 4 | 5 | #ifndef CS_LOONGARCH_MODULE_H 6 | #define CS_LOONGARCH_MODULE_H 7 | 8 | #include "../../utils.h" 9 | 10 | cs_err LoongArch_global_init(cs_struct *ud); 11 | cs_err LoongArch_option(cs_struct *handle, cs_opt_type type, size_t value); 12 | 13 | #endif // CS_LOONGARCH_MODULE_H 14 | -------------------------------------------------------------------------------- /arch/Mips/MipsDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_MIPSDISASSEMBLER_H 5 | #define CS_MIPSDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCInst.h" 9 | #include "../../MCRegisterInfo.h" 10 | 11 | void Mips_init(MCRegisterInfo *MRI); 12 | 13 | bool Mips_getFeatureBits(unsigned int mode, unsigned int feature); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /cstool/getopt.h: -------------------------------------------------------------------------------- 1 | #ifndef CSTOOL_GETOPT_H 2 | #define CSTOOL_GETOPT_H 3 | 4 | // global 5 | extern int opterr, /* if error message should be printed */ 6 | optind, /* index into parent argv vector */ 7 | optopt, /* character checked for validity */ 8 | optreset; /* reset getopt */ 9 | 10 | extern const char *optarg; /* argument associated with option */ 11 | 12 | int getopt(int nargc, char *const nargv[], const char *ostr); 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /packages/freebsd/ports/devel/capstone/pkg-plist: -------------------------------------------------------------------------------- 1 | include/capstone/arm.h 2 | include/capstone/arm64.h 3 | include/capstone/capstone.h 4 | include/capstone/mips.h 5 | include/capstone/ppc.h 6 | include/capstone/sparc.h 7 | include/capstone/systemz.h 8 | include/capstone/x86.h 9 | include/capstone/xcore.h 10 | include/capstone/platform.h 11 | lib/libcapstone.a 12 | lib/libcapstone.so 13 | libdata/pkgconfig/capstone.pc 14 | @dirrmtry include/capstone 15 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fcvtzs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc121e000 == {z0.s, z1.s}, {z0.s, z1.s} 3 | 0xc121e154 == {z20.s, z21.s}, {z10.s, z11.s} 4 | 0xc121e196 == {z22.s, z23.s}, {z12.s, z13.s} 5 | 0xc121e3de == {z30.s, z31.s}, {z30.s, z31.s} 6 | 0xc131e000 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc131e114 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc131e194 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc131e39c == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fcvtzu.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc121e020 == {z0.s, z1.s}, {z0.s, z1.s} 3 | 0xc121e174 == {z20.s, z21.s}, {z10.s, z11.s} 4 | 0xc121e1b6 == {z22.s, z23.s}, {z12.s, z13.s} 5 | 0xc121e3fe == {z30.s, z31.s}, {z30.s, z31.s} 6 | 0xc131e020 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc131e134 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc131e1b4 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc131e3bc == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-saturating-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0x4c,0x22,0x5e == sqshl b0, b1, b2 4 | 0x6a,0x4d,0x6c,0x5e == sqshl h10, h11, h12 5 | 0xb4,0x4e,0xa2,0x5e == sqshl s20, s21, s2 6 | 0xf1,0x4f,0xe8,0x5e == sqshl d17, d31, d8 7 | 0x20,0x4c,0x22,0x7e == uqshl b0, b1, b2 8 | 0x6a,0x4d,0x6c,0x7e == uqshl h10, h11, h12 9 | 0xb4,0x4e,0xa2,0x7e == uqshl s20, s21, s2 10 | 0xf1,0x4f,0xe8,0x7e == uqshl d17, d31, d8 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/scvtf.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc122e000 == {z0.s, z1.s}, {z0.s, z1.s} 3 | 0xc122e154 == {z20.s, z21.s}, {z10.s, z11.s} 4 | 0xc122e196 == {z22.s, z23.s}, {z12.s, z13.s} 5 | 0xc122e3de == {z30.s, z31.s}, {z30.s, z31.s} 6 | 0xc132e000 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc132e114 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc132e194 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc132e39c == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ucvtf.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc122e020 == {z0.s, z1.s}, {z0.s, z1.s} 3 | 0xc122e174 == {z20.s, z21.s}, {z10.s, z11.s} 4 | 0xc122e1b6 == {z22.s, z23.s}, {z12.s, z13.s} 5 | 0xc122e3fe == {z30.s, z31.s}, {z30.s, z31.s} 6 | 0xc132e020 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc132e134 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc132e1b4 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc132e3bc == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/arm-alu.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x91,0x14,0x37,0x00 = armadd.w $a0, $a1, 1 3 | 0x91,0x94,0x37,0x00 = armsub.w $a0, $a1, 1 4 | 0x91,0x14,0x38,0x00 = armadc.w $a0, $a1, 1 5 | 0x91,0x94,0x38,0x00 = armsbc.w $a0, $a1, 1 6 | 0x91,0x14,0x39,0x00 = armand.w $a0, $a1, 1 7 | 0x91,0x94,0x39,0x00 = armor.w $a0, $a1, 1 8 | 0x91,0x14,0x3a,0x00 = armxor.w $a0, $a1, 1 9 | 0x9c,0xc4,0x3f,0x00 = armnot.w $a0, 1 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-shift-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x83,0x00,0x00,0x38 = sll $a0, $v1, 7 3 | 0x65,0x00,0x10,0x10 = sllv $v0, $v1, $a1 4 | 0x83,0x00,0x80,0x38 = sra $a0, $v1, 7 5 | 0x65,0x00,0x90,0x10 = srav $v0, $v1, $a1 6 | 0x83,0x00,0x40,0x38 = srl $a0, $v1, 7 7 | 0x65,0x00,0x50,0x10 = srlv $v0, $v1, $a1 8 | 0x26,0x01,0xc0,0x38 = rotr $t1, $a2, 7 9 | 0xc7,0x00,0xd0,0x48 = rotrv $t1, $a2, $a3 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ld1w_q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xa5008000 == {z0.q}, p0/z, [x0, x0, lsl #2] 3 | 0xa5159555 == {z21.q}, p5/z, [x10, x21, lsl #2] 4 | 0xa5088db7 == {z23.q}, p3/z, [x13, x8, lsl #2] 5 | 0xa5088db7 == z23.q, p3/z, [x13, x8, lsl #2] 6 | 0xa5102000 == {z0.q}, p0/z, [x0] 7 | 0xa5153555 == {z21.q}, p5/z, [x10, #5, mul vl] 8 | 0xa5182db7 == {z23.q}, p3/z, [x13, #-8, mul vl] 9 | 0xa51f3fff == {z31.q}, p7/z, [sp, #-1, mul vl] 10 | -------------------------------------------------------------------------------- /suite/MC/ARM/armv8.2a-dotprod-a32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x12,0x0d,0x21,0xfc = vudot.u8 d0, d1, d2 3 | 0x02,0x0d,0x21,0xfc = vsdot.s8 d0, d1, d2 4 | 0x58,0x0d,0x22,0xfc = vudot.u8 q0, q1, q4 5 | 0x48,0x0d,0x22,0xfc = vsdot.s8 q0, q1, q4 6 | 0x12,0x0d,0x21,0xfe = vudot.u8 d0, d1, d2[0] 7 | 0x22,0x0d,0x21,0xfe = vsdot.s8 d0, d1, d2[1] 8 | 0x54,0x0d,0x22,0xfe = vudot.u8 q0, q1, d4[0] 9 | 0x64,0x0d,0x22,0xfe = vsdot.s8 q0, q1, d4[1] 10 | -------------------------------------------------------------------------------- /suite/MC/ARM/armv8.2a-dotprod-t32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x21,0xfc,0x12,0x0d = vudot.u8 d0, d1, d2 3 | 0x21,0xfc,0x02,0x0d = vsdot.s8 d0, d1, d2 4 | 0x22,0xfc,0x58,0x0d = vudot.u8 q0, q1, q4 5 | 0x22,0xfc,0x48,0x0d = vsdot.s8 q0, q1, q4 6 | 0x21,0xfe,0x12,0x0d = vudot.u8 d0, d1, d2[0] 7 | 0x21,0xfe,0x22,0x0d = vsdot.s8 d0, d1, d2[1] 8 | 0x22,0xfe,0x54,0x0d = vudot.u8 q0, q1, d4[0] 9 | 0x22,0xfe,0x64,0x0d = vsdot.s8 q0, q1, d4[1] 10 | -------------------------------------------------------------------------------- /suite/MC/ARM/armv8a-fpmul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x91,0x08,0x20,0xfc = vfmal.f16 d0, s1, s2 3 | 0x91,0x08,0xa0,0xfc = vfmsl.f16 d0, s1, s2 4 | 0x52,0x08,0x21,0xfc = vfmal.f16 q0, d1, d2 5 | 0x52,0x08,0xa1,0xfc = vfmsl.f16 q0, d1, d2 6 | 0x99,0x08,0x00,0xfe = vfmal.f16 d0, s1, s2[1] 7 | 0x99,0x08,0x10,0xfe = vfmsl.f16 d0, s1, s2[1] 8 | 0x7a,0x08,0x01,0xfe = vfmal.f16 q0, d1, d2[3] 9 | 0x7a,0x08,0x11,0xfe = vfmsl.f16 q0, d1, d2[3] 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x1c,0xa4,0x00,0x08 = lb $a1, 8($a0) 3 | 0x14,0xc4,0x00,0x08 = lbu $a2, 8($a0) 4 | 0x3c,0x44,0x00,0x08 = lh $v0, 8($a0) 5 | 0x34,0x82,0x00,0x08 = lhu $a0, 8($v0) 6 | 0xfc,0xc5,0x00,0x04 = lw $a2, 4($a1) 7 | 0x18,0xa4,0x00,0x08 = sb $a1, 8($a0) 8 | 0x38,0x44,0x00,0x08 = sh $v0, 8($a0) 9 | 0xf8,0xa6,0x00,0x04 = sw $a1, 4($a2) 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_i10.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 3 | 0x7b,0x06,0x32,0x07 == ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07] 4 | 0x7b,0x29,0xcd,0x07 == ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07] 5 | 0x7b,0x4f,0x66,0x07 == ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07] 6 | 0x7b,0x7a,0x66,0xc7 == ldi.d $w27, -180 # encoding: [0x7b,0x7a,0x66,0xc7] 7 | -------------------------------------------------------------------------------- /suite/auto-sync/src/autosync/Tests/test_header.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2024 Rot127 2 | // SPDX-License-Identifier: BSD-3 3 | 4 | 5 | // Include the whole file 6 | // generated content begin 7 | // generated content end 8 | 9 | // Include only a part of the file. 10 | // generated content begin 11 | // generated content end 12 | 13 | -------------------------------------------------------------------------------- /tests/MC/ARM/bfloat16-t32.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xb6, 0xff, 0x46, 0x16, 0x18, 0xbf, 0xf3, 0xee, 0xe1, 0x09 ] 5 | arch: "CS_ARCH_ARM" 6 | options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "vcvt.bf16.f32 d1, q3" 11 | - 12 | asm_text: "it ne" 13 | - 14 | asm_text: "vcvtt.bf16.f32 s1, s3" 15 | -------------------------------------------------------------------------------- /tests/unit/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | enable_testing() 4 | set(UNIT_TEST_SOURCES sstream.c utils.c) 5 | include_directories(include) 6 | 7 | foreach(TSRC ${UNIT_TEST_SOURCES}) 8 | string(REGEX REPLACE ".c$" "" TBIN ${TSRC}) 9 | add_executable(${TBIN} "${TESTS_UNIT_DIR}/${TSRC}") 10 | target_link_libraries(${TBIN} PRIVATE capstone) 11 | add_test(NAME "unit_${TBIN}" COMMAND ${TBIN}) 12 | endforeach() 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/frinta.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc1ace000 == {z0.s - z1.s}, {z0.s - z1.s} 3 | 0xc1ace154 == {z20.s - z21.s}, {z10.s - z11.s} 4 | 0xc1ace196 == {z22.s - z23.s}, {z12.s - z13.s} 5 | 0xc1ace3de == {z30.s - z31.s}, {z30.s - z31.s} 6 | 0xc1bce000 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc1bce114 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc1bce194 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc1bce39c == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/frintm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc1aae000 == {z0.s - z1.s}, {z0.s - z1.s} 3 | 0xc1aae154 == {z20.s - z21.s}, {z10.s - z11.s} 4 | 0xc1aae196 == {z22.s - z23.s}, {z12.s - z13.s} 5 | 0xc1aae3de == {z30.s - z31.s}, {z30.s - z31.s} 6 | 0xc1bae000 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc1bae114 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc1bae194 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc1bae39c == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/frintn.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc1a8e000 == {z0.s - z1.s}, {z0.s - z1.s} 3 | 0xc1a8e154 == {z20.s - z21.s}, {z10.s - z11.s} 4 | 0xc1a8e196 == {z22.s - z23.s}, {z12.s - z13.s} 5 | 0xc1a8e3de == {z30.s - z31.s}, {z30.s - z31.s} 6 | 0xc1b8e000 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc1b8e114 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc1b8e194 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc1b8e39c == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/frintp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xc1a9e000 == {z0.s - z1.s}, {z0.s - z1.s} 3 | 0xc1a9e154 == {z20.s - z21.s}, {z10.s - z11.s} 4 | 0xc1a9e196 == {z22.s - z23.s}, {z12.s - z13.s} 5 | 0xc1a9e3de == {z30.s - z31.s}, {z30.s - z31.s} 6 | 0xc1b9e000 == {z0.s - z3.s}, {z0.s - z3.s} 7 | 0xc1b9e114 == {z20.s - z23.s}, {z8.s - z11.s} 8 | 0xc1b9e194 == {z20.s - z23.s}, {z12.s - z15.s} 9 | 0xc1b9e39c == {z28.s - z31.s}, {z28.s - z31.s} 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ptrue.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x25607810 == pn8.h 3 | 0x25607815 == pn13.h 4 | 0x25607817 == pn15.h 5 | 0x25607811 == pn9.h 6 | 0x25a07810 == pn8.s 7 | 0x25a07815 == pn13.s 8 | 0x25a07817 == pn15.s 9 | 0x25a07811 == pn9.s 10 | 0x25e07810 == pn8.d 11 | 0x25e07815 == pn13.d 12 | 0x25e07817 == pn15.d 13 | 0x25e07811 == pn9.d 14 | 0x25207810 == pn8.b 15 | 0x25207815 == pn13.b 16 | 0x25207817 == pn15.b 17 | 0x25207811 == pn9.b 18 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/bit-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x78,0x5f,0x17,0x00 = sll.w $s1, $s4, $s0 3 | 0x3f,0x9e,0x17,0x00 = srl.w $s8, $t5, $a3 4 | 0x8c,0x2b,0x18,0x00 = sra.w $t0, $s5, $a6 5 | 0x41,0x4b,0x1b,0x00 = rotr.w $ra, $s3, $t6 6 | 0x5a,0x82,0x40,0x00 = slli.w $s3, $t6, 0 7 | 0xca,0xf9,0x44,0x00 = srli.w $a6, $t2, 0x1e 8 | 0x28,0xe2,0x48,0x00 = srai.w $a4, $t5, 0x18 9 | 0x97,0xde,0x4c,0x00 = rotri.w $s0, $t8, 0x17 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_elm_insve.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 3 | 0x79,0x43,0x4e,0x59 == insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59] 4 | 0x79,0x62,0x16,0x19 == insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19] 5 | 0x79,0x72,0x68,0x19 == insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19] 6 | 0x79,0x78,0x90,0xd9 == insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9] 7 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-extract-narrow.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xd3,0x29,0x21,0x7e == sqxtun b19, h14 4 | 0xf5,0x29,0x61,0x7e == sqxtun h21, s15 5 | 0x94,0x29,0xa1,0x7e == sqxtun s20, d12 6 | 0x52,0x4a,0x21,0x5e == sqxtn b18, h18 7 | 0x34,0x4a,0x61,0x5e == sqxtn h20, s17 8 | 0xd3,0x49,0xa1,0x5e == sqxtn s19, d14 9 | 0x52,0x4a,0x21,0x7e == uqxtn b18, h18 10 | 0x34,0x4a,0x61,0x7e == uqxtn h20, s17 11 | 0xd3,0x49,0xa1,0x7e == uqxtn s19, d14 12 | -------------------------------------------------------------------------------- /suite/MC/ARM/mve-reductions-fp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None 2 | 0xee,0xfe,0x86,0xef = vminnmv.f16 lr, q3 3 | 0xee,0xee,0x82,0xef = vminnmv.f32 lr, q1 4 | 0xec,0xfe,0x80,0xef = vminnmav.f16 lr, q0 5 | 0xec,0xee,0x86,0xef = vminnmav.f32 lr, q3 6 | 0xee,0xfe,0x02,0xef = vmaxnmv.f16 lr, q1 7 | 0xee,0xee,0x02,0xaf = vmaxnmv.f32 r10, q1 8 | 0xec,0xfe,0x0c,0x0f = vmaxnmav.f16 r0, q6 9 | 0xec,0xee,0x0e,0xef = vmaxnmav.f32 lr, q7 10 | -------------------------------------------------------------------------------- /tests/integration/compat_header/src/main.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2024 Rot127 2 | // SPDX-License-Identifier: BSD-3.0-Clause 3 | 4 | #include "compat.h" 5 | #include 6 | 7 | int main() 8 | { 9 | if (arm64() != 0) { 10 | printf("Failed the arm64 compatibility header test.\n"); 11 | return -1; 12 | } 13 | if (sysz() != 0) { 14 | printf("Failed the sysz compatibility header test.\n"); 15 | return -1; 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /bindings/python/capstone/evm.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .evm_const import * 6 | 7 | # define the API 8 | class CsEvm(ctypes.Structure): 9 | _fields_ = ( 10 | ('pop', ctypes.c_byte), 11 | ('push', ctypes.c_byte), 12 | ('fee', ctypes.c_uint), 13 | ) 14 | 15 | def get_arch_info(a): 16 | return (a.pop, a.push, a.fee) 17 | 18 | -------------------------------------------------------------------------------- /bindings/python/cstest_py/pyproject.toml: -------------------------------------------------------------------------------- 1 | # Copyright © 2024 Rot127 2 | # SPDX-License-Identifier: BSD-3 3 | 4 | [project] 5 | name = "cstest_py" 6 | version = "0.1.0" 7 | dependencies = [ 8 | "pyyaml >= 6.0.2", 9 | "capstone >= 5.0.0", 10 | ] 11 | requires-python = ">= 3.8" 12 | 13 | [tool.setuptools] 14 | packages = ["cstest_py"] 15 | package-dir = { "" = "src" } 16 | 17 | [project.scripts] 18 | cstest_py = "cstest_py.cstest:main" 19 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.9a-prfm-slc.txt.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x66,0x00,0x80,0xf9 == prfm pldslckeep, [x3] 4 | 0x67,0x00,0x80,0xf9 == prfm pldslcstrm, [x3] 5 | 0x6e,0x00,0x80,0xf9 == prfm plislckeep, [x3] 6 | 0x6f,0x00,0x80,0xf9 == prfm plislcstrm, [x3] 7 | 0x76,0x00,0x80,0xf9 == prfm pstslckeep, [x3] 8 | 0x77,0x00,0x80,0xf9 == prfm pstslcstrm, [x3] 9 | 0x06,0x00,0x00,0xd8 == prfm pldslckeep, #0 10 | 0x66,0x68,0xa5,0xf8 == prfm pldslckeep, [x3, x5] 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0x20,0x5c,0x22,0x5e == sqrshl b0, b1, b2 4 | 0x6a,0x5d,0x6c,0x5e == sqrshl h10, h11, h12 5 | 0xb4,0x5e,0xa2,0x5e == sqrshl s20, s21, s2 6 | 0xf1,0x5f,0xe8,0x5e == sqrshl d17, d31, d8 7 | 0x20,0x5c,0x22,0x7e == uqrshl b0, b1, b2 8 | 0x6a,0x5d,0x6c,0x7e == uqrshl h10, h11, h12 9 | 0xb4,0x5e,0xa2,0x7e == uqrshl s20, s21, s2 10 | 0xf1,0x5f,0xe8,0x7e == uqrshl d17, d31, d8 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/st3q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xe4a00000 == {z0.q, z1.q, z2.q}, p0, [x0, x0, lsl #4] 3 | 0xe4b51555 == {z21.q, z22.q, z23.q}, p5, [x10, x21, lsl #4] 4 | 0xe4a80db7 == {z23.q, z24.q, z25.q}, p3, [x13, x8, lsl #4] 5 | 0xe4800000 == {z0.q, z1.q, z2.q}, p0, [x0] 6 | 0xe4851555 == {z21.q, z22.q, z23.q}, p5, [x10, #15, mul vl] 7 | 0xe4880db7 == {z23.q, z24.q, z25.q}, p3, [x13, #-24, mul vl] 8 | 0xe48f1fff == {z31.q, z0.q, z1.q}, p7, [sp, #-3, mul vl] 9 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-ctrl-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x9f,0xc0,0x40,0x1a = call %g1+%i2 3 | 0x9f,0xc2,0x60,0x08 = call %o1+8 4 | 0x9f,0xc0,0x60,0x00 = call %g1 5 | 0x81,0xc0,0x40,0x1a = jmp %g1+%i2 6 | 0x81,0xc2,0x60,0x08 = jmp %o1+8 7 | 0x81,0xc0,0x60,0x00 = jmp %g1 8 | 0x85,0xc0,0x40,0x1a = jmpl %g1+%i2, %g2 9 | 0x85,0xc2,0x60,0x08 = jmpl %o1+8, %g2 10 | 0x85,0xc0,0x60,0x00 = jmpl %g1, %g2 11 | 0x81,0xcf,0xe0,0x08 = rett %i7+8 12 | -------------------------------------------------------------------------------- /suite/MC/Xtensa/shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN, None 2 | 0x20,0x17,0x74 = extui a1, a2, 7, 8 3 | 0x0,0xb,0x1 = sll a10, a11 4 | 0x10,0x51,0x11 = slli a5, a1, 15 5 | 0x30,0xc0,0xb1 = sra a12, a3 6 | 0x50,0x80,0x21 = srai a8, a5, 0 7 | 0x50,0x34,0x81 = src a3, a4, a5 8 | 0x70,0x60,0x91 = srl a6, a7 9 | 0x40,0x38,0x41 = srli a3, a4, 8 10 | 0x0,0x2e,0x40 = ssa8l a14 11 | 0x10,0x4f,0x40 = ssai 31 12 | 0x0,0x10,0x40 = ssl a0 13 | 0x0,0x2,0x40 = ssr a2 14 | -------------------------------------------------------------------------------- /suite/MC/AArch64/arm64-basic-a64-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xe5,0x40,0xd4,0x1a == crc32b w5, w7, w20 4 | 0xfc,0x47,0xde,0x1a == crc32h w28, wzr, w30 5 | 0x20,0x48,0xc2,0x1a == crc32w w0, w1, w2 6 | 0x27,0x4d,0xd4,0x9a == crc32x w7, w9, x20 7 | 0xa9,0x50,0xc4,0x1a == crc32cb w9, w5, w4 8 | 0x2d,0x56,0xd9,0x1a == crc32ch w13, w17, w25 9 | 0x7f,0x58,0xc5,0x1a == crc32cw wzr, w3, w5 10 | 0x12,0x5e,0xdf,0x9a == crc32cx w18, w16, xzr 11 | -------------------------------------------------------------------------------- /suite/MC/AArch64/dot-req.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xe5,0x03,0x0b,0xaa == mov x5, x11 4 | 0xe1,0x03,0x06,0x2a == mov w1, w6 5 | 0xe1,0x03,0x06,0x2a == mov w1, w6 6 | 0x06,0xb8,0x31,0x0e == addv b6, v0.8b 7 | 0x85,0x04,0x0e,0x5e == mov h5, v4.h[3] 8 | 0x80,0x28,0x24,0x1e == fadd s0, s4, s4 9 | 0x62,0x40,0x60,0x1e == fmov d2, d3 10 | 0xe2,0x03,0xc0,0x3d == ldr q2, [sp] 11 | 0x20,0x1c,0xa1,0x0e == mov v0.8b, v1.8b 12 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/sat.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf6,0x28,0x24,0x77 = xvsat.b $xr22, $xr7, 2 3 | 0x03,0x54,0x24,0x77 = xvsat.h $xr3, $xr0, 5 4 | 0x09,0x82,0x24,0x77 = xvsat.w $xr9, $xr16, 0 5 | 0x03,0x05,0x25,0x77 = xvsat.d $xr3, $xr8, 1 6 | 0xc6,0x30,0x28,0x77 = xvsat.bu $xr6, $xr6, 4 7 | 0x2c,0x73,0x28,0x77 = xvsat.hu $xr12, $xr25, 0xc 8 | 0x34,0x8c,0x28,0x77 = xvsat.wu $xr20, $xr1, 3 9 | 0x85,0x1e,0x29,0x77 = xvsat.du $xr5, $xr20, 7 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-shift-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0x83,0x38,0x00 = sll $a0, $v1, 7 3 | 0x00,0x65,0x10,0x10 = sllv $v0, $v1, $a1 4 | 0x00,0x83,0x38,0x80 = sra $a0, $v1, 7 5 | 0x00,0x65,0x10,0x90 = srav $v0, $v1, $a1 6 | 0x00,0x83,0x38,0x40 = srl $a0, $v1, 7 7 | 0x00,0x65,0x10,0x50 = srlv $v0, $v1, $a1 8 | 0x01,0x26,0x38,0xc0 = rotr $t1, $a2, 7 9 | 0x00,0xc7,0x48,0xd0 = rotrv $t1, $a2, $a3 10 | -------------------------------------------------------------------------------- /tests/MC/Xtensa/memorder.s.yaml: -------------------------------------------------------------------------------- 1 | test_cases: 2 | - 3 | input: 4 | bytes: [ 0xd0, 0x20, 0x00 ] 5 | arch: "CS_ARCH_XTENSA" 6 | options: [ "xtensa" ] 7 | expected: 8 | insns: 9 | - 10 | asm_text: "extw" 11 | 12 | - 13 | input: 14 | bytes: [ 0xc0, 0x20, 0x00 ] 15 | arch: "CS_ARCH_XTENSA" 16 | options: [ "xtensa" ] 17 | expected: 18 | insns: 19 | - 20 | asm_text: "memw" 21 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_lsa.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 3 | 0x01,0x2a,0x40,0x05 == lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05] 4 | 0x01,0x2a,0x40,0x45 == lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45] 5 | 0x01,0x2a,0x40,0x85 == lsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x85] 6 | 0x01,0x2a,0x40,0xc5 == lsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xc5] 7 | -------------------------------------------------------------------------------- /arch/WASM/WASMInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifndef CS_WASMINSTPRINTER_H 5 | #define CS_WASMINSTPRINTER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCInst.h" 9 | #include "../../SStream.h" 10 | #include "../../cs_priv.h" 11 | 12 | struct SStream; 13 | 14 | void WASM_printInst(MCInst *MI, struct SStream *O, void *Info); 15 | void printOperand(MCInst *MI, unsigned OpNo, SStream *O); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /suite/MC/AArch64/ld3q.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0xa5208000 == {z0.q, z1.q, z2.q}, p0/z, [x0, x0, lsl #4] 3 | 0xa5359555 == {z21.q, z22.q, z23.q}, p5/z, [x10, x21, lsl #4] 4 | 0xa5288db7 == {z23.q, z24.q, z25.q}, p3/z, [x13, x8, lsl #4] 5 | 0xa510e000 == {z0.q, z1.q, z2.q}, p0/z, [x0] 6 | 0xa515f555 == {z21.q, z22.q, z23.q}, p5/z, [x10, #15, mul vl] 7 | 0xa518edb7 == {z23.q, z24.q, z25.q}, p3/z, [x13, #-24, mul vl] 8 | 0xa51fffff == {z31.q, z0.q, z1.q}, p7/z, [sp, #-3, mul vl] 9 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/crc.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xf8,0x08,0x24,0x00 = crc.w.b.w $s1, $a3, $tp 3 | 0x5f,0xc9,0x24,0x00 = crc.w.h.w $s8, $a6, $t6 4 | 0xdc,0x28,0x25,0x00 = crc.w.w.w $s5, $a2, $a6 5 | 0x7c,0xfd,0x25,0x00 = crc.w.d.w $s5, $a7, $s8 6 | 0x4f,0x0e,0x26,0x00 = crcc.w.b.w $t3, $t6, $sp 7 | 0xb5,0xcb,0x26,0x00 = crcc.w.h.w $r21, $s6, $t6 8 | 0xd1,0x35,0x27,0x00 = crcc.w.w.w $t5, $t2, $t1 9 | 0xbe,0xee,0x27,0x00 = crcc.w.d.w $s7, $r21, $s4 10 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/exth.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x4f,0xe1,0x9e,0x76 = xvexth.h.b $xr15, $xr10 3 | 0x7a,0xe5,0x9e,0x76 = xvexth.w.h $xr26, $xr11 4 | 0x62,0xeb,0x9e,0x76 = xvexth.d.w $xr2, $xr27 5 | 0x36,0xef,0x9e,0x76 = xvexth.q.d $xr22, $xr25 6 | 0xd5,0xf3,0x9e,0x76 = xvexth.hu.bu $xr21, $xr30 7 | 0x7c,0xf5,0x9e,0x76 = xvexth.wu.hu $xr28, $xr11 8 | 0x3b,0xfb,0x9e,0x76 = xvexth.du.wu $xr27, $xr25 9 | 0x90,0xff,0x9e,0x76 = xvexth.qu.du $xr16, $xr28 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/faddqv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64d0a000 == v0.2d, p0, z0.d 3 | 0x64d0b555 == v21.2d, p5, z10.d 4 | 0x64d0adb7 == v23.2d, p3, z13.d 5 | 0x64d0bfff == v31.2d, p7, z31.d 6 | 0x6450a000 == v0.8h, p0, z0.h 7 | 0x6450b555 == v21.8h, p5, z10.h 8 | 0x6450adb7 == v23.8h, p3, z13.h 9 | 0x6450bfff == v31.8h, p7, z31.h 10 | 0x6490a000 == v0.4s, p0, z0.s 11 | 0x6490b555 == v21.4s, p5, z10.s 12 | 0x6490adb7 == v23.4s, p3, z13.s 13 | 0x6490bfff == v31.4s, p7, z31.s 14 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fmaxqv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64d6a000 == v0.2d, p0, z0.d 3 | 0x64d6b555 == v21.2d, p5, z10.d 4 | 0x64d6adb7 == v23.2d, p3, z13.d 5 | 0x64d6bfff == v31.2d, p7, z31.d 6 | 0x6456a000 == v0.8h, p0, z0.h 7 | 0x6456b555 == v21.8h, p5, z10.h 8 | 0x6456adb7 == v23.8h, p3, z13.h 9 | 0x6456bfff == v31.8h, p7, z31.h 10 | 0x6496a000 == v0.4s, p0, z0.s 11 | 0x6496b555 == v21.4s, p5, z10.s 12 | 0x6496adb7 == v23.4s, p3, z13.s 13 | 0x6496bfff == v31.4s, p7, z31.s 14 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fminqv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64d7a000 == v0.2d, p0, z0.d 3 | 0x64d7b555 == v21.2d, p5, z10.d 4 | 0x64d7adb7 == v23.2d, p3, z13.d 5 | 0x64d7bfff == v31.2d, p7, z31.d 6 | 0x6457a000 == v0.8h, p0, z0.h 7 | 0x6457b555 == v21.8h, p5, z10.h 8 | 0x6457adb7 == v23.8h, p3, z13.h 9 | 0x6457bfff == v31.8h, p7, z31.h 10 | 0x6497a000 == v0.4s, p0, z0.s 11 | 0x6497b555 == v21.4s, p5, z10.s 12 | 0x6497adb7 == v23.4s, p3, z13.s 13 | 0x6497bfff == v31.4s, p7, z31.s 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/fconst.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x00,0x2a,0xb0,0xee = vmov.f32 s4, #2.000000e+00 3 | 0x00,0x2a,0xb7,0xee = vmov.f32 s4, #1.000000e+00 4 | 0x00,0x3b,0xb0,0xee = vmov.f64 d3, #2.000000e+00 5 | 0x00,0x3b,0xb7,0xee = vmov.f64 d3, #1.000000e+00 6 | 0x01,0x2a,0xf0,0x1e = vmovne.f32 s5, #2.125000e+00 7 | 0x00,0x2a,0xf2,0xce = vmovgt.f32 s5, #8.000000e+00 8 | 0x03,0x2b,0xb0,0xbe = vmovlt.f64 d2, #2.375000e+00 9 | 0x00,0x2b,0xb4,0xae = vmovge.f64 d2, #1.250000e-01 10 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/seq.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x83,0x4c,0x00,0x74 = xvseq.b $xr3, $xr4, $xr19 3 | 0xa0,0x96,0x00,0x74 = xvseq.h $xr0, $xr21, $xr5 4 | 0x06,0x4e,0x01,0x74 = xvseq.w $xr6, $xr16, $xr19 5 | 0xa8,0xb5,0x01,0x74 = xvseq.d $xr8, $xr13, $xr13 6 | 0x2c,0x03,0x80,0x76 = xvseqi.b $xr12, $xr25, 0 7 | 0x89,0xa8,0x80,0x76 = xvseqi.h $xr9, $xr4, 0xa 8 | 0x99,0x50,0x81,0x76 = xvseqi.w $xr25, $xr4, -0xc 9 | 0xeb,0x9c,0x81,0x76 = xvseqi.d $xr11, $xr7, 7 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fmaxnmqv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64d4a000 == v0.2d, p0, z0.d 3 | 0x64d4b555 == v21.2d, p5, z10.d 4 | 0x64d4adb7 == v23.2d, p3, z13.d 5 | 0x64d4bfff == v31.2d, p7, z31.d 6 | 0x6454a000 == v0.8h, p0, z0.h 7 | 0x6454b555 == v21.8h, p5, z10.h 8 | 0x6454adb7 == v23.8h, p3, z13.h 9 | 0x6454bfff == v31.8h, p7, z31.h 10 | 0x6494a000 == v0.4s, p0, z0.s 11 | 0x6494b555 == v21.4s, p5, z10.s 12 | 0x6494adb7 == v23.4s, p3, z13.s 13 | 0x6494bfff == v31.4s, p7, z31.s 14 | -------------------------------------------------------------------------------- /suite/MC/AArch64/fminnmqv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, None, None 2 | 0x64d5a000 == v0.2d, p0, z0.d 3 | 0x64d5b555 == v21.2d, p5, z10.d 4 | 0x64d5adb7 == v23.2d, p3, z13.d 5 | 0x64d5bfff == v31.2d, p7, z31.d 6 | 0x6455a000 == v0.8h, p0, z0.h 7 | 0x6455b555 == v21.8h, p5, z10.h 8 | 0x6455adb7 == v23.8h, p3, z13.h 9 | 0x6455bfff == v31.8h, p7, z31.h 10 | 0x6495a000 == v0.4s, p0, z0.s 11 | 0x6495b555 == v21.4s, p5, z10.s 12 | 0x6495adb7 == v23.4s, p3, z13.s 13 | 0x6495bfff == v31.4s, p7, z31.s 14 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/sra.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x4b,0x00,0xec,0x74 = xvsra.b $xr11, $xr2, $xr0 3 | 0x71,0x9b,0xec,0x74 = xvsra.h $xr17, $xr27, $xr6 4 | 0x8d,0x31,0xed,0x74 = xvsra.w $xr13, $xr12, $xr12 5 | 0xe6,0x85,0xed,0x74 = xvsra.d $xr6, $xr15, $xr1 6 | 0x50,0x2c,0x34,0x77 = xvsrai.b $xr16, $xr2, 3 7 | 0x6e,0x70,0x34,0x77 = xvsrai.h $xr14, $xr3, 0xc 8 | 0x51,0xd6,0x34,0x77 = xvsrai.w $xr17, $xr18, 0x15 9 | 0x8a,0x12,0x35,0x77 = xvsrai.d $xr10, $xr20, 4 10 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/srl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x14,0x77,0xea,0x74 = xvsrl.b $xr20, $xr24, $xr29 3 | 0x2b,0xfe,0xea,0x74 = xvsrl.h $xr11, $xr17, $xr31 4 | 0x42,0x21,0xeb,0x74 = xvsrl.w $xr2, $xr10, $xr8 5 | 0xcd,0xeb,0xeb,0x74 = xvsrl.d $xr13, $xr30, $xr26 6 | 0x9d,0x2c,0x30,0x77 = xvsrli.b $xr29, $xr4, 3 7 | 0xdc,0x71,0x30,0x77 = xvsrli.h $xr28, $xr14, 0xc 8 | 0x4c,0x9e,0x30,0x77 = xvsrli.w $xr12, $xr18, 7 9 | 0x80,0xb8,0x31,0x77 = xvsrli.d $xr0, $xr4, 0x2e 10 | -------------------------------------------------------------------------------- /arch/MOS65XX/MOS65XXDisassemblerInternals.h: -------------------------------------------------------------------------------- 1 | #ifndef CS_MOS65XXDISASSEMBLERINTERNALS_H 2 | #define CS_MOS65XXDISASSEMBLERINTERNALS_H 3 | 4 | #include "capstone/mos65xx.h" 5 | 6 | enum { 7 | MOS65XX_CPU_TYPE_6502, 8 | MOS65XX_CPU_TYPE_65C02, 9 | MOS65XX_CPU_TYPE_W65C02, 10 | MOS65XX_CPU_TYPE_65816, 11 | }; 12 | 13 | typedef struct mos65xx_info { 14 | const char *hex_prefix; 15 | unsigned cpu_type; 16 | unsigned long_m; 17 | unsigned long_x; 18 | 19 | } mos65xx_info; 20 | 21 | #endif 22 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv9a-rme.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xa0,0x60,0x1e,0xd5 == msr MFAR_EL3, x0 4 | 0xc0,0x21,0x1e,0xd5 == msr GPCCR_EL3, x0 5 | 0x80,0x21,0x1e,0xd5 == msr GPTBR_EL3, x0 6 | 0xa0,0x60,0x3e,0xd5 == mrs x0, MFAR_EL3 7 | 0xc0,0x21,0x3e,0xd5 == mrs x0, GPCCR_EL3 8 | 0x80,0x21,0x3e,0xd5 == mrs x0, GPTBR_EL3 9 | 0x60,0x84,0x0e,0xd5 == tlbi rpaos, x0 10 | 0xe0,0x84,0x0e,0xd5 == tlbi rpalos, x0 11 | 0x9f,0x81,0x0e,0xd5 == tlbi paallos 12 | 0x9f,0x87,0x0e,0xd5 == tlbi paall 13 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/arm-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x91,0x94,0x3a,0x00 = armsll.w $a0, $a1, 1 3 | 0x91,0x14,0x3b,0x00 = armsrl.w $a0, $a1, 1 4 | 0x91,0x94,0x3b,0x00 = armsra.w $a0, $a1, 1 5 | 0x91,0x14,0x3c,0x00 = armrotr.w $a0, $a1, 1 6 | 0x91,0x84,0x3c,0x00 = armslli.w $a0, 1, 1 7 | 0x91,0x04,0x3d,0x00 = armsrli.w $a0, 1, 1 8 | 0x91,0x84,0x3d,0x00 = armsrai.w $a0, 1, 1 9 | 0x91,0x04,0x3e,0x00 = armrotri.w $a0, 1, 1 10 | 0x9f,0xc4,0x3f,0x00 = armrrx.w $a0, 1 11 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/memory.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x18,0x55,0x00,0x28 = ld.b $s1, $a4, 0x15 3 | 0x47,0x42,0x41,0x28 = ld.h $a3, $t6, 0x50 4 | 0x52,0x73,0x81,0x28 = ld.w $t6, $s3, 0x5c 5 | 0xad,0x59,0x02,0x2a = ld.bu $t1, $t1, 0x96 6 | 0xb2,0x1b,0x43,0x2a = ld.hu $t6, $s6, 0xc6 7 | 0xe3,0x7c,0x01,0x29 = st.b $sp, $a3, 0x5f 8 | 0x19,0xea,0x41,0x29 = st.h $s2, $t4, 0x7a 9 | 0xad,0xbd,0x82,0x29 = st.w $t1, $t1, 0xaf 10 | 0x0a,0x5c,0xc0,0x2a = preld 0xa, $zero, 0x17 11 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/sll.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xa8,0x27,0xe8,0x74 = xvsll.b $xr8, $xr29, $xr9 3 | 0x95,0xf7,0xe8,0x74 = xvsll.h $xr21, $xr28, $xr29 4 | 0xd1,0x2b,0xe9,0x74 = xvsll.w $xr17, $xr30, $xr10 5 | 0xd3,0xe8,0xe9,0x74 = xvsll.d $xr19, $xr6, $xr26 6 | 0x59,0x27,0x2c,0x77 = xvslli.b $xr25, $xr26, 1 7 | 0x91,0x7b,0x2c,0x77 = xvslli.h $xr17, $xr28, 0xe 8 | 0xfa,0xf7,0x2c,0x77 = xvslli.w $xr26, $xr31, 0x1d 9 | 0x8a,0xbb,0x2d,0x77 = xvslli.d $xr10, $xr28, 0x2e 10 | -------------------------------------------------------------------------------- /suite/MC/README.md: -------------------------------------------------------------------------------- 1 | # Input files for fuzzing input 2 | 3 | These files were the legacy test files but replaced. 4 | No it only is consumed by `test_corpus3.py` to generate input cases for the fuzzer. 5 | 6 | ### Test file formatting 7 | 8 | **Format of input files:** 9 | ``` 10 | # ARCH, MODE, OPTION 11 | = 12 | ``` 13 | 14 | **Example** 15 | ``` 16 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 17 | 0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16 18 | ... 19 | ``` 20 | -------------------------------------------------------------------------------- /suite/MC/AArch64/armv8.4a-ras.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_AARCH64, 0, None 2 | 3 | 0xa0,0x54,0x18,0xd5 == msr ERXPFGCTL_EL1, x0 4 | 0xa0,0x54,0x38,0xd5 == mrs x0, ERXPFGCTL_EL1 5 | 0xc0,0x54,0x18,0xd5 == msr ERXPFGCDN_EL1, x0 6 | 0xc0,0x54,0x38,0xd5 == mrs x0, ERXPFGCDN_EL1 7 | 0x40,0x55,0x18,0xd5 == msr ERXMISC2_EL1, x0 8 | 0x40,0x55,0x38,0xd5 == mrs x0, ERXMISC2_EL1 9 | 0x60,0x55,0x18,0xd5 == msr ERXMISC3_EL1, x0 10 | 0x60,0x55,0x38,0xd5 == mrs x0, ERXMISC3_EL1 11 | 0x80,0x54,0x38,0xd5 == mrs x0, ERXPFGF_EL1 12 | -------------------------------------------------------------------------------- /suite/MC/BPF/classic-be.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_BPF, CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC, None 2 | 0x00,0x01,0x00,0x00,0x33,0x00,0x0c,0x11 = ldx 0x33000c11 3 | 0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00 = ld #len 4 | 0x00,0xa1,0x00,0x00,0x10,0x00,0x00,0x00 = ldx 4*([0x10000000]&0xf) 5 | 0x00,0x60,0x00,0x00,0x09,0x00,0x00,0x00 = ld m[0x9000000] 6 | 0x00,0x30,0x00,0x00,0x37,0x13,0x03,0x00 = ldb [0x37130300] 7 | 0x00,0x63,0x00,0x00,0x0f,0x00,0x30,0x00 = stx m[0xf003000] 8 | 0x00,0x84,0x00,0x00,0x00,0x00,0x00,0x00 = neg 9 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/avg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0xc5,0x57,0x64,0x74 = xvavg.b $xr5, $xr30, $xr21 3 | 0x32,0xd6,0x64,0x74 = xvavg.h $xr18, $xr17, $xr21 4 | 0xe3,0x52,0x65,0x74 = xvavg.w $xr3, $xr23, $xr20 5 | 0x1b,0xec,0x65,0x74 = xvavg.d $xr27, $xr0, $xr27 6 | 0x8b,0x40,0x66,0x74 = xvavg.bu $xr11, $xr4, $xr16 7 | 0x22,0xcc,0x66,0x74 = xvavg.hu $xr2, $xr1, $xr19 8 | 0x9b,0x6e,0x67,0x74 = xvavg.wu $xr27, $xr20, $xr27 9 | 0x97,0xf6,0x67,0x74 = xvavg.du $xr23, $xr20, $xr29 10 | -------------------------------------------------------------------------------- /suite/MC/LoongArch/div.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, None 2 | 0x29,0x23,0xe0,0x74 = xvdiv.b $xr9, $xr25, $xr8 3 | 0x32,0xec,0xe0,0x74 = xvdiv.h $xr18, $xr1, $xr27 4 | 0x45,0x6f,0xe1,0x74 = xvdiv.w $xr5, $xr26, $xr27 5 | 0x5b,0xb3,0xe1,0x74 = xvdiv.d $xr27, $xr26, $xr12 6 | 0xc0,0x7a,0xe4,0x74 = xvdiv.bu $xr0, $xr22, $xr30 7 | 0xff,0xe6,0xe4,0x74 = xvdiv.hu $xr31, $xr23, $xr25 8 | 0x21,0x1f,0xe5,0x74 = xvdiv.wu $xr1, $xr25, $xr7 9 | 0x27,0x9f,0xe5,0x74 = xvdiv.du $xr7, $xr25, $xr7 10 | --------------------------------------------------------------------------------