├── .ci-scripts ├── bits.tcl └── run-linter.py ├── .gitignore ├── .gitlab-ci.yml ├── .gitmodules ├── README.md ├── asm ├── Makefile └── user-sample.s ├── cpp-cpu-model ├── CMakeLists.txt ├── bin-crypto.h ├── bin-kernel.h ├── bin-matrix.h ├── bin2c.c ├── bpu.cc ├── bpu.h ├── cache.cc ├── cache.h ├── cpu.cc ├── cpu.h ├── termtest.cc ├── termtest.h ├── test.py ├── uart.cc └── uart.h ├── thinpad_top.srcs ├── constrs_1 │ └── new │ │ └── thinpad_top.xdc ├── sim_1 │ ├── imports │ │ ├── CFImemory64Mb_bottom.mem │ │ └── CFImemory64Mb_top.mem │ └── new │ │ ├── 28F640P30.v │ │ ├── clock.v │ │ ├── cpld_model.v │ │ ├── flag_sync_cpld.v │ │ ├── include │ │ ├── BankLib.h │ │ ├── CUIcommandData.h │ │ ├── TimingData.h │ │ ├── UserData.h │ │ ├── data.h │ │ └── def.h │ │ ├── sram_model.v │ │ ├── tb.sv │ │ ├── tb_fifo_fwft.v │ │ └── tb_uart.v └── sources_1 │ ├── ip │ ├── blk_mem_icache │ │ ├── blk_mem_icache.xci │ │ ├── blk_mem_icache.xml │ │ ├── blk_mem_icache_ooc.xdc │ │ ├── doc │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ ├── misc │ │ │ └── blk_mem_gen_v8_4.vhd │ │ ├── sim │ │ │ └── blk_mem_icache.v │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_4.v │ │ └── synth │ │ │ └── blk_mem_icache.vhd │ ├── blk_mem_regfile │ │ ├── blk_mem_regfile.xci │ │ ├── blk_mem_regfile.xml │ │ ├── blk_mem_regfile_ooc.xdc │ │ ├── doc │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ ├── misc │ │ │ └── blk_mem_gen_v8_4.vhd │ │ ├── sim │ │ │ └── blk_mem_regfile.v │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_4.v │ │ └── synth │ │ │ └── blk_mem_regfile.vhd │ ├── c_add_s32 │ │ ├── c_add_s32.xci │ │ ├── c_add_s32.xml │ │ ├── doc │ │ │ └── c_addsub_v12_0_changelog.txt │ │ ├── hdl │ │ │ ├── c_addsub_v12_0_vh_rfs.vhd │ │ │ ├── c_reg_fd_v12_0_vh_rfs.vhd │ │ │ ├── xbip_addsub_v3_0_vh_rfs.vhd │ │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ ├── sim │ │ │ └── c_add_s32.vhd │ │ └── synth │ │ │ └── c_add_s32.vhd │ ├── fifo_uart_queue │ │ ├── doc │ │ │ └── fifo_generator_v13_2_changelog.txt │ │ ├── fifo_uart_queue.xci │ │ ├── fifo_uart_queue.xdc │ │ ├── fifo_uart_queue.xml │ │ ├── fifo_uart_queue_ooc.xdc │ │ ├── hdl │ │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── fifo_generator_v13_2_rfs.v │ │ │ ├── fifo_generator_v13_2_rfs.vhd │ │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ │ ├── sim │ │ │ └── fifo_uart_queue.v │ │ ├── simulation │ │ │ └── fifo_generator_vlog_beh.v │ │ └── synth │ │ │ └── fifo_uart_queue.vhd │ ├── mult_exu │ │ ├── doc │ │ │ └── mult_gen_v12_0_changelog.txt │ │ ├── hdl │ │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ ├── mult_exu.xci │ │ ├── mult_exu.xml │ │ ├── mult_exu_ooc.xdc │ │ ├── sim │ │ │ └── mult_exu.vhd │ │ └── synth │ │ │ └── mult_exu.vhd │ └── pll_example │ │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_plus_pll.vh │ │ ├── pll_example.v │ │ ├── pll_example.xci │ │ ├── pll_example.xdc │ │ ├── pll_example.xml │ │ ├── pll_example_board.xdc │ │ ├── pll_example_clk_wiz.v │ │ └── pll_example_ooc.xdc │ └── new │ ├── SEG7_LUT.v │ ├── async.v │ ├── bypass_net.v │ ├── fake_uart.v │ ├── fifo_fwft_sclk.v │ ├── thinpad_top.v │ ├── uart.v │ ├── vga.v │ ├── xpm_sdpram_bypass.v │ ├── yamp32_biu.v │ ├── yamp32_bpu.v │ ├── yamp32_core.v │ ├── yamp32_ctrl.v │ ├── yamp32_exu.v │ ├── yamp32_icache.v │ ├── yamp32_idec.v │ ├── yamp32_idu.v │ ├── yamp32_ifu.v │ ├── yamp32_lsu.v │ ├── yamp32_parameters.vh │ ├── yamp32_regfile.v │ ├── yamp32_segmap.v │ └── yamp32_wb_mux.v └── thinpad_top.xpr /.ci-scripts/bits.tcl: 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