├── GODIL ├── godil6809 │ ├── .gitignore │ ├── gd6809.bit │ ├── godil6809.ucf │ ├── godil6809.xise │ └── godil6809 │ │ └── gd6809.v ├── godil6809e │ ├── .gitignore │ ├── gd6809e.bit │ ├── godil6809e.ucf │ ├── godil6809e.xise │ ├── godil6809e │ │ └── gd6809e.v │ └── godilmap.xlsx └── godil_clk.v ├── README.md ├── devboards ├── DE1-SoC │ ├── .gitignore │ ├── CPUROM.v │ ├── alt_top.qsf │ ├── alt_top.sdc │ ├── alt_top.v │ ├── bram.v │ ├── clk.v │ ├── cpuroma.qip │ ├── cpuroma.v │ ├── demo.qpf │ ├── dpbram.qip │ ├── dpbram.v │ ├── fontrom_glue.v │ ├── fontroma.qip │ ├── fontroma.v │ ├── pll.qip │ ├── pll.sip │ ├── pll.v │ └── pll │ │ ├── pll_0002.qip │ │ └── pll_0002.v ├── EP4CE6 │ ├── .gitignore │ ├── CPUROM.v │ ├── alt_top.v │ ├── bram.v │ ├── clk.v │ ├── cpuroma.qip │ ├── cpuroma.v │ ├── demo.qpf │ ├── demo_root.qsf │ ├── fontrom_glue.v │ ├── fontroma.qip │ ├── fontroma.v │ ├── pll.qip │ └── pll.v ├── LX9 │ ├── .gitignore │ ├── W25Q64BV.pdf │ ├── bram.v │ ├── demo │ │ ├── .gitignore │ │ ├── demo.xise │ │ └── ipcore_dir │ │ │ ├── .gitignore │ │ │ ├── CPUROM.v │ │ │ ├── CPUROM.xco │ │ │ ├── CPUROM.xise │ │ │ ├── clk.ucf │ │ │ ├── clk.v │ │ │ ├── clk.xco │ │ │ ├── clk.xise │ │ │ ├── dpbram.v │ │ │ ├── dpbram.xco │ │ │ ├── dpbram.xise │ │ │ ├── fontrom.v │ │ │ ├── fontrom.xco │ │ │ └── fontrom.xise │ ├── font.coe │ ├── lx9.ucf │ └── lx9_root.v ├── demo_root.v ├── font.coe ├── font.mif ├── ps2_communication.v ├── simplefifo.v ├── src6809 │ ├── img.bin │ ├── img.coe │ ├── img.mif │ └── startup.asm ├── sseg.v └── vga.v ├── documentation ├── 6809Details.md ├── APP.jpg ├── Acknowledgements.md ├── Blaster.jpg ├── CoCoCMD.jpg ├── CoreDesign.md ├── Cyc5.jpg ├── Cyc5SOC.jpg ├── EGlitch.png ├── EP4CE6.jpg ├── ElectricYoyo.jpg ├── FinalThoughts.md ├── Implementation.md ├── JROKWilliams.jpg ├── LICENSE.md ├── LX9.jpg ├── PoweredZooQWithGODIL.jpg ├── ROM.jpg ├── Validation.md ├── VectrexGODIL.jpg ├── VectrexGame1.jpg ├── VectrexOscillator.jpg ├── VectrexRemovedXtal.jpg ├── WilliamsGODIL1.jpg ├── WilliamsGODIL2.jpg ├── ZooQ.jpg ├── ZooQTop.jpg ├── bubbles.jpg ├── bus_sections.png ├── coco3.jpg ├── coco3boot.jpg ├── coco3pcb.jpg ├── coco3pcbgodil.jpg ├── complexX.jpg ├── critical.png ├── defender.jpg ├── godil.md ├── godil_btm.jpg ├── godil_top.jpg ├── joust.jpg ├── kram.jpg ├── onebuscycle.png ├── patch.md ├── qix.jpg ├── qix2.jpg ├── robotron.jpg ├── samples.md ├── sinistar.jpg ├── spacedungeon.jpg ├── splat.jpg ├── stargate-patch.png ├── stargate.jpg ├── super6809.md └── zookeeper.jpg ├── mc6809.v ├── mc6809e.v ├── mc6809i.v └── mc6809s.v /GODIL/godil6809/.gitignore: -------------------------------------------------------------------------------- 1 | *.bgn 2 | *.bld 3 | *.cmd_log 4 | *.csv 5 | *.drc 6 | *.gise 7 | *.lso 8 | *.map 9 | *.mrp 10 | *.ncd 11 | *.ngc 12 | *.ngm 13 | *.ngr 14 | *.pad 15 | *.par 16 | *.prj 17 | *.ptwx 18 | *.stx 19 | *.syr 20 | *.twr 21 | *.twx 22 | *.txt 23 | *.unroutes 24 | *.ut 25 | *.xpi 26 | *.xst 27 | *.xwbt 28 | *.html 29 | *.xrpt 30 | *.xml 31 | _ 32 | -------------------------------------------------------------------------------- /GODIL/godil6809/gd6809.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/GODIL/godil6809/gd6809.bit -------------------------------------------------------------------------------- /GODIL/godil6809/godil6809.ucf: -------------------------------------------------------------------------------- 1 | # GODIL40 .ucf sample 2 | # godil40 timing contraints 3 | #NET m49 PERIOD = 20.34505 ns ; 4 | #OFFSET = IN 10 ns BEFORE m49 ; 5 | #OFFSET = OUT 10 ns AFTER m49 ; 6 | #TIMESPEC TS_P2P = FROM PADS TO PADS 10 ns ; 7 | 8 | # inputs only 9 | 10 | NET fpgaclk LOC=P89 | IOSTANDARD = LVTTL | PERIOD = 20.34505ns ; 11 | #NET fpgaclk CLOCK_DEDICATED_ROUTE=FALSE; 12 | #NET sw1 LOC=P39 | IOSTANDARD = LVTTL ; 13 | #NET sw2 LOC=P69 | IOSTANDARD = LVTTL | PULLUP ; 14 | 15 | #NET d13 LOC=P88 | IOSTANDARD = LVTTL | PULLUP ; 16 | #NET sout LOC=P13 | IOSTANDARD = LVTTL | PULLUP ; 17 | #NET rts LOC=P30 | IOSTANDARD = LVTTL | PULLUP ; 18 | 19 | # I/O's for uart & spi flash 20 | #NET sin LOC=P43 | IOSTANDARD = LVTTL ; 21 | #NET cts LOC=P25 | IOSTANDARD = LVTTL ; 22 | #NET cso LOC=P24 | IOSTANDARD = LVTTL ; 23 | #NET vs2 LOC=P47 | IOSTANDARD = LVTTL ; 24 | 25 | # I/O's for test connector 26 | #NET tvs1 LOC=P48 | IOSTANDARD = LVTTL | DRIVE=16 ; 27 | #NET tvs0 LOC=P49 | IOSTANDARD = LVTTL | DRIVE=16 ; 28 | #NET tmosi LOC=P27 | IOSTANDARD = LVTTL | DRIVE=16 ; 29 | #NET tdin LOC=P44 | IOSTANDARD = LVTTL | DRIVE=16 ; 30 | #NET tcclk LOC=P50 | IOSTANDARD = LVTTL | DRIVE=16 ; 31 | #NET tm1 LOC=P42 | IOSTANDARD = LVTTL | DRIVE=16 ; 32 | #NET thsw LOC=P99 | IOSTANDARD = LVTTL | DRIVE=16 ; 33 | 34 | # I/O's for DIL / main connector 35 | 36 | #NET pin_a2 LOC=P15 | IOSTANDARD = LVTTL | PULLUP ; 37 | # The pins above aren't related to the 40 pin DIP; they can be used 38 | # for extraneous I/O or configuration. 39 | 40 | 41 | #NET GND LOC=P16 | IOSTANDARD = LVTTL ; 42 | NET nNMI LOC=P95 | IOSTANDARD = LVTTL ; 43 | NET nIRQ LOC=P18 | IOSTANDARD = LVTTL ; 44 | NET nFIRQ LOC=P17 | IOSTANDARD = LVTTL ; 45 | NET BS LOC=P94 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6; 46 | NET BA LOC=P22 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 47 | #NET Vcc LOC=P23 | IOSTANDARD = LVTTL ; 48 | NET A<0> LOC=P33 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 49 | NET A<1> LOC=P32 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 50 | NET A<2> LOC=P34 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 51 | NET A<3> LOC=P40 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 52 | NET A<4> LOC=P41 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 53 | NET A<5> LOC=P36 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 54 | NET A<6> LOC=P35 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 55 | NET A<7> LOC=P53 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 56 | NET A<8> LOC=P54 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 57 | NET A<9> LOC=P57 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 58 | NET A<10> LOC=P58 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 59 | NET A<11> LOC=P60 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 60 | NET A<12> LOC=P61 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 61 | #NET IRnW LOC=P62 | IOSTANDARD = LVTTL ; 62 | #NET pin_c25 LOC=P63 | IOSTANDARD = LVTTL ; 63 | #NET pin_d1 LOC=P91 | IOSTANDARD = LVTTL ; 64 | #NET pin_b2 LOC=P12 | IOSTANDARD = LVTTL ; 65 | NET nHALT LOC=P11 | IOSTANDARD = LVTTL ; 66 | NET XTAL LOC=P10 | IOSTANDARD = LVTTL ; 67 | NET EXTAL LOC=P9 | IOSTANDARD = LVTTL ; 68 | NET nRESET LOC=P90 | IOSTANDARD = LVTTL ; 69 | NET MRDY LOC=P5 | IOSTANDARD = LVTTL ; 70 | NET Q LOC=P4 | IOSTANDARD = LVTTL ; 71 | NET E LOC=P2 | IOSTANDARD = LVTTL ; 72 | NET nDMABREQ LOC=P3 | IOSTANDARD = LVTTL ; 73 | NET RnW LOC=P98 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 74 | NET D<0> LOC=P92 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 75 | NET D<1> LOC=P85 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 76 | NET D<2> LOC=P79 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 77 | NET D<3> LOC=P78 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 78 | NET D<4> LOC=P83 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 79 | NET D<5> LOC=P84 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 80 | NET D<6> LOC=P86 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 81 | NET D<7> LOC=P71 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 82 | NET A<15> LOC=P70 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 83 | NET A<14> LOC=P68 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 84 | NET A<13> LOC=P67 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 85 | 86 | #NET ELatched LOC=P65 | IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=6 ; 87 | 88 | 89 | # The pins below aren't related to the 40 pin DIP; they can be used 90 | # for extraneous I/O or configuration. 91 | #NET EBus LOC=P66 | IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=6 ; 92 | 93 | -------------------------------------------------------------------------------- /GODIL/godil6809/godil6809/gd6809.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09:10:47 09/23/2016 7 | // Design Name: 8 | // Module Name: gd6809 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module gd6809( 22 | input fpgaclk, 23 | inout [7:0] D, 24 | inout [15:0] A, 25 | inout RnW, 26 | output E, 27 | output Q, 28 | output BS, 29 | output BA, 30 | input nIRQ, 31 | input nFIRQ, 32 | input nNMI, 33 | input EXTAL, 34 | input XTAL, 35 | input MRDY, 36 | input nDMABREQ, 37 | input nHALT, 38 | input nRESET 39 | ); 40 | 41 | wire CLK; 42 | assign CLK=EXTAL; 43 | 44 | // Get a much faster clock than the XTAL on the GODIL board for filtering and delaying 45 | // precisely 46 | wire fpga6x; 47 | wire oscclk; 48 | 49 | // Instantiate the module 50 | godil_clk clkgen ( 51 | .CLKIN_IN(fpgaclk), 52 | .USER_RST_IN(0), 53 | .CLKFX_OUT(fpga6x), 54 | .CLKIN_IBUFG_OUT(oscclk) 55 | ); 56 | 57 | 58 | wire wTristated = (BA); 59 | 60 | 61 | // Generate a Power On Reset; 6809 says '1 cycle minimum', 4 is just spiffy. 62 | reg [1:0] PORCount; 63 | reg nPOR; 64 | 65 | // The /RESET signal we send to the core needs to be carefully filtered, as the 6809's trigger on /RESET is 4V, not the typical TTL 2V. 66 | // Otherwise, we'll come out of RESET likely before anyone else. 67 | localparam MINIMUM_RESET_SETTLE_CLOCKS=13'H1000; 68 | reg rnRESET; 69 | reg [12:0] RESETReleaseCount; 70 | 71 | 72 | reg [23:0] EDelay; 73 | 74 | reg [15:0] AOutLatched; 75 | reg RnWOutLatched; 76 | reg [7:0] DOutLatched; 77 | 78 | reg NMILatch; 79 | 80 | 81 | wire [15:0] AFromCPU; 82 | wire RnWFromCPU; 83 | wire [7:0] DOut; 84 | 85 | // Tristatable Address Bus 86 | genvar gab; 87 | generate 88 | for (gab= 0; gab < 16; gab = gab + 1) 89 | begin : godilabus 90 | assign A[gab] = ~wTristated ? AOutLatched[gab] : 1'bZ; 91 | end 92 | endgenerate 93 | 94 | reg RnWBusControl; 95 | 96 | assign RnW = wTristated ? 1'bZ : RnWOutLatched; 97 | 98 | 99 | 100 | assign IRnW = RnWFromCPU; 101 | 102 | 103 | initial 104 | begin 105 | PORCount = 2'b00; 106 | nPOR = 1'b0; 107 | rnRESET = 1'b0; 108 | RESETReleaseCount = 13'H0000; 109 | end 110 | 111 | 112 | wire EFilterSrc = E; // Just slightly delayed from E; a BUFG delay primarily. 113 | wire EFilterBusSrc = EDelay[23]; // 114 | wire EFilterAddrSrc = EDelay[10]; 115 | wire EFilterBusRnWSrc = EDelay[14]; 116 | 117 | wire EFilter; 118 | BUFG CLKB_EF( .I(EFilterSrc), 119 | .O(EFilter)); 120 | 121 | wire EFilterBus; 122 | BUFG CLKB_EFB( .I(EFilterBusSrc), 123 | .O(EFilterBus)); 124 | 125 | wire EFilterAddr; 126 | BUFG CLKB_EFA( .I(EFilterAddrSrc), 127 | .O(EFilterAddr)); 128 | 129 | wire EFilterBusRnW; 130 | BUFG CLKB_EFBRW( .I(EFilterBusRnWSrc), 131 | .O(EFilterBusRnW)); 132 | 133 | 134 | assign ELatched = EFilter; 135 | assign EBus = EFilterBus; 136 | 137 | assign D = (wTristated | RnWBusControl) ? 8'HZZ : DOutLatched; 138 | 139 | always @(posedge fpga6x) 140 | begin 141 | // I see Ringing on E on the GODIL, likely due to the high drive characteristics of E on many systems. 142 | // That forces me to do filtering to eliminate the glitches that otherwise appear. I've only ever 143 | // seen ringing after a falling edge [the rising edge is likely happening as well, but with a LVTTL 144 | // 2.0V high signal and E driven to 5V, it's likely happening and retaining a logic 1 the entire time]. 145 | // Thus, I filter out sampled clock pulses that are shorter than 3 samples in width (3.39ns * 3). This 146 | // has an unfortunate effect of delaying (and shortening) E by the same amount of time, and while Q is latched, 147 | // it isn't equally delayed. Thus, in a relative sense, the core sees 'Q' slightly early in the sense 148 | // of quadrature. 149 | // 150 | // I admit that I removed the filtering several times before eventually giving up and leaving it in here; 151 | // too many times I struggled with chaos before finding a very short 'E' pulse made it to the CPU core 152 | // before the core had time to actually do anything. Thus, it stays on. :| 153 | // 154 | EDelay[0] <= E; 155 | EDelay[23:1] <= EDelay[22:0]; 156 | NMILatch <= nNMI; 157 | end 158 | 159 | // Latch RnW and the Address bus from the CPU 160 | always @(negedge EFilterAddr) 161 | begin 162 | AOutLatched <= AFromCPU; 163 | RnWOutLatched <= RnWFromCPU; 164 | end 165 | 166 | // Latch a copy of RnW from the CPU; this is intentionally after the latch above; the intent is to 167 | // copy 6809 behavior where the RnW output actually doesn't match identically the Data Bus behavior, 168 | // and write data can be held for a few nanoseconds even though RnW might be high. 169 | // (Yes, I put a 6809 on an analyzer, as well as a 6309 to note that they had that characteristic.) 170 | always @(negedge EFilterBusRnW) 171 | begin 172 | RnWBusControl <= RnWFromCPU; 173 | end 174 | 175 | // Much later, latch the Data bus *OUTPUT* from the CPU. This is only used if RnWOutBusControl == 0, of course. 176 | always @(negedge EFilterBus) 177 | begin 178 | DOutLatched <= DOut; 179 | end 180 | 181 | // Generate a Power On Reset 182 | always @(negedge EFilter) 183 | begin 184 | if (PORCount != 2'b11) 185 | begin 186 | nPOR = 1'b0; 187 | PORCount <= PORCount + 2'b01; 188 | end 189 | else 190 | nPOR = 1'b1; 191 | end 192 | 193 | // The 6809 has a very high VIH for /RESET; 4V. That isn't detectable in a 3.3V LVTTL. 194 | // The design intent was to ensure that the 6809 left RESET last - after peripheral components. 195 | // 196 | // Since a 4V level can't be detected here, to achieve the same thing - to try to ensure 197 | // that the CPU doesn't come out of RESET before the peripherals (as it'll be quite disappointed if 198 | // it does - accesses to different addresses, depending on architecture, just wouldn't work) - 199 | // we end up having to do something different. 200 | // 201 | // We could rewire the GODIL to detect the 4V trigger, but that defeats the point. 202 | // 203 | // Instead, we stall the signal while also doing debouncing on it. 204 | // 205 | // Any '0' on the input signal causes the value we send to the core to go to 0. 206 | // Once we begin seeing '1's we need to see '1's for N cycles in a row before we accept that reset is released. 207 | // This provides debounce (for those systems using a pushbutton) and an admittedly rough estimation of when we should 208 | // let the core out of /RESET so that other hardware isn't still RESET when the CPU exits the state. 209 | // 210 | always @(negedge EFilter) 211 | begin 212 | if (nRESET == 0) 213 | begin 214 | rnRESET <= 1'b0; 215 | RESETReleaseCount <= MINIMUM_RESET_SETTLE_CLOCKS; 216 | end 217 | else 218 | begin 219 | // if ((rnRESET == 0) && (nRESET == 0)) 220 | // RESETReleaseCount <= MINIMUM_RESET_SETTLE_CLOCKS; 221 | // else 222 | if ((rnRESET == 0) && (nRESET == 1)) 223 | begin 224 | RESETReleaseCount <= RESETReleaseCount - 1'b1; 225 | if (RESETReleaseCount == 13'H0001) 226 | rnRESET <= 1'b1; 227 | end 228 | end 229 | end 230 | 231 | 232 | wire nRESETPlusPOR = (rnRESET & nPOR); // 0 if either are low, 1 otherwise. 233 | 234 | 235 | 236 | mc6809 cpu(.D(D), .DOut(DOut), .ADDR(AFromCPU), .RnW(RnWFromCPU), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), 237 | .nNMI(NMILatch), .MRDY(MRDY), .nHALT(nHALT), .nDMABREQ(nDMABREQ), .nRESET(nRESETPlusPOR), .EXTAL(EXTAL), .XTAL(XTAL) ); 238 | 239 | 240 | endmodule 241 | -------------------------------------------------------------------------------- /GODIL/godil6809e/.gitignore: -------------------------------------------------------------------------------- 1 | *.bgn 2 | *.bld 3 | *.cmd_log 4 | *.csv 5 | *.drc 6 | *.gise 7 | *.lso 8 | *.map 9 | *.mrp 10 | *.ncd 11 | *.ngc 12 | *.ngm 13 | *.ngr 14 | *.pad 15 | *.par 16 | *.prj 17 | *.ptwx 18 | *.stx 19 | *.syr 20 | *.twr 21 | *.twx 22 | *.txt 23 | *.unroutes 24 | *.ut 25 | *.xpi 26 | *.xst 27 | *.xwbt 28 | *.html 29 | *.xrpt 30 | *.xml 31 | _ 32 | -------------------------------------------------------------------------------- /GODIL/godil6809e/gd6809e.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/GODIL/godil6809e/gd6809e.bit -------------------------------------------------------------------------------- /GODIL/godil6809e/godil6809e.ucf: -------------------------------------------------------------------------------- 1 | # GODIL40 .ucf sample 2 | # godil40 timing contraints 3 | #NET m49 PERIOD = 20.34505 ns ; 4 | #OFFSET = IN 10 ns BEFORE m49 ; 5 | #OFFSET = OUT 10 ns AFTER m49 ; 6 | #TIMESPEC TS_P2P = FROM PADS TO PADS 10 ns ; 7 | 8 | # inputs only 9 | 10 | NET fpgaclk LOC=P89 | IOSTANDARD = LVTTL | PERIOD = 20.34505ns ; 11 | #NET fpgaclk CLOCK_DEDICATED_ROUTE=FALSE; 12 | #NET sw1 LOC=P39 | IOSTANDARD = LVTTL ; 13 | #NET sw2 LOC=P69 | IOSTANDARD = LVTTL | PULLUP ; 14 | 15 | #NET d13 LOC=P88 | IOSTANDARD = LVTTL | PULLUP ; 16 | #NET sout LOC=P13 | IOSTANDARD = LVTTL | PULLUP ; 17 | #NET rts LOC=P30 | IOSTANDARD = LVTTL | PULLUP ; 18 | 19 | # I/O's for uart & spi flash 20 | #NET sin LOC=P43 | IOSTANDARD = LVTTL ; 21 | #NET cts LOC=P25 | IOSTANDARD = LVTTL ; 22 | #NET cso LOC=P24 | IOSTANDARD = LVTTL ; 23 | #NET vs2 LOC=P47 | IOSTANDARD = LVTTL ; 24 | 25 | # I/O's for test connector 26 | #NET tvs1 LOC=P48 | IOSTANDARD = LVTTL | DRIVE=16 ; 27 | #NET tvs0 LOC=P49 | IOSTANDARD = LVTTL | DRIVE=16 ; 28 | #NET tmosi LOC=P27 | IOSTANDARD = LVTTL | DRIVE=16 ; 29 | #NET tdin LOC=P44 | IOSTANDARD = LVTTL | DRIVE=16 ; 30 | #NET tcclk LOC=P50 | IOSTANDARD = LVTTL | DRIVE=16 ; 31 | #NET tm1 LOC=P42 | IOSTANDARD = LVTTL | DRIVE=16 ; 32 | #NET thsw LOC=P99 | IOSTANDARD = LVTTL | DRIVE=16 ; 33 | 34 | # I/O's for DIL / main connector 35 | 36 | #NET pin_a2 LOC=P15 | IOSTANDARD = LVTTL | PULLUP ; 37 | # The pins above aren't related to the 40 pin DIP; they can be used 38 | # for extraneous I/O or configuration. 39 | 40 | 41 | #NET GND LOC=P16 | IOSTANDARD = LVTTL ; 42 | NET nNMI LOC=P95 | IOSTANDARD = LVTTL ; 43 | NET nIRQ LOC=P18 | IOSTANDARD = LVTTL ; 44 | NET nFIRQ LOC=P17 | IOSTANDARD = LVTTL ; 45 | NET BS LOC=P94 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6; 46 | NET BA LOC=P22 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 47 | NET A<0> LOC=P33 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 48 | NET A<1> LOC=P32 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 49 | NET A<2> LOC=P34 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 50 | NET A<3> LOC=P40 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 51 | NET A<4> LOC=P41 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 52 | NET A<5> LOC=P36 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 53 | NET A<6> LOC=P35 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 54 | NET A<7> LOC=P53 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 55 | NET A<8> LOC=P54 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 56 | NET A<9> LOC=P57 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 57 | NET A<10> LOC=P58 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 58 | NET A<11> LOC=P60 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 59 | NET A<12> LOC=P61 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6 ; 60 | #NET IRnW LOC=P62 | IOSTANDARD = LVTTL ; 61 | #NET pin_c25 LOC=P63 | IOSTANDARD = LVTTL ; 62 | #NET pin_d1 LOC=P91 | IOSTANDARD = LVTTL ; 63 | #NET pin_b2 LOC=P12 | IOSTANDARD = LVTTL ; 64 | NET nHALT LOC=P11 | IOSTANDARD = LVTTL ; 65 | NET TSC LOC=P10 | IOSTANDARD = LVTTL ; 66 | NET LIC LOC=P9 | IOSTANDARD = LVTTL ; 67 | NET nRESET LOC=P90 | IOSTANDARD = LVTTL ; 68 | NET AVMA LOC=P5 | IOSTANDARD = LVTTL ; 69 | NET Q LOC=P4 | IOSTANDARD = LVTTL ; 70 | NET E LOC=P2 | IOSTANDARD = LVTTL ; 71 | NET BUSY LOC=P3 | IOSTANDARD = LVTTL ; 72 | NET RnW LOC=P98 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 73 | NET D<0> LOC=P92 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 74 | NET D<1> LOC=P85 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 75 | NET D<2> LOC=P79 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 76 | NET D<3> LOC=P78 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 77 | NET D<4> LOC=P83 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 78 | NET D<5> LOC=P84 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 79 | NET D<6> LOC=P86 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 80 | NET D<7> LOC=P71 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 81 | NET A<15> LOC=P70 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 82 | NET A<14> LOC=P68 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 83 | NET A<13> LOC=P67 | IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=4 ; 84 | 85 | #NET IRQCopy LOC=P65 | IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=6 ; 86 | 87 | 88 | # The pins below aren't related to the 40 pin DIP; they can be used 89 | # for extraneous I/O or configuration. 90 | #NET EBus LOC=P66 | IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=6 ; 91 | 92 | 93 | -------------------------------------------------------------------------------- /GODIL/godil6809e/godil6809e/gd6809e.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09:10:47 09/23/2016 7 | // Design Name: 8 | // Module Name: gd6809e 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module gd6809e( 22 | input fpgaclk, 23 | inout [7:0] D, 24 | inout [15:0] A, 25 | inout RnW, 26 | input E, 27 | input Q, 28 | output BS, 29 | output BA, 30 | input nIRQ, 31 | input nFIRQ, 32 | input nNMI, 33 | output AVMA, 34 | output BUSY, 35 | input TSC, 36 | output LIC, 37 | input nHALT, 38 | input nRESET 39 | ); 40 | 41 | // Get a much faster clock than the XTAL on the GODIL board for filtering and delaying 42 | // precisely 43 | wire fpga6x; 44 | wire oscclk; 45 | 46 | // Instantiate the module 47 | godil_clk clkgen ( 48 | .CLKIN_IN(fpgaclk), 49 | .USER_RST_IN(0), 50 | .CLKFX_OUT(fpga6x), 51 | .CLKIN_IBUFG_OUT(oscclk) 52 | ); 53 | 54 | 55 | wire wTristated = (BA | TSC); 56 | 57 | 58 | // Generate a Power On Reset; 6809 says '1 cycle minimum', 4 is just spiffy. 59 | reg [1:0] PORCount; 60 | reg nPOR; 61 | 62 | // The /RESET signal we send to the core needs to be carefully filtered, as the 6809's trigger on /RESET is 4V, not the typical TTL 2V. 63 | // Otherwise, we'll come out of RESET likely before anyone else. 64 | localparam MINIMUM_RESET_SETTLE_CLOCKS=13'H1000; 65 | reg rnRESET; 66 | reg [12:0] RESETReleaseCount; 67 | 68 | 69 | reg QLatch; 70 | reg [23:0] EDelay; 71 | 72 | reg [15:0] AOutLatched; 73 | reg RnWOutLatched; 74 | reg [7:0] DOutLatched; 75 | 76 | reg NMILatch; 77 | 78 | 79 | // Tristatable Address Bus 80 | genvar gab; 81 | generate 82 | for (gab= 0; gab < 16; gab = gab + 1) 83 | begin : godilabus 84 | assign A[gab] = ~wTristated ? AOutLatched[gab] : 1'bZ; 85 | end 86 | endgenerate 87 | 88 | reg RnWBusControl; 89 | 90 | assign RnW = wTristated ? 1'bZ : RnWOutLatched; 91 | 92 | 93 | 94 | wire [15:0] AFromCPU; 95 | wire RnWFromCPU; 96 | wire [7:0] DOut; 97 | 98 | initial 99 | begin 100 | PORCount = 2'b00; 101 | nPOR = 1'b0; 102 | rnRESET = 1'b0; 103 | RESETReleaseCount = 13'H0000; 104 | end 105 | 106 | 107 | wire EFilterSrc = EDelay[1] & EDelay[0] & E; // Just slightly delayed from E; a BUFG delay primarily. 108 | wire EFilterBusSrc = EDelay[23]; // This is roughly 75ns of delay from E. 109 | wire EFilterAddrSrc = EDelay[10]; // Roughly 35ns 110 | wire EFilterBusRnWSrc = EDelay[14]; // Roughly 50ns 111 | 112 | wire EFilter; 113 | BUFG CLKB_EF( .I(EFilterSrc), 114 | .O(EFilter)); 115 | 116 | wire EFilterBus; 117 | BUFG CLKB_EFB( .I(EFilterBusSrc), 118 | .O(EFilterBus)); 119 | 120 | wire EFilterAddr; 121 | BUFG CLKB_EFA( .I(EFilterAddrSrc), 122 | .O(EFilterAddr)); 123 | 124 | wire EFilterBusRnW; 125 | BUFG CLKB_EFBRW( .I(EFilterBusRnWSrc), 126 | .O(EFilterBusRnW)); 127 | 128 | 129 | assign D = (wTristated | RnWBusControl) ? 8'HZZ : DOutLatched; 130 | 131 | always @(posedge fpga6x) 132 | begin 133 | // I see Ringing on E on the GODIL, likely due to the high drive characteristics of E on many systems. 134 | // That forces me to do filtering to eliminate the glitches that otherwise appear. I've only ever 135 | // seen ringing after a falling edge [the rising edge is likely happening as well, but with a LVTTL 136 | // 2.0V high signal and E driven to 5V, it's likely happening and retaining a logic 1 the entire time]. 137 | // Thus, I filter out sampled clock pulses that are shorter than 3 samples in width (3.39ns * 3). This 138 | // has an unfortunate effect of delaying (and shortening) E by the same amount of time, and while Q is latched, 139 | // it isn't equally delayed. Thus, in a relative sense, the core sees 'Q' slightly early in the sense 140 | // of quadrature. 141 | // 142 | // I admit that I removed the filtering several times before eventually giving up and leaving it in here; 143 | // too many times I struggled with chaos before finding a very short 'E' pulse made it to the CPU core 144 | // before the core had time to actually do anything. Thus, it stays on. :| 145 | // 146 | EDelay[0] <= E; 147 | EDelay[1] <= EDelay[0] & E; 148 | EDelay[2] <= EDelay[1] & EDelay[0] & E; 149 | EDelay[23:3] <= EDelay[22:2]; 150 | QLatch <= Q; 151 | NMILatch <= nNMI; 152 | end 153 | 154 | // Latch RnW and the Address bus from the CPU 155 | always @(negedge EFilterAddr) 156 | begin 157 | AOutLatched <= AFromCPU; 158 | RnWOutLatched <= RnWFromCPU; 159 | end 160 | 161 | // Latch a copy of RnW from the CPU; this is intentionally after the latch above; the intent is to 162 | // copy 6809 behavior where the RnW output actually doesn't match identically the Data Bus behavior, 163 | // and write data can be held for a few nanoseconds even though RnW might be high. 164 | // (Yes, I put a 6809 on an analyzer, as well as a 6309 to note that they had that characteristic.) 165 | always @(negedge EFilterBusRnW) 166 | begin 167 | RnWBusControl <= RnWFromCPU; 168 | end 169 | 170 | // Much later, latch the Data bus *OUTPUT* from the CPU. 171 | always @(negedge EFilterBus) 172 | begin 173 | DOutLatched <= DOut; 174 | end 175 | 176 | // Generate a Power On Reset 177 | always @(negedge EFilter) 178 | begin 179 | if (PORCount != 2'b11) 180 | begin 181 | nPOR = 1'b0; 182 | PORCount <= PORCount + 2'b01; 183 | end 184 | else 185 | nPOR = 1'b1; 186 | end 187 | 188 | // The 6809 has a very high VIH for /RESET; 4V. That isn't detectable in a 3.3V LVTTL. 189 | // The design intent was to ensure that the 6809 left RESET last - after peripheral components. 190 | // 191 | // Since a 4V level can't be detected here, to achieve the same thing - to try to ensure 192 | // that the CPU doesn't come out of RESET before the peripherals (as it'll be quite disappointed if 193 | // it does - accesses to different addresses, depending on architecture, just wouldn't work) - 194 | // we end up having to do something different. 195 | // 196 | // We could rewire the GODIL to detect the 4V trigger, but that defeats the point. 197 | // 198 | // Instead, we stall the signal while also doing debouncing on it. 199 | // 200 | // Any '0' on the input signal causes the value we send to the core to go to 0. 201 | // Once we begin seeing '1's we need to see '1's for N cycles in a row before we accept that reset is released. 202 | // This provides debounce (for those systems using a pushbutton) and an admittedly rough estimation of when we should 203 | // let the core out of /RESET so that other hardware isn't still RESET when the CPU exits the state. 204 | // 205 | always @(negedge EFilter) 206 | begin 207 | if (nRESET == 0) 208 | begin 209 | rnRESET <= 1'b0; 210 | RESETReleaseCount <= MINIMUM_RESET_SETTLE_CLOCKS; 211 | end 212 | else 213 | begin 214 | // if ((rnRESET == 0) && (nRESET == 0)) 215 | // RESETReleaseCount <= MINIMUM_RESET_SETTLE_CLOCKS; 216 | // else 217 | if ((rnRESET == 0) && (nRESET == 1)) 218 | begin 219 | RESETReleaseCount <= RESETReleaseCount - 1'b1; 220 | if (RESETReleaseCount == 13'H0001) 221 | rnRESET <= 1'b1; 222 | end 223 | end 224 | end 225 | 226 | 227 | wire nRESETPlusPOR = (rnRESET & nPOR); // 0 if either are low, 1 otherwise. 228 | 229 | 230 | 231 | mc6809e cpu(.D(D), .DOut(DOut), .ADDR(AFromCPU), .RnW(RnWFromCPU), .E(EFilter), .Q(QLatch), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), 232 | .nNMI(NMILatch), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESETPlusPOR) 233 | ); 234 | 235 | 236 | endmodule 237 | -------------------------------------------------------------------------------- /GODIL/godil6809e/godilmap.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/GODIL/godil6809e/godilmap.xlsx -------------------------------------------------------------------------------- /GODIL/godil_clk.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // ____ ____ 5 | // / /\/ / 6 | // /___/ \ / Vendor: Xilinx 7 | // \ \ \/ Version : 14.7 8 | // \ \ Application : xaw2verilog 9 | // / / Filename : godil_clk.v 10 | // /___/ /\ Timestamp : 10/01/2016 21:49:51 11 | // \ \ / \ 12 | // \___\/\___\ 13 | // 14 | //Command: xaw2verilog -st C:\Users\gmiller\OneDrive\mcm6809\GODIL\godil6809e\godil6809e\ipcore_dir\.\godil_clk.xaw C:\Users\gmiller\OneDrive\mcm6809\GODIL\godil6809e\godil6809e\ipcore_dir\.\godil_clk 15 | //Design Name: godil_clk 16 | //Device: xc3s500e-4vq100 17 | // 18 | // Module godil_clk 19 | // Generated by Xilinx Architecture Wizard 20 | // Written for synthesis tool: XST 21 | // Period Jitter (unit interval) for block DCM_SP_INST = 0.10 UI 22 | // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.70 ns 23 | `timescale 1ns / 1ps 24 | 25 | module godil_clk(CLKIN_IN, 26 | USER_RST_IN, 27 | CLKFX_OUT, 28 | CLKIN_IBUFG_OUT); 29 | 30 | input CLKIN_IN; 31 | input USER_RST_IN; 32 | output CLKFX_OUT; 33 | output CLKIN_IBUFG_OUT; 34 | 35 | wire CLKFX_BUF; 36 | wire CLKIN_IBUFG; 37 | wire FDS_Q_OUT; 38 | wire FD1_Q_OUT; 39 | wire FD2_Q_OUT; 40 | wire FD3_Q_OUT; 41 | wire GND_BIT; 42 | wire OR3_O_OUT; 43 | wire RST_IN; 44 | 45 | assign GND_BIT = 0; 46 | assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; 47 | BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), 48 | .O(CLKFX_OUT)); 49 | IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), 50 | .O(CLKIN_IBUFG)); 51 | DCM_SP #( .CLK_FEEDBACK("NONE"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1), 52 | .CLKFX_MULTIPLY(6), .CLKIN_DIVIDE_BY_2("FALSE"), 53 | .CLKIN_PERIOD(20.345), .CLKOUT_PHASE_SHIFT("NONE"), 54 | .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), 55 | .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), 56 | .FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) 57 | DCM_SP_INST (.CLKFB(GND_BIT), 58 | .CLKIN(CLKIN_IBUFG), 59 | .DSSEN(GND_BIT), 60 | .PSCLK(GND_BIT), 61 | .PSEN(GND_BIT), 62 | .PSINCDEC(GND_BIT), 63 | .RST(RST_IN), 64 | .CLKDV(), 65 | .CLKFX(CLKFX_BUF), 66 | .CLKFX180(), 67 | .CLK0(), 68 | .CLK2X(), 69 | .CLK2X180(), 70 | .CLK90(), 71 | .CLK180(), 72 | .CLK270(), 73 | .LOCKED(), 74 | .PSDONE(), 75 | .STATUS()); 76 | FDS FDS_INST (.C(CLKIN_IBUFG), 77 | .D(GND_BIT), 78 | .S(GND_BIT), 79 | .Q(FDS_Q_OUT)); 80 | FD FD1_INST (.C(CLKIN_IBUFG), 81 | .D(FDS_Q_OUT), 82 | .Q(FD1_Q_OUT)); 83 | FD FD2_INST (.C(CLKIN_IBUFG), 84 | .D(FD1_Q_OUT), 85 | .Q(FD2_Q_OUT)); 86 | FD FD3_INST (.C(CLKIN_IBUFG), 87 | .D(FD2_Q_OUT), 88 | .Q(FD3_Q_OUT)); 89 | OR2 OR2_INST (.I0(USER_RST_IN), 90 | .I1(OR3_O_OUT), 91 | .O(RST_IN)); 92 | OR3 OR3_INST (.I0(FD3_Q_OUT), 93 | .I1(FD2_Q_OUT), 94 | .I2(FD1_Q_OUT), 95 | .O(OR3_O_OUT)); 96 | endmodule 97 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/.gitignore: -------------------------------------------------------------------------------- 1 | *.ddb 2 | 3 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/CPUROM.v: -------------------------------------------------------------------------------- 1 | module CPUROM( 2 | input clka, 3 | input ena, 4 | input [9:0] addra, 5 | output [7:0] douta 6 | ); 7 | 8 | cpuroma cpurom_glue(.address(addra), 9 | .clock(clka), 10 | .rden(ena), 11 | .q(douta) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/alt_top.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Web Edition 22 | # Date created = 13:24:49 November 27, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # alt_top_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone V" 41 | set_global_assignment -name DEVICE 5CSEMA5F31C6 42 | set_global_assignment -name TOP_LEVEL_ENTITY alt_top 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:24:49 NOVEMBER 27, 2016" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 52 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 53 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 54 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 55 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 56 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 57 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 58 | set_location_assignment PIN_AF14 -to OSCCLK 59 | set_location_assignment PIN_F10 -to vgablank 60 | set_location_assignment PIN_C10 -to vgasync 61 | set_location_assignment PIN_D11 -to vsync 62 | set_location_assignment PIN_B11 -to hsync 63 | set_location_assignment PIN_AH28 -to sseg1[6] 64 | set_location_assignment PIN_AG28 -to sseg1[5] 65 | set_location_assignment PIN_AF28 -to sseg1[4] 66 | set_location_assignment PIN_AG27 -to sseg1[3] 67 | set_location_assignment PIN_AE28 -to sseg1[2] 68 | set_location_assignment PIN_AE27 -to sseg1[1] 69 | set_location_assignment PIN_AE26 -to sseg1[0] 70 | set_location_assignment PIN_AD27 -to sseg2[6] 71 | set_location_assignment PIN_AF30 -to sseg2[5] 72 | set_location_assignment PIN_AF29 -to sseg2[4] 73 | set_location_assignment PIN_AG30 -to sseg2[3] 74 | set_location_assignment PIN_AH30 -to sseg2[2] 75 | set_location_assignment PIN_AH29 -to sseg2[1] 76 | set_location_assignment PIN_AJ29 -to sseg2[0] 77 | set_location_assignment PIN_AC30 -to sseg3[6] 78 | set_location_assignment PIN_AC29 -to sseg3[5] 79 | set_location_assignment PIN_AD30 -to sseg3[4] 80 | set_location_assignment PIN_AC28 -to sseg3[3] 81 | set_location_assignment PIN_AD29 -to sseg3[2] 82 | set_location_assignment PIN_AE29 -to sseg3[1] 83 | set_location_assignment PIN_AB23 -to sseg3[0] 84 | set_location_assignment PIN_W25 -to sseg4[6] 85 | set_location_assignment PIN_V23 -to sseg4[5] 86 | set_location_assignment PIN_W24 -to sseg4[4] 87 | set_location_assignment PIN_W22 -to sseg4[3] 88 | set_location_assignment PIN_Y24 -to sseg4[2] 89 | set_location_assignment PIN_Y23 -to sseg4[1] 90 | set_location_assignment PIN_AA24 -to sseg4[0] 91 | set_location_assignment PIN_A11 -to vga_clk 92 | set_location_assignment PIN_B12 -to red[3] 93 | set_location_assignment PIN_E13 -to red[2] 94 | set_location_assignment PIN_C13 -to red[1] 95 | set_location_assignment PIN_A13 -to red[0] 96 | set_location_assignment PIN_F14 -to blue[3] 97 | set_location_assignment PIN_H13 -to blue[2] 98 | set_location_assignment PIN_G13 -to blue[1] 99 | set_location_assignment PIN_B13 -to blue[0] 100 | set_location_assignment PIN_G10 -to green[3] 101 | set_location_assignment PIN_H12 -to green[2] 102 | set_location_assignment PIN_J10 -to green[1] 103 | set_location_assignment PIN_J9 -to green[0] 104 | set_location_assignment PIN_AD7 -to ps2_clk 105 | set_location_assignment PIN_AE7 -to ps2_data 106 | set_global_assignment -name FITTER_EFFORT "FAST FIT" 107 | set_location_assignment PIN_J14 -to blue[7] 108 | set_location_assignment PIN_G15 -to blue[6] 109 | set_location_assignment PIN_F15 -to blue[5] 110 | set_location_assignment PIN_H14 -to blue[4] 111 | set_location_assignment PIN_E11 -to green[7] 112 | set_location_assignment PIN_F11 -to green[6] 113 | set_location_assignment PIN_G12 -to green[5] 114 | set_location_assignment PIN_G11 -to green[4] 115 | set_location_assignment PIN_F13 -to red[7] 116 | set_location_assignment PIN_E12 -to red[6] 117 | set_location_assignment PIN_D12 -to red[5] 118 | set_location_assignment PIN_C12 -to red[4] 119 | set_global_assignment -name VERILOG_FILE ../sseg.v 120 | set_global_assignment -name SDC_FILE alt_top.sdc 121 | set_global_assignment -name VERILOG_FILE ../../mc6809i.v 122 | set_global_assignment -name VERILOG_FILE ../../mc6809.v 123 | set_global_assignment -name VERILOG_FILE CPUROM.v 124 | set_global_assignment -name VERILOG_FILE fontrom_glue.v 125 | set_global_assignment -name VERILOG_FILE clk.v 126 | set_global_assignment -name VERILOG_FILE alt_top.v 127 | set_global_assignment -name VERILOG_FILE ../vga.v 128 | set_global_assignment -name VERILOG_FILE ../simplefifo.v 129 | set_global_assignment -name VERILOG_FILE ../ps2_communication.v 130 | set_global_assignment -name VERILOG_FILE ../demo_root.v 131 | set_global_assignment -name QIP_FILE pll.qip 132 | set_global_assignment -name SIP_FILE pll.sip 133 | set_global_assignment -name QIP_FILE fontroma.qip 134 | set_global_assignment -name QIP_FILE dpbram.qip 135 | set_global_assignment -name VERILOG_FILE bram.v 136 | set_global_assignment -name QIP_FILE cpuroma.qip 137 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /devboards/DE1-SoC/alt_top.v: -------------------------------------------------------------------------------- 1 | module alt_top( 2 | input OSCCLK, 3 | output hsync, 4 | output vsync, 5 | output [7:0] red, 6 | output [7:0] green, 7 | output [7:0] blue, 8 | output vgablank, 9 | output vgasync, 10 | output vga_clk, 11 | 12 | output [6:0] sseg1, 13 | output [6:0] sseg2, 14 | output [6:0] sseg3, 15 | output [6:0] sseg4, 16 | 17 | input ps2_clk, 18 | input ps2_data 19 | ); 20 | 21 | 22 | wire led1_led2; 23 | wire led3; 24 | 25 | assign vgablank=1'b1; 26 | assign vgasync=1'b0; 27 | 28 | wire [3:0] an; 29 | wire [7:0] sseg; 30 | 31 | reg [6:0] seg1; 32 | reg [6:0] seg2; 33 | reg [6:0] seg3; 34 | reg [6:0] seg4; 35 | assign sseg1 = seg1; 36 | assign sseg2 = seg2; 37 | assign sseg3 = seg3; 38 | assign sseg4 = seg4; 39 | 40 | wire [7:0] sseg_in; 41 | 42 | demo_root alt_map( 43 | .OSCCLK(OSCCLK), 44 | .hsync(hsync), 45 | .vsync(vsync), 46 | .red(red), 47 | .green(green), 48 | .blue(blue), 49 | .sseg(sseg_in), 50 | .an(an), 51 | .ps2_clk(ps2_clk), 52 | .ps2_data(ps2_data), 53 | .vga_clk(vga_clk) 54 | ); 55 | always @(*) 56 | begin 57 | if (~an[0]) 58 | seg1 = sseg_in[6:0]; 59 | if (~an[1]) 60 | seg2 = sseg_in[6:0]; 61 | if (~an[2]) 62 | seg3 = sseg_in[6:0]; 63 | if (~an[3]) 64 | seg4 = sseg_in[6:0]; 65 | end 66 | 67 | endmodule 68 | 69 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/bram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module bram # ( 4 | parameter DATA=8, 5 | parameter ADDR=15 6 | )( 7 | // Port A 8 | input wire a_clk, 9 | input wire a_en, 10 | input wire a_wr, 11 | input wire [ADDR-1:0] a_addr, 12 | input wire [DATA-1:0] a_din, 13 | output wire [DATA-1:0] a_dout, 14 | 15 | // Port B 16 | input wire b_clk, 17 | input wire b_en, 18 | input wire b_wr, 19 | input wire [ADDR-1:0] b_addr, 20 | input wire [DATA-1:0] b_din, 21 | output wire [DATA-1:0] b_dout 22 | 23 | 24 | ); 25 | 26 | 27 | dpbram cpuram ( 28 | .clock_a(a_clk), // input clka 29 | .rden_a(a_en), // input ena 30 | .wren_a(a_wr), // input [0 : 0] wea 31 | .address_a(a_addr), // input [14 : 0] addra 32 | .data_a(a_din), // input [7 : 0] dina 33 | .q_a(a_dout), // output [7 : 0] douta 34 | .clock_b(b_clk), // input clkb 35 | .rden_b(b_en), // input enb 36 | .wren_b(b_wr), // input [0 : 0] web 37 | .address_b(b_addr), // input [14 : 0] addrb 38 | .data_b(b_din), // input [7 : 0] dinb 39 | .q_b(b_dout) // output [7 : 0] doutb 40 | ); 41 | 42 | endmodule -------------------------------------------------------------------------------- /devboards/DE1-SoC/clk.v: -------------------------------------------------------------------------------- 1 | module clk( 2 | input CLK_IN1, 3 | output CLK_OUT1, 4 | output CLK_OUT2, 5 | output CLK_OUT3, 6 | output CLK_OUT4, 7 | output LOCKED, 8 | input RESET 9 | ); 10 | 11 | pll pll_clk(.rst(RESET), 12 | .refclk(CLK_IN1), 13 | .outclk_0(CLK_OUT1), 14 | .outclk_1(CLK_OUT2), 15 | .outclk_2(CLK_OUT3), 16 | .outclk_3(CLK_OUT4), 17 | .locked(LOCKED) 18 | ); 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/cpuroma.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cpuroma.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cpuroma_bb.v"] 6 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/cpuroma.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: cpuroma.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 15.0.0 Build 145 04/22/2015 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module cpuroma ( 41 | address, 42 | clock, 43 | rden, 44 | q); 45 | 46 | input [9:0] address; 47 | input clock; 48 | input rden; 49 | output [7:0] q; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_off 52 | `endif 53 | tri1 clock; 54 | tri1 rden; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [7:0] sub_wire0; 60 | wire [7:0] q = sub_wire0[7:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .rden_a (rden), 66 | .q_a (sub_wire0), 67 | .aclr0 (1'b0), 68 | .aclr1 (1'b0), 69 | .address_b (1'b1), 70 | .addressstall_a (1'b0), 71 | .addressstall_b (1'b0), 72 | .byteena_a (1'b1), 73 | .byteena_b (1'b1), 74 | .clock1 (1'b1), 75 | .clocken0 (1'b1), 76 | .clocken1 (1'b1), 77 | .clocken2 (1'b1), 78 | .clocken3 (1'b1), 79 | .data_a ({8{1'b1}}), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_b (1'b1), 84 | .wren_a (1'b0), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.address_aclr_a = "NONE", 88 | altsyncram_component.clock_enable_input_a = "BYPASS", 89 | altsyncram_component.clock_enable_output_a = "BYPASS", 90 | altsyncram_component.init_file = "../src6809/img.mif", 91 | altsyncram_component.intended_device_family = "Cyclone V", 92 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 93 | altsyncram_component.lpm_type = "altsyncram", 94 | altsyncram_component.numwords_a = 1024, 95 | altsyncram_component.operation_mode = "ROM", 96 | altsyncram_component.outdata_aclr_a = "NONE", 97 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 98 | altsyncram_component.widthad_a = 10, 99 | altsyncram_component.width_a = 8, 100 | altsyncram_component.width_byteena_a = 1; 101 | 102 | 103 | endmodule 104 | 105 | // ============================================================ 106 | // CNX file retrieval info 107 | // ============================================================ 108 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 109 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 112 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 114 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 115 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 118 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 119 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 120 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 121 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 122 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 123 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 124 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 125 | // Retrieval info: PRIVATE: MIFfilename STRING "../src6809/img.mif" 126 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" 127 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 128 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 129 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 130 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 131 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 132 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 133 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "10" 134 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 135 | // Retrieval info: PRIVATE: rden NUMERIC "1" 136 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 137 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 138 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 139 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 140 | // Retrieval info: CONSTANT: INIT_FILE STRING "../src6809/img.mif" 141 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 142 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 143 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 144 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" 145 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 146 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 147 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 148 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" 149 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 150 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 151 | // Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" 152 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 153 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 154 | // Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" 155 | // Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 156 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 157 | // Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 158 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.v TRUE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.inc FALSE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.cmp FALSE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.bsf FALSE 163 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma_inst.v FALSE 164 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma_bb.v TRUE 165 | // Retrieval info: LIB_FILE: altera_mf 166 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/demo.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Web Edition 22 | # Date created = 13:24:49 November 27, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.0" 27 | DATE = "13:24:49 November 27, 2016" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "alt_top" 32 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/dpbram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dpbram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpbram_bb.v"] 6 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/fontrom_glue.v: -------------------------------------------------------------------------------- 1 | module fontrom( 2 | input clka, 3 | input [10:0] addra, 4 | output [7:0] douta 5 | ); 6 | 7 | fontroma fontrom_glue( 8 | .address(addra), 9 | .clock(clka), 10 | .q(douta) 11 | ); 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/fontroma.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fontroma.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fontroma_bb.v"] 6 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/fontroma.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: fontroma.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 15.0.0 Build 145 04/22/2015 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module fontroma ( 41 | address, 42 | clock, 43 | q); 44 | 45 | input [11:0] address; 46 | input clock; 47 | output [7:0] q; 48 | `ifndef ALTERA_RESERVED_QIS 49 | // synopsys translate_off 50 | `endif 51 | tri1 clock; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_on 54 | `endif 55 | 56 | wire [7:0] sub_wire0; 57 | wire [7:0] q = sub_wire0[7:0]; 58 | 59 | altsyncram altsyncram_component ( 60 | .address_a (address), 61 | .clock0 (clock), 62 | .q_a (sub_wire0), 63 | .aclr0 (1'b0), 64 | .aclr1 (1'b0), 65 | .address_b (1'b1), 66 | .addressstall_a (1'b0), 67 | .addressstall_b (1'b0), 68 | .byteena_a (1'b1), 69 | .byteena_b (1'b1), 70 | .clock1 (1'b1), 71 | .clocken0 (1'b1), 72 | .clocken1 (1'b1), 73 | .clocken2 (1'b1), 74 | .clocken3 (1'b1), 75 | .data_a ({8{1'b1}}), 76 | .data_b (1'b1), 77 | .eccstatus (), 78 | .q_b (), 79 | .rden_a (1'b1), 80 | .rden_b (1'b1), 81 | .wren_a (1'b0), 82 | .wren_b (1'b0)); 83 | defparam 84 | altsyncram_component.address_aclr_a = "NONE", 85 | altsyncram_component.clock_enable_input_a = "BYPASS", 86 | altsyncram_component.clock_enable_output_a = "BYPASS", 87 | altsyncram_component.init_file = "../font.mif", 88 | altsyncram_component.intended_device_family = "Cyclone V", 89 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 90 | altsyncram_component.lpm_type = "altsyncram", 91 | altsyncram_component.numwords_a = 2112, 92 | altsyncram_component.operation_mode = "ROM", 93 | altsyncram_component.outdata_aclr_a = "NONE", 94 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 95 | altsyncram_component.widthad_a = 12, 96 | altsyncram_component.width_a = 8, 97 | altsyncram_component.width_byteena_a = 1; 98 | 99 | 100 | endmodule 101 | 102 | // ============================================================ 103 | // CNX file retrieval info 104 | // ============================================================ 105 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 108 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 110 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 111 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 114 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 115 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 116 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 117 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 118 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 119 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 120 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 121 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 122 | // Retrieval info: PRIVATE: MIFfilename STRING "../font.mif" 123 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2112" 124 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 125 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 126 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 127 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 128 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 129 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 130 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 131 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 132 | // Retrieval info: PRIVATE: rden NUMERIC "0" 133 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 134 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 137 | // Retrieval info: CONSTANT: INIT_FILE STRING "../font.mif" 138 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 139 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 140 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 141 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2112" 142 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 143 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 144 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 145 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 146 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 147 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 148 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 149 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 150 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 151 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 152 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 153 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.v TRUE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.inc FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.cmp FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.bsf FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma_inst.v FALSE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma_bb.v TRUE 160 | // Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/pll.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_pll" -name SPD_FILE [file join $::quartus(sip_path) "pll.spd"] 5 | 6 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /devboards/DE1-SoC/pll/pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'outclk2' 17 | output wire outclk_2, 18 | 19 | // interface 'outclk3' 20 | output wire outclk_3, 21 | 22 | // interface 'locked' 23 | output wire locked 24 | ); 25 | 26 | altera_pll #( 27 | .fractional_vco_multiplier("true"), 28 | .reference_clock_frequency("50.0 MHz"), 29 | .operation_mode("direct"), 30 | .number_of_clocks(4), 31 | .output_clock_frequency0("40.000000 MHz"), 32 | .phase_shift0("0 ps"), 33 | .duty_cycle0(50), 34 | .output_clock_frequency1("100.000000 MHz"), 35 | .phase_shift1("0 ps"), 36 | .duty_cycle1(50), 37 | .output_clock_frequency2("50.000000 MHz"), 38 | .phase_shift2("0 ps"), 39 | .duty_cycle2(50), 40 | .output_clock_frequency3("200.000000 MHz"), 41 | .phase_shift3("0 ps"), 42 | .duty_cycle3(50), 43 | .output_clock_frequency4("0 MHz"), 44 | .phase_shift4("0 ps"), 45 | .duty_cycle4(50), 46 | .output_clock_frequency5("0 MHz"), 47 | .phase_shift5("0 ps"), 48 | .duty_cycle5(50), 49 | .output_clock_frequency6("0 MHz"), 50 | .phase_shift6("0 ps"), 51 | .duty_cycle6(50), 52 | .output_clock_frequency7("0 MHz"), 53 | .phase_shift7("0 ps"), 54 | .duty_cycle7(50), 55 | .output_clock_frequency8("0 MHz"), 56 | .phase_shift8("0 ps"), 57 | .duty_cycle8(50), 58 | .output_clock_frequency9("0 MHz"), 59 | .phase_shift9("0 ps"), 60 | .duty_cycle9(50), 61 | .output_clock_frequency10("0 MHz"), 62 | .phase_shift10("0 ps"), 63 | .duty_cycle10(50), 64 | .output_clock_frequency11("0 MHz"), 65 | .phase_shift11("0 ps"), 66 | .duty_cycle11(50), 67 | .output_clock_frequency12("0 MHz"), 68 | .phase_shift12("0 ps"), 69 | .duty_cycle12(50), 70 | .output_clock_frequency13("0 MHz"), 71 | .phase_shift13("0 ps"), 72 | .duty_cycle13(50), 73 | .output_clock_frequency14("0 MHz"), 74 | .phase_shift14("0 ps"), 75 | .duty_cycle14(50), 76 | .output_clock_frequency15("0 MHz"), 77 | .phase_shift15("0 ps"), 78 | .duty_cycle15(50), 79 | .output_clock_frequency16("0 MHz"), 80 | .phase_shift16("0 ps"), 81 | .duty_cycle16(50), 82 | .output_clock_frequency17("0 MHz"), 83 | .phase_shift17("0 ps"), 84 | .duty_cycle17(50), 85 | .pll_type("General"), 86 | .pll_subtype("General") 87 | ) altera_pll_i ( 88 | .rst (rst), 89 | .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), 90 | .locked (locked), 91 | .fboutclk ( ), 92 | .fbclk (1'b0), 93 | .refclk (refclk) 94 | ); 95 | endmodule 96 | 97 | -------------------------------------------------------------------------------- /devboards/EP4CE6/.gitignore: -------------------------------------------------------------------------------- 1 | *.ddb 2 | 3 | -------------------------------------------------------------------------------- /devboards/EP4CE6/CPUROM.v: -------------------------------------------------------------------------------- 1 | module CPUROM( 2 | input clka, 3 | input ena, 4 | input [9:0] addra, 5 | output [7:0] douta 6 | ); 7 | 8 | cpuroma cpurom_glue(.address(addra), 9 | .clock(clka), 10 | .rden(ena), 11 | .q(douta) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /devboards/EP4CE6/alt_top.v: -------------------------------------------------------------------------------- 1 | module alt_top( 2 | input OSCCLK, 3 | output hsync, 4 | output vsync, 5 | output [2:0] red, 6 | output [2:0] green, 7 | output [1:0] blue, 8 | 9 | output [7:0] sseg, 10 | output [3:0] an, 11 | 12 | input ps2_clk, 13 | input ps2_data 14 | ); 15 | 16 | wire [7:0] wr; 17 | wire [7:0] wg; 18 | wire [7:0] wb; 19 | 20 | assign red = wr[7:5]; 21 | assign green = wg[7:5]; 22 | assign blue = wb[7:6]; 23 | 24 | demo_root alt_map( 25 | .OSCCLK(OSCCLK), 26 | .hsync(hsync), 27 | .vsync(vsync), 28 | .red(wr), 29 | .green(wg), 30 | .blue(wb), 31 | .sseg(sseg), 32 | .an(an), 33 | .ps2_clk(ps2_clk), 34 | .ps2_data(ps2_data) 35 | ); 36 | 37 | 38 | endmodule 39 | 40 | -------------------------------------------------------------------------------- /devboards/EP4CE6/bram.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module bram #( 4 | parameter DATA=8, 5 | parameter ADDR=13 6 | ) ( 7 | // Port A 8 | input wire a_clk, 9 | input wire a_en, 10 | input wire a_wr, 11 | input wire [ADDR-1:0] a_addr, 12 | input wire [DATA-1:0] a_din, 13 | output reg [DATA-1:0] a_dout, 14 | 15 | // Port B 16 | input wire b_clk, 17 | input wire b_en, 18 | input wire b_wr, 19 | input wire [ADDR-1:0] b_addr, 20 | input wire [DATA-1:0] b_din, 21 | output reg [DATA-1:0] b_dout 22 | 23 | 24 | ); 25 | 26 | // Shared memory 27 | reg [DATA-1:0] mem [(2**ADDR)-1:0]; 28 | 29 | 30 | // Port A 31 | always @(posedge a_clk) 32 | begin 33 | if (a_en) 34 | begin 35 | a_dout <= mem[a_addr]; 36 | if (a_wr) 37 | begin 38 | a_dout <= a_din; 39 | mem[a_addr] <= a_din; 40 | end 41 | end 42 | end 43 | 44 | // Port B 45 | always @(posedge b_clk) 46 | begin 47 | if (b_en) 48 | begin 49 | b_dout <= mem[b_addr]; 50 | if (b_wr) 51 | begin 52 | b_dout <= b_din; 53 | mem[b_addr] <= b_din; 54 | end 55 | end 56 | end 57 | 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /devboards/EP4CE6/clk.v: -------------------------------------------------------------------------------- 1 | module clk( 2 | input CLK_IN1, 3 | output CLK_OUT1, 4 | output CLK_OUT2, 5 | output CLK_OUT3, 6 | output CLK_OUT4, 7 | output LOCKED, 8 | input RESET 9 | ); 10 | 11 | pll pll_clk(.areset(RESET), 12 | .inclk0(CLK_IN1), 13 | .c0(CLK_OUT1), 14 | .c1(CLK_OUT2), 15 | .c2(CLK_OUT3), 16 | .c3(CLK_OUT4), 17 | .locked(LOCKED) 18 | ); 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /devboards/EP4CE6/cpuroma.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cpuroma.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cpuroma_bb.v"] 6 | -------------------------------------------------------------------------------- /devboards/EP4CE6/cpuroma.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: cpuroma.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 15.0.0 Build 145 04/22/2015 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module cpuroma ( 41 | address, 42 | clock, 43 | rden, 44 | q); 45 | 46 | input [9:0] address; 47 | input clock; 48 | input rden; 49 | output [7:0] q; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_off 52 | `endif 53 | tri1 clock; 54 | tri1 rden; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [7:0] sub_wire0; 60 | wire [7:0] q = sub_wire0[7:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .rden_a (rden), 66 | .q_a (sub_wire0), 67 | .aclr0 (1'b0), 68 | .aclr1 (1'b0), 69 | .address_b (1'b1), 70 | .addressstall_a (1'b0), 71 | .addressstall_b (1'b0), 72 | .byteena_a (1'b1), 73 | .byteena_b (1'b1), 74 | .clock1 (1'b1), 75 | .clocken0 (1'b1), 76 | .clocken1 (1'b1), 77 | .clocken2 (1'b1), 78 | .clocken3 (1'b1), 79 | .data_a ({8{1'b1}}), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_b (1'b1), 84 | .wren_a (1'b0), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.address_aclr_a = "NONE", 88 | altsyncram_component.clock_enable_input_a = "BYPASS", 89 | altsyncram_component.clock_enable_output_a = "BYPASS", 90 | altsyncram_component.init_file = "../src6809/img.mif", 91 | altsyncram_component.intended_device_family = "Cyclone IV E", 92 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 93 | altsyncram_component.lpm_type = "altsyncram", 94 | altsyncram_component.numwords_a = 1024, 95 | altsyncram_component.operation_mode = "ROM", 96 | altsyncram_component.outdata_aclr_a = "NONE", 97 | altsyncram_component.outdata_reg_a = "CLOCK0", 98 | altsyncram_component.widthad_a = 10, 99 | altsyncram_component.width_a = 8, 100 | altsyncram_component.width_byteena_a = 1; 101 | 102 | 103 | endmodule 104 | 105 | // ============================================================ 106 | // CNX file retrieval info 107 | // ============================================================ 108 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 109 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 112 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 114 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 115 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 118 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 119 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 120 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 121 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 122 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 123 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 124 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 125 | // Retrieval info: PRIVATE: MIFfilename STRING "../src6809/img.mif" 126 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" 127 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 128 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 129 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 130 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 131 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 132 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 133 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "10" 134 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 135 | // Retrieval info: PRIVATE: rden NUMERIC "1" 136 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 137 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 138 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 139 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 140 | // Retrieval info: CONSTANT: INIT_FILE STRING "../src6809/img.mif" 141 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 142 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 143 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 144 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" 145 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 146 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 147 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 148 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" 149 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 150 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 151 | // Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" 152 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 153 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 154 | // Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" 155 | // Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 156 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 157 | // Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 158 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.v TRUE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.inc FALSE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.cmp FALSE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma.bsf FALSE 163 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma_inst.v FALSE 164 | // Retrieval info: GEN_FILE: TYPE_NORMAL cpuroma_bb.v TRUE 165 | // Retrieval info: LIB_FILE: altera_mf 166 | -------------------------------------------------------------------------------- /devboards/EP4CE6/demo.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Web Edition 22 | # Date created = 20:59:36 November 18, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.0" 27 | DATE = "20:59:36 November 18, 2016" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "demo_root" 32 | -------------------------------------------------------------------------------- /devboards/EP4CE6/demo_root.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Web Edition 22 | # Date created = 20:59:36 November 18, 2016 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # demo_root_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone IV E" 41 | set_global_assignment -name DEVICE EP4CE6E22C8 42 | set_global_assignment -name TOP_LEVEL_ENTITY alt_top 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:59:36 NOVEMBER 18, 2016" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 50 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 51 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 52 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 53 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 54 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 55 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 56 | set_location_assignment PIN_91 -to OSCCLK 57 | set_location_assignment PIN_11 -to an[3] 58 | set_location_assignment PIN_10 -to an[2] 59 | set_location_assignment PIN_138 -to an[1] 60 | set_location_assignment PIN_137 -to an[0] 61 | set_location_assignment PIN_129 -to blue[1] 62 | set_location_assignment PIN_128 -to blue[0] 63 | set_location_assignment PIN_126 -to green[1] 64 | set_location_assignment PIN_125 -to green[0] 65 | set_location_assignment PIN_121 -to red[1] 66 | set_location_assignment PIN_120 -to red[0] 67 | set_location_assignment PIN_114 -to sseg[7] 68 | set_location_assignment PIN_142 -to sseg[6] 69 | set_location_assignment PIN_143 -to sseg[5] 70 | set_location_assignment PIN_144 -to sseg[4] 71 | set_location_assignment PIN_1 -to sseg[3] 72 | set_location_assignment PIN_2 -to sseg[2] 73 | set_location_assignment PIN_3 -to sseg[1] 74 | set_location_assignment PIN_7 -to sseg[0] 75 | set_location_assignment PIN_133 -to hsync 76 | set_location_assignment PIN_132 -to vsync 77 | set_location_assignment PIN_88 -to ps2_clk 78 | set_location_assignment PIN_119 -to ps2_data 79 | set_location_assignment PIN_127 -to green[2] 80 | set_location_assignment PIN_124 -to red[2] 81 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 82 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 83 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 84 | set_global_assignment -name ENABLE_SIGNALTAP OFF 85 | set_global_assignment -name VERILOG_FILE ../sseg.v 86 | set_global_assignment -name VERILOG_FILE alt_top.v 87 | set_global_assignment -name VERILOG_FILE CPUROM.v 88 | set_global_assignment -name VERILOG_FILE fontrom_glue.v 89 | set_global_assignment -name VERILOG_FILE clk.v 90 | set_global_assignment -name VERILOG_FILE ../../mc6809i.v 91 | set_global_assignment -name VERILOG_FILE ../../mc6809.v 92 | set_global_assignment -name VERILOG_FILE ../vga.v 93 | set_global_assignment -name VERILOG_FILE ../simplefifo.v 94 | set_global_assignment -name VERILOG_FILE ../ps2_communication.v 95 | set_global_assignment -name VERILOG_FILE ../demo_root.v 96 | set_global_assignment -name VERILOG_FILE bram.v 97 | set_global_assignment -name QIP_FILE pll.qip 98 | set_global_assignment -name QIP_FILE fontroma.qip 99 | set_global_assignment -name QIP_FILE cpuroma.qip 100 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 101 | -------------------------------------------------------------------------------- /devboards/EP4CE6/fontrom_glue.v: -------------------------------------------------------------------------------- 1 | module fontrom( 2 | input clka, 3 | input [10:0] addra, 4 | output [7:0] douta 5 | ); 6 | 7 | fontroma fontrom_glue( 8 | .address(addra), 9 | .clock(clka), 10 | .q(douta) 11 | ); 12 | 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /devboards/EP4CE6/fontroma.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fontroma.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fontroma_bb.v"] 6 | -------------------------------------------------------------------------------- /devboards/EP4CE6/fontroma.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: fontroma.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 15.0.0 Build 145 04/22/2015 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module fontroma ( 41 | address, 42 | clock, 43 | q); 44 | 45 | input [11:0] address; 46 | input clock; 47 | output [7:0] q; 48 | `ifndef ALTERA_RESERVED_QIS 49 | // synopsys translate_off 50 | `endif 51 | tri1 clock; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_on 54 | `endif 55 | 56 | wire [7:0] sub_wire0; 57 | wire [7:0] q = sub_wire0[7:0]; 58 | 59 | altsyncram altsyncram_component ( 60 | .address_a (address), 61 | .clock0 (clock), 62 | .q_a (sub_wire0), 63 | .aclr0 (1'b0), 64 | .aclr1 (1'b0), 65 | .address_b (1'b1), 66 | .addressstall_a (1'b0), 67 | .addressstall_b (1'b0), 68 | .byteena_a (1'b1), 69 | .byteena_b (1'b1), 70 | .clock1 (1'b1), 71 | .clocken0 (1'b1), 72 | .clocken1 (1'b1), 73 | .clocken2 (1'b1), 74 | .clocken3 (1'b1), 75 | .data_a ({8{1'b1}}), 76 | .data_b (1'b1), 77 | .eccstatus (), 78 | .q_b (), 79 | .rden_a (1'b1), 80 | .rden_b (1'b1), 81 | .wren_a (1'b0), 82 | .wren_b (1'b0)); 83 | defparam 84 | altsyncram_component.address_aclr_a = "NONE", 85 | altsyncram_component.clock_enable_input_a = "BYPASS", 86 | altsyncram_component.clock_enable_output_a = "BYPASS", 87 | altsyncram_component.init_file = "../font.mif", 88 | altsyncram_component.intended_device_family = "Cyclone IV E", 89 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 90 | altsyncram_component.lpm_type = "altsyncram", 91 | altsyncram_component.numwords_a = 2200, 92 | altsyncram_component.operation_mode = "ROM", 93 | altsyncram_component.outdata_aclr_a = "NONE", 94 | altsyncram_component.outdata_reg_a = "CLOCK0", 95 | altsyncram_component.widthad_a = 12, 96 | altsyncram_component.width_a = 8, 97 | altsyncram_component.width_byteena_a = 1; 98 | 99 | 100 | endmodule 101 | 102 | // ============================================================ 103 | // CNX file retrieval info 104 | // ============================================================ 105 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 108 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 110 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 111 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 114 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 115 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 116 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 117 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 118 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 119 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 120 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 121 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 122 | // Retrieval info: PRIVATE: MIFfilename STRING "../font.mif" 123 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2200" 124 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 125 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 126 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 127 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 128 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 129 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 130 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 131 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 132 | // Retrieval info: PRIVATE: rden NUMERIC "0" 133 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 134 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 137 | // Retrieval info: CONSTANT: INIT_FILE STRING "../font.mif" 138 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 139 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 140 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 141 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2200" 142 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 143 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 144 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 145 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 146 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 147 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 148 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 149 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 150 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 151 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 152 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 153 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.v TRUE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.inc FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.cmp FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma.bsf FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma_inst.v TRUE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL fontroma_bb.v TRUE 160 | // Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /devboards/EP4CE6/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "15.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 8 | -------------------------------------------------------------------------------- /devboards/LX9/.gitignore: -------------------------------------------------------------------------------- 1 | *.bgn 2 | *.bld 3 | *.cmd_log 4 | *.csv 5 | *.drc 6 | *.gise 7 | *.lso 8 | *.map 9 | *.mrp 10 | *.ncd 11 | *.ngc 12 | *.ngm 13 | *.ngr 14 | *.pad 15 | *.par 16 | *.prj 17 | *.ptwx 18 | *.stx 19 | *.syr 20 | *.twr 21 | *.twx 22 | *.txt 23 | *.unroutes 24 | *.ut 25 | *.xpi 26 | *.xst 27 | *.xwbt 28 | *.html 29 | *.xrpt 30 | *.xml 31 | _ 32 | -------------------------------------------------------------------------------- /devboards/LX9/W25Q64BV.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/devboards/LX9/W25Q64BV.pdf -------------------------------------------------------------------------------- /devboards/LX9/bram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:33:44 11/25/2016 7 | // Design Name: 8 | // Module Name: bram 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module bram # ( 22 | parameter DATA=8, 23 | parameter ADDR=15 24 | )( 25 | // Port A 26 | input wire a_clk, 27 | input wire a_en, 28 | input wire a_wr, 29 | input wire [ADDR-1:0] a_addr, 30 | input wire [DATA-1:0] a_din, 31 | output wire [DATA-1:0] a_dout, 32 | 33 | // Port B 34 | input wire b_clk, 35 | input wire b_en, 36 | input wire b_wr, 37 | input wire [ADDR-1:0] b_addr, 38 | input wire [DATA-1:0] b_din, 39 | output wire [DATA-1:0] b_dout 40 | 41 | 42 | ); 43 | 44 | dpbram cpuram ( 45 | .clka(a_clk), // input clka 46 | .ena(a_en), // input ena 47 | .wea(a_wr), // input [0 : 0] wea 48 | .addra(a_addr), // input [14 : 0] addra 49 | .dina(a_din), // input [7 : 0] dina 50 | .douta(a_dout), // output [7 : 0] douta 51 | .clkb(b_clk), // input clkb 52 | .enb(b_en), // input enb 53 | .web(b_wr), // input [0 : 0] web 54 | .addrb(b_addr), // input [14 : 0] addrb 55 | .dinb(b_din), // input [7 : 0] dinb 56 | .doutb(b_dout) // output [7 : 0] doutb 57 | ); 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /devboards/LX9/demo/.gitignore: -------------------------------------------------------------------------------- 1 | *.bgn 2 | *.bld 3 | *.cmd_log 4 | *.csv 5 | *.drc 6 | *.gise 7 | *.lso 8 | *.map 9 | *.mrp 10 | *.ncd 11 | *.ngc 12 | *.ngm 13 | *.ngr 14 | *.pad 15 | *.par 16 | *.prj 17 | *.ptwx 18 | *.stx 19 | *.syr 20 | *.twr 21 | *.twx 22 | *.txt 23 | *.unroutes 24 | *.ut 25 | *.xpi 26 | *.xst 27 | *.xwbt 28 | *.html 29 | *.xrpt 30 | *.xml 31 | _ 32 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/.gitignore: -------------------------------------------------------------------------------- 1 | *.bgn 2 | *.bld 3 | *.cmd_log 4 | *.csv 5 | *.drc 6 | *.gise 7 | *.lso 8 | *.map 9 | *.mrp 10 | *.ncd 11 | *.ngm 12 | *.ngr 13 | *.pad 14 | *.par 15 | *.prj 16 | *.ptwx 17 | *.stx 18 | *.syr 19 | *.twr 20 | *.twx 21 | *.txt 22 | *.unroutes 23 | *.ut 24 | *.xpi 25 | *.xst 26 | *.xwbt 27 | *.html 28 | *.xrpt 29 | *.xml 30 | _ 31 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/CPUROM.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2016 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | // You must compile the wrapper file CPUROM.v when simulating 29 | // the core, CPUROM. When compiling the wrapper file, be sure to 30 | // reference the XilinxCoreLib Verilog simulation library. For detailed 31 | // instructions, please refer to the "CORE Generator Help". 32 | 33 | // The synthesis directives "translate_off/translate_on" specified below are 34 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 35 | // tools. Ensure they are correct for your synthesis tool(s). 36 | 37 | `timescale 1ns/1ps 38 | 39 | module CPUROM( 40 | clka, 41 | ena, 42 | addra, 43 | douta 44 | ); 45 | 46 | input clka; 47 | input ena; 48 | input [9 : 0] addra; 49 | output [7 : 0] douta; 50 | 51 | // synthesis translate_off 52 | 53 | BLK_MEM_GEN_V7_3 #( 54 | .C_ADDRA_WIDTH(10), 55 | .C_ADDRB_WIDTH(10), 56 | .C_ALGORITHM(1), 57 | .C_AXI_ID_WIDTH(4), 58 | .C_AXI_SLAVE_TYPE(0), 59 | .C_AXI_TYPE(1), 60 | .C_BYTE_SIZE(9), 61 | .C_COMMON_CLK(0), 62 | .C_DEFAULT_DATA("0"), 63 | .C_DISABLE_WARN_BHV_COLL(0), 64 | .C_DISABLE_WARN_BHV_RANGE(0), 65 | .C_ENABLE_32BIT_ADDRESS(0), 66 | .C_FAMILY("spartan6"), 67 | .C_HAS_AXI_ID(0), 68 | .C_HAS_ENA(1), 69 | .C_HAS_ENB(0), 70 | .C_HAS_INJECTERR(0), 71 | .C_HAS_MEM_OUTPUT_REGS_A(0), 72 | .C_HAS_MEM_OUTPUT_REGS_B(0), 73 | .C_HAS_MUX_OUTPUT_REGS_A(0), 74 | .C_HAS_MUX_OUTPUT_REGS_B(0), 75 | .C_HAS_REGCEA(0), 76 | .C_HAS_REGCEB(0), 77 | .C_HAS_RSTA(0), 78 | .C_HAS_RSTB(0), 79 | .C_HAS_SOFTECC_INPUT_REGS_A(0), 80 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), 81 | .C_INIT_FILE("BlankString"), 82 | .C_INIT_FILE_NAME("CPUROM.mif"), 83 | .C_INITA_VAL("0"), 84 | .C_INITB_VAL("0"), 85 | .C_INTERFACE_TYPE(0), 86 | .C_LOAD_INIT_FILE(1), 87 | .C_MEM_TYPE(3), 88 | .C_MUX_PIPELINE_STAGES(0), 89 | .C_PRIM_TYPE(1), 90 | .C_READ_DEPTH_A(1024), 91 | .C_READ_DEPTH_B(1024), 92 | .C_READ_WIDTH_A(8), 93 | .C_READ_WIDTH_B(8), 94 | .C_RST_PRIORITY_A("CE"), 95 | .C_RST_PRIORITY_B("CE"), 96 | .C_RST_TYPE("SYNC"), 97 | .C_RSTRAM_A(0), 98 | .C_RSTRAM_B(0), 99 | .C_SIM_COLLISION_CHECK("ALL"), 100 | .C_USE_BRAM_BLOCK(0), 101 | .C_USE_BYTE_WEA(0), 102 | .C_USE_BYTE_WEB(0), 103 | .C_USE_DEFAULT_DATA(0), 104 | .C_USE_ECC(0), 105 | .C_USE_SOFTECC(0), 106 | .C_WEA_WIDTH(1), 107 | .C_WEB_WIDTH(1), 108 | .C_WRITE_DEPTH_A(1024), 109 | .C_WRITE_DEPTH_B(1024), 110 | .C_WRITE_MODE_A("WRITE_FIRST"), 111 | .C_WRITE_MODE_B("WRITE_FIRST"), 112 | .C_WRITE_WIDTH_A(8), 113 | .C_WRITE_WIDTH_B(8), 114 | .C_XDEVICEFAMILY("spartan6") 115 | ) 116 | inst ( 117 | .CLKA(clka), 118 | .ENA(ena), 119 | .ADDRA(addra), 120 | .DOUTA(douta), 121 | .RSTA(), 122 | .REGCEA(), 123 | .WEA(), 124 | .DINA(), 125 | .CLKB(), 126 | .RSTB(), 127 | .ENB(), 128 | .REGCEB(), 129 | .WEB(), 130 | .ADDRB(), 131 | .DINB(), 132 | .DOUTB(), 133 | .INJECTSBITERR(), 134 | .INJECTDBITERR(), 135 | .SBITERR(), 136 | .DBITERR(), 137 | .RDADDRECC(), 138 | .S_ACLK(), 139 | .S_ARESETN(), 140 | .S_AXI_AWID(), 141 | .S_AXI_AWADDR(), 142 | .S_AXI_AWLEN(), 143 | .S_AXI_AWSIZE(), 144 | .S_AXI_AWBURST(), 145 | .S_AXI_AWVALID(), 146 | .S_AXI_AWREADY(), 147 | .S_AXI_WDATA(), 148 | .S_AXI_WSTRB(), 149 | .S_AXI_WLAST(), 150 | .S_AXI_WVALID(), 151 | .S_AXI_WREADY(), 152 | .S_AXI_BID(), 153 | .S_AXI_BRESP(), 154 | .S_AXI_BVALID(), 155 | .S_AXI_BREADY(), 156 | .S_AXI_ARID(), 157 | .S_AXI_ARADDR(), 158 | .S_AXI_ARLEN(), 159 | .S_AXI_ARSIZE(), 160 | .S_AXI_ARBURST(), 161 | .S_AXI_ARVALID(), 162 | .S_AXI_ARREADY(), 163 | .S_AXI_RID(), 164 | .S_AXI_RDATA(), 165 | .S_AXI_RRESP(), 166 | .S_AXI_RLAST(), 167 | .S_AXI_RVALID(), 168 | .S_AXI_RREADY(), 169 | .S_AXI_INJECTSBITERR(), 170 | .S_AXI_INJECTDBITERR(), 171 | .S_AXI_SBITERR(), 172 | .S_AXI_DBITERR(), 173 | .S_AXI_RDADDRECC() 174 | ); 175 | 176 | // synthesis translate_on 177 | 178 | endmodule 179 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/CPUROM.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Sat Nov 26 03:31:51 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:blk_mem_gen:7.3 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx9 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = tqg144 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 40 | # END Select 41 | # BEGIN Parameters 42 | CSET additional_inputs_for_power_estimation=false 43 | CSET algorithm=Minimum_Area 44 | CSET assume_synchronous_clk=false 45 | CSET axi_id_width=4 46 | CSET axi_slave_type=Memory_Slave 47 | CSET axi_type=AXI4_Full 48 | CSET byte_size=9 49 | CSET coe_file=C:\Users\gmiller\OneDrive\mcm6809\DevBoards\src6809\img.coe 50 | CSET collision_warnings=ALL 51 | CSET component_name=CPUROM 52 | CSET disable_collision_warnings=false 53 | CSET disable_out_of_range_warnings=false 54 | CSET ecc=false 55 | CSET ecctype=No_ECC 56 | CSET enable_32bit_address=false 57 | CSET enable_a=Use_ENA_Pin 58 | CSET enable_b=Always_Enabled 59 | CSET error_injection_type=Single_Bit_Error_Injection 60 | CSET fill_remaining_memory_locations=false 61 | CSET interface_type=Native 62 | CSET load_init_file=true 63 | CSET mem_file=no_Mem_file_loaded 64 | CSET memory_type=Single_Port_ROM 65 | CSET operating_mode_a=WRITE_FIRST 66 | CSET operating_mode_b=WRITE_FIRST 67 | CSET output_reset_value_a=0 68 | CSET output_reset_value_b=0 69 | CSET pipeline_stages=0 70 | CSET port_a_clock=100 71 | CSET port_a_enable_rate=100 72 | CSET port_a_write_rate=0 73 | CSET port_b_clock=0 74 | CSET port_b_enable_rate=0 75 | CSET port_b_write_rate=0 76 | CSET primitive=8kx2 77 | CSET read_width_a=8 78 | CSET read_width_b=8 79 | CSET register_porta_input_of_softecc=false 80 | CSET register_porta_output_of_memory_core=false 81 | CSET register_porta_output_of_memory_primitives=false 82 | CSET register_portb_output_of_memory_core=false 83 | CSET register_portb_output_of_memory_primitives=false 84 | CSET register_portb_output_of_softecc=false 85 | CSET remaining_memory_locations=0 86 | CSET reset_memory_latch_a=false 87 | CSET reset_memory_latch_b=false 88 | CSET reset_priority_a=CE 89 | CSET reset_priority_b=CE 90 | CSET reset_type=SYNC 91 | CSET softecc=false 92 | CSET use_axi_id=false 93 | CSET use_bram_block=Stand_Alone 94 | CSET use_byte_write_enable=false 95 | CSET use_error_injection_pins=false 96 | CSET use_regcea_pin=false 97 | CSET use_regceb_pin=false 98 | CSET use_rsta_pin=false 99 | CSET use_rstb_pin=false 100 | CSET write_depth_a=1024 101 | CSET write_width_a=8 102 | CSET write_width_b=8 103 | # END Parameters 104 | # BEGIN Extra information 105 | MISC pkg_timestamp=2012-11-19T16:22:25Z 106 | # END Extra information 107 | GENERATE 108 | # CRC: 65e4d342 109 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/CPUROM.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/clk.ucf: -------------------------------------------------------------------------------- 1 | # file: clk.ucf 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system 52 | #---------------------------------------------------------------- 53 | NET "CLK_IN1" TNM_NET = "CLK_IN1"; 54 | TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; 55 | 56 | 57 | # FALSE PATH constraints 58 | PIN "RESET" TIG; 59 | 60 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/clk.v: -------------------------------------------------------------------------------- 1 | // file: clk.v 2 | // 3 | // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // "Output Output Phase Duty Pk-to-Pk Phase" 56 | // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" 57 | //---------------------------------------------------------------------------- 58 | // CLK_OUT1____40.000______0.000______50.0______280.096____251.827 59 | // CLK_OUT2___100.000______0.000______50.0______231.478____251.827 60 | // CLK_OUT3____50.000______0.000______50.0______267.325____251.827 61 | // CLK_OUT4___200.000______0.000______50.0______204.071____251.827 62 | // 63 | //---------------------------------------------------------------------------- 64 | // "Input Clock Freq (MHz) Input Jitter (UI)" 65 | //---------------------------------------------------------------------------- 66 | // __primary_________50.0000____________0.010 67 | 68 | `timescale 1ps/1ps 69 | 70 | (* CORE_GENERATION_INFO = "clk,clk_wiz_v3_6,{component_name=clk,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) 71 | module clk 72 | (// Clock in ports 73 | input CLK_IN1, 74 | // Clock out ports 75 | output CLK_OUT1, 76 | output CLK_OUT2, 77 | output CLK_OUT3, 78 | output CLK_OUT4, 79 | // Status and control signals 80 | input RESET, 81 | output LOCKED 82 | ); 83 | 84 | // Input buffering 85 | //------------------------------------ 86 | IBUFG clkin1_buf 87 | (.O (clkin1), 88 | .I (CLK_IN1)); 89 | 90 | 91 | // Clocking primitive 92 | //------------------------------------ 93 | // Instantiation of the PLL primitive 94 | // * Unused inputs are tied off 95 | // * Unused outputs are labeled unused 96 | wire [15:0] do_unused; 97 | wire drdy_unused; 98 | wire clkfbout; 99 | wire clkfbout_buf; 100 | wire clkout4_unused; 101 | wire clkout5_unused; 102 | 103 | PLL_BASE 104 | #(.BANDWIDTH ("OPTIMIZED"), 105 | .CLK_FEEDBACK ("CLKFBOUT"), 106 | .COMPENSATION ("SYSTEM_SYNCHRONOUS"), 107 | .DIVCLK_DIVIDE (1), 108 | .CLKFBOUT_MULT (8), 109 | .CLKFBOUT_PHASE (0.000), 110 | .CLKOUT0_DIVIDE (10), 111 | .CLKOUT0_PHASE (0.000), 112 | .CLKOUT0_DUTY_CYCLE (0.500), 113 | .CLKOUT1_DIVIDE (4), 114 | .CLKOUT1_PHASE (0.000), 115 | .CLKOUT1_DUTY_CYCLE (0.500), 116 | .CLKOUT2_DIVIDE (8), 117 | .CLKOUT2_PHASE (0.000), 118 | .CLKOUT2_DUTY_CYCLE (0.500), 119 | .CLKOUT3_DIVIDE (2), 120 | .CLKOUT3_PHASE (0.000), 121 | .CLKOUT3_DUTY_CYCLE (0.500), 122 | .CLKIN_PERIOD (20.0), 123 | .REF_JITTER (0.010)) 124 | pll_base_inst 125 | // Output clocks 126 | (.CLKFBOUT (clkfbout), 127 | .CLKOUT0 (clkout0), 128 | .CLKOUT1 (clkout1), 129 | .CLKOUT2 (clkout2), 130 | .CLKOUT3 (clkout3), 131 | .CLKOUT4 (clkout4_unused), 132 | .CLKOUT5 (clkout5_unused), 133 | // Status and control signals 134 | .LOCKED (LOCKED), 135 | .RST (RESET), 136 | // Input clock control 137 | .CLKFBIN (clkfbout_buf), 138 | .CLKIN (clkin1)); 139 | 140 | 141 | // Output buffering 142 | //----------------------------------- 143 | BUFG clkf_buf 144 | (.O (clkfbout_buf), 145 | .I (clkfbout)); 146 | 147 | BUFG clkout1_buf 148 | (.O (CLK_OUT1), 149 | .I (clkout0)); 150 | 151 | 152 | BUFG clkout2_buf 153 | (.O (CLK_OUT2), 154 | .I (clkout1)); 155 | 156 | BUFG clkout3_buf 157 | (.O (CLK_OUT3), 158 | .I (clkout2)); 159 | 160 | BUFG clkout4_buf 161 | (.O (CLK_OUT4), 162 | .I (clkout3)); 163 | 164 | 165 | 166 | endmodule 167 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/clk.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/dpbram.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2016 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | // You must compile the wrapper file dpbram.v when simulating 29 | // the core, dpbram. When compiling the wrapper file, be sure to 30 | // reference the XilinxCoreLib Verilog simulation library. For detailed 31 | // instructions, please refer to the "CORE Generator Help". 32 | 33 | // The synthesis directives "translate_off/translate_on" specified below are 34 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 35 | // tools. Ensure they are correct for your synthesis tool(s). 36 | 37 | `timescale 1ns/1ps 38 | 39 | module dpbram( 40 | clka, 41 | ena, 42 | wea, 43 | addra, 44 | dina, 45 | douta, 46 | clkb, 47 | enb, 48 | web, 49 | addrb, 50 | dinb, 51 | doutb 52 | ); 53 | 54 | input clka; 55 | input ena; 56 | input [0 : 0] wea; 57 | input [14 : 0] addra; 58 | input [7 : 0] dina; 59 | output [7 : 0] douta; 60 | input clkb; 61 | input enb; 62 | input [0 : 0] web; 63 | input [14 : 0] addrb; 64 | input [7 : 0] dinb; 65 | output [7 : 0] doutb; 66 | 67 | // synthesis translate_off 68 | 69 | BLK_MEM_GEN_V7_3 #( 70 | .C_ADDRA_WIDTH(15), 71 | .C_ADDRB_WIDTH(15), 72 | .C_ALGORITHM(1), 73 | .C_AXI_ID_WIDTH(4), 74 | .C_AXI_SLAVE_TYPE(0), 75 | .C_AXI_TYPE(1), 76 | .C_BYTE_SIZE(9), 77 | .C_COMMON_CLK(0), 78 | .C_DEFAULT_DATA("0"), 79 | .C_DISABLE_WARN_BHV_COLL(0), 80 | .C_DISABLE_WARN_BHV_RANGE(0), 81 | .C_ENABLE_32BIT_ADDRESS(0), 82 | .C_FAMILY("spartan6"), 83 | .C_HAS_AXI_ID(0), 84 | .C_HAS_ENA(1), 85 | .C_HAS_ENB(1), 86 | .C_HAS_INJECTERR(0), 87 | .C_HAS_MEM_OUTPUT_REGS_A(0), 88 | .C_HAS_MEM_OUTPUT_REGS_B(0), 89 | .C_HAS_MUX_OUTPUT_REGS_A(0), 90 | .C_HAS_MUX_OUTPUT_REGS_B(0), 91 | .C_HAS_REGCEA(0), 92 | .C_HAS_REGCEB(0), 93 | .C_HAS_RSTA(0), 94 | .C_HAS_RSTB(0), 95 | .C_HAS_SOFTECC_INPUT_REGS_A(0), 96 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), 97 | .C_INIT_FILE("BlankString"), 98 | .C_INIT_FILE_NAME("dpbram.mif"), 99 | .C_INITA_VAL("0"), 100 | .C_INITB_VAL("0"), 101 | .C_INTERFACE_TYPE(0), 102 | .C_LOAD_INIT_FILE(1), 103 | .C_MEM_TYPE(2), 104 | .C_MUX_PIPELINE_STAGES(0), 105 | .C_PRIM_TYPE(1), 106 | .C_READ_DEPTH_A(32768), 107 | .C_READ_DEPTH_B(32768), 108 | .C_READ_WIDTH_A(8), 109 | .C_READ_WIDTH_B(8), 110 | .C_RST_PRIORITY_A("CE"), 111 | .C_RST_PRIORITY_B("CE"), 112 | .C_RST_TYPE("SYNC"), 113 | .C_RSTRAM_A(0), 114 | .C_RSTRAM_B(0), 115 | .C_SIM_COLLISION_CHECK("ALL"), 116 | .C_USE_BRAM_BLOCK(0), 117 | .C_USE_BYTE_WEA(0), 118 | .C_USE_BYTE_WEB(0), 119 | .C_USE_DEFAULT_DATA(0), 120 | .C_USE_ECC(0), 121 | .C_USE_SOFTECC(0), 122 | .C_WEA_WIDTH(1), 123 | .C_WEB_WIDTH(1), 124 | .C_WRITE_DEPTH_A(32768), 125 | .C_WRITE_DEPTH_B(32768), 126 | .C_WRITE_MODE_A("WRITE_FIRST"), 127 | .C_WRITE_MODE_B("WRITE_FIRST"), 128 | .C_WRITE_WIDTH_A(8), 129 | .C_WRITE_WIDTH_B(8), 130 | .C_XDEVICEFAMILY("spartan6") 131 | ) 132 | inst ( 133 | .CLKA(clka), 134 | .ENA(ena), 135 | .WEA(wea), 136 | .ADDRA(addra), 137 | .DINA(dina), 138 | .DOUTA(douta), 139 | .CLKB(clkb), 140 | .ENB(enb), 141 | .WEB(web), 142 | .ADDRB(addrb), 143 | .DINB(dinb), 144 | .DOUTB(doutb), 145 | .RSTA(), 146 | .REGCEA(), 147 | .RSTB(), 148 | .REGCEB(), 149 | .INJECTSBITERR(), 150 | .INJECTDBITERR(), 151 | .SBITERR(), 152 | .DBITERR(), 153 | .RDADDRECC(), 154 | .S_ACLK(), 155 | .S_ARESETN(), 156 | .S_AXI_AWID(), 157 | .S_AXI_AWADDR(), 158 | .S_AXI_AWLEN(), 159 | .S_AXI_AWSIZE(), 160 | .S_AXI_AWBURST(), 161 | .S_AXI_AWVALID(), 162 | .S_AXI_AWREADY(), 163 | .S_AXI_WDATA(), 164 | .S_AXI_WSTRB(), 165 | .S_AXI_WLAST(), 166 | .S_AXI_WVALID(), 167 | .S_AXI_WREADY(), 168 | .S_AXI_BID(), 169 | .S_AXI_BRESP(), 170 | .S_AXI_BVALID(), 171 | .S_AXI_BREADY(), 172 | .S_AXI_ARID(), 173 | .S_AXI_ARADDR(), 174 | .S_AXI_ARLEN(), 175 | .S_AXI_ARSIZE(), 176 | .S_AXI_ARBURST(), 177 | .S_AXI_ARVALID(), 178 | .S_AXI_ARREADY(), 179 | .S_AXI_RID(), 180 | .S_AXI_RDATA(), 181 | .S_AXI_RRESP(), 182 | .S_AXI_RLAST(), 183 | .S_AXI_RVALID(), 184 | .S_AXI_RREADY(), 185 | .S_AXI_INJECTSBITERR(), 186 | .S_AXI_INJECTDBITERR(), 187 | .S_AXI_SBITERR(), 188 | .S_AXI_DBITERR(), 189 | .S_AXI_RDADDRECC() 190 | ); 191 | 192 | // synthesis translate_on 193 | 194 | endmodule 195 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/dpbram.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Fri Nov 25 21:27:28 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:blk_mem_gen:7.3 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx9 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = tqg144 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 40 | # END Select 41 | # BEGIN Parameters 42 | CSET additional_inputs_for_power_estimation=false 43 | CSET algorithm=Minimum_Area 44 | CSET assume_synchronous_clk=false 45 | CSET axi_id_width=4 46 | CSET axi_slave_type=Memory_Slave 47 | CSET axi_type=AXI4_Full 48 | CSET byte_size=9 49 | CSET coe_file=C:\Users\gmiller\OneDrive\mcm6809\DevBoards\demo6809bins\bedlam.coe 50 | CSET collision_warnings=ALL 51 | CSET component_name=dpbram 52 | CSET disable_collision_warnings=false 53 | CSET disable_out_of_range_warnings=false 54 | CSET ecc=false 55 | CSET ecctype=No_ECC 56 | CSET enable_32bit_address=false 57 | CSET enable_a=Use_ENA_Pin 58 | CSET enable_b=Use_ENB_Pin 59 | CSET error_injection_type=Single_Bit_Error_Injection 60 | CSET fill_remaining_memory_locations=false 61 | CSET interface_type=Native 62 | CSET load_init_file=true 63 | CSET mem_file=no_Mem_file_loaded 64 | CSET memory_type=True_Dual_Port_RAM 65 | CSET operating_mode_a=WRITE_FIRST 66 | CSET operating_mode_b=WRITE_FIRST 67 | CSET output_reset_value_a=0 68 | CSET output_reset_value_b=0 69 | CSET pipeline_stages=0 70 | CSET port_a_clock=100 71 | CSET port_a_enable_rate=100 72 | CSET port_a_write_rate=50 73 | CSET port_b_clock=100 74 | CSET port_b_enable_rate=100 75 | CSET port_b_write_rate=50 76 | CSET primitive=8kx2 77 | CSET read_width_a=8 78 | CSET read_width_b=8 79 | CSET register_porta_input_of_softecc=false 80 | CSET register_porta_output_of_memory_core=false 81 | CSET register_porta_output_of_memory_primitives=false 82 | CSET register_portb_output_of_memory_core=false 83 | CSET register_portb_output_of_memory_primitives=false 84 | CSET register_portb_output_of_softecc=false 85 | CSET remaining_memory_locations=0 86 | CSET reset_memory_latch_a=false 87 | CSET reset_memory_latch_b=false 88 | CSET reset_priority_a=CE 89 | CSET reset_priority_b=CE 90 | CSET reset_type=SYNC 91 | CSET softecc=false 92 | CSET use_axi_id=false 93 | CSET use_bram_block=Stand_Alone 94 | CSET use_byte_write_enable=false 95 | CSET use_error_injection_pins=false 96 | CSET use_regcea_pin=false 97 | CSET use_regceb_pin=false 98 | CSET use_rsta_pin=false 99 | CSET use_rstb_pin=false 100 | CSET write_depth_a=32768 101 | CSET write_width_a=8 102 | CSET write_width_b=8 103 | # END Parameters 104 | # BEGIN Extra information 105 | MISC pkg_timestamp=2012-11-19T16:22:25Z 106 | # END Extra information 107 | GENERATE 108 | # CRC: f658df93 109 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/dpbram.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/fontrom.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2016 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | // You must compile the wrapper file fontrom.v when simulating 29 | // the core, fontrom. When compiling the wrapper file, be sure to 30 | // reference the XilinxCoreLib Verilog simulation library. For detailed 31 | // instructions, please refer to the "CORE Generator Help". 32 | 33 | // The synthesis directives "translate_off/translate_on" specified below are 34 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 35 | // tools. Ensure they are correct for your synthesis tool(s). 36 | 37 | `timescale 1ns/1ps 38 | 39 | module fontrom( 40 | clka, 41 | addra, 42 | douta 43 | ); 44 | 45 | input clka; 46 | input [11 : 0] addra; 47 | output [7 : 0] douta; 48 | 49 | // synthesis translate_off 50 | 51 | BLK_MEM_GEN_V7_3 #( 52 | .C_ADDRA_WIDTH(12), 53 | .C_ADDRB_WIDTH(12), 54 | .C_ALGORITHM(1), 55 | .C_AXI_ID_WIDTH(4), 56 | .C_AXI_SLAVE_TYPE(0), 57 | .C_AXI_TYPE(1), 58 | .C_BYTE_SIZE(9), 59 | .C_COMMON_CLK(0), 60 | .C_DEFAULT_DATA("0"), 61 | .C_DISABLE_WARN_BHV_COLL(0), 62 | .C_DISABLE_WARN_BHV_RANGE(0), 63 | .C_ENABLE_32BIT_ADDRESS(0), 64 | .C_FAMILY("spartan6"), 65 | .C_HAS_AXI_ID(0), 66 | .C_HAS_ENA(0), 67 | .C_HAS_ENB(0), 68 | .C_HAS_INJECTERR(0), 69 | .C_HAS_MEM_OUTPUT_REGS_A(0), 70 | .C_HAS_MEM_OUTPUT_REGS_B(0), 71 | .C_HAS_MUX_OUTPUT_REGS_A(0), 72 | .C_HAS_MUX_OUTPUT_REGS_B(0), 73 | .C_HAS_REGCEA(0), 74 | .C_HAS_REGCEB(0), 75 | .C_HAS_RSTA(0), 76 | .C_HAS_RSTB(0), 77 | .C_HAS_SOFTECC_INPUT_REGS_A(0), 78 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), 79 | .C_INIT_FILE("BlankString"), 80 | .C_INIT_FILE_NAME("fontrom.mif"), 81 | .C_INITA_VAL("0"), 82 | .C_INITB_VAL("0"), 83 | .C_INTERFACE_TYPE(0), 84 | .C_LOAD_INIT_FILE(1), 85 | .C_MEM_TYPE(3), 86 | .C_MUX_PIPELINE_STAGES(0), 87 | .C_PRIM_TYPE(1), 88 | .C_READ_DEPTH_A(2200), 89 | .C_READ_DEPTH_B(2200), 90 | .C_READ_WIDTH_A(8), 91 | .C_READ_WIDTH_B(8), 92 | .C_RST_PRIORITY_A("CE"), 93 | .C_RST_PRIORITY_B("CE"), 94 | .C_RST_TYPE("SYNC"), 95 | .C_RSTRAM_A(0), 96 | .C_RSTRAM_B(0), 97 | .C_SIM_COLLISION_CHECK("ALL"), 98 | .C_USE_BRAM_BLOCK(0), 99 | .C_USE_BYTE_WEA(0), 100 | .C_USE_BYTE_WEB(0), 101 | .C_USE_DEFAULT_DATA(0), 102 | .C_USE_ECC(0), 103 | .C_USE_SOFTECC(0), 104 | .C_WEA_WIDTH(1), 105 | .C_WEB_WIDTH(1), 106 | .C_WRITE_DEPTH_A(2200), 107 | .C_WRITE_DEPTH_B(2200), 108 | .C_WRITE_MODE_A("WRITE_FIRST"), 109 | .C_WRITE_MODE_B("WRITE_FIRST"), 110 | .C_WRITE_WIDTH_A(8), 111 | .C_WRITE_WIDTH_B(8), 112 | .C_XDEVICEFAMILY("spartan6") 113 | ) 114 | inst ( 115 | .CLKA(clka), 116 | .ADDRA(addra), 117 | .DOUTA(douta), 118 | .RSTA(), 119 | .ENA(), 120 | .REGCEA(), 121 | .WEA(), 122 | .DINA(), 123 | .CLKB(), 124 | .RSTB(), 125 | .ENB(), 126 | .REGCEB(), 127 | .WEB(), 128 | .ADDRB(), 129 | .DINB(), 130 | .DOUTB(), 131 | .INJECTSBITERR(), 132 | .INJECTDBITERR(), 133 | .SBITERR(), 134 | .DBITERR(), 135 | .RDADDRECC(), 136 | .S_ACLK(), 137 | .S_ARESETN(), 138 | .S_AXI_AWID(), 139 | .S_AXI_AWADDR(), 140 | .S_AXI_AWLEN(), 141 | .S_AXI_AWSIZE(), 142 | .S_AXI_AWBURST(), 143 | .S_AXI_AWVALID(), 144 | .S_AXI_AWREADY(), 145 | .S_AXI_WDATA(), 146 | .S_AXI_WSTRB(), 147 | .S_AXI_WLAST(), 148 | .S_AXI_WVALID(), 149 | .S_AXI_WREADY(), 150 | .S_AXI_BID(), 151 | .S_AXI_BRESP(), 152 | .S_AXI_BVALID(), 153 | .S_AXI_BREADY(), 154 | .S_AXI_ARID(), 155 | .S_AXI_ARADDR(), 156 | .S_AXI_ARLEN(), 157 | .S_AXI_ARSIZE(), 158 | .S_AXI_ARBURST(), 159 | .S_AXI_ARVALID(), 160 | .S_AXI_ARREADY(), 161 | .S_AXI_RID(), 162 | .S_AXI_RDATA(), 163 | .S_AXI_RRESP(), 164 | .S_AXI_RLAST(), 165 | .S_AXI_RVALID(), 166 | .S_AXI_RREADY(), 167 | .S_AXI_INJECTSBITERR(), 168 | .S_AXI_INJECTDBITERR(), 169 | .S_AXI_SBITERR(), 170 | .S_AXI_DBITERR(), 171 | .S_AXI_RDADDRECC() 172 | ); 173 | 174 | // synthesis translate_on 175 | 176 | endmodule 177 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/fontrom.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Sat Nov 19 05:13:29 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:blk_mem_gen:7.3 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx9 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = tqg144 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 40 | # END Select 41 | # BEGIN Parameters 42 | CSET additional_inputs_for_power_estimation=false 43 | CSET algorithm=Minimum_Area 44 | CSET assume_synchronous_clk=false 45 | CSET axi_id_width=4 46 | CSET axi_slave_type=Memory_Slave 47 | CSET axi_type=AXI4_Full 48 | CSET byte_size=9 49 | CSET coe_file=C:\Users\gmiller\OneDrive\mcm6809\DevBoards\font.coe 50 | CSET collision_warnings=ALL 51 | CSET component_name=fontrom 52 | CSET disable_collision_warnings=false 53 | CSET disable_out_of_range_warnings=false 54 | CSET ecc=false 55 | CSET ecctype=No_ECC 56 | CSET enable_32bit_address=false 57 | CSET enable_a=Always_Enabled 58 | CSET enable_b=Always_Enabled 59 | CSET error_injection_type=Single_Bit_Error_Injection 60 | CSET fill_remaining_memory_locations=false 61 | CSET interface_type=Native 62 | CSET load_init_file=true 63 | CSET mem_file=no_Mem_file_loaded 64 | CSET memory_type=Single_Port_ROM 65 | CSET operating_mode_a=WRITE_FIRST 66 | CSET operating_mode_b=WRITE_FIRST 67 | CSET output_reset_value_a=0 68 | CSET output_reset_value_b=0 69 | CSET pipeline_stages=0 70 | CSET port_a_clock=100 71 | CSET port_a_enable_rate=100 72 | CSET port_a_write_rate=0 73 | CSET port_b_clock=0 74 | CSET port_b_enable_rate=0 75 | CSET port_b_write_rate=0 76 | CSET primitive=8kx2 77 | CSET read_width_a=8 78 | CSET read_width_b=8 79 | CSET register_porta_input_of_softecc=false 80 | CSET register_porta_output_of_memory_core=false 81 | CSET register_porta_output_of_memory_primitives=false 82 | CSET register_portb_output_of_memory_core=false 83 | CSET register_portb_output_of_memory_primitives=false 84 | CSET register_portb_output_of_softecc=false 85 | CSET remaining_memory_locations=0 86 | CSET reset_memory_latch_a=false 87 | CSET reset_memory_latch_b=false 88 | CSET reset_priority_a=CE 89 | CSET reset_priority_b=CE 90 | CSET reset_type=SYNC 91 | CSET softecc=false 92 | CSET use_axi_id=false 93 | CSET use_bram_block=Stand_Alone 94 | CSET use_byte_write_enable=false 95 | CSET use_error_injection_pins=false 96 | CSET use_regcea_pin=false 97 | CSET use_regceb_pin=false 98 | CSET use_rsta_pin=false 99 | CSET use_rstb_pin=false 100 | CSET write_depth_a=2200 101 | CSET write_width_a=8 102 | CSET write_width_b=8 103 | # END Parameters 104 | # BEGIN Extra information 105 | MISC pkg_timestamp=2012-11-19T16:22:25Z 106 | # END Extra information 107 | GENERATE 108 | # CRC: 32b4b2 109 | -------------------------------------------------------------------------------- /devboards/LX9/demo/ipcore_dir/fontrom.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /devboards/LX9/lx9.ucf: -------------------------------------------------------------------------------- 1 | 2 | 3 | NET "blue[0]" LOC = P6; 4 | NET "blue[1]" LOC = P5; 5 | NET "blue[2]" LOC = P2; 6 | NET "blue[3]" LOC = P1; 7 | NET "green[0]" LOC = P10; 8 | NET "green[1]" LOC = P9; 9 | NET "green[2]" LOC = P8; 10 | NET "green[3]" LOC = P7; 11 | NET "red[0]" LOC = P15; 12 | NET "red[1]" LOC = P14; 13 | NET "red[2]" LOC = P12; 14 | NET "red[3]" LOC = P11; 15 | NET "hsync" LOC = P16; 16 | NET "vsync" LOC = P17; 17 | NET "ps2_clk" LOC = P24; 18 | NET "ps2_data" LOC = P26; 19 | 20 | 21 | NET "OSCCLK" LOC = P21; 22 | 23 | 24 | 25 | NET "blue[3]" IOSTANDARD = LVCMOS33; 26 | NET "blue[2]" IOSTANDARD = LVCMOS33; 27 | NET "blue[1]" IOSTANDARD = LVCMOS33; 28 | NET "blue[0]" IOSTANDARD = LVCMOS33; 29 | NET "green[3]" IOSTANDARD = LVCMOS33; 30 | NET "green[2]" IOSTANDARD = LVCMOS33; 31 | NET "green[1]" IOSTANDARD = LVCMOS33; 32 | NET "green[0]" IOSTANDARD = LVCMOS33; 33 | NET "red[3]" IOSTANDARD = LVCMOS33; 34 | NET "red[2]" IOSTANDARD = LVCMOS33; 35 | NET "red[1]" IOSTANDARD = LVCMOS33; 36 | NET "red[0]" IOSTANDARD = LVCMOS33; 37 | NET "OSCCLK" IOSTANDARD = LVCMOS33; 38 | 39 | NET "hsync" IOSTANDARD = LVCMOS33; 40 | NET "vsync" IOSTANDARD = LVCMOS33; 41 | NET "ps2_clk" IOSTANDARD = LVCMOS33; 42 | NET "ps2_data" IOSTANDARD = LVCMOS33; 43 | 44 | NET "an[0]" LOC = P126; 45 | NET "an[1]" LOC = P127; 46 | NET "an[2]" LOC = P111; 47 | NET "an[3]" LOC = P112; 48 | NET "sseg[0]" LOC = P116; 49 | NET "sseg[1]" LOC = P114; 50 | NET "sseg[2]" LOC = P117; 51 | NET "sseg[3]" LOC = P118; 52 | NET "sseg[4]" LOC = P119; 53 | NET "sseg[5]" LOC = P121; 54 | NET "sseg[6]" LOC = P115; 55 | NET "sseg[7]" LOC = P123; 56 | 57 | 58 | NET "an[0]" IOSTANDARD = LVCMOS33; 59 | NET "sseg[7]" IOSTANDARD = LVCMOS33; 60 | NET "sseg[6]" IOSTANDARD = LVCMOS33; 61 | NET "sseg[5]" IOSTANDARD = LVCMOS33; 62 | NET "sseg[4]" IOSTANDARD = LVCMOS33; 63 | NET "sseg[3]" IOSTANDARD = LVCMOS33; 64 | NET "sseg[2]" IOSTANDARD = LVCMOS33; 65 | NET "sseg[1]" IOSTANDARD = LVCMOS33; 66 | NET "sseg[0]" IOSTANDARD = LVCMOS33; 67 | NET "an[2]" IOSTANDARD = LVCMOS33; 68 | NET "an[1]" IOSTANDARD = LVCMOS33; 69 | NET "an[3]" IOSTANDARD = LVCMOS33; 70 | 71 | -------------------------------------------------------------------------------- /devboards/LX9/lx9_root.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:52:15 12/29/2016 7 | // Design Name: 8 | // Module Name: lx9_root 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module lx9_root( 22 | input OSCCLK, 23 | output hsync, 24 | output vsync, 25 | output [3:0] red, 26 | output [3:0] green, 27 | output [3:0] blue, 28 | 29 | output [7:0] sseg, 30 | output [3:0] an, 31 | 32 | input ps2_clk, 33 | input ps2_data 34 | ); 35 | 36 | // This LX9 doesn't need the pixel clock for something like a D/A converter 37 | wire vga_clk_in; 38 | 39 | wire [7:0] vred; 40 | wire [7:0] vgreen; 41 | wire [7:0] vblue; 42 | assign red = vred[7:4]; 43 | assign green = vgreen[7:4]; 44 | assign blue = vblue[7:4]; 45 | 46 | demo_root lx9( .OSCCLK(OSCCLK), 47 | .hsync(hsync), 48 | .vsync(vsync), 49 | .red(vred), 50 | .green(vgreen), 51 | .blue(vblue), 52 | .vga_clk(vga_clk_in), 53 | .sseg(sseg), 54 | .an(an), 55 | .ps2_clk(ps2_clk), 56 | .ps2_data(ps2_data) 57 | ); 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /devboards/demo_root.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:10:21 10/24/2016 7 | // Design Name: 8 | // Module Name: demo_root 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module demo_root(input OSCCLK, 22 | output hsync, 23 | output vsync, 24 | output [7:0] red, 25 | output [7:0] green, 26 | output [7:0] blue, 27 | output vga_clk, 28 | 29 | output [7:0] sseg, 30 | output [3:0] an, 31 | 32 | input ps2_clk, 33 | input ps2_data 34 | ); 35 | 36 | wire clk40Mhz; 37 | wire clk100Mhz; 38 | wire clk200Mhz; 39 | wire clk50Mhz; 40 | reg PLLReset=0; 41 | wire PLLLocked; 42 | 43 | clk clkpll ( 44 | .CLK_IN1(OSCCLK), // IN 45 | .CLK_OUT1(clk40Mhz), // OUT 46 | .CLK_OUT2(clk100Mhz), // OUT 47 | .CLK_OUT3(clk50Mhz), 48 | .CLK_OUT4(clk200Mhz), 49 | .RESET(PLLReset), // IN 50 | .LOCKED(PLLLocked) // OUT 51 | ); 52 | 53 | assign vga_clk = clk40Mhz; 54 | 55 | reg BusRAMWriteEnable; 56 | reg [14:0] BusRAMAddress; 57 | reg [7:0] BusRAMWriteData; 58 | wire [7:0] BusRAMReadData; 59 | 60 | wire [15:0] VideoRAMAddress; 61 | wire [7:0] VideoRAMData; 62 | 63 | 64 | bram SRAM ( 65 | .a_clk(clk200Mhz), 66 | .a_en(1'b1), 67 | .a_wr(BusRAMWriteEnable), 68 | .a_addr(BusRAMAddress), 69 | .a_din(BusRAMWriteData), 70 | .a_dout(BusRAMReadData), 71 | .b_clk(clk40Mhz), 72 | .b_en(1'b1), 73 | .b_wr(1'b0), 74 | .b_addr(VideoRAMAddress[14:0]), 75 | .b_din(8'H49), 76 | .b_dout(VideoRAMData) 77 | ); 78 | 79 | wire [7:0] vgared; 80 | wire [7:0] vgagreen; 81 | wire [7:0] vgablue; 82 | wire vgahsync; 83 | wire vgavsync; 84 | wire vgablank; 85 | 86 | assign red = vgared[7:0]; 87 | assign green = vgagreen[7:0]; 88 | assign blue = vgablue[7:0]; 89 | assign hsync = vgahsync; 90 | assign vsync = vgavsync; 91 | 92 | vga_top display( 93 | .logic_clock(clk100Mhz), 94 | .pixel_clock(clk40Mhz), 95 | .hSync(vgahsync), 96 | .vSync(vgavsync), 97 | .Red(vgared), 98 | .Green(vgagreen), 99 | .Blue(vgablue), 100 | .Blank(vgablank), 101 | .RAMAddr(VideoRAMAddress), 102 | .RAMData(VideoRAMData) 103 | ); 104 | 105 | wire CodeROMCS; 106 | reg [9:0] CodeROMAddr; 107 | wire [7:0] CodeROMData; 108 | CPUROM CodeROM ( 109 | .clka(clk200Mhz), // input clka 110 | .ena(1'b1), //CodeROMCS), 111 | .addra(CodeROMAddr), // input [9 : 0] addra 112 | .douta(CodeROMData) // output [7 : 0] douta 113 | ); 114 | 115 | reg [7:0] DToCPU; 116 | wire [7:0] DFromCPU; 117 | wire [15:0] AFromCPU; 118 | wire RnWFromCPU; 119 | wire E; 120 | wire Q; 121 | wire BS; 122 | wire BA; 123 | reg nIRQ; 124 | reg nFIRQ; 125 | reg nNMI; 126 | reg nHALT; 127 | reg nRESET=0; 128 | reg MRDY; 129 | reg nDMABREQ; 130 | wire xtal; // actually useless 131 | 132 | 133 | reg [11:0] PORCount=12'H000; 134 | 135 | always @(negedge clk50Mhz) 136 | begin 137 | if (PORCount == 12'HFFF) 138 | begin 139 | nRESET <= 1; 140 | nIRQ <= 1; 141 | nFIRQ <= 1; 142 | nNMI <= 1; 143 | nHALT <= 1; 144 | MRDY <= 1; 145 | nDMABREQ <= 1; 146 | end 147 | else 148 | begin 149 | nRESET <= 0; 150 | PORCount <= PORCount + 1'b1; 151 | end 152 | end 153 | 154 | wire nCPURESET; 155 | assign nCPURESET = nRESET; 156 | reg [15:0] ACPULatched; 157 | reg [7:0] DCPULatched; 158 | reg RnWLatched; 159 | 160 | wire [15:0] ADDR; 161 | wire [7:0] DOUT; 162 | wire RNW; 163 | 164 | assign ADDR = (E|Q) ? AFromCPU : ACPULatched; 165 | assign RNW = (E|Q) ? RnWFromCPU : RnWLatched; 166 | assign DOUT = (E|Q) ? DFromCPU : DCPULatched; 167 | 168 | assign CodeROMCS = (ADDR[15:10] == 6'b101000); // ROM at $A000-$A3FF 1010 00XX 169 | wire VectorRemapCS = (ADDR[15:4] == 12'b111111111111); // $FFF0 -> $FFFF 170 | wire KeyboardFIFOCS = (ADDR[15:1] == (15'H7800)); // $F000 = FIFO Read, $F001 = FIFO Status 171 | 172 | // RAM maps in from 0000-7FFF 173 | wire RAMCS = (ADDR[15] == 1'b0); 174 | 175 | always @(negedge Q) 176 | begin 177 | ACPULatched <= AFromCPU; 178 | RnWLatched <= RnWFromCPU; 179 | DCPULatched <= DFromCPU; 180 | end 181 | 182 | always @(negedge E) 183 | begin 184 | KeyFIFOAck <= KeyboardFIFOCS & (~ADDR[0]); 185 | end 186 | 187 | mc6809 cpu( 188 | .D(DToCPU), 189 | .DOut(DFromCPU), 190 | .ADDR(AFromCPU), 191 | .RnW(RnWFromCPU), 192 | .E(E), 193 | .Q(Q), 194 | .BS(BS), 195 | .BA(BA), 196 | .nIRQ(nIRQ), 197 | .nFIRQ(nFIRQ), 198 | .nNMI(nNMI), 199 | .EXTAL(clk100Mhz), 200 | .XTAL(xtal), 201 | .nHALT(nHALT), 202 | .nRESET(nCPURESET), 203 | .MRDY(MRDY), 204 | .nDMABREQ(nDMABREQ) 205 | ); 206 | 207 | 208 | wire [7:0] KeyFIFOData; 209 | wire KeyFIFOFull; 210 | wire KeyFIFOEmpty; 211 | reg KeyFIFOAck; 212 | 213 | ps2_communication keybd( 214 | .reset(~nCPURESET), 215 | .clk(clk50Mhz), 216 | .ps2clk(ps2_clk), 217 | .ps2dat(ps2_data), 218 | .FIFOClock(E), 219 | .FIFOReadAck(KeyFIFOAck), 220 | .FIFORead(KeyFIFOData), 221 | .FIFOFull(KeyFIFOFull), 222 | .FIFOEmpty(KeyFIFOEmpty) ); 223 | 224 | 225 | always @(*) 226 | begin 227 | CodeROMAddr = ADDR[9:0]; 228 | BusRAMAddress = ADDR[14:0]; 229 | 230 | BusRAMWriteEnable = (~RNW) & (RAMCS) & E; 231 | DToCPU = 8'H00; 232 | BusRAMWriteData = 8'H00; 233 | 234 | if (RNW) // Reads 235 | begin 236 | if (CodeROMCS | VectorRemapCS) 237 | begin 238 | DToCPU = CodeROMData; 239 | end 240 | else if (RAMCS) 241 | begin 242 | DToCPU = BusRAMReadData; 243 | end 244 | else if (KeyboardFIFOCS) 245 | begin 246 | if (~ADDR[0]) 247 | begin 248 | DToCPU = KeyFIFOData; 249 | end 250 | else 251 | begin 252 | DToCPU = {6'b0, KeyFIFOFull, KeyFIFOEmpty}; 253 | end 254 | end 255 | end 256 | else // Writes 257 | begin 258 | // Writes to ROM are meaningless 259 | if (RAMCS) 260 | begin 261 | BusRAMWriteData = DOUT; 262 | end 263 | end 264 | 265 | end 266 | 267 | 268 | sseg sevenseg( .clk(clk50Mhz), 269 | .reset( ~nCPURESET ), 270 | .data({14'H0000, KeyFIFOFull, KeyFIFOEmpty}), 271 | .sseg(sseg), 272 | .an(an) ); 273 | 274 | 275 | endmodule 276 | -------------------------------------------------------------------------------- /devboards/ps2_communication.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:27:12 11/06/2016 7 | // Design Name: 8 | // Module Name: ps2_communication 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ps2_communication( 22 | input reset, 23 | input clk, 24 | input ps2clk, 25 | input ps2dat, 26 | 27 | input FIFOClock, 28 | input FIFOReadAck, 29 | output [7:0] FIFORead, 30 | output FIFOFull, 31 | output FIFOEmpty 32 | ); 33 | 34 | 35 | reg Done; 36 | reg receiving; 37 | reg [3:0] bitNumber; 38 | reg [7:0] buffer; 39 | 40 | reg [10:0] constantCount=11'H000; 41 | reg latchedClk=1'b0; 42 | reg filteredClk=1'b0; 43 | 44 | reg FIFOWrite; 45 | reg LastDone; 46 | 47 | 48 | // MOVE DATA INTO FIFO 49 | 50 | // I'll admit that I'm using a crappy/lazy clock-domain crossing here for brevity. 51 | // I know that the FIFOClock is much faster than the PS2 Clock & I'm going to get 52 | // away with it & this is intended to demo the CPU only. :) 53 | // Good lord, don't try to leverage this code for something else. If you're 54 | // desperate, ask me. 55 | always @(negedge FIFOClock) 56 | begin 57 | if (reset) 58 | begin 59 | FIFOWrite <= 1'b0; 60 | LastDone <= 1'b0; 61 | end 62 | else 63 | begin 64 | FIFOWrite <= 1'b0; 65 | if (Done != LastDone) 66 | begin 67 | if (~FIFOFull) 68 | begin 69 | if (Done) 70 | FIFOWrite <= 1'b1; 71 | end 72 | LastDone <= Done; 73 | end 74 | end 75 | end 76 | 77 | // FILTER THE NOISY PS2 CLOCK TO SOMETHING WE CAN USE 78 | always @(negedge clk) 79 | begin 80 | if (ps2clk != latchedClk) 81 | begin 82 | latchedClk <= ps2clk; 83 | constantCount <= 11'H000; 84 | end 85 | else 86 | begin 87 | if (constantCount != 11'H01F) 88 | begin 89 | constantCount <= constantCount + 1'b1; 90 | end 91 | else 92 | filteredClk <= latchedClk; 93 | end 94 | end 95 | 96 | // ACTUALLY READ BYTES IN (NOT BOTHERING TO CHECK PARITY, SORRY) 97 | 98 | always @(negedge filteredClk) 99 | begin 100 | if (Done) 101 | Done <= 1'b0; 102 | if (reset) 103 | begin 104 | receiving <= 1'b0; 105 | Done <= 1'b0; 106 | bitNumber <= 4'H0; 107 | end 108 | else 109 | begin 110 | if (receiving) 111 | begin 112 | if (bitNumber == 4'HF) 113 | begin 114 | receiving <= 0; 115 | Done <= 1'b1; 116 | end 117 | else 118 | begin 119 | buffer[~(bitNumber[2:0])] <= ps2dat; 120 | bitNumber <= bitNumber-1'b1; 121 | end 122 | end 123 | else 124 | begin 125 | if (ps2dat == 1'b0) // start bit 126 | begin 127 | receiving <= 1'b1; 128 | bitNumber <= 4'H7; 129 | end 130 | end 131 | end 132 | end 133 | 134 | simplefifo keyfifo( 135 | .clk(FIFOClock), 136 | .reset(reset), 137 | .DataWrite(buffer), 138 | .WriteEnable(FIFOWrite), 139 | .DataRead(FIFORead), 140 | .ReadEnable(FIFOReadAck), 141 | .Full(FIFOFull), 142 | .Empty(FIFOEmpty) 143 | ); 144 | 145 | endmodule 146 | -------------------------------------------------------------------------------- /devboards/simplefifo.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:47:13 11/09/2016 7 | // Design Name: 8 | // Module Name: simplefifo 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module simplefifo #(parameter ELEMENTWIDTH=8, ELEMENTDEPTHBITS=4) 22 | ( 23 | input wire clk, 24 | input wire reset, 25 | input wire [ELEMENTWIDTH-1:0] DataWrite, 26 | input wire WriteEnable, 27 | output reg [ELEMENTWIDTH-1:0] DataRead, 28 | input wire ReadEnable, 29 | output reg Empty, 30 | output reg Full 31 | ); 32 | 33 | localparam ELEMENTDEPTH=2**ELEMENTDEPTHBITS; 34 | 35 | reg [ELEMENTWIDTH-1:0] FIFO[ELEMENTDEPTH-1:0]; 36 | reg [ELEMENTDEPTHBITS-1:0] WriteIndex; 37 | reg [ELEMENTDEPTHBITS-1:0] ReadIndex; 38 | 39 | wire [ELEMENTDEPTHBITS-1:0] NextReadIndex; 40 | assign NextReadIndex = ReadIndex+1'b1; 41 | wire [ELEMENTDEPTHBITS-1:0] NextWriteIndex; 42 | assign NextWriteIndex = WriteIndex+1'b1; 43 | 44 | 45 | // Index == means empty 46 | // Full is Write+1 == Read 47 | 48 | always @(negedge clk) 49 | begin 50 | if (reset) 51 | begin 52 | WriteIndex <= 1'b0; 53 | ReadIndex <= 1'b0; 54 | Empty <= 1'b1; 55 | Full <= 1'b0; 56 | end 57 | else 58 | begin 59 | // DataRead always reflects the next value to read 60 | DataRead <= FIFO[ReadIndex]; 61 | 62 | // 4 cases 63 | // Not Read, Not Write 64 | // Read, Not Write 65 | // Write, not Read 66 | // Read and Write 67 | case ({WriteEnable,ReadEnable}) 68 | 2'b00: // Neither 69 | begin 70 | end 71 | 2'b01: // Read, not write 72 | begin 73 | if (~Empty) 74 | begin 75 | ReadIndex <= NextReadIndex; 76 | Empty <= (NextReadIndex == WriteIndex); 77 | Full <= 1'b0; // We just read a value, we didn't write one, it cannot be full. 78 | end 79 | // else 80 | // begin 81 | // Empty <= (ReadIndex == WriteIndex); 82 | // Full <= (NextWriteIndex == ReadIndex); 83 | // end 84 | end 85 | 2'b10: // Write, not read 86 | begin 87 | if (~Full) 88 | begin 89 | FIFO[WriteIndex] <= DataWrite; 90 | WriteIndex <= NextWriteIndex; 91 | Empty <= 1'b0; // We just wrote a value, it isn't empty 92 | Full <= (NextWriteIndex == ReadIndex); 93 | end 94 | end 95 | 2'b11: // Write and Read 96 | begin 97 | FIFO[WriteIndex] <= DataWrite; 98 | WriteIndex <= NextWriteIndex; 99 | ReadIndex <= NextReadIndex; 100 | // Empty and Full should remain whatever they were before. 101 | end 102 | 103 | endcase 104 | end 105 | 106 | end 107 | 108 | 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /devboards/src6809/img.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/devboards/src6809/img.bin -------------------------------------------------------------------------------- /devboards/src6809/startup.asm: -------------------------------------------------------------------------------- 1 | 2 | org $a000 3 | 4 | CURPOS equ $88 5 | KEYSTAT equ $87 6 | 7 | KEYLS equ $1 8 | KEYRS equ $2 9 | KEYSHF equ $4 10 | KEYUP equ $8 11 | 12 | EXECPTR equ 487 13 | 14 | FDB POLCAT 15 | FDB CHROUT 16 | 17 | start orcc #$50 18 | 19 | clr KEYSTAT 20 | lds #$3FF 21 | jsr CLS 22 | 23 | ldx #GREGMSG 24 | jsr PRTMSG 25 | 26 | ldx EXECPTR 27 | cmpx #0 28 | beq keylp 29 | jmp ,x 30 | 31 | keylp 32 | jsr POLCAT 33 | beq keylp 34 | 35 | ;bsr PRTHEX 36 | bsr PUTCHR 37 | bra keylp 38 | 39 | lp bra lp 40 | 41 | PRTNYB cmpa #10 42 | blo NYB1 43 | adda #7 44 | NYB1 adda #$30 45 | bra PUTCHR 46 | 47 | 48 | PRTHEX pshs a 49 | lsra 50 | lsra 51 | lsra 52 | lsra 53 | bsr PRTNYB 54 | lda ,s 55 | anda #$F 56 | bsr PRTNYB 57 | lda #$20 58 | bsr PUTCHR 59 | puls a,pc 60 | 61 | 62 | 63 | PUTCHR ldu CURPOS 64 | cmpa #13 65 | beq CHRCR 66 | cmpa #8 67 | beq CHRBS 68 | cmpa #32 69 | bhs CHRSYM 70 | rts 71 | CHRSYM cmpa #$40 // Symbols & Numbers from $20 to $3F ? 72 | bhs 1$ 73 | eora #$40 74 | bra CHRWRT 75 | 1$ cmpa #$60 // Is this uppercase or lowercase? 76 | blo CHRWRT // Uppercase, write directly. 77 | eora #$60 78 | CHRWRT sta ,u+ 79 | CHRPST cmpu #$600 80 | beq CHRSCR 81 | stu CURPOS 82 | rts 83 | CHRSCR pshs x 84 | bsr SCROLL 85 | puls x 86 | ldu #$5E0 87 | stu CURPOS 88 | rts 89 | CHRCR tfr u,d 90 | andb #$E0 91 | addd #$20 92 | tfr d,u 93 | bra CHRPST 94 | CHRBS cmpu #$400 95 | bne CHRBS1 96 | rts 97 | CHRBS1 leau -1,u 98 | lda #$60 99 | sta ,u 100 | stu CURPOS 101 | rts 102 | 103 | CHROUT pshs u,d 104 | bsr PUTCHR 105 | puls u,d,pc 106 | 107 | PRTMSG lda ,x+ 108 | beq PRTEND 109 | bsr PUTCHR 110 | bra PRTMSG 111 | PRTEND rts 112 | 113 | CLS ldx #$400 114 | stx CURPOS 115 | lda #$60 116 | CLS1 sta ,x+ 117 | cmpx #$600 118 | bne CLS1 119 | rts 120 | 121 | SCROLL ldx #$420 122 | SCRLP lda ,x+ 123 | sta -33,x 124 | cmpx #$600 125 | bne SCRLP 126 | ldx #$5E0 127 | lda #$60 128 | CLRLN sta ,x+ 129 | cmpx #$600 130 | bne CLRLN 131 | rts 132 | 133 | RDFIFO lda KEYSTAT ; If either shift is pressed, set the KEYSHF flag 134 | lsla 135 | ora KEYSTAT 136 | lsla 137 | anda #KEYSHF 138 | pshs a 139 | lda KEYSTAT 140 | anda #~KEYSHF 141 | ora ,s+ 142 | sta KEYSTAT 143 | 144 | lda $F001 // Bit 0 = EMPTY, Bit 1 = FULL 145 | coma 146 | bita #$1 // ~Empty flag 147 | bne rdkey 148 | rts 149 | rdkey lda $F000 150 | 151 | cmpa #$F0 // keyup 152 | bne 1$ 153 | lda KEYSTAT ; Last code was keyup 154 | ora #KEYUP 155 | sta KEYSTAT 156 | bra RDFIFO 157 | 1$ pshs b 158 | ldb #KEYLS 159 | cmpa #$12 ; L-SHIFT 160 | bne 2$ 161 | 3$ lda KEYSTAT 162 | bita #KEYUP 163 | beq 4$ 164 | comb 165 | andb KEYSTAT 166 | bra 5$ 167 | 4$ orb KEYSTAT 168 | 5$ stb KEYSTAT 169 | puls b 170 | ldb KEYSTAT ; Last code wasn't keyup 171 | andb #~KEYUP 172 | stb KEYSTAT 173 | bra RDFIFO 174 | 2$ ldb #KEYRS 175 | cmpa #$59 ; R-SHIFT 176 | beq 3$ 177 | ldb KEYSTAT ; Last code wasn't keyup 178 | bitb #KEYUP 179 | beq 6$ 180 | clra ; Ignore keyups 181 | 6$ andb #~KEYUP 182 | stb KEYSTAT 183 | puls b 184 | tsta 185 | rts 186 | 187 | POLCAT jsr RDFIFO 188 | bne 10$ 189 | clra 190 | rts 191 | 10$ jsr KeyCodeToASCII 192 | tsta 193 | rts 194 | 195 | GREGMSG FCC /Greg's 25Mhz 6809 Micro-Demo/ 196 | FCB 13 197 | FCC /Type:/ 198 | FCB 13 199 | FCB 0 200 | 201 | LKUP0 202 | FCB 13,9,9 203 | FCB 14,126,96 204 | 205 | 206 | LKUP1 207 | FCB 21,81,113 208 | FCB 22,33,49 209 | FCB 26,90,122 210 | FCB 27,83,115 211 | FCB 28,65,97 212 | FCB 29,87,119 213 | FCB 30,64,50 214 | 215 | 216 | TAB2 217 | FCB 0,0 218 | FCB 67,99 219 | FCB 88,120 220 | FCB 68,100 221 | FCB 69,101 222 | FCB 36,52 223 | FCB 35,51 224 | FCB 0,0 225 | FCB 0,0 226 | FCB 32,32 227 | FCB 86,118 228 | FCB 70,102 229 | FCB 84,116 230 | FCB 82,114 231 | FCB 37,53 232 | FCB 0,0 233 | 234 | 235 | TAB3 236 | FCB 0,0 237 | FCB 78,110 238 | FCB 66,98 239 | FCB 72,104 240 | FCB 71,103 241 | FCB 89,121 242 | FCB 94,54 243 | FCB 0,0 244 | FCB 0,0 245 | FCB 0,0 246 | FCB 77,109 247 | FCB 74,106 248 | FCB 85,117 249 | FCB 38,55 250 | FCB 42,56 251 | FCB 0,0 252 | 253 | 254 | TAB4 255 | FCB 0,0 256 | FCB 60,44 257 | FCB 75,107 258 | FCB 73,105 259 | FCB 79,111 260 | FCB 41,48 261 | FCB 40,57 262 | FCB 0,0 263 | FCB 0,0 264 | FCB 62,46 265 | FCB 63,47 266 | FCB 76,108 267 | FCB 58,59 268 | FCB 80,112 269 | FCB 95,45 270 | FCB 0,0 271 | 272 | 273 | LKUP5 274 | FCB 82,34,39 275 | FCB 84,123,91 276 | FCB 85,43,61 277 | FCB 90,13,13 278 | FCB 91,125,93 279 | FCB 93,124,92 280 | 281 | 282 | LKUP6 283 | FCB 102,8,8 284 | 285 | 286 | LKUP7 287 | FCB 118,26,26 288 | 289 | 290 | MasterLookup 291 | FDB LKUP0,2 292 | FDB LKUP1,7 293 | FDB TAB2,0 294 | FDB TAB3,0 295 | FDB TAB4,0 296 | FDB LKUP5,6 297 | FDB LKUP6,1 298 | FDB LKUP7,1 299 | 300 | KeyCodeToASCII 301 | pshs a,x 302 | ldx #MasterLookup 303 | lsra 304 | lsra 305 | anda #$FC 306 | leax a,x 307 | ldd 2,x 308 | beq KeyTable 309 | lda ,s 310 | ldx ,x 311 | LkUp 312 | tstb 313 | beq KeyNotFound 314 | cmpa ,x 315 | beq KeyFound 316 | leax 3,x 317 | decb 318 | bra LkUp 319 | KeyFound 320 | puls a 321 | lda KEYSTAT 322 | bita #KEYSHF 323 | beq 1$ 324 | lda 1,x 325 | bra 2$ 326 | 1$ lda 2,x 327 | 2$ puls x,pc 328 | KeyNotFound 329 | puls a,x 330 | clra 331 | rts 332 | KeyTable 333 | lda ,s 334 | anda #$f 335 | lsla 336 | ldx ,x 337 | leax a,x 338 | puls a 339 | lda KEYSTAT 340 | bita #KEYSHF 341 | beq 3$ 342 | lda ,x 343 | bra 4$ 344 | 3$ lda 1,x 345 | 4$ puls x,pc 346 | 347 | 348 | 349 | org $a3f0 350 | fdb start 351 | fdb start 352 | fdb start 353 | fdb start 354 | fdb start 355 | fdb start 356 | fdb start 357 | fdb start 358 | -------------------------------------------------------------------------------- /devboards/sseg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:58:13 09/23/2016 7 | // Design Name: 8 | // Module Name: sseg 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module sseg( 23 | input clk, 24 | input reset, 25 | input [15:0] data, 26 | output [7:0] sseg, 27 | output [3:0] an 28 | ); 29 | 30 | reg [15:0] delay=16'H0000; 31 | reg [3:0] digit=4'H0; 32 | 33 | reg [3:0] anode; 34 | assign an = anode; 35 | 36 | reg [7:0] ss; 37 | assign sseg = ss; 38 | 39 | always @(*) 40 | begin 41 | case (delay[15:14]) 42 | 2'b00: 43 | begin 44 | anode = 4'b1110; 45 | digit = data[3:0]; 46 | end 47 | 2'b01: 48 | begin 49 | anode = 4'b1101; 50 | digit = data[7:4]; 51 | end 52 | 2'b10: 53 | begin 54 | anode = 4'b1011; 55 | digit = data[11:8]; 56 | end 57 | 2'b11: 58 | begin 59 | anode = 4'b0111; 60 | digit = data[15:12]; 61 | end 62 | endcase 63 | 64 | case (digit) 65 | 4'H0: 66 | ss = 8'b11000000; 67 | 4'H1: 68 | ss = 8'b11111001; 69 | 4'H2: 70 | ss = 8'b10100100; 71 | 4'H3: 72 | ss = 8'b10110000; 73 | 4'H4: 74 | ss = 8'b10011001; 75 | 4'H5: 76 | ss = 8'b10010010; 77 | 4'H6: 78 | ss = 8'b10000010; 79 | 4'H7: 80 | ss = 8'b11111000; 81 | 4'H8: 82 | ss = 8'b10000000; 83 | 4'H9: 84 | ss = 8'b10010000; 85 | 4'HA: 86 | ss = 8'b10001000; 87 | 4'HB: 88 | ss = 8'b10000011; 89 | 4'HC: 90 | ss = 8'b11000110; 91 | 4'HD: 92 | ss = 8'b10100001; 93 | 4'HE: 94 | ss = 8'b10000110; 95 | 4'HF: 96 | ss = 8'b10001110; 97 | endcase 98 | end 99 | 100 | always @(posedge clk or posedge reset) 101 | begin 102 | if (reset) 103 | delay <= 16'H0000; 104 | else 105 | delay <= delay + 1'b1; 106 | end 107 | 108 | 109 | 110 | 111 | endmodule 112 | -------------------------------------------------------------------------------- /documentation/6809Details.md: -------------------------------------------------------------------------------- 1 | # MC6809 Specifics 2 | 3 | I merely want to mention a few tidbits, rather than attempt to cover the 6809 in general. The best reference is the MC6809 and MC6809E Motorola datasheets. (Although on a few occasions, I found the Hitachi datasheets to clearer on details that were vague in the Motorola datasheets.) 4 | 5 | ## Clocking 6 | 7 | The MC6809 and the MC6809E differ primarily on the origin of the quadrature clocks, E and Q. The 6809 receives a singular clock that is 4x the desired rate of E and Q (either through driving a crystal or from an oscillator), and it *generates* E and Q. The 6809E expects external circuitry to provide E and Q. The latter case tends to be more flexible, while the former is more of a straight-and-simple solution. 8 | 9 | E and Q together describe the 6809's bus behavior. Both clocks run at the same rate; however, Q "leads" E by 90 degrees (one quarter period). A single bus cycle begins at the falling edge of E through to the next falling edge of E, as shown in the diagram below: 10 | 11 | ![One 6809 Bus Cycle](onebuscycle.png) 12 | 13 | The MC6809 and MC6809E datasheets have *all* of the critical timing data, and I won't attempt to recreate that here. However, I do need to point out a few specifics: 14 | 15 | 1. You should not always consider the bus valid. A simple perspective would be that the bus is only valid when E is high. That isn't perfectly accurate, though. The Address bus and R/W are guaranteed to be valid before the rising edge of Q, Write data is available on the Data bus before the rising edge of E (specifics as to how much in advance of these edges are in the MC6809 datasheet, and vary depending on clock speed). 16 | 17 | 2. The 6809 actually latches the address bus and R/W at a particular time after the falling edge of E. A real 6809 is combinatorial, but the latching minimizes the transition effect of one value to another. This actually isn't guaranteed in the MC6809 datasheet, but some designs depend on it. (Depending on it is somewhat dangerous. You might very rarely see a problem, but during a transition you might have an instant of 'write' to an address other than what is intended - even with the latching.) The correct design strategy is to only depend on the Address bus, the Data bus, and the R/W signal (as well as signals such as BS and BA) when they're guaranteed to be valid (if E and Q are both low, they're in a state of transition). 18 | 19 | 3. The 6809 latches the Data bus on read on the falling edge of E. Data is required to be valid and stable well before the falling edge. A real MC6809 as well as an internal-to-an-FPGA implementation requires *some* Hold time after the falling edge. Internal-to-an-FPGA doesn't require a tremendous amount, and if E and Q are in sync with the clocks providing internal resources, effectively none. 20 | 21 | Stating that something must/will be stable at a clock edge means that it actually needs to happen *before* the edge. The actual cycle is more accurately as follows: 22 | 23 | ![Bus Section Timing](bus_sections.png) 24 | 25 | The specifics of the exact amount of time between these points and different edges is listed in the MC6809 datasheet, Figure 1. 26 | 27 | The point about not depending on a bus that isn't guaranteed to be stable is highlighted in the following diagram. In the area marked by a '1', the Data Bus is not stable. For Writes, it will transition between values in an indeterminate manner. For a Write to a Read or a Read to a Write, it can be variable. The CPU driving the bus while a peripheral also drives it (to different states) is an ugly current sink. In the area marked by a '2', the Address Bus and R/W (as well as BS and BA) is not stable. They are transitioning from the prior state to the current state. 28 | 29 | ![Critical Timing](critical.png) 30 | 31 | ## Bus Related Signals 32 | 33 | The 6809 can cede the address and data busses as well as the R/W signal if requested (all three are tristated). The /HALT signal asks the CPU to do so when the current instruction is complete. The /DMABREQ signal (which only exists on the 6809, not on the 6809E) is *very* similar, except that every 15 cycles, the CPU will wake and reclaim the bus for the purpose of - and this is the word used in the Motorola datasheet - "refresh". There are two output signals from the 6809 that indicate multiple states or indications: BA and BS. When both of these signals are set to '1', the 6809 is off of the bus and stopped. 34 | 35 | On the 6809, a signal called 'MRDY' exists. Normally high, driving MRDY low indicates that "memory is not ready". The 6809 will then *stretch* the E and Q clocks by multiples of a quarter period. If a peripheral needs to be accessed that happens to be slow, the CPU effectively stalls until the peripheral is ready. Note that this *cannot* exist on the 6809E, as the E and Q clocks originate from an external source. *That* source could have a similar functionality, but the 6809E is a slave to those clocks and cannot modify them. 36 | 37 | The 6809E offers a signal that's convenient for CPU designers (or annoying people reimplementing the CPU in an FPGA), but less valuable to others - LIC. *Last Instruction Cycle* goes high on the cycle representing the last cycle; LIC is extremely useful in delineating the end of the last instruction and the beginning of the next instruction. 38 | 39 | There are lesser used signals, such as AVMA (which is intended to be predictive at permitting non-CPU devices to know explictly when the 6809 plans to actively use the bus in the next cycle (as opposed to having the bus entirely unused for a cycle). BUSY is intended to provide a mechanism by which atomic actions could be created with a bit of glue. TSC permits a Tristate (Three-State Control) over the busses and R/W, albeit with a fairly heavy-hand. [TSC is one the signals I've never seen actively used.] Again, refer to the MC6809 and MC6809E datasheets for the actual details. 40 | 41 | 42 | 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /documentation/APP.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/APP.jpg -------------------------------------------------------------------------------- /documentation/Acknowledgements.md: -------------------------------------------------------------------------------- 1 | # Acknowledgements 2 | 3 | I'd like to voice my appreciation to a few groups or individuals: 4 | 5 | *Erik Gavriluk*, who deftly convinced me to do the work, provided the CoCo 3 and both JROK boards. Erik spent untold hours sifting through code when I had an implementation bug attempting to get me detailed per-instruction dumps of execution of code on known-good platforms. He helped put together code that was used for testbenches and provided the 'known good' copies of the execution. He also offered feedback when I was just too close to a problem to recognize the obvious. 6 | 7 | *The MAME contributors*, who have spent so much time emulating old hardware. For the most part, schematics are available for old hardware. However, the perspectives of so many other people are so helpful when attempting to determine pragmatically how a four-page schematic distills into functionality, or that a specific undefined instruction maps to which specific instruction on the original hardware. 8 | 9 | *JROK*, for making multiple cool boards and clearly investing a ton of time into them. My test hardware would've been far smaller without his efforts. The fact that he's a nice guy and quickly offered advice and help when I introduced myself speaks for his character. 10 | 11 | *Roger Taylor*, for sifting through irritating `CWAI`, `SYNC`, the-second-NMI-doesn't-work, and maddening `/HALT` issues, patiently waiting for me to figure out what the heck I'd done wrong each time. Roger has to be one of the most patient and humble people out there, and I'd still have several items not-quite-right if not for his time and help. 12 | 13 | ##Addenda: 14 | 15 | Many thanks to Greg Sander and Jose Tejada for pointing out that I had a bug in the DAA instruction. 16 | 17 | When Greg suggested there might be a bug, I wasn't very convinced until he suggested that it might be in DAA. I'd never bothered to use DAA, and instantly believed that it could be broken. 18 | 19 | Greg didn't know 6809; he didn't know Verilog (knew VHDL), but was fiddling with it and narrowing in on proving that it was DAA so fast my head spun. 20 | 21 | When I finally got around to fixing it, I had gone through multiple conflicting references (how many people know that carry out on DAA is basically an OR of the original contents of the carry bit and the carry-out of the DAA addition?) and deleted several lines where I was too clever for my own good. 22 | 23 | Greg and Jose have both given me a thumbs up on it working correctly for them, so my sincere appreciation goes out to both for investing time in it. Thanks! 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /documentation/Blaster.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/Blaster.jpg -------------------------------------------------------------------------------- /documentation/CoCoCMD.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/CoCoCMD.jpg -------------------------------------------------------------------------------- /documentation/Cyc5.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/Cyc5.jpg -------------------------------------------------------------------------------- /documentation/Cyc5SOC.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/Cyc5SOC.jpg -------------------------------------------------------------------------------- /documentation/EGlitch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/EGlitch.png -------------------------------------------------------------------------------- /documentation/EP4CE6.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/EP4CE6.jpg -------------------------------------------------------------------------------- /documentation/ElectricYoyo.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/ElectricYoyo.jpg -------------------------------------------------------------------------------- /documentation/FinalThoughts.md: -------------------------------------------------------------------------------- 1 | # Final Thoughts 2 | 3 | I'll invest the time to track down bugs; ping me. 4 | 5 | If you're trying to apply it and having trouble, feel free to ping me there as well. The odds are good that I can help. 6 | 7 | I am interested in making some changes when I get a bit of time: 8 | 9 | - I'd like to add a parameter to the core that permits you to instantiate the module such that the 'unnecessary delays' that provide for the cycle-accuracy can be disabled. Considering that my interest has been cycle-accuracy, I haven't done that - but I've been aware from the beginning that it would be useful. 10 | 11 | - I'd like to sort out the Test Bench that I was using and start including it. I used ISim and ModelSim (mostly the latter). I'd have to do some cleaning up, but it would be worthwhile. 12 | 13 | - I'd like to go through and clean up the warnings. The fascinating thing is that Quartus, ISE, and Vivado all give some warnings that the others do not. Something that synthesizes clean in one may well get complaints from one of the other two (yes, the latter pair are both from Xilinx, but are definitely different). Heck, I've gotten warnings on a Cyclone V in Quartus that didn't appear for a Cyclone IV. I'd be tickled to have it synthesize on all of the above and every warning that is removable be entirely gone. 14 | 15 | - I wouldn't mind adding another sample that does SRAM out of the FPGA, but the rest of the FPGA is internal. The other Cyclone V board that I pointed out seems like a good candidate. 16 | 17 | That said, I'm likely to take a break (aside from bugs). I do work for a living, and this kind of project occupies a very tiny window in my evenings after my children go to bed and before I do. I do have some other interests (similar interests, but different topics), and I'm eager to put the tiny portion of time I can spare into them. 18 | 19 | Best wishes! 20 | 21 | Greg 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /documentation/Implementation.md: -------------------------------------------------------------------------------- 1 | # Implementations 2 | 3 | The core has been used in multiple implementations. Some of the implementations are intended for Validation. Others are intended as examples of how to use the core in specific scenarios, spread across Altera and Xilinx FPGAs. 4 | 5 | The GODIL is an example of the core interfacing entirely with real-world components; it deals with some 'edge' issues of a 6809 and timing when signals pass outside an FPGA. 6 | 7 | The other boards are all examples of how to use the core either completely or partially internal to an FPGA. (Some use purely block RAM for the example.) To read more about what the example actually is, click here. 8 | 9 | ## GODIL (Spartan 3E) 10 | 11 | ## EP4CE6 Bargain Board (Cyclone IV) 12 | 13 | ## Alterate EP4CE6 Bargain Board (Cyclone IV) 14 | 15 | ## LX9 Bargain Board (Spartan 6) 16 | 17 | ## Terasic Cyclone V GX Starter Board (Cyclone V) 18 | 19 | ## Terasic DE1-SOC Boards (Cyclone V) 20 | 21 | -------------------------------------------------------------------------------- /documentation/JROKWilliams.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/JROKWilliams.jpg -------------------------------------------------------------------------------- /documentation/LICENSE.md: -------------------------------------------------------------------------------- 1 | # LICENSE 2 | 3 | I dislike having to record licenses at all. My experiences have been that 99% of folks I deal with are honest and reasonable. However, there is also a small subset who seem to be ethically absent. I'm really only interested in being a hinderance to them and protecting myself from them. 4 | 5 | I've been reminded that many people work for companies and organizations that have policies regarding use of source code from outside their domain, and that they typically have a set of predefined standard licenses that they'll accept. My ideal is not the BSD license, but closer to a modified version. 6 | 7 | For those who wish to redistribute the source, or for those who require a well-known and standardized license, the stock BSD license is available. 8 | 9 | For those willing to *not* redistribute the source and only wish to utilize the work - and don't care if the license is standardized or not, a modified license is available. (The primary difference is that the modified version is binary-only, but does not require any citations.) 10 | 11 | You must select one. 12 | 13 | [Feel free to contact me if your needs fall outside of these. Since I really just want to see the darned thing used, I'm likely to be fairly accomodating.] 14 | 15 | 16 | ## Standard BSD license 17 | 18 | Copyright (c) 2016, Greg Miller 19 | All rights reserved. 20 | 21 | Redistribution and use in source and binary forms, with or without 22 | modification, are permitted provided that the following conditions are met: 23 | * Redistributions of source code must retain the above copyright 24 | notice, this list of conditions and the following disclaimer. 25 | * Redistributions in binary form must reproduce the above copyright 26 | notice, this list of conditions and the following disclaimer in the 27 | documentation and/or other materials provided with the distribution. 28 | * The name of the author may not be used to endorse or promote products 29 | derived from this software without specific prior written permission. 30 | 31 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 32 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 33 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 34 | DISCLAIMED. IN NO EVENT SHALL GREG MILLER BE LIABLE FOR ANY 35 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 36 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 37 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 38 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 40 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 | 42 | 43 | ## Modified BSD License 44 | 45 | Copyright (c) 2016, Greg Miller 46 | All rights reserved. 47 | 48 | Redistribution and use in binary form, with or without 49 | modification, is permitted provided that the following condition are met: 50 | 51 | * The name of the author may not be used to endorse or promote products 52 | derived from this software without specific prior written permission. 53 | 54 | Redistribution in source form is not permitted under this license. 55 | 56 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 57 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 58 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 59 | DISCLAIMED. IN NO EVENT SHALL GREG MILLER BE LIABLE FOR ANY 60 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 61 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 62 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 63 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 65 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 | 67 | 68 | -------------------------------------------------------------------------------- /documentation/LX9.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/LX9.jpg -------------------------------------------------------------------------------- /documentation/PoweredZooQWithGODIL.jpg: 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Williams Stargate subroutine at $119 contains a minor error. At $11D if the value of the U register is nonzero, the BNE instruction jumps incorrectly into the middle of the next instruction. 2 | 3 | Williams Stargate disassembly and hex dump 4 | 5 | The intent is to skip over the JSR $115. Instead the code jumps to $120, executing $01 $15. $01 is documented as an invalid opcode, however the Motorola 6809 actually executes it as NEG <$15. In contrast, the Hitachi 6309 traps on the illegal instruction. 6 | 7 | The code at $11D can be patched to execute BNE $0122 instead of BNE $0120 as follows. 8 | 9 | Assuming the first Stargate ROM is a file named "01" with SHA-1 hash *f003a5a9319c4eb8991fa2aae3f10c72d6b8e81a* use the following command line: 10 | 11 | echo "11e: 03" | xxd -r - 01 12 | 13 | Alternately change $2601 to $2603 using a hex editor. 14 | 15 | End result is a file with SHA-1 hash *6a467d3619dae915d192c3b5171064a5c273c870* which is now Hitachi 6309 compatible. 16 | -------------------------------------------------------------------------------- /documentation/qix.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/qix.jpg -------------------------------------------------------------------------------- /documentation/qix2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/qix2.jpg -------------------------------------------------------------------------------- /documentation/robotron.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/robotron.jpg -------------------------------------------------------------------------------- /documentation/sinistar.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/sinistar.jpg -------------------------------------------------------------------------------- /documentation/spacedungeon.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/spacedungeon.jpg -------------------------------------------------------------------------------- /documentation/splat.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/splat.jpg -------------------------------------------------------------------------------- /documentation/stargate-patch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/stargate-patch.png -------------------------------------------------------------------------------- /documentation/stargate.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/stargate.jpg -------------------------------------------------------------------------------- /documentation/super6809.md: -------------------------------------------------------------------------------- 1 | # A Supercharged 6809 2 | 3 | My opinions only. I expect some folks to disagree, which is certainly their right. 4 | 5 | The topic is "How do you make a *better* 6809?" 6 | 7 | ## Don't go HD6309 8 | 9 | The Hitachi HD6309 and HD6309E are neat CPUs. Investigate them, read about them, and darnit, those Hitachi guys did a great job. It's really a pity that something like the TRS-80 Color Computer 3 didn't ship with a HD63C09. Compatibility would have been retained for software written for older units, but new instructions and registers would've made the CoCo 3 just downright better. (Hitachi would've had to have admitted to having added the new features by the CoCo 3 launch.) 10 | 11 | Extending a soft core - a core written with the intention of being accurate to the original - to include the 6309's features? The point in doing this would be ... to gain compatibility with .. wait, what? A handful of 6309-specific chunks of code? 12 | 13 | No, this is just one-upsmanship. 14 | 15 | If you seriously want to make a truly fast 6809, I have suggestions, but they may not be the pop-scene favorites: 16 | 17 | ## Start making architectural changes 18 | 19 | ### Break the CPU/Bus Cycle link 20 | 21 | The 6809 has the notion that a bus cycle is equivilent to a CPU clock cycle. This made sense in the late 1970s. By the mid 1980s, it wasn't making sense any longer. Today, the notion is archaic. Permit the CPU to run at a specific clock speed, but to only stall when entirely dependent on a bus transaction. All real-world software timing needs to be through external timing sources - cycle counting "just doesn't work" any longer. 22 | 23 | ### Add a cache 24 | 25 | In fact, start with just an I cache. A tiny bit of code would be needed to flush the I cache in specific situations (code loaded into RAM), but then things like loops that fit entirely within an I cache can run at the CPU's clock speed, not blocked by every byte of instruction required. Add a D cache next. Enjoy bursts of *very* fast throughput. 26 | 27 | ### Permit bursty memory 28 | 29 | SDRAM/DDR/DDR2/DDR3/etc. are a confusing thing. They're actually quite perky in reads and writes of many values at once, but they're absolutely awful for a single read/write transaction. There's a very good reason why lots of designs around legacy microprocessors are designed today to use SRAM - it's more expensive, but darnit, it can perform single accesses in a very concrete amount of time [which fits with late-70s/early-80s CPU design structure perfectly]. However, when it comes down to it, you can't beat SDRAM. They're stunningly cheap, available, and when you're moving bursts of data at a time (ahem, like *cache lines*), they're very efficient. 30 | 31 | ### Copy the late 1980s Intel Playbook 32 | 33 | Want to keep going? Expand the register set by depth, with compatibility maintained via existing opcodes. Newer opcodes - identical in purpose, but not identical in form - service, say, the 32-bit version of X, Y, S, and U. Say that LX, LY, LS, and LU refer to the full 32 bit register, while X, Y, S, and U refer to the 16-bit version only. A similar plan for A, B, D - although my inclination is that A and B become 32-bits as well and D merely is the lower 8 bits of A concatenated with the lower 8 bits of B. (I'm oversimplifying a bit; the 6809 depends on 16-bit offsets to handle wrap-around; that'd have to still work, but only within the 16-bit zone.) 34 | 35 | Instructions might be 6, 8 bytes long on average. However, the impact is fairly low; the massively increased throughput from the caching (FPGA block ram can run remarkably fast) trivializes the doubled and perhaps tripled instruction lengths. 36 | 37 | Does it "feel" like a 6809 any longer? Yeah, it does. The instruction set for 32-bit-register instructions is very similar to the compatible 8/16-bit instruction set. 38 | 39 | Is it neat and tidy? Gosh, no. If you want that, toss compatibility and do a pipelined interlocked CPU. 40 | 41 | ### The point 42 | 43 | My apologies if this comes off in a negative light. That really isn't my intent. 44 | 45 | My knee-jerk sense here is that the 6809 was (nearly) the last big combinatorial non-microcoded CPU for a good reason. Some of us adore it, but there's a pragmatic limit to attempting to make a 'super' version of it; the supercharged "thing" quickly ceases to be a "6809" any more. 46 | 47 | [Finally, the guilty admission: I've considered doing everything above myself several times. However, I have other strange notions in my head for projects these days, so I'm not likely to pursue these kinds of things.] 48 | 49 | 50 | -------------------------------------------------------------------------------- /documentation/zookeeper.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cavnex/mc6809/17e94a6ef163be8b79a9b15b2e814847b6062f0f/documentation/zookeeper.jpg -------------------------------------------------------------------------------- /mc6809.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 08:11:34 09/23/2016 7 | // Design Name: 8 | // Module Name: mc6809e 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mc6809( 22 | input [7:0] D, 23 | output [7:0] DOut, 24 | output [15:0] ADDR, 25 | output RnW, 26 | output E, 27 | output Q, 28 | output BS, 29 | output BA, 30 | input nIRQ, 31 | input nFIRQ, 32 | input nNMI, 33 | input EXTAL, 34 | input XTAL, 35 | input nHALT, 36 | input nRESET, 37 | input MRDY, 38 | input nDMABREQ 39 | 40 | , output [111:0] RegData 41 | 42 | ); 43 | 44 | reg [1:0] clk_phase=2'b00; 45 | 46 | wire CLK; 47 | assign CLK=EXTAL; 48 | 49 | wire LIC; 50 | wire BUSY; 51 | wire AVMA; 52 | reg rE; 53 | reg rQ; 54 | assign E = rE; 55 | assign Q = rQ; 56 | 57 | mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), 58 | .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ) 59 | ,.RegData(RegData) 60 | ); 61 | 62 | always @(negedge CLK) 63 | begin 64 | case (clk_phase) 65 | 2'b00: 66 | rE <= 0; 67 | 2'b01: 68 | rQ <= 1; 69 | 2'b10: 70 | rE <= 1; 71 | 2'b11: 72 | rQ <= 0; 73 | endcase 74 | 75 | if (MRDY == 1'b1) 76 | clk_phase <= clk_phase + 2'b01; 77 | end 78 | 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /mc6809e.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 08:11:34 09/23/2016 7 | // Design Name: 8 | // Module Name: mc6809e 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mc6809e( 22 | input [7:0] D, 23 | output [7:0] DOut, 24 | output [15:0] ADDR, 25 | output RnW, 26 | input E, 27 | input Q, 28 | output BS, 29 | output BA, 30 | input nIRQ, 31 | input nFIRQ, 32 | input nNMI, 33 | output AVMA, 34 | output BUSY, 35 | output LIC, 36 | input nHALT, 37 | input nRESET 38 | 39 | ); 40 | 41 | 42 | 43 | mc6809i cpucore (.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), 44 | .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(1'b1) 45 | ); 46 | 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /mc6809s.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09/18/2016 09:25:01 PM 7 | // Design Name: 8 | // Module Name: 6809 Superset module of MC6809 and MC6809E signals 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mc6809s( 24 | input [7:0] D, 25 | output [7:0] DOut, 26 | output [15:0] ADDR, 27 | output RnW, 28 | input CLK4, 29 | output BS, 30 | output BA, 31 | input nIRQ, 32 | input nFIRQ, 33 | input nNMI, 34 | output AVMA, 35 | output BUSY, 36 | output LIC, 37 | input nRESET, 38 | input nHALT, 39 | input nDMABREQ, 40 | output E, 41 | output Q, 42 | output reg [1:0] clk4_cnt, 43 | output [111:0] RegData 44 | ); 45 | 46 | reg rE; 47 | reg rQ; 48 | assign E = rE; 49 | assign Q = rQ; 50 | reg nCoreRESET; 51 | 52 | mc6809i corecpu(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(rE), .Q(rQ), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nRESET(nCoreRESET), 53 | .nDMABREQ(nDMABREQ), .nHALT(nHALT), .RegData(RegData) ); 54 | 55 | always @(posedge CLK4) 56 | begin 57 | clk4_cnt <= clk4_cnt+2'b01; 58 | 59 | if (nRESET == 0) 60 | begin 61 | clk4_cnt <= 0; 62 | nCoreRESET <= 0; 63 | end 64 | 65 | if ( clk4_cnt == 2'b00 ) // RISING EDGE OF E 66 | rE <= 1; 67 | 68 | if (clk4_cnt == 2'b01) // RISING EDGE OF Q 69 | rQ <= 1; 70 | 71 | if (clk4_cnt == 2'b10) // FALLING EDGE OF E 72 | rE <= 0; 73 | 74 | if (clk4_cnt == 2'b11) // FALLING EDGE OF Q 75 | begin 76 | rQ <= 0; 77 | nCoreRESET <= 1; 78 | end 79 | end 80 | 81 | 82 | endmodule 83 | --------------------------------------------------------------------------------