HTML Online Editor Sample

├── README.md ├── fuse_tests ├── README ├── tests.expected ├── tests.in └── tests.py ├── roms ├── BASIC.HEX ├── INTMINI.HEX ├── ROM.HEX ├── basic.asm └── intmini.asm └── src ├── units ├── 16bit_arith.asm ├── 16bit_load.asm ├── 8bit_arith.asm ├── 8bit_load.asm ├── bit_set.asm ├── call_return.asm ├── exchange.asm ├── general_purp.asm ├── input_output.asm ├── jump_group.asm ├── rotate_shift.asm ├── test_register.py └── test_z80.py ├── z80 ├── __init__.py ├── gui.py ├── instructions.py ├── io.py ├── registers.py └── util.py └── z80sbc.py /README.md: -------------------------------------------------------------------------------- 1 | ## Z80 CPU Emulator 2 | 3 | This is a Zilog Z80 CPU emulator, written in Python. 4 | It runs a 1978 Microsoft Basic 4.7 ROM taken from [Grant Searle's Z80 SBC project](http://searle.hostei.com/grant/z80/SimpleZ80.html) 5 | 6 | ### Why? 7 | Just for fun. I like the Z80 CPU - it was in many devices I played with as a 8 | kid. 9 | 10 | ### Is it useful? 11 | No. It runs really slowly, and is a completely non-optimal software design for 12 | an emulator, but (in my opinion) the code is readable. If you want a CPU emulator, 13 | probably don't use Python. That said, an optimised python coded emulator could run 14 | a lot faster than this :-) 15 | 16 | ### Running 17 | BASIC: 18 | ``` 19 | cd src 20 | python z80sbc.py 21 | ``` 22 | Unit tests: 23 | ``` 24 | cd src 25 | PYTHONPATH=`pwd`:$PYTHONPATH python ../tests/test_z80.py 26 | PYTHONPATH=`pwd`:$PYTHONPATH python ../tests/test_registers.py 27 | ``` 28 | 29 | Fuse tests: 30 | ``` 31 | cd src 32 | PYTHONPATH=`pwd`:$PYTHONPATH python ../fuse_tests/tests.py 33 | ``` 34 | 35 | ### Missing and todo 36 | - Most undocumented opcodes 37 | - Undocumented flags for `CPI` and `CPIR`. 38 | 39 | ### Credits 40 | 41 | [Grant Searle's Z80 SBC project](http://searle.hostei.com/grant/z80/SimpleZ80.html) 42 | 43 | [FUSE - Free Unix Spectrum Emulator](http://fuse-emulator.sourceforge.net/) for the instruction set tests 44 | 45 | ### License 46 | Public domain; do what you like. 47 | -------------------------------------------------------------------------------- /fuse_tests/README: -------------------------------------------------------------------------------- 1 | File formats 2 | ============ 3 | 4 | tests.in 5 | -------- 6 | 7 | Each test has the format: 8 | 9 | 10 | AF BC DE HL AF' BC' DE' HL' IX IY SP PC 11 | I R IFF1 IFF2 IM 12 | 13 | specifies whether the Z80 is halted. 14 | specifies the number of tstates to run the test for, in 15 | decimal; the number actually executed may be higher, as the final 16 | instruction is allowed to complete. 17 | 18 | Then followed by lines specifying the initial memory setup. Each has 19 | the format: 20 | 21 | ... -1 22 | 23 | eg 24 | 25 | 1234 56 78 9a -1 26 | 27 | says to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236. 28 | 29 | Finally, -1 to end the test. Blank lines may follow before the next test. 30 | 31 | tests.expected 32 | -------------- 33 | 34 | Each test output starts with the test description, followed by a list 35 | of 'events': each has the format 36 | 37 |

is the address (or IO port) affected. 43 | is the byte written or read. Missing for contentions. 44 | 45 | After that, lines specifying AF, BC etc as for .in files. 46 | now specifies the final time. 47 | 48 | After that, lines specifying which bits of memory have changed since 49 | the initial setup. Same format as for .in files. 50 | 51 | Why some specific tests are here 52 | ================================ 53 | 54 | 37_{1,2,3}: check the behaviour of SCF with respect to bits 3 and 5 55 | (bug fixed on 20040225). 56 | 57 | cb{4,5,6,7}{7,f}_1: designed to check that bits 3 and 5 are copied to 58 | F only for BIT 3, and BIT 5, respectively 59 | (bug fixed on 20040225). 60 | 61 | However, later research has revealed the bits 3 62 | and 5 are copied on all BIT instructions, l. 63 | tests are now essentially redundant. 64 | 65 | d{3,b}_{1,2,3}: check for correct port contention on IO in the four 66 | relevant states (port high byte in 0x40 to 0x7f or not, 67 | port low bit set or reset). 68 | 69 | dd00.in, ddfd00.in: test timings of "extended NOP" opcodes DD 00 and 70 | DD FD 00; the extra 00 at the end is to check the 71 | next opcode executes at the right time (bug fixed 72 | on 20060722). 73 | 74 | -------------------------------------------------------------------------------- /fuse_tests/tests.py: -------------------------------------------------------------------------------- 1 | from z80 import io, gui, instructions, registers, util 2 | import copy 3 | 4 | from time import sleep, time 5 | import sys 6 | from PySide2.QtCore import * 7 | from PySide2.QtGui import * 8 | 9 | import threading 10 | import os 11 | import inspect 12 | 13 | #logging.basicConfig(level=logging.INFO) 14 | 15 | class Z80Tester(io.Interruptable): 16 | def __init__(self): 17 | self.registers = registers.Registers() 18 | self.instructions = instructions.InstructionSet(self.registers) 19 | self._memory = bytearray(64*1024) 20 | 21 | self._interrupted = False 22 | 23 | def interrupt(self): 24 | self._interrupted = True 25 | 26 | def step_instruction(self): 27 | trace = "" 28 | ins, args = False, [] 29 | pc = self.registers.PC 30 | 31 | if self._interrupted and self.registers.IFF: 32 | self.registers.IFF = False 33 | self._interrupted = False 34 | if self.registers.IM == 1: 35 | print ("!!! Interrupt !!!") 36 | ins, args = self.instructions << 0xCD 37 | ins, args = self.instructions << 0x38 38 | ins, args = self.instructions << 0x00 39 | self.registers.IFF = False 40 | else: 41 | while not ins: 42 | try: 43 | ins, args = self.instructions << self._memory[self.registers.PC] 44 | except: 45 | raise Exception("Can't decode instruction.") 46 | self.registers.PC = util.inc16(self.registers.PC) 47 | trace += "{0:X} : {1}\n ".format(pc, ins.assembler(args)) 48 | 49 | rd = ins.get_read_list(args) 50 | data = [0] * len(rd) 51 | for n, i in enumerate(rd): 52 | if i < 0x10000: 53 | data[n] = self._memory[i] 54 | else: 55 | address = i & 0xFF 56 | #data[n] = self._iomap.address[address].read(address) 57 | data[n] = self.registers.A 58 | print ("Read IO "), 59 | raise Exception("Skip.") 60 | wrt = ins.execute(data, args) 61 | for i in wrt: 62 | 63 | if i[0] > 0x10000: 64 | address = i[0] & 0xFF 65 | #iomap.address[address].write.emit(address, i[1]) 66 | #self._iomap.address[address].write(address, i[1]) 67 | #print (chr(i[1])) 68 | print ("Write IO "), 69 | raise Exception("Skip.") 70 | else: 71 | try: 72 | self._memory[i[0]] = i[1] 73 | except: 74 | print (i) 75 | print (trace) 76 | raise 77 | return ins.tstates, trace 78 | 79 | 80 | if __name__ == '__main__': 81 | ''' Main Program ''' 82 | mach = Z80Tester() 83 | infile = file = os.path.join(os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe()))), 84 | "tests.in") 85 | expectfile = file = os.path.join(os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe()))), 86 | "tests.expected") 87 | 88 | with open(infile, "r") as f: 89 | tests_in = f.read() 90 | 91 | with open(expectfile, "r") as f: 92 | tests_expected = f.read() 93 | fails = passes = 0 94 | for t, results in zip(tests_in.split("\n\n"), tests_expected.split("\n\n")): 95 | #print "---\n", t, "\n====\n", results,"\n---\n" 96 | test_lines = t.split("\n") 97 | test_key = test_lines[0] 98 | regs = [int(s, 16) for s in test_lines[1].split()] 99 | mach.registers.AF = regs[0] 100 | mach.registers.BC = regs[1] 101 | mach.registers.DE = regs[2] 102 | mach.registers.HL = regs[3] 103 | mach.registers.A_ = regs[4] >> 8 104 | mach.registers.F_ = regs[4] & 0xFF 105 | mach.registers.B_ = regs[5] >> 8 106 | mach.registers.C_ = regs[5] & 0xFF 107 | mach.registers.D_ = regs[6] >> 8 108 | mach.registers.E_ = regs[6] & 0xFF 109 | mach.registers.H_ = regs[7] >> 8 110 | mach.registers.L_ = regs[7] & 0xFF 111 | mach.registers.IX = regs[8] 112 | mach.registers.IY = regs[9] 113 | mach.registers.SP = regs[10] 114 | mach.registers.PC = regs[11] 115 | regs2 = [s for s in test_lines[2].split()] 116 | mach.registers.I = int(regs2[0], 16) 117 | mach.registers.R = int(regs2[1], 16) 118 | mach.registers.IFF = regs2[2] == "1" 119 | mach.registers.IFF2 = regs2[3] == "1" 120 | mach.registers.IFF2 = regs2[3] == "1" 121 | mach.registers.IM = regs2[4] == "1" 122 | mach.registers.HALT = regs2[5] == "1" 123 | tstates = int(regs2[6]) 124 | for memline in test_lines[3:]: 125 | memsplit = memline.split() 126 | base = int(memsplit[0], 16) 127 | for val in memsplit[1:-1]: 128 | if int(val, 16) == -1: 129 | continue 130 | mach._memory[base] = int(val, 16) 131 | base += 1 132 | 133 | 134 | print (": Test '%s' : "%(str(test_key))), 135 | if test_key.startswith("27"): 136 | print ("SKIPPED") 137 | continue 138 | trace = "" 139 | taken= 0 140 | try: 141 | while taken < tstates: 142 | states, asm = mach.step_instruction() 143 | taken += states 144 | trace += "%d/%d\t%d\t" % (taken, tstates, states) + asm 145 | except Exception as e: 146 | if e == "Can't decode instruction.": 147 | print (" - NO INSTRUCTION") 148 | mach.instructions.reset_composer() 149 | continue 150 | elif e == "Skip.": 151 | print ("Skipped.") 152 | mach.instructions.reset_composer() 153 | continue 154 | else: 155 | print ("FAULTY") 156 | mach.instructions.reset_composer() 157 | raise 158 | 159 | expected_lines = results.split('\n') 160 | if expected_lines[0] != test_key: 161 | print ("Test expectation mismatch") 162 | sys.exit(1) 163 | i = 1 164 | while expected_lines[i].startswith(" "): 165 | i += 1 166 | regs = [int(s, 16) for s in expected_lines[i].split()] 167 | try: 168 | if mach.registers.A != regs[0] >> 8: 169 | raise Exception("Bad A register") 170 | if mach.registers.BC != regs[1]: 171 | raise Exception("Bad register") 172 | if mach.registers.DE != regs[2]: 173 | raise Exception("Bad register") 174 | if mach.registers.HL != regs[3]: 175 | raise Exception("Bad register") 176 | if mach.registers.A_ != regs[4] >> 8: 177 | raise Exception("Bad register") 178 | if mach.registers.F_ != regs[4] & 0xFF: 179 | raise Exception("Bad register") 180 | if mach.registers.B_ != regs[5] >> 8: 181 | raise Exception("Bad register") 182 | if mach.registers.C_ != regs[5] & 0xFF: 183 | raise Exception("Bad register") 184 | if mach.registers.D_ != regs[6] >> 8: 185 | raise Exception("Bad register") 186 | if mach.registers.E_ != regs[6] & 0xFF: 187 | raise Exception("Bad register") 188 | if mach.registers.H_ != regs[7] >> 8: 189 | raise Exception("Bad register") 190 | if mach.registers.L_ != regs[7] & 0xFF: 191 | raise Exception("Bad register") 192 | if mach.registers.IX != regs[8]: 193 | raise Exception("Bad register") 194 | if mach.registers.IY != regs[9]: 195 | raise Exception("Bad register") 196 | if mach.registers.SP != regs[10]: 197 | raise Exception("Bad register") 198 | if mach.registers.PC != regs[11]: 199 | raise Exception("Bad register") 200 | regs2 = [s for s in expected_lines[i+1].split()] 201 | if mach.registers.I != int(regs2[0], 16): 202 | raise Exception("Bad register") 203 | #if mach.registers.R != regs2[1]: 204 | #raise Exception("Bad register") 205 | if mach.registers.IFF != (regs2[2] == "1"): 206 | print ("Bad interrups flag flop") 207 | print (regs2[2]) 208 | print (mach.registers.IFF) 209 | raise Exception("Bad register") 210 | if mach.registers.IFF2 != (regs2[3] == "1"): 211 | print ("Bad interrups flag flop") 212 | print (regs2[3]) 213 | print (mach.registers.IFF2) 214 | raise Exception("Bad register") 215 | #if mach.registers.IFF2 != (regs2[3] == "1"): 216 | #raise Exception("Bad register") 217 | if mach.registers.IM != int(regs2[4]): 218 | raise Exception("Bad register") 219 | if mach.registers.HALT != (regs2[5] == "1"): 220 | raise Exception("Bad HALT register. "+str(mach.registers.HALT)+"!="+ str(regs2[5]=='1')) 221 | if taken != int(regs2[6]): 222 | raise Exception("Bad number of tstates taken.") 223 | 224 | if mach.registers.F != regs[0] & 0xFF: 225 | raise Exception("Bad F register") 226 | 227 | for memline in expected_lines[i+3:]: 228 | memsplit = memline.split() 229 | base = int(memsplit[0], 16) 230 | for val in memsplit[1:-1]: 231 | if int(val, 16) == -1: 232 | continue 233 | if mach._memory[base] != int(val, 16): 234 | raise Exception("Memory mismatch") 235 | base += 1 236 | except Exception as e: 237 | print ("FAILED:",e.message) 238 | fails += 1 239 | continue 240 | print ("TRACE:") 241 | print (trace) 242 | print ("") 243 | flags = ["S", "Z", "F5", "H", "F3", "PV", "N", "C"] 244 | s = "" 245 | for i, f in enumerate(flags): 246 | s += f+':' + str((regs[0] >> (7 - i)) & 0x01) + ' ' 247 | print ("\nTarget flags: ", s) 248 | s = "" 249 | for i, f in enumerate(flags): 250 | s += f+':' + str((mach.registers.F >> (7 - i)) & 0x01) + ' ' 251 | print ("Actual flags: ", s) 252 | print 253 | print ("--INITIAL--\n", t, "\n--TARGET--\n", results,"\n==--==\n") 254 | regs = ['PC', 'SP', 'I', 255 | 'A', 'F', 'B', 'C', 256 | 'D', 'E', 'H', 'L', 257 | 'IFF'] 258 | regsr = ['IX', 'IY', 'R','A_', 'F_', 'B_', 'C_','D_', 'E_','H_', 'L_', 'IM'] 259 | print ("Registers:") 260 | for rl, rr in zip(regs, regsr): 261 | print (rl, ": {0:X}".format( mach.registers[rl]), "\t\t", rr, ": {0:X}".format( mach.registers[rr])) 262 | raise 263 | print ("PASSED") 264 | passes += 1 265 | 266 | print ("Failed:", fails) 267 | print ("Passed:", passes) 268 | print ("Passed:", passes) -------------------------------------------------------------------------------- /roms/BASIC.HEX: -------------------------------------------------------------------------------- 1 | :18015000C35601C3F401DD210000C36101070A7D11214520F9C39C1D08 2 | :18016800112E0406632145201A77231305C27001F9CD2F06CDFD0B324C 3 | :18018000EF20323E21214302CD9B12CD4C06CD5509B7C2AA0121A22195 4 | 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:201D8000CA7C1DFE30D8FE323FC91E28C31105DD21FFFFC36101C30800C300003E003292D2 238 | :201DA00020C36801ED45F5A0C1B83E00C9CDD607C3FD0BFFFFFFFFFFFFFFFFFFFFFFFFFF28 239 | :201DC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF23 240 | :201DE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF03 241 | :201E0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE2 242 | :201E2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC2 243 | :201E4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA2 244 | :201E6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF82 245 | :201E8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF62 246 | :201EA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF42 247 | :201EC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF22 248 | :201EE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF02 249 | :201F0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE1 250 | :201F2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC1 251 | :201F4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA1 252 | :201F6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81 253 | :201F8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF61 254 | :201FA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF41 255 | :201FC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF21 256 | :201FE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01 257 | :00000001FF 258 | -------------------------------------------------------------------------------- /roms/intmini.asm: -------------------------------------------------------------------------------- 1 | ;================================================================================== 2 | ; Contents of this file are copyright Grant Searle 3 | ; 4 | ; You have permission to use this for NON COMMERCIAL USE ONLY 5 | ; If you wish to use it elsewhere, please include an acknowledgement to myself. 6 | ; 7 | ; http://searle.hostei.com/grant/index.html 8 | ; 9 | ; eMail: home.micros01@btinternet.com 10 | ; 11 | ; If the above don't work, please perform an Internet search to see if I have 12 | ; updated the web page hosting service. 13 | ; 14 | ;================================================================================== 15 | 16 | ; Minimum 6850 ACIA interrupt driven serial I/O to run modified NASCOM Basic 4.7 17 | ; Full input buffering with incoming data hardware handshaking 18 | ; Handshake shows full before the buffer is totally filled to allow run-on from the sender 19 | 20 | SER_BUFSIZE .EQU 3FH 21 | SER_FULLSIZE .EQU 30H 22 | SER_EMPTYSIZE .EQU 5 23 | 24 | RTS_HIGH .EQU 0D6H 25 | RTS_LOW .EQU 096H 26 | 27 | serBuf .EQU $2000 28 | serInPtr .EQU serBuf+SER_BUFSIZE 29 | serRdPtr .EQU serInPtr+2 30 | serBufUsed .EQU serRdPtr+2 31 | basicStarted .EQU serBufUsed+1 32 | TEMPSTACK .EQU $20ED ; Top of BASIC line input buffer so is "free ram" when BASIC resets 33 | 34 | CR .EQU 0DH 35 | LF .EQU 0AH 36 | CS .EQU 0CH ; Clear screen 37 | 38 | .ORG $0000 39 | ;------------------------------------------------------------------------------ 40 | ; Reset 41 | 42 | RST00 DI ;Disable interrupts 43 | JP INIT ;Initialize Hardware and go 44 | 45 | ;------------------------------------------------------------------------------ 46 | ; TX a character over RS232 47 | 48 | .ORG 0008H 49 | RST08 JP TXA 50 | 51 | ;------------------------------------------------------------------------------ 52 | ; RX a character over RS232 Channel A [Console], hold here until char ready. 53 | 54 | .ORG 0010H 55 | RST10 JP RXA 56 | 57 | ;------------------------------------------------------------------------------ 58 | ; Check serial status 59 | 60 | .ORG 0018H 61 | RST18 JP CKINCHAR 62 | 63 | ;------------------------------------------------------------------------------ 64 | ; RST 38 - INTERRUPT VECTOR [ for IM 1 ] 65 | 66 | .ORG 0038H 67 | RST38 JR serialInt 68 | 69 | ;------------------------------------------------------------------------------ 70 | serialInt: PUSH AF 71 | PUSH HL 72 | 73 | IN A,($80) 74 | AND $01 ; Check if interupt due to read buffer full 75 | JR Z,rts0 ; if not, ignore 76 | 77 | IN A,($81) 78 | PUSH AF 79 | LD A,(serBufUsed) 80 | CP SER_BUFSIZE ; If full then ignore 81 | JR NZ,notFull 82 | POP AF 83 | JR rts0 84 | 85 | notFull: LD HL,(serInPtr) 86 | INC HL 87 | LD A,L ; Only need to check low byte becasuse buffer<256 bytes 88 | CP (serBuf+SER_BUFSIZE) & $FF 89 | JR NZ, notWrap 90 | LD HL,serBuf 91 | notWrap: LD (serInPtr),HL 92 | POP AF 93 | LD (HL),A 94 | LD A,(serBufUsed) 95 | INC A 96 | LD (serBufUsed),A 97 | CP SER_FULLSIZE 98 | JR C,rts0 99 | LD A,RTS_HIGH 100 | OUT ($80),A 101 | rts0: POP HL 102 | POP AF 103 | EI 104 | RETI 105 | 106 | ;------------------------------------------------------------------------------ 107 | RXA: 108 | waitForChar: LD A,(serBufUsed) 109 | CP $00 110 | JR Z, waitForChar 111 | PUSH HL 112 | LD HL,(serRdPtr) 113 | INC HL 114 | LD A,L ; Only need to check low byte becasuse buffer<256 bytes 115 | CP (serBuf+SER_BUFSIZE) & $FF 116 | JR NZ, notRdWrap 117 | LD HL,serBuf 118 | notRdWrap: DI 119 | LD (serRdPtr),HL 120 | LD A,(serBufUsed) 121 | DEC A 122 | LD (serBufUsed),A 123 | CP SER_EMPTYSIZE 124 | JR NC,rts1 125 | LD A,RTS_LOW 126 | OUT ($80),A 127 | rts1: 128 | LD A,(HL) 129 | EI 130 | POP HL 131 | RET ; Char ready in A 132 | 133 | ;------------------------------------------------------------------------------ 134 | TXA: PUSH AF ; Store character 135 | conout1: IN A,($80) ; Status byte 136 | BIT 1,A ; Set Zero flag if still transmitting character 137 | JR Z,conout1 ; Loop until flag signals ready 138 | POP AF ; Retrieve character 139 | OUT ($81),A ; Output the character 140 | RET 141 | 142 | ;------------------------------------------------------------------------------ 143 | CKINCHAR LD A,(serBufUsed) 144 | CP $0 145 | RET 146 | 147 | PRINT: LD A,(HL) ; Get character 148 | OR A ; Is it $00 ? 149 | RET Z ; Then RETurn on terminator 150 | RST 08H ; Print it 151 | INC HL ; Next Character 152 | JR PRINT ; Continue until $00 153 | RET 154 | ;------------------------------------------------------------------------------ 155 | INIT: 156 | LD HL,TEMPSTACK ; Temp stack 157 | LD SP,HL ; Set up a temporary stack 158 | LD HL,serBuf 159 | LD (serInPtr),HL 160 | LD (serRdPtr),HL 161 | XOR A ;0 to accumulator 162 | LD (serBufUsed),A 163 | LD A,RTS_LOW 164 | OUT ($80),A ; Initialise ACIA 165 | IM 1 166 | EI 167 | LD HL,SIGNON1 ; Sign-on message 168 | CALL PRINT ; Output string 169 | LD A,(basicStarted); Check the BASIC STARTED flag 170 | CP 'Y' ; to see if this is power-up 171 | JR NZ,COLDSTART ; If not BASIC started then always do cold start 172 | LD HL,SIGNON2 ; Cold/warm message 173 | CALL PRINT ; Output string 174 | CORW: 175 | CALL RXA 176 | AND %11011111 ; lower to uppercase 177 | CP 'C' 178 | JR NZ, CHECKWARM 179 | RST 08H 180 | LD A,$0D 181 | RST 08H 182 | LD A,$0A 183 | RST 08H 184 | COLDSTART: LD A,'Y' ; Set the BASIC STARTED flag 185 | LD (basicStarted),A 186 | JP $0150 ; Start BASIC COLD 187 | CHECKWARM: 188 | CP 'W' 189 | JR NZ, CORW 190 | RST 08H 191 | LD A,$0D 192 | RST 08H 193 | LD A,$0A 194 | RST 08H 195 | JP $0153 ; Start BASIC WARM 196 | 197 | SIGNON1: .BYTE CS 198 | .BYTE "Z80 SBC By Grant Searle",CR,LF,0 199 | SIGNON2: .BYTE CR,LF 200 | .BYTE "Cold or warm start (C or W)? ",0 201 | 202 | .END 203 | -------------------------------------------------------------------------------- /src/units/16bit_arith.asm: -------------------------------------------------------------------------------- 1 | ADD HL, SP 2 | ADD HL, BC 3 | ADD HL, DE 4 | ADD HL, HL 5 | ADC HL, SP 6 | ADC HL, BC 7 | ADC HL, DE 8 | ADC HL, HL 9 | SBC HL, SP 10 | SBC HL, BC 11 | SBC HL, DE 12 | SBC HL, HL 13 | ADD IX, SP 14 | ADD IX, BC 15 | ADD IX, DE 16 | ADD IX, IX 17 | ADD IY, SP 18 | ADD IY, BC 19 | ADD IY, DE 20 | add IY, IY 21 | inc hl 22 | inc bc 23 | inc de 24 | inc sp 25 | inc ix 26 | inc iy 27 | dec hl 28 | dec bc 29 | dec de 30 | dec sp 31 | DEC ix 32 | dec iy 33 | -------------------------------------------------------------------------------- /src/units/16bit_load.asm: -------------------------------------------------------------------------------- 1 | PUSH DE 2 | PUSH BC 3 | PUSH HL 4 | PUSH AF 5 | PUSH IX 6 | PUSH IY 7 | POP IY 8 | POP IX 9 | POP DE 10 | POP BC 11 | POP HL 12 | POP AF 13 | LD SP, HL 14 | LD BC, 4567H 15 | LD DE, 4567H 16 | LD HL, 4567H 17 | LD IX, 4567H 18 | LD IY, 4567H 19 | LD SP, 4567H 20 | LD BC, (4567H) 21 | LD DE, (4567H) 22 | LD HL, (4567H) 23 | LD IX, (4567H) 24 | LD IY, (4567H) 25 | LD SP, (4567H) 26 | LD (4567H), IX 27 | LD (4567H), IY 28 | LD (4567H), SP 29 | LD (4567H), BC 30 | LD (4567H), DE 31 | LD (4567H), HL 32 | LD SP, HL 33 | LD SP, IX 34 | LD SP, IY 35 | -------------------------------------------------------------------------------- /src/units/8bit_arith.asm: -------------------------------------------------------------------------------- 1 | ADD A, A 2 | ADD A, B 3 | ADD A, C 4 | ADD A, D 5 | ADD A, E 6 | ADD A, H 7 | ADD A, L 8 | ADD A, (HL) 9 | ADD A, 45H 10 | ADD A, (IX+45H) 11 | ADC A, A 12 | ADC A, B 13 | ADC A, C 14 | ADC A, D 15 | ADC A, E 16 | ADC A, H 17 | ADC A, L 18 | ADC A, (HL) 19 | ADC A, 45H 20 | ADC A, (IX+45H) 21 | SUB A, A 22 | SUB A, B 23 | SUB A, C 24 | SUB A, D 25 | SUB A, E 26 | SUB A, H 27 | SUB A, L 28 | SUB A, (HL) 29 | SUB A, 45H 30 | SUB A, (IX+45H) 31 | AND A 32 | AND B 33 | AND C 34 | AND D 35 | AND E 36 | AND H 37 | AND L 38 | AND (HL) 39 | AND 56H 40 | AND (IX+54H) 41 | AND (IY+54H) 42 | OR A 43 | OR B 44 | OR C 45 | OR D 46 | OR E 47 | OR H 48 | OR L 49 | OR (HL) 50 | OR 56H 51 | OR (IX+54H) 52 | OR (IY+54H) 53 | XOR A 54 | XOR B 55 | XOR C 56 | XOR D 57 | XOR E 58 | XOR H 59 | XOR L 60 | XOR (HL) 61 | XOR 56H 62 | XOR (IX+54H) 63 | XOR (IY+54H) 64 | CP A 65 | CP B 66 | CP C 67 | CP D 68 | CP E 69 | CP H 70 | CP L 71 | CP (HL) 72 | CP 56H 73 | CP (IX+54H) 74 | CP (IY+54H) 75 | INC A 76 | INC B 77 | INC C 78 | INC D 79 | INC E 80 | INC H 81 | INC L 82 | INC (HL) 83 | INC (IX+76H) 84 | INC (IY+76H) 85 | DEC A 86 | DEC B 87 | DEC C 88 | DEC D 89 | DEC E 90 | DEC H 91 | DEC L 92 | DEC (HL) 93 | DEC (IX+76H) 94 | DEC (IY+76H) 95 | 96 | 97 | -------------------------------------------------------------------------------- /src/units/8bit_load.asm: -------------------------------------------------------------------------------- 1 | LD A, A 2 | LD A, B 3 | LD A, C 4 | LD A, D 5 | LD A, E 6 | LD A, H 7 | LD A, L 8 | LD A, I 9 | LD A, R 10 | LD B, A 11 | LD B, B 12 | LD B, C 13 | LD B, D 14 | LD B, E 15 | LD B, H 16 | LD B, L 17 | LD C, A 18 | LD C, B 19 | LD C, C 20 | LD C, D 21 | LD C, E 22 | LD C, H 23 | LD C, L 24 | LD D, A 25 | LD D, B 26 | LD D, C 27 | LD D, D 28 | LD D, E 29 | LD D, H 30 | LD D, L 31 | LD E, A 32 | LD E, B 33 | LD E, C 34 | LD E, D 35 | LD E, E 36 | LD E, H 37 | LD H, A 38 | LD H, B 39 | LD H, C 40 | LD H, D 41 | LD H, E 42 | LD H, H 43 | LD H, L 44 | LD L, A 45 | LD L, B 46 | LD L, C 47 | LD L, D 48 | LD L, E 49 | LD L, H 50 | LD L, L 51 | LD E, A 52 | LD I, A 53 | LD R, A 54 | LD (HL), A 55 | LD (HL), B 56 | LD (HL), C 57 | LD (HL), D 58 | LD (HL), E 59 | LD (HL), H 60 | LD (HL), L 61 | LD A, (HL) 62 | LD B, (HL) 63 | LD C, (HL) 64 | LD D, (HL) 65 | LD E, (HL) 66 | LD H, (HL) 67 | LD L, (HL) 68 | LD (BC), A 69 | LD (DE), A 70 | LD A, (BC) 71 | LD A, (DE) 72 | LD A, (IX+3DH) 73 | LD B, (IX+3DH) 74 | LD C, (IX+3DH) 75 | LD D, (IX+3DH) 76 | LD E, (IX+3DH) 77 | LD H, (IX+3DH) 78 | LD L, (IX+3DH) 79 | LD A, (IY+1DH) 80 | LD B, (IY+8DH) 81 | LD C, (IY+2DH) 82 | LD D, (IY+15H) 83 | LD E, (IY+3DH) 84 | LD H, (IY+3DH) 85 | LD L, (IY+3DH) 86 | LD A, (IX+3DH) 87 | LD B, (IX+3DH) 88 | LD C, (IX+3DH) 89 | LD D, (IX+3DH) 90 | LD E, (IX+3DH) 91 | LD H, (IX+3DH) 92 | LD L, (IX+3DH) 93 | LD A, (IY+1DH) 94 | LD B, (IY+8DH) 95 | LD C, (IY+2DH) 96 | LD D, (IY+15H) 97 | LD E, (IY+3DH) 98 | LD H, (IY+3DH) 99 | LD (IX+3DH), A 100 | LD (IX+3DH), B 101 | LD (IX+3DH), C 102 | LD (IX+3DH), D 103 | LD (IX+3DH), E 104 | LD (IX+3DH), H 105 | LD (IX+3DH), L 106 | LD (IY+3DH), A 107 | LD (IY+3DH), B 108 | LD (IY+3DH), C 109 | LD (IY+3DH), D 110 | LD (IY+3DH), E 111 | LD (IY+3DH), H 112 | LD (IY+3DH), L 113 | LD A, 31H 114 | LD B, 31H 115 | LD C, 31H 116 | LD D, 31H 117 | LD E, 31H 118 | LD H, 31H 119 | LD L, 31H 120 | LD (BC), A 121 | LD (DE), A 122 | LD I, A 123 | LD R, A 124 | LD A, (8765H) 125 | LD (8762H), A 126 | LD (IX+87H), 65H 127 | LD (IY+87H), 65H -------------------------------------------------------------------------------- /src/units/bit_set.asm: -------------------------------------------------------------------------------- 1 | BIT 0, A 2 | BIT 0, B 3 | BIT 0, C 4 | BIT 0, D 5 | BIT 0, E 6 | BIT 0, H 7 | BIT 0, L 8 | BIT 1, A 9 | BIT 1, B 10 | BIT 1, C 11 | BIT 1, D 12 | BIT 1, E 13 | BIT 1, H 14 | BIT 1, L 15 | BIT 2, A 16 | BIT 2, B 17 | BIT 2, C 18 | BIT 2, D 19 | BIT 2, E 20 | BIT 2, H 21 | BIT 2, L 22 | BIT 3, A 23 | BIT 3, B 24 | BIT 3, C 25 | BIT 3, D 26 | BIT 3, E 27 | BIT 3, H 28 | BIT 3, L 29 | BIT 4, A 30 | BIT 4, B 31 | BIT 4, C 32 | BIT 4, D 33 | BIT 4, E 34 | BIT 4, H 35 | BIT 4, L 36 | BIT 5, A 37 | BIT 5, B 38 | BIT 5, C 39 | BIT 5, D 40 | BIT 5, E 41 | BIT 5, H 42 | BIT 5, L 43 | BIT 6, A 44 | BIT 6, B 45 | BIT 6, C 46 | BIT 6, D 47 | BIT 6, E 48 | BIT 6, H 49 | BIT 6, L 50 | BIT 7, A 51 | BIT 7, B 52 | BIT 7, C 53 | BIT 7, D 54 | BIT 7, E 55 | BIT 7, H 56 | BIT 7, L 57 | BIT 0, (HL) 58 | BIT 1, (HL) 59 | BIT 2, (HL) 60 | BIT 3, (HL) 61 | BIT 4, (HL) 62 | BIT 5, (HL) 63 | BIT 6, (HL) 64 | BIT 7, (HL) 65 | BIT 0, (IX+87H) 66 | BIT 1, (IX+87H) 67 | BIT 2, (IX+87H) 68 | BIT 3, (IX+87H) 69 | BIT 4, (IX+87H) 70 | BIT 5, (IX+87H) 71 | BIT 6, (IX+87H) 72 | BIT 7, (IX+87H) 73 | BIT 0, (IY+87H) 74 | BIT 1, (IY+87H) 75 | BIT 2, (IY+87H) 76 | BIT 3, (IY+87H) 77 | BIT 4, (IY+87H) 78 | BIT 5, (IY+87H) 79 | BIT 6, (IY+87H) 80 | BIT 7, (IY+87H) 81 | SET 0, A 82 | SET 0, B 83 | SET 0, C 84 | SET 0, D 85 | SET 0, E 86 | SET 0, H 87 | SET 0, L 88 | SET 1, A 89 | SET 1, B 90 | SET 1, C 91 | SET 1, D 92 | SET 1, E 93 | SET 1, H 94 | SET 1, L 95 | SET 2, A 96 | SET 2, B 97 | SET 2, C 98 | SET 2, D 99 | SET 2, E 100 | SET 2, H 101 | SET 2, L 102 | SET 3, A 103 | SET 3, B 104 | SET 3, C 105 | SET 3, D 106 | SET 3, E 107 | SET 3, H 108 | SET 3, L 109 | SET 4, A 110 | SET 4, B 111 | SET 4, C 112 | SET 4, D 113 | SET 4, E 114 | SET 4, H 115 | SET 4, L 116 | SET 5, A 117 | SET 5, B 118 | SET 5, C 119 | SET 5, D 120 | SET 5, E 121 | SET 5, H 122 | SET 5, L 123 | SET 6, A 124 | SET 6, B 125 | SET 6, C 126 | SET 6, D 127 | SET 6, E 128 | SET 6, H 129 | SET 6, L 130 | SET 7, A 131 | SET 7, B 132 | SET 7, C 133 | SET 7, D 134 | SET 7, E 135 | SET 7, H 136 | SET 7, L 137 | SET 0, (HL) 138 | SET 1, (HL) 139 | SET 2, (HL) 140 | SET 3, (HL) 141 | SET 4, (HL) 142 | SET 5, (HL) 143 | SET 6, (HL) 144 | SET 7, (HL) 145 | SET 0, (IX+87H) 146 | SET 1, (IX+87H) 147 | SET 2, (IX+87H) 148 | SET 3, (IX+87H) 149 | SET 4, (IX+87H) 150 | SET 5, (IX+87H) 151 | SET 6, (IX+87H) 152 | SET 7, (IX+87H) 153 | SET 0, (IY+87H) 154 | SET 1, (IY+87H) 155 | SET 2, (IY+87H) 156 | SET 3, (IY+87H) 157 | SET 4, (IY+87H) 158 | SET 5, (IY+87H) 159 | SET 6, (IY+87H) 160 | SET 7, (IY+87H) 161 | RES 0, A 162 | RES 0, B 163 | RES 0, C 164 | RES 0, D 165 | RES 0, E 166 | RES 0, H 167 | RES 0, L 168 | RES 1, A 169 | RES 1, B 170 | RES 1, C 171 | RES 1, D 172 | RES 1, E 173 | RES 1, H 174 | RES 1, L 175 | RES 2, A 176 | RES 2, B 177 | RES 2, C 178 | RES 2, D 179 | RES 2, E 180 | RES 2, H 181 | RES 2, L 182 | RES 3, A 183 | RES 3, B 184 | RES 3, C 185 | RES 3, D 186 | RES 3, E 187 | RES 3, H 188 | RES 3, L 189 | RES 4, A 190 | RES 4, B 191 | RES 4, C 192 | RES 4, D 193 | RES 4, E 194 | RES 4, H 195 | RES 4, L 196 | RES 5, A 197 | RES 5, B 198 | RES 5, C 199 | RES 5, D 200 | RES 5, E 201 | RES 5, H 202 | RES 5, L 203 | RES 6, A 204 | RES 6, B 205 | RES 6, C 206 | RES 6, D 207 | RES 6, E 208 | RES 6, H 209 | RES 6, L 210 | RES 7, A 211 | RES 7, B 212 | RES 7, C 213 | RES 7, D 214 | RES 7, E 215 | RES 7, H 216 | RES 7, L 217 | RES 0, (HL) 218 | RES 1, (HL) 219 | RES 2, (HL) 220 | RES 3, (HL) 221 | RES 4, (HL) 222 | RES 5, (HL) 223 | RES 6, (HL) 224 | RES 7, (HL) 225 | RES 0, (IX+87H) 226 | RES 1, (IX+87H) 227 | RES 2, (IX+87H) 228 | RES 3, (IX+87H) 229 | RES 4, (IX+87H) 230 | RES 5, (IX+87H) 231 | RES 6, (IX+87H) 232 | RES 7, (IX+87H) 233 | RES 0, (IY+87H) 234 | RES 1, (IY+87H) 235 | RES 2, (IY+87H) 236 | RES 3, (IY+87H) 237 | RES 4, (IY+87H) 238 | RES 5, (IY+87H) 239 | RES 6, (IY+87H) 240 | RES 7, (IY+87H) -------------------------------------------------------------------------------- /src/units/call_return.asm: -------------------------------------------------------------------------------- 1 | CALL 7219H 2 | CALL NZ, 7219H 3 | CALL Z, 7219H 4 | CALL NC, 7219H 5 | CALL C, 7219H 6 | CALL PO, 7219H 7 | CALL PE, 7219H 8 | CALL P, 7219H 9 | CALL M, 7219H 10 | RETI 11 | RETN 12 | RET 13 | RET NZ 14 | RET Z 15 | RET NC 16 | RET C 17 | RET PO 18 | RET PE 19 | RET P 20 | RET M 21 | RST 0H 22 | RST 8H 23 | RST 10H 24 | RST 18H 25 | RST 20H 26 | RST 28H 27 | RST 30H 28 | RST 38H -------------------------------------------------------------------------------- /src/units/exchange.asm: -------------------------------------------------------------------------------- 1 | EX DE, HL 2 | EX AF, AF' 3 | EXX 4 | EX (SP), HL 5 | EX (SP), IX 6 | EX (SP), IY 7 | LDI 8 | LDIR 9 | LDD 10 | LDDR 11 | CPI 12 | CPIR 13 | CPD 14 | CPDR 15 | -------------------------------------------------------------------------------- /src/units/general_purp.asm: -------------------------------------------------------------------------------- 1 | CPL 2 | DAA 3 | NEG 4 | CCF 5 | SCF 6 | HALT 7 | DI 8 | EI 9 | NOP 10 | IM 0 11 | IM 1 12 | IM 2 13 | 14 | 15 | -------------------------------------------------------------------------------- /src/units/input_output.asm: -------------------------------------------------------------------------------- 1 | IN A, (32H) 2 | IN B, (C) 3 | IN C, (C) 4 | IN D, (C) 5 | IN E, (C) 6 | IN F, (C) 7 | IN H, (C) 8 | IN L, (C) 9 | INI 10 | INIR 11 | IND 12 | INDR 13 | OUT (32H), A 14 | OUT (C), B 15 | OUT (C), C 16 | OUT (C), D 17 | OUT (C), E 18 | OUT (C), H 19 | OUT (C), L 20 | OUTI 21 | OTIR 22 | OUTD 23 | OTDR 24 | 25 | 26 | -------------------------------------------------------------------------------- /src/units/jump_group.asm: -------------------------------------------------------------------------------- 1 | JP 7219H 2 | JP NZ, 7219H 3 | JP Z, 7219H 4 | JP NC, 7219H 5 | JP C, 7219H 6 | JP PO, 7219H 7 | JP PE, 7219H 8 | JP P, 7219H 9 | JP M, 7219H 10 | JP (HL) 11 | JP (IX) 12 | JP (IY) -------------------------------------------------------------------------------- /src/units/rotate_shift.asm: -------------------------------------------------------------------------------- 1 | RLCA 2 | RLA 3 | RRA 4 | RLC A 5 | RLC B 6 | RLC C 7 | RLC D 8 | RLC E 9 | RLC H 10 | RLC L 11 | RLC (HL) 12 | RLC (IX+87H) 13 | RLC (IY+87H) 14 | RL A 15 | RL B 16 | RL C 17 | RL D 18 | RL E 19 | RL h 20 | RL l 21 | rl (hl) 22 | rl (ix+65h) 23 | rl (iy+43h) 24 | rr a 25 | rr b 26 | rr c 27 | rr d 28 | rr e 29 | rr h 30 | rr l 31 | rr (hl) 32 | rr (ix+87H) 33 | rr (iy+71H) 34 | rrc a 35 | rrc b 36 | rrc c 37 | rrc d 38 | rrc e 39 | rrc h 40 | rrc l 41 | rrc (hl) 42 | rrc (ix+87H) 43 | rrc (iy+71H) 44 | sla a 45 | sla b 46 | sla c 47 | sla d 48 | sla e 49 | sla h 50 | sla l 51 | sla (hl) 52 | sla (ix+76H) 53 | sla (iy+87h) 54 | sra a 55 | sra b 56 | sra c 57 | sra d 58 | sra e 59 | sra h 60 | sra l 61 | sra (hl) 62 | sra (ix+76H) 63 | sra (iy+87h) 64 | rld 65 | rrd -------------------------------------------------------------------------------- /src/units/test_register.py: -------------------------------------------------------------------------------- 1 | from z80 import registers 2 | import unittest 3 | 4 | class TestZ80Registers(unittest.TestCase): 5 | 6 | def setUp(self): 7 | self.registers = registers.Registers(power=None) 8 | 9 | def test_double_register_access(self): 10 | self.registers.H = 0x45 11 | self.registers.L = 0x46 12 | self.assertEqual(self.registers.HL, 0x4546) 13 | 14 | def test_condition_flags(self): 15 | self.registers.F=0x0 16 | self.registers.condition.C=True 17 | self.assertEqual(self.registers.F, 0x01 << 0) 18 | 19 | self.registers.F=0x0 20 | self.registers.condition.S=True 21 | self.assertEqual(self.registers.F, 0x01 << 7) 22 | 23 | self.registers.F=0x0 24 | self.registers.condition.PV=True 25 | self.assertEqual(self.registers.F, 0x01 << 2) 26 | 27 | 28 | if __name__ == '__main__': 29 | unittest.main() 30 | raw_input() 31 | 32 | -------------------------------------------------------------------------------- /src/units/test_z80.py: -------------------------------------------------------------------------------- 1 | import random 2 | import unittest 3 | from time import sleep 4 | import logging 5 | logging.basicConfig(level=logging.ERROR) 6 | import subprocess 7 | from subprocess import PIPE, STDOUT, Popen 8 | from z80 import util, registers, instructions 9 | import tempfile 10 | import string 11 | import inspect 12 | import os 13 | 14 | def compile_code(code): 15 | p = Popen(["z80asm", "-o", "-"], stdout=PIPE, stdin=PIPE) 16 | 17 | by = p.communicate(input=code)[0] 18 | object_code = [ord(b) for b in by] 19 | return object_code 20 | 21 | class TestZ80Instructions(unittest.TestCase): 22 | 23 | def setUp(self): 24 | self.registers = registers.Registers(power=None) 25 | self.instructions = instructions.InstructionSet(self.registers) 26 | 27 | self.mem = bytearray(48*1024) 28 | 29 | def pass_bytes(self, bytes): 30 | for i in bytes: 31 | ins, args = self.instructions << i 32 | if ins: 33 | yield ins, args 34 | 35 | def execute(self, ins): 36 | rd = ins[0].get_read_list(ins[1]) 37 | data = [self.mem[i] for i in rd] 38 | wrt = ins[0].execute(data, ins[1]) 39 | for i in wrt: 40 | self.mem[i[0]] = i[1] 41 | 42 | def test_ld(self): 43 | by = [0x3E, 0x45] 44 | for ins in self.pass_bytes(by): 45 | print ins 46 | self.execute(ins) 47 | self.assertEqual(self.registers.A, 0x45) 48 | 49 | def _test_assembler(self, file_name): 50 | file = os.path.join(os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe()))), 51 | file_name) 52 | with open(file, "r") as f: 53 | asm = f.read() 54 | by = subprocess.check_output(["z80asm", "-i", file, "-o", "-"]) 55 | byts = [ord(b) for b in by] 56 | res = "" 57 | for ins, a in zip(self.pass_bytes(byts), asm.split("\n")): 58 | res = ins[0].assembler(ins[1]) 59 | self.assertEqual(res, a.strip().upper()) 60 | print res 61 | res = res[:-1] 62 | 63 | def test_assembler_8bit_load(self): 64 | self._test_assembler("8bit_load.asm") 65 | 66 | def test_assembler_16bit_load(self): 67 | self._test_assembler("16bit_load.asm") 68 | 69 | def test_assembler_exchange_block_transfer(self): 70 | self._test_assembler("exchange.asm") 71 | 72 | def test_assembler_8bit_arith(self): 73 | self._test_assembler("8bit_arith.asm") 74 | 75 | def test_assembler_16bit_arith(self): 76 | self._test_assembler("16bit_arith.asm") 77 | 78 | def test_assembler_general_arith(self): 79 | self._test_assembler("general_purp.asm") 80 | 81 | 82 | def test_assembler_rotate_and_shift_group(self): 83 | self._test_assembler("rotate_shift.asm") 84 | 85 | 86 | def test_assembler_bit_set_and_test_group(self): 87 | self._test_assembler("bit_set.asm") 88 | 89 | def test_assembler_jump_group(self): 90 | self._test_assembler("jump_group.asm") 91 | 92 | def test_assembler_call_return_group(self): 93 | self._test_assembler("call_return.asm") 94 | 95 | def test_assembler_input_output(self): 96 | self._test_assembler("input_output.asm") 97 | 98 | def compile_and_load(self,program): 99 | obj = compile_code(program) 100 | p=0 101 | for i in obj: 102 | self.mem[p]=i 103 | p+=1 104 | self.registers.reset() 105 | self.assertGreater(p, 0, msg="Zero length program, bad compile") 106 | return p 107 | 108 | def test_program1(self): 109 | program = ("LD A, 54H", 110 | "NOP", 111 | "LD BC, 6543H", 112 | "LD HL, 1234H", 113 | "ADD HL, BC", 114 | "ADD A, A", 115 | "SUB A, 37H", 116 | # "LD B, 0H", 117 | # "LD C, 54H", 118 | "LD BC, 54H", 119 | "INC BC", 120 | "SBC HL, BC", 121 | "ADD IX, BC", 122 | "ADD IX, IX", 123 | "ADD IX, SP", 124 | "inc ix", 125 | "inc iy", 126 | "inc iy", 127 | "dec iy", 128 | "ld b, a", 129 | "ld a, 0x01", 130 | "rla", 131 | "ld C, 1H", 132 | "rlc c", 133 | "rlc c", 134 | "rlc c", 135 | "ld iy, 1ffH", 136 | "ld (iy+0H), 0x8", 137 | "rlc (iy+0H)", 138 | "HALT" 139 | ) 140 | program = string.join(program, "\n") 141 | self.compile_and_load(program) 142 | while not self.registers.HALT: 143 | ins, args = False, [] 144 | while not ins: 145 | ins, args = self.instructions << self.mem[self.registers.PC] 146 | self.registers.PC = util.inc8(self.registers.PC) 147 | 148 | self.execute((ins, args)) 149 | print self.registers.A 150 | 151 | self.assertEqual(self.registers.B, 0x54+0x54-0x37) 152 | self.assertEqual(self.registers.HL, 0x6543+0x1234-0x55) 153 | self.assertEqual(self.registers.IX, 0x55 + 0x55 + 1) 154 | # self.assertEqual(self.registers.IY, 0x01) 155 | self.assertEqual(self.registers.A, 2) 156 | self.assertEqual(self.registers.C, 8) 157 | self.assertEqual(self.mem[0x1ff], 16) 158 | 159 | class TestAdditionSubtraction(unittest.TestCase): 160 | 161 | def setUp(self): 162 | self.registers = registers.Registers(power=None) 163 | 164 | def test_addition_overflow1_flag(self): 165 | res = util.add8(util.make_8bit_twos_comp(10), util.make_8bit_twos_comp(10), 166 | self.registers) 167 | self.assertEqual(util.get_8bit_twos_comp(res), 20) 168 | self.assertFalse(self.registers.condition.PV) 169 | 170 | def test_addition_overflow2_flag(self): 171 | res = util.add8(util.make_8bit_twos_comp(-10), util.make_8bit_twos_comp(10), 172 | self.registers) 173 | print util.get_8bit_twos_comp(res) 174 | self.assertEqual(util.get_8bit_twos_comp(res), 0) 175 | self.assertFalse(self.registers.condition.PV) 176 | self.assertFalse(self.registers.condition.S) 177 | 178 | def test_addition_overflow3_flag(self): 179 | res = util.add8(util.make_8bit_twos_comp(-10), util.make_8bit_twos_comp(-10), 180 | self.registers) 181 | self.assertEqual(util.get_8bit_twos_comp(res), util.get_8bit_twos_comp(-20)) 182 | print util.get_8bit_twos_comp(res) 183 | self.assertFalse(self.registers.condition.PV) 184 | self.assertTrue(self.registers.condition.S) 185 | 186 | def test_addition_overflow4_flag(self): 187 | res = util.add8(util.make_8bit_twos_comp(-100), util.make_8bit_twos_comp(-100), 188 | self.registers) 189 | self.assertTrue(self.registers.condition.PV) 190 | 191 | def test_addition_overflow5_flag(self): 192 | res = util.add8(util.make_8bit_twos_comp(100), util.make_8bit_twos_comp(100), 193 | self.registers) 194 | self.assertTrue(self.registers.condition.PV) 195 | 196 | def test_subtraction_overflow_flag_1(self): 197 | res = util.subtract8_check_overflow(util.make_8bit_twos_comp(10), util.make_8bit_twos_comp(10), 198 | self.registers) 199 | self.assertEqual(res, util.get_8bit_twos_comp(0)) 200 | self.assertFalse(self.registers.condition.PV) 201 | 202 | def test_subtraction_overflow_flag_2(self): 203 | res = util.subtract8_check_overflow(util.make_8bit_twos_comp(-10), util.make_8bit_twos_comp(10), 204 | self.registers) 205 | self.assertEqual(util.get_8bit_twos_comp(res), -20) 206 | self.assertFalse(self.registers.condition.PV) 207 | self.assertTrue(self.registers.condition.S) 208 | 209 | def test_subtraction_overflow_flag_3(self): 210 | res = util.subtract8_check_overflow(util.make_8bit_twos_comp(-10), util.make_8bit_twos_comp(-10), 211 | self.registers) 212 | self.assertEqual(util.get_8bit_twos_comp(res), 0) 213 | self.assertFalse(self.registers.condition.PV) 214 | 215 | def test_subtraction_overflow_flag_4(self): 216 | res = util.subtract8_check_overflow(util.make_8bit_twos_comp(-100), util.make_8bit_twos_comp(100), 217 | self.registers) 218 | self.assertTrue(self.registers.condition.PV) 219 | 220 | def test_subtraction_overflow_flag_5(self): 221 | res = util.subtract8_check_overflow(util.make_8bit_twos_comp(100), util.make_8bit_twos_comp(-100), 222 | self.registers) 223 | self.assertTrue(self.registers.condition.PV) 224 | 225 | def test_twos_comp(self): 226 | self.assertEqual(util.get_8bit_twos_comp(0b100), 4) 227 | self.assertEqual(util.get_8bit_twos_comp(0b11100011), -29) 228 | self.assertEqual(util.make_8bit_twos_comp(-29),0b11100011) 229 | self.assertEqual(util.make_8bit_twos_comp(25),0b00011001) 230 | 231 | if __name__ == '__main__': 232 | unittest.main() 233 | raw_input() -------------------------------------------------------------------------------- /src/z80/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cburbridge/z80/e85caef3be5dca385132582be565c36e9c3d8562/src/z80/__init__.py -------------------------------------------------------------------------------- /src/z80/gui.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | from PySide2.QtCore import * 4 | from PySide2.QtGui import * 5 | from PySide2.QtWidgets import * 6 | from PySide2.QtWebEngineWidgets import * 7 | 8 | from io import StringIO 9 | 10 | class RegistersGUI(QWidget): 11 | _addresses = [0x80, 0x81] 12 | _update_sgl = Signal() 13 | format_data = """ 14 | 15 | 16 | HTML Online Editor Sample 17 | 18 | 19 |

20 |

21 | 22 | 23 | 24 | 26 | 28 | 29 | 30 | 73 | 74 | 75 | 77 | 79 | 80 | 81 | 83 | 85 | 86 | 87 | 89 | 91 | 92 | 93 | 95 | 97 | 98 | 99 | 101 | 103 | 104 | 105 | 107 | 109 | 110 | 111 | 113 | 115 | 116 | 117 | 119 | 121 | 122 | 123 | 125 | 127 | 128 | 129 |

25 | A

27 | 0x{A:X}

31 | Flags 32 | 33 | 34 | 35 | 37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 52 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 | 69 | 70 | 71 |

36 \| S	38 \| Z	40 \| F5	42 \| H	44 \| F3	46 \| PV	48 \| N	50 \| C
54 \| {FS}	56 \| {FZ}	58 \| {FF5}	60 \| {FH}	62 \| {FF3}	64 \| {FPV}	66 \| {FN}	68 \| {FC}

72 |

76 | BC

78 | 0x{BC:X}

82 | DE

84 | 0x{DE:X}

88 | HL

90 | 0x{HL:X}

94 | PC

96 | 0x{PC:X}

100 | SP

102 | 0x{SP:X}

106 | IX

108 | 0x{IX:X}

112 | IY

114 | 0x{IY:X}

118 | I

120 | 0x{I:X}

124 | R

126 | 0x{R:X}

130 | 131 | 132 | 133 | """ 134 | def __init__(self, registers): 135 | super(RegistersGUI, self).__init__() 136 | 137 | vbox=QVBoxLayout() 138 | self.setLayout(vbox) 139 | 140 | self._view = QWebEngineView(self) 141 | vbox.addWidget(self._view) 142 | 143 | 144 | 145 | #self.setPlainText("") 146 | #self.setFontFamily("Mono") 147 | #self.setFontPointSize(8) 148 | #self._modifiers = {} 149 | #self.setCursorWidth(0) 150 | self._registers = registers 151 | self._update_sgl.connect(self._update) 152 | #self.setReadOnly(True) 153 | self.setGeometry(100, 0, 200, 480) 154 | 155 | self.update() 156 | 157 | @Slot() 158 | def update(self): 159 | #print "WRITE ", address 160 | self._update_sgl.emit() 161 | 162 | def _update(self): 163 | fields = {} 164 | for f in "A,BC,DE,HL,SP,IX,IY,I,R,PC".split(","): 165 | fields[f] = self._registers[f] 166 | for b in ["S", "Z", "F5", "H", "F3", "PV", "N", "C"]: 167 | fields["F{}".format(b)] = getattr(self._registers.condition, b) 168 | self._view.setHtml(self.format_data.format(**fields)) 169 | 170 | 171 | 172 | class MemoryView(QWidget): 173 | _update_sgl = Signal(int) 174 | def __init__(self, memory, registers): 175 | super(MemoryView, self).__init__() 176 | self._modifiers = {} 177 | 178 | self._page_height = 16 179 | 180 | self._memory = memory 181 | self._registers = registers 182 | self._update_sgl.connect(self._update) 183 | self._web_view = QWebEngineView(self) 184 | vbox = QVBoxLayout() 185 | self.setLayout(vbox) 186 | 187 | hbox = QHBoxLayout() 188 | self._offset_entry = QLineEdit() 189 | self._offset_entry.returnPressed.connect(self.address_change) 190 | self._offset = 0x0 191 | self._offset_entry.setText(hex(self._offset)) 192 | self._offset_next = QPushButton(">>") 193 | self._offset_prev = QPushButton("<<") 194 | self._offset_next.clicked.connect(self.on_next) 195 | self._offset_prev.clicked.connect(self.on_prev) 196 | hbox.addWidget(self._offset_entry) 197 | hbox.addWidget(self._offset_prev) 198 | hbox.addWidget(self._offset_next) 199 | hbox.addStretch(1) 200 | 201 | vbox.addLayout(hbox) 202 | vbox.addWidget(self._web_view) 203 | 204 | self.setGeometry(100, 580, 840, 480) 205 | self.update() 206 | 207 | def on_next(self): 208 | self._offset += self._page_height * 16 209 | self._offset_entry.setText(hex(self._offset)) 210 | self.update() 211 | pass 212 | def on_prev(self): 213 | if self._offset < 1: 214 | return 215 | self._offset -= self._page_height * 16 216 | self._offset_entry.setText(hex(self._offset)) 217 | self.update() 218 | pass 219 | 220 | def address_change(self): 221 | new_val=self._offset_entry.text() 222 | val=0 223 | ln=0 224 | try: 225 | val=int(new_val,16) 226 | ln=(val-(val%16))# * 16 227 | pg = ln - ln%(self._page_height*16) 228 | except: 229 | return 230 | 231 | self._offset_entry.setText(hex(pg)) 232 | self._offset=pg 233 | self.update(val) 234 | 235 | 236 | @Slot() 237 | def update(self,highlight=-1): 238 | self._update_sgl.emit(highlight) 239 | 240 | def _update(self,highlight): 241 | 242 | sp = self._registers.SP 243 | txt = StringIO() 244 | txt.write("") 245 | for i in range(16): 246 | txt.write("".format(i)) 247 | txt.write("") 248 | 249 | for i in range(self._offset, min(len(self._memory), 250 | self._offset+16*self._page_height), 16): 251 | txt.write("") 252 | offset = i 253 | txt.write("".format(hex(offset))) 254 | ascii = "" 255 | for j in range(16): 256 | v = self._memory[offset+j] 257 | if v > 31 and v < 127: 258 | ascii += chr(self._memory[offset+j]) 259 | else: 260 | ascii += "." 261 | if offset+j == sp: 262 | txt.write("".format(v)) 263 | elif highlight > 0 and offset+j==highlight: 264 | txt.write("".format(v)) 265 | else: 266 | txt.write("".format(v)) 267 | txt.write("".format(ascii)) 268 | txt.write("") 269 | txt.write( "

Offset	{:X}	ASCII
{}	{:2X}	{:2X}	{:2X}	`{}`

") 270 | text = txt.getvalue() 271 | txt.close() 272 | self._web_view.setHtml(text) 273 | 274 | 275 | pass 276 | 277 | -------------------------------------------------------------------------------- /src/z80/instructions.py: -------------------------------------------------------------------------------- 1 | import copy 2 | import logging 3 | from . util import * 4 | import sys 5 | 6 | class instruction(object): 7 | def __init__(self, opcode_args, n_operands, string, tstates=1): 8 | self.string = string 9 | self.super_op = 0 10 | #op_args = [] 11 | #for i in opcode_args: 12 | ##super_op = i[0] >> 8 13 | ##self.super_op = super_op 14 | ##op = i[0] & 255 15 | #op_args.append((op, i[1])) 16 | #self.opcode_args = op_args 17 | self.opcode_args = opcode_args 18 | 19 | self.n_operands = n_operands # number bytes to read pos opcodeaa() 20 | self.tstates = tstates 21 | 22 | def __call__(self, f): 23 | return Instruction(self, f) 24 | 25 | 26 | class Instruction(object): 27 | def __init__(self, ins, executer): 28 | self.string = ins.string 29 | self.super_op = ins.super_op 30 | self.opcode_args = ins.opcode_args 31 | self.n_operands = ins.n_operands 32 | self.tstates = ins.tstates 33 | self.executer = executer 34 | self.incrementR = 1 35 | 36 | def get_read_list(self, operands=()): 37 | return self.executer(*((self, self.registers, True, None) + self.args + 38 | tuple([operands[i] for i in self.operands]) )) 39 | 40 | def execute(self, data=None, operands=()): 41 | return self.executer(*((self, self.registers, False, data) + self.args + 42 | tuple([operands[i] for i in self.operands]) )) 43 | 44 | def assembler(self, operands=()): 45 | return self.string.format(*(self.args + tuple([operands[i] for i in self.operands]))) 46 | 47 | 48 | def __str__(self): 49 | s = "Instruction: " + self.string + "\n" 50 | s += "args: " + str(self.args) + "\n" 51 | s += "operand bytes: " + str(self.operands) + "\n" 52 | return s 53 | 54 | 55 | class InstructionSet(): 56 | 57 | def __init__(self, registers): 58 | self._registers = registers 59 | 60 | self._instructions = {} #0: [None] * 256} #keys of this are super_ops 61 | 62 | self._instructions2 = {} 63 | # Fill instruction lookup 64 | for i in dir(self): 65 | f = getattr(self, i) 66 | if f.__class__ == Instruction: 67 | print (i, ":") 68 | for o in f.opcode_args: 69 | print (o) 70 | ff = copy.copy(f) 71 | ff.registers = self._registers 72 | ff.args = o[1] 73 | if len(o) == 3: 74 | ff.tstates = o[2] 75 | #print "Tstates=", ff.tstates 76 | else: 77 | # print "missing tstates for " 78 | # tstates not specified so used instruction group number 79 | # so default... 80 | pass 81 | ff.operands = [] 82 | d = self._instructions2 83 | opargs = o 84 | if type(o[0]) == type(0x4): 85 | if o[0] > 0xFF: 86 | opargs = ((o[0] >> 8, o[0] & 0xFF), o[1]) 87 | else: 88 | opargs = ((o[0], ), o[1]) 89 | for n, i in enumerate(opargs[0][:-1]): 90 | if i in d: 91 | d = d[i] 92 | elif i == "-": 93 | ff.operands.append(n) 94 | if len(d.keys()) == 0: 95 | d2 = {} 96 | for i in range(256): 97 | d[i] = d2 98 | d = d2 99 | else: 100 | d = d[0] 101 | else: 102 | d[i] = {} 103 | d = d[i] 104 | if (opargs[0][0] in [0xCB, 0xED, 0xDD, 0xFD]): 105 | if (opargs[0][0] in [0xDD, 0xFD]) & (opargs[0][1] == 0xCB): ff.incrementR = 3 106 | else: ff.incrementR = 2 107 | else: ff.incrementR = 1 108 | if opargs[0][-1] == "-": 109 | ff.operands.append(n+1) 110 | for i in range(256): 111 | d[i] = ff 112 | else: 113 | d[opargs[0][-1]] = ff 114 | 115 | 116 | 117 | self._instructions = self._instructions2 118 | 119 | self._instruction_composer = [] 120 | self._composer_instruction = None 121 | self._composer_len = 1 122 | 123 | 124 | def __getitem__(self, ins): 125 | if self.is_two_parter(ins): 126 | return self._instructions[ins] 127 | else: 128 | if ins in self._instructions[0]: 129 | return self._instructions[0][ins] 130 | raise AttributeError("Unknown opcode") 131 | 132 | def __lshift__(self, op): 133 | self._instruction_composer.append(op) 134 | q = self._instructions 135 | for i in self._instruction_composer: 136 | q = q[i] 137 | if isinstance(q, dict): 138 | return False, 0 139 | else: 140 | ops = tuple(self._instruction_composer) 141 | self._instruction_composer = [] 142 | self._registers.R = ((self._registers.R + q.incrementR) & 0x7F) | (self._registers.R & 0x80) 143 | # print q, ops 144 | return q, ops 145 | 146 | def reset_composer(self): 147 | self._instruction_composer = [] 148 | 149 | def is_two_parter(self, ins): 150 | return ins in self._instructions 151 | 152 | #---------------------------------------------------------------------- 153 | 154 | #---------------------------------------------------------------------- 155 | # 8-bit Load Instructions 156 | #---------------------------------------------------------------------- 157 | @instruction([(0x7F, ("A", "A")), (0x78, ("A", "B")), (0x79, ("A", "C")), (0x7A, ("A", "D")), (0x7B, ("A", "E")), 158 | (0x7C, ("A", "H")), (0x7D, ("A", "L")), 159 | (0x47, ("B", "A")), (0x40, ("B", "B")), (0x41, ("B", "C")), (0x42, ("B", "D")), (0x43, ("B", "E")), 160 | (0x44, ("B", "H")), (0x45, ("B", "L")), 161 | (0x4F, ("C", "A")), (0x48, ("C", "B")), (0x49, ("C", "C")), (0x4A, ("C", "D")), (0x4B, ("C", "E")), 162 | (0x4C, ("C", "H")), (0x4D, ("C", "L")), 163 | (0x57, ("D", "A")), (0x50, ("D", "B")), (0x51, ("D", "C")), (0x52, ("D", "D")), (0x53, ("D", "E")), 164 | (0x54, ("D", "H")), (0x55, ("D", "L")), 165 | (0x5F, ("E", "A")), (0x58, ("E", "B")), (0x59, ("E", "C")), (0x5A, ("E", "D")), (0x5B, ("E", "E")), 166 | (0x5C, ("E", "H")), (0x5D, ("E", "L")), 167 | (0x67, ("H", "A")), (0x60, ("H", "B")), (0x61, ("H", "C")), (0x62, ("H", "D")), (0x63, ("H", "E")), 168 | (0x64, ("H", "H")), (0x65, ("H", "L")), 169 | (0x6F, ("L", "A")), (0x68, ("L", "B")), (0x69, ("L", "C")), (0x6A, ("L", "D")), (0x6B, ("L", "E")), 170 | (0x6C, ("L", "H")), (0x6D, ("L", "L")), 171 | (0xDD7F, ("A", "A"), 8), (0xDD78, ("A", "B"), 8), (0xDD79, ("A", "C"), 8), (0xDD7A, ("A", "D"), 8), (0xDD7B, ("A", "E"), 8), 172 | (0xDD7C, ("A", "IXH"), 8), (0xDD7D, ("A", "IXL"), 8), 173 | (0xDD47, ("B", "A"), 8), (0xDD40, ("B", "B"), 8), (0xDD41, ("B", "C"), 8), (0xDD42, ("B", "D"), 8), (0xDD43, ("B", "E"), 8), 174 | (0xDD44, ("B", "IXH"), 8), (0xDD45, ("B", "IXL"), 8), 175 | (0xDD4F, ("C", "A"), 8), (0xDD48, ("C", "B"), 8), (0xDD49, ("C", "C"), 8), (0xDD4A, ("C", "D"), 8), (0xDD4B, ("C", "E"), 8), 176 | (0xDD4C, ("C", "IXH"), 8), (0xDD4D, ("C", "IXL"), 8), 177 | (0xDD57, ("D", "A"), 8), (0xDD50, ("D", "B"), 8), (0xDD51, ("D", "C"), 8), (0xDD52, ("D", "D"), 8), (0xDD53, ("D", "E"), 8), 178 | (0xDD54, ("D", "IXH"), 8), (0xDD55, ("D", "IXL"), 8), 179 | (0xDD5F, ("E", "A"), 8), (0xDD58, ("E", "B"), 8), (0xDD59, ("E", "C"), 8), (0xDD5A, ("E", "D"), 8), (0xDD5B, ("E", "E"), 8), 180 | (0xDD5C, ("E", "IXH"), 8), (0xDD5D, ("E", "IXL"), 8), 181 | (0xDD67, ("IXH", "A"), 8), (0xDD60, ("IXH", "B"), 8), (0xDD61, ("IXH", "C"), 8), (0xDD62, ("IXH", "D"), 8), (0xDD63, ("IXH", "E"), 8), 182 | (0xDD64, ("IXH", "IXH"), 8), (0xDD65, ("IXH", "IXL"), 8), 183 | (0xDD6F, ("IXL", "A"), 8), (0xDD68, ("IXL", "B"), 8), (0xDD69, ("IXL", "C"), 8), (0xDD6A, ("IXL", "D"), 8), (0xDD6B, ("IXL", "E"), 8), 184 | (0xDD6C, ("IXL", "IXH"), 8), (0xDD6D, ("IXL", "IXL"), 8), 185 | (0xFD7F, ("A", "A"), 8), (0xFD78, ("A", "B"), 8), (0xFD79, ("A", "C"), 8), (0xFD7A, ("A", "D"), 8), (0xFD7B, ("A", "E"), 8), 186 | (0xFD7C, ("A", "IYH"), 8), (0xFD7D, ("A", "IYL"), 8), 187 | (0xFD47, ("B", "A"), 8), (0xFD40, ("B", "B"), 8), (0xFD41, ("B", "C"), 8), (0xFD42, ("B", "D"), 8), (0xFD43, ("B", "E"), 8), 188 | (0xFD44, ("B", "IYH"), 8), (0xFD45, ("B", "IYL"), 8), 189 | (0xFD4F, ("C", "A"), 8), (0xFD48, ("C", "B"), 8), (0xFD49, ("C", "C"), 8), (0xFD4A, ("C", "D"), 8), (0xFD4B, ("C", "E"), 8), 190 | (0xFD4C, ("C", "IYH"), 8), (0xFD4D, ("C", "IYL"), 8), 191 | (0xFD57, ("D", "A"), 8), (0xFD50, ("D", "B"), 8), (0xFD51, ("D", "C"), 8), (0xFD52, ("D", "D"), 8), (0xFD53, ("D", "E"), 8), 192 | (0xFD54, ("D", "IYH"), 8), (0xFD55, ("D", "IYL"), 8), 193 | (0xFD5F, ("E", "A"), 8), (0xFD58, ("E", "B"), 8), (0xFD59, ("E", "C"), 8), (0xFD5A, ("E", "D"), 8), (0xFD5B, ("E", "E"), 8), 194 | (0xFD5C, ("E", "IYH"), 8), (0xFD5D, ("E", "IYL"), 8), 195 | (0xFD67, ("IYH", "A"), 8), (0xFD60, ("IYH", "B"), 8), (0xFD61, ("IYH", "C"), 8), (0xFD62, ("IYH", "D"), 8), (0xFD63, ("IYH", "E"), 8), 196 | (0xFD64, ("IYH", "IYH"), 8), (0xFD65, ("IYH", "IYL"), 8), 197 | (0xFD6F, ("IYL", "A"), 8), (0xFD68, ("IYL", "B"), 8), (0xFD69, ("IYL", "C"), 8), (0xFD6A, ("IYL", "D"), 8), (0xFD6B, ("IYL", "E"), 8), 198 | (0xFD6C, ("IYL", "IYH"), 8), (0xFD6D, ("IYL", "IYL"), 8), 199 | (0xED47, ("I", "A"), 9), (0xED4F, ("R", "A"), 9), 200 | ], 0, "LD {0}, {1}", 4) 201 | def ld_r_r_(instruction, registers, get_reads, data, r, r_): 202 | if get_reads: 203 | return [] 204 | else: 205 | registers[r] = registers[r_] 206 | return [] 207 | 208 | @instruction([(0xED57, ('I', )), (0xED5F, ("R", ))], 0, "LD A, {0}", 9) 209 | def ld_a_ir(instruction, registers, get_reads, data, r): 210 | if get_reads: 211 | return [] 212 | else: 213 | registers.A = registers[r] 214 | registers.condition.S = registers[r] >> 7 215 | registers.condition.Z = registers[r] == 0 216 | registers.condition.H = 0 217 | registers.condition.PV = registers.IFF2 218 | registers.condition.N = 0 219 | set_f5_f3_from_a(registers) 220 | return [] 221 | 222 | #@instruction([(0xED47, ("I", )), (0xED5F, ("R", )), (0x00, (), 30) ], 223 | #1, "LD {0}, {1}", 9) 224 | #def ld_a_ir(instruction, registers, get_reads, data, r): 225 | #if get_reads: 226 | #return [] 227 | #else: 228 | ##registers.A = registers[r] 229 | ##registers.condition.S = registers[r] >> 7 230 | ##registers.condition.Z = registers[r] == 0 231 | ##registers.condition.H = 0 232 | ##registers.condition.PV = registers.IFF2 233 | ##registers.condition.N = 0 234 | ##set_f5_f3_from_a(registers) 235 | #return [] 236 | 237 | 238 | 239 | @instruction([([0x3E, '-'], ("A", )), ([0x06, '-'], ("B", )), ([0x0E, '-'], ("C", )), 240 | ([0x16, '-'], ("D", )), ([0x1E, '-'], ("E", )), ([0x26, '-'], ("H", )), 241 | ([0x2E, '-'], ("L", )), 242 | ([0xDD, 0x3E, '-'], ("A", ), 11), ([0xDD, 0x06, '-'], ("B", ), 11), ([0xDD, 0x0E, '-'], ("C", ), 11), 243 | ([0xDD, 0x16, '-'], ("D", ), 11), ([0xDD, 0x1E, '-'], ("E", ), 11), ([0xDD, 0x26, '-'], ("IXH", ), 11), 244 | ([0xDD, 0x2E, '-'], ("IXL", ), 11), 245 | ([0xFD, 0x3E, '-'], ("A", ), 11), ([0xFD, 0x06, '-'], ("B", ), 11), ([0xFD, 0x0E, '-'], ("C", ), 11), 246 | ([0xFD, 0x16, '-'], ("D", ), 11), ([0xFD, 0x1E, '-'], ("E", ), 11), ([0xFD, 0x26, '-'], ("IYH", ), 11), 247 | ([0xFD, 0x2E, '-'], ("IYL", ), 11)], 248 | 1, "LD {0}, {1:X}H", 7) 249 | def ld_r_n(instruction, registers, get_reads, data, r, n): 250 | if get_reads: 251 | return [] 252 | else: 253 | registers[r] = n 254 | return [] 255 | 256 | 257 | @instruction([(0x7E, ("A", )), (0x46, ("B", )), (0x4E, ("C", )), (0x56, ("D", )), (0x5E, ("E", )), (0x66, ("H", )), 258 | (0x6E, ("L", ))], 259 | 0, "LD {0}, (HL)", 7) 260 | def ld_r_hl(instruction, registers, get_reads, data, r): 261 | if get_reads: 262 | return [registers.H << 8 | registers.L] 263 | else: 264 | registers[r] = data[0] 265 | return [] 266 | 267 | @instruction([([0xDD, 0x7E, '-'], ("A", "IX")), ([0xDD, 0x46, '-'], ("B", "IX")), 268 | ([0xDD, 0x4E, '-'], ("C", "IX")), ([0xDD, 0x56, '-'], ("D", "IX")), 269 | ([0xDD, 0x5E, '-'], ("E", "IX")), ([0xDD, 0x66, '-'], ("H", "IX")), 270 | ([0xDD, 0x6E, '-'], ("L", "IX")), 271 | ([0xFD, 0x7E, '-'], ("A", "IY")), ([0xFD, 0x46, '-'], ("B", "IY")), 272 | ([0xFD, 0x4E, '-'], ("C", "IY")), ([0xFD, 0x56, '-'], ("D", "IY")), 273 | ([0xFD, 0x5E, '-'], ("E", "IY")), ([0xFD, 0x66, '-'], ("H", "IY")), 274 | ([0xFD, 0x6E, '-'], ("L", "IY"))], 275 | 1, "LD {0}, ({1}+{2:X}H)", 19) 276 | def ld_r_i_d(instruction, registers, get_reads, data, r, i, d): 277 | if get_reads: 278 | return [registers[i] + get_8bit_twos_comp(d)] 279 | else: 280 | registers[r] = data[0] 281 | return [] 282 | 283 | @instruction([(0x77, ("A", )), (0x70, ("B", )), (0x71, ("C", )), (0x72, ("D", )), (0x73, ("E", )), (0x74, ("H", )), 284 | (0x75, ("L", ))], 285 | 0, "LD (HL), {0}", 7) 286 | def ld_hl_r(instruction, registers, get_reads, data, r): 287 | if get_reads: 288 | return [] 289 | else: 290 | return [(registers.H << 8 | registers.L, registers[r])] 291 | 292 | @instruction([([0xDD, 0x77, '-'], ("A", "IX")), ([0xDD, 0x70, '-'], ("B", "IX")), 293 | ([0xDD, 0x71, '-'], ("C", "IX")), ([0xDD, 0x72, '-'], ("D", "IX")), 294 | ([0xDD, 0x73, '-'], ("E", "IX")), ([0xDD, 0x74, '-'], ("H", "IX")), 295 | ([0xDD, 0x75, '-'], ("L", "IX")), 296 | ([0xFD, 0x77, '-'], ("A", "IY")), ([0xFD, 0x70, '-'], ("B", "IY")), 297 | ([0xFD, 0x71, '-'], ("C", "IY")), ([0xFD, 0x72, '-'], ("D", "IY")), 298 | ([0xFD, 0x73, '-'], ("E", "IY")), ([0xFD, 0x74, '-'], ("H", "IY")), 299 | ([0xFD, 0x75, '-'], ("L", "IY"))], 300 | 1, "LD ({1}+{2:X}H), {0}", 19) 301 | def ld_i_d_r(instruction, registers, get_reads, data, r, i, d): 302 | if get_reads: 303 | return [] 304 | else: 305 | return [( registers[i] + get_8bit_twos_comp(d), registers[r])] 306 | 307 | @instruction([([0x36, '-'], ( ))], 1, "LD (HL), {0:X}H", 10) 308 | def ld_hl_n(instruction, registers, get_reads, data, n): 309 | if get_reads: 310 | return [] 311 | else: 312 | return [(registers.H << 8 | registers.L, n)] 313 | 314 | @instruction([([0xDD, 0x36, '-', '-'], ("IX", )), ([0xFD, 0x36, '-', '-'], ("IY", ))], 315 | 2, "LD ({0}+{1:X}H), {2:X}H", 19) 316 | def ld_i_d_n(instruction, registers, get_reads, data, i, d, n): 317 | if get_reads: 318 | return [] 319 | else: 320 | return [( registers[i] + get_8bit_twos_comp(d), n)] 321 | 322 | @instruction([(0x0A, ("B", "C")), (0x1A, ("D", "E"))], 323 | 0, "LD A, ({0}{1})", 7) 324 | def ld_a_rr(instruction, registers, get_reads, data, r, r2): 325 | if get_reads: 326 | return [registers[r] << 8 | registers[r2]] 327 | else: 328 | registers.A = data[0] 329 | return [] 330 | 331 | @instruction([([0x3A, '-', '-'], ())], 332 | 2, "LD A, ({1:x}{0:X}H)", 13) 333 | def ld_a_nn(instruction, registers, get_reads, data, n, n2): 334 | if get_reads: 335 | return [n2 << 8 | n] 336 | else: 337 | registers.A = data[0] 338 | return [] 339 | 340 | 341 | @instruction([(0x02, ("B", "C")), (0x12, ("D", "E"))], 342 | 0, "LD ({0}{1}), A", 7) 343 | def ld_rr_a(instruction, registers, get_reads, data, r, r2): 344 | if get_reads: 345 | return [] 346 | else: 347 | return [(registers[r] << 8 | registers[r2], registers.A)] 348 | 349 | 350 | @instruction([([0x32, '-', '-'], ())], 351 | 2, "LD ({1:x}{0:X}H), A", 13) 352 | def ld_nn_a(instruction, registers, get_reads, data, n, n2): 353 | if get_reads: 354 | return [] 355 | else: 356 | return [(n2 << 8 | n, registers.A)] 357 | 358 | 359 | #---------------------------------------------------------------------- 360 | # 16-bit Load instructions 361 | #---------------------------------------------------------------------- 362 | @instruction([([0x01, '-', '-'], ("B", "C")), ([0x11, '-', '-'], ("D", "E")), ([0x21, '-', '-'], ("H", "L"))], 363 | 2, "LD {0}{1}, {3:X}{2:X}H", 10) 364 | def ld_dd_nn(instruction, registers, get_reads, data, r, r2, n, n2): 365 | if get_reads: 366 | return [] 367 | else: 368 | registers[r] = n2 369 | registers[r2] = n 370 | return [] 371 | 372 | @instruction([([0x31, '-', '-'], ("SP",), 10), ([0xDD, 0x21, '-', '-'], ("IX", )), 373 | ([0xFD, 0x21, '-', '-'], ("IY", ))], 374 | 2, "LD {0}, {2:X}{1:X}H", 14) 375 | def ld_D_nn(instruction, registers, get_reads, data, r, n, n2): 376 | if get_reads: 377 | return [] 378 | else: 379 | registers[r] = n2 << 8 | n 380 | return [] 381 | 382 | @instruction([([0xED, 0x4B, '-', '-'], ("B", "C" )), ([0xED, 0x5B, '-', '-'], ("D", "E" )), 383 | ([0xED, 0x6B, '-', '-'], ("H", "L" )), ([0x2A, '-', '-'], ("H", "L" ), 16), ], 384 | 2, "LD {0}{1}, ({3:X}{2:X}H)", 20) 385 | def ld_dd_nn_(instruction, registers, get_reads, data, r, r_, n, n_): 386 | if get_reads: 387 | return [n_ << 8 | n, (n_ << 8 | n) + 1] 388 | else: 389 | registers[r] = data[1] 390 | registers[r_] = data[0] 391 | return [] 392 | 393 | @instruction([([0xDD, 0x2A, '-', '-'], ("IX", )), ([0xFD, 0x2A, '-', '-'], ("IY", )), 394 | ([0xED, 0x7B, '-', '-'], ("SP", ))], 395 | 2, "LD {0}, ({2:X}{1:X}H)", 20) 396 | def ld_D_nn_(instruction, registers, get_reads, data, r, n, n2): 397 | if get_reads: 398 | return [n2 << 8 | n, (n2 << 8 | n) + 1] 399 | else: 400 | registers[r] = data[1] << 8 | data[0] 401 | return [] 402 | 403 | 404 | @instruction([([0xED, 0x73, '-', '-'], ("SP", )), ([0xDD, 0x22, '-', '-'], ("IX", )), 405 | ([0xFD, 0x22, '-', '-'], ("IY", ))], 406 | 2, "LD ({2:X}{1:X}H), {0}", 20) 407 | def ld_nn__D(instruction, registers, get_reads, data, r, n, n2): 408 | if get_reads: 409 | return [] 410 | else: 411 | ad = n2 << 8 | n 412 | return [(ad + 1, registers[r] >> 8), 413 | (ad, registers[r] & 255)] 414 | 415 | @instruction([([0xED, 0x63, '-', '-'], ("H", "L", )), ([0x22, '-', '-'], ("H", "L", ), 16), 416 | ([0xED, 0x43, '-', '-'], ("B", "C", )), ([0xED, 0x53, '-', '-'], ("D", "E", ))], 417 | 2, "LD ({3:X}{2:X}H), {0}{1}", 20) 418 | def ld_nn_D(instruction, registers, get_reads, data, r, r2, n, n2): 419 | if get_reads: 420 | return [] 421 | else: 422 | ad = n2 << 8 | n 423 | return [(ad + 1, registers[r]), 424 | (ad, registers[r2])] 425 | 426 | @instruction([(0xF9, ())], 427 | 0, "LD SP, HL", 6) 428 | def ld_sp_hl(instruction, registers, get_reads, data): 429 | if get_reads: 430 | return [] 431 | else: 432 | registers.SP = registers.H << 8 | registers.L 433 | return [] 434 | 435 | @instruction([(0xDDF9, ("IX", )), (0xFDF9, ("IY", ))], 436 | 0, "LD SP, {0}", 10) 437 | def ld_sp_i(instruction, registers, get_reads, data, i): 438 | if get_reads: 439 | return [] 440 | else: 441 | registers.SP = registers[i] 442 | return [] 443 | 444 | 445 | @instruction([(0xC5, ("B", "C" )), (0xD5, ("D", "E" )), (0xE5, ("H", "L" )), (0xF5, ("A", "F" ))], 446 | 0, "PUSH {0}{1}", 11) 447 | def push_qq(instruction, registers, get_reads, data, q, q2): 448 | if get_reads: 449 | return [] 450 | else: 451 | stack = registers.SP 452 | registers.SP = dec16(registers.SP) 453 | registers.SP = dec16(registers.SP) 454 | return [(stack - 1, registers[q]), (stack - 2, registers[q2])] 455 | 456 | 457 | @instruction([(0xDDE5, ("IX", )), (0xFDE5, ("IY", ))], 458 | 0, "PUSH {0}", 15) 459 | def push_i(instruction, registers, get_reads, data, i): 460 | if get_reads: 461 | return [] 462 | else: 463 | stack = registers.SP 464 | registers.SP = dec16(registers.SP) 465 | registers.SP = dec16(registers.SP) 466 | return [(stack - 1, registers[i] >> 8), (stack - 2, registers[i] & 255)] 467 | 468 | 469 | @instruction([(0xC1, ("B", "C" )), (0xD1, ("D", "E" )), (0xE1, ("H", "L" )), (0xF1, ("A", "F" ))], 470 | 0, "POP {0}{1}", 10) 471 | def pop_qq(instruction, registers, get_reads, data, q, q2): 472 | if get_reads: 473 | stack = registers.SP 474 | return [stack, stack + 1] 475 | else: 476 | registers.SP = inc16(registers.SP) 477 | registers.SP = inc16(registers.SP) 478 | registers[q2] = data[0] 479 | registers[q] = data[1] 480 | return [] 481 | 482 | 483 | @instruction([(0xDDE1, ("IX", )), (0xFDE1, ("IY", ))], 484 | 0, "POP {0}", 14) 485 | def pop_i(instruction, registers, get_reads, data, i): 486 | if get_reads: 487 | stack = registers.SP 488 | return [stack, stack + 1] 489 | else: 490 | registers.SP = inc16(registers.SP) 491 | registers.SP = inc16(registers.SP) 492 | registers[i] = data[1] << 8 | data[0] 493 | return [] 494 | 495 | #---------------------------------------------------------------------- 496 | # Exchange, Block Transfer, and Search Group 497 | #---------------------------------------------------------------------- 498 | @instruction([(0xEB, ())], 0, "EX DE, HL", 4) 499 | def ex_de_hl(instruction, registers, get_reads, data): 500 | if get_reads: 501 | return [] 502 | else: 503 | registers.D, registers.H = (registers.H, registers.D) 504 | registers.E, registers.L = (registers.L, registers.E) 505 | return [] 506 | 507 | @instruction([(0x08, ())], 0, "EX AF, AF'", 4) 508 | def ex_af_af_(instruction, registers, get_reads, data): 509 | if get_reads: 510 | return [] 511 | else: 512 | registers.A, registers.A_ = (registers.A_, registers.A) 513 | registers.F, registers.F_ = (registers.F_, registers.F) 514 | return [] 515 | 516 | @instruction([(0xD9, ())], 0, "EXX", 4) 517 | def exx(instruction, registers, get_reads, data): 518 | if get_reads: 519 | return [] 520 | else: 521 | registers.B, registers.B_ = (registers.B_, registers.B) 522 | registers.C, registers.C_ = (registers.C_, registers.C) 523 | registers.D, registers.D_ = (registers.D_, registers.D) 524 | registers.E, registers.E_ = (registers.E_, registers.E) 525 | registers.H, registers.H_ = (registers.H_, registers.H) 526 | registers.L, registers.L_ = (registers.L_, registers.L) 527 | return [] 528 | 529 | @instruction([(0xE3, ())], 0, "EX (SP), HL", 19) 530 | def ex_sp__hl(instruction, registers, get_reads, data): 531 | if get_reads: 532 | return [registers.SP, registers.SP + 1] 533 | else: 534 | h = registers.H 535 | l = registers.L 536 | registers.H = data[1] 537 | registers.L = data[0] 538 | return [(registers.SP, l), (registers.SP + 1, h)] 539 | 540 | @instruction([(0xDDE3, ("IX", )), (0xFDE3, ("IY", ))], 0, 541 | "EX (SP), {0}", 23) 542 | def ex_sp__i(instruction, registers, get_reads, data, i): 543 | if get_reads: 544 | return [registers.SP, registers.SP + 1] 545 | else: 546 | ix = registers[i] 547 | registers[i] = data[1] << 8 | data[0] 548 | 549 | return [(registers.SP, ix & 0xFF), 550 | (registers.SP + 1, ix >> 8)] 551 | 552 | @instruction([(0xEDA0, ())], 0, "LDI", 16) 553 | def ldi(instruction, registers, get_reads, data): 554 | if get_reads: 555 | return [registers.H << 8 | registers.L] 556 | 557 | else: 558 | de_ = de = registers.D << 8 | registers.E 559 | hl = registers.H << 8 | registers.L 560 | bc = registers.B << 8 | registers.C 561 | hl += 1 562 | if hl > 0xFFFF: hl = 0 563 | registers.H = hl >> 8 564 | registers.L = hl & 0xFF 565 | bc -= 1 566 | if bc < 0: bc = 0xFFFF 567 | registers.B = bc >> 8 568 | registers.C = bc & 0xFF 569 | de += 1 570 | if de > 0xFFFF: de = 0 571 | registers.D = de >> 8 572 | registers.E = de & 0xFF 573 | 574 | registers.condition.H = 0 575 | if bc != 0: 576 | registers.condition.PV = 1 577 | else: 578 | registers.condition.PV = 0 579 | registers.condition.N = 0 580 | registers.condition.F3 = (registers.A + data[0]) & 0x08 581 | registers.condition.F5 = (registers.A + data[0]) & 0x02 582 | return [(de_, data[0])] 583 | 584 | @instruction([(0xEDB0, ())], 0, "LDIR", 21) 585 | def ldir(instruction, registers, get_reads, data): 586 | if get_reads: 587 | return [registers.H << 8 | registers.L] 588 | else: 589 | de_ = de = registers.D << 8 | registers.E 590 | hl = registers.H << 8 | registers.L 591 | bc = registers.B << 8 | registers.C 592 | hl += 1 593 | if hl > 0xFFFF: hl = 0 594 | registers.H = hl >> 8 595 | registers.L = hl & 0xFF 596 | bc -= 1 597 | if bc < 0: bc = 0xFFFF 598 | registers.B = bc >> 8 599 | registers.C = bc & 0xFF 600 | de += 1 601 | if de > 0xFFFF: de = 0 602 | registers.D = de >> 8 603 | registers.E = de & 0xFF 604 | 605 | registers.condition.H = 0 606 | if bc != 0: 607 | registers.PC = dec16(registers.PC) 608 | registers.PC = dec16(registers.PC) 609 | instruction.tstates = 21 610 | else: 611 | instruction.tstates = 16 612 | 613 | registers.condition.PV = 0 614 | registers.condition.N = 0 615 | registers.condition.F3 = (registers.A + data[0]) & 0x08 616 | registers.condition.F5 = (registers.A + data[0]) & 0x02 617 | return [(de_, data[0])] 618 | 619 | 620 | @instruction([(0xEDA8, ())], 0, "LDD", 16) 621 | def ldd(instruction, registers, get_reads, data): 622 | if get_reads: 623 | return [registers.H << 8 | registers.L] 624 | else: 625 | de_ = de = registers.D << 8 | registers.E 626 | hl = registers.H << 8 | registers.L 627 | bc = registers.B << 8 | registers.C 628 | hl -= 1 629 | if hl < 0: hl = 0xFFFF 630 | registers.H = hl >> 8 631 | registers.L = hl & 0xFF 632 | bc -= 1 633 | if bc < 0: bc = 0xFFFF 634 | registers.B = bc >> 8 635 | registers.C = bc & 0xFF 636 | de -= 1 637 | if de < 0: de = 0xFFFF 638 | registers.D = de >> 8 639 | registers.E = de & 0xFF 640 | 641 | registers.condition.H = 0 642 | if bc != 0: 643 | registers.condition.PV = 1 644 | else: 645 | registers.condition.PV = 0 646 | registers.condition.N = 0 647 | registers.condition.F3 = (registers.A + data[0]) & 0x08 648 | registers.condition.F5 = (registers.A + data[0]) & 0x02 649 | return [(de_, data[0])] 650 | 651 | @instruction([(0xEDB8, ())], 0, "LDDR", 16) 652 | def lddr(instruction, registers, get_reads, data): 653 | if get_reads: 654 | return [registers.H << 8 | registers.L] 655 | else: 656 | de_ = de = registers.D << 8 | registers.E 657 | hl = registers.H << 8 | registers.L 658 | bc = registers.B << 8 | registers.C 659 | hl -= 1 660 | if hl < 0: hl = 0xFFFF 661 | registers.H = hl >> 8 662 | registers.L = hl & 0xFF 663 | bc -= 1 664 | if bc < 0: bc = 0xFFFF 665 | registers.B = bc >> 8 666 | registers.C = bc & 0xFF 667 | de -= 1 668 | if de < 0: de = 0xFFFF 669 | registers.D = de >> 8 670 | registers.E = de & 0xFF 671 | 672 | registers.condition.H = 0 673 | if bc != 0: 674 | registers.PC = dec16(registers.PC) 675 | registers.PC = dec16(registers.PC) 676 | instruction.tstates = 21 677 | else: 678 | instruction.tstates = 16 679 | 680 | registers.condition.PV = 0 681 | registers.condition.N = 0 682 | registers.condition.F3 = (registers.A + data[0]) & 0x08 683 | registers.condition.F5 = (registers.A + data[0]) & 0x02 684 | return [(de_, data[0])] 685 | 686 | 687 | @instruction([(0xEDA1, ())], 0, "CPI", 16) 688 | def cpi(instruction, registers, get_reads, data): 689 | if get_reads: 690 | return [registers.HL] 691 | else: 692 | registers.HL = inc16(registers.HL) 693 | registers.BC = dec16(registers.BC) 694 | 695 | subtract8(registers.A, data[0], registers) 696 | registers.condition.PV = registers.BC != 0 697 | # F3 is bit 3 of (A - (HL) - H), H 698 | # F5 is bit 1 of (A - (HL) - H), H a 699 | f5f3 = registers.A - data[0] - registers.condition.H 700 | registers.condition.F5 = f5f3 & 0x02 701 | registers.condition.F3 = f5f3 & 0x08 702 | return [] 703 | 704 | @instruction([(0xEDB1, ())], 0, "CPIR", 16) 705 | def cpir(instruction, registers, get_reads, data): 706 | if get_reads: 707 | return [registers.HL] 708 | else: 709 | registers.HL = inc16(registers.HL) 710 | registers.BC = dec16(registers.BC) 711 | 712 | res = subtract8(registers.A, data[0], registers) 713 | 714 | if registers.BC != 0 and res != 0: 715 | registers.PC = dec16(registers.PC) 716 | registers.PC = dec16(registers.PC) 717 | instruction.tstates = 21 718 | else: 719 | instruction.tstates = 16 720 | registers.condition.PV = registers.BC != 0 721 | f5f3 = registers.A - data[0] - registers.condition.H 722 | registers.condition.F5 = f5f3 & 0x02 723 | registers.condition.F3 = f5f3 & 0x08 724 | return [] 725 | 726 | @instruction([(0xEDA9, ())], 0, "CPD", 16) 727 | def cpd(instruction, registers, get_reads, data): 728 | if get_reads: 729 | return [registers.HL] 730 | else: 731 | registers.HL = dec16(registers.HL) 732 | registers.BC = dec16(registers.BC) 733 | 734 | subtract8(registers.A, data[0], registers) 735 | registers.condition.PV = registers.BC != 0 736 | f5f3 = registers.A - data[0] - registers.condition.H 737 | registers.condition.F5 = f5f3 & 0x02 738 | registers.condition.F3 = f5f3 & 0x08 739 | return [] 740 | 741 | @instruction([(0xEDB9, ())], 0, "CPDR", 16) 742 | def cpdr(instruction, registers, get_reads, data): 743 | if get_reads: 744 | return [registers.HL] 745 | else: 746 | registers.HL = dec16(registers.HL) 747 | registers.BC = dec16(registers.BC) 748 | 749 | res = subtract8(registers.A, data[0], registers) 750 | 751 | if registers.BC != 0 and res != 0: 752 | registers.PC = dec16(registers.PC) 753 | registers.PC = dec16(registers.PC) 754 | instruction.tstates = 21 755 | else: 756 | instruction.tstates = 16 757 | registers.condition.PV = registers.BC != 0 758 | f5f3 = registers.A - data[0] - registers.condition.H 759 | registers.condition.F5 = f5f3 & 0x02 760 | registers.condition.F3 = f5f3 & 0x08 761 | return [] 762 | 763 | #---------------------------------------------------------------------- 764 | # 8-Bit Arithmetic Group 765 | #---------------------------------------------------------------------- 766 | #---- ADD ---- 767 | @instruction([(0x87, ("A",)), (0x80, ("B",)), (0x81, ("C",)), 768 | (0x82, ("D",)), (0x83, ("E",)), (0x84, ("H",)), 769 | (0x85, ("L",)), 770 | (0xDD87, ("A",), 8), (0xDD80, ("B",), 8), (0xDD81, ("C",), 8), 771 | (0xDD82, ("D",), 8), (0xDD83, ("E",), 8), (0xDD84, ("IXH",), 8), 772 | (0xDD85, ("IXL",), 8), 773 | (0xFD87, ("A",), 8), (0xFD80, ("B",), 8), (0xFD81, ("C",), 8), 774 | (0xFD82, ("D",), 8), (0xFD83, ("E",), 8), (0xFD84, ("IYH",), 8), 775 | (0xFD85, ("IYL",), 8)], 0, "ADD A, {0}", 4) 776 | def add_a_r(instruction, registers, get_reads, data, r): 777 | if get_reads: 778 | return [] 779 | else: 780 | registers.A = add8(registers.A, registers[r], registers) 781 | return [] 782 | 783 | @instruction([([0xC6, '-'], ())], 1, "ADD A, {0:X}H", 7) 784 | def add_a_n(instruction, registers, get_reads, data, n): 785 | if get_reads: 786 | return [] 787 | else: 788 | registers.A = add8(registers.A, n, registers) 789 | return [] 790 | 791 | 792 | @instruction([(0x86, ())], 0, "ADD A, (HL)", 7) 793 | def add_a_hl_(instruction, registers, get_reads, data): 794 | if get_reads: 795 | return [registers.HL] 796 | else: 797 | registers.A = add8(registers.A, data[0], registers) 798 | return [] 799 | 800 | @instruction([([0xDD, 0x86, '-'], ("IX",)), 801 | ([0xFD, 0x86, '-'], ("IY",))], 1, "ADD A, ({0}+{1:X}H)", 19) 802 | def add_a_i_(instruction, registers, get_reads, data, i, d): 803 | if get_reads: 804 | return [registers[i] + get_8bit_twos_comp(d)] 805 | else: 806 | registers.A = add8(registers.A, data[0], registers) 807 | return [] 808 | 809 | #---- ADC ---- 810 | @instruction([(0x8f, ("A",)), (0x88, ("B",)), (0x89, ("C",)), 811 | (0x8A, ("D",)), (0x8B, ("E",)), (0x8C, ("H",)), 812 | (0x8D, ("L",)), 813 | (0xDD8f, ("A",), 8), (0xDD88, ("B",), 8), (0xDD89, ("C",), 8), 814 | (0xDD8A, ("D",), 8), (0xDD8B, ("E",), 8), (0xDD8C, ("IXH",), 8), 815 | (0xDD8D, ("IXL",), 8), 816 | (0xFD8f, ("A",), 8), (0xFD88, ("B",), 8), (0xFD89, ("C",), 8), 817 | (0xFD8A, ("D",), 8), (0xFD8B, ("E",), 8), (0xFD8C, ("IYH",), 8), 818 | (0xFD8D, ("IYL",), 8)], 0, "ADC A, {0}", 4) 819 | def adc_a_r(instruction, registers, get_reads, data, r): 820 | if get_reads: 821 | return [] 822 | else: 823 | registers.A = add8(registers.A + registers.condition.C, registers[r], registers) 824 | return [] 825 | 826 | @instruction([([0xCE, '-'], ())], 1, "ADC A, {0:X}H", 7) 827 | def adc_a_n(instruction, registers, get_reads, data, n): 828 | if get_reads: 829 | return [] 830 | else: 831 | registers.A = add8(registers.A + registers.condition.C, n, registers) 832 | return [] 833 | 834 | 835 | @instruction([(0x8E, ())], 0, "ADC A, (HL)", 7) 836 | def adc_a_hl_(instruction, registers, get_reads, data): 837 | if get_reads: 838 | return [registers.HL] 839 | else: 840 | registers.A = add8(registers.A + registers.condition.C, data[0], registers) 841 | return [] 842 | 843 | @instruction([([0xDD, 0x8E, '-'], ("IX",)), 844 | ([0xFD, 0x8E, '-'], ("IY",))], 1, "ADC A, ({0}+{1:X}H)", 19) 845 | def adc_a_i_(instruction, registers, get_reads, data, i, d): 846 | if get_reads: 847 | return [registers[i] + get_8bit_twos_comp(d)] 848 | else: 849 | registers.A = add8(registers.A + registers.condition.C, data[0], registers) 850 | return [] 851 | 852 | #---- SUB ---- 853 | @instruction([(0x97, ("A",)), (0x90, ("B",)), (0x91, ("C",)), 854 | (0x92, ("D",)), (0x93, ("E",)), (0x94, ("H",)), 855 | (0x95, ("L",)), 856 | (0xDD97, ("A",), 8), (0xDD90, ("B",), 8), (0xDD91, ("C",), 8), 857 | (0xDD92, ("D",), 8), (0xDD93, ("E",), 8), (0xDD94, ("IXH",), 8), 858 | (0xDD95, ("IXL",), 8), 859 | (0xFD97, ("A",), 8), (0xFD90, ("B",), 8), (0xFD91, ("C",), 8), 860 | (0xFD92, ("D",), 8), (0xFD93, ("E",), 8), (0xFD94, ("IYH",), 8), 861 | (0xFD95, ("IYL",), 8)], 0, "SUB A, {0}", 4) 862 | def sub_a_r(instruction, registers, get_reads, data, r): 863 | if get_reads: 864 | return [] 865 | else: 866 | registers.A = subtract8_check_overflow(registers.A, registers[r], registers) 867 | return [] 868 | 869 | @instruction([([0xD6, '-'], ())], 1, "SUB A, {0:X}H", 7) 870 | def sub_a_n(instruction, registers, get_reads, data, n): 871 | if get_reads: 872 | return [] 873 | else: 874 | registers.A = subtract8_check_overflow(registers.A, n, registers) 875 | return [] 876 | 877 | 878 | @instruction([(0x96, ())], 0, "SUB A, (HL)", 7) 879 | def sub_a_hl_(instruction, registers, get_reads, data): 880 | if get_reads: 881 | return [registers.HL] 882 | else: 883 | registers.A = subtract8_check_overflow(registers.A, data[0], registers) 884 | return [] 885 | 886 | @instruction([([0xDD, 0x96, '-'], ("IX",)), 887 | ([0xFD, 0x96, '-'], ("IY",))], 1, "SUB A, ({0}+{1:X}H)", 19) 888 | def sub_a_i_(instruction, registers, get_reads, data, i, d): 889 | if get_reads: 890 | return [registers[i] + get_8bit_twos_comp(d)] 891 | else: 892 | registers.A = subtract8_check_overflow(registers.A, data[0], registers) 893 | return [] 894 | 895 | #---- SBC ---- 896 | @instruction([(0x9f, ("A",)), (0x98, ("B",)), (0x99, ("C",)), 897 | (0x9A, ("D",)), (0x9B, ("E",)), (0x9C, ("H",)), 898 | (0x9D, ("L",)), 899 | (0xDD9f, ("A",), 8), (0xDD98, ("B",), 8), (0xDD99, ("C",), 8), 900 | (0xDD9A, ("D",), 8), (0xDD9B, ("E",), 8), (0xDD9C, ("IXH",), 8), 901 | (0xDD9D, ("IXL",), 8), 902 | (0xFD9f, ("A",), 8), (0xFD98, ("B",), 8), (0xFD99, ("C",), 8), 903 | (0xFD9A, ("D",), 8), (0xFD9B, ("E",), 8), (0xFD9C, ("IYH",), 8), 904 | (0xFD9D, ("IYL",), 8)], 0, "SBC A, {0}", 4) 905 | def sbc_a_r(instruction, registers, get_reads, data, r): 906 | if get_reads: 907 | return [] 908 | else: 909 | registers.A = subtract8_check_overflow(registers.A - registers.condition.C, registers[r], registers) 910 | return [] 911 | 912 | @instruction([([0xDE, '-'], ())], 1, "SBC A, {0:X}H", 7) 913 | def sbc_a_n(instruction, registers, get_reads, data, n): 914 | if get_reads: 915 | return [] 916 | else: 917 | registers.A = subtract8_check_overflow(registers.A - registers.condition.C, n, registers) 918 | return [] 919 | 920 | 921 | @instruction([(0x9E, ())], 0, "SBC A, (HL)", 7) 922 | def sbc_a_hl_(instruction, registers, get_reads, data): 923 | if get_reads: 924 | return [registers.HL] 925 | else: 926 | registers.A = subtract8_check_overflow(registers.A - registers.condition.C, data[0], registers) 927 | return [] 928 | 929 | @instruction([([0xDD, 0x9E, '-'], ("IX",)), 930 | ([0xFD, 0x9E, '-'], ("IY",))], 1, "SBC A, ({0}+{1:X}H)", 19) 931 | def sbc_a_i_(instruction, registers, get_reads, data, i, d): 932 | if get_reads: 933 | return [registers[i] + get_8bit_twos_comp(d)] 934 | else: 935 | registers.A = subtract8_check_overflow(registers.A - registers.condition.C, data[0], registers) 936 | return [] 937 | 938 | #---- AND ---- 939 | @instruction([(0xa7, ("A",)), (0xa0, ("B",)), (0xa1, ("C",)), 940 | (0xa2, ("D",)), (0xa3, ("E",)), (0xa4, ("H",)), 941 | (0xa5, ("L",)), 942 | (0xDDa7, ("A",), 8), (0xDDa0, ("B",), 8), (0xDDa1, ("C",), 8), 943 | (0xDDa2, ("D",), 8), (0xDDa3, ("E",), 8), (0xDDa4, ("IXH",), 8), 944 | (0xDDa5, ("IXL",), 8), 945 | (0xFDa7, ("A",), 8), (0xFDa0, ("B",), 8), (0xFDa1, ("C",), 8), 946 | (0xFDa2, ("D",), 8), (0xFDa3, ("E",), 8), (0xFDa4, ("IYH",), 8), 947 | (0xFDa5, ("IYL",), 8)], 0, "AND {0}", 4) 948 | def and_a_r(instruction, registers, get_reads, data, r): 949 | if get_reads: 950 | return [] 951 | else: 952 | a_and_n(registers, registers[r]) 953 | return [] 954 | 955 | @instruction([([0xe6, '-'], ())], 1, "AND {0:X}H", 7) 956 | def and_a_n(instruction, registers, get_reads, data, n): 957 | if get_reads: 958 | return [] 959 | else: 960 | a_and_n(registers, n) 961 | return [] 962 | 963 | 964 | @instruction([(0xa6, ())], 0, "AND (HL)", 7) 965 | def and_a_hl_(instruction, registers, get_reads, data): 966 | if get_reads: 967 | return [registers.HL] 968 | else: 969 | a_and_n(registers, data[0]) 970 | return [] 971 | 972 | @instruction([([0xDD, 0xA6, '-'], ("IX",)), 973 | ([0xFD, 0xA6, '-'], ("IY",))], 1, "AND ({0}+{1:X}H)", 19) 974 | def and_a_i_(instruction, registers, get_reads, data, i, d): 975 | if get_reads: 976 | return [registers[i] + get_8bit_twos_comp(d)] 977 | else: 978 | a_and_n(registers, data[0]) 979 | return [] 980 | 981 | #---- OR ---- 982 | @instruction([(0xb7, ("A",)), (0xb0, ("B",)), (0xb1, ("C",)), 983 | (0xb2, ("D",)), (0xb3, ("E",)), (0xb4, ("H",)), 984 | (0xb5, ("L",)), 985 | (0xDDb7, ("A",), 8), (0xDDb0, ("B",), 8), (0xDDb1, ("C",), 8), 986 | (0xDDb2, ("D",), 8), (0xDDb3, ("E",), 8), (0xDDb4, ("IXH",), 8), 987 | (0xDDb5, ("IXL",), 8), 988 | (0xFDb7, ("A",), 8), (0xFDb0, ("B",), 8), (0xFDb1, ("C",), 8), 989 | (0xFDb2, ("D",), 8), (0xFDb3, ("E",), 8), (0xFDb4, ("IYH",), 8), 990 | (0xFDb5, ("IYL",), 8)], 0, "OR {0}", 4) 991 | def or_a_r(instruction, registers, get_reads, data, r): 992 | if get_reads: 993 | return [] 994 | else: 995 | a_or_n(registers, registers[r]) 996 | return [] 997 | 998 | @instruction([([0xf6, '-'], ())], 1, "OR {0:X}H", 7) 999 | def or_a_n(instruction, registers, get_reads, data, n): 1000 | if get_reads: 1001 | return [] 1002 | else: 1003 | a_or_n(registers, n) 1004 | return [] 1005 | 1006 | 1007 | @instruction([(0xb6, ())], 0, "OR (HL)", 7) 1008 | def or_a_hl_(instruction, registers, get_reads, data): 1009 | if get_reads: 1010 | return [registers.HL] 1011 | else: 1012 | a_or_n(registers, data[0]) 1013 | return [] 1014 | 1015 | @instruction([([0xDD, 0xB6, '-'], ("IX",)), 1016 | ([0xFD, 0xB6, '-'], ("IY",))], 1, "OR ({0}+{1:X}H)", 19) 1017 | def or_a_i_(instruction, registers, get_reads, data, i, d): 1018 | if get_reads: 1019 | return [registers[i] + get_8bit_twos_comp(d)] 1020 | else: 1021 | a_or_n(registers, data[0]) 1022 | return [] 1023 | 1024 | #---- XOR ---- 1025 | @instruction([(0xaf, ("A",)), (0xa8, ("B",)), (0xa9, ("C",)), 1026 | (0xaa, ("D",)), (0xab, ("E",)), (0xac, ("H",)), 1027 | (0xad, ("L",)), 1028 | (0xDDaf, ("A",), 8), (0xDDa8, ("B",), 8), (0xDDa9, ("C",), 8), 1029 | (0xDDaa, ("D",), 8), (0xDDab, ("E",), 8), (0xDDac, ("IXH",), 8), 1030 | (0xDDad, ("IXL",), 8), 1031 | (0xFDaf, ("A",), 8), (0xFDa8, ("B",), 8), (0xFDa9, ("C",), 8), 1032 | (0xFDaa, ("D",), 8), (0xFDab, ("E",), 8), (0xFDac, ("IYH",), 8), 1033 | (0xFDad, ("IYL",), 8)], 0, "XOR {0}", 4) 1034 | def xor_a_r(instruction, registers, get_reads, data, r): 1035 | if get_reads: 1036 | return [] 1037 | else: 1038 | a_xor_n(registers, registers[r]) 1039 | return [] 1040 | 1041 | @instruction([([0xee, '-'], ())], 1, "XOR {0:X}H", 7) 1042 | def xor_a_n(instruction, registers, get_reads, data, n): 1043 | if get_reads: 1044 | return [] 1045 | else: 1046 | a_xor_n(registers, n) 1047 | return [] 1048 | 1049 | 1050 | @instruction([(0xae, ())], 0, "XOR (HL)", 7) 1051 | def xor_a_hl_(instruction, registers, get_reads, data): 1052 | if get_reads: 1053 | return [registers.HL] 1054 | else: 1055 | a_xor_n(registers, data[0]) 1056 | return [] 1057 | 1058 | @instruction([([0xDD, 0xAE, '-'], ("IX",)), 1059 | ([0xFD, 0xAE, '-'], ("IY",))], 1, "XOR ({0}+{1:X}H)", 19) 1060 | def xor_a_i_(instruction, registers, get_reads, data, i, d): 1061 | if get_reads: 1062 | return [registers[i] + get_8bit_twos_comp(d)] 1063 | else: 1064 | a_xor_n(registers, data[0]) 1065 | return [] 1066 | 1067 | #---- CP ---- 1068 | @instruction([(0xbf, ("A",)), (0xb8, ("B",)), (0xb9, ("C",)), 1069 | (0xba, ("D",)), (0xbb, ("E",)), (0xbc, ("H",)), 1070 | (0xbd, ("L",)), 1071 | (0xDDbf, ("A",), 8), (0xDDb8, ("B",), 8), (0xDDb9, ("C",), 8), 1072 | (0xDDba, ("D",), 8), (0xDDbb, ("E",), 8), (0xDDbc, ("IXH",), 8), 1073 | (0xDDbd, ("IXL",), 8), 1074 | (0xFDbf, ("A",), 8), (0xFDb8, ("B",), 8), (0xFDb9, ("C",), 8), 1075 | (0xFDba, ("D",), 8), (0xFDbb, ("E",), 8), (0xFDbc, ("IYH",), 8), 1076 | (0xFDbd, ("IYL",), 8)], 0, "CP {0}", 4) 1077 | def cp_a_r(instruction, registers, get_reads, data, r): 1078 | if get_reads: 1079 | return [] 1080 | else: 1081 | subtract8_check_overflow(registers.A, registers[r], registers) 1082 | set_f5_f3(registers, registers[r]) 1083 | return [] 1084 | 1085 | @instruction([([0xfe, '-'], ())], 1, "CP {0:X}H", 7) 1086 | def cp_a_n(instruction, registers, get_reads, data, n): 1087 | if get_reads: 1088 | return [] 1089 | else: 1090 | subtract8_check_overflow(registers.A, n, registers) 1091 | set_f5_f3(registers, n) 1092 | return [] 1093 | 1094 | 1095 | @instruction([(0xbe, ())], 0, "CP (HL)", 7) 1096 | def cp_a_hl_(instruction, registers, get_reads, data): 1097 | if get_reads: 1098 | return [registers.HL] 1099 | else: 1100 | subtract8_check_overflow(registers.A, data[0], registers) 1101 | set_f5_f3(registers, data[0]) 1102 | return [] 1103 | 1104 | @instruction([([0xDD, 0xBE, '-'], ("IX",)), 1105 | ([0xFD, 0xBE, '-'], ("IY",))], 1, "CP ({0}+{1:X}H)", 19) 1106 | def cp_a_i_(instruction, registers, get_reads, data, i, d): 1107 | if get_reads: 1108 | return [registers[i] + get_8bit_twos_comp(d)] 1109 | else: 1110 | subtract8_check_overflow(registers.A, data[0], registers) 1111 | set_f5_f3(registers, data[0]) 1112 | return [] 1113 | 1114 | #---- INC s ---- 1115 | @instruction([(0x3c, ("A",)), (0x04, ("B",)), (0x0c, ("C",)), 1116 | (0x14, ("D",)), (0x1c, ("E",)), (0x24, ("H",)), 1117 | (0x2c, ("L",)), 1118 | (0xDD3c, ("A",), 8), (0xDD04, ("B",), 8), (0xDD0c, ("C",), 8), 1119 | (0xDD14, ("D",), 8), (0xDD1c, ("E",), 8), (0xDD24, ("IXH",), 8), 1120 | (0xDD2c, ("IXL",), 8), 1121 | (0xFD3c, ("A",), 8), (0xFD04, ("B",), 8), (0xFD0c, ("C",), 8), 1122 | (0xFD14, ("D",), 8), (0xFD1c, ("E",), 8), (0xFD24, ("IYH",), 8), 1123 | (0xFD2c, ("IYL",), 8)], 0, "INC {0}", 4) 1124 | def inc_r(instruction, registers, get_reads, data, r): 1125 | if get_reads: 1126 | return [] 1127 | else: 1128 | registers[r] = add8(registers[r], 1, registers, C=False ) 1129 | return [] 1130 | 1131 | @instruction([(0x34, ())], 0, "INC (HL)", 11) 1132 | def inc_hl_(instruction, registers, get_reads, data): 1133 | if get_reads: 1134 | return [registers.HL] 1135 | else: 1136 | new = add8(data[0], 1, registers, C=False ) 1137 | return [(registers.HL, new)] 1138 | 1139 | @instruction([([0xDD, 0x34, '-'], ("IX",)), 1140 | ([0xFD, 0x34, '-'], ("IY",))], 1, "INC ({0}+{1:X}H)", 23) 1141 | def inc_i_(instruction, registers, get_reads, data, i, d): 1142 | if get_reads: 1143 | return [registers[i] + get_8bit_twos_comp(d)] 1144 | else: 1145 | new = add8(data[0], 1, registers, C=False ) 1146 | return [(registers[i] + get_8bit_twos_comp(d), new)] 1147 | 1148 | 1149 | #---- DEC s ---- 1150 | @instruction([(0x3d, ("A",)), (0x05, ("B",)), (0x0d, ("C",)), 1151 | (0x15, ("D",)), (0x1d, ("E",)), (0x25, ("H",)), 1152 | (0x2d, ("L",)), 1153 | (0xDD3d, ("A",), 8), (0xDD05, ("B",), 8), (0xDD0d, ("C",), 8), 1154 | (0xDD15, ("D",), 8), (0xDD1d, ("E",), 8), (0xDD25, ("IXH",), 8), 1155 | (0xDD2d, ("IXL",), 8), 1156 | (0xFD3d, ("A",), 8), (0xFD05, ("B",), 8), (0xFD0d, ("C",), 8), 1157 | (0xFD15, ("D",), 8), (0xFD1d, ("E",), 8), (0xFD25, ("IYH",), 8), 1158 | (0xFD2d, ("IYL",), 8)], 0, "DEC {0}", 4) 1159 | def dec_r(instruction, registers, get_reads, data, r): 1160 | if get_reads: 1161 | return [] 1162 | else: 1163 | registers.condition.PV = registers[r] == 0x80 1164 | registers[r] = subtract8(registers[r], 1, registers, 1165 | PV=False) 1166 | 1167 | return [] 1168 | 1169 | @instruction([(0x35, ())], 0, "DEC (HL)", 11) 1170 | def dec_hl_(instruction, registers, get_reads, data): 1171 | if get_reads: 1172 | return [registers.HL] 1173 | else: 1174 | new = subtract8(data[0], 1, registers, 1175 | PV=False) 1176 | if data[0] == 0x80: 1177 | registers.condition.PV = 1 1178 | else: 1179 | registers.condition.PV = 0 1180 | 1181 | return [(registers.HL, new)] 1182 | 1183 | @instruction([([0xDD, 0x35, '-'], ("IX",)), 1184 | ([0xFD, 0x35, '-'], ("IY",))], 1, "DEC ({0}+{1:X}H)", 23) 1185 | def dec_i_(instruction, registers, get_reads, data, i, d): 1186 | if get_reads: 1187 | return [registers[i] + get_8bit_twos_comp(d)] 1188 | else: 1189 | new = subtract8(data[0], 1, registers, 1190 | PV=False) 1191 | if data[0] == 0x80: 1192 | registers.condition.PV = 1 1193 | else: 1194 | registers.condition.PV = 0 1195 | return [(registers[i] + get_8bit_twos_comp(d), new)] 1196 | 1197 | #-------------------------------------------------------------------- 1198 | # General-Purpose Arithmetic and CPU Control Groups 1199 | #-------------------------------------------------------------------- 1200 | @instruction([(0x27, ())], 0, "DAA", 4) 1201 | def daa(instruction, registers, get_reads, data): 1202 | if get_reads: 1203 | return [] 1204 | else: 1205 | # https://raine.1emulation.com/archive/dev/z80-documented.pdf 1206 | # (The Undocumented Z80 Documented) 1207 | hn = (registers.A & 0xF0) >> 4 # high nibble 1208 | ln = registers.A & 0x0F # low nibble 1209 | 1210 | # Flag C 1211 | if (registers.condition.C == 0): 1212 | if ( 1213 | ((hn >= 0x09) & (ln >= 0x0A)) | 1214 | ((hn >= 0x0A) & (ln <= 0x09)) 1215 | ): c_ = 1 1216 | else: c_ = 0 1217 | else: c_ = 1 1218 | 1219 | # Flag H 1220 | if (registers.condition.N == 0): 1221 | if (ln < 0x0A): h_ = 0 1222 | else: h_ = 1 1223 | else: 1224 | if (registers.condition.H == 0): h_ = 0 1225 | else: 1226 | if (ln < 0x06): h_ = 1 1227 | else: h_ = 0 1228 | 1229 | # Calculate diff 1230 | diff = 0 1231 | if (registers.condition.C == 0): 1232 | if ((hn <= 0x09) & (ln <= 0x09) & (registers.condition.H == 0)): diff = 0x00 1233 | elif ((hn <= 0x09) & (ln <= 0x09) & (registers.condition.H == 1)): diff = 0x06 1234 | elif ((hn <= 0x08) & (ln >= 0x0A)): diff = 0x06 1235 | elif ((hn >= 0x0A) & (ln <= 0x09) & (registers.condition.H == 0)): diff = 0x60 1236 | elif ((hn >= 0x09) & (ln >= 0x0A)): diff = 0x66 1237 | elif ((hn >= 0x0A) & (ln <= 0x09) & (registers.condition.H == 1)): diff = 0x66 1238 | else: 1239 | if ((ln <= 0x09) & (registers.condition.H == 0)): diff = 0x60 1240 | elif ((ln <= 0x09) & (registers.condition.H == 1)): diff = 0x66 1241 | elif (ln >= 0x0A): diff = 0x66 1242 | 1243 | if registers.condition.N == 1: 1244 | registers.A = get_8bit_twos_comp((registers.A - diff)) & 0xFF 1245 | else: 1246 | registers.A = (registers.A + diff) & 0xFF 1247 | 1248 | registers.condition.C = c_ 1249 | registers.condition.H = h_ 1250 | registers.condition.S = registers.A >> 7 1251 | registers.condition.Z = (registers.A == 0) 1252 | registers.condition.PV = parity(registers.A) 1253 | set_f5_f3_from_a(registers) 1254 | return [] 1255 | 1256 | @instruction([(0x2F, ())], 0, "CPL", 4) 1257 | def cpl(instruction, registers, get_reads, data): 1258 | if get_reads: 1259 | return [] 1260 | else: 1261 | registers.A = 0xFF ^ registers.A 1262 | registers.condition.N = 1 1263 | registers.condition.H = 1 1264 | set_f5_f3_from_a(registers) 1265 | return [] 1266 | 1267 | 1268 | @instruction([(0xED44, ())], 0, "NEG", 8) 1269 | def neg(instruction, registers, get_reads, data): 1270 | if get_reads: 1271 | return [] 1272 | else: 1273 | a = registers.A 1274 | registers.A = subtract8(0, a, registers) 1275 | registers.condition.PV = (a == 0x80) 1276 | registers.condition.C = (a != 0x00) 1277 | return [] 1278 | 1279 | @instruction([(0x3F, ())], 0, "CCF", 4) 1280 | def ccf(instruction, registers, get_reads, data): 1281 | if get_reads: 1282 | return [] 1283 | else: 1284 | registers.condition.H = registers.condition.C 1285 | registers.condition.N = 0 1286 | registers.condition.C = not registers.condition.C 1287 | set_f5_f3_from_a(registers) 1288 | return [] 1289 | 1290 | @instruction([(0x37, ())], 0, "SCF", 4) 1291 | def scf(instruction, registers, get_reads, data): 1292 | if get_reads: 1293 | return [] 1294 | else: 1295 | registers.condition.H = 0 1296 | registers.condition.N = 0 1297 | registers.condition.C = 1 1298 | set_f5_f3_from_a(registers) 1299 | return [] 1300 | 1301 | @instruction([(0x00, ())], 0, "NOP", 4) 1302 | def nop(instruction, registers, get_reads, data): 1303 | if get_reads: 1304 | return [] 1305 | else: 1306 | return [] 1307 | 1308 | @instruction([(0x76, ())], 0, "HALT", 4) 1309 | def halt(instruction, registers, get_reads, data): 1310 | if get_reads: 1311 | return [] 1312 | else: 1313 | registers.HALT = True 1314 | registers.PC = dec16(registers.PC) 1315 | return [] 1316 | 1317 | 1318 | @instruction([(0xF3, ())], 0, "DI", 4) 1319 | def di(instruction, registers, get_reads, data): 1320 | if get_reads: 1321 | return [] 1322 | else: 1323 | registers.IFF = False 1324 | registers.IFF2 = False 1325 | return [] 1326 | 1327 | @instruction([(0xFB, ())], 0, "EI", 4) 1328 | def ei(instruction, registers, get_reads, data): 1329 | if get_reads: 1330 | return [] 1331 | else: 1332 | registers.IFF = True 1333 | registers.IFF2 = True 1334 | return [] 1335 | 1336 | @instruction([(0xED46, (0,)), (0xED56, (1,)), (0xED5E, (2,))], 0, "IM {}", 8) 1337 | def im(instruction, registers, get_reads, data, mode): 1338 | if get_reads: 1339 | return [] 1340 | else: 1341 | registers.IM = mode 1342 | return [] 1343 | 1344 | 1345 | #-------------------------------------------------------------------- 1346 | # 16-Bit Arithmetic Group 1347 | #-------------------------------------------------------------------- 1348 | @instruction([(0x39, ("SP",)), (0x09, ("BC",)), (0x19, ("DE",)),(0x29, ("HL",))], 0, "ADD HL, {0}", 11) 1349 | def add16_hl(instruction, registers, get_reads, data, reg): 1350 | if get_reads: 1351 | return [] 1352 | else: 1353 | val = registers.HL + getattr(registers, reg) 1354 | dummy_reg = registers.create() 1355 | add8(registers.HL & 0xFF, getattr(registers, reg) & 0xFF, dummy_reg, PV=True) 1356 | registers.condition.H = dummy_reg.condition.C 1357 | add8(registers.HL >> 8, getattr(registers, reg) >> 8, dummy_reg, PV=True) 1358 | registers.condition.F3 = dummy_reg.condition.F3 1359 | registers.condition.F5 = dummy_reg.condition.F5 1360 | registers.condition.N = 0 1361 | registers.condition.C = ((val & 0x10000) != 0) 1362 | registers.HL = val & 0xFFFF 1363 | return [] 1364 | 1365 | @instruction([(0xED7A, ("SP",)), (0xED4A, ("BC",)), (0xED5A, ("DE",)),(0xED6A, ("HL",))], 0, "ADC HL, {0}", 15) 1366 | def adc16_hl(instruction, registers, get_reads, data, reg): 1367 | if get_reads: 1368 | return [] 1369 | else: 1370 | registers.HL = add16(registers.HL + registers.condition.C, getattr(registers, reg), registers) 1371 | 1372 | return [] 1373 | 1374 | @instruction([(0xED72, ("SP",)), (0xED42, ("BC",)), (0xED52, ("DE",)),(0xED62, ("HL",))], 0, "SBC HL, {0}", 15) 1375 | def sbc16_hl(instruction, registers, get_reads, data, reg): 1376 | if get_reads: 1377 | return [] 1378 | else: 1379 | a = registers.HL 1380 | b = registers[reg] 1381 | res = a - b 1382 | if registers.condition.C: 1383 | res -= 1 1384 | registers.condition.S = (res >> 15) & 0x01 1385 | registers.condition.N = 1 1386 | registers.condition.Z = (res == 0) 1387 | registers.condition.F3 = res & 0x0800 1388 | registers.condition.F5 = res & 0x2000 1389 | if (b & 0xFFF) > (a & 0xFFF) - registers.condition.C : 1390 | registers.condition.H = 1 1391 | else: 1392 | registers.condition.H = 0 1393 | 1394 | pvtest = get_16bit_twos_comp(a) - get_16bit_twos_comp(b) - registers.condition.C 1395 | if pvtest < -32768 or pvtest > 32767: 1396 | registers.condition.PV = 1 # overflow 1397 | else: 1398 | registers.condition.PV = 0 1399 | 1400 | registers.condition.C = ((res & 0x10000) != 0) 1401 | registers.HL = res & 0xFFFF 1402 | 1403 | return [] 1404 | 1405 | @instruction([(0xDD39, ("IX", "SP",)), (0xDD09, ("IX", "BC",)), (0xDD19, ("IX", "DE",)),(0xDD29, ("IX", "IX",)), 1406 | (0xFD39, ("IY", "SP",)), (0xFD09, ("IY", "BC",)), (0xFD19, ("IY", "DE",)),(0xFD29, ("IY", "IY",))], 1407 | 0, "ADD {0}, {1}", 15) 1408 | def add16_i_pp(instruction, registers, get_reads, data, i, r): 1409 | if get_reads: 1410 | return [] 1411 | else: 1412 | val = registers[i] + registers[r] 1413 | if ((registers[i] & 0xFFF) + (registers[r] & 0xFFF)) > 0xFFF : 1414 | registers.condition.H = 1 1415 | else: 1416 | registers.condition.H = 0 1417 | registers.condition.N = 0 1418 | registers.condition.C = ((val & 0x10000) != 0) 1419 | set_f5_f3(registers, (registers[i] >>8)+(registers[r]>>8)) 1420 | registers[i] = val & 0xFFFF 1421 | return [] 1422 | 1423 | 1424 | @instruction([(0x33, ("SP",)), (0x03, ("BC",)), (0x13, ("DE",)),(0x23, ("HL",)), 1425 | (0xDD23, ("IX",), 10), (0xFD23, ("IY",), 10)], 1426 | 0, "INC {0}", 6) 1427 | def inc16_ss(instruction, registers, get_reads, data, s): 1428 | if get_reads: 1429 | return [] 1430 | else: 1431 | registers[s] = inc16(registers[s]) 1432 | return [] 1433 | 1434 | 1435 | @instruction([(0x3b, ("SP",)), (0x0b, ("BC",)), (0x1b, ("DE",)),(0x2b, ("HL",)), 1436 | (0xDD2b, ("IX",), 10), (0xFD2b, ("IY",), 10)], 1437 | 0, "DEC {0}", 6) 1438 | def dec16_ss(instruction, registers, get_reads, data, s): 1439 | if get_reads: 1440 | return [] 1441 | else: 1442 | registers[s] = dec16(registers[s]) 1443 | return [] 1444 | 1445 | #-------------------------------------------------------------------- 1446 | # Rotate and Shift Group 1447 | #-------------------------------------------------------------------- 1448 | @instruction([(0x07, ())], 0, "RLCA", 4) 1449 | def rlca(instruction, registers, get_reads, data): 1450 | if get_reads: 1451 | return [] 1452 | else: 1453 | c = registers.A >> 7 1454 | registers.A = ((registers.A << 1) | c) & 0xFF 1455 | registers.condition.C = c 1456 | registers.condition.H = 0 1457 | registers.condition.N = 0 1458 | set_f5_f3_from_a(registers) 1459 | return [] 1460 | 1461 | @instruction([(0x17, ())], 0, "RLA", 4) 1462 | def rla(instruction, registers, get_reads, data): 1463 | if get_reads: 1464 | return [] 1465 | else: 1466 | c = registers.A >> 7 1467 | pc = registers.condition.C 1468 | registers.A = (registers.A << 1 | pc) & 0xFF 1469 | registers.condition.C = c 1470 | registers.condition.H = 0 1471 | registers.condition.N = 0 1472 | set_f5_f3_from_a(registers) 1473 | return [] 1474 | 1475 | @instruction([(0x0F, ())], 0, "RRCA", 4) 1476 | def rrca(instruction, registers, get_reads, data): 1477 | if get_reads: 1478 | return [] 1479 | else: 1480 | c = registers.A & 0x01 1481 | registers.A = (registers.A >> 1 | c << 7) & 0xFF 1482 | registers.condition.C = c 1483 | registers.condition.H = 0 1484 | registers.condition.N = 0 1485 | set_f5_f3_from_a(registers) 1486 | return [] 1487 | 1488 | @instruction([(0x1F, ())], 0, "RRA", 4) 1489 | def rra(instruction, registers, get_reads, data): 1490 | if get_reads: 1491 | return [] 1492 | else: 1493 | c = registers.A & 0x01 1494 | pc = registers.condition.C 1495 | registers.A = (registers.A >> 1 | pc << 7) & 0xFF 1496 | registers.condition.C = c 1497 | registers.condition.H = 0 1498 | registers.condition.N = 0 1499 | set_f5_f3_from_a(registers) 1500 | return [] 1501 | 1502 | 1503 | # RLC m 1504 | @instruction([(0xCB07, ("A", )), (0xCB00, ("B", )), (0xCB01, ("C", )), (0xCB02, ("D", )), 1505 | (0xCB03, ("E", )), (0xCB04, ("H", )), (0xCB05, ("L", ))], 1506 | 0, "RLC {0}", 8) 1507 | def rlc(instruction, registers, get_reads, data, r): 1508 | if get_reads: 1509 | return [] 1510 | else: 1511 | registers[r] = rotate_left_carry(registers, registers[r]) 1512 | set_f5_f3(registers, registers[r]) 1513 | return [] 1514 | 1515 | @instruction([(0xCB06, ( ))], 1516 | 0, "RLC (HL)", 15) 1517 | def rlc_hl_(instruction, registers, get_reads, data): 1518 | if get_reads: 1519 | return [registers.HL] 1520 | else: 1521 | val = rotate_left_carry(registers, data[0]) 1522 | set_f5_f3(registers, val) 1523 | return [(registers.HL, val)] 1524 | 1525 | 1526 | @instruction([([0xDD, 0xCB, '-', 0x06], ("IX", )), 1527 | ([0xFD, 0xCB, '-', 0x06], ("IY", ))], 1528 | 2, "RLC ({0}+{1:X}H)", 23) 1529 | def rlc_i_d(instruction, registers, get_reads, data, i, d): 1530 | if get_reads: 1531 | return [registers[i] + get_8bit_twos_comp(d)] 1532 | else: 1533 | new = rotate_left_carry(registers, data[0]) 1534 | set_f5_f3(registers, new) 1535 | return [(registers[i] + get_8bit_twos_comp(d), new)] 1536 | 1537 | # RL m 1538 | @instruction([([0xCB, 0x10], ("B", )), ([0xCB, 0x11], ("C", )), ([0xCB, 0x12], ("D", )), 1539 | ([0xCB, 0x13], ("E", )), ([0xCB, 0x14], ("H", )), ([0xCB, 0x15], ("L", )), 1540 | ([0xCB, 0x17], ("A", ))], 1541 | 2, "RL {0}", 8) 1542 | def rl_r(instruction, registers, get_reads, data, r): 1543 | if get_reads: 1544 | return [] 1545 | else: 1546 | registers[r] = rotate_left(registers, registers[r]) 1547 | set_f5_f3(registers, registers[r]) 1548 | return [] 1549 | 1550 | @instruction([([0xCB, 0x16], ())], 1551 | 2, "RL (HL)", 15) 1552 | def rl_hl(instruction, registers, get_reads, data): 1553 | if get_reads: 1554 | return [registers.HL] 1555 | else: 1556 | val = rotate_left(registers, data[0]) 1557 | set_f5_f3(registers, val) 1558 | return [(registers.HL, val)] 1559 | 1560 | @instruction([([0xDD, 0xCB, "-", 0x16], ("IX", )), 1561 | ([0xFD, 0xCB, "-", 0x16], ("IY", ))], 1562 | 2, "RL ({0}+{1:X}H)", 23) 1563 | def rl_i(instruction, registers, get_reads, data, i, d): 1564 | if get_reads: 1565 | return [registers[i] + get_8bit_twos_comp(d)] 1566 | else: 1567 | val = rotate_left(registers, data[0]) 1568 | set_f5_f3(registers, val) 1569 | return [(registers[i] + get_8bit_twos_comp(d), val)] 1570 | 1571 | 1572 | 1573 | 1574 | 1575 | 1576 | # RRC m 1577 | @instruction([(0xCB0F, ("A", )), (0xCB08, ("B", )), (0xCB09, ("C", )), (0xCB0A, ("D", )), 1578 | (0xCB0B, ("E", )), (0xCB0C, ("H", )), (0xCB0D, ("L", ))], 1579 | 0, "RRC {0}", 8) 1580 | def rrc(instruction, registers, get_reads, data, r): 1581 | if get_reads: 1582 | return [] 1583 | else: 1584 | registers[r] = rotate_right_carry(registers, registers[r]) 1585 | set_f5_f3(registers, registers[r]) 1586 | return [] 1587 | 1588 | @instruction([(0xCB0E, ( ))], 1589 | 0, "RRC (HL)", 15) 1590 | def rrc_hl_(instruction, registers, get_reads, data): 1591 | if get_reads: 1592 | return [registers.HL] 1593 | else: 1594 | val = rotate_right_carry(registers, data[0]) 1595 | set_f5_f3(registers, val) 1596 | return [(registers.HL, val)] 1597 | 1598 | 1599 | @instruction([([0xDD, 0xCB, '-', 0x0E], ("IX", )), 1600 | ([0xFD, 0xCB, '-', 0x0E], ("IY", ))], 1601 | 2, "RRC ({0}+{1:X}H)", 23) 1602 | def rrc_i_d(instruction, registers, get_reads, data, i, d): 1603 | if get_reads: 1604 | return [registers[i] + get_8bit_twos_comp(d)] 1605 | else: 1606 | new = rotate_right_carry(registers, data[0]) 1607 | set_f5_f3(registers, new) 1608 | return [(registers[i] + get_8bit_twos_comp(d), new)] 1609 | 1610 | # RR m 1611 | @instruction([([0xCB, 0x18], ("B", )), ([0xCB, 0x19], ("C", )), ([0xCB, 0x1A], ("D", )), 1612 | ([0xCB, 0x1B], ("E", )), ([0xCB, 0x1C], ("H", )), ([0xCB, 0x1D], ("L", )), 1613 | ([0xCB, 0x1F], ("A", ))], 1614 | 2, "RR {0}", 8) 1615 | def rr_r(instruction, registers, get_reads, data, r): 1616 | if get_reads: 1617 | return [] 1618 | else: 1619 | registers[r] = rotate_right(registers, registers[r]) 1620 | set_f5_f3(registers, registers[r]) 1621 | return [] 1622 | 1623 | @instruction([([0xCB, 0x1E], ())], 1624 | 2, "RR (HL)", 15) 1625 | def rr_hl(instruction, registers, get_reads, data): 1626 | if get_reads: 1627 | return [registers.HL] 1628 | else: 1629 | val = rotate_right(registers, data[0]) 1630 | set_f5_f3(registers, val) 1631 | return [(registers.HL, val)] 1632 | 1633 | @instruction([([0xDD, 0xCB, "-", 0x1E], ("IX", )), 1634 | ([0xFD, 0xCB, "-", 0x1E], ("IY", ))], 1635 | 2, "RR ({0}+{1:X}H)", 23) 1636 | def rr_i(instruction, registers, get_reads, data, i, d): 1637 | if get_reads: 1638 | return [registers[i] + get_8bit_twos_comp(d)] 1639 | else: 1640 | val = rotate_right(registers, data[0]) 1641 | set_f5_f3(registers, val) 1642 | return [(registers[i] + get_8bit_twos_comp(d), val)] 1643 | 1644 | 1645 | 1646 | 1647 | 1648 | 1649 | # SLA m 1650 | @instruction([(0xCB27, ("A", )), (0xCB20, ("B", )), (0xCB21, ("C", )), (0xCB22, ("D", )), 1651 | (0xCB23, ("E", )), (0xCB24, ("H", )), (0xCB25, ("L", ))], 1652 | 0, "SLA {0}", 8) 1653 | def sla_r(instruction, registers, get_reads, data, r): 1654 | if get_reads: 1655 | return [] 1656 | else: 1657 | registers[r] = shift_left(registers, registers[r]) 1658 | set_f5_f3(registers, registers[r]) 1659 | return [] 1660 | 1661 | @instruction([(0xCB26, ( ))], 1662 | 0, "SLA (HL)", 15) 1663 | def sla_hl_(instruction, registers, get_reads, data): 1664 | if get_reads: 1665 | return [registers.HL] 1666 | else: 1667 | val = shift_left(registers, data[0]) 1668 | set_f5_f3(registers, val) 1669 | return [(registers.HL, val)] 1670 | 1671 | 1672 | @instruction([([0xDD, 0xCB, '-', 0x26], ("IX", )), 1673 | ([0xFD, 0xCB, '-', 0x26], ("IY", ))], 1674 | 2, "SLA ({0}+{1:X}H)", 23) 1675 | def sla_i_d(instruction, registers, get_reads, data, i, d): 1676 | if get_reads: 1677 | return [registers[i] + get_8bit_twos_comp(d)] 1678 | else: 1679 | new = shift_left(registers, data[0]) 1680 | set_f5_f3(registers, new) 1681 | return [(registers[i] + get_8bit_twos_comp(d), new)] 1682 | 1683 | 1684 | # SLL m 1685 | @instruction([(0xCB37, ("A", )), (0xCB30, ("B", )), (0xCB31, ("C", )), (0xCB32, ("D", )), 1686 | (0xCB33, ("E", )), (0xCB34, ("H", )), (0xCB35, ("L", ))], 1687 | 0, "SLL {0}", 8) 1688 | def sll_r(instruction, registers, get_reads, data, r): 1689 | if get_reads: 1690 | return [] 1691 | else: 1692 | registers[r] = shift_left_logical(registers, registers[r]) 1693 | set_f5_f3(registers, registers[r]) 1694 | return [] 1695 | 1696 | @instruction([(0xCB36, ( ))], 1697 | 0, "SLL (HL)", 15) 1698 | def sll_hl_(instruction, registers, get_reads, data): 1699 | if get_reads: 1700 | return [registers.HL] 1701 | else: 1702 | val = shift_left_logical(registers, data[0]) 1703 | set_f5_f3(registers, val) 1704 | return [(registers.HL, val)] 1705 | 1706 | 1707 | @instruction([([0xDD, 0xCB, '-', 0x36], ("IX", )), 1708 | ([0xFD, 0xCB, '-', 0x36], ("IY", ))], 1709 | 2, "SLL ({0}+{1:X}H)", 23) 1710 | def sll_i_d(instruction, registers, get_reads, data, i, d): 1711 | if get_reads: 1712 | return [registers[i] + get_8bit_twos_comp(d)] 1713 | else: 1714 | new = shift_left_logical(registers, data[0]) 1715 | set_f5_f3(registers, new) 1716 | return [(registers[i] + get_8bit_twos_comp(d), new)] 1717 | 1718 | 1719 | # SRA m 1720 | @instruction([([0xCB, 0x28], ("B", )), ([0xCB, 0x29], ("C", )), ([0xCB, 0x2A], ("D", )), 1721 | ([0xCB, 0x2B], ("E", )), ([0xCB, 0x2C], ("H", )), ([0xCB, 0x2D], ("L", )), 1722 | ([0xCB, 0x2F], ("A", ))], 1723 | 2, "SRA {0}", 8) 1724 | def sra_r(instruction, registers, get_reads, data, r): 1725 | if get_reads: 1726 | return [] 1727 | else: 1728 | registers[r] = shift_right(registers, registers[r]) 1729 | set_f5_f3(registers, registers[r]) 1730 | return [] 1731 | 1732 | @instruction([([0xCB, 0x2E], ())], 1733 | 2, "SRA (HL)", 15) 1734 | def sra_hl(instruction, registers, get_reads, data): 1735 | if get_reads: 1736 | return [registers.HL] 1737 | else: 1738 | val = shift_right(registers, data[0]) 1739 | set_f5_f3(registers, val) 1740 | return [(registers.HL, val)] 1741 | 1742 | @instruction([([0xDD, 0xCB, "-", 0x2E], ("IX", )), 1743 | ([0xFD, 0xCB, "-", 0x2E], ("IY", ))], 1744 | 2, "SRA ({0}+{1:X}H)", 23) 1745 | def sra_i(instruction, registers, get_reads, data, i, d): 1746 | if get_reads: 1747 | return [registers[i] + get_8bit_twos_comp(d)] 1748 | else: 1749 | val = shift_right(registers, data[0]) 1750 | set_f5_f3(registers, val) 1751 | return [(registers[i] + get_8bit_twos_comp(d), val)] 1752 | 1753 | 1754 | # SRL m 1755 | @instruction([([0xCB, 0x38], ("B", )), ([0xCB, 0x39], ("C", )), ([0xCB, 0x3A], ("D", )), 1756 | ([0xCB, 0x3B], ("E", )), ([0xCB, 0x3C], ("H", )), ([0xCB, 0x3D], ("L", )), 1757 | ([0xCB, 0x3F], ("A", ))], 1758 | 2, "SRL {0}", 8) 1759 | def srl_r(instruction, registers, get_reads, data, r): 1760 | if get_reads: 1761 | return [] 1762 | else: 1763 | registers[r] = shift_right_logical(registers, registers[r]) 1764 | set_f5_f3(registers, registers[r]) 1765 | return [] 1766 | 1767 | @instruction([([0xCB, 0x3E], ())], 1768 | 2, "SRL (HL)", 15) 1769 | def srl_hl(instruction, registers, get_reads, data): 1770 | if get_reads: 1771 | return [registers.HL] 1772 | else: 1773 | val = shift_right_logical(registers, data[0]) 1774 | set_f5_f3(registers, val) 1775 | return [(registers.HL, val)] 1776 | 1777 | @instruction([([0xDD, 0xCB, "-", 0x3E], ("IX", )), 1778 | ([0xFD, 0xCB, "-", 0x3E], ("IY", ))], 1779 | 2, "SRL ({0}+{1:X}H)", 23) 1780 | def srl_i(instruction, registers, get_reads, data, i, d): 1781 | if get_reads: 1782 | return [registers[i] + get_8bit_twos_comp(d)] 1783 | else: 1784 | val = shift_right_logical(registers, data[0]) 1785 | set_f5_f3(registers, val) 1786 | return [(registers[i] + get_8bit_twos_comp(d), val)] 1787 | 1788 | 1789 | @instruction([([0xED, 0x6F], ())], 1790 | 2, "RLD", 18) 1791 | def rld(instruction, registers, get_reads, data): 1792 | if get_reads: 1793 | return [registers.HL] 1794 | else: 1795 | a = (data[0] >> 4) | (registers.A & 0xF0) 1796 | hl = ((data[0] << 4) | (registers.A & 0x0f)) & 0xFF 1797 | registers.A = a 1798 | registers.condition.S = a >> 7 1799 | registers.condition.Z = a == 0 1800 | registers.condition.H = 0 1801 | registers.condition.N = 0 1802 | registers.condition.PV = parity(a) 1803 | set_f5_f3(registers, registers.A) 1804 | return [(registers.HL, hl)] 1805 | 1806 | @instruction([([0xED, 0x67], ())], 1807 | 2, "RRD", 18) 1808 | def rrd(instruction, registers, get_reads, data): 1809 | if get_reads: 1810 | return [registers.HL] 1811 | else: 1812 | a = (data[0] & 0x0F) | (registers.A & 0xF0) 1813 | hl = ((data[0] >> 4) | (registers.A << 4)) & 0xFF 1814 | registers.A = a 1815 | registers.condition.S = a >> 7 1816 | registers.condition.Z = a == 0 1817 | registers.condition.H = 0 1818 | registers.condition.N = 0 1819 | registers.condition.PV = parity(a) 1820 | set_f5_f3(registers, registers.A) 1821 | return [(registers.HL, hl)] 1822 | 1823 | 1824 | 1825 | 1826 | #-------------------------------------------------------------------- 1827 | # Bit Set, Reset, and Test Group 1828 | #-------------------------------------------------------------------- 1829 | @instruction([ ([0xCB, 0x40 + (b << 3) + register_bits[reg]], (b, reg)) 1830 | for b in range(8) 1831 | for reg in ['A', 'B', 'C', 'D', 'E', 'H', 'L'] ] , 1832 | 2, "BIT {0}, {1}", 8) 1833 | def bit_r(instruction, registers, get_reads, data, bit, reg): 1834 | if get_reads: 1835 | return [] 1836 | else: 1837 | # print "Test bit ", bit 1838 | val = registers[reg] & (0x01 << bit) 1839 | registers.condition.Z = (val == 0) 1840 | registers.condition.H = 1 1841 | registers.condition.N = 0 1842 | registers.condition.PV = registers.condition.Z 1843 | registers.condition.S = (val >> 7) 1844 | #if bit == 5: 1845 | #registers.condition.F5 = (registers[reg] & (0x01 << bit)) 1846 | #if bit == 3: 1847 | #registers.condition.F3 = (registers[reg] & (0x01 << bit)) 1848 | set_f5_f3(registers, registers[reg]) 1849 | return [] 1850 | 1851 | @instruction( [ ([0xCB, 0x40 + (b << 3) + 6], (b,)) for b in range(8) ] , 1852 | 2, "BIT {0}, (HL)", 12) 1853 | def bit_hl(instruction, registers, get_reads, data, bit): 1854 | if get_reads: 1855 | return [registers.HL] 1856 | else: 1857 | val = data[0] & (0x01 << bit) 1858 | registers.condition.Z = (val == 0) 1859 | registers.condition.H = 1 1860 | registers.condition.N = 0 1861 | registers.condition.PV = registers.condition.Z 1862 | registers.condition.S = (val >> 7) 1863 | set_f5_f3(registers, data[0]) 1864 | return [] 1865 | 1866 | @instruction( [ ([I, 0xCB, '-', 0x40 + (b << 3) + 6], (Ir, b,)) for b in range(8) for I, Ir in index_bytes] , 1867 | 2, "BIT {1}, ({0}+{2:X}H)", 20) 1868 | def bit_i(instruction, registers, get_reads, data, i, bit, d): 1869 | if get_reads: 1870 | return [registers[i]+get_8bit_twos_comp(d)] 1871 | else: 1872 | val = data[0] & (0x01 << bit) 1873 | registers.condition.Z = (val == 0) 1874 | registers.condition.H = 1 1875 | registers.condition.N = 0 1876 | registers.condition.PV = registers.condition.Z 1877 | registers.condition.S = (val >> 7) 1878 | set_f5_f3(registers, (registers[i]+get_8bit_twos_comp(d)) >> 8) 1879 | return [] 1880 | 1881 | @instruction([ ([0xCB, 0xc0 + (b << 3) + register_bits[reg]], (b, reg)) 1882 | for b in range(8) 1883 | for reg in ['A', 'B', 'C', 'D', 'E', 'H', 'L'] ] , 1884 | 2, "SET {0}, {1}", 8) 1885 | def set_r(instruction, registers, get_reads, data, bit, reg): 1886 | if get_reads: 1887 | return [] 1888 | else: 1889 | registers[reg] |= (0x01 << bit) 1890 | return [] 1891 | 1892 | @instruction( [ ([0xCB, 0xc0 + (b << 3) + 6], (b,)) for b in range(8) ] , 1893 | 2, "SET {0}, (HL)", 15) 1894 | def set_hl(instruction, registers, get_reads, data, bit): 1895 | if get_reads: 1896 | return [registers.HL] 1897 | else: 1898 | val = data[0] | (0x01 << bit) 1899 | return [(registers.HL, val)] 1900 | 1901 | @instruction( [ ([I, 0xCB, '-', 0xc0 + (b << 3) + 6], (Ir, b,)) 1902 | for b in range(8) 1903 | for I, Ir in index_bytes] , 1904 | 2, "SET {1}, ({0}+{2:X}H)", 23) 1905 | def set_i(instruction, registers, get_reads, data, i, bit, d): 1906 | if get_reads: 1907 | return [registers[i] + get_8bit_twos_comp(d)] 1908 | else: 1909 | val = data[0] | (0x01 << bit) 1910 | return [(registers[i] + get_8bit_twos_comp(d), val)] 1911 | 1912 | @instruction([ ([0xCB, 0x80 + (b << 3) + register_bits[reg]], (b, reg)) 1913 | for b in range(8) 1914 | for reg in ['A', 'B', 'C', 'D', 'E', 'H', 'L'] ] , 1915 | 2, "RES {0}, {1}", 8) 1916 | def res_r(instruction, registers, get_reads, data, bit, reg): 1917 | if get_reads: 1918 | return [] 1919 | else: 1920 | registers[reg] &= ~(0x01 << bit) 1921 | return [] 1922 | 1923 | @instruction( [ ([0xCB, 0x80 + (b << 3) + 6], (b,)) 1924 | for b in range(8) ] , 1925 | 2, "RES {0}, (HL)", 15) 1926 | def res_hl(instruction, registers, get_reads, data, bit): 1927 | if get_reads: 1928 | return [registers.HL] 1929 | else: 1930 | val = data[0] & ~(0x01 << bit) 1931 | return [(registers.HL, val)] 1932 | 1933 | @instruction( [ ([I, 0xCB, '-', 0x80 + (b << 3) + 6], (Ir, b,)) 1934 | for b in range(8) 1935 | for I, Ir in index_bytes] , 1936 | 2, "RES {1}, ({0}+{2:X}H)", 23) 1937 | def res_i(instruction, registers, get_reads, data, i, bit, d): 1938 | if get_reads: 1939 | return [registers[i] + get_8bit_twos_comp(d)] 1940 | else: 1941 | val = data[0] & ~(0x01 << bit) 1942 | return [(registers[i] + get_8bit_twos_comp(d), val)] 1943 | 1944 | 1945 | 1946 | #-------------------------------------------------------------------- 1947 | # Jump Group 1948 | #-------------------------------------------------------------------- 1949 | @instruction([([0xC3, '-', '-'], ())], 1950 | 2, "JP {1:X}{0:X}H", 10) 1951 | def jp(instruction, registers, get_reads, data, n, n2): 1952 | if get_reads: 1953 | return [] 1954 | else: 1955 | registers.PC = n2 << 8 | n 1956 | return [] 1957 | 1958 | 1959 | @instruction([([0xC2+offset, '-', '-'], (reg, reg_name, val)) 1960 | for offset, reg_name, reg, val in conditions], 1961 | 2, "JP {1}, {4:x}{3:X}H", 10) 1962 | def jp_c(instruction, registers, get_reads, data, reg, reg_name, val, n, n2): 1963 | if get_reads: 1964 | return [] 1965 | else: 1966 | if getattr(registers.condition, reg) == val: 1967 | registers.PC = n2 << 8 | n 1968 | return [] 1969 | 1970 | 1971 | 1972 | @instruction([([0x18, '-'], ())], 1973 | 2, "JR {0:X}H", 12) 1974 | def jr(instruction, registers, get_reads, data, n): 1975 | if get_reads: 1976 | return [] 1977 | else: 1978 | offset_pc(registers, n) 1979 | return [] 1980 | 1981 | @instruction([([0x20, '-'], ())], 1982 | 2, "JR NZ, {0:X}H", 12) 1983 | def jr_nz(instruction, registers, get_reads, data, n): 1984 | if get_reads: 1985 | return [] 1986 | else: 1987 | if not registers.condition.Z: 1988 | offset_pc(registers, n) 1989 | instruction.tstates = 12 1990 | else: 1991 | instruction.tstates = 7 1992 | return [] 1993 | 1994 | 1995 | @instruction([([0x28, '-'], ())], 1996 | 2, "JR Z, {0:X}H", 12) 1997 | def jr_z(instruction, registers, get_reads, data, n): 1998 | if get_reads: 1999 | return [] 2000 | else: 2001 | if registers.condition.Z: 2002 | offset_pc(registers, n) 2003 | instruction.tstates = 12 2004 | else: 2005 | instruction.tstates = 7 2006 | return [] 2007 | 2008 | 2009 | @instruction([([0x30, '-'], ())], 2010 | 2, "JR NC, {0:X}H", 12) 2011 | def jr_nc(instruction, registers, get_reads, data, n): 2012 | if get_reads: 2013 | return [] 2014 | else: 2015 | if not registers.condition.C: 2016 | offset_pc(registers, n) 2017 | instruction.tstates = 12 2018 | else: 2019 | instruction.tstates = 7 2020 | return [] 2021 | 2022 | 2023 | @instruction([([0x38, '-'], ())], 2024 | 2, "JR C, {0:X}H", 12) 2025 | def jr_c(instruction, registers, get_reads, data, n): 2026 | if get_reads: 2027 | return [] 2028 | else: 2029 | if registers.condition.C: 2030 | offset_pc(registers, n) 2031 | instruction.tstates = 12 2032 | else: 2033 | instruction.tstates = 7 2034 | return [] 2035 | 2036 | @instruction([([0xE9], ("HL", )),([0xDD, 0xE9], ("IX", ), 8),([0xFD, 0xE9], ("IY", ), 8) ], 2037 | 2, "JP ({})", 4) 2038 | def jp_r(instruction, registers, get_reads, data, r): 2039 | if get_reads: 2040 | return [] 2041 | else: 2042 | registers.PC = registers[r] 2043 | return [] 2044 | 2045 | @instruction([([0x10, '-'], ())], 2046 | 2, "DJNZ {0:X}H", 13) 2047 | def djnz(instruction, registers, get_reads, data, n): 2048 | if get_reads: 2049 | return [] 2050 | else: 2051 | registers.B = dec8(registers.B) 2052 | if not registers.B == 0: 2053 | offset_pc(registers, n) 2054 | instruction.tstates = 13 2055 | else: 2056 | instruction.tstates = 8 2057 | return [] 2058 | 2059 | #-------------------------------------------------------------------- 2060 | # Call And Return Group 2061 | #-------------------------------------------------------------------- 2062 | @instruction([([0xCD, '-', '-'], ())], 2063 | 2, "CALL {1:X}{0:X}H", 17) 2064 | def call(instruction, registers, get_reads, data, n, n2): 2065 | if get_reads: 2066 | return [] 2067 | else: 2068 | sp = registers.SP 2069 | pc = registers.PC 2070 | registers.SP = dec16(registers.SP) 2071 | registers.SP = dec16(registers.SP) 2072 | registers.PC = n2 << 8 | n 2073 | return [(dec16(sp), pc >> 8), 2074 | (dec16(dec16(sp)), pc & 0xFF)] 2075 | 2076 | @instruction([([0xC4+offset, '-', '-'], (reg, reg_name, val)) 2077 | for offset, reg_name, reg, val in conditions], 2078 | 2, "CALL {1}, {4:x}{3:X}H", 17) 2079 | def call_c(instruction, registers, get_reads, data, reg, reg_name, val, n, n2): 2080 | if get_reads: 2081 | return [] 2082 | else: 2083 | if getattr(registers.condition, reg) == val: 2084 | instruction.tstates = 17 2085 | sp = registers.SP 2086 | pc = registers.PC 2087 | registers.SP = dec16(registers.SP) 2088 | registers.SP = dec16(registers.SP) 2089 | registers.PC = n2 << 8 | n 2090 | return [(dec16(sp), pc >> 8), 2091 | (dec16(dec16(sp)), pc & 0xFF)] 2092 | else: 2093 | instruction.tstates = 10 2094 | return [] 2095 | 2096 | @instruction([([0xC9], ())], 2097 | 2, "RET", 10) 2098 | def ret(instruction, registers, get_reads, data): 2099 | if get_reads: 2100 | return [registers.SP, inc16(registers.SP)] 2101 | else: 2102 | registers.SP = inc16(registers.SP) 2103 | registers.SP = inc16(registers.SP) 2104 | registers.PC = data[1] << 8 | data[0] 2105 | return [] 2106 | 2107 | @instruction([([0xC0+offset], (reg, reg_name, val)) 2108 | for offset, reg_name, reg, val in conditions], 2109 | 2, "RET {1}", 11) 2110 | def ret_c(instruction, registers, get_reads, data, reg, reg_name, val): 2111 | if get_reads: 2112 | return [registers.SP, inc16(registers.SP)] 2113 | else: 2114 | if getattr(registers.condition, reg) == val: 2115 | registers.SP = inc16(registers.SP) 2116 | registers.SP = inc16(registers.SP) 2117 | registers.PC = data[1] << 8 | data[0] 2118 | instruction.tstates = 11 2119 | else: 2120 | instruction.tstates = 5 2121 | return [] 2122 | 2123 | @instruction([([0xed, 0x4d], ())], 2, "RETI", 14) 2124 | def reti(instruction, registers, get_reads, data): 2125 | if get_reads: 2126 | return [registers.SP, inc16(registers.SP)] 2127 | else: 2128 | #TODO: implement return from interrupt 2129 | logging.warn("RETI not fully implemented") 2130 | registers.SP = inc16(registers.SP) 2131 | registers.SP = inc16(registers.SP) 2132 | registers.PC = data[1] << 8 | data[0] 2133 | return [] 2134 | 2135 | @instruction([([0xed, 0x45], ())], 2, "RETN", 14) 2136 | def retn(instruction, registers, get_reads, data): 2137 | if get_reads: 2138 | return [registers.SP, inc16(registers.SP)] 2139 | else: 2140 | #TODO: implement from non masked interrupt 2141 | logging.warn("RETN not fully implemented") 2142 | registers.SP = inc16(registers.SP) 2143 | registers.SP = inc16(registers.SP) 2144 | registers.PC = data[1] << 8 | data[0] 2145 | registers.IFF = registers.IFF2 2146 | return [] 2147 | 2148 | @instruction([([0xC7 + (t << 3) ], (p, )) for t, p in enumerate([0x0, 0x08, 0x10, 0x18, 2149 | 0x20, 0x28, 0x30, 0x38]) ] , 2150 | 2, "RST {0:X}H", 11) 2151 | def rst_p(instruction, registers, get_reads, data, p): 2152 | if get_reads: 2153 | return [] 2154 | else: 2155 | sp = registers.SP 2156 | pc = registers.PC 2157 | registers.SP = dec16(registers.SP) 2158 | registers.SP = dec16(registers.SP) 2159 | registers.PC = p 2160 | return [(dec16(sp), pc >> 8), 2161 | (dec16(dec16(sp)), pc & 0xFF)] 2162 | 2163 | #-------------------------------------------------------------------- 2164 | # Input Output Group 2165 | #-------------------------------------------------------------------- 2166 | @instruction([([0xDB, '-'], ( )) ] , 2167 | 2, "IN A, ({0:X}H)", 11) 2168 | def in_a_n(instruction, registers, get_reads, data, n): 2169 | if get_reads: 2170 | address = n | (registers.A << 8) # registers.C | (registers.B << 8) 2171 | return [address+0x10000] 2172 | else: 2173 | registers.A = data[0] 2174 | return [] 2175 | 2176 | @instruction([([0xEd, 0x40+(i<<3)], (r, )) for i, r in enumerate("BCDEHLFA")] , 2177 | 2, "IN {0}, (C)", 12) 2178 | def in_r_c(instruction, registers, get_reads, data, r): 2179 | if get_reads: 2180 | address = registers.C | (registers.B << 8) #n | (registers.A << 8) 2181 | return [address+0x10000] 2182 | else: 2183 | registers.condition.S = data[0] & 0x80 2184 | registers.condition.Z = data[0] == 0 2185 | registers.condition.H = 0 2186 | registers.condition.PV = parity(data[0]) 2187 | registers.condition.N = 0 2188 | if r == "F": 2189 | return [] 2190 | registers[r] = data[0] 2191 | return [] 2192 | 2193 | @instruction([([0xed, 0xa2], ( )) ] , 2194 | 2, "INI", 16) 2195 | def ini(instruction, registers, get_reads, data): 2196 | if get_reads: 2197 | address = registers.C | (dec8(registers.B) << 8) 2198 | return [address+0x10000] 2199 | else: 2200 | hl = registers.HL 2201 | registers.B = dec8(registers.B) 2202 | registers.HL = inc16(hl) 2203 | registers.condition.N = 1 2204 | registers.condition.Z = registers.B == 0 2205 | return [(hl, data[0])] 2206 | 2207 | 2208 | @instruction([([0xed, 0xb2], ( )) ] , 2209 | 2, "INIR", 21) 2210 | def inir(instruction, registers, get_reads, data): 2211 | if get_reads: 2212 | address = registers.C | (dec8(registers.B) << 8) 2213 | return [address+0x10000] 2214 | else: 2215 | hl = registers.HL 2216 | registers.B = dec8(registers.B) 2217 | registers.HL = inc16(hl) 2218 | registers.condition.N = 1 2219 | registers.condition.Z = registers.B == 0 2220 | if registers.B != 0: 2221 | registers.PC = dec16(registers.PC) 2222 | registers.PC = dec16(registers.PC) 2223 | instruction.tstates = 21 2224 | else: 2225 | instruction.tstates = 16 2226 | return [(hl, data[0])] 2227 | 2228 | @instruction([([0xed, 0xaa], ( )) ] , 2229 | 2, "IND", 16) 2230 | def ind(instruction, registers, get_reads, data): 2231 | if get_reads: 2232 | address = registers.C | (dec8(registers.B) << 8) 2233 | return [address+0x10000] 2234 | else: 2235 | hl = registers.HL 2236 | registers.B = dec8(registers.B) 2237 | registers.HL = dec16(hl) 2238 | registers.condition.N = 1 2239 | registers.condition.Z = registers.B == 0 2240 | return [(hl, data[0])] 2241 | 2242 | 2243 | @instruction([([0xed, 0xba], ( )) ] , 2244 | 2, "INDR", 21) 2245 | def indr(instruction, registers, get_reads, data): 2246 | if get_reads: 2247 | address = registers.C | (dec8(registers.B) << 8) 2248 | return [address+0x10000] 2249 | else: 2250 | hl = registers.HL 2251 | registers.B = dec8(registers.B) 2252 | registers.HL = dec16(hl) 2253 | registers.condition.N = 1 2254 | registers.condition.Z = registers.B == 0 2255 | if registers.B != 0: 2256 | registers.PC = dec16(registers.PC) 2257 | registers.PC = dec16(registers.PC) 2258 | instruction.tstates = 21 2259 | else: 2260 | instruction.tstates = 16 2261 | return [(hl, data[0])] 2262 | 2263 | @instruction([([0xD3, '-'], ( )) ] , 2264 | 2, "OUT ({0:X}H), A", 11) 2265 | def out_a_n(instruction, registers, get_reads, data, n): 2266 | if get_reads: 2267 | return [] 2268 | else: 2269 | address = n | (registers.A << 8) 2270 | #if n == 0x81: 2271 | ##logging.info("=========================================== %s =="%chr(registers.A)) 2272 | ##print chr(registers.A), 2273 | #sys.stdout.flush() 2274 | return [(address+0x10000, registers.A)] 2275 | 2276 | @instruction([([0xEd, 0x41+(i<<3)], (r, )) for i, r in enumerate("BCDEHLFA")] , 2277 | 2, "OUT (C), {0}", 12) 2278 | def out_r_c(instruction, registers, get_reads, data, r): 2279 | if get_reads: 2280 | return [] 2281 | else: 2282 | if r == "F": 2283 | return [] 2284 | return [(registers.BC+0x10000, registers[r])] 2285 | 2286 | @instruction([([0xed, 0xa3], ( )) ] , 2287 | 2, "OUTI", 16) 2288 | def outi(instruction, registers, get_reads, data): 2289 | if get_reads: 2290 | return [registers.HL] 2291 | else: 2292 | address = registers.C | (registers.B << 8) 2293 | registers.B = dec8(registers.B) 2294 | registers.HL = inc16(registers.HL) 2295 | registers.condition.N = 1 2296 | registers.condition.Z = registers.B == 0 2297 | return [(address+0x10000, data[0])] 2298 | 2299 | 2300 | @instruction([([0xed, 0xb3], ( )) ] , 2301 | 2, "OTIR", 21) 2302 | def otir(instruction, registers, get_reads, data): 2303 | if get_reads: 2304 | return [registers.HL] 2305 | else: 2306 | address = registers.C | (registers.B << 8) 2307 | registers.B = dec8(registers.B) 2308 | registers.HL = inc16(registers.HL) 2309 | registers.condition.N = 1 2310 | registers.condition.Z = registers.B == 0 2311 | if registers.B != 0: 2312 | registers.PC = dec16(registers.PC) 2313 | registers.PC = dec16(registers.PC) 2314 | instruction.tstates = 21 2315 | else: 2316 | instruction.tstates = 16 2317 | 2318 | return [(address+0x10000, data[0])] 2319 | 2320 | @instruction([([0xed, 0xab], ( )) ] , 2321 | 2, "OUTD", 16) 2322 | def outd(instruction, registers, get_reads, data): 2323 | if get_reads: 2324 | return [registers.HL] 2325 | else: 2326 | address = registers.C | (registers.B << 8) 2327 | registers.B = dec8(registers.B) 2328 | registers.HL = dec16(registers.HL) 2329 | registers.condition.N = 1 2330 | registers.condition.Z = registers.B == 0 2331 | return [(address+0x10000, data[0])] 2332 | 2333 | 2334 | @instruction([([0xed, 0xbb], ( )) ] , 2335 | 2, "OTDR", 21) 2336 | def otdr(instruction, registers, get_reads, data): 2337 | if get_reads: 2338 | return [registers.HL] 2339 | else: 2340 | address = registers.C | (registers.B << 8) 2341 | registers.B = dec8(registers.B) 2342 | registers.HL = dec16(registers.HL) 2343 | registers.condition.N = 1 2344 | registers.condition.Z = registers.B == 0 2345 | if registers.B != 0: 2346 | registers.PC = dec16(registers.PC) 2347 | registers.PC = dec16(registers.PC) 2348 | instruction.tstates = 21 2349 | else: 2350 | instruction.tstates = 16 2351 | 2352 | return [(address+0x10000, data[0])] 2353 | -------------------------------------------------------------------------------- /src/z80/io.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | from PySide2.QtCore import * 4 | from PySide2.QtGui import * 5 | from PySide2.QtWidgets import * 6 | 7 | class IO(object): 8 | _addresses = [] 9 | def read(self, address): 10 | pass 11 | def write(self, address, value): 12 | pass 13 | 14 | class Interruptable(object): 15 | def interrupt(self): 16 | print ("interrupt") 17 | pass 18 | 19 | class Console(QTextEdit, IO): 20 | _addresses = [0x80, 0x81] 21 | _wrt_sgnl = Signal(int, int) 22 | def __init__(self, interruptable): 23 | #assert isinstance(interruptable, Interruptable ) 24 | super(Console, self).__init__() 25 | self.setPlainText("") 26 | self.setFontFamily("Courier") 27 | self.setFontPointSize(12) 28 | self._modifiers = {} 29 | self.setCursorWidth(0) 30 | self._interruptable = interruptable 31 | self._wrt_sgnl.connect(self._write) 32 | self.setReadOnly(True) 33 | self.setGeometry(300, 0, 640, 480) 34 | 35 | 36 | self._send_queue = None 37 | 38 | def read(self, address): 39 | print ("READ ", address) 40 | if address == 0x80: 41 | v = ((1 << 1) | # RTS 42 | ((self._send_queue is not None) << 0) | # interrupt? 43 | 0 ) 44 | return v 45 | elif address == 0x81: 46 | if self._send_queue is not None: 47 | val = self._send_queue 48 | self._send_queue = None 49 | return val 50 | return 0x13 51 | 52 | 53 | @Slot(int, int) 54 | def write(self, address, value): 55 | print ("------> WRITE ", address) 56 | self._wrt_sgnl.emit(address, value) 57 | 58 | def _write(self, address, value): 59 | if address == 0x80: 60 | pass 61 | elif address == 0x81: 62 | if value < 128 and value > 10: 63 | self.setText(self.toPlainText()+chr(value)) 64 | else: 65 | self.setText(self.toPlainText()+".") 66 | else: 67 | raise Exception("Trying Console IO with wrong address") 68 | 69 | def keyPressEvent(self, event): 70 | # print ("Event:", event) 71 | if isinstance(event, QKeyEvent): 72 | if event.key() > 255: 73 | self._modifiers[event.key()] = True 74 | #else: 75 | #self.setText(self.toPlainText()+chr(event.key())) 76 | if True: 77 | super(QTextEdit, self).keyPressEvent(event) 78 | 79 | def keyReleaseEvent(self, event): 80 | # print ("Event:", event) 81 | if isinstance(event, QKeyEvent): 82 | key = event.key() 83 | if key == Qt.Key_Return or event.key() == Qt.Key_Enter: 84 | key = 13 85 | if event.key() > 255: 86 | self._modifiers[event.key()] = False 87 | #print (key) 88 | 89 | if self._send_queue is None: 90 | self._send_queue = key 91 | self._interruptable.interrupt() 92 | pass 93 | 94 | 95 | class IOMap(object): 96 | def __init__(self): 97 | self.address = {} 98 | pass 99 | def addDevice(self, dev): 100 | assert isinstance(dev, IO) 101 | for i in dev._addresses: 102 | self.address[i] = dev 103 | 104 | def interupt(self): 105 | pass 106 | 107 | -------------------------------------------------------------------------------- /src/z80/registers.py: -------------------------------------------------------------------------------- 1 | class BitAccesser(object): 2 | def __init__(self, bit_names, registers, reg): 3 | object.__setattr__(self, "bits", 4 | dict(zip(bit_names, range(7, -1, -1)))) 5 | self.registers = registers 6 | #self.registers = registers 7 | self.reg = reg 8 | 9 | def __getattr__(self, b): 10 | return (self.registers[self.reg] >> self.bits[b]) & 1 11 | 12 | def __setattr__(self, b, v): 13 | if not b in self.bits: 14 | object.__setattr__(self, b, v) 15 | return 16 | 17 | if v: 18 | self.registers[self.reg] = self.registers[self.reg] | (1 << self.bits[b]) 19 | else: 20 | self.registers[self.reg] = self.registers[self.reg] & ((1 << self.bits[b]) ^ 0xFF) 21 | 22 | class Registers(dict): 23 | def __init__(self, *arg, **kw): 24 | super(Registers, self).__init__(*arg, **kw) 25 | 26 | self.reset() 27 | 28 | def reset(self): 29 | self["PC"] = 0 # Program Counter (16bit) 30 | self["SP"] = 0 # Stack Pointer (16bit) 31 | self["IX"] = 0 # Index Register X (16bit) 32 | self["IY"] = 0 # Index Register Y (16bit) 33 | self["I"] = 0 # Interrupt Page Address (8bit) 34 | self["R"] = 0 # Memory Refresh (8bit) 35 | 36 | self["A"] = 0 # Accumulator (8bit) 37 | self["F"] = 0 # Flags (8bit) 38 | self["A_"] = 0 # Alt. Accumulator (8bit) 39 | self["F_"] = 0 # Alt. Flags (8bit) 40 | 41 | self["B"] = 0 # General (8bit) 42 | self["C"] = 0 # General (8bit) 43 | self["B_"] = 0 # General (8bit) 44 | self["C_"] = 0 # General (8bit) 45 | 46 | self["D"] = 0 # General (8bit) 47 | self["E"] = 0 # General (8bit) 48 | self["D_"] = 0 # General (8bit) 49 | self["E_"] = 0 # General (8bit) 50 | 51 | self["H"] = 0 # General (8bit) 52 | self["L"] = 0 # General (8bit) 53 | self["H_"] = 0 # General (8bit) 54 | self["L_"] = 0 # General (8bit) 55 | 56 | self["condition"] = BitAccesser(["S", "Z", "F5", "H", "F3", "PV", "N", "C"], self, "F") 57 | 58 | self['HALT']=False # 59 | self['IFF']=False # Interrupt flip flop 60 | self['IFF2']=False # NM Interrupt flip flop 61 | self['IM']=False # Iterrupt mode 62 | 63 | def __setattr__(self, attr, val): 64 | if attr in ["HL", "AF", "BC", "DE"]: 65 | self[attr[0]] = val >> 8 66 | self[attr[1]] = val & 0xFF 67 | elif attr in ["IXH", "IYH"]: 68 | self[attr[0:2]] = (self[attr[0:2]] & 0x00FF) | (val << 8) 69 | elif attr in ["IXL", "IYL"]: 70 | self[attr[0:2]] = (self[attr[0:2]] & 0xFF00) | val 71 | else: 72 | self[attr] = val 73 | 74 | def __getattr__(self, reg): 75 | if reg in self: 76 | return self[reg] 77 | elif reg in ["HL", "AF", "BC", "DE"]: 78 | return self[reg[0]] << 8 | self[reg[1]] 79 | elif reg in ["IXH", "IYH"]: 80 | return self[reg[0:2]] >> 8 81 | elif reg in ["IXL", "IYL"]: 82 | return self[reg[0:2]] & 0xFF 83 | else: 84 | raise AttributeError("%s Not a known register."%reg) 85 | 86 | def __getitem__(self, reg): 87 | if reg in ["BC", "HL", "DE", "AF", "IXH", "IXL", "IYH", "IYL"]: 88 | return getattr(self, reg) 89 | else: 90 | return super(Registers, self).__getitem__(reg) 91 | 92 | def __setitem__(self, reg, val): 93 | if reg in ["BC", "HL", "DE", "AF", "IXH", "IXL", "IYH", "IYL"]: 94 | return setattr(self, reg, val) 95 | else: 96 | return super(Registers, self).__setitem__(reg, val) 97 | 98 | @classmethod 99 | def create(cls): 100 | return cls() 101 | 102 | -------------------------------------------------------------------------------- /src/z80/util.py: -------------------------------------------------------------------------------- 1 | register_bits = {'A': 7, 'B': 0, 'C': 1, 'D': 2, 'E': 3, 'H': 4, 'L': 5} 2 | index_bytes = [(0xDD, 'IX'), (0xfd, 'IY')] 3 | # i, name, bit, val 4 | conditions = [(0 << 3, 'NZ', 'Z', 0), 5 | (1 << 3, 'Z', 'Z', 1), 6 | (2 << 3, 'NC', 'C', 0), 7 | (3 << 3, 'C', 'C', 1), 8 | (4 << 3, 'PO', 'PV', 0), 9 | (5 << 3, 'PE', 'PV', 1), 10 | (6 << 3, 'P', 'S', 0), 11 | (7 << 3, 'M', 'S', 1),] 12 | 13 | def get_16bit_twos_comp(val): 14 | """ Return the value of an 8bit 2s comp number""" 15 | sg = val >> 15 16 | if sg == 1: 17 | mag = - ((val ^ 0xFFFF) + 1) 18 | return mag 19 | else: 20 | return val 21 | 22 | def get_8bit_twos_comp(val): 23 | """ Return the value of an 8bit 2s comp number""" 24 | sg = val >> 7 25 | if sg == 1: 26 | mag = - ((val ^ 0xFF) + 1) 27 | return mag 28 | else: 29 | return val 30 | 31 | def make_8bit_twos_comp(val): 32 | if val > -1: 33 | return val 34 | val = (0 - val) ^ 0xFF 35 | val += 1 36 | return val 37 | 38 | def subtract8(a, b, registers, S=True, N=True, Z=True, 39 | F3=True, F5=True, H=True, PV=False, C=False): 40 | """ subtract b from a, return result and set flags """ 41 | res = a - b 42 | if S: 43 | registers.condition.S = (res >> 7) & 0x01 44 | if N: 45 | registers.condition.N = 1 46 | if Z: 47 | registers.condition.Z = (res == 0) 48 | if F3: 49 | registers.condition.F3 = res & 0x08 50 | if F5: 51 | registers.condition.F5 = res & 0x20 52 | if H: 53 | if (b & 0xF) > (a & 0xF) : 54 | registers.condition.H = 1 55 | else: 56 | registers.condition.H = 0 57 | if PV: 58 | #if (a >> 7 != b >> 7): 59 | #if (b >> 7): 60 | #if a > (a | (0x1 << 7)): 61 | #registers.condition.PV = 1 # overflow 62 | a = get_8bit_twos_comp(a) 63 | b = get_8bit_twos_comp(b) 64 | if (a - b) < -127 or (a - b) > 128: 65 | registers.condition.PV = 1 # overflow 66 | #if get_8bit_twos_comp(res) < -127 or get_8bit_twos_comp(res) > 128: 67 | #registers.condition.PV = 1 # overflow 68 | else: 69 | registers.condition.PV = 0 70 | if C: 71 | registers.condition.C = ((res & 0x100) != 0) 72 | return res & 0xFF 73 | 74 | def subtract8_check_overflow(a, b, registers): 75 | return subtract8(a, b, registers, PV=True, C=True) 76 | 77 | def add8(a, b, registers, S=True, Z=True, H=True, 78 | PV=True, N=True, C=True, F3=True, F5=True): 79 | """ add a and b, return result and set flags """ 80 | res = a + b 81 | if S: 82 | registers.condition.S = (res >> 7) & 0x01 83 | if Z: 84 | registers.condition.Z = (res & 0xFF == 0) 85 | if H: 86 | if ((a & 0xF) + (b & 0xF)) > 0xF : 87 | registers.condition.H = 1 88 | else: 89 | registers.condition.H = 0 90 | if PV: 91 | if ((a >> 7) == (b >> 7) and (a >> 7) != ((res & 0xFF) >> 7)): 92 | registers.condition.PV = 1 # overflow 93 | else: 94 | registers.condition.PV = 0 95 | if N: 96 | registers.condition.N = 0 97 | if C: 98 | registers.condition.C = ((res & 0x100) != 0) 99 | if F3: 100 | registers.condition.F3 = res & 0x08 101 | if F5: 102 | registers.condition.F5 = res & 0x20 103 | return res & 0xFF 104 | 105 | def add16(a, b, registers): 106 | """ add a and b, return result and set flags """ 107 | res = a + b 108 | print (a, "+",b,"=",res) 109 | registers.condition.S = (res >> 15) & 0x01 110 | registers.condition.Z = (res == 0) 111 | if ((a & 0xFFF) + (b & 0xFFF)) > 0xFFF : 112 | registers.condition.H = 1 113 | else: 114 | registers.condition.H = 0 115 | if ((a >> 15) == (b >> 15) and (a >> 15) != ((res & 0xFFFF) >> 15)): 116 | registers.condition.PV = 1 # overflow 117 | else: 118 | registers.condition.PV = 0 119 | registers.condition.N = 0 120 | registers.condition.C = ((res & 0x10000) != 0) 121 | 122 | registers.condition.F3 = res & 0x0800 123 | registers.condition.F5 = res & 0x2000 124 | return res & 0xFFFF 125 | 126 | def subtract16(a, b, registers): 127 | """ subtract b from a, return result and set flags """ 128 | res = a - b 129 | print (a, "-", b, "=", res, "(", hex(res), ")") 130 | registers.condition.S = (res >> 15) & 0x01 131 | registers.condition.N = 1 132 | registers.condition.Z = (res == 0) 133 | registers.condition.F3 = res & 0x0800 134 | registers.condition.F5 = res & 0x2000 135 | if (b & 0xFFF) > (a & 0xFFF) : 136 | registers.condition.H = 1 137 | else: 138 | registers.condition.H = 0 139 | 140 | if (a >> 15 != (res&0xFFFF) >> 15): 141 | registers.condition.PV = 1 # overflow 142 | else: 143 | registers.condition.PV = 0 144 | 145 | registers.condition.C = ((res & 0x10000) != 0) 146 | return res & 0xFFFF 147 | 148 | def inc16(val): 149 | val += 1 150 | if val > 0xFFFF: 151 | val = 0x0 152 | return val 153 | 154 | def dec16(val): 155 | val -= 1 156 | if val < 0: 157 | val = 0xFFFF 158 | return val 159 | 160 | def inc8(val): 161 | val += 1 162 | if val > 0xFF: 163 | val = 0x0 164 | return val 165 | 166 | def dec8(val): 167 | val -= 1 168 | if val < 0: 169 | val = 0xFF 170 | return val 171 | 172 | def parity(n): 173 | p=0 174 | for i in range(0,8): 175 | p+=(n >> i) & 0x01 176 | return not (p % 2) 177 | 178 | def a_and_n(registers, n): 179 | registers.A = registers.A & n 180 | registers.condition.H = 1 181 | registers.condition.N = 0 182 | registers.condition.PV = parity(registers.A) 183 | registers.condition.C = 0 184 | registers.condition.Z = (registers.A==0) 185 | registers.condition.S = (registers.A>>7) 186 | set_f5_f3_from_a(registers) 187 | 188 | 189 | def a_or_n(registers, n): 190 | registers.A = registers.A | n 191 | registers.condition.H = 0 192 | registers.condition.N = 0 193 | registers.condition.PV = parity(registers.A) 194 | registers.condition.C = 0 195 | registers.condition.Z = (registers.A==0) 196 | registers.condition.S = (registers.A>>7) 197 | set_f5_f3_from_a(registers) 198 | 199 | def a_xor_n(registers, n): 200 | registers.A = registers.A ^ n 201 | registers.condition.H = 0 202 | registers.condition.N = 0 203 | registers.condition.PV = parity(registers.A) 204 | registers.condition.C = 0 205 | registers.condition.Z = (registers.A==0) 206 | registers.condition.S = (registers.A>>7) 207 | set_f5_f3_from_a(registers) 208 | 209 | def rotate_left_carry(registers, n): 210 | c = n >> 7 211 | v = (n << 1 | c) & 0xFF 212 | registers.condition.S = v >> 7 213 | registers.condition.Z = (v == 0) 214 | registers.condition.H = 0 215 | registers.condition.N = 0 216 | registers.condition.PV = parity(v) 217 | registers.condition.C = c 218 | return v 219 | 220 | 221 | def rotate_left(registers, n): 222 | c = n >> 7 223 | v = (n << 1 | registers.condition.C) & 0xFF 224 | registers.condition.S = v >> 7 225 | registers.condition.Z = (v == 0) 226 | registers.condition.H = 0 227 | registers.condition.N = 0 228 | registers.condition.PV = parity(v) 229 | registers.condition.C = c 230 | return v 231 | 232 | 233 | 234 | 235 | def rotate_right_carry(registers, n): 236 | c = n & 0x01 237 | v = n >> 1 | (c << 7) 238 | registers.condition.S = v >> 7 239 | registers.condition.Z = (v == 0) 240 | registers.condition.H = 0 241 | registers.condition.N = 0 242 | registers.condition.PV = parity(v) 243 | registers.condition.C = c 244 | return v 245 | 246 | 247 | def rotate_right(registers, n): 248 | c = n & 0x01 249 | v = n >> 1 | (registers.condition.C << 7) 250 | registers.condition.S = v >> 7 251 | registers.condition.Z = (v == 0) 252 | registers.condition.H = 0 253 | registers.condition.N = 0 254 | registers.condition.PV = parity(v) 255 | registers.condition.C = c 256 | return v 257 | 258 | 259 | def shift_left(registers, n): 260 | c = n >> 7 261 | v = (n << 1 ) & 0xFF 262 | registers.condition.S = v >> 7 263 | registers.condition.Z = (v == 0) 264 | registers.condition.H = 0 265 | registers.condition.N = 0 266 | registers.condition.PV = parity(v) 267 | registers.condition.C = c 268 | return v 269 | 270 | 271 | def shift_left_logical(registers, n): 272 | c = n >> 7 273 | v = ((n << 1 ) & 0xFF) | 0x01 274 | registers.condition.S = v >> 7 275 | registers.condition.Z = (v == 0) 276 | registers.condition.H = 0 277 | registers.condition.N = 0 278 | registers.condition.PV = parity(v) 279 | registers.condition.C = c 280 | return v 281 | 282 | 283 | def shift_right(registers, n): 284 | c = n & 0x01 285 | msb = n >> 7 286 | v = n >> 1 | (msb << 7) 287 | registers.condition.S = v >> 7 288 | registers.condition.Z = (v == 0) 289 | registers.condition.H = 0 290 | registers.condition.N = 0 291 | registers.condition.PV = parity(v) 292 | registers.condition.C = c 293 | return v 294 | 295 | 296 | def shift_right_logical(registers, n): 297 | c = n & 0x01 298 | v = n >> 1 299 | registers.condition.S = 0 300 | registers.condition.Z = (v == 0) 301 | registers.condition.H = 0 302 | registers.condition.N = 0 303 | registers.condition.PV = parity(v) 304 | registers.condition.C = c 305 | return v 306 | 307 | 308 | def offset_pc(registers, jump): 309 | registers.PC += get_8bit_twos_comp(jump) 310 | if registers.PC > 0xFFFF: 311 | registers.PC -= 0xFFFF - 1 312 | if registers.PC < 0: 313 | registers.PC += 0xFFFF + 1 314 | 315 | def set_f5_f3(registers, v): 316 | registers.condition.F5 = v & 0x20 317 | registers.condition.F3 = v & 0x08 318 | 319 | def set_f5_f3_from_a(registers): 320 | set_f5_f3(registers, registers.A) 321 | -------------------------------------------------------------------------------- /src/z80sbc.py: -------------------------------------------------------------------------------- 1 | from z80 import util, io, gui, registers, instructions 2 | 3 | import copy 4 | 5 | from time import sleep, time 6 | import sys 7 | from PySide2.QtCore import * 8 | from PySide2.QtGui import * 9 | from PySide2.QtWidgets import * 10 | 11 | import threading 12 | 13 | #logging.basicConfig(level=logging.INFO) 14 | 15 | class Z80SBC(io.Interruptable): 16 | def __init__(self): 17 | self.registers = registers.Registers() 18 | self.instructions = instructions.InstructionSet(self.registers) 19 | self._memory = bytearray(64*1024) 20 | self._read_rom("../roms/ROM.HEX") 21 | self._iomap = io.IOMap() 22 | self._console = io.Console(self) 23 | self._reg_gui = gui.RegistersGUI(self.registers) 24 | self._mem_view = gui.MemoryView(self._memory, self.registers) 25 | 26 | self._iomap.addDevice(self._console) 27 | self._console.show() 28 | self._reg_gui.show() 29 | self._mem_view.show() 30 | 31 | self._interrupted = False 32 | 33 | def interrupt(self): 34 | self._interrupted = True 35 | 36 | def _read_rom(self, romfile): 37 | with open(romfile, "r") as f: 38 | while True: 39 | line = f.readline() 40 | if line[0] != ":": 41 | raise Exception("Bad start code in hex file.") 42 | count = int(line[1:3], 16)#.decode("hex") 43 | address = int(line[3:7], 16) #.decode("hex") 44 | if address + count > len(self._memory): 45 | raise Exception("Trying to create M2764 ROM with too large a ROM file") 46 | rtype = line[7:9] 47 | pos = 9 48 | if rtype == "01": 49 | break 50 | for b in range(count): 51 | byte = int(line[pos+(2*b):pos+(2*b)+2], 16) #. decode("hex") 52 | self._memory[address+b] = byte 53 | 54 | def step_instruction(self): 55 | ins, args = False, [] 56 | pc = self.registers.PC 57 | 58 | if self._interrupted and self.registers.IFF: 59 | self.registers.IFF = False 60 | self._interrupted = False 61 | if self.registers.IM == 1: 62 | print ("!!! Interrupt !!!") 63 | ins, args = self.instructions << 0xCD 64 | ins, args = self.instructions << 0x38 65 | ins, args = self.instructions << 0x00 66 | self.registers.IFF = False 67 | else: 68 | while not ins: 69 | ins, args = self.instructions << self._memory[self.registers.PC] 70 | self.registers.PC = util.inc16(self.registers.PC) 71 | #print( "{0:X} : {1} ".format(pc, ins.assembler(args))) 72 | 73 | rd = ins.get_read_list(args) 74 | data = [0] * len(rd) 75 | for n, i in enumerate(rd): 76 | if i < 0x10000: 77 | data[n] = self._memory[i] 78 | else: 79 | address = i & 0xFF 80 | data[n] = self._iomap.address[address].read(address) 81 | wrt = ins.execute(data, args) 82 | for i in wrt: 83 | 84 | if i[0] > 0x10000: 85 | address = i[0] & 0xFF 86 | #iomap.address[address].write.emit(address, i[1]) 87 | self._iomap.address[address].write(address, i[1]) 88 | #print (chr(i[1])) 89 | else: 90 | self._memory[i[0]] = i[1] 91 | 92 | return ins, args 93 | 94 | 95 | if __name__ == '__main__': 96 | ''' Main Program ''' 97 | qt_app = QApplication(sys.argv) 98 | 99 | mach = Z80SBC() 100 | def worker(): 101 | t = time() 102 | 103 | while True: 104 | # t = time() 105 | ins, args = mach.step_instruction() 106 | print (ins.assembler(args)) 107 | sleep(0.00000001) 108 | # print (time() - t) / ins.tstates 109 | 110 | # mach._mem_view.update() 111 | # mach._reg_gui.update() 112 | 113 | 114 | 115 | thread = threading.Thread(target=worker) 116 | thread.setDaemon(True) 117 | thread.start() 118 | 119 | qt_app.exec_() 120 | --------------------------------------------------------------------------------