├── FullyConnectedSNN ├── readmeImages │ ├── readmeImages │ ├── trainingProgress.jpg │ └── fullyConnectedParallel.png ├── vsim.wlf ├── src-verilog │ ├── nn │ │ ├── NN_GRADCALC.v │ │ ├── NN_ReLU.v │ │ ├── NN_InputWeight_POLAR.v │ │ ├── NN_ZOFFSET.v │ │ ├── NN_DNODE.v │ │ ├── NN_BGPRIME.v │ │ ├── NN_DELTABP_POLAR.v │ │ ├── NN_BGCluster.v │ │ ├── BURST.v │ │ ├── NN_NODE_BGPOLAR.v │ │ └── NN_SMOOTHGRAD_POLAR.v │ └── stochastic │ │ ├── MPX.v │ │ ├── SS_RERANDOMIZER.v │ │ ├── DFFN.v │ │ ├── MUX_ADD.v │ │ ├── LFSR_LIMIT16.v │ │ ├── M_XOR.v │ │ ├── DEC2STCH.v │ │ ├── M_AND.v │ │ ├── M_OR.v │ │ ├── SS_MOVAVG.v │ │ ├── M_SIDEADD.v │ │ ├── LFSR16.v │ │ ├── M_OR_CARRY.v │ │ ├── M_MUX_ADD.v │ │ ├── cascLFSR.v │ │ ├── LFSR16_FullTap.v │ │ ├── cascLFSR_16Tap.v │ │ ├── MEAN.v │ │ ├── SS_ADDSUB2.v │ │ ├── SS_ADDSUB.v │ │ ├── ME_LFSR16.v │ │ ├── SS_ADDSUB2_POS.v │ │ └── SS_ADDSUB_CARRY_N.v ├── NN.do ├── evaluate.do ├── Readme.md ├── Decimal_IO_Declarations.v ├── TRAINING_portDefinitions.v ├── COSTMOD.v ├── FULLCONNBLOCK_L3.v ├── SEED_portDefinitions.v ├── FULLCONNBLOCKBP_L2.v ├── FULLCONNBLOCK_L2.v ├── DecimalParam_Declarations.v ├── RN_SEED_Declarations.v ├── FWDPROP.v ├── DECC.v ├── RNE_portDefinitions.v ├── FULLCONNBLOCK_L1.v ├── FULLCONNBLOCKBP_L1.v ├── PARAMS_portDefinitions.v ├── RNE.v └── BCKDPROP.v └── README.md /FullyConnectedSNN/readmeImages/readmeImages: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /FullyConnectedSNN/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cceroici/Stochastic-Neural-Network/HEAD/FullyConnectedSNN/vsim.wlf -------------------------------------------------------------------------------- /FullyConnectedSNN/readmeImages/trainingProgress.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cceroici/Stochastic-Neural-Network/HEAD/FullyConnectedSNN/readmeImages/trainingProgress.jpg -------------------------------------------------------------------------------- /FullyConnectedSNN/readmeImages/fullyConnectedParallel.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cceroici/Stochastic-Neural-Network/HEAD/FullyConnectedSNN/readmeImages/fullyConnectedParallel.png -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_GRADCALC.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module NN_GRADCALC(delta,a,dalpha); 5 | 6 | input delta,a; 7 | 8 | output dalpha; 9 | 10 | and a0(dalpha,delta,a); 11 | 12 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_ReLU.v: -------------------------------------------------------------------------------- 1 | 2 | module NN_ReLU(z, SIGN_z, a, CLK, INIT); 3 | 4 | input CLK, INIT; 5 | input z, SIGN_z; 6 | 7 | output a; 8 | 9 | assign a = (SIGN_z) ? 1'b0 : z; 10 | 11 | 12 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/NN.do: -------------------------------------------------------------------------------- 1 | vlog TOPsim.v RNE.v SEED.v STOCH.v BCKDPROP.v FWDPROP.v COSTMOD.v DECC.v TRAINING.v NETPAR_GRADIENT.v PARAMS_sim.v FULLCONNBLOCK_L3.v FULLCONNBLOCK_L2.v FULLCONNBLOCK_L1.v FULLCONNBLOCKBP_L2.v FULLCONNBLOCKBP_L1.v -y src-verilog/nn/ +libext+.v -y src-verilog/stochastic/ +libext+.v 2 | vsim TOP -novopt 3 | vsim TOP -novopt 4 | 5 | do wave_NNGeneric.do 6 | 7 | run 10ms -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_InputWeight_POLAR.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module NN_InputWeight_POLAR(a,alpha,SIGN_alpha,zp_pos,zp_neg); 5 | 6 | 7 | input a,alpha,SIGN_alpha; 8 | 9 | output zp_pos,zp_neg; 10 | 11 | wire zp; 12 | 13 | assign zp = aα 14 | 15 | assign zp_pos = (SIGN_alpha) ? 1'b0 : zp; 16 | 17 | assign zp_neg = (SIGN_alpha) ? zp : 1'b0; 18 | 19 | 20 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/evaluate.do: -------------------------------------------------------------------------------- 1 | force -freeze sim:/TOP/PARAMS0/TrainingActive 0 0 2 | force -freeze sim:/TOP/TRAINING_SET 0 0 3 | run 4ms 4 | 5 | force -freeze sim:/TOP/TRAINING_SET 1 0 6 | run 4ms 7 | 8 | force -freeze sim:/TOP/TRAINING_SET 10 0 9 | run 4ms 10 | 11 | force -freeze sim:/TOP/TRAINING_SET 11 0 12 | run 4ms 13 | 14 | force -freeze sim:/TOP/TRAINING_SET 100 0 15 | run 4ms 16 | 17 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/MPX.v: -------------------------------------------------------------------------------- 1 | // N bit decimal multiplexor 2 | 3 | module MPX(EN,SEL,D,Q); 4 | // EN --> Enable 5 | // SEL --> Nsel-bit address for output selection 6 | // D --> input N-bit vector 7 | // Q --> selected output 8 | parameter N = 2; // number of inputs 9 | parameter Nsel = 8; // number of selection bits 10 | input EN; 11 | input [Nsel-1:0] SEL; 12 | input [N-1:0] D; 13 | 14 | output Q; 15 | 16 | assign Q = (EN) ? D[SEL] : 1'b0; 17 | 18 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/SS_RERANDOMIZER.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // Chris Ceroici 5/2/2017 4 | 5 | // Use a shift register to rerandomize a single signal in time 6 | 7 | module SS_RERANDOMIZER(CLK,INIT,IN,OUT); 8 | 9 | parameter N = 3; // Buffer length 10 | 11 | input CLK, INIT; 12 | 13 | input IN; 14 | 15 | output reg [N-1:0] OUT = 1'b0; 16 | 17 | always @(posedge CLK or posedge INIT) begin 18 | 19 | if (INIT) OUT <= 1'b0; 20 | else OUT <= {OUT[N-2:0],IN}; 21 | 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_ZOFFSET.v: -------------------------------------------------------------------------------- 1 | 2 | // Chris Ceroici 5/1/2017 3 | // Apply offset to z prior to burst gate 4 | 5 | 6 | module NN_ZOFFSET(CLK,INIT,z,SIGN_z,d,zd); 7 | 8 | input CLK,INIT; 9 | 10 | input z, SIGN_z, d; 11 | 12 | output zd; 13 | 14 | 15 | //LFSR16 LFSR0(.TRIG(CLK),.RESET(INIT),.OUT1(R1),.OUT2(R2),.SEED(16'd13441)); 16 | 17 | //DEC2STCH DS0(.CLK(CLK),.INIT(INIT),.D(8'd128),.LFSR(R1),.S(d)); 18 | 19 | SS_ADDSUB2_POS ADDSUB0(.CLK(CLK), .INIT(INIT), .IN({z,d}), .SIGN({SIGN_z,1'b0}), .OUT(zd)); 20 | 21 | 22 | 23 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/DFFN.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // July 14 2013 3 | 4 | // D Flip Flop 5 | /* 6 | |------------| 7 | | Q |------> 8 | ---->| D | 9 | | CLK ~Q |------> 10 | |-----^-----| 11 | | 12 | */ 13 | module DFFN(CLK,D,Q); 14 | 15 | parameter N = 1; 16 | 17 | input [N-1:0] D; 18 | input CLK; 19 | output [N-1:0] Q; 20 | 21 | reg [N-1:0] hold=1'b0; 22 | reg [N-1:0] Dtemp=1'b0; 23 | 24 | assign Q = Dtemp; 25 | 26 | always @(posedge CLK) begin 27 | //hold <= D; 28 | //Dtemp <= #0 hold; 29 | Dtemp <= D; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/MUX_ADD.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 10, 2013 3 | // 4 | // MUX add gate 5 | 6 | module MUX_ADD(CLK,EN,IN,OUT); 7 | 8 | input CLK; 9 | input [1:0] IN; 10 | input EN; 11 | 12 | output OUT; 13 | 14 | wire OUT_temp; 15 | 16 | wire sel, sel_new; 17 | wire cond; 18 | 19 | M_XOR #(.N(3)) XOR_cond(.EN(EN),.IN({IN,sel}),.OUT(sel_new)); 20 | 21 | DFFN DFFN_hold(.CLK(CLK),.D(sel_new),.Q(sel)); 22 | defparam DFFN_hold.N = 1; 23 | 24 | MPX MPX_single(.EN(EN),.SEL(sel),.D(IN),.Q(OUT_temp)); 25 | defparam MPX_single.N = 2; 26 | defparam MPX_single.Nsel = 1; 27 | 28 | assign OUT = (EN) ? OUT_temp : 1'b0; 29 | 30 | 31 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/LFSR_LIMIT16.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // Feb 2 2016 3 | // 4 | // 16 bit output-limited LFSR 5 | // Primitive Polynomial: 1+x2+x3+x5+x16 6 | // 7 | module LFSR_LIMIT16( 8 | TRIG,RESET, 9 | LIMIT, 10 | OUT1,OUT2, 11 | SEED 12 | ); 13 | 14 | input TRIG, RESET; 15 | input [15:0] SEED; 16 | input [7:0] LIMIT; 17 | 18 | output [7:0] OUT1, OUT2; 19 | 20 | wire [7:0] OUT1_full, OUT2_full; 21 | wire [15:0] OUT1_scaled, OUT2_scaled; 22 | 23 | 24 | LFSR16 LFSR_base(.TRIG(TRIG),.RESET(RESET),.OUT1(OUT1_full),.OUT2(OUT2_full),.SEED(SEED)); 25 | 26 | assign OUT1_scaled = OUT1_full * LIMIT; 27 | assign OUT2_scaled = OUT2_full * LIMIT; 28 | 29 | assign OUT1 = OUT1_scaled[15:8]; 30 | assign OUT2 = OUT2_scaled[15:8]; 31 | 32 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/M_XOR.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 10, 2013 3 | // 4 | // Cascading xor gates 5 | 6 | module M_XOR #(parameter N = 3) (EN,IN,OUT); 7 | 8 | input [N-1:0] IN; 9 | input EN; 10 | 11 | output OUT; 12 | 13 | wire OUT_temp; 14 | wire [N-3:0] Temp; 15 | 16 | xor Ustart (Temp[0],IN[0],IN[1]); // generate cascading XOR gates 17 | genvar n; 18 | generate 19 | case (N) 20 | 1: begin 21 | assign OUT_temp = IN[0]; 22 | end 23 | 2: begin 24 | xor U_single(OUT_temp,IN[0],IN[1]); 25 | end 26 | default: begin 27 | assign OUT_temp = Temp[N-3]|IN[N-1]; 28 | for (n=0; n<(N-3);n=n+1) begin : COR1 29 | xor U (Temp[n+1],Temp[n],IN[n+2]); 30 | end 31 | end 32 | endcase 33 | endgenerate 34 | 35 | 36 | assign OUT = (EN) ? OUT_temp : 1'b0; 37 | 38 | 39 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/DEC2STCH.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 12 2013 3 | // 4 | // Converts a decimal probability into an 8-bit stochastic stream 5 | // Input fraction must be scaled to x/256 6 | 7 | module DEC2STCH(CLK,D,LFSR,S,INIT); 8 | 9 | parameter ND = 8; // precision of decimal fraction 10 | parameter LFSR_S = ND; // LFSR size 11 | 12 | input [ND-1:0] D; // input probability scaled to x/256 13 | input [LFSR_S-1:0] LFSR; // LFSR comparator value 14 | input CLK,INIT; 15 | 16 | output S; // stochastic bit 17 | 18 | //reg Comp = 1'b0; // comparator output 19 | 20 | //assign S = Comp; 21 | 22 | //always @(posedge CLK) begin 23 | // #2 Comp <= (D>LFSR) ? 1'b1 : 1'b0; 24 | //end 25 | 26 | wire [ND-1:0] maxOut; 27 | assign maxOut = 1'b0-1'b1; 28 | 29 | assign S = (D>LFSR)|(D==maxOut); 30 | 31 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/M_AND.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 10, 2013 3 | // 4 | // Cascading and gates 5 | 6 | module M_AND(EN,IN,OUT); 7 | 8 | parameter N = 3; // number of inputs 9 | 10 | input [N-1:0] IN; 11 | input EN; 12 | 13 | output OUT; 14 | 15 | wire OUT_temp; 16 | wire [N-3:0] Temp; 17 | 18 | and Ustart (Temp[0],IN[0],IN[1]); // generate cascading XOR gates 19 | genvar n; 20 | generate 21 | case (N) 22 | 1: begin 23 | assign OUT_temp = IN[0]; 24 | end 25 | 2: begin 26 | and U_single(OUT_temp,IN[0],IN[1]); 27 | end 28 | default: begin 29 | assign OUT_temp = Temp[N-3]&IN[N-1]; 30 | for (n=0; n<(N-3);n=n+1) begin : COR1 31 | and U (Temp[n+1],Temp[n],IN[n+2]); 32 | end 33 | end 34 | endcase 35 | endgenerate 36 | 37 | 38 | assign OUT = (EN) ? OUT_temp : 1'b0; 39 | 40 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/M_OR.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 10, 2013 3 | // 4 | // Cascading or gates 5 | 6 | module M_OR(EN,IN,OUT); 7 | 8 | parameter N = 3; // number of inputs 9 | 10 | input [N-1:0] IN; 11 | input EN; 12 | 13 | output OUT; 14 | 15 | wire OUT_temp; 16 | wire [N-3:0] Temp; 17 | 18 | or Ustart (Temp[0],IN[0],IN[1]); // generate cascading XOR gates 19 | genvar n; 20 | generate 21 | case (N) 22 | 1: begin 23 | assign OUT_temp = IN[0]; 24 | end 25 | 2: begin 26 | or U_single(OUT_temp,IN[0],IN[1]); 27 | end 28 | default: begin 29 | assign OUT_temp = Temp[N-3]|IN[N-1]; 30 | for (n=0; n<(N-3);n=n+1) begin : COR1 31 | or U (Temp[n+1],Temp[n],IN[n+2]); 32 | end 33 | end 34 | endcase 35 | endgenerate 36 | 37 | 38 | assign OUT = (EN) ? OUT_temp : 1'b0; 39 | 40 | 41 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/Readme.md: -------------------------------------------------------------------------------- 1 | This project demonstrates a network with 5 inputs, two fully connected hidden layers with 25 and 8 nodes and 5 output nodes. 2 | 3 | ![Block diagram of system](https://github.com/cceroici/Stochastic-Neural-Network/blob/master/FullyConnectedSNN/readmeImages/fullyConnectedParallel.png?raw=true) 4 | 5 | To run the project in ModelSim, navigate to the .../FullyConnectedSNN/ directory and run the compilation + simulation macro file with: "do nn.do" 6 | 7 | The waveform window will show the training progress including the netowork parameters and stochastic error: 8 | 9 | ![Image of Training Window](https://github.com/cceroici/Stochastic-Neural-Network/blob/master/FullyConnectedSNN/readmeImages/trainingProgress.jpg?raw=true) 10 | 11 | 12 | The project can also be compiled for an FPGA with some modification of the top-level TOPsim.v file. 13 | 14 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/SS_MOVAVG.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // Moving average of stochastic stream 4 | 5 | module SS_MOVAVG(IN,AVG,CLK,INIT); 6 | 7 | 8 | parameter W = 1000; 9 | parameter N = 16; 10 | parameter F_sampling = 5; 11 | 12 | input IN; 13 | input CLK, INIT; 14 | 15 | output [N-1:0] AVG; 16 | 17 | reg [W-1:0] BUFFER = 1'b0 - 1'b1; 18 | reg [7:0] sampleCOUNTER = 8'd0; 19 | 20 | always @(posedge CLK) begin 21 | if (sampleCOUNTERn+1; 45 | end 46 | endgenerate 47 | 48 | 49 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/M_MUX_ADD.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 10, 2013 3 | // 4 | // Cascading MUX add gates 5 | 6 | module M_MUX_ADD #(parameter N=3) (EN,CLK,IN,OUT); 7 | 8 | input CLK; 9 | input [N-1:0] IN; 10 | input EN; 11 | 12 | output OUT; 13 | 14 | wire OUT_temp; 15 | wire [N-3:0] Temp; 16 | 17 | or Ustart (Temp[0],IN[0],IN[1]); // generate cascading XOR gates 18 | genvar n; 19 | generate 20 | case (N) 21 | 1: begin 22 | assign OUT_temp = IN[0]; 23 | end 24 | 2: begin 25 | MUX_ADD MUX_ADD_SINGLE(.CLK(CLK),.EN(EN),.IN(IN),.OUT(OUT_temp)); 26 | end 27 | default: begin 28 | MUX_ADD MUX_ADD_end(.CLK(CLK),.EN(EN),.IN({Temp[N-3],IN[N-1]}),.OUT(OUT_temp)); 29 | for (n=0; n<(N-3);n=n+1) begin : COR1 30 | MUX_ADD U (.CLK(CLK),.EN(EN),.IN({Temp[n],IN[n+2]}),.OUT(Temp[n+1])); 31 | end 32 | /* 33 | assign OUT_temp = Temp[N-3]|IN[N-1]; 34 | for (n=0; n<(N-3);n=n+1) begin : COR1 35 | or U (Temp[n+1],Temp[n],IN[n+2]); 36 | end 37 | */ 38 | end 39 | endcase 40 | endgenerate 41 | 42 | 43 | assign OUT = (EN) ? OUT_temp : 1'b0; 44 | 45 | 46 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/Decimal_IO_Declarations.v: -------------------------------------------------------------------------------- 1 | wire [DP_in - 1:0] aD_L0_0, aD_L0_1, aD_L0_2, aD_L0_3, aD_L0_4; 2 | wire [DP_in-1:0] aD_L0_0_netPar0, aD_L0_0_netPar1, aD_L0_0_netPar2; 3 | wire [DP_in-1:0] aD_L0_1_netPar0, aD_L0_1_netPar1, aD_L0_1_netPar2; 4 | wire [DP_in-1:0] aD_L0_2_netPar0, aD_L0_2_netPar1, aD_L0_2_netPar2; 5 | wire [DP_in-1:0] aD_L0_3_netPar0, aD_L0_3_netPar1, aD_L0_3_netPar2; 6 | wire [DP_in-1:0] aD_L0_4_netPar0, aD_L0_4_netPar1, aD_L0_4_netPar2; 7 | wire [DP_out - 1:0] aD_L1_0, aD_L1_1, aD_L1_2, aD_L1_3, aD_L1_4, aD_L1_5, aD_L1_6, aD_L1_7, aD_L1_8, aD_L1_9, aD_L1_10, aD_L1_11, aD_L1_12, aD_L1_13, aD_L1_14, aD_L1_15, aD_L1_16, aD_L1_17, aD_L1_18, aD_L1_19, aD_L1_20, aD_L1_21, aD_L1_22, aD_L1_23, aD_L1_24; 8 | wire [DP_out - 1:0] aD_L2_0, aD_L2_1, aD_L2_2, aD_L2_3, aD_L2_4, aD_L2_5, aD_L2_6, aD_L2_7; 9 | wire [DP_out - 1:0] aD_L3_0, aD_L3_1, aD_L3_2, aD_L3_3, aD_L3_4; 10 | wire [DP_out - 1:0] YD0, YD1, YD2, YD3, YD4; 11 | wire [DP_out - 1:0] YD0_netPar0, YD0_netPar1, YD0_netPar2; 12 | wire [DP_out - 1:0] YD1_netPar0, YD1_netPar1, YD1_netPar2; 13 | wire [DP_out - 1:0] YD2_netPar0, YD2_netPar1, YD2_netPar2; 14 | wire [DP_out - 1:0] YD3_netPar0, YD3_netPar1, YD3_netPar2; 15 | wire [DP_out - 1:0] YD4_netPar0, YD4_netPar1, YD4_netPar2; 16 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/cascLFSR.v: -------------------------------------------------------------------------------- 1 | // Cascade LFSR group module 2 | // bottom level LFSR seeds are stored external. Top level LFSR seeds are generated by bottom level. 3 | 4 | module cascLFSR(TRIG,RESET,OUT1,OUT2,SEED,SDcount); 5 | 6 | input TRIG,RESET; 7 | input [15:0] SEED; // bottom level LFSR seed 8 | input [31:0] SDcount; 9 | 10 | output [7:0] OUT1,OUT2; 11 | 12 | wire [15:0] SD_TOP; // top level LFSR seed 13 | 14 | reg SDcountTOP_Flag = 1'b0; 15 | reg SDcountBOT_Flag = 1'b0; 16 | reg TOP_Flag, BOT_Flag = 1'b1; 17 | 18 | always @(posedge TRIG) begin 19 | if (TOP_Flag&SDcount[15]) begin 20 | TOP_Flag = 1'b0; 21 | SDcountTOP_Flag = 1'b1; 22 | end 23 | else if (SDcount[15]) begin 24 | SDcountTOP_Flag = 1'b0; 25 | end 26 | else TOP_Flag = 1'b1; 27 | 28 | if (BOT_Flag&SDcount[31]) begin 29 | BOT_Flag = 1'b0; 30 | SDcountBOT_Flag = 1'b1; 31 | end 32 | else if (SDcount[31]) begin 33 | SDcountBOT_Flag = 1'b0; 34 | end 35 | else BOT_Flag = 1'b1; 36 | end 37 | 38 | LFSR16 LFSRtop(.TRIG(TRIG),.RESET(SDcountTOP_Flag||RESET),.OUT1(OUT1),.OUT2(OUT2),.SEED(SD_TOP)); 39 | 40 | LFSR16 LFSRsub(.TRIG(SDcount[15]),.RESET(SDcountBOT_Flag||RESET),.OUT1(SD_TOP[7:0]),.OUT2(SD_TOP[15:8]),.SEED(SEED)); 41 | 42 | 43 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | # Hardware-Based Stochastic Neural Network Framework 3 | Fully Hardware-Based Stochastic Neural Network 4 | 5 | This project demonstrates fully hardware-based neural networks which perform calculations entirely through stochastic signal processing. The code in this project is mainly written in Verilog HDL with tcl macros to be used for ModelSim simulations. However, the code can be easily adapted for FPGA implementations. 6 | 7 | These fully-stochastic networks operate with the principle of simultaneous forward- and back-propagation, similar to analog or neuromorphic networks. 8 | 9 | **Note: For the high-level code used for generating the necessary HDL for an arbitrary dense/CNN/RNN/GAN model, see [this repository](https://github.com/cceroici/Stochastic-FPGA-Neural-Network-HDL-Generator)** 10 | 11 | **Stochastic Fully-Connected Network With Parallel Training** 12 | 13 | This project demonstrates a fully-connected network operating on a sample set of training inputs. The network consists of several parallel networks performing training on multiple training inputs and optimizing a single set of parameters. 14 | 15 | **Stochastic Convolutional Network** 16 | 17 | Coming soon. 18 | 19 | **Stochastic Recurrent Network** 20 | 21 | Coming soon. 22 | 23 | **Stochastic Adverserial Generative Network** 24 | 25 | Coming soon. 26 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_BGPRIME.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Burst Gate Derivative 4 | 5 | module NN_BGPRIME(z,zp,CLK,INIT); 6 | 7 | parameter MEMSIZE = 6; 8 | 9 | input z; 10 | input CLK, INIT; 11 | 12 | output wire zp; 13 | 14 | reg zp_temp = 1'b0; 15 | reg [MEMSIZE-1:0] MEM = 1'b0; 16 | 17 | wire [4-1:0] MEM_SUM; 18 | //wire n_ss; 19 | //wire [7:0] R; 20 | 21 | M_SIDEADD SIDEADD0(.EN(1'b1),.IN(MEM),.OUT(MEM_SUM)); 22 | defparam SIDEADD0.N_inputs = MEMSIZE; 23 | defparam SIDEADD0.NB_out = 4; 24 | 25 | always @(posedge INIT or posedge CLK) begin 26 | 27 | if (INIT) begin 28 | zp_temp <= 1'b0; 29 | MEM <= 1'b0; 30 | end 31 | else if (MEM_SUM<8'd3) begin 32 | //zp_temp <= z&MEM[MEMSIZE-2]&MEM[MEMSIZE-3]; 33 | zp_temp <= 1'b0; 34 | MEM <= {MEM[MEMSIZE-2:0],z}; 35 | end 36 | else if (MEM_SUM>8'd5) begin 37 | //zp_temp <= z&(~MEM[MEMSIZE-2])&(~MEM[MEMSIZE-3]); 38 | zp_temp <= 1'b0; 39 | MEM <= {MEM[MEMSIZE-2:0],z}; 40 | end 41 | else begin // if (MEMSIZE==8'd4) begin 42 | zp_temp <= 1'b1; 43 | MEM <= {MEM[MEMSIZE-2:0],z}; 44 | end 45 | 46 | end 47 | 48 | //wire [7:0] junk0; 49 | 50 | //LFSR16 LFSR0(.TRIG(CLK),.RESET(INIT),.OUT1(junk0),.OUT2(R),.SEED(16'd9391)); 51 | 52 | //DEC2STCH DS0(.CLK(CLK),.D(n),.LFSR(R),.S(n_ss)); 53 | 54 | //JK_FF JK0(.J(zp_temp), .K(n_ss), .CLK(CLK), .Q(zp), .RESET(INIT)); 55 | 56 | assign zp = zp_temp; 57 | 58 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_DELTABP_POLAR.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // Chris Ceroici 4 | // Back Propogate Delta calculation 5 | 6 | 7 | module NN_DELTABP_POLAR(CLK,INIT,R_condition,delta,SIGN_delta,SIGN_alpha,alpha,delta_out,SIGN_out,z,zp); 8 | 9 | parameter N = 3; // Number of Nodes in next layer 10 | 11 | input CLK,INIT; 12 | input [N-1:0] delta, SIGN_delta, alpha, SIGN_alpha; 13 | input z,zp; 14 | input R_condition; 15 | 16 | output delta_out; 17 | output SIGN_out; 18 | 19 | wire [N-1:0] SIGN; 20 | 21 | wire delta_out_temp; 22 | 23 | wire zp; // z burst gate derivative w.r.t. input z 24 | 25 | assign SIGN = SIGN_delta^SIGN_alpha; 26 | 27 | /* 28 | SS_ADDSUB ADDSUB0(.CLK(CLK),.INIT(INIT),.IN(delta&alpha),.SIGN(SIGN),.R_condition(R_condition),.OUT(delta_out_temp),.SIGN_out(SIGN_out)); 29 | defparam ADDSUB0.N = N; 30 | defparam ADDSUB0.DIFFCOUNTER_SIZE = 1; 31 | defparam ADDSUB0.DIFFCOUNT_LOWERLIM = 0; 32 | */ 33 | 34 | /* 35 | SS_ADDSUB ADDSUB0(.CLK(CLK),.INIT(INIT),.IN(delta&alpha),.SIGN(SIGN),.R_condition(R_condition),.OUT(delta_out_temp),.SIGN_out(SIGN_out)); 36 | defparam ADDSUB0.N = N; 37 | defparam ADDSUB0.DIFFCOUNTER_SIZE = 1; 38 | */ 39 | 40 | SS_ADDSUB_CARRY_N #(.N(N), .N_CARRY(2), .DIFFCOUNTER_SIZE(1)) ADDSUB0(.CLK(CLK),.INIT(INIT),.IN(delta&alpha),.SIGN(SIGN),.R_condition(R_condition),.OUT(delta_out_temp),.SIGN_out(SIGN_out)); 41 | 42 | 43 | //NN_BGPRIME BGPRIME0(.z(z),.zp(zp),.CLK(CLK),.INIT(INIT)); 44 | 45 | assign delta_out = delta_out_temp&zp; 46 | //assign delta_out = delta_out_temp; 47 | 48 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_BGCluster.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Burst Gate Cluster 4 | 5 | module NN_BGCluster(IN,OUT,INIT_STATE,CLK,INIT); 6 | 7 | parameter MEMSIZE = 16; 8 | parameter Ngates = 3; 9 | 10 | input IN; 11 | input INIT_STATE; 12 | input CLK, INIT; 13 | 14 | output reg OUT = 1'b0; 15 | 16 | wire [Ngates-1:0] OUTburst; 17 | 18 | reg CLK0,CLK1,CLK2; 19 | reg [2:0] CLKcounter = 1'd0; 20 | 21 | 22 | BURST BURST0(.IN(IN),.OUT(OUTburst[0]),.INIT_STATE(INIT_STATE),.CLK(CLK0),.INIT(INIT)); 23 | defparam BURST0.MEMSIZE = MEMSIZE; 24 | BURST BURST1(.IN(IN),.OUT(OUTburst[1]),.INIT_STATE(INIT_STATE),.CLK(CLK1),.INIT(INIT)); 25 | defparam BURST1.MEMSIZE = MEMSIZE; 26 | BURST BURST2(.IN(IN),.OUT(OUTburst[2]),.INIT_STATE(INIT_STATE),.CLK(CLK2),.INIT(INIT)); 27 | defparam BURST2.MEMSIZE = MEMSIZE; 28 | 29 | always @(posedge CLK) begin 30 | if (CLKcounter > (Ngates-1)) CLKcounter <= 1'd0; 31 | else CLKcounter <= CLKcounter + 1'b1; 32 | 33 | if (CLKcounter == 2'd0) begin 34 | CLK0<=1'b1; 35 | CLK1<=1'b0; 36 | CLK2<=1'b0; 37 | end else if (CLKcounter == 2'd1) begin 38 | CLK0<=1'b0; 39 | CLK1<=1'b1; 40 | CLK2<=1'b0; 41 | end else if (CLKcounter == 2'd2) begin 42 | CLK0<=1'b0; 43 | CLK1<=1'b0; 44 | CLK2<=1'b1; 45 | end 46 | 47 | end 48 | 49 | always @(posedge CLK) begin 50 | if (INIT) OUT <= INIT_STATE; 51 | else if (OUTburst[0]&OUTburst[1]&OUTburst[2]) OUT <= 1'b1; 52 | else if (~OUTburst[0]&~OUTburst[1]&~OUTburst[2]) OUT <= 1'b0; 53 | else OUT <= OUT; 54 | end 55 | 56 | 57 | 58 | 59 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/LFSR16_FullTap.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 12 2013 3 | // 4 | // 16 bit LFSR 5 | // Primitive Polynomial: 1+x2+x3+x5+x16 6 | // 7 | module LFSR16_FullTap(TRIG,RESET,OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15,SEED); 8 | 9 | input TRIG, RESET; // TRIG: shift registers trigger 10 | input [15:0] SEED; 11 | 12 | output [7:0] OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15; 13 | 14 | reg [15:0] D = 16'd0 /* synthesis preserve */; 15 | wire [2:0] Q /* synthesis keep */; 16 | 17 | assign OUT0[7:0] = {D[7:0]}; 18 | assign OUT1[7:0] = {D[8:1]}; 19 | assign OUT2[7:0] = {D[9:2]}; 20 | assign OUT3[7:0] = {D[10:3]}; 21 | assign OUT4[7:0] = {D[11:4]}; 22 | assign OUT5[7:0] = {D[12:5]}; 23 | assign OUT6[7:0] = {D[13:6]}; 24 | assign OUT7[7:0] = {D[14:7]}; 25 | assign OUT8[7:0] = {D[15:8]}; 26 | assign OUT9[7:0] = {D[15:9],D[0]}; 27 | assign OUT10[7:0] = {D[15:10],D[1:0]}; 28 | assign OUT11[7:0] = {D[15:11],D[2:0]}; 29 | assign OUT12[7:0] = {D[15:12],D[3:0]}; 30 | assign OUT13[7:0] = {D[15:13],D[4:0]}; 31 | assign OUT14[7:0] = {D[15:14],D[5:0]}; 32 | assign OUT15[7:0] = {D[15],D[6:0]}; 33 | 34 | xor U1(Q[0],D[15],D[4]); 35 | xor U2(Q[1],Q[0],D[2]); 36 | xor U3(Q[2],Q[1],D[1]); 37 | 38 | //assign Q[0] = D[15]^D[4]; 39 | //assign Q[1] = D[2]^Q[0]; 40 | //assign Q[2] = D[1]&Q[1]; 41 | 42 | wire [15:0] Dtemp; 43 | 44 | /* 45 | always @(posedge TRIG) begin 46 | D[15:0] <= #3 {D[14:0],Q[2]}; 47 | end 48 | */ 49 | 50 | always @(posedge TRIG or posedge RESET) begin 51 | if (RESET) D <= SEED; 52 | else D[15:0] <= #3 {D[14:0],Q[2]}; 53 | end 54 | 55 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/cascLFSR_16Tap.v: -------------------------------------------------------------------------------- 1 | // Cascade LFSR group module 2 | // bottom level LFSR seeds are stored external. Top level LFSR seeds are generated by bottom level. 3 | 4 | module cascLFSR_16Tap(TRIG,RESET,OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15,SEED,SDcount); 5 | 6 | input TRIG,RESET; 7 | input [15:0] SEED; // bottom level LFSR seed 8 | input [31:0] SDcount; 9 | 10 | output [7:0] OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15; 11 | 12 | wire [15:0] SD_TOP; // top level LFSR seed 13 | 14 | reg SDcountTOP_Flag = 1'b0; 15 | reg SDcountBOT_Flag = 1'b0; 16 | reg TOP_Flag, BOT_Flag = 1'b1; 17 | 18 | always @(posedge TRIG) begin 19 | if (TOP_Flag&SDcount[15]) begin 20 | TOP_Flag = 1'b0; 21 | SDcountTOP_Flag = 1'b1; 22 | end 23 | else if (SDcount[15]) begin 24 | SDcountTOP_Flag = 1'b0; 25 | end 26 | else TOP_Flag = 1'b1; 27 | 28 | if (BOT_Flag&SDcount[31]) begin 29 | BOT_Flag = 1'b0; 30 | SDcountBOT_Flag = 1'b1; 31 | end 32 | else if (SDcount[31]) begin 33 | SDcountBOT_Flag = 1'b0; 34 | end 35 | else BOT_Flag = 1'b1; 36 | end 37 | 38 | LFSR16_FullTap LFSRtop( 39 | .TRIG(TRIG),.RESET(SDcountTOP_Flag||RESET), 40 | .OUT0(OUT0),.OUT1(OUT1),.OUT2(OUT2),.OUT3(OUT3),.OUT4(OUT4),.OUT5(OUT5),.OUT6(OUT6),.OUT7(OUT7),.OUT8(OUT8), 41 | .OUT9(OUT9),.OUT10(OUT10),.OUT11(OUT11),.OUT12(OUT12),.OUT13(OUT13),.OUT14(OUT14),.OUT15(OUT15), 42 | .SEED(SD_TOP) 43 | ); 44 | 45 | LFSR16 LFSRsub(.TRIG(SDcount[15]),.RESET(SDcountBOT_Flag||RESET),.OUT1(SD_TOP[7:0]),.OUT2(SD_TOP[15:8]),.SEED(SEED)); 46 | 47 | 48 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/BURST.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Burst Gate Operator 4 | 5 | module BURST(IN,OUT,INIT_STATE,CLK,INIT); 6 | 7 | parameter MEMSIZE = 6; 8 | 9 | input IN; 10 | input INIT_STATE; 11 | input CLK, INIT; 12 | 13 | output reg OUT; 14 | 15 | reg MODE = 1'b1; // output mode 16 | 17 | reg [MEMSIZE-1:0] MEM = 1'b0; 18 | 19 | wire MEMsig1,MEMsig0; 20 | 21 | M_AND AND0(.EN(1'b1),.IN(~MEM),.OUT(MEMsig0)); 22 | defparam AND0.N = MEMSIZE; 23 | //and u0(MEMsig0,~MEM[0],~MEM[1]); 24 | 25 | M_AND AND1(.EN(1'b1),.IN(MEM),.OUT(MEMsig1)); 26 | defparam AND1.N = MEMSIZE; 27 | 28 | always @(posedge INIT or posedge CLK) begin 29 | if (INIT) begin 30 | OUT <= INIT_STATE; 31 | MODE <= INIT_STATE; 32 | MEM <= INIT_STATE; 33 | end 34 | else if ((MODE==1'b1)&(IN==1'b1)) begin // Mode 1: '1' input, no change 35 | OUT <= 1'b1; 36 | MODE <= MODE; 37 | MEM <= {MEM[MEMSIZE-2:0],IN}; 38 | end 39 | else if ((MODE==1'b0)&(IN==1'b0)) begin // Mode 0: '0' input, no change 40 | OUT <= 1'b0; 41 | MODE <= MODE; 42 | MEM <= {MEM[MEMSIZE-2:0],IN}; 43 | end 44 | else if ((MODE==1'b1)&(IN==1'b0)&(MEMsig0==1'b0)) begin // Mode 1: no mode switch 45 | OUT <= 1'b1; 46 | MODE <= MODE; 47 | MEM <= {MEM[MEMSIZE-2:0],IN}; 48 | end 49 | else if ((MODE==1'b0)&(IN==1'b1)&(MEMsig1==1'b0)) begin // Mode 0: no mode switch 50 | OUT <= 1'b0; 51 | MODE <= MODE; 52 | MEM <= {MEM[MEMSIZE-2:0],IN}; 53 | end 54 | else if ((MODE==1'b1)&(IN==1'b0)&(MEMsig0==1'b1)) begin // Mode 1 -> Mode 0 55 | OUT <= 1'b0; 56 | MODE <= 1'b0; 57 | MEM <= {MEM[MEMSIZE-2:0],IN}; 58 | end 59 | else if ((MODE==1'b0)&(IN==1'b1)&(MEMsig1==1'b1)) begin // Mode 0 -> Mode 1 60 | OUT <= 1'b1; 61 | MODE <= 1'b1; 62 | MEM <= {MEM[MEMSIZE-2:0],IN}; 63 | end 64 | 65 | 66 | end 67 | 68 | 69 | 70 | 71 | 72 | 73 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/TRAINING_portDefinitions.v: -------------------------------------------------------------------------------- 1 | .a_L1_netPar0(a_L1_netPar0), .a_L1_netPar1(a_L1_netPar1), .a_L1_netPar2(a_L1_netPar2), 2 | .a_L2_netPar0(a_L2_netPar0), .a_L2_netPar1(a_L2_netPar1), .a_L2_netPar2(a_L2_netPar2), 3 | .a_L3_netPar0(a_L3_netPar0), .a_L3_netPar1(a_L3_netPar1), .a_L3_netPar2(a_L3_netPar2), 4 | .aD_L0_0_netPar0(aD_L0_0_netPar0), .aD_L0_1_netPar0(aD_L0_1_netPar0), .aD_L0_2_netPar0(aD_L0_2_netPar0), .aD_L0_3_netPar0(aD_L0_3_netPar0), .aD_L0_4_netPar0(aD_L0_4_netPar0), 5 | .aD_L0_0_netPar1(aD_L0_0_netPar1), .aD_L0_1_netPar1(aD_L0_1_netPar1), .aD_L0_2_netPar1(aD_L0_2_netPar1), .aD_L0_3_netPar1(aD_L0_3_netPar1), .aD_L0_4_netPar1(aD_L0_4_netPar1), 6 | .aD_L0_0_netPar2(aD_L0_0_netPar2), .aD_L0_1_netPar2(aD_L0_1_netPar2), .aD_L0_2_netPar2(aD_L0_2_netPar2), .aD_L0_3_netPar2(aD_L0_3_netPar2), .aD_L0_4_netPar2(aD_L0_4_netPar2), 7 | .YD0_netPar0(YD0_netPar0), .YD1_netPar0(YD1_netPar0), .YD2_netPar0(YD2_netPar0), .YD3_netPar0(YD3_netPar0), .YD4_netPar0(YD4_netPar0), 8 | .YD0_netPar1(YD0_netPar1), .YD1_netPar1(YD1_netPar1), .YD2_netPar1(YD2_netPar1), .YD3_netPar1(YD3_netPar1), .YD4_netPar1(YD4_netPar1), 9 | .YD0_netPar2(YD0_netPar2), .YD1_netPar2(YD1_netPar2), .YD2_netPar2(YD2_netPar2), .YD3_netPar2(YD3_netPar2), .YD4_netPar2(YD4_netPar2), 10 | .a_MEM_ACTIVE_L1_netPar0(a_MEM_ACTIVE_L1_netPar0), .a_MEM_ACTIVE_L1_netPar1(a_MEM_ACTIVE_L1_netPar1), .a_MEM_ACTIVE_L1_netPar2(a_MEM_ACTIVE_L1_netPar2), 11 | .a_MEM_ACTIVE_L2_netPar0(a_MEM_ACTIVE_L2_netPar0), .a_MEM_ACTIVE_L2_netPar1(a_MEM_ACTIVE_L2_netPar1), .a_MEM_ACTIVE_L2_netPar2(a_MEM_ACTIVE_L2_netPar2), 12 | .a_MEM_ACTIVE_L3_netPar0(a_MEM_ACTIVE_L3_netPar0), .a_MEM_ACTIVE_L3_netPar1(a_MEM_ACTIVE_L3_netPar1), .a_MEM_ACTIVE_L3_netPar2(a_MEM_ACTIVE_L3_netPar2), 13 | 14 | .TRAINING_SET_netPar0(TRAINING_SET_netPar0), 15 | .TRAINING_SET_netPar1(TRAINING_SET_netPar1), 16 | .TRAINING_SET_netPar2(TRAINING_SET_netPar2), 17 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/MEAN.v: -------------------------------------------------------------------------------- 1 | // Calculate statistical mean of input stochastic sequence. Output N-bit mean at counter edge 2 | 3 | 4 | module MEAN(in,out,START,RESET,CLK,INIT,ENABLE,preRESET); 5 | 6 | parameter N = 8; // output mean precision 7 | parameter N_Count = 8; 8 | 9 | input CLK, INIT, ENABLE; 10 | input in; // input stochastic sequence 11 | input [N_Count-1:0] START; // output initialization 12 | input RESET,preRESET; // Store new value and reset SUM 13 | 14 | //output [N-1:0] outshift; // output (bit shifted) 15 | 16 | //output reg [N_Count-1:0] out = 1'd0; // output sum (latched) 17 | output reg [N_Count-1:0] out = 1'd0; // output sum (latched) 18 | 19 | reg [N_Count-1:0] SUM = 1'd0; // output sum 20 | //reg RESETflag = 1'b1 /* synthesis keep */; 21 | 22 | //wire [N_Count-1:0] SUM_wire; 23 | 24 | //assign out = SUM; 25 | //assign SUM_wire = SUM+in; 26 | 27 | //reg [N_Count-1:0] BACKUP_LATCH = 1'd0 /* synthesis noprune */; // possibly reuse reg out 28 | //wire GLITCH; 29 | //assign GLITCH = ((BACKUP_LATCH>(SUM+1'b1))&(~RESET)) ? 1'b1 : 1'b0 /* synthesis keep */; 30 | 31 | 32 | always @(posedge CLK or posedge RESET or posedge preRESET or posedge INIT) begin 33 | if (INIT) begin 34 | //out = {START,2'b00}; 35 | out <= START; 36 | //RESETflag <= 1'd0; 37 | end 38 | else if (RESET) begin 39 | //BACKUP_LATCH <=1'd0; 40 | //SUM <= 1'd0; 41 | SUM <= 5'd0; 42 | out <= out; 43 | end 44 | else if (preRESET) begin 45 | SUM <= SUM; 46 | out <= SUM; 47 | end 48 | else if (ENABLE) begin 49 | //BACKUP_LATCH <= SUM; 50 | //SUM <= SUM_wire; 51 | SUM<= SUM+in; 52 | out <= out; 53 | end else begin 54 | SUM<= SUM; 55 | end 56 | end 57 | 58 | /* always @(posedge CLK) begin 59 | 60 | case (in) 61 | 1'd0 : SUM = SUM; 62 | 1'd1 : SUM = SUM + 1'b1; 63 | default : 64 | endcase 65 | 66 | if (RESET) */ 67 | 68 | 69 | 70 | endmodule 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /FullyConnectedSNN/COSTMOD.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Cost function calculation 4 | 5 | module COSTMOD( 6 | Y, 7 | SIGN_L3, 8 | eps, 9 | a_out, 10 | R0, R1, R2, 11 | CLK, CLK_TRAINING_flag, INIT 12 | ); 13 | 14 | parameter DP_in = 8; 15 | parameter DP_out = 16; 16 | parameter SUPPRESS_TIME = 8; 17 | 18 | input wire CLK, CLK_TRAINING_flag, INIT; 19 | input wire [5-1:0] Y; 20 | input wire [5-1:0] a_out; 21 | input wire [7:0] R0, R1, R2; 22 | output wire [5-1:0] SIGN_L3; 23 | output wire [5-1:0] eps; 24 | 25 | wire [5-1:0] R_condition; 26 | wire [5 - 1:0] eps_temp; 27 | reg [8-1:0] SUPPRESS_COUNTER = 1'd0; 28 | 29 | // Cost Evaluation: 30 | 31 | SS_RERANDOMIZER RERANDOMIZER0(.CLK(CLK), .INIT(INIT), .IN(R0[0]), .OUT(R_condition)); 32 | defparam RERANDOMIZER0.N = 5; 33 | 34 | SS_ADDSUB2 ADDSUB0(.CLK(CLK),.INIT(INIT|CLK_TRAINING_flag),.IN({Y[0],a_out[0]}),.SIGN({1'b0,1'b1}),.OUT(eps_temp[0]),.R_condition(R_condition[0]),.SIGN_out(SIGN_L3[0])); 35 | SS_ADDSUB2 ADDSUB1(.CLK(CLK),.INIT(INIT|CLK_TRAINING_flag),.IN({Y[1],a_out[1]}),.SIGN({1'b0,1'b1}),.OUT(eps_temp[1]),.R_condition(R_condition[1]),.SIGN_out(SIGN_L3[1])); 36 | SS_ADDSUB2 ADDSUB2(.CLK(CLK),.INIT(INIT|CLK_TRAINING_flag),.IN({Y[2],a_out[2]}),.SIGN({1'b0,1'b1}),.OUT(eps_temp[2]),.R_condition(R_condition[2]),.SIGN_out(SIGN_L3[2])); 37 | SS_ADDSUB2 ADDSUB3(.CLK(CLK),.INIT(INIT|CLK_TRAINING_flag),.IN({Y[3],a_out[3]}),.SIGN({1'b0,1'b1}),.OUT(eps_temp[3]),.R_condition(R_condition[3]),.SIGN_out(SIGN_L3[3])); 38 | SS_ADDSUB2 ADDSUB4(.CLK(CLK),.INIT(INIT|CLK_TRAINING_flag),.IN({Y[4],a_out[4]}),.SIGN({1'b0,1'b1}),.OUT(eps_temp[4]),.R_condition(R_condition[4]),.SIGN_out(SIGN_L3[4])); 39 | defparam ADDSUB0.N = 2; 40 | defparam ADDSUB1.N = 2; 41 | defparam ADDSUB2.N = 2; 42 | defparam ADDSUB3.N = 2; 43 | defparam ADDSUB4.N = 2; 44 | 45 | 46 | always @(posedge CLK or posedge CLK_TRAINING_flag or posedge INIT) begin 47 | if (CLK_TRAINING_flag | INIT) SUPPRESS_COUNTER <= 1'b0; 48 | else if (SUPPRESS_COUNTER <= SUPPRESS_TIME) SUPPRESS_COUNTER <= SUPPRESS_COUNTER + 1'b1; 49 | else SUPPRESS_COUNTER <= SUPPRESS_COUNTER; 50 | end 51 | 52 | assign eps = (SUPPRESS_COUNTER>SUPPRESS_TIME) ? eps_temp : 3'b000; 53 | 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_NODE_BGPOLAR.v: -------------------------------------------------------------------------------- 1 | 2 | module NN_NODE_BGPOLAR(a,alpha,beta,SIGN_alpha,SIGN_beta,z,a_out,d,INIT_STATE,r,CLK,INIT); 3 | 4 | parameter ACT_F_BGCLUSTER = 3'b001,ACT_F_BG = 3'b010,ACT_F_RELU = 3'b100 ; 5 | parameter ACT_F = ACT_F_BGCLUSTER; 6 | parameter N = 4; 7 | parameter MEMSIZE = 3; 8 | 9 | 10 | 11 | input CLK, INIT; 12 | input [N-1:0] a,alpha; 13 | input [N-1:0] SIGN_alpha; 14 | input SIGN_beta; 15 | input beta; 16 | input d; 17 | input INIT_STATE; 18 | input r; 19 | 20 | output a_out,z; 21 | 22 | //wire [N-1:0] zp; 23 | wire [N-1:0] zp_pos; 24 | wire [N-1:0] zp_neg; 25 | wire z_pos,z_neg,z_temp,SIGN_z; 26 | 27 | genvar n; 28 | generate 29 | for (n=0; n=N_INPUTS_pos) : (N_INPUTS_neg>N_INPUTS_pos); 38 | 39 | always @(posedge CLK) begin 40 | 41 | if (INIT) begin 42 | DIFFCOUNT_SIGN = DIFFCOUNT_SIGN; 43 | DIFFCOUNT <= 1'b0; 44 | end else if (EQUAL) DIFFCOUNT <= DIFFCOUNT; 45 | else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)&(DIFFCOUNT +ve 46 | DIFFCOUNT_SIGN = 1'b0; 47 | DIFFCOUNT <= N_INPUTS_pos; 48 | end else if ((!INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos))&(!DIFFCOUNT_SIGN)) begin // +ve input, currently +ve, stay as positive and increment 49 | DIFFCOUNT <= DIFFCOUNT + N_INPUTS_pos; 50 | end else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)) begin // +ve input, currently -ve, stay -ve and decrement 51 | DIFFCOUNT <= DIFFCOUNT - N_INPUTS_pos; 52 | end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)&(DIFFCOUNT -ve 53 | DIFFCOUNT_SIGN = 1'b1; 54 | DIFFCOUNT <= N_INPUTS_neg; 55 | end else if ((INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_neg))&(DIFFCOUNT_SIGN)) begin // -ve input, currently -ve, stay as negative and increment 56 | DIFFCOUNT <= DIFFCOUNT + N_INPUTS_neg; 57 | end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, stay +ve and decrement 58 | DIFFCOUNT <= DIFFCOUNT - N_INPUTS_neg; 59 | end else DIFFCOUNT <= DIFFCOUNT; 60 | 61 | end 62 | 63 | 64 | assign SIGN_out = DIFFCOUNT_SIGN; 65 | 66 | assign INPUT_SUM_pos = (IN[0]&(~SIGN[0]))|(IN[1]&(~SIGN[1])); 67 | assign INPUT_SUM_neg = (IN[0]&(SIGN[0]))|(IN[1]&(SIGN[1])); 68 | 69 | assign OUTPUT_pos = INPUT_SUM_pos&(~INPUT_SUM_neg); 70 | assign OUTPUT_neg = INPUT_SUM_neg&(~INPUT_SUM_pos); 71 | 72 | //assign OUTPUT_pos = INPUT_SUM_pos&(~INPUT_SUM_neg)&(DIFFCOUNT>DIFFCOUNT_MIN); 73 | //assign OUTPUT_neg = INPUT_SUM_neg&(~INPUT_SUM_pos)&(DIFFCOUNT>DIFFCOUNT_MIN); 74 | 75 | assign OUT_temp = (SIGN_out) ? (OUTPUT_neg) : (OUTPUT_pos); 76 | 77 | assign OUT = (DIFFCOUNT > (DIFFCOUNT_MIN)) ? OUT_temp : 1'b0; 78 | 79 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/SS_ADDSUB.v: -------------------------------------------------------------------------------- 1 | 2 | // Chris Ceroici 3 | // Perform stochastic arithmetic for N inputs 4 | // requires SIGN input for each input argument 5 | 6 | module SS_ADDSUB(CLK,INIT,IN,SIGN,R_condition,OUT,SIGN_out); 7 | 8 | parameter N = 6; 9 | //parameter DIFFCOUNTER_SIZE = 5; 10 | //parameter DIFFCOUNT_LOWERLIM = 4; 11 | parameter DIFFCOUNTER_SIZE = 1; 12 | parameter DIFFCOUNT_LOWERLIM = 0; 13 | 14 | input CLK,INIT; 15 | input [N-1:0] IN,SIGN; 16 | input R_condition; 17 | 18 | output OUT,SIGN_out; 19 | 20 | wire INPUT_SUM_pos, INPUT_SUM_neg; 21 | wire OUTPUT_pos, OUTPUT_neg, OUT; 22 | //wire COUNT_ACTIVE; 23 | 24 | reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT = 1'd0; 25 | reg DIFFCOUNT_SIGN = 1'd0; 26 | 27 | reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT_LIMIT = 1'd0-1'd1; 28 | 29 | wire [N-1:0] N_INPUTS_pos; 30 | wire [N-1:0] N_INPUTS_neg; 31 | 32 | 33 | M_SIDEADD #(.N_inputs(N), .NB_out(N)) SIDEADDpos(.EN(1'b1),.IN(IN&(~SIGN)),.OUT(N_INPUTS_pos)); 34 | M_SIDEADD #(.N_inputs(N), .NB_out(N)) SIDEADDneg(.EN(1'b1),.IN(IN&(SIGN)),.OUT(N_INPUTS_neg)); 35 | //defparam SIDEADDpos.N_inputs = N; 36 | //defparam SIDEADDpos.NB_out = N; 37 | //defparam SIDEADDneg.N_inputs = N; 38 | //defparam SIDEADDneg.NB_out = N; 39 | 40 | wire EQUAL, INPUT_SIGN; 41 | 42 | assign EQUAL = (N_INPUTS_pos==N_INPUTS_neg); 43 | 44 | assign INPUT_SIGN = (R_condition) ? (N_INPUTS_neg>=N_INPUTS_pos) : (N_INPUTS_neg>N_INPUTS_pos); 45 | 46 | always @(posedge CLK or posedge INIT) begin 47 | 48 | if (INIT) begin 49 | DIFFCOUNT_SIGN = 1'b0; 50 | //DIFFCOUNT_SIGN = DIFFCOUNT_SIGN; 51 | DIFFCOUNT <= 1'b0; 52 | end else if (EQUAL) DIFFCOUNT <= DIFFCOUNT; 53 | else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)&(DIFFCOUNT +ve 54 | DIFFCOUNT_SIGN = 1'b0; 55 | DIFFCOUNT <= N_INPUTS_pos; 56 | // NOTE: If DIFFCOUNT = 1, (DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos) will never be satisfied when only a single input is 1. 57 | end else if ((!INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos))&(!DIFFCOUNT_SIGN)) begin // +ve input, currently +ve, stay as positive and increment 58 | DIFFCOUNT <= DIFFCOUNT + N_INPUTS_pos; 59 | end else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)) begin // +ve input, currently -ve, stay -ve and decrement 60 | DIFFCOUNT <= DIFFCOUNT - N_INPUTS_pos; 61 | end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)&(DIFFCOUNT -ve 62 | DIFFCOUNT_SIGN = 1'b1; 63 | DIFFCOUNT <= N_INPUTS_neg; 64 | end else if ((INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_neg))&(DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, cross: +ve -> -ve 65 | DIFFCOUNT <= DIFFCOUNT + N_INPUTS_neg; 66 | end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, stay +ve and decrement 67 | DIFFCOUNT <= DIFFCOUNT - N_INPUTS_neg; 68 | end else DIFFCOUNT <= DIFFCOUNT; 69 | 70 | end 71 | 72 | assign SIGN_out = DIFFCOUNT_SIGN; 73 | 74 | M_OR OR_pos(1'b1,IN&(~SIGN),INPUT_SUM_pos); 75 | defparam OR_pos.N = N; 76 | 77 | M_OR OR_neg(1'b1,IN&(SIGN),INPUT_SUM_neg); 78 | defparam OR_neg.N = N; 79 | 80 | assign OUTPUT_pos = INPUT_SUM_pos&(~INPUT_SUM_neg); 81 | assign OUTPUT_neg = INPUT_SUM_neg&(~INPUT_SUM_pos); 82 | 83 | assign OUT_temp = (SIGN_out) ? (OUTPUT_neg) : (OUTPUT_pos); 84 | 85 | //assign OUT = (DIFFCOUNT > (DIFFCOUNT_LIMIT-2'd2)) ? OUT_temp : 1'b0; 86 | assign OUT = (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) ? OUT_temp : 1'b0; 87 | 88 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/FULLCONNBLOCK_L3.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Fully Connected Layer 3 4 | 5 | module FULLCONNBLOCK_L3( 6 | a_input, 7 | a_MEM_ACTIVE, 8 | alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, 9 | beta, 10 | SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, 11 | SIGN_beta, 12 | z, 13 | zp, 14 | a_out, 15 | R_FPsource, zeroCenterSource, 16 | CLK, INIT, CLK_TRAINING_flag 17 | ); 18 | 19 | parameter MEMSIZE = 3; 20 | parameter DP_in = 8; 21 | parameter DP_out = 16; 22 | 23 | input wire [8 - 1:0] a_input; 24 | input wire [5-1:0] a_MEM_ACTIVE; 25 | input wire [8-1:0] alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4; 26 | input wire [5-1:0] beta; 27 | input wire [8-1:0] SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4; 28 | input wire [5-1:0] SIGN_beta; 29 | input wire R_FPsource, zeroCenterSource; 30 | input wire CLK, INIT, CLK_TRAINING_flag; 31 | 32 | output wire [5-1:0] z; 33 | output wire [5-1:0] zp; 34 | output wire [5-1:0] a_out; 35 | 36 | wire [5-1:0] zeroCenter, R_FP; 37 | SS_RERANDOMIZER RERANDOMIZER_zC(.CLK(CLK), .INIT(INIT), .IN(zeroCenterSource), .OUT(zeroCenter)); 38 | defparam RERANDOMIZER_zC.N = 5; 39 | SS_RERANDOMIZER RERANDOMIZER_FP(.CLK(CLK), .INIT(INIT), .IN(R_FPsource), .OUT(R_FP)); 40 | defparam RERANDOMIZER_FP.N = 5; 41 | 42 | NN_NODE_BGPOLAR NODE_0(.a(a_input), .alpha(alpha_j_0), .beta(beta[0]), .SIGN_alpha(SIGN_alpha_j_0), .SIGN_beta(SIGN_beta[0]), .z(z[0]), .d(zeroCenter[0]), .r(R_FP[0]), .a_out(a_out[0]), .INIT_STATE(a_MEM_ACTIVE[0]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 3 node 0 43 | NN_NODE_BGPOLAR NODE_1(.a(a_input), .alpha(alpha_j_1), .beta(beta[1]), .SIGN_alpha(SIGN_alpha_j_1), .SIGN_beta(SIGN_beta[1]), .z(z[1]), .d(zeroCenter[1]), .r(R_FP[1]), .a_out(a_out[1]), .INIT_STATE(a_MEM_ACTIVE[1]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 3 node 1 44 | NN_NODE_BGPOLAR NODE_2(.a(a_input), .alpha(alpha_j_2), .beta(beta[2]), .SIGN_alpha(SIGN_alpha_j_2), .SIGN_beta(SIGN_beta[2]), .z(z[2]), .d(zeroCenter[2]), .r(R_FP[2]), .a_out(a_out[2]), .INIT_STATE(a_MEM_ACTIVE[2]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 3 node 2 45 | NN_NODE_BGPOLAR NODE_3(.a(a_input), .alpha(alpha_j_3), .beta(beta[3]), .SIGN_alpha(SIGN_alpha_j_3), .SIGN_beta(SIGN_beta[3]), .z(z[3]), .d(zeroCenter[3]), .r(R_FP[3]), .a_out(a_out[3]), .INIT_STATE(a_MEM_ACTIVE[3]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 3 node 3 46 | NN_NODE_BGPOLAR NODE_4(.a(a_input), .alpha(alpha_j_4), .beta(beta[4]), .SIGN_alpha(SIGN_alpha_j_4), .SIGN_beta(SIGN_beta[4]), .z(z[4]), .d(zeroCenter[4]), .r(R_FP[4]), .a_out(a_out[4]), .INIT_STATE(a_MEM_ACTIVE[4]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 3 node 4 47 | defparam NODE_0.N = 8; 48 | defparam NODE_0.MEMSIZE = MEMSIZE; 49 | defparam NODE_1.N = 8; 50 | defparam NODE_1.MEMSIZE = MEMSIZE; 51 | defparam NODE_2.N = 8; 52 | defparam NODE_2.MEMSIZE = MEMSIZE; 53 | defparam NODE_3.N = 8; 54 | defparam NODE_3.MEMSIZE = MEMSIZE; 55 | defparam NODE_4.N = 8; 56 | defparam NODE_4.MEMSIZE = MEMSIZE; 57 | 58 | NN_BGPRIME BGPRIME_0(.z(z[0]), .zp(zp[0]), .CLK(CLK), .INIT(INIT)); 59 | NN_BGPRIME BGPRIME_1(.z(z[1]), .zp(zp[1]), .CLK(CLK), .INIT(INIT)); 60 | NN_BGPRIME BGPRIME_2(.z(z[2]), .zp(zp[2]), .CLK(CLK), .INIT(INIT)); 61 | NN_BGPRIME BGPRIME_3(.z(z[3]), .zp(zp[3]), .CLK(CLK), .INIT(INIT)); 62 | NN_BGPRIME BGPRIME_4(.z(z[4]), .zp(zp[4]), .CLK(CLK), .INIT(INIT)); 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/ME_LFSR16.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | // August 12 2013 3 | // 4 | // 16 bit LFSR 5 | // Primitive Polynomial: 1+x2+x3+x5+x16 6 | // 7 | module ME_LFSR16(TRIG,RESET,IN0,IN1,IN2,IN3,OUT0,OUT1,OUT2,OUT3,SEED); 8 | 9 | input TRIG, RESET; // TRIG: shift registers trigger 10 | input [15:0] SEED; 11 | input [7:0] IN0,IN1,IN2,IN3; 12 | 13 | output [7:0] OUT0,OUT1,OUT2,OUT3; 14 | 15 | 16 | //wire [7:0] OUTtemp0,OUTtemp1,OUTtemp2,OUTtemp3; 17 | reg [7:0] OUTtemp0 = 1'd0,OUTtemp1 = 1'd0,OUTtemp2 = 1'd0,OUTtemp3 = 1'd0; 18 | wire [2:0] Q /* synthesis keep */; 19 | wire [3:0] mut0,mut1,mut2,mut3; 20 | 21 | reg [15:0] D = 16'd0 /* synthesis preserve */; 22 | 23 | // Note: Combinational loops here. Better to use: 24 | /* 25 | always @(posedge INIT) begin 26 | OUT0 = ... ; 27 | . 28 | . 29 | . 30 | end 31 | */ 32 | 33 | always @(posedge TRIG) begin 34 | OUTtemp0 = ((mut0[3] | (OUT0>8'd240))&(~(OUT0<8'd15))) ? (IN0 - {mut0[2],mut0[1],mut0[0],1'd1}) : (IN0 + {mut0[2],mut0[1],mut0[0],1'd1}); 35 | OUTtemp1 = ((mut1[3] | (OUT1>8'd240))&(~(OUT1<8'd15))) ? (IN1 - {mut1[2],mut1[1],mut1[0],1'd1}) : (IN1 + {mut1[2],mut1[1],mut1[0],1'd1}); 36 | OUTtemp2 = ((mut2[3] | (OUT2>8'd240))&(~(OUT2<8'd15))) ? (IN2 - {mut2[2],mut2[1],mut2[0],1'd1}) : (IN2 + {mut2[2],mut2[1],mut2[0],1'd1}); 37 | OUTtemp3 = ((mut3[3] | (OUT3>8'd240))&(~(OUT3<8'd15))) ? (IN3 - {mut3[2],mut3[1],mut3[0],1'd1}) : (IN3 + {mut3[2],mut3[1],mut3[0],1'd1}); 38 | end 39 | 40 | //wire [7:0] T0,T1,T2,T3; 41 | 42 | //assign T0 = ((mut0[3] | (OUT0>8'd240))&(~(OUT0<8'd15))) ? (1'd0 - {mut0[2],mut0[1],mut0[0],1'd1}) : ({mut0[2],mut0[1],mut0[0],1'd1}); 43 | //assign T1 = ((mut1[3] | (OUT1>8'd240))&(~(OUT1<8'd15))) ? (1'd0 - {mut1[2],mut1[1],mut1[0],1'd1}) : ({mut1[2],mut1[1],mut1[0],1'd1}); 44 | //assign T2 = ((mut2[3] | (OUT2>8'd240))&(~(OUT2<8'd15))) ? (1'd0 - {mut2[2],mut2[1],mut2[0],1'd1}) : ({mut2[2],mut2[1],mut2[0],1'd1}); 45 | //assign T3 = ((mut3[3] | (OUT3>8'd240))&(~(OUT3<8'd15))) ? (1'd0 - {mut3[2],mut3[1],mut3[0],1'd1}) : ({mut3[2],mut3[1],mut3[0],1'd1}); 46 | 47 | /* 48 | assign #1 OUTtemp0 = ((mut0[3] | (OUT0>8'd247))&(~(OUT0<8'd7))) ? (IN0 - {mut0[2],mut0[1],mut0[0]}) : (IN0 + {mut0[2],mut0[1],mut0[0]}); 49 | assign #1 OUTtemp1 = ((mut1[3] | (OUT1>8'd247))&(~(OUT1<8'd7))) ? (IN1 - {mut1[2],mut1[1],mut1[0]}) : (IN1 + {mut1[2],mut1[1],mut1[0]}); 50 | assign #1 OUTtemp2 = ((mut2[3] | (OUT2>8'd247))&(~(OUT2<8'd7))) ? (IN2 - {mut2[2],mut2[1],mut2[0]}) : (IN2 + {mut2[2],mut2[1],mut2[0]}); 51 | assign #1 OUTtemp3 = ((mut3[3] | (OUT3>8'd247))&(~(OUT3<8'd7))) ? (IN3 - {mut3[2],mut3[1],mut3[0]}) : (IN3 + {mut3[2],mut3[1],mut3[0]}); 52 | */ 53 | assign #1 OUT0 = (RESET) ? 8'd100 : OUTtemp0; 54 | assign #1 OUT1 = (RESET) ? 8'd100 : OUTtemp1; 55 | assign #1 OUT2 = (RESET) ? 8'd100 : OUTtemp2; 56 | assign #1 OUT3 = (RESET) ? 8'd100 : OUTtemp3; 57 | 58 | 59 | 60 | assign mut0[3:0] = {D[0],D[15],D[2],D[13]}; 61 | assign mut1[3:0] = {D[4],D[11],D[6],D[9]}; 62 | assign mut2[3:0] = {D[8],D[14],D[7],D[12]}; 63 | assign mut3[3:0] = {D[5],D[10],D[3],D[1]}; 64 | 65 | xor U1(Q[0],D[15],D[4]); 66 | xor U2(Q[1],Q[0],D[2]); 67 | xor U3(Q[2],Q[1],D[1]); 68 | 69 | //assign Q[0] = D[15]^D[4]; 70 | //assign Q[1] = D[2]^Q[0]; 71 | //assign Q[2] = D[1]&Q[1]; 72 | 73 | 74 | 75 | /* 76 | always @(posedge TRIG) begin 77 | D[15:0] <= #3 {D[14:0],Q[2]}; 78 | end 79 | */ 80 | 81 | always @(posedge TRIG or posedge RESET) begin 82 | if (RESET) D <= SEED; 83 | else D[15:0] <= #3 {D[14:0],Q[2]}; 84 | end 85 | 86 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/SEED_portDefinitions.v: -------------------------------------------------------------------------------- 1 | .S0(SD0), .S1(SD1), .S2(SD2), .S3(SD3), .S4(SD4), .S5(SD5), .S6(SD6), .S7(SD7), .S8(SD8), .S9(SD9), .S10(SD10), .S11(SD11), .S12(SD12), .S13(SD13), .S14(SD14), .S15(SD15), .S16(SD16), .S17(SD17), .S18(SD18), .S19(SD19), .S20(SD20), .S21(SD21), .S22(SD22), .S23(SD23), .S24(SD24), .S25(SD25), .S26(SD26), .S27(SD27), .S28(SD28), .S29(SD29), .S30(SD30), .S31(SD31), .S32(SD32), .S33(SD33), .S34(SD34), .S35(SD35), .S36(SD36), .S37(SD37), .S38(SD38), .S39(SD39), .S40(SD40), .S41(SD41), .S42(SD42), .S43(SD43), .S44(SD44), .S45(SD45), .S46(SD46), .S47(SD47), .S48(SD48), .S49(SD49), .S50(SD50), .S51(SD51), .S52(SD52), .S53(SD53), .S54(SD54), .S55(SD55), .S56(SD56), .S57(SD57), .S58(SD58), .S59(SD59), .S60(SD60), .S61(SD61), .S62(SD62), .S63(SD63), .S64(SD64), .S65(SD65), .S66(SD66), .S67(SD67), .S68(SD68), .S69(SD69), .S70(SD70), .S71(SD71), .S72(SD72), .S73(SD73), .S74(SD74), .S75(SD75), .S76(SD76), .S77(SD77), .S78(SD78), .S79(SD79), .S80(SD80), .S81(SD81), .S82(SD82), .S83(SD83), .S84(SD84), .S85(SD85), .S86(SD86), .S87(SD87), .S88(SD88), .S89(SD89), .S90(SD90), .S91(SD91), .S92(SD92), .S93(SD93), .S94(SD94), .S95(SD95), .S96(SD96), .S97(SD97), .S98(SD98), .S99(SD99), .S100(SD100), .S101(SD101), .S102(SD102), .S103(SD103), .S104(SD104), .S105(SD105), .S106(SD106), .S107(SD107), .S108(SD108), .S109(SD109), .S110(SD110), .S111(SD111), .S112(SD112), .S113(SD113), .S114(SD114), .S115(SD115), .S116(SD116), .S117(SD117), .S118(SD118), .S119(SD119), .S120(SD120), .S121(SD121), .S122(SD122), .S123(SD123), .S124(SD124), .S125(SD125), .S126(SD126), .S127(SD127), .S128(SD128), .S129(SD129), .S130(SD130), .S131(SD131), .S132(SD132), .S133(SD133), .S134(SD134), .S135(SD135), .S136(SD136), .S137(SD137), .S138(SD138), .S139(SD139), .S140(SD140), .S141(SD141), .S142(SD142), .S143(SD143), .S144(SD144), .S145(SD145), .S146(SD146), .S147(SD147), .S148(SD148), .S149(SD149), .S150(SD150), .S151(SD151), .S152(SD152), .S153(SD153), .S154(SD154), .S155(SD155), .S156(SD156), .S157(SD157), .S158(SD158), .S159(SD159), .S160(SD160), .S161(SD161), .S162(SD162), .S163(SD163), .S164(SD164), .S165(SD165), .S166(SD166), .S167(SD167), .S168(SD168), .S169(SD169), .S170(SD170), .S171(SD171), .S172(SD172), .S173(SD173), .S174(SD174), .S175(SD175), .S176(SD176), .S177(SD177), .S178(SD178), .S179(SD179), .S180(SD180), .S181(SD181), .S182(SD182), .S183(SD183), .S184(SD184), .S185(SD185), .S186(SD186), .S187(SD187), .S188(SD188), .S189(SD189), .S190(SD190), .S191(SD191), .S192(SD192), .S193(SD193), .S194(SD194), .S195(SD195), .S196(SD196), .S197(SD197), .S198(SD198), .S199(SD199), .S200(SD200), .S201(SD201), .S202(SD202), .S203(SD203), .S204(SD204), .S205(SD205), .S206(SD206), .S207(SD207), .S208(SD208), .S209(SD209), .S210(SD210), .S211(SD211), .S212(SD212), .S213(SD213), .S214(SD214), .S215(SD215), .S216(SD216), .S217(SD217), .S218(SD218), .S219(SD219), .S220(SD220), .S221(SD221), .S222(SD222), .S223(SD223), .S224(SD224), .S225(SD225), .S226(SD226), .S227(SD227), .S228(SD228), .S229(SD229), .S230(SD230), .S231(SD231), .S232(SD232), .S233(SD233), .S234(SD234), .S235(SD235), .S236(SD236), .S237(SD237), .S238(SD238), .S239(SD239), .S240(SD240), .S241(SD241), .S242(SD242), .S243(SD243), .S244(SD244), .S245(SD245), .S246(SD246), .S247(SD247), .S248(SD248), .S249(SD249), .S250(SD250), .S251(SD251), .S252(SD252), .S253(SD253), .S254(SD254), .S255(SD255), .S256(SD256), .S257(SD257), .S258(SD258), .S259(SD259), .S260(SD260), .S261(SD261), .S262(SD262), .S263(SD263), .S264(SD264), .S265(SD265), .S266(SD266), .S267(SD267), .S268(SD268), .S269(SD269), .S270(SD270), .S271(SD271), .S272(SD272), .S273(SD273), .S274(SD274), .S275(SD275), .S276(SD276), .S277(SD277), .S278(SD278), .S279(SD279), 2 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/nn/NN_SMOOTHGRAD_POLAR.v: -------------------------------------------------------------------------------- 1 | 2 | // With dynamic resistance 3 | 4 | module NN_SMOOTHGRAD_POLAR(CLK, CLK_TRAINING_flag, INIT, IN_SS, SIGN, OUT, SIGN_out, RESISTANCE, TransitionChange_TRIG, OUT_INIT, SIGN_OUT_INIT, EN); 5 | 6 | parameter N = 8; // decimal output size 7 | parameter N_RESISTANCE = 9; 8 | 9 | input CLK, CLK_TRAINING_flag, INIT, EN; 10 | input IN_SS, SIGN; 11 | input [N-1:0] OUT_INIT; 12 | input SIGN_OUT_INIT; 13 | input [N_RESISTANCE-1:0] RESISTANCE; 14 | //input [N_RESISTANCE -1:0] RESISTANCE_MAX; 15 | 16 | output reg [N-1:0] OUT = 0; 17 | output reg SIGN_out = 1'b0; 18 | 19 | output wire TransitionChange_TRIG; 20 | 21 | reg [N-1:0] MaxVal_reg = 1'd0-1'd1; 22 | //reg [3-1:0] MaxVal_flag = 1'd0 - 1'd1; 23 | reg [N_RESISTANCE-1:0] flag_counter = 1'b0; 24 | //reg [N_RESISTANCE-1:0] flag_neg = 1'b0; 25 | 26 | //reg [N_RESISTANCE-1:0] RESISTANCE_MAX = 1'd0 - 1'd1; 27 | //reg [N_RESISTANCE-1:0] RESISTANCE_MAX = 8'd100; 28 | 29 | reg Transition = 1'd0; // sign of current flag saturation (direction parameter has moved) 30 | reg lastTransition = 1'd0; // sign of last flag saturation (direction parameter has moved) 31 | reg Transition_TRIG = 1'b0; 32 | 33 | //wire Transition_neg; 34 | //wire RESISTANCE_NOTATMAX, RESISTANCE_NOTATZERO; 35 | wire OUT_ATMAX, OUT_ATMAX_neg, OUT_ATMAX_pos, OUT_ATZERO; 36 | wire SIGNS_EQUAL; 37 | wire flag_ATRESISTANCE; 38 | 39 | //assign Transition_neg = ~Transition; 40 | 41 | assign OUT_ATMAX = (OUT==MaxVal_reg); 42 | assign OUT_ATMAX_neg = (OUT==MaxVal_reg)&(SIGN_out==1'b1); 43 | assign OUT_ATMAX_pos = (OUT==MaxVal_reg)&(SIGN_out==1'b0); 44 | assign OUT_ATZERO = (OUT==1'b0); 45 | assign SIGNS_EQUAL = (SIGN==SIGN_out); 46 | assign flag_ATRESISTANCE = (flag_counter>=RESISTANCE); 47 | //assign flag_neg_ATRESISTANCE = (flag_neg>=RESISTANCE); 48 | 49 | /* 50 | assign RESISTANCE_NOTATMAX = ~(RESISTANCE==RESISTANCE_MAX); 51 | assign RESISTANCE_NOTATZERO = ~(RESISTANCE==1'd0); 52 | 53 | always @(posedge INIT or posedge Transition_TRIG) begin 54 | if (INIT) begin 55 | RESISTANCE <= RESISTANCE; 56 | lastTransition <= 1'b0; 57 | end else if ((Transition!=lastTransition)&RESISTANCE_NOTATMAX) begin 58 | RESISTANCE <= RESISTANCE+1'b1; 59 | lastTransition <= Transition; 60 | end 61 | end 62 | */ 63 | 64 | assign TransitionChange_TRIG = Transition_TRIG&(Transition!=lastTransition); 65 | 66 | 67 | /* 68 | condition: 69 | flag_pos_ATRESISTANCE 70 | flag_neg_ATRESISTANCE 71 | OUT_ATZERO 72 | */ 73 | 74 | always @(posedge INIT or posedge CLK) begin 75 | 76 | if (INIT) begin 77 | OUT <= OUT_INIT; 78 | SIGN_out <= SIGN_OUT_INIT; 79 | flag_counter <= 1'b0; 80 | 81 | end else if (~EN) begin 82 | OUT <= OUT; 83 | SIGN_out <= SIGN_out; 84 | flag_counter <= flag_counter; 85 | 86 | end else if (!IN_SS) begin // input zero 87 | OUT <= OUT; 88 | SIGN_out <= SIGN_out; 89 | flag_counter <= flag_counter; 90 | 91 | end else if (flag_ATRESISTANCE&OUT_ATZERO) begin 92 | OUT <= 1'b1; 93 | SIGN_out <= SIGN; 94 | flag_counter <= 1'b0; 95 | 96 | end else if (flag_ATRESISTANCE) begin 97 | OUT <= OUT + ((SIGNS_EQUAL==1'b1)&(~OUT_ATMAX)) - (SIGNS_EQUAL==1'b0); 98 | SIGN_out <= SIGN_out; 99 | flag_counter <= 1'b0; 100 | 101 | end else if (~flag_ATRESISTANCE) begin 102 | OUT <= OUT; 103 | SIGN_out <= SIGN_out; 104 | flag_counter <= flag_counter + 1'b1; 105 | 106 | // Default: 107 | end else begin 108 | OUT <= OUT; // Input Positive/Negative: parameter at upper/lower limit -> do nothing 109 | SIGN_out <= SIGN_out; 110 | 111 | end 112 | 113 | 114 | end 115 | 116 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/SS_ADDSUB2_POS.v: -------------------------------------------------------------------------------- 1 | 2 | // Chris Ceroici 3 | // Perform stochastic arithmetic for N inputs 4 | // requires SIGN input for each input argument 5 | 6 | // Output only positive sum 7 | 8 | module SS_ADDSUB2_POS(CLK,INIT,IN,SIGN,OUT); 9 | 10 | parameter N = 2; 11 | parameter DIFFCOUNTER_SIZE = 2; 12 | 13 | input CLK,INIT; 14 | input [N-1:0] IN,SIGN; 15 | 16 | output OUT; 17 | 18 | wire INPUT_SUM_pos, INPUT_SUM_neg; 19 | //wire SIGN_out; 20 | wire OUTPUT_pos, OUT; 21 | wire COUNT_ACTIVE; 22 | 23 | reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT = 1'd0; 24 | reg DIFFCOUNT_SIGN = 1'd0; 25 | 26 | reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT_LIMIT = 1'd0-1'd1; 27 | 28 | wire [N-1:0] N_INPUTS_pos; 29 | wire [N-1:0] N_INPUTS_neg; 30 | 31 | //assign N_INPUTS_pos = {1'b0,IN[0]&(~SIGN[0])} + {1'b0,IN[1]&(~SIGN[1])}; 32 | //assign N_INPUTS_neg = {1'b0,IN[0]&(SIGN[0])} + {1'b0,IN[1]&(SIGN[1])}; 33 | 34 | //wire EQUAL, INPUT_SIGN; 35 | 36 | //assign EQUAL = (N_INPUTS_pos==N_INPUTS_neg); 37 | 38 | //assign INPUT_SIGN = N_INPUTS_neg>=N_INPUTS_pos; 39 | 40 | /* 41 | always @(posedge CLK) begin 42 | 43 | if (INIT) begin 44 | DIFFCOUNT_SIGN = DIFFCOUNT_SIGN; 45 | DIFFCOUNT <= 1'b0; 46 | end else if (EQUAL) DIFFCOUNT <= DIFFCOUNT; 47 | else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)&(DIFFCOUNT +ve 48 | DIFFCOUNT_SIGN = 1'b0; 49 | DIFFCOUNT <= N_INPUTS_pos; 50 | end else if ((!INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos))&(!DIFFCOUNT_SIGN)) begin // +ve input, currently +ve, stay as positive and increment 51 | DIFFCOUNT <= DIFFCOUNT + N_INPUTS_pos; 52 | end else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)) begin // +ve input, currently -ve, stay -ve and decrement 53 | DIFFCOUNT <= DIFFCOUNT - N_INPUTS_pos; 54 | end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)&(DIFFCOUNT -ve 55 | DIFFCOUNT_SIGN = 1'b1; 56 | DIFFCOUNT <= N_INPUTS_neg; 57 | end else if ((INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_neg))&(DIFFCOUNT_SIGN)) begin // -ve input, currently -ve, stay as negative and increment 58 | DIFFCOUNT <= DIFFCOUNT + N_INPUTS_neg; 59 | end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, stay +ve and decrement 60 | DIFFCOUNT <= DIFFCOUNT - N_INPUTS_neg; 61 | end else DIFFCOUNT <= DIFFCOUNT; 62 | 63 | end 64 | */ 65 | /* 66 | always @(posedge CLK) begin 67 | 68 | if (INPUT_pos_any&(!INPUT_neg_any)&(DIFFCOUNT==1'd0)) begin // cross neg->positive 69 | DIFFCOUNT_SIGN = 1'b0; 70 | DIFFCOUNT <= DIFFCOUNT + 1'd1; 71 | end else if (INPUT_pos_any&(!INPUT_neg_any)&(DIFFCOUNT!=DIFFCOUNT_LIMIT)&(!DIFFCOUNT_SIGN)) begin // positive increment 72 | DIFFCOUNT <= DIFFCOUNT + 1'd1; 73 | end else if (INPUT_pos_any&(!INPUT_neg_any)&(DIFFCOUNT_SIGN)) begin // positive decrement 74 | DIFFCOUNT <= DIFFCOUNT - 1'd1; 75 | end else if (INPUT_neg_any&(!INPUT_pos_any)&(DIFFCOUNT==1'd0)) begin // cross pos -> negative 76 | DIFFCOUNT_SIGN = 1'b1; 77 | DIFFCOUNT <= DIFFCOUNT + 1'd1; 78 | end else if (INPUT_neg_any&(!INPUT_pos_any)&(DIFFCOUNT!=DIFFCOUNT_LIMIT)&(DIFFCOUNT_SIGN)) begin // negative increment 79 | DIFFCOUNT <= DIFFCOUNT + 1'd1; 80 | end else if (INPUT_neg_any&(!INPUT_pos_any)&(!DIFFCOUNT_SIGN)) begin // negative decrement 81 | DIFFCOUNT <= DIFFCOUNT - 1'd1; 82 | end else DIFFCOUNT <= DIFFCOUNT; 83 | 84 | end */ 85 | 86 | //assign SIGN_out = DIFFCOUNT_SIGN; 87 | 88 | assign INPUT_SUM_pos = (IN[0]&(~SIGN[0]))|(IN[1]&(~SIGN[1])); 89 | assign INPUT_SUM_neg = (IN[0]&(SIGN[0]))|(IN[1]&(SIGN[1])); 90 | 91 | assign OUTPUT_pos = INPUT_SUM_pos&(~INPUT_SUM_neg); 92 | //assign OUTPUT_neg = INPUT_SUM_neg&(~INPUT_SUM_pos); 93 | 94 | assign OUT = OUTPUT_pos; 95 | 96 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/FULLCONNBLOCKBP_L2.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Fully Connected Backpropagation Layer 2 4 | 5 | module FULLCONNBLOCKBP_L2( 6 | alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, 7 | SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, 8 | z, 9 | zp, 10 | delta_in, 11 | SIGN_delta_in, 12 | delta_out, 13 | SIGN_delta_out, 14 | R_BPsource, 15 | CLK, INIT 16 | ); 17 | 18 | input wire [8-1:0] alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4; 19 | input wire [8-1:0] SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4; 20 | input wire [8-1:0] z; 21 | input wire [8-1:0] zp; 22 | input wire [5-1:0] delta_in; 23 | input wire [5-1:0] SIGN_delta_in; 24 | input wire R_BPsource; 25 | input wire CLK, INIT; 26 | 27 | output wire [8-1:0] delta_out; 28 | output wire [8-1:0] SIGN_delta_out; 29 | 30 | wire [8-1:0] R_BP; 31 | 32 | SS_RERANDOMIZER RERANDOMIZER0(.CLK(CLK), .INIT(INIT), .IN(R_BPsource), .OUT(R_BP)); 33 | defparam RERANDOMIZER0.N = 8; 34 | 35 | NN_DELTABP_POLAR DELTABP_0(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[0]),.z(z[0]),.zp(zp[0]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[0], alpha_j_3[0], alpha_j_2[0], alpha_j_1[0], alpha_j_0[0]}), .SIGN_alpha({SIGN_alpha_j_4[0], SIGN_alpha_j_3[0], SIGN_alpha_j_2[0], SIGN_alpha_j_1[0], SIGN_alpha_j_0[0]}), .delta_out(delta_out[0]), .SIGN_out(SIGN_delta_out[0])); 36 | NN_DELTABP_POLAR DELTABP_1(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[1]),.z(z[1]),.zp(zp[1]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[1], alpha_j_3[1], alpha_j_2[1], alpha_j_1[1], alpha_j_0[1]}), .SIGN_alpha({SIGN_alpha_j_4[1], SIGN_alpha_j_3[1], SIGN_alpha_j_2[1], SIGN_alpha_j_1[1], SIGN_alpha_j_0[1]}), .delta_out(delta_out[1]), .SIGN_out(SIGN_delta_out[1])); 37 | NN_DELTABP_POLAR DELTABP_2(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[2]),.z(z[2]),.zp(zp[2]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[2], alpha_j_3[2], alpha_j_2[2], alpha_j_1[2], alpha_j_0[2]}), .SIGN_alpha({SIGN_alpha_j_4[2], SIGN_alpha_j_3[2], SIGN_alpha_j_2[2], SIGN_alpha_j_1[2], SIGN_alpha_j_0[2]}), .delta_out(delta_out[2]), .SIGN_out(SIGN_delta_out[2])); 38 | NN_DELTABP_POLAR DELTABP_3(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[3]),.z(z[3]),.zp(zp[3]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[3], alpha_j_3[3], alpha_j_2[3], alpha_j_1[3], alpha_j_0[3]}), .SIGN_alpha({SIGN_alpha_j_4[3], SIGN_alpha_j_3[3], SIGN_alpha_j_2[3], SIGN_alpha_j_1[3], SIGN_alpha_j_0[3]}), .delta_out(delta_out[3]), .SIGN_out(SIGN_delta_out[3])); 39 | NN_DELTABP_POLAR DELTABP_4(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[4]),.z(z[4]),.zp(zp[4]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[4], alpha_j_3[4], alpha_j_2[4], alpha_j_1[4], alpha_j_0[4]}), .SIGN_alpha({SIGN_alpha_j_4[4], SIGN_alpha_j_3[4], SIGN_alpha_j_2[4], SIGN_alpha_j_1[4], SIGN_alpha_j_0[4]}), .delta_out(delta_out[4]), .SIGN_out(SIGN_delta_out[4])); 40 | NN_DELTABP_POLAR DELTABP_5(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[5]),.z(z[5]),.zp(zp[5]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[5], alpha_j_3[5], alpha_j_2[5], alpha_j_1[5], alpha_j_0[5]}), .SIGN_alpha({SIGN_alpha_j_4[5], SIGN_alpha_j_3[5], SIGN_alpha_j_2[5], SIGN_alpha_j_1[5], SIGN_alpha_j_0[5]}), .delta_out(delta_out[5]), .SIGN_out(SIGN_delta_out[5])); 41 | NN_DELTABP_POLAR DELTABP_6(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[6]),.z(z[6]),.zp(zp[6]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[6], alpha_j_3[6], alpha_j_2[6], alpha_j_1[6], alpha_j_0[6]}), .SIGN_alpha({SIGN_alpha_j_4[6], SIGN_alpha_j_3[6], SIGN_alpha_j_2[6], SIGN_alpha_j_1[6], SIGN_alpha_j_0[6]}), .delta_out(delta_out[6]), .SIGN_out(SIGN_delta_out[6])); 42 | NN_DELTABP_POLAR DELTABP_7(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[7]),.z(z[7]),.zp(zp[7]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_4[7], alpha_j_3[7], alpha_j_2[7], alpha_j_1[7], alpha_j_0[7]}), .SIGN_alpha({SIGN_alpha_j_4[7], SIGN_alpha_j_3[7], SIGN_alpha_j_2[7], SIGN_alpha_j_1[7], SIGN_alpha_j_0[7]}), .delta_out(delta_out[7]), .SIGN_out(SIGN_delta_out[7])); 43 | defparam DELTABP_0.N = 5; 44 | defparam DELTABP_1.N = 5; 45 | defparam DELTABP_2.N = 5; 46 | defparam DELTABP_3.N = 5; 47 | defparam DELTABP_4.N = 5; 48 | defparam DELTABP_5.N = 5; 49 | defparam DELTABP_6.N = 5; 50 | defparam DELTABP_7.N = 5; 51 | 52 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/FULLCONNBLOCK_L2.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Fully Connected Layer 2 4 | 5 | module FULLCONNBLOCK_L2( 6 | a_input, 7 | a_MEM_ACTIVE, 8 | alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, alpha_j_5, alpha_j_6, alpha_j_7, 9 | beta, 10 | SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, SIGN_alpha_j_5, SIGN_alpha_j_6, SIGN_alpha_j_7, 11 | SIGN_beta, 12 | z, 13 | zp, 14 | a_out, 15 | R_FPsource, zeroCenterSource, 16 | CLK, INIT, CLK_TRAINING_flag 17 | ); 18 | 19 | parameter MEMSIZE = 3; 20 | parameter DP_in = 8; 21 | parameter DP_out = 16; 22 | 23 | input wire [25 - 1:0] a_input; 24 | input wire [8-1:0] a_MEM_ACTIVE; 25 | input wire [25-1:0] alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, alpha_j_5, alpha_j_6, alpha_j_7; 26 | input wire [8-1:0] beta; 27 | input wire [25-1:0] SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, SIGN_alpha_j_5, SIGN_alpha_j_6, SIGN_alpha_j_7; 28 | input wire [8-1:0] SIGN_beta; 29 | input wire R_FPsource, zeroCenterSource; 30 | input wire CLK, INIT, CLK_TRAINING_flag; 31 | 32 | output wire [8-1:0] z; 33 | output wire [8-1:0] zp; 34 | output wire [8-1:0] a_out; 35 | 36 | wire [8-1:0] zeroCenter, R_FP; 37 | SS_RERANDOMIZER RERANDOMIZER_zC(.CLK(CLK), .INIT(INIT), .IN(zeroCenterSource), .OUT(zeroCenter)); 38 | defparam RERANDOMIZER_zC.N = 8; 39 | SS_RERANDOMIZER RERANDOMIZER_FP(.CLK(CLK), .INIT(INIT), .IN(R_FPsource), .OUT(R_FP)); 40 | defparam RERANDOMIZER_FP.N = 8; 41 | 42 | NN_NODE_BGPOLAR NODE_0(.a(a_input), .alpha(alpha_j_0), .beta(beta[0]), .SIGN_alpha(SIGN_alpha_j_0), .SIGN_beta(SIGN_beta[0]), .z(z[0]), .d(zeroCenter[0]), .r(R_FP[0]), .a_out(a_out[0]), .INIT_STATE(a_MEM_ACTIVE[0]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 0 43 | NN_NODE_BGPOLAR NODE_1(.a(a_input), .alpha(alpha_j_1), .beta(beta[1]), .SIGN_alpha(SIGN_alpha_j_1), .SIGN_beta(SIGN_beta[1]), .z(z[1]), .d(zeroCenter[1]), .r(R_FP[1]), .a_out(a_out[1]), .INIT_STATE(a_MEM_ACTIVE[1]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 1 44 | NN_NODE_BGPOLAR NODE_2(.a(a_input), .alpha(alpha_j_2), .beta(beta[2]), .SIGN_alpha(SIGN_alpha_j_2), .SIGN_beta(SIGN_beta[2]), .z(z[2]), .d(zeroCenter[2]), .r(R_FP[2]), .a_out(a_out[2]), .INIT_STATE(a_MEM_ACTIVE[2]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 2 45 | NN_NODE_BGPOLAR NODE_3(.a(a_input), .alpha(alpha_j_3), .beta(beta[3]), .SIGN_alpha(SIGN_alpha_j_3), .SIGN_beta(SIGN_beta[3]), .z(z[3]), .d(zeroCenter[3]), .r(R_FP[3]), .a_out(a_out[3]), .INIT_STATE(a_MEM_ACTIVE[3]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 3 46 | NN_NODE_BGPOLAR NODE_4(.a(a_input), .alpha(alpha_j_4), .beta(beta[4]), .SIGN_alpha(SIGN_alpha_j_4), .SIGN_beta(SIGN_beta[4]), .z(z[4]), .d(zeroCenter[4]), .r(R_FP[4]), .a_out(a_out[4]), .INIT_STATE(a_MEM_ACTIVE[4]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 4 47 | NN_NODE_BGPOLAR NODE_5(.a(a_input), .alpha(alpha_j_5), .beta(beta[5]), .SIGN_alpha(SIGN_alpha_j_5), .SIGN_beta(SIGN_beta[5]), .z(z[5]), .d(zeroCenter[5]), .r(R_FP[5]), .a_out(a_out[5]), .INIT_STATE(a_MEM_ACTIVE[5]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 5 48 | NN_NODE_BGPOLAR NODE_6(.a(a_input), .alpha(alpha_j_6), .beta(beta[6]), .SIGN_alpha(SIGN_alpha_j_6), .SIGN_beta(SIGN_beta[6]), .z(z[6]), .d(zeroCenter[6]), .r(R_FP[6]), .a_out(a_out[6]), .INIT_STATE(a_MEM_ACTIVE[6]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 6 49 | NN_NODE_BGPOLAR NODE_7(.a(a_input), .alpha(alpha_j_7), .beta(beta[7]), .SIGN_alpha(SIGN_alpha_j_7), .SIGN_beta(SIGN_beta[7]), .z(z[7]), .d(zeroCenter[7]), .r(R_FP[7]), .a_out(a_out[7]), .INIT_STATE(a_MEM_ACTIVE[7]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 2 node 7 50 | defparam NODE_0.N = 25; 51 | defparam NODE_0.MEMSIZE = MEMSIZE; 52 | defparam NODE_1.N = 25; 53 | defparam NODE_1.MEMSIZE = MEMSIZE; 54 | defparam NODE_2.N = 25; 55 | defparam NODE_2.MEMSIZE = MEMSIZE; 56 | defparam NODE_3.N = 25; 57 | defparam NODE_3.MEMSIZE = MEMSIZE; 58 | defparam NODE_4.N = 25; 59 | defparam NODE_4.MEMSIZE = MEMSIZE; 60 | defparam NODE_5.N = 25; 61 | defparam NODE_5.MEMSIZE = MEMSIZE; 62 | defparam NODE_6.N = 25; 63 | defparam NODE_6.MEMSIZE = MEMSIZE; 64 | defparam NODE_7.N = 25; 65 | defparam NODE_7.MEMSIZE = MEMSIZE; 66 | 67 | NN_BGPRIME BGPRIME_0(.z(z[0]), .zp(zp[0]), .CLK(CLK), .INIT(INIT)); 68 | NN_BGPRIME BGPRIME_1(.z(z[1]), .zp(zp[1]), .CLK(CLK), .INIT(INIT)); 69 | NN_BGPRIME BGPRIME_2(.z(z[2]), .zp(zp[2]), .CLK(CLK), .INIT(INIT)); 70 | NN_BGPRIME BGPRIME_3(.z(z[3]), .zp(zp[3]), .CLK(CLK), .INIT(INIT)); 71 | NN_BGPRIME BGPRIME_4(.z(z[4]), .zp(zp[4]), .CLK(CLK), .INIT(INIT)); 72 | NN_BGPRIME BGPRIME_5(.z(z[5]), .zp(zp[5]), .CLK(CLK), .INIT(INIT)); 73 | NN_BGPRIME BGPRIME_6(.z(z[6]), .zp(zp[6]), .CLK(CLK), .INIT(INIT)); 74 | NN_BGPRIME BGPRIME_7(.z(z[7]), .zp(zp[7]), .CLK(CLK), .INIT(INIT)); 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /FullyConnectedSNN/DecimalParam_Declarations.v: -------------------------------------------------------------------------------- 1 | wire [DP_in - 1:0] alphaD_L1_0_0, alphaD_L1_0_1, alphaD_L1_0_2, alphaD_L1_0_3, alphaD_L1_0_4, alphaD_L1_0_5, alphaD_L1_0_6, alphaD_L1_0_7, alphaD_L1_0_8, alphaD_L1_0_9, alphaD_L1_0_10, alphaD_L1_0_11, alphaD_L1_0_12, alphaD_L1_0_13, alphaD_L1_0_14, alphaD_L1_0_15, alphaD_L1_0_16, alphaD_L1_0_17, alphaD_L1_0_18, alphaD_L1_0_19, alphaD_L1_0_20, alphaD_L1_0_21, alphaD_L1_0_22, alphaD_L1_0_23, alphaD_L1_0_24; 2 | wire [DP_in - 1:0] alphaD_L1_1_0, alphaD_L1_1_1, alphaD_L1_1_2, alphaD_L1_1_3, alphaD_L1_1_4, alphaD_L1_1_5, alphaD_L1_1_6, alphaD_L1_1_7, alphaD_L1_1_8, alphaD_L1_1_9, alphaD_L1_1_10, alphaD_L1_1_11, alphaD_L1_1_12, alphaD_L1_1_13, alphaD_L1_1_14, alphaD_L1_1_15, alphaD_L1_1_16, alphaD_L1_1_17, alphaD_L1_1_18, alphaD_L1_1_19, alphaD_L1_1_20, alphaD_L1_1_21, alphaD_L1_1_22, alphaD_L1_1_23, alphaD_L1_1_24; 3 | wire [DP_in - 1:0] alphaD_L1_2_0, alphaD_L1_2_1, alphaD_L1_2_2, alphaD_L1_2_3, alphaD_L1_2_4, alphaD_L1_2_5, alphaD_L1_2_6, alphaD_L1_2_7, alphaD_L1_2_8, alphaD_L1_2_9, alphaD_L1_2_10, alphaD_L1_2_11, alphaD_L1_2_12, alphaD_L1_2_13, alphaD_L1_2_14, alphaD_L1_2_15, alphaD_L1_2_16, alphaD_L1_2_17, alphaD_L1_2_18, alphaD_L1_2_19, alphaD_L1_2_20, alphaD_L1_2_21, alphaD_L1_2_22, alphaD_L1_2_23, alphaD_L1_2_24; 4 | wire [DP_in - 1:0] alphaD_L1_3_0, alphaD_L1_3_1, alphaD_L1_3_2, alphaD_L1_3_3, alphaD_L1_3_4, alphaD_L1_3_5, alphaD_L1_3_6, alphaD_L1_3_7, alphaD_L1_3_8, alphaD_L1_3_9, alphaD_L1_3_10, alphaD_L1_3_11, alphaD_L1_3_12, alphaD_L1_3_13, alphaD_L1_3_14, alphaD_L1_3_15, alphaD_L1_3_16, alphaD_L1_3_17, alphaD_L1_3_18, alphaD_L1_3_19, alphaD_L1_3_20, alphaD_L1_3_21, alphaD_L1_3_22, alphaD_L1_3_23, alphaD_L1_3_24; 5 | wire [DP_in - 1:0] alphaD_L1_4_0, alphaD_L1_4_1, alphaD_L1_4_2, alphaD_L1_4_3, alphaD_L1_4_4, alphaD_L1_4_5, alphaD_L1_4_6, alphaD_L1_4_7, alphaD_L1_4_8, alphaD_L1_4_9, alphaD_L1_4_10, alphaD_L1_4_11, alphaD_L1_4_12, alphaD_L1_4_13, alphaD_L1_4_14, alphaD_L1_4_15, alphaD_L1_4_16, alphaD_L1_4_17, alphaD_L1_4_18, alphaD_L1_4_19, alphaD_L1_4_20, alphaD_L1_4_21, alphaD_L1_4_22, alphaD_L1_4_23, alphaD_L1_4_24; 6 | wire [DP_in - 1:0] betaD_L1_0, betaD_L1_1, betaD_L1_2, betaD_L1_3, betaD_L1_4, betaD_L1_5, betaD_L1_6, betaD_L1_7, betaD_L1_8, betaD_L1_9, betaD_L1_10, betaD_L1_11, betaD_L1_12, betaD_L1_13, betaD_L1_14, betaD_L1_15, betaD_L1_16, betaD_L1_17, betaD_L1_18, betaD_L1_19, betaD_L1_20, betaD_L1_21, betaD_L1_22, betaD_L1_23, betaD_L1_24; 7 | wire [DP_in - 1:0] alphaD_L2_0_0, alphaD_L2_0_1, alphaD_L2_0_2, alphaD_L2_0_3, alphaD_L2_0_4, alphaD_L2_0_5, alphaD_L2_0_6, alphaD_L2_0_7; 8 | wire [DP_in - 1:0] alphaD_L2_1_0, alphaD_L2_1_1, alphaD_L2_1_2, alphaD_L2_1_3, alphaD_L2_1_4, alphaD_L2_1_5, alphaD_L2_1_6, alphaD_L2_1_7; 9 | wire [DP_in - 1:0] alphaD_L2_2_0, alphaD_L2_2_1, alphaD_L2_2_2, alphaD_L2_2_3, alphaD_L2_2_4, alphaD_L2_2_5, alphaD_L2_2_6, alphaD_L2_2_7; 10 | wire [DP_in - 1:0] alphaD_L2_3_0, alphaD_L2_3_1, alphaD_L2_3_2, alphaD_L2_3_3, alphaD_L2_3_4, alphaD_L2_3_5, alphaD_L2_3_6, alphaD_L2_3_7; 11 | wire [DP_in - 1:0] alphaD_L2_4_0, alphaD_L2_4_1, alphaD_L2_4_2, alphaD_L2_4_3, alphaD_L2_4_4, alphaD_L2_4_5, alphaD_L2_4_6, alphaD_L2_4_7; 12 | wire [DP_in - 1:0] alphaD_L2_5_0, alphaD_L2_5_1, alphaD_L2_5_2, alphaD_L2_5_3, alphaD_L2_5_4, alphaD_L2_5_5, alphaD_L2_5_6, alphaD_L2_5_7; 13 | wire [DP_in - 1:0] alphaD_L2_6_0, alphaD_L2_6_1, alphaD_L2_6_2, alphaD_L2_6_3, alphaD_L2_6_4, alphaD_L2_6_5, alphaD_L2_6_6, alphaD_L2_6_7; 14 | wire [DP_in - 1:0] alphaD_L2_7_0, alphaD_L2_7_1, alphaD_L2_7_2, alphaD_L2_7_3, alphaD_L2_7_4, alphaD_L2_7_5, alphaD_L2_7_6, alphaD_L2_7_7; 15 | wire [DP_in - 1:0] alphaD_L2_8_0, alphaD_L2_8_1, alphaD_L2_8_2, alphaD_L2_8_3, alphaD_L2_8_4, alphaD_L2_8_5, alphaD_L2_8_6, alphaD_L2_8_7; 16 | wire [DP_in - 1:0] alphaD_L2_9_0, alphaD_L2_9_1, alphaD_L2_9_2, alphaD_L2_9_3, alphaD_L2_9_4, alphaD_L2_9_5, alphaD_L2_9_6, alphaD_L2_9_7; 17 | wire [DP_in - 1:0] alphaD_L2_10_0, alphaD_L2_10_1, alphaD_L2_10_2, alphaD_L2_10_3, alphaD_L2_10_4, alphaD_L2_10_5, alphaD_L2_10_6, alphaD_L2_10_7; 18 | wire [DP_in - 1:0] alphaD_L2_11_0, alphaD_L2_11_1, alphaD_L2_11_2, alphaD_L2_11_3, alphaD_L2_11_4, alphaD_L2_11_5, alphaD_L2_11_6, alphaD_L2_11_7; 19 | wire [DP_in - 1:0] alphaD_L2_12_0, alphaD_L2_12_1, alphaD_L2_12_2, alphaD_L2_12_3, alphaD_L2_12_4, alphaD_L2_12_5, alphaD_L2_12_6, alphaD_L2_12_7; 20 | wire [DP_in - 1:0] alphaD_L2_13_0, alphaD_L2_13_1, alphaD_L2_13_2, alphaD_L2_13_3, alphaD_L2_13_4, alphaD_L2_13_5, alphaD_L2_13_6, alphaD_L2_13_7; 21 | wire [DP_in - 1:0] alphaD_L2_14_0, alphaD_L2_14_1, alphaD_L2_14_2, alphaD_L2_14_3, alphaD_L2_14_4, alphaD_L2_14_5, alphaD_L2_14_6, alphaD_L2_14_7; 22 | wire [DP_in - 1:0] alphaD_L2_15_0, alphaD_L2_15_1, alphaD_L2_15_2, alphaD_L2_15_3, alphaD_L2_15_4, alphaD_L2_15_5, alphaD_L2_15_6, alphaD_L2_15_7; 23 | wire [DP_in - 1:0] alphaD_L2_16_0, alphaD_L2_16_1, alphaD_L2_16_2, alphaD_L2_16_3, alphaD_L2_16_4, alphaD_L2_16_5, alphaD_L2_16_6, alphaD_L2_16_7; 24 | wire [DP_in - 1:0] alphaD_L2_17_0, alphaD_L2_17_1, alphaD_L2_17_2, alphaD_L2_17_3, alphaD_L2_17_4, alphaD_L2_17_5, alphaD_L2_17_6, alphaD_L2_17_7; 25 | wire [DP_in - 1:0] alphaD_L2_18_0, alphaD_L2_18_1, alphaD_L2_18_2, alphaD_L2_18_3, alphaD_L2_18_4, alphaD_L2_18_5, alphaD_L2_18_6, alphaD_L2_18_7; 26 | wire [DP_in - 1:0] alphaD_L2_19_0, alphaD_L2_19_1, alphaD_L2_19_2, alphaD_L2_19_3, alphaD_L2_19_4, alphaD_L2_19_5, alphaD_L2_19_6, alphaD_L2_19_7; 27 | wire [DP_in - 1:0] alphaD_L2_20_0, alphaD_L2_20_1, alphaD_L2_20_2, alphaD_L2_20_3, alphaD_L2_20_4, alphaD_L2_20_5, alphaD_L2_20_6, alphaD_L2_20_7; 28 | wire [DP_in - 1:0] alphaD_L2_21_0, alphaD_L2_21_1, alphaD_L2_21_2, alphaD_L2_21_3, alphaD_L2_21_4, alphaD_L2_21_5, alphaD_L2_21_6, alphaD_L2_21_7; 29 | wire [DP_in - 1:0] alphaD_L2_22_0, alphaD_L2_22_1, alphaD_L2_22_2, alphaD_L2_22_3, alphaD_L2_22_4, alphaD_L2_22_5, alphaD_L2_22_6, alphaD_L2_22_7; 30 | wire [DP_in - 1:0] alphaD_L2_23_0, alphaD_L2_23_1, alphaD_L2_23_2, alphaD_L2_23_3, alphaD_L2_23_4, alphaD_L2_23_5, alphaD_L2_23_6, alphaD_L2_23_7; 31 | wire [DP_in - 1:0] alphaD_L2_24_0, alphaD_L2_24_1, alphaD_L2_24_2, alphaD_L2_24_3, alphaD_L2_24_4, alphaD_L2_24_5, alphaD_L2_24_6, alphaD_L2_24_7; 32 | wire [DP_in - 1:0] betaD_L2_0, betaD_L2_1, betaD_L2_2, betaD_L2_3, betaD_L2_4, betaD_L2_5, betaD_L2_6, betaD_L2_7; 33 | wire [DP_in - 1:0] alphaD_L3_0_0, alphaD_L3_0_1, alphaD_L3_0_2, alphaD_L3_0_3, alphaD_L3_0_4; 34 | wire [DP_in - 1:0] alphaD_L3_1_0, alphaD_L3_1_1, alphaD_L3_1_2, alphaD_L3_1_3, alphaD_L3_1_4; 35 | wire [DP_in - 1:0] alphaD_L3_2_0, alphaD_L3_2_1, alphaD_L3_2_2, alphaD_L3_2_3, alphaD_L3_2_4; 36 | wire [DP_in - 1:0] alphaD_L3_3_0, alphaD_L3_3_1, alphaD_L3_3_2, alphaD_L3_3_3, alphaD_L3_3_4; 37 | wire [DP_in - 1:0] alphaD_L3_4_0, alphaD_L3_4_1, alphaD_L3_4_2, alphaD_L3_4_3, alphaD_L3_4_4; 38 | wire [DP_in - 1:0] alphaD_L3_5_0, alphaD_L3_5_1, alphaD_L3_5_2, alphaD_L3_5_3, alphaD_L3_5_4; 39 | wire [DP_in - 1:0] alphaD_L3_6_0, alphaD_L3_6_1, alphaD_L3_6_2, alphaD_L3_6_3, alphaD_L3_6_4; 40 | wire [DP_in - 1:0] alphaD_L3_7_0, alphaD_L3_7_1, alphaD_L3_7_2, alphaD_L3_7_3, alphaD_L3_7_4; 41 | wire [DP_in - 1:0] betaD_L3_0, betaD_L3_1, betaD_L3_2, betaD_L3_3, betaD_L3_4; 42 | -------------------------------------------------------------------------------- /FullyConnectedSNN/RN_SEED_Declarations.v: -------------------------------------------------------------------------------- 1 | wire [DP_in - 1:0] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456; 2 | wire [DP_in - 1:0] R0_ADDSUB_FP_netPar0, R1_ADDSUB_FP_netPar0, R2_ADDSUB_FP_netPar0, R3_ADDSUB_FP_netPar0, R4_ADDSUB_FP_netPar0, R5_ADDSUB_FP_netPar0, R6_ADDSUB_FP_netPar0, R7_ADDSUB_FP_netPar0, R8_ADDSUB_FP_netPar0; 3 | wire [DP_in - 1:0] R0_ADDSUB_FP_netPar1, R1_ADDSUB_FP_netPar1, R2_ADDSUB_FP_netPar1, R3_ADDSUB_FP_netPar1, R4_ADDSUB_FP_netPar1, R5_ADDSUB_FP_netPar1, R6_ADDSUB_FP_netPar1, R7_ADDSUB_FP_netPar1, R8_ADDSUB_FP_netPar1; 4 | wire [DP_in - 1:0] R0_ADDSUB_FP_netPar2, R1_ADDSUB_FP_netPar2, R2_ADDSUB_FP_netPar2, R3_ADDSUB_FP_netPar2, R4_ADDSUB_FP_netPar2, R5_ADDSUB_FP_netPar2, R6_ADDSUB_FP_netPar2, R7_ADDSUB_FP_netPar2, R8_ADDSUB_FP_netPar2; 5 | wire [DP_in - 1:0] R0_ADDSUB_BP_netPar0, R1_ADDSUB_BP_netPar0, R2_ADDSUB_BP_netPar0, R3_ADDSUB_BP_netPar0, R4_ADDSUB_BP_netPar0, R5_ADDSUB_BP_netPar0, R6_ADDSUB_BP_netPar0, R7_ADDSUB_BP_netPar0, R8_ADDSUB_BP_netPar0; 6 | wire [DP_in - 1:0] R0_ADDSUB_BP_netPar1, R1_ADDSUB_BP_netPar1, R2_ADDSUB_BP_netPar1, R3_ADDSUB_BP_netPar1, R4_ADDSUB_BP_netPar1, R5_ADDSUB_BP_netPar1, R6_ADDSUB_BP_netPar1, R7_ADDSUB_BP_netPar1, R8_ADDSUB_BP_netPar1; 7 | wire [DP_in - 1:0] R0_ADDSUB_BP_netPar2, R1_ADDSUB_BP_netPar2, R2_ADDSUB_BP_netPar2, R3_ADDSUB_BP_netPar2, R4_ADDSUB_BP_netPar2, R5_ADDSUB_BP_netPar2, R6_ADDSUB_BP_netPar2, R7_ADDSUB_BP_netPar2, R8_ADDSUB_BP_netPar2; 8 | wire [DP_in - 1:0] R0_ADDSUB_error_netPar0, R1_ADDSUB_error_netPar0, R2_ADDSUB_error_netPar0; 9 | wire [DP_in - 1:0] R0_ADDSUB_error_netPar1, R1_ADDSUB_error_netPar1, R2_ADDSUB_error_netPar1; 10 | wire [DP_in - 1:0] R0_ADDSUB_error_netPar2, R1_ADDSUB_error_netPar2, R2_ADDSUB_error_netPar2; 11 | wire [DP_in - 1:0] R0_ADDSUB_NETPAR, R1_ADDSUB_NETPAR, R2_ADDSUB_NETPAR, R3_ADDSUB_NETPAR, R4_ADDSUB_NETPAR, R5_ADDSUB_NETPAR, R6_ADDSUB_NETPAR, R7_ADDSUB_NETPAR, R8_ADDSUB_NETPAR, R9_ADDSUB_NETPAR, R10_ADDSUB_NETPAR, R11_ADDSUB_NETPAR, R12_ADDSUB_NETPAR, R13_ADDSUB_NETPAR, R14_ADDSUB_NETPAR, R15_ADDSUB_NETPAR, R16_ADDSUB_NETPAR, R17_ADDSUB_NETPAR, R18_ADDSUB_NETPAR, R19_ADDSUB_NETPAR, R20_ADDSUB_NETPAR, R21_ADDSUB_NETPAR, R22_ADDSUB_NETPAR, R23_ADDSUB_NETPAR, R24_ADDSUB_NETPAR, R25_ADDSUB_NETPAR, R26_ADDSUB_NETPAR, R27_ADDSUB_NETPAR, R28_ADDSUB_NETPAR, R29_ADDSUB_NETPAR, R30_ADDSUB_NETPAR, R31_ADDSUB_NETPAR, R32_ADDSUB_NETPAR, R33_ADDSUB_NETPAR, R34_ADDSUB_NETPAR, R35_ADDSUB_NETPAR, R36_ADDSUB_NETPAR, R37_ADDSUB_NETPAR, R38_ADDSUB_NETPAR, R39_ADDSUB_NETPAR, R40_ADDSUB_NETPAR, R41_ADDSUB_NETPAR, R42_ADDSUB_NETPAR, R43_ADDSUB_NETPAR, R44_ADDSUB_NETPAR, R45_ADDSUB_NETPAR, R46_ADDSUB_NETPAR, R47_ADDSUB_NETPAR, R48_ADDSUB_NETPAR, R49_ADDSUB_NETPAR, R50_ADDSUB_NETPAR; 12 | wire [DP_out - 1:0] R_long0, R_long1, R_long2, R_long3, R_long4, R_long5, R_long6, R_long7, R_long8, R_long9, R_long10, R_long11, R_long12, R_long13, R_long14; 13 | wire [16 - 1:0] SD0, SD1, SD2, SD3, SD4, SD5, SD6, SD7, SD8, SD9, SD10, SD11, SD12, SD13, SD14, SD15, SD16, SD17, SD18, SD19, SD20, SD21, SD22, SD23, SD24, SD25, SD26, SD27, SD28, SD29, SD30, SD31, SD32, SD33, SD34, SD35, SD36, SD37, SD38, SD39, SD40, SD41, SD42, SD43, SD44, SD45, SD46, SD47, SD48, SD49, SD50, SD51, SD52, SD53, SD54, SD55, SD56, SD57, SD58, SD59, SD60, SD61, SD62, SD63, SD64, SD65, SD66, SD67, SD68, SD69, SD70, SD71, SD72, SD73, SD74, SD75, SD76, SD77, SD78, SD79, SD80, SD81, SD82, SD83, SD84, SD85, SD86, SD87, SD88, SD89, SD90, SD91, SD92, SD93, SD94, SD95, SD96, SD97, SD98, SD99, SD100, SD101, SD102, SD103, SD104, SD105, SD106, SD107, SD108, SD109, SD110, SD111, SD112, SD113, SD114, SD115, SD116, SD117, SD118, SD119, SD120, SD121, SD122, SD123, SD124, SD125, SD126, SD127, SD128, SD129, SD130, SD131, SD132, SD133, SD134, SD135, SD136, SD137, SD138, SD139, SD140, SD141, SD142, SD143, SD144, SD145, SD146, SD147, SD148, SD149, SD150, SD151, SD152, SD153, SD154, SD155, SD156, SD157, SD158, SD159, SD160, SD161, SD162, SD163, SD164, SD165, SD166, SD167, SD168, SD169, SD170, SD171, SD172, SD173, SD174, SD175, SD176, SD177, SD178, SD179, SD180, SD181, SD182, SD183, SD184, SD185, SD186, SD187, SD188, SD189, SD190, SD191, SD192, SD193, SD194, SD195, SD196, SD197, SD198, SD199, SD200, SD201, SD202, SD203, SD204, SD205, SD206, SD207, SD208, SD209, SD210, SD211, SD212, SD213, SD214, SD215, SD216, SD217, SD218, SD219, SD220, SD221, SD222, SD223, SD224, SD225, SD226, SD227, SD228, SD229, SD230, SD231, SD232, SD233, SD234, SD235, SD236, SD237, SD238, SD239, SD240, SD241, SD242, SD243, SD244, SD245, SD246, SD247, SD248, SD249, SD250, SD251, SD252, SD253, SD254, SD255, SD256, SD257, SD258, SD259, SD260, SD261, SD262, SD263, SD264, SD265, SD266, SD267, SD268, SD269, SD270, SD271, SD272, SD273, SD274, SD275, SD276, SD277, SD278, SD279; 14 | wire [39-1:0] zeroCenterSource_netPar0; 15 | wire [39-1:0] zeroCenterSource_netPar1; 16 | wire [39-1:0] zeroCenterSource_netPar2; 17 | -------------------------------------------------------------------------------- /FullyConnectedSNN/FWDPROP.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Neural Network Forward Propagation 4 | 5 | module FWDPROP( 6 | alpha_L1_j_0, alpha_L1_j_1, alpha_L1_j_2, alpha_L1_j_3, alpha_L1_j_4, alpha_L1_j_5, alpha_L1_j_6, alpha_L1_j_7, alpha_L1_j_8, alpha_L1_j_9, alpha_L1_j_10, alpha_L1_j_11, alpha_L1_j_12, alpha_L1_j_13, alpha_L1_j_14, alpha_L1_j_15, alpha_L1_j_16, alpha_L1_j_17, alpha_L1_j_18, alpha_L1_j_19, alpha_L1_j_20, alpha_L1_j_21, alpha_L1_j_22, alpha_L1_j_23, alpha_L1_j_24, 7 | beta_L1, 8 | alpha_L2_j_0, alpha_L2_j_1, alpha_L2_j_2, alpha_L2_j_3, alpha_L2_j_4, alpha_L2_j_5, alpha_L2_j_6, alpha_L2_j_7, 9 | beta_L2, 10 | alpha_L3_j_0, alpha_L3_j_1, alpha_L3_j_2, alpha_L3_j_3, alpha_L3_j_4, 11 | beta_L3, 12 | SIGN_alpha_L1_j_0, SIGN_alpha_L1_j_1, SIGN_alpha_L1_j_2, SIGN_alpha_L1_j_3, SIGN_alpha_L1_j_4, SIGN_alpha_L1_j_5, SIGN_alpha_L1_j_6, SIGN_alpha_L1_j_7, SIGN_alpha_L1_j_8, SIGN_alpha_L1_j_9, SIGN_alpha_L1_j_10, SIGN_alpha_L1_j_11, SIGN_alpha_L1_j_12, SIGN_alpha_L1_j_13, SIGN_alpha_L1_j_14, SIGN_alpha_L1_j_15, SIGN_alpha_L1_j_16, SIGN_alpha_L1_j_17, SIGN_alpha_L1_j_18, SIGN_alpha_L1_j_19, SIGN_alpha_L1_j_20, SIGN_alpha_L1_j_21, SIGN_alpha_L1_j_22, SIGN_alpha_L1_j_23, SIGN_alpha_L1_j_24, 13 | SIGN_beta_L1, 14 | SIGN_alpha_L2_j_0, SIGN_alpha_L2_j_1, SIGN_alpha_L2_j_2, SIGN_alpha_L2_j_3, SIGN_alpha_L2_j_4, SIGN_alpha_L2_j_5, SIGN_alpha_L2_j_6, SIGN_alpha_L2_j_7, 15 | SIGN_beta_L2, 16 | SIGN_alpha_L3_j_0, SIGN_alpha_L3_j_1, SIGN_alpha_L3_j_2, SIGN_alpha_L3_j_3, SIGN_alpha_L3_j_4, 17 | SIGN_beta_L3, 18 | R_FP0, R_FP1, R_FP2, R_FP3, R_FP4, R_FP5, R_FP6, R_FP7, R_FP8, 19 | zeroCenterSource, 20 | a_L0, 21 | a_L1, 22 | a_L2, 23 | a_L3, 24 | z_L0, 25 | z_L1, 26 | z_L2, 27 | z_L3, 28 | zp_L0, 29 | zp_L1, 30 | zp_L2, 31 | zp_L3, 32 | a_MEM_ACTIVE_L1, 33 | a_MEM_ACTIVE_L2, 34 | a_MEM_ACTIVE_L3, 35 | CLK, INIT, CLK_TRAINING_flag 36 | ); 37 | 38 | parameter MEMSIZE = 3; 39 | parameter DP_in = 8; 40 | parameter DP_out = 16; 41 | 42 | input wire CLK, INIT, CLK_TRAINING_flag; 43 | input wire [5 - 1:0] alpha_L1_j_0, alpha_L1_j_1, alpha_L1_j_2, alpha_L1_j_3, alpha_L1_j_4, alpha_L1_j_5, alpha_L1_j_6, alpha_L1_j_7, alpha_L1_j_8, alpha_L1_j_9, alpha_L1_j_10, alpha_L1_j_11, alpha_L1_j_12, alpha_L1_j_13, alpha_L1_j_14, alpha_L1_j_15, alpha_L1_j_16, alpha_L1_j_17, alpha_L1_j_18, alpha_L1_j_19, alpha_L1_j_20, alpha_L1_j_21, alpha_L1_j_22, alpha_L1_j_23, alpha_L1_j_24; 44 | input wire [25 - 1:0] beta_L1; 45 | input wire [25 - 1:0] alpha_L2_j_0, alpha_L2_j_1, alpha_L2_j_2, alpha_L2_j_3, alpha_L2_j_4, alpha_L2_j_5, alpha_L2_j_6, alpha_L2_j_7; 46 | input wire [8 - 1:0] beta_L2; 47 | input wire [8 - 1:0] alpha_L3_j_0, alpha_L3_j_1, alpha_L3_j_2, alpha_L3_j_3, alpha_L3_j_4; 48 | input wire [5 - 1:0] beta_L3; 49 | input wire [5 - 1:0] SIGN_alpha_L1_j_0, SIGN_alpha_L1_j_1, SIGN_alpha_L1_j_2, SIGN_alpha_L1_j_3, SIGN_alpha_L1_j_4, SIGN_alpha_L1_j_5, SIGN_alpha_L1_j_6, SIGN_alpha_L1_j_7, SIGN_alpha_L1_j_8, SIGN_alpha_L1_j_9, SIGN_alpha_L1_j_10, SIGN_alpha_L1_j_11, SIGN_alpha_L1_j_12, SIGN_alpha_L1_j_13, SIGN_alpha_L1_j_14, SIGN_alpha_L1_j_15, SIGN_alpha_L1_j_16, SIGN_alpha_L1_j_17, SIGN_alpha_L1_j_18, SIGN_alpha_L1_j_19, SIGN_alpha_L1_j_20, SIGN_alpha_L1_j_21, SIGN_alpha_L1_j_22, SIGN_alpha_L1_j_23, SIGN_alpha_L1_j_24; 50 | input wire [25 - 1:0] SIGN_beta_L1; 51 | input wire [25 - 1:0] SIGN_alpha_L2_j_0, SIGN_alpha_L2_j_1, SIGN_alpha_L2_j_2, SIGN_alpha_L2_j_3, SIGN_alpha_L2_j_4, SIGN_alpha_L2_j_5, SIGN_alpha_L2_j_6, SIGN_alpha_L2_j_7; 52 | input wire [8 - 1:0] SIGN_beta_L2; 53 | input wire [8 - 1:0] SIGN_alpha_L3_j_0, SIGN_alpha_L3_j_1, SIGN_alpha_L3_j_2, SIGN_alpha_L3_j_3, SIGN_alpha_L3_j_4; 54 | input wire [5 - 1:0] SIGN_beta_L3; 55 | input wire [5 - 1:0] a_L0; 56 | output wire [25 - 1:0] a_L1; 57 | output wire [8 - 1:0] a_L2; 58 | output wire [5 - 1:0] a_L3; 59 | output wire [5 - 1:0] z_L0; 60 | output wire [25 - 1:0] z_L1; 61 | output wire [8 - 1:0] z_L2; 62 | output wire [5 - 1:0] z_L3; 63 | output wire [5 - 1:0] zp_L0; 64 | output wire [25 - 1:0] zp_L1; 65 | output wire [8 - 1:0] zp_L2; 66 | output wire [5 - 1:0] zp_L3; 67 | input wire [25 - 1:0] a_MEM_ACTIVE_L1; 68 | input wire [8 - 1:0] a_MEM_ACTIVE_L2; 69 | input wire [5 - 1:0] a_MEM_ACTIVE_L3; 70 | input wire [7:0] R_FP0, R_FP1, R_FP2, R_FP3, R_FP4, R_FP5, R_FP6, R_FP7, R_FP8; 71 | input wire [39-1:0] zeroCenterSource; 72 | 73 | wire [8:0] R_FP_source; 74 | 75 | 76 | DEC2STCH DSRFP0(.CLK(CLK), .INIT(INIT), .D(8'd127),.LFSR(R_FP0),.S(R_FP_source[0])); 77 | DEC2STCH DSRFP1(.CLK(CLK), .INIT(INIT), .D(8'd127),.LFSR(R_FP1),.S(R_FP_source[1])); 78 | DEC2STCH DSRFP2(.CLK(CLK), .INIT(INIT), .D(8'd127),.LFSR(R_FP2),.S(R_FP_source[2])); 79 | 80 | FULLCONNBLOCK_L1 FULLCONNBLOCK_L1_0( 81 | .a_input(a_L0), 82 | .a_MEM_ACTIVE(a_MEM_ACTIVE_L1), 83 | .alpha_j_0(alpha_L1_j_0), .alpha_j_1(alpha_L1_j_1), .alpha_j_2(alpha_L1_j_2), .alpha_j_3(alpha_L1_j_3), .alpha_j_4(alpha_L1_j_4), .alpha_j_5(alpha_L1_j_5), .alpha_j_6(alpha_L1_j_6), .alpha_j_7(alpha_L1_j_7), .alpha_j_8(alpha_L1_j_8), .alpha_j_9(alpha_L1_j_9), .alpha_j_10(alpha_L1_j_10), .alpha_j_11(alpha_L1_j_11), .alpha_j_12(alpha_L1_j_12), .alpha_j_13(alpha_L1_j_13), .alpha_j_14(alpha_L1_j_14), .alpha_j_15(alpha_L1_j_15), .alpha_j_16(alpha_L1_j_16), .alpha_j_17(alpha_L1_j_17), .alpha_j_18(alpha_L1_j_18), .alpha_j_19(alpha_L1_j_19), .alpha_j_20(alpha_L1_j_20), .alpha_j_21(alpha_L1_j_21), .alpha_j_22(alpha_L1_j_22), .alpha_j_23(alpha_L1_j_23), .alpha_j_24(alpha_L1_j_24), 84 | .beta(beta_L1), 85 | .SIGN_alpha_j_0(SIGN_alpha_L1_j_0), .SIGN_alpha_j_1(SIGN_alpha_L1_j_1), .SIGN_alpha_j_2(SIGN_alpha_L1_j_2), .SIGN_alpha_j_3(SIGN_alpha_L1_j_3), .SIGN_alpha_j_4(SIGN_alpha_L1_j_4), .SIGN_alpha_j_5(SIGN_alpha_L1_j_5), .SIGN_alpha_j_6(SIGN_alpha_L1_j_6), .SIGN_alpha_j_7(SIGN_alpha_L1_j_7), .SIGN_alpha_j_8(SIGN_alpha_L1_j_8), .SIGN_alpha_j_9(SIGN_alpha_L1_j_9), .SIGN_alpha_j_10(SIGN_alpha_L1_j_10), .SIGN_alpha_j_11(SIGN_alpha_L1_j_11), .SIGN_alpha_j_12(SIGN_alpha_L1_j_12), .SIGN_alpha_j_13(SIGN_alpha_L1_j_13), .SIGN_alpha_j_14(SIGN_alpha_L1_j_14), .SIGN_alpha_j_15(SIGN_alpha_L1_j_15), .SIGN_alpha_j_16(SIGN_alpha_L1_j_16), .SIGN_alpha_j_17(SIGN_alpha_L1_j_17), .SIGN_alpha_j_18(SIGN_alpha_L1_j_18), .SIGN_alpha_j_19(SIGN_alpha_L1_j_19), .SIGN_alpha_j_20(SIGN_alpha_L1_j_20), .SIGN_alpha_j_21(SIGN_alpha_L1_j_21), .SIGN_alpha_j_22(SIGN_alpha_L1_j_22), .SIGN_alpha_j_23(SIGN_alpha_L1_j_23), .SIGN_alpha_j_24(SIGN_alpha_L1_j_24), 86 | .SIGN_beta(SIGN_beta_L1), 87 | .z(z_L1), 88 | .zp(zp_L1), 89 | .a_out(a_L1), 90 | .R_FPsource(R_FP_source[0]), .zeroCenterSource(zeroCenterSource[0]), 91 | .CLK(CLK), .INIT(INIT), .CLK_TRAINING_flag(CLK_TRAINING_flag) 92 | ); 93 | 94 | FULLCONNBLOCK_L2 FULLCONNBLOCK_L2_0( 95 | .a_input(a_L1), 96 | .a_MEM_ACTIVE(a_MEM_ACTIVE_L2), 97 | .alpha_j_0(alpha_L2_j_0), .alpha_j_1(alpha_L2_j_1), .alpha_j_2(alpha_L2_j_2), .alpha_j_3(alpha_L2_j_3), .alpha_j_4(alpha_L2_j_4), .alpha_j_5(alpha_L2_j_5), .alpha_j_6(alpha_L2_j_6), .alpha_j_7(alpha_L2_j_7), 98 | .beta(beta_L2), 99 | .SIGN_alpha_j_0(SIGN_alpha_L2_j_0), .SIGN_alpha_j_1(SIGN_alpha_L2_j_1), .SIGN_alpha_j_2(SIGN_alpha_L2_j_2), .SIGN_alpha_j_3(SIGN_alpha_L2_j_3), .SIGN_alpha_j_4(SIGN_alpha_L2_j_4), .SIGN_alpha_j_5(SIGN_alpha_L2_j_5), .SIGN_alpha_j_6(SIGN_alpha_L2_j_6), .SIGN_alpha_j_7(SIGN_alpha_L2_j_7), 100 | .SIGN_beta(SIGN_beta_L2), 101 | .z(z_L2), 102 | .zp(zp_L2), 103 | .a_out(a_L2), 104 | .R_FPsource(R_FP_source[1]), .zeroCenterSource(zeroCenterSource[1]), 105 | .CLK(CLK), .INIT(INIT), .CLK_TRAINING_flag(CLK_TRAINING_flag) 106 | ); 107 | 108 | FULLCONNBLOCK_L3 FULLCONNBLOCK_L3_0( 109 | .a_input(a_L2), 110 | .a_MEM_ACTIVE(a_MEM_ACTIVE_L3), 111 | .alpha_j_0(alpha_L3_j_0), .alpha_j_1(alpha_L3_j_1), .alpha_j_2(alpha_L3_j_2), .alpha_j_3(alpha_L3_j_3), .alpha_j_4(alpha_L3_j_4), 112 | .beta(beta_L3), 113 | .SIGN_alpha_j_0(SIGN_alpha_L3_j_0), .SIGN_alpha_j_1(SIGN_alpha_L3_j_1), .SIGN_alpha_j_2(SIGN_alpha_L3_j_2), .SIGN_alpha_j_3(SIGN_alpha_L3_j_3), .SIGN_alpha_j_4(SIGN_alpha_L3_j_4), 114 | .SIGN_beta(SIGN_beta_L3), 115 | .z(z_L3), 116 | .zp(zp_L3), 117 | .a_out(a_L3), 118 | .R_FPsource(R_FP_source[2]), .zeroCenterSource(zeroCenterSource[2]), 119 | .CLK(CLK), .INIT(INIT), .CLK_TRAINING_flag(CLK_TRAINING_flag) 120 | ); 121 | 122 | 123 | endmodule 124 | -------------------------------------------------------------------------------- /FullyConnectedSNN/DECC.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | module DECC( 4 | a_L1, 5 | a_L2, 6 | a_L3, 7 | aD_L1_0, aD_L1_1, aD_L1_2, aD_L1_3, aD_L1_4, aD_L1_5, aD_L1_6, aD_L1_7, aD_L1_8, aD_L1_9, aD_L1_10, aD_L1_11, aD_L1_12, aD_L1_13, aD_L1_14, aD_L1_15, aD_L1_16, aD_L1_17, aD_L1_18, aD_L1_19, aD_L1_20, aD_L1_21, aD_L1_22, aD_L1_23, aD_L1_24, 8 | aD_L2_0, aD_L2_1, aD_L2_2, aD_L2_3, aD_L2_4, aD_L2_5, aD_L2_6, aD_L2_7, 9 | aD_L3_0, aD_L3_1, aD_L3_2, aD_L3_3, aD_L3_4, 10 | NodeOutputExp_clk, NodeOutputExp_index, NodeOutputExp_data, 11 | CLK, BP_FRAME, pre_BP_FRAME, FP_FRAME, pre_FP_FRAME, INIT 12 | ); 13 | 14 | parameter DP_in = 8; 15 | parameter DP_out = 16; 16 | 17 | input wire [25 - 1:0] a_L1; 18 | input wire [8 - 1:0] a_L2; 19 | input wire [5 - 1:0] a_L3; 20 | input NodeOutputExp_clk; 21 | input [15:0] NodeOutputExp_index; 22 | input wire CLK, BP_FRAME, pre_BP_FRAME, FP_FRAME, pre_FP_FRAME, INIT; 23 | 24 | // Outputs: 25 | output reg [15:0] NodeOutputExp_data; 26 | 27 | output wire [DP_out - 1:0] aD_L1_0, aD_L1_1, aD_L1_2, aD_L1_3, aD_L1_4, aD_L1_5, aD_L1_6, aD_L1_7, aD_L1_8, aD_L1_9, aD_L1_10, aD_L1_11, aD_L1_12, aD_L1_13, aD_L1_14, aD_L1_15, aD_L1_16, aD_L1_17, aD_L1_18, aD_L1_19, aD_L1_20, aD_L1_21, aD_L1_22, aD_L1_23, aD_L1_24; 28 | output wire [DP_out - 1:0] aD_L2_0, aD_L2_1, aD_L2_2, aD_L2_3, aD_L2_4, aD_L2_5, aD_L2_6, aD_L2_7; 29 | output wire [DP_out - 1:0] aD_L3_0, aD_L3_1, aD_L3_2, aD_L3_3, aD_L3_4; 30 | MEAN MEANa_L1_0(.in(a_L1[0]), .out(aD_L1_0), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 31 | MEAN MEANa_L1_1(.in(a_L1[1]), .out(aD_L1_1), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 32 | MEAN MEANa_L1_2(.in(a_L1[2]), .out(aD_L1_2), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 33 | MEAN MEANa_L1_3(.in(a_L1[3]), .out(aD_L1_3), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 34 | MEAN MEANa_L1_4(.in(a_L1[4]), .out(aD_L1_4), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 35 | MEAN MEANa_L1_5(.in(a_L1[5]), .out(aD_L1_5), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 36 | MEAN MEANa_L1_6(.in(a_L1[6]), .out(aD_L1_6), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 37 | MEAN MEANa_L1_7(.in(a_L1[7]), .out(aD_L1_7), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 38 | MEAN MEANa_L1_8(.in(a_L1[8]), .out(aD_L1_8), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 39 | MEAN MEANa_L1_9(.in(a_L1[9]), .out(aD_L1_9), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 40 | MEAN MEANa_L1_10(.in(a_L1[10]), .out(aD_L1_10), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 41 | MEAN MEANa_L1_11(.in(a_L1[11]), .out(aD_L1_11), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 42 | MEAN MEANa_L1_12(.in(a_L1[12]), .out(aD_L1_12), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 43 | MEAN MEANa_L1_13(.in(a_L1[13]), .out(aD_L1_13), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 44 | MEAN MEANa_L1_14(.in(a_L1[14]), .out(aD_L1_14), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 45 | MEAN MEANa_L1_15(.in(a_L1[15]), .out(aD_L1_15), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 46 | MEAN MEANa_L1_16(.in(a_L1[16]), .out(aD_L1_16), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 47 | MEAN MEANa_L1_17(.in(a_L1[17]), .out(aD_L1_17), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 48 | MEAN MEANa_L1_18(.in(a_L1[18]), .out(aD_L1_18), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 49 | MEAN MEANa_L1_19(.in(a_L1[19]), .out(aD_L1_19), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 50 | MEAN MEANa_L1_20(.in(a_L1[20]), .out(aD_L1_20), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 51 | MEAN MEANa_L1_21(.in(a_L1[21]), .out(aD_L1_21), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 52 | MEAN MEANa_L1_22(.in(a_L1[22]), .out(aD_L1_22), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 53 | MEAN MEANa_L1_23(.in(a_L1[23]), .out(aD_L1_23), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 54 | MEAN MEANa_L1_24(.in(a_L1[24]), .out(aD_L1_24), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 55 | defparam MEANa_L1_0.N_Count = DP_out; 56 | defparam MEANa_L1_1.N_Count = DP_out; 57 | defparam MEANa_L1_2.N_Count = DP_out; 58 | defparam MEANa_L1_3.N_Count = DP_out; 59 | defparam MEANa_L1_4.N_Count = DP_out; 60 | defparam MEANa_L1_5.N_Count = DP_out; 61 | defparam MEANa_L1_6.N_Count = DP_out; 62 | defparam MEANa_L1_7.N_Count = DP_out; 63 | defparam MEANa_L1_8.N_Count = DP_out; 64 | defparam MEANa_L1_9.N_Count = DP_out; 65 | defparam MEANa_L1_10.N_Count = DP_out; 66 | defparam MEANa_L1_11.N_Count = DP_out; 67 | defparam MEANa_L1_12.N_Count = DP_out; 68 | defparam MEANa_L1_13.N_Count = DP_out; 69 | defparam MEANa_L1_14.N_Count = DP_out; 70 | defparam MEANa_L1_15.N_Count = DP_out; 71 | defparam MEANa_L1_16.N_Count = DP_out; 72 | defparam MEANa_L1_17.N_Count = DP_out; 73 | defparam MEANa_L1_18.N_Count = DP_out; 74 | defparam MEANa_L1_19.N_Count = DP_out; 75 | defparam MEANa_L1_20.N_Count = DP_out; 76 | defparam MEANa_L1_21.N_Count = DP_out; 77 | defparam MEANa_L1_22.N_Count = DP_out; 78 | defparam MEANa_L1_23.N_Count = DP_out; 79 | defparam MEANa_L1_24.N_Count = DP_out; 80 | 81 | MEAN MEANa_L2_0(.in(a_L2[0]), .out(aD_L2_0), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 82 | MEAN MEANa_L2_1(.in(a_L2[1]), .out(aD_L2_1), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 83 | MEAN MEANa_L2_2(.in(a_L2[2]), .out(aD_L2_2), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 84 | MEAN MEANa_L2_3(.in(a_L2[3]), .out(aD_L2_3), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 85 | MEAN MEANa_L2_4(.in(a_L2[4]), .out(aD_L2_4), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 86 | MEAN MEANa_L2_5(.in(a_L2[5]), .out(aD_L2_5), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 87 | MEAN MEANa_L2_6(.in(a_L2[6]), .out(aD_L2_6), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 88 | MEAN MEANa_L2_7(.in(a_L2[7]), .out(aD_L2_7), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 89 | defparam MEANa_L2_0.N_Count = DP_out; 90 | defparam MEANa_L2_1.N_Count = DP_out; 91 | defparam MEANa_L2_2.N_Count = DP_out; 92 | defparam MEANa_L2_3.N_Count = DP_out; 93 | defparam MEANa_L2_4.N_Count = DP_out; 94 | defparam MEANa_L2_5.N_Count = DP_out; 95 | defparam MEANa_L2_6.N_Count = DP_out; 96 | defparam MEANa_L2_7.N_Count = DP_out; 97 | 98 | MEAN MEANa_L3_0(.in(a_L3[0]), .out(aD_L3_0), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 99 | MEAN MEANa_L3_1(.in(a_L3[1]), .out(aD_L3_1), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 100 | MEAN MEANa_L3_2(.in(a_L3[2]), .out(aD_L3_2), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 101 | MEAN MEANa_L3_3(.in(a_L3[3]), .out(aD_L3_3), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 102 | MEAN MEANa_L3_4(.in(a_L3[4]), .out(aD_L3_4), .START(16'd0),.RESET(FP_FRAME),.CLK(CLK),.INIT(INIT),.ENABLE(1'b1), .preRESET(pre_FP_FRAME)); 103 | defparam MEANa_L3_0.N_Count = DP_out; 104 | defparam MEANa_L3_1.N_Count = DP_out; 105 | defparam MEANa_L3_2.N_Count = DP_out; 106 | defparam MEANa_L3_3.N_Count = DP_out; 107 | defparam MEANa_L3_4.N_Count = DP_out; 108 | 109 | always @(posedge NodeOutputExp_clk) begin 110 | case (NodeOutputExp_index) 111 | 16'd0: NodeOutputExp_data = aD_L1_0; 112 | 16'd1: NodeOutputExp_data = aD_L1_1; 113 | 16'd2: NodeOutputExp_data = aD_L1_2; 114 | 16'd3: NodeOutputExp_data = aD_L1_3; 115 | 16'd4: NodeOutputExp_data = aD_L1_4; 116 | 16'd5: NodeOutputExp_data = aD_L1_5; 117 | 16'd6: NodeOutputExp_data = aD_L1_6; 118 | 16'd7: NodeOutputExp_data = aD_L1_7; 119 | 16'd8: NodeOutputExp_data = aD_L1_8; 120 | 16'd9: NodeOutputExp_data = aD_L1_9; 121 | 16'd10: NodeOutputExp_data = aD_L1_10; 122 | 16'd11: NodeOutputExp_data = aD_L1_11; 123 | 16'd12: NodeOutputExp_data = aD_L1_12; 124 | 16'd13: NodeOutputExp_data = aD_L1_13; 125 | 16'd14: NodeOutputExp_data = aD_L1_14; 126 | 16'd15: NodeOutputExp_data = aD_L1_15; 127 | 16'd16: NodeOutputExp_data = aD_L1_16; 128 | 16'd17: NodeOutputExp_data = aD_L1_17; 129 | 16'd18: NodeOutputExp_data = aD_L1_18; 130 | 16'd19: NodeOutputExp_data = aD_L1_19; 131 | 16'd20: NodeOutputExp_data = aD_L1_20; 132 | 16'd21: NodeOutputExp_data = aD_L1_21; 133 | 16'd22: NodeOutputExp_data = aD_L1_22; 134 | 16'd23: NodeOutputExp_data = aD_L1_23; 135 | 16'd24: NodeOutputExp_data = aD_L1_24; 136 | 16'd25: NodeOutputExp_data = aD_L2_0; 137 | 16'd26: NodeOutputExp_data = aD_L2_1; 138 | 16'd27: NodeOutputExp_data = aD_L2_2; 139 | 16'd28: NodeOutputExp_data = aD_L2_3; 140 | 16'd29: NodeOutputExp_data = aD_L2_4; 141 | 16'd30: NodeOutputExp_data = aD_L2_5; 142 | 16'd31: NodeOutputExp_data = aD_L2_6; 143 | 16'd32: NodeOutputExp_data = aD_L2_7; 144 | 16'd33: NodeOutputExp_data = aD_L3_0; 145 | 16'd34: NodeOutputExp_data = aD_L3_1; 146 | 16'd35: NodeOutputExp_data = aD_L3_2; 147 | 16'd36: NodeOutputExp_data = aD_L3_3; 148 | 16'd37: NodeOutputExp_data = aD_L3_4; 149 | default: NodeOutputExp_data = 1'b0; 150 | 151 | endcase 152 | end 153 | 154 | 155 | endmodule 156 | -------------------------------------------------------------------------------- /FullyConnectedSNN/RNE_portDefinitions.v: -------------------------------------------------------------------------------- 1 | .S0(SD0), .S1(SD1), .S2(SD2), .S3(SD3), .S4(SD4), .S5(SD5), .S6(SD6), .S7(SD7), .S8(SD8), .S9(SD9), .S10(SD10), .S11(SD11), .S12(SD12), .S13(SD13), .S14(SD14), .S15(SD15), .S16(SD16), .S17(SD17), .S18(SD18), .S19(SD19), .S20(SD20), .S21(SD21), .S22(SD22), .S23(SD23), .S24(SD24), .S25(SD25), .S26(SD26), .S27(SD27), .S28(SD28), .S29(SD29), .S30(SD30), .S31(SD31), .S32(SD32), .S33(SD33), .S34(SD34), .S35(SD35), .S36(SD36), .S37(SD37), .S38(SD38), .S39(SD39), .S40(SD40), .S41(SD41), .S42(SD42), .S43(SD43), .S44(SD44), .S45(SD45), .S46(SD46), .S47(SD47), .S48(SD48), .S49(SD49), .S50(SD50), .S51(SD51), .S52(SD52), .S53(SD53), .S54(SD54), .S55(SD55), .S56(SD56), .S57(SD57), .S58(SD58), .S59(SD59), .S60(SD60), .S61(SD61), .S62(SD62), .S63(SD63), .S64(SD64), .S65(SD65), .S66(SD66), .S67(SD67), .S68(SD68), .S69(SD69), .S70(SD70), .S71(SD71), .S72(SD72), .S73(SD73), .S74(SD74), .S75(SD75), .S76(SD76), .S77(SD77), .S78(SD78), .S79(SD79), .S80(SD80), .S81(SD81), .S82(SD82), .S83(SD83), .S84(SD84), .S85(SD85), .S86(SD86), .S87(SD87), .S88(SD88), .S89(SD89), .S90(SD90), .S91(SD91), .S92(SD92), .S93(SD93), .S94(SD94), .S95(SD95), .S96(SD96), .S97(SD97), .S98(SD98), .S99(SD99), .S100(SD100), .S101(SD101), .S102(SD102), .S103(SD103), .S104(SD104), .S105(SD105), .S106(SD106), .S107(SD107), .S108(SD108), .S109(SD109), .S110(SD110), .S111(SD111), .S112(SD112), .S113(SD113), .S114(SD114), .S115(SD115), .S116(SD116), .S117(SD117), .S118(SD118), .S119(SD119), .S120(SD120), .S121(SD121), .S122(SD122), .S123(SD123), .S124(SD124), .S125(SD125), .S126(SD126), .S127(SD127), .S128(SD128), .S129(SD129), .S130(SD130), .S131(SD131), .S132(SD132), .S133(SD133), .S134(SD134), .S135(SD135), .S136(SD136), .S137(SD137), .S138(SD138), .S139(SD139), .S140(SD140), .S141(SD141), .S142(SD142), .S143(SD143), .S144(SD144), .S145(SD145), .S146(SD146), .S147(SD147), .S148(SD148), .S149(SD149), .S150(SD150), .S151(SD151), .S152(SD152), .S153(SD153), .S154(SD154), .S155(SD155), .S156(SD156), .S157(SD157), .S158(SD158), .S159(SD159), .S160(SD160), .S161(SD161), .S162(SD162), .S163(SD163), .S164(SD164), .S165(SD165), .S166(SD166), .S167(SD167), .S168(SD168), .S169(SD169), .S170(SD170), .S171(SD171), .S172(SD172), .S173(SD173), .S174(SD174), .S175(SD175), .S176(SD176), .S177(SD177), .S178(SD178), .S179(SD179), .S180(SD180), .S181(SD181), .S182(SD182), .S183(SD183), .S184(SD184), .S185(SD185), .S186(SD186), .S187(SD187), .S188(SD188), .S189(SD189), .S190(SD190), .S191(SD191), .S192(SD192), .S193(SD193), .S194(SD194), .S195(SD195), .S196(SD196), .S197(SD197), .S198(SD198), .S199(SD199), .S200(SD200), .S201(SD201), .S202(SD202), .S203(SD203), .S204(SD204), .S205(SD205), .S206(SD206), .S207(SD207), .S208(SD208), .S209(SD209), .S210(SD210), .S211(SD211), .S212(SD212), .S213(SD213), .S214(SD214), .S215(SD215), .S216(SD216), .S217(SD217), .S218(SD218), .S219(SD219), .S220(SD220), .S221(SD221), .S222(SD222), .S223(SD223), .S224(SD224), .S225(SD225), .S226(SD226), .S227(SD227), .S228(SD228), .S229(SD229), .S230(SD230), .S231(SD231), .S232(SD232), .S233(SD233), .S234(SD234), .S235(SD235), .S236(SD236), .S237(SD237), .S238(SD238), .S239(SD239), .S240(SD240), .S241(SD241), .S242(SD242), .S243(SD243), .S244(SD244), .S245(SD245), .S246(SD246), .S247(SD247), .S248(SD248), .S249(SD249), .S250(SD250), .S251(SD251), .S252(SD252), .S253(SD253), .S254(SD254), .S255(SD255), .S256(SD256), .S257(SD257), .S258(SD258), .S259(SD259), .S260(SD260), .S261(SD261), .S262(SD262), .S263(SD263), .S264(SD264), .S265(SD265), .S266(SD266), .S267(SD267), .S268(SD268), .S269(SD269), .S270(SD270), .S271(SD271), .S272(SD272), .S273(SD273), .S274(SD274), .S275(SD275), .S276(SD276), .S277(SD277), .S278(SD278), .S279(SD279), 2 | .R0(R0), .R1(R1), .R2(R2), .R3(R3), .R4(R4), .R5(R5), .R6(R6), .R7(R7), .R8(R8), .R9(R9), .R10(R10), .R11(R11), .R12(R12), .R13(R13), .R14(R14), .R15(R15), .R16(R16), .R17(R17), .R18(R18), .R19(R19), .R20(R20), .R21(R21), .R22(R22), .R23(R23), .R24(R24), .R25(R25), .R26(R26), .R27(R27), .R28(R28), .R29(R29), .R30(R30), .R31(R31), .R32(R32), .R33(R33), .R34(R34), .R35(R35), .R36(R36), .R37(R37), .R38(R38), .R39(R39), .R40(R40), .R41(R41), .R42(R42), .R43(R43), .R44(R44), .R45(R45), .R46(R46), .R47(R47), .R48(R48), .R49(R49), .R50(R50), .R51(R51), .R52(R52), .R53(R53), .R54(R54), .R55(R55), .R56(R56), .R57(R57), .R58(R58), .R59(R59), .R60(R60), .R61(R61), .R62(R62), .R63(R63), .R64(R64), .R65(R65), .R66(R66), .R67(R67), .R68(R68), .R69(R69), .R70(R70), .R71(R71), .R72(R72), .R73(R73), .R74(R74), .R75(R75), .R76(R76), .R77(R77), .R78(R78), .R79(R79), .R80(R80), .R81(R81), .R82(R82), .R83(R83), .R84(R84), .R85(R85), .R86(R86), .R87(R87), .R88(R88), .R89(R89), .R90(R90), .R91(R91), .R92(R92), .R93(R93), .R94(R94), .R95(R95), .R96(R96), .R97(R97), .R98(R98), .R99(R99), .R100(R100), .R101(R101), .R102(R102), .R103(R103), .R104(R104), .R105(R105), .R106(R106), .R107(R107), .R108(R108), .R109(R109), .R110(R110), .R111(R111), .R112(R112), .R113(R113), .R114(R114), .R115(R115), .R116(R116), .R117(R117), .R118(R118), .R119(R119), .R120(R120), .R121(R121), .R122(R122), .R123(R123), .R124(R124), .R125(R125), .R126(R126), .R127(R127), .R128(R128), .R129(R129), .R130(R130), .R131(R131), .R132(R132), .R133(R133), .R134(R134), .R135(R135), .R136(R136), .R137(R137), .R138(R138), .R139(R139), .R140(R140), .R141(R141), .R142(R142), .R143(R143), .R144(R144), .R145(R145), .R146(R146), .R147(R147), .R148(R148), .R149(R149), .R150(R150), .R151(R151), .R152(R152), .R153(R153), .R154(R154), .R155(R155), .R156(R156), .R157(R157), .R158(R158), .R159(R159), .R160(R160), .R161(R161), .R162(R162), .R163(R163), .R164(R164), .R165(R165), .R166(R166), .R167(R167), .R168(R168), .R169(R169), .R170(R170), .R171(R171), .R172(R172), .R173(R173), .R174(R174), .R175(R175), .R176(R176), .R177(R177), .R178(R178), .R179(R179), .R180(R180), .R181(R181), .R182(R182), .R183(R183), .R184(R184), .R185(R185), .R186(R186), .R187(R187), .R188(R188), .R189(R189), .R190(R190), .R191(R191), .R192(R192), .R193(R193), .R194(R194), .R195(R195), .R196(R196), .R197(R197), .R198(R198), .R199(R199), .R200(R200), .R201(R201), .R202(R202), .R203(R203), .R204(R204), .R205(R205), .R206(R206), .R207(R207), .R208(R208), .R209(R209), .R210(R210), .R211(R211), .R212(R212), .R213(R213), .R214(R214), .R215(R215), .R216(R216), .R217(R217), .R218(R218), .R219(R219), .R220(R220), .R221(R221), .R222(R222), .R223(R223), .R224(R224), .R225(R225), .R226(R226), .R227(R227), .R228(R228), .R229(R229), .R230(R230), .R231(R231), .R232(R232), .R233(R233), .R234(R234), .R235(R235), .R236(R236), .R237(R237), .R238(R238), .R239(R239), .R240(R240), .R241(R241), .R242(R242), .R243(R243), .R244(R244), .R245(R245), .R246(R246), .R247(R247), .R248(R248), .R249(R249), .R250(R250), .R251(R251), .R252(R252), .R253(R253), .R254(R254), .R255(R255), .R256(R256), .R257(R257), .R258(R258), .R259(R259), .R260(R260), .R261(R261), .R262(R262), .R263(R263), .R264(R264), .R265(R265), .R266(R266), .R267(R267), .R268(R268), .R269(R269), .R270(R270), .R271(R271), .R272(R272), .R273(R273), .R274(R274), .R275(R275), .R276(R276), .R277(R277), .R278(R278), .R279(R279), .R280(R280), .R281(R281), .R282(R282), .R283(R283), .R284(R284), .R285(R285), .R286(R286), .R287(R287), .R288(R288), .R289(R289), .R290(R290), .R291(R291), .R292(R292), .R293(R293), .R294(R294), .R295(R295), .R296(R296), .R297(R297), .R298(R298), .R299(R299), .R300(R300), .R301(R301), .R302(R302), .R303(R303), .R304(R304), .R305(R305), .R306(R306), .R307(R307), .R308(R308), .R309(R309), .R310(R310), .R311(R311), .R312(R312), .R313(R313), .R314(R314), .R315(R315), .R316(R316), .R317(R317), .R318(R318), .R319(R319), .R320(R320), .R321(R321), .R322(R322), .R323(R323), .R324(R324), .R325(R325), .R326(R326), .R327(R327), .R328(R328), .R329(R329), .R330(R330), .R331(R331), .R332(R332), .R333(R333), .R334(R334), .R335(R335), .R336(R336), .R337(R337), .R338(R338), .R339(R339), .R340(R340), .R341(R341), .R342(R342), .R343(R343), .R344(R344), .R345(R345), .R346(R346), .R347(R347), .R348(R348), .R349(R349), .R350(R350), .R351(R351), .R352(R352), .R353(R353), .R354(R354), .R355(R355), .R356(R356), .R357(R357), .R358(R358), .R359(R359), .R360(R360), .R361(R361), .R362(R362), .R363(R363), .R364(R364), .R365(R365), .R366(R366), .R367(R367), .R368(R368), .R369(R369), .R370(R370), .R371(R371), .R372(R372), .R373(R373), .R374(R374), .R375(R375), .R376(R376), .R377(R377), .R378(R378), .R379(R379), .R380(R380), .R381(R381), .R382(R382), .R383(R383), .R384(R384), .R385(R385), .R386(R386), .R387(R387), .R388(R388), .R389(R389), .R390(R390), .R391(R391), .R392(R392), .R393(R393), .R394(R394), .R395(R395), .R396(R396), .R397(R397), .R398(R398), .R399(R399), .R400(R400), .R401(R401), .R402(R402), .R403(R403), .R404(R404), .R405(R405), .R406(R406), .R407(R407), .R408(R408), .R409(R409), .R410(R410), .R411(R411), .R412(R412), .R413(R413), .R414(R414), .R415(R415), .R416(R416), .R417(R417), .R418(R418), .R419(R419), .R420(R420), .R421(R421), .R422(R422), .R423(R423), .R424(R424), .R425(R425), .R426(R426), .R427(R427), .R428(R428), .R429(R429), .R430(R430), .R431(R431), .R432(R432), .R433(R433), .R434(R434), .R435(R435), .R436(R436), .R437(R437), .R438(R438), .R439(R439), .R440(R440), .R441(R441), .R442(R442), .R443(R443), .R444(R444), .R445(R445), .R446(R446), .R447(R447), .R448(R448), .R449(R449), .R450(R450), .R451(R451), .R452(R452), .R453(R453), .R454(R454), .R455(R455), .R456(R456), 3 | .R457(R0_ADDSUB_FP_netPar0), .R458(R1_ADDSUB_FP_netPar0), .R459(R2_ADDSUB_FP_netPar0), 4 | .R460(R0_ADDSUB_FP_netPar1), .R461(R1_ADDSUB_FP_netPar1), .R462(R2_ADDSUB_FP_netPar1), 5 | .R463(R0_ADDSUB_FP_netPar2), .R464(R1_ADDSUB_FP_netPar2), .R465(R2_ADDSUB_FP_netPar2), 6 | .R466(R0_ADDSUB_BP_netPar0), .R467(R1_ADDSUB_BP_netPar0), .R468(R2_ADDSUB_BP_netPar0), 7 | .R469(R0_ADDSUB_BP_netPar1), .R470(R1_ADDSUB_BP_netPar1), .R471(R2_ADDSUB_BP_netPar1), 8 | .R472(R0_ADDSUB_BP_netPar2), .R473(R1_ADDSUB_BP_netPar2), .R474(R2_ADDSUB_BP_netPar2), 9 | .R475(R0_ADDSUB_error_netPar0), 10 | .R476(R0_ADDSUB_error_netPar1), 11 | .R477(R0_ADDSUB_error_netPar2), 12 | .R478(R0_ADDSUB_NETPAR), .R479(R1_ADDSUB_NETPAR), .R480(R2_ADDSUB_NETPAR), .R481(R3_ADDSUB_NETPAR), .R482(R4_ADDSUB_NETPAR), .R483(R5_ADDSUB_NETPAR), .R484(R6_ADDSUB_NETPAR), .R485(R7_ADDSUB_NETPAR), .R486(R8_ADDSUB_NETPAR), .R487(R9_ADDSUB_NETPAR), .R488(R10_ADDSUB_NETPAR), .R489(R11_ADDSUB_NETPAR), .R490(R12_ADDSUB_NETPAR), .R491(R13_ADDSUB_NETPAR), .R492(R14_ADDSUB_NETPAR), .R493(R15_ADDSUB_NETPAR), .R494(R16_ADDSUB_NETPAR), .R495(R17_ADDSUB_NETPAR), .R496(R18_ADDSUB_NETPAR), .R497(R19_ADDSUB_NETPAR), .R498(R20_ADDSUB_NETPAR), .R499(R21_ADDSUB_NETPAR), .R500(R22_ADDSUB_NETPAR), .R501(R23_ADDSUB_NETPAR), .R502(R24_ADDSUB_NETPAR), .R503(R25_ADDSUB_NETPAR), .R504(R26_ADDSUB_NETPAR), .R505(R27_ADDSUB_NETPAR), .R506(R28_ADDSUB_NETPAR), .R507(R29_ADDSUB_NETPAR), .R508(R30_ADDSUB_NETPAR), .R509(R31_ADDSUB_NETPAR), .R510(R32_ADDSUB_NETPAR), .R511(R33_ADDSUB_NETPAR), .R512(R34_ADDSUB_NETPAR), .R513(R35_ADDSUB_NETPAR), .R514(R36_ADDSUB_NETPAR), .R515(R37_ADDSUB_NETPAR), .R516(R38_ADDSUB_NETPAR), .R517(R39_ADDSUB_NETPAR), .R518(R40_ADDSUB_NETPAR), .R519(R41_ADDSUB_NETPAR), .R520(R42_ADDSUB_NETPAR), .R521(R43_ADDSUB_NETPAR), .R522(R44_ADDSUB_NETPAR), .R523(R45_ADDSUB_NETPAR), .R524(R46_ADDSUB_NETPAR), .R525(R47_ADDSUB_NETPAR), .R526(R48_ADDSUB_NETPAR), .R527(R49_ADDSUB_NETPAR), .R528(R50_ADDSUB_NETPAR), 13 | .R_long0(R_long0), .R_long1(R_long1), .R_long2(R_long2), .R_long3(R_long3), .R_long4(R_long4), .R_long5(R_long5), .R_long6(R_long6), .R_long7(R_long7), .R_long8(R_long8), .R_long9(R_long9), .R_long10(R_long10), .R_long11(R_long11), .R_long12(R_long12), .R_long13(R_long13), .R_long14(R_long14), 14 | -------------------------------------------------------------------------------- /FullyConnectedSNN/FULLCONNBLOCK_L1.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Fully Connected Layer 1 4 | 5 | module FULLCONNBLOCK_L1( 6 | a_input, 7 | a_MEM_ACTIVE, 8 | alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, alpha_j_5, alpha_j_6, alpha_j_7, alpha_j_8, alpha_j_9, alpha_j_10, alpha_j_11, alpha_j_12, alpha_j_13, alpha_j_14, alpha_j_15, alpha_j_16, alpha_j_17, alpha_j_18, alpha_j_19, alpha_j_20, alpha_j_21, alpha_j_22, alpha_j_23, alpha_j_24, 9 | beta, 10 | SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, SIGN_alpha_j_5, SIGN_alpha_j_6, SIGN_alpha_j_7, SIGN_alpha_j_8, SIGN_alpha_j_9, SIGN_alpha_j_10, SIGN_alpha_j_11, SIGN_alpha_j_12, SIGN_alpha_j_13, SIGN_alpha_j_14, SIGN_alpha_j_15, SIGN_alpha_j_16, SIGN_alpha_j_17, SIGN_alpha_j_18, SIGN_alpha_j_19, SIGN_alpha_j_20, SIGN_alpha_j_21, SIGN_alpha_j_22, SIGN_alpha_j_23, SIGN_alpha_j_24, 11 | SIGN_beta, 12 | z, 13 | zp, 14 | a_out, 15 | R_FPsource, zeroCenterSource, 16 | CLK, INIT, CLK_TRAINING_flag 17 | ); 18 | 19 | parameter MEMSIZE = 3; 20 | parameter DP_in = 8; 21 | parameter DP_out = 16; 22 | 23 | input wire [5 - 1:0] a_input; 24 | input wire [25-1:0] a_MEM_ACTIVE; 25 | input wire [5-1:0] alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, alpha_j_5, alpha_j_6, alpha_j_7, alpha_j_8, alpha_j_9, alpha_j_10, alpha_j_11, alpha_j_12, alpha_j_13, alpha_j_14, alpha_j_15, alpha_j_16, alpha_j_17, alpha_j_18, alpha_j_19, alpha_j_20, alpha_j_21, alpha_j_22, alpha_j_23, alpha_j_24; 26 | input wire [25-1:0] beta; 27 | input wire [5-1:0] SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, SIGN_alpha_j_5, SIGN_alpha_j_6, SIGN_alpha_j_7, SIGN_alpha_j_8, SIGN_alpha_j_9, SIGN_alpha_j_10, SIGN_alpha_j_11, SIGN_alpha_j_12, SIGN_alpha_j_13, SIGN_alpha_j_14, SIGN_alpha_j_15, SIGN_alpha_j_16, SIGN_alpha_j_17, SIGN_alpha_j_18, SIGN_alpha_j_19, SIGN_alpha_j_20, SIGN_alpha_j_21, SIGN_alpha_j_22, SIGN_alpha_j_23, SIGN_alpha_j_24; 28 | input wire [25-1:0] SIGN_beta; 29 | input wire R_FPsource, zeroCenterSource; 30 | input wire CLK, INIT, CLK_TRAINING_flag; 31 | 32 | output wire [25-1:0] z; 33 | output wire [25-1:0] zp; 34 | output wire [25-1:0] a_out; 35 | 36 | wire [25-1:0] zeroCenter, R_FP; 37 | SS_RERANDOMIZER RERANDOMIZER_zC(.CLK(CLK), .INIT(INIT), .IN(zeroCenterSource), .OUT(zeroCenter)); 38 | defparam RERANDOMIZER_zC.N = 25; 39 | SS_RERANDOMIZER RERANDOMIZER_FP(.CLK(CLK), .INIT(INIT), .IN(R_FPsource), .OUT(R_FP)); 40 | defparam RERANDOMIZER_FP.N = 25; 41 | 42 | NN_NODE_BGPOLAR NODE_0(.a(a_input), .alpha(alpha_j_0), .beta(beta[0]), .SIGN_alpha(SIGN_alpha_j_0), .SIGN_beta(SIGN_beta[0]), .z(z[0]), .d(zeroCenter[0]), .r(R_FP[0]), .a_out(a_out[0]), .INIT_STATE(a_MEM_ACTIVE[0]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 0 43 | NN_NODE_BGPOLAR NODE_1(.a(a_input), .alpha(alpha_j_1), .beta(beta[1]), .SIGN_alpha(SIGN_alpha_j_1), .SIGN_beta(SIGN_beta[1]), .z(z[1]), .d(zeroCenter[1]), .r(R_FP[1]), .a_out(a_out[1]), .INIT_STATE(a_MEM_ACTIVE[1]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 1 44 | NN_NODE_BGPOLAR NODE_2(.a(a_input), .alpha(alpha_j_2), .beta(beta[2]), .SIGN_alpha(SIGN_alpha_j_2), .SIGN_beta(SIGN_beta[2]), .z(z[2]), .d(zeroCenter[2]), .r(R_FP[2]), .a_out(a_out[2]), .INIT_STATE(a_MEM_ACTIVE[2]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 2 45 | NN_NODE_BGPOLAR NODE_3(.a(a_input), .alpha(alpha_j_3), .beta(beta[3]), .SIGN_alpha(SIGN_alpha_j_3), .SIGN_beta(SIGN_beta[3]), .z(z[3]), .d(zeroCenter[3]), .r(R_FP[3]), .a_out(a_out[3]), .INIT_STATE(a_MEM_ACTIVE[3]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 3 46 | NN_NODE_BGPOLAR NODE_4(.a(a_input), .alpha(alpha_j_4), .beta(beta[4]), .SIGN_alpha(SIGN_alpha_j_4), .SIGN_beta(SIGN_beta[4]), .z(z[4]), .d(zeroCenter[4]), .r(R_FP[4]), .a_out(a_out[4]), .INIT_STATE(a_MEM_ACTIVE[4]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 4 47 | NN_NODE_BGPOLAR NODE_5(.a(a_input), .alpha(alpha_j_5), .beta(beta[5]), .SIGN_alpha(SIGN_alpha_j_5), .SIGN_beta(SIGN_beta[5]), .z(z[5]), .d(zeroCenter[5]), .r(R_FP[5]), .a_out(a_out[5]), .INIT_STATE(a_MEM_ACTIVE[5]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 5 48 | NN_NODE_BGPOLAR NODE_6(.a(a_input), .alpha(alpha_j_6), .beta(beta[6]), .SIGN_alpha(SIGN_alpha_j_6), .SIGN_beta(SIGN_beta[6]), .z(z[6]), .d(zeroCenter[6]), .r(R_FP[6]), .a_out(a_out[6]), .INIT_STATE(a_MEM_ACTIVE[6]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 6 49 | NN_NODE_BGPOLAR NODE_7(.a(a_input), .alpha(alpha_j_7), .beta(beta[7]), .SIGN_alpha(SIGN_alpha_j_7), .SIGN_beta(SIGN_beta[7]), .z(z[7]), .d(zeroCenter[7]), .r(R_FP[7]), .a_out(a_out[7]), .INIT_STATE(a_MEM_ACTIVE[7]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 7 50 | NN_NODE_BGPOLAR NODE_8(.a(a_input), .alpha(alpha_j_8), .beta(beta[8]), .SIGN_alpha(SIGN_alpha_j_8), .SIGN_beta(SIGN_beta[8]), .z(z[8]), .d(zeroCenter[8]), .r(R_FP[8]), .a_out(a_out[8]), .INIT_STATE(a_MEM_ACTIVE[8]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 8 51 | NN_NODE_BGPOLAR NODE_9(.a(a_input), .alpha(alpha_j_9), .beta(beta[9]), .SIGN_alpha(SIGN_alpha_j_9), .SIGN_beta(SIGN_beta[9]), .z(z[9]), .d(zeroCenter[9]), .r(R_FP[9]), .a_out(a_out[9]), .INIT_STATE(a_MEM_ACTIVE[9]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 9 52 | NN_NODE_BGPOLAR NODE_10(.a(a_input), .alpha(alpha_j_10), .beta(beta[10]), .SIGN_alpha(SIGN_alpha_j_10), .SIGN_beta(SIGN_beta[10]), .z(z[10]), .d(zeroCenter[10]), .r(R_FP[10]), .a_out(a_out[10]), .INIT_STATE(a_MEM_ACTIVE[10]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 10 53 | NN_NODE_BGPOLAR NODE_11(.a(a_input), .alpha(alpha_j_11), .beta(beta[11]), .SIGN_alpha(SIGN_alpha_j_11), .SIGN_beta(SIGN_beta[11]), .z(z[11]), .d(zeroCenter[11]), .r(R_FP[11]), .a_out(a_out[11]), .INIT_STATE(a_MEM_ACTIVE[11]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 11 54 | NN_NODE_BGPOLAR NODE_12(.a(a_input), .alpha(alpha_j_12), .beta(beta[12]), .SIGN_alpha(SIGN_alpha_j_12), .SIGN_beta(SIGN_beta[12]), .z(z[12]), .d(zeroCenter[12]), .r(R_FP[12]), .a_out(a_out[12]), .INIT_STATE(a_MEM_ACTIVE[12]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 12 55 | NN_NODE_BGPOLAR NODE_13(.a(a_input), .alpha(alpha_j_13), .beta(beta[13]), .SIGN_alpha(SIGN_alpha_j_13), .SIGN_beta(SIGN_beta[13]), .z(z[13]), .d(zeroCenter[13]), .r(R_FP[13]), .a_out(a_out[13]), .INIT_STATE(a_MEM_ACTIVE[13]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 13 56 | NN_NODE_BGPOLAR NODE_14(.a(a_input), .alpha(alpha_j_14), .beta(beta[14]), .SIGN_alpha(SIGN_alpha_j_14), .SIGN_beta(SIGN_beta[14]), .z(z[14]), .d(zeroCenter[14]), .r(R_FP[14]), .a_out(a_out[14]), .INIT_STATE(a_MEM_ACTIVE[14]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 14 57 | NN_NODE_BGPOLAR NODE_15(.a(a_input), .alpha(alpha_j_15), .beta(beta[15]), .SIGN_alpha(SIGN_alpha_j_15), .SIGN_beta(SIGN_beta[15]), .z(z[15]), .d(zeroCenter[15]), .r(R_FP[15]), .a_out(a_out[15]), .INIT_STATE(a_MEM_ACTIVE[15]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 15 58 | NN_NODE_BGPOLAR NODE_16(.a(a_input), .alpha(alpha_j_16), .beta(beta[16]), .SIGN_alpha(SIGN_alpha_j_16), .SIGN_beta(SIGN_beta[16]), .z(z[16]), .d(zeroCenter[16]), .r(R_FP[16]), .a_out(a_out[16]), .INIT_STATE(a_MEM_ACTIVE[16]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 16 59 | NN_NODE_BGPOLAR NODE_17(.a(a_input), .alpha(alpha_j_17), .beta(beta[17]), .SIGN_alpha(SIGN_alpha_j_17), .SIGN_beta(SIGN_beta[17]), .z(z[17]), .d(zeroCenter[17]), .r(R_FP[17]), .a_out(a_out[17]), .INIT_STATE(a_MEM_ACTIVE[17]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 17 60 | NN_NODE_BGPOLAR NODE_18(.a(a_input), .alpha(alpha_j_18), .beta(beta[18]), .SIGN_alpha(SIGN_alpha_j_18), .SIGN_beta(SIGN_beta[18]), .z(z[18]), .d(zeroCenter[18]), .r(R_FP[18]), .a_out(a_out[18]), .INIT_STATE(a_MEM_ACTIVE[18]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 18 61 | NN_NODE_BGPOLAR NODE_19(.a(a_input), .alpha(alpha_j_19), .beta(beta[19]), .SIGN_alpha(SIGN_alpha_j_19), .SIGN_beta(SIGN_beta[19]), .z(z[19]), .d(zeroCenter[19]), .r(R_FP[19]), .a_out(a_out[19]), .INIT_STATE(a_MEM_ACTIVE[19]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 19 62 | NN_NODE_BGPOLAR NODE_20(.a(a_input), .alpha(alpha_j_20), .beta(beta[20]), .SIGN_alpha(SIGN_alpha_j_20), .SIGN_beta(SIGN_beta[20]), .z(z[20]), .d(zeroCenter[20]), .r(R_FP[20]), .a_out(a_out[20]), .INIT_STATE(a_MEM_ACTIVE[20]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 20 63 | NN_NODE_BGPOLAR NODE_21(.a(a_input), .alpha(alpha_j_21), .beta(beta[21]), .SIGN_alpha(SIGN_alpha_j_21), .SIGN_beta(SIGN_beta[21]), .z(z[21]), .d(zeroCenter[21]), .r(R_FP[21]), .a_out(a_out[21]), .INIT_STATE(a_MEM_ACTIVE[21]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 21 64 | NN_NODE_BGPOLAR NODE_22(.a(a_input), .alpha(alpha_j_22), .beta(beta[22]), .SIGN_alpha(SIGN_alpha_j_22), .SIGN_beta(SIGN_beta[22]), .z(z[22]), .d(zeroCenter[22]), .r(R_FP[22]), .a_out(a_out[22]), .INIT_STATE(a_MEM_ACTIVE[22]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 22 65 | NN_NODE_BGPOLAR NODE_23(.a(a_input), .alpha(alpha_j_23), .beta(beta[23]), .SIGN_alpha(SIGN_alpha_j_23), .SIGN_beta(SIGN_beta[23]), .z(z[23]), .d(zeroCenter[23]), .r(R_FP[23]), .a_out(a_out[23]), .INIT_STATE(a_MEM_ACTIVE[23]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 23 66 | NN_NODE_BGPOLAR NODE_24(.a(a_input), .alpha(alpha_j_24), .beta(beta[24]), .SIGN_alpha(SIGN_alpha_j_24), .SIGN_beta(SIGN_beta[24]), .z(z[24]), .d(zeroCenter[24]), .r(R_FP[24]), .a_out(a_out[24]), .INIT_STATE(a_MEM_ACTIVE[24]), .CLK(CLK), .INIT(INIT | CLK_TRAINING_flag)); // layer 1 node 24 67 | defparam NODE_0.N = 5; 68 | defparam NODE_0.MEMSIZE = MEMSIZE; 69 | defparam NODE_1.N = 5; 70 | defparam NODE_1.MEMSIZE = MEMSIZE; 71 | defparam NODE_2.N = 5; 72 | defparam NODE_2.MEMSIZE = MEMSIZE; 73 | defparam NODE_3.N = 5; 74 | defparam NODE_3.MEMSIZE = MEMSIZE; 75 | defparam NODE_4.N = 5; 76 | defparam NODE_4.MEMSIZE = MEMSIZE; 77 | defparam NODE_5.N = 5; 78 | defparam NODE_5.MEMSIZE = MEMSIZE; 79 | defparam NODE_6.N = 5; 80 | defparam NODE_6.MEMSIZE = MEMSIZE; 81 | defparam NODE_7.N = 5; 82 | defparam NODE_7.MEMSIZE = MEMSIZE; 83 | defparam NODE_8.N = 5; 84 | defparam NODE_8.MEMSIZE = MEMSIZE; 85 | defparam NODE_9.N = 5; 86 | defparam NODE_9.MEMSIZE = MEMSIZE; 87 | defparam NODE_10.N = 5; 88 | defparam NODE_10.MEMSIZE = MEMSIZE; 89 | defparam NODE_11.N = 5; 90 | defparam NODE_11.MEMSIZE = MEMSIZE; 91 | defparam NODE_12.N = 5; 92 | defparam NODE_12.MEMSIZE = MEMSIZE; 93 | defparam NODE_13.N = 5; 94 | defparam NODE_13.MEMSIZE = MEMSIZE; 95 | defparam NODE_14.N = 5; 96 | defparam NODE_14.MEMSIZE = MEMSIZE; 97 | defparam NODE_15.N = 5; 98 | defparam NODE_15.MEMSIZE = MEMSIZE; 99 | defparam NODE_16.N = 5; 100 | defparam NODE_16.MEMSIZE = MEMSIZE; 101 | defparam NODE_17.N = 5; 102 | defparam NODE_17.MEMSIZE = MEMSIZE; 103 | defparam NODE_18.N = 5; 104 | defparam NODE_18.MEMSIZE = MEMSIZE; 105 | defparam NODE_19.N = 5; 106 | defparam NODE_19.MEMSIZE = MEMSIZE; 107 | defparam NODE_20.N = 5; 108 | defparam NODE_20.MEMSIZE = MEMSIZE; 109 | defparam NODE_21.N = 5; 110 | defparam NODE_21.MEMSIZE = MEMSIZE; 111 | defparam NODE_22.N = 5; 112 | defparam NODE_22.MEMSIZE = MEMSIZE; 113 | defparam NODE_23.N = 5; 114 | defparam NODE_23.MEMSIZE = MEMSIZE; 115 | defparam NODE_24.N = 5; 116 | defparam NODE_24.MEMSIZE = MEMSIZE; 117 | 118 | NN_BGPRIME BGPRIME_0(.z(z[0]), .zp(zp[0]), .CLK(CLK), .INIT(INIT)); 119 | NN_BGPRIME BGPRIME_1(.z(z[1]), .zp(zp[1]), .CLK(CLK), .INIT(INIT)); 120 | NN_BGPRIME BGPRIME_2(.z(z[2]), .zp(zp[2]), .CLK(CLK), .INIT(INIT)); 121 | NN_BGPRIME BGPRIME_3(.z(z[3]), .zp(zp[3]), .CLK(CLK), .INIT(INIT)); 122 | NN_BGPRIME BGPRIME_4(.z(z[4]), .zp(zp[4]), .CLK(CLK), .INIT(INIT)); 123 | NN_BGPRIME BGPRIME_5(.z(z[5]), .zp(zp[5]), .CLK(CLK), .INIT(INIT)); 124 | NN_BGPRIME BGPRIME_6(.z(z[6]), .zp(zp[6]), .CLK(CLK), .INIT(INIT)); 125 | NN_BGPRIME BGPRIME_7(.z(z[7]), .zp(zp[7]), .CLK(CLK), .INIT(INIT)); 126 | NN_BGPRIME BGPRIME_8(.z(z[8]), .zp(zp[8]), .CLK(CLK), .INIT(INIT)); 127 | NN_BGPRIME BGPRIME_9(.z(z[9]), .zp(zp[9]), .CLK(CLK), .INIT(INIT)); 128 | NN_BGPRIME BGPRIME_10(.z(z[10]), .zp(zp[10]), .CLK(CLK), .INIT(INIT)); 129 | NN_BGPRIME BGPRIME_11(.z(z[11]), .zp(zp[11]), .CLK(CLK), .INIT(INIT)); 130 | NN_BGPRIME BGPRIME_12(.z(z[12]), .zp(zp[12]), .CLK(CLK), .INIT(INIT)); 131 | NN_BGPRIME BGPRIME_13(.z(z[13]), .zp(zp[13]), .CLK(CLK), .INIT(INIT)); 132 | NN_BGPRIME BGPRIME_14(.z(z[14]), .zp(zp[14]), .CLK(CLK), .INIT(INIT)); 133 | NN_BGPRIME BGPRIME_15(.z(z[15]), .zp(zp[15]), .CLK(CLK), .INIT(INIT)); 134 | NN_BGPRIME BGPRIME_16(.z(z[16]), .zp(zp[16]), .CLK(CLK), .INIT(INIT)); 135 | NN_BGPRIME BGPRIME_17(.z(z[17]), .zp(zp[17]), .CLK(CLK), .INIT(INIT)); 136 | NN_BGPRIME BGPRIME_18(.z(z[18]), .zp(zp[18]), .CLK(CLK), .INIT(INIT)); 137 | NN_BGPRIME BGPRIME_19(.z(z[19]), .zp(zp[19]), .CLK(CLK), .INIT(INIT)); 138 | NN_BGPRIME BGPRIME_20(.z(z[20]), .zp(zp[20]), .CLK(CLK), .INIT(INIT)); 139 | NN_BGPRIME BGPRIME_21(.z(z[21]), .zp(zp[21]), .CLK(CLK), .INIT(INIT)); 140 | NN_BGPRIME BGPRIME_22(.z(z[22]), .zp(zp[22]), .CLK(CLK), .INIT(INIT)); 141 | NN_BGPRIME BGPRIME_23(.z(z[23]), .zp(zp[23]), .CLK(CLK), .INIT(INIT)); 142 | NN_BGPRIME BGPRIME_24(.z(z[24]), .zp(zp[24]), .CLK(CLK), .INIT(INIT)); 143 | 144 | endmodule 145 | -------------------------------------------------------------------------------- /FullyConnectedSNN/src-verilog/stochastic/SS_ADDSUB_CARRY_N.v: -------------------------------------------------------------------------------- 1 | 2 | // Chris Ceroici 3 | // Perform stochastic arithmetic for N inputs 4 | // requires SIGN input for each input argument 5 | 6 | module SS_ADDSUB_CARRY_N #(parameter N=6, N_CARRY=2, DIFFCOUNTER_SIZE = 1, DIFFCOUNT_LOWERLIM = 0, OR_CALC = 2'b01, MUX_CALC = 2'b10, CALC_METHOD = OR_CALC) (CLK,INIT,IN,SIGN,R_condition,OUT,SIGN_out); 7 | 8 | 9 | input CLK,INIT; 10 | input [N-1:0] IN,SIGN; 11 | input R_condition; 12 | 13 | output reg OUT,SIGN_out; 14 | 15 | wire INPUT_SUM_pos, INPUT_SUM_neg; 16 | wire [N_CARRY-1:0] INPUT_CARRY_pos, INPUT_CARRY_neg; 17 | wire OUTPUT_pos, OUTPUT_neg, OUT_temp; 18 | 19 | reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT = 1'd0; 20 | reg DIFFCOUNT_SIGN = 1'd0; 21 | 22 | reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT_LIMIT = 1'd0-1'd1; 23 | 24 | wire [N-1:0] N_INPUTS_pos; 25 | wire [N-1:0] N_INPUTS_neg; 26 | 27 | M_SIDEADD #(.N_inputs(N), .NB_out(N)) SIDEADDpos(.EN(1'b1),.IN(IN&(~SIGN)),.OUT(N_INPUTS_pos)); 28 | M_SIDEADD #(.N_inputs(N), .NB_out(N)) SIDEADDneg(.EN(1'b1),.IN(IN&(SIGN)),.OUT(N_INPUTS_neg)); 29 | 30 | wire EQUAL, INPUT_SIGN; 31 | 32 | assign EQUAL = (N_INPUTS_pos==N_INPUTS_neg); 33 | 34 | assign INPUT_SIGN = (R_condition) ? (N_INPUTS_neg>=N_INPUTS_pos) : (N_INPUTS_neg>N_INPUTS_pos); 35 | 36 | always @(posedge CLK or posedge INIT) begin 37 | 38 | if (INIT) begin 39 | DIFFCOUNT_SIGN = 1'b0; 40 | //DIFFCOUNT_SIGN = DIFFCOUNT_SIGN; 41 | DIFFCOUNT <= 1'b0; 42 | end else if (EQUAL) DIFFCOUNT <= DIFFCOUNT; 43 | else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)&(DIFFCOUNT +ve 44 | DIFFCOUNT_SIGN = 1'b0; 45 | DIFFCOUNT <= N_INPUTS_pos; 46 | // NOTE: If DIFFCOUNT = 1, (DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos) will never be satisfied when only a single input is 1. 47 | end else if ((!INPUT_SIGN)&(DIFFCOUNT -ve 57 | DIFFCOUNT_SIGN = 1'b1; 58 | DIFFCOUNT <= N_INPUTS_neg; 59 | end else if ((INPUT_SIGN)&(DIFFCOUNT (DIFFCOUNT_LOWERLIM)) ? OUT_temp : 1'b0; 104 | 105 | genvar n; 106 | generate 107 | case (N_CARRY) 108 | 2 : begin 109 | always @(posedge CLK or posedge INIT) begin 110 | if (INIT) begin 111 | OUT <= 1'b0; 112 | SIGN_out <= 1'b0; 113 | end else if (INPUT_CARRY_pos[1]&INPUT_CARRY_neg[1]) begin 114 | OUT <= 1'b0; 115 | SIGN_out <= 1'b0; 116 | end else if (INPUT_CARRY_pos[1]&(~INPUT_CARRY_neg[1])) begin 117 | OUT <= 1'b1; 118 | SIGN_out <= 1'b0; 119 | end else if ((~INPUT_CARRY_pos[1])&INPUT_CARRY_neg[1]) begin 120 | OUT <= 1'b1; 121 | SIGN_out <= 1'b1; 122 | end else if (INPUT_CARRY_pos[0]&INPUT_CARRY_neg[0]) begin 123 | OUT <= 1'b0; 124 | SIGN_out <= 1'b0; 125 | end else if (INPUT_CARRY_pos[0]&(~INPUT_CARRY_neg[0])) begin 126 | OUT <= 1'b1; 127 | SIGN_out <= 1'b0; 128 | end else if ((~INPUT_CARRY_pos[0])&INPUT_CARRY_neg[0]) begin 129 | OUT <= 1'b1; 130 | SIGN_out <= 1'b1; 131 | end else if (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) begin 132 | OUT <= OUT_temp; 133 | SIGN_out <= DIFFCOUNT_SIGN; 134 | end else begin 135 | OUT <= 1'b0; 136 | SIGN_out <= SIGN_out; 137 | end 138 | end 139 | end 140 | 3 : begin 141 | always @(posedge CLK or posedge INIT) begin 142 | if (INIT) begin 143 | OUT <= 1'b0; 144 | SIGN_out <= 1'b0; 145 | end else if (INPUT_CARRY_pos[2]&INPUT_CARRY_neg[2]) begin 146 | OUT <= 1'b0; 147 | SIGN_out <= 1'b0; 148 | end else if (INPUT_CARRY_pos[2]&(~INPUT_CARRY_neg[2])) begin 149 | OUT <= 1'b1; 150 | SIGN_out <= 1'b0; 151 | end else if ((~INPUT_CARRY_pos[2])&INPUT_CARRY_neg[2]) begin 152 | OUT <= 1'b1; 153 | SIGN_out <= 1'b1; 154 | end else if (INPUT_CARRY_pos[1]&INPUT_CARRY_neg[1]) begin 155 | OUT <= 1'b0; 156 | SIGN_out <= 1'b0; 157 | end else if (INPUT_CARRY_pos[1]&(~INPUT_CARRY_neg[1])) begin 158 | OUT <= 1'b1; 159 | SIGN_out <= 1'b0; 160 | end else if ((~INPUT_CARRY_pos[1])&INPUT_CARRY_neg[1]) begin 161 | OUT <= 1'b1; 162 | SIGN_out <= 1'b1; 163 | end else if (INPUT_CARRY_pos[0]&INPUT_CARRY_neg[0]) begin 164 | OUT <= 1'b0; 165 | SIGN_out <= 1'b0; 166 | end else if (INPUT_CARRY_pos[0]&(~INPUT_CARRY_neg[0])) begin 167 | OUT <= 1'b1; 168 | SIGN_out <= 1'b0; 169 | end else if ((~INPUT_CARRY_pos[0])&INPUT_CARRY_neg[0]) begin 170 | OUT <= 1'b1; 171 | SIGN_out <= 1'b1; 172 | end else if (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) begin 173 | OUT <= OUT_temp; 174 | SIGN_out <= DIFFCOUNT_SIGN; 175 | end else begin 176 | OUT <= 1'b0; 177 | SIGN_out <= SIGN_out; 178 | end 179 | end 180 | end 181 | 4 : begin 182 | always @(posedge CLK or posedge INIT) begin 183 | if (INIT) begin 184 | OUT <= 1'b0; 185 | SIGN_out <= 1'b0; 186 | end else if (INPUT_CARRY_pos[3]&INPUT_CARRY_neg[3]) begin 187 | OUT <= 1'b0; 188 | SIGN_out <= 1'b0; 189 | end else if (INPUT_CARRY_pos[3]&(~INPUT_CARRY_neg[3])) begin 190 | OUT <= 1'b1; 191 | SIGN_out <= 1'b0; 192 | end else if ((~INPUT_CARRY_pos[3])&INPUT_CARRY_neg[3]) begin 193 | OUT <= 1'b1; 194 | SIGN_out <= 1'b1; 195 | end else if (INPUT_CARRY_pos[2]&INPUT_CARRY_neg[2]) begin 196 | OUT <= 1'b0; 197 | SIGN_out <= 1'b0; 198 | end else if (INPUT_CARRY_pos[2]&(~INPUT_CARRY_neg[2])) begin 199 | OUT <= 1'b1; 200 | SIGN_out <= 1'b0; 201 | end else if ((~INPUT_CARRY_pos[2])&INPUT_CARRY_neg[2]) begin 202 | OUT <= 1'b1; 203 | SIGN_out <= 1'b1; 204 | end else if (INPUT_CARRY_pos[1]&INPUT_CARRY_neg[1]) begin 205 | OUT <= 1'b0; 206 | SIGN_out <= 1'b0; 207 | end else if (INPUT_CARRY_pos[1]&(~INPUT_CARRY_neg[1])) begin 208 | OUT <= 1'b1; 209 | SIGN_out <= 1'b0; 210 | end else if ((~INPUT_CARRY_pos[1])&INPUT_CARRY_neg[1]) begin 211 | OUT <= 1'b1; 212 | SIGN_out <= 1'b1; 213 | end else if (INPUT_CARRY_pos[0]&INPUT_CARRY_neg[0]) begin 214 | OUT <= 1'b0; 215 | SIGN_out <= 1'b0; 216 | end else if (INPUT_CARRY_pos[0]&(~INPUT_CARRY_neg[0])) begin 217 | OUT <= 1'b1; 218 | SIGN_out <= 1'b0; 219 | end else if ((~INPUT_CARRY_pos[0])&INPUT_CARRY_neg[0]) begin 220 | OUT <= 1'b1; 221 | SIGN_out <= 1'b1; 222 | end else if (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) begin 223 | OUT <= OUT_temp; 224 | SIGN_out <= DIFFCOUNT_SIGN; 225 | end else begin 226 | OUT <= 1'b0; 227 | SIGN_out <= SIGN_out; 228 | end 229 | end 230 | end 231 | 8 : begin 232 | always @(posedge CLK or posedge INIT) begin 233 | if (INIT) begin 234 | OUT <= 1'b0; 235 | SIGN_out <= 1'b0; 236 | end else if (INPUT_CARRY_pos[7]&INPUT_CARRY_neg[7]) begin 237 | OUT <= 1'b0; 238 | SIGN_out <= 1'b0; 239 | end else if (INPUT_CARRY_pos[7]&(~INPUT_CARRY_neg[7])) begin 240 | OUT <= 1'b1; 241 | SIGN_out <= 1'b0; 242 | end else if ((~INPUT_CARRY_pos[7])&INPUT_CARRY_neg[7]) begin 243 | OUT <= 1'b1; 244 | SIGN_out <= 1'b1; 245 | end else if (INPUT_CARRY_pos[6]&INPUT_CARRY_neg[6]) begin 246 | OUT <= 1'b0; 247 | SIGN_out <= 1'b0; 248 | end else if (INPUT_CARRY_pos[6]&(~INPUT_CARRY_neg[6])) begin 249 | OUT <= 1'b1; 250 | SIGN_out <= 1'b0; 251 | end else if ((~INPUT_CARRY_pos[6])&INPUT_CARRY_neg[6]) begin 252 | OUT <= 1'b1; 253 | SIGN_out <= 1'b1; 254 | end else if (INPUT_CARRY_pos[5]&INPUT_CARRY_neg[5]) begin 255 | OUT <= 1'b0; 256 | SIGN_out <= 1'b0; 257 | end else if (INPUT_CARRY_pos[5]&(~INPUT_CARRY_neg[5])) begin 258 | OUT <= 1'b1; 259 | SIGN_out <= 1'b0; 260 | end else if ((~INPUT_CARRY_pos[5])&INPUT_CARRY_neg[5]) begin 261 | OUT <= 1'b1; 262 | SIGN_out <= 1'b1; 263 | end else if (INPUT_CARRY_pos[4]&INPUT_CARRY_neg[4]) begin 264 | OUT <= 1'b0; 265 | SIGN_out <= 1'b0; 266 | end else if (INPUT_CARRY_pos[4]&(~INPUT_CARRY_neg[4])) begin 267 | OUT <= 1'b1; 268 | SIGN_out <= 1'b0; 269 | end else if ((~INPUT_CARRY_pos[4])&INPUT_CARRY_neg[4]) begin 270 | OUT <= 1'b1; 271 | SIGN_out <= 1'b1; 272 | end else if (INPUT_CARRY_pos[3]&INPUT_CARRY_neg[3]) begin 273 | OUT <= 1'b0; 274 | SIGN_out <= 1'b0; 275 | end else if (INPUT_CARRY_pos[3]&(~INPUT_CARRY_neg[3])) begin 276 | OUT <= 1'b1; 277 | SIGN_out <= 1'b0; 278 | end else if ((~INPUT_CARRY_pos[3])&INPUT_CARRY_neg[3]) begin 279 | OUT <= 1'b1; 280 | SIGN_out <= 1'b1; 281 | end else if (INPUT_CARRY_pos[2]&INPUT_CARRY_neg[2]) begin 282 | OUT <= 1'b0; 283 | SIGN_out <= 1'b0; 284 | end else if (INPUT_CARRY_pos[2]&(~INPUT_CARRY_neg[2])) begin 285 | OUT <= 1'b1; 286 | SIGN_out <= 1'b0; 287 | end else if ((~INPUT_CARRY_pos[2])&INPUT_CARRY_neg[2]) begin 288 | OUT <= 1'b1; 289 | SIGN_out <= 1'b1; 290 | end else if (INPUT_CARRY_pos[1]&INPUT_CARRY_neg[1]) begin 291 | OUT <= 1'b0; 292 | SIGN_out <= 1'b0; 293 | end else if (INPUT_CARRY_pos[1]&(~INPUT_CARRY_neg[1])) begin 294 | OUT <= 1'b1; 295 | SIGN_out <= 1'b0; 296 | end else if ((~INPUT_CARRY_pos[1])&INPUT_CARRY_neg[1]) begin 297 | OUT <= 1'b1; 298 | SIGN_out <= 1'b1; 299 | end else if (INPUT_CARRY_pos[0]&INPUT_CARRY_neg[0]) begin 300 | OUT <= 1'b0; 301 | SIGN_out <= 1'b0; 302 | end else if (INPUT_CARRY_pos[0]&(~INPUT_CARRY_neg[0])) begin 303 | OUT <= 1'b1; 304 | SIGN_out <= 1'b0; 305 | end else if ((~INPUT_CARRY_pos[0])&INPUT_CARRY_neg[0]) begin 306 | OUT <= 1'b1; 307 | SIGN_out <= 1'b1; 308 | end else if (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) begin 309 | OUT <= OUT_temp; 310 | SIGN_out <= DIFFCOUNT_SIGN; 311 | end else begin 312 | OUT <= 1'b0; 313 | SIGN_out <= SIGN_out; 314 | end 315 | end 316 | end 317 | default : begin 318 | always @(posedge CLK or posedge INIT) begin 319 | if (INIT) begin 320 | OUT <= 1'b0; 321 | SIGN_out <= 1'b0; 322 | end else if (INPUT_CARRY_pos[1]&INPUT_CARRY_neg[1]) begin 323 | OUT <= 1'b0; 324 | SIGN_out <= 1'b0; 325 | end else if (INPUT_CARRY_pos[1]&(~INPUT_CARRY_neg[1])) begin 326 | OUT <= 1'b1; 327 | SIGN_out <= 1'b0; 328 | end else if ((~INPUT_CARRY_pos[1])&INPUT_CARRY_neg[1]) begin 329 | OUT <= 1'b1; 330 | SIGN_out <= 1'b1; 331 | end else if (INPUT_CARRY_pos[0]&INPUT_CARRY_neg[0]) begin 332 | OUT <= 1'b0; 333 | SIGN_out <= 1'b0; 334 | end else if (INPUT_CARRY_pos[0]&(~INPUT_CARRY_neg[0])) begin 335 | OUT <= 1'b1; 336 | SIGN_out <= 1'b0; 337 | end else if ((~INPUT_CARRY_pos[0])&INPUT_CARRY_neg[0]) begin 338 | OUT <= 1'b1; 339 | SIGN_out <= 1'b1; 340 | end else if (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) begin 341 | OUT <= OUT_temp; 342 | SIGN_out <= DIFFCOUNT_SIGN; 343 | end else begin 344 | OUT <= 1'b0; 345 | SIGN_out <= SIGN_out; 346 | end 347 | end 348 | end 349 | endcase 350 | endgenerate 351 | 352 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/FULLCONNBLOCKBP_L1.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Fully Connected Backpropagation Layer 1 4 | 5 | module FULLCONNBLOCKBP_L1( 6 | alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, alpha_j_5, alpha_j_6, alpha_j_7, 7 | SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, SIGN_alpha_j_5, SIGN_alpha_j_6, SIGN_alpha_j_7, 8 | z, 9 | zp, 10 | delta_in, 11 | SIGN_delta_in, 12 | delta_out, 13 | SIGN_delta_out, 14 | R_BPsource, 15 | CLK, INIT 16 | ); 17 | 18 | input wire [25-1:0] alpha_j_0, alpha_j_1, alpha_j_2, alpha_j_3, alpha_j_4, alpha_j_5, alpha_j_6, alpha_j_7; 19 | input wire [25-1:0] SIGN_alpha_j_0, SIGN_alpha_j_1, SIGN_alpha_j_2, SIGN_alpha_j_3, SIGN_alpha_j_4, SIGN_alpha_j_5, SIGN_alpha_j_6, SIGN_alpha_j_7; 20 | input wire [25-1:0] z; 21 | input wire [25-1:0] zp; 22 | input wire [8-1:0] delta_in; 23 | input wire [8-1:0] SIGN_delta_in; 24 | input wire R_BPsource; 25 | input wire CLK, INIT; 26 | 27 | output wire [25-1:0] delta_out; 28 | output wire [25-1:0] SIGN_delta_out; 29 | 30 | wire [25-1:0] R_BP; 31 | 32 | SS_RERANDOMIZER RERANDOMIZER0(.CLK(CLK), .INIT(INIT), .IN(R_BPsource), .OUT(R_BP)); 33 | defparam RERANDOMIZER0.N = 25; 34 | 35 | NN_DELTABP_POLAR DELTABP_0(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[0]),.z(z[0]),.zp(zp[0]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[0], alpha_j_6[0], alpha_j_5[0], alpha_j_4[0], alpha_j_3[0], alpha_j_2[0], alpha_j_1[0], alpha_j_0[0]}), .SIGN_alpha({SIGN_alpha_j_7[0], SIGN_alpha_j_6[0], SIGN_alpha_j_5[0], SIGN_alpha_j_4[0], SIGN_alpha_j_3[0], SIGN_alpha_j_2[0], SIGN_alpha_j_1[0], SIGN_alpha_j_0[0]}), .delta_out(delta_out[0]), .SIGN_out(SIGN_delta_out[0])); 36 | NN_DELTABP_POLAR DELTABP_1(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[1]),.z(z[1]),.zp(zp[1]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[1], alpha_j_6[1], alpha_j_5[1], alpha_j_4[1], alpha_j_3[1], alpha_j_2[1], alpha_j_1[1], alpha_j_0[1]}), .SIGN_alpha({SIGN_alpha_j_7[1], SIGN_alpha_j_6[1], SIGN_alpha_j_5[1], SIGN_alpha_j_4[1], SIGN_alpha_j_3[1], SIGN_alpha_j_2[1], SIGN_alpha_j_1[1], SIGN_alpha_j_0[1]}), .delta_out(delta_out[1]), .SIGN_out(SIGN_delta_out[1])); 37 | NN_DELTABP_POLAR DELTABP_2(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[2]),.z(z[2]),.zp(zp[2]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[2], alpha_j_6[2], alpha_j_5[2], alpha_j_4[2], alpha_j_3[2], alpha_j_2[2], alpha_j_1[2], alpha_j_0[2]}), .SIGN_alpha({SIGN_alpha_j_7[2], SIGN_alpha_j_6[2], SIGN_alpha_j_5[2], SIGN_alpha_j_4[2], SIGN_alpha_j_3[2], SIGN_alpha_j_2[2], SIGN_alpha_j_1[2], SIGN_alpha_j_0[2]}), .delta_out(delta_out[2]), .SIGN_out(SIGN_delta_out[2])); 38 | NN_DELTABP_POLAR DELTABP_3(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[3]),.z(z[3]),.zp(zp[3]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[3], alpha_j_6[3], alpha_j_5[3], alpha_j_4[3], alpha_j_3[3], alpha_j_2[3], alpha_j_1[3], alpha_j_0[3]}), .SIGN_alpha({SIGN_alpha_j_7[3], SIGN_alpha_j_6[3], SIGN_alpha_j_5[3], SIGN_alpha_j_4[3], SIGN_alpha_j_3[3], SIGN_alpha_j_2[3], SIGN_alpha_j_1[3], SIGN_alpha_j_0[3]}), .delta_out(delta_out[3]), .SIGN_out(SIGN_delta_out[3])); 39 | NN_DELTABP_POLAR DELTABP_4(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[4]),.z(z[4]),.zp(zp[4]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[4], alpha_j_6[4], alpha_j_5[4], alpha_j_4[4], alpha_j_3[4], alpha_j_2[4], alpha_j_1[4], alpha_j_0[4]}), .SIGN_alpha({SIGN_alpha_j_7[4], SIGN_alpha_j_6[4], SIGN_alpha_j_5[4], SIGN_alpha_j_4[4], SIGN_alpha_j_3[4], SIGN_alpha_j_2[4], SIGN_alpha_j_1[4], SIGN_alpha_j_0[4]}), .delta_out(delta_out[4]), .SIGN_out(SIGN_delta_out[4])); 40 | NN_DELTABP_POLAR DELTABP_5(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[5]),.z(z[5]),.zp(zp[5]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[5], alpha_j_6[5], alpha_j_5[5], alpha_j_4[5], alpha_j_3[5], alpha_j_2[5], alpha_j_1[5], alpha_j_0[5]}), .SIGN_alpha({SIGN_alpha_j_7[5], SIGN_alpha_j_6[5], SIGN_alpha_j_5[5], SIGN_alpha_j_4[5], SIGN_alpha_j_3[5], SIGN_alpha_j_2[5], SIGN_alpha_j_1[5], SIGN_alpha_j_0[5]}), .delta_out(delta_out[5]), .SIGN_out(SIGN_delta_out[5])); 41 | NN_DELTABP_POLAR DELTABP_6(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[6]),.z(z[6]),.zp(zp[6]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[6], alpha_j_6[6], alpha_j_5[6], alpha_j_4[6], alpha_j_3[6], alpha_j_2[6], alpha_j_1[6], alpha_j_0[6]}), .SIGN_alpha({SIGN_alpha_j_7[6], SIGN_alpha_j_6[6], SIGN_alpha_j_5[6], SIGN_alpha_j_4[6], SIGN_alpha_j_3[6], SIGN_alpha_j_2[6], SIGN_alpha_j_1[6], SIGN_alpha_j_0[6]}), .delta_out(delta_out[6]), .SIGN_out(SIGN_delta_out[6])); 42 | NN_DELTABP_POLAR DELTABP_7(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[7]),.z(z[7]),.zp(zp[7]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[7], alpha_j_6[7], alpha_j_5[7], alpha_j_4[7], alpha_j_3[7], alpha_j_2[7], alpha_j_1[7], alpha_j_0[7]}), .SIGN_alpha({SIGN_alpha_j_7[7], SIGN_alpha_j_6[7], SIGN_alpha_j_5[7], SIGN_alpha_j_4[7], SIGN_alpha_j_3[7], SIGN_alpha_j_2[7], SIGN_alpha_j_1[7], SIGN_alpha_j_0[7]}), .delta_out(delta_out[7]), .SIGN_out(SIGN_delta_out[7])); 43 | NN_DELTABP_POLAR DELTABP_8(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[8]),.z(z[8]),.zp(zp[8]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[8], alpha_j_6[8], alpha_j_5[8], alpha_j_4[8], alpha_j_3[8], alpha_j_2[8], alpha_j_1[8], alpha_j_0[8]}), .SIGN_alpha({SIGN_alpha_j_7[8], SIGN_alpha_j_6[8], SIGN_alpha_j_5[8], SIGN_alpha_j_4[8], SIGN_alpha_j_3[8], SIGN_alpha_j_2[8], SIGN_alpha_j_1[8], SIGN_alpha_j_0[8]}), .delta_out(delta_out[8]), .SIGN_out(SIGN_delta_out[8])); 44 | NN_DELTABP_POLAR DELTABP_9(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[9]),.z(z[9]),.zp(zp[9]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[9], alpha_j_6[9], alpha_j_5[9], alpha_j_4[9], alpha_j_3[9], alpha_j_2[9], alpha_j_1[9], alpha_j_0[9]}), .SIGN_alpha({SIGN_alpha_j_7[9], SIGN_alpha_j_6[9], SIGN_alpha_j_5[9], SIGN_alpha_j_4[9], SIGN_alpha_j_3[9], SIGN_alpha_j_2[9], SIGN_alpha_j_1[9], SIGN_alpha_j_0[9]}), .delta_out(delta_out[9]), .SIGN_out(SIGN_delta_out[9])); 45 | NN_DELTABP_POLAR DELTABP_10(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[10]),.z(z[10]),.zp(zp[10]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[10], alpha_j_6[10], alpha_j_5[10], alpha_j_4[10], alpha_j_3[10], alpha_j_2[10], alpha_j_1[10], alpha_j_0[10]}), .SIGN_alpha({SIGN_alpha_j_7[10], SIGN_alpha_j_6[10], SIGN_alpha_j_5[10], SIGN_alpha_j_4[10], SIGN_alpha_j_3[10], SIGN_alpha_j_2[10], SIGN_alpha_j_1[10], SIGN_alpha_j_0[10]}), .delta_out(delta_out[10]), .SIGN_out(SIGN_delta_out[10])); 46 | NN_DELTABP_POLAR DELTABP_11(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[11]),.z(z[11]),.zp(zp[11]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[11], alpha_j_6[11], alpha_j_5[11], alpha_j_4[11], alpha_j_3[11], alpha_j_2[11], alpha_j_1[11], alpha_j_0[11]}), .SIGN_alpha({SIGN_alpha_j_7[11], SIGN_alpha_j_6[11], SIGN_alpha_j_5[11], SIGN_alpha_j_4[11], SIGN_alpha_j_3[11], SIGN_alpha_j_2[11], SIGN_alpha_j_1[11], SIGN_alpha_j_0[11]}), .delta_out(delta_out[11]), .SIGN_out(SIGN_delta_out[11])); 47 | NN_DELTABP_POLAR DELTABP_12(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[12]),.z(z[12]),.zp(zp[12]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[12], alpha_j_6[12], alpha_j_5[12], alpha_j_4[12], alpha_j_3[12], alpha_j_2[12], alpha_j_1[12], alpha_j_0[12]}), .SIGN_alpha({SIGN_alpha_j_7[12], SIGN_alpha_j_6[12], SIGN_alpha_j_5[12], SIGN_alpha_j_4[12], SIGN_alpha_j_3[12], SIGN_alpha_j_2[12], SIGN_alpha_j_1[12], SIGN_alpha_j_0[12]}), .delta_out(delta_out[12]), .SIGN_out(SIGN_delta_out[12])); 48 | NN_DELTABP_POLAR DELTABP_13(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[13]),.z(z[13]),.zp(zp[13]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[13], alpha_j_6[13], alpha_j_5[13], alpha_j_4[13], alpha_j_3[13], alpha_j_2[13], alpha_j_1[13], alpha_j_0[13]}), .SIGN_alpha({SIGN_alpha_j_7[13], SIGN_alpha_j_6[13], SIGN_alpha_j_5[13], SIGN_alpha_j_4[13], SIGN_alpha_j_3[13], SIGN_alpha_j_2[13], SIGN_alpha_j_1[13], SIGN_alpha_j_0[13]}), .delta_out(delta_out[13]), .SIGN_out(SIGN_delta_out[13])); 49 | NN_DELTABP_POLAR DELTABP_14(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[14]),.z(z[14]),.zp(zp[14]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[14], alpha_j_6[14], alpha_j_5[14], alpha_j_4[14], alpha_j_3[14], alpha_j_2[14], alpha_j_1[14], alpha_j_0[14]}), .SIGN_alpha({SIGN_alpha_j_7[14], SIGN_alpha_j_6[14], SIGN_alpha_j_5[14], SIGN_alpha_j_4[14], SIGN_alpha_j_3[14], SIGN_alpha_j_2[14], SIGN_alpha_j_1[14], SIGN_alpha_j_0[14]}), .delta_out(delta_out[14]), .SIGN_out(SIGN_delta_out[14])); 50 | NN_DELTABP_POLAR DELTABP_15(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[15]),.z(z[15]),.zp(zp[15]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[15], alpha_j_6[15], alpha_j_5[15], alpha_j_4[15], alpha_j_3[15], alpha_j_2[15], alpha_j_1[15], alpha_j_0[15]}), .SIGN_alpha({SIGN_alpha_j_7[15], SIGN_alpha_j_6[15], SIGN_alpha_j_5[15], SIGN_alpha_j_4[15], SIGN_alpha_j_3[15], SIGN_alpha_j_2[15], SIGN_alpha_j_1[15], SIGN_alpha_j_0[15]}), .delta_out(delta_out[15]), .SIGN_out(SIGN_delta_out[15])); 51 | NN_DELTABP_POLAR DELTABP_16(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[16]),.z(z[16]),.zp(zp[16]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[16], alpha_j_6[16], alpha_j_5[16], alpha_j_4[16], alpha_j_3[16], alpha_j_2[16], alpha_j_1[16], alpha_j_0[16]}), .SIGN_alpha({SIGN_alpha_j_7[16], SIGN_alpha_j_6[16], SIGN_alpha_j_5[16], SIGN_alpha_j_4[16], SIGN_alpha_j_3[16], SIGN_alpha_j_2[16], SIGN_alpha_j_1[16], SIGN_alpha_j_0[16]}), .delta_out(delta_out[16]), .SIGN_out(SIGN_delta_out[16])); 52 | NN_DELTABP_POLAR DELTABP_17(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[17]),.z(z[17]),.zp(zp[17]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[17], alpha_j_6[17], alpha_j_5[17], alpha_j_4[17], alpha_j_3[17], alpha_j_2[17], alpha_j_1[17], alpha_j_0[17]}), .SIGN_alpha({SIGN_alpha_j_7[17], SIGN_alpha_j_6[17], SIGN_alpha_j_5[17], SIGN_alpha_j_4[17], SIGN_alpha_j_3[17], SIGN_alpha_j_2[17], SIGN_alpha_j_1[17], SIGN_alpha_j_0[17]}), .delta_out(delta_out[17]), .SIGN_out(SIGN_delta_out[17])); 53 | NN_DELTABP_POLAR DELTABP_18(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[18]),.z(z[18]),.zp(zp[18]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[18], alpha_j_6[18], alpha_j_5[18], alpha_j_4[18], alpha_j_3[18], alpha_j_2[18], alpha_j_1[18], alpha_j_0[18]}), .SIGN_alpha({SIGN_alpha_j_7[18], SIGN_alpha_j_6[18], SIGN_alpha_j_5[18], SIGN_alpha_j_4[18], SIGN_alpha_j_3[18], SIGN_alpha_j_2[18], SIGN_alpha_j_1[18], SIGN_alpha_j_0[18]}), .delta_out(delta_out[18]), .SIGN_out(SIGN_delta_out[18])); 54 | NN_DELTABP_POLAR DELTABP_19(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[19]),.z(z[19]),.zp(zp[19]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[19], alpha_j_6[19], alpha_j_5[19], alpha_j_4[19], alpha_j_3[19], alpha_j_2[19], alpha_j_1[19], alpha_j_0[19]}), .SIGN_alpha({SIGN_alpha_j_7[19], SIGN_alpha_j_6[19], SIGN_alpha_j_5[19], SIGN_alpha_j_4[19], SIGN_alpha_j_3[19], SIGN_alpha_j_2[19], SIGN_alpha_j_1[19], SIGN_alpha_j_0[19]}), .delta_out(delta_out[19]), .SIGN_out(SIGN_delta_out[19])); 55 | NN_DELTABP_POLAR DELTABP_20(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[20]),.z(z[20]),.zp(zp[20]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[20], alpha_j_6[20], alpha_j_5[20], alpha_j_4[20], alpha_j_3[20], alpha_j_2[20], alpha_j_1[20], alpha_j_0[20]}), .SIGN_alpha({SIGN_alpha_j_7[20], SIGN_alpha_j_6[20], SIGN_alpha_j_5[20], SIGN_alpha_j_4[20], SIGN_alpha_j_3[20], SIGN_alpha_j_2[20], SIGN_alpha_j_1[20], SIGN_alpha_j_0[20]}), .delta_out(delta_out[20]), .SIGN_out(SIGN_delta_out[20])); 56 | NN_DELTABP_POLAR DELTABP_21(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[21]),.z(z[21]),.zp(zp[21]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[21], alpha_j_6[21], alpha_j_5[21], alpha_j_4[21], alpha_j_3[21], alpha_j_2[21], alpha_j_1[21], alpha_j_0[21]}), .SIGN_alpha({SIGN_alpha_j_7[21], SIGN_alpha_j_6[21], SIGN_alpha_j_5[21], SIGN_alpha_j_4[21], SIGN_alpha_j_3[21], SIGN_alpha_j_2[21], SIGN_alpha_j_1[21], SIGN_alpha_j_0[21]}), .delta_out(delta_out[21]), .SIGN_out(SIGN_delta_out[21])); 57 | NN_DELTABP_POLAR DELTABP_22(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[22]),.z(z[22]),.zp(zp[22]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[22], alpha_j_6[22], alpha_j_5[22], alpha_j_4[22], alpha_j_3[22], alpha_j_2[22], alpha_j_1[22], alpha_j_0[22]}), .SIGN_alpha({SIGN_alpha_j_7[22], SIGN_alpha_j_6[22], SIGN_alpha_j_5[22], SIGN_alpha_j_4[22], SIGN_alpha_j_3[22], SIGN_alpha_j_2[22], SIGN_alpha_j_1[22], SIGN_alpha_j_0[22]}), .delta_out(delta_out[22]), .SIGN_out(SIGN_delta_out[22])); 58 | NN_DELTABP_POLAR DELTABP_23(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[23]),.z(z[23]),.zp(zp[23]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[23], alpha_j_6[23], alpha_j_5[23], alpha_j_4[23], alpha_j_3[23], alpha_j_2[23], alpha_j_1[23], alpha_j_0[23]}), .SIGN_alpha({SIGN_alpha_j_7[23], SIGN_alpha_j_6[23], SIGN_alpha_j_5[23], SIGN_alpha_j_4[23], SIGN_alpha_j_3[23], SIGN_alpha_j_2[23], SIGN_alpha_j_1[23], SIGN_alpha_j_0[23]}), .delta_out(delta_out[23]), .SIGN_out(SIGN_delta_out[23])); 59 | NN_DELTABP_POLAR DELTABP_24(.CLK(CLK),.INIT(INIT),.R_condition(R_BP[24]),.z(z[24]),.zp(zp[24]),.delta(delta_in),.SIGN_delta(SIGN_delta_in), .alpha({alpha_j_7[24], alpha_j_6[24], alpha_j_5[24], alpha_j_4[24], alpha_j_3[24], alpha_j_2[24], alpha_j_1[24], alpha_j_0[24]}), .SIGN_alpha({SIGN_alpha_j_7[24], SIGN_alpha_j_6[24], SIGN_alpha_j_5[24], SIGN_alpha_j_4[24], SIGN_alpha_j_3[24], SIGN_alpha_j_2[24], SIGN_alpha_j_1[24], SIGN_alpha_j_0[24]}), .delta_out(delta_out[24]), .SIGN_out(SIGN_delta_out[24])); 60 | defparam DELTABP_0.N = 8; 61 | defparam DELTABP_1.N = 8; 62 | defparam DELTABP_2.N = 8; 63 | defparam DELTABP_3.N = 8; 64 | defparam DELTABP_4.N = 8; 65 | defparam DELTABP_5.N = 8; 66 | defparam DELTABP_6.N = 8; 67 | defparam DELTABP_7.N = 8; 68 | defparam DELTABP_8.N = 8; 69 | defparam DELTABP_9.N = 8; 70 | defparam DELTABP_10.N = 8; 71 | defparam DELTABP_11.N = 8; 72 | defparam DELTABP_12.N = 8; 73 | defparam DELTABP_13.N = 8; 74 | defparam DELTABP_14.N = 8; 75 | defparam DELTABP_15.N = 8; 76 | defparam DELTABP_16.N = 8; 77 | defparam DELTABP_17.N = 8; 78 | defparam DELTABP_18.N = 8; 79 | defparam DELTABP_19.N = 8; 80 | defparam DELTABP_20.N = 8; 81 | defparam DELTABP_21.N = 8; 82 | defparam DELTABP_22.N = 8; 83 | defparam DELTABP_23.N = 8; 84 | defparam DELTABP_24.N = 8; 85 | 86 | endmodule -------------------------------------------------------------------------------- /FullyConnectedSNN/PARAMS_portDefinitions.v: -------------------------------------------------------------------------------- 1 | .alphaD_L1_0_0(alphaD_L1_0_0), .alphaD_L1_0_1(alphaD_L1_0_1), .alphaD_L1_0_2(alphaD_L1_0_2), .alphaD_L1_0_3(alphaD_L1_0_3), .alphaD_L1_0_4(alphaD_L1_0_4), .alphaD_L1_0_5(alphaD_L1_0_5), .alphaD_L1_0_6(alphaD_L1_0_6), .alphaD_L1_0_7(alphaD_L1_0_7), .alphaD_L1_0_8(alphaD_L1_0_8), .alphaD_L1_0_9(alphaD_L1_0_9), .alphaD_L1_0_10(alphaD_L1_0_10), .alphaD_L1_0_11(alphaD_L1_0_11), .alphaD_L1_0_12(alphaD_L1_0_12), .alphaD_L1_0_13(alphaD_L1_0_13), .alphaD_L1_0_14(alphaD_L1_0_14), .alphaD_L1_0_15(alphaD_L1_0_15), .alphaD_L1_0_16(alphaD_L1_0_16), .alphaD_L1_0_17(alphaD_L1_0_17), .alphaD_L1_0_18(alphaD_L1_0_18), .alphaD_L1_0_19(alphaD_L1_0_19), .alphaD_L1_0_20(alphaD_L1_0_20), .alphaD_L1_0_21(alphaD_L1_0_21), .alphaD_L1_0_22(alphaD_L1_0_22), .alphaD_L1_0_23(alphaD_L1_0_23), .alphaD_L1_0_24(alphaD_L1_0_24), 2 | .alphaD_L1_1_0(alphaD_L1_1_0), .alphaD_L1_1_1(alphaD_L1_1_1), .alphaD_L1_1_2(alphaD_L1_1_2), .alphaD_L1_1_3(alphaD_L1_1_3), .alphaD_L1_1_4(alphaD_L1_1_4), .alphaD_L1_1_5(alphaD_L1_1_5), .alphaD_L1_1_6(alphaD_L1_1_6), .alphaD_L1_1_7(alphaD_L1_1_7), .alphaD_L1_1_8(alphaD_L1_1_8), .alphaD_L1_1_9(alphaD_L1_1_9), .alphaD_L1_1_10(alphaD_L1_1_10), .alphaD_L1_1_11(alphaD_L1_1_11), .alphaD_L1_1_12(alphaD_L1_1_12), .alphaD_L1_1_13(alphaD_L1_1_13), .alphaD_L1_1_14(alphaD_L1_1_14), .alphaD_L1_1_15(alphaD_L1_1_15), .alphaD_L1_1_16(alphaD_L1_1_16), .alphaD_L1_1_17(alphaD_L1_1_17), .alphaD_L1_1_18(alphaD_L1_1_18), .alphaD_L1_1_19(alphaD_L1_1_19), .alphaD_L1_1_20(alphaD_L1_1_20), .alphaD_L1_1_21(alphaD_L1_1_21), .alphaD_L1_1_22(alphaD_L1_1_22), .alphaD_L1_1_23(alphaD_L1_1_23), .alphaD_L1_1_24(alphaD_L1_1_24), 3 | .alphaD_L1_2_0(alphaD_L1_2_0), .alphaD_L1_2_1(alphaD_L1_2_1), .alphaD_L1_2_2(alphaD_L1_2_2), .alphaD_L1_2_3(alphaD_L1_2_3), .alphaD_L1_2_4(alphaD_L1_2_4), .alphaD_L1_2_5(alphaD_L1_2_5), .alphaD_L1_2_6(alphaD_L1_2_6), .alphaD_L1_2_7(alphaD_L1_2_7), .alphaD_L1_2_8(alphaD_L1_2_8), .alphaD_L1_2_9(alphaD_L1_2_9), .alphaD_L1_2_10(alphaD_L1_2_10), .alphaD_L1_2_11(alphaD_L1_2_11), .alphaD_L1_2_12(alphaD_L1_2_12), .alphaD_L1_2_13(alphaD_L1_2_13), .alphaD_L1_2_14(alphaD_L1_2_14), .alphaD_L1_2_15(alphaD_L1_2_15), .alphaD_L1_2_16(alphaD_L1_2_16), .alphaD_L1_2_17(alphaD_L1_2_17), .alphaD_L1_2_18(alphaD_L1_2_18), .alphaD_L1_2_19(alphaD_L1_2_19), .alphaD_L1_2_20(alphaD_L1_2_20), .alphaD_L1_2_21(alphaD_L1_2_21), .alphaD_L1_2_22(alphaD_L1_2_22), .alphaD_L1_2_23(alphaD_L1_2_23), .alphaD_L1_2_24(alphaD_L1_2_24), 4 | .alphaD_L1_3_0(alphaD_L1_3_0), .alphaD_L1_3_1(alphaD_L1_3_1), .alphaD_L1_3_2(alphaD_L1_3_2), .alphaD_L1_3_3(alphaD_L1_3_3), .alphaD_L1_3_4(alphaD_L1_3_4), .alphaD_L1_3_5(alphaD_L1_3_5), .alphaD_L1_3_6(alphaD_L1_3_6), .alphaD_L1_3_7(alphaD_L1_3_7), .alphaD_L1_3_8(alphaD_L1_3_8), .alphaD_L1_3_9(alphaD_L1_3_9), .alphaD_L1_3_10(alphaD_L1_3_10), .alphaD_L1_3_11(alphaD_L1_3_11), .alphaD_L1_3_12(alphaD_L1_3_12), .alphaD_L1_3_13(alphaD_L1_3_13), .alphaD_L1_3_14(alphaD_L1_3_14), .alphaD_L1_3_15(alphaD_L1_3_15), .alphaD_L1_3_16(alphaD_L1_3_16), .alphaD_L1_3_17(alphaD_L1_3_17), .alphaD_L1_3_18(alphaD_L1_3_18), .alphaD_L1_3_19(alphaD_L1_3_19), .alphaD_L1_3_20(alphaD_L1_3_20), .alphaD_L1_3_21(alphaD_L1_3_21), .alphaD_L1_3_22(alphaD_L1_3_22), .alphaD_L1_3_23(alphaD_L1_3_23), .alphaD_L1_3_24(alphaD_L1_3_24), 5 | .alphaD_L1_4_0(alphaD_L1_4_0), .alphaD_L1_4_1(alphaD_L1_4_1), .alphaD_L1_4_2(alphaD_L1_4_2), .alphaD_L1_4_3(alphaD_L1_4_3), .alphaD_L1_4_4(alphaD_L1_4_4), .alphaD_L1_4_5(alphaD_L1_4_5), .alphaD_L1_4_6(alphaD_L1_4_6), .alphaD_L1_4_7(alphaD_L1_4_7), .alphaD_L1_4_8(alphaD_L1_4_8), .alphaD_L1_4_9(alphaD_L1_4_9), .alphaD_L1_4_10(alphaD_L1_4_10), .alphaD_L1_4_11(alphaD_L1_4_11), .alphaD_L1_4_12(alphaD_L1_4_12), .alphaD_L1_4_13(alphaD_L1_4_13), .alphaD_L1_4_14(alphaD_L1_4_14), .alphaD_L1_4_15(alphaD_L1_4_15), .alphaD_L1_4_16(alphaD_L1_4_16), .alphaD_L1_4_17(alphaD_L1_4_17), .alphaD_L1_4_18(alphaD_L1_4_18), .alphaD_L1_4_19(alphaD_L1_4_19), .alphaD_L1_4_20(alphaD_L1_4_20), .alphaD_L1_4_21(alphaD_L1_4_21), .alphaD_L1_4_22(alphaD_L1_4_22), .alphaD_L1_4_23(alphaD_L1_4_23), .alphaD_L1_4_24(alphaD_L1_4_24), 6 | .betaD_L1_0(betaD_L1_0), .betaD_L1_1(betaD_L1_1), .betaD_L1_2(betaD_L1_2), .betaD_L1_3(betaD_L1_3), .betaD_L1_4(betaD_L1_4), .betaD_L1_5(betaD_L1_5), .betaD_L1_6(betaD_L1_6), .betaD_L1_7(betaD_L1_7), .betaD_L1_8(betaD_L1_8), .betaD_L1_9(betaD_L1_9), .betaD_L1_10(betaD_L1_10), .betaD_L1_11(betaD_L1_11), .betaD_L1_12(betaD_L1_12), .betaD_L1_13(betaD_L1_13), .betaD_L1_14(betaD_L1_14), .betaD_L1_15(betaD_L1_15), .betaD_L1_16(betaD_L1_16), .betaD_L1_17(betaD_L1_17), .betaD_L1_18(betaD_L1_18), .betaD_L1_19(betaD_L1_19), .betaD_L1_20(betaD_L1_20), .betaD_L1_21(betaD_L1_21), .betaD_L1_22(betaD_L1_22), .betaD_L1_23(betaD_L1_23), .betaD_L1_24(betaD_L1_24), 7 | .alphaD_L2_0_0(alphaD_L2_0_0), .alphaD_L2_0_1(alphaD_L2_0_1), .alphaD_L2_0_2(alphaD_L2_0_2), .alphaD_L2_0_3(alphaD_L2_0_3), .alphaD_L2_0_4(alphaD_L2_0_4), .alphaD_L2_0_5(alphaD_L2_0_5), .alphaD_L2_0_6(alphaD_L2_0_6), .alphaD_L2_0_7(alphaD_L2_0_7), 8 | .alphaD_L2_1_0(alphaD_L2_1_0), .alphaD_L2_1_1(alphaD_L2_1_1), .alphaD_L2_1_2(alphaD_L2_1_2), .alphaD_L2_1_3(alphaD_L2_1_3), .alphaD_L2_1_4(alphaD_L2_1_4), .alphaD_L2_1_5(alphaD_L2_1_5), .alphaD_L2_1_6(alphaD_L2_1_6), .alphaD_L2_1_7(alphaD_L2_1_7), 9 | .alphaD_L2_2_0(alphaD_L2_2_0), .alphaD_L2_2_1(alphaD_L2_2_1), .alphaD_L2_2_2(alphaD_L2_2_2), .alphaD_L2_2_3(alphaD_L2_2_3), .alphaD_L2_2_4(alphaD_L2_2_4), .alphaD_L2_2_5(alphaD_L2_2_5), .alphaD_L2_2_6(alphaD_L2_2_6), .alphaD_L2_2_7(alphaD_L2_2_7), 10 | .alphaD_L2_3_0(alphaD_L2_3_0), .alphaD_L2_3_1(alphaD_L2_3_1), .alphaD_L2_3_2(alphaD_L2_3_2), .alphaD_L2_3_3(alphaD_L2_3_3), .alphaD_L2_3_4(alphaD_L2_3_4), .alphaD_L2_3_5(alphaD_L2_3_5), .alphaD_L2_3_6(alphaD_L2_3_6), .alphaD_L2_3_7(alphaD_L2_3_7), 11 | .alphaD_L2_4_0(alphaD_L2_4_0), .alphaD_L2_4_1(alphaD_L2_4_1), .alphaD_L2_4_2(alphaD_L2_4_2), .alphaD_L2_4_3(alphaD_L2_4_3), .alphaD_L2_4_4(alphaD_L2_4_4), .alphaD_L2_4_5(alphaD_L2_4_5), .alphaD_L2_4_6(alphaD_L2_4_6), .alphaD_L2_4_7(alphaD_L2_4_7), 12 | .alphaD_L2_5_0(alphaD_L2_5_0), .alphaD_L2_5_1(alphaD_L2_5_1), .alphaD_L2_5_2(alphaD_L2_5_2), .alphaD_L2_5_3(alphaD_L2_5_3), .alphaD_L2_5_4(alphaD_L2_5_4), .alphaD_L2_5_5(alphaD_L2_5_5), .alphaD_L2_5_6(alphaD_L2_5_6), .alphaD_L2_5_7(alphaD_L2_5_7), 13 | .alphaD_L2_6_0(alphaD_L2_6_0), .alphaD_L2_6_1(alphaD_L2_6_1), .alphaD_L2_6_2(alphaD_L2_6_2), .alphaD_L2_6_3(alphaD_L2_6_3), .alphaD_L2_6_4(alphaD_L2_6_4), .alphaD_L2_6_5(alphaD_L2_6_5), .alphaD_L2_6_6(alphaD_L2_6_6), .alphaD_L2_6_7(alphaD_L2_6_7), 14 | .alphaD_L2_7_0(alphaD_L2_7_0), .alphaD_L2_7_1(alphaD_L2_7_1), .alphaD_L2_7_2(alphaD_L2_7_2), .alphaD_L2_7_3(alphaD_L2_7_3), .alphaD_L2_7_4(alphaD_L2_7_4), .alphaD_L2_7_5(alphaD_L2_7_5), .alphaD_L2_7_6(alphaD_L2_7_6), .alphaD_L2_7_7(alphaD_L2_7_7), 15 | .alphaD_L2_8_0(alphaD_L2_8_0), .alphaD_L2_8_1(alphaD_L2_8_1), .alphaD_L2_8_2(alphaD_L2_8_2), .alphaD_L2_8_3(alphaD_L2_8_3), .alphaD_L2_8_4(alphaD_L2_8_4), .alphaD_L2_8_5(alphaD_L2_8_5), .alphaD_L2_8_6(alphaD_L2_8_6), .alphaD_L2_8_7(alphaD_L2_8_7), 16 | .alphaD_L2_9_0(alphaD_L2_9_0), .alphaD_L2_9_1(alphaD_L2_9_1), .alphaD_L2_9_2(alphaD_L2_9_2), .alphaD_L2_9_3(alphaD_L2_9_3), .alphaD_L2_9_4(alphaD_L2_9_4), .alphaD_L2_9_5(alphaD_L2_9_5), .alphaD_L2_9_6(alphaD_L2_9_6), .alphaD_L2_9_7(alphaD_L2_9_7), 17 | .alphaD_L2_10_0(alphaD_L2_10_0), .alphaD_L2_10_1(alphaD_L2_10_1), .alphaD_L2_10_2(alphaD_L2_10_2), .alphaD_L2_10_3(alphaD_L2_10_3), .alphaD_L2_10_4(alphaD_L2_10_4), .alphaD_L2_10_5(alphaD_L2_10_5), .alphaD_L2_10_6(alphaD_L2_10_6), .alphaD_L2_10_7(alphaD_L2_10_7), 18 | .alphaD_L2_11_0(alphaD_L2_11_0), .alphaD_L2_11_1(alphaD_L2_11_1), .alphaD_L2_11_2(alphaD_L2_11_2), .alphaD_L2_11_3(alphaD_L2_11_3), .alphaD_L2_11_4(alphaD_L2_11_4), .alphaD_L2_11_5(alphaD_L2_11_5), .alphaD_L2_11_6(alphaD_L2_11_6), .alphaD_L2_11_7(alphaD_L2_11_7), 19 | .alphaD_L2_12_0(alphaD_L2_12_0), .alphaD_L2_12_1(alphaD_L2_12_1), .alphaD_L2_12_2(alphaD_L2_12_2), .alphaD_L2_12_3(alphaD_L2_12_3), .alphaD_L2_12_4(alphaD_L2_12_4), .alphaD_L2_12_5(alphaD_L2_12_5), .alphaD_L2_12_6(alphaD_L2_12_6), .alphaD_L2_12_7(alphaD_L2_12_7), 20 | .alphaD_L2_13_0(alphaD_L2_13_0), .alphaD_L2_13_1(alphaD_L2_13_1), .alphaD_L2_13_2(alphaD_L2_13_2), .alphaD_L2_13_3(alphaD_L2_13_3), .alphaD_L2_13_4(alphaD_L2_13_4), .alphaD_L2_13_5(alphaD_L2_13_5), .alphaD_L2_13_6(alphaD_L2_13_6), .alphaD_L2_13_7(alphaD_L2_13_7), 21 | .alphaD_L2_14_0(alphaD_L2_14_0), .alphaD_L2_14_1(alphaD_L2_14_1), .alphaD_L2_14_2(alphaD_L2_14_2), .alphaD_L2_14_3(alphaD_L2_14_3), .alphaD_L2_14_4(alphaD_L2_14_4), .alphaD_L2_14_5(alphaD_L2_14_5), .alphaD_L2_14_6(alphaD_L2_14_6), .alphaD_L2_14_7(alphaD_L2_14_7), 22 | .alphaD_L2_15_0(alphaD_L2_15_0), .alphaD_L2_15_1(alphaD_L2_15_1), .alphaD_L2_15_2(alphaD_L2_15_2), .alphaD_L2_15_3(alphaD_L2_15_3), .alphaD_L2_15_4(alphaD_L2_15_4), .alphaD_L2_15_5(alphaD_L2_15_5), .alphaD_L2_15_6(alphaD_L2_15_6), .alphaD_L2_15_7(alphaD_L2_15_7), 23 | .alphaD_L2_16_0(alphaD_L2_16_0), .alphaD_L2_16_1(alphaD_L2_16_1), .alphaD_L2_16_2(alphaD_L2_16_2), .alphaD_L2_16_3(alphaD_L2_16_3), .alphaD_L2_16_4(alphaD_L2_16_4), .alphaD_L2_16_5(alphaD_L2_16_5), .alphaD_L2_16_6(alphaD_L2_16_6), .alphaD_L2_16_7(alphaD_L2_16_7), 24 | .alphaD_L2_17_0(alphaD_L2_17_0), .alphaD_L2_17_1(alphaD_L2_17_1), .alphaD_L2_17_2(alphaD_L2_17_2), .alphaD_L2_17_3(alphaD_L2_17_3), .alphaD_L2_17_4(alphaD_L2_17_4), .alphaD_L2_17_5(alphaD_L2_17_5), .alphaD_L2_17_6(alphaD_L2_17_6), .alphaD_L2_17_7(alphaD_L2_17_7), 25 | .alphaD_L2_18_0(alphaD_L2_18_0), .alphaD_L2_18_1(alphaD_L2_18_1), .alphaD_L2_18_2(alphaD_L2_18_2), .alphaD_L2_18_3(alphaD_L2_18_3), .alphaD_L2_18_4(alphaD_L2_18_4), .alphaD_L2_18_5(alphaD_L2_18_5), .alphaD_L2_18_6(alphaD_L2_18_6), .alphaD_L2_18_7(alphaD_L2_18_7), 26 | .alphaD_L2_19_0(alphaD_L2_19_0), .alphaD_L2_19_1(alphaD_L2_19_1), .alphaD_L2_19_2(alphaD_L2_19_2), .alphaD_L2_19_3(alphaD_L2_19_3), .alphaD_L2_19_4(alphaD_L2_19_4), .alphaD_L2_19_5(alphaD_L2_19_5), .alphaD_L2_19_6(alphaD_L2_19_6), .alphaD_L2_19_7(alphaD_L2_19_7), 27 | .alphaD_L2_20_0(alphaD_L2_20_0), .alphaD_L2_20_1(alphaD_L2_20_1), .alphaD_L2_20_2(alphaD_L2_20_2), .alphaD_L2_20_3(alphaD_L2_20_3), .alphaD_L2_20_4(alphaD_L2_20_4), .alphaD_L2_20_5(alphaD_L2_20_5), .alphaD_L2_20_6(alphaD_L2_20_6), .alphaD_L2_20_7(alphaD_L2_20_7), 28 | .alphaD_L2_21_0(alphaD_L2_21_0), .alphaD_L2_21_1(alphaD_L2_21_1), .alphaD_L2_21_2(alphaD_L2_21_2), .alphaD_L2_21_3(alphaD_L2_21_3), .alphaD_L2_21_4(alphaD_L2_21_4), .alphaD_L2_21_5(alphaD_L2_21_5), .alphaD_L2_21_6(alphaD_L2_21_6), .alphaD_L2_21_7(alphaD_L2_21_7), 29 | .alphaD_L2_22_0(alphaD_L2_22_0), .alphaD_L2_22_1(alphaD_L2_22_1), .alphaD_L2_22_2(alphaD_L2_22_2), .alphaD_L2_22_3(alphaD_L2_22_3), .alphaD_L2_22_4(alphaD_L2_22_4), .alphaD_L2_22_5(alphaD_L2_22_5), .alphaD_L2_22_6(alphaD_L2_22_6), .alphaD_L2_22_7(alphaD_L2_22_7), 30 | .alphaD_L2_23_0(alphaD_L2_23_0), .alphaD_L2_23_1(alphaD_L2_23_1), .alphaD_L2_23_2(alphaD_L2_23_2), .alphaD_L2_23_3(alphaD_L2_23_3), .alphaD_L2_23_4(alphaD_L2_23_4), .alphaD_L2_23_5(alphaD_L2_23_5), .alphaD_L2_23_6(alphaD_L2_23_6), .alphaD_L2_23_7(alphaD_L2_23_7), 31 | .alphaD_L2_24_0(alphaD_L2_24_0), .alphaD_L2_24_1(alphaD_L2_24_1), .alphaD_L2_24_2(alphaD_L2_24_2), .alphaD_L2_24_3(alphaD_L2_24_3), .alphaD_L2_24_4(alphaD_L2_24_4), .alphaD_L2_24_5(alphaD_L2_24_5), .alphaD_L2_24_6(alphaD_L2_24_6), .alphaD_L2_24_7(alphaD_L2_24_7), 32 | .betaD_L2_0(betaD_L2_0), .betaD_L2_1(betaD_L2_1), .betaD_L2_2(betaD_L2_2), .betaD_L2_3(betaD_L2_3), .betaD_L2_4(betaD_L2_4), .betaD_L2_5(betaD_L2_5), .betaD_L2_6(betaD_L2_6), .betaD_L2_7(betaD_L2_7), 33 | .alphaD_L3_0_0(alphaD_L3_0_0), .alphaD_L3_0_1(alphaD_L3_0_1), .alphaD_L3_0_2(alphaD_L3_0_2), .alphaD_L3_0_3(alphaD_L3_0_3), .alphaD_L3_0_4(alphaD_L3_0_4), 34 | .alphaD_L3_1_0(alphaD_L3_1_0), .alphaD_L3_1_1(alphaD_L3_1_1), .alphaD_L3_1_2(alphaD_L3_1_2), .alphaD_L3_1_3(alphaD_L3_1_3), .alphaD_L3_1_4(alphaD_L3_1_4), 35 | .alphaD_L3_2_0(alphaD_L3_2_0), .alphaD_L3_2_1(alphaD_L3_2_1), .alphaD_L3_2_2(alphaD_L3_2_2), .alphaD_L3_2_3(alphaD_L3_2_3), .alphaD_L3_2_4(alphaD_L3_2_4), 36 | .alphaD_L3_3_0(alphaD_L3_3_0), .alphaD_L3_3_1(alphaD_L3_3_1), .alphaD_L3_3_2(alphaD_L3_3_2), .alphaD_L3_3_3(alphaD_L3_3_3), .alphaD_L3_3_4(alphaD_L3_3_4), 37 | .alphaD_L3_4_0(alphaD_L3_4_0), .alphaD_L3_4_1(alphaD_L3_4_1), .alphaD_L3_4_2(alphaD_L3_4_2), .alphaD_L3_4_3(alphaD_L3_4_3), .alphaD_L3_4_4(alphaD_L3_4_4), 38 | .alphaD_L3_5_0(alphaD_L3_5_0), .alphaD_L3_5_1(alphaD_L3_5_1), .alphaD_L3_5_2(alphaD_L3_5_2), .alphaD_L3_5_3(alphaD_L3_5_3), .alphaD_L3_5_4(alphaD_L3_5_4), 39 | .alphaD_L3_6_0(alphaD_L3_6_0), .alphaD_L3_6_1(alphaD_L3_6_1), .alphaD_L3_6_2(alphaD_L3_6_2), .alphaD_L3_6_3(alphaD_L3_6_3), .alphaD_L3_6_4(alphaD_L3_6_4), 40 | .alphaD_L3_7_0(alphaD_L3_7_0), .alphaD_L3_7_1(alphaD_L3_7_1), .alphaD_L3_7_2(alphaD_L3_7_2), .alphaD_L3_7_3(alphaD_L3_7_3), .alphaD_L3_7_4(alphaD_L3_7_4), 41 | .betaD_L3_0(betaD_L3_0), .betaD_L3_1(betaD_L3_1), .betaD_L3_2(betaD_L3_2), .betaD_L3_3(betaD_L3_3), .betaD_L3_4(betaD_L3_4), 42 | .SIGN_alpha_L1_j_0(SIGN_alpha_L1_j_0), .SIGN_alpha_L1_j_1(SIGN_alpha_L1_j_1), .SIGN_alpha_L1_j_2(SIGN_alpha_L1_j_2), .SIGN_alpha_L1_j_3(SIGN_alpha_L1_j_3), .SIGN_alpha_L1_j_4(SIGN_alpha_L1_j_4), .SIGN_alpha_L1_j_5(SIGN_alpha_L1_j_5), .SIGN_alpha_L1_j_6(SIGN_alpha_L1_j_6), .SIGN_alpha_L1_j_7(SIGN_alpha_L1_j_7), .SIGN_alpha_L1_j_8(SIGN_alpha_L1_j_8), .SIGN_alpha_L1_j_9(SIGN_alpha_L1_j_9), .SIGN_alpha_L1_j_10(SIGN_alpha_L1_j_10), .SIGN_alpha_L1_j_11(SIGN_alpha_L1_j_11), .SIGN_alpha_L1_j_12(SIGN_alpha_L1_j_12), .SIGN_alpha_L1_j_13(SIGN_alpha_L1_j_13), .SIGN_alpha_L1_j_14(SIGN_alpha_L1_j_14), .SIGN_alpha_L1_j_15(SIGN_alpha_L1_j_15), .SIGN_alpha_L1_j_16(SIGN_alpha_L1_j_16), .SIGN_alpha_L1_j_17(SIGN_alpha_L1_j_17), .SIGN_alpha_L1_j_18(SIGN_alpha_L1_j_18), .SIGN_alpha_L1_j_19(SIGN_alpha_L1_j_19), .SIGN_alpha_L1_j_20(SIGN_alpha_L1_j_20), .SIGN_alpha_L1_j_21(SIGN_alpha_L1_j_21), .SIGN_alpha_L1_j_22(SIGN_alpha_L1_j_22), .SIGN_alpha_L1_j_23(SIGN_alpha_L1_j_23), .SIGN_alpha_L1_j_24(SIGN_alpha_L1_j_24), 43 | .SIGN_beta_L1(SIGN_beta_L1), 44 | .SIGN_alpha_L2_j_0(SIGN_alpha_L2_j_0), .SIGN_alpha_L2_j_1(SIGN_alpha_L2_j_1), .SIGN_alpha_L2_j_2(SIGN_alpha_L2_j_2), .SIGN_alpha_L2_j_3(SIGN_alpha_L2_j_3), .SIGN_alpha_L2_j_4(SIGN_alpha_L2_j_4), .SIGN_alpha_L2_j_5(SIGN_alpha_L2_j_5), .SIGN_alpha_L2_j_6(SIGN_alpha_L2_j_6), .SIGN_alpha_L2_j_7(SIGN_alpha_L2_j_7), 45 | .SIGN_beta_L2(SIGN_beta_L2), 46 | .SIGN_alpha_L3_j_0(SIGN_alpha_L3_j_0), .SIGN_alpha_L3_j_1(SIGN_alpha_L3_j_1), .SIGN_alpha_L3_j_2(SIGN_alpha_L3_j_2), .SIGN_alpha_L3_j_3(SIGN_alpha_L3_j_3), .SIGN_alpha_L3_j_4(SIGN_alpha_L3_j_4), 47 | .SIGN_beta_L3(SIGN_beta_L3), 48 | .dalpha_L1_j_0(dalpha_L1_j_0), .dalpha_L1_j_1(dalpha_L1_j_1), .dalpha_L1_j_2(dalpha_L1_j_2), .dalpha_L1_j_3(dalpha_L1_j_3), .dalpha_L1_j_4(dalpha_L1_j_4), .dalpha_L1_j_5(dalpha_L1_j_5), .dalpha_L1_j_6(dalpha_L1_j_6), .dalpha_L1_j_7(dalpha_L1_j_7), .dalpha_L1_j_8(dalpha_L1_j_8), .dalpha_L1_j_9(dalpha_L1_j_9), .dalpha_L1_j_10(dalpha_L1_j_10), .dalpha_L1_j_11(dalpha_L1_j_11), .dalpha_L1_j_12(dalpha_L1_j_12), .dalpha_L1_j_13(dalpha_L1_j_13), .dalpha_L1_j_14(dalpha_L1_j_14), .dalpha_L1_j_15(dalpha_L1_j_15), .dalpha_L1_j_16(dalpha_L1_j_16), .dalpha_L1_j_17(dalpha_L1_j_17), .dalpha_L1_j_18(dalpha_L1_j_18), .dalpha_L1_j_19(dalpha_L1_j_19), .dalpha_L1_j_20(dalpha_L1_j_20), .dalpha_L1_j_21(dalpha_L1_j_21), .dalpha_L1_j_22(dalpha_L1_j_22), .dalpha_L1_j_23(dalpha_L1_j_23), .dalpha_L1_j_24(dalpha_L1_j_24), 49 | .dbeta_L1(dbeta_L1), 50 | .dalpha_L2_j_0(dalpha_L2_j_0), .dalpha_L2_j_1(dalpha_L2_j_1), .dalpha_L2_j_2(dalpha_L2_j_2), .dalpha_L2_j_3(dalpha_L2_j_3), .dalpha_L2_j_4(dalpha_L2_j_4), .dalpha_L2_j_5(dalpha_L2_j_5), .dalpha_L2_j_6(dalpha_L2_j_6), .dalpha_L2_j_7(dalpha_L2_j_7), 51 | .dbeta_L2(dbeta_L2), 52 | .dalpha_L3_j_0(dalpha_L3_j_0), .dalpha_L3_j_1(dalpha_L3_j_1), .dalpha_L3_j_2(dalpha_L3_j_2), .dalpha_L3_j_3(dalpha_L3_j_3), .dalpha_L3_j_4(dalpha_L3_j_4), 53 | .dbeta_L3(dbeta_L3), 54 | .SIGN_dalpha_L1_j_0(SIGN_dalpha_L1_j_0), .SIGN_dalpha_L1_j_1(SIGN_dalpha_L1_j_1), .SIGN_dalpha_L1_j_2(SIGN_dalpha_L1_j_2), .SIGN_dalpha_L1_j_3(SIGN_dalpha_L1_j_3), .SIGN_dalpha_L1_j_4(SIGN_dalpha_L1_j_4), .SIGN_dalpha_L1_j_5(SIGN_dalpha_L1_j_5), .SIGN_dalpha_L1_j_6(SIGN_dalpha_L1_j_6), .SIGN_dalpha_L1_j_7(SIGN_dalpha_L1_j_7), .SIGN_dalpha_L1_j_8(SIGN_dalpha_L1_j_8), .SIGN_dalpha_L1_j_9(SIGN_dalpha_L1_j_9), .SIGN_dalpha_L1_j_10(SIGN_dalpha_L1_j_10), .SIGN_dalpha_L1_j_11(SIGN_dalpha_L1_j_11), .SIGN_dalpha_L1_j_12(SIGN_dalpha_L1_j_12), .SIGN_dalpha_L1_j_13(SIGN_dalpha_L1_j_13), .SIGN_dalpha_L1_j_14(SIGN_dalpha_L1_j_14), .SIGN_dalpha_L1_j_15(SIGN_dalpha_L1_j_15), .SIGN_dalpha_L1_j_16(SIGN_dalpha_L1_j_16), .SIGN_dalpha_L1_j_17(SIGN_dalpha_L1_j_17), .SIGN_dalpha_L1_j_18(SIGN_dalpha_L1_j_18), .SIGN_dalpha_L1_j_19(SIGN_dalpha_L1_j_19), .SIGN_dalpha_L1_j_20(SIGN_dalpha_L1_j_20), .SIGN_dalpha_L1_j_21(SIGN_dalpha_L1_j_21), .SIGN_dalpha_L1_j_22(SIGN_dalpha_L1_j_22), .SIGN_dalpha_L1_j_23(SIGN_dalpha_L1_j_23), .SIGN_dalpha_L1_j_24(SIGN_dalpha_L1_j_24), 55 | .SIGN_dbeta_L1(SIGN_dbeta_L1), 56 | .SIGN_dalpha_L2_j_0(SIGN_dalpha_L2_j_0), .SIGN_dalpha_L2_j_1(SIGN_dalpha_L2_j_1), .SIGN_dalpha_L2_j_2(SIGN_dalpha_L2_j_2), .SIGN_dalpha_L2_j_3(SIGN_dalpha_L2_j_3), .SIGN_dalpha_L2_j_4(SIGN_dalpha_L2_j_4), .SIGN_dalpha_L2_j_5(SIGN_dalpha_L2_j_5), .SIGN_dalpha_L2_j_6(SIGN_dalpha_L2_j_6), .SIGN_dalpha_L2_j_7(SIGN_dalpha_L2_j_7), 57 | .SIGN_dbeta_L2(SIGN_dbeta_L2), 58 | .SIGN_dalpha_L3_j_0(SIGN_dalpha_L3_j_0), .SIGN_dalpha_L3_j_1(SIGN_dalpha_L3_j_1), .SIGN_dalpha_L3_j_2(SIGN_dalpha_L3_j_2), .SIGN_dalpha_L3_j_3(SIGN_dalpha_L3_j_3), .SIGN_dalpha_L3_j_4(SIGN_dalpha_L3_j_4), 59 | .SIGN_dbeta_L3(SIGN_dbeta_L3), 60 | -------------------------------------------------------------------------------- /FullyConnectedSNN/RNE.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | module RNE( 4 | S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32, S33, S34, S35, S36, S37, S38, S39, S40, S41, S42, S43, S44, S45, S46, S47, S48, S49, S50, S51, S52, S53, S54, S55, S56, S57, S58, S59, S60, S61, S62, S63, S64, S65, S66, S67, S68, S69, S70, S71, S72, S73, S74, S75, S76, S77, S78, S79, S80, S81, S82, S83, S84, S85, S86, S87, S88, S89, S90, S91, S92, S93, S94, S95, S96, S97, S98, S99, S100, S101, S102, S103, S104, S105, S106, S107, S108, S109, S110, S111, S112, S113, S114, S115, S116, S117, S118, S119, S120, S121, S122, S123, S124, S125, S126, S127, S128, S129, S130, S131, S132, S133, S134, S135, S136, S137, S138, S139, S140, S141, S142, S143, S144, S145, S146, S147, S148, S149, S150, S151, S152, S153, S154, S155, S156, S157, S158, S159, S160, S161, S162, S163, S164, S165, S166, S167, S168, S169, S170, S171, S172, S173, S174, S175, S176, S177, S178, S179, S180, S181, S182, S183, S184, S185, S186, S187, S188, S189, S190, S191, S192, S193, S194, S195, S196, S197, S198, S199, S200, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S212, S213, S214, S215, S216, S217, S218, S219, S220, S221, S222, S223, S224, S225, S226, S227, S228, S229, S230, S231, S232, S233, S234, S235, S236, S237, S238, S239, S240, S241, S242, S243, S244, S245, S246, S247, S248, S249, S250, S251, S252, S253, S254, S255, S256, S257, S258, S259, S260, S261, S262, S263, S264, S265, S266, S267, S268, S269, S270, S271, S272, S273, S274, S275, S276, S277, S278, S279, 5 | R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, 6 | R_long0, R_long1, R_long2, R_long3, R_long4, R_long5, R_long6, R_long7, R_long8, R_long9, R_long10, R_long11, R_long12, R_long13, R_long14, 7 | CLK, INIT_powerup, SDcount 8 | ); 9 | 10 | parameter DP = 8; // RN precision 11 | parameter DPlong =16; // RN alpha precision 12 | parameter LFSR_S = 16; // LFSR size 13 | 14 | input CLK, INIT_powerup; // Initialization signal (new set) 15 | input [31:0] SDcount; 16 | input wire [16 - 1:0] S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32, S33, S34, S35, S36, S37, S38, S39, S40, S41, S42, S43, S44, S45, S46, S47, S48, S49, S50, S51, S52, S53, S54, S55, S56, S57, S58, S59, S60, S61, S62, S63, S64, S65, S66, S67, S68, S69, S70, S71, S72, S73, S74, S75, S76, S77, S78, S79, S80, S81, S82, S83, S84, S85, S86, S87, S88, S89, S90, S91, S92, S93, S94, S95, S96, S97, S98, S99, S100, S101, S102, S103, S104, S105, S106, S107, S108, S109, S110, S111, S112, S113, S114, S115, S116, S117, S118, S119, S120, S121, S122, S123, S124, S125, S126, S127, S128, S129, S130, S131, S132, S133, S134, S135, S136, S137, S138, S139, S140, S141, S142, S143, S144, S145, S146, S147, S148, S149, S150, S151, S152, S153, S154, S155, S156, S157, S158, S159, S160, S161, S162, S163, S164, S165, S166, S167, S168, S169, S170, S171, S172, S173, S174, S175, S176, S177, S178, S179, S180, S181, S182, S183, S184, S185, S186, S187, S188, S189, S190, S191, S192, S193, S194, S195, S196, S197, S198, S199, S200, S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S212, S213, S214, S215, S216, S217, S218, S219, S220, S221, S222, S223, S224, S225, S226, S227, S228, S229, S230, S231, S232, S233, S234, S235, S236, S237, S238, S239, S240, S241, S242, S243, S244, S245, S246, S247, S248, S249, S250, S251, S252, S253, S254, S255, S256, S257, S258, S259, S260, S261, S262, S263, S264, S265, S266, S267, S268, S269, S270, S271, S272, S273, S274, S275, S276, S277, S278, S279; 17 | output [DP - 1:0] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528; 18 | output [DPlong - 1:0] R_long0, R_long1, R_long2, R_long3, R_long4, R_long5, R_long6, R_long7, R_long8, R_long9, R_long10, R_long11, R_long12, R_long13, R_long14; 19 | 20 | wire [DP-1:0] R529,R530,R531,R532,R533,R534,R535,R536,R537,R538,R539,R540,R541,R542,R543; 21 | 22 | // Short RN LFSRs 23 | cascLFSR_16Tap xLFSR0(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R0),.OUT1(R527),.OUT2(R32),.OUT3(R495),.OUT4(R64),.OUT5(R463),.OUT6(R96),.OUT7(R431),.OUT8(R128),.OUT9(R399),.OUT10(R160),.OUT11(R367),.OUT12(R192),.OUT13(R335),.OUT14(R224),.OUT15(R303),.SEED(S0), .SDcount(SDcount)); 24 | cascLFSR_16Tap xLFSR1(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R256),.OUT1(R271),.OUT2(R288),.OUT3(R239),.OUT4(R320),.OUT5(R207),.OUT6(R352),.OUT7(R175),.OUT8(R384),.OUT9(R143),.OUT10(R416),.OUT11(R111),.OUT12(R448),.OUT13(R79),.OUT14(R480),.OUT15(R47),.SEED(S8), .SDcount(SDcount)); 25 | cascLFSR_16Tap xLFSR2(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R512),.OUT1(R15),.OUT2(R1),.OUT3(R526),.OUT4(R33),.OUT5(R494),.OUT6(R65),.OUT7(R462),.OUT8(R97),.OUT9(R430),.OUT10(R129),.OUT11(R398),.OUT12(R161),.OUT13(R366),.OUT14(R193),.OUT15(R334),.SEED(S16), .SDcount(SDcount)); 26 | cascLFSR_16Tap xLFSR3(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R225),.OUT1(R302),.OUT2(R257),.OUT3(R270),.OUT4(R289),.OUT5(R238),.OUT6(R321),.OUT7(R206),.OUT8(R353),.OUT9(R174),.OUT10(R385),.OUT11(R142),.OUT12(R417),.OUT13(R110),.OUT14(R449),.OUT15(R78),.SEED(S24), .SDcount(SDcount)); 27 | cascLFSR_16Tap xLFSR4(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R481),.OUT1(R46),.OUT2(R513),.OUT3(R14),.OUT4(R2),.OUT5(R525),.OUT6(R34),.OUT7(R493),.OUT8(R66),.OUT9(R461),.OUT10(R98),.OUT11(R429),.OUT12(R130),.OUT13(R397),.OUT14(R162),.OUT15(R365),.SEED(S32), .SDcount(SDcount)); 28 | cascLFSR_16Tap xLFSR5(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R194),.OUT1(R333),.OUT2(R226),.OUT3(R301),.OUT4(R258),.OUT5(R269),.OUT6(R290),.OUT7(R237),.OUT8(R322),.OUT9(R205),.OUT10(R354),.OUT11(R173),.OUT12(R386),.OUT13(R141),.OUT14(R418),.OUT15(R109),.SEED(S40), .SDcount(SDcount)); 29 | cascLFSR_16Tap xLFSR6(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R450),.OUT1(R77),.OUT2(R482),.OUT3(R45),.OUT4(R514),.OUT5(R13),.OUT6(R3),.OUT7(R524),.OUT8(R35),.OUT9(R492),.OUT10(R67),.OUT11(R460),.OUT12(R99),.OUT13(R428),.OUT14(R131),.OUT15(R396),.SEED(S48), .SDcount(SDcount)); 30 | cascLFSR_16Tap xLFSR7(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R163),.OUT1(R364),.OUT2(R195),.OUT3(R332),.OUT4(R227),.OUT5(R300),.OUT6(R259),.OUT7(R268),.OUT8(R291),.OUT9(R236),.OUT10(R323),.OUT11(R204),.OUT12(R355),.OUT13(R172),.OUT14(R387),.OUT15(R140),.SEED(S56), .SDcount(SDcount)); 31 | cascLFSR_16Tap xLFSR8(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R419),.OUT1(R108),.OUT2(R451),.OUT3(R76),.OUT4(R483),.OUT5(R44),.OUT6(R515),.OUT7(R12),.OUT8(R4),.OUT9(R523),.OUT10(R36),.OUT11(R491),.OUT12(R68),.OUT13(R459),.OUT14(R100),.OUT15(R427),.SEED(S64), .SDcount(SDcount)); 32 | cascLFSR_16Tap xLFSR9(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R132),.OUT1(R395),.OUT2(R164),.OUT3(R363),.OUT4(R196),.OUT5(R331),.OUT6(R228),.OUT7(R299),.OUT8(R260),.OUT9(R267),.OUT10(R292),.OUT11(R235),.OUT12(R324),.OUT13(R203),.OUT14(R356),.OUT15(R171),.SEED(S72), .SDcount(SDcount)); 33 | cascLFSR_16Tap xLFSR10(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R388),.OUT1(R139),.OUT2(R420),.OUT3(R107),.OUT4(R452),.OUT5(R75),.OUT6(R484),.OUT7(R43),.OUT8(R516),.OUT9(R11),.OUT10(R5),.OUT11(R522),.OUT12(R37),.OUT13(R490),.OUT14(R69),.OUT15(R458),.SEED(S80), .SDcount(SDcount)); 34 | cascLFSR_16Tap xLFSR11(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R101),.OUT1(R426),.OUT2(R133),.OUT3(R394),.OUT4(R165),.OUT5(R362),.OUT6(R197),.OUT7(R330),.OUT8(R229),.OUT9(R298),.OUT10(R261),.OUT11(R266),.OUT12(R293),.OUT13(R234),.OUT14(R325),.OUT15(R202),.SEED(S88), .SDcount(SDcount)); 35 | cascLFSR_16Tap xLFSR12(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R357),.OUT1(R170),.OUT2(R389),.OUT3(R138),.OUT4(R421),.OUT5(R106),.OUT6(R453),.OUT7(R74),.OUT8(R485),.OUT9(R42),.OUT10(R517),.OUT11(R10),.OUT12(R6),.OUT13(R521),.OUT14(R38),.OUT15(R489),.SEED(S96), .SDcount(SDcount)); 36 | cascLFSR_16Tap xLFSR13(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R70),.OUT1(R457),.OUT2(R102),.OUT3(R425),.OUT4(R134),.OUT5(R393),.OUT6(R166),.OUT7(R361),.OUT8(R198),.OUT9(R329),.OUT10(R230),.OUT11(R297),.OUT12(R262),.OUT13(R265),.OUT14(R294),.OUT15(R233),.SEED(S104), .SDcount(SDcount)); 37 | cascLFSR_16Tap xLFSR14(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R326),.OUT1(R201),.OUT2(R358),.OUT3(R169),.OUT4(R390),.OUT5(R137),.OUT6(R422),.OUT7(R105),.OUT8(R454),.OUT9(R73),.OUT10(R486),.OUT11(R41),.OUT12(R518),.OUT13(R9),.OUT14(R7),.OUT15(R520),.SEED(S112), .SDcount(SDcount)); 38 | cascLFSR_16Tap xLFSR15(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R39),.OUT1(R488),.OUT2(R71),.OUT3(R456),.OUT4(R103),.OUT5(R424),.OUT6(R135),.OUT7(R392),.OUT8(R167),.OUT9(R360),.OUT10(R199),.OUT11(R328),.OUT12(R231),.OUT13(R296),.OUT14(R263),.OUT15(R264),.SEED(S120), .SDcount(SDcount)); 39 | cascLFSR_16Tap xLFSR16(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R295),.OUT1(R232),.OUT2(R327),.OUT3(R200),.OUT4(R359),.OUT5(R168),.OUT6(R391),.OUT7(R136),.OUT8(R423),.OUT9(R104),.OUT10(R455),.OUT11(R72),.OUT12(R487),.OUT13(R40),.OUT14(R519),.OUT15(R8),.SEED(S128), .SDcount(SDcount)); 40 | cascLFSR_16Tap xLFSR17(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R535),.OUT1(R24),.OUT2(R503),.OUT3(R56),.OUT4(R471),.OUT5(R88),.OUT6(R439),.OUT7(R120),.OUT8(R407),.OUT9(R152),.OUT10(R375),.OUT11(R184),.OUT12(R343),.OUT13(R216),.OUT14(R311),.OUT15(R248),.SEED(S136), .SDcount(SDcount)); 41 | cascLFSR_16Tap xLFSR18(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R279),.OUT1(R280),.OUT2(R247),.OUT3(R312),.OUT4(R215),.OUT5(R344),.OUT6(R183),.OUT7(R376),.OUT8(R151),.OUT9(R408),.OUT10(R119),.OUT11(R440),.OUT12(R87),.OUT13(R472),.OUT14(R55),.OUT15(R504),.SEED(S144), .SDcount(SDcount)); 42 | cascLFSR_16Tap xLFSR19(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R23),.OUT1(R536),.OUT2(R534),.OUT3(R25),.OUT4(R502),.OUT5(R57),.OUT6(R470),.OUT7(R89),.OUT8(R438),.OUT9(R121),.OUT10(R406),.OUT11(R153),.OUT12(R374),.OUT13(R185),.OUT14(R342),.OUT15(R217),.SEED(S152), .SDcount(SDcount)); 43 | cascLFSR_16Tap xLFSR20(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R310),.OUT1(R249),.OUT2(R278),.OUT3(R281),.OUT4(R246),.OUT5(R313),.OUT6(R214),.OUT7(R345),.OUT8(R182),.OUT9(R377),.OUT10(R150),.OUT11(R409),.OUT12(R118),.OUT13(R441),.OUT14(R86),.OUT15(R473),.SEED(S160), .SDcount(SDcount)); 44 | cascLFSR_16Tap xLFSR21(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R54),.OUT1(R505),.OUT2(R22),.OUT3(R537),.OUT4(R533),.OUT5(R26),.OUT6(R501),.OUT7(R58),.OUT8(R469),.OUT9(R90),.OUT10(R437),.OUT11(R122),.OUT12(R405),.OUT13(R154),.OUT14(R373),.OUT15(R186),.SEED(S168), .SDcount(SDcount)); 45 | cascLFSR_16Tap xLFSR22(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R341),.OUT1(R218),.OUT2(R309),.OUT3(R250),.OUT4(R277),.OUT5(R282),.OUT6(R245),.OUT7(R314),.OUT8(R213),.OUT9(R346),.OUT10(R181),.OUT11(R378),.OUT12(R149),.OUT13(R410),.OUT14(R117),.OUT15(R442),.SEED(S176), .SDcount(SDcount)); 46 | cascLFSR_16Tap xLFSR23(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R85),.OUT1(R474),.OUT2(R53),.OUT3(R506),.OUT4(R21),.OUT5(R538),.OUT6(R532),.OUT7(R27),.OUT8(R500),.OUT9(R59),.OUT10(R468),.OUT11(R91),.OUT12(R436),.OUT13(R123),.OUT14(R404),.OUT15(R155),.SEED(S184), .SDcount(SDcount)); 47 | cascLFSR_16Tap xLFSR24(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R372),.OUT1(R187),.OUT2(R340),.OUT3(R219),.OUT4(R308),.OUT5(R251),.OUT6(R276),.OUT7(R283),.OUT8(R244),.OUT9(R315),.OUT10(R212),.OUT11(R347),.OUT12(R180),.OUT13(R379),.OUT14(R148),.OUT15(R411),.SEED(S192), .SDcount(SDcount)); 48 | cascLFSR_16Tap xLFSR25(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R116),.OUT1(R443),.OUT2(R84),.OUT3(R475),.OUT4(R52),.OUT5(R507),.OUT6(R20),.OUT7(R539),.OUT8(R531),.OUT9(R28),.OUT10(R499),.OUT11(R60),.OUT12(R467),.OUT13(R92),.OUT14(R435),.OUT15(R124),.SEED(S200), .SDcount(SDcount)); 49 | cascLFSR_16Tap xLFSR26(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R403),.OUT1(R156),.OUT2(R371),.OUT3(R188),.OUT4(R339),.OUT5(R220),.OUT6(R307),.OUT7(R252),.OUT8(R275),.OUT9(R284),.OUT10(R243),.OUT11(R316),.OUT12(R211),.OUT13(R348),.OUT14(R179),.OUT15(R380),.SEED(S208), .SDcount(SDcount)); 50 | cascLFSR_16Tap xLFSR27(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R147),.OUT1(R412),.OUT2(R115),.OUT3(R444),.OUT4(R83),.OUT5(R476),.OUT6(R51),.OUT7(R508),.OUT8(R19),.OUT9(R540),.OUT10(R530),.OUT11(R29),.OUT12(R498),.OUT13(R61),.OUT14(R466),.OUT15(R93),.SEED(S216), .SDcount(SDcount)); 51 | cascLFSR_16Tap xLFSR28(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R434),.OUT1(R125),.OUT2(R402),.OUT3(R157),.OUT4(R370),.OUT5(R189),.OUT6(R338),.OUT7(R221),.OUT8(R306),.OUT9(R253),.OUT10(R274),.OUT11(R285),.OUT12(R242),.OUT13(R317),.OUT14(R210),.OUT15(R349),.SEED(S224), .SDcount(SDcount)); 52 | cascLFSR_16Tap xLFSR29(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R178),.OUT1(R381),.OUT2(R146),.OUT3(R413),.OUT4(R114),.OUT5(R445),.OUT6(R82),.OUT7(R477),.OUT8(R50),.OUT9(R509),.OUT10(R18),.OUT11(R541),.OUT12(R529),.OUT13(R30),.OUT14(R497),.OUT15(R62),.SEED(S232), .SDcount(SDcount)); 53 | cascLFSR_16Tap xLFSR30(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R465),.OUT1(R94),.OUT2(R433),.OUT3(R126),.OUT4(R401),.OUT5(R158),.OUT6(R369),.OUT7(R190),.OUT8(R337),.OUT9(R222),.OUT10(R305),.OUT11(R254),.OUT12(R273),.OUT13(R286),.OUT14(R241),.OUT15(R318),.SEED(S240), .SDcount(SDcount)); 54 | cascLFSR_16Tap xLFSR31(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R209),.OUT1(R350),.OUT2(R177),.OUT3(R382),.OUT4(R145),.OUT5(R414),.OUT6(R113),.OUT7(R446),.OUT8(R81),.OUT9(R478),.OUT10(R49),.OUT11(R510),.OUT12(R17),.OUT13(R542),.OUT14(R528),.OUT15(R31),.SEED(S248), .SDcount(SDcount)); 55 | cascLFSR_16Tap xLFSR32(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R496),.OUT1(R63),.OUT2(R464),.OUT3(R95),.OUT4(R432),.OUT5(R127),.OUT6(R400),.OUT7(R159),.OUT8(R368),.OUT9(R191),.OUT10(R336),.OUT11(R223),.OUT12(R304),.OUT13(R255),.OUT14(R272),.OUT15(R287),.SEED(S256), .SDcount(SDcount)); 56 | cascLFSR_16Tap xLFSR33(.TRIG(CLK),.RESET(INIT_powerup),.OUT0(R240),.OUT1(R319),.OUT2(R208),.OUT3(R351),.OUT4(R176),.OUT5(R383),.OUT6(R144),.OUT7(R415),.OUT8(R112),.OUT9(R447),.OUT10(R80),.OUT11(R479),.OUT12(R48),.OUT13(R511),.OUT14(R16),.OUT15(R543),.SEED(S264), .SDcount(SDcount)); 57 | 58 | // Long RN LFSRs 59 | cascLFSR xLFSR_L0(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long0[7:0]),.OUT2(R_long0[15:8]),.SEED(S265),.SDcount(SDcount)); 60 | cascLFSR xLFSR_L1(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long1[7:0]),.OUT2(R_long1[15:8]),.SEED(S266),.SDcount(SDcount)); 61 | cascLFSR xLFSR_L2(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long2[7:0]),.OUT2(R_long2[15:8]),.SEED(S267),.SDcount(SDcount)); 62 | cascLFSR xLFSR_L3(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long3[7:0]),.OUT2(R_long3[15:8]),.SEED(S268),.SDcount(SDcount)); 63 | cascLFSR xLFSR_L4(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long4[7:0]),.OUT2(R_long4[15:8]),.SEED(S269),.SDcount(SDcount)); 64 | cascLFSR xLFSR_L5(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long5[7:0]),.OUT2(R_long5[15:8]),.SEED(S270),.SDcount(SDcount)); 65 | cascLFSR xLFSR_L6(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long6[7:0]),.OUT2(R_long6[15:8]),.SEED(S271),.SDcount(SDcount)); 66 | cascLFSR xLFSR_L7(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long7[7:0]),.OUT2(R_long7[15:8]),.SEED(S272),.SDcount(SDcount)); 67 | cascLFSR xLFSR_L8(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long8[7:0]),.OUT2(R_long8[15:8]),.SEED(S273),.SDcount(SDcount)); 68 | cascLFSR xLFSR_L9(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long9[7:0]),.OUT2(R_long9[15:8]),.SEED(S274),.SDcount(SDcount)); 69 | cascLFSR xLFSR_L10(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long10[7:0]),.OUT2(R_long10[15:8]),.SEED(S275),.SDcount(SDcount)); 70 | cascLFSR xLFSR_L11(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long11[7:0]),.OUT2(R_long11[15:8]),.SEED(S276),.SDcount(SDcount)); 71 | cascLFSR xLFSR_L12(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long12[7:0]),.OUT2(R_long12[15:8]),.SEED(S277),.SDcount(SDcount)); 72 | cascLFSR xLFSR_L13(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long13[7:0]),.OUT2(R_long13[15:8]),.SEED(S278),.SDcount(SDcount)); 73 | cascLFSR xLFSR_L14(.TRIG(CLK),.RESET(INIT_powerup),.OUT1(R_long14[7:0]),.OUT2(R_long14[15:8]),.SEED(S279),.SDcount(SDcount)); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /FullyConnectedSNN/BCKDPROP.v: -------------------------------------------------------------------------------- 1 | // Chris Ceroici 2 | 3 | // Neural Network Backward Propagation 4 | 5 | module BCKDPROP( 6 | alpha_L1_j_0, alpha_L1_j_1, alpha_L1_j_2, alpha_L1_j_3, alpha_L1_j_4, alpha_L1_j_5, alpha_L1_j_6, alpha_L1_j_7, alpha_L1_j_8, alpha_L1_j_9, alpha_L1_j_10, alpha_L1_j_11, alpha_L1_j_12, alpha_L1_j_13, alpha_L1_j_14, alpha_L1_j_15, alpha_L1_j_16, alpha_L1_j_17, alpha_L1_j_18, alpha_L1_j_19, alpha_L1_j_20, alpha_L1_j_21, alpha_L1_j_22, alpha_L1_j_23, alpha_L1_j_24, 7 | beta_L1, 8 | alpha_L2_j_0, alpha_L2_j_1, alpha_L2_j_2, alpha_L2_j_3, alpha_L2_j_4, alpha_L2_j_5, alpha_L2_j_6, alpha_L2_j_7, 9 | beta_L2, 10 | alpha_L3_j_0, alpha_L3_j_1, alpha_L3_j_2, alpha_L3_j_3, alpha_L3_j_4, 11 | beta_L3, 12 | SIGN_alpha_L1_j_0, SIGN_alpha_L1_j_1, SIGN_alpha_L1_j_2, SIGN_alpha_L1_j_3, SIGN_alpha_L1_j_4, SIGN_alpha_L1_j_5, SIGN_alpha_L1_j_6, SIGN_alpha_L1_j_7, SIGN_alpha_L1_j_8, SIGN_alpha_L1_j_9, SIGN_alpha_L1_j_10, SIGN_alpha_L1_j_11, SIGN_alpha_L1_j_12, SIGN_alpha_L1_j_13, SIGN_alpha_L1_j_14, SIGN_alpha_L1_j_15, SIGN_alpha_L1_j_16, SIGN_alpha_L1_j_17, SIGN_alpha_L1_j_18, SIGN_alpha_L1_j_19, SIGN_alpha_L1_j_20, SIGN_alpha_L1_j_21, SIGN_alpha_L1_j_22, SIGN_alpha_L1_j_23, SIGN_alpha_L1_j_24, 13 | SIGN_beta_L1, 14 | SIGN_alpha_L2_j_0, SIGN_alpha_L2_j_1, SIGN_alpha_L2_j_2, SIGN_alpha_L2_j_3, SIGN_alpha_L2_j_4, SIGN_alpha_L2_j_5, SIGN_alpha_L2_j_6, SIGN_alpha_L2_j_7, 15 | SIGN_beta_L2, 16 | SIGN_alpha_L3_j_0, SIGN_alpha_L3_j_1, SIGN_alpha_L3_j_2, SIGN_alpha_L3_j_3, SIGN_alpha_L3_j_4, 17 | SIGN_beta_L3, 18 | a_L0, 19 | a_L1, 20 | a_L2, 21 | a_L3, 22 | z_L0, 23 | z_L1, 24 | z_L2, 25 | z_L3, 26 | zp_L0, 27 | zp_L1, 28 | zp_L2, 29 | zp_L3, 30 | SIGN_L3, 31 | dalpha_L1_j_0, dalpha_L1_j_1, dalpha_L1_j_2, dalpha_L1_j_3, dalpha_L1_j_4, dalpha_L1_j_5, dalpha_L1_j_6, dalpha_L1_j_7, dalpha_L1_j_8, dalpha_L1_j_9, dalpha_L1_j_10, dalpha_L1_j_11, dalpha_L1_j_12, dalpha_L1_j_13, dalpha_L1_j_14, dalpha_L1_j_15, dalpha_L1_j_16, dalpha_L1_j_17, dalpha_L1_j_18, dalpha_L1_j_19, dalpha_L1_j_20, dalpha_L1_j_21, dalpha_L1_j_22, dalpha_L1_j_23, dalpha_L1_j_24, 32 | dbeta_L1, 33 | dalpha_L2_j_0, dalpha_L2_j_1, dalpha_L2_j_2, dalpha_L2_j_3, dalpha_L2_j_4, dalpha_L2_j_5, dalpha_L2_j_6, dalpha_L2_j_7, 34 | dbeta_L2, 35 | dalpha_L3_j_0, dalpha_L3_j_1, dalpha_L3_j_2, dalpha_L3_j_3, dalpha_L3_j_4, 36 | dbeta_L3, 37 | SIGN_dalpha_L1_j_0, SIGN_dalpha_L1_j_1, SIGN_dalpha_L1_j_2, SIGN_dalpha_L1_j_3, SIGN_dalpha_L1_j_4, SIGN_dalpha_L1_j_5, SIGN_dalpha_L1_j_6, SIGN_dalpha_L1_j_7, SIGN_dalpha_L1_j_8, SIGN_dalpha_L1_j_9, SIGN_dalpha_L1_j_10, SIGN_dalpha_L1_j_11, SIGN_dalpha_L1_j_12, SIGN_dalpha_L1_j_13, SIGN_dalpha_L1_j_14, SIGN_dalpha_L1_j_15, SIGN_dalpha_L1_j_16, SIGN_dalpha_L1_j_17, SIGN_dalpha_L1_j_18, SIGN_dalpha_L1_j_19, SIGN_dalpha_L1_j_20, SIGN_dalpha_L1_j_21, SIGN_dalpha_L1_j_22, SIGN_dalpha_L1_j_23, SIGN_dalpha_L1_j_24, 38 | SIGN_dbeta_L1, 39 | SIGN_dalpha_L2_j_0, SIGN_dalpha_L2_j_1, SIGN_dalpha_L2_j_2, SIGN_dalpha_L2_j_3, SIGN_dalpha_L2_j_4, SIGN_dalpha_L2_j_5, SIGN_dalpha_L2_j_6, SIGN_dalpha_L2_j_7, 40 | SIGN_dbeta_L2, 41 | SIGN_dalpha_L3_j_0, SIGN_dalpha_L3_j_1, SIGN_dalpha_L3_j_2, SIGN_dalpha_L3_j_3, SIGN_dalpha_L3_j_4, 42 | SIGN_dbeta_L3, 43 | eps, 44 | R_BP0, R_BP1, R_BP2, R_BP3, R_BP4, R_BP5, R_BP6, R_BP7, R_BP8, 45 | CLK, BP_FRAME, FP_FRAME, INIT 46 | ); 47 | 48 | parameter MEMSIZE = 6; 49 | parameter DP_in = 8; 50 | parameter DP_out = 16; 51 | 52 | input wire CLK, BP_FRAME, FP_FRAME, INIT; 53 | input wire [5 - 1:0] alpha_L1_j_0, alpha_L1_j_1, alpha_L1_j_2, alpha_L1_j_3, alpha_L1_j_4, alpha_L1_j_5, alpha_L1_j_6, alpha_L1_j_7, alpha_L1_j_8, alpha_L1_j_9, alpha_L1_j_10, alpha_L1_j_11, alpha_L1_j_12, alpha_L1_j_13, alpha_L1_j_14, alpha_L1_j_15, alpha_L1_j_16, alpha_L1_j_17, alpha_L1_j_18, alpha_L1_j_19, alpha_L1_j_20, alpha_L1_j_21, alpha_L1_j_22, alpha_L1_j_23, alpha_L1_j_24; 54 | input wire [25 - 1:0] beta_L1; 55 | input wire [25 - 1:0] alpha_L2_j_0, alpha_L2_j_1, alpha_L2_j_2, alpha_L2_j_3, alpha_L2_j_4, alpha_L2_j_5, alpha_L2_j_6, alpha_L2_j_7; 56 | input wire [8 - 1:0] beta_L2; 57 | input wire [8 - 1:0] alpha_L3_j_0, alpha_L3_j_1, alpha_L3_j_2, alpha_L3_j_3, alpha_L3_j_4; 58 | input wire [5 - 1:0] beta_L3; 59 | input wire [5 - 1:0] SIGN_alpha_L1_j_0, SIGN_alpha_L1_j_1, SIGN_alpha_L1_j_2, SIGN_alpha_L1_j_3, SIGN_alpha_L1_j_4, SIGN_alpha_L1_j_5, SIGN_alpha_L1_j_6, SIGN_alpha_L1_j_7, SIGN_alpha_L1_j_8, SIGN_alpha_L1_j_9, SIGN_alpha_L1_j_10, SIGN_alpha_L1_j_11, SIGN_alpha_L1_j_12, SIGN_alpha_L1_j_13, SIGN_alpha_L1_j_14, SIGN_alpha_L1_j_15, SIGN_alpha_L1_j_16, SIGN_alpha_L1_j_17, SIGN_alpha_L1_j_18, SIGN_alpha_L1_j_19, SIGN_alpha_L1_j_20, SIGN_alpha_L1_j_21, SIGN_alpha_L1_j_22, SIGN_alpha_L1_j_23, SIGN_alpha_L1_j_24; 60 | input wire [25 - 1:0] SIGN_beta_L1; 61 | input wire [25 - 1:0] SIGN_alpha_L2_j_0, SIGN_alpha_L2_j_1, SIGN_alpha_L2_j_2, SIGN_alpha_L2_j_3, SIGN_alpha_L2_j_4, SIGN_alpha_L2_j_5, SIGN_alpha_L2_j_6, SIGN_alpha_L2_j_7; 62 | input wire [8 - 1:0] SIGN_beta_L2; 63 | input wire [8 - 1:0] SIGN_alpha_L3_j_0, SIGN_alpha_L3_j_1, SIGN_alpha_L3_j_2, SIGN_alpha_L3_j_3, SIGN_alpha_L3_j_4; 64 | input wire [5 - 1:0] SIGN_beta_L3; 65 | input wire [5 - 1:0] a_L0; 66 | input wire [25 - 1:0] a_L1; 67 | input wire [8 - 1:0] a_L2; 68 | input wire [5 - 1:0] a_L3; 69 | input wire [5 - 1:0] z_L0; 70 | input wire [25 - 1:0] z_L1; 71 | input wire [8 - 1:0] z_L2; 72 | input wire [5 - 1:0] z_L3; 73 | input wire [5 - 1:0] zp_L0; 74 | input wire [25 - 1:0] zp_L1; 75 | input wire [8 - 1:0] zp_L2; 76 | input wire [5 - 1:0] zp_L3; 77 | input wire [5-1:0] SIGN_L3; 78 | input wire [5-1:0] eps; 79 | input wire [7:0] R_BP0, R_BP1, R_BP2, R_BP3, R_BP4, R_BP5, R_BP6, R_BP7, R_BP8; 80 | 81 | output wire [5 - 1:0] dalpha_L1_j_0, dalpha_L1_j_1, dalpha_L1_j_2, dalpha_L1_j_3, dalpha_L1_j_4, dalpha_L1_j_5, dalpha_L1_j_6, dalpha_L1_j_7, dalpha_L1_j_8, dalpha_L1_j_9, dalpha_L1_j_10, dalpha_L1_j_11, dalpha_L1_j_12, dalpha_L1_j_13, dalpha_L1_j_14, dalpha_L1_j_15, dalpha_L1_j_16, dalpha_L1_j_17, dalpha_L1_j_18, dalpha_L1_j_19, dalpha_L1_j_20, dalpha_L1_j_21, dalpha_L1_j_22, dalpha_L1_j_23, dalpha_L1_j_24; 82 | output wire [25 - 1:0] dbeta_L1; 83 | output wire [25 - 1:0] dalpha_L2_j_0, dalpha_L2_j_1, dalpha_L2_j_2, dalpha_L2_j_3, dalpha_L2_j_4, dalpha_L2_j_5, dalpha_L2_j_6, dalpha_L2_j_7; 84 | output wire [8 - 1:0] dbeta_L2; 85 | output wire [8 - 1:0] dalpha_L3_j_0, dalpha_L3_j_1, dalpha_L3_j_2, dalpha_L3_j_3, dalpha_L3_j_4; 86 | output wire [5 - 1:0] dbeta_L3; 87 | output wire [5 - 1:0] SIGN_dalpha_L1_j_0, SIGN_dalpha_L1_j_1, SIGN_dalpha_L1_j_2, SIGN_dalpha_L1_j_3, SIGN_dalpha_L1_j_4, SIGN_dalpha_L1_j_5, SIGN_dalpha_L1_j_6, SIGN_dalpha_L1_j_7, SIGN_dalpha_L1_j_8, SIGN_dalpha_L1_j_9, SIGN_dalpha_L1_j_10, SIGN_dalpha_L1_j_11, SIGN_dalpha_L1_j_12, SIGN_dalpha_L1_j_13, SIGN_dalpha_L1_j_14, SIGN_dalpha_L1_j_15, SIGN_dalpha_L1_j_16, SIGN_dalpha_L1_j_17, SIGN_dalpha_L1_j_18, SIGN_dalpha_L1_j_19, SIGN_dalpha_L1_j_20, SIGN_dalpha_L1_j_21, SIGN_dalpha_L1_j_22, SIGN_dalpha_L1_j_23, SIGN_dalpha_L1_j_24; 88 | output wire [25 - 1:0] SIGN_dbeta_L1; 89 | output wire [25 - 1:0] SIGN_dalpha_L2_j_0, SIGN_dalpha_L2_j_1, SIGN_dalpha_L2_j_2, SIGN_dalpha_L2_j_3, SIGN_dalpha_L2_j_4, SIGN_dalpha_L2_j_5, SIGN_dalpha_L2_j_6, SIGN_dalpha_L2_j_7; 90 | output wire [8 - 1:0] SIGN_dbeta_L2; 91 | output wire [8 - 1:0] SIGN_dalpha_L3_j_0, SIGN_dalpha_L3_j_1, SIGN_dalpha_L3_j_2, SIGN_dalpha_L3_j_3, SIGN_dalpha_L3_j_4; 92 | output wire [5 - 1:0] SIGN_dbeta_L3; 93 | wire [25 - 1:0] delta_L1; 94 | wire [8 - 1:0] delta_L2; 95 | wire [5 - 1:0] delta_L3; 96 | wire [5-1:0] dbeta_L3_n; 97 | wire [8-1:0] dbeta_L2_n; 98 | wire [25-1:0] dbeta_L1_n; 99 | 100 | wire [25 - 1:0] SIGN_L1; 101 | wire [8 - 1:0] SIGN_L2; 102 | 103 | 104 | // Backwards Evaluation: 105 | 106 | NN_DNODE DNODE_L3_0(.delta(delta_L3[0]), .atj(a_L2), .zk(z_L3[0]), .dalpha(dalpha_L3_j_0), .dbeta(dbeta_L3[0]), .CLK(CLK), .INIT(BP_FRAME)); // layer 3 node 0 107 | NN_DNODE DNODE_L3_1(.delta(delta_L3[1]), .atj(a_L2), .zk(z_L3[1]), .dalpha(dalpha_L3_j_1), .dbeta(dbeta_L3[1]), .CLK(CLK), .INIT(BP_FRAME)); // layer 3 node 1 108 | NN_DNODE DNODE_L3_2(.delta(delta_L3[2]), .atj(a_L2), .zk(z_L3[2]), .dalpha(dalpha_L3_j_2), .dbeta(dbeta_L3[2]), .CLK(CLK), .INIT(BP_FRAME)); // layer 3 node 2 109 | NN_DNODE DNODE_L3_3(.delta(delta_L3[3]), .atj(a_L2), .zk(z_L3[3]), .dalpha(dalpha_L3_j_3), .dbeta(dbeta_L3[3]), .CLK(CLK), .INIT(BP_FRAME)); // layer 3 node 3 110 | NN_DNODE DNODE_L3_4(.delta(delta_L3[4]), .atj(a_L2), .zk(z_L3[4]), .dalpha(dalpha_L3_j_4), .dbeta(dbeta_L3[4]), .CLK(CLK), .INIT(BP_FRAME)); // layer 3 node 4 111 | defparam DNODE_L3_0.NN = 8; 112 | defparam DNODE_L3_0.MEMSIZE = MEMSIZE; 113 | defparam DNODE_L3_1.NN = 8; 114 | defparam DNODE_L3_1.MEMSIZE = MEMSIZE; 115 | defparam DNODE_L3_2.NN = 8; 116 | defparam DNODE_L3_2.MEMSIZE = MEMSIZE; 117 | defparam DNODE_L3_3.NN = 8; 118 | defparam DNODE_L3_3.MEMSIZE = MEMSIZE; 119 | defparam DNODE_L3_4.NN = 8; 120 | defparam DNODE_L3_4.MEMSIZE = MEMSIZE; 121 | 122 | assign SIGN_dalpha_L3_j_0 = {SIGN_L3[0], SIGN_L3[0], SIGN_L3[0], SIGN_L3[0], SIGN_L3[0], SIGN_L3[0], SIGN_L3[0], SIGN_L3[0]}; 123 | assign SIGN_dalpha_L3_j_1 = {SIGN_L3[1], SIGN_L3[1], SIGN_L3[1], SIGN_L3[1], SIGN_L3[1], SIGN_L3[1], SIGN_L3[1], SIGN_L3[1]}; 124 | assign SIGN_dalpha_L3_j_2 = {SIGN_L3[2], SIGN_L3[2], SIGN_L3[2], SIGN_L3[2], SIGN_L3[2], SIGN_L3[2], SIGN_L3[2], SIGN_L3[2]}; 125 | assign SIGN_dalpha_L3_j_3 = {SIGN_L3[3], SIGN_L3[3], SIGN_L3[3], SIGN_L3[3], SIGN_L3[3], SIGN_L3[3], SIGN_L3[3], SIGN_L3[3]}; 126 | assign SIGN_dalpha_L3_j_4 = {SIGN_L3[4], SIGN_L3[4], SIGN_L3[4], SIGN_L3[4], SIGN_L3[4], SIGN_L3[4], SIGN_L3[4], SIGN_L3[4]}; 127 | assign SIGN_dbeta_L3 = SIGN_L3; 128 | 129 | NN_DNODE DNODE_L2_0(.delta(delta_L2[0]), .atj(a_L1), .zk(z_L2[0]), .dalpha(dalpha_L2_j_0), .dbeta(dbeta_L2[0]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 0 130 | NN_DNODE DNODE_L2_1(.delta(delta_L2[1]), .atj(a_L1), .zk(z_L2[1]), .dalpha(dalpha_L2_j_1), .dbeta(dbeta_L2[1]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 1 131 | NN_DNODE DNODE_L2_2(.delta(delta_L2[2]), .atj(a_L1), .zk(z_L2[2]), .dalpha(dalpha_L2_j_2), .dbeta(dbeta_L2[2]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 2 132 | NN_DNODE DNODE_L2_3(.delta(delta_L2[3]), .atj(a_L1), .zk(z_L2[3]), .dalpha(dalpha_L2_j_3), .dbeta(dbeta_L2[3]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 3 133 | NN_DNODE DNODE_L2_4(.delta(delta_L2[4]), .atj(a_L1), .zk(z_L2[4]), .dalpha(dalpha_L2_j_4), .dbeta(dbeta_L2[4]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 4 134 | NN_DNODE DNODE_L2_5(.delta(delta_L2[5]), .atj(a_L1), .zk(z_L2[5]), .dalpha(dalpha_L2_j_5), .dbeta(dbeta_L2[5]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 5 135 | NN_DNODE DNODE_L2_6(.delta(delta_L2[6]), .atj(a_L1), .zk(z_L2[6]), .dalpha(dalpha_L2_j_6), .dbeta(dbeta_L2[6]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 6 136 | NN_DNODE DNODE_L2_7(.delta(delta_L2[7]), .atj(a_L1), .zk(z_L2[7]), .dalpha(dalpha_L2_j_7), .dbeta(dbeta_L2[7]), .CLK(CLK), .INIT(BP_FRAME)); // layer 2 node 7 137 | defparam DNODE_L2_0.NN = 25; 138 | defparam DNODE_L2_0.MEMSIZE = MEMSIZE; 139 | defparam DNODE_L2_1.NN = 25; 140 | defparam DNODE_L2_1.MEMSIZE = MEMSIZE; 141 | defparam DNODE_L2_2.NN = 25; 142 | defparam DNODE_L2_2.MEMSIZE = MEMSIZE; 143 | defparam DNODE_L2_3.NN = 25; 144 | defparam DNODE_L2_3.MEMSIZE = MEMSIZE; 145 | defparam DNODE_L2_4.NN = 25; 146 | defparam DNODE_L2_4.MEMSIZE = MEMSIZE; 147 | defparam DNODE_L2_5.NN = 25; 148 | defparam DNODE_L2_5.MEMSIZE = MEMSIZE; 149 | defparam DNODE_L2_6.NN = 25; 150 | defparam DNODE_L2_6.MEMSIZE = MEMSIZE; 151 | defparam DNODE_L2_7.NN = 25; 152 | defparam DNODE_L2_7.MEMSIZE = MEMSIZE; 153 | 154 | assign SIGN_dalpha_L2_j_0 = {SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0], SIGN_L2[0]}; 155 | assign SIGN_dalpha_L2_j_1 = {SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1], SIGN_L2[1]}; 156 | assign SIGN_dalpha_L2_j_2 = {SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2], SIGN_L2[2]}; 157 | assign SIGN_dalpha_L2_j_3 = {SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3], SIGN_L2[3]}; 158 | assign SIGN_dalpha_L2_j_4 = {SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4], SIGN_L2[4]}; 159 | assign SIGN_dalpha_L2_j_5 = {SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5], SIGN_L2[5]}; 160 | assign SIGN_dalpha_L2_j_6 = {SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6], SIGN_L2[6]}; 161 | assign SIGN_dalpha_L2_j_7 = {SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7], SIGN_L2[7]}; 162 | assign SIGN_dbeta_L2 = SIGN_L2; 163 | 164 | NN_DNODE DNODE_L1_0(.delta(delta_L1[0]), .atj(a_L0), .zk(z_L1[0]), .dalpha(dalpha_L1_j_0), .dbeta(dbeta_L1[0]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 0 165 | NN_DNODE DNODE_L1_1(.delta(delta_L1[1]), .atj(a_L0), .zk(z_L1[1]), .dalpha(dalpha_L1_j_1), .dbeta(dbeta_L1[1]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 1 166 | NN_DNODE DNODE_L1_2(.delta(delta_L1[2]), .atj(a_L0), .zk(z_L1[2]), .dalpha(dalpha_L1_j_2), .dbeta(dbeta_L1[2]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 2 167 | NN_DNODE DNODE_L1_3(.delta(delta_L1[3]), .atj(a_L0), .zk(z_L1[3]), .dalpha(dalpha_L1_j_3), .dbeta(dbeta_L1[3]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 3 168 | NN_DNODE DNODE_L1_4(.delta(delta_L1[4]), .atj(a_L0), .zk(z_L1[4]), .dalpha(dalpha_L1_j_4), .dbeta(dbeta_L1[4]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 4 169 | NN_DNODE DNODE_L1_5(.delta(delta_L1[5]), .atj(a_L0), .zk(z_L1[5]), .dalpha(dalpha_L1_j_5), .dbeta(dbeta_L1[5]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 5 170 | NN_DNODE DNODE_L1_6(.delta(delta_L1[6]), .atj(a_L0), .zk(z_L1[6]), .dalpha(dalpha_L1_j_6), .dbeta(dbeta_L1[6]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 6 171 | NN_DNODE DNODE_L1_7(.delta(delta_L1[7]), .atj(a_L0), .zk(z_L1[7]), .dalpha(dalpha_L1_j_7), .dbeta(dbeta_L1[7]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 7 172 | NN_DNODE DNODE_L1_8(.delta(delta_L1[8]), .atj(a_L0), .zk(z_L1[8]), .dalpha(dalpha_L1_j_8), .dbeta(dbeta_L1[8]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 8 173 | NN_DNODE DNODE_L1_9(.delta(delta_L1[9]), .atj(a_L0), .zk(z_L1[9]), .dalpha(dalpha_L1_j_9), .dbeta(dbeta_L1[9]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 9 174 | NN_DNODE DNODE_L1_10(.delta(delta_L1[10]), .atj(a_L0), .zk(z_L1[10]), .dalpha(dalpha_L1_j_10), .dbeta(dbeta_L1[10]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 10 175 | NN_DNODE DNODE_L1_11(.delta(delta_L1[11]), .atj(a_L0), .zk(z_L1[11]), .dalpha(dalpha_L1_j_11), .dbeta(dbeta_L1[11]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 11 176 | NN_DNODE DNODE_L1_12(.delta(delta_L1[12]), .atj(a_L0), .zk(z_L1[12]), .dalpha(dalpha_L1_j_12), .dbeta(dbeta_L1[12]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 12 177 | NN_DNODE DNODE_L1_13(.delta(delta_L1[13]), .atj(a_L0), .zk(z_L1[13]), .dalpha(dalpha_L1_j_13), .dbeta(dbeta_L1[13]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 13 178 | NN_DNODE DNODE_L1_14(.delta(delta_L1[14]), .atj(a_L0), .zk(z_L1[14]), .dalpha(dalpha_L1_j_14), .dbeta(dbeta_L1[14]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 14 179 | NN_DNODE DNODE_L1_15(.delta(delta_L1[15]), .atj(a_L0), .zk(z_L1[15]), .dalpha(dalpha_L1_j_15), .dbeta(dbeta_L1[15]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 15 180 | NN_DNODE DNODE_L1_16(.delta(delta_L1[16]), .atj(a_L0), .zk(z_L1[16]), .dalpha(dalpha_L1_j_16), .dbeta(dbeta_L1[16]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 16 181 | NN_DNODE DNODE_L1_17(.delta(delta_L1[17]), .atj(a_L0), .zk(z_L1[17]), .dalpha(dalpha_L1_j_17), .dbeta(dbeta_L1[17]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 17 182 | NN_DNODE DNODE_L1_18(.delta(delta_L1[18]), .atj(a_L0), .zk(z_L1[18]), .dalpha(dalpha_L1_j_18), .dbeta(dbeta_L1[18]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 18 183 | NN_DNODE DNODE_L1_19(.delta(delta_L1[19]), .atj(a_L0), .zk(z_L1[19]), .dalpha(dalpha_L1_j_19), .dbeta(dbeta_L1[19]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 19 184 | NN_DNODE DNODE_L1_20(.delta(delta_L1[20]), .atj(a_L0), .zk(z_L1[20]), .dalpha(dalpha_L1_j_20), .dbeta(dbeta_L1[20]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 20 185 | NN_DNODE DNODE_L1_21(.delta(delta_L1[21]), .atj(a_L0), .zk(z_L1[21]), .dalpha(dalpha_L1_j_21), .dbeta(dbeta_L1[21]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 21 186 | NN_DNODE DNODE_L1_22(.delta(delta_L1[22]), .atj(a_L0), .zk(z_L1[22]), .dalpha(dalpha_L1_j_22), .dbeta(dbeta_L1[22]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 22 187 | NN_DNODE DNODE_L1_23(.delta(delta_L1[23]), .atj(a_L0), .zk(z_L1[23]), .dalpha(dalpha_L1_j_23), .dbeta(dbeta_L1[23]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 23 188 | NN_DNODE DNODE_L1_24(.delta(delta_L1[24]), .atj(a_L0), .zk(z_L1[24]), .dalpha(dalpha_L1_j_24), .dbeta(dbeta_L1[24]), .CLK(CLK), .INIT(BP_FRAME)); // layer 1 node 24 189 | defparam DNODE_L1_0.NN = 5; 190 | defparam DNODE_L1_0.MEMSIZE = MEMSIZE; 191 | defparam DNODE_L1_1.NN = 5; 192 | defparam DNODE_L1_1.MEMSIZE = MEMSIZE; 193 | defparam DNODE_L1_2.NN = 5; 194 | defparam DNODE_L1_2.MEMSIZE = MEMSIZE; 195 | defparam DNODE_L1_3.NN = 5; 196 | defparam DNODE_L1_3.MEMSIZE = MEMSIZE; 197 | defparam DNODE_L1_4.NN = 5; 198 | defparam DNODE_L1_4.MEMSIZE = MEMSIZE; 199 | defparam DNODE_L1_5.NN = 5; 200 | defparam DNODE_L1_5.MEMSIZE = MEMSIZE; 201 | defparam DNODE_L1_6.NN = 5; 202 | defparam DNODE_L1_6.MEMSIZE = MEMSIZE; 203 | defparam DNODE_L1_7.NN = 5; 204 | defparam DNODE_L1_7.MEMSIZE = MEMSIZE; 205 | defparam DNODE_L1_8.NN = 5; 206 | defparam DNODE_L1_8.MEMSIZE = MEMSIZE; 207 | defparam DNODE_L1_9.NN = 5; 208 | defparam DNODE_L1_9.MEMSIZE = MEMSIZE; 209 | defparam DNODE_L1_10.NN = 5; 210 | defparam DNODE_L1_10.MEMSIZE = MEMSIZE; 211 | defparam DNODE_L1_11.NN = 5; 212 | defparam DNODE_L1_11.MEMSIZE = MEMSIZE; 213 | defparam DNODE_L1_12.NN = 5; 214 | defparam DNODE_L1_12.MEMSIZE = MEMSIZE; 215 | defparam DNODE_L1_13.NN = 5; 216 | defparam DNODE_L1_13.MEMSIZE = MEMSIZE; 217 | defparam DNODE_L1_14.NN = 5; 218 | defparam DNODE_L1_14.MEMSIZE = MEMSIZE; 219 | defparam DNODE_L1_15.NN = 5; 220 | defparam DNODE_L1_15.MEMSIZE = MEMSIZE; 221 | defparam DNODE_L1_16.NN = 5; 222 | defparam DNODE_L1_16.MEMSIZE = MEMSIZE; 223 | defparam DNODE_L1_17.NN = 5; 224 | defparam DNODE_L1_17.MEMSIZE = MEMSIZE; 225 | defparam DNODE_L1_18.NN = 5; 226 | defparam DNODE_L1_18.MEMSIZE = MEMSIZE; 227 | defparam DNODE_L1_19.NN = 5; 228 | defparam DNODE_L1_19.MEMSIZE = MEMSIZE; 229 | defparam DNODE_L1_20.NN = 5; 230 | defparam DNODE_L1_20.MEMSIZE = MEMSIZE; 231 | defparam DNODE_L1_21.NN = 5; 232 | defparam DNODE_L1_21.MEMSIZE = MEMSIZE; 233 | defparam DNODE_L1_22.NN = 5; 234 | defparam DNODE_L1_22.MEMSIZE = MEMSIZE; 235 | defparam DNODE_L1_23.NN = 5; 236 | defparam DNODE_L1_23.MEMSIZE = MEMSIZE; 237 | defparam DNODE_L1_24.NN = 5; 238 | defparam DNODE_L1_24.MEMSIZE = MEMSIZE; 239 | 240 | assign SIGN_dalpha_L1_j_0 = {SIGN_L1[0], SIGN_L1[0], SIGN_L1[0], SIGN_L1[0], SIGN_L1[0]}; 241 | assign SIGN_dalpha_L1_j_1 = {SIGN_L1[1], SIGN_L1[1], SIGN_L1[1], SIGN_L1[1], SIGN_L1[1]}; 242 | assign SIGN_dalpha_L1_j_2 = {SIGN_L1[2], SIGN_L1[2], SIGN_L1[2], SIGN_L1[2], SIGN_L1[2]}; 243 | assign SIGN_dalpha_L1_j_3 = {SIGN_L1[3], SIGN_L1[3], SIGN_L1[3], SIGN_L1[3], SIGN_L1[3]}; 244 | assign SIGN_dalpha_L1_j_4 = {SIGN_L1[4], SIGN_L1[4], SIGN_L1[4], SIGN_L1[4], SIGN_L1[4]}; 245 | assign SIGN_dalpha_L1_j_5 = {SIGN_L1[5], SIGN_L1[5], SIGN_L1[5], SIGN_L1[5], SIGN_L1[5]}; 246 | assign SIGN_dalpha_L1_j_6 = {SIGN_L1[6], SIGN_L1[6], SIGN_L1[6], SIGN_L1[6], SIGN_L1[6]}; 247 | assign SIGN_dalpha_L1_j_7 = {SIGN_L1[7], SIGN_L1[7], SIGN_L1[7], SIGN_L1[7], SIGN_L1[7]}; 248 | assign SIGN_dalpha_L1_j_8 = {SIGN_L1[8], SIGN_L1[8], SIGN_L1[8], SIGN_L1[8], SIGN_L1[8]}; 249 | assign SIGN_dalpha_L1_j_9 = {SIGN_L1[9], SIGN_L1[9], SIGN_L1[9], SIGN_L1[9], SIGN_L1[9]}; 250 | assign SIGN_dalpha_L1_j_10 = {SIGN_L1[10], SIGN_L1[10], SIGN_L1[10], SIGN_L1[10], SIGN_L1[10]}; 251 | assign SIGN_dalpha_L1_j_11 = {SIGN_L1[11], SIGN_L1[11], SIGN_L1[11], SIGN_L1[11], SIGN_L1[11]}; 252 | assign SIGN_dalpha_L1_j_12 = {SIGN_L1[12], SIGN_L1[12], SIGN_L1[12], SIGN_L1[12], SIGN_L1[12]}; 253 | assign SIGN_dalpha_L1_j_13 = {SIGN_L1[13], SIGN_L1[13], SIGN_L1[13], SIGN_L1[13], SIGN_L1[13]}; 254 | assign SIGN_dalpha_L1_j_14 = {SIGN_L1[14], SIGN_L1[14], SIGN_L1[14], SIGN_L1[14], SIGN_L1[14]}; 255 | assign SIGN_dalpha_L1_j_15 = {SIGN_L1[15], SIGN_L1[15], SIGN_L1[15], SIGN_L1[15], SIGN_L1[15]}; 256 | assign SIGN_dalpha_L1_j_16 = {SIGN_L1[16], SIGN_L1[16], SIGN_L1[16], SIGN_L1[16], SIGN_L1[16]}; 257 | assign SIGN_dalpha_L1_j_17 = {SIGN_L1[17], SIGN_L1[17], SIGN_L1[17], SIGN_L1[17], SIGN_L1[17]}; 258 | assign SIGN_dalpha_L1_j_18 = {SIGN_L1[18], SIGN_L1[18], SIGN_L1[18], SIGN_L1[18], SIGN_L1[18]}; 259 | assign SIGN_dalpha_L1_j_19 = {SIGN_L1[19], SIGN_L1[19], SIGN_L1[19], SIGN_L1[19], SIGN_L1[19]}; 260 | assign SIGN_dalpha_L1_j_20 = {SIGN_L1[20], SIGN_L1[20], SIGN_L1[20], SIGN_L1[20], SIGN_L1[20]}; 261 | assign SIGN_dalpha_L1_j_21 = {SIGN_L1[21], SIGN_L1[21], SIGN_L1[21], SIGN_L1[21], SIGN_L1[21]}; 262 | assign SIGN_dalpha_L1_j_22 = {SIGN_L1[22], SIGN_L1[22], SIGN_L1[22], SIGN_L1[22], SIGN_L1[22]}; 263 | assign SIGN_dalpha_L1_j_23 = {SIGN_L1[23], SIGN_L1[23], SIGN_L1[23], SIGN_L1[23], SIGN_L1[23]}; 264 | assign SIGN_dalpha_L1_j_24 = {SIGN_L1[24], SIGN_L1[24], SIGN_L1[24], SIGN_L1[24], SIGN_L1[24]}; 265 | assign SIGN_dbeta_L1 = SIGN_L1; 266 | 267 | 268 | // Backpropagation: 269 | 270 | assign delta_L3[0] = eps[0] & (zp_L3[0]); 271 | assign delta_L3[1] = eps[1] & (zp_L3[1]); 272 | assign delta_L3[2] = eps[2] & (zp_L3[2]); 273 | assign delta_L3[3] = eps[3] & (zp_L3[3]); 274 | assign delta_L3[4] = eps[4] & (zp_L3[4]); 275 | 276 | FULLCONNBLOCKBP_L2 FULLCONNBLOCKBP_L2_0( 277 | .alpha_j_0(alpha_L3_j_0), .alpha_j_1(alpha_L3_j_1), .alpha_j_2(alpha_L3_j_2), .alpha_j_3(alpha_L3_j_3), .alpha_j_4(alpha_L3_j_4), 278 | .SIGN_alpha_j_0(SIGN_alpha_L3_j_0), .SIGN_alpha_j_1(SIGN_alpha_L3_j_1), .SIGN_alpha_j_2(SIGN_alpha_L3_j_2), .SIGN_alpha_j_3(SIGN_alpha_L3_j_3), .SIGN_alpha_j_4(SIGN_alpha_L3_j_4), 279 | .z(z_L2), 280 | .zp(zp_L2), 281 | .delta_in(delta_L3), 282 | .SIGN_delta_in(SIGN_L3), 283 | .delta_out(delta_L2), 284 | .SIGN_delta_out(SIGN_L2), 285 | .R_BPsource(R_BP0[2]), 286 | .CLK(CLK), .INIT(INIT) 287 | ); 288 | 289 | FULLCONNBLOCKBP_L1 FULLCONNBLOCKBP_L1_0( 290 | .alpha_j_0(alpha_L2_j_0), .alpha_j_1(alpha_L2_j_1), .alpha_j_2(alpha_L2_j_2), .alpha_j_3(alpha_L2_j_3), .alpha_j_4(alpha_L2_j_4), .alpha_j_5(alpha_L2_j_5), .alpha_j_6(alpha_L2_j_6), .alpha_j_7(alpha_L2_j_7), 291 | .SIGN_alpha_j_0(SIGN_alpha_L2_j_0), .SIGN_alpha_j_1(SIGN_alpha_L2_j_1), .SIGN_alpha_j_2(SIGN_alpha_L2_j_2), .SIGN_alpha_j_3(SIGN_alpha_L2_j_3), .SIGN_alpha_j_4(SIGN_alpha_L2_j_4), .SIGN_alpha_j_5(SIGN_alpha_L2_j_5), .SIGN_alpha_j_6(SIGN_alpha_L2_j_6), .SIGN_alpha_j_7(SIGN_alpha_L2_j_7), 292 | .z(z_L1), 293 | .zp(zp_L1), 294 | .delta_in(delta_L2), 295 | .SIGN_delta_in(SIGN_L2), 296 | .delta_out(delta_L1), 297 | .SIGN_delta_out(SIGN_L1), 298 | .R_BPsource(R_BP0[1]), 299 | .CLK(CLK), .INIT(INIT) 300 | ); 301 | 302 | 303 | endmodule 304 | --------------------------------------------------------------------------------