├── LICENSE ├── Makefile ├── README.md ├── cape-univ-audio-00A0.dts ├── cape-univ-emmc-00A0.dts ├── cape-univ-hdmi-00A0.dts ├── cape-universal-00A0.dts ├── cape-universala-00A0.dts ├── cape-universalh-00A0.dts ├── cape-universaln-00A0.dts └── config-pin /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. By contrast, the GNU General Public 13 | License is intended to guarantee your freedom to share and change free 14 | software--to make sure the software is free for all its users. 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It is safest 289 | to attach them to the start of each source file to most effectively 290 | convey the exclusion of warranty; and each file should have at least 291 | the "copyright" line and a pointer to where the full notice is found. 292 | 293 | {description} 294 | Copyright (C) {year} {fullname} 295 | 296 | This program is free software; you can redistribute it and/or modify 297 | it under the terms of the GNU General Public License as published by 298 | the Free Software Foundation; either version 2 of the License, or 299 | (at your option) any later version. 300 | 301 | This program is distributed in the hope that it will be useful, 302 | but WITHOUT ANY WARRANTY; without even the implied warranty of 303 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 304 | GNU General Public License for more details. 305 | 306 | You should have received a copy of the GNU General Public License along 307 | with this program; if not, write to the Free Software Foundation, Inc., 308 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this 313 | when it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author 316 | Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 317 | This is free software, and you are welcome to redistribute it 318 | under certain conditions; type `show c' for details. 319 | 320 | The hypothetical commands `show w' and `show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | {signature of Ty Coon}, 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | PREFIX ?= /usr/bin 2 | FIRMWAREPATH ?= /lib/firmware 3 | BUILDPATH = . 4 | 5 | SRC = cape-universal-00A0.dts 6 | SRC += cape-universala-00A0.dts 7 | SRC += cape-universaln-00A0.dts 8 | SRC += cape-universalh-00A0.dts 9 | SRC += cape-univ-emmc-00A0.dts 10 | SRC += cape-univ-hdmi-00A0.dts 11 | SRC += cape-univ-audio-00A0.dts 12 | TARGET = config-pin 13 | 14 | all: ensure_path build 15 | 16 | install: install_overlays install_target 17 | 18 | # Compile: create dtbo files from dts files. 19 | $(BUILDPATH)/%.dtbo : %.dts 20 | @echo "Compiling file: $<" 21 | dtc -@ -I dts -O dtb -o $@ $< 22 | 23 | ensure_path: 24 | mkdir -p $(BUILDPATH) 25 | mkdir -p $(PREFIX) 26 | mkdir -p $(FIRMWAREPATH) 27 | 28 | 29 | build : $(SRC:%.dts=$(BUILDPATH)/%.dtbo) 30 | 31 | $(FIRMWAREPATH)/%.dtbo : $(BUILDPATH)/%.dtbo 32 | @echo "Installing file: $<" 33 | cp $< $@ 34 | 35 | install_overlays: $(SRC:%.dts=$(FIRMWAREPATH)/%.dtbo) 36 | 37 | install_target: 38 | @echo "Installing config-pin utility" 39 | cp $(TARGET) $(PREFIX)/ 40 | chmod +x $(PREFIX)/$(TARGET) 41 | 42 | clean: 43 | rm -f $(BUILDPATH)/*.dtbo 44 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # beaglebone-universal-io 2 | 3 | ## Overview 4 | 5 | Device tree overlay and support scripts for using most available 6 | hardware I/O on the BeagleBone without editing dts files or rebuilding 7 | the kernel. 8 | 9 | This project is a series of four overlay files, designed to work with 10 | the BeagleBone Black: 11 | 12 | * cape-universal Exports all pins not used by HDMIN and eMMC (including audio) 13 | * cape-universaln Exports all pins not used by HDMI and eMMC (no audio pins are exported) 14 | * cape-unversalh Exports all pins not used by eMMC 15 | * cape-unversala Exports all pins 16 | * cape-univ-emmc Exports pins used by eMMC, load if eMMC is disabled 17 | * cape-univ-hdmi Exports pins used by HDMI video, load if HDMI is disabled 18 | * cape-univ-audio Exports pins used by HDMI audio 19 | 20 | 21 | ## Usage 22 | 23 | If using a 3.14 or newer kernel, make sure your device tree inclues the 24 | pinmux helper entries required for the pins you want to use. If you're 25 | using an RCN built kernel (if you don't know, you probably are), these 26 | should be present by default. 27 | 28 | If using a 3.8.13 kernel with capemgr, load the overlay as usual 29 | 30 | echo cape-universaln > /sys/devices/bone_capemgr.*/slots 31 | 32 | At this point, the various devices are loaded and all gpio have been 33 | exported. All pins currently default to gpio inputs, with pull up or 34 | pull down resistors set the same as when the AM335x comes out of reset. 35 | This behavior may change, however. If the BeagleBone begins shipping 36 | with some I/O pins configured by default at boot, this overlay will 37 | likely change to match. 38 | 39 | The provided config-pin utility is intended to assist with setting up 40 | the various pin modes and querying the current pin state. 41 | 42 | ``` 43 | # Configure a pin for a specific mode 44 | config-pin P8.07 timer 45 | 46 | # Configure a pin as gpio output and setting the state 47 | config-pin P8.07 hi 48 | config-pin P8.07 low 49 | 50 | # Configure a pin as a gpio input 51 | config-pin P8.07 in 52 | 53 | # List the valid modes for a specific pin 54 | config-pin -l P8.07 55 | 56 | # Query the status of a pin (note the appropriate universal cape 57 | # must be loaded for this to work) 58 | config-pin -q P8.07 59 | 60 | # Complete usage details 61 | config-pin -h 62 | ``` 63 | 64 | ## GUI 65 | 66 | You can find a Qt based graphical user interface for the 67 | beaglebone-universal-io here: https://github.com/strahlex/BBIOConfig 68 | 69 | 70 | ## Details 71 | 72 | If you wish to setup the pins manually, or to know what is happening 73 | behind the curtain, keep reading. 74 | 75 | To control the gpio pins, you may use the sysfs interface. Each 76 | exported gpio pin has an entry under /sys/class/gpio/gpioNN, where NN 77 | represents the kernel gpio number for that pin. If you have forgotten 78 | the BeagleBone pin to kernel gpio number mapping, you may refer to the 79 | list created for you in the status file of the device tree overlay: 80 | 81 | root@arm:~# cat /sys/devices/ocp.*/cape-universal.*/status 82 | 0 P9_92 114 IN 0 83 | 1 P9_42 7 IN 0 84 | 2 P9_91 116 IN 0 85 | 3 P9_41 20 IN 0 86 | 4 P9_31 110 IN 0 87 | 5 P9_30 112 IN 0 88 | ... 89 | 90 | Pin multiplexing is controled via files in /sys/devices/ocp.*/, where 91 | each exported I/O pin has a pinmux control directory. The directory is 92 | named using the actual BeagleBone pin header number, so P8_ or P9_ 93 | followed by the pin number, the suffix _pinmux, and an instance number 94 | (that is subject to change). So a typical full path to the pinmux 95 | control directory for P8 pin 7 might be: 96 | 97 | /sys/devices/ocp.3/P8_07_pinmux.13/ 98 | 99 | However since the instance numbers are subject to change, you are 100 | advised to use shell wildcards for the instance values when referencing 101 | these paths: 102 | 103 | /sys/devices/ocp.*/P8_07_pinmux.*/ 104 | 105 | Each pinmux directory contains a state file, which you can read to 106 | determine the current pinmux setting of the pin: 107 | 108 | root@arm:~# cat /sys/devices/ocp.*/P8_07_pinmux.*/state 109 | default 110 | 111 | Or you can write to change the pinmux setting for the pin: 112 | 113 | root@arm:~# echo timer > /sys/devices/ocp.*/P8_07_pinmux.*/state 114 | root@arm:~# cat /sys/devices/ocp.*/P8_07_pinmux.*/state 115 | timer 116 | 117 | Each pin has a default state and a gpio state. Currently the default 118 | state for all pins is gpio with pull-up/down resistor set to the reset 119 | default value, but this could change. If the BeagleBone begins shipping 120 | with a default I/O setup that enables some special functions, this 121 | overlay will likely change to match. Most pins have other functions 122 | available besides gpio, see the list below for valid settings. 123 | 124 | For a list of valid pinmux states for each pin, use the config-pin 125 | utility: 126 | 127 | config-pin -l 128 | 129 | You will need to reference the AM335x data sheet and Technical Reference 130 | Manual from TI to determine how to setup pin multiplexing for the 131 | various special functions. I find the following reference quite 132 | helpful, particularly the spreadsheet file: 133 | 134 | https://github.com/selsinork/beaglebone-black-pinmux 135 | 136 | -------------------------------------------------------------------------------- /cape-univ-audio-00A0.dts: -------------------------------------------------------------------------------- 1 | // Copyright 2013 2 | // Charles Steinkuehler , Aditya Patadia (aditya.patadia.org) 3 | // 4 | // This program is free software; you can redistribute it and/or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation; either version 2 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with this program; if not, write to the Free Software 16 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 | 18 | /dts-v1/; 19 | /plugin/; 20 | 21 | / { 22 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 23 | 24 | /* identification */ 25 | part-number = "cape-bone-audio"; 26 | version = "00A0"; 27 | 28 | /* state the resources this cape uses */ 29 | exclusive-use = 30 | "P9.25", 31 | "P9.28", 32 | "P9.29", 33 | "P9.31"; 34 | 35 | 36 | fragment@0 { 37 | target = <&am33xx_pinmux>; 38 | __overlay__ { 39 | 40 | /*************************/ 41 | /* P9 Header */ 42 | /*************************/ 43 | 44 | /* P9_25 (ZCZ ball A14) Audio */ 45 | P9_25_default_pin: pinmux_P9_25_default_pin { 46 | pinctrl-single,pins = <0x1ac 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 47 | P9_25_gpio_pin: pinmux_P9_25_gpio_pin { 48 | pinctrl-single,pins = <0x1ac 0x2F>; }; /* Mode 7, RxActive */ 49 | P9_25_gpio_pu_pin: pinmux_P9_25_gpio_pu_pin { 50 | pinctrl-single,pins = <0x1ac 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 51 | P9_25_gpio_pd_pin: pinmux_P9_25_gpio_pd_pin { 52 | pinctrl-single,pins = <0x1ac 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 53 | P9_25_qep_pin: pinmux_P9_25_qep_pin { 54 | pinctrl-single,pins = <0x1ac 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 55 | P9_25_pruout_pin: pinmux_P9_25_pruout_pin { 56 | pinctrl-single,pins = <0x1ac 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 57 | P9_25_pruin_pin: pinmux_P9_25_pruin_pin { 58 | pinctrl-single,pins = <0x1ac 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 59 | 60 | 61 | /* P9_28 (ZCZ ball C12) Audio */ 62 | P9_28_default_pin: pinmux_P9_28_default_pin { 63 | pinctrl-single,pins = <0x19c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 64 | P9_28_gpio_pin: pinmux_P9_28_gpio_pin { 65 | pinctrl-single,pins = <0x19c 0x2F>; }; /* Mode 7, RxActive */ 66 | P9_28_gpio_pu_pin: pinmux_P9_28_gpio_pu_pin { 67 | pinctrl-single,pins = <0x19c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 68 | P9_28_gpio_pd_pin: pinmux_P9_28_gpio_pd_pin { 69 | pinctrl-single,pins = <0x19c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 70 | P9_28_pwm_pin: pinmux_P9_28_pwm_pin { 71 | pinctrl-single,pins = <0x19c 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 72 | P9_28_spi_pin: pinmux_P9_28_spi_pin { 73 | pinctrl-single,pins = <0x19c 0x23>; }; /* Mode 3, Pull-Down, RxActive */ 74 | P9_28_pwm2_pin: pinmux_P9_28_pwm2_pin { 75 | pinctrl-single,pins = <0x19c 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 76 | P9_28_pruout_pin: pinmux_P9_28_pruout_pin { 77 | pinctrl-single,pins = <0x19c 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 78 | P9_28_pruin_pin: pinmux_P9_28_pruin_pin { 79 | pinctrl-single,pins = <0x19c 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 80 | 81 | 82 | /* P9_29 (ZCZ ball B13) Audio */ 83 | P9_29_default_pin: pinmux_P9_29_default_pin { 84 | pinctrl-single,pins = <0x194 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 85 | P9_29_gpio_pin: pinmux_P9_29_gpio_pin { 86 | pinctrl-single,pins = <0x194 0x2F>; }; /* Mode 7, RxActive */ 87 | P9_29_gpio_pu_pin: pinmux_P9_29_gpio_pu_pin { 88 | pinctrl-single,pins = <0x194 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 89 | P9_29_gpio_pd_pin: pinmux_P9_29_gpio_pd_pin { 90 | pinctrl-single,pins = <0x194 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 91 | P9_29_pwm_pin: pinmux_P9_29_pwm_pin { 92 | pinctrl-single,pins = <0x194 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 93 | P9_29_spi_pin: pinmux_P9_29_spi_pin { 94 | pinctrl-single,pins = <0x194 0x23>; }; /* Mode 3, Pull-Down, RxActive */ 95 | P9_29_pruout_pin: pinmux_P9_29_pruout_pin { 96 | pinctrl-single,pins = <0x194 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 97 | P9_29_pruin_pin: pinmux_P9_29_pruin_pin { 98 | pinctrl-single,pins = <0x194 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 99 | 100 | 101 | /* P9_31 (ZCZ ball A13) Audio */ 102 | P9_31_default_pin: pinmux_P9_31_default_pin { 103 | pinctrl-single,pins = <0x190 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 104 | P9_31_gpio_pin: pinmux_P9_31_gpio_pin { 105 | pinctrl-single,pins = <0x190 0x2F>; }; /* Mode 7, RxActive */ 106 | P9_31_gpio_pu_pin: pinmux_P9_31_gpio_pu_pin { 107 | pinctrl-single,pins = <0x190 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 108 | P9_31_gpio_pd_pin: pinmux_P9_31_gpio_pd_pin { 109 | pinctrl-single,pins = <0x190 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 110 | P9_31_pwm_pin: pinmux_P9_31_pwm_pin { 111 | pinctrl-single,pins = <0x190 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 112 | P9_31_spi_pin: pinmux_P9_31_spi_pin { 113 | pinctrl-single,pins = <0x190 0x23>; }; /* Mode 3, Pull-Down, RxActive */ 114 | P9_31_pruout_pin: pinmux_P9_31_pruout_pin { 115 | pinctrl-single,pins = <0x190 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 116 | P9_31_pruin_pin: pinmux_P9_31_pruin_pin { 117 | pinctrl-single,pins = <0x190 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 118 | 119 | 120 | }; 121 | }; 122 | 123 | 124 | /************************/ 125 | /* Pin Multiplexing */ 126 | /************************/ 127 | 128 | fragment@1 { 129 | target = <&ocp>; 130 | __overlay__ { 131 | 132 | /************************/ 133 | /* P9 Header */ 134 | /************************/ 135 | 136 | 137 | P9_25_pinmux { 138 | compatible = "bone-pinmux-helper"; 139 | status = "okay"; 140 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; 141 | pinctrl-0 = <&P9_25_default_pin>; 142 | pinctrl-1 = <&P9_25_gpio_pin>; 143 | pinctrl-2 = <&P9_25_gpio_pu_pin>; 144 | pinctrl-3 = <&P9_25_gpio_pd_pin>; 145 | pinctrl-4 = <&P9_25_qep_pin>; 146 | pinctrl-5 = <&P9_25_pruout_pin>; 147 | pinctrl-6 = <&P9_25_pruin_pin>; 148 | }; 149 | 150 | P9_28_pinmux { 151 | compatible = "bone-pinmux-helper"; 152 | status = "okay"; 153 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pwm2", "pruout", "pruin"; 154 | pinctrl-0 = <&P9_28_default_pin>; 155 | pinctrl-1 = <&P9_28_gpio_pin>; 156 | pinctrl-2 = <&P9_28_gpio_pu_pin>; 157 | pinctrl-3 = <&P9_28_gpio_pd_pin>; 158 | pinctrl-4 = <&P9_28_pwm_pin>; 159 | pinctrl-5 = <&P9_28_spi_pin>; 160 | pinctrl-6 = <&P9_28_pwm2_pin>; 161 | pinctrl-7 = <&P9_28_pruout_pin>; 162 | pinctrl-8 = <&P9_28_pruin_pin>; 163 | }; 164 | 165 | P9_29_pinmux { 166 | compatible = "bone-pinmux-helper"; 167 | status = "okay"; 168 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pruout", "pruin"; 169 | pinctrl-0 = <&P9_29_default_pin>; 170 | pinctrl-1 = <&P9_29_gpio_pin>; 171 | pinctrl-2 = <&P9_29_gpio_pu_pin>; 172 | pinctrl-3 = <&P9_29_gpio_pd_pin>; 173 | pinctrl-4 = <&P9_29_pwm_pin>; 174 | pinctrl-5 = <&P9_29_spi_pin>; 175 | pinctrl-6 = <&P9_29_pruout_pin>; 176 | pinctrl-7 = <&P9_29_pruin_pin>; 177 | }; 178 | 179 | P9_31_pinmux { 180 | compatible = "bone-pinmux-helper"; 181 | status = "okay"; 182 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pruout", "pruin"; 183 | pinctrl-0 = <&P9_31_default_pin>; 184 | pinctrl-1 = <&P9_31_gpio_pin>; 185 | pinctrl-2 = <&P9_31_gpio_pu_pin>; 186 | pinctrl-3 = <&P9_31_gpio_pd_pin>; 187 | pinctrl-4 = <&P9_31_pwm_pin>; 188 | pinctrl-5 = <&P9_31_spi_pin>; 189 | pinctrl-6 = <&P9_31_pruout_pin>; 190 | pinctrl-7 = <&P9_31_pruin_pin>; 191 | }; 192 | }; 193 | }; 194 | 195 | fragment@2 { 196 | target = <&ocp>; 197 | __overlay__ { 198 | 199 | // !!!WARNING!!! 200 | // gpio-of-helper &gpio pointers are off-by-one vs. the hardware: 201 | // hardware GPIO bank 0 = &gpio1 202 | cape-universal { 203 | compatible = "gpio-of-helper"; 204 | status = "okay"; 205 | pinctrl-names = "default"; 206 | pinctrl-0 = <>; 207 | 208 | P9_25 { 209 | gpio-name = "P9_25"; 210 | gpio = <&gpio4 21 0>; 211 | input; 212 | dir-changeable; 213 | }; 214 | 215 | P9_28 { 216 | gpio-name = "P9_28"; 217 | gpio = <&gpio4 17 0>; 218 | input; 219 | dir-changeable; 220 | }; 221 | 222 | P9_29 { 223 | gpio-name = "P9_29"; 224 | gpio = <&gpio4 15 0>; 225 | input; 226 | dir-changeable; 227 | }; 228 | 229 | P9_31 { 230 | gpio-name = "P9_31"; 231 | gpio = <&gpio4 14 0>; 232 | input; 233 | dir-changeable; 234 | }; 235 | 236 | }; 237 | }; 238 | }; 239 | }; 240 | -------------------------------------------------------------------------------- /cape-univ-emmc-00A0.dts: -------------------------------------------------------------------------------- 1 | // Copyright 2013 2 | // Charles Steinkuehler 3 | // 4 | // This program is free software; you can redistribute it and/or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation; either version 2 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with this program; if not, write to the Free Software 16 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 | 18 | /dts-v1/; 19 | /plugin/; 20 | 21 | / { 22 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 23 | 24 | /* identification */ 25 | part-number = "cape-bone-universal"; 26 | version = "00A0"; 27 | 28 | /* state the resources this cape uses */ 29 | exclusive-use = 30 | 31 | "P8.3", /* emmc */ 32 | "P8.4", /* emmc */ 33 | "P8.5", /* emmc */ 34 | "P8.6", /* emmc */ 35 | "P8.20", /* emmc */ 36 | "P8.21", /* emmc */ 37 | "P8.22", /* emmc */ 38 | "P8.23", /* emmc */ 39 | "P8.24", /* emmc */ 40 | "P8.25"; /* emmc */ 41 | 42 | fragment@0 { 43 | target = <&am33xx_pinmux>; 44 | __overlay__ { 45 | 46 | /************************/ 47 | /* P8 Header */ 48 | /************************/ 49 | 50 | /* P8_01 GND */ 51 | /* P8_02 GND */ 52 | /* P8_03 (ZCZ ball R9 ) emmc */ 53 | P8_03_default_pin: pinmux_P8_03_default_pin { 54 | pinctrl-single,pins = <0x018 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 55 | P8_03_gpio_pin: pinmux_P8_03_gpio_pin { 56 | pinctrl-single,pins = <0x018 0x2F>; }; /* Mode 7, RxActive */ 57 | P8_03_gpio_pu_pin: pinmux_P8_03_gpio_pu_pin { 58 | pinctrl-single,pins = <0x018 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 59 | P8_03_gpio_pd_pin: pinmux_P8_03_gpio_pd_pin { 60 | pinctrl-single,pins = <0x018 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 61 | 62 | /* P8_04 (ZCZ ball T9 ) emmc */ 63 | P8_04_default_pin: pinmux_P8_04_default_pin { 64 | pinctrl-single,pins = <0x01c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 65 | P8_04_gpio_pin: pinmux_P8_04_gpio_pin { 66 | pinctrl-single,pins = <0x01c 0x2F>; }; /* Mode 7, RxActive */ 67 | P8_04_gpio_pu_pin: pinmux_P8_04_gpio_pu_pin { 68 | pinctrl-single,pins = <0x01c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 69 | P8_04_gpio_pd_pin: pinmux_P8_04_gpio_pd_pin { 70 | pinctrl-single,pins = <0x01c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 71 | 72 | /* P8_05 (ZCZ ball R8 ) emmc */ 73 | P8_05_default_pin: pinmux_P8_05_default_pin { 74 | pinctrl-single,pins = <0x008 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 75 | P8_05_gpio_pin: pinmux_P8_05_gpio_pin { 76 | pinctrl-single,pins = <0x008 0x2F>; }; /* Mode 7, RxActive */ 77 | P8_05_gpio_pu_pin: pinmux_P8_05_gpio_pu_pin { 78 | pinctrl-single,pins = <0x008 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 79 | P8_05_gpio_pd_pin: pinmux_P8_05_gpio_pd_pin { 80 | pinctrl-single,pins = <0x008 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 81 | 82 | /* P8_06 (ZCZ ball T8 ) emmc */ 83 | P8_06_default_pin: pinmux_P8_06_default_pin { 84 | pinctrl-single,pins = <0x00c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 85 | P8_06_gpio_pin: pinmux_P8_06_gpio_pin { 86 | pinctrl-single,pins = <0x00c 0x2F>; }; /* Mode 7, RxActive */ 87 | P8_06_gpio_pu_pin: pinmux_P8_06_gpio_pu_pin { 88 | pinctrl-single,pins = <0x00c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 89 | P8_06_gpio_pd_pin: pinmux_P8_06_gpio_pd_pin { 90 | pinctrl-single,pins = <0x00c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 91 | 92 | 93 | /* P8_20 (ZCZ ball V9 ) emmc */ 94 | P8_20_default_pin: pinmux_P8_20_default_pin { 95 | pinctrl-single,pins = <0x084 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 96 | P8_20_gpio_pin: pinmux_P8_20_gpio_pin { 97 | pinctrl-single,pins = <0x084 0x2F>; }; /* Mode 7, RxActive */ 98 | P8_20_gpio_pu_pin: pinmux_P8_20_gpio_pu_pin { 99 | pinctrl-single,pins = <0x084 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 100 | P8_20_gpio_pd_pin: pinmux_P8_20_gpio_pd_pin { 101 | pinctrl-single,pins = <0x084 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 102 | P8_20_pruout_pin: pinmux_P8_20_pruout_pin { 103 | pinctrl-single,pins = <0x084 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 104 | P8_20_pruin_pin: pinmux_P8_20_pruin_pin { 105 | pinctrl-single,pins = <0x084 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 106 | 107 | 108 | /* P8_21 (ZCZ ball U9 ) emmc */ 109 | P8_21_default_pin: pinmux_P8_21_default_pin { 110 | pinctrl-single,pins = <0x080 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 111 | P8_21_gpio_pin: pinmux_P8_21_gpio_pin { 112 | pinctrl-single,pins = <0x080 0x2F>; }; /* Mode 7, RxActive */ 113 | P8_21_gpio_pu_pin: pinmux_P8_21_gpio_pu_pin { 114 | pinctrl-single,pins = <0x080 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 115 | P8_21_gpio_pd_pin: pinmux_P8_21_gpio_pd_pin { 116 | pinctrl-single,pins = <0x080 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 117 | P8_21_pruout_pin: pinmux_P8_21_pruout_pin { 118 | pinctrl-single,pins = <0x080 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 119 | P8_21_pruin_pin: pinmux_P8_21_pruin_pin { 120 | pinctrl-single,pins = <0x080 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 121 | 122 | /* P8_22 (ZCZ ball V8 ) emmc */ 123 | P8_22_default_pin: pinmux_P8_22_default_pin { 124 | pinctrl-single,pins = <0x014 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 125 | P8_22_gpio_pin: pinmux_P8_22_gpio_pin { 126 | pinctrl-single,pins = <0x014 0x2F>; }; /* Mode 7, RxActive */ 127 | P8_22_gpio_pu_pin: pinmux_P8_22_gpio_pu_pin { 128 | pinctrl-single,pins = <0x014 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 129 | P8_22_gpio_pd_pin: pinmux_P8_22_gpio_pd_pin { 130 | pinctrl-single,pins = <0x014 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 131 | 132 | /* P8_23 (ZCZ ball U8 ) emmc */ 133 | P8_23_default_pin: pinmux_P8_23_default_pin { 134 | pinctrl-single,pins = <0x010 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 135 | P8_23_gpio_pin: pinmux_P8_23_gpio_pin { 136 | pinctrl-single,pins = <0x010 0x2F>; }; /* Mode 7, RxActive */ 137 | P8_23_gpio_pu_pin: pinmux_P8_23_gpio_pu_pin { 138 | pinctrl-single,pins = <0x010 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 139 | P8_23_gpio_pd_pin: pinmux_P8_23_gpio_pd_pin { 140 | pinctrl-single,pins = <0x010 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 141 | 142 | /* P8_24 (ZCZ ball V7 ) emmc */ 143 | P8_24_default_pin: pinmux_P8_24_default_pin { 144 | pinctrl-single,pins = <0x004 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 145 | P8_24_gpio_pin: pinmux_P8_24_gpio_pin { 146 | pinctrl-single,pins = <0x004 0x2F>; }; /* Mode 7, RxActive */ 147 | P8_24_gpio_pu_pin: pinmux_P8_24_gpio_pu_pin { 148 | pinctrl-single,pins = <0x004 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 149 | P8_24_gpio_pd_pin: pinmux_P8_24_gpio_pd_pin { 150 | pinctrl-single,pins = <0x004 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 151 | 152 | /* P8_25 (ZCZ ball U7 ) emmc */ 153 | P8_25_default_pin: pinmux_P8_25_default_pin { 154 | pinctrl-single,pins = <0x000 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 155 | P8_25_gpio_pin: pinmux_P8_25_gpio_pin { 156 | pinctrl-single,pins = <0x000 0x2F>; }; /* Mode 7, RxActive */ 157 | P8_25_gpio_pu_pin: pinmux_P8_25_gpio_pu_pin { 158 | pinctrl-single,pins = <0x000 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 159 | P8_25_gpio_pd_pin: pinmux_P8_25_gpio_pd_pin { 160 | pinctrl-single,pins = <0x000 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 161 | 162 | }; 163 | }; 164 | 165 | 166 | /************************/ 167 | /* Pin Multiplexing */ 168 | /************************/ 169 | 170 | fragment@1 { 171 | target = <&ocp>; 172 | __overlay__ { 173 | 174 | /************************/ 175 | /* P8 Header */ 176 | /************************/ 177 | 178 | P8_03_pinmux { 179 | compatible = "bone-pinmux-helper"; 180 | status = "okay"; 181 | 182 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 183 | pinctrl-0 = <&P8_03_default_pin>; 184 | pinctrl-1 = <&P8_03_gpio_pin>; 185 | pinctrl-2 = <&P8_03_gpio_pu_pin>; 186 | pinctrl-3 = <&P8_03_gpio_pd_pin>; 187 | }; 188 | 189 | P8_04_pinmux { 190 | compatible = "bone-pinmux-helper"; 191 | status = "okay"; 192 | 193 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 194 | pinctrl-0 = <&P8_04_default_pin>; 195 | pinctrl-1 = <&P8_04_gpio_pin>; 196 | pinctrl-2 = <&P8_04_gpio_pu_pin>; 197 | pinctrl-3 = <&P8_04_gpio_pd_pin>; 198 | }; 199 | 200 | P8_05_pinmux { 201 | compatible = "bone-pinmux-helper"; 202 | status = "okay"; 203 | 204 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 205 | pinctrl-0 = <&P8_05_default_pin>; 206 | pinctrl-1 = <&P8_05_gpio_pin>; 207 | pinctrl-2 = <&P8_05_gpio_pu_pin>; 208 | pinctrl-3 = <&P8_05_gpio_pd_pin>; 209 | }; 210 | 211 | P8_06_pinmux { 212 | compatible = "bone-pinmux-helper"; 213 | status = "okay"; 214 | 215 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 216 | pinctrl-0 = <&P8_06_default_pin>; 217 | pinctrl-1 = <&P8_06_gpio_pin>; 218 | pinctrl-2 = <&P8_06_gpio_pu_pin>; 219 | pinctrl-3 = <&P8_06_gpio_pd_pin>; 220 | }; 221 | 222 | P8_20_pinmux { 223 | compatible = "bone-pinmux-helper"; 224 | status = "okay"; 225 | 226 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 227 | pinctrl-0 = <&P8_20_default_pin>; 228 | pinctrl-1 = <&P8_20_gpio_pin>; 229 | pinctrl-2 = <&P8_20_gpio_pu_pin>; 230 | pinctrl-3 = <&P8_20_gpio_pd_pin>; 231 | pinctrl-4 = <&P8_20_pruout_pin>; 232 | pinctrl-5 = <&P8_20_pruin_pin>; 233 | }; 234 | 235 | P8_21_pinmux { 236 | compatible = "bone-pinmux-helper"; 237 | status = "okay"; 238 | 239 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 240 | pinctrl-0 = <&P8_21_default_pin>; 241 | pinctrl-1 = <&P8_21_gpio_pin>; 242 | pinctrl-2 = <&P8_21_gpio_pu_pin>; 243 | pinctrl-3 = <&P8_21_gpio_pd_pin>; 244 | pinctrl-4 = <&P8_21_pruout_pin>; 245 | pinctrl-5 = <&P8_21_pruin_pin>; 246 | }; 247 | 248 | P8_22_pinmux { 249 | compatible = "bone-pinmux-helper"; 250 | status = "okay"; 251 | 252 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 253 | pinctrl-0 = <&P8_22_default_pin>; 254 | pinctrl-1 = <&P8_22_gpio_pin>; 255 | pinctrl-2 = <&P8_22_gpio_pu_pin>; 256 | pinctrl-3 = <&P8_22_gpio_pd_pin>; 257 | }; 258 | 259 | P8_23_pinmux { 260 | compatible = "bone-pinmux-helper"; 261 | status = "okay"; 262 | 263 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 264 | pinctrl-0 = <&P8_23_default_pin>; 265 | pinctrl-1 = <&P8_23_gpio_pin>; 266 | pinctrl-2 = <&P8_23_gpio_pu_pin>; 267 | pinctrl-3 = <&P8_23_gpio_pd_pin>; 268 | }; 269 | 270 | P8_24_pinmux { 271 | compatible = "bone-pinmux-helper"; 272 | status = "okay"; 273 | 274 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 275 | pinctrl-0 = <&P8_24_default_pin>; 276 | pinctrl-1 = <&P8_24_gpio_pin>; 277 | pinctrl-2 = <&P8_24_gpio_pu_pin>; 278 | pinctrl-3 = <&P8_24_gpio_pd_pin>; 279 | }; 280 | 281 | P8_25_pinmux { 282 | compatible = "bone-pinmux-helper"; 283 | status = "okay"; 284 | 285 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 286 | pinctrl-0 = <&P8_25_default_pin>; 287 | pinctrl-1 = <&P8_25_gpio_pin>; 288 | pinctrl-2 = <&P8_25_gpio_pu_pin>; 289 | pinctrl-3 = <&P8_25_gpio_pd_pin>; 290 | }; 291 | }; 292 | }; 293 | 294 | fragment@2 { 295 | target = <&ocp>; 296 | __overlay__ { 297 | 298 | // !!!WARNING!!! 299 | // gpio-of-helper &gpio pointers are off-by-one vs. the hardware: 300 | // hardware GPIO bank 0 = &gpio1 301 | cape-universal { 302 | compatible = "gpio-of-helper"; 303 | status = "okay"; 304 | pinctrl-names = "default"; 305 | pinctrl-0 = <>; 306 | 307 | P8_03 { 308 | gpio-name = "P8_03"; 309 | gpio = <&gpio2 6 0>; 310 | input; 311 | dir-changeable; 312 | }; 313 | P8_04 { 314 | gpio-name = "P8_04"; 315 | gpio = <&gpio2 7 0>; 316 | input; 317 | dir-changeable; 318 | }; 319 | P8_05 { 320 | gpio-name = "P8_05"; 321 | gpio = <&gpio2 2 0>; 322 | input; 323 | dir-changeable; 324 | }; 325 | P8_06 { 326 | gpio-name = "P8_06"; 327 | gpio = <&gpio2 3 0>; 328 | input; 329 | dir-changeable; 330 | }; 331 | P8_20 { 332 | gpio-name = "P8_20"; 333 | gpio = <&gpio2 31 0>; 334 | input; 335 | dir-changeable; 336 | }; 337 | P8_21 { 338 | gpio-name = "P8_21"; 339 | gpio = <&gpio2 30 0>; 340 | input; 341 | dir-changeable; 342 | }; 343 | P8_22 { 344 | gpio-name = "P8_22"; 345 | gpio = <&gpio2 5 0>; 346 | input; 347 | dir-changeable; 348 | }; 349 | P8_23 { 350 | gpio-name = "P8_23"; 351 | gpio = <&gpio2 4 0>; 352 | input; 353 | dir-changeable; 354 | }; 355 | P8_24 { 356 | gpio-name = "P8_24"; 357 | gpio = <&gpio2 1 0>; 358 | input; 359 | dir-changeable; 360 | }; 361 | P8_25 { 362 | gpio-name = "P8_25"; 363 | gpio = <&gpio2 0 0>; 364 | input; 365 | dir-changeable; 366 | }; 367 | 368 | }; 369 | }; 370 | }; 371 | 372 | }; 373 | -------------------------------------------------------------------------------- /cape-univ-hdmi-00A0.dts: -------------------------------------------------------------------------------- 1 | // Copyright 2013 2 | // Charles Steinkuehler 3 | // 4 | // This program is free software; you can redistribute it and/or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation; either version 2 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with this program; if not, write to the Free Software 16 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 | 18 | /dts-v1/; 19 | /plugin/; 20 | 21 | / { 22 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 23 | 24 | /* identification */ 25 | part-number = "cape-univ-hdmi"; 26 | version = "00A0"; 27 | 28 | /* state the resources this cape uses */ 29 | exclusive-use = 30 | "P8.27", 31 | "P8.28", 32 | "P8.29", 33 | "P8.30", 34 | "P8.31", 35 | "P8.32", 36 | "P8.33", 37 | "P8.34", 38 | "P8.35", 39 | "P8.36", 40 | "P8.37", 41 | "P8.38", 42 | "P8.39", 43 | "P8.40", 44 | "P8.41", 45 | "P8.42", 46 | "P8.43", 47 | "P8.44", 48 | "P8.45", 49 | "P8.46", 50 | "uart5", 51 | "epwmss0", 52 | "ehrpwm0", 53 | "ecap0", 54 | "epwmss1", 55 | "ehrpwm1", 56 | "epwmss2", 57 | "ehrpwm2", 58 | "ecap2"; 59 | 60 | 61 | fragment@0 { 62 | target = <&am33xx_pinmux>; 63 | __overlay__ { 64 | 65 | /*************************/ 66 | /* P8 Header */ 67 | /*************************/ 68 | 69 | /* P8_01 GND */ 70 | /* P8_02 GND */ 71 | /* P8_03 (ZCZ ball R9 ) emmc */ 72 | /* P8_04 (ZCZ ball T9 ) emmc */ 73 | /* P8_05 (ZCZ ball R8 ) emmc */ 74 | /* P8_06 (ZCZ ball T8 ) emmc */ 75 | /* P8_07 (ZCZ ball R7 ) */ 76 | /* P8_08 (ZCZ ball T7 ) */ 77 | /* P8_09 (ZCZ ball T6 ) */ 78 | /* P8_10 (ZCZ ball U6 ) */ 79 | /* P8_11 (ZCZ ball R12) */ 80 | /* P8_12 (ZCZ ball T12) */ 81 | /* P8_13 (ZCZ ball T10) */ 82 | /* P8_14 (ZCZ ball T11) */ 83 | /* P8_15 (ZCZ ball U13) */ 84 | /* P8_16 (ZCZ ball V13) */ 85 | /* P8_17 (ZCZ ball U12) */ 86 | /* P8_18 (ZCZ ball V12) */ 87 | /* P8_19 (ZCZ ball U10) */ 88 | /* P8_20 (ZCZ ball V9 ) emmc */ 89 | /* P8_21 (ZCZ ball U9 ) emmc */ 90 | /* P8_22 (ZCZ ball V8 ) emmc */ 91 | /* P8_23 (ZCZ ball U8 ) emmc */ 92 | /* P8_24 (ZCZ ball V7 ) emmc */ 93 | /* P8_25 (ZCZ ball U7 ) emmc */ 94 | /* P8_26 (ZCZ ball V6 ) */ 95 | /* P8_27 (ZCZ ball U5 ) hdmi */ 96 | P8_27_default_pin: pinmux_P8_27_default_pin { 97 | pinctrl-single,pins = <0x0E0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 98 | P8_27_gpio_pin: pinmux_P8_27_gpio_pin { 99 | pinctrl-single,pins = <0x0E0 0x2F>; }; /* Mode 7, RxActive */ 100 | P8_27_gpio_pu_pin: pinmux_P8_27_gpio_pu_pin { 101 | pinctrl-single,pins = <0x0E0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 102 | P8_27_gpio_pd_pin: pinmux_P8_27_gpio_pd_pin { 103 | pinctrl-single,pins = <0x0E0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 104 | P8_27_pruout_pin: pinmux_P8_27_pruout_pin { 105 | pinctrl-single,pins = <0x0E0 0x05>; }; /* Mode 5, Pull-Down*/ 106 | P8_27_pruin_pin: pinmux_P8_27_pruin_pin { 107 | pinctrl-single,pins = <0x0E0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 108 | 109 | /* P8_28 (ZCZ ball V5 ) hdmi */ 110 | P8_28_default_pin: pinmux_P8_28_default_pin { 111 | pinctrl-single,pins = <0x0E8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 112 | P8_28_gpio_pin: pinmux_P8_28_gpio_pin { 113 | pinctrl-single,pins = <0x0E8 0x2F>; }; /* Mode 7, RxActive */ 114 | P8_28_gpio_pu_pin: pinmux_P8_28_gpio_pu_pin { 115 | pinctrl-single,pins = <0x0E8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 116 | P8_28_gpio_pd_pin: pinmux_P8_28_gpio_pd_pin { 117 | pinctrl-single,pins = <0x0E8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 118 | P8_28_pruout_pin: pinmux_P8_28_pruout_pin { 119 | pinctrl-single,pins = <0x0E8 0x05>; }; /* Mode 5, Pull-Down */ 120 | P8_28_pruin_pin: pinmux_P8_28_pruin_pin { 121 | pinctrl-single,pins = <0x0E8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 122 | 123 | /* P8_29 (ZCZ ball R5 ) hdmi */ 124 | P8_29_default_pin: pinmux_P8_29_default_pin { 125 | pinctrl-single,pins = <0x0E4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 126 | P8_29_gpio_pin: pinmux_P8_29_gpio_pin { 127 | pinctrl-single,pins = <0x0E4 0x2F>; }; /* Mode 7, RxActive */ 128 | P8_29_gpio_pu_pin: pinmux_P8_29_gpio_pu_pin { 129 | pinctrl-single,pins = <0x0E4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 130 | P8_29_gpio_pd_pin: pinmux_P8_29_gpio_pd_pin { 131 | pinctrl-single,pins = <0x0E4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 132 | P8_29_pruout_pin: pinmux_P8_29_pruout_pin { 133 | pinctrl-single,pins = <0x0E4 0x05>; }; /* Mode 5, Pull-Down*/ 134 | P8_29_pruin_pin: pinmux_P8_29_pruin_pin { 135 | pinctrl-single,pins = <0x0E4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 136 | 137 | /* P8_30 (ZCZ ball R6 ) hdmi */ 138 | P8_30_default_pin: pinmux_P8_30_default_pin { 139 | pinctrl-single,pins = <0x0EC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 140 | P8_30_gpio_pin: pinmux_P8_30_gpio_pin { 141 | pinctrl-single,pins = <0x0EC 0x2F>; }; /* Mode 7, RxActive */ 142 | P8_30_gpio_pu_pin: pinmux_P8_30_gpio_pu_pin { 143 | pinctrl-single,pins = <0x0EC 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 144 | P8_30_gpio_pd_pin: pinmux_P8_30_gpio_pd_pin { 145 | pinctrl-single,pins = <0x0EC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 146 | P8_30_pruout_pin: pinmux_P8_30_pruout_pin { 147 | pinctrl-single,pins = <0x0EC 0x05>; }; /* Mode 5, Pull-Down*/ 148 | P8_30_pruin_pin: pinmux_P8_30_pruin_pin { 149 | pinctrl-single,pins = <0x0EC 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 150 | 151 | /* P8_31 (ZCZ ball V4 ) hdmi */ 152 | P8_31_default_pin: pinmux_P8_31_default_pin { 153 | pinctrl-single,pins = <0x0D8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 154 | P8_31_gpio_pin: pinmux_P8_31_gpio_pin { 155 | pinctrl-single,pins = <0x0D8 0x2F>; }; /* Mode 7, RxActive */ 156 | P8_31_gpio_pu_pin: pinmux_P8_31_gpio_pu_pin { 157 | pinctrl-single,pins = <0x0D8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 158 | P8_31_gpio_pd_pin: pinmux_P8_31_gpio_pd_pin { 159 | pinctrl-single,pins = <0x0D8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 160 | P8_31_uart_pin: pinmux_P8_31_uart_pin { 161 | pinctrl-single,pins = <0x0D8 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 162 | 163 | /* P8_32 (ZCZ ball T5 ) hdmi */ 164 | P8_32_default_pin: pinmux_P8_32_default_pin { 165 | pinctrl-single,pins = <0x0DC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 166 | P8_32_gpio_pin: pinmux_P8_32_gpio_pin { 167 | pinctrl-single,pins = <0x0DC 0x2F>; }; /* Mode 7, RxActive */ 168 | P8_32_gpio_pu_pin: pinmux_P8_32_gpio_pu_pin { 169 | pinctrl-single,pins = <0x0DC 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 170 | P8_32_gpio_pd_pin: pinmux_P8_32_gpio_pd_pin { 171 | pinctrl-single,pins = <0x0DC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 172 | P8_32_uart_pin: pinmux_P8_32_uart_pin { 173 | pinctrl-single,pins = <0x0DC 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 174 | /* P8_33 (ZCZ ball V3 ) hdmi */ 175 | P8_33_default_pin: pinmux_P8_33_default_pin { 176 | pinctrl-single,pins = <0x0D4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 177 | P8_33_gpio_pin: pinmux_P8_33_gpio_pin { 178 | pinctrl-single,pins = <0x0D4 0x2F>; }; /* Mode 7, RxActive */ 179 | P8_33_gpio_pu_pin: pinmux_P8_33_gpio_pu_pin { 180 | pinctrl-single,pins = <0x0D4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 181 | P8_33_gpio_pd_pin: pinmux_P8_33_gpio_pd_pin { 182 | pinctrl-single,pins = <0x0D4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 183 | 184 | /* P8_34 (ZCZ ball U4 ) hdmi */ 185 | P8_34_default_pin: pinmux_P8_34_default_pin { 186 | pinctrl-single,pins = <0x0CC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 187 | P8_34_gpio_pin: pinmux_P8_34_gpio_pin { 188 | pinctrl-single,pins = <0x0CC 0x2F>; }; /* Mode 7, RxActive */ 189 | P8_34_gpio_pu_pin: pinmux_P8_34_gpio_pu_pin { 190 | pinctrl-single,pins = <0x0CC 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 191 | P8_34_gpio_pd_pin: pinmux_P8_34_gpio_pd_pin { 192 | pinctrl-single,pins = <0x0CC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 193 | P8_34_pwm_pin: pinmux_P8_34_pwm_pin { 194 | pinctrl-single,pins = <0x0CC 0x22>; }; /* Mode 2, Pull-Down, RxActive */ 195 | 196 | /* P8_35 (ZCZ ball V2 ) hdmi */ 197 | P8_35_default_pin: pinmux_P8_35_default_pin { 198 | pinctrl-single,pins = <0x0D0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 199 | P8_35_gpio_pin: pinmux_P8_35_gpio_pin { 200 | pinctrl-single,pins = <0x0D0 0x2F>; }; /* Mode 7, RxActive */ 201 | P8_35_gpio_pu_pin: pinmux_P8_35_gpio_pu_pin { 202 | pinctrl-single,pins = <0x0D0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 203 | P8_35_gpio_pd_pin: pinmux_P8_35_gpio_pd_pin { 204 | pinctrl-single,pins = <0x0D0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 205 | 206 | /* P8_36 (ZCZ ball U3 ) hdmi */ 207 | P8_36_default_pin: pinmux_P8_36_default_pin { 208 | pinctrl-single,pins = <0x0C8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 209 | P8_36_gpio_pin: pinmux_P8_36_gpio_pin { 210 | pinctrl-single,pins = <0x0C8 0x2F>; }; /* Mode 7, RxActive */ 211 | P8_36_gpio_pu_pin: pinmux_P8_36_gpio_pu_pin { 212 | pinctrl-single,pins = <0x0C8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 213 | P8_36_gpio_pd_pin: pinmux_P8_36_gpio_pd_pin { 214 | pinctrl-single,pins = <0x0C8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 215 | P8_36_pwm_pin: pinmux_P8_36_pwm_pin { 216 | pinctrl-single,pins = <0x0C8 0x22>; }; /* Mode 2, Pull-Down, RxActive */ 217 | 218 | /* P8_37 (ZCZ ball U1 ) hdmi */ 219 | P8_37_default_pin: pinmux_P8_37_default_pin { 220 | pinctrl-single,pins = <0x0C0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 221 | P8_37_gpio_pin: pinmux_P8_37_gpio_pin { 222 | pinctrl-single,pins = <0x0C0 0x2F>; }; /* Mode 7, RxActive */ 223 | P8_37_gpio_pu_pin: pinmux_P8_37_gpio_pu_pin { 224 | pinctrl-single,pins = <0x0C0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 225 | P8_37_gpio_pd_pin: pinmux_P8_37_gpio_pd_pin { 226 | pinctrl-single,pins = <0x0C0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 227 | P8_37_uart_pin: pinmux_P8_37_uart_pin { 228 | pinctrl-single,pins = <0x0C0 0x04>; }; /* Mode 4, Pull-Down*/ 229 | P8_37_pwm_pin: pinmux_P8_37_pwm_pin { 230 | pinctrl-single,pins = <0x0C0 0x02>; }; /* Mode 2, Pull-Down*/ 231 | 232 | 233 | /* P8_38 (ZCZ ball U2 ) hdmi */ 234 | P8_38_default_pin: pinmux_P8_38_default_pin { 235 | pinctrl-single,pins = <0x0C4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 236 | P8_38_gpio_pin: pinmux_P8_38_gpio_pin { 237 | pinctrl-single,pins = <0x0C4 0x2F>; }; /* Mode 7, RxActive */ 238 | P8_38_gpio_pu_pin: pinmux_P8_38_gpio_pu_pin { 239 | pinctrl-single,pins = <0x0C4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 240 | P8_38_gpio_pd_pin: pinmux_P8_38_gpio_pd_pin { 241 | pinctrl-single,pins = <0x0C4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 242 | P8_38_uart_pin: pinmux_P8_38_uart_pin { 243 | pinctrl-single,pins = <0x0C4 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 244 | P8_38_pwm_pin: pinmux_P8_38_pwm_pin { 245 | pinctrl-single,pins = <0x0C4 0x22>; }; /* Mode 2, Pull-Down, RxActive */ 246 | 247 | 248 | /* P8_39 (ZCZ ball T3 ) hdmi */ 249 | P8_39_default_pin: pinmux_P8_39_default_pin { 250 | pinctrl-single,pins = <0x0B8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 251 | P8_39_gpio_pin: pinmux_P8_39_gpio_pin { 252 | pinctrl-single,pins = <0x0B8 0x2F>; }; /* Mode 7, RxActive */ 253 | P8_39_gpio_pu_pin: pinmux_P8_39_gpio_pu_pin { 254 | pinctrl-single,pins = <0x0B8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 255 | P8_39_gpio_pd_pin: pinmux_P8_39_gpio_pd_pin { 256 | pinctrl-single,pins = <0x0B8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 257 | P8_39_pruout_pin: pinmux_P8_39_pruout_pin { 258 | pinctrl-single,pins = <0x0B8 0x05>; }; /* Mode 5, Pull-Down*/ 259 | P8_39_pruin_pin: pinmux_P8_39_pruin_pin { 260 | pinctrl-single,pins = <0x0B8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 261 | 262 | /* P8_40 (ZCZ ball T4 ) hdmi */ 263 | P8_40_default_pin: pinmux_P8_40_default_pin { 264 | pinctrl-single,pins = <0x0BC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 265 | P8_40_gpio_pin: pinmux_P8_40_gpio_pin { 266 | pinctrl-single,pins = <0x0BC 0x2F>; }; /* Mode 7, RxActive */ 267 | P8_40_gpio_pu_pin: pinmux_P8_40_gpio_pu_pin { 268 | pinctrl-single,pins = <0x0BC 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 269 | P8_40_gpio_pd_pin: pinmux_P8_40_gpio_pd_pin { 270 | pinctrl-single,pins = <0x0BC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 271 | P8_40_pruout_pin: pinmux_P8_40_pruout_pin { 272 | pinctrl-single,pins = <0x0BC 0x05>; }; /* Mode 5, Pull-Down*/ 273 | P8_40_pruin_pin: pinmux_P8_40_pruin_pin { 274 | pinctrl-single,pins = <0x0BC 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 275 | 276 | /* P8_41 (ZCZ ball T1 ) hdmi */ 277 | P8_41_default_pin: pinmux_P8_41_default_pin { 278 | pinctrl-single,pins = <0x0B0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 279 | P8_41_gpio_pin: pinmux_P8_41_gpio_pin { 280 | pinctrl-single,pins = <0x0B0 0x2F>; }; /* Mode 7, RxActive */ 281 | P8_41_gpio_pu_pin: pinmux_P8_41_gpio_pu_pin { 282 | pinctrl-single,pins = <0x0B0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 283 | P8_41_gpio_pd_pin: pinmux_P8_41_gpio_pd_pin { 284 | pinctrl-single,pins = <0x0B0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 285 | P8_41_pruout_pin: pinmux_P8_41_pruout_pin { 286 | pinctrl-single,pins = <0x0B0 0x05>; }; /* Mode 5, Pull-Down*/ 287 | P8_41_pruin_pin: pinmux_P8_41_pruin_pin { 288 | pinctrl-single,pins = <0x0B0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 289 | 290 | /* P8_42 (ZCZ ball T2 ) hdmi */ 291 | P8_42_default_pin: pinmux_P8_42_default_pin { 292 | pinctrl-single,pins = <0x0B4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 293 | P8_42_gpio_pin: pinmux_P8_42_gpio_pin { 294 | pinctrl-single,pins = <0x0B4 0x2F>; }; /* Mode 7, RxActive */ 295 | P8_42_gpio_pu_pin: pinmux_P8_42_gpio_pu_pin { 296 | pinctrl-single,pins = <0x0B4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 297 | P8_42_gpio_pd_pin: pinmux_P8_42_gpio_pd_pin { 298 | pinctrl-single,pins = <0x0B4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 299 | P8_42_pruout_pin: pinmux_P8_42_pruout_pin { 300 | pinctrl-single,pins = <0x0B4 0x05>; }; /* Mode 5, Pull-Down*/ 301 | P8_42_pruin_pin: pinmux_P8_42_pruin_pin { 302 | pinctrl-single,pins = <0x0B4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 303 | 304 | /* P8_43 (ZCZ ball R3 ) hdmi */ 305 | P8_43_default_pin: pinmux_P8_43_default_pin { 306 | pinctrl-single,pins = <0x0A8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 307 | P8_43_gpio_pin: pinmux_P8_43_gpio_pin { 308 | pinctrl-single,pins = <0x0A8 0x2F>; }; /* Mode 7, RxActive */ 309 | P8_43_gpio_pu_pin: pinmux_P8_43_gpio_pu_pin { 310 | pinctrl-single,pins = <0x0A8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 311 | P8_43_gpio_pd_pin: pinmux_P8_43_gpio_pd_pin { 312 | pinctrl-single,pins = <0x0A8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 313 | P8_43_pruout_pin: pinmux_P8_43_pruout_pin { 314 | pinctrl-single,pins = <0x0A8 0x05>; }; /* Mode 5, Pull-Down*/ 315 | P8_43_pruin_pin: pinmux_P8_43_pruin_pin { 316 | pinctrl-single,pins = <0x0A8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 317 | P8_43_pwm_pin: pinmux_P8_43_pwm_pin { 318 | pinctrl-single,pins = <0x0A8 0x03>; }; /* Mode 3, Pull-Down */ 319 | 320 | /* P8_44 (ZCZ ball R4 ) hdmi */ 321 | P8_44_default_pin: pinmux_P8_44_default_pin { 322 | pinctrl-single,pins = <0x0AC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 323 | P8_44_gpio_pin: pinmux_P8_44_gpio_pin { 324 | pinctrl-single,pins = <0x0AC 0x2F>; }; /* Mode 7, RxActive */ 325 | P8_44_gpio_pu_pin: pinmux_P8_44_gpio_pu_pin { 326 | pinctrl-single,pins = <0x0AC 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 327 | P8_44_gpio_pd_pin: pinmux_P8_44_gpio_pd_pin { 328 | pinctrl-single,pins = <0x0AC 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 329 | P8_44_pruout_pin: pinmux_P8_44_pruout_pin { 330 | pinctrl-single,pins = <0x0AC 0x05>; }; /* Mode 5, Pull-Down*/ 331 | P8_44_pruin_pin: pinmux_P8_44_pruin_pin { 332 | pinctrl-single,pins = <0x0AC 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 333 | P8_44_pwm_pin: pinmux_P8_44_pwm_pin { 334 | pinctrl-single,pins = <0x0AC 0x23>; }; /* Mode 3, Pull-Down, RxActive */ 335 | 336 | /* P8_45 (ZCZ ball R1 ) hdmi */ 337 | P8_45_default_pin: pinmux_P8_45_default_pin { 338 | pinctrl-single,pins = <0x0A0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 339 | P8_45_gpio_pin: pinmux_P8_45_gpio_pin { 340 | pinctrl-single,pins = <0x0A0 0x2F>; }; /* Mode 7, RxActive */ 341 | P8_45_gpio_pu_pin: pinmux_P8_45_gpio_pu_pin { 342 | pinctrl-single,pins = <0x0A0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 343 | P8_45_gpio_pd_pin: pinmux_P8_45_gpio_pd_pin { 344 | pinctrl-single,pins = <0x0A0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 345 | P8_45_pruout_pin: pinmux_P8_45_pruout_pin { 346 | pinctrl-single,pins = <0x0A0 0x05>; }; /* Mode 5, Pull-Down*/ 347 | P8_45_pruin_pin: pinmux_P8_45_pruin_pin { 348 | pinctrl-single,pins = <0x0A0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 349 | P8_45_pwm_pin: pinmux_P8_45_pwm_pin { 350 | pinctrl-single,pins = <0x0A0 0x03>; }; /* Mode 3, Pull-Down*/ 351 | 352 | /* P8_46 (ZCZ ball R2 ) hdmi */ 353 | P8_46_default_pin: pinmux_P8_46_default_pin { 354 | pinctrl-single,pins = <0x0A4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 355 | P8_46_gpio_pin: pinmux_P8_46_gpio_pin { 356 | pinctrl-single,pins = <0x0A4 0x2F>; }; /* Mode 7, RxActive */ 357 | P8_46_gpio_pu_pin: pinmux_P8_46_gpio_pu_pin { 358 | pinctrl-single,pins = <0x0A4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 359 | P8_46_gpio_pd_pin: pinmux_P8_46_gpio_pd_pin { 360 | pinctrl-single,pins = <0x0A4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 361 | P8_46_pruout_pin: pinmux_P8_46_pruout_pin { 362 | pinctrl-single,pins = <0x0A4 0x05>; }; /* Mode 5, Pull-Down*/ 363 | P8_46_pruin_pin: pinmux_P8_46_pruin_pin { 364 | pinctrl-single,pins = <0x0A4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 365 | P8_46_pwm_pin: pinmux_P8_46_pwm_pin { 366 | pinctrl-single,pins = <0x0A4 0x03>; }; /* Mode 3, Pull-Down*/ 367 | 368 | }; 369 | }; 370 | 371 | 372 | /************************/ 373 | /* Pin Multiplexing */ 374 | /************************/ 375 | 376 | fragment@1 { 377 | target = <&ocp>; 378 | __overlay__ { 379 | 380 | /************************/ 381 | /* P8 Header */ 382 | /************************/ 383 | 384 | 385 | P8_27_pinmux { 386 | compatible = "bone-pinmux-helper"; 387 | status = "okay"; 388 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 389 | pinctrl-0 = <&P8_27_default_pin>; 390 | pinctrl-1 = <&P8_27_gpio_pin>; 391 | pinctrl-2 = <&P8_27_gpio_pu_pin>; 392 | pinctrl-3 = <&P8_27_gpio_pd_pin>; 393 | pinctrl-4 = <&P8_27_pruout_pin>; 394 | pinctrl-5 = <&P8_27_pruin_pin>; 395 | }; 396 | 397 | P8_28_pinmux { 398 | compatible = "bone-pinmux-helper"; 399 | status = "okay"; 400 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 401 | pinctrl-0 = <&P8_28_default_pin>; 402 | pinctrl-1 = <&P8_28_gpio_pin>; 403 | pinctrl-2 = <&P8_28_gpio_pu_pin>; 404 | pinctrl-3 = <&P8_28_gpio_pd_pin>; 405 | pinctrl-4 = <&P8_28_pruout_pin>; 406 | pinctrl-5 = <&P8_28_pruin_pin>; 407 | }; 408 | 409 | P8_29_pinmux { 410 | compatible = "bone-pinmux-helper"; 411 | status = "okay"; 412 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 413 | pinctrl-0 = <&P8_29_default_pin>; 414 | pinctrl-1 = <&P8_29_gpio_pin>; 415 | pinctrl-2 = <&P8_29_gpio_pu_pin>; 416 | pinctrl-3 = <&P8_29_gpio_pd_pin>; 417 | pinctrl-4 = <&P8_29_pruout_pin>; 418 | pinctrl-5 = <&P8_29_pruin_pin>; 419 | }; 420 | 421 | P8_30_pinmux { 422 | compatible = "bone-pinmux-helper"; 423 | status = "okay"; 424 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 425 | pinctrl-0 = <&P8_30_default_pin>; 426 | pinctrl-1 = <&P8_30_gpio_pin>; 427 | pinctrl-2 = <&P8_30_gpio_pu_pin>; 428 | pinctrl-3 = <&P8_30_gpio_pd_pin>; 429 | pinctrl-4 = <&P8_30_pruout_pin>; 430 | pinctrl-5 = <&P8_30_pruin_pin>; 431 | }; 432 | 433 | P8_31_pinmux { 434 | compatible = "bone-pinmux-helper"; 435 | status = "okay"; 436 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","uart"; 437 | pinctrl-0 = <&P8_31_default_pin>; 438 | pinctrl-1 = <&P8_31_gpio_pin>; 439 | pinctrl-2 = <&P8_31_gpio_pu_pin>; 440 | pinctrl-3 = <&P8_31_gpio_pd_pin>; 441 | pinctrl-4 = <&P8_31_uart_pin>; 442 | }; 443 | 444 | P8_32_pinmux { 445 | compatible = "bone-pinmux-helper"; 446 | status = "okay"; 447 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 448 | pinctrl-0 = <&P8_32_default_pin>; 449 | pinctrl-1 = <&P8_32_gpio_pin>; 450 | pinctrl-2 = <&P8_32_gpio_pu_pin>; 451 | pinctrl-3 = <&P8_32_gpio_pd_pin>; 452 | }; 453 | 454 | P8_33_pinmux { 455 | compatible = "bone-pinmux-helper"; 456 | status = "okay"; 457 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 458 | pinctrl-0 = <&P8_33_default_pin>; 459 | pinctrl-1 = <&P8_33_gpio_pin>; 460 | pinctrl-2 = <&P8_33_gpio_pu_pin>; 461 | pinctrl-3 = <&P8_33_gpio_pd_pin>; 462 | }; 463 | 464 | P8_34_pinmux { 465 | compatible = "bone-pinmux-helper"; 466 | status = "okay"; 467 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","pwm"; 468 | pinctrl-0 = <&P8_34_default_pin>; 469 | pinctrl-1 = <&P8_34_gpio_pin>; 470 | pinctrl-2 = <&P8_34_gpio_pu_pin>; 471 | pinctrl-3 = <&P8_34_gpio_pd_pin>; 472 | pinctrl-4 = <&P8_34_pwm_pin>; 473 | }; 474 | 475 | P8_35_pinmux { 476 | compatible = "bone-pinmux-helper"; 477 | status = "okay"; 478 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 479 | pinctrl-0 = <&P8_35_default_pin>; 480 | pinctrl-1 = <&P8_35_gpio_pin>; 481 | pinctrl-2 = <&P8_35_gpio_pu_pin>; 482 | pinctrl-3 = <&P8_35_gpio_pd_pin>; 483 | }; 484 | 485 | P8_36_pinmux { 486 | compatible = "bone-pinmux-helper"; 487 | status = "okay"; 488 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","pwm"; 489 | pinctrl-0 = <&P8_36_default_pin>; 490 | pinctrl-1 = <&P8_36_gpio_pin>; 491 | pinctrl-2 = <&P8_36_gpio_pu_pin>; 492 | pinctrl-3 = <&P8_36_gpio_pd_pin>; 493 | pinctrl-4 = <&P8_36_pwm_pin>; 494 | }; 495 | 496 | P8_37_pinmux { 497 | compatible = "bone-pinmux-helper"; 498 | status = "okay"; 499 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","uart","pwm"; 500 | pinctrl-0 = <&P8_37_default_pin>; 501 | pinctrl-1 = <&P8_37_gpio_pin>; 502 | pinctrl-2 = <&P8_37_gpio_pu_pin>; 503 | pinctrl-3 = <&P8_37_gpio_pd_pin>; 504 | pinctrl-4 = <&P8_37_uart_pin>; 505 | pinctrl-5 = <&P8_37_pwm_pin>; 506 | }; 507 | 508 | P8_38_pinmux { 509 | compatible = "bone-pinmux-helper"; 510 | status = "okay"; 511 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","uart","pwm"; 512 | pinctrl-0 = <&P8_38_default_pin>; 513 | pinctrl-1 = <&P8_38_gpio_pin>; 514 | pinctrl-2 = <&P8_38_gpio_pu_pin>; 515 | pinctrl-3 = <&P8_38_gpio_pd_pin>; 516 | pinctrl-4 = <&P8_38_uart_pin>; 517 | pinctrl-5 = <&P8_38_pwm_pin>; 518 | }; 519 | 520 | P8_39_pinmux { 521 | compatible = "bone-pinmux-helper"; 522 | status = "okay"; 523 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 524 | pinctrl-0 = <&P8_39_default_pin>; 525 | pinctrl-1 = <&P8_39_gpio_pin>; 526 | pinctrl-2 = <&P8_39_gpio_pu_pin>; 527 | pinctrl-3 = <&P8_39_gpio_pd_pin>; 528 | pinctrl-4 = <&P8_39_pruout_pin>; 529 | pinctrl-5 = <&P8_39_pruin_pin>; 530 | }; 531 | 532 | P8_40_pinmux { 533 | compatible = "bone-pinmux-helper"; 534 | status = "okay"; 535 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 536 | pinctrl-0 = <&P8_40_default_pin>; 537 | pinctrl-1 = <&P8_40_gpio_pin>; 538 | pinctrl-2 = <&P8_40_gpio_pu_pin>; 539 | pinctrl-3 = <&P8_40_gpio_pd_pin>; 540 | pinctrl-4 = <&P8_40_pruout_pin>; 541 | pinctrl-5 = <&P8_40_pruin_pin>; 542 | }; 543 | 544 | P8_41_pinmux { 545 | compatible = "bone-pinmux-helper"; 546 | status = "okay"; 547 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 548 | pinctrl-0 = <&P8_41_default_pin>; 549 | pinctrl-1 = <&P8_41_gpio_pin>; 550 | pinctrl-2 = <&P8_41_gpio_pu_pin>; 551 | pinctrl-3 = <&P8_41_gpio_pd_pin>; 552 | pinctrl-4 = <&P8_41_pruout_pin>; 553 | pinctrl-5 = <&P8_41_pruin_pin>; 554 | }; 555 | 556 | P8_42_pinmux { 557 | compatible = "bone-pinmux-helper"; 558 | status = "okay"; 559 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin"; 560 | pinctrl-0 = <&P8_42_default_pin>; 561 | pinctrl-1 = <&P8_42_gpio_pin>; 562 | pinctrl-2 = <&P8_42_gpio_pu_pin>; 563 | pinctrl-3 = <&P8_42_gpio_pd_pin>; 564 | pinctrl-4 = <&P8_42_pruout_pin>; 565 | pinctrl-5 = <&P8_42_pruin_pin>; 566 | }; 567 | 568 | P8_43_pinmux { 569 | compatible = "bone-pinmux-helper"; 570 | status = "okay"; 571 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm"; 572 | pinctrl-0 = <&P8_43_default_pin>; 573 | pinctrl-1 = <&P8_43_gpio_pin>; 574 | pinctrl-2 = <&P8_43_gpio_pu_pin>; 575 | pinctrl-3 = <&P8_43_gpio_pd_pin>; 576 | pinctrl-4 = <&P8_43_pruout_pin>; 577 | pinctrl-5 = <&P8_43_pruin_pin>; 578 | pinctrl-6 = <&P8_43_pwm_pin>; 579 | }; 580 | 581 | P8_44_pinmux { 582 | compatible = "bone-pinmux-helper"; 583 | status = "okay"; 584 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm"; 585 | pinctrl-0 = <&P8_44_default_pin>; 586 | pinctrl-1 = <&P8_44_gpio_pin>; 587 | pinctrl-2 = <&P8_44_gpio_pu_pin>; 588 | pinctrl-3 = <&P8_44_gpio_pd_pin>; 589 | pinctrl-4 = <&P8_44_pruout_pin>; 590 | pinctrl-5 = <&P8_44_pruin_pin>; 591 | pinctrl-6 = <&P8_44_pwm_pin>; 592 | }; 593 | 594 | P8_45_pinmux { 595 | compatible = "bone-pinmux-helper"; 596 | status = "okay"; 597 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm"; 598 | pinctrl-0 = <&P8_45_default_pin>; 599 | pinctrl-1 = <&P8_45_gpio_pin>; 600 | pinctrl-2 = <&P8_45_gpio_pu_pin>; 601 | pinctrl-3 = <&P8_45_gpio_pd_pin>; 602 | pinctrl-4 = <&P8_45_pruout_pin>; 603 | pinctrl-5 = <&P8_45_pruin_pin>; 604 | pinctrl-6 = <&P8_45_pwm_pin>; 605 | }; 606 | 607 | P8_46_pinmux { 608 | compatible = "bone-pinmux-helper"; 609 | status = "okay"; 610 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm"; 611 | pinctrl-0 = <&P8_46_default_pin>; 612 | pinctrl-1 = <&P8_46_gpio_pin>; 613 | pinctrl-2 = <&P8_46_gpio_pu_pin>; 614 | pinctrl-3 = <&P8_46_gpio_pd_pin>; 615 | pinctrl-4 = <&P8_46_pruout_pin>; 616 | pinctrl-5 = <&P8_46_pruin_pin>; 617 | pinctrl-6 = <&P8_46_pwm_pin>; 618 | }; 619 | }; 620 | }; 621 | 622 | fragment@2 { 623 | target = <&ocp>; 624 | __overlay__ { 625 | 626 | // !!!WARNING!!! 627 | // gpio-of-helper &gpio pointers are off-by-one vs. the hardware: 628 | // hardware GPIO bank 0 = &gpio1 629 | cape-universal { 630 | compatible = "gpio-of-helper"; 631 | status = "okay"; 632 | pinctrl-names = "default"; 633 | pinctrl-0 = <>; 634 | 635 | P8_27 { 636 | gpio-name = "P8_27"; 637 | gpio = <&gpio3 22 0>; 638 | input; 639 | dir-changeable; 640 | }; 641 | P8_28 { 642 | gpio-name = "P8_28"; 643 | gpio = <&gpio3 24 0>; 644 | input; 645 | dir-changeable; 646 | }; 647 | P8_29 { 648 | gpio-name = "P8_29"; 649 | gpio = <&gpio3 23 0>; 650 | input; 651 | dir-changeable; 652 | }; 653 | P8_30 { 654 | gpio-name = "P8_30"; 655 | gpio = <&gpio3 25 0>; 656 | input; 657 | dir-changeable; 658 | }; 659 | P8_31 { 660 | gpio-name = "P8_31"; 661 | gpio = <&gpio1 10 0>; 662 | input; 663 | dir-changeable; 664 | }; 665 | P8_32 { 666 | gpio-name = "P8_32"; 667 | gpio = <&gpio1 11 0>; 668 | input; 669 | dir-changeable; 670 | }; 671 | P8_33 { 672 | gpio-name = "P8_33"; 673 | gpio = <&gpio1 9 0>; 674 | input; 675 | dir-changeable; 676 | }; 677 | P8_34 { 678 | gpio-name = "P8_34"; 679 | gpio = <&gpio3 17 0>; 680 | input; 681 | dir-changeable; 682 | }; 683 | P8_35 { 684 | gpio-name = "P8_35"; 685 | gpio = <&gpio1 8 0>; 686 | input; 687 | dir-changeable; 688 | }; 689 | P8_36 { 690 | gpio-name = "P8_36"; 691 | gpio = <&gpio3 16 0>; 692 | input; 693 | dir-changeable; 694 | }; 695 | P8_37 { 696 | gpio-name = "P8_37"; 697 | gpio = <&gpio3 14 0>; 698 | input; 699 | dir-changeable; 700 | }; 701 | P8_38 { 702 | gpio-name = "P8_38"; 703 | gpio = <&gpio3 15 0>; 704 | input; 705 | dir-changeable; 706 | }; 707 | P8_39 { 708 | gpio-name = "P8_39"; 709 | gpio = <&gpio3 12 0>; 710 | input; 711 | dir-changeable; 712 | }; 713 | P8_40 { 714 | gpio-name = "P8_40"; 715 | gpio = <&gpio3 13 0>; 716 | input; 717 | dir-changeable; 718 | }; 719 | P8_41 { 720 | gpio-name = "P8_41"; 721 | gpio = <&gpio3 10 0>; 722 | input; 723 | dir-changeable; 724 | }; 725 | P8_42 { 726 | gpio-name = "P8_42"; 727 | gpio = <&gpio3 11 0>; 728 | input; 729 | dir-changeable; 730 | }; 731 | P8_43 { 732 | gpio-name = "P8_43"; 733 | gpio = <&gpio3 8 0>; 734 | input; 735 | dir-changeable; 736 | }; 737 | P8_44 { 738 | gpio-name = "P8_44"; 739 | gpio = <&gpio3 9 0>; 740 | input; 741 | dir-changeable; 742 | }; 743 | P8_45 { 744 | gpio-name = "P8_45"; 745 | gpio = <&gpio3 6 0>; 746 | input; 747 | dir-changeable; 748 | }; 749 | P8_46 { 750 | gpio-name = "P8_46"; 751 | gpio = <&gpio3 7 0>; 752 | input; 753 | dir-changeable; 754 | }; 755 | 756 | }; 757 | }; 758 | }; 759 | 760 | /************************/ 761 | /* UARTs */ 762 | /************************/ 763 | 764 | fragment@12 { 765 | target = <&uart6>; /* really uart5 */ 766 | __overlay__ { 767 | status = "okay"; 768 | pinctrl-names = "default"; 769 | pinctrl-0 = <>; 770 | }; 771 | }; 772 | }; 773 | -------------------------------------------------------------------------------- /cape-universaln-00A0.dts: -------------------------------------------------------------------------------- 1 | // Copyright 2013 2 | // Charles Steinkuehler 3 | // 4 | // This program is free software; you can redistribute it and/or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation; either version 2 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with this program; if not, write to the Free Software 16 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 | 18 | /dts-v1/; 19 | /plugin/; 20 | 21 | / { 22 | compatible = "ti,beaglebone", "ti,beaglebone-black"; 23 | 24 | /* identification */ 25 | part-number = "cape-bone-universaln"; 26 | version = "00A0"; 27 | 28 | /* state the resources this cape uses */ 29 | exclusive-use = 30 | 31 | /* "P8.1", GND */ 32 | /* "P8.2", GND */ 33 | /* "P8.3", emmc */ 34 | /* "P8.4", emmc */ 35 | /* "P8.5", emmc */ 36 | /* "P8.6", emmc */ 37 | "P8.7", 38 | "P8.8", 39 | "P8.9", 40 | "P8.10", 41 | "P8.11", 42 | "P8.12", 43 | "P8.13", 44 | "P8.14", 45 | "P8.15", 46 | "P8.16", 47 | "P8.17", 48 | "P8.18", 49 | "P8.19", 50 | /* "P8.20", emmc */ 51 | /* "P8.21", emmc */ 52 | /* "P8.22", emmc */ 53 | /* "P8.23", emmc */ 54 | /* "P8.24", emmc */ 55 | /* "P8.25", emmc */ 56 | "P8.26", 57 | /* "P8.27", hdmi */ 58 | /* "P8.28", hdmi */ 59 | /* "P8.29", hdmi */ 60 | /* "P8.30", hdmi */ 61 | /* "P8.31", hdmi */ 62 | /* "P8.32", hdmi */ 63 | /* "P8.33", hdmi */ 64 | /* "P8.34", hdmi */ 65 | /* "P8.35", hdmi */ 66 | /* "P8.36", hdmi */ 67 | /* "P8.37", hdmi */ 68 | /* "P8.38", hdmi */ 69 | /* "P8.39", hdmi */ 70 | /* "P8.40", hdmi */ 71 | /* "P8.41", hdmi */ 72 | /* "P8.42", hdmi */ 73 | /* "P8.43", hdmi */ 74 | /* "P8.44", hdmi */ 75 | /* "P8.45", hdmi */ 76 | /* "P8.46", hdmi */ 77 | 78 | /* "P9.1", GND */ 79 | /* "P9.2", GND */ 80 | /* "P9.3", 3.3V */ 81 | /* "P9.4", 3.3V */ 82 | /* "P9.5", VDD_5V */ 83 | /* "P9.6", VDD_5V */ 84 | /* "P9.7", SYS_5V */ 85 | /* "P9.8", SYS_5V */ 86 | /* "P9.9", PWR_BUT */ 87 | /* "P9.10", RESETn */ 88 | "P9.11", 89 | "P9.12", 90 | "P9.13", 91 | "P9.14", 92 | "P9.15", 93 | "P9.16", 94 | "P9.17", 95 | "P9.18", 96 | /* "P9.19", I2C */ 97 | /* "P9.20", I2C */ 98 | "P9.21", 99 | "P9.22", 100 | "P9.23", 101 | "P9.24", 102 | /* "P9.25", Audio */ 103 | "P9.26", 104 | "P9.27", 105 | /* "P9.28", Audio */ 106 | /* "P9.29", Audio */ 107 | "P9.30", 108 | /* "P9.31", Audio */ 109 | /* "P9.32", VADC */ 110 | /* "P9.33", AIN4 */ 111 | /* "P9.34", AGND */ 112 | /* "P9.35", AIN6 */ 113 | /* "P9.36", AIN5 */ 114 | /* "P9.37", AIN2 */ 115 | /* "P9.38", AIN3 */ 116 | /* "P9.39", AIN0 */ 117 | /* "P9.40", AIN1 */ 118 | "P9.41", 119 | "P9.41.1", 120 | "P9.42", 121 | "P9.42.1", 122 | /* "P9.43", GND */ 123 | /* "P9.44", GND */ 124 | /* "P9.45", GND */ 125 | /* "P9.46", GND */ 126 | 127 | "uart1", 128 | "uart2", 129 | "uart4", 130 | // "uart5", /* Conflicts with HDMI */ 131 | 132 | "ehrpwm0A", 133 | "ehrpwm0B", 134 | "ehrpwm1A", 135 | "ehrpwm1B", 136 | "ehrpwm2A", 137 | "ehrpwm2B", 138 | 139 | // "epwmss0", 140 | // "ehrpwm0", 141 | // "ecap0", 142 | // "epwmss1", 143 | // "ehrpwm1", 144 | // "epwmss2", 145 | // "ehrpwm2", 146 | // "ecap2", 147 | 148 | "i2c1", 149 | "spi1", 150 | "spi0", 151 | "dcan0", 152 | "dcan1", 153 | 154 | "pru0", 155 | "pru1", 156 | "pruss"; 157 | 158 | fragment@0 { 159 | target = <&am33xx_pinmux>; 160 | __overlay__ { 161 | 162 | /************************/ 163 | /* P8 Header */ 164 | /************************/ 165 | 166 | /* P8_01 GND */ 167 | /* P8_02 GND */ 168 | /* P8_03 (ZCZ ball R9 ) emmc */ 169 | /* P8_04 (ZCZ ball T9 ) emmc */ 170 | /* P8_05 (ZCZ ball R8 ) emmc */ 171 | /* P8_06 (ZCZ ball T8 ) emmc */ 172 | 173 | /* P8_07 (ZCZ ball R7 ) */ 174 | P8_07_default_pin: pinmux_P8_07_default_pin { 175 | pinctrl-single,pins = <0x090 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 176 | P8_07_gpio_pin: pinmux_P8_07_gpio_pin { 177 | pinctrl-single,pins = <0x090 0x2F>; }; /* Mode 7, RxActive */ 178 | P8_07_gpio_pu_pin: pinmux_P8_07_gpio_pu_pin { 179 | pinctrl-single,pins = <0x090 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 180 | P8_07_gpio_pd_pin: pinmux_P8_07_gpio_pd_pin { 181 | pinctrl-single,pins = <0x090 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 182 | P8_07_timer_pin: pinmux_P8_07_timer_pin { 183 | pinctrl-single,pins = <0x090 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 184 | 185 | /* P8_08 (ZCZ ball T7 ) */ 186 | P8_08_default_pin: pinmux_P8_08_default_pin { 187 | pinctrl-single,pins = <0x094 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 188 | P8_08_gpio_pin: pinmux_P8_08_gpio_pin { 189 | pinctrl-single,pins = <0x094 0x2F>; }; /* Mode 7, RxActive */ 190 | P8_08_gpio_pu_pin: pinmux_P8_08_gpio_pu_pin { 191 | pinctrl-single,pins = <0x094 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 192 | P8_08_gpio_pd_pin: pinmux_P8_08_gpio_pd_pin { 193 | pinctrl-single,pins = <0x094 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 194 | P8_08_timer_pin: pinmux_P8_08_timer_pin { 195 | pinctrl-single,pins = <0x094 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 196 | 197 | /* P8_09 (ZCZ ball T6 ) */ 198 | P8_09_default_pin: pinmux_P8_09_default_pin { 199 | pinctrl-single,pins = <0x09c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 200 | P8_09_gpio_pin: pinmux_P8_09_gpio_pin { 201 | pinctrl-single,pins = <0x09c 0x2F>; }; /* Mode 7, RxActive */ 202 | P8_09_gpio_pu_pin: pinmux_P8_09_gpio_pu_pin { 203 | pinctrl-single,pins = <0x09c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 204 | P8_09_gpio_pd_pin: pinmux_P8_09_gpio_pd_pin { 205 | pinctrl-single,pins = <0x09c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 206 | P8_09_timer_pin: pinmux_P8_09_timer_pin { 207 | pinctrl-single,pins = <0x09c 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 208 | 209 | /* P8_10 (ZCZ ball U6 ) */ 210 | P8_10_default_pin: pinmux_P8_10_default_pin { 211 | pinctrl-single,pins = <0x098 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 212 | P8_10_gpio_pin: pinmux_P8_10_gpio_pin { 213 | pinctrl-single,pins = <0x098 0x2F>; }; /* Mode 7, RxActive */ 214 | P8_10_gpio_pu_pin: pinmux_P8_10_gpio_pu_pin { 215 | pinctrl-single,pins = <0x098 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 216 | P8_10_gpio_pd_pin: pinmux_P8_10_gpio_pd_pin { 217 | pinctrl-single,pins = <0x098 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 218 | P8_10_timer_pin: pinmux_P8_10_timer_pin { 219 | pinctrl-single,pins = <0x098 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 220 | 221 | /* P8_11 (ZCZ ball R12) */ 222 | P8_11_default_pin: pinmux_P8_11_default_pin { 223 | pinctrl-single,pins = <0x034 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 224 | P8_11_gpio_pin: pinmux_P8_11_gpio_pin { 225 | pinctrl-single,pins = <0x034 0x2F>; }; /* Mode 7, RxActive */ 226 | P8_11_gpio_pu_pin: pinmux_P8_11_gpio_pu_pin { 227 | pinctrl-single,pins = <0x034 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 228 | P8_11_gpio_pd_pin: pinmux_P8_11_gpio_pd_pin { 229 | pinctrl-single,pins = <0x034 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 230 | P8_11_pruout_pin: pinmux_P8_11_pruout_pin { 231 | pinctrl-single,pins = <0x034 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 232 | P8_11_qep_pin: pinmux_P8_11_qep_pin { 233 | pinctrl-single,pins = <0x034 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 234 | 235 | /* P8_12 (ZCZ ball T12) */ 236 | P8_12_default_pin: pinmux_P8_12_default_pin { 237 | pinctrl-single,pins = <0x030 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 238 | P8_12_gpio_pin: pinmux_P8_12_gpio_pin { 239 | pinctrl-single,pins = <0x030 0x2F>; }; /* Mode 7, RxActive */ 240 | P8_12_gpio_pu_pin: pinmux_P8_12_gpio_pu_pin { 241 | pinctrl-single,pins = <0x030 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 242 | P8_12_gpio_pd_pin: pinmux_P8_12_gpio_pd_pin { 243 | pinctrl-single,pins = <0x030 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 244 | P8_12_pruout_pin: pinmux_P8_12_pruout_pin { 245 | pinctrl-single,pins = <0x030 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 246 | P8_12_qep_pin: pinmux_P8_12_qep_pin { 247 | pinctrl-single,pins = <0x030 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 248 | 249 | /* P8_13 (ZCZ ball T10) */ 250 | P8_13_default_pin: pinmux_P8_13_default_pin { 251 | pinctrl-single,pins = <0x024 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 252 | P8_13_gpio_pin: pinmux_P8_13_gpio_pin { 253 | pinctrl-single,pins = <0x024 0x2F>; }; /* Mode 7, RxActive */ 254 | P8_13_gpio_pu_pin: pinmux_P8_13_gpio_pu_pin { 255 | pinctrl-single,pins = <0x024 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 256 | P8_13_gpio_pd_pin: pinmux_P8_13_gpio_pd_pin { 257 | pinctrl-single,pins = <0x024 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 258 | P8_13_pwm_pin: pinmux_P8_13_pwm_pin { 259 | pinctrl-single,pins = <0x024 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 260 | 261 | /* P8_14 (ZCZ ball T11) */ 262 | P8_14_default_pin: pinmux_P8_14_default_pin { 263 | pinctrl-single,pins = <0x028 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 264 | P8_14_gpio_pin: pinmux_P8_14_gpio_pin { 265 | pinctrl-single,pins = <0x028 0x2F>; }; /* Mode 7, RxActive */ 266 | P8_14_gpio_pu_pin: pinmux_P8_14_gpio_pu_pin { 267 | pinctrl-single,pins = <0x028 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 268 | P8_14_gpio_pd_pin: pinmux_P8_14_gpio_pd_pin { 269 | pinctrl-single,pins = <0x028 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 270 | P8_14_pwm_pin: pinmux_P8_14_pwm_pin { 271 | pinctrl-single,pins = <0x028 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 272 | 273 | /* P8_15 (ZCZ ball U13) */ 274 | P8_15_default_pin: pinmux_P8_15_default_pin { 275 | pinctrl-single,pins = <0x03c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 276 | P8_15_gpio_pin: pinmux_P8_15_gpio_pin { 277 | pinctrl-single,pins = <0x03c 0x2F>; }; /* Mode 7, RxActive */ 278 | P8_15_gpio_pu_pin: pinmux_P8_15_gpio_pu_pin { 279 | pinctrl-single,pins = <0x03c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 280 | P8_15_gpio_pd_pin: pinmux_P8_15_gpio_pd_pin { 281 | pinctrl-single,pins = <0x03c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 282 | P8_15_pruin_pin: pinmux_P8_15_pruin_pin { 283 | pinctrl-single,pins = <0x03c 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 284 | P8_15_pru_ecap_pin: pinmux_P8_15_pru_ecap_pin { 285 | pinctrl-single,pins = <0x03c 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 286 | P8_15_qep_pin: pinmux_P8_15_qep_pin { 287 | pinctrl-single,pins = <0x03c 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 288 | 289 | /* P8_16 (ZCZ ball V13) */ 290 | P8_16_default_pin: pinmux_P8_16_default_pin { 291 | pinctrl-single,pins = <0x038 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 292 | P8_16_gpio_pin: pinmux_P8_16_gpio_pin { 293 | pinctrl-single,pins = <0x038 0x2F>; }; /* Mode 7, RxActive */ 294 | P8_16_gpio_pu_pin: pinmux_P8_16_gpio_pu_pin { 295 | pinctrl-single,pins = <0x038 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 296 | P8_16_gpio_pd_pin: pinmux_P8_16_gpio_pd_pin { 297 | pinctrl-single,pins = <0x038 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 298 | P8_16_pruin_pin: pinmux_P8_16_pruin_pin { 299 | pinctrl-single,pins = <0x038 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 300 | P8_16_qep_pin: pinmux_P8_16_qep_pin { 301 | pinctrl-single,pins = <0x038 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 302 | 303 | /* P8_17 (ZCZ ball U12) */ 304 | P8_17_default_pin: pinmux_P8_17_default_pin { 305 | pinctrl-single,pins = <0x02c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 306 | P8_17_gpio_pin: pinmux_P8_17_gpio_pin { 307 | pinctrl-single,pins = <0x02c 0x2F>; }; /* Mode 7, RxActive */ 308 | P8_17_gpio_pu_pin: pinmux_P8_17_gpio_pu_pin { 309 | pinctrl-single,pins = <0x02c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 310 | P8_17_gpio_pd_pin: pinmux_P8_17_gpio_pd_pin { 311 | pinctrl-single,pins = <0x02c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 312 | P8_17_pwm_pin: pinmux_P8_17_pwm_pin { 313 | pinctrl-single,pins = <0x02c 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 314 | 315 | /* P8_18 (ZCZ ball V12) */ 316 | P8_18_default_pin: pinmux_P8_18_default_pin { 317 | pinctrl-single,pins = <0x08c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 318 | P8_18_gpio_pin: pinmux_P8_18_gpio_pin { 319 | pinctrl-single,pins = <0x08c 0x2F>; }; /* Mode 7, RxActive */ 320 | P8_18_gpio_pu_pin: pinmux_P8_18_gpio_pu_pin { 321 | pinctrl-single,pins = <0x08c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 322 | P8_18_gpio_pd_pin: pinmux_P8_18_gpio_pd_pin { 323 | pinctrl-single,pins = <0x08c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 324 | 325 | /* P8_19 (ZCZ ball U10) */ 326 | P8_19_default_pin: pinmux_P8_19_default_pin { 327 | pinctrl-single,pins = <0x020 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 328 | P8_19_gpio_pin: pinmux_P8_19_gpio_pin { 329 | pinctrl-single,pins = <0x020 0x2F>; }; /* Mode 7, RxActive */ 330 | P8_19_gpio_pu_pin: pinmux_P8_19_gpio_pu_pin { 331 | pinctrl-single,pins = <0x020 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 332 | P8_19_gpio_pd_pin: pinmux_P8_19_gpio_pd_pin { 333 | pinctrl-single,pins = <0x020 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 334 | P8_19_pwm_pin: pinmux_P8_19_pwm_pin { 335 | pinctrl-single,pins = <0x020 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 336 | 337 | /* P8_20 (ZCZ ball V9 ) emmc */ 338 | /* P8_21 (ZCZ ball U9 ) emmc */ 339 | /* P8_22 (ZCZ ball V8 ) emmc */ 340 | /* P8_23 (ZCZ ball U8 ) emmc */ 341 | /* P8_24 (ZCZ ball V7 ) emmc */ 342 | /* P8_25 (ZCZ ball U7 ) emmc */ 343 | 344 | /* P8_26 (ZCZ ball V6 ) */ 345 | P8_26_default_pin: pinmux_P8_26_default_pin { 346 | pinctrl-single,pins = <0x07c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 347 | P8_26_gpio_pin: pinmux_P8_26_gpio_pin { 348 | pinctrl-single,pins = <0x07c 0x2F>; }; /* Mode 7, RxActive */ 349 | P8_26_gpio_pu_pin: pinmux_P8_26_gpio_pu_pin { 350 | pinctrl-single,pins = <0x07c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 351 | P8_26_gpio_pd_pin: pinmux_P8_26_gpio_pd_pin { 352 | pinctrl-single,pins = <0x07c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 353 | 354 | /* P8_27 (ZCZ ball U5 ) hdmi */ 355 | /* P8_28 (ZCZ ball V5 ) hdmi */ 356 | /* P8_29 (ZCZ ball R5 ) hdmi */ 357 | /* P8_30 (ZCZ ball R6 ) hdmi */ 358 | /* P8_31 (ZCZ ball V4 ) hdmi */ 359 | /* P8_32 (ZCZ ball T5 ) hdmi */ 360 | /* P8_33 (ZCZ ball V3 ) hdmi */ 361 | /* P8_34 (ZCZ ball U4 ) hdmi */ 362 | /* P8_35 (ZCZ ball V2 ) hdmi */ 363 | /* P8_36 (ZCZ ball U3 ) hdmi */ 364 | /* P8_37 (ZCZ ball U1 ) hdmi */ 365 | /* P8_38 (ZCZ ball U2 ) hdmi */ 366 | /* P8_39 (ZCZ ball T3 ) hdmi */ 367 | /* P8_40 (ZCZ ball T4 ) hdmi */ 368 | /* P8_41 (ZCZ ball T1 ) hdmi */ 369 | /* P8_42 (ZCZ ball T2 ) hdmi */ 370 | /* P8_43 (ZCZ ball R3 ) hdmi */ 371 | /* P8_44 (ZCZ ball R4 ) hdmi */ 372 | /* P8_45 (ZCZ ball R1 ) hdmi */ 373 | /* P8_46 (ZCZ ball R2 ) hdmi */ 374 | 375 | 376 | /************************/ 377 | /* P9 Header */ 378 | /************************/ 379 | 380 | /* P9_01 GND */ 381 | /* P9_02 GND */ 382 | /* P9_03 3.3V */ 383 | /* P9_04 3.3V */ 384 | /* P9_05 VDD_5V */ 385 | /* P9_06 VDD_5V */ 386 | /* P9_07 SYS_5V */ 387 | /* P9_08 SYS_5V */ 388 | /* P9_09 PWR_BUT */ 389 | /* P9_10 (ZCZ ball A10) RESETn */ 390 | 391 | /* P9_11 (ZCZ ball T17) */ 392 | P9_11_default_pin: pinmux_P9_11_default_pin { 393 | pinctrl-single,pins = <0x070 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 394 | P9_11_gpio_pin: pinmux_P9_11_gpio_pin { 395 | pinctrl-single,pins = <0x070 0x2F>; }; /* Mode 7, RxActive */ 396 | P9_11_gpio_pu_pin: pinmux_P9_11_gpio_pu_pin { 397 | pinctrl-single,pins = <0x070 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 398 | P9_11_gpio_pd_pin: pinmux_P9_11_gpio_pd_pin { 399 | pinctrl-single,pins = <0x070 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 400 | P9_11_uart_pin: pinmux_P9_11_uart_pin { 401 | pinctrl-single,pins = <0x070 0x36>; }; /* Mode 6, Pull-Up, RxActive */ 402 | 403 | /* P9_12 (ZCZ ball U18) */ 404 | P9_12_default_pin: pinmux_P9_12_default_pin { 405 | pinctrl-single,pins = <0x078 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 406 | P9_12_gpio_pin: pinmux_P9_12_gpio_pin { 407 | pinctrl-single,pins = <0x078 0x2F>; }; /* Mode 7, RxActive */ 408 | P9_12_gpio_pu_pin: pinmux_P9_12_gpio_pu_pin { 409 | pinctrl-single,pins = <0x078 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 410 | P9_12_gpio_pd_pin: pinmux_P9_12_gpio_pd_pin { 411 | pinctrl-single,pins = <0x078 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 412 | 413 | /* P9_13 (ZCZ ball U17) */ 414 | P9_13_default_pin: pinmux_P9_13_default_pin { 415 | pinctrl-single,pins = <0x074 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 416 | P9_13_gpio_pin: pinmux_P9_13_gpio_pin { 417 | pinctrl-single,pins = <0x074 0x2F>; }; /* Mode 7, RxActive */ 418 | P9_13_gpio_pu_pin: pinmux_P9_13_gpio_pu_pin { 419 | pinctrl-single,pins = <0x074 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 420 | P9_13_gpio_pd_pin: pinmux_P9_13_gpio_pd_pin { 421 | pinctrl-single,pins = <0x074 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 422 | P9_13_uart_pin: pinmux_P9_13_uart_pin { 423 | pinctrl-single,pins = <0x074 0x36>; }; /* Mode 6, Pull-Up, RxActive */ 424 | 425 | /* P9_14 (ZCZ ball U14) */ 426 | P9_14_default_pin: pinmux_P9_14_default_pin { 427 | pinctrl-single,pins = <0x048 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 428 | P9_14_gpio_pin: pinmux_P9_14_gpio_pin { 429 | pinctrl-single,pins = <0x048 0x2F>; }; /* Mode 7, RxActive */ 430 | P9_14_gpio_pu_pin: pinmux_P9_14_gpio_pu_pin { 431 | pinctrl-single,pins = <0x048 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 432 | P9_14_gpio_pd_pin: pinmux_P9_14_gpio_pd_pin { 433 | pinctrl-single,pins = <0x048 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 434 | P9_14_pwm_pin: pinmux_P9_14_pwm_pin { 435 | pinctrl-single,pins = <0x048 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 436 | 437 | /* P9_15 (ZCZ ball R13) */ 438 | P9_15_default_pin: pinmux_P9_15_default_pin { 439 | pinctrl-single,pins = <0x040 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 440 | P9_15_gpio_pin: pinmux_P9_15_gpio_pin { 441 | pinctrl-single,pins = <0x040 0x2F>; }; /* Mode 7, RxActive */ 442 | P9_15_gpio_pu_pin: pinmux_P9_15_gpio_pu_pin { 443 | pinctrl-single,pins = <0x040 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 444 | P9_15_gpio_pd_pin: pinmux_P9_15_gpio_pd_pin { 445 | pinctrl-single,pins = <0x040 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 446 | P9_15_pwm_pin: pinmux_P9_15_pwm_pin { 447 | pinctrl-single,pins = <0x040 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 448 | 449 | /* P9_16 (ZCZ ball T14) */ 450 | P9_16_default_pin: pinmux_P9_16_default_pin { 451 | pinctrl-single,pins = <0x04c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 452 | P9_16_gpio_pin: pinmux_P9_16_gpio_pin { 453 | pinctrl-single,pins = <0x04c 0x2F>; }; /* Mode 7, RxActive */ 454 | P9_16_gpio_pu_pin: pinmux_P9_16_gpio_pu_pin { 455 | pinctrl-single,pins = <0x04c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 456 | P9_16_gpio_pd_pin: pinmux_P9_16_gpio_pd_pin { 457 | pinctrl-single,pins = <0x04c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 458 | P9_16_pwm_pin: pinmux_P9_16_pwm_pin { 459 | pinctrl-single,pins = <0x04c 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 460 | 461 | /* P9_17 (ZCZ ball A16) */ 462 | P9_17_default_pin: pinmux_P9_17_default_pin { 463 | pinctrl-single,pins = <0x15c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 464 | P9_17_gpio_pin: pinmux_P9_17_gpio_pin { 465 | pinctrl-single,pins = <0x15c 0x2F>; }; /* Mode 7, RxActive */ 466 | P9_17_gpio_pu_pin: pinmux_P9_17_gpio_pu_pin { 467 | pinctrl-single,pins = <0x15c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 468 | P9_17_gpio_pd_pin: pinmux_P9_17_gpio_pd_pin { 469 | pinctrl-single,pins = <0x15c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 470 | P9_17_spi_pin: pinmux_P9_17_spi_pin { 471 | pinctrl-single,pins = <0x15c 0x30>; }; /* Mode 0, Pull-Up, RxActive */ 472 | P9_17_i2c_pin: pinmux_P9_17_i2c_pin { 473 | pinctrl-single,pins = <0x15c 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 474 | P9_17_pwm_pin: pinmux_P9_17_pwm_pin { 475 | pinctrl-single,pins = <0x15c 0x33>; }; /* Mode 3, Pull-Up, RxActive */ 476 | P9_17_pru_uart_pin: pinmux_P9_17_pru_uart_pin { 477 | pinctrl-single,pins = <0x15c 0x34>; }; /* Mode 4, Pull-Up, RxActive */ 478 | 479 | /* P9_18 (ZCZ ball B16) */ 480 | P9_18_default_pin: pinmux_P9_18_default_pin { 481 | pinctrl-single,pins = <0x158 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 482 | P9_18_gpio_pin: pinmux_P9_18_gpio_pin { 483 | pinctrl-single,pins = <0x158 0x2F>; }; /* Mode 7, RxActive */ 484 | P9_18_gpio_pu_pin: pinmux_P9_18_gpio_pu_pin { 485 | pinctrl-single,pins = <0x158 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 486 | P9_18_gpio_pd_pin: pinmux_P9_18_gpio_pd_pin { 487 | pinctrl-single,pins = <0x158 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 488 | P9_18_spi_pin: pinmux_P9_18_spi_pin { 489 | pinctrl-single,pins = <0x158 0x30>; }; /* Mode 0, Pull-Up, RxActive */ 490 | P9_18_i2c_pin: pinmux_P9_18_i2c_pin { 491 | pinctrl-single,pins = <0x158 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 492 | P9_18_pwm_pin: pinmux_P9_18_pwm_pin { 493 | pinctrl-single,pins = <0x158 0x33>; }; /* Mode 3, Pull-Up, RxActive */ 494 | P9_18_pru_uart_pin: pinmux_P9_18_pru_uart_pin { 495 | pinctrl-single,pins = <0x158 0x34>; }; /* Mode 4, Pull-Up, RxActive */ 496 | 497 | // Leave the cape I2C EEPROM bus alone 498 | /* P9_19 (ZCZ ball D17) I2C */ 499 | /* P9_20 (ZCZ ball D18) I2C */ 500 | 501 | /* P9_21 (ZCZ ball B17) */ 502 | P9_21_default_pin: pinmux_P9_21_default_pin { 503 | pinctrl-single,pins = <0x154 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 504 | P9_21_gpio_pin: pinmux_P9_21_gpio_pin { 505 | pinctrl-single,pins = <0x154 0x2F>; }; /* Mode 7, RxActive */ 506 | P9_21_gpio_pu_pin: pinmux_P9_21_gpio_pu_pin { 507 | pinctrl-single,pins = <0x154 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 508 | P9_21_gpio_pd_pin: pinmux_P9_21_gpio_pd_pin { 509 | pinctrl-single,pins = <0x154 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 510 | P9_21_spi_pin: pinmux_P9_21_spi_pin { 511 | pinctrl-single,pins = <0x154 0x30>; }; /* Mode 0, Pull-Up, RxActive */ 512 | P9_21_uart_pin: pinmux_P9_21_uart_pin { 513 | pinctrl-single,pins = <0x154 0x31>; }; /* Mode 1, Pull-Up, RxActive */ 514 | P9_21_i2c_pin: pinmux_P9_21_i2c_pin { 515 | pinctrl-single,pins = <0x154 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 516 | P9_21_pwm_pin: pinmux_P9_21_pwm_pin { 517 | pinctrl-single,pins = <0x154 0x33>; }; /* Mode 3, Pull-Up, RxActive */ 518 | P9_21_pru_uart_pin: pinmux_P9_21_pru_uart_pin { 519 | pinctrl-single,pins = <0x154 0x34>; }; /* Mode 4, Pull-Up, RxActive */ 520 | 521 | /* P9_22 (ZCZ ball A17) */ 522 | P9_22_default_pin: pinmux_P9_22_default_pin { 523 | pinctrl-single,pins = <0x150 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 524 | P9_22_gpio_pin: pinmux_P9_22_gpio_pin { 525 | pinctrl-single,pins = <0x150 0x2F>; }; /* Mode 7, RxActive */ 526 | P9_22_gpio_pu_pin: pinmux_P9_22_gpio_pu_pin { 527 | pinctrl-single,pins = <0x150 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 528 | P9_22_gpio_pd_pin: pinmux_P9_22_gpio_pd_pin { 529 | pinctrl-single,pins = <0x150 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 530 | P9_22_spi_pin: pinmux_P9_22_spi_pin { 531 | pinctrl-single,pins = <0x150 0x30>; }; /* Mode 0, Pull-Up, RxActive */ 532 | P9_22_uart_pin: pinmux_P9_22_uart_pin { 533 | pinctrl-single,pins = <0x150 0x31>; }; /* Mode 1, Pull-Up, RxActive */ 534 | P9_22_i2c_pin: pinmux_P9_22_i2c_pin { 535 | pinctrl-single,pins = <0x150 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 536 | P9_22_pwm_pin: pinmux_P9_22_pwm_pin { 537 | pinctrl-single,pins = <0x150 0x33>; }; /* Mode 3, Pull-Up, RxActive */ 538 | P9_22_pru_uart_pin: pinmux_P9_22_pru_uart_pin { 539 | pinctrl-single,pins = <0x150 0x34>; }; /* Mode 4, Pull-Up, RxActive */ 540 | 541 | /* P9_23 (ZCZ ball V14) */ 542 | P9_23_default_pin: pinmux_P9_23_default_pin { 543 | pinctrl-single,pins = <0x044 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 544 | P9_23_gpio_pin: pinmux_P9_23_gpio_pin { 545 | pinctrl-single,pins = <0x044 0x2F>; }; /* Mode 7, RxActive */ 546 | P9_23_gpio_pu_pin: pinmux_P9_23_gpio_pu_pin { 547 | pinctrl-single,pins = <0x044 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 548 | P9_23_gpio_pd_pin: pinmux_P9_23_gpio_pd_pin { 549 | pinctrl-single,pins = <0x044 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 550 | P9_23_pwm_pin: pinmux_P9_23_pwm_pin { 551 | pinctrl-single,pins = <0x044 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 552 | 553 | /* P9_24 (ZCZ ball D15) */ 554 | P9_24_default_pin: pinmux_P9_24_default_pin { 555 | pinctrl-single,pins = <0x184 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 556 | P9_24_gpio_pin: pinmux_P9_24_gpio_pin { 557 | pinctrl-single,pins = <0x184 0x2F>; }; /* Mode 7, RxActive */ 558 | P9_24_gpio_pu_pin: pinmux_P9_24_gpio_pu_pin { 559 | pinctrl-single,pins = <0x184 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 560 | P9_24_gpio_pd_pin: pinmux_P9_24_gpio_pd_pin { 561 | pinctrl-single,pins = <0x184 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 562 | P9_24_uart_pin: pinmux_P9_24_uart_pin { 563 | pinctrl-single,pins = <0x184 0x30>; }; /* Mode 0, Pull-Up, RxActive */ 564 | P9_24_can_pin: pinmux_P9_24_can_pin { 565 | pinctrl-single,pins = <0x184 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 566 | P9_24_i2c_pin: pinmux_P9_24_i2c_pin { 567 | pinctrl-single,pins = <0x184 0x33>; }; /* Mode 3, Pull-Up, RxActive */ 568 | P9_24_pru_uart_pin: pinmux_P9_24_pru_uart_pin { 569 | pinctrl-single,pins = <0x184 0x35>; }; /* Mode 5, Pull-Up, RxActive */ 570 | P9_24_pruin_pin: pinmux_P9_24_pruin_pin { 571 | pinctrl-single,pins = <0x184 0x36>; }; /* Mode 6, Pull-Up, RxActive */ 572 | 573 | /* P9_25 (ZCZ ball A14) Audio */ 574 | 575 | /* P9_26 (ZCZ ball D16) */ 576 | P9_26_default_pin: pinmux_P9_26_default_pin { 577 | pinctrl-single,pins = <0x180 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 578 | P9_26_gpio_pin: pinmux_P9_26_gpio_pin { 579 | pinctrl-single,pins = <0x180 0x2F>; }; /* Mode 7, RxActive */ 580 | P9_26_gpio_pu_pin: pinmux_P9_26_gpio_pu_pin { 581 | pinctrl-single,pins = <0x180 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 582 | P9_26_gpio_pd_pin: pinmux_P9_26_gpio_pd_pin { 583 | pinctrl-single,pins = <0x180 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 584 | P9_26_uart_pin: pinmux_P9_26_uart_pin { 585 | pinctrl-single,pins = <0x180 0x30>; }; /* Mode 0, Pull-Up, RxActive */ 586 | P9_26_can_pin: pinmux_P9_26_can_pin { 587 | pinctrl-single,pins = <0x180 0x32>; }; /* Mode 2, Pull-Up, RxActive */ 588 | P9_26_i2c_pin: pinmux_P9_26_i2c_pin { 589 | pinctrl-single,pins = <0x180 0x33>; }; /* Mode 3, Pull-Up, RxActive */ 590 | P9_26_pru_uart_pin: pinmux_P9_26_pru_uart_pin { 591 | pinctrl-single,pins = <0x180 0x35>; }; /* Mode 5, Pull-Up, RxActive */ 592 | P9_26_pruin_pin: pinmux_P9_26_pruin_pin { 593 | pinctrl-single,pins = <0x180 0x36>; }; /* Mode 6, Pull-Up, RxActive */ 594 | 595 | /* P9_27 (ZCZ ball C13) */ 596 | P9_27_default_pin: pinmux_P9_27_default_pin { 597 | pinctrl-single,pins = <0x1a4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 598 | P9_27_gpio_pin: pinmux_P9_27_gpio_pin { 599 | pinctrl-single,pins = <0x1a4 0x2F>; }; /* Mode 7, RxActive */ 600 | P9_27_gpio_pu_pin: pinmux_P9_27_gpio_pu_pin { 601 | pinctrl-single,pins = <0x1a4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 602 | P9_27_gpio_pd_pin: pinmux_P9_27_gpio_pd_pin { 603 | pinctrl-single,pins = <0x1a4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 604 | P9_27_qep_pin: pinmux_P9_27_qep_pin { 605 | pinctrl-single,pins = <0x1a4 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 606 | P9_27_pruout_pin: pinmux_P9_27_pruout_pin { 607 | pinctrl-single,pins = <0x1a4 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 608 | P9_27_pruin_pin: pinmux_P9_27_pruin_pin { 609 | pinctrl-single,pins = <0x1a4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 610 | 611 | /* P9_28 (ZCZ ball C12) Audio */ 612 | /* P9_29 (ZCZ ball B13) Audio */ 613 | 614 | /* P9_30 (ZCZ ball D12) */ 615 | P9_30_default_pin: pinmux_P9_30_default_pin { 616 | pinctrl-single,pins = <0x198 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 617 | P9_30_gpio_pin: pinmux_P9_30_gpio_pin { 618 | pinctrl-single,pins = <0x198 0x2F>; }; /* Mode 7, RxActive */ 619 | P9_30_gpio_pu_pin: pinmux_P9_30_gpio_pu_pin { 620 | pinctrl-single,pins = <0x198 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 621 | P9_30_gpio_pd_pin: pinmux_P9_30_gpio_pd_pin { 622 | pinctrl-single,pins = <0x198 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 623 | P9_30_pwm_pin: pinmux_P9_30_pwm_pin { 624 | pinctrl-single,pins = <0x198 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 625 | P9_30_spi_pin: pinmux_P9_30_spi_pin { 626 | pinctrl-single,pins = <0x198 0x23>; }; /* Mode 3, Pull-Down, RxActive */ 627 | P9_30_pruout_pin: pinmux_P9_30_pruout_pin { 628 | pinctrl-single,pins = <0x198 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 629 | P9_30_pruin_pin: pinmux_P9_30_pruin_pin { 630 | pinctrl-single,pins = <0x198 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 631 | 632 | /* P9_31 (ZCZ ball A13) Audio */ 633 | 634 | /* P9_32 VADC */ 635 | /* P9_33 (ZCZ ball C8 ) AIN4 */ 636 | /* P9_34 AGND */ 637 | /* P9_35 (ZCZ ball A8 ) AIN6 */ 638 | /* P9_36 (ZCZ ball B8 ) AIN5 */ 639 | /* P9_37 (ZCZ ball B7 ) AIN2 */ 640 | /* P9_38 (ZCZ ball A7 ) AIN3 */ 641 | /* P9_39 (ZCZ ball B6 ) AIN0 */ 642 | /* P9_40 (ZCZ ball C7 ) AIN1 */ 643 | 644 | /* P9_41 (ZCZ ball D14) */ 645 | P9_41_default_pin: pinmux_P9_41_default_pin { 646 | pinctrl-single,pins = <0x1b4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 647 | P9_41_gpio_pin: pinmux_P9_41_gpio_pin { 648 | pinctrl-single,pins = <0x1b4 0x2F>; }; /* Mode 7, RxActive */ 649 | P9_41_gpio_pu_pin: pinmux_P9_41_gpio_pu_pin { 650 | pinctrl-single,pins = <0x1b4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 651 | P9_41_gpio_pd_pin: pinmux_P9_41_gpio_pd_pin { 652 | pinctrl-single,pins = <0x1b4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 653 | P9_41_timer_pin: pinmux_P9_41_timer_pin { 654 | pinctrl-single,pins = <0x1b4 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 655 | P9_41_pruin_pin: pinmux_P9_41_pruin_pin { 656 | pinctrl-single,pins = <0x1b4 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 657 | 658 | /* P9_41.1 */ 659 | /* P9_91 (ZCZ ball D13) */ 660 | P9_91_default_pin: pinmux_P9_91_default_pin { 661 | pinctrl-single,pins = <0x1a8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 662 | P9_91_gpio_pin: pinmux_P9_91_gpio_pin { 663 | pinctrl-single,pins = <0x1a8 0x2F>; }; /* Mode 7, RxActive */ 664 | P9_91_gpio_pu_pin: pinmux_P9_91_gpio_pu_pin { 665 | pinctrl-single,pins = <0x1a8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 666 | P9_91_gpio_pd_pin: pinmux_P9_91_gpio_pd_pin { 667 | pinctrl-single,pins = <0x1a8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 668 | P9_91_qep_pin: pinmux_P9_91_qep_pin { 669 | pinctrl-single,pins = <0x1a8 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 670 | P9_91_pruout_pin: pinmux_P9_91_pruout_pin { 671 | pinctrl-single,pins = <0x1a8 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 672 | P9_91_pruin_pin: pinmux_P9_91_pruin_pin { 673 | pinctrl-single,pins = <0x1a8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 674 | 675 | /* P9_42 (ZCZ ball C18) */ 676 | P9_42_default_pin: pinmux_P9_42_default_pin { 677 | pinctrl-single,pins = <0x164 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 678 | P9_42_gpio_pin: pinmux_P9_42_gpio_pin { 679 | pinctrl-single,pins = <0x164 0x2F>; }; /* Mode 7, RxActive */ 680 | P9_42_gpio_pu_pin: pinmux_P9_42_gpio_pu_pin { 681 | pinctrl-single,pins = <0x164 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 682 | P9_42_gpio_pd_pin: pinmux_P9_42_gpio_pd_pin { 683 | pinctrl-single,pins = <0x164 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 684 | P9_42_pwm_pin: pinmux_P9_42_pwm_pin { 685 | pinctrl-single,pins = <0x164 0x20>; }; /* Mode 0, Pull-Down, RxActive */ 686 | P9_42_uart_pin: pinmux_P9_42_uart_pin { 687 | pinctrl-single,pins = <0x164 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 688 | P9_42_spics_pin: pinmux_P9_42_spics_pin { 689 | pinctrl-single,pins = <0x164 0x22>; }; /* Mode 2, Pull-Down, RxActive */ 690 | P9_42_pru_ecap_pin: pinmux_P9_42_pru_ecap_pin { 691 | pinctrl-single,pins = <0x164 0x23>; }; /* Mode 3, Pull-Down, RxActive */ 692 | P9_42_spiclk_pin: pinmux_P9_42_spiclk_pin { 693 | pinctrl-single,pins = <0x164 0x24>; }; /* Mode 4, Pull-Down, RxActive */ 694 | 695 | /* P9_42.1 */ 696 | /* P9_92 (ZCZ ball B12) */ 697 | P9_92_default_pin: pinmux_P9_92_default_pin { 698 | pinctrl-single,pins = <0x1a0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 699 | P9_92_gpio_pin: pinmux_P9_92_gpio_pin { 700 | pinctrl-single,pins = <0x1a0 0x2F>; }; /* Mode 7, RxActive */ 701 | P9_92_gpio_pu_pin: pinmux_P9_92_gpio_pu_pin { 702 | pinctrl-single,pins = <0x1a0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ 703 | P9_92_gpio_pd_pin: pinmux_P9_92_gpio_pd_pin { 704 | pinctrl-single,pins = <0x1a0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ 705 | P9_92_qep_pin: pinmux_P9_92_qep_pin { 706 | pinctrl-single,pins = <0x1a0 0x21>; }; /* Mode 1, Pull-Down, RxActive */ 707 | P9_92_pruout_pin: pinmux_P9_92_pruout_pin { 708 | pinctrl-single,pins = <0x1a0 0x25>; }; /* Mode 5, Pull-Down, RxActive */ 709 | P9_92_pruin_pin: pinmux_P9_92_pruin_pin { 710 | pinctrl-single,pins = <0x1a0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ 711 | 712 | /* P9_43 GND */ 713 | /* P9_44 GND */ 714 | /* P9_45 GND */ 715 | /* P9_46 GND */ 716 | 717 | }; 718 | }; 719 | 720 | 721 | /************************/ 722 | /* Pin Multiplexing */ 723 | /************************/ 724 | 725 | fragment@1 { 726 | target = <&ocp>; 727 | __overlay__ { 728 | 729 | /************************/ 730 | /* P8 Header */ 731 | /************************/ 732 | 733 | P8_07_pinmux { 734 | compatible = "bone-pinmux-helper"; 735 | status = "okay"; 736 | 737 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; 738 | pinctrl-0 = <&P8_07_default_pin>; 739 | pinctrl-1 = <&P8_07_gpio_pin>; 740 | pinctrl-2 = <&P8_07_gpio_pu_pin>; 741 | pinctrl-3 = <&P8_07_gpio_pd_pin>; 742 | pinctrl-4 = <&P8_07_timer_pin>; 743 | }; 744 | 745 | P8_08_pinmux { 746 | compatible = "bone-pinmux-helper"; 747 | status = "okay"; 748 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; 749 | pinctrl-0 = <&P8_08_default_pin>; 750 | pinctrl-1 = <&P8_08_gpio_pin>; 751 | pinctrl-2 = <&P8_08_gpio_pu_pin>; 752 | pinctrl-3 = <&P8_08_gpio_pd_pin>; 753 | pinctrl-4 = <&P8_08_timer_pin>; 754 | }; 755 | 756 | P8_09_pinmux { 757 | compatible = "bone-pinmux-helper"; 758 | status = "okay"; 759 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; 760 | pinctrl-0 = <&P8_09_default_pin>; 761 | pinctrl-1 = <&P8_09_gpio_pin>; 762 | pinctrl-2 = <&P8_09_gpio_pu_pin>; 763 | pinctrl-3 = <&P8_09_gpio_pd_pin>; 764 | pinctrl-4 = <&P8_09_timer_pin>; 765 | }; 766 | 767 | P8_10_pinmux { 768 | compatible = "bone-pinmux-helper"; 769 | status = "okay"; 770 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; 771 | pinctrl-0 = <&P8_10_default_pin>; 772 | pinctrl-1 = <&P8_10_gpio_pin>; 773 | pinctrl-2 = <&P8_10_gpio_pu_pin>; 774 | pinctrl-3 = <&P8_10_gpio_pd_pin>; 775 | pinctrl-4 = <&P8_10_timer_pin>; 776 | }; 777 | 778 | P8_11_pinmux { 779 | compatible = "bone-pinmux-helper"; 780 | status = "okay"; 781 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "qep"; 782 | pinctrl-0 = <&P8_11_default_pin>; 783 | pinctrl-1 = <&P8_11_gpio_pin>; 784 | pinctrl-2 = <&P8_11_gpio_pu_pin>; 785 | pinctrl-3 = <&P8_11_gpio_pd_pin>; 786 | pinctrl-4 = <&P8_11_pruout_pin>; 787 | pinctrl-5 = <&P8_11_qep_pin>; 788 | }; 789 | 790 | P8_12_pinmux { 791 | compatible = "bone-pinmux-helper"; 792 | status = "okay"; 793 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "qep"; 794 | pinctrl-0 = <&P8_12_default_pin>; 795 | pinctrl-1 = <&P8_12_gpio_pin>; 796 | pinctrl-2 = <&P8_12_gpio_pu_pin>; 797 | pinctrl-3 = <&P8_12_gpio_pd_pin>; 798 | pinctrl-4 = <&P8_12_pruout_pin>; 799 | pinctrl-5 = <&P8_12_qep_pin>; 800 | }; 801 | 802 | P8_13_pinmux { 803 | compatible = "bone-pinmux-helper"; 804 | status = "okay"; 805 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 806 | pinctrl-0 = <&P8_13_default_pin>; 807 | pinctrl-1 = <&P8_13_gpio_pin>; 808 | pinctrl-2 = <&P8_13_gpio_pu_pin>; 809 | pinctrl-3 = <&P8_13_gpio_pd_pin>; 810 | pinctrl-4 = <&P8_13_pwm_pin>; 811 | }; 812 | 813 | P8_14_pinmux { 814 | compatible = "bone-pinmux-helper"; 815 | status = "okay"; 816 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 817 | pinctrl-0 = <&P8_14_default_pin>; 818 | pinctrl-1 = <&P8_14_gpio_pin>; 819 | pinctrl-2 = <&P8_14_gpio_pu_pin>; 820 | pinctrl-3 = <&P8_14_gpio_pd_pin>; 821 | pinctrl-4 = <&P8_14_pwm_pin>; 822 | }; 823 | 824 | P8_15_pinmux { 825 | compatible = "bone-pinmux-helper"; 826 | status = "okay"; 827 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruin", "pru_ecap", "qep"; 828 | pinctrl-0 = <&P8_15_default_pin>; 829 | pinctrl-1 = <&P8_15_gpio_pin>; 830 | pinctrl-2 = <&P8_15_gpio_pu_pin>; 831 | pinctrl-3 = <&P8_15_gpio_pd_pin>; 832 | pinctrl-4 = <&P8_15_pruin_pin>; 833 | pinctrl-5 = <&P8_15_pru_ecap_pin>; 834 | pinctrl-6 = <&P8_15_qep_pin>; 835 | }; 836 | 837 | P8_16_pinmux { 838 | compatible = "bone-pinmux-helper"; 839 | status = "okay"; 840 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruin", "qep"; 841 | pinctrl-0 = <&P8_16_default_pin>; 842 | pinctrl-1 = <&P8_16_gpio_pin>; 843 | pinctrl-2 = <&P8_16_gpio_pu_pin>; 844 | pinctrl-3 = <&P8_16_gpio_pd_pin>; 845 | pinctrl-4 = <&P8_16_pruin_pin>; 846 | pinctrl-5 = <&P8_16_qep_pin>; 847 | }; 848 | 849 | P8_17_pinmux { 850 | compatible = "bone-pinmux-helper"; 851 | status = "okay"; 852 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 853 | pinctrl-0 = <&P8_17_default_pin>; 854 | pinctrl-1 = <&P8_17_gpio_pin>; 855 | pinctrl-2 = <&P8_17_gpio_pu_pin>; 856 | pinctrl-3 = <&P8_17_gpio_pd_pin>; 857 | pinctrl-4 = <&P8_17_pwm_pin>; 858 | }; 859 | 860 | P8_18_pinmux { 861 | compatible = "bone-pinmux-helper"; 862 | status = "okay"; 863 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 864 | pinctrl-0 = <&P8_18_default_pin>; 865 | pinctrl-1 = <&P8_18_gpio_pin>; 866 | pinctrl-2 = <&P8_18_gpio_pu_pin>; 867 | pinctrl-3 = <&P8_18_gpio_pd_pin>; 868 | }; 869 | 870 | P8_19_pinmux { 871 | compatible = "bone-pinmux-helper"; 872 | status = "okay"; 873 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 874 | pinctrl-0 = <&P8_19_default_pin>; 875 | pinctrl-1 = <&P8_19_gpio_pin>; 876 | pinctrl-2 = <&P8_19_gpio_pu_pin>; 877 | pinctrl-3 = <&P8_19_gpio_pd_pin>; 878 | pinctrl-4 = <&P8_19_pwm_pin>; 879 | }; 880 | 881 | P8_26_pinmux { 882 | compatible = "bone-pinmux-helper"; 883 | status = "okay"; 884 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 885 | pinctrl-0 = <&P8_26_default_pin>; 886 | pinctrl-1 = <&P8_26_gpio_pin>; 887 | pinctrl-2 = <&P8_26_gpio_pu_pin>; 888 | pinctrl-3 = <&P8_26_gpio_pd_pin>; 889 | }; 890 | 891 | 892 | /************************/ 893 | /* P9 Header */ 894 | /************************/ 895 | 896 | P9_11_pinmux { 897 | compatible = "bone-pinmux-helper"; 898 | status = "okay"; 899 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart"; 900 | pinctrl-0 = <&P9_11_default_pin>; 901 | pinctrl-1 = <&P9_11_gpio_pin>; 902 | pinctrl-2 = <&P9_11_gpio_pu_pin>; 903 | pinctrl-3 = <&P9_11_gpio_pd_pin>; 904 | pinctrl-4 = <&P9_11_uart_pin>; 905 | }; 906 | 907 | P9_12_pinmux { 908 | compatible = "bone-pinmux-helper"; 909 | status = "okay"; 910 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd"; 911 | pinctrl-0 = <&P9_12_default_pin>; 912 | pinctrl-1 = <&P9_12_gpio_pin>; 913 | pinctrl-2 = <&P9_12_gpio_pu_pin>; 914 | pinctrl-3 = <&P9_12_gpio_pd_pin>; 915 | }; 916 | 917 | P9_13_pinmux { 918 | compatible = "bone-pinmux-helper"; 919 | status = "okay"; 920 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart"; 921 | pinctrl-0 = <&P9_13_default_pin>; 922 | pinctrl-1 = <&P9_13_gpio_pin>; 923 | pinctrl-2 = <&P9_13_gpio_pu_pin>; 924 | pinctrl-3 = <&P9_13_gpio_pd_pin>; 925 | pinctrl-4 = <&P9_13_uart_pin>; 926 | }; 927 | 928 | P9_14_pinmux { 929 | compatible = "bone-pinmux-helper"; 930 | status = "okay"; 931 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 932 | pinctrl-0 = <&P9_14_default_pin>; 933 | pinctrl-1 = <&P9_14_gpio_pin>; 934 | pinctrl-2 = <&P9_14_gpio_pu_pin>; 935 | pinctrl-3 = <&P9_14_gpio_pd_pin>; 936 | pinctrl-4 = <&P9_14_pwm_pin>; 937 | }; 938 | 939 | P9_15_pinmux { 940 | compatible = "bone-pinmux-helper"; 941 | status = "okay"; 942 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 943 | pinctrl-0 = <&P9_15_default_pin>; 944 | pinctrl-1 = <&P9_15_gpio_pin>; 945 | pinctrl-2 = <&P9_15_gpio_pu_pin>; 946 | pinctrl-3 = <&P9_15_gpio_pd_pin>; 947 | pinctrl-4 = <&P9_15_pwm_pin>; 948 | }; 949 | 950 | P9_16_pinmux { 951 | compatible = "bone-pinmux-helper"; 952 | status = "okay"; 953 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 954 | pinctrl-0 = <&P9_16_default_pin>; 955 | pinctrl-1 = <&P9_16_gpio_pin>; 956 | pinctrl-2 = <&P9_16_gpio_pu_pin>; 957 | pinctrl-3 = <&P9_16_gpio_pd_pin>; 958 | pinctrl-4 = <&P9_16_pwm_pin>; 959 | }; 960 | 961 | P9_17_pinmux { 962 | compatible = "bone-pinmux-helper"; 963 | status = "okay"; 964 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "i2c", "pwm", "pru_uart"; 965 | pinctrl-0 = <&P9_17_default_pin>; 966 | pinctrl-1 = <&P9_17_gpio_pin>; 967 | pinctrl-2 = <&P9_17_gpio_pu_pin>; 968 | pinctrl-3 = <&P9_17_gpio_pd_pin>; 969 | pinctrl-4 = <&P9_17_spi_pin>; 970 | pinctrl-5 = <&P9_17_i2c_pin>; 971 | pinctrl-6 = <&P9_17_pwm_pin>; 972 | pinctrl-7 = <&P9_17_pru_uart_pin>; 973 | }; 974 | 975 | P9_18_pinmux { 976 | compatible = "bone-pinmux-helper"; 977 | status = "okay"; 978 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "i2c", "pwm", "pru_uart"; 979 | pinctrl-0 = <&P9_18_default_pin>; 980 | pinctrl-1 = <&P9_18_gpio_pin>; 981 | pinctrl-2 = <&P9_18_gpio_pu_pin>; 982 | pinctrl-3 = <&P9_18_gpio_pd_pin>; 983 | pinctrl-4 = <&P9_18_spi_pin>; 984 | pinctrl-5 = <&P9_18_i2c_pin>; 985 | pinctrl-6 = <&P9_18_pwm_pin>; 986 | pinctrl-7 = <&P9_18_pru_uart_pin>; 987 | }; 988 | 989 | // I2C Pins 990 | // P9_19_pinmux 991 | // P9_20_pinmux 992 | 993 | P9_21_pinmux { 994 | compatible = "bone-pinmux-helper"; 995 | status = "okay"; 996 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "uart", "i2c", "pwm", "pru_uart"; 997 | pinctrl-0 = <&P9_21_default_pin>; 998 | pinctrl-1 = <&P9_21_gpio_pin>; 999 | pinctrl-2 = <&P9_21_gpio_pu_pin>; 1000 | pinctrl-3 = <&P9_21_gpio_pd_pin>; 1001 | pinctrl-4 = <&P9_21_spi_pin>; 1002 | pinctrl-5 = <&P9_21_uart_pin>; 1003 | pinctrl-6 = <&P9_21_i2c_pin>; 1004 | pinctrl-7 = <&P9_21_pwm_pin>; 1005 | pinctrl-8 = <&P9_21_pru_uart_pin>; 1006 | }; 1007 | 1008 | P9_22_pinmux { 1009 | compatible = "bone-pinmux-helper"; 1010 | status = "okay"; 1011 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "uart", "i2c", "pwm", "pru_uart"; 1012 | pinctrl-0 = <&P9_22_default_pin>; 1013 | pinctrl-1 = <&P9_22_gpio_pin>; 1014 | pinctrl-2 = <&P9_22_gpio_pu_pin>; 1015 | pinctrl-3 = <&P9_22_gpio_pd_pin>; 1016 | pinctrl-4 = <&P9_22_spi_pin>; 1017 | pinctrl-5 = <&P9_22_uart_pin>; 1018 | pinctrl-6 = <&P9_22_i2c_pin>; 1019 | pinctrl-7 = <&P9_22_pwm_pin>; 1020 | pinctrl-8 = <&P9_22_pru_uart_pin>; 1021 | }; 1022 | 1023 | P9_23_pinmux { 1024 | compatible = "bone-pinmux-helper"; 1025 | status = "okay"; 1026 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; 1027 | pinctrl-0 = <&P9_23_default_pin>; 1028 | pinctrl-1 = <&P9_23_gpio_pin>; 1029 | pinctrl-2 = <&P9_23_gpio_pu_pin>; 1030 | pinctrl-3 = <&P9_23_gpio_pd_pin>; 1031 | pinctrl-4 = <&P9_23_pwm_pin>; 1032 | }; 1033 | 1034 | P9_24_pinmux { 1035 | compatible = "bone-pinmux-helper"; 1036 | status = "okay"; 1037 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "can", "i2c", "pru_uart", "pruin"; 1038 | pinctrl-0 = <&P9_24_default_pin>; 1039 | pinctrl-1 = <&P9_24_gpio_pin>; 1040 | pinctrl-2 = <&P9_24_gpio_pu_pin>; 1041 | pinctrl-3 = <&P9_24_gpio_pd_pin>; 1042 | pinctrl-4 = <&P9_24_uart_pin>; 1043 | pinctrl-5 = <&P9_24_can_pin>; 1044 | pinctrl-6 = <&P9_24_i2c_pin>; 1045 | pinctrl-7 = <&P9_24_pru_uart_pin>; 1046 | pinctrl-8 = <&P9_24_pruin_pin>; 1047 | }; 1048 | 1049 | 1050 | // Audio pin 1051 | // P9_25_pinmux 1052 | 1053 | P9_26_pinmux { 1054 | compatible = "bone-pinmux-helper"; 1055 | status = "okay"; 1056 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "can", "i2c", "pru_uart", "pruin"; 1057 | pinctrl-0 = <&P9_26_default_pin>; 1058 | pinctrl-1 = <&P9_26_gpio_pin>; 1059 | pinctrl-2 = <&P9_26_gpio_pu_pin>; 1060 | pinctrl-3 = <&P9_26_gpio_pd_pin>; 1061 | pinctrl-4 = <&P9_26_uart_pin>; 1062 | pinctrl-5 = <&P9_26_can_pin>; 1063 | pinctrl-6 = <&P9_26_i2c_pin>; 1064 | pinctrl-7 = <&P9_26_pru_uart_pin>; 1065 | pinctrl-8 = <&P9_26_pruin_pin>; 1066 | }; 1067 | 1068 | P9_27_pinmux { 1069 | compatible = "bone-pinmux-helper"; 1070 | status = "okay"; 1071 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; 1072 | pinctrl-0 = <&P9_27_default_pin>; 1073 | pinctrl-1 = <&P9_27_gpio_pin>; 1074 | pinctrl-2 = <&P9_27_gpio_pu_pin>; 1075 | pinctrl-3 = <&P9_27_gpio_pd_pin>; 1076 | pinctrl-4 = <&P9_27_qep_pin>; 1077 | pinctrl-5 = <&P9_27_pruout_pin>; 1078 | pinctrl-6 = <&P9_27_pruin_pin>; 1079 | }; 1080 | 1081 | // Audio pins 1082 | // P9_28_pinmux 1083 | // P9_29_pinmux 1084 | 1085 | P9_30_pinmux { 1086 | compatible = "bone-pinmux-helper"; 1087 | status = "okay"; 1088 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pruout", "pruin"; 1089 | pinctrl-0 = <&P9_30_default_pin>; 1090 | pinctrl-1 = <&P9_30_gpio_pin>; 1091 | pinctrl-2 = <&P9_30_gpio_pu_pin>; 1092 | pinctrl-3 = <&P9_30_gpio_pd_pin>; 1093 | pinctrl-4 = <&P9_30_pwm_pin>; 1094 | pinctrl-5 = <&P9_30_spi_pin>; 1095 | pinctrl-6 = <&P9_30_pruout_pin>; 1096 | pinctrl-7 = <&P9_30_pruin_pin>; 1097 | }; 1098 | 1099 | // Audio pin 1100 | // P9_31_pinmux 1101 | 1102 | P9_41_pinmux { 1103 | compatible = "bone-pinmux-helper"; 1104 | status = "okay"; 1105 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer", "pruin"; 1106 | pinctrl-0 = <&P9_41_default_pin>; 1107 | pinctrl-1 = <&P9_41_gpio_pin>; 1108 | pinctrl-2 = <&P9_41_gpio_pu_pin>; 1109 | pinctrl-3 = <&P9_41_gpio_pd_pin>; 1110 | pinctrl-4 = <&P9_41_timer_pin>; 1111 | pinctrl-5 = <&P9_41_pruin_pin>; 1112 | }; 1113 | 1114 | P9_91_pinmux { 1115 | compatible = "bone-pinmux-helper"; 1116 | status = "okay"; 1117 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; 1118 | pinctrl-0 = <&P9_91_default_pin>; 1119 | pinctrl-1 = <&P9_91_gpio_pin>; 1120 | pinctrl-2 = <&P9_91_gpio_pu_pin>; 1121 | pinctrl-3 = <&P9_91_gpio_pd_pin>; 1122 | pinctrl-4 = <&P9_91_qep_pin>; 1123 | pinctrl-5 = <&P9_91_pruout_pin>; 1124 | pinctrl-6 = <&P9_91_pruin_pin>; 1125 | }; 1126 | 1127 | P9_42_pinmux { 1128 | compatible = "bone-pinmux-helper"; 1129 | status = "okay"; 1130 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "uart", "spics", "pru_ecap", "spiclk"; 1131 | pinctrl-0 = <&P9_42_default_pin>; 1132 | pinctrl-1 = <&P9_42_gpio_pin>; 1133 | pinctrl-2 = <&P9_42_gpio_pu_pin>; 1134 | pinctrl-3 = <&P9_42_gpio_pd_pin>; 1135 | pinctrl-4 = <&P9_42_pwm_pin>; 1136 | pinctrl-5 = <&P9_42_uart_pin>; 1137 | pinctrl-6 = <&P9_42_spics_pin>; 1138 | pinctrl-7 = <&P9_42_pru_ecap_pin>; 1139 | pinctrl-8 = <&P9_42_spiclk_pin>; 1140 | }; 1141 | 1142 | P9_92_pinmux { 1143 | compatible = "bone-pinmux-helper"; 1144 | status = "okay"; 1145 | pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; 1146 | pinctrl-0 = <&P9_92_default_pin>; 1147 | pinctrl-1 = <&P9_92_gpio_pin>; 1148 | pinctrl-2 = <&P9_92_gpio_pu_pin>; 1149 | pinctrl-3 = <&P9_92_gpio_pd_pin>; 1150 | pinctrl-4 = <&P9_92_qep_pin>; 1151 | pinctrl-5 = <&P9_92_pruout_pin>; 1152 | pinctrl-6 = <&P9_92_pruin_pin>; 1153 | }; 1154 | }; 1155 | }; 1156 | 1157 | fragment@2 { 1158 | target = <&ocp>; 1159 | __overlay__ { 1160 | 1161 | // !!!WARNING!!! 1162 | // gpio-of-helper &gpio pointers are off-by-one vs. the hardware: 1163 | // hardware GPIO bank 0 = &gpio1 1164 | cape-universal { 1165 | compatible = "gpio-of-helper"; 1166 | status = "okay"; 1167 | pinctrl-names = "default"; 1168 | pinctrl-0 = <>; 1169 | 1170 | P8_07 { 1171 | gpio-name = "P8_07"; 1172 | gpio = <&gpio3 2 0>; 1173 | input; 1174 | dir-changeable; 1175 | }; 1176 | P8_08 { 1177 | gpio-name = "P8_08"; 1178 | gpio = <&gpio3 3 0>; 1179 | input; 1180 | dir-changeable; 1181 | }; 1182 | P8_09 { 1183 | gpio-name = "P8_09"; 1184 | gpio = <&gpio3 5 0>; 1185 | input; 1186 | dir-changeable; 1187 | }; 1188 | P8_10 { 1189 | gpio-name = "P8_10"; 1190 | gpio = <&gpio3 4 0>; 1191 | input; 1192 | dir-changeable; 1193 | }; 1194 | P8_11 { 1195 | gpio-name = "P8_11"; 1196 | gpio = <&gpio2 13 0>; 1197 | input; 1198 | dir-changeable; 1199 | }; 1200 | P8_12 { 1201 | gpio-name = "P8_12"; 1202 | gpio = <&gpio2 12 0>; 1203 | input; 1204 | dir-changeable; 1205 | }; 1206 | P8_13 { 1207 | gpio-name = "P8_13"; 1208 | gpio = <&gpio1 23 0>; 1209 | input; 1210 | dir-changeable; 1211 | }; 1212 | P8_14 { 1213 | gpio-name = "P8_14"; 1214 | gpio = <&gpio1 26 0>; 1215 | input; 1216 | dir-changeable; 1217 | }; 1218 | P8_15 { 1219 | gpio-name = "P8_15"; 1220 | gpio = <&gpio2 15 0>; 1221 | input; 1222 | dir-changeable; 1223 | }; 1224 | P8_16 { 1225 | gpio-name = "P8_16"; 1226 | gpio = <&gpio2 14 0>; 1227 | input; 1228 | dir-changeable; 1229 | }; 1230 | P8_17 { 1231 | gpio-name = "P8_17"; 1232 | gpio = <&gpio1 27 0>; 1233 | input; 1234 | dir-changeable; 1235 | }; 1236 | P8_18 { 1237 | gpio-name = "P8_18"; 1238 | gpio = <&gpio3 1 0>; 1239 | input; 1240 | dir-changeable; 1241 | }; 1242 | P8_19 { 1243 | gpio-name = "P8_19"; 1244 | gpio = <&gpio1 22 0>; 1245 | input; 1246 | dir-changeable; 1247 | }; 1248 | P8_26 { 1249 | gpio-name = "P8_26"; 1250 | gpio = <&gpio2 29 0>; 1251 | input; 1252 | dir-changeable; 1253 | }; 1254 | 1255 | 1256 | P9_11 { 1257 | gpio-name = "P9_11"; 1258 | gpio = <&gpio1 30 0>; 1259 | input; 1260 | dir-changeable; 1261 | }; 1262 | P9_12 { 1263 | gpio-name = "P9_12"; 1264 | gpio = <&gpio2 28 0>; 1265 | input; 1266 | dir-changeable; 1267 | }; 1268 | P9_13 { 1269 | gpio-name = "P9_13"; 1270 | gpio = <&gpio1 31 0>; 1271 | input; 1272 | dir-changeable; 1273 | }; 1274 | P9_14 { 1275 | gpio-name = "P9_14"; 1276 | gpio = <&gpio2 18 0>; 1277 | input; 1278 | dir-changeable; 1279 | }; 1280 | P9_15 { 1281 | gpio-name = "P9_15"; 1282 | gpio = <&gpio2 16 0>; 1283 | input; 1284 | dir-changeable; 1285 | }; 1286 | P9_16 { 1287 | gpio-name = "P9_16"; 1288 | gpio = <&gpio2 19 0>; 1289 | input; 1290 | dir-changeable; 1291 | }; 1292 | P9_17 { 1293 | gpio-name = "P9_17"; 1294 | gpio = <&gpio1 5 0>; 1295 | input; 1296 | dir-changeable; 1297 | }; 1298 | P9_18 { 1299 | gpio-name = "P9_18"; 1300 | gpio = <&gpio1 4 0>; 1301 | input; 1302 | dir-changeable; 1303 | }; 1304 | 1305 | // I2C pins 1306 | // P9_19 1307 | // P9_20 1308 | 1309 | P9_21 { 1310 | gpio-name = "P9_21"; 1311 | gpio = <&gpio1 3 0>; 1312 | input; 1313 | dir-changeable; 1314 | }; 1315 | P9_22 { 1316 | gpio-name = "P9_22"; 1317 | gpio = <&gpio1 2 0>; 1318 | input; 1319 | dir-changeable; 1320 | }; 1321 | P9_23 { 1322 | gpio-name = "P9_23"; 1323 | gpio = <&gpio2 17 0>; 1324 | input; 1325 | dir-changeable; 1326 | }; 1327 | P9_24 { 1328 | gpio-name = "P9_24"; 1329 | gpio = <&gpio1 15 0>; 1330 | input; 1331 | dir-changeable; 1332 | }; 1333 | 1334 | // Audio pin 1335 | // P9_25 1336 | 1337 | P9_26 { 1338 | gpio-name = "P9_26"; 1339 | gpio = <&gpio1 14 0>; 1340 | input; 1341 | dir-changeable; 1342 | }; 1343 | P9_27 { 1344 | gpio-name = "P9_27"; 1345 | gpio = <&gpio4 19 0>; 1346 | input; 1347 | dir-changeable; 1348 | }; 1349 | 1350 | // Audio pins 1351 | // P9_28 1352 | // P9_29 1353 | 1354 | P9_30 { 1355 | gpio-name = "P9_30"; 1356 | gpio = <&gpio4 16 0>; 1357 | input; 1358 | dir-changeable; 1359 | }; 1360 | 1361 | // Audio pin 1362 | // P9_31 1363 | 1364 | P9_41 { 1365 | gpio-name = "P9_41"; 1366 | gpio = <&gpio1 20 0>; 1367 | input; 1368 | dir-changeable; 1369 | }; 1370 | P9_91 { 1371 | gpio-name = "P9_91"; 1372 | gpio = <&gpio4 20 0>; 1373 | input; 1374 | dir-changeable; 1375 | }; 1376 | P9_42 { 1377 | gpio-name = "P9_42"; 1378 | gpio = <&gpio1 7 0>; 1379 | input; 1380 | dir-changeable; 1381 | }; 1382 | P9_92 { 1383 | gpio-name = "P9_92"; 1384 | gpio = <&gpio4 18 0>; 1385 | input; 1386 | dir-changeable; 1387 | }; 1388 | }; 1389 | }; 1390 | }; 1391 | 1392 | 1393 | 1394 | /************************/ 1395 | /* UARTs */ 1396 | /************************/ 1397 | 1398 | fragment@10 { 1399 | target = <&uart2>; /* really uart1 */ 1400 | __overlay__ { 1401 | status = "okay"; 1402 | pinctrl-names = "default"; 1403 | pinctrl-0 = <>; 1404 | }; 1405 | }; 1406 | 1407 | fragment@11 { 1408 | target = <&uart3>; /* really uart2 */ 1409 | __overlay__ { 1410 | status = "okay"; 1411 | pinctrl-names = "default"; 1412 | pinctrl-0 = <>; 1413 | }; 1414 | }; 1415 | 1416 | fragment@12 { 1417 | target = <&uart5>; /* really uart4 */ 1418 | __overlay__ { 1419 | status = "okay"; 1420 | pinctrl-names = "default"; 1421 | pinctrl-0 = <>; 1422 | }; 1423 | }; 1424 | 1425 | // /* UART 5 only available on LCD/HDMI pins */ 1426 | // fragment@13 { 1427 | // target = <&uart6>; /* really uart5 */ 1428 | // __overlay__ { 1429 | // status = "okay"; 1430 | // pinctrl-names = "default"; 1431 | // pinctrl-0 = <>; 1432 | // }; 1433 | // }; 1434 | 1435 | /************************/ 1436 | /* Timers / PWM */ 1437 | /************************/ 1438 | 1439 | fragment@20 { 1440 | target = <&epwmss0>; 1441 | __overlay__ { 1442 | status = "okay"; 1443 | }; 1444 | }; 1445 | 1446 | fragment@21 { 1447 | target = <&ehrpwm0>; 1448 | __overlay__ { 1449 | status = "okay"; 1450 | pinctrl-names = "default"; 1451 | pinctrl-0 = <>; 1452 | }; 1453 | }; 1454 | 1455 | fragment@22 { 1456 | target = <&ecap0>; 1457 | __overlay__ { 1458 | status = "okay"; 1459 | pinctrl-names = "default"; 1460 | pinctrl-0 = <>; 1461 | }; 1462 | }; 1463 | 1464 | fragment@23 { 1465 | target = <&epwmss1>; 1466 | __overlay__ { 1467 | status = "okay"; 1468 | }; 1469 | }; 1470 | 1471 | fragment@24 { 1472 | target = <&ehrpwm1>; 1473 | __overlay__ { 1474 | status = "okay"; 1475 | pinctrl-names = "default"; 1476 | pinctrl-0 = <>; 1477 | }; 1478 | }; 1479 | 1480 | fragment@25 { 1481 | target = <&epwmss2>; 1482 | __overlay__ { 1483 | status = "okay"; 1484 | }; 1485 | }; 1486 | 1487 | fragment@26 { 1488 | target = <&ehrpwm2>; 1489 | __overlay__ { 1490 | status = "okay"; 1491 | pinctrl-names = "default"; 1492 | pinctrl-0 = <>; 1493 | }; 1494 | }; 1495 | 1496 | fragment@27 { 1497 | target = <&ecap2>; 1498 | __overlay__ { 1499 | status = "okay"; 1500 | pinctrl-names = "default"; 1501 | pinctrl-0 = <>; 1502 | }; 1503 | }; 1504 | 1505 | /************************/ 1506 | /* I2C / SPI */ 1507 | /************************/ 1508 | 1509 | 1510 | fragment@30 { 1511 | target = <&i2c1>; /* i2c1 is numbered correctly */ 1512 | __overlay__ { 1513 | status = "okay"; 1514 | pinctrl-names = "default"; 1515 | pinctrl-0 = <>; 1516 | 1517 | /* this is the configuration part */ 1518 | clock-frequency = <100000>; 1519 | 1520 | #address-cells = <1>; 1521 | #size-cells = <0>; 1522 | 1523 | /* add any i2c devices on the bus here */ 1524 | 1525 | // commented out example of a touchscreen (taken from BB-BONE-LCD7-01-00A4) */ 1526 | // maxtouch@4a { 1527 | // compatible = "mXT224"; 1528 | // reg = <0x4a>; 1529 | // interrupt-parent = <&gpio4>; 1530 | // interrupts = <19 0x0>; 1531 | // atmel,irq-gpio = <&gpio4 19 0>; 1532 | // }; 1533 | }; 1534 | }; 1535 | 1536 | fragment@31 { 1537 | target = <&spi0>; /* spi0 is numbered correctly */ 1538 | __overlay__ { 1539 | #address-cells = <1>; 1540 | #size-cells = <0>; 1541 | 1542 | status = "okay"; 1543 | pinctrl-names = "default"; 1544 | pinctrl-0 = <>; 1545 | 1546 | spi0channel@0 { 1547 | #address-cells = <1>; 1548 | #size-cells = <0>; 1549 | 1550 | compatible = "spidev"; 1551 | 1552 | reg = <0>; 1553 | spi-max-frequency = <16000000>; 1554 | spi-cpha; 1555 | }; 1556 | 1557 | 1558 | spi0channel@1 { 1559 | #address-cells = <1>; 1560 | #size-cells = <0>; 1561 | 1562 | compatible = "spidev"; 1563 | 1564 | reg = <1>; 1565 | spi-max-frequency = <16000000>; 1566 | }; 1567 | }; 1568 | }; 1569 | 1570 | fragment@32 { 1571 | target = <&spi1>; /* spi1 is numbered correctly */ 1572 | __overlay__ { 1573 | status = "okay"; 1574 | pinctrl-names = "default"; 1575 | pinctrl-0 = <>; 1576 | 1577 | #address-cells = <1>; 1578 | #size-cells = <0>; 1579 | 1580 | spi1channel@0 { 1581 | #address-cells = <1>; 1582 | #size-cells = <0>; 1583 | 1584 | compatible = "spidev"; 1585 | 1586 | reg = <0>; 1587 | spi-max-frequency = <16000000>; 1588 | spi-cpha; 1589 | }; 1590 | 1591 | spi1channel@1 { 1592 | #address-cells = <1>; 1593 | #size-cells = <0>; 1594 | 1595 | compatible = "spidev"; 1596 | 1597 | reg = <1>; 1598 | spi-max-frequency = <16000000>; 1599 | }; 1600 | }; 1601 | }; 1602 | 1603 | fragment@33 { 1604 | target = <&dcan0>; 1605 | __overlay__ { 1606 | status = "okay"; 1607 | pinctrl-names = "default"; 1608 | pinctrl-0 = <>; 1609 | }; 1610 | }; 1611 | 1612 | fragment@34 { 1613 | target = <&dcan1>; 1614 | __overlay__ { 1615 | status = "okay"; 1616 | pinctrl-names = "default"; 1617 | pinctrl-0 = <>; 1618 | }; 1619 | }; 1620 | 1621 | 1622 | /************************/ 1623 | /* PRUSS */ 1624 | /************************/ 1625 | 1626 | fragment@40 { 1627 | target = <&pruss>; 1628 | __overlay__ { 1629 | status = "okay"; 1630 | }; 1631 | }; 1632 | 1633 | 1634 | /************************/ 1635 | /* eQEP */ 1636 | /************************/ 1637 | 1638 | fragment@50 { 1639 | target = <&eqep0>; 1640 | __overlay__ { 1641 | pinctrl-names = "default"; 1642 | pinctrl-0 = <>; 1643 | 1644 | count_mode = <0>; /* 0 - Quadrature mode, normal 90 phase offset cha & chb. 1 - Direction mode. cha input = clock, chb input = direction */ 1645 | swap_inputs = <0>; /* Are channel A and channel B swapped? (0 - no, 1 - yes) */ 1646 | invert_qa = <1>; /* Should we invert the channel A input? */ 1647 | invert_qb = <1>; /* Should we invert the channel B input? I invert these because my encoder outputs drive transistors that pull down the pins */ 1648 | invert_qi = <0>; /* Should we invert the index input? */ 1649 | invert_qs = <0>; /* Should we invert the strobe input? */ 1650 | 1651 | status = "okay"; 1652 | }; 1653 | }; 1654 | 1655 | fragment@51 { 1656 | target = <&eqep1>; 1657 | __overlay__ { 1658 | pinctrl-names = "default"; 1659 | pinctrl-0 = <>; 1660 | 1661 | count_mode = <0>; /* 0 - Quadrature mode, normal 90 phase offset cha & chb. 1 - Direction mode. cha input = clock, chb input = direction */ 1662 | swap_inputs = <0>; /* Are channel A and channel B swapped? (0 - no, 1 - yes) */ 1663 | invert_qa = <1>; /* Should we invert the channel A input? */ 1664 | invert_qb = <1>; /* Should we invert the channel B input? I invert these because my encoder outputs drive transistors that pull down the pins */ 1665 | invert_qi = <0>; /* Should we invert the index input? */ 1666 | invert_qs = <0>; /* Should we invert the strobe input? */ 1667 | 1668 | status = "okay"; 1669 | }; 1670 | }; 1671 | 1672 | fragment@52 { 1673 | target = <&eqep2>; 1674 | __overlay__ { 1675 | pinctrl-names = "default"; 1676 | pinctrl-0 = <>; 1677 | 1678 | count_mode = <0>; /* 0 - Quadrature mode, normal 90 phase offset cha & chb. 1 - Direction mode. cha input = clock, chb input = direction */ 1679 | swap_inputs = <0>; /* Are channel A and channel B swapped? (0 - no, 1 - yes) */ 1680 | invert_qa = <1>; /* Should we invert the channel A input? */ 1681 | invert_qb = <1>; /* Should we invert the channel B input? I invert these because my encoder outputs drive transistors that pull down the pins */ 1682 | invert_qi = <0>; /* Should we invert the index input? */ 1683 | invert_qs = <0>; /* Should we invert the strobe input? */ 1684 | 1685 | status = "okay"; 1686 | }; 1687 | }; 1688 | }; 1689 | -------------------------------------------------------------------------------- /config-pin: -------------------------------------------------------------------------------- 1 | #!/bin/dash 2 | 3 | # Some important directories for use later 4 | OCPDIR=/sys/devices/ocp.* 5 | GPIODIR=/sys/class/gpio 6 | SLOTS=/sys/devices/bone_capemgr.*/slots 7 | 8 | #4.1.x where lots of things changed... 9 | #use the new location of bone_capemgr for detection.. 10 | if [ -d /sys/devices/platform/bone_capemgr/ ] ; then 11 | OCPDIR=/sys/devices/platform/ocp/ocp* 12 | SLOTS=/sys/devices/platform/bone_capemgr/slots 13 | fi 14 | 15 | # Create mappings between BeagleBone header pins and kernel gpio 16 | # numbers. These could be bash arrays or coded in python, but simple 17 | # shell constructs are used so this code runs on a minimal system 18 | # (including the BusyBox shell in an initrd, ash, and dash) 19 | 20 | # PIN: function when no cape is loaded 21 | # PINMUX: pin multiplexer functions when cape is loaded 22 | # INFO: information to pin functions, starts with information for PIN and then PINMUX 23 | # CAPE: cape that enables pinmuxing for specific pin, if no cape is set the pin is not modifiable 24 | # GPIO: kernel GPIO pin number 25 | # PRU: PRU pin number 26 | 27 | P8_01_PIN="gnd" 28 | P8_01_INFO="GND" 29 | P8_01_CAPE="" 30 | 31 | P8_02_PIN="gnd" 32 | P8_02_INFO="GND" 33 | P8_02_CAPE="" 34 | 35 | P8_03_PRU="70" 36 | P8_03_GPIO="38" 37 | P8_03_PIN="emmc" 38 | P8_03_PINMUX="default gpio gpio_pu gpio_pd" 39 | P8_03_INFO="mmc1_dat6 default gpio1_6 gpio1_6 gpio1_6" 40 | P8_03_CAPE="cape-universala cape-univ-emmc" 41 | 42 | P8_04_PRU="71" 43 | P8_04_GPIO="39" 44 | P8_04_PIN="emmc" 45 | P8_04_PINMUX="default gpio gpio_pu gpio_pd" 46 | P8_04_INFO="mmc1_dat7 default gpio1_7 gpio1_7 gpio1_7" 47 | P8_04_CAPE="cape-universala cape-univ-emmc" 48 | 49 | P8_05_PRU="66" 50 | P8_05_GPIO="34" 51 | P8_05_PIN="emmc" 52 | P8_05_PINMUX="default gpio gpio_pu gpio_pd" 53 | P8_05_INFO="mmc1_dat2 default gpio1_2 gpio1_2 gpio1_2" 54 | P8_05_CAPE="cape-universala cape-univ-emmc" 55 | 56 | P8_06_PRU="67" 57 | P8_06_GPIO="35" 58 | P8_06_PIN="emmc" 59 | P8_06_PINMUX="default gpio gpio_pu gpio_pd" 60 | P8_06_INFO="mmc1_dat3 default gpio1_3 gpio1_3 gpio1_3" 61 | P8_06_CAPE="cape-universala cape-univ-emmc" 62 | 63 | P8_07_PRU="98" 64 | P8_07_GPIO="66" 65 | P8_07_PIN="gpio" 66 | P8_07_PINMUX="default gpio gpio_pu gpio_pd timer" 67 | P8_07_INFO="gio2_2 default gpio2_2 gpio2_2 gpio2_2 timer4" 68 | P8_07_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 69 | 70 | P8_08_PRU="99" 71 | P8_08_GPIO="67" 72 | P8_08_PIN="gpio" 73 | P8_08_PINMUX="default gpio gpio_pu gpio_pd timer" 74 | P8_08_INFO="gpio2_3 default gpio2_3 gpio2_3 gpio2_3 timer7" 75 | P8_08_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 76 | 77 | P8_09_PRU="101" 78 | P8_09_GPIO="69" 79 | P8_09_PIN="gpio" 80 | P8_09_PINMUX="default gpio gpio_pu gpio_pd timer" 81 | P8_09_INFO="gpio2_5 default gpio2_5 gpio2_5 gpio2_5 timer5" 82 | P8_09_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 83 | 84 | P8_10_PRU="100" 85 | P8_10_GPIO="68" 86 | P8_10_PIN="gpio" 87 | P8_10_PINMUX="default gpio gpio_pu gpio_pd timer" 88 | P8_10_INFO="gpio2_4 default gpio2_4 gpio2_4 gpio2_4 timer6" 89 | P8_10_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 90 | 91 | P8_11_PRU="77" 92 | P8_11_GPIO="45" 93 | P8_11_PIN="gpio" 94 | P8_11_PINMUX="default gpio gpio_pu gpio_pd pruout qep" 95 | P8_11_INFO="gpio1_13 default gpio1_13 gpio1_13 gpio1_13 pr1_pru0_pru_r30_15 eQEP2B_in" 96 | P8_11_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 97 | 98 | P8_12_PRU="76" 99 | P8_12_GPIO="44" 100 | P8_12_PIN="gpio" 101 | P8_12_PINMUX="default gpio gpio_pu gpio_pd pruout qep" 102 | P8_12_INFO="gpio1_12 default gpio1_12 gpio1_12 gpio1_12 pr1_pru0_pru_r30_14 eQEP2A_in" 103 | P8_12_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 104 | 105 | P8_13_PRU="55" 106 | P8_13_GPIO="23" 107 | P8_13_PIN="gpio" 108 | P8_13_PINMUX="default gpio gpio_pu gpio_pd pwm" 109 | P8_13_INFO="gpio0_23 default gpio0_23 gpio0_23 gpio0_23 ehrpwm2B" 110 | P8_13_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 111 | 112 | P8_14_PRU="58" 113 | P8_14_GPIO="26" 114 | P8_14_PIN="gpio" 115 | P8_14_PINMUX="default gpio gpio_pu gpio_pd pwm" 116 | P8_14_INFO="gpio0_26 default gpio0_26 gpio0_26 gpio0_26 ehrpwm2_tripzone_input" 117 | P8_14_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 118 | 119 | P8_15_PRU="79" 120 | P8_15_GPIO="47" 121 | P8_15_PIN="gpio" 122 | P8_15_PINMUX="default gpio gpio_pu gpio_pd pruin pru_ecap qep" 123 | P8_15_INFO="gpio1_15 default gpio1_15 gpio1_15 gpio1_15 pr1_pru0_pru_r31_15 pr1_ecap0_ecap_capin_apwm_o eQEP2_strobe" 124 | P8_15_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 125 | 126 | P8_16_PRU="78" 127 | P8_16_GPIO="46" 128 | P8_16_PIN="gpio" 129 | P8_16_PINMUX="default gpio gpio_pu gpio_pd pruin qep" 130 | P8_16_INFO="gpio1_14 default gpio1_14 gpio1_14 gpio1_14 pr1_pru0_pru_r31_14 eQEP2_index" 131 | P8_16_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 132 | 133 | P8_17_PRU="59" 134 | P8_17_GPIO="27" 135 | P8_17_PIN="gpio" 136 | P8_17_PINMUX="default gpio gpio_pu gpio_pd pwm" 137 | P8_17_INFO="gpio0_27 default gpio0_27 gpio0_27 gpio0_27 ehrpwm0_synco" 138 | P8_17_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 139 | 140 | P8_18_PRU="97" 141 | P8_18_GPIO="65" 142 | P8_18_PIN="gpio" 143 | P8_18_PINMUX="default gpio gpio_pu gpio_pd" 144 | P8_18_INFO="gpio2_1 default gpio2_1 gpio2_1 gpio2_1" 145 | P8_18_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 146 | 147 | P8_19_PRU="54" 148 | P8_19_GPIO="22" 149 | P8_19_PIN="gpio" 150 | P8_19_PINMUX="default gpio gpio_pu gpio_pd pwm" 151 | P8_19_INFO="gpio0_22 default gpio0_22 gpio0_22 gpio0_22 ehrpwm2A" 152 | P8_19_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 153 | 154 | P8_20_PRU="95" 155 | P8_20_GPIO="63" 156 | P8_20_PIN="emmc" 157 | P8_20_PINMUX="default gpio gpio_pu gpio_pd pruout pruin" 158 | P8_20_INFO="mmc1_cmd default gpio1_31 gpio1_31 gpio1_31 pr1_pru1_pru_r30_13 pr1_pru1_pru_r31_13" 159 | P8_20_CAPE="cape-universala cape-univ-emmc" 160 | 161 | P8_21_PRU="94" 162 | P8_21_GPIO="62" 163 | P8_21_PIN="emmc" 164 | P8_21_PINMUX="default gpio gpio_pu gpio_pd pruout pruin" 165 | P8_21_INFO="mmc1_clk default gpio1_30 gpio1_30 gpio1_30 pr1_pru1_pru_r30_12 pr1_pru1_pru_r31_12" 166 | P8_21_CAPE="cape-universala cape-univ-emmc" 167 | 168 | P8_22_PRU="69" 169 | P8_22_GPIO="37" 170 | P8_22_PIN="emmc" 171 | P8_22_PINMUX="default gpio gpio_pu gpio_pd" 172 | P8_22_INFO="mmc1_dat5 default gpio1_5 gpio1_5 gpio1_5" 173 | P8_22_CAPE="cape-universala cape-univ-emmc" 174 | 175 | P8_23_PRU="68" 176 | P8_23_GPIO="36" 177 | P8_23_PIN="emmc" 178 | P8_23_PINMUX="default gpio gpio_pu gpio_pd" 179 | P8_23_INFO="mmc1_dat4 default gpio1_4 gpio1_4 gpio1_4" 180 | P8_23_CAPE="cape-universala cape-univ-emmc" 181 | 182 | P8_24_PRU="65" 183 | P8_24_GPIO="33" 184 | P8_24_PIN="emmc" 185 | P8_24_PINMUX="default gpio gpio_pu gpio_pd" 186 | P8_24_INFO="mmc1_dat1 default gpio1_1 gpio1_1 gpio1_1" 187 | P8_24_CAPE="cape-universala cape-univ-emmc" 188 | 189 | P8_25_PRU="64" 190 | P8_25_GPIO="32" 191 | P8_25_PIN="emmc" 192 | P8_25_PINMUX="default gpio gpio_pu gpio_pd" 193 | P8_25_INFO="mmc1_dat0 default gpio1_0 gpio1_0 gpio1_0" 194 | P8_25_CAPE="cape-universala cape-univ-emmc" 195 | 196 | P8_26_PRU="93" 197 | P8_26_GPIO="61" 198 | P8_26_PIN="gpio" 199 | P8_26_PINMUX="default gpio gpio_pu gpio_pd" 200 | P8_26_INFO="gpio1_29 default gpio1_29 gpio1_29 gpio1_29" 201 | P8_26_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 202 | 203 | P8_27_PRU="118" 204 | P8_27_GPIO="86" 205 | P8_27_PIN="hdmi" 206 | P8_27_PINMUX="default gpio gpio_pu gpio_pd pruout pruin" 207 | P8_27_INFO="lcd_vsync default gpio2_22 gpio2_22 gpio2_22 pr1_pru1_pru_r30_8 pr1_pru1_pru_r31_8" 208 | P8_27_CAPE="cape-universala cape-univ-hdmi cape-universalh" 209 | 210 | P8_28_PRU="120" 211 | P8_28_GPIO="88" 212 | P8_28_PIN="hdmi" 213 | P8_28_PINMUX="default gpio gpio_pu gpio_pd pruout pruin" 214 | P8_28_INFO="lcd_pclk default gpio2_24 gpio2_24 gpio2_24 pr1_pru1_pru_r30_10 pr1_pru1_pru_r31_10" 215 | P8_28_CAPE="cape-universala cape-univ-hdmi cape-universalh" 216 | 217 | P8_29_PRU="119" 218 | P8_29_GPIO="87" 219 | P8_29_PIN="hdmi" 220 | P8_29_PINMUX="default gpio gpio_pu gpio_pd pruout pruin" 221 | P8_29_INFO="lcd_hsync default gpio2_23 gpio2_23 gpio2_23 pr1_pru1_pru_r30_9 pr1_pru1_pru_r31_9" 222 | P8_29_CAPE="cape-universala cape-univ-hdmi cape-universalh" 223 | 224 | P8_30_PRU="121" 225 | P8_30_GPIO="89" 226 | P8_30_PIN="hdmi" 227 | P8_30_PINMUX="default gpio gpio_pu gpio_pd pruout pruin" 228 | P8_30_INFO="lcd_ac_bias_en default gpio2_25 gpio2_25 gpio2_25 pr1_pru1_pru_r30_11 pr1_pru1_pru_r31_11" 229 | P8_30_CAPE="cape-universala cape-univ-hdmi cape-universalh" 230 | 231 | P8_31_PRU="42" 232 | P8_31_GPIO="10" 233 | P8_31_PIN="hdmi" 234 | P8_31_PINMUX="default gpio gpio_pu gpio_pd uart qep" 235 | P8_31_INFO="lcd_data14 default gpio0_10 gpio0_10 gpio0_10 uart5_ctsn eQEP1_index" 236 | P8_31_CAPE="cape-universala cape-univ-hdmi cape-universalh" 237 | 238 | P8_32_PRU="43" 239 | P8_32_GPIO="11" 240 | P8_32_PIN="hdmi" 241 | P8_32_PINMUX="default gpio gpio_pu gpio_pd uart qep" 242 | P8_32_INFO="lcd_data15 default gpio0_11 gpio0_11 gpio0_11 uart5_rtsn eQEP1_strobe" 243 | P8_32_CAPE="cape-universala cape-univ-hdmi cape-universalh" 244 | 245 | P8_33_PRU="41" 246 | P8_33_GPIO="9" 247 | P8_33_PIN="hdmi" 248 | P8_33_PINMUX="default gpio gpio_pu gpio_pd qep" 249 | P8_33_INFO="lcd_data13 default gpio0_9 gpio0_9 gpio0_9 eQEP1B_in" 250 | P8_33_CAPE="cape-universala cape-univ-hdmi cape-universalh" 251 | 252 | P8_34_PRU="113" 253 | P8_34_GPIO="81" 254 | P8_34_PIN="hdmi" 255 | P8_34_PINMUX="default gpio gpio_pu gpio_pd pwm" 256 | P8_34_INFO="lcd_data11 default gpio2_17 gpio2_17 gpio2_17 ehrpwm1B" 257 | P8_34_CAPE="cape-universala cape-univ-hdmi cape-universalh" 258 | 259 | P8_35_PRU="40" 260 | P8_35_GPIO="8" 261 | P8_35_PIN="hdmi" 262 | P8_35_PINMUX="default gpio gpio_pu gpio_pd qep" 263 | P8_35_INFO="lcd_data12 default gpio0_8 gpio0_8 gpio0_8 eQEP1A_in" 264 | P8_35_CAPE="cape-universala cape-univ-hdmi cape-universalh" 265 | 266 | P8_36_PRU="112" 267 | P8_36_GPIO="80" 268 | P8_36_PIN="hdmi" 269 | P8_36_PINMUX="default gpio gpio_pu gpio_pd pwm" 270 | P8_36_INFO="lcd_data10 default gpio2_16 gpio2_16 gpio2_16 ehrpwm1A" 271 | P8_36_CAPE="cape-universala cape-univ-hdmi cape-universalh" 272 | 273 | P8_37_PRU="110" 274 | P8_37_GPIO="78" 275 | P8_37_PIN="hdmi" 276 | P8_37_PINMUX="default gpio gpio_pu gpio_pd uart pwm" 277 | P8_37_INFO="lcd_data8 default gpio2_14 gpio2_14 gpio2_14 uart5_txd ehrpwm1_tripzone_input" 278 | P8_37_CAPE="cape-universala cape-univ-hdmi cape-universalh" 279 | 280 | P8_38_PRU="111" 281 | P8_38_GPIO="79" 282 | P8_38_PIN="hdmi" 283 | P8_38_PINMUX="default gpio gpio_pu gpio_pd uart pwm" 284 | P8_38_INFO="lcd_data9 default gpio2_15 gpio2_15 gpio2_15 uart5_rxd ehrpwm0_synco" 285 | P8_38_CAPE="cape-universala cape-univ-hdmi cape-universalh" 286 | 287 | P8_39_PRU="108" 288 | P8_39_GPIO="76" 289 | P8_39_PIN="hdmi" 290 | P8_39_PINMUX="default gpio gpio_pu gpio_pd pruout pruin qep" 291 | P8_39_INFO="lcd_data6 default gpio2_12 gpio2_12 gpio2_12 pr1_pru1_pru_r30_6 pr1_pru1_pru_r31_6 eQEP2_index" 292 | P8_39_CAPE="cape-universala cape-univ-hdmi cape-universalh" 293 | 294 | P8_40_PRU="109" 295 | P8_40_GPIO="77" 296 | P8_40_PIN="hdmi" 297 | P8_40_PINMUX="default gpio gpio_pu gpio_pd pruout pruin qep" 298 | P8_40_INFO="lcd_data7 default gpio2_13 gpio2_13 gpio2_13 pr1_pru1_pru_r30_7 pr1_pru1_pru_r31_7 eQEP2_strobe" 299 | P8_40_CAPE="cape-universala cape-univ-hdmi cape-universalh" 300 | 301 | P8_41_PRU="106" 302 | P8_41_GPIO="74" 303 | P8_41_PIN="hdmi" 304 | P8_41_PINMUX="default gpio gpio_pu gpio_pd pruout pruin qep" 305 | P8_41_INFO="lcd_data4 default gpio2_10 gpio2_10 gpio2_10 pr1_pru1_pru_r30_4 pr1_pru1_pru_r31_4 eQEP2A_in" 306 | P8_41_CAPE="cape-universala cape-univ-hdmi cape-universalh" 307 | 308 | P8_42_PRU="107" 309 | P8_42_GPIO="75" 310 | P8_42_PIN="hdmi" 311 | P8_42_PINMUX="default gpio gpio_pu gpio_pd pruout pruin qep" 312 | P8_42_INFO="lcd_data5 default gpio2_11 gpio2_11 gpio2_11 pr1_pru1_pru_r30_5 pr1_pru1_pru_r31_5 eQEP2A_in" 313 | P8_42_CAPE="cape-universala cape-univ-hdmi cape-universalh" 314 | 315 | P8_43_PRU="104" 316 | P8_43_GPIO="72" 317 | P8_43_PIN="hdmi" 318 | P8_43_PINMUX="default gpio gpio_pu gpio_pd pruout pruin pwm" 319 | P8_43_INFO="lcd_data2 default gpio2_8 gpio2_8 gpio2_8 pr1_pru1_pru_r30_2 pr1_pru1_pru_r31_2 ehrpwm2_tripzone_input" 320 | P8_43_CAPE="cape-universala cape-univ-hdmi cape-universalh" 321 | 322 | P8_44_PRU="105" 323 | P8_44_GPIO="73" 324 | P8_44_PIN="hdmi" 325 | P8_44_PINMUX="default gpio gpio_pu gpio_pd pruout pruin pwm" 326 | P8_44_INFO="lcd_data3 default gpio2_9 gpio2_9 gpio2_9 pr1_pru1_pru_r30_3 pr1_pru1_pru_r31_3 ehrpwm0_synco" 327 | P8_44_CAPE="cape-universala cape-univ-hdmi cape-universalh" 328 | 329 | P8_45_PRU="102" 330 | P8_45_GPIO="70" 331 | P8_45_PIN="hdmi" 332 | P8_45_PINMUX="default gpio gpio_pu gpio_pd pruout pruin pwm" 333 | P8_45_INFO="lcd_data0 default gpio2_6 gpio2_6 gpio2_6 pr1_pru1_pru_r30_0 pr1_pru1_pru_r31_0 ehrpwm2A" 334 | P8_45_CAPE="cape-universala cape-univ-hdmi cape-universalh" 335 | 336 | P8_46_PRU="103" 337 | P8_46_GPIO="71" 338 | P8_46_PIN="hdmi" 339 | P8_46_PINMUX="default gpio gpio_pu gpio_pd pruout pruin pwm" 340 | P8_46_INFO="lcd_data1 default gpio2_7 gpio2_7 gpio2_7 pr1_pru1_pru_r30_1 pr1_pru1_pru_r31_1 ehrpwm2B" 341 | P8_46_CAPE="cape-universala cape-univ-hdmi cape-universalh" 342 | 343 | P9_01_PIN="gnd" 344 | P9_01_INFO="GND" 345 | P9_01_CAPE="" 346 | 347 | P9_02_PIN="gnd" 348 | P9_02_INFO="GND" 349 | P9_02_CAPE="" 350 | 351 | P9_03_PIN="power" 352 | P9_03_INFO="3V3" 353 | P9_03_CAPE="" 354 | 355 | P9_04_PIN="power" 356 | P9_04_INFO="3V3" 357 | P9_04_CAPE="" 358 | 359 | P9_05_PIN="power" 360 | P9_05_INFO="VDD_5V" 361 | P9_05_CAPE="" 362 | 363 | P9_06_PIN="power" 364 | P9_06_INFO="VDD_5V" 365 | P9_06_CAPE="" 366 | 367 | P9_07_PIN="power" 368 | P9_07_INFO="SYS_5V" 369 | P9_07_CAPE="" 370 | 371 | P9_08_PIN="power" 372 | P9_08_INFO="SYS_5V" 373 | P9_08_CAPE="" 374 | 375 | P9_09_PIN="system" 376 | P9_09_INFO="PWR_BUT" 377 | P9_09_CAPE="" 378 | 379 | P9_10_PIN="system" 380 | P9_10_INFO="RSTn" 381 | P9_10_CAPE="" 382 | 383 | P9_11_PRU="62" 384 | P9_11_GPIO="30" 385 | P9_11_PIN="gpio" 386 | P9_11_PINMUX="default gpio gpio_pu gpio_pd uart" 387 | P9_11_INFO="gpio0_30 default gpio0_30 gpio0_30 gpio0_30 uart4_rxd" 388 | P9_11_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 389 | 390 | P9_12_PRU="92" 391 | P9_12_GPIO="60" 392 | P9_12_PIN="gpio" 393 | P9_12_PINMUX="default gpio gpio_pu gpio_pd" 394 | P9_12_INFO="gpio1_28 default gpio1_28 gpio1_28 gpio1_28" 395 | P9_12_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 396 | 397 | P9_13_PRU="63" 398 | P9_13_GPIO="31" 399 | P9_13_PIN="gpio" 400 | P9_13_PINMUX="default gpio gpio_pu gpio_pd uart" 401 | P9_13_INFO="gpio0_31 default gpio0_31 gpio0_31 gpio0_31 uart4_txd" 402 | P9_13_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 403 | 404 | P9_14_PRU="82" 405 | P9_14_GPIO="50" 406 | P9_14_PIN="gpio" 407 | P9_14_PINMUX="default gpio gpio_pu gpio_pd pwm" 408 | P9_14_INFO="gpio1_18 default gpio1_18 gpio1_18 gpio1_18 ehrpwm1A" 409 | P9_14_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 410 | 411 | P9_15_PRU="80" 412 | P9_15_GPIO="48" 413 | P9_15_PIN="gpio" 414 | P9_15_PINMUX="default gpio gpio_pu gpio_pd pwm" 415 | P9_15_INFO="gpio1_16 default gpio1_16 gpio1_16 gpio1_16 ehrpwm1_tripzone_input" 416 | P9_15_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 417 | 418 | P9_16_PRU="83" 419 | P9_16_GPIO="51" 420 | P9_16_PIN="gpio" 421 | P9_16_PINMUX="default gpio gpio_pu gpio_pd pwm" 422 | P9_16_INFO="gpio1_19 default gpio1_19 gpio1_19 gpio1_19 ehrpwm1B" 423 | P9_16_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 424 | 425 | P9_17_PRU="37" 426 | P9_17_GPIO="5" 427 | P9_17_PIN="gpio" 428 | P9_17_PINMUX="default gpio gpio_pu gpio_pd spi i2c pwm pru_uart" 429 | P9_17_INFO="gpio0_5 default gpio0_5 gpio0_5 gpio0_5 spi0_cs0 i2c1_scl ehrpwm0_synci pr1_uart0_txd" 430 | P9_17_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 431 | 432 | P9_18_PRU="36" 433 | P9_18_GPIO="4" 434 | P9_18_PIN="gpio" 435 | P9_18_PINMUX="default gpio gpio_pu gpio_pd spi i2c pwm pru_uart" 436 | P9_18_INFO="gpio0_4 default gpio0_4 gpio0_4 gpio0_4 spi0_d1 i2c1_sda ehrpwm0_tripzone_input pr1_uart0_rxd" 437 | P9_18_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 438 | 439 | P9_19_PRU="45" 440 | P9_19_GPIO="13" 441 | P9_19_PIN="i2c" 442 | P9_19_INFO="i2c2_scl" 443 | P9_19_CAPE="" 444 | 445 | P9_20_PRU="44" 446 | P9_20_GPIO="12" 447 | P9_20_PIN="i2c" 448 | P9_20_INFO="i2c2_sda" 449 | P9_20_CAPE="" 450 | 451 | P9_21_PRU="35" 452 | P9_21_GPIO="3" 453 | P9_21_PIN="gpio" 454 | P9_21_PINMUX="default gpio gpio_pu gpio_pd spi uart i2c pwm pru_uart" 455 | P9_21_INFO="gpio0_3 default gpio0_3 gpio0_3 gpio0_3 spi0_d0 uart2_txd i2c2_scl ehrpwm0B pr1_uart0_rts_n" 456 | P9_21_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 457 | 458 | P9_22_PRU="34" 459 | P9_22_GPIO="2" 460 | P9_22_PIN="gpio" 461 | P9_22_PINMUX="default gpio gpio_pu gpio_pd spi uart i2c pwm pru_uart" 462 | P9_22_INFO="gpio0_2 default gpio0_2 gpio0_2 gpio0_2 spi0_sclk uart2_rxd i2c2_sda ehrpwm0A pr1_uart0_cts_n" 463 | P9_22_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 464 | 465 | 466 | P9_23_PRU="81" 467 | P9_23_GPIO="49" 468 | P9_23_PIN="gpio" 469 | P9_23_PINMUX="default gpio gpio_pu gpio_pd pwm" 470 | P9_23_INFO="gpio1_17 default gpio1_17 gpio1_17 gpio1_17 ehrpwm0_synco" 471 | P9_23_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 472 | 473 | P9_24_PRU="47" 474 | P9_24_GPIO="15" 475 | P9_24_PIN="gpio" 476 | P9_24_PINMUX="default gpio gpio_pu gpio_pd uart can i2c pru_uart pruin" 477 | P9_24_INFO="gpio0_15 default gpio0_15 gpio0_15 gpio0_15 uart1_txd dcan1_rx i2c1_scl pr1_uart0_txd pr1_pru0_pru_r31_16" 478 | P9_24_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 479 | 480 | P9_25_PRU="149" 481 | P9_25_GPIO="117" 482 | P9_25_PIN="gpio" 483 | P9_25_PINMUX="default gpio gpio_pu gpio_pd qep pruout pruin" 484 | P9_25_INFO="gpio3_21 default gpio3_21 gpio3_21 gpio3_21 eQEP0_strobe pr1_pru0_pru_r30_7 pr1_pru0_pru_r31_7" 485 | P9_25_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 486 | 487 | P9_26_PRU="46" 488 | P9_26_GPIO="14" 489 | P9_26_PIN="gpio" 490 | P9_26_PINMUX="default gpio gpio_pu gpio_pd uart can i2c pru_uart pruin" 491 | P9_26_INFO="gpio0_14 default gpio0_14 gpio0_14 gpio0_14 uart1_rxd dcan1_tx i2c1_sda pr1_uart0_rxd pr1_pru1_pru_r31_16" 492 | P9_26_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 493 | 494 | P9_27_PRU="147" 495 | P9_27_GPIO="115" 496 | P9_27_PIN="gpio" 497 | P9_27_PINMUX="default gpio gpio_pu gpio_pd qep pruout pruin" 498 | P9_27_INFO="gpio3_19 default gpio3_19 gpio3_19 gpio3_19 eQEP0b_in pr1_pru0_pru_r30_5 pr1_pru0_pru_r31_5" 499 | P9_27_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 500 | 501 | P9_28_PRU="145" 502 | P9_28_GPIO="113" 503 | P9_28_PIN="gpio" 504 | P9_28_PINMUX="default gpio gpio_pu gpio_pd pwm spi pwm2 pruout pruin" 505 | P9_28_INFO="gpio3_17 default gpio3_17 gpio3_17 gpio3_17 ehrpwm0_synci spi1_cs0 eCAP2_in_PWM2_out pr1_pru0_pru_r30_3 pr1_pru0_pru_r31_3" 506 | P9_28_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 507 | 508 | P9_29_PRU="143" 509 | P9_29_GPIO="111" 510 | P9_29_PIN="gpio" 511 | P9_29_PINMUX="default gpio gpio_pu gpio_pd pwm spi pruout pruin" 512 | P9_29_INFO="gpio3_15 default gpio3_15 gpio3_15 gpio3_15 ehrpwm0B spi1_d0 pr1_pru0_pru_r30_1 pr1_pru0_pru_r31_1" 513 | P9_29_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 514 | 515 | P9_30_PRU="144" 516 | P9_30_GPIO="112" 517 | P9_30_PIN="gpio" 518 | P9_30_PINMUX="default gpio gpio_pu gpio_pd pwm spi pruout pruin" 519 | P9_30_INFO="gpio3_16 default gpio3_16 gpio3_16 gpio3_16 ehrpwm0_tripzone_input spi1_d1 pr1_pru0_pru_r30_2 pr1_pru0_pru_r31_2" 520 | P9_30_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 521 | 522 | P9_31_PRU="142" 523 | P9_31_GPIO="110" 524 | P9_31_PIN="gpio" 525 | P9_31_PINMUX="default gpio gpio_pu gpio_pd pwm spi pruout pruin" 526 | P9_31_INFO="gpio3_14 default gpio3_14 gpio3_14 gpio3_14 ehrpwm0A spi1_sclk pr1_pru0_pru_r30_0 pr1_pru0_pru_r31_0" 527 | P9_31_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 528 | 529 | P9_32_PIN="power" 530 | P9_32_INFO="VADC" 531 | P9_32_CAPE="" 532 | 533 | P9_33_PIN="adc" 534 | P9_33_INFO="AIN4" 535 | P9_33_CAPE="cape-bone-iio" 536 | 537 | P9_34_PIN="gnd" 538 | P9_34_INFO="AGND" 539 | P9_34_CAPE="" 540 | 541 | P9_35_PIN="adc" 542 | P9_35_INFO="AIN6" 543 | P9_35_CAPE="cape-bone-iio" 544 | 545 | P9_36_PIN="adc" 546 | P9_36_INFO="AIN5" 547 | P9_36_CAPE="cape-bone-iio" 548 | 549 | P9_37_PIN="adc" 550 | P9_37_INFO="AIN2" 551 | P9_37_CAPE="cape-bone-iio" 552 | 553 | P9_38_PIN="adc" 554 | P9_38_INFO="AIN3" 555 | P9_38_CAPE="cape-bone-iio" 556 | 557 | P9_39_PIN="adc" 558 | P9_39_INFO="AIN0" 559 | P9_39_CAPE="cape-bone-iio" 560 | 561 | P9_40_PIN="adc" 562 | P9_40_INFO="AIN1" 563 | P9_40_CAPE="cape-bone-iio" 564 | 565 | P9_41_PRU="52" 566 | P9_41_GPIO="20" 567 | P9_41_PIN="gpio" 568 | P9_41_PINMUX="default gpio gpio_pu gpio_pd timer pruin" 569 | P9_41_INFO="gpio0_20 default gpio0_20,pru:52 gpio0_20 gpio0_20 timer7 pr1_pru0_pru_r31_16" 570 | P9_41_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 571 | 572 | P9_91_PRU="148" 573 | P9_91_GPIO="116" 574 | P9_91_PIN="gpio" 575 | P9_91_PINMUX="default gpio gpio_pu gpio_pd qep pruout pruin" 576 | P9_91_INFO="gpio3_20 default gpio3_20 gpio3_20 gpio3_20 eQEP0_index pr1_pru0_pru_r30_6 pr1_pru0_pru_r31_6" 577 | P9_91_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 578 | 579 | P9_42_PRU="39" 580 | P9_42_GPIO="7" 581 | P9_42_PIN="gpio" 582 | P9_42_PINMUX="default gpio gpio_pu gpio_pd pwm uart spics pru_ecap spiclk" 583 | P9_42_INFO="gpio0_7 default gpio0_7 gpio0_7 gpio0_7 eCAP0_in_PWM0_out uart3_txd spi1_cs1 pr1_ecap0_ecap_capin_apwm_o spi1_sclk" 584 | P9_42_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 585 | 586 | P9_92_PRU="146" 587 | P9_92_GPIO="114" 588 | P9_92_PIN="gpio" 589 | P9_92_PINMUX="default gpio gpio_pu gpio_pd qep pruout pruin" 590 | P9_92_INFO="gpio3_18 default gpio3_18 gpio3_18 gpio3_18 eQEP0A_in pr1_pru0_pru_r30_4 pr1_pru0_pru_r31_4" 591 | P9_92_CAPE="cape-universala cape-universal cape-universaln cape-universalh" 592 | 593 | P9_43_PIN="gnd" 594 | P9_43_INFO="GND" 595 | P9_43_CAPE="" 596 | 597 | P9_44_PIN="gnd" 598 | P9_44_INFO="GND" 599 | P9_44_CAPE="" 600 | 601 | P9_45_PIN="gnd" 602 | P9_45_INFO="GND" 603 | P9_45_CAPE="" 604 | 605 | P9_46_PIN="gnd" 606 | P9_46_INFO="GND" 607 | P9_46_CAPE="" 608 | 609 | 610 | 611 | echo_err () { 612 | echo "$@" 1>&2 613 | } 614 | 615 | echo_std () { 616 | echo "$@" 617 | } 618 | 619 | echo_dbg () { 620 | if [ -n "$DEBUG" ] ; then 621 | echo "$@" 1>&2 622 | fi 623 | } 624 | 625 | usage () { 626 | NAME="$(basename $0)" 627 | cat <<- EOF 628 | $NAME [-a] 629 | Set to , configuring pin multiplexing and optionally 630 | configuring the gpio. Valid strings vary based on , 631 | however all pins have a default and gpio mode. The default mode is 632 | the reset state of the pin, with the pin mux set to gpio, the pull 633 | up/down resistor set to its reset value, and the pin receive buffer 634 | enabled. To setup gpio, the following strings are all valid: 635 | 636 | gpio : 637 | Set pinmux to gpio, existing direction and value unchanged 638 | in | input: 639 | Set pinmux to gpio and set gpio direction to input 640 | out | output : 641 | Set pinmux to gpio and set gpio direction to output 642 | hi | high | 1 : 643 | Set pinmux to gpio and set gpio direction to output driving high 644 | lo | low | 0 : 645 | Set pinmux to gpio and set gpio direction to output driving low 646 | 647 | To enable pull-up or pull-down resistors, a suffix may be appended to 648 | any of the above gpio modes. Use + or _pu to enable the pull-up resistor 649 | and - or _pd to enable the pull-down resistor. Examples: 650 | 651 | in+ | in_pu: 652 | Enable pull-up resistor and setup pin as per input, above. 653 | hi- | hi_pd: 654 | Enable pull-down resistor and setup pin as per high, above. 655 | While the pull-down resistor will be enabled, it will not do much 656 | until application software changes the pin direction to input. 657 | 658 | -a automatically loads missing device tree overlays 659 | 660 | $NAME overlay 661 | loads the device tree overlay 662 | 663 | $NAME -l 664 | list valid values for 665 | 666 | $NAME -i 667 | show information for 668 | 669 | $NAME -q 670 | query pin and report configuration details 671 | 672 | $NAME -f [file] 673 | Read list of pin configurations from file, one per line 674 | Comments and white-space are allowed 675 | With no file, or when file is -, read standard input. 676 | $NAME -h 677 | Display this help text 678 | 679 | EOF 680 | } 681 | 682 | # Be friendly about pin naming conventions 683 | # $1 = Pin name 684 | fixup_pin () { 685 | local PIN 686 | # Use ash-friendly substitutions: ${ % } ${ # } 687 | case "$1" in 688 | [pP]*) X="${1#?}" ;; 689 | *) X="$1" ;; 690 | esac 691 | 692 | case "$X" in 693 | # There is no pin 00 694 | *00) echo_err "Invalid pin: $1" 695 | exit 1 696 | ;; 697 | # Missing separator, single digit pin number 698 | [89][1-9]) 699 | PIN=P${X%?}_0${X#?} 700 | ;; 701 | # Missing separator, two digit pin number 702 | [89][0-49][0-9]) 703 | PIN=P${X%??}_${X#?} 704 | ;; 705 | # Single digit pin number 706 | [89][!0-9][1-9]) 707 | PIN=P${X%??}_0${X#??} 708 | ;; 709 | # Two digit pin number 710 | [89][!0-9][0-49][0-9]) 711 | PIN=P${X%???}_${X#??} 712 | ;; 713 | # Anything else is an error 714 | *) echo_err "Invalid pin: \"$1\" \"$X\"" 715 | exit 1 716 | ;; 717 | esac 718 | 719 | echo $PIN 720 | } 721 | 722 | # Be friendly about overlay naming conventions 723 | # $1 = Overlay name 724 | fixup_overlay () { 725 | case "$1" in 726 | [oO][vV]|[oO][vV][eE][rR][lL][aA][yY]) 727 | echo "1" 728 | ;; 729 | [cC][aA][pP][eE]) 730 | echo "1" 731 | ;; 732 | *) echo "0" 733 | ;; 734 | esac 735 | } 736 | 737 | # List the default mode value 738 | # $1 = Pin Name 739 | listmode () { 740 | PIN=$(fixup_pin $1) 741 | eval MODES="\$${PIN}_PIN" 742 | if [ -z "$MODES" ] ; then 743 | echo_err "Unknown pin name: $1" 744 | exit 1 745 | else 746 | echo "$MODES" 747 | fi 748 | } 749 | 750 | # List the legal mode values for a pin 751 | # $1 = Pin Name 752 | listmodes () { 753 | PIN=$(fixup_pin $1) 754 | eval MODES="\$${PIN}_PINMUX" 755 | eval INFO="\$${PIN}_INFO" 756 | if [ -z "$MODES" ] ; then 757 | echo_err "Pin is not modifyable: $1 $INFO" 758 | exit 1 759 | else 760 | echo "$MODES" 761 | fi 762 | } 763 | 764 | # List the capes for a pin 765 | # $1 = Pin Name 766 | listcape () { 767 | PIN=$(fixup_pin $1) 768 | eval CAPE="\$${PIN}_CAPE" 769 | if [ -z "$CAPE" ] ; then 770 | echo_err "Pin has no cape: $1" 771 | exit 1 772 | else 773 | echo "$CAPE" 774 | fi 775 | } 776 | 777 | # List info for a pin 778 | # $1 = Pin Name 779 | listinfo () { 780 | PIN=$(fixup_pin $1) 781 | eval INFO="\$${PIN}_INFO" 782 | echo "$INFO" 783 | } 784 | 785 | # List the kernel GPIO id for a pin 786 | # $1 = Pin Name 787 | listgpio () { 788 | PIN=$(fixup_pin $1) 789 | eval GPIO="\$${PIN}_GPIO" 790 | echo "$GPIO" 791 | } 792 | 793 | # List ther PRU GPIO id for a pin 794 | # $1 = Pin Name 795 | listpru () { 796 | PIN=$(fixup_pin $1) 797 | eval PRU="\$${PIN}_PRU" 798 | echo "$PRU" 799 | } 800 | 801 | # List current pin settings 802 | # $1 = Pin name 803 | query_pin () { 804 | set -e 805 | PIN=$(fixup_pin $1) 806 | MODES="$(listmodes $PIN)" 807 | 808 | check_pin $PIN 809 | 810 | if [ -d /sys/devices/platform/bone_capemgr/ ] ; then 811 | # Expand filename using shell globbing 812 | for FILE in $OCPDIR${PIN}_pinmux/state ; do 813 | if [ -r $FILE ] ; then 814 | read MODE JUNK < $FILE 815 | else 816 | echo_err "Cannot read pinmux file: $FILE" 817 | exit 1 818 | fi 819 | done 820 | else 821 | # Expand filename using shell globbing 822 | for FILE in $OCPDIR/${PIN}_pinmux.*/state ; do 823 | if [ -r $FILE ] ; then 824 | read MODE JUNK < $FILE 825 | else 826 | echo_err "Cannot read pinmux file: $FILE" 827 | exit 1 828 | fi 829 | done 830 | fi 831 | 832 | case "$MODE" in 833 | default|gpio*) 834 | VALUE=pin_not_exported 835 | DIR=pin_not_exported 836 | eval GPIO="\$${PIN}_GPIO" 837 | FILE="$GPIODIR/gpio$GPIO/value" 838 | [ -r $FILE ] && read VALUE JUNK < $FILE 839 | FILE="$GPIODIR/gpio$GPIO/direction" 840 | [ -r $FILE ] && read DIR JUNK < $FILE 841 | echo "$PIN Mode: $MODE Direction: $DIR Value: $VALUE" 842 | ;; 843 | *) echo "$PIN Mode: $MODE" 844 | ;; 845 | esac 846 | } 847 | 848 | # Show information to a specific pin 849 | # $1 = Pin name 850 | show_pin () { 851 | set -e 852 | PIN=$(fixup_pin $1) 853 | MODE="$(listmode $PIN)" 854 | MODES="$(listmodes $PIN)" 855 | CAPE="$(listcape $PIN)" 856 | INFO="$(listinfo $PIN)" 857 | GPIOID="$(listgpio $PIN)" 858 | PRUID="$(listpru $PIN)" 859 | 860 | echo Pin name: $PIN 861 | echo Function if no cape loaded: $MODE 862 | echo Function if cape loaded: $MODES 863 | echo Function information: $INFO 864 | echo Cape: $CAPE 865 | echo Kernel GPIO id: $GPIOID 866 | echo PRU GPIO id: $PRUID 867 | } 868 | 869 | # Load a installed cape 870 | # $1 cape to load 871 | load_cape () { 872 | # Make sure required device tree overlay(s) are loaded 873 | # cape-bone-iio 874 | for DTBO in $1 ; do 875 | 876 | if grep -q $DTBO $SLOTS ; then 877 | echo_std $DTBO already loaded 878 | else 879 | # Expand filename using shell globbing 880 | for FILE in $SLOTS ; do 881 | echo_std Loading $DTBO overlay 882 | sudo -A bash -c "echo $DTBO > $SLOTS" || (echo_err "Error loading device tree overlay file: $DTBO" && exit 1) 883 | sleep 1 884 | done 885 | fi 886 | done; 887 | } 888 | 889 | # Check whether support for a specific pin is loaded or not 890 | # $1 pin to check 891 | check_pin () { 892 | if [ -e $OCPDIR/${PIN}_pinmux.* ] ; then 893 | echo_dbg $1 pinmux file found 894 | elif [ -e $OCPDIR${PIN}_pinmux ] ; then 895 | echo_dbg $1 pinmux file found 896 | else 897 | echo_err $1 pinmux file not found! 898 | 899 | CAPE="$(listcape $1)" 900 | # use only first overlay 901 | CAPE=`echo "$CAPE" | cut -d' ' -f1` 902 | 903 | if [ $AUTOLOAD -eq 0 ] ; then 904 | if [ -e $SLOTS ] ; then 905 | echo_err "$CAPE overlay not found" 906 | echo_err "run \"$(basename $0) overlay $CAPE\" to load the cape" 907 | else 908 | echo_err "Please verify your device tree file" 909 | fi 910 | exit 1 911 | else 912 | echo_std $1 overlay not found 913 | load_cape $CAPE 914 | fi 915 | fi 916 | } 917 | 918 | # Configure a single pin 919 | # $1 = Pin name 920 | # $2 = Pin mode 921 | config_pin () { 922 | set -e 923 | OVERLAY=$(fixup_overlay $1) 924 | 925 | if [ $OVERLAY = "1" ] ; then 926 | load_cape $2 927 | else 928 | PIN=$(fixup_pin $1) 929 | 930 | MODE="$(listmode $PIN)" 931 | MODES="$(listmodes $PIN)" 932 | DIR="" 933 | 934 | check_pin $PIN 935 | 936 | case $2 in 937 | # Map special GPIO setup modes to gpio with direction set 938 | 939 | # GPIO with pull-up/down disabled 940 | [iI][nN]|[iI][nN][pP][uU][tT]) 941 | MODE=gpio; 942 | DIR=in 943 | ;; 944 | [oO][uU][tT]|[oO][uU][tT][pP][uU][tT]) 945 | MODE=gpio; 946 | DIR=out 947 | ;; 948 | [lL][oO]|[lL][oO][wW]|0) 949 | MODE=gpio; 950 | DIR=low 951 | ;; 952 | [hH][iI]|[hH][iI][gG][hH]|1) 953 | MODE=gpio; 954 | DIR=high 955 | ;; 956 | 957 | # GPIO with pull-down enabled 958 | [iI][nN]-|[iI][nN][pP][uU][tT]-|[iI][nN][-_][pP][dD]|[iI][nN][pP][dD][tT][-_][pP][dD]) 959 | MODE=gpio_pd; 960 | DIR=in 961 | ;; 962 | [oO][uU][tT]-|[oO][uU][tT][pP][uU][tT]-|[oO][uU][tT][-_][pP][dD]|[oO][uU][tT][pP][uU][tT][-_][pP][dD]) 963 | MODE=gpio_pd; 964 | DIR=out 965 | ;; 966 | [lL][oO]-|[lL][oO][wW]-|0-|[lL][oO][-_][pP][dD]|[lL][oO][wW][-_][pP][dD]|0[-_][pP][dD]) 967 | MODE=gpio_pd; 968 | DIR=low 969 | ;; 970 | [hH][iI]-|[hH][iI][gG][hH]-|1-|[hH][iI][-_][pP][dD]|[hH][iI][gG][hH][-_][pP][dD]|1[-_][pP][dD]) 971 | MODE=gpio_pd; 972 | DIR=high 973 | ;; 974 | 975 | # GPIO with pull-up enabled 976 | [iI][nN]+|[iI][nN][pP][uU][tT]+|[iI][nN][-_][pP][uU]|[iI][nN][pP][uU][tT][-_][pP][uU]) 977 | MODE=gpio_pu; 978 | DIR=in 979 | ;; 980 | [oO][uU][tT]+|[oO][uU][tT][pP][uU][tT]+|[oO][uU][tT][-_][pP][uU]|[oO][uU][tT][pP][uU][tT][-_][pP][uU]) 981 | MODE=gpio_pu; 982 | DIR=out 983 | ;; 984 | [lL][oO]+|[lL][oO][wW]+|0+|[lL][oO][-_][pP][uU]|[lL][oO][wW][-_][pP][uU]|0[-_][pP][uU]) 985 | MODE=gpio_pu; 986 | DIR=low 987 | ;; 988 | [hH][iI]+|[hH][iI][gG][hH]+|1+|[hH][iI][-_][pP][uU]|[hH][iI][gG][hH][-_][pP][uU]|1[-_][pP][uU]) 989 | MODE=gpio_pd; 990 | DIR=high 991 | ;; 992 | 993 | # Check to make sure the provided mode is legal 994 | *) MODE="$2"; DIR="" 995 | FOUND=0 996 | set -- $MODES 997 | while [ $# -gt 0 ] ; do 998 | if [ "$MODE" = "$1" ] ; then 999 | FOUND=1 1000 | break 1001 | fi 1002 | shift 1003 | done 1004 | 1005 | if [ $FOUND != 1 ] ; then 1006 | echo_err "Invalid mode: $MODE" 1007 | exit 1 1008 | fi 1009 | esac 1010 | 1011 | echo_dbg "PIN: \"$PIN\" MODE: \"$MODE\" DIR: \"$DIR\"" 1012 | 1013 | if [ -n "$DIR" ] ; then 1014 | eval GPIO="\$${PIN}_GPIO" 1015 | FILE="$GPIODIR/gpio$GPIO/direction" 1016 | if [ -e $FILE ] ; then 1017 | sudo -A bash -c "echo $DIR > $FILE" || (echo_err "Cannot write gpio direction file: $FILE" && exit 1) 1018 | else 1019 | echo_err "WARNING: GPIO pin not exported, cannot set direction or value!" 1020 | fi 1021 | fi 1022 | 1023 | if [ -d /sys/devices/platform/bone_capemgr/ ] ; then 1024 | # Expand filename using shell globbing 1025 | for FILE in $OCPDIR${PIN}_pinmux/state ; do 1026 | echo_dbg "echo $MODE > $FILE" 1027 | sudo -A bash -c "echo $MODE > $FILE" || (echo_err "Cannot write pinmux file: $FILE" && exit 1) 1028 | done 1029 | else 1030 | # Expand filename using shell globbing 1031 | for FILE in $OCPDIR/${PIN}_pinmux.*/state ; do 1032 | echo_dbg "echo $MODE > $FILE" 1033 | sudo -A bash -c "echo $MODE > $FILE" || (echo_err "Cannot write pinmux file: $FILE" && exit 1) 1034 | done 1035 | fi 1036 | fi 1037 | } 1038 | 1039 | # Read a file containing pin setup tuples and optional comments and whitespace 1040 | # $1 filename to read 1041 | readfile () { 1042 | case $1 in 1043 | # Use standard in 1044 | ""|-) exec 3<&0 ;; 1045 | 1046 | # Use actual file 1047 | *) if [ ! -r "$1" ] ; then 1048 | echo_err "Cannot read file: $1" 1049 | exit 1 1050 | fi 1051 | exec 3< $1 1052 | ;; 1053 | esac 1054 | 1055 | while read PIN MODE JUNK ; do 1056 | case $PIN in 1057 | ""|\#*) continue ;; 1058 | *) config_pin $PIN $MODE ;; 1059 | esac 1060 | done <&3 1061 | 1062 | } 1063 | 1064 | # main () 1065 | 1066 | DEBUG="" 1067 | CMD="" 1068 | CMDARG="" 1069 | AUTOLOAD=0 1070 | 1071 | while getopts adfhl:q:i: opt ; do 1072 | case $opt in 1073 | d) [ "$DEBUG" = 1 ] && set -x 1074 | DEBUG=1 1075 | ;; 1076 | a) AUTOLOAD=1 1077 | ;; 1078 | l) CMD=list 1079 | CMDARG="$OPTARG" 1080 | ;; 1081 | i) CMD=info 1082 | CMDARG="$OPTARG" 1083 | ;; 1084 | q) CMD=query 1085 | CMDARG="$OPTARG" 1086 | ;; 1087 | f) CMD=file 1088 | ;; 1089 | \?) usage 1090 | exit 1 1091 | ;; 1092 | esac 1093 | done 1094 | 1095 | shift `expr $OPTIND - 1` 1096 | 1097 | echo_dbg AUTOLOAD=$AUTOLOAD 1098 | echo_dbg "Args: $@" 1099 | 1100 | case $CMD in 1101 | list) listmodes "$CMDARG" ;; 1102 | info) show_pin "$CMDARG" ;; 1103 | query) query_pin "$CMDARG" ;; 1104 | file) readfile "$@" ;; 1105 | *) if [ $# -ne 2 ] ; then 1106 | usage 1107 | exit 1 1108 | else 1109 | config_pin "$1" "$2" 1110 | fi 1111 | ;; 1112 | esac 1113 | 1114 | exit 0 1115 | 1116 | --------------------------------------------------------------------------------