├── .gitignore ├── .vscode └── settings.json ├── README.md ├── rtl ├── CONFREG │ └── confreg.v ├── axi_wrap │ └── axi_wrap.v ├── myCPU │ ├── EXE_stage.v │ ├── ID_stage.v │ ├── IF_stage.v │ ├── MEM_stage.v │ ├── WB_stage.v │ ├── alu.v │ ├── cp0.v │ ├── mycpu.h │ ├── mycpu_core.v │ ├── mycpu_top.v │ ├── pre_IF_stage.v │ ├── regfile.v │ ├── tlb_mmu.v │ ├── tools.v │ └── transfer_bridge.v ├── ram_wrap │ └── axi_wrap_ram.v ├── soc_axi_lite_top.v └── xilinx_ip │ ├── axi_crossbar_1x2 │ └── axi_crossbar_1x2.xci │ ├── axi_ram │ └── axi_ram.xci │ ├── clk_pll │ └── clk_pll.xci │ ├── signed_divider │ └── signed_divider.xci │ └── unsigned_divider │ └── unsigned_divider.xci ├── run_vivado ├── mycpu_prj1 │ ├── mycpu.xpr │ └── tb_top_behav.wcfg └── soc_lite.xdc └── testbench └── mycpu_tb.v /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cebarobot/UCAS-CALab-mycpu_axi_verify/HEAD/.gitignore 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