├── .gitignore ├── LICENSE ├── README.md ├── rtl ├── BRIDGE │ └── bridge_1x2.v ├── CONFREG │ └── confreg.v ├── myCPU │ ├── EXE_stage.v │ ├── ID_stage.v │ ├── IF_stage.v │ ├── MEM_stage.v │ ├── WB_stage.v │ ├── alu.v │ ├── cp0.v │ ├── mycpu.h │ ├── mycpu_top.v │ ├── regfile.v │ └── tools.v ├── soc_lite_top.v └── xilinx_ip │ ├── clk_pll │ ├── clk_pll.dcp │ ├── clk_pll.v │ ├── clk_pll.xci │ ├── clk_pll.xdc │ ├── clk_pll.xml │ ├── clk_pll_board.xdc │ ├── clk_pll_clk_wiz.v │ ├── clk_pll_ooc.xdc │ ├── clk_pll_sim_netlist.v │ ├── clk_pll_sim_netlist.vhdl │ ├── clk_pll_stub.v │ ├── clk_pll_stub.vhdl │ └── doc │ │ └── clk_wiz_v6_0_changelog.txt │ ├── data_ram │ ├── data_ram.dcp │ ├── data_ram.xci │ ├── data_ram.xml │ ├── data_ram_ooc.xdc │ ├── data_ram_sim_netlist.v │ ├── data_ram_sim_netlist.vhdl │ ├── data_ram_stub.v │ ├── data_ram_stub.vhdl │ ├── doc │ │ └── blk_mem_gen_v8_4_changelog.txt │ ├── hdl │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ ├── misc │ │ └── blk_mem_gen_v8_4.vhd │ ├── sim │ │ └── data_ram.v │ ├── simulation │ │ └── blk_mem_gen_v8_4.v │ └── synth │ │ └── data_ram.vhd │ └── inst_ram │ ├── doc │ └── blk_mem_gen_v8_4_changelog.txt │ ├── hdl │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ ├── inst_ram.dcp │ ├── inst_ram.xci │ ├── inst_ram.xml │ ├── inst_ram_ooc.xdc │ ├── inst_ram_sim_netlist.v │ ├── inst_ram_sim_netlist.vhdl │ ├── inst_ram_stub.v │ ├── inst_ram_stub.vhdl │ ├── misc │ └── blk_mem_gen_v8_4.vhd │ ├── sim │ └── inst_ram.v │ ├── simulation │ └── blk_mem_gen_v8_4.v │ └── synth │ └── inst_ram.vhd ├── run_vivado ├── mycpu_prj1 │ ├── mycpu_prj1.hw │ │ └── hw_1 │ │ │ └── hw.xml │ ├── mycpu_prj1.ip_user_files │ │ ├── README.txt │ │ ├── ip │ │ │ ├── clk_pll │ │ │ │ ├── clk_pll_stub.v │ │ │ │ └── clk_pll_stub.vhdl │ │ │ ├── data_ram │ │ │ │ ├── data_ram_stub.v │ │ │ │ └── data_ram_stub.vhdl │ │ │ └── inst_ram │ │ │ │ ├── inst_ram_stub.v │ │ │ │ └── inst_ram_stub.vhdl │ │ ├── ipstatic │ │ │ ├── hdl │ │ │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ │ │ ├── div_gen_v5_1_vh_rfs.vhd │ │ │ │ ├── floating_point_v7_0_vh_rfs.vhd │ │ │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_mult_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ └── simulation │ │ │ │ └── blk_mem_gen_v8_4.v │ │ ├── mem_init_files │ │ │ └── inst_ram.coe │ │ └── sim_scripts │ │ │ ├── clk_pll │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── xcelium │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── cmd.tcl │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── vhdl.prj │ │ │ │ └── vlog.prj │ │ │ ├── data_ram │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── xcelium │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── cmd.tcl │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── vhdl.prj │ │ │ │ └── vlog.prj │ │ │ ├── inst_ram │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ ├── xcelium │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ └── inst_ram.coe │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── cmd.tcl │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── inst_ram.coe │ │ │ │ ├── vhdl.prj │ │ │ │ └── vlog.prj │ │ │ ├── signed_divider │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── ies │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── modelsim │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── questa │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── riviera │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── vcs │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ ├── xcelium │ │ │ │ ├── README.txt │ │ │ │ ├── file_info.txt │ │ │ │ └── glbl.v │ │ │ └── xsim │ │ │ │ ├── README.txt │ │ │ │ ├── cmd.tcl │ │ │ │ ├── file_info.txt │ │ │ │ ├── glbl.v │ │ │ │ ├── vhdl.prj │ │ │ │ └── vlog.prj │ │ │ └── unsigned_divider │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── file_info.txt │ │ │ └── glbl.v │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vhdl.prj │ │ │ └── vlog.prj │ ├── mycpu_prj1.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_11.xml │ │ │ ├── vrs_config_12.xml │ │ │ ├── vrs_config_13.xml │ │ │ ├── vrs_config_14.xml │ │ │ ├── vrs_config_15.xml │ │ │ ├── vrs_config_16.xml │ │ │ ├── vrs_config_17.xml │ │ │ ├── vrs_config_18.xml │ │ │ ├── vrs_config_19.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_20.xml │ │ │ ├── vrs_config_21.xml │ │ │ ├── vrs_config_22.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_8.xml │ │ │ └── vrs_config_9.xml │ │ ├── clk_pll_synth_1 │ │ │ ├── .Xil │ │ │ │ └── clk_pll_propImpl.xdc │ │ │ ├── clk_pll.dcp │ │ │ ├── clk_pll.tcl │ │ │ ├── clk_pll.vds │ │ │ ├── clk_pll_utilization_synth.pb │ │ │ ├── clk_pll_utilization_synth.rpt │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ ├── data_ram_synth_1 │ │ │ ├── data_ram.dcp │ │ │ ├── data_ram.tcl │ │ │ ├── data_ram.vds │ │ │ ├── data_ram_utilization_synth.pb │ │ │ ├── data_ram_utilization_synth.rpt │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ ├── impl_1 │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── init_design.pb │ │ │ ├── opt_design.pb │ │ │ ├── place_design.pb │ │ │ ├── route_design.pb │ │ │ ├── soc_lite_top.tcl │ │ │ ├── soc_lite_top.vdi │ │ │ ├── soc_lite_top_bus_skew_routed.pb │ │ │ ├── soc_lite_top_bus_skew_routed.rpt │ │ │ ├── soc_lite_top_clock_utilization_routed.rpt │ │ │ ├── soc_lite_top_control_sets_placed.rpt │ │ │ ├── soc_lite_top_drc_opted.pb │ │ │ ├── soc_lite_top_drc_opted.rpt │ │ │ ├── soc_lite_top_drc_routed.pb │ │ │ ├── soc_lite_top_drc_routed.rpt │ │ │ ├── soc_lite_top_io_placed.rpt │ │ │ ├── soc_lite_top_methodology_drc_routed.pb │ │ │ ├── soc_lite_top_methodology_drc_routed.rpt │ │ │ ├── soc_lite_top_opt.dcp │ │ │ ├── soc_lite_top_placed.dcp │ │ │ ├── soc_lite_top_power_routed.rpt │ │ │ ├── soc_lite_top_power_summary_routed.pb │ │ │ ├── soc_lite_top_route_status.pb │ │ │ ├── soc_lite_top_route_status.rpt │ │ │ ├── soc_lite_top_routed.dcp │ │ │ ├── soc_lite_top_timing_summary_routed.pb │ │ │ ├── soc_lite_top_timing_summary_routed.rpt │ │ │ ├── soc_lite_top_utilization_placed.pb │ │ │ ├── soc_lite_top_utilization_placed.rpt │ │ │ ├── usage_statistics_webtalk.xml │ │ │ ├── vivado.jou │ │ │ ├── vivado.pb │ │ │ └── write_bitstream.pb │ │ ├── inst_ram_synth_1 │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── inst_ram.dcp │ │ │ ├── inst_ram.tcl │ │ │ ├── inst_ram.vds │ │ │ ├── inst_ram_utilization_synth.pb │ │ │ ├── inst_ram_utilization_synth.rpt │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ │ └── synth_1 │ │ │ ├── .Xil │ │ │ └── soc_lite_top_propImpl.xdc │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── soc_lite_top.dcp │ │ │ ├── soc_lite_top.tcl │ │ │ ├── soc_lite_top.vds │ │ │ ├── soc_lite_top_utilization_synth.pb │ │ │ ├── soc_lite_top_utilization_synth.rpt │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── mycpu_prj1.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ └── xsim │ │ │ ├── glbl.v │ │ │ ├── inst_ram.coe │ │ │ ├── tb_top.tcl │ │ │ ├── tb_top_vhdl.prj │ │ │ ├── tb_top_vlog.prj │ │ │ ├── webtalk.jou │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ └── tb_top_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_2.c │ │ │ │ ├── webtalk │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ │ └── xsim.mem │ │ │ ├── xvhdl.pb │ │ │ └── xvlog.pb │ ├── mycpu_prj1.srcs │ │ └── sources_1 │ │ │ ├── imports │ │ │ └── myCPU │ │ │ │ └── cp0.v │ │ │ └── ip │ │ │ ├── signed_divider │ │ │ ├── demo_tb │ │ │ │ └── tb_signed_divider.vhd │ │ │ ├── doc │ │ │ │ └── div_gen_v5_1_changelog.txt │ │ │ ├── hdl │ │ │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ │ │ ├── div_gen_v5_1_vh_rfs.vhd │ │ │ │ ├── floating_point_v7_0_vh_rfs.vhd │ │ │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_mult_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ ├── signed_divider.dcp │ │ │ ├── signed_divider.xci │ │ │ ├── signed_divider.xml │ │ │ ├── signed_divider_ooc.xdc │ │ │ ├── signed_divider_sim_netlist.v │ │ │ ├── signed_divider_sim_netlist.vhdl │ │ │ ├── signed_divider_stub.v │ │ │ ├── signed_divider_stub.vhdl │ │ │ ├── sim │ │ │ │ └── signed_divider.vhd │ │ │ └── synth │ │ │ │ └── signed_divider.vhd │ │ │ └── unsigned_divider │ │ │ ├── demo_tb │ │ │ └── tb_unsigned_divider.vhd │ │ │ ├── doc │ │ │ └── div_gen_v5_1_changelog.txt │ │ │ ├── hdl │ │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ │ ├── div_gen_v5_1_vh_rfs.vhd │ │ │ ├── floating_point_v7_0_vh_rfs.vhd │ │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ │ ├── xbip_dsp48_mult_v3_0_vh_rfs.vhd │ │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ │ ├── sim │ │ │ └── unsigned_divider.vhd │ │ │ ├── synth │ │ │ └── unsigned_divider.vhd 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