├── .gitignore ├── README.md └── cpu ├── alu_module ├── alu.v └── alu_tb.v ├── assembler └── RV32IMAssembler.c ├── bj_detect_module ├── bj_detect.v └── bj_detect_tb.v ├── control_unit_module ├── control_unit.v └── control_unit_tb.v ├── cpu_pipeline ├── cpu_pipeline.v └── cpu_pipeline_tb.v ├── cpu_single_cycle ├── cpu_single_cycle.v └── cpu_single_cycle_tb.v ├── data_cache_module ├── data_cache.v └── data_cache_tb.v ├── data_memory_module ├── data_memory.v └── data_memory_tb.v ├── forwarding_unit_module ├── forwarding_unit.v └── forwarding_unit_tb.v ├── immediate_gen_module ├── immediate_generate.v └── immediate_generate_tb.v ├── instruction_cache_module ├── instruction_cache.v └── instruction_cache_tb.v ├── instruction_memory_module ├── instruction_memory.v └── instruction_memory_tb.v ├── other_modules ├── adder_32bit │ └── adder_32bit.v ├── mux_2x1_32bit │ ├── mux_2x1_32bit.v │ └── mux_2x1_32bit_tb.v ├── mux_4x1_32bit │ ├── mux_4x1_32bit.v │ └── mux_4x1_32bit_tb.v └── register_32bit │ └── register_32bit.v ├── pipeline_reg_modules ├── EX_MEM_pipeline_reg_module │ ├── ex_mem_pipeline_reg.v │ └── ex_mem_pipeline_reg_tb.v ├── ID_EX_pipeline_reg_module │ ├── id_ex_pipeline_reg.v │ └── id_ex_pipeline_reg_tb.v ├── IF_ID_pipeline_reg_module │ ├── if_id_pipeline_reg.v │ └── if_id_pipeline_reg_tb.v └── MEM_WB_pipeline_reg_module │ ├── mem_wb_pipeline_reg.v │ └── mem_wb_pipeline_reg_tb.v ├── program.s ├── program2.s ├── reg_file_module ├── reg_file.v └── reg_file_tb.v ├── scripts ├── clean.sh ├── test-alu.sh ├── test-bj-detect-unit.sh ├── test-control-unit.sh ├── test-cpu-pipeline.sh ├── test-cpu-single-cycle.sh ├── test-data-cache.sh ├── test-data-memory.sh ├── test-ex-mem-pipeline-reg.sh ├── test-forwarding-unit.sh ├── test-id-ex-pipelline-reg.sh ├── test-if-id-pipeline-reg.sh ├── test-immediate-generate.sh ├── test-instruction-cache.sh ├── test-instruction-memory.sh ├── test-loading-unit.sh ├── test-mem-wb-pipeline-reg.sh ├── test-mux-2x1-32bit.sh ├── test-mux-4x1-32bit.s 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