├── .gitignore ├── COPYING ├── HDMIDirect.png ├── HDMIDirect.v ├── LICENSE.md ├── Notes.md ├── README.md ├── Wiring.md ├── altera └── 13.0sp1 │ ├── HDMIDirect.bdf │ ├── HDMIDirect.bsf │ ├── HDMIDirect.qpf │ ├── HDMIDirect.qsf │ ├── HDMIDirect.qws │ ├── HDMIDirect.v │ ├── HDMIDirectV.bsf │ ├── HDMI_test.bsf │ ├── TERC4_encoder.bsf │ ├── TMDS_encoder.bsf │ ├── altpll_masterclk.bsf │ ├── altpll_masterclk.ppf │ ├── altpll_masterclk.qip │ ├── altpll_masterclk.v │ ├── altpll_masterclk_bb.v │ ├── font │ └── logo.hex │ └── output_files │ ├── HDMIDirect.pof │ └── HDMIDirect.sof └── font ├── logo.hex ├── makelogo.c ├── messages.h ├── messages.xcf ├── neogeo.h └── neogeo.xcf /.gitignore: -------------------------------------------------------------------------------- 1 | # Temps 2 | *.bak 3 | *.cdf 4 | *.done 5 | *.jdi 6 | *.pin 7 | 8 | # Output files 9 | *.asm.* 10 | *.eda.* 11 | *.fit.* 12 | *.flow.* 13 | *.map.* 14 | *.sta.* 15 | 16 | # Output directories 17 | altera/13.0sp1/db/ 18 | altera/13.0sp1/greybox_tmp/ 19 | altera/13.0sp1/incremental_db/ 20 | altera/13.0sp1/output_files/greybox_tmp/ 21 | altera/13.0sp1/simulation/ 22 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | {signature of Ty Coon}, 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /HDMIDirect.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/charcole/NeoGeoHDMI/8d66141d150ea53abcc77258ed8db8890887f646/HDMIDirect.png -------------------------------------------------------------------------------- /HDMIDirect.v: -------------------------------------------------------------------------------- 1 | // Charlie Cole 2015 2 | // HDMI output for Neo Geo MVS 3 | // Originally based on fpga4fun.com HDMI/DVI sample code (c) fpga4fun.com & KNJN LLC 2013 4 | // Added Neo Geo MVS input, scan doubling, HDMI data packets and audio 5 | // Offers fake scanline generation (select via button) 6 | // 0: Line doubled but even lines are half brightness 7 | // 1: Only show even lines (odd lines are black) 8 | // 2: Line doubled 9 | 10 | module HDMIDirectV( 11 | input pixclk, 12 | input pixclk72, 13 | input pixclk144, 14 | input [16:0] videobus, 15 | input [4:0] Rin, Gin, Bin, 16 | input dak, sha, 17 | input button, 18 | input sync, 19 | input audioLR, 20 | input audioClk, 21 | input audioData, 22 | input audioLR2, 23 | input [7:0] fontData, 24 | output [2:0] TMDSp, TMDSn, 25 | output TMDSp_clock, TMDSn_clock, 26 | output [11:0] videoaddressw, 27 | output videoramenable, 28 | output videoramclk, 29 | output videoramoutclk, 30 | output videowrite, 31 | output [11:0] videoaddressoutw, 32 | output [16:0] videobusoutw, 33 | output neogeoclk, 34 | output [10:0] fontAddress, 35 | output fontROMClock 36 | ); 37 | 38 | //////////////////////////////////////////////////////////////////////// 39 | // User configuration defines 40 | 41 | `define OLD_SYNC // Comment out if have NeoGeo that clears at end of line 42 | `define YM3016 // Comment out for BU9480F (chip found on newer boards) 43 | `define SPLASH_SCREEN 44 | `define BAD_SYNC_DETECT 45 | `define DELAY_UNTIL_SPLASH_SCREEN 240 // In frames (/60 for seconds) 46 | 47 | //////////////////////////////////////////////////////////////////////// 48 | 49 | // Defines to do with video signal generation 50 | `define DISPLAY_WIDTH 720 51 | `define DISPLAY_HEIGHT 480 52 | `define FULL_WIDTH 858 53 | `define FULL_HEIGHT 525 54 | `define H_FRONT_PORCH 16 55 | `define H_SYNC 62 56 | `define V_FRONT_PORCH 9 57 | `define V_SYNC 6 58 | 59 | `define NEOGEO_DISPLAY_WIDTH 640 60 | `define NEOGEO_DISPLAY_HEIGHT 448 61 | `define NEOGEO_FULL_WIDTH 768 62 | `define NEOGEO_FULL_HEIGHT 528 63 | `ifdef OLD_SYNC 64 | `define NEOGEO_VSYNC_LENGTH 81 65 | `else 66 | `define NEOGEO_VSYNC_LENGTH 80 67 | `endif 68 | 69 | `define CENTERING_X ((`DISPLAY_WIDTH-`NEOGEO_DISPLAY_WIDTH)/2) // For centering NeoGeo's 4:3 screen 70 | `define CENTERING_Y ((`DISPLAY_HEIGHT-`NEOGEO_DISPLAY_HEIGHT)/2) // Should be multiple of 8 71 | 72 | // Defines to do with data packet sending 73 | `define DATA_START (`DISPLAY_WIDTH+4) // Need 4 cycles of control data first 74 | `define DATA_PREAMBLE 8 75 | `define DATA_GUARDBAND 2 76 | `define DATA_SIZE 32 77 | `define VIDEO_PREAMBLE 8 78 | `define VIDEO_GUARDBAND 2 79 | `define CTL_END (`FULL_WIDTH-`VIDEO_PREAMBLE-`VIDEO_GUARDBAND) 80 | 81 | wire clk_TMDS = pixclk72; 82 | 83 | //////////////////////////////////////////////////////////////////////// 84 | // Neo Geo Clk Gen 85 | //////////////////////////////////////////////////////////////////////// 86 | 87 | reg [10:0] fraction; 88 | reg [3:0] neoGeoClks; 89 | 90 | initial 91 | begin 92 | neoGeoClks=0; 93 | fraction=0; 94 | end 95 | 96 | wire x10clk = pixclk72^pixclk144; // These clocks are 2 135MHz clocks 90 degrees apart so this makes a 270MHz clock 97 | reg latch, nlatch; 98 | 99 | always @(posedge x10clk) 100 | begin 101 | // To make the timings work we want a neo geo cycle every 11+(111/1024) 270MHz cycles 102 | // Keep track of fractional part and when overflows do a longer cycle to bring us back 103 | if (neoGeoClks==0) begin 104 | nlatch<=latch; 105 | end 106 | if (neoGeoClks==10) begin 107 | neoGeoClks<=(fraction<1024)?0:15; 108 | fraction<=(fraction&1023)+111; 109 | end else begin 110 | neoGeoClks<=neoGeoClks+1; 111 | end 112 | end 113 | 114 | assign risingEdge=(neoGeoClks==6 && !x10clk); 115 | 116 | always @(posedge risingEdge) 117 | begin 118 | latch<=!nlatch; 119 | end 120 | 121 | assign neogeoclk=latch^nlatch; 122 | 123 | //////////////////////////////////////////////////////////////////////// 124 | // Line doubler 125 | // Takes the 480i video data from the NeoGeo and doubles the line 126 | // frequency by storing a line in RAM and then displaying it twice. 127 | // Also takes care of centring the picture (using the sync input). 128 | //////////////////////////////////////////////////////////////////////// 129 | 130 | reg [7:0] redneo, greenneo, blueneo; 131 | reg [9:0] CounterX, CounterY; 132 | reg [9:0] NeoCounterX, NeoCounterY; 133 | reg [11:0] videoaddress; 134 | reg [11:0] videoaddressout; 135 | reg [16:0] videobusout; 136 | reg [1:0] scanlineType; 137 | reg [8:0] frames; 138 | reg [23:0] syncWait; 139 | reg bOverlay; 140 | reg hSync, vSync, DrawArea; 141 | 142 | initial 143 | begin 144 | redneo=0; 145 | greenneo=0; 146 | blueneo=0; 147 | CounterX=0; 148 | CounterY=0; 149 | videoaddress=0; 150 | videoaddressout=0; 151 | videobusout=0; 152 | scanlineType=0; 153 | hSync=0; 154 | vSync=0; 155 | DrawArea=0; 156 | frames=0; 157 | syncWait=0; 158 | bOverlay=0; 159 | 160 | NeoCounterX=0; 161 | NeoCounterY=0; 162 | end 163 | 164 | assign videoramenable=1'b1; 165 | assign videoramclk=!clk_TMDS; 166 | assign videoramoutclk=!clk_TMDS; 167 | assign videowrite=1'b1; 168 | assign videoaddressoutw=videoaddressout; 169 | assign videobusoutw=videobusout; 170 | assign videoaddressw=videoaddress; 171 | 172 | always @(posedge pixclk) DrawArea <= (CounterX<`DISPLAY_WIDTH) && (CounterY<`DISPLAY_HEIGHT); 173 | always @(posedge pixclk) hSync <= !((CounterX>=(`DISPLAY_WIDTH+`H_FRONT_PORCH)) && (CounterX<(`DISPLAY_WIDTH+`H_FRONT_PORCH+`H_SYNC))); 174 | always @(posedge pixclk) vSync <= !(( 175 | (CounterY==(`DISPLAY_HEIGHT+`V_FRONT_PORCH-1) && CounterX>=(`DISPLAY_WIDTH+`H_FRONT_PORCH)) || 176 | CounterY>=(`DISPLAY_HEIGHT+`V_FRONT_PORCH)) 177 | && ( 178 | (CounterY==(`DISPLAY_HEIGHT+`V_FRONT_PORCH+`V_SYNC-1) && CounterX<(`DISPLAY_WIDTH+`H_FRONT_PORCH)) || 179 | CounterY<(`DISPLAY_HEIGHT+`V_FRONT_PORCH+`V_SYNC-1) 180 | )); // VSync and HSync seem to need to transition at the same time 181 | 182 | `ifdef OLD_SYNC 183 | always @(posedge neogeoclk) 184 | `else 185 | always @(negedge neogeoclk) 186 | `endif 187 | begin 188 | NeoCounterX <= (NeoCounterX==(`NEOGEO_FULL_WIDTH-1)) ? 0 : NeoCounterX+1; 189 | if(NeoCounterX==(`NEOGEO_FULL_WIDTH-1)) begin 190 | if (NeoCounterY==(`NEOGEO_FULL_HEIGHT-1)) begin 191 | NeoCounterY <= 0; 192 | end else begin 193 | NeoCounterY <= NeoCounterY+1; 194 | end 195 | end 196 | if (sync) begin 197 | `ifdef OLD_SYNC 198 | if (NeoCounterY > `NEOGEO_FULL_HEIGHT-`NEOGEO_VSYNC_LENGTH) begin 199 | NeoCounterY <= `NEOGEO_FULL_HEIGHT-`NEOGEO_VSYNC_LENGTH+1; 200 | NeoCounterX <= 0; 201 | end 202 | `else 203 | if (NeoCounterY > `NEOGEO_FULL_HEIGHT-`NEOGEO_VSYNC_LENGTH) 204 | NeoCounterY <= `NEOGEO_FULL_HEIGHT-`NEOGEO_VSYNC_LENGTH+1; 205 | if ((NeoCounterX>>1)+(NeoCounterY[0]?`NEOGEO_FULL_WIDTH/2:0)>=`NEOGEO_DISPLAY_WIDTH) 206 | NeoCounterX <= 2*`NEOGEO_DISPLAY_WIDTH-`NEOGEO_FULL_WIDTH; 207 | `endif 208 | end 209 | if ((NeoCounterX>>1)+(NeoCounterY[0]?`NEOGEO_FULL_WIDTH/2:0)<`NEOGEO_DISPLAY_WIDTH) begin 210 | if (NeoCounterX[0]) begin 211 | videoaddressout<=(NeoCounterY[2:1]*`NEOGEO_DISPLAY_WIDTH)+(NeoCounterY[0]?`NEOGEO_FULL_WIDTH/2:0)+(NeoCounterX>>1); 212 | videobusout[4:0]<=Rin; 213 | videobusout[9:5]<=Gin; 214 | videobusout[14:10]<=Bin; 215 | videobusout[15]<=!dak; 216 | videobusout[16]<=!sha; 217 | end 218 | end 219 | end 220 | 221 | always @(posedge pixclk) 222 | begin 223 | if(CounterX==(`FULL_WIDTH-1)) begin 224 | if (CounterY==(`FULL_HEIGHT-1)) begin 225 | // Sync screen output with NeoGeo output 226 | // +2 means there's a line in the doubler ready 227 | if (NeoCounterY==(`NEOGEO_FULL_HEIGHT-`CENTERING_Y+2) && NeoCounterX==0) begin 228 | syncWait <= 0; 229 | bOverlay <= 0; 230 | CounterY <= 0; 231 | CounterX <= 0; 232 | if (frames!=`DELAY_UNTIL_SPLASH_SCREEN) 233 | frames <= frames + 1; 234 | end 235 | `ifdef BAD_SYNC_DETECT 236 | else if (syncWait==24'hFFFFFF) begin // If not synced within half a second then display error 237 | bOverlay <= 1; 238 | CounterY <= 0; 239 | CounterX <= 0; 240 | if (frames!=`DELAY_UNTIL_SPLASH_SCREEN) 241 | frames <= frames + 1; 242 | end else begin 243 | syncWait <= syncWait + 1; 244 | end 245 | `endif 246 | end else begin 247 | CounterY <= CounterY+1; 248 | CounterX <= 0; 249 | end 250 | end else begin 251 | CounterX<=CounterX+1; 252 | end 253 | videoaddress<=(CounterY[2:1]*`NEOGEO_DISPLAY_WIDTH) + (CounterX+2-`CENTERING_X); // Look ahead two pixels 254 | if (CounterX>=`CENTERING_X && CounterX<`DISPLAY_WIDTH+`CENTERING_X) begin 255 | if ((CounterX-`CENTERING_X)<`NEOGEO_DISPLAY_WIDTH) begin 256 | if (scanlineType==2 || !(CounterY&1)) begin 257 | redneo <= ((videobus[4:0]<<1)|videobus[15])*3 + (videobus[16]?((videobus[4:0]<<1)|videobus[15]):0); 258 | greenneo <= ((videobus[9:5]<<1)|videobus[15])*3 + (videobus[16]?((videobus[9:5]<<1)|videobus[15]):0); 259 | blueneo <= ((videobus[14:10]<<1)|videobus[15])*3 + (videobus[16]?((videobus[14:10]<<1)|videobus[15]):0); 260 | end else begin 261 | if (!scanlineType[0]) begin 262 | redneo <= (((videobus[4:0]<<1)|videobus[15])*3 + (videobus[16]?((videobus[4:0]<<1)|videobus[15]):0)) >> 1; 263 | greenneo <= (((videobus[9:5]<<1)|videobus[15])*3 + (videobus[16]?((videobus[9:5]<<1)|videobus[15]):0)) >> 1; 264 | blueneo <= (((videobus[14:10]<<1)|videobus[15])*3 + (videobus[16]?((videobus[14:10]<<1)|videobus[15]):0)) >> 1; 265 | end else begin 266 | redneo <= 0; 267 | greenneo <= 0; 268 | blueneo <= 0; 269 | end 270 | end 271 | end else begin 272 | redneo <= 0; 273 | greenneo <= 0; 274 | blueneo <= 0; 275 | end 276 | end 277 | end 278 | 279 | //////////////////////////////////////////////////////////////////////// 280 | // Error overlay 281 | //////////////////////////////////////////////////////////////////////// 282 | 283 | reg [7:0] red, green, blue; 284 | reg [10:0] fontAddr; 285 | reg [7:0] scroll; 286 | reg [6:0] logo; 287 | reg [7:0] ba; 288 | reg [9:0] dx; 289 | reg [9:0] dx2; 290 | reg [9:0] dy; 291 | reg [15:0] d; 292 | reg [15:0] dd; 293 | reg [15:0] dd2; 294 | reg [7:0] ax; 295 | reg [8:0] num [7:0]; 296 | reg [8:0] den [7:0]; 297 | reg [8:0] res [7:0]; 298 | reg [9:0] s; 299 | reg [19:0] cc; 300 | reg [1:0] lastScanlineType; 301 | reg [7:0] scanlineChanged; 302 | reg shadow; 303 | 304 | initial 305 | begin 306 | red=0; 307 | green=0; 308 | blue=0; 309 | fontAddr=0; 310 | scroll=0; 311 | logo=0; 312 | s=0; 313 | cc=0; 314 | lastScanlineType=0; 315 | scanlineChanged=0; 316 | shadow=0; 317 | end 318 | 319 | assign fontROMClock = pixclk; 320 | assign fontAddress = fontAddr; 321 | 322 | function [9:0] abs; 323 | input [9:0] v; 324 | begin 325 | abs=($signed(v)<0)?-v:v; 326 | end 327 | endfunction 328 | 329 | always @(posedge pixclk) 330 | begin 331 | `ifdef SPLASH_SCREEN 332 | if (logo!=127) begin 333 | // Splash screen rendering 334 | dx<=(CounterX+9-`DISPLAY_WIDTH/2); // divide is latent so look ahead 335 | dx2<=(CounterX-`DISPLAY_WIDTH/2); 336 | dy<=(CounterY-`DISPLAY_HEIGHT/2); 337 | // Calulate distance from centre 338 | dd<=(((`DISPLAY_WIDTH*`DISPLAY_WIDTH/8)-($signed(dx2)*$signed(dx2)+$signed(dy)*$signed(dy)))>>8) 339 | -((logo<32)?8*(32-logo):0)+((logo>96)?32*(logo-96):0); 340 | // atan approximation 341 | if (abs(dx)0)?3:1); 346 | end else begin 347 | num[0]<=abs(dy); 348 | den[0]<=abs(dx); 349 | s<=(s<<1)|(dx[9]^dy[9]^1); 350 | cc<=(cc<<2)|(($signed(dx)<0)?2:0); 351 | end 352 | // 8 cycle latency divide 353 | if (num[0]>=den[0]) begin num[1]<=num[0]-den[0]; res[0]<= +128; end else begin num[1]<=num[0]; res[0]<=0; end den[1]<=den[0]>>1; 354 | if (num[1]>=den[1]) begin num[2]<=num[1]-den[1]; res[1]<=res[0]+ 64; end else begin num[2]<=num[1]; res[1]<=res[0]; end den[2]<=den[1]>>1; 355 | if (num[2]>=den[2]) begin num[3]<=num[2]-den[2]; res[2]<=res[1]+ 32; end else begin num[3]<=num[2]; res[2]<=res[1]; end den[3]<=den[2]>>1; 356 | if (num[3]>=den[3]) begin num[4]<=num[3]-den[3]; res[3]<=res[2]+ 16; end else begin num[4]<=num[3]; res[3]<=res[2]; end den[4]<=den[3]>>1; 357 | if (num[4]>=den[4]) begin num[5]<=num[4]-den[4]; res[4]<=res[3]+ 8; end else begin num[5]<=num[4]; res[4]<=res[3]; end den[5]<=den[4]>>1; 358 | if (num[5]>=den[5]) begin num[6]<=num[5]-den[5]; res[5]<=res[4]+ 4; end else begin num[6]<=num[5]; res[5]<=res[4]; end den[6]<=den[5]>>1; 359 | if (num[6]>=den[6]) begin num[7]<=num[6]-den[6]; res[6]<=res[5]+ 2; end else begin num[7]<=num[6]; res[6]<=res[5]; end den[7]<=den[6]>>1; 360 | if (num[7]>=den[7]) begin res[7]<=res[6]+ 1; end else begin res[7]<=res[6]; end 361 | ax<=(((s[9]?-res[7]:res[7])+(2*cc[19:18]+1)*128+logo*4)>>2)&'hFF; 362 | // Look up texture maps 363 | if (CounterX>=`DISPLAY_WIDTH/2-64 && CounterX<=`DISPLAY_WIDTH/2+64 && CounterY>=`DISPLAY_HEIGHT-16 && CounterY<`DISPLAY_HEIGHT-8) begin 364 | // Display the link 365 | fontAddr<=3*256+CounterX-(`DISPLAY_WIDTH/2-64); 366 | if (CounterX>`DISPLAY_WIDTH/2-64+2 && logo>32) 367 | ba<=fontData[CounterY-(`DISPLAY_HEIGHT-16)]?((logo<96)?(logo-32)>>1:32):0; 368 | else 369 | ba<=0; 370 | end else begin 371 | // Logo 372 | fontAddr<=(3*(255-ax))+((dd-128)>>5); 373 | ba<=0; 374 | end 375 | dd2<=dd; 376 | d<=dd2; 377 | // Output 378 | if ($signed(d)>=256) begin 379 | red <= redneo; 380 | green <= greenneo; 381 | blue <= blueneo; 382 | end else begin 383 | if (CounterX>3 && $signed(d)>=0 && (d<128 || d>=224 || !fontData[(d>>2)&7])) begin 384 | red<=(ba+d<255)?ba+d:255; 385 | green<=(d*d)>>8; 386 | blue<=0; 387 | end else begin 388 | red<=0; 389 | green<=0; 390 | blue<=0; 391 | end 392 | end 393 | if (frames==`DELAY_UNTIL_SPLASH_SCREEN && CounterX==0 && CounterY==0) 394 | logo<=logo+1; 395 | end else 396 | `endif 397 | if (bOverlay && CounterY>=`DISPLAY_HEIGHT/2-8 && CounterY<`DISPLAY_HEIGHT/2+8) begin 398 | // Scrolling error message 399 | red <= 0; 400 | fontAddr<=3*256+(((CounterX>>1)+scroll)&'hFF); 401 | if (CounterX>3) 402 | green <= fontData[(CounterY-(`DISPLAY_HEIGHT/2-8))>>1]?255:0; 403 | else 404 | green <= 0; 405 | blue <= 0; 406 | end else if (scanlineChanged>0 && CounterX>=`DISPLAY_WIDTH-154 && CounterY>=`DISPLAY_HEIGHT-16) begin 407 | // Display scanline mode 408 | fontAddr<=(4*256)+(scanlineType*75)+((CounterX-(`DISPLAY_WIDTH-154))>>1); 409 | shadow<=fontData[(CounterY-(`DISPLAY_HEIGHT-16))>>1]; 410 | if (CounterX>=`DISPLAY_WIDTH-150 && fontData[(CounterY-(`DISPLAY_HEIGHT-16))>>1]|shadow) begin 411 | if (shadow) begin 412 | if (scanlineType==2 || !(CounterY&1)) 413 | green <= 255; 414 | else if (scanlineType==0) 415 | green <= 127; 416 | else 417 | green <= 0; 418 | end else begin 419 | green <=0; 420 | end 421 | red<=0; 422 | blue<=0; 423 | end else begin 424 | red <= redneo; 425 | green <= greenneo; 426 | blue <= blueneo; 427 | end 428 | end else begin 429 | // normal output 430 | red <= redneo; 431 | green <= greenneo; 432 | blue <= blueneo; 433 | end 434 | if (CounterX==0 && CounterY==0) begin 435 | scroll<=scroll+1; 436 | if (scanlineChanged>0) 437 | scanlineChanged <= scanlineChanged - 1; 438 | if (scanlineType!=lastScanlineType) begin 439 | lastScanlineType <= scanlineType; 440 | scanlineChanged <= 60; 441 | end 442 | end 443 | end 444 | 445 | //////////////////////////////////////////////////////////////////////// 446 | // Neo Geo audio input 447 | //////////////////////////////////////////////////////////////////////// 448 | 449 | reg [15:0] audioInput [1:0]; 450 | reg [15:0] curSampleL; 451 | reg [15:0] curSampleR; 452 | 453 | initial 454 | begin 455 | audioInput[0]=0; 456 | audioInput[1]=0; 457 | curSampleL=0; 458 | curSampleR=0; 459 | end 460 | 461 | `ifdef YM3016 462 | always @(negedge audioClk) 463 | begin 464 | audioInput[0]<=(audioInput[0]>>1)|(audioData<<15); 465 | audioInput[1]<=(audioInput[1]>>1)|(audioData<<15); 466 | end 467 | always @(negedge audioLR) begin curSampleL<=audioInput[0]-16'h8000; end 468 | always @(negedge audioLR2) begin curSampleR<=audioInput[1]-16'h8000; end 469 | `else // BU9480F 470 | always @(posedge audioClk) if (audioLR) audioInput[0]<=(audioInput[0]<<1)|audioData; else audioInput[1]<=(audioInput[1]<<1)|audioData; 471 | always @(negedge audioLR) begin curSampleL<=audioInput[0]; curSampleR<=audioInput[1]; end 472 | `endif 473 | 474 | //////////////////////////////////////////////////////////////////////// 475 | // HDMI audio packet generator 476 | //////////////////////////////////////////////////////////////////////// 477 | 478 | // Timing for 32KHz audio at 27MHz 479 | `define AUDIO_TIMER_ADDITION 4 480 | `define AUDIO_TIMER_LIMIT 3375 481 | 482 | localparam [191:0] channelStatus = 192'hc203004004; // 32KHz 16-bit LPCM audio 483 | reg [23:0] audioPacketHeader; 484 | reg [55:0] audioSubPacket[3:0]; 485 | reg [7:0] channelStatusIdx; 486 | reg [11:0] audioTimer; 487 | reg [9:0] audioSamples; 488 | reg [1:0] samplesHead; 489 | reg sendRegenPacket; 490 | 491 | initial 492 | begin 493 | audioPacketHeader=0; 494 | audioSubPacket[0]=0; 495 | audioSubPacket[1]=0; 496 | audioSubPacket[2]=0; 497 | audioSubPacket[3]=0; 498 | channelStatusIdx=0; 499 | audioTimer=0; 500 | audioSamples=0; 501 | samplesHead=0; 502 | sendRegenPacket=0; 503 | end 504 | 505 | task AudioPacketGeneration; 506 | begin 507 | // Buffer up an audio sample every 750 pixel clocks (32KHz output from 24MHz pixel clock) 508 | // Don't add to the audio output if we're currently sending that packet though 509 | if (!( 510 | CounterX>=(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND+`DATA_SIZE) && 511 | CounterX<(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND+`DATA_SIZE+`DATA_SIZE) 512 | )) begin 513 | if (audioTimer>=`AUDIO_TIMER_LIMIT) begin 514 | audioTimer<=audioTimer-`AUDIO_TIMER_LIMIT+`AUDIO_TIMER_ADDITION; 515 | audioPacketHeader<=audioPacketHeader|24'h000002|((channelStatusIdx==0?24'h100100:24'h000100)<=`DATA_START) 647 | begin 648 | if (CounterX<(`DATA_START+`DATA_PREAMBLE)) 649 | begin 650 | // Send the data period preamble 651 | // A nice "feature" of my test monitor (GL2450) is if you comment out 652 | // this line you see your data next to your image which is useful for 653 | // debugging 654 | preamble<='b0101; 655 | end 656 | else if (CounterX<(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND)) 657 | begin 658 | // Start sending leading data guard band 659 | tercData<=1; 660 | dataGuardBand<=1; 661 | dataChannel0<={1'b1, 1'b1, vSync, hSync}; 662 | preamble<=0; 663 | // Set up the first of the packets we'll send 664 | if (sendRegenPacket) begin 665 | packetHeader<=24'h000001; // audio clock regeneration packet 666 | subpacket[0]<=56'h00100078690000; // N=0x1000 CTS=0x6978 (27MHz pixel clock -> 32KHz audio clock) 667 | subpacket[1]<=56'h00100078690000; 668 | subpacket[2]<=56'h00100078690000; 669 | subpacket[3]<=56'h00100078690000; 670 | if (CounterX==(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND-1)) 671 | sendRegenPacket<=0; 672 | end else begin 673 | if (!CounterY[0]) begin 674 | packetHeader<=24'h0D0282; // infoframe AVI packet 675 | // Byte0: Checksum 676 | // Byte1: 10 = 0(Y1:Y0=0 RGB)(A0=1 No active format)(B1:B0=00 No bar info)(S1:S0=00 No scan info) 677 | // Byte2: 2A = (C1:C0=0 No colorimetry)(M1:M0=2 16:9)(R3:R0=A 16:9) 678 | // Byte3: 00 = 0(SC1:SC0=0 No scaling) 679 | // Byte4: 03 = 0(VIC6:VIC0=3 720x480p) 680 | // Byte5: 00 = 0(PR5:PR0=0 No repeation) 681 | subpacket[0]<=56'h000003002A1032; 682 | subpacket[1]<=56'h00000000000000; 683 | end else begin 684 | packetHeader<=24'h0A0184; // infoframe audio packet 685 | // Byte0: Checksum 686 | // Byte1: 11 = (CT3:0=1 PCM)0(CC2:0=1 2ch) 687 | // Byte2: 00 = 000(SF2:0=0 As stream)(SS1:0=0 As stream) 688 | // Byte3: 00 = LPCM doesn't use this 689 | // Byte4-5: 00 Multichannel only (>2ch) 690 | subpacket[0]<=56'h00000000001160; 691 | subpacket[1]<=56'h00000000000000; 692 | end 693 | subpacket[2]<=56'h00000000000000; 694 | subpacket[3]<=56'h00000000000000; 695 | end 696 | end 697 | else if (CounterX<(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND+`DATA_SIZE)) 698 | begin 699 | dataGuardBand<=0; 700 | // Send first data packet (Infoframe or audio clock regen) 701 | SendPacket(packetHeader, subpacket[0], subpacket[1], subpacket[2], subpacket[3], 1); 702 | end 703 | else if (CounterX<(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND+`DATA_SIZE+`DATA_SIZE)) 704 | begin 705 | // Send second data packet (audio data) 706 | SendPacket(audioPacketHeader, audioSubPacket[0], audioSubPacket[1], audioSubPacket[2], audioSubPacket[3], 0); 707 | end 708 | else if (CounterX<(`DATA_START+`DATA_PREAMBLE+`DATA_GUARDBAND+`DATA_SIZE+`DATA_SIZE+`DATA_GUARDBAND)) 709 | begin 710 | // Trailing guardband for data period 711 | dataGuardBand<=1; 712 | dataChannel0<={1'b1, 1'b1, vSync, hSync}; 713 | end 714 | else 715 | begin 716 | // Back to normal DVI style control data 717 | tercData<=0; 718 | dataGuardBand<=0; 719 | end 720 | end 721 | // After we've sent data packets we need to do the video preamble and 722 | // guardband just before sending active video data 723 | if (CounterX>=(`CTL_END+`VIDEO_PREAMBLE)) 724 | begin 725 | preamble<=0; 726 | videoGuardBand<=1; 727 | end 728 | else if (CounterX>=(`CTL_END)) 729 | begin 730 | preamble<='b0001; 731 | end 732 | else 733 | begin 734 | videoGuardBand<=0; 735 | end 736 | end 737 | 738 | //////////////////////////////////////////////////////////////////////// 739 | // HDMI encoder 740 | // Encodes video data (TMDS) or packet data (TERC4) ready for sending 741 | //////////////////////////////////////////////////////////////////////// 742 | 743 | reg tercDataDelayed [1:0]; 744 | reg videoGuardBandDelayed [1:0]; 745 | reg dataGuardBandDelayed [1:0]; 746 | 747 | initial 748 | begin 749 | tercDataDelayed[0]=0; 750 | tercDataDelayed[1]=0; 751 | videoGuardBandDelayed[0]=0; 752 | videoGuardBandDelayed[1]=0; 753 | dataGuardBandDelayed[0]=0; 754 | dataGuardBandDelayed[1]=0; 755 | end 756 | 757 | always @(posedge pixclk) 758 | begin 759 | // Cycle 1 760 | tercDataDelayed[0]<=tercData; // To account for delay through encoder 761 | videoGuardBandDelayed[0]<=videoGuardBand; 762 | dataGuardBandDelayed[0]<=dataGuardBand; 763 | // Cycle 2 764 | tercDataDelayed[1]<=tercDataDelayed[0]; 765 | videoGuardBandDelayed[1]<=videoGuardBandDelayed[0]; 766 | dataGuardBandDelayed[1]<=dataGuardBandDelayed[0]; 767 | end 768 | 769 | wire [9:0] TMDS_red, TMDS_green, TMDS_blue; 770 | TMDS_encoder encode_R(.clk(pixclk), .VD(red ), .CD(preamble[3:2]), .VDE(DrawArea), .TMDS(TMDS_red)); 771 | TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD(preamble[1:0]), .VDE(DrawArea), .TMDS(TMDS_green)); 772 | TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vSync,hSync}), .VDE(DrawArea), .TMDS(TMDS_blue)); 773 | 774 | wire [9:0] TERC4_red, TERC4_green, TERC4_blue; 775 | TERC4_encoder encode_R4(.clk(pixclk), .data(dataChannel2), .TERC(TERC4_red)); 776 | TERC4_encoder encode_G4(.clk(pixclk), .data(dataChannel1), .TERC(TERC4_green)); 777 | TERC4_encoder encode_B4(.clk(pixclk), .data(dataChannel0), .TERC(TERC4_blue)); 778 | 779 | //////////////////////////////////////////////////////////////////////// 780 | // HDMI data serialiser 781 | // Outputs the encoded video data as serial data across the HDMI bus 782 | //////////////////////////////////////////////////////////////////////// 783 | 784 | reg [3:0] TMDS_mod10; // modulus 10 counter 785 | reg [9:0] TMDS_shift_red, TMDS_shift_green, TMDS_shift_blue; 786 | reg [9:0] TMDS_shift_red_delay, TMDS_shift_green_delay, TMDS_shift_blue_delay; 787 | 788 | initial 789 | begin 790 | TMDS_mod10=0; 791 | TMDS_shift_red=0; 792 | TMDS_shift_green=0; 793 | TMDS_shift_blue=0; 794 | TMDS_shift_red_delay=0; 795 | TMDS_shift_green_delay=0; 796 | TMDS_shift_blue_delay=0; 797 | end 798 | 799 | always @(posedge pixclk) 800 | begin 801 | TMDS_shift_red_delay<=videoGuardBandDelayed[1] ? 10'b1011001100 : (dataGuardBandDelayed[1] ? 10'b0100110011 : (tercDataDelayed[1] ? TERC4_red : TMDS_red)); 802 | TMDS_shift_green_delay<=(dataGuardBandDelayed[1] || videoGuardBandDelayed[1]) ? 10'b0100110011 : (tercDataDelayed[1] ? TERC4_green : TMDS_green); 803 | TMDS_shift_blue_delay<=videoGuardBandDelayed[1] ? 10'b1011001100 : (tercDataDelayed[1] ? TERC4_blue : TMDS_blue); 804 | end 805 | 806 | always @(posedge clk_TMDS) 807 | begin 808 | TMDS_shift_red <= (TMDS_mod10==4'd8) ? TMDS_shift_red_delay : TMDS_shift_red [9:2]; 809 | TMDS_shift_green <= (TMDS_mod10==4'd8) ? TMDS_shift_green_delay : TMDS_shift_green[9:2]; 810 | TMDS_shift_blue <= (TMDS_mod10==4'd8) ? TMDS_shift_blue_delay : TMDS_shift_blue [9:2]; 811 | TMDS_mod10 <= (TMDS_mod10==4'd8) ? 4'd0 : TMDS_mod10+4'd2; 812 | end 813 | 814 | assign TMDSp[2]=clk_TMDS?TMDS_shift_red[0]:TMDS_shift_red[1]; 815 | assign TMDSn[2]=~TMDSp[2]; 816 | assign TMDSp[1]=clk_TMDS?TMDS_shift_green[0]:TMDS_shift_green[1]; 817 | assign TMDSn[1]=!TMDSp[1]; 818 | assign TMDSp[0]=clk_TMDS?TMDS_shift_blue[0]:TMDS_shift_blue[1]; 819 | assign TMDSn[0]=!TMDSp[0]; 820 | assign TMDSp_clock=(TMDS_mod10==4)?!clk_TMDS:(TMDS_mod10>5); 821 | assign TMDSn_clock=!TMDSp_clock; 822 | 823 | //////////////////////////////////////////////////////////////////////// 824 | // Scanline method selection button debouncer 825 | //////////////////////////////////////////////////////////////////////// 826 | 827 | reg [16:0] buttonDebounce; 828 | 829 | initial 830 | begin 831 | buttonDebounce=0; 832 | end 833 | 834 | always @(posedge pixclk) 835 | begin 836 | if (!button) begin 837 | if (buttonDebounce=='h1ffff) 838 | scanlineType<=scanlineType!=2?scanlineType+1:0; 839 | buttonDebounce<=0; 840 | end else if (buttonDebounce!='h1ffff) begin // Audio clock is 6MHz so this is about 22ms 841 | buttonDebounce<=buttonDebounce+1; 842 | end 843 | end 844 | 845 | endmodule 846 | 847 | //////////////////////////////////////////////////////////////////////// 848 | // TMDS encoder 849 | // Used to encode HDMI/DVI video data 850 | //////////////////////////////////////////////////////////////////////// 851 | 852 | module TMDS_encoder( 853 | input clk, 854 | input [7:0] VD, // video data (red, green or blue) 855 | input [1:0] CD, // control data 856 | input VDE, // video data enable, to choose between CD (when VDE=0) and VD (when VDE=1) 857 | output reg [9:0] TMDS 858 | ); 859 | 860 | reg [3:0] balance_acc; 861 | reg [8:0] q_m; 862 | reg [1:0] CD2; 863 | reg VDE2; 864 | 865 | initial begin 866 | balance_acc=0; 867 | q_m=0; 868 | CD2=0; 869 | VDE2=0; 870 | end 871 | 872 | function [3:0] balance; 873 | input [7:0] qm; 874 | begin 875 | balance = qm[0] + qm[1] + qm[2] + qm[3] + qm[4] + qm[5] + qm[6] + qm[7] - 4'd4; 876 | end 877 | endfunction 878 | 879 | always @(posedge clk) 880 | begin 881 | // Cycle 1 882 | if ((VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7])>(VD[0]?4'd4:4'd3)) begin 883 | q_m <= {1'b0,~^VD[7:0],^VD[6:0],~^VD[5:0],^VD[4:0],~^VD[3:0],^VD[2:0],~^VD[1:0],VD[0]}; 884 | end else begin 885 | q_m <= {1'b1, ^VD[7:0],^VD[6:0], ^VD[5:0],^VD[4:0], ^VD[3:0],^VD[2:0], ^VD[1:0],VD[0]}; 886 | end 887 | VDE2 <= VDE; 888 | CD2 <= CD; 889 | // Cycle 2 890 | if (VDE2) begin 891 | if (balance(q_m)==0 || balance_acc==0) begin 892 | if (q_m[8]) begin 893 | TMDS <= {1'b0, q_m[8], q_m[7:0]}; 894 | balance_acc <= balance_acc+balance(q_m); 895 | end else begin 896 | TMDS <= {1'b1, q_m[8], ~q_m[7:0]}; 897 | balance_acc <= balance_acc-balance(q_m); 898 | end 899 | end else begin 900 | if (balance(q_m)>>3 == balance_acc[3]) begin 901 | TMDS <= {1'b1, q_m[8], ~q_m[7:0]}; 902 | balance_acc <= balance_acc+q_m[8]-balance(q_m); 903 | end else begin 904 | TMDS <= {1'b0, q_m[8], q_m[7:0]}; 905 | balance_acc <= balance_acc-(~q_m[8])+balance(q_m); 906 | end 907 | end 908 | end else begin 909 | balance_acc <= 0; 910 | TMDS <= CD2[1] ? (CD2[0] ? 10'b1010101011 : 10'b0101010100) : (CD2[0] ? 10'b0010101011 : 10'b1101010100); 911 | end 912 | end 913 | 914 | endmodule 915 | 916 | //////////////////////////////////////////////////////////////////////// 917 | // TERC4 Encoder 918 | // Used to encode the HDMI data packets such as audio 919 | //////////////////////////////////////////////////////////////////////// 920 | 921 | module TERC4_encoder( 922 | input clk, 923 | input [3:0] data, 924 | output reg [9:0] TERC 925 | ); 926 | 927 | reg [9:0] TERC_pre; 928 | 929 | initial 930 | begin 931 | TERC_pre=0; 932 | end 933 | 934 | always @(posedge clk) 935 | begin 936 | // Cycle 1 937 | case (data) 938 | 4'b0000: TERC_pre <= 10'b1010011100; 939 | 4'b0001: TERC_pre <= 10'b1001100011; 940 | 4'b0010: TERC_pre <= 10'b1011100100; 941 | 4'b0011: TERC_pre <= 10'b1011100010; 942 | 4'b0100: TERC_pre <= 10'b0101110001; 943 | 4'b0101: TERC_pre <= 10'b0100011110; 944 | 4'b0110: TERC_pre <= 10'b0110001110; 945 | 4'b0111: TERC_pre <= 10'b0100111100; 946 | 4'b1000: TERC_pre <= 10'b1011001100; 947 | 4'b1001: TERC_pre <= 10'b0100111001; 948 | 4'b1010: TERC_pre <= 10'b0110011100; 949 | 4'b1011: TERC_pre <= 10'b1011000110; 950 | 4'b1100: TERC_pre <= 10'b1010001110; 951 | 4'b1101: TERC_pre <= 10'b1001110001; 952 | 4'b1110: TERC_pre <= 10'b0101100011; 953 | 4'b1111: TERC_pre <= 10'b1011000011; 954 | endcase 955 | // Cycle 2 956 | TERC <= TERC_pre; 957 | end 958 | 959 | endmodule 960 | 961 | //////////////////////////////////////////////////////////////////////// 962 | 963 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | **NeoGeoHDMI : HDMI Output mod for Neo Geo MVS** 2 | 3 | Copyright (C) 2015 Charles Cole 4 | 5 | Copyright (C) 2013 fpga4fun.com & KNJN LLC 6 | 7 | This program is free software; you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation; either version 2 of the License, or 10 | (at your option) any later version. 11 | 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License along 18 | with this program; if not, write to the Free Software Foundation, Inc., 19 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 | -------------------------------------------------------------------------------- /Notes.md: -------------------------------------------------------------------------------- 1 | Motivation 2 | ---------- 3 | 4 | I made a small supergun board last year which was featured on Hack-a-Day. A 5 | lot of the comments focused on the output being SCART, a Europian video 6 | standard that supports RGB which isn't common in other parts of the world. The 7 | obvious solution seemed to be a supergun with HDMI output. I didn't really 8 | have a huge amount of motivation to do it and it ended up on the back burner. 9 | Over Christmas I had some time though and had recently been messing around 10 | with cheap FPGA dev boards from eBay. The FPGA could be used to generate the 11 | HDMI signal (just) and as it has a small amount of fast memory to be able to 12 | upscale the image to the 480p. However I'd gone off the HDMI supergun concept 13 | a bit by this point. Firstly I didn't have any ADCs fast enough to process video on hand and 14 | secondly SCART to HDMI adapters aren't all that expensive anymore (although 15 | this solution is admittedly clunkier). So, a slightly different idea came to 16 | me. The Neo Geo the digitised video signal is easy to get before it's converted to 17 | an analogue signal so by tapping it from there we can get a direct digital to 18 | digital connection theorectially giving the best possible video quality. 19 | Hopefully this will able to be extended to the audio too giving the best 20 | possible sound quality too. 21 | Nb. This isn't totally original. Half way through I found a NeoGAF post, when 22 | searching for some video timings info, where someone was doing something very 23 | similar although it looked to end up with a VGA signal so not a fully digital 24 | connection. I also wondered about extending the concept to old video consoles 25 | but many of the really old consoles have analogue video coming out of their 26 | custom chips. The newer the console the easier it looks to be. Dreamcast, 27 | Gamecube, N64 and possibly SNES look feasible. N64 looks to have been done 28 | before though. 29 | 30 | Clock trouble 31 | ------------- 32 | 33 | _This second is outdated as I now overclock the Neo Geo to get the clock I need_ 34 | 35 | The obvious clock to use is the clock on the video output latches. 36 | It's 6.?MHz which gives us a nice multiple to get to around 25MHz. 37 | Also in sync with the video data is it's the latch. 38 | However 6MHz is too slow to use the PLL on the Cyclone II. 39 | Therefore we can use the 12MHz CPU clock as it's fairly easy to get as it's on a big pin close to the video data. 40 | Next problem was all the voltages are 5V which is above the maximum input voltage for the FPGA inputs. 41 | I originally tried a 1Kohm resistor and 3.3V Zener to do the voltage division but looking on the oscilloscope it performed awfully (800 mVpp)! 42 | So I then went back to the obvious of just a resistor voltage divider. This worked fine at 6MHz but was too attenuated at 12MHz to be used. 43 | Adding a 1uF capacitor across the first resistor reduced the attenuation enough to finally become usable. 44 | Next problem was that to produce a 250MHz signal which is needed for the FPGA4FUN HDMI output because it's not a possible multipler for the PLL. 45 | To get around this a DDR type scheme was used. The original code shifted data 10 times a pixel. 46 | Using a DDR scheme I shift data 5 times a pixel but route the first or second bit based on the level of the input clock. 47 | This allowed a 125MHz clock to drive the HDMI output and so now have all the clocks needed. 48 | 49 | Video DAC 50 | --------- 51 | 52 | The video DAC on the MVS is fairly simple resistor divider. 53 | Each digital output is connected via a resistor to the RGB output terminals. 54 | A digital output that's on contributes to the resistance at the top. 55 | A digital output that's off contributes to the resistance at the bottom of the divider. 56 | The monitor would have an input resistance (probably 75 ohms) which also adds to the bottom of the divider. 57 | The two slightly different and originally confusing part are two digital inputs which effect red, green and blue simulataneously. 58 | Shadow and DAK (Darken?). Both of these go through not gates which crucially are open collector outputs. 59 | This means they only sync current and so their resistors only add to the bottom of the divider. 60 | Shadow effectively darkens the output by 0.75. 61 | DAK seems very ineffective. It looks like it should add a new LSB but due to the use of an open collector it has much less effect especially at the low range. 62 | The video ramp in general is reasonably linear but has gaps due to the resistors being common values and not precisely what's needed. 63 | I decided to avoid the bad ramp and ineffective DAK input as the intention for a linear ramp and an additional LSB seems obvious and it's probably an improvement over the original. 64 | Shadow was implemented as a 0.75 multiply however it seems at least on the game I have neither shadow or DAK are used. 65 | 66 | Scan doubling 67 | ------------- 68 | 69 | The JAMMA video standard is basically NTSC (the old TV standard) but with RGB and sync pre seperated. 70 | HDMI won't allow any resolution lower than 640x480. NTSC is 640x240 each frame as it's interlaced so each frame only has the odd or even lines. 71 | Therefore the signal can't be fed in directly. Instead each line has to be sent twice to meet the minimum requirements. 72 | This is done by using the small amount of RAM on the FPGA. 73 | Over the course of two lines the data read from the MVS is stored into RAM. 74 | While this is happening the last line of data is being output twice. 75 | This doesn't work perfectly. The original image was interlaced and it's obvious on some effects that they are not like they used to be. 76 | For example the shadows now obviously flicker instead of looking stripey on the a CRT. 77 | To get some of this effect alternate lines are dimmed each frame (black made the whole image too dim). 78 | It'd be better to have the dimmed data from the last frame (recreating the phosperous on a TV slowly fading) but the amount of RAM availible is only another for a handful of lines and nothing like a whole frame. 79 | 80 | Synchronisation 81 | --------------- 82 | 83 | At this stage the whole image was now being displayed correctly but it wasn't synced at all so the image appeared somewhere randomly on screen. 84 | The obvious thing to use would be the SYNC output that goes to the JAMMA connector. 85 | Unfortunately there isn't a nice place to tap it out apart form the JAMMA connector and that'd interfer with connecting a JAMMA connector. 86 | Luckily the video latches have a CLEAR input to stop data being clocked out when HSYNC or VSYNC are active. This is effectively exactly the same as the SYNC output at the JAMMA connector. 87 | While clocking out HDMI data if we see CLEAR being high when we're displaying data the counters are reset. 88 | And finally we now have a syncronised, scan doubled video output. 89 | 90 | Sound 91 | ----- 92 | 93 | After so many issues with video sound actually turned out to be incredibly 94 | straight forward. The chip on my board was a BU9480F which is a stereo DAC. It 95 | has three lines: Clock, Data and LRCK. Clock and Data form a simple two line 96 | serial interface. The LRCK is high for data intended for the left channel, low 97 | for the right channel. When LRCK transitions all the data for that channel has 98 | been transfered. 99 | 100 | The tricky bit is that the frequency of LRCK is 55.6KHz which means we get 101 | 55.6KHz audio. Unfortunately this is not a nice multiple of any standard audio 102 | frequency. Also the HDMI spec says we can only assume 32KHz audio support. I 103 | implemented very basic downsampling (just point sampling at 32KHz) which isn't 104 | the best quality possible but the output sounds good to my ear. 105 | 106 | Sound over HDMI 107 | --------------- 108 | 109 | This was a huge, huge pain to get working. Mainly due to getting the data islands working correctly (the difference between a DVI signal and a HDMI one). After this it was just a case of getting the channel status bit stream working correctly and the parity bits correct. Hopefully this code will serve as a help to people that try this after me. 110 | 111 | Overclocking 112 | ------------ 113 | 114 | The test monitor I used accepted a 24MHz pixel clock and that the signal 115 | timing was out of spec (only 768 horizontal pixels including control periods 116 | instead of 800 and an extra 3 lines on the vertical. My TVs proved a lot 117 | fussier though. So, I knew I had to get to a standard timing. The biggest 118 | problem was that the Neo Geo was outputing just 59.1fps. Therefore whatever I 119 | did I couldn't achieve a standard timing without having enough memory to store 120 | an entire frame (and accept screen tearing). I needed to overclock the NeoGeo 121 | to get to 60fps. Hopefully the speed up would be so small as to be 122 | inperceptable. 123 | 124 | To get 60 I would need to overclock the NeoGeo to 24.33024MHz. We aren't luck 125 | enough for that to be a standard frequency and it isn't a nice multiple of any 126 | of the pixel clocks. Therefore I decided to drive the NeoGeo from the FPGA and 127 | overclock the occational cycle so that the NeoGeo would complete a frame every 128 | 60th of a second. 129 | 130 | I chose to run the pixel clock at 27MHz (rate for 720x480p at 60) which meant 131 | the DDR TMDS clock was only 135MHz. Every positive edge of the TMDS clock I 132 | checked to see if enough time had passed that I needed to toggle the NeoGeo 133 | clock. This effectively meant running at 24.54MHz (with uneven duty cycle) 134 | with the occational downclock to 22.5MHz. The NeoGeo didn't seem to mind this 135 | luckily. 136 | 137 | All that was left to do was split the pixel reading (based on the NeoGeo's 138 | new clock) from the output (pixel clock based). The 3 fewer vertical lines 139 | on the output meant that the line buffer had to be big enough to allow the 140 | NeoGeo to run up to 3 lines ahead but that was a trivial change. All this work 141 | meant we were now perfectly in spec. 142 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | HDMI output for NeoGeo MVS 2 | ========================== 3 | 4 | Summary: The digital video and audio outputs from the Neo Geo MVS are tapped off before going through the DACs. Instead an FPGA reads the data and outputs the signal over HDMI forming a direct digital to digital connection. 5 | 6 | This video should explain things: 7 | 8 | IMAGE ALT TEXT HERE 11 | 12 | The FPGA generates the HDMI video signal with data islands to embed the audio. It also controls the clock of the Neo Geo MVS so it can produce the exact 720x480p at 60fps timing that the HDMI specification demands. See the [notes](Notes.md) for more details. 13 | 14 | If you've built hardware based on older releases of the [wiring](Wiring.md) information then note that in the new build I've changed pin 73 to pin 104 for the lowest bit of the blue channel. This is because pin 73 was connected to the power rail on the dev board. 15 | 16 | *This project might also be notable in that it's one of the very few (that I know of) that features working audio over HDMI.* 17 | 18 | *Nb. The code was originally based off the HDMI/DVI sample code from [fpga4fun.com](http://www.fpga4fun.com/HDMI.html).* 19 | -------------------------------------------------------------------------------- /Wiring.md: -------------------------------------------------------------------------------- 1 | Wiring 2 | ====== 3 | 4 | Wiring is fairly straight forward. It doesn't seem worth making a schematic as it's all just point to point stuff. 5 | 6 | FPGA to HDMI 7 | ------------ 8 | 9 | | HDMI | FPGA | 10 | | --------------------------------------------------- | ------------------------------------------- | 11 | | ```Pin 1 TMDS Data2+ ``` | ```Pin 32 hdmip[2] ``` | 12 | | ```Pin 2 TMDS Data2 Shield ``` | ```GND ``` | 13 | | ```Pin 3 TMDS Data2− ``` | ```Pin 31 hdmin[2] ``` | 14 | | ```Pin 4 TMDS Data1+ ``` | ```Pin 30 hdmip[1] ``` | 15 | | ```Pin 5 TMDS Data1 Shield ``` | ```GND ``` | 16 | | ```Pin 6 TMDS Data1− ``` | ```Pin 28 hdmin[1] ``` | 17 | | ```Pin 7 TMDS Data0+ ``` | ```Pin 7 hdmip[0] ``` | 18 | | ```Pin 8 TMDS Data0 Shield ``` | ```GND ``` | 19 | | ```Pin 9 TMDS Data0− ``` | ```Pin 8 hdmin[0] ``` | 20 | | ```Pin 10 TMDS Clock+ ``` | ```Pin 25 hdmiclkp ``` | 21 | | ```Pin 11 TMDS Clock Shield ``` | ```GND ``` | 22 | | ```Pin 12 TMDS Clock− ``` | ```Pin 24 hdmiclkn ``` | 23 | | ```Pin 13 CEC ``` | ```NC ``` | 24 | | ```Pin 14 Reserved ``` | ```NC ``` | 25 | | ```Pin 15 SCL (I²C Serial Clock for DDC) ``` | ```NC 1K pull up to 5V ``` | 26 | | ```Pin 16 SDA (I²C Serial Data Line for DDC) ``` | ```NC 1K pull up to 5V ``` | 27 | | ```Pin 17 DDC/CEC/ARC/HEC Ground ``` | ```GND ``` | 28 | | ```Pin 18 +5 V ``` | ```Vin +5V (Power input) ``` | 29 | | ```Pin 19 Hot Plug detect ``` | ```NC ``` | 30 | 31 | 32 | Neo Geo to FPGA 33 | --------------- 34 | 35 | | FPGA | Neo Geo MVS (SvC board) | 36 | | ---------------------------- | -------------------------------------------------------------------------------- | 37 | | ```Pin 64 NEOGEOCLK ``` | ```OSC Oscillator removed and this wired into the right hand pin ``` | 38 | | ```Pin 75 R[0] ``` | ```IC7 Pin 16 Red[0] (Found 3.9Kohm to red JAMMA output) ``` | 39 | | ```Pin 92 R[1] ``` | ```IC7 Pin 2 Red[1] (Found 2.2Kohm to red JAMMA output) ``` | 40 | | ```Pin 90 R[2] ``` | ```IC7 Pin 5 Red[2] (Found 1Kohm to red JAMMA output) ``` | 41 | | ```Pin 87 R[3] ``` | ```IC7 Pin 6 Red[3] (Found 470ohm to red JAMMA output) ``` | 42 | | ```Pin 100 R[4] ``` | ```IC7 Pin 9 Red[4] (Found 220ohm to red JAMMA output) ``` | 43 | | ```Pin 74 G[0] ``` | ```IC7 Pin 15 Green[0] (Found 3.9Kohm to green JAMMA output) ``` | 44 | | ```Pin 101 G[1] ``` | ```IC6 Pin 12 Green[1] (Found 2.2Kohm to green JAMMA output) ``` | 45 | | ```Pin 86 G[2] ``` | ```IC6 Pin 15 Green[2] (Found 1Kohm to green JAMMA output) ``` | 46 | | ```Pin 89 G[3] ``` | ```IC6 Pin 16 Green[3] (Found 470ohm to green JAMMA output) ``` | 47 | | ```Pin 91 G[4] ``` | ```IC6 Pin 19 Green[4] (Found 220ohm to green JAMMA output) ``` | 48 | | ```Pin 104 B[0] ``` | ```IC7 Pin 12 Blue[0] (Found 3.9Kohm to blue JAMMA output) ``` | 49 | | ```Pin 97 B[1] ``` | ```IC6 Pin 2 Blue[1] (Found 2.2Kohm to blue JAMMA output) ``` | 50 | | ```Pin 96 B[2] ``` | ```IC6 Pin 5 Blue[2] (Found 1Kohm to blue JAMMA output) ``` | 51 | | ```Pin 94 B[3] ``` | ```IC6 Pin 6 Blue[3] (Found 470ohm to blue JAMMA output) ``` | 52 | | ```Pin 93 B[4] ``` | ```IC6 Pin 9 Blue[4] (Found 220ohm to blue JAMMA output) ``` | 53 | | ```Pin 79 DAK ``` | ```IC7 Pin 19 DAK (Didn't check) ``` | 54 | | ```Pin 99 SHA ``` | ```IC8 Pin 4 SHA (Found 150ohm to red JAMMA output. See note) ``` | 55 | | ```Pin 103 SYNC ``` | ```IC6 Pin 1 Clear ``` | 56 | | ```Pin 114 audioLR ``` | ```IC12 Pin 5 LRCK ``` | 57 | | ```Pin 120 audioClk ``` | ```IC12 Pin 7 BCLK ``` | 58 | | ```Pin 118 audioData ``` | ```IC12 Pin 6 SDAT ``` | 59 | 60 | Note IC8 is a 74LS05 which is open collector. Therefore we must use the inputs of the logic gate, otherwise it'd be effected by the other outputs when high. Be careful of this if transposing to a different board. 61 | 62 | If you are doing this on an older Neo Geo with a YM3016 audio DAC then you need to change the audio connections. 63 | 64 | | FPGA | YM3016 | 65 | | ---------------------------- | -------------------------------------------------------------------------------- | 66 | | ```Pin 114 audioLR ``` | ```Pin 8 SMP1 ``` | 67 | | ```Pin 112 audioLR2 ``` | ```Pin 7 SMP2 ``` | 68 | | ```Pin 120 audioClk ``` | ```Pin 5 CLOCK ``` | 69 | | ```Pin 118 audioData ``` | ```Pin 4 SD ``` | 70 | 71 | Previsional info for wiring on MV1-FS. Update coming 72 | 73 | |IC |Pin|Name | FPGA Pin | 74 | |-------------|---|-----|-----------| 75 | |Left LS273 |2 |G480 | Pin 89 | 76 | |Left LS273 |5 |G220 | Pin 91 | 77 | |Left LS273 |6 |R3K8 | Pin 75 | 78 | |Left LS273 |9 |R2K2 | Pin 92 | 79 | |Left LS273 |12 |R1K0 | Pin 90 | 80 | |Left LS273 |15 |R470 | Pin 87 | 81 | |Left LS273 |16 |R220 | Pin 100 | 82 | |Left LS273 |19 |DAK | Pin 79 | 83 | |Right LS273 |1 |!CLR | Pin 103 | 84 | |Right LS273 |2 |B3K8 | Pin 104 | 85 | |Right LS273 |5 |B2K2 | Pin 97 | 86 | |Right LS273 |6 |B1K0 | Pin 96 | 87 | |Right LS273 |9 |B470 | Pin 94 | 88 | |Right LS273 |12 |B220 | Pin 93 | 89 | |Right LS273 |15 |G3K8 | Pin 74 | 90 | |Right LS273 |16 |G2K2 | Pin 101 | 91 | |Right LS273 |19 |G1K0 | Pin 86 | 92 | |LS05 |1 |!R150| Pin 99 | 93 | |LS05 |2 |R150 | | 94 | |LS05 |4 |G150 | | 95 | |LS05 |6 |B150 | | 96 | |LS05 |8 |B8K3 | | 97 | |LS05 |10 |G8K3 | | 98 | |LS05 |12 |R8K3 | | 99 | 100 | *All lines go through 500Ohm/1KOhm resistor voltage dividers to get from 5V input to 3.3V output. Except NEOGEOCLK which is the only output from the FPGA and drives OSC input directly.* 101 | 102 | FPGA dev board internals 103 | ------------------------ 104 | 105 | ``` 106 | Pin 17 INCLK 50MHz clock 107 | Pin 144 SWITCH 108 | ``` 109 | 110 | *INCLK goes through the PLL to generate 27MHz (pixclk) and 135MHz (pixclk72). SWITCH needs the weak internal pull up set to work.* 111 | -------------------------------------------------------------------------------- /altera/13.0sp1/HDMIDirect.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 216 128) 24 | (text "HDMIDirect" (rect 5 0 53 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "pixclk" (rect 0 0 21 12)(font "Arial" )) 30 | (text "pixclk" (rect 21 27 42 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clk_TMDS" (rect 0 0 43 12)(font "Arial" )) 37 | (text "clk_TMDS" (rect 21 43 64 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 200 32) 42 | (output) 43 | (text "TMDSp[2..0]" (rect 0 0 51 12)(font "Arial" )) 44 | (text "TMDSp[2..0]" (rect 128 27 179 39)(font "Arial" )) 45 | (line (pt 200 32)(pt 184 32)(line_width 3)) 46 | ) 47 | (port 48 | (pt 200 48) 49 | (output) 50 | (text "TMDSn[2..0]" (rect 0 0 51 12)(font "Arial" )) 51 | (text "TMDSn[2..0]" (rect 128 43 179 55)(font "Arial" )) 52 | (line (pt 200 48)(pt 184 48)(line_width 3)) 53 | ) 54 | (port 55 | (pt 200 64) 56 | (output) 57 | (text "TMDSp_clock" (rect 0 0 57 12)(font "Arial" )) 58 | (text "TMDSp_clock" (rect 122 59 179 71)(font "Arial" )) 59 | (line (pt 200 64)(pt 184 64)(line_width 1)) 60 | ) 61 | (port 62 | (pt 200 80) 63 | (output) 64 | (text "TMDSn_clock" (rect 0 0 57 12)(font "Arial" )) 65 | (text "TMDSn_clock" (rect 122 75 179 87)(font "Arial" )) 66 | (line (pt 200 80)(pt 184 80)(line_width 1)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 184 96)(line_width 1)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /altera/13.0sp1/HDMIDirect.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 12:41:04 December 20, 2014 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "12:41:04 December 20, 2014" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "HDMIDirect" 31 | -------------------------------------------------------------------------------- /altera/13.0sp1/HDMIDirect.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 12:41:04 December 20, 2014 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # HDMIDirect_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone II" 40 | set_global_assignment -name DEVICE EP2C5T144C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY HDMIDirect 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:41:04 DECEMBER 20, 2014" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 52 | set_global_assignment -name VERILOG_FILE HDMIDirect.v 53 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 54 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 55 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 56 | set_global_assignment -name BDF_FILE HDMIDirect.bdf 57 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 58 | set_location_assignment PIN_88 -to clk 59 | set_location_assignment PIN_24 -to hdmiclkn 60 | set_location_assignment PIN_25 -to hdmiclkp 61 | set_location_assignment PIN_8 -to hdmin[0] 62 | set_location_assignment PIN_28 -to hdmin[1] 63 | set_location_assignment PIN_31 -to hdmin[2] 64 | set_location_assignment PIN_7 -to hdmip[0] 65 | set_location_assignment PIN_30 -to hdmip[1] 66 | set_location_assignment PIN_32 -to hdmip[2] 67 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmiclkn 68 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmiclkp 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmin[2] 70 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmin[1] 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmin[0] 72 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmip[2] 73 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmip[0] 74 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hdmip[1] 75 | set_location_assignment PIN_75 -to R[0] 76 | set_location_assignment PIN_104 -to B[0] 77 | set_location_assignment PIN_74 -to G[0] 78 | set_location_assignment PIN_79 -to DAK 79 | set_location_assignment PIN_101 -to G[1] 80 | set_location_assignment PIN_100 -to R[4] 81 | set_location_assignment PIN_87 -to R[3] 82 | set_location_assignment PIN_90 -to R[2] 83 | set_location_assignment PIN_92 -to R[1] 84 | set_location_assignment PIN_86 -to G[2] 85 | set_location_assignment PIN_89 -to G[3] 86 | set_location_assignment PIN_91 -to G[4] 87 | set_location_assignment PIN_97 -to B[1] 88 | set_location_assignment PIN_96 -to B[2] 89 | set_location_assignment PIN_94 -to B[3] 90 | set_location_assignment PIN_93 -to B[4] 91 | set_location_assignment PIN_99 -to SHA 92 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to B[4] 93 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to B[3] 94 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to B[2] 95 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to B[1] 96 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to B[0] 97 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to clk 98 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DAK 99 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to G[4] 100 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to G[3] 101 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to G[2] 102 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to G[1] 103 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to G[0] 104 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SHA 105 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to R[0] 106 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to R[1] 107 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to R[3] 108 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to R[4] 109 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to R[2] 110 | set_location_assignment PIN_144 -to SWITCH 111 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SWITCH 112 | set_location_assignment PIN_103 -to SYNC 113 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SYNC 114 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SWITCH 115 | set_location_assignment PIN_114 -to audioLR 116 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to audioLR 117 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to audioData 118 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to audioClk 119 | set_location_assignment PIN_118 -to audioData 120 | set_location_assignment PIN_120 -to audioClk 121 | set_global_assignment -name QIP_FILE altpll_masterclk.qip 122 | set_location_assignment PIN_17 -to INCLK 123 | set_location_assignment PIN_64 -to NEOGEOCLK 124 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to NEOGEOCLK 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to audioLR 126 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to audioData 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to audioClk 128 | set_location_assignment PIN_112 -to audioLR2 129 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to audioLR2 130 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to audioLR2 131 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to NEOGEOCLK 132 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /altera/13.0sp1/HDMIDirect.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/charcole/NeoGeoHDMI/8d66141d150ea53abcc77258ed8db8890887f646/altera/13.0sp1/HDMIDirect.qws -------------------------------------------------------------------------------- /altera/13.0sp1/HDMIDirectV.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 272 320) 24 | (text "HDMIDirectV" (rect 5 0 61 12)(font "Arial" )) 25 | (text "inst" (rect 8 288 20 300)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "pixclk" (rect 0 0 21 12)(font "Arial" )) 30 | (text "pixclk" (rect 21 27 42 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "pixclk72" (rect 0 0 30 12)(font "Arial" )) 37 | (text "pixclk72" (rect 21 43 51 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "pixclk144" (rect 0 0 36 12)(font "Arial" )) 44 | (text "pixclk144" (rect 21 59 57 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "videobus[16..0]" (rect 0 0 59 12)(font "Arial" )) 51 | (text "videobus[16..0]" (rect 21 75 80 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "Rin[4..0]" (rect 0 0 35 12)(font "Arial" )) 58 | (text "Rin[4..0]" (rect 21 91 56 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 3)) 60 | ) 61 | (port 62 | (pt 0 112) 63 | (input) 64 | (text "Gin[4..0]" (rect 0 0 34 12)(font "Arial" )) 65 | (text "Gin[4..0]" (rect 21 107 55 119)(font "Arial" )) 66 | (line (pt 0 112)(pt 16 112)(line_width 3)) 67 | ) 68 | (port 69 | (pt 0 128) 70 | (input) 71 | (text "Bin[4..0]" (rect 0 0 33 12)(font "Arial" )) 72 | (text "Bin[4..0]" (rect 21 123 54 135)(font "Arial" )) 73 | (line (pt 0 128)(pt 16 128)(line_width 3)) 74 | ) 75 | (port 76 | (pt 0 144) 77 | (input) 78 | (text "dak" (rect 0 0 14 12)(font "Arial" )) 79 | (text "dak" (rect 21 139 35 151)(font "Arial" )) 80 | (line (pt 0 144)(pt 16 144)(line_width 1)) 81 | ) 82 | (port 83 | (pt 0 160) 84 | (input) 85 | (text "sha" (rect 0 0 14 12)(font "Arial" )) 86 | (text "sha" (rect 21 155 35 167)(font "Arial" )) 87 | (line (pt 0 160)(pt 16 160)(line_width 1)) 88 | ) 89 | (port 90 | (pt 0 176) 91 | (input) 92 | (text "button" (rect 0 0 23 12)(font "Arial" )) 93 | (text "button" (rect 21 171 44 183)(font "Arial" )) 94 | (line (pt 0 176)(pt 16 176)(line_width 1)) 95 | ) 96 | (port 97 | (pt 0 192) 98 | (input) 99 | (text "sync" (rect 0 0 20 12)(font "Arial" )) 100 | (text "sync" (rect 21 187 41 199)(font "Arial" )) 101 | (line (pt 0 192)(pt 16 192)(line_width 1)) 102 | ) 103 | (port 104 | (pt 0 208) 105 | (input) 106 | (text "audioLR" (rect 0 0 34 12)(font "Arial" )) 107 | (text "audioLR" (rect 21 203 55 215)(font "Arial" )) 108 | (line (pt 0 208)(pt 16 208)(line_width 1)) 109 | ) 110 | (port 111 | (pt 0 224) 112 | (input) 113 | (text "audioClk" (rect 0 0 33 12)(font "Arial" )) 114 | (text "audioClk" (rect 21 219 54 231)(font "Arial" )) 115 | (line (pt 0 224)(pt 16 224)(line_width 1)) 116 | ) 117 | (port 118 | (pt 0 240) 119 | (input) 120 | (text "audioData" (rect 0 0 38 12)(font "Arial" )) 121 | (text "audioData" (rect 21 235 59 247)(font "Arial" )) 122 | (line (pt 0 240)(pt 16 240)(line_width 1)) 123 | ) 124 | (port 125 | (pt 0 256) 126 | (input) 127 | (text "audioLR2" (rect 0 0 38 12)(font "Arial" )) 128 | (text "audioLR2" (rect 21 251 59 263)(font "Arial" )) 129 | (line (pt 0 256)(pt 16 256)(line_width 1)) 130 | ) 131 | (port 132 | (pt 0 272) 133 | (input) 134 | (text "fontData[7..0]" (rect 0 0 54 12)(font "Arial" )) 135 | (text "fontData[7..0]" (rect 21 267 75 279)(font "Arial" )) 136 | (line (pt 0 272)(pt 16 272)(line_width 3)) 137 | ) 138 | (port 139 | (pt 256 32) 140 | (output) 141 | (text "TMDSp[2..0]" (rect 0 0 51 12)(font "Arial" )) 142 | (text "TMDSp[2..0]" (rect 184 27 235 39)(font "Arial" )) 143 | (line (pt 256 32)(pt 240 32)(line_width 3)) 144 | ) 145 | (port 146 | (pt 256 48) 147 | (output) 148 | (text "TMDSn[2..0]" (rect 0 0 51 12)(font "Arial" )) 149 | (text "TMDSn[2..0]" (rect 184 43 235 55)(font "Arial" )) 150 | (line (pt 256 48)(pt 240 48)(line_width 3)) 151 | ) 152 | (port 153 | (pt 256 64) 154 | (output) 155 | (text "TMDSp_clock" (rect 0 0 57 12)(font "Arial" )) 156 | (text "TMDSp_clock" (rect 178 59 235 71)(font "Arial" )) 157 | (line (pt 256 64)(pt 240 64)(line_width 1)) 158 | ) 159 | (port 160 | (pt 256 80) 161 | (output) 162 | (text "TMDSn_clock" (rect 0 0 57 12)(font "Arial" )) 163 | (text "TMDSn_clock" (rect 178 75 235 87)(font "Arial" )) 164 | (line (pt 256 80)(pt 240 80)(line_width 1)) 165 | ) 166 | (port 167 | (pt 256 96) 168 | (output) 169 | (text "videoaddressw[11..0]" (rect 0 0 81 12)(font "Arial" )) 170 | (text "videoaddressw[11..0]" (rect 154 91 235 103)(font "Arial" )) 171 | (line (pt 256 96)(pt 240 96)(line_width 3)) 172 | ) 173 | (port 174 | (pt 256 112) 175 | (output) 176 | (text "videoramenable" (rect 0 0 62 12)(font "Arial" )) 177 | (text "videoramenable" (rect 173 107 235 119)(font "Arial" )) 178 | (line (pt 256 112)(pt 240 112)(line_width 1)) 179 | ) 180 | (port 181 | (pt 256 128) 182 | (output) 183 | (text "videoramclk" (rect 0 0 48 12)(font "Arial" )) 184 | (text "videoramclk" (rect 187 123 235 135)(font "Arial" )) 185 | (line (pt 256 128)(pt 240 128)(line_width 1)) 186 | ) 187 | (port 188 | (pt 256 144) 189 | (output) 190 | (text "videoramoutclk" (rect 0 0 60 12)(font "Arial" )) 191 | (text "videoramoutclk" (rect 175 139 235 151)(font "Arial" )) 192 | (line (pt 256 144)(pt 240 144)(line_width 1)) 193 | ) 194 | (port 195 | (pt 256 160) 196 | (output) 197 | (text "videowrite" (rect 0 0 38 12)(font "Arial" )) 198 | (text "videowrite" (rect 197 155 235 167)(font "Arial" )) 199 | (line (pt 256 160)(pt 240 160)(line_width 1)) 200 | ) 201 | (port 202 | (pt 256 176) 203 | (output) 204 | (text "videoaddressoutw[11..0]" (rect 0 0 93 12)(font "Arial" )) 205 | (text "videoaddressoutw[11..0]" (rect 142 171 235 183)(font "Arial" )) 206 | (line (pt 256 176)(pt 240 176)(line_width 3)) 207 | ) 208 | (port 209 | (pt 256 192) 210 | (output) 211 | (text "videobusoutw[16..0]" (rect 0 0 76 12)(font "Arial" )) 212 | (text "videobusoutw[16..0]" (rect 159 187 235 199)(font "Arial" )) 213 | (line (pt 256 192)(pt 240 192)(line_width 3)) 214 | ) 215 | (port 216 | (pt 256 208) 217 | (output) 218 | (text "neogeoclk" (rect 0 0 38 12)(font "Arial" )) 219 | (text "neogeoclk" (rect 197 203 235 215)(font "Arial" )) 220 | (line (pt 256 208)(pt 240 208)(line_width 1)) 221 | ) 222 | (port 223 | (pt 256 224) 224 | (output) 225 | (text "fontAddress[10..0]" (rect 0 0 74 12)(font "Arial" )) 226 | (text "fontAddress[10..0]" (rect 161 219 235 231)(font "Arial" )) 227 | (line (pt 256 224)(pt 240 224)(line_width 3)) 228 | ) 229 | (port 230 | (pt 256 240) 231 | (output) 232 | (text "fontROMClock" (rect 0 0 61 12)(font "Arial" )) 233 | (text "fontROMClock" (rect 174 235 235 247)(font "Arial" )) 234 | (line (pt 256 240)(pt 240 240)(line_width 1)) 235 | ) 236 | (drawing 237 | (rectangle (rect 16 16 240 288)(line_width 1)) 238 | ) 239 | ) 240 | -------------------------------------------------------------------------------- /altera/13.0sp1/HDMI_test.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 200 128) 24 | (text "HDMI_test" (rect 5 0 49 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "pixclk" (rect 0 0 21 12)(font "Arial" )) 30 | (text "pixclk" (rect 21 27 42 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 184 32) 35 | (output) 36 | (text "TMDSp[2..0]" (rect 0 0 51 12)(font "Arial" )) 37 | (text "TMDSp[2..0]" (rect 112 27 163 39)(font "Arial" )) 38 | (line (pt 184 32)(pt 168 32)(line_width 3)) 39 | ) 40 | (port 41 | (pt 184 48) 42 | (output) 43 | (text "TMDSn[2..0]" (rect 0 0 51 12)(font "Arial" )) 44 | (text "TMDSn[2..0]" (rect 112 43 163 55)(font "Arial" )) 45 | (line (pt 184 48)(pt 168 48)(line_width 3)) 46 | ) 47 | (port 48 | (pt 184 64) 49 | (output) 50 | (text "TMDSp_clock" (rect 0 0 57 12)(font "Arial" )) 51 | (text "TMDSp_clock" (rect 106 59 163 71)(font "Arial" )) 52 | (line (pt 184 64)(pt 168 64)(line_width 1)) 53 | ) 54 | (port 55 | (pt 184 80) 56 | (output) 57 | (text "TMDSn_clock" (rect 0 0 57 12)(font "Arial" )) 58 | (text "TMDSn_clock" (rect 106 75 163 87)(font "Arial" )) 59 | (line (pt 184 80)(pt 168 80)(line_width 1)) 60 | ) 61 | (drawing 62 | (rectangle (rect 16 16 168 96)(line_width 1)) 63 | ) 64 | ) 65 | -------------------------------------------------------------------------------- /altera/13.0sp1/TERC4_encoder.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 200 96) 24 | (text "TERC4_encoder" (rect 5 0 76 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "data[3..0]" (rect 0 0 36 12)(font "Arial" )) 37 | (text "data[3..0]" (rect 21 43 57 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 184 32) 42 | (output) 43 | (text "TERC[9..0]" (rect 0 0 48 12)(font "Arial" )) 44 | (text "TERC[9..0]" (rect 115 27 163 39)(font "Arial" )) 45 | (line (pt 184 32)(pt 168 32)(line_width 3)) 46 | ) 47 | (drawing 48 | (rectangle (rect 16 16 168 64)(line_width 1)) 49 | ) 50 | ) 51 | -------------------------------------------------------------------------------- /altera/13.0sp1/TMDS_encoder.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 200 128) 24 | (text "TMDS_encoder" (rect 5 0 69 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "VD[7..0]" (rect 0 0 35 12)(font "Arial" )) 37 | (text "VD[7..0]" (rect 21 43 56 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "CD[1..0]" (rect 0 0 33 12)(font "Arial" )) 44 | (text "CD[1..0]" (rect 21 59 54 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "VDE" (rect 0 0 22 12)(font "Arial" )) 51 | (text "VDE" (rect 21 75 43 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 1)) 53 | ) 54 | (port 55 | (pt 184 32) 56 | (output) 57 | (text "TMDS[9..0]" (rect 0 0 47 12)(font "Arial" )) 58 | (text "TMDS[9..0]" (rect 116 27 163 39)(font "Arial" )) 59 | (line (pt 184 32)(pt 168 32)(line_width 3)) 60 | ) 61 | (drawing 62 | (rectangle (rect 16 16 168 96)(line_width 1)) 63 | ) 64 | ) 65 | -------------------------------------------------------------------------------- /altera/13.0sp1/altpll_masterclk.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 240 176) 24 | (text "altpll_masterclk" (rect 74 0 183 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 161 26 172)(font "Arial" )) 26 | (port 27 | (pt 0 64) 28 | (input) 29 | (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) 30 | (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) 31 | (line (pt 0 64)(pt 40 64)) 32 | ) 33 | (port 34 | (pt 240 64) 35 | (output) 36 | (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) 37 | (text "c0" (rect 225 51 237 63)(font "Arial" (font_size 8))) 38 | ) 39 | (port 40 | (pt 240 80) 41 | (output) 42 | (text "c1" (rect 0 0 15 13)(font "Arial" (font_size 8))) 43 | (text "c1" (rect 225 67 237 79)(font "Arial" (font_size 8))) 44 | ) 45 | (port 46 | (pt 240 96) 47 | (output) 48 | (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) 49 | (text "c2" (rect 225 83 237 95)(font "Arial" (font_size 8))) 50 | ) 51 | (drawing 52 | (text "Cyclone II" (rect 187 162 417 334)(font "Arial" )) 53 | (text "inclk0 frequency: 50.000 MHz" (rect 50 60 226 130)(font "Arial" )) 54 | (text "Operation Mode: Normal" (rect 50 72 203 154)(font "Arial" )) 55 | (text "Clk " (rect 51 91 117 192)(font "Arial" )) 56 | (text "Ratio" (rect 71 91 165 192)(font "Arial" )) 57 | (text "Ph (dg)" (rect 98 91 227 192)(font "Arial" )) 58 | (text "DC (%)" (rect 133 91 298 192)(font "Arial" )) 59 | (text "c0" (rect 54 104 119 218)(font "Arial" )) 60 | (text "27/50" (rect 71 104 166 218)(font "Arial" )) 61 | (text "0.00" (rect 104 104 227 218)(font "Arial" )) 62 | (text "50.00" (rect 137 104 298 218)(font "Arial" )) 63 | (text "c1" (rect 54 117 119 244)(font "Arial" )) 64 | (text "27/10" (rect 71 117 166 244)(font "Arial" )) 65 | (text "0.00" (rect 104 117 227 244)(font "Arial" )) 66 | (text "50.00" (rect 137 117 298 244)(font "Arial" )) 67 | (text "c2" (rect 54 130 119 270)(font "Arial" )) 68 | (text "27/10" (rect 71 130 166 270)(font "Arial" )) 69 | (text "90.00" (rect 102 130 228 270)(font "Arial" )) 70 | (text "50.00" (rect 137 130 298 270)(font "Arial" )) 71 | (line (pt 0 0)(pt 241 0)) 72 | (line (pt 241 0)(pt 241 177)) 73 | (line (pt 0 177)(pt 241 177)) 74 | (line (pt 0 0)(pt 0 177)) 75 | (line (pt 48 89)(pt 165 89)) 76 | (line (pt 48 101)(pt 165 101)) 77 | (line (pt 48 114)(pt 165 114)) 78 | (line (pt 48 127)(pt 165 127)) 79 | (line (pt 48 140)(pt 165 140)) 80 | (line (pt 48 89)(pt 48 140)) 81 | (line (pt 68 89)(pt 68 140)(line_width 3)) 82 | (line (pt 95 89)(pt 95 140)(line_width 3)) 83 | (line (pt 130 89)(pt 130 140)(line_width 3)) 84 | (line (pt 164 89)(pt 164 140)) 85 | (line (pt 40 48)(pt 207 48)) 86 | (line (pt 207 48)(pt 207 159)) 87 | (line (pt 40 159)(pt 207 159)) 88 | (line (pt 40 48)(pt 40 159)) 89 | (line (pt 239 64)(pt 207 64)) 90 | (line (pt 239 80)(pt 207 80)) 91 | (line (pt 239 96)(pt 207 96)) 92 | ) 93 | ) 94 | -------------------------------------------------------------------------------- /altera/13.0sp1/altpll_masterclk.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altera/13.0sp1/altpll_masterclk.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll_masterclk.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_masterclk.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_masterclk_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_masterclk.ppf"] 7 | -------------------------------------------------------------------------------- /altera/13.0sp1/altpll_masterclk.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: altpll_masterclk.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module altpll_masterclk ( 40 | inclk0, 41 | c0, 42 | c1, 43 | c2); 44 | 45 | input inclk0; 46 | output c0; 47 | output c1; 48 | output c2; 49 | 50 | wire [5:0] sub_wire0; 51 | wire [0:0] sub_wire6 = 1'h0; 52 | wire [2:2] sub_wire3 = sub_wire0[2:2]; 53 | wire [0:0] sub_wire2 = sub_wire0[0:0]; 54 | wire [1:1] sub_wire1 = sub_wire0[1:1]; 55 | wire c1 = sub_wire1; 56 | wire c0 = sub_wire2; 57 | wire c2 = sub_wire3; 58 | wire sub_wire4 = inclk0; 59 | wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; 60 | 61 | altpll altpll_component ( 62 | .inclk (sub_wire5), 63 | .clk (sub_wire0), 64 | .activeclock (), 65 | .areset (1'b0), 66 | .clkbad (), 67 | .clkena ({6{1'b1}}), 68 | .clkloss (), 69 | .clkswitch (1'b0), 70 | .configupdate (1'b0), 71 | .enable0 (), 72 | .enable1 (), 73 | .extclk (), 74 | .extclkena ({4{1'b1}}), 75 | .fbin (1'b1), 76 | .fbmimicbidir (), 77 | .fbout (), 78 | .fref (), 79 | .icdrclk (), 80 | .locked (), 81 | .pfdena (1'b1), 82 | .phasecounterselect ({4{1'b1}}), 83 | .phasedone (), 84 | .phasestep (1'b1), 85 | .phaseupdown (1'b1), 86 | .pllena (1'b1), 87 | .scanaclr (1'b0), 88 | .scanclk (1'b0), 89 | .scanclkena (1'b1), 90 | .scandata (1'b0), 91 | .scandataout (), 92 | .scandone (), 93 | .scanread (1'b0), 94 | .scanwrite (1'b0), 95 | .sclkout0 (), 96 | .sclkout1 (), 97 | .vcooverrange (), 98 | .vcounderrange ()); 99 | defparam 100 | altpll_component.clk0_divide_by = 50, 101 | altpll_component.clk0_duty_cycle = 50, 102 | altpll_component.clk0_multiply_by = 27, 103 | altpll_component.clk0_phase_shift = "0", 104 | altpll_component.clk1_divide_by = 10, 105 | altpll_component.clk1_duty_cycle = 50, 106 | altpll_component.clk1_multiply_by = 27, 107 | altpll_component.clk1_phase_shift = "0", 108 | altpll_component.clk2_divide_by = 10, 109 | altpll_component.clk2_duty_cycle = 50, 110 | altpll_component.clk2_multiply_by = 27, 111 | altpll_component.clk2_phase_shift = "1852", 112 | altpll_component.compensate_clock = "CLK0", 113 | altpll_component.inclk0_input_frequency = 20000, 114 | altpll_component.intended_device_family = "Cyclone II", 115 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpll_masterclk", 116 | altpll_component.lpm_type = "altpll", 117 | altpll_component.operation_mode = "NORMAL", 118 | altpll_component.port_activeclock = "PORT_UNUSED", 119 | altpll_component.port_areset = "PORT_UNUSED", 120 | altpll_component.port_clkbad0 = "PORT_UNUSED", 121 | altpll_component.port_clkbad1 = "PORT_UNUSED", 122 | altpll_component.port_clkloss = "PORT_UNUSED", 123 | altpll_component.port_clkswitch = "PORT_UNUSED", 124 | altpll_component.port_configupdate = "PORT_UNUSED", 125 | altpll_component.port_fbin = "PORT_UNUSED", 126 | altpll_component.port_inclk0 = "PORT_USED", 127 | altpll_component.port_inclk1 = "PORT_UNUSED", 128 | altpll_component.port_locked = "PORT_UNUSED", 129 | altpll_component.port_pfdena = "PORT_UNUSED", 130 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 131 | altpll_component.port_phasedone = "PORT_UNUSED", 132 | altpll_component.port_phasestep = "PORT_UNUSED", 133 | altpll_component.port_phaseupdown = "PORT_UNUSED", 134 | altpll_component.port_pllena = "PORT_UNUSED", 135 | altpll_component.port_scanaclr = "PORT_UNUSED", 136 | altpll_component.port_scanclk = "PORT_UNUSED", 137 | altpll_component.port_scanclkena = "PORT_UNUSED", 138 | altpll_component.port_scandata = "PORT_UNUSED", 139 | altpll_component.port_scandataout = "PORT_UNUSED", 140 | altpll_component.port_scandone = "PORT_UNUSED", 141 | altpll_component.port_scanread = "PORT_UNUSED", 142 | altpll_component.port_scanwrite = "PORT_UNUSED", 143 | altpll_component.port_clk0 = "PORT_USED", 144 | altpll_component.port_clk1 = "PORT_USED", 145 | altpll_component.port_clk2 = "PORT_USED", 146 | altpll_component.port_clk3 = "PORT_UNUSED", 147 | altpll_component.port_clk4 = "PORT_UNUSED", 148 | altpll_component.port_clk5 = "PORT_UNUSED", 149 | altpll_component.port_clkena0 = "PORT_UNUSED", 150 | altpll_component.port_clkena1 = "PORT_UNUSED", 151 | altpll_component.port_clkena2 = "PORT_UNUSED", 152 | altpll_component.port_clkena3 = "PORT_UNUSED", 153 | altpll_component.port_clkena4 = "PORT_UNUSED", 154 | altpll_component.port_clkena5 = "PORT_UNUSED", 155 | altpll_component.port_extclk0 = "PORT_UNUSED", 156 | altpll_component.port_extclk1 = "PORT_UNUSED", 157 | altpll_component.port_extclk2 = "PORT_UNUSED", 158 | altpll_component.port_extclk3 = "PORT_UNUSED"; 159 | 160 | 161 | endmodule 162 | 163 | // ============================================================ 164 | // CNX file retrieval info 165 | // ============================================================ 166 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 168 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" 169 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 170 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 171 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 172 | // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" 173 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 174 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 175 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 176 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" 177 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 178 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 179 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 180 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 181 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 182 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 183 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 184 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 185 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 186 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 187 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 188 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 189 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000" 190 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "135.000000" 191 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "135.000000" 192 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 193 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 194 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 195 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" 196 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 197 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 198 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 199 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 200 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 201 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 202 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 203 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 204 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 205 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 206 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 207 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 208 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 209 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 210 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 211 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 212 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 213 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" 214 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 215 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 216 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 217 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 218 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 219 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 220 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 221 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 222 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.00000000" 223 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "135.00000000" 224 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "135.00000000" 225 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 226 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 227 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 228 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 229 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 230 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 231 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" 232 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 233 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 234 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 235 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "90.00000000" 236 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 237 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 238 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" 239 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" 240 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 241 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 242 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 243 | // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" 244 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 245 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 246 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 247 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 248 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 249 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 250 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 251 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll_masterclk.mif" 252 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 253 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" 254 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 255 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 256 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 257 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 258 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 259 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 260 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 261 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 262 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 263 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 264 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 265 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 266 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 267 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 268 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 269 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 270 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 271 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 272 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 273 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 274 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 275 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 276 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 277 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" 278 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 279 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "27" 280 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 281 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "10" 282 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 283 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "27" 284 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 285 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10" 286 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 287 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "27" 288 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1852" 289 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 290 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 291 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 292 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 293 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 294 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 295 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 296 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 297 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 298 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 299 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 300 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 301 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 302 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 303 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 304 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 305 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 306 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 307 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 308 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 309 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 310 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 311 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 312 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 313 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 314 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 315 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 316 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 317 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 318 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 319 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 320 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 321 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 322 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 323 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 324 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 325 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 326 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 327 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 328 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 329 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 330 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 331 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 332 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 333 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 334 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 335 | // Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" 336 | // Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" 337 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 338 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 339 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 340 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 341 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 342 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 343 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 344 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 345 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 346 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.v TRUE 347 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.ppf TRUE 348 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.inc FALSE 349 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.cmp FALSE 350 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.bsf TRUE 351 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk_inst.v FALSE 352 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk_bb.v TRUE 353 | // Retrieval info: LIB_FILE: altera_mf 354 | // Retrieval info: CBX_MODULE_PREFIX: ON 355 | -------------------------------------------------------------------------------- /altera/13.0sp1/altpll_masterclk_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: altpll_masterclk.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module altpll_masterclk ( 35 | inclk0, 36 | c0, 37 | c1, 38 | c2); 39 | 40 | input inclk0; 41 | output c0; 42 | output c1; 43 | output c2; 44 | 45 | endmodule 46 | 47 | // ============================================================ 48 | // CNX file retrieval info 49 | // ============================================================ 50 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 51 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 52 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" 53 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 54 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 55 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 56 | // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" 57 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 58 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 59 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 60 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" 61 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 62 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 63 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 64 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 65 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 66 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 67 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 68 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 69 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 70 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 71 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 72 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 73 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000" 74 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "135.000000" 75 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "135.000000" 76 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 77 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 78 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 79 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" 80 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 81 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 82 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 83 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 84 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 85 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 86 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 87 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 88 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 89 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 90 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 91 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 92 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 93 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 94 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 95 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 96 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 97 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" 98 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 99 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 100 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 101 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 102 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 103 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 104 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 105 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 106 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.00000000" 107 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "135.00000000" 108 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "135.00000000" 109 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 110 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 111 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 112 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 113 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 114 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 115 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" 116 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 117 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 118 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 119 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "90.00000000" 120 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 121 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 122 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" 123 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" 124 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 125 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 126 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 127 | // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" 128 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 129 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 130 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 131 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 132 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 133 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 134 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 135 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll_masterclk.mif" 136 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 137 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" 138 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 139 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 140 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 141 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 142 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 143 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 144 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 145 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 146 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 147 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 148 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 149 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 150 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 151 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 152 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 153 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 154 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 155 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 156 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 157 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 158 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 159 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 160 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 161 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" 162 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 163 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "27" 164 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 165 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "10" 166 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 167 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "27" 168 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 169 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10" 170 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 171 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "27" 172 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1852" 173 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 174 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 175 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 176 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 177 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 178 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 179 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 180 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 181 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 182 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 183 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 184 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 185 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 186 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 187 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 188 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 189 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 190 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 191 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 192 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 193 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 194 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 195 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 196 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 197 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 198 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 199 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 200 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 201 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 202 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 203 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 204 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 205 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 206 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 207 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 208 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 209 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 210 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 211 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 212 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 213 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 214 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 215 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 216 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 217 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 218 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 219 | // Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" 220 | // Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" 221 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 222 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 223 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 224 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 225 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 226 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 227 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 228 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 229 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 230 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.v TRUE 231 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.ppf TRUE 232 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.inc FALSE 233 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.cmp FALSE 234 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk.bsf TRUE 235 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk_inst.v FALSE 236 | // Retrieval info: GEN_FILE: TYPE_NORMAL altpll_masterclk_bb.v TRUE 237 | // Retrieval info: LIB_FILE: altera_mf 238 | // Retrieval info: CBX_MODULE_PREFIX: ON 239 | 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1249 | :0104E000001B 1250 | :0104E100001A 1251 | :0104E2000019 1252 | :0104E3000018 1253 | :0104E4000017 1254 | :0104E5000016 1255 | :0104E6000015 1256 | :0104E7000014 1257 | :0104E8000013 1258 | :0104E9000012 1259 | :0104EA000011 1260 | :0104EB000010 1261 | :0104EC00000F 1262 | :0104ED00000E 1263 | :0104EE00000D 1264 | :0104EF00000C 1265 | :0104F000000B 1266 | :0104F100000A 1267 | :0104F2000009 1268 | :0104F3000008 1269 | :0104F4000007 1270 | :0104F5000006 1271 | :0104F6000005 1272 | :0104F7000004 1273 | :0104F8000003 1274 | :0104F9000002 1275 | :0104FA000001 1276 | :0104FB000000 1277 | :0104FC0000FF 1278 | :0104FD0000FE 1279 | :0104FE0000FD 1280 | :0104FF0000FC 1281 | :00000001FF 1282 | -------------------------------------------------------------------------------- /font/makelogo.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "neogeo.h" 4 | 5 | #define width mwidth 6 | #define height mheight 7 | #define header_data mheader_data 8 | #define header_data_cmap mheader_data_cmap 9 | #include "messages.h" 10 | #undef width 11 | #undef height 12 | #undef header_data 13 | #undef header_data_cmap 14 | 15 | #define CHAR_WIDTH 3 16 | 17 | unsigned char data[CHAR_WIDTH*256+512]; 18 | 19 | void fontCreate() 20 | { 21 | int x,y,c=0; 22 | memset(data, 0, sizeof(data)); 23 | for (x=0; x