├── PT ├── runPTPR ├── runPT ├── NPU_ADD_TREE_PTPX.tcl └── NPU_PTPX_PR.tcl ├── SYN ├── runDC ├── NPU_ADD_TREE.tcl └── NPU_ADD_TREE.sdc ├── LibChar ├── netlists │ └── readme ├── process │ └── readme ├── setup │ ├── klib_setup.tcl │ ├── run180nm.tcl │ └── configure_180nm.tcl ├── Makefile └── inst │ └── A2D4B_SRAM.inst ├── APR ├── pnr │ └── scripts │ │ ├── starrc_in_design.corners.txt │ │ ├── starrc_in_design.config.txt │ │ ├── initialization_settings.tcl │ │ ├── low_power.tcl │ │ ├── 01_icc2_import_design.tcl │ │ ├── starrc_in_design.cmd │ │ ├── 00_common_initial_settings.tcl │ │ ├── 09_chipfinish.tcl │ │ ├── 05_clock.tcl │ │ ├── 04_placeopt.tcl │ │ ├── 02_create_floorplan.tcl │ │ ├── 06_clockopt.tcl │ │ ├── 07_route.tcl │ │ ├── 08_routeopt.tcl │ │ ├── 03_power_routing.tcl │ │ ├── scenarios_setup.tcl │ │ └── place_hard_macros.tcl └── Makefile ├── VCS ├── NPU_ADD_TREE_NETLIST ├── NPU_TREE_PRNetlist └── NPU_CUBE_ADD_TREE ├── README.md ├── Verilog ├── NPU_CUBE_TREE_INPUT.v ├── booth_enc.v ├── NPU_GEN_PROD_EXTEND.v ├── NPU_CUBE_ADD_PRODUCT_CODE.v ├── NPU_CUBE_ADD_TREE_WALLACE_PRODUCT_CODE.v ├── NPU_CUBE_ADD_TREE_WALLACE_EXTEND_SIGN.v ├── NPU_GEN_PROD.v ├── NPU_ADD_TREE_TOP.v ├── NPU_CUBE_ADD_TREE_CODE.v └── NPU_CUBE_ADD_TEST.sv └── Innovus ├── parse_io_to_tcl.py └── pad_place.tcl /PT/runPTPR: -------------------------------------------------------------------------------- 1 | pt_shell -f NPU_PTPX_PR.tcl 2 | -------------------------------------------------------------------------------- /SYN/runDC: -------------------------------------------------------------------------------- 1 | dc_shell -f NPU_ADD_TREE.tcl 2 | -------------------------------------------------------------------------------- /PT/runPT: -------------------------------------------------------------------------------- 1 | pt_shell -f NPU_ADD_TREE_PTPX.tcl 2 | -------------------------------------------------------------------------------- /LibChar/netlists/readme: -------------------------------------------------------------------------------- 1 | put your spice netlists here. 2 | -------------------------------------------------------------------------------- /LibChar/process/readme: -------------------------------------------------------------------------------- 1 | put your process-related files here, such as cr018gpii_v1d0.l 2 | -------------------------------------------------------------------------------- /APR/pnr/scripts/starrc_in_design.corners.txt: -------------------------------------------------------------------------------- 1 | ss0p75v125c_cmax ./library/tech/starrc/saed32nm_1p9m_Cmax.nxtgrd 2 | ff0p95vm40c_cmin ./library/tech/starrc/saed32nm_1p9m_Cmin.nxtgrd 3 | ff0p95v125c_cmin ./library/tech/starrc/saed32nm_1p9m_Cmin.nxtgrd 4 | -------------------------------------------------------------------------------- /VCS/NPU_ADD_TREE_NETLIST: -------------------------------------------------------------------------------- 1 | #/bin/bash 2 | #ALL_DEFINE = +define+NET_SIM 3 | vcs -V -R -timescale=1ns/1ps -sverilog +neg_tchk ../Verilog/NPU_CUBE_ADD_TEST.sv ../SYN/NPU_ADD_TREE.v \ 4 | ../SM28lib/synthesis/lib/scc28nhkcp_hdc30p140_rvt.v \ 5 | +define+SDF_SIM \ 6 | -o simv -gui -debug_pp -full64 7 | -------------------------------------------------------------------------------- /VCS/NPU_TREE_PRNetlist: -------------------------------------------------------------------------------- 1 | #/bin/bash 2 | #ALL_DEFINE = +define+NET_SIM 3 | vcs -V -R -timescale=1ns/1ps -sverilog +neg_tchk ../Verilog/NPU_CUBE_ADD_TEST.sv ../PR/data/NPU_ADD_TREE.v \ 4 | ../SM28lib/synthesis/lib/scc28nhkcp_hdc30p140_rvt.v \ 5 | +define+SDF_PR_SIM \ 6 | -o simv -gui -debug_pp -full64 7 | -------------------------------------------------------------------------------- /APR/pnr/scripts/starrc_in_design.config.txt: -------------------------------------------------------------------------------- 1 | SIGNOFF_IMAGE: singularity exec /home/work/default/container/starrc_hercules.sif StarXtract 2 | MAPPING_FILE: ./library/tech//starrc/saed32nm_tf_itf_tluplus.starrc_in_design.map 3 | CORNER_GRD_FILE:./pnr/scripts/starrc_in_design.corners.txt 4 | COMMAND_FILE:../pnr/scripts/starrc_in_design.cmd 5 | -------------------------------------------------------------------------------- /VCS/NPU_CUBE_ADD_TREE: -------------------------------------------------------------------------------- 1 | #/bin/bash 2 | vcs -V -R -sverilog ../Verilog/NPU_CUBE_ADD_TEST.sv ../Verilog/NPU_ADD_TREE_TOP.v ../Verilog/NPU_CUBE_ADD_TREE_WALLACE_PRODUCT_CODE.v ../Verilog/NPU_CUBE_ADD_PRODUCT_CODE.v ../Verilog/NPU_CUBE_ADD_TREE_CODE.v ../Verilog/NPU_GEN_PROD.v ../Verilog/NPU_GEN_PROD_EXTEND.v ../Verilog/NPU_CUBE_ADD_TREE_WALLACE_EXTEND_SIGN.v ../Verilog/booth_enc.v ../Verilog/NPU_CUBE_TREE_INPUT.v -o simv -gui -debug_pp -full64 3 | -------------------------------------------------------------------------------- /APR/pnr/scripts/initialization_settings.tcl: -------------------------------------------------------------------------------- 1 | ### initialization settings for icc2 2 | ## time unit needs to match with SDC 3 | set_user_units -type time -value 1ns 4 | 5 | set_attribute [get_site_defs unit] symmetry Y 6 | set_attribute [get_site_defs unit] is_default true 7 | 8 | ### what if this is not set 9 | set_attribute [get_layers {M1 M3 M5 M7 M9}] routing_direction horizontal 10 | set_attribute [get_layers {M2 M4 M6 M8 MRDL}] routing_direction vertical 11 | get_attribute [get_layers M?] routing_direction 12 | 13 | set_ignored_layers -min_routing_layer M1 -max_routing_layer M8 14 | set_message_info -id LGL-003 -limit 10 15 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # IC_FLOW 2 | PR脚本已取消Github分享。请前往《吾爱IC社区》获取，读者可在社区内更深入地学习IC的相关Flow。 3 | 2021/11/17 VCS Script upload （RTL simulation） 4 | 2021/11/18 DC Script upload 5 | 2021/11/21 VCS front-end Script upload （Netlist simulation） 6 | 2021/11/22 PT front-end Script upload 7 | 2021/12/01 PR Initial Script upload 8 | 2021/12/02 PR floorplan Script upload 9 | 2021/12/03 PR powerplan Script upload 10 | 2021/12/04 PR placement Script upload 11 | 2021/12/05 PR CTS Script upload 12 | 2021/12/06 PR route Script upload 13 | 2021/12/07 PR chipfinish Script upload 14 | 2021/12/08 PR Spef & sdf Script upload 15 | 2021/12/09 VCS back-end Script upload 16 | 2021/12/10 PT back-end Script upload 17 | 2024/01/12 ICC2 APR Script upload (ref:https://github.com/Juanx65/RISC-V) 18 | 2025/10/26 Innovus PAD placement Script upload 19 | 2025/10/29 Primelib Script (LibChar) upload 20 | -------------------------------------------------------------------------------- /Verilog/NPU_CUBE_TREE_INPUT.v: -------------------------------------------------------------------------------- 1 | //data*para=8_[8*8] 2 | module NPU_CUBE_TREE_INPUT( 3 | clk, 4 | input_add_tree_data, 5 | input_add_tree_para, 6 | add_tree_data, 7 | add_tree_para 8 | ); 9 | 10 | parameter DWA = 8; 11 | parameter DWB = 8; 12 | //3bit: [2]=~+1 [1][0]=* 13 | parameter DWB_CODE = 12; 14 | parameter DWS = 21; 15 | parameter NPU_CUBE_MAC_NUM = 8; 16 | parameter SIGNED_A = 0; 17 | parameter DWM = DWA + DWB; 18 | parameter DWPRODUCT = 19; 19 | parameter DWOUPUT = 19; 20 | parameter DWPPLEN = 9; 21 | 22 | input clk; 23 | input [DWA*NPU_CUBE_MAC_NUM-1:0] input_add_tree_data; 24 | input [DWB*NPU_CUBE_MAC_NUM-1:0] input_add_tree_para; 25 | 26 | output reg [DWA*NPU_CUBE_MAC_NUM-1:0] add_tree_data; 27 | output reg [DWB*NPU_CUBE_MAC_NUM-1:0] add_tree_para; 28 | 29 | always @ (posedge clk) 30 | begin 31 | add_tree_data <= input_add_tree_data; 32 | add_tree_para <= input_add_tree_para; 33 | end 34 | 35 | endmodule -------------------------------------------------------------------------------- /LibChar/setup/klib_setup.tcl: -------------------------------------------------------------------------------- 1 | #if { [info exists env(SYN_ROOT)] } { 2 | # set simple_etm 1 3 | # source -echo -verbose $env(SYN_ROOT)/setup/dc_setup.tcl 4 | #} else { 5 | # set simple_etm 0 6 | # source -echo -verbose $env(PT_ROOT)/setup/pt_common_setup.tcl 7 | #} 8 | 9 | # source $env(PROJ_SRC_ROOT)/common/backend/pt/run_tcl/pt_common_procs.tcl 10 | 11 | # specify synthesis technology from env variable 12 | if { [info exists env(KLIB_CELLS)] } { 13 | set klib_cells $env(KLIB_CELLS) 14 | } else { 15 | puts "env variable klib_cells is not specified" 16 | exit 17 | } 18 | 19 | if { [info exists env(KLIB_TAG)] } { 20 | set klib_tag $env(KLIB_TAG) 21 | } else { 22 | puts "env variable klib_tag is not specified" 23 | exit 24 | } 25 | 26 | if { [info exists env(CFG_FILE)] } { 27 | set cfg_file $env(CFG_FILE) 28 | } else { 29 | puts "env variable cfg_file is not specified" 30 | exit 31 | } 32 | 33 | set klibcells [lsort -unique $klib_cells] 34 | 35 | puts "INFO: klib cells are: $klibcells" 36 | -------------------------------------------------------------------------------- /APR/pnr/scripts/low_power.tcl: -------------------------------------------------------------------------------- 1 | ### preplace level shifters 2 | 3 | ### create bound for LS cells 4 | remove_bounds * 5 | 6 | ### DEFUALT 7 | set default_lvl_cells [get_cells *_UPF_LS] 8 | create_bound -name BOUND_DEFUALT_LS -boundary {{0.0000 596.9040} {489.1360 632.0160}} -exclusive $default_lvl_cells 9 | 10 | ### PD_RISC_CORE domain 11 | set risc_lvl_cells [get_flat_cells I_RISC_CORE/*_UPF_LS] 12 | create_bound -name BOUND_RISC_LS -boundary {{0.0000 642.0480} {489.1360 677.1600}} -exclusive $risc_lvl_cells 13 | 14 | set lvl_buf_prefix "USR_BUF_LS" 15 | set lvl_buf_ref "*/NBUFFX8_LVT" 16 | 17 | ### insert buffer on LS pins 18 | # EndOfInstrn_UPF_LS 19 | set driver_pin [get_flat_pins -of [get_flat_nets -of EndOfInstrn_UPF_LS/A] -filter "direction==out"] 20 | add_buffer -lib_cell $lvl_buf_ref $driver_pin -new_cell_names ${lvl_buf_prefix}_EndOfInstrn_CELL -new_net_names ${lvl_buf_prefix}_EndOfInstrn_NET 21 | 22 | ### set dont_touch on LS nets 23 | set dont_touch_nets "" 24 | append_to_collection dont_touch_nets [get_flat_nets -of [get_flat_pins *${lvl_buf_prefix}*/Y]] 25 | set_dont_touch $dont_touch_nets true 26 | 27 | -------------------------------------------------------------------------------- /APR/pnr/scripts/01_icc2_import_design.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: read gate level netlist into ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | source ./pnr/scripts/00_common_initial_settings.tcl 6 | 7 | ### variables 8 | set current_step "01_icc2_import" 9 | 10 | ### create nlib 11 | file mkdir $nlib_dir 12 | file delete -force $nlib_dir/${design}_${current_step}.nlib 13 | create_lib -technology $synopsys_tech_tf -ref_libs $ndm_files $nlib_dir/${design}_${current_step}.nlib 14 | 15 | ### read verilog 16 | read_verilog -library ${design}_${current_step}.nlib -design ${design} -top $design $import_netlists 17 | 18 | ### initialization script 19 | source ./pnr/scripts/initialization_settings.tcl 20 | 21 | ### load upf 22 | set_app_options -name mv.upf.enable_golden_upf -value true 23 | reset_upf 24 | load_upf $golden_upf 25 | commit_upf 26 | 27 | ### connect pg 28 | connect_pg_net -automatic 29 | 30 | ### save design 31 | save_block 32 | save_lib 33 | 34 | ### exit icc2 35 | print_message_info 36 | #quit! 37 | 38 | ############################################################## 39 | # END 40 | ############################################################## 41 | -------------------------------------------------------------------------------- /Verilog/booth_enc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module booth_enc( 3 | muli, 4 | code 5 | ); 6 | 7 | input [7:0] muli; 8 | output [11:0] code; 9 | wire [11:0] mul; 10 | 11 | assign mul[2:0] = {muli[1:0],1'b0};// == 3'b111) ? 3'd0 : {muli[1:0],1'b0}; 12 | assign mul[5:3] = muli[3:1];// == 3'b111) ? 3'd0 : muli[3:1]; 13 | assign mul[8:6] = muli[5:3];// == 3'b111) ? 3'd0 : muli[5:3]; 14 | assign mul[11:9] = muli[7:5];// == 3'b111) ? 3'd0 : muli[7:5]; 15 | 16 | assign code[2] = mul[2]; 17 | assign code[1] = (mul[2:0] == 3'b100) || (mul[2:0] == 3'b011); 18 | assign code[0] = (mul[2:0] == 3'b001) || (mul[2:0] == 3'b010) || (mul[2:0] == 3'b101) || (mul[2:0] == 3'b110); 19 | 20 | assign code[5] = mul[5]; 21 | assign code[4] = (mul[5:3] == 3'b100) || (mul[5:3] == 3'b011); 22 | assign code[3] = (mul[5:3] == 3'b001) || (mul[5:3] == 3'b010) || (mul[5:3] == 3'b101) || (mul[5:3] == 3'b110); 23 | 24 | assign code[8] = mul[8]; 25 | assign code[7] = (mul[8:6] == 3'b100) || (mul[8:6] == 3'b011); 26 | assign code[6] = (mul[8:6] == 3'b001) || (mul[8:6] == 3'b010) || (mul[8:6] == 3'b101) || (mul[8:6] == 3'b110); 27 | 28 | assign code[11] = mul[11]; 29 | assign code[10] = (mul[11:9] == 3'b100) || (mul[11:9] == 3'b011); 30 | assign code[9] = (mul[11:9] == 3'b001) || (mul[11:9] == 3'b010) || (mul[11:9] == 3'b101) || (mul[11:9] == 3'b110); 31 | 32 | endmodule -------------------------------------------------------------------------------- /PT/NPU_ADD_TREE_PTPX.tcl: -------------------------------------------------------------------------------- 1 | 2 | set prj_path ../ 3 | set work_path $prj_path/synthesis 4 | set rtl_path $prj_path/rtl 5 | set library_path "$prj_path/SM28lib/synthesis/lib" 6 | 7 | set search_path "$search_path $work_path $rtl_path $library_path" 8 | set target_library {scc28nhkcp_hdc30p140_rvt_tt_v1p0_25c_basic.db} 9 | set synthetic_library "dw_foundation.sldb" 10 | set link_library {* scc28nhkcp_hdc30p140_rvt_tt_v1p0_25c_basic.db} 11 | 12 | set hdlin_enable_presto "true" 13 | set hdlin_unsigned_integers "false" 14 | set_host_options -max_cores 16 15 | 16 | 17 | set power_enable_analysis TRUE 18 | #Two mode : averaged , time_based 19 | set power_analysis_mode time_based 20 | 21 | read_verilog ../SYN/NPU_ADD_TREE.v 22 | current_design NPU_ADD_TREE_TOP 23 | #INPUT_PROCESSING 24 | link 25 | #create_clock [get_ports clk] -period 6 -waveform[6 12] 26 | #create_clock -name clk -period 1 27 | read_sdc ../SYN/NPU_ADD_TREE.sdc 28 | #set_disable_timing [get_lib_pins ssc_core_typ/*/G] 29 | # 30 | # 31 | 32 | check_timing 33 | update_timing 34 | redirect NPU_ADD_TREE.pttiming.log { report_timing -max_paths 100000 -sort_by slack -slack_lesser_than 2 -nosplit} 35 | 36 | read_vcd "../VCS/random.vcd" -strip_path "NPU_CUBE_ADD_TEST/NPU_CUBE_ADD_TOP_sign" 37 | redirect NPU_ADD_TREE.switchpower.log { report_switching_activity -list_not_annotated } 38 | set_power_analysis_options -waveform_format fsdb -waveform_output NPU_ADD_TREE.ptfsdb.fsdb 39 | 40 | check_power 41 | update_power 42 | redirect NPU_ADD_TREE.ptpower.log { report_power -nosplit -hierarchy } 43 | quit 44 | -------------------------------------------------------------------------------- /LibChar/setup/run180nm.tcl: -------------------------------------------------------------------------------- 1 | source -echo -verbose $env(KLIB_ROOT)/setup/klib_setup.tcl 2 | 3 | set cells $klib_cells 4 | set charpoint $klib_tag 5 | set cfgfile $cfg_file 6 | create $charpoint 7 | set_log_file $charpoint/sis.log 8 | 9 | exec cp setup/${cfgfile} ${charpoint}/config/configure.tcl 10 | set_location $charpoint 11 | 12 | #FR with just netlists 13 | #set_parameter configure_from_structure true 14 | #set_parameter state_partitions value 15 | #set_config_opt simulator_bisection 0 16 | 17 | import -extension .spi -netlist_dir netlists/ $cells 18 | #exec cp A2D4B_SRAM.inst ${charpoint}/control/A2D4B_SRAM.inst 19 | 20 | foreach c $cells { 21 | puts "Copying $c.inst → $charpoint/control/" 22 | exec cp inst/${c}.inst ${charpoint}/control/${c}.inst 23 | } 24 | #exec cp ${cells}.inst ${charpoint}/control/${cells}.inst 25 | 26 | #import -fast -liberty import.lib -extension .cdl -netlist_dir netlists/ $cells 27 | #find_internal_nodes_for_constraint 28 | #set_config_opt -cell A2D4B_SRAM -from CLK -to DO state_partitions none 29 | #set_config_opt -cell A2D4B_SRAM -from CLK -to WEN state_partitions none 30 | #set_config_opt -cell A2D4B_SRAM -from CLK -to DIN state_partitions none 31 | 32 | set_config_opt separate_cell_initialization 0 33 | #separate_cell_initialization 34 | 35 | configure -timing -power -ccs $cells 36 | characterize $cells 37 | 38 | model -verilog -output my_model $cells 39 | model -timing -power -output nldm $cells 40 | model -timing -power -ccs -output ccs $cells 41 | 42 | log_info "IAMDONE" 43 | 44 | 45 | # wv ..tr0 check_wave 46 | # 47 | -------------------------------------------------------------------------------- /APR/Makefile: -------------------------------------------------------------------------------- 1 | # Este makefile correrá icc2_shell y limpiará los archivos generados 2 | 3 | icc2_shell = singularity exec /home/work/default/container/icc2.sif icc2_shell 4 | 5 | .PHONY: init 6 | init: 7 | @echo "Ejecutando icc2_shell con init" 8 | @${icc2_shell} -gui -f ./pnr/scripts/01_icc2_import_design.tcl 9 | 10 | .PHONY: floorplan 11 | floorplan: 12 | @echo "Ejecutando icc2_shell con floorplan" 13 | @${icc2_shell} -gui -f ./pnr/scripts/02_create_floorplan.tcl 14 | 15 | .PHONY: powerplan 16 | powerplan: 17 | @echo "Ejecutando icc2_shell con powerplan" 18 | @${icc2_shell} -gui -f ./pnr/scripts/03_power_routing.tcl 19 | 20 | .PHONY: place 21 | place: 22 | @echo "Ejecutando icc2_shell con placement" 23 | @${icc2_shell} -gui -f ./pnr/scripts/04_placeopt.tcl 24 | 25 | .PHONY: cts 26 | cts: 27 | @echo "Ejecutando icc2_shell con cts" 28 | @${icc2_shell} -gui -f ./pnr/scripts/05_clock.tcl 29 | 30 | .PHONY: ctsopt 31 | ctsopt: 32 | @echo "Ejecutando icc2_shell con ctsopt" 33 | @${icc2_shell} -gui -f ./pnr/scripts/06_clockopt.tcl 34 | 35 | .PHONY: route 36 | route: 37 | @echo "Ejecutando icc2_shell con route" 38 | @${icc2_shell} -gui -f ./pnr/scripts/07_route.tcl 39 | 40 | .PHONY: routeopt 41 | routeopt: 42 | @echo "Ejecutando icc2_shell con routeopt" 43 | @${icc2_shell} -gui -f ./pnr/scripts/08_routeopt.tcl 44 | 45 | .PHONY: chipfinish 46 | chipfinish: 47 | @echo "Ejecutando icc2_shell con chip_finish" 48 | @${icc2_shell} -gui -f ./pnr/scripts/09_chipfinish.tcl 49 | 50 | .PHONY: clean 51 | clean: 52 | @echo "Limpiando archivos .log, .txt .svf work_dir" 53 | rm -f -r *.log *.txt work_dir *.svf 54 | -------------------------------------------------------------------------------- /APR/pnr/scripts/starrc_in_design.cmd: -------------------------------------------------------------------------------- 1 | 2 | * starrc input type : milkyway, ndm, lef/def 3 | 4 | ***************************************** 5 | * LEF/DEF flow 6 | ***************************************** 7 | * LEF_FILE: (no need in starrc-in-design flow) 8 | * TOP_DEF_FILE: data/ORCA_TOP_10_chipfinish.def.gz (no need in starrc-in-design flow) 9 | * BLOCK: ORCA_TOP (no need in starrc-in-design flow) 10 | * MAPPING_FILE: (no need in starrc-in-design flow) 11 | NETLIST_FORMAT: SPEF 12 | NETLIST_FILE: ./data/ORCA_TOP.spef 13 | STAR_DIRECTORY: ./run_starrc_cmax_125c 14 | EXTRACTION: RC 15 | COUPLE_TO_GROUND: NO 16 | 17 | * SIMULTANEOUS_MULTI_CORNER: YES 18 | * CORNERS_FILE: scripts/live/corners.txt 19 | * SELECTED_CORNERS: cmax_125c 20 | 21 | *** added for metal fill 22 | * METAL_FILL_POLYGON_HANDLING:FLOATING 23 | * METAL_FILL_GDS_FILE:(no need in starrc-in-design flow if no metal fill is used) 24 | * METAL_FILL_BLOCK_NAME:ORCA_TOP 25 | * GDS_LAYER_MAP_FILE:(no need in starrc-in-design flow if no metal fill is used) 26 | 27 | * extra options 28 | NETLIST_COMPRESS_COMMAND: gzip -9f 29 | LEF_USE_OBS : YES 30 | COUPLE_TO_GROUND : NO 31 | COUPLING_ABS_THRESHOLD : 1e-16 32 | COUPLING_REL_THRESHOLD : 0.03 33 | GROUND_CROSS_COUPLING : NO 34 | REMOVE_FLOATING_NETS : YES 35 | REMOVE_DANGLING_NETS : YES 36 | MERGE_VIAS_IN_ARRAY : NO 37 | EXTRACT_VIA_CAPS : YES 38 | NETLIST_NODE_SECTION : YES 39 | MAGNIFICATION_FACTOR : 1.0 40 | TRANSLATE_DEF_BLOCKAGE :YES 41 | NETLIST_CONNECT_OPENS :* 42 | REDUCTION_MAX_DELAY_ERROR: 0.1PS 43 | ENABLE_IPV6:NO 44 | 45 | ***************************************** 46 | * END 47 | ***************************************** 48 | 49 | -------------------------------------------------------------------------------- /PT/NPU_PTPX_PR.tcl: -------------------------------------------------------------------------------- 1 | 2 | set prj_path ../ 3 | set work_path $prj_path/synthesis 4 | set rtl_path $prj_path/rtl 5 | set library_path "$prj_path/SM28lib/synthesis/lib" 6 | 7 | set search_path "$search_path $work_path $rtl_path $library_path" 8 | set target_library {scc28nhkcp_hdc30p140_rvt_tt_v1p0_25c_basic.db} 9 | set synthetic_library "dw_foundation.sldb" 10 | set link_library {* scc28nhkcp_hdc30p140_rvt_tt_v1p0_25c_basic.db} 11 | 12 | set hdlin_enable_presto "true" 13 | set hdlin_unsigned_integers "false" 14 | set_host_options -max_cores 16 15 | 16 | 17 | set power_enable_analysis TRUE 18 | #Two mode : averaged , time_based 19 | set power_analysis_mode time_based 20 | 21 | read_verilog ../PR/data/NPU_ADD_TREE.v 22 | current_design NPU_ADD_TREE_TOP 23 | #INPUT_PROCESSING 24 | link 25 | #create_clock [get_ports clk] -period 6 -waveform[6 12] 26 | #create_clock -name clk -period 1 27 | read_sdc ../SYN/NPU_ADD_TREE.sdc 28 | #set_disable_timing [get_lib_pins ssc_core_typ/*/G] 29 | read_parasitics -format SPEF ../PR/data/NPU_ADD_TREE_TOP.spef 30 | 31 | 32 | check_timing 33 | update_timing 34 | redirect NPU_PR.pttiming.setup.log { report_timing -max_paths 100000 -delay max -sort_by slack -slack_lesser_than 2 -nosplit} 35 | redirect NPU_PR.pttiming.hold.log { report_timing -max_paths 100000 -delay min -sort_by slack -slack_lesser_than 2 -nosplit} 36 | 37 | read_vcd "../VCS/random.vcd" -strip_path "NPU_CUBE_ADD_TEST/NPU_CUBE_ADD_TOP_sign" 38 | redirect NPU_PR.switchpower.log { report_switching_activity -list_not_annotated } 39 | set_power_analysis_options -waveform_interval 0.01 -waveform_format fsdb -waveform_output NPU_PR.ptfsdb.fsdb 40 | 41 | check_power 42 | update_power 43 | redirect NPU_PR.ptpower.log { report_power -nosplit -hierarchy -verb -level 1 -sort_by total_power } 44 | quit 45 | -------------------------------------------------------------------------------- /Innovus/parse_io_to_tcl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # -*- coding: utf-8 -*- 3 | """ 4 | parse_io_to_tcl.py 5 | 6 | 从 Innovus .io 文件中提取 top/left/right/bottom 的 PAD 名称， 7 | 同时生成两个 Tcl 文件： 8 | 1) gen_pad.tcl → myppad60 命令 9 | 2) delete_pad.tcl → deleteInst 命令 10 | """ 11 | 12 | import re 13 | 14 | input_file = "sisyphus_top.saveloc.io" 15 | gen_file = "gen_pad.tcl" 16 | del_file = "delete_pad.tcl" 17 | 18 | # 只处理这四个方向 19 | valid_dirs = ["top", "bottom", "left", "right"] 20 | 21 | with open(input_file, "r", encoding="utf-8") as f: 22 | data = f.read() 23 | 24 | gen_results = [] 25 | del_results = [] 26 | 27 | # 正则匹配四个方向的块 28 | pattern = re.compile(r"\((top|bottom|left|right)\s+(.*?)\n\s*\)", re.S) 29 | sections = pattern.findall(data) 30 | 31 | for direction, content in sections: 32 | names = re.findall(r'name="([^"]+)"', content) 33 | for n in names: 34 | # 跳过电源、地、corner，如果需要保留请注释掉下面两行 35 | # if re.search(r"VDD|VSS|CORNER", n, re.IGNORECASE): 36 | # continue 37 | 38 | # 无论是否带 _pad，都再加一次 _pad 39 | pad_name = f"{n}_pad" 40 | 41 | gen_results.append(f"myppad60 {n} {pad_name} {direction} out") 42 | del_results.append(f"deleteInst {pad_name}") 43 | 44 | # 输出 gen_pad.tcl 45 | with open(gen_file, "w", encoding="utf-8") as f: 46 | f.write("# Auto-generated Tcl script from .io file\n") 47 | f.write("# Generated by parse_io_to_tcl_allinone.py\n\n") 48 | for r in gen_results: 49 | f.write(r + "\n") 50 | 51 | # 输出 delete_pad.tcl 52 | with open(del_file, "w", encoding="utf-8") as f: 53 | f.write("# Auto-generated delete Tcl script from .io file\n") 54 | f.write("# Generated by parse_io_to_tcl_allinone.py\n\n") 55 | for r in del_results: 56 | f.write(r + "\n") 57 | 58 | print(f"Generated {len(gen_results)} lines:") 59 | print(f" → {gen_file}") 60 | print(f" → {del_file}") 61 | -------------------------------------------------------------------------------- /Verilog/NPU_GEN_PROD_EXTEND.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module NPU_GEN_PROD_EXTEND( 3 | //NPU_PROD0_Sign, 4 | //NPU_PROD1_Sign, 5 | //NPU_PROD2_Sign, 6 | //NPU_PROD3_Sign, 7 | line0, 8 | line1, 9 | line2, 10 | line3, 11 | is_signed, 12 | lline0, 13 | lline1, 14 | lline2, 15 | lline3 16 | ); 17 | 18 | parameter DWA = 8; 19 | parameter DWB = 8; 20 | //3bit: [2]=~+1 [1][0]=* 21 | parameter DWB_CODE = 12; 22 | parameter DWS = 21; 23 | parameter NPU_CUBE_MAC_NUM = 8; 24 | parameter SIGNED_A = 0; 25 | parameter DWM = DWA + DWB; 26 | parameter DWPRODUCT = 19; 27 | parameter DWOUPUT = 19; 28 | parameter DWPPLEN = 10; 29 | 30 | input [DWPPLEN-1:0] line0; 31 | input [DWPPLEN-1:0] line1; 32 | input [DWPPLEN-1:0] line2; 33 | input [DWPPLEN-1:0] line3; 34 | input is_signed; 35 | output [(DWB+4)-1:0] lline0;//12 36 | output [(DWB+2)-1:0] lline1;//12 37 | output [(DWB+2)-1:0] lline2;//12 38 | output [(DWB+2)-1:0] lline3;//12 39 | 40 | //input NPU_PROD0_Sign; 41 | //input NPU_PROD1_Sign; 42 | //input NPU_PROD2_Sign; 43 | //input NPU_PROD3_Sign; 44 | 45 | wire e0s; 46 | wire e1s; 47 | wire e2s; 48 | wire e3s; 49 | 50 | assign e0s = ~line0[DWPPLEN-1]; 51 | assign e1s = ~line1[DWPPLEN-1]; 52 | assign e2s = ~line2[DWPPLEN-1]; 53 | assign e3s = ~line3[DWPPLEN-1]; 54 | 55 | assign e0s_inv = line0[DWPPLEN-1]; 56 | 57 | assign s_e0s = e0s;// & is_signed; 58 | assign s_e1s = e1s;// & is_signed; 59 | assign s_e2s = e2s;// & is_signed; 60 | assign s_e3s = e3s;// & is_signed; 61 | 62 | assign s_e0s_inv = e0s_inv;// & is_signed; 63 | 64 | assign lline0 = {s_e0s,s_e0s_inv,s_e0s_inv,line0[DWPPLEN-2:0]}; 65 | assign lline1 = {s_e1s,line1[DWPPLEN-2:0]};//,1'b0,NPU_PROD0_Sign}; 66 | assign lline2 = {s_e2s,line2[DWPPLEN-2:0]};//,1'b0,NPU_PROD1_Sign}; 67 | assign lline3 = {s_e3s,line3[DWPPLEN-2:0]};//,1'b0,NPU_PROD2_Sign}; 68 | 69 | endmodule -------------------------------------------------------------------------------- /SYN/NPU_ADD_TREE.tcl: -------------------------------------------------------------------------------- 1 | # 2 | 3 | set verilogout_no_tri "true" 4 | 5 | set prj_path ../ 6 | set work_path $prj_path/SYN 7 | set rtl_path $prj_path/Verilog 8 | set library_path "$prj_path/SM28lib/synthesis/lib" 9 | 10 | 11 | set search_path "$search_path $work_path $rtl_path $library_path" 12 | set target_library {scc28nhkcp_hdc30p140_rvt_tt_v1p0_25c_basic.db} 13 | set synthetic_library "dw_foundation.sldb" 14 | set link_library {* scc28nhkcp_hdc30p140_rvt_tt_v1p0_25c_basic.db} 15 | 16 | set hdlin_enable_presto "true" 17 | set hdlin_unsigned_integers "false" 18 | 19 | set_host_options -max_cores 16 20 | 21 | define_design_lib syn_temp -path ./syn_temp 22 | 23 | analyze -work syn_temp -format verilog "NPU_CUBE_ADD_TREE_CODE.v NPU_CUBE_ADD_TREE_WALLACE_PRODUCT_CODE.v NPU_CUBE_ADD_PRODUCT_CODE.v NPU_GEN_PROD.v NPU_GEN_PROD_EXTEND.v NPU_CUBE_ADD_TREE_WALLACE_EXTEND_SIGN.v NPU_CUBE_TREE_INPUT.v booth_enc.v NPU_ADD_TREE_TOP.v" 24 | elaborate -work syn_temp NPU_ADD_TREE_TOP 25 | 26 | current_design NPU_ADD_TREE_TOP 27 | link 28 | check_design 29 | 30 | 31 | create_clock -name clk -period 2 [get_ports clk] 32 | set_input_delay 0.27272 -clock clk [all_inputs] 33 | set_input_delay 0 [get_ports clk] 34 | 35 | set_output_delay 0 -clock clk [all_outputs] 36 | set_load [expr 0.00771681 * 3] [all_outputs] 37 | 38 | 39 | set_max_area 0 40 | 41 | #compile -ungroup_all 42 | compile_ultra -no_autoungroup 43 | # ungroup -all -flatten 44 | 45 | #define_name_rules verilog -allowed "A-Z0-9_" 46 | change_names -rules verilog -hierarchy 47 | 48 | write -f verilog -hier -o NPU_ADD_TREE.v 49 | write -f ddc -hier -o NPU_ADD_TREE.ddc 50 | write_sdf -version 1.2 NPU_ADD_TREE.sdf 51 | write_sdc NPU_ADD_TREE.sdc 52 | 53 | redirect NPU_ADD_TREE.timing.log { report_timing -max_paths 100000 -sort_by slack -slack_lesser_than 2 -nosplit} 54 | redirect NPU_ADD_TREE.qor.log { report_qor} 55 | redirect NPU_ADD_TREE.area.log { report_area -nosplit -hierarchy } 56 | redirect NPU_ADD_TREE.power.log { report_power -nosplit -hierarchy} 57 | #quit 58 | -------------------------------------------------------------------------------- /Verilog/NPU_CUBE_ADD_PRODUCT_CODE.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/18 03:18:09 7 | // Design Name: 8 | // Module Name: NPU_CUBE_ADD_PRODUCT_CODE 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NPU_CUBE_ADD_PRODUCT_CODE 22 | # (parameter NPU_CUBE_MAC_PP = 11)//*2+1 23 | ( 24 | linedata, 25 | addresult 26 | ); 27 | //3bit: [2]=~+1 [1][0]=* 28 | parameter DWB_CODE = 12; 29 | parameter DWB_PER_CODE = 3; 30 | parameter DWA = 8; 31 | parameter DWB = 8; 32 | parameter DWS = 21; 33 | parameter NPU_CUBE_MAC_NUM = 8; 34 | parameter DWPRODUCT = 19; 35 | input [DWA*NPU_CUBE_MAC_PP-1:0] linedata; 36 | output [NPU_CUBE_MAC_PP+3-1:0] addresult; 37 | 38 | wire [NPU_CUBE_MAC_PP-1:0] pp0; 39 | wire [NPU_CUBE_MAC_PP-1:0] pp1; 40 | wire [NPU_CUBE_MAC_PP-1:0] pp2; 41 | wire [NPU_CUBE_MAC_PP-1:0] pp3; 42 | wire [NPU_CUBE_MAC_PP-1:0] pp4; 43 | wire [NPU_CUBE_MAC_PP-1:0] pp5; 44 | wire [NPU_CUBE_MAC_PP-1:0] pp6; 45 | wire [NPU_CUBE_MAC_PP-1:0] pp7; 46 | 47 | assign pp0 = linedata[NPU_CUBE_MAC_PP*1 - 1 : NPU_CUBE_MAC_PP * 0]; 48 | assign pp1 = linedata[NPU_CUBE_MAC_PP*2 - 1 : NPU_CUBE_MAC_PP * 1]; 49 | assign pp2 = linedata[NPU_CUBE_MAC_PP*3 - 1 : NPU_CUBE_MAC_PP * 2]; 50 | assign pp3 = linedata[NPU_CUBE_MAC_PP*4 - 1 : NPU_CUBE_MAC_PP * 3]; 51 | assign pp4 = linedata[NPU_CUBE_MAC_PP*5 - 1 : NPU_CUBE_MAC_PP * 4]; 52 | assign pp5 = linedata[NPU_CUBE_MAC_PP*6 - 1 : NPU_CUBE_MAC_PP * 5]; 53 | assign pp6 = linedata[NPU_CUBE_MAC_PP*7 - 1 : NPU_CUBE_MAC_PP * 6]; 54 | assign pp7 = linedata[NPU_CUBE_MAC_PP*8 - 1 : NPU_CUBE_MAC_PP * 7]; 55 | 56 | assign addresult = pp0 + pp1 + pp2 + pp3 + pp4 + pp5 + pp6 + pp7; 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /LibChar/Makefile: -------------------------------------------------------------------------------- 1 | export 2 | PRJ := Klib996 3 | PRJ_VER := V1_1 4 | KLIB_ROOT := $(PWD) 5 | #The prefix dir of RTL code 6 | XL_FABLIB_BASE := ../../T180lib 7 | #TOT := $(shell depth.pl) no such file or dir 8 | TOT := ../ 9 | PVT := ss 10 | #Usually, we only use ss corner for synthesis. 11 | ifeq ($(PVT),tt) 12 | CORNER := tt0p9v25c 13 | else ifeq ($(PVT),ss) 14 | CORNER := ssg0p81v0c 15 | endif 16 | 17 | CORNER_FF := ffg0p99v0c 18 | CORNER_SS := ssg0p81v0c 19 | 20 | KLIB_TAG := $(PRJ)_tsmc180_$(PRJ_VER) 21 | LIB_ROOT := $(XL_FABLIB_BASE) 22 | DATE_TAG := $(shell date +%h%d_%H%M) 23 | PR_LOG_FILE := apr_$(DATE_TAG).log 24 | DC_OPEN_LOG := ./$(SYN_TAG)/dc_open_$(DATE_TAG).log 25 | #currently, we do not use topo mode. So SYN_mode should be set to 1. 26 | #SYN_MODE := 1 27 | #TOP := chaos996_soc 28 | #SDC_FILE := ./constraints/chaos996.sdc 29 | #DFT_SDC_FILE := ./constraints/chip_dft.sdc 30 | START_GUI := 0 31 | LINK_ONLY := 0 32 | DFT_EN := 0 33 | USE_ALL_LIB := 0 34 | SYN_TECH := tsmc180 35 | DO_EXP := 0 36 | #FREQ_SCALE := 1.0 37 | #RTL_FILELIST := ./rtl.vf 38 | #ORIGIN_FILELIST := ./origin_rtl.vf 39 | OPER_COND := tt_v0p90_+25c 40 | WORK_MODE := func 41 | CFG_FILE := configure_180nm.tcl 42 | KLIB_CELLS := A2D4B_SRAM 43 | 44 | .PHONY: klib clean 45 | 46 | 47 | klibeg: 48 | primelib ./setup/run_klib.tcl 49 | 50 | klib180: 51 | primelib ./setup/run180nm.tcl 52 | #source ./setup/run180nm.tcl 53 | 54 | clean: 55 | @rm -rf $(KLIB_TAG) WORK* 56 | -------------------------------------------------------------------------------- /Verilog/NPU_CUBE_ADD_TREE_WALLACE_PRODUCT_CODE.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/18 00:45:36 7 | // Design Name: 8 | // Module Name: NPU_CUBE_ADD_TREE_WALLACE_PRODUCT_CODE 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module NPU_CUBE_ADD_TREE_WALLACE_PRODUCT_CODE 22 | ( 23 | add_tree_data, 24 | add_tree_para, 25 | is_signed, 26 | line0, 27 | line1, 28 | line2, 29 | line3, 30 | ); 31 | 32 | 33 | //3bit: [2]=~+1 [1][0]=* 34 | parameter DWB_CODE = 12; 35 | parameter DWB_PER_CODE = 3; 36 | parameter DWA = 8; 37 | parameter DWB = 8; 38 | parameter DWS = 21; 39 | parameter NPU_CUBE_MAC_NUM = 8; 40 | parameter NPU_CUBE_MAC_PP = 10;//8+1 41 | parameter SIGNED_A = 0; 42 | parameter DWM = DWA + DWB; 43 | input [DWA*NPU_CUBE_MAC_NUM-1:0] add_tree_data; 44 | input [DWB_CODE*NPU_CUBE_MAC_NUM-1:0] add_tree_para; 45 | input is_signed; 46 | output [NPU_CUBE_MAC_PP*NPU_CUBE_MAC_NUM-1:0] line0; 47 | output [NPU_CUBE_MAC_PP*NPU_CUBE_MAC_NUM-1:0] line1; 48 | output [NPU_CUBE_MAC_PP*NPU_CUBE_MAC_NUM-1:0] line2; 49 | output [NPU_CUBE_MAC_PP*NPU_CUBE_MAC_NUM-1:0] line3; 50 | 51 | 52 | genvar i,j; 53 | generate 54 | for(i=0;i ${report_dir}/check_legality.rpt 65 | check_mv_design > ${report_dir}/check_mv_design.rpt 66 | report_qor -summary > ${report_dir}/report_qor.summary.rpt 67 | report_timing -nosplit -report_by scenario -transition_time -capacitance -physical -nets -input_pins -nworst 1 -max_paths 200 -attribute -derate -voltage -delay_type max > ${report_dir}/report_timing.rpt 68 | if { [get_utilization_configurations util_config -quiet] != "" } { 69 | create_utilization_configuration util_config -exclude {hard_macros macro_keepouts soft_macros io_cells hard_blockages} 70 | } 71 | report_utilization -config util_config > ${report_dir}/report_utilization.rpt 72 | report_utilization -config util_config -of_objects [get_voltage_areas PD_RISC_CORE] > ${report_dir}/report_utilization.PD_RISC_CORE.rpt 73 | redirect -file ${report_dir}/report_clock_qor.structure.rpt { report_clock_qor -type structure } 74 | redirect -file ${report_dir}/report_clock_qor.all.rpt { report_clock_qor -all } 75 | foreach_in_collection clk [get_clocks -filter "is_virtual == false" -quiet] { 76 | set clk_name [get_object_name $clk] 77 | redirect ${report_dir}/report_clock_qor.${clk_name}.latency.rpt { report_clock_qor -clock $clk_name -type latency -show_verbose_paths -largest 1 -smallest 1 } 78 | redirect ${report_dir}/report_clock_qor.${clk_name}.local_skew.rpt { report_clock_qor -clock $clk_name -type local_skew -largest 1000 } 79 | redirect ${report_dir}/report_clock_qor.${clk_name}.summary.rpt { report_clock_qor -clock $clk_name -type summary } 80 | } 81 | 82 | ### save design 83 | save_block -force 84 | save_lib 85 | 86 | ### exit icc2 87 | print_message_info 88 | #quit! 89 | 90 | ############################################################## 91 | # END 92 | ############################################################## 93 | -------------------------------------------------------------------------------- /APR/pnr/scripts/04_placeopt.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: Run place_opt in ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | source ./pnr/scripts/00_common_initial_settings.tcl 6 | 7 | ### variables 8 | set current_step "04_icc2_placeopt" 9 | set before_step "03_icc2_pgrouting" 10 | 11 | ### open database 12 | file mkdir $nlib_dir 13 | file delete -force $nlib_dir/${design}_${current_step}.nlib 14 | copy_lib -from_lib ${nlib_dir}/${design}_${before_step}.nlib -to_lib ${nlib_dir}/${design}_${current_step}.nlib -force 15 | current_lib ${design}_${current_step}.nlib 16 | open_block ${design} 17 | 18 | ### initialize tool 19 | source ./pnr/scripts/initialization_settings.tcl 20 | 21 | ### create scenarios 22 | set scenarios_list $placeopt_scenarios 23 | source ./pnr/scripts/scenarios_setup.tcl 24 | 25 | ### set routing layers 26 | set_ignored_layers -min_routing_layer M1 -max_routing_layer M8 27 | 28 | ### enable tie cell insertion during optimization 29 | set_lib_cell_purpose -include optimization [get_lib_cells */*TIE*] 30 | set_dont_touch [get_lib_cells */*TIE*] false 31 | set_app_options -name opt.tie_cell.max_fanout -value 8 32 | 33 | ### manually control density 34 | #set_app_options -name place.coarse.congestion_driven_max_util -value 0.70 35 | #set_app_options -name place.coarse.congestion_layer_aware -value true 36 | #set_app_options -name place.coarse.max_density -value 0.50 37 | #set_app_options -name place.coarse.pin_density_aware -value true 38 | 39 | ### auto density control 40 | set_app_options -name opt.common.enable_rde -value true 41 | set_app_options -name place.coarse.enhanced_auto_density_control -value true 42 | 43 | ### read and optimize scan def 44 | set_app_options -name place.coarse.continue_on_missing_scandef -value false 45 | remove_scan_def 46 | read_def $scandef_file 47 | set_app_options -name opt.dft.optimize_scan_chain -value true 48 | 49 | ### optimization options 50 | set_app_options -name place.legalize.enable_advanced_legalizer -value true 51 | set_app_options -name place_opt.congestion.effort -value high 52 | set_app_options -name route.global.effort_level -value high 53 | set_app_options -name opt.area.effort -value ultra 54 | set_app_options -name opt.common.buffer_area_effort -value ultra 55 | set_app_options -name place_opt.flow.clock_aware_placement -value true 56 | set_app_options -name refine_opt.flow.clock_aware_placement -value true 57 | set_app_options -name place_opt.flow.enable_power -value true 58 | set_app_options -name opt.power.leakage_type -value conventional 59 | set_app_options -name place.coarse.auto_timing_control -value true 60 | set_app_options -name place_opt.final_place.effort -value high 61 | set_app_options -name route.global.timing_driven_effort_level -value high 62 | set_app_options -name opt.timing.effort -value high 63 | 64 | ### set cell prefix added by place_opt command 65 | set_app_options -name opt.common.user_instance_name_prefix -value POPT_ 66 | 67 | ### disable default enabled advanced feature 68 | set_app_options -name place_opt.flow.estimate_clock_gate_latency -value false 69 | set_app_options -name place_opt.flow.enable_ccd -value false 70 | 71 | ### run placeopt 72 | place_opt 73 | 74 | ### connect pg 75 | connect_pg_net -automatic 76 | 77 | ### get reports 78 | set report_dir "reports/$current_step" 79 | file mkdir $report_dir 80 | check_legality > ${report_dir}/check_legality.rpt 81 | check_mv_design > ${report_dir}/check_mv_design.rpt 82 | report_qor -summary > ${report_dir}/report_qor.summary.rpt 83 | report_timing -nosplit -report_by scenario -transition_time -capacitance -physical -nets -input_pins -nworst 1 -max_paths 200 -attribute -derate -voltage -delay_type max > ${report_dir}/report_timing.rpt 84 | create_utilization_configuration util_config -exclude {hard_macros macro_keepouts soft_macros io_cells hard_blockages} 85 | report_utilization -config util_config > ${report_dir}/report_utilization.rpt 86 | report_utilization -config util_config -of_objects [get_voltage_areas PD_RISC_CORE] > ${report_dir}/report_utilization.PD_RISC_CORE.rpt 87 | 88 | ### save design 89 | save_block -force 90 | save_lib 91 | 92 | ### exit icc2 93 | print_message_info 94 | #quit! 95 | 96 | ############################################################## 97 | # END 98 | ############################################################## 99 | -------------------------------------------------------------------------------- /APR/pnr/scripts/02_create_floorplan.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: Create floorplan in ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | source ./pnr/scripts/00_common_initial_settings.tcl 6 | 7 | ### variables 8 | set current_step "02_icc2_floorplan" 9 | set before_step "01_icc2_import" 10 | 11 | ### open database 12 | file mkdir $nlib_dir 13 | file delete -force $nlib_dir/${design}_${current_step}.nlib 14 | copy_lib -from_lib ${nlib_dir}/${design}_${before_step}.nlib -to_lib ${nlib_dir}/${design}_${current_step}.nlib -force 15 | current_lib ${design}_${current_step}.nlib 16 | 17 | ### get blocks -all 18 | open_block ${design} 19 | 20 | ### initialize tool 21 | source ./pnr/scripts/initialization_settings.tcl 22 | 23 | ### create scenarios 24 | set scenarios_list $default_scenarios 25 | source ./pnr/scripts/scenarios_setup.tcl 26 | 27 | ### create floorplan 28 | ## non-rectangle shapes 29 | initialize_floorplan -boundary {{0 0} {999.856 999.856}} -core_offset {0 1.672} 30 | 31 | ## non-rectangle shapes 32 | # _a_ ___________ _b_ _f_ 33 | # __a___ | | | | | | | | 34 | # | | | b | a a c e | 35 | # | | | | |_f_ _b_| | |_d_| | 36 | # b | | |_c_ | | | | 37 | # | | | | e c |___________| 38 | # |____| | d | | 39 | # |_______| |_d_| 40 | 41 | ### place ports 42 | if { [get_terminals * -quiet] != "" } { remove_terminals * } 43 | remove_individual_pin_constraints 44 | set input_ports [get_ports -filter direction==in] 45 | set_individual_pin_constraints -ports $input_ports -allowed_layers [get_layers {M5 M7}] -side 1 -offset {400 500} 46 | 47 | set output_ports [get_ports -filter direction==out] 48 | set_individual_pin_constraints -ports $output_ports -allowed_layers [get_layers {M5 M7}] -side 3 -offset {500 600} 49 | place_pins -self -ports [get_ports *] 50 | 51 | ### create voltage areas 52 | create_voltage_area -power_domains PD_RISC_CORE -guard_band {{10.032 10}} -region {{0.0000 642.0480} {489.1360 999.8560}} 53 | 54 | ### place hard macros 55 | #source ./data/ORCA_TOP.place_macros.tcl 56 | read_def ./data/ORCA_TOP.place_macros.def.gz 57 | 58 | ## what happens if macros are not fixed 59 | set_att [get_flat_cells -filter "design_type==macro"] physical_status fixed 60 | #set_app_options -name place.coarse.fix_hard_macros -value false 61 | #set_app_options -name plan.place.auto_create_blockages -value auto 62 | #create_placement -floorplan -effort low 63 | 64 | ### create keepout margin for macros : how to get macros 65 | create_keepout_margin -outer {5 5 5 5} [get_flat_cells -filter "design_type==macro"] 66 | 67 | ### create boundary cells : check and set up corner cells 68 | remove_boundary_cell_rules -all 69 | 70 | set_boundary_cell_rules -left_boundary_cell $endcap_left -right_boundary_cell $endcap_right -top_boundary_cell $endcap_top -bottom_boundary_cell $endcap_bottom 71 | #set_boundary_cell_rules -left_boundary_cell $endcap_left -right_boundary_cell $endcap_right -top_boundary_cell $endcap_top -bottom_boundary_cell $endcap_bottom -bottom_right_inside_corner_cells $endcap_left -bottom_right_outside_corner_cell $endcap_left -top_left_inside_corner_cells $endcap_left -bottom_left_outside_corner_cell $endcap_left -top_left_outside_corner_cell $endcap_left -top_right_outside_corner_cell $endcap_left -bottom_left_inside_corner_cells $endcap_left -top_left_inside_corner_cells $endcap_left -top_right_inside_corner_cells $endcap_left -at_va_boundary 72 | 73 | compile_boundary_cells -voltage_area "PD_RISC_CORE" 74 | compile_boundary_cells -voltage_area "DEFAULT_VA" 75 | 76 | ### create tap cells 77 | create_tap_cells -lib_cell $tapcell_ref -pattern stagger -distance 70 -skip_fixed_cells -voltage_area "PD_RISC_CORE" 78 | create_tap_cells -lib_cell $tapcell_ref -pattern stagger -distance 70 -skip_fixed_cells -voltage_area "DEFAULT_VA" 79 | 80 | ### connect pg 81 | connect_pg_net -automatic 82 | 83 | ### save design 84 | save_block -force 85 | save_lib 86 | 87 | ### exit icc2 88 | print_message_info 89 | #quit! 90 | 91 | ############################################################## 92 | # END 93 | ############################################################## 94 | -------------------------------------------------------------------------------- /APR/pnr/scripts/06_clockopt.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: Run Post-CTS Optimization in ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | source ./pnr/scripts/00_common_initial_settings.tcl 6 | 7 | ### variables 8 | set current_step "06_icc2_clockopt" 9 | set before_step "05_icc2_clock" 10 | 11 | ### open database 12 | file mkdir $nlib_dir 13 | file delete -force $nlib_dir/${design}_${current_step}.nlib 14 | copy_lib -from_lib ${nlib_dir}/${design}_${before_step}.nlib -to_lib ${nlib_dir}/${design}_${current_step}.nlib -force 15 | current_lib ${design}_${current_step}.nlib 16 | open_block ${design} 17 | 18 | ### initialize tool 19 | source ./pnr/scripts/initialization_settings.tcl 20 | 21 | ### create scenarios 22 | set scenarios_list $clockopt_scenarios 23 | source ./pnr/scripts/scenarios_setup.tcl 24 | foreach scenario [get_att [all_scenarios] name] { 25 | echo "Setting propagated clock on scenario $scenario" 26 | current_scenario $scenario 27 | set_propagated_clock [get_clocks -filter "is_virtual == false"] 28 | } 29 | 30 | ### set routing layers 31 | set_ignored_layers -min_routing_layer M1 -max_routing_layer M9 32 | 33 | ### set lib cell purpose for tie 34 | set_lib_cell_purpose -include optimization [get_lib_cells */*TIE*] 35 | set_dont_touch [get_lib_cells */*TIE*] false 36 | set_app_options -name opt.tie_cell.max_fanout -value 8 37 | 38 | ### set lib cell purpose for hold fix 39 | set_dont_touch $holdfix_ref false 40 | set_attribute $holdfix_ref dont_use false 41 | set_lib_cell_purpose -exclude hold [get_lib_cells */*] 42 | set_lib_cell_purpose -include hold $holdfix_ref 43 | 44 | ### choose CTS cells type 45 | set CTS_LIB_CELL_PATTERN_LIST "*/NBUFF*LVT */INVX*_LVT */CG* */AOBUFX*_LVT */AOINV* */*DFF*" 46 | set CTS_CELLS [get_lib_cells $CTS_LIB_CELL_PATTERN_LIST] 47 | set_dont_touch $CTS_CELLS false 48 | set_attribute $CTS_CELLS dont_use false 49 | set_lib_cell_purpose -exclude cts [get_lib_cells */*] 50 | set_lib_cell_purpose -include cts $CTS_CELLS 51 | 52 | ### set CTS NDR 53 | create_routing_rule CTS_NDR_2w2s -default_reference_rule \ 54 | -widths {M1 0.1 M2 0.112 M3 0.112 M4 0.112 M5 0.112 M6 0.112 M7 0.112 M8 0.112 M9 0.32} \ 55 | -spacings {M1 0.1 M2 0.112 M3 0.112 M4 0.112 M5 0.112 M6 0.112 M7 0.112 M8 0.112 M9 0.32} \ 56 | -spacing_weight_levels { M1 {medium} M2 {medium} M3 {medium} M4 {medium} M5 {hard} M6 {hard} M7 {hard} M8 {hard} M9 {medium}} 57 | 58 | ### set CTS settings (spec) 59 | set_app_options -name time.remove_clock_reconvergence_pessimism -value true 60 | set_app_options -name clock_opt.flow.enable_ccd -value false 61 | set_app_options -name clock_opt.hold.effort -value high 62 | set_app_options -name clock_opt.place.congestion_effort -value high 63 | set_app_options -name clock_opt.place.effort -value high 64 | set_app_options -name opt.dft.clock_aware_scan_reorder -value true 65 | 66 | ### set cell prefix added by cts command 67 | set_app_options -name cts.common.user_instance_name_prefix -value CTS_ 68 | set_app_options -name opt.common.user_instance_name_prefix -value CLKOPT_ 69 | 70 | ### run clock_opt 71 | clock_opt -from final_opto -to final_opto 72 | 73 | ### connect pg 74 | connect_pg_net -automatic 75 | 76 | ### save design 77 | save_block -force 78 | save_lib 79 | 80 | ### get reports 81 | set report_dir "reports/$current_step" 82 | file mkdir $report_dir 83 | check_legality > ${report_dir}/check_legality.rpt 84 | check_mv_design > ${report_dir}/check_mv_design.rpt 85 | report_qor -summary > ${report_dir}/report_qor.summary.rpt 86 | report_timing -nosplit -report_by scenario -transition_time -capacitance -physical -nets -input_pins -nworst 1 -max_paths 200 -attribute -derate -voltage -delay_type max > ${report_dir}/report_timing.rpt 87 | if { [get_utilization_configurations util_config -quiet] == "" } { 88 | create_utilization_configuration util_config -exclude {hard_macros macro_keepouts soft_macros io_cells hard_blockages} 89 | } 90 | report_utilization -config util_config > ${report_dir}/report_utilization.rpt 91 | report_utilization -config util_config -of_objects [get_voltage_areas PD_RISC_CORE] > ${report_dir}/report_utilization.PD_RISC_CORE.rpt 92 | 93 | ### exit icc2 94 | print_message_info 95 | #quit! 96 | 97 | ############################################################## 98 | # END 99 | ############################################################## 100 | -------------------------------------------------------------------------------- /APR/pnr/scripts/07_route.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: Run Routing ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | source ./pnr/scripts/00_common_initial_settings.tcl 6 | 7 | ### variables 8 | set current_step "07_icc2_route" 9 | set before_step "06_icc2_clockopt" 10 | 11 | ### open database 12 | file mkdir $nlib_dir 13 | file delete -force $nlib_dir/${design}_${current_step}.nlib 14 | copy_lib -from_lib ${nlib_dir}/${design}_${before_step}.nlib -to_lib ${nlib_dir}/${design}_${current_step}.nlib -force 15 | current_lib ${design}_${current_step}.nlib 16 | open_block ${design} 17 | 18 | ### initialize tool 19 | source ./pnr/scripts/initialization_settings.tcl 20 | 21 | ### create scenarios 22 | set scenarios_list $default_scenarios 23 | source ./pnr/scripts/scenarios_setup.tcl 24 | foreach scenario [get_att [all_scenarios] name] { 25 | echo "Setting propagated clock on scenario $scenario" 26 | current_scenario $scenario 27 | set_propagated_clock [get_clocks -filter "is_virtual == false"] 28 | } 29 | 30 | ### set routing layers 31 | set_ignored_layers -min_routing_layer M1 -max_routing_layer M9 32 | 33 | ### set lib cell purpose for tie 34 | set_lib_cell_purpose -include optimization [get_lib_cells */*TIE*] 35 | set_dont_touch [get_lib_cells */*TIE*] false 36 | set_app_options -name opt.tie_cell.max_fanout -value 8 37 | 38 | ### set lib cell purpose for hold fix 39 | set_dont_touch $holdfix_ref false 40 | set_attribute $holdfix_ref dont_use false 41 | set_lib_cell_purpose -exclude hold [get_lib_cells */*] 42 | set_lib_cell_purpose -include hold $holdfix_ref 43 | 44 | ### choose CTS cells type 45 | set CTS_LIB_CELL_PATTERN_LIST "*/NBUFF*LVT */INVX*_LVT */CG* */AOBUFX*_LVT */AOINV* */*DFF*" 46 | set CTS_CELLS [get_lib_cells $CTS_LIB_CELL_PATTERN_LIST] 47 | set_dont_touch $CTS_CELLS false 48 | set_attribute $CTS_CELLS dont_use false 49 | set_lib_cell_purpose -exclude cts [get_lib_cells */*] 50 | set_lib_cell_purpose -include cts $CTS_CELLS 51 | 52 | ### set CTS NDR 53 | if { [get_routing_rule CTS_NDR_2w2s -quiet] == "" } { 54 | create_routing_rule CTS_NDR_2w2s -default_reference_rule \ 55 | -widths {M1 0.1 M2 0.112 M3 0.112 M4 0.112 M5 0.112 M6 0.112 M7 0.112 M8 0.112 M9 0.32} \ 56 | -spacings {M1 0.1 M2 0.112 M3 0.112 M4 0.112 M5 0.112 M6 0.112 M7 0.112 M8 0.112 M9 0.32} \ 57 | -spacing_weight_levels { M1 {medium} M2 {medium} M3 {medium} M4 {medium} M5 {hard} M6 {hard} M7 {hard} M8 {hard} M9 {medium}} 58 | } 59 | 60 | ### set CTS settings (spec) 61 | set_app_options -name time.remove_clock_reconvergence_pessimism -value true 62 | set_app_options -name clock_opt.flow.enable_ccd -value false 63 | set_app_options -name clock_opt.hold.effort -value high 64 | set_app_options -name clock_opt.place.congestion_effort -value high 65 | set_app_options -name clock_opt.place.effort -value high 66 | set_app_options -name opt.dft.clock_aware_scan_reorder -value true 67 | 68 | ### set cell prefix added by cts command 69 | set_app_options -name cts.common.user_instance_name_prefix -value CTS_ 70 | set_app_options -name opt.common.user_instance_name_prefix -value ROPT_ 71 | 72 | ### set route app options 73 | set_app_options -name route.global.effort_level -value high 74 | set_app_options -name route.global.timing_driven -value true 75 | set_app_options -name route.global.crosstalk_driven -value true 76 | set_app_options -name route.track.timing_driven -value true 77 | set_app_options -name route.track.crosstalk_driven -value true 78 | set_app_options -name route.detail.timing_driven -value true 79 | 80 | set_app_options -name route.detail.save_after_iterations -value 30 81 | set_app_options -name route.detail.antenna_fixing_preference -value use_diodes 82 | set_app_options -name route.detail.insert_diodes_during_routing -value true 83 | #set_app_options -name route.common.global_max_layer_mode -value soft 84 | #set_app_options -name route.common.global_min_layer_mode -value soft 85 | set_app_options -name route.detail.diode_libcell_names -value */ANTENNA_RVT 86 | 87 | ### run route 88 | route_auto 89 | #route_global 90 | #route_track 91 | #route_detail 92 | 93 | ### connect pg 94 | connect_pg_net -automatic 95 | 96 | ### save design 97 | save_block -force 98 | save_lib 99 | 100 | ### get reports 101 | set report_dir "reports/$current_step" 102 | file mkdir $report_dir 103 | check_legality > ${report_dir}/check_legality.rpt 104 | check_mv_design > ${report_dir}/check_mv_design.rpt 105 | report_qor -summary > ${report_dir}/report_qor.summary.rpt 106 | report_timing -nosplit -report_by scenario -transition_time -capacitance -physical -nets -input_pins -nworst 1 -max_paths 200 -attribute -derate -voltage -delay_type max > ${report_dir}/report_timing.rpt 107 | if { [get_utilization_configurations util_config -quiet] == "" } { 108 | create_utilization_configuration util_config -exclude {hard_macros macro_keepouts soft_macros io_cells hard_blockages} 109 | } 110 | report_utilization -config util_config > ${report_dir}/report_utilization.rpt 111 | report_utilization -config util_config -of_objects [get_voltage_areas PD_RISC_CORE] > ${report_dir}/report_utilization.PD_RISC_CORE.rpt 112 | 113 | ### exit icc2 114 | print_message_info 115 | #quit! 116 | 117 | ############################################################## 118 | # END 119 | ############################################################## 120 | -------------------------------------------------------------------------------- /Innovus/pad_place.tcl: -------------------------------------------------------------------------------- 1 | # CLASS BLOCK ; 2 | # FOREIGN PAD63D1GU 0.000 -11.660 ; 3 | # ORIGIN 0.000 11.660 ; 4 | # SIZE 20.000 BY 84.710 ; 5 | 6 | # CLASS BLOCK ; 7 | # FOREIGN PAD63D1NU 0.000 0.000 ; 8 | # ORIGIN 0.000 0.000 ; 9 | # SIZE 20.000 BY 160.840 ; 10 | 11 | proc myppad60Out {io pad dir} { 12 | set pad_h 84.710 13 | set pad_w 20 14 | set io_h 110.0 15 | set io_w 30 16 | set ori_x 0.0 17 | set ori_y 11.660 18 | addInst -physical PAD63D1GU $pad 19 | if {$dir == "top"} { 20 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + ($io_w - $pad_w)/2]; 21 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + $io_h-$pad_h + $ori_y]; 22 | dbSet [dbGet -p top.insts.name $pad].orient R180; 23 | set padpos "{$x $y}"; 24 | } elseif {$dir == "bottom"} { 25 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + ($io_w - $pad_w)/2]; 26 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y]-$ori_y]; 27 | set padpos "{$x $y}"; 28 | } elseif {$dir == "left"} { 29 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] - $ori_y]; 30 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + ($io_w - $pad_w)/2]; 31 | set padpos "{$x $y}"; 32 | dbSet [dbGet -p top.insts.name $pad].orient R270; 33 | } elseif {$dir == "right"} { 34 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + $io_h-$pad_h+$ori_y]; 35 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + ($io_w - $pad_w)/2]; 36 | set padpos "{$x $y}"; 37 | dbSet [dbGet -p top.insts.name $pad].orient R90; 38 | } else { 39 | echo "Error direction" 40 | } 41 | dbSet [dbGet -p top.insts.name $pad].pt $padpos; 42 | } 43 | 44 | 45 | proc myppad60In {io pad dir} { 46 | set pad_h 160.840 47 | set pad_w 20 48 | set io_h 110.0 49 | set io_w 30 50 | addInst -physical PAD63D1NU $pad 51 | if {$dir == "top"} { 52 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + ($io_w - $pad_w)/2]; 53 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + $io_h-$pad_h]; 54 | dbSet [dbGet -p top.insts.name $pad].orient R180; 55 | set padpos "{$x $y}"; 56 | } elseif {$dir == "bottom"} { 57 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + ($io_w - $pad_w)/2]; 58 | set y [dbGet [dbGet -p top.insts.name $io].pt_y]; 59 | set padpos "{$x $y}"; 60 | } elseif {$dir == "left"} { 61 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + 0]; 62 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + ($io_w - $pad_w)/2]; 63 | set padpos "{$x $y}"; 64 | dbSet [dbGet -p top.insts.name $pad].orient R270; 65 | } elseif {$dir == "right"} { 66 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + $io_h-$pad_h]; 67 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + ($io_w - $pad_w)/2]; 68 | set padpos "{$x $y}"; 69 | dbSet [dbGet -p top.insts.name $pad].orient R90; 70 | } else { 71 | echo "Error direction" 72 | } 73 | dbSet [dbGet -p top.insts.name $pad].pt $padpos; 74 | } 75 | 76 | # ================================================ 77 | # 统一 PAD 生成函数 78 | # 用法: 79 | # myppad60 IO_NAME PAD_NAME DIRECTION TYPE 80 | # TYPE 可为 "in" 或 "out" 81 | # ================================================ 82 | proc myppad60 {io pad dir type} { 83 | 84 | # 根据类型设置参数 85 | if {$type == "out"} { 86 | set pad_h 84.710 87 | set pad_w 20 88 | set io_h 110.0 89 | set io_w 30 90 | set ori_x 0.0 91 | set ori_y 11.660 92 | set cell "PAD63D1GU" 93 | } elseif {$type == "in"} { 94 | set pad_h 160.840 95 | set pad_w 20 96 | set io_h 110.0 97 | set io_w 30 98 | set ori_x 0.0 99 | set ori_y 0.0 100 | set cell "PAD63D1NU" 101 | } else { 102 | echo "Error: type must be 'in' or 'out'" 103 | return 104 | } 105 | 106 | if {[dbGet top.insts.name $pad] eq 0x0} { 107 | addInst -physical $cell $pad 108 | } else { 109 | puts "Instance $pad already exists, skip addInst." 110 | } 111 | # 实例化 PAD 112 | # addInst -physical $cell $pad 113 | 114 | # 不同方向的放置逻辑 115 | if {$dir == "top"} { 116 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + ($io_w - $pad_w)/2] 117 | if {$type == "out"} { 118 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + $io_h - $pad_h + $ori_y] 119 | } else { 120 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + $io_h - $pad_h] 121 | } 122 | dbSet [dbGet -p top.insts.name $pad].orient R180 123 | 124 | } elseif {$dir == "bottom"} { 125 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + ($io_w - $pad_w)/2] 126 | if {$type == "out"} { 127 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] - $ori_y] 128 | } else { 129 | set y [dbGet [dbGet -p top.insts.name $io].pt_y] 130 | } 131 | 132 | } elseif {$dir == "left"} { 133 | if {$type == "out"} { 134 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] - $ori_y] 135 | } else { 136 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x]] 137 | } 138 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + ($io_w - $pad_w)/2] 139 | dbSet [dbGet -p top.insts.name $pad].orient R270 140 | 141 | } elseif {$dir == "right"} { 142 | if {$type == "out"} { 143 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + $io_h - $pad_h + $ori_y] 144 | } else { 145 | set x [expr [dbGet [dbGet -p top.insts.name $io].pt_x] + $io_h - $pad_h] 146 | } 147 | set y [expr [dbGet [dbGet -p top.insts.name $io].pt_y] + ($io_w - $pad_w)/2] 148 | dbSet [dbGet -p top.insts.name $pad].orient R90 149 | 150 | } else { 151 | echo "Error: direction must be top/bottom/left/right" 152 | return 153 | } 154 | 155 | # 设置 pad 坐标 156 | set padpos "{$x $y}" 157 | dbSet [dbGet -p top.insts.name $pad].pt $padpos 158 | # 打印信息 159 | echo "PAD: $pad, DIR: $dir, TYPE: $type, POS: $padpos" 160 | } 161 | 162 | # 163 | # 164 | -------------------------------------------------------------------------------- /LibChar/setup/configure_180nm.tcl: -------------------------------------------------------------------------------- 1 | # See SiliconSmart User Guide Appendix B for a complete list of parameters and definitions 2 | 3 | ################################# 4 | # OPERATING CONDITIONS DEFINITION 5 | ################################# 6 | create_operating_condition op_cond_all 7 | add_opc_supplies op_cond_all VDD 1.8 8 | add_opc_grounds op_cond_all VSS 0 9 | set_opc_temperature op_cond_all 25 10 | set_opc_process op_cond_all [subst { 11 | { .lib '[get_location]/../process/cr018gpii_v1d0.l' stat_noise} 12 | { .lib '[get_location]/../process/cr018gpii_v1d0.l' TT } 13 | }] 14 | 15 | ################################# 16 | # GLOBAL CONFIGURATION PARAMETERS 17 | ################################# 18 | define_parameters default { 19 | 20 | set nmos_model_names { nch } 21 | set pmos_model_names { pch } 22 | 23 | set constraint_mode independent 24 | set smc_constraint_style relative-degradation 25 | set smc_degrade 0.1 26 | set path_constraint_mode off 27 | 28 | # List of operating conditions as defined by create_operation_condition 29 | set active_pvts { op_cond_all } 30 | 31 | # If using IBIS, one operating condition must be specified in ibis_typ_pvt 32 | # set ibis_typ_pvt op_cond 33 | 34 | # FINESIM 35 | set simulator finesim 36 | set simulator_cmd {finesim -w -o >&/dev/null} 37 | set simulation_tmpdir /tmp 38 | 39 | # FINESIM EMBEDDED 40 | #set simulator hspice 41 | 42 | # HSPICE 43 | # set simulator hspice 44 | #set simulator_cmd {hspice -o } 45 | 46 | # HSPICE (client/server mode) 47 | # set simulator hspice_cs 48 | # set simulator_cmd {hspice -CC -port -o } 49 | 50 | # SPECTRE 51 | # set simulator spectre6 52 | # set simulator_cmd {spectremdl -tab -batch -design >&/dev/null} 53 | 54 | # ELDO 55 | # set simulator eldo 56 | # set simulator_cmd {eldo -compat -i > >&/dev/null} 57 | 58 | # MSIM 59 | # set simulator msim 60 | # (csh) 61 | # set simulator_cmd {msim -hsp -i -o >&/dev/null} 62 | # (sh) 63 | # set simulator_cmd {msim -hsp -i -o 2>/dev/null} 64 | 65 | 66 | # Default simulator options for Finesim, Hspice, Spectre, Msim, and Eldo 67 | set simulator_options { 68 | "common,finesim_embedded: probe=1 finesim_output=fsdb finesim_mode=spicehd finesim_method=gearv numdgt=7 measdgt=7" 69 | "common,finesim: probe=1 finesim_output=fsdb finesim_mode=spicehd finesim_method=gearv numdgt=7 measdgt=7" 70 | "power,finesim_embedded: probe=1 finesim_output=tr0 finesim_mode=spice2 finesim_qlevel=3 finesim_method=gear finesim_leakage_mode=1" 71 | "common,hspice: probe=1 runlvl=5 numdgt=7 measdgt=7 acct=1 nopage" 72 | 73 | "common,spectre6: compression=yes step=10ps maxstep=1ns relref=allglobal" 74 | "common,spectre6: method=trap lteratio=4 gmin=1e-18 autostop=0 save=none" 75 | 76 | "common,msim: probe=1 accurate=1" 77 | 78 | "common,eldo: gmindc=1n gmin=1p itl1=500 ingold=1 numdgt=4 measout=0 cptime=18000 relvar=0.01" 79 | "op,eldo: dv=0.5 method=gear" 80 | "tran,eldo: brief=0 relvar=0.001" 81 | "optimize,eldo: lvltim=3 relvar=0.001" 82 | "power,eldo: method=gear" 83 | } 84 | 85 | # Simulation resolution 86 | set time_res_high 1e-12 87 | set time_res_low 100e-12 88 | #set gate_leakage_time_scaling_factor 100 89 | 90 | # Controls which supplies are measured for power consumption 91 | #set power_meas_supplies { VDD VDDH VDDL } 92 | set power_meas_supplies { VDD } 93 | 94 | # list of ground supplies used (required for Functional Recognition) 95 | set power_meas_grounds { VSS } 96 | 97 | # specifies which multi-rail format to be used in Liberty model; none, v1, or v2. 98 | set liberty_multi_rail_format v2 99 | 100 | set slew_derate_upper_threshold 0.9 101 | set slew_derate_lower_threshold 0.1 102 | 103 | set liberty_max_transition 1 104 | set liberty_max_capacitance 1 105 | 106 | set archive_condition_on_success compress 107 | set archive_condition_on_failure yes 108 | 109 | # LOAD SHARE PARAMETERS 110 | # job_scheduler: 'lsf' (Platform), 'grid' (SunGrid), or 'standalone' (local machine) 111 | set job_scheduler standalone 112 | set run_list_maxsize 5 113 | set normal_queue {bnormal -R rusage[mem=4000]} 114 | 115 | #set max_hold 1e-9 116 | } 117 | 118 | 119 | ############################ 120 | # DEFAULT PINTYPE PARAMETERS 121 | ############################ 122 | pintype default { 123 | 124 | set total_slew_multiplier 2.0 125 | 126 | set logic_high_name VDD 127 | set logic_high_threshold 0.8 128 | 129 | set logic_low_name VSS 130 | set logic_low_threshold 0.2 131 | 132 | set prop_delay_level 0.5 133 | 134 | # Number of slew and load indices 135 | # (when importing with -use_default_slews -use_default_loads) 136 | set numsteps_slew 5 137 | set numsteps_load 5 138 | set constraint_numsteps_slew 3 139 | 140 | # Operating load ranges 141 | set smallest_load 10e-15 142 | #set largest_load 90e-15 143 | #set autorange_load state 144 | 145 | # Operating slew ranges 146 | # this is what is in the liberty 147 | #set smallest_slew 28e-12 148 | #set largest_slew 1.02e-09 149 | #set max_tout 1.02e-09 150 | # 151 | # due to slew_derate_from_library=0.5 152 | set smallest_slew 10.0e-12 153 | set largest_slew 5.0e-9 154 | set max_tout 5.0e-9 155 | 156 | # Automatically determine largest_load based on max_tout; off or on 157 | set autorange_load on 158 | 159 | # Noise of points in for noise height 160 | set numsteps_height 8 161 | 162 | # Input noise width. 163 | set numsteps_width 5 164 | 165 | # driver model: pwl, emulated, active, active-waveform, custom 166 | set driver_mode emulated 167 | 168 | # driver cell name (relevant only when driver_mode is "active") 169 | # set driver pwl 170 | } 171 | 172 | ##################################### 173 | # LIBERTY MODEL GENERATION PARAMETERS 174 | ##################################### 175 | define_parameters liberty_model { 176 | # Add Liberty header attributes here for use with "model -create_new_model" 177 | set delay_model "table_lookup" 178 | set default_fanout_load 1.0 179 | set default_inout_pin_cap 1.0 180 | set default_input_pin_cap 1.0 181 | set default_output_pin_cap 0.0 182 | set default_cell_leakage_power 0.0 183 | set default_leakage_power_density 0.0 184 | set in_place_swap_mode match_footprint 185 | } 186 | 187 | 188 | ####################### 189 | # VALIDATION PARAMETERS 190 | ####################### 191 | define_parameters validation { 192 | # Add validation parameters here 193 | } 194 | pintype sis_address_4->default { 195 | set bus_width 4 196 | } 197 | 198 | pintype sis_data_4->default { 199 | set bus_width 4 200 | } 201 | -------------------------------------------------------------------------------- /APR/pnr/scripts/08_routeopt.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: Run Post-Route Optimization in ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | ### load setting 6 | source ./pnr/scripts/00_common_initial_settings.tcl 7 | 8 | ### variables 9 | set current_step "08_icc2_routeopt" 10 | set before_step "07_icc2_route" 11 | 12 | ### open database 13 | file mkdir $nlib_dir 14 | file delete -force $nlib_dir/${design}_${current_step}.nlib 15 | copy_lib -from_lib ${nlib_dir}/${design}_${before_step}.nlib -to_lib ${nlib_dir}/${design}_${current_step}.nlib -force 16 | current_lib ${design}_${current_step}.nlib 17 | open_block ${design} 18 | 19 | ### temporarily removed below layers to fix starrc-in-design errors 20 | ### revised by chengquan 21 | #remove_layers PO 22 | #remove_layers CO 23 | 24 | ### initialize setting 25 | source ./pnr/scripts/initialization_settings.tcl 26 | 27 | ### reset upf 28 | reset_upf 29 | load_upf data/ORCA_TOP.upf 30 | commit_upf 31 | 32 | ### scenario setup 33 | set scenarios_list $routeopt_scenarios 34 | source ./pnr/scripts/scenarios_setup.tcl 35 | foreach scenario [get_att [all_scenarios] name] { 36 | echo "YFT-Information: Setting propagated clock on scenario $scenario" 37 | current_scenario $scenario 38 | set_propagated_clock [get_clocks -filter "is_virtual==false"] 39 | } 40 | 41 | ### routing layer 42 | set_ignored_layers -min_routing_layer M1 -max_routing_layer M9 43 | 44 | ### lib cell selection (tie, cts cells, hold fix) 45 | set_dont_touch [get_lib_cells */*TIE*] false 46 | set_attribute [get_lib_cells */*TIE*] dont_use false 47 | set_lib_cell_purpose -include {optimization} [get_lib_cells */*TIE*] 48 | set cts_cells "*/NBUFFX16_LVT */NBUFFX4_LVT */NBUFFX8_LVT */INVX16_LVT */INVX4_LVT */INVX8_LVT */*CG* */*DFF*" 49 | set cts_cells_more "saed32_lvt|saed32_lvt_std/NBUFFX16_LVT saed32_lvt|saed32_lvt_std/NBUFFX2_LVT saed32_lvt|saed32_lvt_std/NBUFFX32_LVT saed32_lvt|saed32_lvt_std/NBUFFX4_LVT saed32_lvt|saed32_lvt_std/NBUFFX8_LVT saed32_rvt|saed32_rvt_std/NBUFFX16_RVT saed32_rvt|saed32_rvt_std/NBUFFX2_RVT saed32_rvt|saed32_rvt_std/NBUFFX32_RVT saed32_rvt|saed32_rvt_std/NBUFFX4_RVT saed32_rvt|saed32_rvt_std/NBUFFX8_RVT saed32_lvt|saed32_lvt_std/AOBUFX2_LVT saed32_lvt|saed32_lvt_std/AOBUFX4_LVT saed32_rvt|saed32_rvt_std/AOBUFX2_RVT saed32_rvt|saed32_rvt_std/AOBUFX4_RVT saed32_lvt|saed32_lvt_std/IBUFFX16_LVT saed32_lvt|saed32_lvt_std/IBUFFX2_LVT saed32_lvt|saed32_lvt_std/IBUFFX4_LVT saed32_lvt|saed32_lvt_std/IBUFFX8_LVT saed32_lvt|saed32_lvt_std/INVX0_LVT saed32_lvt|saed32_lvt_std/INVX16_LVT saed32_lvt|saed32_lvt_std/INVX2_LVT saed32_lvt|saed32_lvt_std/INVX4_LVT saed32_lvt|saed32_lvt_std/INVX8_LVT saed32_rvt|saed32_rvt_std/IBUFFX16_RVT saed32_rvt|saed32_rvt_std/IBUFFX2_RVT saed32_rvt|saed32_rvt_std/IBUFFX4_RVT saed32_rvt|saed32_rvt_std/IBUFFX8_RVT saed32_rvt|saed32_rvt_std/INVX0_RVT saed32_rvt|saed32_rvt_std/INVX16_RVT saed32_rvt|saed32_rvt_std/INVX2_RVT saed32_rvt|saed32_rvt_std/INVX4_RVT saed32_rvt|saed32_rvt_std/INVX8_RVT saed32_lvt|saed32_lvt_std/AOINVX4_LVT saed32_rvt|saed32_rvt_std/AOINVX4_RVT" 50 | 51 | set_dont_touch [get_lib_cells $cts_cells] false 52 | set_att [get_lib_cells $cts_cells] dont_use false 53 | set_lib_cell_purpose -exclude cts [get_lib_cells */*] 54 | set_lib_cell_purpose -include cts [get_lib_cells {*/*BUF* */*INV*}] 55 | 56 | ### CTS NDR (Reminder: ) 57 | if { [get_routing_rule ndr_2w2s -quiet] == "" } { 58 | create_routing_rule ndr_2w2s -default_reference_rule -multiplier_width 2 -multiplier_spacing 2 59 | } 60 | if { [get_routing_rule ndr_2w2s_manual -quiet] == "" } { 61 | create_routing_rule ndr_2w2s_manual -default_reference_rule \ 62 | -widths { M1 0.1 M2 0.112 M3 0.112 M4 0.112 M5 0.112 M6 0.112 M7 0.112 M8 0.112 M9 0.32 } \ 63 | -spacings { M1 0.1 M2 0.112 M3 0.112 M4 0.112 M5 0.112 M6 0.112 M7 0.112 M8 0.112 M9 0.32 } \ 64 | -spacing_weight_levels { M1 {medium} M2 {medium} M3 {medium} M4 {medium} M5 {hard} M6 {hard} M7 {hard} M8 {hard} M9 {medium} } 65 | } 66 | set all_master_clocks [get_clocks -filter "is_virtual==false&&is_generated==false"] 67 | set all_real_clocks [get_clocks -filter "is_virtual==false"] 68 | set_clock_routing_rules -min_routing_layer M5 -max_routing_layer M8 -clocks $all_master_clocks -rules ndr_2w2s_manual 69 | 70 | ### post cts app option 71 | set_app_options -name clock_opt.flow.enable_ccd -value false 72 | set_app_options -name clock_opt.hold.effort -value high 73 | set_app_options -name clock_opt.place.congestion_effort -value high 74 | set_app_options -name clock_opt.place.effort -value high 75 | set_app_options -name cts.common.user_instance_name_prefix -value "CCDOPT_" 76 | 77 | set_app_options -name opt.common.user_instance_name_prefix -value "ROPT_" 78 | 79 | ### route app options 80 | # global route 81 | set_app_options -name route.global.crosstalk_driven -value true 82 | set_app_options -name route.global.timing_driven -value true 83 | set_app_options -name route.global.effort_level -value high 84 | set_app_options -name route.global.timing_driven_effort_level -value high 85 | 86 | # track assignment 87 | set_app_options -name route.track.crosstalk_driven -value true 88 | set_app_options -name route.track.timing_driven -value true 89 | 90 | # detail route 91 | set_app_options -name route.detail.antenna -value true 92 | set_app_options -name route.detail.antenna_fixing_preference -value use_diodes 93 | set_app_options -name route.detail.diode_libcell_names -value */ANTENNA_LVT 94 | set_app_options -name route.detail.timing_driven -value true 95 | #set_app_options -name route.detail.save_after_iterations -value 2 96 | 97 | ### update design latency 98 | compute_clock_latency -verbose 99 | 100 | ### routeopt app options 101 | set_app_options -name route_opt.flow.enable_ccd -value false 102 | set_app_options -name route_opt.flow.enable_ccd_clock_drc_fixing -value auto 103 | set_app_options -name route_opt.flow.enable_clock_power_recovery -value false 104 | set_app_options -name route_opt.flow.enable_irdrivenopt -value false 105 | set_app_options -name route_opt.flow.enable_power -value true 106 | set_app_options -name time.si_enable_analysis -value true 107 | 108 | # rc scaling : set_extraction_options 109 | 110 | #=========================== Added for New Features ============================ 111 | ### insert decap/filler 112 | #create_stdcell_fillers -lib_cells $fillers_ref -continue_on_error 113 | #connect_pg_net 114 | #remove_stdcell_fillers_with_violation 115 | 116 | #### icv in design : create metal fill 117 | #reset_app_options signoff.create_metal* 118 | #reset_app_options signoff.physical* 119 | #set_app_options -name signoff.create_metal_fill.runset -value [file normalize "./library/tech/icv/saed32nm_1p9m_mfill_rules.rs"] 120 | # 121 | ## application options about rundir 122 | #set icv_rundir "icv_rundir_mfill" 123 | #file mkdir $icv_rundir 124 | #set_app_options -name signoff.create_metal_fill.run_dir -value $icv_rundir 125 | # 126 | 127 | ### starrc in design revised by chengquan 128 | #cq set_app_options -name extract.starrc_mode -value in_design 129 | #cq set_starrc_in_design -config ./pnr/scripts/starrc_in_design.config.txt 130 | 131 | #============================ End for New Features ===========================-= 132 | 133 | ### run routeot command 134 | ### power opt/ crosstalk(xtalk) opt/ hold + setup/ ccd enable 135 | route_opt 136 | #set_app_options -name route_opt.flow.enable_power -value false 137 | #route_opt 138 | 139 | #route_opt 140 | 141 | ## pt power recovery 142 | 143 | ### connect pg 144 | connect_pg_net -all_blocks -automatic 145 | 146 | ### save 147 | save_block 148 | save_lib -all 149 | 150 | ### report 151 | set reports_dir "./reports/${current_step}" 152 | file mkdir $reports_dir 153 | check_legality -verbose > ${reports_dir}/check_legality.rpt 154 | check_mv_design > ${reports_dir}/check_mv_design.rpt 155 | report_qor -summary -significant_digits 4 > ${reports_dir}/report_qor.summary.rpt 156 | report_timing -nosplit -transition_time -capacitance -input_pins -nets -derate -delay_type max -path_type full_clock_expanded -voltage -significant_digits 4 -nworst 1 -physical -max_paths 100 > ${reports_dir}/report_timing.full.rpt 157 | report_timing -nosplit -transition_time -capacitance -input_pins -nets -derate -delay_type max -voltage -significant_digits 4 -nworst 1 -physical -max_paths 100 > ${reports_dir}/report_timing.data.rpt 158 | foreach_in_col scenario [all_scenario] { 159 | set sce_name [get_att $scenario name] 160 | report_constraints -scenarios $sce_name -max_transition -all_violators -significant_digits 3 -verbose > reports/${current_step}/report_constraints.max_transition.${sce_name}.rpt 161 | report_constraints -scenarios $sce_name -max_capacitance -all_violators -significant_digits 3 -verbose > reports/${current_step}/report_constraints.max_capacitance.${sce_name}.rpt 162 | } 163 | # postroute reports/check 164 | check_routes > ${reports_dir}/check_routes.rpt 165 | check_lvs > ${reports_dir}/check_lvs.rpt 166 | #check_lvs -nets [get_nets {}] -checks open > ${reports_dir}/check_lvs.open_nets.rpt 167 | 168 | ### exit 169 | print_message_info 170 | #quit! 171 | 172 | ############################################################## 173 | # END 174 | ############################################################## 175 | -------------------------------------------------------------------------------- /APR/pnr/scripts/03_power_routing.tcl: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # Function: Create power ground shapes and vias in ICC2 3 | # Created by Ahmed Abdelazeem 4 | ############################################################## 5 | source ./pnr/scripts/00_common_initial_settings.tcl 6 | 7 | ### variables 8 | set current_step "03_icc2_pgrouting" 9 | set before_step "02_icc2_floorplan" 10 | 11 | ### open database 12 | file mkdir $nlib_dir 13 | file delete -force $nlib_dir/${design}_${current_step}.nlib 14 | copy_lib -from_lib ${nlib_dir}/${design}_${before_step}.nlib -to_lib ${nlib_dir}/${design}_${current_step}.nlib -force 15 | current_lib ${design}_${current_step}.nlib 16 | open_block ${design} 17 | 18 | ### initialize tool 19 | source ./pnr/scripts/initialization_settings.tcl 20 | 21 | ### create scenarios 22 | set scenarios_list $default_scenarios 23 | source ./pnr/scripts/scenarios_setup.tcl 24 | 25 | ### connect pg 26 | connect_pg_net -automatic 27 | 28 | ### remove all pg regions 29 | remove_pg_regions -all 30 | 31 | ### remove power settings 32 | remove_pg_patterns -all 33 | remove_pg_strategies -all 34 | remove_pg_via_master_rules -all 35 | remove_pg_strategy_via_rules -all 36 | 37 | ### remove all pg routes 38 | remove_routes -net_types {power ground} -ring -stripe -macro_pin_connect -lib_cell_pin_connect 39 | 40 | ### create pg regions for all macros 41 | remove_pg_regions -all 42 | set macros_col [get_cells -physical_context -filter "is_hard_macro==true" -quiet] 43 | set memory_risc [get_cells -filter "is_hard_macro==true" -physical_context *REG_FILE_*_RAM*] 44 | set memory_top [remove_from_collection $macros_col $memory_risc] 45 | set region_cnt 0 46 | foreach_in_col _macro $memory_top { 47 | set macro_bbox [get_att ${_macro} bbox] ;# check the difference between boundary bbox and bbxo 48 | create_pg_region -polygon $macro_bbox MEMORY_REGION_TOP_${region_cnt} 49 | incr region_cnt 50 | } 51 | set region_cnt 0 52 | foreach_in_col _macro $memory_risc { 53 | set macro_bbox [get_att ${_macro} bbox] ;# check the difference between boundary bbox and bbxo 54 | create_pg_region -polygon $macro_bbox MEMORY_REGION_RISC_${region_cnt} 55 | incr region_cnt 56 | } 57 | 58 | ### create basic patterns 59 | ## rail pattern 60 | create_pg_std_cell_conn_pattern pattern_pg_rail -layers M1 -rail_width {@w} -parameters {w} 61 | ## stripe pattern with 5 parameters 62 | create_pg_wire_pattern pattern_stripe -layer @l -direction @d -width @w -spacing @s -pitch @p -track_alignment @t -parameters {l d w s p t} 63 | ## wire based pattern with 5 parameters 64 | create_pg_wire_pattern pattern_wire_based_on_track -layer @l -direction @d -width @w -spacing @s -pitch @p -parameters {l d w s p} -track_alignment track 65 | 66 | ### create pg rails strategies : check rails at keepout boundary 67 | set_pg_strategy strategy_pg_rail_top -pattern "{name: pattern_pg_rail} {nets: VDD VSS} {parameters: 0.06}" -blockage {{macros_with_keepout: $macros_col} {placement_blockages: all}} -voltage_areas DEFAULT_VA 68 | set_pg_strategy strategy_pg_rail_risc -pattern "{name: pattern_pg_rail} {nets: VDDH VSS} {parameters: 0.06}" -blockage {{macros_with_keepout: $macros_col} {placement_blockages: all}} -voltage_areas PD_RISC_CORE 69 | compile_pg -strategies {strategy_pg_rail_top strategy_pg_rail_risc} -tag pg_rail 70 | 71 | ### create power stripes strategies 72 | create_pg_composite_pattern pattern_core_m6_mesh_top -nets {VDD VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDD VSS}} {parameters: {M6 vertical 0.224 0.112 6.72 }}{offset: 0.1 }}} 73 | create_pg_composite_pattern pattern_core_m7_mesh_top -nets {VDD VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDD VSS}} {parameters: {M7 horizontal 0.224 0.112 6.72 }}{offset: 0.1 }}} 74 | create_pg_composite_pattern pattern_core_m8_mesh_top -nets {VDD VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDD VSS}} {parameters: {M8 vertical 0.224 0.112 6.72 }}{offset: 0.1 }}} 75 | 76 | create_pg_composite_pattern pattern_core_m6_mesh_risc -nets {VDDH VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDDH VSS}} {parameters: {M6 vertical 0.224 0.112 6.72 }}{offset: 0.1 }}} 77 | create_pg_composite_pattern pattern_core_m7_mesh_risc -nets {VDDH VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDDH VSS}} {parameters: {M7 horizontal 0.224 0.112 6.72 }}{offset: 0.1 }}} 78 | create_pg_composite_pattern pattern_core_m8_mesh_risc -nets {VDDH VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDDH VSS}} {parameters: {M8 vertical 0.224 0.112 6.72 }}{offset: 0.1 }}} 79 | 80 | create_pg_composite_pattern pattern_core_m9_mesh -nets {VDD VDDH VSS} -add_patterns {{{pattern: pattern_wire_based_on_track} {nets: {VDD VDDH VSS}} {parameters: {M9 horizontal 0.64 0.32 3.20 }}{offset: 0.1 }}} 81 | 82 | set memory_regions_top [get_pg_regions MEMORY_REGION_TOP_* -quiet] 83 | set_pg_strategy strategy_m6_pg_mesh_top -pattern {{name: pattern_core_m6_mesh_top} {nets: {VDD VSS}}} -blockage {pg_regions: $memory_regions_top} -voltage_areas DEFAULT_VA 84 | set_pg_strategy strategy_m7_pg_mesh_top -pattern {{name: pattern_core_m7_mesh_top} {nets: {VDD VSS}}} -blockage {pg_regions: $memory_regions_top} -voltage_areas DEFAULT_VA 85 | set_pg_strategy strategy_m8_pg_mesh_top -pattern {{name: pattern_core_m8_mesh_top} {nets: {VDD VSS}}} -blockage {pg_regions: $memory_regions_top} -voltage_areas DEFAULT_VA 86 | 87 | set memory_regions_risc [get_pg_regions MEMORY_REGION_RISC_* -quiet] 88 | set_pg_strategy strategy_m6_pg_mesh_risc -pattern {{name: pattern_core_m6_mesh_risc} {nets: {VDDH VSS}}} -blockage {pg_regions: $memory_regions_risc} -voltage_areas PD_RISC_CORE 89 | set_pg_strategy strategy_m7_pg_mesh_risc -pattern {{name: pattern_core_m7_mesh_risc} {nets: {VDDH VSS}}} -blockage {pg_regions: $memory_regions_risc} -voltage_areas PD_RISC_CORE 90 | set_pg_strategy strategy_m8_pg_mesh_risc -pattern {{name: pattern_core_m8_mesh_risc} {nets: {VDDH VSS}}} -blockage {pg_regions: $memory_regions_risc} -voltage_areas PD_RISC_CORE 91 | set_pg_strategy strategy_m9_pg_mesh -pattern {{name: pattern_core_m9_mesh} {nets: {VDD VDDH VSS}}} -design_boundary 92 | 93 | ### create via rules stripes 94 | #set_pg_via_master_rule pgvia_array_8x10 -via_array_dimension {8 10} 95 | set_pg_strategy_via_rule via_pg_core -via_rule { \ 96 | {{{strategies: strategy_m9_pg_mesh}{layers: M9}}{{strategies: strategy_m8_pg_mesh_top}{layers: M8}}{via_master:default} } \ 97 | {{{strategies: strategy_m9_pg_mesh}{layers: M9}}{{strategies: strategy_m8_pg_mesh_risc}{layers: M8}}{via_master:default} } \ 98 | {{{strategies: strategy_m8_pg_mesh_top}{layers: M8}}{{strategies: strategy_m7_pg_mesh_top}{layers: M7}}{via_master:default} } \ 99 | {{{strategies: strategy_m8_pg_mesh_risc}{layers: M8}}{{strategies: strategy_m7_pg_mesh_risc}{layers: M7}}{via_master:default} } \ 100 | {{{strategies: strategy_m7_pg_mesh_top}{layers: M7}}{{strategies: strategy_m6_pg_mesh_top}{layers: M6}}{via_master:default} } \ 101 | {{{strategies: strategy_m7_pg_mesh_risc}{layers: M7}}{{strategies: strategy_m6_pg_mesh_risc}{layers: M6}}{via_master:default} } \ 102 | {{{existing : std_conn }}{{strategies: strategy_m6_pg_mesh_top}{layers: M6}}{via_master:default} } \ 103 | {{{existing : std_conn }}{{strategies: strategy_m6_pg_mesh_risc}{layers: M6}}{via_master:default} } \ 104 | {{intersection: adjacent}{via_master: default}} } 105 | 106 | #compile_pg -strategies {strategy_m6_pg_mesh} -tag pg_stripes -via_rule {via_pg_core} -ignore_via_drc 107 | compile_pg -strategies {strategy_m6_pg_mesh_top strategy_m6_pg_mesh_risc strategy_m7_pg_mesh_top strategy_m7_pg_mesh_risc strategy_m8_pg_mesh_top strategy_m8_pg_mesh_risc strategy_m9_pg_mesh} -tag pg_stripes -via_rule {via_pg_core} -ignore_via_drc 108 | 109 | ### create macro ring and pin connection 110 | create_pg_ring_pattern pattern_memory_ring -horizontal_layer M5 -horizontal_width {1} -vertical_layer M6 -vertical_width {1} -corner_bridge false 111 | set_pg_strategy strategy_memory_ring_top -macros $memory_top -pattern { {pattern: pattern_memory_ring} {nets: {VSS VDD}} {offset: {0.3 0.3}} } 112 | set_pg_strategy strategy_memory_ring_risc -macros $memory_risc -pattern { {pattern: pattern_memory_ring} {nets: {VSS VDDH}} {offset: {0.3 0.3}} } 113 | set_pg_strategy_via_rule strategy_memory_ring_vias -via_rule { \ 114 | {{{strategies: {strategy_memory_ring_top strategy_memory_ring_risc}} {layers: {M5}}} {existing: {strap }}{via_master: {default}}} \ 115 | {{{strategies: {strategy_memory_ring_top strategy_memory_ring_risc}} {layers: {M6}}} {existing: {strap }}{via_master: {default}}} \ 116 | } 117 | compile_pg -strategies {strategy_memory_ring_top strategy_memory_ring_risc} -via_rule {strategy_memory_ring_vias} 118 | 119 | ### connect macro pins 120 | create_pg_macro_conn_pattern pattern_memory_pin -pin_conn_type scattered_pin -layers {M5 M6} 121 | set_pg_strategy strategy_top_pins -macros $memory_top -pattern { {pattern: pattern_memory_pin} {nets: {VSS VDD}} } 122 | set_pg_strategy strategy_risc_pins -macros $memory_risc -pattern { {pattern: pattern_memory_pin} {nets: {VSS VDDH}} } 123 | compile_pg -strategies {strategy_top_pins strategy_risc_pins} 124 | 125 | ### save design 126 | save_block -force 127 | save_lib 128 | 129 | ### exit icc2 130 | print_message_info 131 | #quit! 132 | 133 | ############################################################## 134 | # END 135 | ############################################################## 136 | 137 | -------------------------------------------------------------------------------- /APR/pnr/scripts/scenarios_setup.tcl: -------------------------------------------------------------------------------- 1 | source $data_dir/constraints/ORCA_TOP_port_lists.tcl 2 | 3 | remove_scenarios -all 4 | remove_corners -all 5 | remove_modes -all 6 | 7 | ### create modes, corners and scenarios : check errors 8 | ## func_ss0p75v125c_cmax 9 | if { [get_scenarios func_ss0p75v125c_cmax -quiet] == "" && [info exists scenarios_list] && [lsearch $scenarios_list "func_ss0p75v125c_cmax"] != -1 } { 10 | if { [get_modes func -quiet] == "" } { 11 | create_mode func 12 | } 13 | if { [get_corner ss0p75v125c_cmax -quiet] == "" } { 14 | create_corner ss0p75v125c_cmax 15 | } 16 | create_scenario -mode func -corner ss0p75v125c_cmax -name func_ss0p75v125c_cmax 17 | current_scenario func_ss0p75v125c_cmax 18 | read_parasitic_tech -layermap $itf_tluplus_map -tlup $icc2rc_tech(cmax) -name maxTLU 19 | remove_sdc -scenarios [current_scenario] 20 | source $data_dir/constraints/ORCA_TOP_m_func.tcl 21 | source $data_dir/constraints/ORCA_TOP_c_ss_125c.tcl 22 | source $data_dir/constraints/ORCA_TOP_s_func.ss_125c.tcl 23 | # set clock uncertainty 24 | if { [regexp {place} $current_step] } { 25 | set_clock_uncertainty -setup 0.200 [get_clocks SYS_*] 26 | set_clock_uncertainty -setup 0.300 [get_clocks PCI_CLK] 27 | set_clock_uncertainty -setup 0.200 [get_clocks SDRAM_CLK] 28 | } elseif { [regexp {clock} $current_step] } { 29 | set_clock_uncertainty -setup 0.200 [get_clocks SYS_*] 30 | set_clock_uncertainty -hold 0.100 [get_clocks SYS_*] 31 | set_clock_uncertainty -setup 0.300 [get_clocks PCI_CLK] 32 | set_clock_uncertainty -hold 0.100 [get_clocks PCI_CLK] 33 | set_clock_uncertainty -setup 0.200 [get_clocks SDRAM_CLK] 34 | set_clock_uncertainty -hold 0.100 [get_clocks SDRAM_CLK] 35 | } elseif { [regexp {route} $current_step] } { 36 | set_clock_uncertainty -setup 0.200 [get_clocks SYS_*] 37 | set_clock_uncertainty -hold 0.100 [get_clocks SYS_*] 38 | set_clock_uncertainty -setup 0.300 [get_clocks PCI_CLK] 39 | set_clock_uncertainty -hold 0.100 [get_clocks PCI_CLK] 40 | set_clock_uncertainty -setup 0.200 [get_clocks SDRAM_CLK] 41 | set_clock_uncertainty -hold 0.100 [get_clocks SDRAM_CLK] 42 | } 43 | set_max_transition 0.15 [get_clock *] -clock_path 44 | set_max_transition 0.25 [get_clock *] -data_path 45 | set_max_capacitance 150 [current_design] 46 | set_scenario_status func_ss0p75v125c_cmax -active true -setup true -hold true -max_capacitance true -max_transition true -min_capacitance true -leakage_power false -dynamic_power false 47 | } 48 | 49 | ## test_ss0p75v125c_cmax 50 | if { [get_scenarios test_ss0p75v125c_cmax -quiet] == "" && [info exists scenarios_list] && [lsearch $scenarios_list "test_ss0p75v125c_cmax"] != -1 } { 51 | if { [get_modes test -quiet] == "" } { 52 | create_mode test 53 | } 54 | if { [get_corner ss0p75v125c_cmax -quiet] == "" } { 55 | create_corner ss0p75v125c_cmax 56 | } 57 | create_scenario -mode test -corner ss0p75v125c_cmax -name test_ss0p75v125c_cmax 58 | read_parasitic_tech -layermap $itf_tluplus_map -tlup $icc2rc_tech(cmax) -name maxTLU 59 | current_scenario test_ss0p75v125c_cmax 60 | source $data_dir/constraints/ORCA_TOP_m_test.tcl 61 | source $data_dir/constraints/ORCA_TOP_c_ss_125c.tcl 62 | source $data_dir/constraints/ORCA_TOP_s_test.ss_125c.tcl 63 | # set clock uncertainty 64 | if { [regexp {place} $current_step] } { 65 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 66 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 67 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 68 | set_clock_uncertainty -setup 0.3 [get_clocks ate_clk] 69 | } elseif { [regexp {clock} $current_step] } { 70 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 71 | set_clock_uncertainty -hold 0.1 [get_clocks SYS_*] 72 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 73 | set_clock_uncertainty -hold 0.1 [get_clocks PCI_CLK] 74 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 75 | set_clock_uncertainty -hold 0.1 [get_clocks SDRAM_CLK] 76 | set_clock_uncertainty -setup 0.3 [get_clocks ate_clk] 77 | set_clock_uncertainty -hold 0.2 [get_clocks ate_clk] 78 | } elseif { [regexp {route} $current_step] } { 79 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 80 | set_clock_uncertainty -hold 0.1 [get_clocks SYS_*] 81 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 82 | set_clock_uncertainty -hold 0.1 [get_clocks PCI_CLK] 83 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 84 | set_clock_uncertainty -hold 0.1 [get_clocks SDRAM_CLK] 85 | set_clock_uncertainty -setup 0.3 [get_clocks ate_clk] 86 | set_clock_uncertainty -hold 0.2 [get_clocks ate_clk] 87 | } 88 | set_max_transition 0.15 [get_clock *] -clock_path 89 | set_max_transition 0.25 [get_clock *] -data_path 90 | set_max_capacitance 150 [current_design] 91 | set_scenario_status test_ss0p75v125c_cmax -active true -setup true -hold true -max_capacitance true -max_transition true -min_capacitance true -leakage_power false -dynamic_power false 92 | } 93 | 94 | ## func_ff0p95v125c_cmin 95 | if { [get_scenarios func_ff0p95vm40c_cmin -quiet] == "" && [info exists scenarios_list] && [lsearch $scenarios_list "func_ff0p95vm40c_cmin"] != -1 } { 96 | if { [get_modes func -quiet] == "" } { 97 | create_mode func 98 | } 99 | if { [get_corner ff0p95vm40c_cmin -quiet] == "" } { 100 | create_corner ff0p95vm40c_cmin 101 | } 102 | create_scenario -mode func -corner ff0p95vm40c_cmin -name func_ff0p95vm40c_cmin 103 | current_scenario func_ff0p95vm40c_cmin 104 | read_parasitic_tech -layermap $itf_tluplus_map -tlup $icc2rc_tech(cmin) -name minTLU 105 | source $data_dir/constraints/ORCA_TOP_m_func.tcl 106 | source $data_dir/constraints/ORCA_TOP_c_ss_m40c.tcl 107 | source $data_dir/constraints/ORCA_TOP_s_func.ss_m40c.tcl 108 | # set clock uncertainty 109 | if { [regexp {place} $current_step] } { 110 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 111 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 112 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 113 | } elseif { [regexp {clock} $current_step] } { 114 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 115 | set_clock_uncertainty -hold 0.1 [get_clocks SYS_*] 116 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 117 | set_clock_uncertainty -hold 0.1 [get_clocks PCI_CLK] 118 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 119 | set_clock_uncertainty -hold 0.1 [get_clocks SDRAM_CLK] 120 | } elseif { [regexp {route} $current_step] } { 121 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 122 | set_clock_uncertainty -hold 0.1 [get_clocks SYS_*] 123 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 124 | set_clock_uncertainty -hold 0.1 [get_clocks PCI_CLK] 125 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 126 | set_clock_uncertainty -hold 0.1 [get_clocks SDRAM_CLK] 127 | } 128 | set_max_transition 0.15 [get_clock *] -clock_path 129 | set_max_transition 0.25 [get_clock *] -data_path 130 | set_max_capacitance 150 [current_design] 131 | set_scenario_status func_ff0p95vm40c_cmin -active true -setup true -hold true -max_capacitance true -max_transition true -min_capacitance true -leakage_power false -dynamic_power false 132 | } 133 | 134 | ## test_ff0p95v125c_cmin 135 | if { [get_scenarios test_ff0p95v125c_cmin -quiet] == "" && [info exists scenarios_list] && [lsearch $scenarios_list "test_ff0p95v125c_cmin"] != -1 } { 136 | if { [get_modes test -quiet] == "" } { 137 | create_mode test 138 | } 139 | if { [get_corner ff0p95v125c_cmin -quiet] == "" } { 140 | create_corner ff0p95v125c_cmin 141 | } 142 | create_scenario -mode test -corner ff0p95v125c_cmin -name test_ff0p95v125c_cmin 143 | read_parasitic_tech -layermap $itf_tluplus_map -tlup $icc2rc_tech(cmin) -name minTLU 144 | current_scenario test_ff0p95v125c_cmin 145 | source $data_dir/constraints/ORCA_TOP_m_test.tcl 146 | source $data_dir/constraints/ORCA_TOP_c_ss_125c.tcl 147 | source $data_dir/constraints/ORCA_TOP_s_test.ss_125c.tcl 148 | # set clock uncertainty 149 | if { [regexp {place} $current_step] } { 150 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 151 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 152 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 153 | set_clock_uncertainty -setup 0.3 [get_clocks ate_clk] 154 | } elseif { [regexp {clock} $current_step] } { 155 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 156 | set_clock_uncertainty -hold 0.1 [get_clocks SYS_*] 157 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 158 | set_clock_uncertainty -hold 0.1 [get_clocks PCI_CLK] 159 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 160 | set_clock_uncertainty -hold 0.1 [get_clocks SDRAM_CLK] 161 | set_clock_uncertainty -setup 0.3 [get_clocks ate_clk] 162 | set_clock_uncertainty -hold 0.2 [get_clocks ate_clk] 163 | } elseif { [regexp {route} $current_step] } { 164 | set_clock_uncertainty -setup 0.2 [get_clocks SYS_*] 165 | set_clock_uncertainty -hold 0.1 [get_clocks SYS_*] 166 | set_clock_uncertainty -setup 0.3 [get_clocks PCI_CLK] 167 | set_clock_uncertainty -hold 0.1 [get_clocks PCI_CLK] 168 | set_clock_uncertainty -setup 0.2 [get_clocks SDRAM_CLK] 169 | set_clock_uncertainty -hold 0.1 [get_clocks SDRAM_CLK] 170 | set_clock_uncertainty -setup 0.3 [get_clocks ate_clk] 171 | set_clock_uncertainty -hold 0.2 [get_clocks ate_clk] 172 | } 173 | set_max_transition 0.15 [get_clock *] -clock_path 174 | set_max_transition 0.25 [get_clock *] -data_path 175 | set_max_capacitance 150 [current_design] 176 | set_scenario_status test_ff0p95v125c_cmin -active true -setup true -hold true -max_capacitance true -max_transition true -min_capacitance true -leakage_power false -dynamic_power false 177 | } 178 | 179 | ## cts_ss0p75v125c_cmax 180 | if { [get_scenarios cts_ss0p75v125c_cmax -quiet] == "" && [info exists scenarios_list] && [lsearch $scenarios_list "cts_ss0p75v125c_cmax"] != -1 } { 181 | create_mode cts 182 | create_corner ss0p75v125c_cmax 183 | create_scenario -mode cts -corner ss0p75v125c_cmax -name cts_ss0p75v125c_cmax 184 | read_parasitic_tech -layermap $itf_tluplus_map -tlup $icc2rc_tech(cmax) -name maxTLU 185 | current_scenario cts_ss0p75v125c_cmax 186 | remove_sdc -scenarios [current_scenario] 187 | source $data_dir/constraints/ORCA_TOP_m_cts.tcl 188 | source $data_dir/constraints/ORCA_TOP_c_ss_125c.tcl 189 | source $data_dir/constraints/ORCA_TOP_s_func.ss_125c.tcl 190 | set_max_transition 0.15 [get_clock *] -clock_path 191 | set_max_transition 0.25 [get_clock *] -data_path 192 | set_max_capacitance 150 [current_design] 193 | set_scenario_status cts_ss0p75v125c_cmax -active true -setup true -hold true -max_capacitance true -max_transition true -min_capacitance true -leakage_power false -dynamic_power false 194 | } 195 | 196 | 197 | -------------------------------------------------------------------------------- /SYN/NPU_ADD_TREE.sdc: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | 3 | # Created by write_sdc on Tue Dec 7 01:27:19 2021 4 | 5 | ################################################################### 6 | set sdc_version 2.1 7 | 8 | set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA 9 | set_max_area 0 10 | set_load -pin_load 0.0231504 [get_ports {add_result[18]}] 11 | set_load -pin_load 0.0231504 [get_ports {add_result[17]}] 12 | set_load -pin_load 0.0231504 [get_ports {add_result[16]}] 13 | set_load -pin_load 0.0231504 [get_ports {add_result[15]}] 14 | set_load -pin_load 0.0231504 [get_ports {add_result[14]}] 15 | set_load -pin_load 0.0231504 [get_ports {add_result[13]}] 16 | set_load -pin_load 0.0231504 [get_ports {add_result[12]}] 17 | set_load -pin_load 0.0231504 [get_ports {add_result[11]}] 18 | set_load -pin_load 0.0231504 [get_ports {add_result[10]}] 19 | set_load -pin_load 0.0231504 [get_ports {add_result[9]}] 20 | set_load -pin_load 0.0231504 [get_ports {add_result[8]}] 21 | set_load -pin_load 0.0231504 [get_ports {add_result[7]}] 22 | set_load -pin_load 0.0231504 [get_ports {add_result[6]}] 23 | set_load -pin_load 0.0231504 [get_ports {add_result[5]}] 24 | set_load -pin_load 0.0231504 [get_ports {add_result[4]}] 25 | set_load -pin_load 0.0231504 [get_ports {add_result[3]}] 26 | set_load -pin_load 0.0231504 [get_ports {add_result[2]}] 27 | set_load -pin_load 0.0231504 [get_ports {add_result[1]}] 28 | set_load -pin_load 0.0231504 [get_ports {add_result[0]}] 29 | create_clock [get_ports clk] -period 2 -waveform {0 1} 30 | set_input_delay 0 [get_ports clk] 31 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[63]}] 32 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[62]}] 33 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[61]}] 34 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[60]}] 35 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[59]}] 36 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[58]}] 37 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[57]}] 38 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[56]}] 39 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[55]}] 40 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[54]}] 41 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[53]}] 42 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[52]}] 43 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[51]}] 44 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[50]}] 45 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[49]}] 46 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[48]}] 47 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[47]}] 48 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[46]}] 49 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[45]}] 50 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[44]}] 51 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[43]}] 52 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[42]}] 53 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[41]}] 54 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[40]}] 55 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[39]}] 56 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[38]}] 57 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[37]}] 58 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[36]}] 59 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[35]}] 60 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[34]}] 61 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[33]}] 62 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[32]}] 63 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[31]}] 64 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[30]}] 65 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[29]}] 66 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[28]}] 67 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[27]}] 68 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[26]}] 69 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[25]}] 70 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[24]}] 71 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[23]}] 72 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[22]}] 73 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[21]}] 74 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[20]}] 75 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[19]}] 76 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[18]}] 77 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[17]}] 78 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[16]}] 79 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[15]}] 80 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[14]}] 81 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[13]}] 82 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[12]}] 83 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[11]}] 84 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[10]}] 85 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[9]}] 86 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[8]}] 87 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[7]}] 88 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[6]}] 89 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[5]}] 90 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[4]}] 91 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[3]}] 92 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[2]}] 93 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[1]}] 94 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_data[0]}] 95 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[63]}] 96 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[62]}] 97 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[61]}] 98 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[60]}] 99 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[59]}] 100 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[58]}] 101 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[57]}] 102 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[56]}] 103 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[55]}] 104 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[54]}] 105 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[53]}] 106 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[52]}] 107 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[51]}] 108 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[50]}] 109 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[49]}] 110 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[48]}] 111 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[47]}] 112 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[46]}] 113 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[45]}] 114 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[44]}] 115 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[43]}] 116 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[42]}] 117 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[41]}] 118 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[40]}] 119 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[39]}] 120 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[38]}] 121 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[37]}] 122 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[36]}] 123 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[35]}] 124 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[34]}] 125 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[33]}] 126 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[32]}] 127 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[31]}] 128 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[30]}] 129 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[29]}] 130 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[28]}] 131 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[27]}] 132 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[26]}] 133 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[25]}] 134 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[24]}] 135 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[23]}] 136 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[22]}] 137 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[21]}] 138 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[20]}] 139 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[19]}] 140 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[18]}] 141 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[17]}] 142 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[16]}] 143 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[15]}] 144 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[14]}] 145 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[13]}] 146 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[12]}] 147 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[11]}] 148 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[10]}] 149 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[9]}] 150 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[8]}] 151 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[7]}] 152 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[6]}] 153 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[5]}] 154 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[4]}] 155 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[3]}] 156 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[2]}] 157 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[1]}] 158 | set_input_delay -clock clk 0.27272 [get_ports {add_tree_para[0]}] 159 | set_input_delay -clock clk 0.27272 [get_ports is_signed_data] 160 | set_output_delay -clock clk 0 [get_ports {add_result[18]}] 161 | set_output_delay -clock clk 0 [get_ports {add_result[17]}] 162 | set_output_delay -clock clk 0 [get_ports {add_result[16]}] 163 | set_output_delay -clock clk 0 [get_ports {add_result[15]}] 164 | set_output_delay -clock clk 0 [get_ports {add_result[14]}] 165 | set_output_delay -clock clk 0 [get_ports {add_result[13]}] 166 | set_output_delay -clock clk 0 [get_ports {add_result[12]}] 167 | set_output_delay -clock clk 0 [get_ports {add_result[11]}] 168 | set_output_delay -clock clk 0 [get_ports {add_result[10]}] 169 | set_output_delay -clock clk 0 [get_ports {add_result[9]}] 170 | set_output_delay -clock clk 0 [get_ports {add_result[8]}] 171 | set_output_delay -clock clk 0 [get_ports {add_result[7]}] 172 | set_output_delay -clock clk 0 [get_ports {add_result[6]}] 173 | set_output_delay -clock clk 0 [get_ports {add_result[5]}] 174 | set_output_delay -clock clk 0 [get_ports {add_result[4]}] 175 | set_output_delay -clock clk 0 [get_ports {add_result[3]}] 176 | set_output_delay -clock clk 0 [get_ports {add_result[2]}] 177 | set_output_delay -clock clk 0 [get_ports {add_result[1]}] 178 | set_output_delay -clock clk 0 [get_ports {add_result[0]}] 179 | -------------------------------------------------------------------------------- /APR/pnr/scripts/place_hard_macros.tcl: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # Created by icc2 write_floorplan on Sun Nov 22 17:07:13 2020 4 | # 5 | ################################################################################ 6 | 7 | 8 | set _dirName__0 [file dirname [file normalize [info script]]] 9 | 10 | ################################################################################ 11 | # Cells 12 | ################################################################################ 13 | 14 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_8 }] 15 | set_attribute -quiet -objects $cellInst -name orientation -value R0 16 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 162.1520 } 17 | set_attribute -quiet -objects $cellInst -name status -value placed 18 | 19 | 20 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_7 }] 21 | set_attribute -quiet -objects $cellInst -name orientation -value R0 22 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 87.3330 } 23 | set_attribute -quiet -objects $cellInst -name status -value placed 24 | 25 | 26 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_6 }] 27 | set_attribute -quiet -objects $cellInst -name orientation -value R0 28 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 12.5140 } 29 | set_attribute -quiet -objects $cellInst -name status -value placed 30 | 31 | 32 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_5 }] 33 | set_attribute -quiet -objects $cellInst -name orientation -value R0 34 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 915.5280 } 35 | set_attribute -quiet -objects $cellInst -name status -value placed 36 | 37 | 38 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_4 }] 39 | set_attribute -quiet -objects $cellInst -name orientation -value R0 40 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 840.7090 } 41 | set_attribute -quiet -objects $cellInst -name status -value placed 42 | 43 | 44 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_3 }] 45 | set_attribute -quiet -objects $cellInst -name orientation -value R0 46 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 765.8900 } 47 | set_attribute -quiet -objects $cellInst -name status -value placed 48 | 49 | 50 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_2 }] 51 | set_attribute -quiet -objects $cellInst -name orientation -value R0 52 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 691.0710 } 53 | set_attribute -quiet -objects $cellInst -name status -value placed 54 | 55 | 56 | set cellInst [get_cells { I_PCI_TOP/I_PCI_READ_FIFO/PCI_FIFO_RAM_1 }] 57 | set_attribute -quiet -objects $cellInst -name orientation -value R0 58 | set_attribute -quiet -objects $cellInst -name origin -value { 919.7860 616.2520 } 59 | set_attribute -quiet -objects $cellInst -name status -value placed 60 | 61 | 62 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_8 }] 63 | set_attribute -quiet -objects $cellInst -name orientation -value R0 64 | set_attribute -quiet -objects $cellInst -name origin -value { 830.4770 915.5280 } 65 | set_attribute -quiet -objects $cellInst -name status -value placed 66 | 67 | 68 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_7 }] 69 | set_attribute -quiet -objects $cellInst -name orientation -value R0 70 | set_attribute -quiet -objects $cellInst -name origin -value { 830.4770 840.7090 } 71 | set_attribute -quiet -objects $cellInst -name status -value placed 72 | 73 | 74 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_6 }] 75 | set_attribute -quiet -objects $cellInst -name orientation -value R0 76 | set_attribute -quiet -objects $cellInst -name origin -value { 830.4770 765.8900 } 77 | set_attribute -quiet -objects $cellInst -name status -value placed 78 | 79 | 80 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_5 }] 81 | set_attribute -quiet -objects $cellInst -name orientation -value R0 82 | set_attribute -quiet -objects $cellInst -name origin -value { 830.4770 691.0710 } 83 | set_attribute -quiet -objects $cellInst -name status -value placed 84 | 85 | 86 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_4 }] 87 | set_attribute -quiet -objects $cellInst -name orientation -value R0 88 | set_attribute -quiet -objects $cellInst -name origin -value { 830.4770 616.2520 } 89 | set_attribute -quiet -objects $cellInst -name status -value placed 90 | 91 | 92 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_3 }] 93 | set_attribute -quiet -objects $cellInst -name orientation -value R0 94 | set_attribute -quiet -objects $cellInst -name origin -value { 834.7280 162.1520 } 95 | set_attribute -quiet -objects $cellInst -name status -value placed 96 | 97 | 98 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_2 }] 99 | set_attribute -quiet -objects $cellInst -name orientation -value R0 100 | set_attribute -quiet -objects $cellInst -name origin -value { 834.7280 87.3330 } 101 | set_attribute -quiet -objects $cellInst -name status -value placed 102 | 103 | 104 | set cellInst [get_cells { I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_1 }] 105 | set_attribute -quiet -objects $cellInst -name orientation -value R0 106 | set_attribute -quiet -objects $cellInst -name origin -value { 834.7280 12.5140 } 107 | set_attribute -quiet -objects $cellInst -name status -value placed 108 | 109 | 110 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_0_1 }] 111 | set_attribute -quiet -objects $cellInst -name orientation -value R0 112 | set_attribute -quiet -objects $cellInst -name origin -value { 274.1890 12.5140 } 113 | set_attribute -quiet -objects $cellInst -name status -value placed 114 | 115 | 116 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_0_2 }] 117 | set_attribute -quiet -objects $cellInst -name orientation -value R0 118 | set_attribute -quiet -objects $cellInst -name origin -value { 274.1890 114.8310 } 119 | set_attribute -quiet -objects $cellInst -name status -value placed 120 | 121 | 122 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_0_3 }] 123 | set_attribute -quiet -objects $cellInst -name orientation -value R0 124 | set_attribute -quiet -objects $cellInst -name origin -value { 274.1890 217.1480 } 125 | set_attribute -quiet -objects $cellInst -name status -value placed 126 | 127 | 128 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_0_4 }] 129 | set_attribute -quiet -objects $cellInst -name orientation -value R0 130 | set_attribute -quiet -objects $cellInst -name origin -value { 274.1890 319.4650 } 131 | set_attribute -quiet -objects $cellInst -name status -value placed 132 | 133 | 134 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_1_1 }] 135 | set_attribute -quiet -objects $cellInst -name orientation -value R0 136 | set_attribute -quiet -objects $cellInst -name origin -value { 187.1330 12.5140 } 137 | set_attribute -quiet -objects $cellInst -name status -value placed 138 | 139 | 140 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_1_2 }] 141 | set_attribute -quiet -objects $cellInst -name orientation -value R0 142 | set_attribute -quiet -objects $cellInst -name origin -value { 187.1330 114.8310 } 143 | set_attribute -quiet -objects $cellInst -name status -value placed 144 | 145 | 146 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_1_3 }] 147 | set_attribute -quiet -objects $cellInst -name orientation -value R0 148 | set_attribute -quiet -objects $cellInst -name origin -value { 187.1330 217.1480 } 149 | set_attribute -quiet -objects $cellInst -name status -value placed 150 | 151 | 152 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_1_4 }] 153 | set_attribute -quiet -objects $cellInst -name orientation -value R0 154 | set_attribute -quiet -objects $cellInst -name origin -value { 187.1330 319.4650 } 155 | set_attribute -quiet -objects $cellInst -name status -value placed 156 | 157 | 158 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_2_1 }] 159 | set_attribute -quiet -objects $cellInst -name orientation -value R0 160 | set_attribute -quiet -objects $cellInst -name origin -value { 100.0770 12.5140 } 161 | set_attribute -quiet -objects $cellInst -name status -value placed 162 | 163 | 164 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_2_2 }] 165 | set_attribute -quiet -objects $cellInst -name orientation -value R0 166 | set_attribute -quiet -objects $cellInst -name origin -value { 100.0770 114.8310 } 167 | set_attribute -quiet -objects $cellInst -name status -value placed 168 | 169 | 170 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_2_3 }] 171 | set_attribute -quiet -objects $cellInst -name orientation -value R0 172 | set_attribute -quiet -objects $cellInst -name origin -value { 100.0770 217.1480 } 173 | set_attribute -quiet -objects $cellInst -name status -value placed 174 | 175 | 176 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_2_4 }] 177 | set_attribute -quiet -objects $cellInst -name orientation -value R0 178 | set_attribute -quiet -objects $cellInst -name origin -value { 100.0770 319.4650 } 179 | set_attribute -quiet -objects $cellInst -name status -value placed 180 | 181 | 182 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_3_1 }] 183 | set_attribute -quiet -objects $cellInst -name orientation -value R0 184 | set_attribute -quiet -objects $cellInst -name origin -value { 13.0210 12.5140 } 185 | set_attribute -quiet -objects $cellInst -name status -value placed 186 | 187 | 188 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_3_2 }] 189 | set_attribute -quiet -objects $cellInst -name orientation -value R0 190 | set_attribute -quiet -objects $cellInst -name origin -value { 13.0210 114.8310 } 191 | set_attribute -quiet -objects $cellInst -name status -value placed 192 | 193 | 194 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_3_3 }] 195 | set_attribute -quiet -objects $cellInst -name orientation -value R0 196 | set_attribute -quiet -objects $cellInst -name origin -value { 13.0210 217.1480 } 197 | set_attribute -quiet -objects $cellInst -name status -value placed 198 | 199 | 200 | set cellInst [get_cells { I_CONTEXT_MEM/I_CONTEXT_RAM_3_4 }] 201 | set_attribute -quiet -objects $cellInst -name orientation -value R0 202 | set_attribute -quiet -objects $cellInst -name origin -value { 13.0210 319.4650 } 203 | set_attribute -quiet -objects $cellInst -name status -value placed 204 | 205 | 206 | set cellInst [get_cells { I_RISC_CORE/I_REG_FILE/REG_FILE_D_RAM }] 207 | set_attribute -quiet -objects $cellInst -name orientation -value R0 208 | set_attribute -quiet -objects $cellInst -name origin -value { 242.7540 833.1940 } 209 | set_attribute -quiet -objects $cellInst -name status -value placed 210 | 211 | 212 | set cellInst [get_cells { I_RISC_CORE/I_REG_FILE/REG_FILE_C_RAM }] 213 | set_attribute -quiet -objects $cellInst -name orientation -value R0 214 | set_attribute -quiet -objects $cellInst -name origin -value { 135.1240 833.1940 } 215 | set_attribute -quiet -objects $cellInst -name status -value placed 216 | 217 | 218 | set cellInst [get_cells { I_RISC_CORE/I_REG_FILE/REG_FILE_B_RAM }] 219 | set_attribute -quiet -objects $cellInst -name orientation -value R0 220 | set_attribute -quiet -objects $cellInst -name origin -value { 27.4940 833.1940 } 221 | set_attribute -quiet -objects $cellInst -name status -value placed 222 | 223 | 224 | set cellInst [get_cells { I_RISC_CORE/I_REG_FILE/REG_FILE_A_RAM }] 225 | set_attribute -quiet -objects $cellInst -name orientation -value R0 226 | set_attribute -quiet -objects $cellInst -name origin -value { 350.3840 833.1940 } 227 | set_attribute -quiet -objects $cellInst -name status -value placed 228 | 229 | 230 | set cellInst [get_cells { I_SDRAM_TOP/I_SDRAM_READ_FIFO/SD_FIFO_RAM_1 }] 231 | set_attribute -quiet -objects $cellInst -name orientation -value R0 232 | set_attribute -quiet -objects $cellInst -name origin -value { 516.9950 745.4030 } 233 | set_attribute -quiet -objects $cellInst -name status -value placed 234 | 235 | 236 | set cellInst [get_cells { I_SDRAM_TOP/I_SDRAM_READ_FIFO/SD_FIFO_RAM_0 }] 237 | set_attribute -quiet -objects $cellInst -name orientation -value R0 238 | set_attribute -quiet -objects $cellInst -name origin -value { 669.4560 745.4030 } 239 | set_attribute -quiet -objects $cellInst -name status -value placed 240 | 241 | 242 | set cellInst [get_cells { I_SDRAM_TOP/I_SDRAM_WRITE_FIFO/SD_FIFO_RAM_1 }] 243 | set_attribute -quiet -objects $cellInst -name orientation -value R0 244 | set_attribute -quiet -objects $cellInst -name origin -value { 516.9950 872.8750 } 245 | set_attribute -quiet -objects $cellInst -name status -value placed 246 | 247 | 248 | set cellInst [get_cells { I_SDRAM_TOP/I_SDRAM_WRITE_FIFO/SD_FIFO_RAM_0 }] 249 | set_attribute -quiet -objects $cellInst -name orientation -value R0 250 | set_attribute -quiet -objects $cellInst -name origin -value { 669.4560 872.8750 } 251 | set_attribute -quiet -objects $cellInst -name status -value placed 252 | 253 | 254 | 255 | 256 | --------------------------------------------------------------------------------