├── READEME ├── example ├── 1.jpg ├── 2.jpg ├── chinese-chess.jpg ├── dig-dug1.jpg ├── dig-dug2.jpg ├── donkey-kong1.jpg ├── donkey-kong2.jpg ├── mario-bros.jpg ├── nestress1.jpg ├── nestress2.jpg ├── nestress3.jpg ├── nestress4.jpg ├── pac-man1.jpg ├── pac-man2.jpg ├── pinball1.jpg ├── pinball2.jpg ├── super-mario1.jpg └── super-mario2.jpg └── src ├── CPU2A03.vhd ├── detest.vhd ├── free6502.vhd ├── linebuf.vhd ├── microcode.vhd ├── ppu.vhd ├── ram.vhd ├── rom.vhd ├── spram.vhd ├── sram.vhd ├── vgacore.vhd ├── vgasig.vhd └── vrom.vhd /READEME: -------------------------------------------------------------------------------- 1 | NES emulator based on VHDL version 0.8 2 | 3 | this code is to run under DE2 board and top is detest.VHDL 4 | -------------------------------------------------------------------------------- /example/1.jpg: -------------------------------------------------------------------------------- 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IEEE.std_logic_unsigned.all; 4 | 5 | entity CPU2A03 is 6 | port( 7 | clk : in std_logic; 8 | reset : in std_logic; 9 | irq_in : in std_logic; 10 | nmi_in : in std_logic; 11 | addr : out std_logic_vector(15 downto 0); 12 | data_in : in std_logic_vector(7 downto 0); 13 | data_out : out std_logic_vector(7 downto 0); 14 | we : out std_logic; 15 | rd : out std_logic; 16 | sync : out std_logic 17 | ); 18 | end CPU2A03; 19 | 20 | architecture behav of CPU2A03 is 21 | component core_6502 22 | port (clk :in std_logic; 23 | reset :in std_logic; 24 | irq_in :in std_logic; 25 | nmi_in :in std_logic; 26 | addr_pin :out std_logic_vector (15 downto 0); 27 | din :in std_logic_vector (7 downto 0); 28 | dout :out std_logic_vector (7 downto 0); 29 | dout_oe :out std_logic; 30 | we_pin :out std_logic; 31 | rd_pin :out std_logic; 32 | sync :out std_logic 33 | ); 34 | end component; 35 | 36 | signal dout_oe : std_logic; 37 | begin 38 | 39 | cpu1: core_6502 port map(clk,reset,irq_in,nmi_in,addr,data_in,data_out,dout_oe,we,rd,sync); 40 | 41 | end behav; -------------------------------------------------------------------------------- /src/detest.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_unsigned.all; 4 | 5 | entity detest is 6 | port( 7 | KEY : in std_logic_vector(3 downto 0); 8 | SW : in std_logic_vector(17 downto 0); 9 | HEX0 : out std_logic_vector(6 downto 0); 10 | HEX1 : out std_logic_vector(6 downto 0); 11 | HEX2 : out std_logic_vector(6 downto 0); 12 | HEX3 : out std_logic_vector(6 downto 0); 13 | LEDR : out std_logic_vector(17 downto 0); 14 | LEDG : out std_logic_vector(7 downto 0); 15 | CLOCK_50 : in std_logic; 16 | PS2_CLK : in std_logic; 17 | PS2_DAT : in std_logic; 18 | VGA_BLANK : out std_logic; 19 | VGA_SYNC : out std_logic; 20 | VGA_CLK : out std_logic; 21 | VGA_R : out std_logic_vector(9 downto 0); 22 | VGA_G : out std_logic_vector(9 downto 0); 23 | VGA_B : out std_logic_vector(9 downto 0); 24 | VGA_HS : out std_logic; 25 | VGA_VS : out std_logic 26 | ); 27 | end detest; 28 | 29 | architecture behav of detest is 30 | 31 | component vgacore is 32 | Port ( clk : in std_logic; 33 | reset : in std_logic; 34 | hs : out std_logic; 35 | vs : out std_logic; 36 | r : out std_logic_vector(3 downto 0); 37 | g : out std_logic_vector(3 downto 0); 38 | b : out std_logic_vector(3 downto 0); 39 | clk2 : in std_logic; 40 | sw : in std_logic_vector(17 downto 0); 41 | ledr : out std_logic_vector(17 downto 0); 42 | ledg : out std_logic_vector(7 downto 0); 43 | key : in std_logic_vector(2 downto 0); 44 | addr_reg : out std_logic_vector(15 downto 0) 45 | ); 46 | end component; 47 | 48 | type hexrom_type is array (0 to 15) of std_logic_vector(6 downto 0); 49 | constant hexrom : hexrom_type := ( 50 | "1000000", 51 | "1111001", 52 | "0100100", 53 | "0110000", 54 | "0011001", 55 | "0010010", 56 | "0000010", 57 | "1111000", 58 | "0000000", 59 | "0010000", 60 | "0001000", 61 | "0000011", 62 | "1000110", 63 | "0100001", 64 | "0000110", 65 | "0001110" 66 | ); 67 | 68 | signal sysclk : std_logic; 69 | signal hs_reg : std_logic; 70 | signal vs_reg : std_logic; 71 | signal addr_reg : std_logic_vector(15 downto 0); 72 | 73 | begin 74 | 75 | divclk: process(CLOCK_50,KEY(0)) 76 | begin 77 | if KEY(0)='0' then 78 | sysclk <= '0'; 79 | elsif CLOCK_50'event and CLOCK_50='1' then 80 | sysclk <= not sysclk; 81 | end if; 82 | end process; 83 | 84 | V : vgacore port map(sysclk,KEY(0),hs_reg,vs_reg,VGA_R(9 downto 6),VGA_G(9 downto 6),VGA_B(9 downto 6),CLOCK_50,SW,LEDR,LEDG,KEY(3 downto 1),addr_reg); 85 | VGA_R(5 downto 0)<="000000"; 86 | VGA_G(5 downto 0)<="000000"; 87 | VGA_B(5 downto 0)<="000000"; 88 | VGA_SYNC<='1'; 89 | VGA_CLK<=sysclk; 90 | VGA_BLANK<=hs_reg and vs_reg; 91 | VGA_HS<=hs_reg; 92 | VGA_VS<=vs_reg; 93 | HEX0<=hexrom(conv_integer(addr_reg(3 downto 0))); 94 | HEX1<=hexrom(conv_integer(addr_reg(7 downto 4))); 95 | HEX2<=hexrom(conv_integer(addr_reg(11 downto 8))); 96 | HEX3<=hexrom(conv_integer(addr_reg(15 downto 12))); 97 | 98 | end; -------------------------------------------------------------------------------- /src/free6502.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------- 2 | ---------------------------------------------------------------------------- 3 | -- The Free IP Project 4 | -- VHDL 6502 Core 5 | -- (c) 1999, The Free IP Project and David Kessner 6 | -- 7 | -- 8 | -- FREE IP GENERAL PUBLIC LICENSE 9 | -- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION 10 | -- 11 | -- 1. You may copy and distribute verbatim copies of this core, as long 12 | -- as this file, and the other associated files, remain intact and 13 | -- unmodified. Modifications are outlined below. Also, see the 14 | -- import/export warning above for further restrictions on 15 | -- distribution. 16 | -- 2. You may use this core in any way, be it academic, commercial, or 17 | -- military. Modified or not. 18 | -- 3. Distribution of this core must be free of charge. Charging is 19 | -- allowed only for value added services. Value added services 20 | -- would include copying fees, modifications, customizations, and 21 | -- inclusion in other products. 22 | -- 4. If a modified source code is distributed, the original unmodified 23 | -- source code must also be included (or a link to the Free IP web 24 | -- site). In the modified source code there must be clear 25 | -- identification of the modified version. 26 | -- 5. Visit the Free IP web site for additional information. 27 | -- http://www.free-ip.com 28 | -- 29 | ---------------------------------------------------------------------------- 30 | ---------------------------------------------------------------------------- 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.std_logic_arith.all; 34 | use ieee.std_logic_unsigned.all; 35 | library work; 36 | 37 | package free_6502 is 38 | component core_6502 39 | port (clk :in std_logic; 40 | reset :in std_logic; 41 | irq_in :in std_logic; 42 | nmi_in :in std_logic; 43 | addr_pin :out std_logic_vector (15 downto 0); 44 | din :in std_logic_vector (7 downto 0); 45 | dout :out std_logic_vector (7 downto 0); 46 | dout_oe :out std_logic; 47 | we_pin :out std_logic; 48 | rd_pin :out std_logic; 49 | sync :out std_logic 50 | ); 51 | end component; 52 | 53 | component core_6502_debug 54 | port (clk :in std_logic; 55 | reset :in std_logic; 56 | irq_in :in std_logic; 57 | nmi_in :in std_logic; 58 | addr_pin :out std_logic_vector (15 downto 0); 59 | din :in std_logic_vector (7 downto 0); 60 | dout :out std_logic_vector (7 downto 0); 61 | dout_oe :out std_logic; 62 | we_pin :out std_logic; 63 | rd_pin :out std_logic; 64 | sync :out std_logic; 65 | stack_page :in std_logic_vector (7 downto 0); 66 | reg_a_out :out std_logic_vector (7 downto 0); 67 | reg_x_out :out std_logic_vector (7 downto 0); 68 | reg_y_out :out std_logic_vector (7 downto 0); 69 | reg_sr_out :out std_logic_vector (7 downto 0); 70 | reg_sp_out :out std_logic_vector (7 downto 0); 71 | reg_pc_out :out std_logic_vector (15 downto 0) 72 | ); 73 | end component; 74 | end free_6502; 75 | 76 | ---------------------------------------------------------------------------- 77 | ---------------------------------------------------------------------------- 78 | library ieee; 79 | use ieee.std_logic_1164.all; 80 | use ieee.std_logic_arith.all; 81 | use ieee.std_logic_unsigned.all; 82 | library work; 83 | use work.microcode.all; 84 | use work.free_6502.all; 85 | 86 | 87 | entity core_6502_debug is 88 | port (clk :in std_logic; 89 | reset :in std_logic; 90 | irq_in :in std_logic; 91 | nmi_in :in std_logic; 92 | addr_pin :out std_logic_vector (15 downto 0); 93 | din :in std_logic_vector (7 downto 0); 94 | dout :out std_logic_vector (7 downto 0); 95 | dout_oe :out std_logic; 96 | we_pin :out std_logic; 97 | rd_pin :out std_logic; 98 | sync :out std_logic; 99 | stack_page :in std_logic_vector (7 downto 0); 100 | reg_a_out :out std_logic_vector (7 downto 0); 101 | reg_x_out :out std_logic_vector (7 downto 0); 102 | reg_y_out :out std_logic_vector (7 downto 0); 103 | reg_sr_out :out std_logic_vector (7 downto 0); 104 | reg_sp_out :out std_logic_vector (7 downto 0); 105 | reg_pc_out :out std_logic_vector (15 downto 0) 106 | ); 107 | end core_6502_debug; 108 | 109 | 110 | architecture core_6502_arch_debug of core_6502_debug is 111 | -- Constants 112 | constant reset_opcode :std_logic_vector (7 downto 0) := "00000011"; 113 | constant irq_opcode :std_logic_vector (7 downto 0) := "01000011"; 114 | constant nmi_opcode :std_logic_vector (7 downto 0) := "00110011"; 115 | constant vect_nmi1 :std_logic_vector (15 downto 0) := "1111111111111010"; 116 | constant vect_nmi2 :std_logic_vector (15 downto 0) := "1111111111111011"; 117 | constant vect_reset1 :std_logic_vector (15 downto 0) := "1111111111111100"; 118 | constant vect_reset2 :std_logic_vector (15 downto 0) := "1111111111111101"; 119 | constant vect_irq1 :std_logic_vector (15 downto 0) := "1111111111111110"; 120 | constant vect_irq2 :std_logic_vector (15 downto 0) := "1111111111111111"; 121 | 122 | -- Internal state info 123 | type STATES is (RESET1, RESET2, FETCH, START_IRQ, START_NMI, RUN); 124 | signal state :STATES; 125 | signal step :std_logic_vector (2 downto 0); 126 | 127 | -- registered inputs 128 | signal nmi_reg1 :std_logic; 129 | signal nmi_reg2 :std_logic; 130 | signal irq_reg :std_logic; 131 | signal data_in :std_logic_vector (7 downto 0); 132 | 133 | -- Microcode ROM outputs 134 | signal done :MCT_DONE; 135 | signal addr_op :MCT_ADDR_OP; 136 | signal din_le :MCT_DIN_LE; 137 | signal rd_en :MCT_RD_EN; 138 | signal dout_op :MCT_DOUT_OP; 139 | signal dint1_op :MCT_DINT1_OP; 140 | signal dint2_op :MCT_DINT2_OP; 141 | signal dint3_op :MCT_DINT3_OP; 142 | signal pc_op :MCT_PC_OP; 143 | signal sp_op :MCT_SP_OP; 144 | signal alu1 :MCT_ALU1; 145 | signal alu2 :MCT_ALU2; 146 | signal alu_op :MCT_ALU_OP; 147 | signal a_le :MCT_A_LE; 148 | signal x_le :MCT_X_LE; 149 | signal y_le :MCT_Y_LE; 150 | signal flag_op :MCT_FLAG_OP; 151 | 152 | -- Internal registers 153 | signal a_reg :std_logic_vector (7 downto 0); 154 | signal x_reg :std_logic_vector (7 downto 0); 155 | signal y_reg :std_logic_vector (7 downto 0); 156 | signal dint1 :std_logic_vector (7 downto 0); 157 | signal dint2 :std_logic_vector (7 downto 0); 158 | signal dint3 :std_logic_vector (7 downto 0); 159 | signal opcode_reg :std_logic_vector (7 downto 0); 160 | signal sp :std_logic_vector (7 downto 0); 161 | signal pc :std_logic_vector (15 downto 0); 162 | signal n_flag :std_logic; 163 | signal v_flag :std_logic; 164 | signal b_flag :std_logic; 165 | signal d_flag :std_logic; 166 | signal i_flag :std_logic; 167 | signal z_flag :std_logic; 168 | signal c_flag :std_logic; 169 | 170 | -- Combinotorial signals 171 | signal opcode :std_logic_vector (7 downto 0); 172 | signal alu_in1 :std_logic_vector (8 downto 0); 173 | signal alu_in2 :std_logic_vector (8 downto 0); 174 | signal alu_out :std_logic_vector (8 downto 0); 175 | 176 | signal alu_add :std_logic_vector (8 downto 0); 177 | signal alu_add_in2 :std_logic_vector (8 downto 0); 178 | signal alu_add_cin :std_logic; 179 | 180 | signal addr_out_d :std_logic_vector(15 downto 0); 181 | 182 | -- Misc signals 183 | signal first_run :std_logic; 184 | signal fetch_d :std_logic; 185 | signal data_out :std_logic_vector (7 downto 0); 186 | signal data_oe :std_logic; 187 | signal addr_out :std_logic_vector (15 downto 0); 188 | signal we_out :std_logic; 189 | signal nmi_event :std_logic; 190 | 191 | begin 192 | -- Debug outputs 193 | reg_a_out <= a_reg; 194 | reg_x_out <= x_reg; 195 | reg_y_out <= y_reg; 196 | reg_sr_out <= n_flag & v_flag & '1' & b_flag & d_flag 197 | & i_flag & z_flag & c_flag; 198 | reg_sp_out <= sp; 199 | reg_pc_out <= pc; 200 | 201 | 202 | -- The sync output 203 | process (clk, reset) 204 | begin 205 | if reset='1' then 206 | sync <= '0'; 207 | elsif clk'event and clk='1' then 208 | case state is 209 | when RESET1 => sync <= '0'; 210 | when RESET2 => sync <= '0'; 211 | when FETCH => sync <= '0'; 212 | when START_IRQ => sync <= '0'; 213 | when START_NMI => sync <= '0'; 214 | when RUN => 215 | if done=MC_DONE then 216 | if nmi_event='1' then 217 | sync <= '0'; 218 | elsif i_flag='0' and irq_reg='1' then 219 | sync <= '0'; 220 | else 221 | sync <= '1'; 222 | end if; 223 | end if; 224 | when others => sync <= '0'; 225 | end case; 226 | end if; 227 | end process; 228 | 229 | 230 | -- The main state machine 231 | process (clk, reset) 232 | begin 233 | if reset='1' then 234 | state <= RESET1; 235 | elsif clk'event and clk='1' then 236 | case state is 237 | when RESET1 => state <= RESET2; 238 | when RESET2 => state <= RUN; 239 | when FETCH => state <= RUN; 240 | when START_IRQ => state <= RUN; 241 | when START_NMI => state <= RUN; 242 | when RUN => 243 | if done=MC_DONE then 244 | if nmi_event='1' then 245 | state <= START_NMI; 246 | elsif i_flag='0' and irq_reg='1' then 247 | state <= START_IRQ; 248 | else 249 | state <= FETCH; 250 | end if; 251 | end if; 252 | when others => state <= RESET1; 253 | end case; 254 | end if; 255 | end process; 256 | 257 | 258 | -- The microcode step counter 259 | process (clk, reset) 260 | begin 261 | if reset='1' then 262 | step<="000"; 263 | elsif clk'event and clk='1' then 264 | case state is 265 | when RESET1 => step <= "000"; 266 | when RESET2 => step <= "000"; 267 | when FETCH => step <= "000"; 268 | when START_IRQ => step <= "000"; 269 | when START_NMI => step <= "000"; 270 | when RUN => step <= step + 1; 271 | when others => step <= step + 1; 272 | end case; 273 | end if; 274 | end process; 275 | 276 | 277 | -- The input registers 278 | process (clk, reset) 279 | begin 280 | if reset='1' then 281 | data_in <= "00000000"; 282 | elsif clk'event and clk='1' then 283 | if din_le=MC_EN or state=FETCH then 284 | data_in <= din; 285 | end if; 286 | end if; 287 | end process; 288 | 289 | process (clk, reset) 290 | begin 291 | if reset='1' then 292 | irq_reg <= '0'; 293 | elsif clk'event and clk='1' then 294 | irq_reg <= irq_in; 295 | end if; 296 | end process; 297 | 298 | process (clk, reset) 299 | begin 300 | if reset='1' then 301 | nmi_reg1 <= '0'; 302 | nmi_reg2 <= '0'; 303 | elsif clk'event and clk='1' then 304 | nmi_reg1 <= nmi_in; 305 | nmi_reg2 <= nmi_reg1; 306 | end if; 307 | end process; 308 | 309 | -- The NMI __RISING_EDGE__ detect 310 | process (clk, reset) 311 | begin 312 | if reset='1' then 313 | nmi_event <= '0'; 314 | elsif clk'event and clk='1' then 315 | if nmi_reg1='1' and nmi_reg2='0' then 316 | nmi_event <= '1'; 317 | elsif state=START_NMI then 318 | nmi_event <= '0'; 319 | end if; 320 | end if; 321 | end process; 322 | 323 | 324 | -- The first run signal. Active on the first run clock 325 | process (clk, reset) 326 | begin 327 | if reset='1' then 328 | first_run <= '0'; 329 | elsif clk'event and clk='1' then 330 | case state is 331 | when RESET2 => first_run <= '0'; 332 | when FETCH => first_run <= '1'; 333 | when START_IRQ => first_run <= '0'; -- was '1' -- bjs 09/05/99 334 | when START_NMI => first_run <= '0'; -- was '1' -- bjs 09/05/99 335 | when RUN => first_run <= '0'; 336 | when others => first_run <= '0'; 337 | end case; 338 | end if; 339 | end process; 340 | 341 | 342 | -- The fetch_d signal. Active one clock after a fetch cycle 343 | process (clk, reset) 344 | begin 345 | if reset='1' then 346 | fetch_d <= '0'; 347 | elsif clk'event and clk='1' then 348 | if state=FETCH then 349 | fetch_d <= '1'; 350 | else 351 | fetch_d <= '0'; 352 | end if; 353 | end if; 354 | end process; 355 | 356 | 357 | -- The opcode register and opcode decode logic 358 | process (clk, reset) 359 | begin 360 | if reset='1' then 361 | opcode_reg <= "00000000"; 362 | elsif clk'event and clk='1' then 363 | case state is 364 | when RESET2 => opcode_reg <= reset_opcode; 365 | when START_IRQ => opcode_reg <= irq_opcode; 366 | when START_NMI => opcode_reg <= nmi_opcode; 367 | 368 | when RUN => 369 | if first_run='1' then 370 | opcode_reg <=data_in; 371 | end if; 372 | 373 | when others => 374 | -- 375 | end case; 376 | end if; 377 | end process; 378 | 379 | opcode <= data_in when fetch_d='1' else opcode_reg; 380 | 381 | 382 | -- The Microcode ROM 383 | MC_ROM0: mc_rom port map 384 | (opcode, step, done, addr_op, din_le, rd_en, dout_op, 385 | dint1_op, dint2_op, dint3_op, pc_op, sp_op, alu1, alu2, 386 | alu_op, a_le, x_le, y_le, flag_op); 387 | 388 | -- The program counter 389 | process (clk, reset) 390 | variable pc_add : std_logic_vector(15 downto 0); 391 | variable pc_inc : std_logic_vector(15 downto 0); 392 | begin 393 | if reset='1' then 394 | pc <= "0000000000000000"; 395 | elsif clk'event and clk='1' then 396 | -- Sept 23, 1999 -- Fixed by David Kessner, reported by Bill Seiler 397 | -- was: pc_add <= pc + data_in 398 | -- now: pc_add <= pc + a sign extended version of data_in 399 | pc_add := pc + 400 | (data_in(7) & data_in(7) & data_in(7) & data_in(7) & 401 | data_in(7) & data_in(7) & data_in(7) & data_in(7) & 402 | data_in); 403 | pc_inc := pc + '1'; 404 | if state=fetch then 405 | pc <= pc_inc; 406 | else 407 | case pc_op is 408 | when MC_NOP => -- Do nothing 409 | when MC_INC => pc <= pc_inc; 410 | when MC_BCC => if c_flag='0' then pc<=pc_add; end if; 411 | when MC_BCS => if c_flag='1' then pc<=pc_add; end if; 412 | when MC_BEQ => if z_flag='1' then pc<=pc_add; end if; 413 | when MC_BNE => if z_flag='0' then pc<=pc_add; end if; 414 | when MC_BMI => if n_flag='1' then pc<=pc_add; end if; 415 | when MC_BPL => if n_flag='0' then pc<=pc_add; end if; 416 | when MC_BVC => if v_flag='0' then pc<=pc_add; end if; 417 | when MC_BVS => if v_flag='1' then pc<=pc_add; end if; 418 | when MC_SPLIT => pc <= data_in & dint1; 419 | when others => -- Do nothing 420 | end case; 421 | end if; 422 | end if; 423 | end process; 424 | 425 | 426 | -- Data output logic 427 | process (clk, reset) 428 | begin 429 | if reset='1' then 430 | data_out <= "00000000"; 431 | data_oe <= '0'; 432 | we_out <= '0'; 433 | elsif clk'event and clk='1' then 434 | case dout_op is 435 | when MC_NOP => data_oe <= '0'; we_out<='0'; data_out <= dint3; 436 | when MC_DINT3 => data_oe <= '1'; we_out<='1'; data_out <= dint3; 437 | when MC_PCH => data_oe <= '1'; we_out<='1'; data_out <= pc(15 downto 8); 438 | when MC_PCL => data_oe <= '1'; we_out<='1'; data_out <= pc (7 downto 0); 439 | when MC_P_REG => data_oe <= '1'; we_out<='1'; 440 | data_out <= n_flag & v_flag & '1' & b_flag & 441 | d_flag & i_flag & z_flag & c_flag; 442 | when MC_A_REG => data_oe <= '1'; we_out<='1'; data_out <= a_reg; 443 | when MC_X_REG => data_oe <= '1'; we_out<='1'; data_out <= x_reg; 444 | when MC_Y_REG => data_oe <= '1'; we_out<='1'; data_out <= y_reg; 445 | when others => data_oe <= '0'; we_out<='0'; data_out <= dint3; 446 | end case; 447 | end if; 448 | end process; 449 | 450 | dout <= data_out; 451 | dout_oe <= data_oe; 452 | 453 | we_pin <= we_out; 454 | 455 | 456 | -- Generate the rd_pin signals 457 | process (reset, clk) 458 | begin 459 | if reset='1' then 460 | rd_pin <= '0'; 461 | elsif clk'event and clk='1' then 462 | case state is 463 | when RESET1 => rd_pin <= '0'; 464 | when RESET2 => rd_pin <= '0'; 465 | when FETCH => rd_pin <= '1'; 466 | when START_IRQ => rd_pin <= '0'; 467 | when START_NMI => rd_pin <= '0'; 468 | when RUN => 469 | if done=MC_DONE then 470 | if nmi_event='1' then 471 | rd_pin <= '0'; 472 | elsif i_flag='0' and irq_reg='1' then 473 | rd_pin <= '0'; 474 | else 475 | rd_pin <= '1'; 476 | end if; 477 | elsif rd_en=MC_READ then 478 | rd_pin <= '1'; 479 | else 480 | rd_pin <= '0'; 481 | end if; 482 | when others => rd_pin <= '0'; 483 | end case; 484 | end if; 485 | end process; 486 | 487 | ----------------------------------------------------------------------------- 488 | -- Revised address output block 489 | ------------------------------- 490 | -- These revisons to the address output block are intended to improve 491 | -- synthesis results for both area and speed. They intended to 492 | -- accomplish the following: 493 | -- - Make the use of a single adder very clear to the synthesis tool. 494 | -- - Move all decoding and muxing in front of the adder. This allows 495 | -- the synthesis more flexibility in optimizing an balancing propagation 496 | -- paths. 497 | -- Ed Beers (sreeb@beers.nu) 9/14/99 498 | ----------------------------------------------------------------------------- 499 | 500 | -- The address output logic 501 | process (clk, reset) 502 | variable addr_add_1 :std_logic_vector(15 downto 0); 503 | variable addr_add_2 :std_logic_vector(7 downto 0); 504 | variable addr_add_cin :std_logic; 505 | 506 | variable addr_out_low :std_logic_vector (8 downto 0); 507 | variable addr_out_high :std_logic_vector (7 downto 0); 508 | variable eight_bit_flag :std_logic; 509 | begin 510 | if reset='1' then 511 | addr_out <= (others=>'0'); 512 | elsif clk'event and clk='1' then 513 | 514 | -- default for adder 515 | addr_add_2 := (others=>'0'); 516 | addr_add_cin := '0'; 517 | eight_bit_flag := '0'; 518 | 519 | if done=MC_DONE then 520 | --addr_out <= pc; 521 | addr_add_1 := pc; 522 | elsif state=FETCH then 523 | --addr_out <= pc + 1; 524 | addr_add_1 := pc; 525 | addr_add_cin := '1'; 526 | else 527 | case addr_op is 528 | when MC_NOP => 529 | --addr_out <= pc; 530 | addr_add_1 := pc; 531 | when MC_PC_P => 532 | --addr_out <= pc + 1; 533 | addr_add_1 := pc; 534 | addr_add_cin := '1'; 535 | when MC_SPLIT => 536 | --addr_out <= data_in & dint1; 537 | addr_add_1 := data_in & dint1; 538 | when MC_SPLIT_P => 539 | --addr_out <= (data_in & dint1) + 1; 540 | addr_add_1 := data_in & dint1; 541 | addr_add_cin := '1'; 542 | when MC_SPLIT_X => 543 | --addr_out <= (data_in & dint1) + x_reg; 544 | addr_add_1 := data_in & dint1; 545 | addr_add_2 := x_reg; 546 | when MC_SPLIT_Y => 547 | --addr_out <= (data_in & dint1) + y_reg; 548 | addr_add_1 := data_in & dint1; 549 | addr_add_2 := y_reg; 550 | when MC_DIN_Z => 551 | --addr_out <= ("00000000" & data_in); 552 | addr_add_1 := "00000000" & data_in; 553 | when MC_DIN_ZP => 554 | --addr_out <= ("00000000" & data_in) + 1; 555 | addr_add_1 := "00000000" & data_in; 556 | addr_add_cin := '1'; 557 | when MC_DIN_ZX => 558 | --addr_out <= ("00000000" & data_in) + x_reg; 559 | addr_add_1 := "00000000" & data_in; 560 | addr_add_2 := x_reg; 561 | eight_bit_flag := '1'; 562 | when MC_DIN_ZXP => 563 | --addr_out <= ("00000000" & data_in) + x_reg + 1; 564 | addr_add_1 := "00000000" & data_in; 565 | addr_add_2 := x_reg; 566 | addr_add_cin := '1'; 567 | eight_bit_flag := '1'; 568 | when MC_DIN_ZY => 569 | --addr_out <= ("00000000" & data_in) + y_reg; 570 | addr_add_1 := "00000000" & data_in; 571 | addr_add_2 := y_reg; 572 | eight_bit_flag := '1'; 573 | when MC_DINT16 => 574 | --addr_out <= dint2 & dint1; 575 | addr_add_1 := dint2 & dint1; 576 | when MC_DINT16_X => 577 | --addr_out <= dint2 & dint1 + x_reg; 578 | addr_add_1 := dint2 & dint1; 579 | addr_add_2 := x_reg; 580 | when MC_DINT1_Z => 581 | --addr_out_d <= ("00000000" & dint1); 582 | addr_add_1 := ("00000000" & dint1); 583 | when MC_DINT1_ZX => 584 | --addr_out <= ("00000000" & dint1) + x_reg; 585 | addr_add_1 := "00000000" & dint1; 586 | addr_add_2 := x_reg; 587 | when MC_SP => 588 | --addr_out <= stack_page & sp; 589 | addr_add_1 := stack_page & sp; 590 | when MC_V_NMI1 => 591 | --addr_out <= vect_nmi1; 592 | addr_add_1 := vect_nmi1; 593 | when MC_V_NMI2 => 594 | --addr_out <= vect_nmi2; 595 | addr_add_1 := vect_nmi2; 596 | when MC_V_RESET1 => 597 | --addr_out <= vect_reset1; 598 | addr_add_1 := vect_reset1; 599 | when MC_V_RESET2 => 600 | --addr_out <= vect_reset2; 601 | addr_add_1 := vect_reset2; 602 | when MC_V_IRQ1 => 603 | --addr_out <= vect_irq1; 604 | addr_add_1 := vect_irq1; 605 | when MC_V_IRQ2 => 606 | --addr_out <= vect_irq2; 607 | addr_add_1 := vect_irq2; 608 | when others => 609 | --addr_out <= pc; 610 | addr_add_1 := pc; 611 | end case; 612 | end if; 613 | 614 | --addr_out <= addr_add_1 + addr_add_2 + addr_add_cin; 615 | addr_out_low := ("0" & addr_add_1(7 downto 0)) + ("0" & addr_add_2) + addr_add_cin; 616 | addr_out_high := addr_add_1(15 downto 8) + (addr_out_low(8) and not eight_bit_flag); 617 | addr_out <= addr_out_high(7 downto 0) & addr_out_low (7 downto 0); 618 | 619 | end if; 620 | end process; 621 | 622 | addr_pin <= addr_out; 623 | 624 | 625 | -- The DINT registers 626 | process (clk, reset) 627 | begin 628 | if reset='1' then 629 | dint1 <= "00000000"; 630 | elsif clk'event and clk='1' then 631 | if dint1_op=MC_DIN then 632 | dint1 <= data_in; 633 | end if; 634 | end if; 635 | end process; 636 | 637 | process (clk, reset) 638 | begin 639 | if reset='1' then 640 | dint2 <= "00000000"; 641 | elsif clk'event and clk='1' then 642 | if dint2_op=MC_DIN then 643 | dint2 <= data_in; 644 | end if; 645 | end if; 646 | end process; 647 | 648 | process (clk, reset) 649 | begin 650 | if reset='1' then 651 | dint3 <= "00000000"; 652 | elsif clk'event and clk='1' then 653 | if dint3_op=MC_ALU then 654 | dint3 <= alu_out (7 downto 0); 655 | end if; 656 | end if; 657 | end process; 658 | 659 | 660 | -- The stack pointer 661 | process (clk, reset) 662 | begin 663 | if reset='1' then 664 | sp <= "11111111"; 665 | elsif clk'event and clk='1' then 666 | case sp_op is 667 | when MC_NOP => -- Do nothing 668 | when MC_PUSH => sp <= sp - 1; 669 | when MC_POP => sp <= sp + 1; 670 | when MC_X_REG => sp <= x_reg; 671 | when others => -- Do nothing 672 | end case; 673 | end if; 674 | end process; 675 | 676 | 677 | -- The registers 678 | process (clk, reset) 679 | begin 680 | if reset='1' then 681 | a_reg <= "00000000"; 682 | elsif clk'event and clk='1' then 683 | if a_le=MC_LE then 684 | a_reg <= alu_out (7 downto 0); 685 | end if; 686 | end if; 687 | end process; 688 | 689 | process (clk, reset) 690 | begin 691 | if reset='1' then 692 | x_reg <= "00000000"; 693 | elsif clk'event and clk='1' then 694 | if x_le=MC_LE then 695 | x_reg <= alu_out (7 downto 0); 696 | end if; 697 | end if; 698 | end process; 699 | 700 | process (clk, reset) 701 | begin 702 | if reset='1' then 703 | y_reg <= "00000000"; 704 | elsif clk'event and clk='1' then 705 | if y_le=MC_LE then 706 | y_reg <= alu_out (7 downto 0); 707 | end if; 708 | end if; 709 | end process; 710 | 711 | 712 | -- The ALU input muxes 713 | process(a_reg, alu1, data_in, x_reg, y_reg) 714 | begin -- process 715 | case alu1 is 716 | when MC_A_REG => alu_in1 <= ("0" & a_reg); 717 | when MC_x_REG => alu_in1 <= ("0" & x_reg); 718 | when MC_Y_REG => alu_in1 <= ("0" & y_reg); 719 | when others => alu_in1 <= ("0" & data_in); 720 | end case; 721 | end process; 722 | 723 | process (alu2, data_in, sp) 724 | begin -- process 725 | case alu2 is 726 | when MC_ONE => alu_in2 <= "000000001"; 727 | when MC_SP_REG => alu_in2 <= ("0" & sp); 728 | when others => alu_in2 <= ("0" & data_in); 729 | end case; 730 | end process; 731 | 732 | -- The ALU adder 733 | alu_add <= alu_in1 + alu_add_in2 + alu_add_cin; 734 | 735 | -- The ALU itself This is purely combinatorial logic 736 | process (alu_add, alu_in1, alu_in2, alu_op, c_flag) 737 | begin 738 | -- default for alu_add inputs 739 | alu_add_in2 <= alu_in2; 740 | alu_add_cin <= c_flag; 741 | 742 | case alu_op is 743 | when MC_PASS1 => alu_out <= alu_in1; 744 | when MC_PASS2 => alu_out <= alu_in2; 745 | when MC_ADD => 746 | --alu_out <= alu_in1 + alu_in2; 747 | alu_add_in2 <= alu_in2; 748 | alu_add_cin <= '0'; 749 | alu_out <= alu_add; 750 | when MC_ADDC => 751 | --alu_out <= alu_in1 + alu_in2 + ("00000000" & c_flag); 752 | alu_add_in2 <= alu_in2; 753 | alu_add_cin <= c_flag; 754 | alu_out <= alu_add; 755 | when MC_SUB => 756 | --alu_out <= alu_in1 - alu_in2; 757 | alu_add_in2 <= not alu_in2; 758 | alu_add_cin <= '1'; 759 | alu_out <= (not alu_add(8)) & alu_add(7 downto 0); 760 | when MC_SUBB => 761 | --alu_out <= alu_in1 - alu_in2 - ("00000000" & c_flag); 762 | alu_add_in2 <= not alu_in2; 763 | alu_add_cin <= c_flag; 764 | alu_out <= (not alu_add(8)) & alu_add(7 downto 0); 765 | when MC_BIT_AND => alu_out <= alu_in1 and alu_in2; 766 | when MC_BIT_OR => alu_out <= alu_in1 or alu_in2; 767 | when MC_BIT_XOR => alu_out <= alu_in1 xor alu_in2; 768 | when MC_BIT_ASL => alu_out <= alu_in1(7 downto 0) & "0"; 769 | when MC_BIT_LSR => alu_out <= alu_in1(0) & "0" & alu_in1(7 downto 1); 770 | when MC_BIT_ROL => alu_out <= alu_in1(7 downto 0) & c_flag; 771 | when MC_BIT_ROR => alu_out <= alu_in1(0) & c_flag & alu_in1(7 downto 1); 772 | when others => alu_out <= alu_in1; 773 | end case; 774 | end process; 775 | 776 | 777 | -- The flag stuff 778 | process (reset, clk) 779 | begin 780 | if reset='1' then 781 | n_flag <= '0'; 782 | elsif clk'event and clk='1' then 783 | case flag_op is 784 | when MC_NOP => -- Do nothing 785 | when MC_NVZC => n_flag <= alu_out(7); 786 | when MC_NZ => n_flag <= alu_out(7); 787 | when MC_NZC => n_flag <= alu_out(7); 788 | when MC_BIT => n_flag <= alu_out(7); 789 | when MC_DIN => n_flag <= data_in(7); 790 | when others => -- Do nothing 791 | end case; 792 | end if; 793 | end process; 794 | 795 | process (reset, clk) 796 | begin 797 | if reset='1' then 798 | v_flag <= '0'; 799 | elsif clk'event and clk='1' then 800 | case flag_op is 801 | when MC_NOP => -- Do nothing 802 | when MC_NVZC => 803 | if alu_op=MC_ADD or alu_op=MC_ADDC then 804 | if alu_in1(7)=alu_in2(7) and alu_in1(7)/=alu_add(7) then 805 | v_flag <= '1'; 806 | else 807 | v_flag <= '0'; 808 | end if; 809 | elsif alu_op=MC_SUB or alu_op=MC_SUBB then 810 | if alu_in1(7)/=alu_in2(7) and alu_in1(7)/=alu_add(7)then 811 | v_flag <= '1'; 812 | else 813 | v_flag <= '0'; 814 | end if; 815 | end if; 816 | when MC_CLEARV => v_flag <= '0'; 817 | when MC_DIN => v_flag <= data_in(6); 818 | when MC_BIT => v_flag <= data_in(6); 819 | when others => -- Do nothing 820 | end case; 821 | end if; 822 | end process; 823 | 824 | 825 | process (reset, clk) 826 | begin 827 | if reset='1' then 828 | b_flag <= '0'; 829 | elsif clk'event and clk='1' then 830 | case flag_op is 831 | when MC_NOP => -- Do nothing 832 | when MC_SETB => b_flag <= '1'; 833 | when MC_DIN => b_flag <= data_in(4); 834 | when others => -- Do nothing 835 | end case; 836 | end if; 837 | end process; 838 | 839 | process (reset, clk) 840 | begin 841 | if reset='1' then 842 | d_flag <= '0'; 843 | elsif clk'event and clk='1' then 844 | case flag_op is 845 | when MC_NOP => -- Do nothing 846 | when MC_CLEARD => d_flag <= '0'; 847 | when MC_DIN => d_flag <= data_in(3); 848 | when MC_SETD => d_flag <= '1'; 849 | when others => -- Do nothing 850 | end case; 851 | end if; 852 | end process; 853 | 854 | process (reset, clk) 855 | begin 856 | if reset='1' then 857 | i_flag <= '1'; 858 | elsif clk'event and clk='1' then 859 | case flag_op is 860 | when MC_NOP => -- Do nothing 861 | when MC_SETI => i_flag <= '1'; 862 | when MC_CLEARI => i_flag <= '0'; 863 | when MC_DIN => i_flag <= data_in(2); 864 | when others => -- Do nothing 865 | end case; 866 | end if; 867 | end process; 868 | 869 | process (reset, clk) 870 | begin 871 | if reset='1' then 872 | z_flag <= '1'; 873 | elsif clk'event and clk='1' then 874 | case flag_op is 875 | when MC_NOP => -- Do nothing 876 | when MC_NVZC => 877 | if alu_out(7 downto 0)="00000000" then 878 | z_flag <='1'; 879 | else 880 | z_flag <= '0'; 881 | end if; 882 | when MC_NZ => 883 | if alu_out(7 downto 0)="00000000" then 884 | z_flag <='1'; 885 | else 886 | z_flag <= '0'; 887 | end if; 888 | when MC_NZC => 889 | if alu_out(7 downto 0)="00000000" then 890 | z_flag <='1'; 891 | else 892 | z_flag <='0'; 893 | end if; 894 | when MC_BIT => 895 | if alu_out(7 downto 0)="00000000" then 896 | z_flag <='1'; 897 | else 898 | z_flag <='0'; 899 | end if; 900 | when MC_DIN => z_flag <= data_in(1); 901 | when others => -- Do nothing 902 | end case; 903 | end if; 904 | end process; 905 | 906 | process (reset, clk) 907 | begin 908 | if reset='1' then 909 | c_flag <= '0'; 910 | elsif clk'event and clk='1' then 911 | case flag_op is 912 | when MC_NOP => -- Do nothing 913 | when MC_NVZC => c_flag <= alu_out(8); 914 | when MC_NZC => c_flag <= alu_out(8); 915 | when MC_CLEARC => c_flag <= '0'; 916 | when MC_DIN => c_flag <= data_in(0); 917 | when MC_SETC => c_flag <= '1'; 918 | when others => -- Do nothing 919 | end case; 920 | end if; 921 | end process; 922 | 923 | end core_6502_arch_debug; 924 | 925 | 926 | ---------------------------------------------------------------------------- 927 | ---------------------------------------------------------------------------- 928 | library ieee; 929 | use ieee.std_logic_1164.all; 930 | use ieee.std_logic_arith.all; 931 | use ieee.std_logic_unsigned.all; 932 | library work; 933 | use work.microcode.all; 934 | use work.free_6502.all; 935 | 936 | 937 | entity core_6502 is 938 | port (clk :in std_logic; 939 | reset :in std_logic; 940 | irq_in :in std_logic; 941 | nmi_in :in std_logic; 942 | addr_pin :out std_logic_vector (15 downto 0); 943 | din :in std_logic_vector (7 downto 0); 944 | dout :out std_logic_vector (7 downto 0); 945 | dout_oe :out std_logic; 946 | we_pin :out std_logic; 947 | rd_pin :out std_logic; 948 | sync :out std_logic 949 | ); 950 | end core_6502; 951 | 952 | 953 | architecture arch_core_6502 of core_6502 is 954 | signal stack_page :std_logic_vector (7 downto 0); 955 | signal reg_a_out :std_logic_vector (7 downto 0); 956 | signal reg_x_out :std_logic_vector (7 downto 0); 957 | signal reg_y_out :std_logic_vector (7 downto 0); 958 | signal reg_sr_out :std_logic_vector (7 downto 0); 959 | signal reg_sp_out :std_logic_vector (7 downto 0); 960 | signal reg_pc_out :std_logic_vector (15 downto 0); 961 | begin 962 | stack_page <= "00000001"; 963 | 964 | U6502: core_6502_debug port map 965 | (clk, reset, irq_in, nmi_in, addr_pin, din, dout, dout_oe, we_pin, 966 | rd_pin, sync, stack_page, reg_a_out, reg_x_out, reg_y_out, 967 | reg_sr_out, reg_sp_out, reg_pc_out); 968 | 969 | end arch_core_6502; 970 | 971 | 972 | ---------------------------------------------------------------------------- 973 | ---------------------------------------------------------------------------- 974 | 975 | -------------------------------------------------------------------------------- /src/linebuf.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.std_logic_unsigned.all; 4 | 5 | entity linebuf is 6 | port ( 7 | address : in std_logic_vector(9 downto 0); 8 | inclock : in std_logic; 9 | we : in std_logic; 10 | data : in std_logic_vector(3 downto 0); 11 | q : out std_logic_vector(3 downto 0) 12 | ); 13 | end linebuf; 14 | 15 | architecture RTL of linebuf is 16 | type Mem is array (0 to 255) of std_logic_vector(3 downto 0); 17 | begin 18 | 19 | process (inclock) 20 | variable iMem : Mem; 21 | begin 22 | if inclock'event and inclock ='1' then 23 | if address<255 and we='0' then 24 | iMem(conv_integer(address)) := data; 25 | end if; 26 | if address<512 then 27 | q <= iMem(conv_integer(Address(8 downto 1))); 28 | else 29 | q<="0000"; 30 | end if; 31 | end if; 32 | end process; 33 | 34 | end RTL; 35 | -------------------------------------------------------------------------------- /src/ppu.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.std_logic_unsigned.all; 4 | 5 | entity ppu is 6 | port ( 7 | clk : in std_logic; 8 | reset : in std_logic; 9 | vx : in std_logic_vector(9 downto 0); 10 | vy : in std_logic_vector(9 downto 0); 11 | r_out : out std_logic_vector(3 downto 0); 12 | g_out : out std_logic_vector(3 downto 0); 13 | b_out : out std_logic_vector(3 downto 0); 14 | clk2 : in std_logic; 15 | sw : in std_logic_vector(17 downto 0); 16 | ledr : out std_logic_vector(17 downto 0); 17 | ledg : out std_logic_vector(7 downto 0); 18 | key : in std_logic_vector(2 downto 0); 19 | addr_pass : out std_logic_vector(15 downto 0) 20 | ); 21 | end ppu; 22 | 23 | architecture behav of ppu is 24 | 25 | --define the type 26 | type color_rom_type is array (0 to 63) of std_logic_vector(3 downto 0); 27 | type palette_table_type is array(0 to 31) of std_logic_vector(5 downto 0); 28 | type line_type is array(0 to 255) of std_logic_vector(3 downto 0); 29 | type line_type2 is array(0 to 511) of std_logic_vector(3 downto 0); 30 | type line_bg_type is array(0 to 255) of std_logic; 31 | type name_mirror_type is array(0 to 3) of std_logic; 32 | 33 | --nes color map 34 | constant r_color : color_rom_type := ( 35 | X"7",X"2",X"2",X"6", 36 | X"9",X"B",X"A",X"7", 37 | X"4",X"3",X"3",X"3", 38 | X"3",X"0",X"0",X"0", 39 | X"B",X"4",X"4",X"9", 40 | X"D",X"D",X"E",X"C", 41 | X"8",X"5",X"4",X"4", 42 | X"4",X"0",X"0",X"0", 43 | X"F",X"6",X"5",X"A", 44 | X"F",X"F",X"F",X"F", 45 | X"E",X"9",X"7",X"7", 46 | X"6",X"6",X"0",X"0", 47 | X"F",X"9",X"A",X"C", 48 | X"E",X"F",X"F",X"F", 49 | X"F",X"C",X"A",X"A", 50 | X"A",X"A",X"0",X"0" 51 | ); 52 | 53 | constant g_color : color_rom_type := ( 54 | X"7",X"0",X"0",X"1", 55 | X"2",X"1",X"3",X"4", 56 | X"5",X"6",X"6",X"6", 57 | X"5",X"0",X"0",X"0", 58 | X"B",X"6",X"4",X"4", 59 | X"4",X"4",X"5",X"7", 60 | X"8",X"A",X"A",X"A", 61 | X"9",X"0",X"0",X"0", 62 | X"F",X"A",X"8",X"7", 63 | X"6",X"6",X"7",X"A", 64 | X"D",X"E",X"F",X"E", 65 | X"D",X"6",X"0",X"0", 66 | X"F",X"D",X"B",X"B", 67 | X"B",X"B",X"C",X"D", 68 | X"F",X"F",X"F",X"F", 69 | X"F",X"A",X"0",X"0" 70 | ); 71 | 72 | constant b_color : color_rom_type := ( 73 | X"7",X"B",X"B",X"A", 74 | X"7",X"3",X"0",X"0", 75 | X"0",X"0",X"0",X"4", 76 | X"8",X"0",X"0",X"0", 77 | X"B",X"F",X"F",X"F", 78 | X"C",X"6",X"0",X"0", 79 | X"0",X"0",X"1",X"6", 80 | X"C",X"0",X"0",X"0", 81 | X"F",X"F",X"F",X"F", 82 | X"F",X"B",X"3",X"0", 83 | X"2",X"0",X"4",X"9", 84 | X"E",X"6",X"0",X"0", 85 | X"F",X"F",X"F",X"F", 86 | X"F",X"E",X"B",X"A", 87 | X"9",X"8",X"A",X"C", 88 | X"F",X"A",X"0",X"0" 89 | ); 90 | 91 | --define the component 92 | component vrom is 93 | PORT 94 | ( 95 | address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 96 | address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 97 | clock : IN STD_LOGIC ; 98 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 99 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 100 | ); 101 | end component; 102 | 103 | component rom is 104 | PORT 105 | ( 106 | address : IN STD_LOGIC_VECTOR (14 DOWNTO 0); 107 | clock : IN STD_LOGIC ; 108 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 109 | ); 110 | end component; 111 | 112 | component ram is 113 | PORT 114 | ( 115 | address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 116 | address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 117 | clock : IN STD_LOGIC ; 118 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 119 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 120 | wren_a : IN STD_LOGIC; 121 | wren_b : IN STD_LOGIC; 122 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 123 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 124 | ); 125 | end component; 126 | 127 | component sram is 128 | PORT 129 | ( 130 | address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 131 | address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 132 | clock : IN STD_LOGIC ; 133 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 134 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 135 | wren_a : IN STD_LOGIC; 136 | wren_b : IN STD_LOGIC; 137 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 138 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 139 | ); 140 | end component; 141 | 142 | component spram IS 143 | PORT 144 | ( 145 | address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 146 | clock : IN STD_LOGIC ; 147 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 148 | wren : IN STD_LOGIC ; 149 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 150 | ); 151 | END component; 152 | 153 | component CPU2A03 is 154 | port( 155 | clk : in std_logic; 156 | reset : in std_logic; 157 | irq_in : in std_logic; 158 | nmi_in : in std_logic; 159 | addr : out std_logic_vector(15 downto 0); 160 | data_in : in std_logic_vector(7 downto 0); 161 | data_out : out std_logic_vector(7 downto 0); 162 | we : out std_logic; 163 | rd : out std_logic; 164 | sync : out std_logic 165 | ); 166 | end component; 167 | 168 | 169 | --define the signal 170 | signal rom_addr : std_logic_vector(14 downto 0); 171 | signal rom_out : std_logic_vector(7 downto 0); 172 | 173 | signal vrom_addra : std_logic_vector(12 downto 0); 174 | signal vrom_addrb : std_logic_vector(12 downto 0); 175 | signal vrom_outa : std_logic_vector(7 downto 0); 176 | signal vrom_outb : std_logic_vector(7 downto 0); 177 | 178 | signal ram_addra : std_logic_vector(10 downto 0); 179 | signal ram_addrb : std_logic_vector(10 downto 0); 180 | signal ram_ina : std_logic_vector(7 downto 0); 181 | signal ram_inb : std_logic_vector(7 downto 0); 182 | signal ram_wea : std_logic; 183 | signal ram_web : std_logic; 184 | signal ram_outa : std_logic_vector(7 downto 0); 185 | signal ram_outb : std_logic_vector(7 downto 0); 186 | 187 | signal sram_addra : std_logic_vector(11 downto 0); 188 | signal sram_addrb : std_logic_vector(11 downto 0); 189 | signal sram_ina : std_logic_vector(7 downto 0); 190 | signal sram_inb : std_logic_vector(7 downto 0); 191 | signal sram_wea : std_logic; 192 | signal sram_web : std_logic :='0'; 193 | signal sram_outa : std_logic_vector(7 downto 0); 194 | signal sram_outb : std_logic_vector(7 downto 0); 195 | 196 | signal spram_addr : std_logic_vector(7 downto 0); 197 | signal spram_in : std_logic_vector(7 downto 0); 198 | signal spram_we : std_logic; 199 | signal spram_out : std_logic_vector(7 downto 0); 200 | 201 | signal state : std_logic_vector(3 downto 0); 202 | signal state2 : std_logic_vector(3 downto 0); 203 | signal name_index_y : std_logic_vector(4 downto 0); 204 | signal name_reg : std_logic_vector(7 downto 0); 205 | signal name_reg2 : std_logic_vector(7 downto 0); 206 | 207 | signal palette_table : palette_table_type; 208 | 209 | signal port2000 : std_logic_vector(7 downto 0); 210 | signal port2001 : std_logic_vector(7 downto 0); 211 | signal port2002 : std_logic_vector(7 downto 0); 212 | 213 | --the spirit confirm port 214 | signal port2003 : std_logic_vector(7 downto 0); 215 | signal port2004 : std_logic_vector(7 downto 0); 216 | 217 | --the scroll confirm port 218 | signal port2005_d : std_logic; 219 | signal port2005_y : std_logic_vector(7 downto 0); 220 | signal port2005_x : std_logic_vector(7 downto 0); 221 | signal port2005_x_reg : std_logic_vector(7 downto 0); 222 | 223 | signal port2006_d : std_logic; 224 | signal port2006_h : std_logic_vector(7 downto 0); 225 | signal port2006_h_reg : std_logic_vector(7 downto 0); 226 | signal port2006_l : std_logic_vector(7 downto 0); 227 | 228 | signal port2007 : std_logic_vector(7 downto 0); 229 | signal port2007_rd : std_logic; 230 | 231 | signal cpu_clk : std_logic; 232 | signal nmi_reg : std_logic; 233 | signal irq_reg : std_logic; 234 | signal addr_reg : std_logic_vector(15 downto 0); 235 | signal data_in : std_logic_vector(7 downto 0); 236 | signal data_out : std_logic_vector(7 downto 0); 237 | signal rd : std_logic; 238 | signal we : std_logic; 239 | signal sync : std_logic; 240 | signal rom_select : std_logic_vector(1 downto 0); 241 | 242 | signal cpu_sp_index : std_logic_vector(7 downto 0); 243 | 244 | signal data_reg : std_logic_vector(7 downto 0); 245 | signal is_first : std_logic; 246 | signal joy1_state : std_logic_vector(3 downto 0); 247 | signal port2002_rd : std_logic; 248 | signal spi_point : std_logic_vector(2 downto 0); 249 | signal port2007_reg : std_logic_vector(7 downto 0); 250 | signal port2007_tmp : std_logic_vector(7 downto 0); 251 | signal yv : std_logic_vector(7 downto 0); 252 | signal yv_n : integer range 0 to 511; 253 | signal is_scan : std_logic_vector(1 downto 0); 254 | signal sp_ram : std_logic_vector(2 downto 0); 255 | signal sp_ram_reg : std_logic_vector(2 downto 0); 256 | signal sprite0 : std_logic_vector(7 downto 0); 257 | signal sram_addra_reg : std_logic_vector(11 downto 0); 258 | signal myclk : std_logic; 259 | signal dma_on : std_logic; 260 | 261 | signal name_mirror : name_mirror_type; 262 | signal spiline : line_type; 263 | signal bakline : line_type; 264 | signal spiline_bg : line_bg_type; 265 | 266 | begin 267 | 268 | sram_web<='0'; 269 | sram_inb<="00000000"; 270 | ram_web<='0'; 271 | ram_inb<="00000000"; 272 | 273 | rom1 : rom port map(rom_addr,clk2,rom_out); 274 | vrom1 : vrom port map(vrom_addra,vrom_addrb,clk2,vrom_outa,vrom_outb); 275 | spram1 : spram port map(spram_addr,clk2,spram_in,spram_we,spram_out); 276 | ram1 : ram port map(ram_addra,ram_addrb,clk2,ram_ina,ram_inb,ram_wea,ram_web,ram_outa,ram_outb); 277 | sram1 : sram port map(name_mirror(conv_integer(sram_addra(11 downto 10)))&sram_addra(9 downto 0),name_mirror(conv_integer(sram_addrb(11 downto 10)))&sram_addrb(9 downto 0),clk2,sram_ina,sram_inb,sram_wea,sram_web,sram_outa,sram_outb); 278 | cpu1 : CPU2A03 port map(myclk,not reset,irq_reg,nmi_reg,addr_reg,data_in,data_out,we,rd,sync); 279 | 280 | --divide the clk to 3Mhz 281 | process(clk,reset) 282 | variable temp : std_logic_vector(3 downto 0); 283 | variable temp2 : std_logic_vector(3 downto 0); 284 | begin 285 | if reset='0' then 286 | temp:="0000"; 287 | elsif clk'event and clk='1' then 288 | temp2:=sw(3)&sw(2)&sw(1)&sw(0); 289 | temp:=temp+1; 290 | if temp=temp2 then 291 | if sw(13)='0' then 292 | cpu_clk<=not cpu_clk; 293 | end if; 294 | temp:="0000"; 295 | end if; 296 | end if; 297 | end process; 298 | 299 | process(clk2) 300 | begin 301 | if clk2'event and clk2='1' then 302 | myclk<=cpu_clk and (not dma_on); 303 | name_mirror(0)<=sw(17); 304 | name_mirror(1)<=sw(16); 305 | name_mirror(2)<=sw(15); 306 | name_mirror(3)<=sw(14); 307 | end if; 308 | end process; 309 | 310 | --the cpu memory map 311 | process(addr_reg,rd,we,sync) 312 | variable temp : std_logic_vector(8 downto 0); 313 | begin 314 | if myclk'event and myclk='0' then 315 | rom_select<="10"; 316 | ram_wea<='0'; 317 | sram_wea<='0'; 318 | port2002_rd<='0'; 319 | sram_addra<=sram_addra_reg; 320 | 321 | case addr_reg(15 downto 13) is 322 | when "000" => 323 | --address is from 0x0000 to 0x1fff 324 | ram_addra<=addr_reg(10 downto 0); 325 | ram_ina<=data_out; 326 | ram_wea<=we; 327 | rom_select<="00"; 328 | when "001" => 329 | --address is from 0x2000 to 0x2007 330 | case addr_reg(2 downto 0) is 331 | when "000" => 332 | if we='1' then 333 | port2000<=data_out; 334 | elsif rd='1' then 335 | data_reg<=port2000; 336 | rom_select<="10"; 337 | end if; 338 | when "001" => 339 | if we='1' then 340 | port2001<=data_out; 341 | elsif rd='1' then 342 | data_reg<=port2001; 343 | rom_select<="10"; 344 | end if; 345 | when "010" => 346 | if rd='1' then 347 | data_reg<=port2002; 348 | port2005_d<='0'; 349 | port2006_d<='0'; 350 | port2002_rd<='1'; 351 | rom_select<="10"; 352 | end if; 353 | when "011" => 354 | if we='1' then 355 | cpu_sp_index<=data_out; 356 | end if; 357 | when "100" => 358 | ram_addra<=sp_ram&cpu_sp_index; 359 | ram_ina<=data_out; 360 | ram_wea<=we; 361 | cpu_sp_index<=cpu_sp_index+1; 362 | rom_select<="00"; 363 | when "101" => 364 | if we='1' then 365 | if port2005_d='0' then 366 | port2005_d<='1'; 367 | port2005_x<=data_out; 368 | else 369 | port2005_d<='0'; 370 | port2005_y<=data_out; 371 | end if; 372 | end if; 373 | when "110" => 374 | if we='1' then 375 | if port2005_d='0' then 376 | port2006_h_reg<=data_out; 377 | port2005_d<='1'; 378 | port2000(1 downto 0)<=port2006_h_reg(3 downto 2); 379 | else 380 | port2005_d<='0'; 381 | port2006_l<=data_out; 382 | port2006_h<=port2006_h_reg; 383 | port2005_x(7 downto 3)<=data_out(4 downto 0); 384 | port2005_y(7 downto 3)<=port2006_h_reg(1 downto 0)&data_out(7 downto 5); 385 | port2000(1 downto 0)<=port2006_h_reg(3 downto 2); 386 | end if; 387 | end if; 388 | when "111" => 389 | if we='1' then 390 | if port2006_h(5 downto 4) = "10" then 391 | sram_addra<=port2006_h(3 downto 0)&port2006_l; 392 | sram_wea<=we; 393 | sram_ina<=data_out; 394 | elsif port2006_h(5 downto 4) = "11" then 395 | if port2006_h(3 downto 0)="1111" then 396 | if (port2006_l(2 downto 0)=0) then 397 | palette_table(0)<=data_out(5 downto 0); 398 | else 399 | palette_table(conv_integer(port2006_l(4 downto 0)))<=data_out(5 downto 0); 400 | end if; 401 | else 402 | sram_addra<=port2006_h(3 downto 0)&port2006_l; 403 | sram_wea<=we; 404 | sram_ina<=data_out; 405 | end if; 406 | end if; 407 | elsif rd='1' then 408 | if port2006_h(5 downto 4) = "10" then 409 | port2007_reg<=sram_outa; 410 | sram_addra<=port2006_h(3 downto 0)&port2006_l; 411 | sram_addra_reg<=port2006_h(3 downto 0)&port2006_l; 412 | rom_select<="11"; 413 | elsif port2006_h(5 downto 4) = "11" then 414 | if port2006_h(3 downto 0)="1111" then 415 | data_reg<="00"&palette_table(conv_integer(port2006_l(4 downto 0))); 416 | rom_select<="10"; 417 | else 418 | port2007_reg<=sram_outa; 419 | sram_addra<=port2006_h(3 downto 0)&port2006_l; 420 | sram_addra_reg<=port2006_h(3 downto 0)&port2006_l; 421 | rom_select<="11"; 422 | end if; 423 | end if; 424 | end if; 425 | if port2000(2)='0' then 426 | temp:='0'&port2006_l+1; 427 | port2006_l<=temp(7 downto 0); 428 | port2006_h<=temp(8)+port2006_h; 429 | else 430 | temp:='0'&port2006_l+32; 431 | port2006_l<=temp(7 downto 0); 432 | port2006_h<=temp(8)+port2006_h; 433 | end if; 434 | end case; 435 | 436 | when "010" => 437 | --address is from 0x4000 to 0x4017 438 | if addr_reg(12 downto 0)="0000000010100" then 439 | if we='1' then 440 | sp_ram<=data_out(2 downto 0); 441 | end if; 442 | elsif addr_reg(12 downto 0)="0000000010110" then 443 | if rd='1' then 444 | rom_select<="10"; 445 | data_reg(1)<='0'; 446 | data_reg(7 downto 6)<="01"; 447 | case joy1_state is 448 | when "0000" => 449 | data_reg(0)<=sw(5); 450 | joy1_state<="0001"; 451 | when "0001" => 452 | data_reg(0)<=sw(6); 453 | joy1_state<="0010"; 454 | when "0010" => 455 | data_reg(0)<=sw(7); 456 | joy1_state<="0011"; 457 | when "0011" => 458 | data_reg(0)<=sw(8); 459 | joy1_state<="0100"; 460 | when "0100" => 461 | data_reg(0)<=sw(9); 462 | joy1_state<="0101"; 463 | when "0101" => 464 | data_reg(0)<=sw(10); 465 | joy1_state<="0110"; 466 | when "0110" => 467 | data_reg(0)<=sw(11); 468 | joy1_state<="0111"; 469 | when "0111" => 470 | data_reg(0)<=sw(12); 471 | joy1_state<="0000"; 472 | when others=> 473 | end case; 474 | elsif we='1' then 475 | joy1_state<="0000"; 476 | end if; 477 | end if; 478 | 479 | 480 | when "011" => 481 | --not used 482 | when others => 483 | --address is from 0x8000 to 0xffff 484 | if rd='1' then 485 | rom_addr<=addr_reg(14 downto 0); 486 | rom_select<="01"; 487 | end if; 488 | end case; 489 | palette_table(4)<=palette_table(0); 490 | palette_table(8)<=palette_table(0); 491 | palette_table(12)<=palette_table(0); 492 | palette_table(16)<=palette_table(0); 493 | palette_table(20)<=palette_table(0); 494 | palette_table(24)<=palette_table(0); 495 | palette_table(28)<=palette_table(0); 496 | end if; 497 | end process; 498 | 499 | process(clk2,rom_select) 500 | begin 501 | if clk2'event and clk2='1' then 502 | case rom_select is 503 | when "00" => 504 | data_in<=ram_outa; 505 | when "01" => 506 | data_in<=rom_out; 507 | when "10" => 508 | data_in<=data_reg; 509 | when "11" => 510 | data_in<=port2007_reg; 511 | end case; 512 | end if; 513 | end process; 514 | 515 | --draw the scanline 516 | process(clk) 517 | variable temp1 : std_logic_vector(3 downto 0); 518 | variable temp2 : std_logic_vector(5 downto 0); 519 | variable temp4 : std_logic_vector(3 downto 0); 520 | variable temp3 : std_logic_vector(7 downto 0); 521 | begin 522 | if clk'event and clk='1' then 523 | if vy0 then 530 | temp2:=palette_table(conv_integer('0'&temp1)); 531 | else 532 | temp2:=palette_table(0); 533 | end if; 534 | temp4:=spiline(conv_integer(vx(7 downto 0))); 535 | if port2001(4)='1' then 536 | if spiline_bg(conv_integer(vx(7 downto 0)))='0' then 537 | if temp4(1 downto 0)>0 then 538 | temp2:=palette_table(conv_integer('1'&temp4)); 539 | else 540 | temp2:=palette_table(conv_integer('0'&temp1)); 541 | end if; 542 | else 543 | if temp1(1 downto 0)=0 then 544 | temp2:=palette_table(conv_integer('1'&temp4)); 545 | else 546 | temp2:=palette_table(conv_integer('0'&temp1)); 547 | end if; 548 | end if; 549 | temp3:=vx(7 downto 0)-sprite0; 550 | if temp3<8 then 551 | if temp1(1 downto 0)>0 and temp4(1 downto 0)>0 then 552 | port2002(6)<='1'; 553 | end if; 554 | end if; 555 | end if; 556 | 557 | r_out<=r_color(conv_integer(temp2)); 558 | g_out<=g_color(conv_integer(temp2)); 559 | b_out<=b_color(conv_integer(temp2)); 560 | else 561 | r_out<=(others=>'0'); 562 | g_out<=(others=>'0'); 563 | b_out<=(others=>'0'); 564 | end if; 565 | else 566 | r_out<=(others=>'0'); 567 | g_out<=(others=>'0'); 568 | b_out<=(others=>'0'); 569 | end if; 570 | end if; 571 | end process; 572 | 573 | --draw the background 574 | process(clk,reset,vx,vy) 575 | variable name_index_y_l,name_index_x_l : std_logic_vector(5 downto 0); 576 | variable vvy : std_logic_vector(7 downto 0); 577 | variable bakline_reg : line_type2; 578 | variable trans : integer range 0 to 255; 579 | variable temp : std_logic_vector(1 downto 0); 580 | begin 581 | if clk'event and clk='1' then 582 | if vy 587 | if vx=0 then 588 | state<="0001"; 589 | name_index_x_l:=(others=>'0'); 590 | end if; 591 | when "0001" => 592 | trans:=0; 593 | name_index_y_l:=port2000(1)&name_index_y+port2005_y(7 downto 3); 594 | if name_index_y_l>29 then 595 | name_index_y_l:=name_index_y_l+2; 596 | end if; 597 | sram_addrb<=name_index_y_l(5)&name_index_x_l(5)&name_index_y_l(4 downto 0)&name_index_x_l(4 downto 0); 598 | state<="0010"; 599 | when "0010" => 600 | vrom_addrb<=port2000(4)&sram_outb&'0'&vvy(2 downto 0); 601 | state<="0011"; 602 | when "0011" => 603 | vrom_addrb<=port2000(4)&sram_outb&'1'&vvy(2 downto 0); 604 | sram_addrb<=name_index_y_l(5)&name_index_x_l(5)&"1111"&name_index_y_l(4 downto 2)&name_index_x_l(4 downto 2); 605 | name_reg<=vrom_outb; 606 | state<="0100"; 607 | when "0100" => 608 | temp:=sram_outb(conv_integer(name_index_y_l(1)&name_index_x_l(1)&'1'))&sram_outb(conv_integer(name_index_y_l(1)&name_index_x_l(1)&'0')); 609 | bakline_reg(conv_integer(name_index_x_l&"000")):=temp&vrom_outb(7)&name_reg(7); 610 | bakline_reg(conv_integer(name_index_x_l&"001")):=temp&vrom_outb(6)&name_reg(6); 611 | bakline_reg(conv_integer(name_index_x_l&"010")):=temp&vrom_outb(5)&name_reg(5); 612 | bakline_reg(conv_integer(name_index_x_l&"011")):=temp&vrom_outb(4)&name_reg(4); 613 | bakline_reg(conv_integer(name_index_x_l&"100")):=temp&vrom_outb(3)&name_reg(3); 614 | bakline_reg(conv_integer(name_index_x_l&"101")):=temp&vrom_outb(2)&name_reg(2); 615 | bakline_reg(conv_integer(name_index_x_l&"110")):=temp&vrom_outb(1)&name_reg(1); 616 | bakline_reg(conv_integer(name_index_x_l&"111")):=temp&vrom_outb(0)&name_reg(0); 617 | if name_index_x_l="111111" then 618 | state<="0101"; 619 | name_index_x_l:="000000"; 620 | else 621 | name_index_x_l:=name_index_x_l+1; 622 | state<="0001"; 623 | end if; 624 | when "0101" => 625 | if vx>240 then 626 | if trans<255 then 627 | bakline(trans)<=bakline_reg(trans+conv_integer(port2000(0)&port2005_x)); 628 | trans:=trans+1; 629 | else 630 | state<="0000"; 631 | end if; 632 | end if; 633 | when others=> 634 | end case; 635 | end if; 636 | end if; 637 | end process; 638 | 639 | 640 | process(clk,vy) 641 | begin 642 | if clk'event and clk='1' then 643 | if vy 693 | if vx=0 then 694 | state2<="0001"; 695 | sp_index:=(others=>'1'); 696 | spram_addr<=sp_index&"00"; 697 | spi_num:="0000"; 698 | spiline_reg:=(OTHERS => (OTHERS => '0')); 699 | port2002(5)<='0'; 700 | sprite0_reg:=(others=>'1'); 701 | end if; 702 | when "0001" => 703 | trans:=0; 704 | sprite0_reg:="00000000"; 705 | temp:=yv-spram_out; 706 | if port2000(5)='0' then 707 | if temp<8 then 708 | spram_addr<=sp_index&"01"; 709 | state2<="0010"; 710 | else 711 | if sp_index="000000" then 712 | state2<="1000"; 713 | else 714 | sp_index:=sp_index-1; 715 | spram_addr<=sp_index&"00"; 716 | state2<="0001"; 717 | end if; 718 | end if; 719 | else 720 | if temp<16 then 721 | spram_addr<=sp_index&"01"; 722 | state2<="0011"; 723 | else 724 | if sp_index="000000" then 725 | state2<="1000"; 726 | else 727 | sp_index:=sp_index-1; 728 | spram_addr<=sp_index&"00"; 729 | state2<="0001"; 730 | end if; 731 | end if; 732 | end if; 733 | when "0010" => 734 | temp2:=spram_out; 735 | spram_addr<=sp_index&"10"; 736 | state2<="0100"; 737 | when "0011" => 738 | temp2:=spram_out; 739 | spram_addr<=sp_index&"10"; 740 | state2<="0101"; 741 | when "0100" => 742 | attrib:=spram_out; 743 | if attrib(7)='0' then 744 | vrom_addra<=port2000(3)&temp2&'0'&temp(2 downto 0); 745 | else 746 | temp(2 downto 0):=not temp(2 downto 0); 747 | vrom_addra<=port2000(3)&temp2&'0'&temp(2 downto 0); 748 | end if; 749 | if spi_num(3)='0' then 750 | state2<="0110"; 751 | spi_num:=spi_num+1; 752 | else 753 | state2<="1000"; 754 | port2002(5)<='1'; 755 | end if; 756 | when "0101" => 757 | attrib:=spram_out; 758 | if attrib(7)='0' then 759 | vrom_addra<=temp2(0)&temp2(7 downto 1)&temp(3)&'0'&temp(2 downto 0); 760 | else 761 | temp(2 downto 0):=not temp(2 downto 0); 762 | vrom_addra<=temp2(0)&temp2(7 downto 1)&temp(3)&'0'&temp(2 downto 0); 763 | end if; 764 | if spi_num(3)='0' then 765 | state2<="0110"; 766 | spi_num:=spi_num+1; 767 | else 768 | state2<="1000"; 769 | port2002(5)<='1'; 770 | end if; 771 | when "0110" => 772 | name_reg2<=vrom_outa; 773 | if port2000(5)='0' then 774 | vrom_addra<=port2000(3)&temp2&'1'&temp(2 downto 0); 775 | else 776 | vrom_addra<=temp2(0)&temp2(7 downto 1)&temp(3)&'1'&temp(2 downto 0); 777 | end if; 778 | state2<="0111"; 779 | spram_addr<=sp_index&"11"; 780 | sprnum:=0; 781 | when "0111" => 782 | temp:=spram_out+sprnum; 783 | temp3:=attrib(1 downto 0)&vrom_outa(sprnum)&name_reg2(sprnum); 784 | temp4:=attrib(1 downto 0)&vrom_outa(7-sprnum)&name_reg2(7-sprnum); 785 | if attrib(6)='1' then 786 | if temp3(1 downto 0)>0 then 787 | spiline_reg(conv_integer(temp)):=temp3; 788 | end if; 789 | else 790 | if temp4(1 downto 0)>0 then 791 | spiline_reg(conv_integer(temp)):=temp4; 792 | end if; 793 | end if; 794 | spiline_bg_reg(conv_integer(temp)):=attrib(5); 795 | if sprnum=7 then 796 | if sp_index="000000" then 797 | state2<="1000"; 798 | sprite0_reg:=spram_out; 799 | else 800 | sp_index:=sp_index-1; 801 | spram_addr<=sp_index&"00"; 802 | state2<="0001"; 803 | end if; 804 | else 805 | sprnum:=sprnum+1; 806 | state2<="0111"; 807 | end if; 808 | when "1000" => 809 | if vx>256 then 810 | if trans<255 then 811 | spiline(trans)<=spiline_reg(trans); 812 | spiline_bg(trans)<=spiline_bg_reg(trans); 813 | trans:=trans+1; 814 | else 815 | state2<="0000"; 816 | sprite0<=sprite0_reg; 817 | end if; 818 | end if; 819 | when others=> 820 | end case; 821 | dma:='1'; 822 | else 823 | if dma='1' then 824 | dma_on<='1'; 825 | dma:='0'; 826 | dma_num:="00000000"; 827 | ram_addrb<=sp_ram&dma_num; 828 | end if; 829 | if dma_on='1' then 830 | spram_addr<=dma_num; 831 | spram_we<='1'; 832 | spram_in<=ram_outb; 833 | if dma_num<255 then 834 | dma_num:=dma_num+1; 835 | else 836 | dma_on<='0'; 837 | spram_we<='0'; 838 | end if; 839 | ram_addrb<=sp_ram&dma_num; 840 | end if; 841 | 842 | end if; 843 | end if; 844 | end process; 845 | 846 | process(clk) 847 | begin 848 | if clk'event and clk='1' then 849 | if is_scan="10" then 850 | port2002(7)<='1'; 851 | elsif is_scan="01" then 852 | port2002(7)<='0'; 853 | elsif port2002_rd='1' then 854 | port2002(7)<='0'; 855 | end if; 856 | end if; 857 | end process; 858 | 859 | end; -------------------------------------------------------------------------------- /src/ram.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 2-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: ram.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2007 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY ram IS 43 | PORT 44 | ( 45 | address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 46 | address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 47 | clock : IN STD_LOGIC ; 48 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 50 | wren_a : IN STD_LOGIC := '1'; 51 | wren_b : IN STD_LOGIC := '1'; 52 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 53 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 54 | ); 55 | END ram; 56 | 57 | 58 | ARCHITECTURE SYN OF ram IS 59 | 60 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 61 | SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); 62 | 63 | 64 | 65 | COMPONENT altsyncram 66 | GENERIC ( 67 | address_reg_b : STRING; 68 | clock_enable_input_a : STRING; 69 | clock_enable_input_b : STRING; 70 | clock_enable_output_a : STRING; 71 | clock_enable_output_b : STRING; 72 | indata_reg_b : STRING; 73 | init_file : STRING; 74 | intended_device_family : STRING; 75 | lpm_type : STRING; 76 | numwords_a : NATURAL; 77 | numwords_b : NATURAL; 78 | operation_mode : STRING; 79 | outdata_aclr_a : STRING; 80 | outdata_aclr_b : STRING; 81 | outdata_reg_a : STRING; 82 | outdata_reg_b : STRING; 83 | power_up_uninitialized : STRING; 84 | read_during_write_mode_mixed_ports : STRING; 85 | widthad_a : NATURAL; 86 | widthad_b : NATURAL; 87 | width_a : NATURAL; 88 | width_b : NATURAL; 89 | width_byteena_a : NATURAL; 90 | width_byteena_b : NATURAL; 91 | wrcontrol_wraddress_reg_b : STRING 92 | ); 93 | PORT ( 94 | wren_a : IN STD_LOGIC ; 95 | clock0 : IN STD_LOGIC ; 96 | wren_b : IN STD_LOGIC ; 97 | address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 98 | address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 99 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 100 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 101 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 102 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) 103 | ); 104 | END COMPONENT; 105 | 106 | BEGIN 107 | q_a <= sub_wire0(7 DOWNTO 0); 108 | q_b <= sub_wire1(7 DOWNTO 0); 109 | 110 | altsyncram_component : altsyncram 111 | GENERIC MAP ( 112 | address_reg_b => "CLOCK0", 113 | clock_enable_input_a => "BYPASS", 114 | clock_enable_input_b => "BYPASS", 115 | clock_enable_output_a => "BYPASS", 116 | clock_enable_output_b => "BYPASS", 117 | indata_reg_b => "CLOCK0", 118 | init_file => "ram.mif", 119 | intended_device_family => "Cyclone II", 120 | lpm_type => "altsyncram", 121 | numwords_a => 2048, 122 | numwords_b => 2048, 123 | operation_mode => "BIDIR_DUAL_PORT", 124 | outdata_aclr_a => "NONE", 125 | outdata_aclr_b => "NONE", 126 | outdata_reg_a => "UNREGISTERED", 127 | outdata_reg_b => "UNREGISTERED", 128 | power_up_uninitialized => "FALSE", 129 | read_during_write_mode_mixed_ports => "DONT_CARE", 130 | widthad_a => 11, 131 | widthad_b => 11, 132 | width_a => 8, 133 | width_b => 8, 134 | width_byteena_a => 1, 135 | width_byteena_b => 1, 136 | wrcontrol_wraddress_reg_b => "CLOCK0" 137 | ) 138 | PORT MAP ( 139 | wren_a => wren_a, 140 | clock0 => clock, 141 | wren_b => wren_b, 142 | address_a => address_a, 143 | address_b => address_b, 144 | data_a => data_a, 145 | data_b => data_b, 146 | q_a => sub_wire0, 147 | q_b => sub_wire1 148 | ); 149 | 150 | 151 | 152 | END SYN; 153 | 154 | -- ============================================================ 155 | -- CNX file retrieval info 156 | -- ============================================================ 157 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 158 | -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 159 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 160 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 161 | -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 162 | -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 163 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 164 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 165 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 166 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 167 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 168 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 169 | -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" 170 | -- Retrieval info: PRIVATE: CLRq NUMERIC "0" 171 | -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 172 | -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" 173 | -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 174 | -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" 175 | -- Retrieval info: PRIVATE: Clock NUMERIC "0" 176 | -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" 177 | -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" 178 | -- Retrieval info: PRIVATE: ECC NUMERIC "0" 179 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 180 | -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 181 | -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 182 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 183 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 184 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 185 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 186 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 187 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 188 | -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" 189 | -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 190 | -- Retrieval info: PRIVATE: MIFfilename STRING "ram.mif" 191 | -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 192 | -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 193 | -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 194 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 195 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 196 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 197 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 198 | -- Retrieval info: PRIVATE: REGdata NUMERIC "1" 199 | -- Retrieval info: PRIVATE: REGq NUMERIC "0" 200 | -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 201 | -- Retrieval info: PRIVATE: REGrren NUMERIC "0" 202 | -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 203 | -- Retrieval info: PRIVATE: REGwren NUMERIC "1" 204 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 205 | -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 206 | -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 207 | -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" 208 | -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" 209 | -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" 210 | -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" 211 | -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" 212 | -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 213 | -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 214 | -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 215 | -- Retrieval info: PRIVATE: enable NUMERIC "0" 216 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 217 | -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 218 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 219 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 220 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 221 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 222 | -- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 223 | -- Retrieval info: CONSTANT: INIT_FILE STRING "ram.mif" 224 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 225 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 226 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" 227 | -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" 228 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 229 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 230 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 231 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 232 | -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 233 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 234 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 235 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" 236 | -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" 237 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 238 | -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" 239 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 240 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 241 | -- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 242 | -- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0] 243 | -- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0] 244 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 245 | -- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] 246 | -- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] 247 | -- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] 248 | -- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] 249 | -- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a 250 | -- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b 251 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 252 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 253 | -- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 254 | -- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 255 | -- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0 256 | -- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 257 | -- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0 258 | -- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 259 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 260 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 261 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram.vhd TRUE 262 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE 263 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE 264 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE 265 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.vhd FALSE 266 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_waveforms.html FALSE 267 | -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_wave*.jpg FALSE 268 | -- Retrieval info: LIB_FILE: altera_mf 269 | -------------------------------------------------------------------------------- /src/rom.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ROM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: rom.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2007 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY rom IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (14 DOWNTO 0); 46 | clock : IN STD_LOGIC ; 47 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 48 | ); 49 | END rom; 50 | 51 | 52 | ARCHITECTURE SYN OF rom IS 53 | 54 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 55 | 56 | 57 | 58 | COMPONENT altsyncram 59 | GENERIC ( 60 | clock_enable_input_a : STRING; 61 | clock_enable_output_a : STRING; 62 | init_file : STRING; 63 | intended_device_family : STRING; 64 | lpm_hint : STRING; 65 | lpm_type : STRING; 66 | numwords_a : NATURAL; 67 | operation_mode : STRING; 68 | outdata_aclr_a : STRING; 69 | outdata_reg_a : STRING; 70 | widthad_a : NATURAL; 71 | width_a : NATURAL; 72 | width_byteena_a : NATURAL 73 | ); 74 | PORT ( 75 | clock0 : IN STD_LOGIC ; 76 | address_a : IN STD_LOGIC_VECTOR (14 DOWNTO 0); 77 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 78 | ); 79 | END COMPONENT; 80 | 81 | BEGIN 82 | q <= sub_wire0(7 DOWNTO 0); 83 | 84 | altsyncram_component : altsyncram 85 | GENERIC MAP ( 86 | clock_enable_input_a => "BYPASS", 87 | clock_enable_output_a => "BYPASS", 88 | init_file => "rom.mif", 89 | intended_device_family => "Cyclone II", 90 | lpm_hint => "ENABLE_RUNTIME_MOD=NO", 91 | lpm_type => "altsyncram", 92 | numwords_a => 32768, 93 | operation_mode => "ROM", 94 | outdata_aclr_a => "NONE", 95 | outdata_reg_a => "UNREGISTERED", 96 | widthad_a => 15, 97 | width_a => 8, 98 | width_byteena_a => 1 99 | ) 100 | PORT MAP ( 101 | clock0 => clock, 102 | address_a => address, 103 | q_a => sub_wire0 104 | ); 105 | 106 | 107 | 108 | END SYN; 109 | 110 | -- ============================================================ 111 | -- CNX file retrieval info 112 | -- ============================================================ 113 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 114 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 115 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 116 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 117 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 118 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 119 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 120 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 121 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 122 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 123 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 124 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 125 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 126 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 127 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 128 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 129 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 130 | -- Retrieval info: PRIVATE: MIFfilename STRING "rom.mif" 131 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" 132 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 133 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 134 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 135 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 138 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 139 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 140 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 141 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 142 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 143 | -- Retrieval info: CONSTANT: INIT_FILE STRING "rom.mif" 144 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 145 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 146 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 147 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" 148 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 149 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 150 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 151 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 152 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 153 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 154 | -- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL address[14..0] 155 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 156 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] 157 | -- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 158 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 159 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 160 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 161 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.vhd TRUE 162 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE 163 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE 164 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE 165 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.vhd FALSE 166 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom_waveforms.html FALSE 167 | -- Retrieval info: GEN_FILE: TYPE_NORMAL rom_wave*.jpg FALSE 168 | -- Retrieval info: LIB_FILE: altera_mf 169 | -------------------------------------------------------------------------------- /src/spram.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: spram.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2007 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY spram IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 46 | clock : IN STD_LOGIC ; 47 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 48 | wren : IN STD_LOGIC ; 49 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 50 | ); 51 | END spram; 52 | 53 | 54 | ARCHITECTURE SYN OF spram IS 55 | 56 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 57 | 58 | 59 | 60 | COMPONENT altsyncram 61 | GENERIC ( 62 | clock_enable_input_a : STRING; 63 | clock_enable_output_a : STRING; 64 | intended_device_family : STRING; 65 | lpm_hint : STRING; 66 | lpm_type : STRING; 67 | numwords_a : NATURAL; 68 | operation_mode : STRING; 69 | outdata_aclr_a : STRING; 70 | outdata_reg_a : STRING; 71 | power_up_uninitialized : STRING; 72 | widthad_a : NATURAL; 73 | width_a : NATURAL; 74 | width_byteena_a : NATURAL 75 | ); 76 | PORT ( 77 | wren_a : IN STD_LOGIC ; 78 | clock0 : IN STD_LOGIC ; 79 | address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 80 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 81 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0) 82 | ); 83 | END COMPONENT; 84 | 85 | BEGIN 86 | q <= sub_wire0(7 DOWNTO 0); 87 | 88 | altsyncram_component : altsyncram 89 | GENERIC MAP ( 90 | clock_enable_input_a => "BYPASS", 91 | clock_enable_output_a => "BYPASS", 92 | intended_device_family => "Cyclone II", 93 | lpm_hint => "ENABLE_RUNTIME_MOD=NO", 94 | lpm_type => "altsyncram", 95 | numwords_a => 256, 96 | operation_mode => "SINGLE_PORT", 97 | outdata_aclr_a => "NONE", 98 | outdata_reg_a => "UNREGISTERED", 99 | power_up_uninitialized => "FALSE", 100 | widthad_a => 8, 101 | width_a => 8, 102 | width_byteena_a => 1 103 | ) 104 | PORT MAP ( 105 | wren_a => wren, 106 | clock0 => clock, 107 | address_a => address, 108 | data_a => data, 109 | q_a => sub_wire0 110 | ); 111 | 112 | 113 | 114 | END SYN; 115 | 116 | -- ============================================================ 117 | -- CNX file retrieval info 118 | -- ============================================================ 119 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 120 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 121 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 122 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 123 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 124 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 125 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 126 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 127 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 128 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 129 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 130 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 131 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 132 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 133 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 134 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 135 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 136 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 137 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 138 | -- Retrieval info: PRIVATE: MIFfilename STRING "" 139 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 140 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 141 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 142 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 143 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 144 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 145 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 146 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 147 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 148 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 149 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 150 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 151 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 152 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 153 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 154 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 155 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 156 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 157 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 158 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 159 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 160 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 161 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 162 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 163 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 164 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 165 | -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] 166 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 167 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] 168 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] 169 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren 170 | -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 171 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 172 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 173 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 174 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 175 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 176 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram.vhd TRUE 177 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram.inc FALSE 178 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram.cmp FALSE 179 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram.bsf FALSE 180 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram_inst.vhd FALSE 181 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram_waveforms.html FALSE 182 | -- Retrieval info: GEN_FILE: TYPE_NORMAL spram_wave*.jpg FALSE 183 | -- Retrieval info: LIB_FILE: altera_mf 184 | -------------------------------------------------------------------------------- /src/sram.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 2-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: sram.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2007 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY sram IS 43 | PORT 44 | ( 45 | address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 46 | address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 47 | clock : IN STD_LOGIC ; 48 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 50 | wren_a : IN STD_LOGIC := '1'; 51 | wren_b : IN STD_LOGIC := '1'; 52 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 53 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 54 | ); 55 | END sram; 56 | 57 | 58 | ARCHITECTURE SYN OF sram IS 59 | 60 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 61 | SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); 62 | 63 | 64 | 65 | COMPONENT altsyncram 66 | GENERIC ( 67 | address_reg_b : STRING; 68 | clock_enable_input_a : STRING; 69 | clock_enable_input_b : STRING; 70 | clock_enable_output_a : STRING; 71 | clock_enable_output_b : STRING; 72 | indata_reg_b : STRING; 73 | init_file : STRING; 74 | intended_device_family : STRING; 75 | lpm_type : STRING; 76 | numwords_a : NATURAL; 77 | numwords_b : NATURAL; 78 | operation_mode : STRING; 79 | outdata_aclr_a : STRING; 80 | outdata_aclr_b : STRING; 81 | outdata_reg_a : STRING; 82 | outdata_reg_b : STRING; 83 | power_up_uninitialized : STRING; 84 | read_during_write_mode_mixed_ports : STRING; 85 | widthad_a : NATURAL; 86 | widthad_b : NATURAL; 87 | width_a : NATURAL; 88 | width_b : NATURAL; 89 | width_byteena_a : NATURAL; 90 | width_byteena_b : NATURAL; 91 | wrcontrol_wraddress_reg_b : STRING 92 | ); 93 | PORT ( 94 | wren_a : IN STD_LOGIC ; 95 | clock0 : IN STD_LOGIC ; 96 | wren_b : IN STD_LOGIC ; 97 | address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 98 | address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0); 99 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 100 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 101 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 102 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) 103 | ); 104 | END COMPONENT; 105 | 106 | BEGIN 107 | q_a <= sub_wire0(7 DOWNTO 0); 108 | q_b <= sub_wire1(7 DOWNTO 0); 109 | 110 | altsyncram_component : altsyncram 111 | GENERIC MAP ( 112 | address_reg_b => "CLOCK0", 113 | clock_enable_input_a => "BYPASS", 114 | clock_enable_input_b => "BYPASS", 115 | clock_enable_output_a => "BYPASS", 116 | clock_enable_output_b => "BYPASS", 117 | indata_reg_b => "CLOCK0", 118 | init_file => "sram.mif", 119 | intended_device_family => "Cyclone II", 120 | lpm_type => "altsyncram", 121 | numwords_a => 2048, 122 | numwords_b => 2048, 123 | operation_mode => "BIDIR_DUAL_PORT", 124 | outdata_aclr_a => "NONE", 125 | outdata_aclr_b => "NONE", 126 | outdata_reg_a => "UNREGISTERED", 127 | outdata_reg_b => "UNREGISTERED", 128 | power_up_uninitialized => "FALSE", 129 | read_during_write_mode_mixed_ports => "DONT_CARE", 130 | widthad_a => 11, 131 | widthad_b => 11, 132 | width_a => 8, 133 | width_b => 8, 134 | width_byteena_a => 1, 135 | width_byteena_b => 1, 136 | wrcontrol_wraddress_reg_b => "CLOCK0" 137 | ) 138 | PORT MAP ( 139 | wren_a => wren_a, 140 | clock0 => clock, 141 | wren_b => wren_b, 142 | address_a => address_a, 143 | address_b => address_b, 144 | data_a => data_a, 145 | data_b => data_b, 146 | q_a => sub_wire0, 147 | q_b => sub_wire1 148 | ); 149 | 150 | 151 | 152 | END SYN; 153 | 154 | -- ============================================================ 155 | -- CNX file retrieval info 156 | -- ============================================================ 157 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 158 | -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 159 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 160 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 161 | -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 162 | -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 163 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 164 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 165 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 166 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 167 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 168 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 169 | -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" 170 | -- Retrieval info: PRIVATE: CLRq NUMERIC "0" 171 | -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 172 | -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" 173 | -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 174 | -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" 175 | -- Retrieval info: PRIVATE: Clock NUMERIC "0" 176 | -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" 177 | -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" 178 | -- Retrieval info: PRIVATE: ECC NUMERIC "0" 179 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 180 | -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 181 | -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 182 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 183 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 184 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 185 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 186 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 187 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 188 | -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" 189 | -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 190 | -- Retrieval info: PRIVATE: MIFfilename STRING "sram.mif" 191 | -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 192 | -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 193 | -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 194 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 195 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 196 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 197 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 198 | -- Retrieval info: PRIVATE: REGdata NUMERIC "1" 199 | -- Retrieval info: PRIVATE: REGq NUMERIC "0" 200 | -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 201 | -- Retrieval info: PRIVATE: REGrren NUMERIC "0" 202 | -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 203 | -- Retrieval info: PRIVATE: REGwren NUMERIC "1" 204 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 205 | -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 206 | -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 207 | -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" 208 | -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" 209 | -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" 210 | -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" 211 | -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" 212 | -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 213 | -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 214 | -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 215 | -- Retrieval info: PRIVATE: enable NUMERIC "0" 216 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 217 | -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 218 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 219 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 220 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 221 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 222 | -- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 223 | -- Retrieval info: CONSTANT: INIT_FILE STRING "sram.mif" 224 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 225 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 226 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" 227 | -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" 228 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 229 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 230 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 231 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 232 | -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 233 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 234 | -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 235 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" 236 | -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" 237 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 238 | -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" 239 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 240 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 241 | -- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 242 | -- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0] 243 | -- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0] 244 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 245 | -- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] 246 | -- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] 247 | -- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] 248 | -- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] 249 | -- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a 250 | -- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b 251 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 252 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 253 | -- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 254 | -- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 255 | -- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0 256 | -- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 257 | -- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0 258 | -- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 259 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 260 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 261 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.vhd TRUE 262 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.inc FALSE 263 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.cmp FALSE 264 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.bsf FALSE 265 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram_inst.vhd FALSE 266 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram_waveforms.html FALSE 267 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram_wave*.jpg FALSE 268 | -- Retrieval info: LIB_FILE: altera_mf 269 | -------------------------------------------------------------------------------- /src/vgacore.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_ARITH.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | entity vgacore is 7 | Port ( clk : in std_logic; 8 | reset : in std_logic; 9 | hs : out std_logic; 10 | vs : out std_logic; 11 | r : out std_logic_vector(3 downto 0); 12 | g : out std_logic_vector(3 downto 0); 13 | b : out std_logic_vector(3 downto 0); 14 | clk2 : in std_logic; 15 | sw : in std_logic_vector(17 downto 0); 16 | ledr : out std_logic_vector(17 downto 0); 17 | ledg : out std_logic_vector(7 downto 0); 18 | key : in std_logic_vector(2 downto 0); 19 | addr_reg : out std_logic_vector(15 downto 0) 20 | ); 21 | end vgacore; 22 | 23 | architecture Behavioral of vgacore is 24 | --signal div_count : std_logic_vector(1 downto 0); 25 | signal hsyncb : std_logic; 26 | signal vsyncb : std_logic; 27 | signal enable : std_logic; 28 | signal hloc : std_logic_vector(9 downto 0); 29 | signal vloc : std_logic_vector(9 downto 0); 30 | signal r_reg,g_reg,b_reg: std_logic_vector(3 downto 0); 31 | signal r_reg2,g_reg2,b_reg2: std_logic_vector(3 downto 0); 32 | --signal mmd : std_logic_vector(1 downto 0); 33 | 34 | component vgasig 35 | Port ( 36 | clock : in std_logic; 37 | reset : in std_logic; 38 | hsyncb : buffer std_logic; 39 | vsyncb : out std_logic; 40 | enable : out std_logic; 41 | Xaddr : out std_logic_vector(9 downto 0); 42 | Yaddr : out std_logic_vector(9 downto 0) 43 | ); 44 | end component; 45 | 46 | component ppu 47 | port ( 48 | clk : in std_logic; 49 | reset : in std_logic; 50 | vx : in std_logic_vector(9 downto 0); 51 | vy : in std_logic_vector(9 downto 0); 52 | r_out : out std_logic_vector(3 downto 0); 53 | g_out : out std_logic_vector(3 downto 0); 54 | b_out : out std_logic_vector(3 downto 0); 55 | clk2 : in std_logic; 56 | sw : in std_logic_vector(17 downto 0); 57 | ledr : out std_logic_vector(17 downto 0); 58 | ledg : out std_logic_vector(7 downto 0); 59 | key : in std_logic_vector(2 downto 0); 60 | addr_pass : out std_logic_vector(15 downto 0) 61 | ); 62 | end component; 63 | 64 | component linebuf 65 | port ( 66 | address : in std_logic_vector(9 downto 0); 67 | inclock : in std_logic; 68 | we : in std_logic; 69 | data : in std_logic_vector(3 downto 0); 70 | q : out std_logic_vector(3 downto 0) 71 | ); 72 | end component; 73 | 74 | begin 75 | 76 | makesig: vgasig Port map( 77 | clock => clk, 78 | reset => reset, 79 | hsyncb => hsyncb, 80 | vsyncb => vsyncb, 81 | enable => enable, 82 | Xaddr => hloc, 83 | Yaddr => vloc 84 | ); 85 | 86 | hs <= hsyncb; 87 | vs <= vsyncb; 88 | ppu0:ppu port map(clk,reset,hloc,vloc,r_reg,g_reg,b_reg,clk2,sw,ledr,ledg,key,addr_reg); 89 | 90 | 91 | linebuf1 : linebuf port map(hloc,clk,vloc(0),r_reg,r_reg2); 92 | linebuf2 : linebuf port map(hloc,clk,vloc(0),g_reg,g_reg2); 93 | linebuf3 : linebuf port map(hloc,clk,vloc(0),b_reg,b_reg2); 94 | 95 | process(clk) 96 | begin 97 | if clk'event and clk='1' then 98 | if sw(4)='1' then 99 | if enable='1' then 100 | r <= r_reg; 101 | g <= g_reg; 102 | b <= b_reg; 103 | else 104 | r<="0000"; 105 | g<="0000"; 106 | b<="0000"; 107 | end if; 108 | else 109 | r<=r_reg2; 110 | g<=g_reg2; 111 | b<=b_reg2; 112 | end if; 113 | end if; 114 | end process; 115 | 116 | 117 | 118 | end Behavioral; 119 | -------------------------------------------------------------------------------- /src/vgasig.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_ARITH.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | entity vgasig is 7 | Port ( clock : in std_logic; 8 | reset : in std_logic; 9 | hsyncb : buffer std_logic; 10 | vsyncb : out std_logic; 11 | enable : out std_logic; 12 | Xaddr : out std_logic_vector(9 downto 0); 13 | Yaddr : out std_logic_vector(9 downto 0)); 14 | end vgasig; 15 | 16 | architecture Behavioral of vgasig is 17 | 18 | constant H_PIXELS: INTEGER:=640; 19 | constant H_FRONT: INTEGER:=16; 20 | constant H_BACK: INTEGER:=48; 21 | constant H_SYNCTIME: INTEGER:=96; 22 | constant H_PERIOD: INTEGER:= H_SYNCTIME + H_PIXELS + H_FRONT + H_BACK; 23 | 24 | -- vertical timing signals 25 | constant V_LINES: INTEGER:=480; 26 | constant V_FRONT: INTEGER:=11; 27 | constant V_BACK: INTEGER:=32; 28 | constant V_SYNCTIME: INTEGER:=2; 29 | constant V_PERIOD: INTEGER:= V_SYNCTIME + V_LINES + V_FRONT + V_BACK; 30 | 31 | signal hcnt: std_logic_vector(9 downto 0); -- horizontal pixel counter 32 | signal vcnt: std_logic_vector(9 downto 0); -- vertical line counter 33 | begin 34 | 35 | -- control the reset, increment and overflow of the horizontal pixel count 36 | A: process(clock, reset) 37 | begin 38 | -- reset asynchronously clears horizontal counter 39 | if reset = '0' then 40 | hcnt <= (others => '0'); 41 | -- horiz. counter increments on rising edge of dot clock 42 | elsif (clock'event and clock = '1') then 43 | -- horiz. counter restarts after the horizontal period (set by the constants) 44 | if hcnt < H_PERIOD then 45 | hcnt <= hcnt + 1; 46 | else 47 | hcnt <= (others => '0'); 48 | end if; 49 | end if; 50 | end process; 51 | 52 | -- control the reset, increment and overflow of the vertical line counter after every horizontal line 53 | B: process(hsyncb, reset) 54 | begin 55 | -- reset asynchronously clears line counter 56 | if reset='0' then 57 | vcnt <= (others => '0'); 58 | -- vert. line counter increments after every horiz. line 59 | elsif (hsyncb'event and hsyncb = '1') then 60 | -- vert. line counter rolls-over after the set number of lines (set by the constants) 61 | if vcnt < V_PERIOD then 62 | vcnt <= vcnt + 1; 63 | else 64 | vcnt <= (others => '0'); 65 | end if; 66 | end if; 67 | end process; 68 | 69 | -- set the horizontal sync high time and low time according to the constants 70 | C: process(clock, reset) 71 | begin 72 | -- reset asynchronously sets horizontal sync to inactive 73 | if reset = '0' then 74 | hsyncb <= '1'; 75 | -- horizontal sync is recomputed on the rising edge of every dot clock 76 | elsif (clock'event and clock = '1') then 77 | -- horiz. sync is low in this interval to signal start of a new line 78 | if (hcnt >= (H_PIXELS + H_FRONT) and hcnt < (H_PIXELS + H_SYNCTIME + H_FRONT)) then 79 | hsyncb <= '0'; 80 | else 81 | hsyncb <= '1'; 82 | end if; 83 | end if; 84 | end process; 85 | 86 | -- set the vertical sync high time and low time according to the constants 87 | D: process(hsyncb, reset) 88 | begin 89 | -- reset asynchronously sets vertical sync to inactive 90 | if reset = '0' then 91 | vsyncb <= '1'; 92 | -- vertical sync is recomputed at the end of every line of pixels 93 | elsif (hsyncb'event and hsyncb = '1') then 94 | -- vert. sync is low in this interval to signal start of a new frame 95 | if (vcnt >= (V_LINES + V_FRONT) and vcnt < (V_LINES + V_SYNCTIME + V_FRONT)) then 96 | vsyncb <= '0'; 97 | else 98 | vsyncb <= '1'; 99 | end if; 100 | end if; 101 | end process; 102 | 103 | -- whether it should latch the current data or not 104 | -- (always with a 50MHz clock - blanking is handled on the RAMDAC by asserting a signal) 105 | --latch <= NOT reset; 106 | 107 | -- asserts the blaking signal (active low) 108 | E: process (clock) 109 | begin 110 | if clock'EVENT and clock = '1' then 111 | -- if we are outside the visible range on the screen then tell the RAMDAC to blank 112 | -- in this section by putting enable low 113 | if hcnt >= H_PIXELS or vcnt >= V_LINES then 114 | enable <= '0'; 115 | else 116 | enable <= '1'; 117 | end if; 118 | end if; 119 | end process; 120 | 121 | -- The video RAM address is built from the lower 9 bits of the vertical 122 | -- line counter and bits 7-2 of the horizontal pixel counter. 123 | -- Allows easy access for the current address of the current pixel in RAM 124 | H: 125 | Xaddr <= hcnt; 126 | Yaddr <= vcnt; 127 | 128 | end Behavioral; 129 | -------------------------------------------------------------------------------- /src/vrom.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ROM: 2-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: vrom.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2007 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY vrom IS 43 | PORT 44 | ( 45 | address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 46 | address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 47 | clock : IN STD_LOGIC ; 48 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 50 | ); 51 | END vrom; 52 | 53 | 54 | ARCHITECTURE SYN OF vrom IS 55 | 56 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 57 | SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); 58 | SIGNAL sub_wire2 : STD_LOGIC ; 59 | SIGNAL sub_wire3_bv : BIT_VECTOR (7 DOWNTO 0); 60 | SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); 61 | 62 | 63 | 64 | COMPONENT altsyncram 65 | GENERIC ( 66 | address_reg_b : STRING; 67 | clock_enable_input_a : STRING; 68 | clock_enable_input_b : STRING; 69 | clock_enable_output_a : STRING; 70 | clock_enable_output_b : STRING; 71 | indata_reg_b : STRING; 72 | init_file : STRING; 73 | intended_device_family : STRING; 74 | lpm_type : STRING; 75 | numwords_a : NATURAL; 76 | numwords_b : NATURAL; 77 | operation_mode : STRING; 78 | outdata_aclr_a : STRING; 79 | outdata_aclr_b : STRING; 80 | outdata_reg_a : STRING; 81 | outdata_reg_b : STRING; 82 | power_up_uninitialized : STRING; 83 | widthad_a : NATURAL; 84 | widthad_b : NATURAL; 85 | width_a : NATURAL; 86 | width_b : NATURAL; 87 | width_byteena_a : NATURAL; 88 | width_byteena_b : NATURAL; 89 | wrcontrol_wraddress_reg_b : STRING 90 | ); 91 | PORT ( 92 | wren_a : IN STD_LOGIC ; 93 | wren_b : IN STD_LOGIC ; 94 | clock0 : IN STD_LOGIC ; 95 | address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 96 | address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0); 97 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 98 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 99 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 100 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) 101 | ); 102 | END COMPONENT; 103 | 104 | BEGIN 105 | sub_wire2 <= '0'; 106 | sub_wire3_bv(7 DOWNTO 0) <= "00000000"; 107 | sub_wire3 <= To_stdlogicvector(sub_wire3_bv); 108 | q_a <= sub_wire0(7 DOWNTO 0); 109 | q_b <= sub_wire1(7 DOWNTO 0); 110 | 111 | altsyncram_component : altsyncram 112 | GENERIC MAP ( 113 | address_reg_b => "CLOCK0", 114 | clock_enable_input_a => "BYPASS", 115 | clock_enable_input_b => "BYPASS", 116 | clock_enable_output_a => "BYPASS", 117 | clock_enable_output_b => "BYPASS", 118 | indata_reg_b => "CLOCK0", 119 | init_file => "vrom.mif", 120 | intended_device_family => "Cyclone II", 121 | lpm_type => "altsyncram", 122 | numwords_a => 8192, 123 | numwords_b => 8192, 124 | operation_mode => "BIDIR_DUAL_PORT", 125 | outdata_aclr_a => "NONE", 126 | outdata_aclr_b => "NONE", 127 | outdata_reg_a => "UNREGISTERED", 128 | outdata_reg_b => "UNREGISTERED", 129 | power_up_uninitialized => "FALSE", 130 | widthad_a => 13, 131 | widthad_b => 13, 132 | width_a => 8, 133 | width_b => 8, 134 | width_byteena_a => 1, 135 | width_byteena_b => 1, 136 | wrcontrol_wraddress_reg_b => "CLOCK0" 137 | ) 138 | PORT MAP ( 139 | wren_a => sub_wire2, 140 | wren_b => sub_wire2, 141 | clock0 => clock, 142 | address_a => address_a, 143 | address_b => address_b, 144 | data_a => sub_wire3, 145 | data_b => sub_wire3, 146 | q_a => sub_wire0, 147 | q_b => sub_wire1 148 | ); 149 | 150 | 151 | 152 | END SYN; 153 | 154 | -- ============================================================ 155 | -- CNX file retrieval info 156 | -- ============================================================ 157 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 158 | -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 159 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 160 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 161 | -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 162 | -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 163 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1" 164 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 165 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 166 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 167 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 168 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 169 | -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" 170 | -- Retrieval info: PRIVATE: CLRq NUMERIC "0" 171 | -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 172 | -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" 173 | -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 174 | -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" 175 | -- Retrieval info: PRIVATE: Clock NUMERIC "0" 176 | -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" 177 | -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" 178 | -- Retrieval info: PRIVATE: ECC NUMERIC "0" 179 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 180 | -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 181 | -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 182 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 183 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 184 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 185 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 186 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 187 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 188 | -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536" 189 | -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 190 | -- Retrieval info: PRIVATE: MIFfilename STRING "vrom.mif" 191 | -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 192 | -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 193 | -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 194 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 195 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 196 | -- Retrieval info: PRIVATE: REGdata NUMERIC "1" 197 | -- Retrieval info: PRIVATE: REGq NUMERIC "0" 198 | -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 199 | -- Retrieval info: PRIVATE: REGrren NUMERIC "0" 200 | -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 201 | -- Retrieval info: PRIVATE: REGwren NUMERIC "1" 202 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 203 | -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 204 | -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 205 | -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" 206 | -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" 207 | -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" 208 | -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" 209 | -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" 210 | -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 211 | -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 212 | -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 213 | -- Retrieval info: PRIVATE: enable NUMERIC "0" 214 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 215 | -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 216 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 217 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 218 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 219 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 220 | -- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 221 | -- Retrieval info: CONSTANT: INIT_FILE STRING "vrom.mif" 222 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 223 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 224 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" 225 | -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" 226 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 227 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 228 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 229 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 230 | -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 231 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 232 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" 233 | -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" 234 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 235 | -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" 236 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 237 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 238 | -- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 239 | -- Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL address_a[12..0] 240 | -- Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL address_b[12..0] 241 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 242 | -- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] 243 | -- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] 244 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 245 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 GND 0 0 8 0 246 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0 247 | -- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 248 | -- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 249 | -- Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0 250 | -- Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0 251 | -- Retrieval info: CONNECT: @data_b 0 0 8 0 GND 0 0 8 0 252 | -- Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0 253 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 254 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom.vhd TRUE 255 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom.inc FALSE 256 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom.cmp FALSE 257 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom.bsf FALSE 258 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom_inst.vhd FALSE 259 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom_waveforms.html FALSE 260 | -- Retrieval info: GEN_FILE: TYPE_NORMAL vrom_wave*.jpg FALSE 261 | -- Retrieval info: LIB_FILE: altera_mf 262 | --------------------------------------------------------------------------------