├── .gitignore ├── 0.doc ├── PCIE-Technology3-0---MindSharePress2012.pdf ├── PCIE-base-spec.Rev2-1.pdf ├── PCIE-card-ElectroMech-Spec.Rev4-0.pdf ├── artwork │ └── openCologne-PCIE.png ├── diagrams │ ├── pcie-ep-top-stack.png │ └── pcie-ep-top.drawio ├── images │ ├── CM4-IO-with-PCIE-M2.jpg │ ├── CM4-IO-with-PCIE-Slot.jpg │ ├── Data Read and Write Test Using devmem.png │ ├── NiteFury-PCIE-M2.JPG │ ├── PCIE-Slot-Connector.JPG │ ├── PCIE-Slot-to-M2-adapter.JPG │ ├── PCIE-interop-with-RPI5.png │ ├── Physical Address fc500000 Assigned to PCIe Device.png │ ├── device-detected-in-WinDevManager.png │ └── lspci-output-on-Linux.png ├── pcie-primer.Simon-Southwell.pdf └── using-busybox-devmem-for-reg-access.txt ├── 1.pcb ├── 0.doc │ └── images │ │ └── ULX4M-PCIe-IO.beta_v2.png └── README.md ├── 2.rtl.PHY ├── 0.doc │ ├── Intel.643108_PIPE_Arch_Spec_Rev_7_1.pdf │ ├── MAC_Overview.pdf │ ├── PIPE_overview.pdf │ ├── ds1001-GateMate-datasheet.Aug2025.pdf │ └── images │ │ ├── PCIE-P-and-N-swaps.png │ │ ├── PHY-Layers-GateMate.png │ │ ├── PHY-Layers.jpg │ │ ├── SerDes-BlockDiagram.png │ │ └── optimizing-pcie-pipe-pwr-mgmt.png └── README.md ├── 2.rtl ├── 0.doc │ └── pcie-ep-rtl.drawio ├── README.md └── ip.infra │ ├── clk_rst_gen.sv │ ├── cpu_fifo.sv │ ├── debounce.sv │ ├── dpe_if.sv │ ├── dpe_if_pipeline.sv │ ├── dpe_if_skid_buffer.sv │ ├── dpe_pkg.sv │ ├── dprf_32x32bit.sv │ ├── soc_csr.sv │ ├── soc_fabric.sv │ ├── soc_if.sv │ ├── soc_pkg.sv │ ├── soc_ram.sv │ ├── sync_fifo_ram.sv │ ├── sync_fifo_srl.sv │ ├── uart.WITH-FIFO.sv │ ├── uart.WITHOUT-FIFO.sv │ └── uart.sv ├── 3.sw ├── 0.doc │ └── pcie-ep-sw.drawio └── README.md ├── 4.build └── README.md ├── 5.sim ├── Makefile ├── README.md ├── hex │ └── ContDisps.hex ├── images │ ├── opencologne-pcie-tb.png │ └── soc-cpu-vproc-stack.png ├── models │ ├── README.md │ ├── bfm_uart.sv │ ├── cosim │ │ ├── README.md │ │ ├── extradefs.v │ │ ├── f_VProc.v │ │ ├── f_mem_model.v │ │ ├── include │ │ │ ├── VProc.h │ │ │ ├── VProcClass.h │ │ │ ├── VProcIrqClass.h │ │ │ ├── VSched_pli.h │ │ │ └── VUser.h │ │ ├── lib │ │ │ ├── libcosimlnx.a │ │ │ └── libcosimwin.a │ │ ├── mem_model.sv │ │ ├── mem_model_dpi.vh │ │ ├── vprocdefs.vh │ │ └── vprocdpi.vh │ ├── images │ │ └── soc_cpu_vproc.png │ ├── pcievhost │ │ ├── README.md │ │ ├── images │ │ │ ├── pcie_disp_terminal.png │ │ │ ├── pcievhost_architecture.png │ │ │ └── pcievhost_module.png │ │ ├── include │ │ │ ├── codec.h │ │ │ ├── mem.h │ │ │ ├── pci_express.h │ │ │ ├── pcie.h │ │ │ ├── pcieModelClass.h │ │ │ ├── pcie_utils.h │ │ │ └── pcie_vhost_map.h │ │ ├── lib │ │ │ ├── libpcielnx.a │ │ │ └── libpciewin.a │ │ ├── ltssm │ │ │ ├── README.md │ │ │ ├── ltssm.c │ │ │ └── ltssm.h │ │ └── verilog │ │ │ ├── headers │ │ │ ├── allheaders.v │ │ │ ├── pcie_vhost_map.v │ │ │ ├── pciedispheader.v │ │ │ ├── pciexpress_header.v │ │ │ ├── test_defs.v │ │ │ └── timescale.v │ │ │ └── pcieVHost │ │ │ ├── pcieVHost.v │ │ │ └── pcieVHostPipex1.v │ ├── rv32 │ │ ├── README.md │ │ ├── include │ │ │ ├── rv32.h │ │ │ ├── rv32_cpu_gdb.h │ │ │ ├── rv32_extensions.h │ │ │ ├── rv32a_cpu.h │ │ │ ├── rv32c_cpu.h │ │ │ ├── rv32csr_cpu.h │ │ │ ├── rv32csr_cpu_hdr.h │ │ │ ├── rv32d_cpu.h │ │ │ ├── rv32f_cpu.h │ │ │ ├── rv32i_cpu.h │ │ │ ├── rv32i_cpu_hdr.h │ │ │ ├── rv32m_cpu.h │ │ │ ├── rv32zba_cpu.h │ │ │ ├── rv32zbb_cpu.h │ │ │ ├── rv32zbc_cpu.h │ │ │ └── rv32zbs_cpu.h │ │ ├── lib │ │ │ ├── librv32lnx.a │ │ │ └── librv32win.a │ │ ├── riscvtest │ │ │ ├── main.bin │ │ │ ├── main.s │ │ │ └── rv_asm.sh │ │ ├── scripts │ │ │ ├── favicon.ico │ │ │ ├── icon.png │ │ │ └── rv32cfg.py │ │ └── usercode │ │ │ ├── VUserMain0.cpp │ │ │ ├── VUserMain0.h │ │ │ ├── getopt.c │ │ │ ├── mem_vproc_api.cpp │ │ │ ├── mem_vproc_api.h │ │ │ ├── rv32_cache.cpp │ │ │ ├── rv32_cache.h │ │ │ ├── rv32_timing_config.h │ │ │ ├── uart.cpp │ │ │ ├── uart.h │ │ │ ├── vuserutils.cpp │ │ │ └── vuserutils.h │ └── soc_cpu.VPROC.sv ├── stubs │ ├── README.md │ └── dut_stub.v ├── tb.prj ├── tb.sv ├── usercode │ ├── VUserMain0.cpp │ ├── VUserMain1.cpp │ └── VUserMain2.cpp └── vusermain.cfg ├── 6.litex └── README.md ├── LICENSE └── README.md /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/.gitignore -------------------------------------------------------------------------------- /0.doc/PCIE-Technology3-0---MindSharePress2012.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/PCIE-Technology3-0---MindSharePress2012.pdf -------------------------------------------------------------------------------- /0.doc/PCIE-base-spec.Rev2-1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/PCIE-base-spec.Rev2-1.pdf -------------------------------------------------------------------------------- /0.doc/PCIE-card-ElectroMech-Spec.Rev4-0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/PCIE-card-ElectroMech-Spec.Rev4-0.pdf -------------------------------------------------------------------------------- /0.doc/artwork/openCologne-PCIE.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/artwork/openCologne-PCIE.png -------------------------------------------------------------------------------- /0.doc/diagrams/pcie-ep-top-stack.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/diagrams/pcie-ep-top-stack.png -------------------------------------------------------------------------------- /0.doc/diagrams/pcie-ep-top.drawio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/diagrams/pcie-ep-top.drawio -------------------------------------------------------------------------------- /0.doc/images/CM4-IO-with-PCIE-M2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/CM4-IO-with-PCIE-M2.jpg -------------------------------------------------------------------------------- /0.doc/images/CM4-IO-with-PCIE-Slot.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/CM4-IO-with-PCIE-Slot.jpg -------------------------------------------------------------------------------- /0.doc/images/Data Read and Write Test Using devmem.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/Data Read and Write Test Using devmem.png -------------------------------------------------------------------------------- /0.doc/images/NiteFury-PCIE-M2.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/NiteFury-PCIE-M2.JPG -------------------------------------------------------------------------------- /0.doc/images/PCIE-Slot-Connector.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/PCIE-Slot-Connector.JPG -------------------------------------------------------------------------------- /0.doc/images/PCIE-Slot-to-M2-adapter.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/PCIE-Slot-to-M2-adapter.JPG -------------------------------------------------------------------------------- /0.doc/images/PCIE-interop-with-RPI5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/PCIE-interop-with-RPI5.png -------------------------------------------------------------------------------- /0.doc/images/Physical Address fc500000 Assigned to PCIe Device.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/Physical Address fc500000 Assigned to PCIe Device.png -------------------------------------------------------------------------------- /0.doc/images/device-detected-in-WinDevManager.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/device-detected-in-WinDevManager.png -------------------------------------------------------------------------------- /0.doc/images/lspci-output-on-Linux.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/images/lspci-output-on-Linux.png -------------------------------------------------------------------------------- /0.doc/pcie-primer.Simon-Southwell.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/pcie-primer.Simon-Southwell.pdf -------------------------------------------------------------------------------- /0.doc/using-busybox-devmem-for-reg-access.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/0.doc/using-busybox-devmem-for-reg-access.txt -------------------------------------------------------------------------------- /1.pcb/0.doc/images/ULX4M-PCIe-IO.beta_v2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/1.pcb/0.doc/images/ULX4M-PCIe-IO.beta_v2.png -------------------------------------------------------------------------------- /1.pcb/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/1.pcb/README.md -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/Intel.643108_PIPE_Arch_Spec_Rev_7_1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/Intel.643108_PIPE_Arch_Spec_Rev_7_1.pdf -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/MAC_Overview.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/MAC_Overview.pdf -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/PIPE_overview.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/PIPE_overview.pdf -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/ds1001-GateMate-datasheet.Aug2025.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/ds1001-GateMate-datasheet.Aug2025.pdf -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/images/PCIE-P-and-N-swaps.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/images/PCIE-P-and-N-swaps.png -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/images/PHY-Layers-GateMate.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/images/PHY-Layers-GateMate.png -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/images/PHY-Layers.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/images/PHY-Layers.jpg -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/images/SerDes-BlockDiagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/images/SerDes-BlockDiagram.png -------------------------------------------------------------------------------- /2.rtl.PHY/0.doc/images/optimizing-pcie-pipe-pwr-mgmt.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/0.doc/images/optimizing-pcie-pipe-pwr-mgmt.png -------------------------------------------------------------------------------- /2.rtl.PHY/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl.PHY/README.md -------------------------------------------------------------------------------- /2.rtl/0.doc/pcie-ep-rtl.drawio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/0.doc/pcie-ep-rtl.drawio -------------------------------------------------------------------------------- /2.rtl/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/README.md -------------------------------------------------------------------------------- /2.rtl/ip.infra/clk_rst_gen.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/clk_rst_gen.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/cpu_fifo.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/cpu_fifo.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/debounce.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/debounce.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/dpe_if.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/dpe_if.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/dpe_if_pipeline.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/dpe_if_pipeline.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/dpe_if_skid_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/dpe_if_skid_buffer.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/dpe_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/dpe_pkg.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/dprf_32x32bit.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/dprf_32x32bit.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/soc_csr.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/soc_csr.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/soc_fabric.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/soc_fabric.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/soc_if.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/soc_if.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/soc_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/soc_pkg.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/soc_ram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/soc_ram.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/sync_fifo_ram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/sync_fifo_ram.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/sync_fifo_srl.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/sync_fifo_srl.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/uart.WITH-FIFO.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/uart.WITH-FIFO.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/uart.WITHOUT-FIFO.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/uart.WITHOUT-FIFO.sv -------------------------------------------------------------------------------- /2.rtl/ip.infra/uart.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/2.rtl/ip.infra/uart.sv -------------------------------------------------------------------------------- /3.sw/0.doc/pcie-ep-sw.drawio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/3.sw/0.doc/pcie-ep-sw.drawio -------------------------------------------------------------------------------- /3.sw/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/3.sw/README.md -------------------------------------------------------------------------------- /4.build/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/4.build/README.md -------------------------------------------------------------------------------- /5.sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/Makefile -------------------------------------------------------------------------------- /5.sim/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/README.md -------------------------------------------------------------------------------- /5.sim/hex/ContDisps.hex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/hex/ContDisps.hex -------------------------------------------------------------------------------- /5.sim/images/opencologne-pcie-tb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/images/opencologne-pcie-tb.png -------------------------------------------------------------------------------- /5.sim/images/soc-cpu-vproc-stack.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/images/soc-cpu-vproc-stack.png -------------------------------------------------------------------------------- /5.sim/models/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/README.md -------------------------------------------------------------------------------- /5.sim/models/bfm_uart.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/bfm_uart.sv -------------------------------------------------------------------------------- /5.sim/models/cosim/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/README.md -------------------------------------------------------------------------------- /5.sim/models/cosim/extradefs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/extradefs.v -------------------------------------------------------------------------------- /5.sim/models/cosim/f_VProc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/f_VProc.v -------------------------------------------------------------------------------- /5.sim/models/cosim/f_mem_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/f_mem_model.v -------------------------------------------------------------------------------- /5.sim/models/cosim/include/VProc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/include/VProc.h -------------------------------------------------------------------------------- /5.sim/models/cosim/include/VProcClass.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/include/VProcClass.h -------------------------------------------------------------------------------- /5.sim/models/cosim/include/VProcIrqClass.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/include/VProcIrqClass.h -------------------------------------------------------------------------------- /5.sim/models/cosim/include/VSched_pli.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/include/VSched_pli.h -------------------------------------------------------------------------------- /5.sim/models/cosim/include/VUser.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/include/VUser.h -------------------------------------------------------------------------------- /5.sim/models/cosim/lib/libcosimlnx.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/lib/libcosimlnx.a -------------------------------------------------------------------------------- /5.sim/models/cosim/lib/libcosimwin.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/lib/libcosimwin.a -------------------------------------------------------------------------------- /5.sim/models/cosim/mem_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/mem_model.sv -------------------------------------------------------------------------------- /5.sim/models/cosim/mem_model_dpi.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/mem_model_dpi.vh -------------------------------------------------------------------------------- /5.sim/models/cosim/vprocdefs.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/vprocdefs.vh -------------------------------------------------------------------------------- /5.sim/models/cosim/vprocdpi.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/cosim/vprocdpi.vh -------------------------------------------------------------------------------- /5.sim/models/images/soc_cpu_vproc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/images/soc_cpu_vproc.png -------------------------------------------------------------------------------- /5.sim/models/pcievhost/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/README.md -------------------------------------------------------------------------------- /5.sim/models/pcievhost/images/pcie_disp_terminal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/images/pcie_disp_terminal.png -------------------------------------------------------------------------------- /5.sim/models/pcievhost/images/pcievhost_architecture.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/images/pcievhost_architecture.png -------------------------------------------------------------------------------- /5.sim/models/pcievhost/images/pcievhost_module.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/images/pcievhost_module.png -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/codec.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/codec.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/mem.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/mem.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/pci_express.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/pci_express.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/pcie.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/pcie.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/pcieModelClass.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/pcieModelClass.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/pcie_utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/pcie_utils.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/include/pcie_vhost_map.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/include/pcie_vhost_map.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/lib/libpcielnx.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/lib/libpcielnx.a -------------------------------------------------------------------------------- /5.sim/models/pcievhost/lib/libpciewin.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/lib/libpciewin.a -------------------------------------------------------------------------------- /5.sim/models/pcievhost/ltssm/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/ltssm/README.md -------------------------------------------------------------------------------- /5.sim/models/pcievhost/ltssm/ltssm.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/ltssm/ltssm.c -------------------------------------------------------------------------------- /5.sim/models/pcievhost/ltssm/ltssm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/ltssm/ltssm.h -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/headers/allheaders.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/headers/allheaders.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/headers/pcie_vhost_map.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/headers/pcie_vhost_map.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/headers/pciedispheader.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/headers/pciedispheader.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/headers/pciexpress_header.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/headers/pciexpress_header.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/headers/test_defs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/headers/test_defs.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/headers/timescale.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/headers/timescale.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/pcieVHost/pcieVHost.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/pcieVHost/pcieVHost.v -------------------------------------------------------------------------------- /5.sim/models/pcievhost/verilog/pcieVHost/pcieVHostPipex1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/pcievhost/verilog/pcieVHost/pcieVHostPipex1.v -------------------------------------------------------------------------------- /5.sim/models/rv32/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/README.md -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32_cpu_gdb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32_cpu_gdb.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32_extensions.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32_extensions.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32a_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32a_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32c_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32c_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32csr_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32csr_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32csr_cpu_hdr.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32csr_cpu_hdr.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32d_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32d_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32f_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32f_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32i_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32i_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32i_cpu_hdr.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32i_cpu_hdr.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32m_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32m_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32zba_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32zba_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32zbb_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32zbb_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32zbc_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32zbc_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/include/rv32zbs_cpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/include/rv32zbs_cpu.h -------------------------------------------------------------------------------- /5.sim/models/rv32/lib/librv32lnx.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/lib/librv32lnx.a -------------------------------------------------------------------------------- /5.sim/models/rv32/lib/librv32win.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/lib/librv32win.a -------------------------------------------------------------------------------- /5.sim/models/rv32/riscvtest/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/riscvtest/main.bin -------------------------------------------------------------------------------- /5.sim/models/rv32/riscvtest/main.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/riscvtest/main.s -------------------------------------------------------------------------------- /5.sim/models/rv32/riscvtest/rv_asm.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/riscvtest/rv_asm.sh -------------------------------------------------------------------------------- /5.sim/models/rv32/scripts/favicon.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/scripts/favicon.ico -------------------------------------------------------------------------------- /5.sim/models/rv32/scripts/icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/scripts/icon.png -------------------------------------------------------------------------------- /5.sim/models/rv32/scripts/rv32cfg.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/scripts/rv32cfg.py -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/VUserMain0.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/VUserMain0.cpp -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/VUserMain0.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/VUserMain0.h -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/getopt.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/getopt.c -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/mem_vproc_api.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/mem_vproc_api.cpp -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/mem_vproc_api.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/mem_vproc_api.h -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/rv32_cache.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/rv32_cache.cpp -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/rv32_cache.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/rv32_cache.h -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/rv32_timing_config.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/rv32_timing_config.h -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/uart.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/uart.cpp -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/uart.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/uart.h -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/vuserutils.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/vuserutils.cpp -------------------------------------------------------------------------------- /5.sim/models/rv32/usercode/vuserutils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/rv32/usercode/vuserutils.h -------------------------------------------------------------------------------- /5.sim/models/soc_cpu.VPROC.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/models/soc_cpu.VPROC.sv -------------------------------------------------------------------------------- /5.sim/stubs/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/stubs/README.md -------------------------------------------------------------------------------- /5.sim/stubs/dut_stub.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/stubs/dut_stub.v -------------------------------------------------------------------------------- /5.sim/tb.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/tb.prj -------------------------------------------------------------------------------- /5.sim/tb.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/tb.sv -------------------------------------------------------------------------------- /5.sim/usercode/VUserMain0.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/usercode/VUserMain0.cpp -------------------------------------------------------------------------------- /5.sim/usercode/VUserMain1.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/usercode/VUserMain1.cpp -------------------------------------------------------------------------------- /5.sim/usercode/VUserMain2.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/usercode/VUserMain2.cpp -------------------------------------------------------------------------------- /5.sim/vusermain.cfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/5.sim/vusermain.cfg -------------------------------------------------------------------------------- /6.litex/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/6.litex/README.md -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chili-chips-ba/openCologne-PCIE/HEAD/README.md --------------------------------------------------------------------------------