├── .github ├── scripts │ ├── breakpoint.sh │ ├── common.inc.sh │ ├── convert_dat.sh │ ├── create_merged_package.sh │ ├── gdb_test.sh │ ├── gdb_test_golden.txt │ ├── get_code_hash.sh │ ├── indexgen │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── dashboard-styles │ │ │ ├── assets │ │ │ │ ├── amber.png │ │ │ │ ├── chips-alliance-logo-mono.svg │ │ │ │ ├── emerald.png │ │ │ │ ├── ruby.png │ │ │ │ └── snow.png │ │ │ ├── gcov.css │ │ │ └── main.css │ │ ├── generate.py │ │ ├── index_redirect │ │ │ └── index.html │ │ ├── requirements.txt │ │ ├── source.template │ │ │ ├── conf.py │ │ │ ├── coverage_dashboard.md │ │ │ ├── dev.md │ │ │ ├── index.md │ │ │ ├── main.md │ │ │ └── verification_dashboard.md │ │ └── update_styles.sh │ ├── info_process_setup.sh │ ├── mapfile │ ├── openocd │ │ ├── board │ │ │ ├── caliptra-verilator-rst.cfg │ │ │ └── caliptra-verilator.cfg │ │ ├── sim-jtagdpi.cfg │ │ ├── veer-el2-rst.cfg │ │ └── veer-el2.cfg │ ├── openocd_test.sh │ ├── peripheral_access.tcl │ ├── prepare_coverage_data.sh │ ├── pytest │ │ ├── assets │ │ │ ├── arrow.svg │ │ │ └── chips-alliance-logo-mono.svg │ │ ├── bar.html │ │ ├── css │ │ │ └── styles.css │ │ ├── script │ │ │ └── script.js │ │ └── style_pytest_report.sh │ ├── requirements-coverage.txt │ ├── riscv_dv_matrix_include.py │ ├── riscv_dv_parse_testlist.py │ ├── run_regression_test.sh │ ├── run_regression_tests.sh │ ├── secrets_version │ ├── test.gdb │ └── utils.sh └── workflows │ ├── build-docs.yml │ ├── ci.yml │ ├── custom-lint.yml │ ├── gh-pages-pr-closed.yml │ ├── gh-pages-pr-comment.yml │ ├── gh-pages-pr-remove.yml │ ├── publish-webpage.yml │ ├── report-coverage.yml │ ├── test-openocd.yml │ ├── test-regression-cache-waypack.yml │ ├── test-regression-dcls.yml │ ├── test-regression-exceptions.yml │ ├── test-renode.yml │ ├── test-riscof.yml │ ├── test-riscv-dv.yml │ ├── test-uarch.yml │ ├── test-uvm.yml │ ├── test-verification.yml │ ├── verible-format.yml │ └── verible-lint.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── MAINTAINERS.md ├── README.md ├── cm.cfg ├── configs ├── README.md ├── veer.config └── veer_config_gen.py ├── design ├── dbg │ └── el2_dbg.sv ├── dec │ ├── cdecode │ ├── csrdecode_m │ ├── csrdecode_mu │ ├── decode │ ├── el2_dec.sv │ ├── el2_dec_decode_ctl.sv │ ├── el2_dec_gpr_ctl.sv │ ├── el2_dec_ib_ctl.sv │ ├── el2_dec_pmp_ctl.sv │ ├── el2_dec_tlu_ctl.sv │ └── el2_dec_trigger.sv ├── dmi │ ├── dmi_jtag_to_core_sync.v │ ├── dmi_mux.v │ ├── dmi_wrapper.v │ └── rvjtag_tap.v ├── el2_dma_ctrl.sv ├── el2_mem.sv ├── el2_pic_ctrl.sv ├── el2_pmp.sv ├── el2_veer.sv ├── el2_veer_lockstep.sv ├── el2_veer_wrapper.sv ├── exu │ ├── el2_exu.sv │ ├── el2_exu_alu_ctl.sv │ ├── el2_exu_div_ctl.sv │ └── el2_exu_mul_ctl.sv ├── flist ├── flist.formal ├── flist.lint ├── flist.questa ├── ifu │ ├── el2_ifu.sv │ ├── el2_ifu_aln_ctl.sv │ ├── el2_ifu_bp_ctl.sv │ ├── el2_ifu_compress_ctl.sv │ ├── el2_ifu_ic_mem.sv │ ├── el2_ifu_iccm_mem.sv │ ├── el2_ifu_ifc_ctl.sv │ ├── el2_ifu_mem_ctl.sv │ └── el2_ifu_tb_memread.sv ├── include │ ├── el2_dec_csr_equ_m.svh │ ├── el2_dec_csr_equ_mu.svh │ └── el2_def.sv ├── lib │ ├── ahb_to_axi4.sv │ ├── axi4_to_ahb.sv │ ├── beh_lib.sv │ ├── el2_lib.sv │ ├── el2_mem_if.sv │ ├── el2_regfile_if.sv │ └── mem_lib.sv └── lsu │ ├── el2_lsu.sv │ ├── el2_lsu_addrcheck.sv │ ├── el2_lsu_bus_buffer.sv │ ├── el2_lsu_bus_intf.sv │ ├── el2_lsu_clkdomain.sv │ ├── el2_lsu_dccm_ctl.sv │ ├── el2_lsu_dccm_mem.sv │ ├── el2_lsu_ecc.sv │ ├── el2_lsu_lsc_ctl.sv │ ├── el2_lsu_stbuf.sv │ └── el2_lsu_trigger.sv ├── docs ├── Makefile ├── RISC-V_VeeR_EL2_PRM.pdf ├── dashboard-styles │ ├── assets │ │ ├── amber.png │ │ ├── chips-alliance-logo-mono.svg │ │ ├── emerald.png │ │ ├── ruby.png │ │ └── snow.png │ ├── gcov.css │ └── main.css ├── requirements.txt ├── source │ ├── adaptations.md │ ├── build-args.md │ ├── cache.md │ ├── clocks.md │ ├── complex-ports.md │ ├── conf.py │ ├── core-control.md │ ├── csrs.md │ ├── debugging.md │ ├── dual-core-lock-step.md │ ├── errata.md │ ├── error-protection.md │ ├── img │ │ ├── 19-riscv_pmp_block_diagram.png │ │ ├── 1_1_bus2core_clock_ratio.png │ │ ├── 1_2_bus2core_clock_ratio.png │ │ ├── 1_3_bus2core_clock_ratio.png │ │ ├── 1_4_bus2core_clock_ratio.png │ │ ├── 1_5_bus2core_clock_ratio.png │ │ ├── 1_6_bus2core_clock_ratio.png │ │ ├── 1_7_bus2core_clock_ratio.png │ │ ├── 1_8_bus2core_clock_ratio.png │ │ ├── VeeR-logo-black-rgb.png │ │ ├── VeeR-logo-white-rgb.png │ │ ├── activity_states.png │ │ ├── breakpoint_timing.png │ │ ├── clock_reset_timing.png │ │ ├── clock_timing.png │ │ ├── comparator.png │ │ ├── core_complex.png │ │ ├── core_pipeline.png │ │ ├── csr_timing.png │ │ ├── dcls_block_diagram.png │ │ ├── debug_csrs.png │ │ ├── ecc_mem_diag.png │ │ ├── gateway.png │ │ ├── gateway_diagram.png │ │ ├── interrupt_chaining.png │ │ ├── logo.png │ │ ├── multicore_csr_timing.png │ │ ├── openocd-jtag.png │ │ ├── pic_diagram.png │ │ ├── riscv-dv-flow.png │ │ └── vei.png │ ├── index.md │ ├── interrupt-priority.md │ ├── interrupts.md │ ├── intro.md │ ├── memory-map.md │ ├── overview.md │ ├── performance.md │ ├── physical-memory-protection.md │ ├── power.md │ ├── simulation-debugging.md │ ├── tests.md │ ├── timers.md │ ├── tock.md │ ├── user-mode.md │ └── verification.md └── update_styles.sh ├── release-notes.md ├── testbench ├── ahb_lite_2to1_mux.sv ├── ahb_lsu_dma_bridge.sv ├── ahb_sif.sv ├── asm │ ├── bitmanip.s │ ├── cmark.c │ ├── cmark.ld │ ├── cmark.mki │ ├── cmark_dccm.ld │ ├── cmark_dccm.mki │ ├── cmark_iccm.ld │ ├── cmark_iccm.mki │ ├── common.s │ ├── crt0.s │ ├── dbus_nonblocking_load_error.s │ ├── dbus_store_error.s │ ├── dside_access_across_region_boundary.s │ ├── dside_access_region_prediction_error.s │ ├── dside_core_local_access_unmapped_address_error.s │ ├── dside_pic_access_error.s │ ├── dside_size_misaligned_access_to_non_idempotent_address.s │ ├── ebreak_ecall.s │ ├── hello_world.ld │ ├── hello_world.s │ ├── hello_world_dccm.ld │ ├── hello_world_dccm.s │ ├── hello_world_iccm.ld │ ├── hello_world_iccm.s │ ├── icache.ld │ ├── icache.s │ ├── illegal_instruction.s │ ├── infinite_loop.ld │ ├── infinite_loop.s │ ├── internal_timer_ints.s │ ├── interrupts.ld │ ├── iside_core_local_unmapped_address_error.s │ ├── iside_fetch_precise_bus_error.s │ ├── lsu_trigger_hit.s │ ├── machine_external_ints.s │ ├── machine_external_vec_ints.s │ ├── nmi_pin_assertion.s │ ├── printf.c │ └── tb.h ├── axi4_mux │ ├── arbiter.v │ ├── axi_crossbar.v │ ├── axi_crossbar_addr.v │ ├── axi_crossbar_rd.v │ ├── axi_crossbar_wr.v │ ├── axi_crossbar_wrap_2x1.v │ ├── axi_register_rd.v │ ├── axi_register_wr.v │ └── priority_encoder.v ├── axi_lsu_dma_bridge.sv ├── dasm.svi ├── flist ├── hex │ ├── user_mode0 │ │ ├── bitmanip.hex │ │ ├── clk_override.hex │ │ ├── cmark.hex │ │ ├── cmark_dccm.hex │ │ ├── cmark_iccm.hex │ │ ├── core_pause.hex │ │ ├── csr_access.hex │ │ ├── csr_misa.hex │ │ ├── csr_mstatus.hex │ │ ├── dbus_nonblocking_load_error.hex │ │ ├── dbus_store_error.hex │ │ ├── dhry.hex │ │ ├── dside_access_across_region_boundary.hex │ │ ├── dside_access_region_prediction_error.hex │ │ ├── dside_core_local_access_unmapped_address_error.hex │ │ ├── dside_pic_access_error.hex │ │ ├── dside_size_misaligned_access_to_non_idempotent_address.hex │ │ ├── ebreak_ecall.hex │ │ ├── ecc.hex │ │ ├── hello_world.hex │ │ ├── hello_world_dccm.hex │ │ ├── hello_world_iccm.hex │ │ ├── icache.hex │ │ ├── illegal_instruction.hex │ │ ├── infinite_loop.hex │ │ ├── insns.hex │ │ ├── internal_timer_ints.hex │ │ ├── irq.hex │ │ ├── iside_core_local_unmapped_address_error.hex │ │ ├── iside_fetch_precise_bus_error.hex │ │ ├── lsu_trigger_hit.hex │ │ ├── machine_external_ints.hex │ │ ├── machine_external_vec_ints.hex │ │ ├── modesw.hex │ │ ├── nmi_pin_assertion.hex │ │ ├── perf_counters.hex │ │ ├── pmp.hex │ │ ├── pmp_random.hex │ │ └── write_unaligned.hex │ └── user_mode1 │ │ ├── bitmanip.hex │ │ ├── clk_override.hex │ │ ├── cmark.hex │ │ ├── cmark_dccm.hex │ │ ├── cmark_iccm.hex │ │ ├── core_pause.hex │ │ ├── csr_access.hex │ │ ├── csr_misa.hex │ │ ├── csr_mseccfg.hex │ │ ├── csr_mstatus.hex │ │ ├── dbus_nonblocking_load_error.hex │ │ ├── dbus_store_error.hex │ │ ├── dhry.hex │ │ ├── dside_access_across_region_boundary.hex │ │ ├── dside_access_region_prediction_error.hex │ │ ├── dside_core_local_access_unmapped_address_error.hex │ │ ├── dside_pic_access_error.hex │ │ ├── dside_size_misaligned_access_to_non_idempotent_address.hex │ │ ├── ebreak_ecall.hex │ │ ├── ecc.hex │ │ ├── hello_world.hex │ │ ├── hello_world_dccm.hex │ │ ├── hello_world_iccm.hex │ │ ├── icache.hex │ │ ├── illegal_instruction.hex │ │ ├── infinite_loop.hex │ │ ├── insns.hex │ │ ├── internal_timer_ints.hex │ │ ├── irq.hex │ │ ├── iside_core_local_unmapped_address_error.hex │ │ ├── iside_fetch_precise_bus_error.hex │ │ ├── lsu_trigger_hit.hex │ │ ├── machine_external_ints.hex │ │ ├── machine_external_vec_ints.hex │ │ ├── modesw.hex │ │ ├── nmi_pin_assertion.hex │ │ ├── perf_counters.hex │ │ ├── pmp.hex │ │ ├── pmp_random.hex │ │ └── write_unaligned.hex ├── icache_macros.svh ├── input.tcl ├── jtagdpi │ ├── README.md │ ├── jtagdpi.c │ ├── jtagdpi.h │ └── jtagdpi.sv ├── link.ld ├── openocd_scripts │ ├── common.tcl │ ├── jtag_cg.tcl │ ├── sim-jtagdpi.cfg │ ├── veer-el2-rst.cfg │ └── verilator-rst.cfg ├── tb_top.sv ├── tb_top_pkg.sv ├── tcp_server │ ├── tcp_server.c │ └── tcp_server.h ├── test_tb_top.cpp ├── tests │ ├── clk_override │ │ ├── clk_override.c │ │ ├── clk_override.ld │ │ ├── clk_override.mki │ │ ├── crt0.s │ │ └── printf.c │ ├── core_pause │ │ ├── core_pause.c │ │ ├── core_pause.ld │ │ ├── core_pause.mki │ │ ├── crt0.s │ │ └── printf.c │ ├── csr_access │ │ ├── crt0.s │ │ ├── csr_access.c │ │ ├── csr_access.ld │ │ ├── csr_access.mki │ │ └── veer.c │ ├── csr_misa │ │ ├── crt0.s │ │ ├── csr_misa.c │ │ ├── csr_misa.ld │ │ ├── csr_misa.mki │ │ └── printf.c │ ├── csr_mseccfg │ │ ├── crt0.s │ │ ├── csr_mseccfg.c │ │ ├── csr_mseccfg.ld │ │ ├── csr_mseccfg.mki │ │ └── printf.c │ ├── csr_mstatus │ │ ├── crt0.s │ │ ├── csr_mstatus.c │ │ ├── csr_mstatus.ld │ │ ├── csr_mstatus.mki │ │ └── printf.c │ ├── dhry │ │ ├── crt0.s │ │ ├── dhry.h │ │ ├── dhry.mki │ │ ├── dhry_1.c │ │ ├── dhry_2.c │ │ └── printf.c │ ├── ecc │ │ ├── crt0.s │ │ ├── ecc.c │ │ ├── ecc.ld │ │ ├── ecc.mki │ │ └── printf.c │ ├── insns │ │ ├── crt0.s │ │ ├── insns.c │ │ ├── insns.ld │ │ ├── insns.mki │ │ └── printf.c │ ├── irq │ │ ├── crt0.s │ │ ├── irq.c │ │ ├── irq.ld │ │ ├── irq.mki │ │ └── printf.c │ ├── modesw │ │ ├── README.md │ │ ├── crt0.s │ │ ├── modesw.c │ │ ├── modesw.ld │ │ ├── modesw.mki │ │ └── printf.c │ ├── perf_counters │ │ ├── crt0.s │ │ ├── perf_counters.c │ │ ├── perf_counters.ld │ │ ├── perf_counters.mki │ │ └── veer.c │ ├── pmp │ │ ├── crt0.s │ │ ├── fault.c │ │ ├── fault.h │ │ ├── main.c │ │ ├── pmp.c │ │ ├── pmp.h │ │ ├── pmp.ld │ │ ├── pmp.mki │ │ ├── trap.h │ │ ├── veer.c │ │ └── veer.h │ ├── pmp_random │ │ ├── crt0.s │ │ ├── fault.c │ │ ├── fault.h │ │ ├── generate_random.sh │ │ ├── main.c │ │ ├── pmp.c │ │ ├── pmp.h │ │ ├── pmp_random.ld │ │ ├── pmp_random.mki │ │ ├── random_data.h │ │ ├── trap.h │ │ ├── veer.c │ │ └── veer.h │ └── write_unaligned │ │ ├── crt0.s │ │ ├── printf.c │ │ ├── write_unaligned.c │ │ ├── write_unaligned.ld │ │ └── write_unaligned.mki ├── user_cells.sv ├── uvm │ └── mem │ │ ├── .gitignore │ │ ├── Makefile │ │ └── hdl │ │ ├── dccm_agent.sv │ │ ├── dccm_base_test.sv │ │ ├── dccm_driver.sv │ │ ├── dccm_interface.sv │ │ ├── dccm_memtest.sv │ │ ├── dccm_monitor.sv │ │ ├── dccm_scoreboard.sv │ │ ├── dccm_sequence.sv │ │ ├── dccm_sequencer.sv │ │ ├── dccm_transaction_sequence_item.sv │ │ └── tbench_top.sv └── veer_wrapper.sv ├── tools ├── JSON.pm ├── Makefile ├── addassign ├── coredecode ├── hex_canned_update.sh ├── picmap ├── picolibc.mk ├── prefix_macros.sh ├── renode │ ├── README.md │ ├── build-all-tests.sh │ ├── veer.repl │ ├── veer.resc │ ├── veer.robot │ └── veer_smepmp.repl ├── riscof │ ├── README.md │ ├── config.ini │ ├── spike │ │ ├── env │ │ │ ├── link.ld │ │ │ └── model_test.h │ │ ├── riscof_spike.py │ │ ├── spike_isa.yaml │ │ └── spike_platform.yaml │ └── veer │ │ ├── env │ │ ├── link.ld │ │ └── model_test.h │ │ ├── riscof_veer.py │ │ ├── veer_isa.yaml │ │ └── veer_platform.yaml ├── riscv-dv │ ├── Makefile │ ├── README.md │ ├── code_fixup.py │ ├── riscv_core_setting.py │ ├── riscv_core_setting.sv │ ├── testlist.yaml │ ├── user_extension.svh │ ├── veer_directed_instr_lib.sv │ └── veer_log_to_trace_csv.py ├── smalldiv ├── unrollforverilator └── vivado.tcl ├── verification ├── block │ ├── .flake8 │ ├── __init__.py │ ├── common.mk │ ├── common │ │ ├── axi.py │ │ ├── csrs.py │ │ └── utils.py │ ├── config.vlt │ ├── dccm │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_lsu_dccm_mem_wrapper.sv │ │ ├── test_readwrite.py │ │ └── testbench.py │ ├── dcls │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── el2_veer_lockstep_wrapper.sv │ │ ├── test_lockstep.py │ │ └── testbench.py │ ├── dec │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── csrs.py │ │ ├── el2_dec_wrapper.sv │ │ ├── test_dec.py │ │ └── testbench.py │ ├── dec_ib │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_dec_ib_ctl_wrapper.sv │ │ ├── test_dec_ib.py │ │ └── testbench.py │ ├── dec_pmp_ctl │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── test_dec_pmp_ctl.py │ │ └── testbench.py │ ├── dec_tl │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_dec_trigger_wrapper.sv │ │ ├── test_dec_tl.py │ │ └── testbench.py │ ├── dec_tlu_ctl │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── common.py │ │ ├── csrs.py │ │ ├── el2_tlu_ctl_wrapper.sv │ │ ├── test_dec_tl.py │ │ └── testbench.py │ ├── dma │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── scoreboards.py │ │ ├── sequences.py │ │ ├── test_address.py │ │ ├── test_debug_address.py │ │ ├── test_debug_read.py │ │ ├── test_debug_write.py │ │ ├── test_ecc.py │ │ ├── test_read.py │ │ ├── test_reset.py │ │ ├── test_write.py │ │ └── testbench.py │ ├── dmi │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── common.py │ │ ├── config.vlt │ │ ├── dmi_agent.py │ │ ├── dmi_bfm.py │ │ ├── dmi_seq.py │ │ ├── dmi_test_wrapper.sv │ │ ├── jtag_agent.py │ │ ├── jtag_bfm.py │ │ ├── jtag_pkg.py │ │ ├── jtag_predictor.py │ │ ├── jtag_seq.py │ │ ├── test_dmi_read_write.py │ │ ├── test_dmi_tap_fsm.py │ │ ├── test_jtag_ir.py │ │ └── testbench.py │ ├── exu_alu │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_exu_alu_ctl_wrapper.sv │ │ ├── test_arith.py │ │ ├── test_logic.py │ │ ├── test_zba.py │ │ ├── test_zbb.py │ │ ├── test_zbp.py │ │ ├── test_zbs.py │ │ └── testbench.py │ ├── exu_div │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_exu_div_ctl_wrapper.sv │ │ ├── test_div.py │ │ └── testbench.py │ ├── exu_mul │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── config.vlt │ │ ├── el2_exu_mul_ctl_wrapper.sv │ │ ├── test_mul.py │ │ └── testbench.py │ ├── iccm │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_ifu_iccm_mem_wrapper.sv │ │ ├── test_readwrite.py │ │ └── testbench.py │ ├── ifu_compress │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── test_compress.py │ │ └── testbench.py │ ├── ifu_mem_ctl │ │ ├── Makefile │ │ ├── cm.cfg │ │ ├── common.py │ │ ├── el2_ifu_mem_ctl_wrapper.sv │ │ ├── test_err.py │ │ ├── test_err_stop.py │ │ └── test_miss.py │ ├── lib_ahb_to_axi4 │ │ ├── Makefile │ │ ├── ahb_to_axi4_wrapper.sv │ │ ├── test_read.py │ │ ├── test_write.py │ │ ├── testbench.py │ │ └── ucli.key │ ├── lib_axi4_to_ahb │ │ ├── Makefile │ │ ├── ahb_lite_agent.py │ │ ├── ahb_lite_bfm.py │ │ ├── ahb_lite_pkg.py │ │ ├── ahb_lite_seq.py │ │ ├── axi_pkg.py │ │ ├── axi_r_agent.py │ │ ├── axi_r_bfm.py │ │ ├── axi_r_seq.py │ │ ├── axi_w_agent.py │ │ ├── axi_w_bfm.py │ │ ├── axi_w_seq.py │ │ ├── cm.cfg │ │ ├── common.py │ │ ├── coordinator_seq.py │ │ ├── test_axi.py │ │ ├── test_axi_read_channel.py │ │ ├── test_axi_read_channel_multiple.py │ │ ├── test_axi_write_channel.py │ │ ├── testbench.py │ │ └── ucli.key │ ├── lsu_tl │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_lsu_trigger_wrapper.sv │ │ ├── test_lsu_tl.py │ │ └── testbench.py │ ├── noxfile.py │ ├── pic │ │ ├── Makefile │ │ ├── test_clken.py │ │ ├── test_config.py │ │ ├── test_pending.py │ │ ├── test_prioritization.py │ │ ├── test_reset.py │ │ ├── test_servicing.py │ │ └── testbench.py │ ├── pic_gw │ │ ├── Makefile │ │ └── test_gateway.py │ ├── pmp │ │ ├── Makefile │ │ ├── common.py │ │ ├── config.vlt │ │ ├── el2_pmp_wrapper.sv │ │ ├── test_address_matching.py │ │ ├── test_multiple_configs.py │ │ ├── test_xwr_access.py │ │ └── testbench.py │ ├── pmp_random │ │ ├── Makefile │ │ ├── config.vlt │ │ ├── el2_pmp_wrapper.sv │ │ ├── test_pmp_random.py │ │ └── testbench.py │ ├── pyproject.toml │ └── requirements.txt ├── test_debug │ └── test_debug.py └── top │ ├── README.md │ ├── requirements.txt │ └── test_pyuvm │ ├── Makefile │ ├── __init__.py │ ├── cm.cfg │ ├── conftest.py │ ├── test_irq │ ├── irq_utils.py │ ├── irq_uvm.py │ └── test_irq.py │ └── test_pyuvm.py └── violations.waiver /.github/scripts/breakpoint.sh: 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