├── verification ├── block │ ├── __init__.py │ ├── lib_ahb_to_axi4 │ │ ├── ucli.key │ │ └── Makefile │ ├── lib_axi4_to_ahb │ │ ├── ucli.key │ │ ├── cm.cfg │ │ ├── Makefile │ │ ├── test_axi_write_channel.py │ │ ├── test_axi.py │ │ ├── test_axi_read_channel.py │ │ └── ahb_lite_pkg.py │ ├── dec │ │ ├── csrs.py │ │ └── Makefile │ ├── dec_tlu_ctl │ │ ├── csrs.py │ │ ├── Makefile │ │ └── common.py │ ├── pmp │ │ ├── config.vlt │ │ ├── Makefile │ │ ├── el2_pmp_wrapper.sv │ │ └── common.py │ ├── pmp_random │ │ ├── config.vlt │ │ ├── Makefile │ │ └── el2_pmp_wrapper.sv │ ├── dec_ib │ │ ├── config.vlt │ │ ├── Makefile │ │ └── test_dec_ib.py │ ├── dmi │ │ ├── cm.cfg │ │ ├── config.vlt │ │ ├── Makefile │ │ ├── jtag_pkg.py │ │ ├── test_jtag_ir.py │ │ ├── dmi_agent.py │ │ ├── common.py │ │ └── jtag_agent.py │ ├── ifu_mem_ctl │ │ ├── cm.cfg │ │ └── Makefile │ ├── dec_tl │ │ ├── config.vlt │ │ ├── Makefile │ │ ├── test_dec_tl.py │ │ └── el2_dec_trigger_wrapper.sv │ ├── lsu_tl │ │ ├── config.vlt │ │ ├── Makefile │ │ └── test_lsu_tl.py │ ├── dma │ │ ├── cm.cfg │ │ ├── Makefile │ │ ├── test_reset.py │ │ ├── test_address.py │ │ └── test_debug_address.py │ ├── exu_alu │ │ ├── config.vlt │ │ ├── Makefile │ │ ├── test_arith.py │ │ ├── test_zbp.py │ │ ├── test_logic.py │ │ └── test_zba.py │ ├── exu_div │ │ ├── config.vlt │ │ ├── Makefile │ │ ├── el2_exu_div_ctl_wrapper.sv │ │ └── test_div.py │ ├── exu_mul │ │ ├── config.vlt │ │ ├── cm.cfg │ │ ├── Makefile │ │ └── test_mul.py │ ├── requirements.txt │ ├── dccm │ │ ├── config.vlt │ │ └── Makefile │ ├── iccm │ │ ├── config.vlt │ │ └── Makefile │ ├── pic │ │ ├── Makefile │ │ └── test_reset.py │ ├── pyproject.toml │ ├── pic_gw │ │ └── Makefile │ ├── .flake8 │ ├── ifu_compress │ │ ├── Makefile │ │ ├── test_compress.py │ │ └── cm.cfg │ └── dec_pmp_ctl │ │ └── Makefile ├── top │ ├── test_pyuvm │ │ ├── __init__.py │ │ ├── test_irq │ │ │ └── test_irq.py │ │ ├── test_pyuvm.py │ │ └── conftest.py │ └── requirements.txt └── test_debug │ └── test_debug.py ├── .github ├── scripts │ ├── secrets_version │ ├── indexgen │ │ ├── .gitignore │ │ ├── source.template │ │ │ ├── index.md │ │ │ ├── main.md │ │ │ ├── dev.md │ │ │ ├── verification_dashboard.md │ │ │ └── coverage_dashboard.md │ │ ├── dashboard-styles │ │ │ ├── assets │ │ │ │ ├── ruby.png │ │ │ │ ├── snow.png │ │ │ │ ├── amber.png │ │ │ │ └── emerald.png │ │ │ └── main.css │ │ ├── index_redirect │ │ │ └── index.html │ │ ├── requirements.txt │ │ └── Makefile │ ├── pytest │ │ ├── script │ │ │ └── script.js │ │ ├── assets │ │ │ └── arrow.svg │ │ ├── bar.html │ │ └── style_pytest_report.sh │ ├── requirements-coverage.txt │ ├── openocd │ │ ├── board │ │ │ ├── caliptra-verilator.cfg │ │ │ └── caliptra-verilator-rst.cfg │ │ ├── sim-jtagdpi.cfg │ │ └── veer-el2-rst.cfg │ ├── convert_dat.sh │ ├── info_process_setup.sh │ ├── get_code_hash.sh │ ├── common.inc.sh │ ├── breakpoint.sh │ ├── riscv_dv_parse_testlist.py │ ├── create_merged_package.sh │ └── riscv_dv_matrix_include.py └── workflows │ ├── gh-pages-pr-closed.yml │ ├── verible-format.yml │ ├── verible-lint.yml │ ├── custom-lint.yml │ ├── build-docs.yml │ ├── test-renode.yml │ ├── test-uvm.yml │ └── gh-pages-pr-comment.yml ├── testbench ├── asm │ ├── cmark.ld │ ├── cmark_dccm.mki │ ├── interrupts.ld │ ├── cmark_dccm.ld │ ├── hello_world_dccm.s │ ├── cmark_iccm.mki │ ├── read_after_read.mki │ ├── cmark.mki │ ├── icache.ld │ ├── illegal_instruction.s │ ├── tb.h │ ├── nmi_pin_assertion.s │ ├── hello_world.ld │ ├── read_after_read.ld │ ├── infinite_loop.ld │ ├── hello_world_iccm.ld │ ├── iside_core_local_unmapped_address_error.s │ ├── ebreak_ecall.s │ ├── hello_world_dccm.ld │ ├── dbus_nonblocking_load_error.s │ ├── lsu_trigger_hit.s │ ├── iside_fetch_precise_bus_error.s │ ├── dbus_store_error.s │ ├── cmark_iccm.ld │ ├── dside_pic_access_error.s │ ├── dside_access_across_region_boundary.s │ ├── dside_access_region_prediction_error.s │ ├── dside_core_local_access_unmapped_address_error.s │ ├── machine_external_ints.s │ ├── dside_size_misaligned_access_to_non_idempotent_address.s │ ├── internal_timer_ints.s │ ├── infinite_loop.s │ ├── icache.s │ ├── crt0.s │ └── common.s ├── tests │ ├── dhry │ │ ├── crt0.s │ │ ├── printf.c │ │ └── dhry.mki │ ├── ecc │ │ ├── printf.c │ │ ├── ecc.mki │ │ ├── ecc.ld │ │ └── crt0.s │ ├── insns │ │ ├── printf.c │ │ ├── insns.mki │ │ └── insns.ld │ ├── irq │ │ ├── printf.c │ │ ├── irq.mki │ │ └── irq.ld │ ├── pmp_random │ │ ├── crt0.s │ │ ├── fault.c │ │ ├── fault.h │ │ ├── pmp.c │ │ ├── pmp.h │ │ ├── trap.h │ │ ├── veer.c │ │ ├── veer.h │ │ ├── pmp_random.ld │ │ ├── pmp_random.mki │ │ └── generate_random.sh │ ├── core_pause │ │ ├── printf.c │ │ ├── core_pause.mki │ │ ├── core_pause.ld │ │ ├── core_pause.c │ │ └── crt0.s │ ├── csr_misa │ │ ├── printf.c │ │ ├── csr_misa.mki │ │ ├── csr_misa.ld │ │ ├── crt0.s │ │ └── csr_misa.c │ ├── modesw │ │ ├── printf.c │ │ ├── modesw.mki │ │ └── modesw.ld │ ├── clk_override │ │ ├── printf.c │ │ ├── clk_override.mki │ │ ├── clk_override.ld │ │ ├── clk_override.c │ │ └── crt0.s │ ├── csr_mseccfg │ │ ├── printf.c │ │ ├── csr_mseccfg.mki │ │ ├── csr_mseccfg.ld │ │ └── crt0.s │ ├── csr_mstatus │ │ ├── printf.c │ │ ├── csr_mstatus.mki │ │ ├── csr_mstatus.ld │ │ └── crt0.s │ ├── write_unaligned │ │ ├── printf.c │ │ ├── write_unaligned.mki │ │ ├── write_unaligned.ld │ │ ├── crt0.s │ │ └── write_unaligned.c │ ├── pmp │ │ ├── pmp.mki │ │ ├── pmp.ld │ │ ├── fault.h │ │ ├── fault.c │ │ ├── veer.h │ │ └── pmp.h │ ├── csr_access │ │ ├── csr_access.mki │ │ ├── csr_access.ld │ │ └── veer.c │ └── perf_counters │ │ ├── perf_counters.mki │ │ ├── perf_counters.ld │ │ └── veer.c ├── uvm │ └── mem │ │ ├── .gitignore │ │ └── hdl │ │ ├── dccm_interface.sv │ │ ├── dccm_sequencer.sv │ │ ├── dccm_memtest.sv │ │ ├── dccm_transaction_sequence_item.sv │ │ ├── dccm_agent.sv │ │ ├── dccm_sequence.sv │ │ ├── dccm_base_test.sv │ │ ├── dccm_driver.sv │ │ └── dccm_monitor.sv ├── openocd_scripts │ ├── verilator-rst.cfg │ ├── sim-jtagdpi.cfg │ ├── veer-el2-rst.cfg │ └── common.tcl ├── input.tcl ├── hex │ ├── user_mode0 │ │ ├── infinite_loop.hex │ │ ├── icache.hex │ │ ├── core_pause.hex │ │ ├── clk_override.hex │ │ ├── bitmanip.hex │ │ ├── hello_world.hex │ │ ├── hello_world_dccm.hex │ │ └── hello_world_iccm.hex │ └── user_mode1 │ │ ├── infinite_loop.hex │ │ ├── icache.hex │ │ ├── core_pause.hex │ │ ├── clk_override.hex │ │ ├── bitmanip.hex │ │ ├── hello_world.hex │ │ ├── hello_world_dccm.hex │ │ └── hello_world_iccm.hex ├── link.ld ├── jtagdpi │ ├── README.md │ └── jtagdpi.sv └── user_cells.sv ├── docs ├── source │ ├── img │ │ ├── logo.png │ │ ├── vei.png │ │ ├── gateway.png │ │ ├── clock_timing.png │ │ ├── comparator.png │ │ ├── core_complex.png │ │ ├── csr_timing.png │ │ ├── debug_csrs.png │ │ ├── ecc_mem_diag.png │ │ ├── openocd-jtag.png │ │ ├── pic_diagram.png │ │ ├── core_pipeline.png │ │ ├── riscv-dv-flow.png │ │ ├── activity_states.png │ │ ├── breakpoint_timing.png │ │ ├── gateway_diagram.png │ │ ├── VeeR-logo-black-rgb.png │ │ ├── VeeR-logo-white-rgb.png │ │ ├── clock_reset_timing.png │ │ ├── dcls_block_diagram.png │ │ ├── interrupt_chaining.png │ │ ├── multicore_csr_timing.png │ │ ├── 1_1_bus2core_clock_ratio.png │ │ ├── 1_2_bus2core_clock_ratio.png │ │ ├── 1_3_bus2core_clock_ratio.png │ │ ├── 1_4_bus2core_clock_ratio.png │ │ ├── 1_5_bus2core_clock_ratio.png │ │ ├── 1_6_bus2core_clock_ratio.png │ │ ├── 1_7_bus2core_clock_ratio.png │ │ ├── 1_8_bus2core_clock_ratio.png │ │ └── 19-riscv_pmp_block_diagram.png │ ├── index.md │ ├── interrupt-priority.md │ ├── errata.md │ └── conf.py ├── requirements.txt ├── RISC-V_VeeR_EL2_PRM.pdf ├── dashboard-styles │ ├── assets │ │ ├── ruby.png │ │ ├── snow.png │ │ ├── amber.png │ │ └── emerald.png │ └── main.css └── Makefile ├── MAINTAINERS.md ├── tools ├── riscof │ ├── spike │ │ ├── spike_platform.yaml │ │ ├── env │ │ │ └── link.ld │ │ └── spike_isa.yaml │ ├── veer │ │ ├── veer_platform.yaml │ │ ├── env │ │ │ └── link.ld │ │ └── veer_isa.yaml │ └── config.ini ├── vivado.tcl ├── renode │ ├── veer.repl │ ├── veer_smepmp.repl │ ├── build-all-tests.sh │ └── veer.resc ├── riscv-dv │ ├── user_extension.svh │ └── veer_directed_instr_lib.sv ├── addassign ├── picmap ├── hex_canned_update.sh └── picolibc.mk ├── .gitmodules ├── .gitignore ├── violations.waiver └── configs └── veer_config_gen.py /verification/block/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.github/scripts/secrets_version: -------------------------------------------------------------------------------- 1 | 3 2 | -------------------------------------------------------------------------------- /testbench/asm/cmark.ld: -------------------------------------------------------------------------------- 1 | hello_world.ld -------------------------------------------------------------------------------- /testbench/asm/cmark_dccm.mki: -------------------------------------------------------------------------------- 1 | cmark.mki -------------------------------------------------------------------------------- /testbench/asm/interrupts.ld: -------------------------------------------------------------------------------- 1 | hello_world.ld -------------------------------------------------------------------------------- /testbench/tests/dhry/crt0.s: -------------------------------------------------------------------------------- 1 | ../../asm/crt0.s -------------------------------------------------------------------------------- /verification/block/lib_ahb_to_axi4/ucli.key: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/ucli.key: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /verification/top/test_pyuvm/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /testbench/asm/cmark_dccm.ld: -------------------------------------------------------------------------------- 1 | hello_world_dccm.ld -------------------------------------------------------------------------------- /testbench/asm/hello_world_dccm.s: -------------------------------------------------------------------------------- 1 | hello_world.s -------------------------------------------------------------------------------- /testbench/tests/dhry/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/ecc/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/insns/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/irq/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/pmp_random/crt0.s: -------------------------------------------------------------------------------- 1 | ../pmp/crt0.s -------------------------------------------------------------------------------- /testbench/tests/pmp_random/fault.c: -------------------------------------------------------------------------------- 1 | ../pmp/fault.c -------------------------------------------------------------------------------- /testbench/tests/pmp_random/fault.h: -------------------------------------------------------------------------------- 1 | ../pmp/fault.h -------------------------------------------------------------------------------- /testbench/tests/pmp_random/pmp.c: -------------------------------------------------------------------------------- 1 | ../pmp/pmp.c -------------------------------------------------------------------------------- /testbench/tests/pmp_random/pmp.h: -------------------------------------------------------------------------------- 1 | ../pmp/pmp.h -------------------------------------------------------------------------------- /testbench/tests/pmp_random/trap.h: -------------------------------------------------------------------------------- 1 | ../pmp/trap.h -------------------------------------------------------------------------------- /testbench/tests/pmp_random/veer.c: -------------------------------------------------------------------------------- 1 | ../pmp/veer.c -------------------------------------------------------------------------------- /testbench/tests/pmp_random/veer.h: -------------------------------------------------------------------------------- 1 | ../pmp/veer.h -------------------------------------------------------------------------------- /verification/block/dec/csrs.py: -------------------------------------------------------------------------------- 1 | ../common/csrs.py -------------------------------------------------------------------------------- /testbench/tests/core_pause/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/csr_misa/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/modesw/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/pmp_random/pmp_random.ld: -------------------------------------------------------------------------------- 1 | ../pmp/pmp.ld -------------------------------------------------------------------------------- /.github/scripts/indexgen/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | source 3 | -------------------------------------------------------------------------------- /testbench/tests/clk_override/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/csr_mseccfg/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/csr_mstatus/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /testbench/tests/write_unaligned/printf.c: -------------------------------------------------------------------------------- 1 | ../../asm/printf.c -------------------------------------------------------------------------------- /verification/block/dec_tlu_ctl/csrs.py: -------------------------------------------------------------------------------- 1 | ../common/csrs.py -------------------------------------------------------------------------------- /testbench/uvm/mem/.gitignore: -------------------------------------------------------------------------------- 1 | *-sim 2 | snapshots 3 | *.vcd 4 | *.fst 5 | uvm 6 | -------------------------------------------------------------------------------- /testbench/tests/ecc/ecc.mki: -------------------------------------------------------------------------------- 1 | OFILES = crt0.o ecc.o printf.o 2 | TEST_CFLAGS = -g -O3 3 | -------------------------------------------------------------------------------- /.github/scripts/pytest/script/script.js: -------------------------------------------------------------------------------- 1 | function previousPage() { 2 | window.history.back() 3 | } 4 | -------------------------------------------------------------------------------- /testbench/tests/dhry/dhry.mki: -------------------------------------------------------------------------------- 1 | OFILES = crt0.o dhry_1.o dhry_2.o printf.o 2 | TEST_CFLAGS = -g -O3 3 | -------------------------------------------------------------------------------- /docs/source/img/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/logo.png -------------------------------------------------------------------------------- /docs/source/img/vei.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/vei.png -------------------------------------------------------------------------------- /testbench/asm/cmark_iccm.mki: -------------------------------------------------------------------------------- 1 | TEST_CFLAGS = -g -O3 -funroll-all-loops 2 | OFILES = crt0.o printf.o cmark.o 3 | -------------------------------------------------------------------------------- /testbench/openocd_scripts/verilator-rst.cfg: -------------------------------------------------------------------------------- 1 | source [find sim-jtagdpi.cfg] 2 | source [find veer-el2-rst.cfg] 3 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/cm.cfg: -------------------------------------------------------------------------------- 1 | +tree * 2 | 3 | -node axi4_to_ahb.ahb_hprot[3:1] // Tied to 3'001 4 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | Sphinx>=8.0.2,<9 2 | https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip 3 | -------------------------------------------------------------------------------- /docs/source/img/gateway.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /verification/block/pmp/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_pmp_wrapper.sv" 4 | -------------------------------------------------------------------------------- /docs/source/img/clock_timing.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/clock_timing.png -------------------------------------------------------------------------------- /docs/source/img/comparator.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/comparator.png -------------------------------------------------------------------------------- /docs/source/img/core_complex.png: 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-------------------------------------------------------------------------------- /.github/scripts/requirements-coverage.txt: -------------------------------------------------------------------------------- 1 | git+https://github.com/antmicro/sitespawner@abff708256a15a5db7c498ff7f484c78cf18d4e3 2 | -------------------------------------------------------------------------------- /docs/source/img/core_pipeline.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/core_pipeline.png -------------------------------------------------------------------------------- /docs/source/img/riscv-dv-flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/riscv-dv-flow.png -------------------------------------------------------------------------------- /verification/block/dec_ib/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl_wrapper.sv" 4 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/source.template/index.md: -------------------------------------------------------------------------------- 1 | # {{ project }} 2 | 3 | ```{toctree} 4 | :maxdepth: 2 5 | 6 | main 7 | dev 8 | ``` 9 | -------------------------------------------------------------------------------- /docs/dashboard-styles/assets/ruby.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/dashboard-styles/assets/ruby.png -------------------------------------------------------------------------------- /docs/dashboard-styles/assets/snow.png: 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https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/1_5_bus2core_clock_ratio.png -------------------------------------------------------------------------------- /docs/source/img/1_6_bus2core_clock_ratio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/1_6_bus2core_clock_ratio.png -------------------------------------------------------------------------------- /docs/source/img/1_7_bus2core_clock_ratio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/1_7_bus2core_clock_ratio.png -------------------------------------------------------------------------------- /docs/source/img/1_8_bus2core_clock_ratio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/1_8_bus2core_clock_ratio.png -------------------------------------------------------------------------------- /testbench/input.tcl: -------------------------------------------------------------------------------- 1 | database -open waves -into waves.shm -default 2 | probe -create tb_top -depth all -database waves -memories -all 3 | run 4 | exit 5 | -------------------------------------------------------------------------------- /docs/source/img/19-riscv_pmp_block_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/docs/source/img/19-riscv_pmp_block_diagram.png -------------------------------------------------------------------------------- /testbench/asm/cmark.mki: -------------------------------------------------------------------------------- 1 | TEST_CFLAGS = -finline-limit=400 -mbranch-cost=1 -Ofast -fno-code-hoisting -funroll-all-loops 2 | OFILES = crt0.o printf.o cmark.o 3 | -------------------------------------------------------------------------------- /testbench/tests/irq/irq.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o irq.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /testbench/tests/insns/insns.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o insns.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /testbench/tests/modesw/modesw.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o modesw.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /verification/block/ifu_mem_ctl/cm.cfg: -------------------------------------------------------------------------------- 1 | +tree el2_ifu_mem_ctl_wrapper.ifu_mem_ctl 2 | 3 | // Tied to '0 4 | -node el2_ifu_mem_ctl_wrapper.ifu_mem_ctl.ifu_axi_araddr[2:0] -------------------------------------------------------------------------------- /testbench/tests/csr_misa/csr_misa.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o csr_misa.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/dashboard-styles/assets/ruby.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/.github/scripts/indexgen/dashboard-styles/assets/ruby.png -------------------------------------------------------------------------------- /.github/scripts/indexgen/dashboard-styles/assets/snow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/.github/scripts/indexgen/dashboard-styles/assets/snow.png -------------------------------------------------------------------------------- /testbench/tests/core_pause/core_pause.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o core_pause.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /testbench/tests/csr_access/csr_access.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o csr_access.o veer.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/dashboard-styles/assets/amber.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/.github/scripts/indexgen/dashboard-styles/assets/amber.png -------------------------------------------------------------------------------- /testbench/tests/clk_override/clk_override.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o clk_override.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /testbench/tests/csr_mseccfg/csr_mseccfg.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o csr_mseccfg.o printf.o 4 | TEST_CFLAGS = -g -O0 -falign-functions=16 5 | -------------------------------------------------------------------------------- /testbench/tests/csr_mstatus/csr_mstatus.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o csr_mstatus.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /testbench/tests/perf_counters/perf_counters.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o perf_counters.o veer.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/dashboard-styles/assets/emerald.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/Cores-VeeR-EL2/HEAD/.github/scripts/indexgen/dashboard-styles/assets/emerald.png -------------------------------------------------------------------------------- /testbench/asm/icache.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | .text : { *(.text*) } 6 | . = 0x10000; 7 | .data : { *(.*data) *(.rodata*)} 8 | } 9 | -------------------------------------------------------------------------------- /verification/block/dmi/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/dmi_test_wrapper.sv" 4 | 5 | lint_off -rule UNUSEDPARAM -file "*/dmi_test_wrapper.sv" 6 | -------------------------------------------------------------------------------- /MAINTAINERS.md: -------------------------------------------------------------------------------- 1 | # Maintainers 2 | 3 | * [Maciej Kurc](https://github.com/mkurc-ant) 4 | * [Tomasz Michalak](https://github.com/tmichalak) 5 | * [Karol Gugala](https://github.com/kgugala) 6 | -------------------------------------------------------------------------------- /testbench/tests/write_unaligned/write_unaligned.mki: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | OFILES = crt0.o write_unaligned.o printf.o 4 | TEST_CFLAGS = -g -O3 -falign-functions=16 5 | -------------------------------------------------------------------------------- /.github/scripts/openocd/board/caliptra-verilator.cfg: -------------------------------------------------------------------------------- 1 | source [find sim-jtagdpi.cfg] 2 | source [find veer-el2.cfg] 3 | 4 | # Increase timeouts in simulation 5 | riscv set_command_timeout_sec 300 6 | -------------------------------------------------------------------------------- /verification/block/dec_tl/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger_wrapper.sv" 4 | 5 | lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger_wrapper.sv" 6 | -------------------------------------------------------------------------------- /verification/block/lsu_tl/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_lsu_trigger_wrapper.sv" 4 | 5 | lint_off -rule UNUSEDPARAM -file "*/el2_lsu_trigger_wrapper.sv" 6 | -------------------------------------------------------------------------------- /.github/scripts/openocd/board/caliptra-verilator-rst.cfg: -------------------------------------------------------------------------------- 1 | source [find sim-jtagdpi.cfg] 2 | source [find veer-el2-rst.cfg] 3 | 4 | # Increase timeouts in simulation 5 | riscv set_command_timeout_sec 300 6 | -------------------------------------------------------------------------------- /verification/block/dma/cm.cfg: -------------------------------------------------------------------------------- 1 | +tree el2_dma_ctrl 2 | 3 | // 'start_addr' and 'region' are tied to module parameters 4 | -node el2_dma_ctrl.*rangecheck.start_addr 5 | -node el2_dma_ctrl.*rangecheck.region 6 | -------------------------------------------------------------------------------- /verification/block/exu_alu/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl_wrapper.sv" 4 | 5 | lint_off -rule UNUSEDPARAM -file "*/el2_exu_alu_ctl_wrapper.sv" 6 | -------------------------------------------------------------------------------- /verification/block/exu_div/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl_wrapper.sv" 4 | 5 | lint_off -rule UNUSEDPARAM -file "*/el2_exu_div_ctl_wrapper.sv" 6 | -------------------------------------------------------------------------------- /verification/block/exu_mul/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl_wrapper.sv" 4 | 5 | lint_off -rule UNUSEDPARAM -file "*/el2_exu_mul_ctl_wrapper.sv" 6 | -------------------------------------------------------------------------------- /verification/block/exu_mul/cm.cfg: -------------------------------------------------------------------------------- 1 | +tree el2_exu_mul_ctl_wrapper.mul 2 | 3 | -node el2_exu_mul_ctl_wrapper.mul.crc32_poly_rev // Tied to 32'hEDB88320 4 | -node el2_exu_mul_ctl_wrapper.mul.crc32c_poly_rev // Tied to 32'h82F63B78 5 | -------------------------------------------------------------------------------- /tools/riscof/spike/spike_platform.yaml: -------------------------------------------------------------------------------- 1 | mtime: 2 | implemented: true 3 | address: 0xbff8 4 | mtimecmp: 5 | implemented: true 6 | address: 0x4000 7 | nmi: 8 | label: nmi_vector 9 | reset: 10 | label: reset_vector 11 | -------------------------------------------------------------------------------- /tools/riscof/veer/veer_platform.yaml: -------------------------------------------------------------------------------- 1 | mtime: 2 | implemented: true 3 | address: 0xbff8 4 | mtimecmp: 5 | implemented: true 6 | address: 0x4000 7 | nmi: 8 | label: nmi_vector 9 | reset: 10 | label: reset_vector 11 | -------------------------------------------------------------------------------- /tools/vivado.tcl: -------------------------------------------------------------------------------- 1 | set_property is_global_include true [get_files config/common_defines.vh] 2 | set_property is_global_include true [get_files config/el2_pdef.vh] 3 | set_property file_type SystemVerilog [get_files config/el2_pdef.vh] 4 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/source.template/main.md: -------------------------------------------------------------------------------- 1 | # Main branch 2 | 3 | * [Coverage](main_coverage_dashboard) 4 | * [Verification tests](main_verification_dashboard) 5 | * [Documentation](external:main/docs_rendered/html/index.html) 6 | -------------------------------------------------------------------------------- /testbench/asm/illegal_instruction.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | illegal_instruction: 4 | li x4, 0x2 5 | li x5, 0x0 6 | .word 0 7 | j fail_if_not_serviced 8 | 9 | main: 10 | call illegal_instruction 11 | j _finish -------------------------------------------------------------------------------- /testbench/hex/user_mode0/infinite_loop.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | B7 50 55 5F 93 80 50 55 73 90 00 7C 91 41 73 90 3 | 91 7F 01 4E 05 0E 93 0E B0 07 FD 1E E3 9F 0E FE 4 | 6F F0 5F FF 00 00 00 00 01 00 00 00 02 00 00 00 5 | 03 00 00 00 04 00 00 00 6 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/infinite_loop.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | B7 50 55 5F 93 80 50 55 73 90 00 7C 91 41 73 90 3 | 91 7F 01 4E 05 0E 93 0E B0 07 FD 1E E3 9F 0E FE 4 | 6F F0 5F FF 00 00 00 00 01 00 00 00 02 00 00 00 5 | 03 00 00 00 04 00 00 00 6 | -------------------------------------------------------------------------------- /verification/block/requirements.txt: -------------------------------------------------------------------------------- 1 | cocotb==1.8.0 2 | cocotb-bus==0.2.1 3 | cocotb-coverage==1.1.0 4 | cocotb-test==0.2.4 5 | pytest==7.4.1 6 | pytest-html==3.2.0 7 | pytest-timeout==2.1.0 8 | pytest-md==0.2.0 9 | pyuvm==2.9.1 10 | scipy==1.13.1 11 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/index_redirect/index.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /verification/block/dccm/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule PINCONNECTEMPTY -file "*/el2_lsu_dccm_mem_wrapper.sv" 4 | 5 | lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem_wrapper.sv" 6 | 7 | lint_off -rule IMPORTSTAR -file "*/el2_mem_if.sv" 8 | -------------------------------------------------------------------------------- /verification/block/iccm/config.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | lint_off -rule PINCONNECTEMPTY -file "*/el2_ifu_iccm_mem_wrapper.sv" 4 | 5 | lint_off -rule WIDTHTRUNC -file "*/el2_ifu_iccm_mem_wrapper.sv" 6 | 7 | lint_off -rule IMPORTSTAR -file "*/el2_mem_if.sv" 8 | -------------------------------------------------------------------------------- /testbench/link.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS 6 | { 7 | . = 0; 8 | .text : { *(.text*) } 9 | _end = .; 10 | . = 0x10000; 11 | .data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; } 12 | } 13 | -------------------------------------------------------------------------------- /.github/scripts/convert_dat.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | DAT_FILE="${1}" 4 | INFO_FILE="${2}" 5 | 6 | verilator_coverage --skip-toggle --write-info "${INFO_FILE}_branch.info" "${DAT_FILE}" 7 | verilator_coverage --toggle-only --write-info "${INFO_FILE}_toggle.info" "${DAT_FILE}" 8 | -------------------------------------------------------------------------------- /.github/scripts/pytest/assets/arrow.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /testbench/asm/tb.h: -------------------------------------------------------------------------------- 1 | #define STDOUT 0xd0580000 2 | 3 | #define TRIGGER_NMI 0x80 4 | #define LOAD_NMI_ADDR 0x81 5 | #define TRIGGER_SOFT_INT 0x84 6 | #define TRIGGER_TIMER_INT 0x85 7 | #define TRIGGER_EXT_INT1 0x86 8 | #define TRIGGER_DBUS_FAULT 0x87 9 | #define TRIGGER_IBUS_FAULT 0x88 10 | -------------------------------------------------------------------------------- /.github/scripts/info_process_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | apt update 6 | apt install -y git pipx 7 | 8 | # By default pipx uses `/root/.local/bin` which isn't in PATH. 9 | export PIPX_BIN_DIR=/usr/local/bin 10 | pipx install git+https://github.com/antmicro/info-process@1d1fa64f 11 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/icache.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | B7 50 55 5F 93 80 50 55 73 90 00 7C 91 41 73 90 3 | 91 7F 01 4E 13 0F 40 06 63 0A EE 01 05 0E 93 0E 4 | B0 07 FD 1E E3 9F 0E FE 6F F0 1F FF B7 01 58 D0 5 | 13 01 F0 0F 23 A0 21 00 01 00 FD BF 00 00 00 00 6 | 01 00 00 00 02 00 00 00 03 00 00 00 04 00 00 00 7 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/icache.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | B7 50 55 5F 93 80 50 55 73 90 00 7C 91 41 73 90 3 | 91 7F 01 4E 13 0F 40 06 63 0A EE 01 05 0E 93 0E 4 | B0 07 FD 1E E3 9F 0E FE 6F F0 1F FF B7 01 58 D0 5 | 13 01 F0 0F 23 A0 21 00 01 00 FD BF 00 00 00 00 6 | 01 00 00 00 02 00 00 00 03 00 00 00 04 00 00 00 7 | -------------------------------------------------------------------------------- /testbench/asm/nmi_pin_assertion.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | nmi_pin_assertion: 4 | li x4, 0x0 5 | li x5, 0x0 6 | // trigger NMI 7 | li x2, TRIGGER_NMI 8 | li x3, STDOUT 9 | sw x2, 0(x3) 10 | j fail_if_not_serviced 11 | 12 | main: 13 | call nmi_pin_assertion 14 | j _finish -------------------------------------------------------------------------------- /tools/renode/veer.repl: -------------------------------------------------------------------------------- 1 | mem: Memory.MappedMemory @sysbus 0x80000000 2 | size: 0x10000000 3 | 4 | htif_mem: Memory.MappedMemory @sysbus 0xD0580000 5 | size: 0x1000 6 | 7 | cpu: CPU.VeeR_EL2 @ sysbus 8 | hartId: 0 9 | 10 | dhry_mem: Memory.MappedMemory @sysbus 0xF0040000 11 | size: 0x10000 12 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/requirements.txt: -------------------------------------------------------------------------------- 1 | myst-parser 2 | sphinx 3 | sphinx_tabs 4 | sphinxcontrib-mermaid 5 | 6 | https://github.com/antmicro/sphinx-immaterial/releases/download/tip/sphinx_immaterial-0.0.post1.tip-py3-none-any.whl 7 | https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip 8 | 9 | jinja2 10 | -------------------------------------------------------------------------------- /verification/test_debug/test_debug.py: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2023 Antmicro 3 | # SPDX-License-Identifier: BSD-2-Clause 4 | 5 | import pytest 6 | import subprocess 7 | 8 | class TestDebug(): 9 | def test_debug(self): 10 | print("This test returns true") 11 | assert True == True 12 | -------------------------------------------------------------------------------- /testbench/asm/hello_world.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | . = 0x80000000; 6 | .text : { *(.text*) } 7 | _end = .; 8 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 9 | .bss : { *(.bss) } 10 | . = 0xd0580000; 11 | .data.io . : { *(.data.io) } 12 | } 13 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/source.template/dev.md: -------------------------------------------------------------------------------- 1 | # Active pull requests 2 | 3 | {%- for branch in branches %} 4 | * {{ branch }} 5 | * [Coverage]({{ branch }}_coverage_dashboard) 6 | * [Verification tests]({{ branch }}_verification_dashboard) 7 | * [Documentation](external:dev/{{ branch }}/docs_rendered/html/index.html) 8 | {%- endfor %} 9 | -------------------------------------------------------------------------------- /testbench/asm/read_after_read.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | . = 0x80000000; 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xc0000000; 9 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 10 | .bss : { *(.bss) } 11 | . = 0xd0580000; 12 | .data.io . : { *(.data.io) } 13 | } 14 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/core_pause.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 17 11 00 00 13 01 01 06 25 28 AA 85 13 05 F0 0F 3 | 91 C1 05 45 97 02 58 50 93 82 C2 FE 23 80 A2 00 4 | E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00 5 | 01 00 01 00 01 00 01 00 00 00 00 00 00 00 00 00 6 | 85 67 FD 17 73 90 27 7C 01 45 82 80 00 00 00 00 7 | 00 00 8 | @D0580000 9 | 00 00 00 00 10 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/core_pause.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 17 11 00 00 13 01 01 06 25 28 AA 85 13 05 F0 0F 3 | 91 C1 05 45 97 02 58 50 93 82 C2 FE 23 80 A2 00 4 | E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00 5 | 01 00 01 00 01 00 01 00 00 00 00 00 00 00 00 00 6 | 85 67 FD 17 73 90 27 7C 01 45 82 80 00 00 00 00 7 | 00 00 8 | @D0580000 9 | 00 00 00 00 10 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/source.template/verification_dashboard.md: -------------------------------------------------------------------------------- 1 | ({{ ref }})= 2 | # Verification tests dashboard 3 | 4 | ## Test reports 5 | 6 | {%- for test in tests %} 7 | * [{{ test }}](external:verification_dashboard/webpage_{{ test }}/{{ test }}.html) 8 | {%- endfor %} 9 | * [RISCOF tests report](external:verification_dashboard/riscof/report.html) 10 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "third-party/picolibc"] 2 | path = third_party/picolibc 3 | url = https://github.com/picolibc/picolibc 4 | [submodule "third_party/riscv-dv"] 5 | path = third_party/riscv-dv 6 | url = https://github.com/chipsalliance/riscv-dv 7 | [submodule "third_party/cocotb"] 8 | path = third_party/cocotb 9 | url = https://github.com/cocotb/cocotb 10 | -------------------------------------------------------------------------------- /testbench/asm/infinite_loop.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | .text : { *(.text*) } 6 | . = 0x10000; 7 | .data : { *(.*data) *(.rodata*)} 8 | . = ALIGN(4); 9 | printf_start = .; 10 | . = 0xee000000; 11 | .data_load : AT(printf_start) {*(.data_text)} 12 | printf_end = printf_start + SIZEOF(.data_load); 13 | } 14 | -------------------------------------------------------------------------------- /testbench/asm/hello_world_iccm.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | . = 0x80000000; 6 | .text : { *(.text*) } 7 | .data : { *(.*data) *(.rodata*)} 8 | . = ALIGN(4); 9 | printf_start = .; 10 | . = 0xee000000; 11 | .data_load : AT(printf_start) {*(.data_text)} 12 | printf_end = printf_start + SIZEOF(.data_load); 13 | } 14 | -------------------------------------------------------------------------------- /tools/renode/veer_smepmp.repl: -------------------------------------------------------------------------------- 1 | mem: Memory.MappedMemory @sysbus 0x80000000 2 | size: 0x10000000 3 | 4 | htif_mem: Memory.MappedMemory @sysbus 0xD0580000 5 | size: 0x1000 6 | 7 | cpu: CPU.VeeR_EL2 @ sysbus 8 | cpuType: "rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs_Smepmp" 9 | hartId: 0 10 | 11 | dhry_mem: Memory.MappedMemory @sysbus 0xF0040000 12 | size: 0x10000 13 | -------------------------------------------------------------------------------- /testbench/asm/iside_core_local_unmapped_address_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | iside_core_local_unmapped_address_error: 4 | li x4, 0x1 5 | li x5, 0x2 6 | // jump to address that's only halfway inside ICCM 7 | li x2, 0xee000000-2 8 | jalr x2, 0(x2) 9 | j fail_if_not_serviced 10 | 11 | main: 12 | call iside_core_local_unmapped_address_error 13 | j _finish -------------------------------------------------------------------------------- /testbench/asm/ebreak_ecall.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | breakpoint_ebreak: 4 | li x4, 0x3 5 | li x5, 0x2 6 | ebreak 7 | j fail_if_not_serviced 8 | 9 | environment_call_from_m_mode: 10 | li x4, 0xB 11 | li x5, 0x0 12 | ecall 13 | j fail_if_not_serviced 14 | 15 | main: 16 | call breakpoint_ebreak 17 | call environment_call_from_m_mode 18 | j _finish -------------------------------------------------------------------------------- /testbench/tests/insns/insns.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | SPHINXOPTS ?= 2 | SPHINXBUILD ?= sphinx-build 3 | SOURCEDIR = source 4 | BUILDDIR = build 5 | 6 | # Catch-all target: route all unknown targets to Sphinx using the "make mode" option. 7 | # $(O) is meant as a shortcut for $(SPHINXOPTS). 8 | %: 9 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 10 | @bash update_styles.sh "$(BUILDDIR)" 11 | 12 | -------------------------------------------------------------------------------- /testbench/tests/csr_misa/csr_misa.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /testbench/tests/modesw/modesw.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /testbench/tests/core_pause/core_pause.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /testbench/tests/csr_access/csr_access.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /testbench/tests/clk_override/clk_override.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /testbench/tests/csr_mstatus/csr_mstatus.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /testbench/tests/perf_counters/perf_counters.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | .text : { *(.text.init*) *(.text*) } 9 | _end = .; 10 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 11 | .bss : { *(.bss) } 12 | . = 0xd0580000; 13 | .data.io . : { *(.data.io) } 14 | } 15 | -------------------------------------------------------------------------------- /verification/top/requirements.txt: -------------------------------------------------------------------------------- 1 | # Installing custom cocotb due to: 2 | # cocotb scheduler incorrectly handles simulation time 3 | # when Verilator is used with flag --timing 4 | ${RV_ROOT}/third_party/cocotb 5 | # cocotb==1.7.2 6 | cocotb-bus==0.2.1 7 | cocotb-coverage==1.1.0 8 | cocotb-test==0.2.4 9 | pytest==7.4.1 10 | pytest-html==3.2.0 11 | pytest-timeout==2.1.0 12 | pytest-md==0.2.0 13 | pyuvm==2.9.1 14 | -------------------------------------------------------------------------------- /tools/riscof/veer/env/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(rvtest_entry_point) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .text : { *(.text) } 10 | . = ALIGN(0x1000); 11 | .data : { *(.data) } 12 | .data.string : { *(.data.string)} 13 | .bss : { *(.bss) } 14 | _end = .; 15 | . = 0xd0580000; 16 | .tohost : { *(.tohost) } 17 | } 18 | 19 | -------------------------------------------------------------------------------- /tools/riscof/spike/env/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(rvtest_entry_point) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | .data : { *(.data) } 14 | .data.string : { *(.data.string)} 15 | .bss : { *(.bss) } 16 | _end = .; 17 | } 18 | 19 | -------------------------------------------------------------------------------- /testbench/asm/hello_world_dccm.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | . = 0x80000000; 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xd0580000; 9 | .data.io . : { *(.data.io) } 10 | . = 0xf0040000; 11 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 12 | .bss : { *(.bss) } 13 | . = 0xfffffff8; 14 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 15 | } 16 | -------------------------------------------------------------------------------- /tools/riscof/config.ini: -------------------------------------------------------------------------------- 1 | [RISCOF] 2 | ReferencePlugin=spike 3 | ReferencePluginPath=spike 4 | DUTPlugin=veer 5 | DUTPluginPath=veer 6 | 7 | [veer] 8 | pluginpath=veer 9 | ispec=veer/veer_isa.yaml 10 | pspec=veer/veer_platform.yaml 11 | sim_binary=obj_dir/Vtb_top 12 | target_run=1 13 | jobs=4 14 | 15 | [spike] 16 | pluginpath=spike 17 | ispec=spike/spike_isa.yaml 18 | pspec=spike/spike_platform.yaml 19 | target_run=1 20 | jobs=4 21 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | configs/snapshots 2 | work 3 | obj_dir 4 | *.vcd 5 | *.csv 6 | *.log 7 | *.exe 8 | *.swp 9 | *.sym 10 | verilator-build 11 | program.hex 12 | snapshots 13 | __pycache__ 14 | sim_build 15 | sim-build* 16 | venv 17 | results.xml 18 | verification/sim 19 | verilator-cocotb-build 20 | *.dat 21 | *.xml 22 | *.json 23 | tools/renode/renode_run 24 | tools/renode/build 25 | tools/renode/*.elf 26 | tools/renode/.venv 27 | docs/build 28 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_interface.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | interface dccm_interface ( 5 | input logic clk, 6 | reset 7 | ); 8 | 9 | `include "el2_param.vh" 10 | ; 11 | 12 | logic [pt.DCCM_BITS-1:0] addr; 13 | logic wr_en; 14 | logic rd_en; 15 | logic [pt.DCCM_FDATA_WIDTH-1:0] wdata; 16 | logic [pt.DCCM_FDATA_WIDTH-1:0] rdata; 17 | 18 | endinterface 19 | -------------------------------------------------------------------------------- /testbench/asm/dbus_nonblocking_load_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dbus_nonblocking_load_error: 4 | li x4, 0xF0000001 5 | li x5, 0x0 6 | // trigger bus fault at next load 7 | li x2, TRIGGER_DBUS_FAULT 8 | li x3, STDOUT 9 | sw x2, 0(x3) 10 | // bus fault is triggered on this instruction 11 | lw x2, 0(zero) 12 | j fail_if_not_serviced 13 | 14 | main: 15 | call dbus_nonblocking_load_error 16 | j _finish -------------------------------------------------------------------------------- /testbench/tests/core_pause/core_pause.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | int main () { 5 | /* pause the core for 0xfff cycles */ 6 | uint32_t value = 0xfff; 7 | __asm__ volatile ( 8 | "csrw 0x7c2, %0" // Write the value of foo to MCPC CSR 9 | : // No output operands 10 | : "r"(value) // Input operand (value) as register 11 | ); 12 | return 0; 13 | } 14 | -------------------------------------------------------------------------------- /docs/dashboard-styles/main.css: -------------------------------------------------------------------------------- 1 | [data-md-color-scheme="slate"] { 2 | --md-hue: 218; 3 | --md-default-bg-color: hsla(var(--md-hue), 22%, 7%, 1); 4 | } 5 | 6 | [data-md-color-primary="teal"] { 7 | --md-primary-fg-color: #25292e; 8 | } 9 | 10 | [data-md-color-scheme="slate"][data-md-color-primary="teal"] { 11 | --md-typeset-a-color: #00d0c9; 12 | } 13 | 14 | .md-social { 15 | display: none; 16 | } 17 | 18 | .md-header__option { 19 | display: none; 20 | } -------------------------------------------------------------------------------- /testbench/asm/lsu_trigger_hit.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | lsu_trigger_hit: 4 | la x4, 0x3 5 | la x5, 0x1 6 | // set up address to trigger on 7 | li x2, 0xdeadbeef 8 | csrw tdata2, x2 9 | // enable trigger in M-mode, fire on address of a load 10 | li x3, 0x41 11 | csrw mcontrol, x3 12 | // load from that address 13 | lw x2, 0(x2) 14 | j fail_if_not_serviced 15 | 16 | main: 17 | call lsu_trigger_hit 18 | j _finish -------------------------------------------------------------------------------- /.github/scripts/pytest/bar.html: -------------------------------------------------------------------------------- 1 | 2 |
3 | 4 | back 5 | 6 | 7 | chips-alliance-logo 8 | 9 | test_pyuvm_branch.html 10 |
11 | -------------------------------------------------------------------------------- /verification/block/pic/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_pic_ctrl 12 | 13 | VERILOG_SOURCES = \ 14 | $(SRCDIR)/el2_pic_ctrl.sv 15 | 16 | include $(TEST_DIR)/../common.mk 17 | -------------------------------------------------------------------------------- /verification/block/pyproject.toml: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | [tool.black] 5 | line-length = 100 6 | exclude = ''' 7 | ( 8 | /( 9 | | \.git 10 | | \.gitignore 11 | | \.gitmodules 12 | | \.github 13 | | \.nox 14 | | \.pytest_cache 15 | | __pycache__ 16 | | venv 17 | )/ 18 | | docs/source/conf.py 19 | ) 20 | ''' 21 | 22 | [tool.isort] 23 | profile = "black" 24 | multi_line_output = 3 25 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/dashboard-styles/main.css: -------------------------------------------------------------------------------- 1 | [data-md-color-scheme="slate"] { 2 | --md-hue: 218; 3 | --md-default-bg-color: hsla(var(--md-hue), 22%, 7%, 1); 4 | } 5 | 6 | [data-md-color-primary="teal"] { 7 | --md-primary-fg-color: #25292e; 8 | } 9 | 10 | [data-md-color-scheme="slate"][data-md-color-primary="teal"] { 11 | --md-typeset-a-color: #00d0c9; 12 | } 13 | 14 | .md-social { 15 | display: none; 16 | } 17 | 18 | .md-header__option { 19 | display: none; 20 | } -------------------------------------------------------------------------------- /testbench/tests/csr_mseccfg/csr_mseccfg.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0x80000000; 8 | _code_begin = .; 9 | .text : { *(.text.init*) *(.text*) } 10 | _code_end = .; 11 | _data_begin = .; 12 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 13 | .bss : { *(.bss) } 14 | . = 0xd0580000; 15 | .data.io . : { *(.data.io) } 16 | _data_end = .; 17 | } 18 | -------------------------------------------------------------------------------- /.github/scripts/openocd/sim-jtagdpi.cfg: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket 6 | # speaking the remote_bitbang protocol. The adapter is implemented as 7 | # SystemVerilog DPI module. 8 | 9 | adapter driver remote_bitbang 10 | remote_bitbang port 5000 11 | remote_bitbang host localhost 12 | -------------------------------------------------------------------------------- /testbench/tests/write_unaligned/write_unaligned.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | .handler : { 8 | KEEP(*(.handler)) 9 | } > RAM = 0x0 10 | 11 | . = 0x80000000; 12 | .text : { *(.text.init*) *(.text*) } 13 | _end = .; 14 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 15 | .bss : { *(.bss) } 16 | . = 0xd0580000; 17 | .data.io . : { *(.data.io) } 18 | } 19 | -------------------------------------------------------------------------------- /verification/block/pic_gw/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_configurable_gw 12 | 13 | VERILOG_SOURCES = \ 14 | $(SRCDIR)/el2_pic_ctrl.sv 15 | 16 | include $(TEST_DIR)/../common.mk 17 | -------------------------------------------------------------------------------- /docs/source/index.md: -------------------------------------------------------------------------------- 1 | # {{project}} 2 | 3 | ```{toctree} 4 | :maxdepth: 2 5 | :numbered: 6 | 7 | intro 8 | overview 9 | memory-map 10 | error-protection 11 | dual-core-lock-step 12 | timers 13 | power 14 | interrupts 15 | performance 16 | cache 17 | debugging 18 | core-control 19 | adaptations 20 | csrs 21 | interrupt-priority 22 | clocks 23 | complex-ports 24 | build-args 25 | tests 26 | errata 27 | physical-memory-protection 28 | user-mode 29 | verification 30 | simulation-debugging 31 | tock 32 | ``` 33 | -------------------------------------------------------------------------------- /verification/block/.flake8: -------------------------------------------------------------------------------- 1 | ; Copyright (C) 2023 Antmicro 2 | ; SPDX-License-Identifier: Apache-2.0 3 | [flake8] 4 | ignore = E203, E266, E501, W503, F403, F401, F405 5 | max-line-length = 100 6 | max-complexity = 27 7 | select = B,C,E,F,W,T4,B9 8 | exclude = 9 | .git, 10 | .gitignore, 11 | .gitmodules, 12 | .github, 13 | .nox, 14 | .pytest_cache, 15 | __pycache__, 16 | docs/source/conf.py, 17 | venv, 18 | count = True 19 | show-source = True 20 | statistics = True 21 | 22 | -------------------------------------------------------------------------------- /verification/block/dma/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = el2_dma_ctrl 13 | CM_FILE = cm.cfg 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRCDIR)/el2_dma_ctrl.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /testbench/asm/iside_fetch_precise_bus_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | iside_fetch_precise_bus_error: 4 | li x4, 0x1 5 | li x5, 0x9 6 | li x2, TRIGGER_IBUS_FAULT 7 | li x3, STDOUT 8 | sw x2, 0(x3) 9 | // ibus fault is triggered on subsequent instruction - force refetch from memory 10 | // since testbench relies on bus transaction happening to trigger bus error 11 | fence.i 12 | j fail_if_not_serviced 13 | 14 | main: 15 | call iside_fetch_precise_bus_error 16 | j _finish -------------------------------------------------------------------------------- /verification/block/pmp/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_pmp_wrapper 12 | 13 | VERILOG_SOURCES = \ 14 | $(TEST_DIR)/el2_pmp_wrapper.sv \ 15 | $(SRCDIR)/el2_pmp.sv 16 | 17 | include $(TEST_DIR)/../common.mk 18 | -------------------------------------------------------------------------------- /testbench/asm/dbus_store_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dbus_store_error: 4 | li x4, 0xF0000000 5 | li x5, 0x0 6 | // address of some data that resides in memory (and not in iccm/dccm) 7 | lw x6, _start 8 | // trigger bus fault at next store 9 | li x2, TRIGGER_DBUS_FAULT 10 | li x3, STDOUT 11 | sw x2, 0(x3) 12 | // bus fault is triggered on this instruction 13 | sw x2, 0(x6) 14 | j fail_if_not_serviced 15 | 16 | main: 17 | call dbus_store_error 18 | j _finish 19 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = axi4_to_ahb 13 | CM_FILE = cm.cfg 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRCDIR)/lib/axi4_to_ahb.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /testbench/openocd_scripts/sim-jtagdpi.cfg: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Copyright 2024 Antmicro 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 4 | # SPDX-License-Identifier: Apache-2.0 5 | 6 | # "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket 7 | # speaking the remote_bitbang protocol. The adapter is implemented as 8 | # SystemVerilog DPI module. 9 | 10 | adapter driver remote_bitbang 11 | remote_bitbang port 5000 12 | remote_bitbang host localhost 13 | -------------------------------------------------------------------------------- /tools/renode/build-all-tests.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | set -x 3 | set -e 4 | 5 | test_dir=${RV_ROOT}/testbench/tests/ 6 | tests="csr_access csr_misa csr_mstatus dhry insns irq modesw perf_counters pmp" 7 | 8 | mkdir -p build 9 | cd build 10 | for test in ${tests}; do 11 | test_name=$(basename ${test}) 12 | make CFLAGS=-DUSE_HTIF=false -f ${RV_ROOT}/tools/Makefile TEST=${test_name} USER_MODE=1 program.hex 13 | mv ${test_name}.exe ../${test_name}.elf 14 | make -f ${RV_ROOT}/tools/Makefile clean 15 | done 16 | cd - 17 | -------------------------------------------------------------------------------- /verification/block/ifu_compress/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_ifu_compress_ctl 12 | CM_FILE = cm.cfg 13 | 14 | VERILOG_SOURCES = \ 15 | $(SRCDIR)/ifu/el2_ifu_compress_ctl.sv 16 | 17 | include $(TEST_DIR)/../common.mk 18 | -------------------------------------------------------------------------------- /verification/block/dec_ib/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_dec_ib_ctl_wrapper 12 | 13 | VERILOG_SOURCES = \ 14 | $(TEST_DIR)/el2_dec_ib_ctl_wrapper.sv \ 15 | $(SRCDIR)/dec/el2_dec_ib_ctl.sv 16 | 17 | include $(TEST_DIR)/../common.mk 18 | -------------------------------------------------------------------------------- /verification/block/pmp_random/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_pmp_wrapper 12 | PMP_TEST := 1 13 | 14 | VERILOG_SOURCES = \ 15 | $(TEST_DIR)/el2_pmp_wrapper.sv \ 16 | $(SRCDIR)/el2_pmp.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /verification/block/dec_tl/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_dec_trigger_wrapper 12 | 13 | VERILOG_SOURCES = \ 14 | $(TEST_DIR)/el2_dec_trigger_wrapper.sv \ 15 | $(SRCDIR)/dec/el2_dec_trigger.sv 16 | 17 | include $(TEST_DIR)/../common.mk 18 | -------------------------------------------------------------------------------- /verification/block/lib_ahb_to_axi4/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = ahb_to_axi4_wrapper 13 | 14 | VERILOG_SOURCES = \ 15 | $(SRCDIR)/lib/ahb_to_axi4.sv \ 16 | $(TEST_DIR)/ahb_to_axi4_wrapper.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /verification/block/lsu_tl/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_lsu_trigger_wrapper 12 | 13 | VERILOG_SOURCES = \ 14 | $(TEST_DIR)/el2_lsu_trigger_wrapper.sv \ 15 | $(SRCDIR)/lsu/el2_lsu_trigger.sv 16 | 17 | include $(TEST_DIR)/../common.mk 18 | -------------------------------------------------------------------------------- /verification/block/exu_alu/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = el2_exu_alu_ctl_wrapper 13 | 14 | VERILOG_SOURCES = \ 15 | $(TEST_DIR)/el2_exu_alu_ctl_wrapper.sv \ 16 | $(SRCDIR)/exu/el2_exu_alu_ctl.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /verification/block/exu_div/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = el2_exu_div_ctl_wrapper 13 | 14 | VERILOG_SOURCES = \ 15 | $(TEST_DIR)/el2_exu_div_ctl_wrapper.sv \ 16 | $(SRCDIR)/exu/el2_exu_div_ctl.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /testbench/asm/cmark_iccm.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | . = 0x80000000 ; 6 | .text : { crt0.o (.text*) } 7 | _end = .; 8 | . = 0xee000000 ; 9 | .text.init : { cmark.o (.text*) } 10 | . = 0xd0580000; 11 | .data.io . : { *(.data.io) } 12 | . = 0xf0040000; 13 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 14 | .bss : { *(.bss) } 15 | . = 0xfffffff0; 16 | .iccm.ctl : { LONG(0xee000000); LONG(0xee008000) } 17 | . = 0xfffffff8; 18 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 19 | } 20 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/clk_override.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 17 11 00 00 13 01 01 0A 25 28 AA 85 13 05 F0 0F 3 | 91 C1 05 45 97 02 58 50 93 82 C2 FE 23 80 A2 00 4 | E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00 5 | 01 00 01 00 01 00 01 00 00 00 00 00 00 00 00 00 6 | 81 47 73 90 87 7F 85 47 73 90 87 7F 89 47 73 90 7 | 87 7F 91 47 73 90 87 7F A1 47 73 90 87 7F C1 47 8 | 73 90 87 7F 93 07 00 02 73 90 87 7F 93 07 00 04 9 | 73 90 87 7F 93 07 00 08 73 90 87 7F 93 07 00 10 10 | 73 90 87 7F 93 07 00 20 73 90 87 7F 01 45 82 80 11 | 00 00 12 | @D0580000 13 | 00 00 00 00 14 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/clk_override.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 17 11 00 00 13 01 01 0A 25 28 AA 85 13 05 F0 0F 3 | 91 C1 05 45 97 02 58 50 93 82 C2 FE 23 80 A2 00 4 | E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00 5 | 01 00 01 00 01 00 01 00 00 00 00 00 00 00 00 00 6 | 81 47 73 90 87 7F 85 47 73 90 87 7F 89 47 73 90 7 | 87 7F 91 47 73 90 87 7F A1 47 73 90 87 7F C1 47 8 | 73 90 87 7F 93 07 00 02 73 90 87 7F 93 07 00 04 9 | 73 90 87 7F 93 07 00 08 73 90 87 7F 93 07 00 10 10 | 73 90 87 7F 93 07 00 20 73 90 87 7F 01 45 82 80 11 | 00 00 12 | @D0580000 13 | 00 00 00 00 14 | -------------------------------------------------------------------------------- /verification/block/exu_mul/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = el2_exu_mul_ctl_wrapper 13 | CM_FILE = cm.cfg 14 | 15 | VERILOG_SOURCES = \ 16 | $(TEST_DIR)/el2_exu_mul_ctl_wrapper.sv \ 17 | $(SRCDIR)/exu/el2_exu_mul_ctl.sv 18 | 19 | include $(TEST_DIR)/../common.mk 20 | -------------------------------------------------------------------------------- /verification/block/ifu_mem_ctl/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_ifu_mem_ctl_wrapper 12 | CM_FILE = cm.cfg 13 | 14 | VERILOG_SOURCES = \ 15 | $(SRCDIR)/ifu/el2_ifu_mem_ctl.sv \ 16 | $(TEST_DIR)/el2_ifu_mem_ctl_wrapper.sv 17 | 18 | include $(TEST_DIR)/../common.mk 19 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/test_axi_write_channel.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import pyuvm 5 | from coordinator_seq import TestWriteChannelSeq 6 | from testbench import BaseTest 7 | 8 | 9 | @pyuvm.test() 10 | class TestAXIWriteChannel(BaseTest): 11 | def end_of_elaboration_phase(self): 12 | self.seq = TestWriteChannelSeq.create("stimulus") 13 | 14 | async def run(self): 15 | self.raise_objection() 16 | await self.seq.start() 17 | self.drop_objection() 18 | -------------------------------------------------------------------------------- /testbench/asm/dside_pic_access_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dside_pic_load_access_error: 4 | li x4, 0x5 5 | li x5, 0x6 6 | // perform not word-sized load from PIC 7 | li x2, RV_PIC_BASE_ADDR 8 | lb x2, 0(x2) 9 | j fail_if_not_serviced 10 | 11 | dside_pic_store_access_error: 12 | li x4, 0x7 13 | li x5, 0x6 14 | // perform not word-sized store to PIC 15 | li x2, RV_PIC_BASE_ADDR 16 | sb x2, 0(x2) 17 | j fail_if_not_serviced 18 | 19 | main: 20 | call dside_pic_load_access_error 21 | call dside_pic_store_access_error 22 | j _finish -------------------------------------------------------------------------------- /testbench/openocd_scripts/veer-el2-rst.cfg: -------------------------------------------------------------------------------- 1 | set _CHIPNAME riscv 2 | 3 | jtag newtap $_CHIPNAME tap -irlen 5 4 | set _TARGETNAME $_CHIPNAME.tap 5 | target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread 6 | 7 | # Mem access mode 8 | riscv set_mem_access sysbus 9 | 10 | # The following commands disable target examination and set explicitly the 11 | # core parameters read from CSRs. These required a modified version of 12 | # OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt 13 | riscv set_nohalt on 14 | riscv set_xlen 32 15 | riscv set_misa 0x40001104 16 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/test_axi.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import pyuvm 5 | from cocotb.queue import QueueFull 6 | from coordinator_seq import TestBothChannelsSeq 7 | from testbench import BaseTest 8 | 9 | 10 | @pyuvm.test() 11 | class TestAXI(BaseTest): 12 | def end_of_elaboration_phase(self): 13 | self.seq = TestBothChannelsSeq.create("stimulus") 14 | 15 | async def run(self): 16 | self.raise_objection() 17 | await self.seq.start() 18 | self.drop_objection() 19 | -------------------------------------------------------------------------------- /testbench/asm/dside_access_across_region_boundary.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dside_load_across_region_boundary: 4 | li x4, 0x4 5 | li x5, 0x2 6 | // load from across region boundary 7 | li x2, 0xe0000000-2 8 | lw x2, 0(x2) 9 | j fail_if_not_serviced 10 | 11 | dside_store_across_region_boundary: 12 | li x4, 0x6 13 | li x5, 0x2 14 | // store across region boundary 15 | li x2, 0xe0000000-2 16 | sw x2, 0(x2) 17 | j fail_if_not_serviced 18 | 19 | main: 20 | call dside_load_across_region_boundary 21 | call dside_store_across_region_boundary 22 | j _finish -------------------------------------------------------------------------------- /verification/block/ifu_compress/test_compress.py: -------------------------------------------------------------------------------- 1 | import pyuvm 2 | from pyuvm import * 3 | from testbench import BaseEnv, BaseTest, CompressedSequence 4 | 5 | 6 | @pyuvm.test() 7 | class TestDecompressor(BaseTest): 8 | """ 9 | Decompression test 10 | """ 11 | 12 | def __init__(self, name, parent): 13 | super().__init__(name, parent, BaseEnv) 14 | 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = CompressedSequence.create("stimulus") 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.dcm_seqr) 21 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/test_axi_read_channel.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import pyuvm 5 | from cocotb.queue import QueueFull 6 | from coordinator_seq import TestReadChannelSeq 7 | from testbench import BaseTest 8 | 9 | 10 | @pyuvm.test() 11 | class TestAXIReadChannel(BaseTest): 12 | def end_of_elaboration_phase(self): 13 | self.seq = TestReadChannelSeq.create("stimulus") 14 | 15 | async def run(self): 16 | self.raise_objection() 17 | await self.seq.start() 18 | self.drop_objection() 19 | -------------------------------------------------------------------------------- /testbench/tests/clk_override/clk_override.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | int main () { 5 | 6 | uint32_t value = 0; 7 | __asm__ volatile ( 8 | "csrw 0x7f8, %0" // Write the value of foo to MCGC CSR 9 | : // No output operands 10 | : "r"(value) // Input operand (value) as register 11 | ); 12 | 13 | for (int bit = 0; bit <= 9; bit++) { 14 | value = 1 << bit; 15 | __asm__ volatile ( 16 | "csrw 0x7f8, %0" 17 | : 18 | : "r"(value) 19 | ); 20 | } 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /verification/block/dec_pmp_ctl/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_dec_tlu_ctl 12 | PMP_TEST := 1 13 | CM_FILE = cm.cfg 14 | 15 | EXTRA_ARGS = -I$(SRCDIR)/include/ 16 | 17 | VERILOG_SOURCES = \ 18 | $(SRCDIR)/dec/el2_dec_tlu_ctl.sv \ 19 | $(SRCDIR)/dec/el2_dec_pmp_ctl.sv 20 | 21 | include $(TEST_DIR)/../common.mk 22 | -------------------------------------------------------------------------------- /.github/workflows/gh-pages-pr-closed.yml: -------------------------------------------------------------------------------- 1 | name: GH-Pages PR Remove 2 | 3 | on: 4 | pull_request: 5 | types: 6 | - closed 7 | 8 | jobs: 9 | build: 10 | name: PR Remove 11 | concurrency: 12 | group: gh-pages 13 | runs-on: ubuntu-24.04 14 | permissions: 15 | contents: write 16 | steps: 17 | 18 | - name: Save PR number 19 | run: | 20 | echo "number=${{ github.event.number }}" >> delete_pr_number.txt 21 | 22 | - name: Upload artifacts 23 | uses: actions/upload-artifact@v4 24 | with: 25 | name: delete_pr_number 26 | path: ./delete_pr_number.txt -------------------------------------------------------------------------------- /testbench/tests/irq/irq.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | OUTPUT_ARCH( "riscv" ) 4 | ENTRY(_start) 5 | 6 | SECTIONS { 7 | . = 0xee000000; 8 | .text.nmi : { KEEP(*(.text.nmi*)) } 9 | . = 0x80000000; 10 | .text.init : { *(.text.init*) } 11 | .text : { *(.text*) } 12 | _end = .; 13 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 14 | .bss : { *(.bss) } 15 | . = 0xd0580000; 16 | .data.io . : { *(.data.io) } 17 | /* The following constants tell the testbench to do ICCM preload */ 18 | . = 0xfffffff0; 19 | .iccm.ctl : { LONG(ADDR(.text.nmi)); LONG(ADDR(.text.nmi) + SIZEOF(.text.nmi)) } 20 | } 21 | -------------------------------------------------------------------------------- /verification/block/dec_tlu_ctl/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_dec_tlu_ctl_wrapper 12 | CM_FILE = cm.cfg 13 | 14 | EXTRA_ARGS = -I$(SRCDIR)/include/ 15 | 16 | VERILOG_SOURCES = \ 17 | $(SRCDIR)/dec/el2_dec_pmp_ctl.sv \ 18 | $(SRCDIR)/dec/el2_dec_tlu_ctl.sv \ 19 | $(TEST_DIR)/el2_tlu_ctl_wrapper.sv 20 | 21 | include $(TEST_DIR)/../common.mk 22 | -------------------------------------------------------------------------------- /testbench/tests/pmp/pmp.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS { 5 | 6 | . = 0x80000000; 7 | _text = .; 8 | .text : { *(.text.init*) *(.text*) } 9 | _text_end = .; 10 | _end = .; 11 | 12 | . = ALIGN(4096); 13 | _data = .; 14 | .data : { *(.*data) *(.rodata*) *(.sbss) } 15 | _bss = .; 16 | .bss : { *(.bss) } 17 | _data_end = .; 18 | 19 | . = ALIGN(4096); 20 | _area = .; 21 | .area : { *(.area.bufr) *(.area.code) } 22 | . = ALIGN(4096); 23 | 24 | . = ALIGN(8192); 25 | _stack_lo = .; 26 | . += 8192; 27 | _stack_hi = .; 28 | 29 | . = 0xd0580000; 30 | .data.io . (NOLOAD) : { KEEP( *(.data.io) ) } 31 | } 32 | -------------------------------------------------------------------------------- /verification/block/exu_mul/test_mul.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseSequence, BaseTest 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestMul(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = BaseSequence("stimulus", ["mul"]) 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.mul_seqr) 21 | -------------------------------------------------------------------------------- /verification/block/dmi/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = dmi_test_wrapper 12 | CM_FILE = cm.cfg 13 | 14 | VERILOG_SOURCES = \ 15 | $(TEST_DIR)/dmi_test_wrapper.sv \ 16 | $(SRCDIR)/dmi/rvjtag_tap.v \ 17 | $(SRCDIR)/dmi/dmi_mux.v \ 18 | $(SRCDIR)/dmi/dmi_jtag_to_core_sync.v \ 19 | $(SRCDIR)/dmi/dmi_wrapper.v 20 | 21 | include $(TEST_DIR)/../common.mk 22 | 23 | -------------------------------------------------------------------------------- /.github/workflows/verible-format.yml: -------------------------------------------------------------------------------- 1 | name: Verible formatter 2 | 3 | on: 4 | pull_request_target: 5 | 6 | jobs: 7 | format-review: 8 | runs-on: ubuntu-24.04 9 | permissions: 10 | checks: write 11 | contents: read 12 | pull-requests: write 13 | steps: 14 | - uses: actions/checkout@v3 15 | with: 16 | ref: ${{ github.event.pull_request.head.sha }} 17 | - uses: antmicro/verible-formatter-action@update-upload-action 18 | with: 19 | github_token: ${{ secrets.GITHUB_TOKEN }} 20 | reviewdog_reporter: 'local' 21 | fail_on_formatting_suggestions: ${{ github.event_name != 'pull_request_target' }} 22 | -------------------------------------------------------------------------------- /.github/workflows/verible-lint.yml: -------------------------------------------------------------------------------- 1 | name: Verible linter 2 | 3 | on: 4 | pull_request_target: 5 | 6 | jobs: 7 | lint-review: 8 | runs-on: ubuntu-24.04 9 | permissions: 10 | checks: write 11 | contents: read 12 | pull-requests: write 13 | steps: 14 | - uses: actions/checkout@v3 15 | with: 16 | ref: ${{ github.event.pull_request.head.sha }} 17 | - uses: chipsalliance/verible-linter-action@main 18 | with: 19 | github_token: ${{ secrets.GITHUB_TOKEN }} 20 | reviewdog_reporter: 'local' 21 | extra_args: '--waiver_files=./violations.waiver' 22 | paths: | 23 | ./design 24 | 25 | -------------------------------------------------------------------------------- /testbench/tests/core_pause/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | .section .text.init 4 | .global _start 5 | _start: 6 | 7 | # Setup stack 8 | la sp, STACK 9 | 10 | # Call main() 11 | call main 12 | 13 | # Map exit code: == 0 - success, != 0 - failure 14 | mv a1, a0 15 | li a0, 0xff # ok 16 | beq a1, x0, _finish 17 | li a0, 1 # fail 18 | 19 | .global _finish 20 | _finish: 21 | la t0, tohost 22 | sb a0, 0(t0) # Signal testbench termination 23 | beq x0, x0, _finish 24 | .rept 10 25 | nop 26 | .endr 27 | 28 | .section .data.io 29 | .global tohost 30 | tohost: .word 0 31 | 32 | -------------------------------------------------------------------------------- /testbench/tests/csr_misa/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | .section .text.init 4 | .global _start 5 | _start: 6 | 7 | # Setup stack 8 | la sp, STACK 9 | 10 | # Call main() 11 | call main 12 | 13 | # Map exit code: == 0 - success, != 0 - failure 14 | mv a1, a0 15 | li a0, 0xff # ok 16 | beq a1, x0, _finish 17 | li a0, 1 # fail 18 | 19 | .global _finish 20 | _finish: 21 | la t0, tohost 22 | sb a0, 0(t0) # Signal testbench termination 23 | beq x0, x0, _finish 24 | .rept 10 25 | nop 26 | .endr 27 | 28 | .section .data.io 29 | .global tohost 30 | tohost: .word 0 31 | 32 | -------------------------------------------------------------------------------- /testbench/tests/clk_override/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | .section .text.init 4 | .global _start 5 | _start: 6 | 7 | # Setup stack 8 | la sp, STACK 9 | 10 | # Call main() 11 | call main 12 | 13 | # Map exit code: == 0 - success, != 0 - failure 14 | mv a1, a0 15 | li a0, 0xff # ok 16 | beq a1, x0, _finish 17 | li a0, 1 # fail 18 | 19 | .global _finish 20 | _finish: 21 | la t0, tohost 22 | sb a0, 0(t0) # Signal testbench termination 23 | beq x0, x0, _finish 24 | .rept 10 25 | nop 26 | .endr 27 | 28 | .section .data.io 29 | .global tohost 30 | tohost: .word 0 31 | 32 | -------------------------------------------------------------------------------- /testbench/tests/write_unaligned/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | .section .text.init 4 | .global _start 5 | _start: 6 | 7 | # Setup stack 8 | la sp, STACK 9 | 10 | # Call main() 11 | call main 12 | 13 | # Map exit code: == 0 - success, != 0 - failure 14 | mv a1, a0 15 | li a0, 0xff # ok 16 | beq a1, x0, _finish 17 | li a0, 1 # fail 18 | 19 | .global _finish 20 | _finish: 21 | la t0, tohost 22 | sb a0, 0(t0) # Signal testbench termination 23 | beq x0, x0, _finish 24 | .rept 10 25 | nop 26 | .endr 27 | 28 | .section .data.io 29 | .global tohost 30 | tohost: .word 0 31 | 32 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | // FIXME: 5 | // In Verilator, user should always use: 6 | // uvm_sequencer#(item, item); 7 | // instead standard (other simulators): 8 | // uvm_sequencer#(item); 9 | 10 | `ifdef VERILATOR 11 | class dccm_sequencer extends uvm_sequencer #(dccm_transaction_sequence_item, dccm_transaction_sequence_item); 12 | `else 13 | class dccm_sequencer extends uvm_sequencer #(dccm_transaction_sequence_item); 14 | `endif 15 | 16 | `uvm_component_utils(dccm_sequencer) 17 | 18 | function new(string name, uvm_component parent); 19 | super.new(name, parent); 20 | endfunction 21 | 22 | endclass 23 | -------------------------------------------------------------------------------- /testbench/asm/dside_access_region_prediction_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dside_load_region_prediction_error: 4 | li x4, 0x5 5 | li x5, 0x5 6 | // We take a large address that will overflow to another region 7 | // when offset is used in an 'lw' instruction: 0xFFFFFFFC + 0x4 8 | li x2, 0xFFFFFFFC 9 | lw x2, 0x4(x2) 10 | j fail_if_not_serviced 11 | 12 | dside_store_region_prediction_error: 13 | li x4, 0x7 14 | li x5, 0x5 15 | // same as in load region prediction error 16 | li x2, 0xFFFFFFFC 17 | sw x2, 0x4(x2) 18 | j fail_if_not_serviced 19 | 20 | main: 21 | call dside_load_region_prediction_error 22 | call dside_store_region_prediction_error 23 | j _finish -------------------------------------------------------------------------------- /violations.waiver: -------------------------------------------------------------------------------- 1 | waive --rule=module-filename --location="design/lib/.*_lib.sv" 2 | waive --rule=line-length --location="design/ifu/.*.sv" 3 | waive --rule=line-length --location="design/dec/.*.sv" 4 | waive --rule=line-length --location="design/lsu/.*.sv" 5 | waive --rule=line-length --location="design/el2_.*_ctrl.sv" 6 | waive --rule=no-trailing-spaces --location="design/ifu/.*.sv" 7 | waive --rule=no-trailing-spaces --location="design/el2_.*_ctrl.sv" 8 | waive --rule=generate-label --location="design/lsu/el2_.*.sv" 9 | 10 | waive --rule=explicit-parameter-storage-type --location="design/el2_pmp.sv" 11 | waive --rule=explicit-parameter-storage-type --location="design/dec/el2_dec_pmp_ctl.sv" 12 | -------------------------------------------------------------------------------- /.github/scripts/get_code_hash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # This script is responsible for computing hash for RISCV-DV generated programs 3 | # cache. 4 | 5 | HASHES=() 6 | HASHES+=($(git submodule status third_party/riscv-dv | cut -d\ -f2)) 7 | HASHES+=($(sha256sum tools/riscv-dv/code_fixup.py | cut -d\ -f1)) 8 | HASHES+=($(sha256sum tools/riscv-dv/testlist.yaml | cut -d\ -f1)) 9 | HASHES+=($(sha256sum tools/riscv-dv/riscv_core_setting.sv | cut -d\ -f1)) 10 | HASHES+=($(sha256sum tools/riscv-dv/Makefile | cut -d\ -f1)) 11 | HASHES+=($(sha256sum tools/riscv-dv/user_extension.svh | cut -d\ -f1)) 12 | HASHES+=($(sha256sum tools/riscv-dv/veer_directed_instr_lib.sv | cut -d\ -f1)) 13 | 14 | echo ${HASHES[@]} | sha256sum | cut -d\ -f1 15 | -------------------------------------------------------------------------------- /verification/block/ifu_compress/cm.cfg: -------------------------------------------------------------------------------- 1 | +tree * 2 | 3 | // Tied to '0 4 | -node el2_ifu_compress_ctl.o[31] 5 | -node el2_ifu_compress_ctl.o[29:21] 6 | -node el2_ifu_compress_ctl.o[19:15] 7 | -node el2_ifu_compress_ctl.o[11:7] 8 | 9 | -node el2_ifu_compress_ctl.o[1:0] // Tied to 2'b11 10 | -node el2_ifu_compress_ctl.l1[1:0] // Tied to o[1:0] (2'b11) 11 | -node el2_ifu_compress_ctl.l2[1:0] // Tied to l1[1:0] (2'b11) 12 | -node el2_ifu_compress_ctl.l3[1:0] // Tied to l2[1:0] (2'b11) 13 | 14 | -node el2_ifu_compress_ctl.l1[31] // Tied to o[31] ('0) 15 | -node el2_ifu_compress_ctl.l1[29:25] // Tied to o[29:25] ('0) 16 | 17 | -node el2_ifu_compress_ctl.rdpd[4:3] // Tied to 2'01 18 | -node el2_ifu_compress_ctl.rs2pd[4:3] // Tied to 2'01 19 | -------------------------------------------------------------------------------- /testbench/asm/dside_core_local_access_unmapped_address_error.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dside_core_local_load_unmapped_address_error: 4 | li x4, 0x5 5 | li x5, 0x2 6 | // load from DCCM upper boundary (this also triggers unmapped address error) 7 | li x2, RV_DCCM_EADR - 1 8 | lw x2, 0(x2) 9 | j fail_if_not_serviced 10 | 11 | dside_core_local_store_unmapped_address_error: 12 | li x4, 0x7 13 | li x5, 0x2 14 | // store to DCCM upper boundary (this also triggers unmapped address error) 15 | li x2, RV_DCCM_EADR - 1 16 | sw x2, 0(x2) 17 | j fail_if_not_serviced 18 | 19 | main: 20 | call dside_core_local_load_unmapped_address_error 21 | call dside_core_local_store_unmapped_address_error 22 | j _finish -------------------------------------------------------------------------------- /verification/block/dccm/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = el2_lsu_dccm_mem_wrapper 13 | 14 | VERILOG_SOURCES = \ 15 | $(SRCDIR)/lib/el2_mem_if.sv \ 16 | $(TEST_DIR)/el2_lsu_dccm_mem_wrapper.sv \ 17 | $(SRCDIR)/lsu/el2_lsu_dccm_mem.sv \ 18 | $(SRCDIR)/lib/mem_lib.sv 19 | 20 | # Undefine the VERILATOR macro to make the code use actual RAM cells instead 21 | # of simulation models 22 | EXTRA_ARGS += -UVERILATOR 23 | 24 | include $(TEST_DIR)/../common.mk 25 | -------------------------------------------------------------------------------- /verification/block/iccm/Makefile: -------------------------------------------------------------------------------- 1 | 2 | null := 3 | space := $(null) # 4 | comma := , 5 | 6 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 7 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 8 | 9 | TEST_FILES = $(sort $(wildcard test_*.py)) 10 | 11 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 12 | TOPLEVEL = el2_ifu_iccm_mem_wrapper 13 | 14 | VERILOG_SOURCES = \ 15 | $(SRCDIR)/lib/el2_mem_if.sv \ 16 | $(TEST_DIR)/el2_ifu_iccm_mem_wrapper.sv \ 17 | $(SRCDIR)/ifu/el2_ifu_iccm_mem.sv \ 18 | $(SRCDIR)/lib/mem_lib.sv 19 | 20 | # Undefine the VERILATOR macro to make the code use actual RAM cells instead 21 | # of simulation models 22 | EXTRA_ARGS += -UVERILATOR 23 | 24 | include $(TEST_DIR)/../common.mk 25 | -------------------------------------------------------------------------------- /.github/scripts/indexgen/source.template/coverage_dashboard.md: -------------------------------------------------------------------------------- 1 | ({{ ref }})= 2 | # Coverage dashboard 3 | 4 | ## Summary reports (all tests) 5 | 6 | {%- for coverage in summary %} 7 | {%- if summary[coverage] %} 8 | * [{{ coverage }} coverage](external:coverage_dashboard/{{ summary[coverage] }}/index.html) 9 | {%- else %} 10 | * {{ coverage }} coverage (no data) 11 | {%- endif %} 12 | {%- endfor %} 13 | 14 | ## Individual test reports 15 | 16 | {%- for coverage in individual %} 17 | ### {{ coverage }} coverage 18 | {%- if individual[coverage] %} 19 | {%- for test in individual[coverage] %} 20 | * [{{ test }}](external:coverage_dashboard/{{ individual[coverage][test] }}/index.html) 21 | {%- endfor %} 22 | {%- else %} 23 | no data 24 | {%- endif %} 25 | {%- endfor %} 26 | -------------------------------------------------------------------------------- /tools/riscv-dv/user_extension.svh: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (c) 2024 Antmicro 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | `include "veer_directed_instr_lib.sv" 17 | -------------------------------------------------------------------------------- /testbench/asm/machine_external_ints.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | machine_software_interrupt: 4 | la x4, 0x80000003 5 | li x5, 0x0 6 | // enable software interrupt 7 | li x2, 0x8 8 | csrw mie, x2 9 | // trigger soft interrupt 10 | li x2, TRIGGER_SOFT_INT 11 | li x3, STDOUT 12 | sw x2, 0(x3) 13 | j fail_if_not_serviced 14 | 15 | machine_timer_interrupt: 16 | la x4, 0x80000007 17 | li x5, 0x0 18 | // enable machine timer interrupt 19 | li x2, 0x80 20 | csrw mie, x2 21 | // trigger timer interrupt 22 | li x2, TRIGGER_TIMER_INT 23 | li x3, STDOUT 24 | sw x2, 0(x3) 25 | j fail_if_not_serviced 26 | 27 | main: 28 | call machine_software_interrupt 29 | call machine_timer_interrupt 30 | j _finish -------------------------------------------------------------------------------- /.github/workflows/custom-lint.yml: -------------------------------------------------------------------------------- 1 | name: Custom lint 2 | 3 | on: 4 | push: 5 | branches: 6 | - main 7 | pull_request: 8 | 9 | jobs: 10 | run-lint: 11 | name: Run lint 12 | runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ] 13 | container: centos:8 14 | env: 15 | GHA_EXTERNAL_DISK: additional-tools-all 16 | GHA_SA: gh-sa-veer-uploader 17 | steps: 18 | - uses: actions/checkout@v3 19 | with: 20 | submodules: recursive 21 | 22 | - name: Set secrets version 23 | run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV 24 | 25 | - name: Run lint 26 | run: _secret_combined_${{ env.SECRETS_VERSION }} 27 | env: 28 | SECRET_NAME: _secret_lint 29 | -------------------------------------------------------------------------------- /testbench/tests/ecc/ecc.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text : { *(.text*) } 8 | _end = .; 9 | 10 | /* STDOUT */ 11 | . = 0xd0580000; 12 | .data.io . : { *(.data.io) } 13 | 14 | /* DCCM */ 15 | . = 0xf0040000; 16 | dccm = .; 17 | .data : { *(.*data) *(.rodata*) *(.sbss)} 18 | .bss : { *(.bss); . = ALIGN(4); } 19 | STACK = ALIGN(16) + 0x1000; 20 | 21 | /* ICCM */ 22 | iccm_start = .; 23 | .iccm_data0 0xee000000 : AT(iccm_start) { 24 | KEEP(*(.iccm_data0)); 25 | . = ALIGN(4); 26 | } = 0x0000, 27 | iccm_end = iccm_start + SIZEOF(.iccm_data0); 28 | 29 | . = 0xfffffff8; 30 | .data.ctl : AT(0xfffffff8) { LONG(0xf0040000); LONG(STACK) } 31 | } 32 | -------------------------------------------------------------------------------- /testbench/tests/ecc/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | #include "defines.h" 4 | 5 | .section .text.init 6 | .global _start 7 | _start: 8 | // enable caching, except region 0xd 9 | li t0, 0x59555555 10 | csrw 0x7c0, t0 11 | 12 | la sp, STACK 13 | 14 | la t0, _trap_handler 15 | csrw mtvec, t0 16 | 17 | call main 18 | 19 | .global _finish 20 | _finish: 21 | la t0, tohost 22 | li t1, 0xff 23 | sb t1, 0(t0) // DemoTB test termination 24 | li t1, 1 25 | sw t1, 0(t0) // Whisper test termination 26 | beq x0, x0, _finish 27 | .rept 10 28 | nop 29 | .endr 30 | 31 | .global _trap_handler 32 | _trap_handler: 33 | call trap_handler 34 | j _start 35 | 36 | .section .data.io 37 | .global tohost 38 | tohost: .word 0 39 | 40 | -------------------------------------------------------------------------------- /testbench/jtagdpi/README.md: -------------------------------------------------------------------------------- 1 | # JTAG DPI module for OpenOCD remote_bitbang driver 2 | 3 | This DPI module provides a "virtual" JTAG connection between a simulated chip and [OpenOCD](http://openocd.org/). 4 | It makes use of the `remote_bitbang` JTAG driver shipped with OpenOCD, which forwards JTAG requests over TCP to a remote server. 5 | The `jtagdpi` module is instantiated in the hardware simulation to receive the JTAG requests from OpenOCD and drive the JTAG pins (TCK, TMS, TDI, etc.) from it. 6 | 7 | The `remote_bitbang` protocol is documented in the OpenOCD source tree in the `doc/manual/jtag/drivers/remote_bitbang.txt` file, or online at [https://repo.or.cz/openocd.git/blob/HEAD:/doc/manual/jtag/drivers/remote_bitbang.txt](https://repo.or.cz/openocd.git/blob/HEAD:/doc/manual/jtag/drivers/remote_bitbang.txt). 8 | -------------------------------------------------------------------------------- /testbench/tests/write_unaligned/write_unaligned.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int handler() __attribute__((section(".handler"))); 4 | 5 | int handler() { 6 | return 0; 7 | } 8 | 9 | int main () { 10 | int (*func)() = (int (*)())0x70000001; 11 | volatile uint32_t csr_value; 12 | 13 | printf("jumping to 0x70000001\n"); 14 | func(); 15 | printf("jumping to 0x80001\n"); 16 | func = 0x80001; 17 | func(); 18 | printf("jumping to 0xe000001\n"); 19 | func = 0xe000001; 20 | func(); 21 | printf("jumping to 0x3fffffff\n"); 22 | func = 0x3fffffff; 23 | func(); 24 | printf("jumping to 0xa001\n"); 25 | func = 0xa001; 26 | func(); 27 | 28 | // read CSR at address 0x7FF (mscause) 29 | __asm__ volatile ("csrr %0, 0x7FF" : "=r"(csr_value)); 30 | 31 | return 0; 32 | } 33 | -------------------------------------------------------------------------------- /tools/riscof/veer/veer_isa.yaml: -------------------------------------------------------------------------------- 1 | hart_ids: [0] 2 | hart0: 3 | ISA: RV32IMCZicsr 4 | physical_addr_sz: 32 5 | User_Spec_Version: '2.3' 6 | supported_xlen: [32] 7 | hw_data_misaligned_support: true 8 | misa: 9 | reset-val: 0x40001104 10 | rv32: 11 | accessible: true 12 | mxl: 13 | implemented: true 14 | type: 15 | warl: 16 | dependency_fields: [] 17 | legal: 18 | - mxl[1:0] in [0x1] 19 | wr_illegal: 20 | - Unchanged 21 | extensions: 22 | implemented: true 23 | type: 24 | warl: 25 | dependency_fields: [] 26 | legal: 27 | - extensions[25:0] bitmask [0x0001104, 0x0000000] 28 | wr_illegal: 29 | - Unchanged 30 | 31 | -------------------------------------------------------------------------------- /verification/block/lib_axi4_to_ahb/ahb_lite_pkg.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | 5 | from enum import IntEnum 6 | 7 | AHB_DRV_SIGNALS = [ 8 | "ahb_hrdata", 9 | "ahb_hready", 10 | "ahb_hresp", 11 | ] 12 | 13 | AHB_RSP_SIGNALS = [ 14 | "ahb_haddr", 15 | "ahb_hburst", 16 | "ahb_hmastlock", 17 | "ahb_hprot", 18 | "ahb_hsize", 19 | "ahb_htrans", 20 | "ahb_hwrite", 21 | "ahb_hwdata", 22 | ] 23 | 24 | 25 | class AHB_LITE_RESPONSE_CODES(IntEnum): 26 | OKAY = 0 27 | 28 | 29 | class AHB_LITE_TRANSFER_TYPE_ENCODING(IntEnum): 30 | IDLE = 0 31 | BUSY = 1 32 | NONSEQ = 2 33 | SEQ = 3 34 | 35 | 36 | class AHB_LITE_NOTIFICATION(IntEnum): 37 | AHB_LITE_WRITE = 1 38 | AHB_LITE_READ = 2 39 | AHB_LITE_IDLE = 3 40 | -------------------------------------------------------------------------------- /tools/riscof/spike/spike_isa.yaml: -------------------------------------------------------------------------------- 1 | hart_ids: [0] 2 | hart0: 3 | ISA: RV32IMCZicsr_Zifencei 4 | physical_addr_sz: 32 5 | User_Spec_Version: '2.3' 6 | supported_xlen: [32] 7 | hw_data_misaligned_support: true 8 | misa: 9 | reset-val: 0x40001104 10 | rv32: 11 | accessible: true 12 | mxl: 13 | implemented: true 14 | type: 15 | warl: 16 | dependency_fields: [] 17 | legal: 18 | - mxl[1:0] in [0x1] 19 | wr_illegal: 20 | - Unchanged 21 | extensions: 22 | implemented: true 23 | type: 24 | warl: 25 | dependency_fields: [] 26 | legal: 27 | - extensions[25:0] bitmask [0x0001104, 0x0000000] 28 | wr_illegal: 29 | - Unchanged 30 | 31 | -------------------------------------------------------------------------------- /verification/top/test_pyuvm/test_irq/test_irq.py: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2023 Antmicro 3 | # SPDX-License-Identifier: BSD-2-Clause 4 | 5 | import pyuvm 6 | from pyuvm import * 7 | from .irq_uvm import VeerEl2Env, IrqRandomSeq 8 | from cocotb.clock import Clock 9 | 10 | @pyuvm.test() 11 | class BaseTest(uvm_test): 12 | def build_phase(self): 13 | self.set_default_logging_level(logging.DEBUG) 14 | self.env = VeerEl2Env("env", self) 15 | 16 | def end_of_elaboration_phase(self): 17 | self.test_all = IrqRandomSeq.create("test_irq") 18 | 19 | async def run_phase(self): 20 | self.raise_objection() 21 | clock = Clock(cocotb.top.clk, 10, units="ns") 22 | cocotb.start_soon(clock.start(start_high=False)) 23 | await self.test_all.start() 24 | self.drop_objection() 25 | -------------------------------------------------------------------------------- /verification/block/dec_tl/test_dec_tl.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseTest, TlSequence 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestTriggerLogic(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = TlSequence("stimulus") 18 | 19 | async def run_phase(self): 20 | self.raise_objection() 21 | 22 | # Run the actual test 23 | await self.run() 24 | 25 | self.drop_objection() 26 | 27 | async def run(self): 28 | await self.seq.start(self.env.tl_seqr) 29 | -------------------------------------------------------------------------------- /verification/block/lsu_tl/test_lsu_tl.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseTest, TlSequence 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestTriggerLogic(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = TlSequence("stimulus") 18 | 19 | async def run_phase(self): 20 | self.raise_objection() 21 | 22 | # Run the actual test 23 | await self.run() 24 | 25 | self.drop_objection() 26 | 27 | async def run(self): 28 | await self.seq.start(self.env.tl_seqr) 29 | -------------------------------------------------------------------------------- /verification/block/dec_ib/test_dec_ib.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseTest, IbCtlSequence 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestIbCtlLogic(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = IbCtlSequence("stimulus") 18 | 19 | async def run_phase(self): 20 | self.raise_objection() 21 | 22 | # Run the actual test 23 | await self.run() 24 | 25 | self.drop_objection() 26 | 27 | async def run(self): 28 | await self.seq.start(self.env.seqr) 29 | -------------------------------------------------------------------------------- /verification/block/dec/Makefile: -------------------------------------------------------------------------------- 1 | null := 2 | space := $(null) # 3 | comma := , 4 | 5 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 6 | SRCDIR := $(abspath $(TEST_DIR)../../../../design) 7 | 8 | TEST_FILES = $(sort $(wildcard test_*.py)) 9 | 10 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 11 | TOPLEVEL = el2_dec_wrapper 12 | DEC_TEST := 1 13 | CM_FILE = cm.cfg 14 | 15 | EXTRA_ARGS = -I$(SRCDIR)/include/ 16 | 17 | VERILOG_SOURCES = \ 18 | $(TEST_DIR)/el2_dec_wrapper.sv \ 19 | $(SRCDIR)/dec/el2_dec.sv \ 20 | $(SRCDIR)/dec/el2_dec_decode_ctl.sv \ 21 | $(SRCDIR)/dec/el2_dec_gpr_ctl.sv \ 22 | $(SRCDIR)/dec/el2_dec_ib_ctl.sv \ 23 | $(SRCDIR)/dec/el2_dec_pmp_ctl.sv \ 24 | $(SRCDIR)/dec/el2_dec_tlu_ctl.sv \ 25 | $(SRCDIR)/dec/el2_dec_trigger.sv 26 | 27 | include $(TEST_DIR)/../common.mk 28 | -------------------------------------------------------------------------------- /verification/block/pic/test_reset.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import cocotb 5 | import pyuvm 6 | from testbench import BaseTest 7 | 8 | # ============================================================================= 9 | 10 | 11 | @pyuvm.test() 12 | class TestReset(BaseTest): 13 | """ 14 | A basic test that resets the DUT 15 | """ 16 | 17 | async def run(self): 18 | # Check state of DUT signals after reset 19 | state = { 20 | "mexintpend": 0, 21 | "mhwakeup": 0, 22 | "pl": 0, 23 | "claimid": 0, 24 | } 25 | 26 | for name, value in state.items(): 27 | signal = getattr(cocotb.top, name) 28 | assert signal.value == value, "{}={}, should be {}".format(name, signal.value, value) 29 | -------------------------------------------------------------------------------- /.github/workflows/build-docs.yml: -------------------------------------------------------------------------------- 1 | name: Documentation build 2 | 3 | on: 4 | workflow_call: 5 | 6 | jobs: 7 | build: 8 | name: Build 9 | runs-on: ubuntu-24.04 10 | env: 11 | DEBIAN_FRONTEND: "noninteractive" 12 | steps: 13 | - name: Install dependencies 14 | run: | 15 | sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ 16 | python3 python3-pip 17 | - name: Setup repository 18 | uses: actions/checkout@v3 19 | - name: Build Docs 20 | run: | 21 | pushd docs 22 | pip3 install -r requirements.txt 23 | TZ=UTC make html 24 | popd 25 | ls -lah docs/build 26 | - name: Pack artifacts 27 | if: always() 28 | uses: actions/upload-artifact@v4 29 | with: 30 | name: docs 31 | path: ./docs/build 32 | -------------------------------------------------------------------------------- /testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | dside_size_misaligned_load_to_non_idempotent_address: 4 | li x4, 0x4 5 | li x5, 0x1 6 | // load from across non-idempotent address (with side effects) 7 | // we take advantage of the fact that STDOUT is such an address 8 | li x2, STDOUT-2 9 | lw x2, 0(x2) 10 | j fail_if_not_serviced 11 | 12 | dside_size_misaligned_store_to_non_idempotent_address: 13 | li x4, 0x6 14 | li x5, 0x1 15 | // store to across non-idempotent address (with side effect) 16 | // we take advantage of the fact that STDOUT is such an address 17 | li x2, STDOUT-2 18 | sw x2, 0(x2) 19 | j fail_if_not_serviced 20 | 21 | main: 22 | call dside_size_misaligned_load_to_non_idempotent_address 23 | call dside_size_misaligned_store_to_non_idempotent_address 24 | j _finish -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_memtest.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | class mem_wr_rd_test extends mem_model_base_test; 5 | 6 | `uvm_component_utils(mem_wr_rd_test) 7 | 8 | dccm_memtest_sequence memtest; 9 | 10 | function new(string name = "mem_wr_rd_test", uvm_component parent = null); 11 | super.new(name, parent); 12 | endfunction : new 13 | 14 | virtual function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | 17 | memtest = dccm_memtest_sequence::type_id::create(); 18 | // Run the memtest 10 times 19 | memtest.loops = 10; 20 | endfunction : build_phase 21 | 22 | task run_phase(uvm_phase phase); 23 | 24 | phase.raise_objection(this); 25 | memtest.start(agent.sequencer); 26 | phase.drop_objection(this); 27 | 28 | endtask : run_phase 29 | 30 | endclass : mem_wr_rd_test 31 | -------------------------------------------------------------------------------- /testbench/tests/csr_mstatus/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | .section .text.init 4 | .global _start 5 | _start: 6 | 7 | # Setup stack 8 | la sp, STACK 9 | 10 | # Setup PMP 11 | # Region 0 TOR 0x00000000-0xFFFFFFFF RWX 12 | li t0, 0xFFFFFFFF 13 | csrw pmpaddr0, t0 14 | li t0, 0x0000000F 15 | csrw pmpcfg0, t0 16 | 17 | # Call main() 18 | call main 19 | 20 | # Map exit code: == 0 - success, != 0 - failure 21 | mv a1, a0 22 | li a0, 0xff # ok 23 | beq a1, x0, _finish 24 | li a0, 1 # fail 25 | 26 | .global _finish 27 | _finish: 28 | la t0, tohost 29 | sb a0, 0(t0) # Signal testbench termination 30 | beq x0, x0, _finish 31 | .rept 10 32 | nop 33 | .endr 34 | 35 | .section .data.io 36 | .global tohost 37 | tohost: .word 0 38 | 39 | -------------------------------------------------------------------------------- /.github/scripts/common.inc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e -u -o pipefail 4 | 5 | COLOR_CLEAR="\033[0m" 6 | COLOR_RED="\033[0;31m" 7 | COLOR_GREEN="\033[1;32m" 8 | COLOR_YELLOW="\033[1;33m" 9 | COLOR_WHITE="\033[1;37m" 10 | 11 | check_args_count(){ 12 | # Check argument count function is meant to be used to check if 13 | # the number of received arguments is equal to the expected. 14 | # If they are unequal, the function returns with error 15 | # Args: 16 | # argc_got - Number of received arguments, e.g.: $# 17 | # argc_expected - Number of expected arguments, e.g.: 2 18 | argc_got=$1 19 | argc_expected=$2 20 | if [ ${argc_got} -ne ${argc_expected} ]; then 21 | echo -e "${COLOR_WHITE}Expected ${argc_expected} arguments, but received ${argc_got} ${COLOR_RED}FAIL${COLOR_CLEAR}" 22 | echo -e "${COLOR_WHITE}Caller:${COLOR_CLEAR}" `caller` 23 | exit 1 24 | fi 25 | } 26 | -------------------------------------------------------------------------------- /.github/scripts/breakpoint.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # SPDX-License-Identifier: Apache-2.0 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | set -ex 17 | 18 | # Invoke GDB 19 | ${GCC_PREFIX}-gdb -n --batch -x breakpoint.gdb >gdb.log 20 | # Parse the log 21 | cat gdb.log | grep 'Breakpoint 1,' >breakpoint.txt 22 | 23 | # Compare the dumps 24 | diff -E -y breakpoint.txt breakpoint_golden.txt || true 25 | 26 | -------------------------------------------------------------------------------- /tools/addassign: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | 3 | use Getopt::Long; 4 | 5 | $helpusage = "placeholder"; 6 | 7 | GetOptions ('in=s' => \$in, 8 | 'prefix=s' => \$prefix) || die("$helpusage"); 9 | 10 | 11 | 12 | @in=`cat $in`; 13 | 14 | 15 | foreach $line (@in) { 16 | 17 | if ($line=~/\#/) { next; } 18 | 19 | if ($line=~/([^=]+)=/) { 20 | $sig=$1; 21 | $sig=~s/\s+//g; 22 | printf("logic $sig;\n"); 23 | } 24 | } 25 | 26 | foreach $line (@in) { 27 | 28 | if ($line=~/\#/) { next; } 29 | 30 | if ($line=~/([^=]+)=\s*;/) { 31 | printf("assign ${prefix}$1 = 1'b0;\n"); 32 | next; 33 | } 34 | 35 | if ($line=~/([^=]+)=\s*\(\s*\);/) { 36 | printf("assign ${prefix}$1 = 1'b0;\n"); 37 | next; 38 | } 39 | 40 | if ($line =~ /=/) { printf("assign ${prefix}$line"); } 41 | else { printf("$line"); } 42 | } 43 | 44 | 45 | exit; 46 | 47 | -------------------------------------------------------------------------------- /testbench/tests/csr_misa/csr_misa.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #define read_csr(csr) ({ \ 5 | unsigned long res; \ 6 | asm volatile ("csrr %0, " #csr : "=r"(res)); \ 7 | res; \ 8 | }) 9 | 10 | int main () { 11 | #ifdef RV_USER_MODE 12 | const unsigned int user_mode = 1; 13 | #else 14 | const unsigned int user_mode = 0; 15 | #endif 16 | const unsigned int compressed_ext = 1; 17 | const unsigned int rv32i_base_isa = 1; 18 | const unsigned int int_mult_ext = 1; 19 | const unsigned int base = 1; 20 | const unsigned long golden = base << 30 | user_mode << 20 | int_mult_ext << 12 | \ 21 | rv32i_base_isa << 8 | compressed_ext << 2; 22 | 23 | // Read and print misa 24 | unsigned long misa = read_csr(misa); 25 | printf("misa = 0x%08X vs. 0x%08X\n", misa, golden); 26 | 27 | // Check 28 | return (misa == golden) ? 0 : -1; 29 | } 30 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_transaction_sequence_item.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | class dccm_transaction_sequence_item extends uvm_sequence_item; 5 | 6 | `include "el2_param.vh" 7 | ; 8 | 9 | rand bit [ pt.DCCM_BITS-1:0] addr; 10 | rand bit [pt.DCCM_FDATA_WIDTH-1:0] wdata; 11 | bit [pt.DCCM_FDATA_WIDTH-1:0] rdata; 12 | // we want to manually control wr_en anf rd_en in the test 13 | bit wr_en; 14 | bit rd_en; 15 | 16 | `uvm_object_utils_begin(dccm_transaction_sequence_item) 17 | `uvm_field_int(addr, UVM_ALL_ON) 18 | `uvm_field_int(wr_en, UVM_ALL_ON) 19 | `uvm_field_int(rd_en, UVM_ALL_ON) 20 | `uvm_field_int(wdata, UVM_ALL_ON) 21 | `uvm_object_utils_end 22 | 23 | function new(string name = "dccm_transation_sequence_item"); 24 | super.new(name); 25 | endfunction 26 | 27 | endclass 28 | -------------------------------------------------------------------------------- /verification/block/exu_div/el2_exu_div_ctl_wrapper.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | module el2_exu_div_ctl_wrapper 4 | import el2_pkg::*; 5 | #( 6 | `include "el2_param.vh" 7 | ) 8 | ( 9 | input logic clk, 10 | input logic rst_l, 11 | input logic scan_mode, 12 | 13 | // el2_div_pkt_t 14 | input logic dp_valid, 15 | input logic dp_unsign, 16 | input logic dp_rem, 17 | 18 | input logic [31:0] dividend, 19 | input logic [31:0] divisor, 20 | 21 | input logic cancel, 22 | 23 | output logic finish_dly, 24 | output logic [31:0] out 25 | ); 26 | 27 | // Pack el2_div_pkt_t 28 | el2_div_pkt_t dp; 29 | assign dp.valid = dp_valid; 30 | assign dp.unsign = dp_unsign; 31 | assign dp.rem = dp_rem; 32 | 33 | // The divider 34 | el2_exu_div_ctl div (.*); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/bitmanip.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | B1 62 93 82 E2 0D 37 C3 DE 00 13 03 E3 0D 81 43 3 | B3 E3 62 08 13 0E F0 0F 63 96 C3 0F B3 E3 62 48 4 | 31 6E 13 0E CE 05 63 9F C3 0D B3 D3 62 68 37 0E 5 | 03 B7 63 99 C3 0D B3 D3 62 28 13 0E F0 FF 63 93 6 | C3 0D B3 93 62 08 37 3E 00 30 13 0E 2E 13 63 9B 7 | C3 0B B3 D3 62 08 37 0E CF 00 19 0E 63 94 C3 0B 8 | 93 13 03 61 37 2E 6B 61 13 0E 3E 11 63 9C C3 09 9 | 93 13 13 61 37 3E DF 84 13 0E FE AF 63 94 C3 09 10 | 93 13 23 61 37 BE 9F 48 13 0E BE 07 63 9C C3 07 11 | 93 13 83 61 37 8E AB 7F 13 0E CE 04 63 94 C3 07 12 | 93 13 93 61 37 8E 47 0C 13 0E CE 9E 63 9C C3 05 13 | 93 13 A3 61 37 0E EC A1 13 0E DE E1 63 94 C3 05 14 | B3 A3 62 28 37 1E 00 EE 13 0E 0E E0 63 9C C3 03 15 | B3 C3 62 28 37 0E 00 DE 63 96 C3 03 B3 E3 62 28 16 | 01 4E 63 91 C3 03 B3 F3 62 48 37 CE 00 80 13 0E 17 | EE 0D 63 99 C3 01 37 05 58 D0 93 05 F0 0F 0C C1 18 | 01 00 FD BF 37 05 58 D0 85 45 0C C1 00 00 00 00 19 | @FFFFFFF8 20 | 00 00 04 F0 00 10 04 F0 21 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/bitmanip.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | B1 62 93 82 E2 0D 37 C3 DE 00 13 03 E3 0D 81 43 3 | B3 E3 62 08 13 0E F0 0F 63 96 C3 0F B3 E3 62 48 4 | 31 6E 13 0E CE 05 63 9F C3 0D B3 D3 62 68 37 0E 5 | 03 B7 63 99 C3 0D B3 D3 62 28 13 0E F0 FF 63 93 6 | C3 0D B3 93 62 08 37 3E 00 30 13 0E 2E 13 63 9B 7 | C3 0B B3 D3 62 08 37 0E CF 00 19 0E 63 94 C3 0B 8 | 93 13 03 61 37 2E 6B 61 13 0E 3E 11 63 9C C3 09 9 | 93 13 13 61 37 3E DF 84 13 0E FE AF 63 94 C3 09 10 | 93 13 23 61 37 BE 9F 48 13 0E BE 07 63 9C C3 07 11 | 93 13 83 61 37 8E AB 7F 13 0E CE 04 63 94 C3 07 12 | 93 13 93 61 37 8E 47 0C 13 0E CE 9E 63 9C C3 05 13 | 93 13 A3 61 37 0E EC A1 13 0E DE E1 63 94 C3 05 14 | B3 A3 62 28 37 1E 00 EE 13 0E 0E E0 63 9C C3 03 15 | B3 C3 62 28 37 0E 00 DE 63 96 C3 03 B3 E3 62 28 16 | 01 4E 63 91 C3 03 B3 F3 62 48 37 CE 00 80 13 0E 17 | EE 0D 63 99 C3 01 37 05 58 D0 93 05 F0 0F 0C C1 18 | 01 00 FD BF 37 05 58 D0 85 45 0C C1 00 00 00 00 19 | @FFFFFFF8 20 | 00 00 04 F0 00 10 04 F0 21 | -------------------------------------------------------------------------------- /.github/scripts/openocd/veer-el2-rst.cfg: -------------------------------------------------------------------------------- 1 | if { [info exists CHIPNAME] } { 2 | set _CHIPNAME $CHIPNAME 3 | } else { 4 | set _CHIPNAME riscv 5 | } 6 | 7 | jtag newtap $_CHIPNAME tap -irlen 5 8 | set _TARGETNAME $_CHIPNAME.tap 9 | target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread 10 | 11 | # Configure work area in on-chip SRAM 12 | $_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0 13 | 14 | # Mem access mode 15 | riscv set_mem_access sysbus 16 | 17 | # The following commands disable target examination and set explicitly the 18 | # core parameters read from CSRs. These required a modified version of 19 | # OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt 20 | riscv set_nohalt on 21 | riscv set_xlen 32 22 | riscv set_misa 0x40001104 23 | 24 | # Be verbose about GDB errors 25 | gdb_report_data_abort enable 26 | gdb_report_register_access_error enable 27 | 28 | # Always use hardware breakpoints. 29 | gdb_breakpoint_override hard 30 | -------------------------------------------------------------------------------- /testbench/tests/csr_mseccfg/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | .option norvc 4 | .option nopic 5 | 6 | .section .text.init 7 | .align 4 8 | .global _start 9 | _start: 10 | 11 | # Setup stack 12 | la sp, STACK 13 | 14 | # Setup trap handler 15 | la t0, _trap_entry 16 | csrw mtvec, t0 17 | 18 | # Call main() 19 | call main 20 | 21 | # Map exit code: == 0 - success, != 0 - failure 22 | mv a1, a0 23 | li a0, 0xff # ok 24 | beq a1, x0, _finish 25 | li a0, 1 # fail 26 | 27 | .global _finish 28 | _finish: 29 | la t0, tohost 30 | sb a0, 0(t0) # Signal testbench termination 31 | beq x0, x0, _finish 32 | .rept 10 33 | nop 34 | .endr 35 | 36 | .align 8 37 | _trap_entry: 38 | # In this test no trap should happen. Trigger test failure if it does. 39 | la a0, 1 40 | j _finish 41 | 42 | .section .data.io 43 | .global tohost 44 | tohost: .word 0 45 | 46 | -------------------------------------------------------------------------------- /testbench/tests/pmp_random/generate_random.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | set -e 4 | 5 | outfile=random_data.h 6 | iterations=100 7 | 8 | printf '// This file was generated with generate_random.sh\n\n' > $outfile 9 | 10 | echo "#define RANDOM_ITERATIONS $iterations" >> $outfile 11 | echo 'const uint32_t rand_address [] = {' >> $outfile 12 | 13 | # generate random data in hex, fold each 8 hex digits, prepend '0x', append ',' 14 | tr -dc 'A-F0-9' < /dev/urandom | dd bs=1 count=$((8 * $iterations)) 2>/dev/null | \ 15 | fold -w8 | \ 16 | sed 's/^/ 0x/' | \ 17 | sed 's/$/,/' >> $outfile 18 | echo >> $outfile 19 | echo '};' >> $outfile 20 | 21 | echo 'const uint32_t rand_config [] = {' >> $outfile 22 | # generate random data in hex, fold each 8 hex digits, prepend '0x', append ',' 23 | tr -dc 'A-F0-9' < /dev/urandom | dd bs=1 count=$((8 * $iterations)) 2>/dev/null | \ 24 | fold -w8 | \ 25 | sed 's/^/ 0x/' | \ 26 | sed 's/$/,/' >> $outfile 27 | echo >> $outfile 28 | echo '};' >> $outfile 29 | 30 | -------------------------------------------------------------------------------- /testbench/asm/internal_timer_ints.s: -------------------------------------------------------------------------------- 1 | #include "common.s" 2 | 3 | machine_internal_timer0_local_interrupt: 4 | li x4, 0x8000001d 5 | li x5, 0x0 6 | csrw 0x7D4, 0x0 // disable incrementing timer0 7 | csrw 0x7D2, 0x0 // reset timer0 count value 8 | csrw 0x7D3, 0x8 // set timer0 threshold to 8 9 | li x2, 0x20000000 10 | csrw mie, x2 // enable timer0 local interrupt 11 | csrw 0x7D4, 0x1 // reenable incrementing timer0 12 | j fail_if_not_serviced 13 | 14 | machine_internal_timer1_local_interrupt: 15 | li x4, 0x8000001c 16 | li x5, 0x0 17 | csrw 0x7D7, 0x0 // disable incrementing timer0 18 | csrw 0x7D5, 0x0 // reset timer0 count value 19 | csrw 0x7D6, 0x8 // set timer0 threshold to 8 20 | li x2, 0x10000000 21 | csrw mie, x2 // enable timer0 local interrupt 22 | csrw 0x7D7, 0x1 // reenable incrementing timer0 23 | j fail_if_not_serviced 24 | 25 | main: 26 | call machine_internal_timer0_local_interrupt 27 | call machine_internal_timer1_local_interrupt 28 | j _finish -------------------------------------------------------------------------------- /.github/scripts/indexgen/Makefile: -------------------------------------------------------------------------------- 1 | SPHINXOPTS ?= 2 | SPHINXBUILD ?= sphinx-build 3 | SOURCEDIR = source.template 4 | GENDIR = source 5 | BUILDDIR ?= build 6 | ROOTDIR ?= work 7 | 8 | all: clean html 9 | 10 | # Sources 11 | SOURCES = $(wildcard $(SOURCEDIR)/*.md) 12 | 13 | # Generate sources 14 | $(GENDIR): 15 | @mkdir -p $@ 16 | 17 | $(GENDIR)/index.md: $(SOURCES) generate.py | $(GENDIR) 18 | @rm -rf $(GENDIR)/* 19 | @python3 generate.py --template "$(SOURCEDIR)" --root "$(ROOTDIR)/html" --output "$(GENDIR)" 20 | 21 | # Build the final webpage. Pass the 'html' target to sphinx, copy report pages 22 | html: Makefile $(GENDIR)/index.md 23 | @$(SPHINXBUILD) -M $@ "$(GENDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 24 | @rsync -avrm --include="*/" --include="coverage_dashboard/***" --include="verification_dashboard/***" --include="docs_rendered/***" --exclude="*" "$(ROOTDIR)/" "$(BUILDDIR)/" 25 | @bash update_styles.sh "$(BUILDDIR)" 26 | 27 | clean: 28 | @rm -rf $(BUILDDIR) 29 | @rm -rf $(GENDIR) 30 | 31 | .PHONY: all clean html 32 | -------------------------------------------------------------------------------- /tools/riscv-dv/veer_directed_instr_lib.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (c) 2024 Antmicro 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | class veer_load_store_rand_addr_instr_stream extends riscv_load_store_rand_addr_instr_stream; 17 | 18 | // Avoid writing in higher memory regions 19 | constraint addr_offset_veer_c {addr_offset[XLEN-1:30] == 0;} 20 | 21 | `uvm_object_utils(veer_load_store_rand_addr_instr_stream) 22 | `uvm_object_new 23 | 24 | endclass 25 | -------------------------------------------------------------------------------- /verification/top/test_pyuvm/test_pyuvm.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | import os 3 | import subprocess 4 | 5 | 6 | class TestPyUVM(): 7 | 8 | @pytest.mark.parametrize("UVM_TEST", ["test_irq.test_irq"]) 9 | def test_pyuvm(self, UVM_TEST, coverage_opt, sim_opt, conf_params): 10 | 11 | os.environ["UVM_TEST"] = UVM_TEST 12 | py_command = [] 13 | py_command += [f"COVERAGE_TYPE={coverage_opt}"] 14 | py_command += [f"SIM={sim_opt}"] 15 | py_command += [f"CONF_PARAMS='{conf_params}'"] 16 | py_command += [ 17 | "make clean all", 18 | ] 19 | py_command = " ".join(py_command) 20 | 21 | print(f"\n----- PyTest -----") 22 | print(f":: py_command >> {py_command}") 23 | p = subprocess.run(py_command, shell=True, 24 | executable="/bin/bash", bufsize=0) 25 | print(f"\n------------------") 26 | 27 | print(f"----- Subprocess Summary -----") 28 | print(f"p.check_returncode") 29 | p.check_returncode() 30 | print(f"------------------------------") 31 | -------------------------------------------------------------------------------- /testbench/tests/pmp/fault.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 2 | * Copyright 2023 Antmicro, Ltd. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef _FAULT_H 18 | #define _FAULT_H 19 | 20 | #include "veer.h" 21 | #include "trap.h" 22 | 23 | #define EXC_INSTRUCTION_ACC_FAULT 1 24 | #define EXC_LOAD_ACC_FAULT 5 25 | #define EXC_STORE_ACC_FAULT 7 26 | 27 | void fault_setjmp(struct rv_jmp_buf* env); 28 | struct fault fault_last_get(void); 29 | void fault_return(const struct fault *fault); 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /verification/block/dmi/jtag_pkg.py: -------------------------------------------------------------------------------- 1 | from enum import IntEnum 2 | 3 | from cocotb.types import LogicArray, Range 4 | 5 | 6 | class JTAGDefaults: 7 | IDLE = LogicArray(0, Range(1, "downto", 0)) 8 | DMI_STAT = LogicArray(0, Range(1, "downto", 0)) 9 | VERSION = LogicArray(1, Range(3, "downto", 0)) 10 | RD_STATUS = LogicArray(0, Range(1, "downto", 0)) 11 | 12 | 13 | class JTAGInstructions: 14 | DEVICE_ID_SEL = LogicArray(0b00001, Range(4, "downto", 0)) 15 | DR_EN_0 = LogicArray(0b10000, Range(4, "downto", 0)) 16 | DR_EN_1 = LogicArray(0b10001, Range(4, "downto", 0)) 17 | 18 | 19 | class JTAGStates(IntEnum): 20 | TEST_LOGIC_RESET_STATE = 0 21 | RUN_TEST_IDLE_STATE = 1 22 | SELECT_DR_SCAN_STATE = 2 23 | CAPTURE_DR_STATE = 3 24 | SHIFT_DR_STATE = 4 25 | EXIT1_DR_STATE = 5 26 | PAUSE_DR_STATE = 6 27 | EXIT2_DR_STATE = 7 28 | UPDATE_DR_STATE = 8 29 | SELECT_IR_SCAN_STATE = 9 30 | CAPTURE_IR_STATE = 10 31 | SHIFT_IR_STATE = 11 32 | EXIT1_IR_STATE = 12 33 | PAUSE_IR_STATE = 13 34 | EXIT2_IR_STATE = 14 35 | UPDATE_IR_STATE = 15 36 | -------------------------------------------------------------------------------- /testbench/user_cells.sv: -------------------------------------------------------------------------------- 1 | 2 | // SPDX-License-Identifier: Apache-2.0 3 | // Copyright 2020 Western Digital Corporation or its affiliates. 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | // This file contains examples of user (technology specific) cells that can 18 | // be used thruought the core 19 | 20 | // Clock gate example 21 | module user_clock_gate ( 22 | input logic CK, 23 | output logic Q, 24 | input logic EN 25 | ); 26 | 27 | logic gate; 28 | 29 | initial gate = 0; 30 | always @(negedge CK) 31 | gate <= EN; 32 | 33 | assign Q = CK & gate; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /testbench/openocd_scripts/common.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | # Copyright 2024 Antmicro 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | proc compare {x y} { 17 | puts "'$x' vs. '$y'" 18 | 19 | if {[llength $y] != [llength $y]} { 20 | puts "length mismatch!" 21 | return -1 22 | } 23 | 24 | for {set i 0} {$i < [llength $x]} {incr i} { 25 | if {[lindex $x $i] != [lindex $y $i]} { 26 | puts "item $i mismatch!" 27 | return -1 28 | } 29 | } 30 | 31 | return 0 32 | } 33 | 34 | set STDOUT 0x300300cc 35 | set dmstatus_addr 0x11 36 | 37 | -------------------------------------------------------------------------------- /tools/renode/veer.resc: -------------------------------------------------------------------------------- 1 | :name: VeeR 2 | $name?="VeeR" 3 | 4 | # Set to path of the ELF program to run 5 | $bin?=$ORIGIN/csr_access.elf 6 | 7 | using sysbus 8 | mach create $name 9 | 10 | $platform?=$ORIGIN/veer.repl 11 | machine LoadPlatformDescription $platform 12 | 13 | macro reset 14 | """ 15 | sysbus LoadELF $bin 16 | """ 17 | 18 | runMacro $reset 19 | 20 | machine CreateVirtualConsole "htif" 21 | 22 | python """ 23 | from Antmicro.Renode.Peripherals.Bus import Access, SysbusAccessWidth 24 | htif = monitor.Machine["sysbus.htif"] 25 | bus = monitor.Machine.SystemBus 26 | 27 | def store_char(_, __, ___, value): 28 | if(value not in (0x1, 0xFF) and value < 0xFF): 29 | htif.DisplayChar(value) 30 | else: 31 | for x in [ord(c) for c in "\nFinished: " + ("FAILED\n" if value == 0x1 else "PASSED\n")]: 32 | htif.DisplayChar(x) 33 | htif.DebugLog("TEST FINISHED") 34 | monitor.Machine.Pause() 35 | 36 | bus.AddWatchpointHook(bus.GetSymbolAddress("tohost"), SysbusAccessWidth.DoubleWord, Access.Write, store_char) 37 | bus.AddWatchpointHook(bus.GetSymbolAddress("tohost"), SysbusAccessWidth.Byte, Access.Write, store_char) 38 | """ 39 | 40 | cpu WfiAsNop true 41 | showAnalyzer htif 42 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_agent.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | `include "dccm_transaction_sequence_item.sv" 5 | `include "dccm_sequencer.sv" 6 | `include "dccm_sequence.sv" 7 | `include "dccm_driver.sv" 8 | `include "dccm_monitor.sv" 9 | 10 | class dccm_agent extends uvm_agent; 11 | 12 | dccm_driver driver; 13 | dccm_sequencer sequencer; 14 | dccm_monitor monitor; 15 | 16 | `uvm_component_utils(dccm_agent) 17 | 18 | function new(string name, uvm_component parent); 19 | super.new(name, parent); 20 | endfunction : new 21 | 22 | function void build_phase(uvm_phase phase); 23 | super.build_phase(phase); 24 | 25 | monitor = dccm_monitor::type_id::create("monitor", this); 26 | 27 | if (get_is_active() == UVM_ACTIVE) begin 28 | driver = dccm_driver::type_id::create("driver", this); 29 | sequencer = dccm_sequencer::type_id::create("sequencer", this); 30 | end 31 | endfunction : build_phase 32 | 33 | function void connect_phase(uvm_phase phase); 34 | if (get_is_active() == UVM_ACTIVE) begin 35 | driver.seq_item_port.connect(sequencer.seq_item_export); 36 | end 37 | endfunction : connect_phase 38 | 39 | endclass : dccm_agent 40 | -------------------------------------------------------------------------------- /verification/block/dma/test_reset.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import cocotb 5 | import pyuvm 6 | from testbench import BaseTest 7 | 8 | # ============================================================================= 9 | 10 | 11 | @pyuvm.test() 12 | class TestReset(BaseTest): 13 | """ 14 | A basic test that resets the DUT 15 | """ 16 | 17 | async def run(self): 18 | # Check state of DUT signals after reset 19 | state = { 20 | "dma_dbg_cmd_done": 0, 21 | "dma_dbg_cmd_fail": 0, 22 | "dma_dccm_req": 0, 23 | "dma_iccm_req": 0, 24 | "dma_active": 0, 25 | "dma_dccm_stall_any": 0, 26 | "dma_iccm_stall_any": 0, 27 | "dma_pmu_dccm_read": 0, 28 | "dma_pmu_dccm_write": 0, 29 | "dma_pmu_any_read": 0, 30 | "dma_pmu_any_write": 0, 31 | "dma_axi_bvalid": 0, 32 | "dma_axi_rvalid": 0, 33 | } 34 | 35 | for name, value in state.items(): 36 | signal = getattr(cocotb.top, name) 37 | assert signal.value == value, "{}={}, should be {}".format(name, signal.value, value) 38 | -------------------------------------------------------------------------------- /docs/source/interrupt-priority.md: -------------------------------------------------------------------------------- 1 | # Interrupt Priorities 2 | 3 | {numref}`tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities` summarizes the VeeR EL2 platform-specific (Local) and standard RISC-V (External, Software, and Timer) relative interrupt priorities. 4 | 5 | :::{list-table} VeeR EL2 Platform-specific and Standard RISC-V Interrupt Priorities. Table is sorted from highest Interrupt priority to lowest Interrupt priority 6 | :name: tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities 7 | 8 | * - **Interrupt** 9 | - **Section** 10 | * - *Non-Maskable Interrupt (standard RISC-V)* 11 | - [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector) 12 | * - *External interrupt (standard RISC-V)* 13 | - [](interrupts.md) 14 | * - Correctable error (local interrupt) 15 | - [](memory-map.md#correctable-error-local-interrupt) 16 | * - *Software interrupt (standard RISC-V)* 17 | - [](memory-map.md#software-interrupts) 18 | * - *Timer interrupt (standard RISC-V)* 19 | - [](performance.md#standard-risc-v-registers) 20 | * - Internal timer 0 (local interrupt) 21 | - [](timers.md#internal-timer-local-interrupts) 22 | * - Internal timer 1 (local interrupt) 23 | - [](timers.md#internal-timer-local-interrupts) 24 | ::: 25 | -------------------------------------------------------------------------------- /verification/block/exu_alu/test_arith.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseSequence, BaseTest 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestAdd(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = BaseSequence("stimulus", ["add"]) 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.alu_seqr) 21 | 22 | 23 | @pyuvm.test() 24 | class TestSub(BaseTest): 25 | def end_of_elaboration_phase(self): 26 | super().end_of_elaboration_phase() 27 | self.seq = BaseSequence("stimulus", ["sub"]) 28 | 29 | async def run(self): 30 | await self.seq.start(self.env.alu_seqr) 31 | 32 | 33 | @pyuvm.test() 34 | class TestAll(BaseTest): 35 | def end_of_elaboration_phase(self): 36 | super().end_of_elaboration_phase() 37 | self.seq = BaseSequence("stimulus", ["add", "sub"]) 38 | 39 | async def run(self): 40 | await self.seq.start(self.env.alu_seqr) 41 | -------------------------------------------------------------------------------- /verification/block/exu_div/test_div.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseSequence, BaseTest 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestDiv(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = BaseSequence("stimulus", ["div"]) 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.div_seqr) 21 | 22 | 23 | @pyuvm.test() 24 | class TestRem(BaseTest): 25 | def end_of_elaboration_phase(self): 26 | super().end_of_elaboration_phase() 27 | self.seq = BaseSequence("stimulus", ["rem"]) 28 | 29 | async def run(self): 30 | await self.seq.start(self.env.div_seqr) 31 | 32 | 33 | @pyuvm.test() 34 | class TestAll(BaseTest): 35 | def end_of_elaboration_phase(self): 36 | super().end_of_elaboration_phase() 37 | self.seq = BaseSequence("stimulus", ["div", "rem"]) 38 | 39 | async def run(self): 40 | await self.seq.start(self.env.div_seqr) 41 | -------------------------------------------------------------------------------- /verification/block/exu_alu/test_zbp.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseSequence, BaseTest 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestPack(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = BaseSequence("stimulus", ["pack"]) 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.alu_seqr) 21 | 22 | 23 | @pyuvm.test() 24 | class TestPackh(BaseTest): 25 | def end_of_elaboration_phase(self): 26 | super().end_of_elaboration_phase() 27 | self.seq = BaseSequence("stimulus", ["packh"]) 28 | 29 | async def run(self): 30 | await self.seq.start(self.env.alu_seqr) 31 | 32 | 33 | @pyuvm.test() 34 | class TestAll(BaseTest): 35 | def end_of_elaboration_phase(self): 36 | super().end_of_elaboration_phase() 37 | self.seq = BaseSequence("stimulus", ["pack", "packh"]) 38 | 39 | async def run(self): 40 | await self.seq.start(self.env.alu_seqr) 41 | -------------------------------------------------------------------------------- /verification/block/dec_tl/el2_dec_trigger_wrapper.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | module el2_dec_trigger_wrapper 4 | import el2_pkg::*; 5 | #( 6 | `include "el2_param.vh" 7 | ) ( 8 | input logic [31:1] dec_i0_pc_d, 9 | 10 | // Unpacked [3:0] trigger_pkt_t 11 | input logic [3:0] select, 12 | input logic [3:0] match, 13 | input logic [3:0] store, 14 | input logic [3:0] load, 15 | input logic [3:0] execute, 16 | input logic [3:0] m, 17 | 18 | input logic [31:0] tdata[4], 19 | 20 | output logic [3:0] dec_i0_trigger_match_d 21 | ); 22 | 23 | // Pack triggers 24 | el2_trigger_pkt_t [3:0] trigger_pkt_any; 25 | for (genvar i = 0; i < 4; i++) begin : g_trigger_assigns 26 | assign trigger_pkt_any[i].select = select[i]; 27 | assign trigger_pkt_any[i].match = match[i]; 28 | assign trigger_pkt_any[i].store = store[i]; 29 | assign trigger_pkt_any[i].load = load[i]; 30 | assign trigger_pkt_any[i].execute = execute[i]; 31 | assign trigger_pkt_any[i].m = m[i]; 32 | assign trigger_pkt_any[i].tdata2 = tdata[i]; 33 | end 34 | 35 | // The trigger unit 36 | el2_dec_trigger tu ( 37 | .dec_i0_pc_d(dec_i0_pc_d[31:1]), 38 | .* 39 | ); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /verification/top/test_pyuvm/conftest.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | 3 | def type_checker_cov(value): 4 | msg = "UsageError --coverage=" 5 | if value not in ["all", "branch", "toggle", "functional"]: 6 | raise pytest.UsageError(msg) 7 | return value 8 | 9 | def type_checker_sim(value): 10 | msg = "UsageError --sim=" 11 | if value not in ["verilator", "vcs"]: 12 | raise pytest.UsageError(msg) 13 | return value 14 | 15 | def pytest_addoption(parser): 16 | parser.addoption( 17 | "--coverage", action="store", default="toggle", help="--coverage=",type=type_checker_cov 18 | ) 19 | parser.addoption( 20 | "--sim", action="store", default="verilator", help="--sim=",type=type_checker_sim 21 | ) 22 | parser.addoption( 23 | "--conf_params", action="store", default="-set build_axi4", help="--conf_params='...'" 24 | ) 25 | 26 | @pytest.fixture 27 | def coverage_opt(request): 28 | return request.config.getoption("--coverage") 29 | 30 | @pytest.fixture 31 | def sim_opt(request): 32 | return request.config.getoption("--sim") 33 | 34 | @pytest.fixture 35 | def conf_params(request): 36 | return request.config.getoption("--conf_params") 37 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/hello_world.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 73 10 20 B0 73 10 20 B8 97 00 00 00 93 80 80 11 3 | 73 90 50 30 B7 50 55 5F 93 80 50 55 73 90 00 7C 4 | B7 01 58 D0 17 02 00 00 13 02 C2 10 83 02 02 00 5 | 23 80 51 00 05 02 E3 9B 02 FE 13 05 F0 0F B7 01 6 | 58 D0 23 80 A1 00 E3 0C 00 FE 01 00 01 00 01 00 7 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 8 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 9 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 10 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 11 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 12 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 13 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 14 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 15 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 17 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 18 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 19 | 01 00 01 00 13 00 00 00 13 00 00 00 13 00 00 00 20 | 05 45 31 BF 00 00 00 00 00 00 00 00 00 00 00 00 21 | @80000130 22 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 23 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 65 6C 6C 6F 20 24 | 57 6F 72 6C 64 20 66 72 6F 6D 20 56 65 65 52 20 25 | 45 4C 32 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 26 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 27 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/hello_world.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 73 10 20 B0 73 10 20 B8 97 00 00 00 93 80 80 11 3 | 73 90 50 30 B7 50 55 5F 93 80 50 55 73 90 00 7C 4 | B7 01 58 D0 17 02 00 00 13 02 C2 10 83 02 02 00 5 | 23 80 51 00 05 02 E3 9B 02 FE 13 05 F0 0F B7 01 6 | 58 D0 23 80 A1 00 E3 0C 00 FE 01 00 01 00 01 00 7 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 8 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 9 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 10 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 11 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 12 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 13 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 14 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 15 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 17 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 18 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 19 | 01 00 01 00 13 00 00 00 13 00 00 00 13 00 00 00 20 | 05 45 31 BF 00 00 00 00 00 00 00 00 00 00 00 00 21 | @80000130 22 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 23 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 65 6C 6C 6F 20 24 | 57 6F 72 6C 64 20 66 72 6F 6D 20 56 65 65 52 20 25 | 45 4C 32 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 26 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 27 | -------------------------------------------------------------------------------- /testbench/tests/csr_access/veer.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 2 | * Copyright 2023 Antmicro, Ltd. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #include 18 | #include 19 | 20 | extern volatile char tohost; 21 | 22 | 23 | __attribute__((__noreturn__)) void _exit (int status) 24 | { 25 | if (!status) tohost = 0xff; 26 | else tohost = 0x01; 27 | while (1) {}; 28 | } 29 | 30 | int veer_tb_putc(char c, FILE *stream) 31 | { 32 | (void) stream; 33 | tohost = c; 34 | return c; 35 | } 36 | 37 | static FILE __stdio = FDEV_SETUP_STREAM(veer_tb_putc, NULL, NULL, _FDEV_SETUP_WRITE); 38 | FILE *const stdin = &__stdio; 39 | __strong_reference(stdin, stdout); 40 | __strong_reference(stdin, stderr); 41 | -------------------------------------------------------------------------------- /.github/scripts/pytest/style_pytest_report.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SELF_DIR="$(dirname $(readlink -f ${BASH_SOURCE[0]}))" 4 | . ${SELF_DIR}/../common.inc.sh 5 | 6 | style_pytest_report(){ 7 | check_args_count $# 3 8 | SRC_DIR=$1 9 | DST_DIR=$2 10 | HTML_FILE=$3 11 | echo -e "${COLOR_WHITE}========== style_pytest_report =========${COLOR_CLEAR}" 12 | echo -e "${COLOR_WHITE} SRC_DIR = ${SRC_DIR}${COLOR_CLEAR}" 13 | echo -e "${COLOR_WHITE} DST_DIR = ${DST_DIR}${COLOR_CLEAR}" 14 | echo -e "${COLOR_WHITE} HTML_FILE = ${HTML_FILE}${COLOR_CLEAR}" 15 | 16 | # Copy assets 17 | 18 | mkdir -p ${DST_DIR}/assets 19 | cp ${SRC_DIR}/assets/* ${DST_DIR}/assets/ 20 | 21 | # Add bar above h1.title 22 | 23 | SEARCH="

" 24 | REPLACE=`cat ${SRC_DIR}/bar.html | tr '\n' ' '` 25 | REPLACE="$REPLACE $SEARCH" 26 | filename="${DST_DIR}/${HTML_FILE}" 27 | 28 | sed -i "s@$SEARCH@$REPLACE@" $filename 29 | 30 | # Copy JS script to build dir 31 | 32 | mkdir -p ${DST_DIR}/script 33 | cp -r ${SRC_DIR}/script/* ${DST_DIR}/script/ 34 | 35 | echo -e "${COLOR_WHITE}Style pytest report ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}" 36 | echo -e "${COLOR_WHITE}========== style_pytest_report =========${COLOR_CLEAR}" 37 | } 38 | 39 | check_args_count $# 3 40 | style_pytest_report "$@" 41 | -------------------------------------------------------------------------------- /testbench/tests/perf_counters/veer.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 2 | * Copyright 2023 Antmicro, Ltd. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #include 18 | #include 19 | 20 | extern volatile char tohost; 21 | 22 | 23 | __attribute__((__noreturn__)) void _exit (int status) 24 | { 25 | if (!status) tohost = 0xff; 26 | else tohost = 0x01; 27 | while (1) {}; 28 | } 29 | 30 | int veer_tb_putc(char c, FILE *stream) 31 | { 32 | (void) stream; 33 | tohost = c; 34 | return c; 35 | } 36 | 37 | static FILE __stdio = FDEV_SETUP_STREAM(veer_tb_putc, NULL, NULL, _FDEV_SETUP_WRITE); 38 | FILE *const stdin = &__stdio; 39 | __strong_reference(stdin, stdout); 40 | __strong_reference(stdin, stderr); 41 | -------------------------------------------------------------------------------- /.github/scripts/riscv_dv_parse_testlist.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import os 3 | from json import dumps 4 | from yaml import load, Loader 5 | from typing import Generator 6 | 7 | RISCV_DV_HOME = "third_party/riscv-dv/" 8 | 9 | 10 | def parse_yaml(path: str) -> Generator[str, None, None]: 11 | with open(path, 'rb') as fd: 12 | tests = load(fd, Loader=Loader) 13 | for test in tests: 14 | if 'import' in test: 15 | import_path = test['import'].split('/', 1)[1] 16 | yield from parse_yaml(RISCV_DV_HOME + import_path) 17 | elif 'test' in test: 18 | yield test['test'] 19 | 20 | 21 | if __name__ == "__main__": 22 | if len(sys.argv) == 2: 23 | testlist = RISCV_DV_HOME + f'target/{sys.argv[1]}/testlist.yaml' 24 | 25 | # check if testlist.yaml is provided by RISCV-DV; if not - it's a 26 | # custom testlist file not provided by RISCV-DV by default; treat the 27 | # script argument as full a path 28 | if not os.path.isdir(testlist): 29 | testlist = sys.argv[1] 30 | 31 | testlist = parse_yaml(testlist) 32 | else: 33 | testlist = parse_yaml(RISCV_DV_HOME + 'yaml/base_testlist.yaml') 34 | testlist = list(testlist) 35 | # remove, will cause incomplete sim, need customized RTL 36 | testlist.remove("riscv_csr_test") 37 | print(dumps(testlist)) 38 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/hello_world_dccm.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 73 10 20 B0 73 10 20 B8 97 00 00 00 93 80 80 11 3 | 73 90 50 30 B7 50 55 5F 93 80 50 55 73 90 00 7C 4 | B7 01 58 D0 17 02 04 70 13 02 C2 FD 83 02 02 00 5 | 23 80 51 00 05 02 E3 9B 02 FE 13 05 F0 0F B7 01 6 | 58 D0 23 80 A1 00 E3 0C 00 FE 01 00 01 00 01 00 7 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 8 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 9 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 10 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 11 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 12 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 13 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 14 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 15 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 17 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 18 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 19 | 01 00 01 00 13 00 00 00 13 00 00 00 13 00 00 00 20 | 05 45 31 BF 00 00 00 00 00 00 00 00 00 00 00 00 21 | @F0040000 22 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 23 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 65 6C 6C 6F 20 24 | 57 6F 72 6C 64 20 66 72 6F 6D 20 56 65 65 52 20 25 | 45 4C 32 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 26 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 27 | @FFFFFFF8 28 | 00 00 04 F0 50 10 04 F0 29 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/hello_world_dccm.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 73 10 20 B0 73 10 20 B8 97 00 00 00 93 80 80 11 3 | 73 90 50 30 B7 50 55 5F 93 80 50 55 73 90 00 7C 4 | B7 01 58 D0 17 02 04 70 13 02 C2 FD 83 02 02 00 5 | 23 80 51 00 05 02 E3 9B 02 FE 13 05 F0 0F B7 01 6 | 58 D0 23 80 A1 00 E3 0C 00 FE 01 00 01 00 01 00 7 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 8 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 9 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 10 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 11 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 12 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 13 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 14 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 15 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 17 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 18 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 19 | 01 00 01 00 13 00 00 00 13 00 00 00 13 00 00 00 20 | 05 45 31 BF 00 00 00 00 00 00 00 00 00 00 00 00 21 | @F0040000 22 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 23 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 65 6C 6C 6F 20 24 | 57 6F 72 6C 64 20 66 72 6F 6D 20 56 65 65 52 20 25 | 45 4C 32 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 26 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 27 | @FFFFFFF8 28 | 00 00 04 F0 50 10 04 F0 29 | -------------------------------------------------------------------------------- /.github/workflows/test-renode.yml: -------------------------------------------------------------------------------- 1 | name: Renode tests 2 | 3 | on: 4 | workflow_call: 5 | 6 | jobs: 7 | tests: 8 | runs-on: ubuntu-24.04 9 | container: ghcr.io/antmicro/cores-veer-el2:20250411084921 10 | strategy: 11 | fail-fast: false 12 | env: 13 | DEBIAN_FRONTEND: "noninteractive" 14 | steps: 15 | - name: Clone repository 16 | uses: actions/checkout@v4 17 | with: 18 | submodules: recursive 19 | 20 | - name: Install dependencies 21 | run: | 22 | sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ 23 | git python3 python3-pip build-essential ninja-build ccache \ 24 | gcc-riscv64-unknown-elf 25 | pip3 install meson 26 | 27 | - name: Build tests 28 | run: | 29 | export RV_ROOT=`pwd` 30 | cd ./tools/renode 31 | ./build-all-tests.sh 32 | 33 | - name: Run tests 34 | run: | 35 | cd ./tools/renode 36 | pip install -r /opt/renode/tests/requirements.txt 37 | /opt/renode/renode-test veer.robot 38 | 39 | - name: Upload artifacts 40 | if: always() 41 | uses: actions/upload-artifact@v4 42 | with: 43 | name: renode_results 44 | path: | 45 | tools/renode/log.html 46 | tools/renode/report.html 47 | tools/renode/robot_output.xml 48 | -------------------------------------------------------------------------------- /.github/workflows/test-uvm.yml: -------------------------------------------------------------------------------- 1 | name: VeeR-EL2 verification 2 | 3 | on: 4 | workflow_call: 5 | 6 | jobs: 7 | tests: 8 | name: UVM tests 9 | runs-on: ubuntu-24.04 10 | container: ghcr.io/antmicro/cores-veer-el2:20250411084921 11 | env: 12 | CCACHE_DIR: "/opt/uvm/.cache/" 13 | DEBIAN_FRONTEND: "noninteractive" 14 | steps: 15 | - name: Setup repository 16 | uses: actions/checkout@v3 17 | with: 18 | submodules: recursive 19 | 20 | - name: Install prerequisities 21 | run: | 22 | sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ 23 | git build-essential ccache 24 | 25 | - name: Setup environment 26 | run: | 27 | echo "/opt/verilator/bin" >> $GITHUB_PATH 28 | RV_ROOT=`pwd` 29 | echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV 30 | PYTHONUNBUFFERED=1 31 | echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV 32 | 33 | - name: Build UVM testbench 34 | run: | 35 | make -C testbench/uvm/mem build -j$(nproc) 36 | 37 | - name: Run UVM testbench 38 | run: | 39 | make -C testbench/uvm/mem simulate | tee test.out 40 | 41 | - name: Upload test output 42 | if: always() 43 | uses: actions/upload-artifact@v4 44 | with: 45 | name: uvm_test_output 46 | path: test.out 47 | -------------------------------------------------------------------------------- /verification/block/dmi/test_jtag_ir.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import pyuvm 5 | from jtag_pkg import JTAGInstructions 6 | from jtag_seq import * 7 | from testbench import BaseTest 8 | 9 | 10 | @pyuvm.test() 11 | class TestJTAGSetIR(BaseTest): 12 | def end_of_elaboration_phase(self): 13 | self.seqr = ConfigDB().get(None, "", "JTAG_SEQR") 14 | self.set_ir_seq = SetIRSequence("set_ir_seq", JTAGInstructions.DEVICE_ID_SEL.integer) 15 | 16 | async def run(self): 17 | await self.set_ir_seq.start(self.seqr) 18 | 19 | 20 | @pyuvm.test() 21 | class TestJTAGReadIDCODE(BaseTest): 22 | def end_of_elaboration_phase(self): 23 | self.seqr = ConfigDB().get(None, "", "JTAG_SEQR") 24 | self.read_idcode_seq = CaptureDRSequence("read_idcode_seq") 25 | 26 | async def run(self): 27 | await self.read_idcode_seq.start(self.seqr) 28 | 29 | 30 | @pyuvm.test() 31 | class TestJTAGSetIRReadDR(BaseTest): 32 | def end_of_elaboration_phase(self): 33 | self.seqr = ConfigDB().get(None, "", "JTAG_SEQR") 34 | self.set_ir_seq = SetIRSequence("set_ir_seq", JTAGInstructions.DEVICE_ID_SEL.integer) 35 | self.read_idcode_seq = CaptureDRSequence("read_idcode_seq") 36 | 37 | async def run(self): 38 | await self.set_ir_seq.start(self.seqr) 39 | await self.read_idcode_seq.start(self.seqr) 40 | -------------------------------------------------------------------------------- /verification/block/dma/test_address.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import pyuvm 5 | from scoreboards import AccessScoreboard 6 | from sequences import InvalidAddressSequence 7 | from testbench import BaseEnv, BaseTest 8 | 9 | # ============================================================================= 10 | 11 | 12 | class TestEnv(BaseEnv): 13 | def build_phase(self): 14 | super().build_phase() 15 | 16 | # Add scoreboard 17 | self.scoreboard = AccessScoreboard("scoreboard", self) 18 | 19 | def connect_phase(self): 20 | super().connect_phase() 21 | 22 | # Connect monitors 23 | self.axi_mon.ap.connect(self.scoreboard.fifo.analysis_export) 24 | self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export) 25 | 26 | 27 | # ============================================================================= 28 | 29 | 30 | @pyuvm.test() 31 | class TestAddressOutOfRange(BaseTest): 32 | """ 33 | Out of range addressing test 34 | """ 35 | 36 | def __init__(self, name, parent): 37 | super().__init__(name, parent, TestEnv) 38 | 39 | def end_of_elaboration_phase(self): 40 | super().end_of_elaboration_phase() 41 | self.seq = InvalidAddressSequence("stimulus", dwidth=self.env.axi_bfm.dwidth) 42 | 43 | async def run(self): 44 | await self.seq.start(self.env.axi_seqr) 45 | -------------------------------------------------------------------------------- /verification/block/dma/test_debug_address.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import pyuvm 5 | from scoreboards import AccessScoreboard 6 | from sequences import InvalidAddressSequence 7 | from testbench import BaseEnv, BaseTest 8 | 9 | # ============================================================================= 10 | 11 | 12 | class TestEnv(BaseEnv): 13 | def build_phase(self): 14 | super().build_phase() 15 | 16 | # Add scoreboard 17 | self.scoreboard = AccessScoreboard("scoreboard", self) 18 | 19 | def connect_phase(self): 20 | super().connect_phase() 21 | 22 | # Connect monitors 23 | self.dbg_mon.ap.connect(self.scoreboard.fifo.analysis_export) 24 | self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export) 25 | 26 | 27 | # ============================================================================= 28 | 29 | 30 | @pyuvm.test() 31 | class TestAddressOutOfRange(BaseTest): 32 | """ 33 | Out of range addressing test 34 | """ 35 | 36 | def __init__(self, name, parent): 37 | super().__init__(name, parent, TestEnv) 38 | 39 | def end_of_elaboration_phase(self): 40 | super().end_of_elaboration_phase() 41 | self.seq = InvalidAddressSequence("stimulus", dwidth=32) # The debug bus is 32-bit wide 42 | 43 | async def run(self): 44 | await self.seq.start(self.env.dbg_seqr) 45 | -------------------------------------------------------------------------------- /docs/source/errata.md: -------------------------------------------------------------------------------- 1 | # Errata 2 | 3 | ## Back-To-Back Write Transactions Not Supported on AHB-Lite Bus 4 | 5 | * **Description**: 6 | The AHB-Lite bus interface for LSU is not optimized for write performance. 7 | Each aligned store is issued to the bus as a single write transaction followed by an idle cycle. 8 | Each unaligned store is issued to the bus as multiple backto-back byte write transactions followed by an idle cycle. 9 | These idle cycles limit the achievable bus utilization for writes. 10 | * **Symptoms**: Potential performance impact for writes with AHB-Lite bus. 11 | * **Workaround**: None. 12 | 13 | ## Debug Abstract Command Register May Return Non-Zero Value On Read 14 | 15 | * **Description**: 16 | The RISC-V External Debug specification specifies the abstract command (`command`) register as write-only (see Section 3.14.7 in [[3]](intro.md#ref-3)). 17 | However, the VeeR EL2 implementation supports write as well as read operations to this register. 18 | This may help a debugger's feature discovery process, but is not fully compliant with the RISC-V External Debug specification. 19 | Because the expected return value for reading this register is always zero, it is unlikely that a debugger expecting a zero value would attempt to read it. 20 | * **Symptoms**: Reading the debug abstract command (`command`) register may return a non-zero value. 21 | * **Workaround**: A debugger should avoid reading the abstract command register if it cannot handle non-zero data. 22 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_sequence.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | // this sequence wites random random data to random address, then reads it back 5 | class dccm_write_read_sequence extends uvm_sequence #(dccm_transaction_sequence_item); 6 | 7 | `uvm_object_utils(dccm_write_read_sequence) 8 | 9 | function new(string name = "write_read_sequence"); 10 | super.new(name); 11 | endfunction 12 | 13 | virtual task body(); 14 | 15 | // Do randomized write 16 | req = dccm_transaction_sequence_item::type_id::create("req"); 17 | wait_for_grant(); 18 | req.randomize(); 19 | req.wr_en = 1'b1; 20 | req.rd_en = 1'b0; 21 | send_request(req); 22 | wait_for_item_done(); 23 | 24 | // Do read from the same address 25 | wait_for_grant(); 26 | req.wr_en = 1'b0; 27 | req.rd_en = 1'b1; 28 | send_request(req); 29 | wait_for_item_done(); 30 | 31 | endtask 32 | endclass 33 | 34 | class dccm_memtest_sequence extends uvm_sequence #(dccm_transaction_sequence_item); 35 | 36 | dccm_write_read_sequence seq; 37 | int loops; 38 | 39 | `uvm_object_utils(dccm_memtest_sequence) 40 | 41 | function new(string name = "dccm_memtest_sequence"); 42 | super.new(name); 43 | endfunction 44 | 45 | virtual task body(); 46 | repeat (loops) begin 47 | `uvm_do(seq) 48 | end 49 | endtask 50 | endclass 51 | //========================================================================= 52 | -------------------------------------------------------------------------------- /.github/workflows/gh-pages-pr-comment.yml: -------------------------------------------------------------------------------- 1 | name: GH-Pages PR Comment 2 | 3 | on: 4 | workflow_run: 5 | workflows: ["VeeR-EL2 CI"] 6 | types: 7 | - completed 8 | 9 | env: 10 | WEB_URL: 'https://chipsalliance.github.io/Cores-VeeR-EL2/' 11 | 12 | jobs: 13 | comment: 14 | name: PR Comment 15 | runs-on: ubuntu-24.04 16 | permissions: 17 | pull-requests: write 18 | if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }} 19 | steps: 20 | 21 | - name: Download artifact 22 | id: download-artifact 23 | uses: dawidd6/action-download-artifact@v2 24 | with: 25 | name: pr_number 26 | path: ./ 27 | run_id: ${{ github.event.workflow_run.id }} 28 | 29 | - name: Extract PR number 30 | id: PR 31 | run: | 32 | cat pr_number.txt | tee "$GITHUB_OUTPUT" 33 | 34 | - uses: actions/github-script@v6 35 | with: 36 | script: | 37 | github.rest.issues.createComment({ 38 | issue_number: ${{ steps.PR.outputs.number }}, 39 | owner: context.repo.owner, 40 | repo: context.repo.repo, 41 | body: 'Coverage report for this PR is available at ${{ env.WEB_URL }}/html/dev/${{ steps.PR.outputs.number }}/coverage_dashboard/all, documentation is available at ${{ env.WEB_URL }}/html/dev/${{ steps.PR.outputs.number }}/docs_rendered/html' 42 | }) 43 | -------------------------------------------------------------------------------- /configs/veer_config_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from fusesoc.capi2.generator import Generator 3 | import os 4 | import subprocess 5 | import sys 6 | 7 | class VeerConfigGenerator(Generator): 8 | def run(self): 9 | script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..')) 10 | files = [ 11 | {"common_defines.vh" : { 12 | "copyto" : "config/common_defines.vh", 13 | "file_type" : "systemVerilogSource"}}, 14 | {"el2_pdef.vh" : { 15 | "copyto" : "config/el2_pdef.vh", 16 | "file_type" : "systemVerilogSource"}}, 17 | {"el2_param.vh" : { 18 | "is_include_file" : True, 19 | "file_type" : "systemVerilogSource"}}, 20 | {"pic_map_auto.h" : { 21 | "is_include_file" : True, 22 | "file_type" : "systemVerilogSource"}}] 23 | 24 | env = os.environ.copy() 25 | env['RV_ROOT'] = script_root 26 | env['BUILD_PATH'] = os.getcwd() 27 | args = ['configs/veer.config'] + self.config.get('args', []) 28 | 29 | rc = subprocess.call(args, cwd=script_root, env=env, stdout=subprocess.DEVNULL) 30 | if rc: 31 | exit(1) 32 | filenames = [] 33 | for f in files: 34 | for k in f: 35 | filenames.append(k) 36 | 37 | self.add_files(files) 38 | 39 | g = VeerConfigGenerator() 40 | g.run() 41 | g.write() 42 | -------------------------------------------------------------------------------- /testbench/jtagdpi/jtagdpi.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Copyright 2024 Antmicro 3 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 4 | // SPDX-License-Identifier: Apache-2.0 5 | 6 | module jtagdpi #( 7 | parameter string Name = "jtag0", // name of the JTAG interface (display only) 8 | parameter int ListenPort = 44853 // TCP port to listen on 9 | )( 10 | input logic clk_i, 11 | input logic rst_ni, 12 | 13 | output logic jtag_tck, 14 | output logic jtag_tms, 15 | output logic jtag_tdi, 16 | input logic jtag_tdo, 17 | output logic jtag_trst_n, 18 | output logic jtag_srst_n 19 | ); 20 | 21 | import "DPI-C" 22 | function chandle jtagdpi_create(input string name, input int listen_port); 23 | 24 | import "DPI-C" 25 | function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms, 26 | output bit tdi, output bit trst_n, 27 | output bit srst_n, input bit tdo); 28 | 29 | import "DPI-C" 30 | function void jtagdpi_close(input chandle ctx); 31 | 32 | chandle ctx; 33 | 34 | initial begin 35 | ctx = jtagdpi_create(Name, ListenPort); 36 | end 37 | 38 | final begin 39 | jtagdpi_close(ctx); 40 | ctx = null; 41 | end 42 | 43 | always_ff @(posedge clk_i, negedge rst_ni) begin 44 | jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n, 45 | jtag_tdo); 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /tools/picmap: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | 3 | use Getopt::Long; 4 | 5 | use integer; 6 | 7 | $helpusage = "placeholder"; 8 | 9 | GetOptions ('total_int=s' => \$total_int)|| die("$helpusage"); 10 | 11 | $LEN=15; 12 | 13 | #printf("logic [2:0] mask;\n"); 14 | 15 | printf("// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }\n"); 16 | printf("always_comb begin\n"); 17 | printf(" case \(address[14:0]\)\n"); 18 | printf(" 15'b011000000000000 : mask[3:0] = 4'b0100;\n"); 19 | for ($i=1; $i<=$total_int; $i++) { 20 | $j=hex("4000"); 21 | printf(" 15'b%s : mask[3:0] = 4'b1000;\n",d2b($j+$i*4)); 22 | } 23 | for ($i=1; $i<=$total_int; $i++) { 24 | $j=hex("2000"); 25 | printf(" 15'b%s : mask[3:0] = 4'b0100;\n",d2b($j+$i*4)); 26 | } 27 | for ($i=1; $i<=$total_int; $i++) { 28 | $j=hex("0"); 29 | printf(" 15'b%s : mask[3:0] = 4'b0010;\n",d2b($j+$i*4)); 30 | } 31 | printf(" %-17s : mask[3:0] = 4'b0001;\n","default"); 32 | printf(" endcase\n"); 33 | printf("end\n"); 34 | 35 | 36 | sub b2d { 37 | my ($v) = @_; 38 | 39 | $v = oct("0b" . $v); 40 | 41 | return($v); 42 | } 43 | 44 | sub d2b { 45 | my ($v) = @_; 46 | 47 | my $repeat; 48 | 49 | $v = sprintf "%b",$v; 50 | if (length($v)<$LEN) { 51 | $repeat=$LEN-length($v); 52 | $v="0"x$repeat.$v; 53 | } 54 | elsif (length($v)>$LEN) { 55 | $v=substr($v,length($v)-$LEN,$LEN); 56 | } 57 | 58 | return($v); 59 | } 60 | -------------------------------------------------------------------------------- /.github/scripts/create_merged_package.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -eux 4 | set -o pipefail 5 | 6 | # The script needs to be run with V package prepared in data_v 7 | # and Verilator package prepared in data_verilator. 8 | 9 | # Note that config.json will contain output of this script. 10 | # It will be basically data_v/config.json with "datasets" key removed 11 | # so that it's regenerated by info-process with minor other modifications. 12 | python3 <config.json 13 | import json 14 | 15 | with open('data_v/config.json') as f: 16 | config = json.load(f) 17 | 18 | with open('data_verilator/config.json') as f: 19 | verilator_config = json.load(f) 20 | 21 | db_count_v = config['additional'].pop('db_count') 22 | config['additional']['db_count_verilator'] = verilator_config['additional']['db_count'] 23 | config['additional']['db_count_v'] = db_count_v 24 | 25 | config['timestamp'] = '`date +"%Y-%m-%dT%H:%M:%S.%3N%z"`' 26 | 27 | del config['datasets'] 28 | 29 | print(json.dumps(config, indent=2)) 30 | END 31 | 32 | _out_dir=data_both 33 | 34 | # The order of INFO files influences order of datasets that will be 35 | # generated based on passed INFO files and added to config.json. 36 | info-process pack --output $_out_dir --config config.json \ 37 | --coverage-files data_v/*.info data_verilator/*.info \ 38 | --description-files data_verilator/*.desc data_v/*.desc \ 39 | --extra-files data_v/logo.svg 40 | 41 | cat $_out_dir/config.json 42 | 43 | echo "Merged coverage data ready to be packaged in $PWD/$_out_dir" 44 | -------------------------------------------------------------------------------- /testbench/asm/infinite_loop.s: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // Copyright 2024 Antmicro 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | // 17 | 18 | // Copied hello_world_iccm with an infinite loop inserted at the end 19 | 20 | #include "defines.h" 21 | 22 | #define STDOUT 0xd0580000 23 | 24 | .set mfdc, 0x7f9 25 | .extern printf_start, printf_end 26 | // Code to execute 27 | .section .text 28 | .global _start 29 | _start: 30 | 31 | 32 | 33 | // Enable Caches in MRAC 34 | li x1, 0x5f555555 35 | csrw 0x7c0, x1 36 | li x3, 4 37 | csrw mfdc, x3 // disable store merging 38 | 39 | // Simple infinite loop program with inner and outer loop 40 | li t3, 0 41 | outer: 42 | addi t3, t3, 1 43 | li t4, 123 44 | inner: 45 | addi t4, t4, -1 46 | bne t4, zero, inner 47 | jal x0, outer 48 | .long 0,1,2,3,4 49 | -------------------------------------------------------------------------------- /verification/block/exu_alu/test_logic.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseSequence, BaseTest 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestAnd(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = BaseSequence("stimulus", ["and"]) 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.alu_seqr) 21 | 22 | 23 | @pyuvm.test() 24 | class TestOr(BaseTest): 25 | def end_of_elaboration_phase(self): 26 | super().end_of_elaboration_phase() 27 | self.seq = BaseSequence("stimulus", ["or"]) 28 | 29 | async def run(self): 30 | await self.seq.start(self.env.alu_seqr) 31 | 32 | 33 | @pyuvm.test() 34 | class TestXor(BaseTest): 35 | def end_of_elaboration_phase(self): 36 | super().end_of_elaboration_phase() 37 | self.seq = BaseSequence("stimulus", ["xor"]) 38 | 39 | async def run(self): 40 | await self.seq.start(self.env.alu_seqr) 41 | 42 | 43 | @pyuvm.test() 44 | class TestAll(BaseTest): 45 | def end_of_elaboration_phase(self): 46 | super().end_of_elaboration_phase() 47 | self.seq = BaseSequence("stimulus", ["and", "or", "xor"]) 48 | 49 | async def run(self): 50 | await self.seq.start(self.env.alu_seqr) 51 | -------------------------------------------------------------------------------- /testbench/tests/pmp/fault.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 2 | * Copyright 2023 Antmicro, Ltd. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #include 18 | #include 19 | #include "veer.h" 20 | #include "trap.h" 21 | #include "fault.h" 22 | 23 | volatile struct rv_jmp_buf* fault_jmp_env = NULL; 24 | volatile struct fault fault_last; 25 | 26 | void fault_setjmp(struct rv_jmp_buf* env) 27 | { 28 | fault_jmp_env = env; 29 | } 30 | 31 | struct fault fault_last_get(void) 32 | { 33 | return fault_last; 34 | } 35 | 36 | void fault_return(const struct fault *fault) 37 | { 38 | // Save register state for later usage 39 | memcpy((struct fault*)&fault_last, fault, sizeof(fault_last)); 40 | 41 | // Return to program if setjmp-based try-catch was used 42 | if (fault_jmp_env != NULL) { 43 | struct rv_jmp_buf* env = (struct rv_jmp_buf*)fault_jmp_env; 44 | fault_jmp_env = NULL; 45 | rv_longjmp_m(env, 1); 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_base_test.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | `include "dccm_agent.sv" 5 | `include "dccm_scoreboard.sv" 6 | class mem_model_base_test extends uvm_test; 7 | 8 | `uvm_component_utils(mem_model_base_test) 9 | 10 | dccm_agent agent; 11 | dccm_scoreboard scoreboard; 12 | 13 | function new(string name = "mem_model_base_test", uvm_component parent = null); 14 | super.new(name, parent); 15 | endfunction : new 16 | 17 | virtual function void build_phase(uvm_phase phase); 18 | super.build_phase(phase); 19 | 20 | agent = dccm_agent::type_id::create("agent", this); 21 | scoreboard = dccm_scoreboard::type_id::create("scoreboard", this); 22 | endfunction : build_phase 23 | 24 | function void connect_phase(uvm_phase phase); 25 | agent.monitor.transaction_analisys_port.connect(scoreboard.item_collected_export); 26 | endfunction : connect_phase 27 | 28 | function void report_phase(uvm_phase phase); 29 | uvm_report_server svr; 30 | int errors; 31 | super.report_phase(phase); 32 | 33 | svr = uvm_report_server::get_server(); 34 | errors = svr.get_severity_count(UVM_FATAL) + svr.get_severity_count(UVM_ERROR); 35 | if (errors > 0) begin 36 | `uvm_info(get_type_name(), "DCCM TEST FAILED!!", UVM_NONE) 37 | `uvm_info(get_type_name(), $sformatf("Found %d errors", errors), UVM_NONE) 38 | end else begin 39 | `uvm_info(get_type_name(), "DCCM TEST PASSED!!", UVM_NONE) 40 | end 41 | endfunction 42 | 43 | endclass : mem_model_base_test 44 | -------------------------------------------------------------------------------- /verification/block/exu_alu/test_zba.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2023 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | import random 4 | 5 | import pyuvm 6 | from cocotb.triggers import ClockCycles 7 | from pyuvm import * 8 | from testbench import BaseSequence, BaseTest 9 | 10 | # ============================================================================= 11 | 12 | 13 | @pyuvm.test() 14 | class TestSh1add(BaseTest): 15 | def end_of_elaboration_phase(self): 16 | super().end_of_elaboration_phase() 17 | self.seq = BaseSequence("stimulus", ["sh1add"]) 18 | 19 | async def run(self): 20 | await self.seq.start(self.env.alu_seqr) 21 | 22 | 23 | @pyuvm.test() 24 | class TestSh2add(BaseTest): 25 | def end_of_elaboration_phase(self): 26 | super().end_of_elaboration_phase() 27 | self.seq = BaseSequence("stimulus", ["sh2add"]) 28 | 29 | async def run(self): 30 | await self.seq.start(self.env.alu_seqr) 31 | 32 | 33 | @pyuvm.test() 34 | class TestSh3add(BaseTest): 35 | def end_of_elaboration_phase(self): 36 | super().end_of_elaboration_phase() 37 | self.seq = BaseSequence("stimulus", ["sh3add"]) 38 | 39 | async def run(self): 40 | await self.seq.start(self.env.alu_seqr) 41 | 42 | 43 | @pyuvm.test() 44 | class TestAll(BaseTest): 45 | def end_of_elaboration_phase(self): 46 | super().end_of_elaboration_phase() 47 | self.seq = BaseSequence("stimulus", ["sh1add", "sh2add", "sh3add"]) 48 | 49 | async def run(self): 50 | await self.seq.start(self.env.alu_seqr) 51 | -------------------------------------------------------------------------------- /testbench/asm/icache.s: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2024 Antmicro 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | // 16 | 17 | #include "defines.h" 18 | 19 | #define STDOUT 0xd0580000 20 | 21 | .set mfdc, 0x7f9 22 | .set mrac, 0x7c0 23 | // Code to execute 24 | .section .text 25 | .global _start 26 | _start: 27 | // Enable Caches in MRAC 28 | li x1, 0x5f555555 29 | csrw mrac, x1 30 | li x3, 4 31 | csrw mfdc, x3 // disable store merging 32 | 33 | li t3, 0 // counter for the outer loop 34 | li t5, 100 // limit the outer loop to 100 iterations 35 | outer: 36 | beq t3, t5, report_success 37 | addi t3, t3, 1 38 | li t4, 123 39 | inner: 40 | addi t4, t4, -1 41 | bne t4, zero, inner 42 | jal x0, outer 43 | report_success: 44 | // write 0xff to STDOUT to report success 45 | li x3, STDOUT 46 | li x2, 0xff 47 | sw x2, 0(x3) 48 | end: 49 | nop 50 | j end 51 | .long 0,1,2,3,4 52 | -------------------------------------------------------------------------------- /testbench/hex/user_mode0/hello_world_iccm.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 97 00 00 00 93 80 00 13 73 90 50 30 B7 50 55 5F 3 | 93 80 50 55 73 90 00 7C 91 41 73 90 91 7F B7 01 4 | 00 EE 17 02 00 00 13 02 E2 17 97 02 00 00 93 82 5 | A2 1A 03 23 02 00 23 A0 61 00 11 02 91 01 E3 6A 6 | 52 FE 0F 10 00 00 97 00 00 6E E7 80 A0 FB B7 01 7 | 58 D0 23 80 A1 00 E3 0C 00 FE 01 00 01 00 01 00 8 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 9 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 10 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 11 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 12 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 13 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 14 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 15 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 17 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 18 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 19 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 20 | 01 00 01 00 13 00 00 00 13 00 00 00 13 00 00 00 21 | 05 45 31 BF 00 00 00 00 00 00 00 00 00 00 00 00 22 | 00 00 23 | @80000142 24 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 25 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 26 | 65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20 27 | 56 65 65 52 20 45 4C 32 20 49 43 43 4D 0A 2D 2D 28 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 29 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 30 | @800001A0 31 | B7 01 58 D0 17 02 00 92 13 02 E2 13 83 02 02 00 32 | 23 80 51 00 05 02 E3 9B 02 FE 13 05 F0 0F 82 80 33 | 00 00 00 00 01 00 00 00 02 00 00 00 03 00 00 00 34 | 04 00 00 00 35 | -------------------------------------------------------------------------------- /testbench/hex/user_mode1/hello_world_iccm.hex: -------------------------------------------------------------------------------- 1 | @80000000 2 | 97 00 00 00 93 80 00 13 73 90 50 30 B7 50 55 5F 3 | 93 80 50 55 73 90 00 7C 91 41 73 90 91 7F B7 01 4 | 00 EE 17 02 00 00 13 02 E2 17 97 02 00 00 93 82 5 | A2 1A 03 23 02 00 23 A0 61 00 11 02 91 01 E3 6A 6 | 52 FE 0F 10 00 00 97 00 00 6E E7 80 A0 FB B7 01 7 | 58 D0 23 80 A1 00 E3 0C 00 FE 01 00 01 00 01 00 8 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 9 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 10 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 11 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 12 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 13 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 14 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 15 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 16 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 17 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 18 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 19 | 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 20 | 01 00 01 00 13 00 00 00 13 00 00 00 13 00 00 00 21 | 05 45 31 BF 00 00 00 00 00 00 00 00 00 00 00 00 22 | 00 00 23 | @80000142 24 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 25 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 26 | 65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20 27 | 56 65 65 52 20 45 4C 32 20 49 43 43 4D 0A 2D 2D 28 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 29 | 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 30 | @800001A0 31 | B7 01 58 D0 17 02 00 92 13 02 E2 13 83 02 02 00 32 | 23 80 51 00 05 02 E3 9B 02 FE 13 05 F0 0F 82 80 33 | 00 00 00 00 01 00 00 00 02 00 00 00 03 00 00 00 34 | 04 00 00 00 35 | -------------------------------------------------------------------------------- /verification/block/pmp/el2_pmp_wrapper.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | module el2_pmp_wrapper 5 | import el2_pkg::*; 6 | #( 7 | parameter PMP_CHANNELS = 3, 8 | `include "el2_param.vh" 9 | ) ( 10 | input logic clk, // Top level clock 11 | input logic rst_l, // Reset 12 | input logic scan_mode, // Scan mode 13 | 14 | input [7:0] pmp_pmpcfg [pt.PMP_ENTRIES], 15 | input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES], 16 | 17 | input logic [ 31:0] pmp_chan_addr[PMP_CHANNELS], 18 | input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS], 19 | output logic [PMP_CHANNELS-1:0] pmp_chan_err 20 | ); 21 | logic pmp_chan_err_unpacked[PMP_CHANNELS]; 22 | el2_pmp_cfg_pkt_t pmp_pmpcfg_int [pt.PMP_ENTRIES]; 23 | 24 | for (genvar c = 0; c < PMP_CHANNELS; c++) begin 25 | assign pmp_chan_err[PMP_CHANNELS-1-c] = pmp_chan_err_unpacked[c]; 26 | end 27 | 28 | for (genvar e = 0; e < pt.PMP_ENTRIES; e++) begin 29 | assign pmp_pmpcfg_int[e].lock = pmp_pmpcfg[e][7]; 30 | assign pmp_pmpcfg_int[e].reserved = pmp_pmpcfg[e][6:5]; 31 | assign pmp_pmpcfg_int[e].mode = el2_pkg::el2_pmp_mode_pkt_t'(pmp_pmpcfg[e][4:3]); 32 | assign pmp_pmpcfg_int[e].execute = pmp_pmpcfg[e][2]; 33 | assign pmp_pmpcfg_int[e].write = pmp_pmpcfg[e][1]; 34 | assign pmp_pmpcfg_int[e].read= pmp_pmpcfg[e][0]; 35 | end 36 | 37 | // The PMP module 38 | el2_pmp pmp ( 39 | .pmp_chan_err(pmp_chan_err_unpacked), 40 | .pmp_pmpcfg(pmp_pmpcfg_int), 41 | .* 42 | ); 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /verification/block/pmp_random/el2_pmp_wrapper.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | module el2_pmp_wrapper 5 | import el2_pkg::*; 6 | #( 7 | parameter PMP_CHANNELS = 3, 8 | `include "el2_param.vh" 9 | ) ( 10 | input logic clk, // Top level clock 11 | input logic rst_l, // Reset 12 | input logic scan_mode, // Scan mode 13 | 14 | input [7:0] pmp_pmpcfg [pt.PMP_ENTRIES], 15 | input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES], 16 | 17 | input logic [ 31:0] pmp_chan_addr[PMP_CHANNELS], 18 | input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS], 19 | output logic [PMP_CHANNELS-1:0] pmp_chan_err 20 | ); 21 | logic pmp_chan_err_unpacked[PMP_CHANNELS]; 22 | el2_pmp_cfg_pkt_t pmp_pmpcfg_int [pt.PMP_ENTRIES]; 23 | 24 | for (genvar c = 0; c < PMP_CHANNELS; c++) begin 25 | assign pmp_chan_err[PMP_CHANNELS-1-c] = pmp_chan_err_unpacked[c]; 26 | end 27 | 28 | for (genvar e = 0; e < pt.PMP_ENTRIES; e++) begin 29 | assign pmp_pmpcfg_int[e].lock = pmp_pmpcfg[e][7]; 30 | assign pmp_pmpcfg_int[e].reserved = pmp_pmpcfg[e][6:5]; 31 | assign pmp_pmpcfg_int[e].mode = el2_pkg::el2_pmp_mode_pkt_t'(pmp_pmpcfg[e][4:3]); 32 | assign pmp_pmpcfg_int[e].execute = pmp_pmpcfg[e][2]; 33 | assign pmp_pmpcfg_int[e].write = pmp_pmpcfg[e][1]; 34 | assign pmp_pmpcfg_int[e].read= pmp_pmpcfg[e][0]; 35 | end 36 | 37 | // The PMP module 38 | el2_pmp pmp ( 39 | .pmp_chan_err(pmp_chan_err_unpacked), 40 | .pmp_pmpcfg(pmp_pmpcfg_int), 41 | .* 42 | ); 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /tools/hex_canned_update.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Expected usage: 3 | # export RV_ROOT=/path/to/cores-veer-el2 4 | # bash tools/hex_canned_update.sh 5 | 6 | if [[ -z "$RV_ROOT" ]]; then 7 | echo "RV_ROOT is not set" 1>&2 8 | exit 1 9 | fi 10 | 11 | ASM=($(find $RV_ROOT/testbench/asm -maxdepth 1 -regex ".*\.\(s\|mki\)" -printf "%f\n" | sed 's/\.\(s\|mki\)$//' | grep -vE "(common|crt0)")) 12 | CT=($(find $RV_ROOT/testbench/tests -mindepth 1 -type d -printf "%f\n")) 13 | TESTS=("${ASM[@]}" "${CT[@]}") 14 | echo "Detected tests:" 15 | echo "---------------" 16 | echo "${TESTS[@]}" 17 | echo "---------------" 18 | 19 | USER_MODES=("0" "1") 20 | 21 | MAKE_CMD="make -f $RV_ROOT/tools/Makefile" 22 | HEX_DIR=testbench/hex 23 | 24 | # Clear old hex files 25 | rm -rdf $HEX_DIR/* 26 | 27 | PARAMS="" 28 | for umode in ${USER_MODES[@]}; do 29 | mkdir -p $HEX_DIR/user_mode$umode 30 | for test in ${TESTS[@]}; do 31 | if [[ "$umode" == "1" ]]; then 32 | PARAMS="-set=user_mode=1 -set=smepmp=1 $PARAMS" 33 | # csr_mseccfg test is only available in user mode 34 | elif [[ "$test" == "csr_mseccfg" ]]; then 35 | continue 36 | fi 37 | $MAKE_CMD clean >/dev/null 38 | $MAKE_CMD program.hex CONF_PARAMS="$PARAMS" TEST=$test >/dev/null 39 | HEX_PATH="$HEX_DIR/user_mode$umode/$test.hex" 40 | echo "TEST = " $test 41 | if [ -f "program.hex" ]; then 42 | echo "Copying $test:program.hex to ["$HEX_PATH"]" 43 | cp program.hex $HEX_PATH 44 | else 45 | echo "program.hex not found. Possible build error." 46 | exit 1 47 | fi 48 | done 49 | done 50 | exit 0 51 | -------------------------------------------------------------------------------- /testbench/asm/crt0.s: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | # Copyright 2020 Western Digital Corporation or its affiliates. 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | // startup code to support HLL programs 17 | 18 | #include "defines.h" 19 | 20 | .section .text.init 21 | .align 4 22 | .global _start 23 | _start: 24 | 25 | // Set trap handler 26 | la x1, _trap 27 | csrw mtvec, x1 28 | 29 | // enable caching, except region 0xd 30 | li t0, 0x59555555 31 | csrw 0x7c0, t0 32 | 33 | la sp, STACK 34 | 35 | call main 36 | 37 | # Map exit code of main() to command to be written to tohost 38 | snez a0, a0 39 | bnez a0, _finish 40 | li a0, 0xFF 41 | 42 | .global _finish 43 | _finish: 44 | la t0, tohost 45 | sb a0, 0(t0) // DemoTB test termination 46 | li a0, 1 47 | sw a0, 0(t0) // Whisper test termination 48 | beq x0, x0, _finish 49 | .rept 10 50 | nop 51 | .endr 52 | 53 | .align 4 54 | _trap: 55 | li a0, 1 # failure 56 | j _finish 57 | 58 | .section .data.io 59 | .global tohost 60 | tohost: .word 0 61 | 62 | -------------------------------------------------------------------------------- /testbench/tests/pmp/veer.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 2 | * Copyright 2023 Antmicro, Ltd. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __VEER_H 18 | #define __VEER_H 19 | 20 | // Set to 1 if using HTIF interface eg. in Spike 21 | #define USE_HTIF 0 22 | 23 | #include 24 | 25 | struct rv_jmp_buf { 26 | long pc; 27 | unsigned long regs[31]; 28 | long exitcode; 29 | }; 30 | 31 | // RISC-V specific setjmp() variant. Must be called from M-mode 32 | extern long rv_setjmp_m (struct rv_jmp_buf*); 33 | // RISC-V specific longjmp() variant. Must be called from M-mode 34 | extern void rv_longjmp_m (struct rv_jmp_buf*, long exitcode); 35 | 36 | #define TRY do { struct rv_jmp_buf try_buf = {0}; if(!rv_setjmp_m(&try_buf)) { fault_setjmp(&try_buf); 37 | #define CATCH } else { 38 | #define END_TRY } } while(0) 39 | 40 | __attribute__((__noreturn__)) void _exit (int status); 41 | 42 | #if USE_HTIF 43 | #define HTIF_SYSCALL_WRITE 64 44 | #define HTIF_SYSCALL_EXIT 93 45 | 46 | int64_t veer_syscall (int64_t a0, int64_t a1, int64_t a2, int64_t a3); 47 | #endif 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /verification/block/pmp/common.py: -------------------------------------------------------------------------------- 1 | from random import randrange 2 | 3 | from pyuvm import ConfigDB, uvm_sequence 4 | from testbench import PMPCheckItem 5 | 6 | 7 | class BaseSequence(uvm_sequence): 8 | MAX_ADDR = 2**32 - 4 9 | 10 | def __init__(self, name): 11 | super().__init__(name) 12 | 13 | self.pmp_regs = ConfigDB().get(None, "", "PMP_CSRS") 14 | self.pmp_seqr = ConfigDB().get(None, "", "PMP_SEQR") 15 | self.pmp_channels = ConfigDB().get(None, "", "PMP_CHANNELS") 16 | 17 | # Access (R, W, X) memory at a given address on all channels 18 | async def accessAtAddr(self, addr): 19 | for t in range(3): 20 | type = 1 << t 21 | for c in range(self.pmp_channels): 22 | item = PMPCheckItem(channel=c, addr=addr, type=type) 23 | await self.pmp_seqr.start_item(item) 24 | await self.pmp_seqr.finish_item(item) 25 | 26 | # Try to access memory at random locations in a given address range 27 | async def randomAccessInAddrRange(self, start_addr, end_addr): 28 | addr = randrange(start_addr, end_addr, 4) 29 | await self.accessAtAddr(addr) 30 | 31 | # Access memory at a given address and at adjacent addresses 32 | async def checkRangeBoundary(self, addr): 33 | # Ensure access address is always aligned and doesn't extend 32 bits, 34 | # address is assumed to be inclusive so increment it by 1 initially. 35 | addr = min(self.MAX_ADDR, (addr + 1) & 0xFFFFFFFC) 36 | 37 | if addr >= 4: 38 | await self.accessAtAddr(addr - 4) 39 | await self.accessAtAddr(addr) 40 | if addr < self.MAX_ADDR: 41 | await self.accessAtAddr(addr + 4) 42 | -------------------------------------------------------------------------------- /verification/block/dec_tlu_ctl/common.py: -------------------------------------------------------------------------------- 1 | from random import randrange 2 | 3 | from pyuvm import ConfigDB, uvm_sequence 4 | from testbench import PMPCheckItem 5 | 6 | 7 | class BaseSequence(uvm_sequence): 8 | MAX_ADDR = 2**32 - 4 9 | 10 | def __init__(self, name): 11 | super().__init__(name) 12 | 13 | self.pmp_regs = ConfigDB().get(None, "", "PMP_CSRS") 14 | self.pmp_seqr = ConfigDB().get(None, "", "PMP_SEQR") 15 | self.pmp_channels = ConfigDB().get(None, "", "PMP_CHANNELS") 16 | 17 | # Access (R, W, X) memory at a given address on all channels 18 | async def accessAtAddr(self, addr): 19 | for t in range(3): 20 | type = 1 << t 21 | for c in range(self.pmp_channels): 22 | item = PMPCheckItem(channel=c, addr=addr, type=type) 23 | await self.pmp_seqr.start_item(item) 24 | await self.pmp_seqr.finish_item(item) 25 | 26 | # Try to access memory at random locations in a given address range 27 | async def randomAccessInAddrRange(self, start_addr, end_addr): 28 | addr = randrange(start_addr, end_addr, 4) 29 | await self.accessAtAddr(addr) 30 | 31 | # Access memory at a given address and at adjacent addresses 32 | async def checkRangeBoundary(self, addr): 33 | # Ensure access address is always aligned and doesn't extend 32 bits, 34 | # address is assumed to be inclusive so increment it by 1 initially. 35 | addr = min(self.MAX_ADDR, (addr + 1) & 0xFFFFFFFC) 36 | 37 | if addr >= 4: 38 | await self.accessAtAddr(addr - 4) 39 | await self.accessAtAddr(addr) 40 | if addr < self.MAX_ADDR: 41 | await self.accessAtAddr(addr + 4) 42 | -------------------------------------------------------------------------------- /verification/block/dmi/dmi_agent.py: -------------------------------------------------------------------------------- 1 | from dmi_bfm import DMITestBfm as BFM 2 | from pyuvm import * 3 | 4 | from common import * 5 | 6 | 7 | class DMIAgent(uvm_agent): 8 | """ 9 | Seqr <---> Driver <---> Top module 10 | Monitor <------^ 11 | """ 12 | 13 | def build_phase(self): 14 | self.seqr = uvm_sequencer("seqr", self) 15 | ConfigDB().set(None, "*", "DMI_SEQR", self.seqr) 16 | 17 | self.monitor = DMIMonitor("dmi_monitor", self, "rsp_monitor_q_get") 18 | self.driver = DMIDriver("dmi_driver", self) 19 | 20 | def connect_phase(self): 21 | self.driver.seq_item_port.connect(self.seqr.seq_item_export) 22 | 23 | 24 | class DMIDriver(uvm_driver): 25 | def build_phase(self): 26 | self.ap = uvm_analysis_port("ap_drv", self) 27 | 28 | def start_of_simulation_phase(self): 29 | self.bfm = BFM() 30 | 31 | async def run_phase(self): 32 | self.bfm.start_bfm() 33 | 34 | while True: 35 | item = await self.seq_item_port.get_next_item() 36 | await self.bfm.req_driver_q_put(item) 37 | self.seq_item_port.item_done() 38 | 39 | 40 | class DMIMonitor(uvm_component): 41 | def __init__(self, name, parent, method_name): 42 | super().__init__(name, parent) 43 | self.method_name = method_name 44 | 45 | def build_phase(self): 46 | self.ap = uvm_analysis_port("ap_mon", self) 47 | self.bfm = BFM() 48 | self.get_method = getattr(self.bfm, self.method_name) 49 | 50 | async def run_phase(self): 51 | while True: 52 | datum = await self.get_method() 53 | self.logger.debug(f"DMI Monitor req: {datum}") 54 | self.ap.write(datum) 55 | -------------------------------------------------------------------------------- /.github/scripts/riscv_dv_matrix_include.py: -------------------------------------------------------------------------------- 1 | from yaml import load, Loader 2 | from json import dumps 3 | from itertools import product 4 | import sys 5 | 6 | RISCV_DV_TESTS = ['riscv_arithmetic_basic_test'] 7 | 8 | 9 | if __name__ == "__main__": 10 | arg1 = sys.argv[1].strip() 11 | 12 | # Entries with pyflow for every RISCV_DV_TESTS. 13 | # These are included in `generate` job matrix but it's also a base for `run*` jobs. 14 | entries = [{ 15 | "test": test, 16 | "version": "pyflow", 17 | } for test in RISCV_DV_TESTS] 18 | 19 | # The argument passed needs to match the job name as variants are generated based on its matrix. 20 | if arg1.startswith('run'): 21 | with open('.github/workflows/test-riscv-dv.yml', 'rb') as fd: 22 | run_tests = load(fd, Loader=Loader)['jobs'][arg1] 23 | job_matrix = run_tests['strategy']['matrix'] 24 | 25 | # Replicate matrix entries for all variants based on the job's matrix keys and values. 26 | # 27 | # For example, if the matrix only has `test`, `version` and `iss` keys, and `iss` values 28 | # are `renode` and `spike`, then `entries` will be doubled after `key=iss` iteration as 29 | # each entry will be replaced by two entries: one with additional `iss: renode` argument 30 | # and the other with additional `iss: spike`. 31 | for key in job_matrix.keys(): 32 | if key in ['test', 'version', 'include', 'exclude']: 33 | continue 34 | entries = [{**entry, key: value} for entry, value in product(entries, job_matrix[key])] 35 | print(dumps(entries)) 36 | elif arg1 == 'generate': 37 | print(dumps(entries)) 38 | else: 39 | exit(1) 40 | -------------------------------------------------------------------------------- /verification/block/dmi/common.py: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2023 Antmicro 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | from cocotb.types import LogicArray, Range, concat 6 | from pyuvm import * 7 | 8 | # ============================================================================== 9 | 10 | 11 | class BaseSeq(uvm_sequence): 12 | async def run_items(self, items): 13 | for item in items: 14 | await self.start_item(item) 15 | item.randomize() 16 | await self.finish_item(item) 17 | 18 | 19 | class Defaults: 20 | # DMI defaults 21 | DMI_STAT = LogicArray(0, Range(11, "downto", 10)) 22 | ABITS = LogicArray(7, Range(9, "downto", 4)) 23 | VERSION = LogicArray(1, Range(3, "downto", 0)) 24 | DTMCS = concat(concat(DMI_STAT, ABITS), VERSION) 25 | 26 | # JTAG defaults 27 | REVISION_CODE = LogicArray(0x0, range(4)) 28 | MANUFACTURERS_ID_CODE = LogicArray(0x0, range(11)) 29 | DEVICE_ID_CODE = LogicArray(0x0, range(16)) 30 | JTAG_ID = concat(concat(REVISION_CODE, DEVICE_ID_CODE), MANUFACTURERS_ID_CODE) 31 | 32 | 33 | def collect_signals(signals, uut, obj): 34 | """ 35 | Collects signal objects from UUT and attaches them to the given object 36 | """ 37 | 38 | for sig in signals: 39 | if hasattr(uut, sig): 40 | s = getattr(uut, sig) 41 | 42 | else: 43 | s = None 44 | logging.error("Module {} does not have a signal '{}'".format(str(uut), sig)) 45 | 46 | setattr(obj, sig, s) 47 | 48 | 49 | def get_int(signal): 50 | if isinstance(signal, LogicArray): 51 | return signal.integer 52 | else: 53 | try: 54 | sig = int(signal) 55 | except ValueError: 56 | sig = 0 57 | return sig 58 | -------------------------------------------------------------------------------- /docs/source/conf.py: -------------------------------------------------------------------------------- 1 | from datetime import datetime 2 | 3 | from antmicro_sphinx_utils.defaults import ( 4 | extensions as default_extensions, 5 | myst_enable_extensions as default_myst_enable_extensions, 6 | myst_fence_as_directive as default_myst_fence_as_directive, 7 | antmicro_html, 8 | ) 9 | 10 | # General information about the project. 11 | project = u'RISC-V VeeR EL2 Programmer\'s Reference Manual' 12 | basic_filename = u'riscv-veer-el2-prm' 13 | authors = u'CHIPS Alliance The Linux Foundation®' 14 | copyright = f'{datetime.now().year} {authors}' 15 | 16 | # The short X.Y version. 17 | version = '' 18 | # The full version, including alpha/beta/rc tags. 19 | release = '' 20 | 21 | # This is temporary before the clash between myst-parser and immaterial is 22 | # fixed 23 | sphinx_immaterial_override_builtin_admonitions = False 24 | 25 | numfig = True 26 | 27 | # If you need to add extensions just add to those lists 28 | extensions = default_extensions 29 | myst_enable_extensions = default_myst_enable_extensions 30 | myst_fence_as_directive = default_myst_fence_as_directive 31 | 32 | myst_substitutions = { 33 | "project": project 34 | } 35 | 36 | myst_heading_anchors = 4 37 | 38 | today_fmt = '%Y-%m-%d' 39 | 40 | todo_include_todos=False 41 | 42 | # -- Options for HTML output --------------------------------------------------- 43 | 44 | html_theme = 'sphinx_immaterial' 45 | 46 | html_last_updated_fmt = today_fmt 47 | 48 | html_show_sphinx = False 49 | 50 | ( 51 | html_logo, 52 | html_theme_options, 53 | html_context 54 | ) = antmicro_html() 55 | 56 | html_theme_options["palette"][0].update({ 57 | "scheme": "slate", 58 | "primary": "teal", 59 | "accent": "white", 60 | }) 61 | 62 | def setup(app): 63 | app.add_css_file('main.css') 64 | -------------------------------------------------------------------------------- /verification/block/dmi/jtag_agent.py: -------------------------------------------------------------------------------- 1 | from jtag_bfm import JTAGBfm as BFM 2 | from pyuvm import * 3 | 4 | from common import * 5 | 6 | 7 | class JTAGAgent(uvm_agent): 8 | """ 9 | Seqr <---> Driver <---> Top module 10 | Monitor <------^ 11 | """ 12 | 13 | def build_phase(self): 14 | self.seqr = uvm_sequencer("seqr", self) 15 | ConfigDB().set(None, "*", "JTAG_SEQR", self.seqr) 16 | 17 | self.monitor = JTAGMonitor("jtag_monitor", self, "rsp_monitor_q_get") 18 | self.driver = JTAGDriver("jtag_driver", self) 19 | 20 | def connect_phase(self): 21 | self.driver.seq_item_port.connect(self.seqr.seq_item_export) 22 | 23 | 24 | class JTAGDriver(uvm_driver): 25 | def build_phase(self): 26 | self.ap = uvm_analysis_port("ap_drv", self) 27 | 28 | def start_of_simulation_phase(self): 29 | self.bfm = BFM() 30 | 31 | async def run_phase(self): 32 | await self.bfm.reset() 33 | self.bfm.start_bfm() 34 | 35 | while True: 36 | item = await self.seq_item_port.get_next_item() 37 | await self.bfm.req_driver_q_put(item.tms, item.tdi) 38 | self.seq_item_port.item_done() 39 | 40 | 41 | class JTAGMonitor(uvm_component): 42 | def __init__(self, name, parent, method_name): 43 | super().__init__(name, parent) 44 | self.method_name = method_name 45 | 46 | def build_phase(self): 47 | self.ap = uvm_analysis_port("ap_mon", self) 48 | self.bfm = BFM() 49 | self.get_method = getattr(self.bfm, self.method_name) 50 | 51 | async def run_phase(self): 52 | while True: 53 | datum = await self.get_method() 54 | self.logger.debug(f"JTAG Monitor req: {datum}") 55 | self.ap.write(datum) 56 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_driver.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | class dccm_driver extends uvm_driver #(dccm_transaction_sequence_item); 5 | 6 | virtual dccm_interface memory_vif; 7 | `uvm_component_utils(dccm_driver) 8 | 9 | function new(string name, uvm_component parent); 10 | super.new(name, parent); 11 | endfunction : new 12 | 13 | function void build_phase(uvm_phase phase); 14 | super.build_phase(phase); 15 | if (!uvm_config_db#(virtual dccm_interface)::get(this, "", "memory_vif", memory_vif)) 16 | `uvm_fatal("NO_VIF", {"virtual interface must be set for: ", get_full_name(), ".memory_vif"}); 17 | endfunction : build_phase 18 | 19 | virtual task run_phase(uvm_phase phase); 20 | forever begin 21 | seq_item_port.get_next_item(req); 22 | drive(); 23 | seq_item_port.item_done(); 24 | end 25 | endtask : run_phase 26 | 27 | virtual task drive(); 28 | memory_vif.wr_en <= 0; 29 | memory_vif.rd_en <= 0; 30 | @(posedge memory_vif.clk); 31 | 32 | memory_vif.addr <= req.addr; 33 | 34 | if (req.wr_en) begin // write operation 35 | `uvm_info(get_type_name(), $sformatf("WR: 0x%08X <= 0x%08X", req.addr, req.wdata), UVM_LOW) 36 | memory_vif.wr_en <= 1'b1; //req.wr_en; 37 | memory_vif.wdata <= req.wdata; 38 | @(posedge memory_vif.clk); 39 | end else if (req.rd_en) begin //read operation 40 | memory_vif.rd_en <= 1'b1; //req.rd_en; 41 | @(posedge memory_vif.clk); 42 | memory_vif.rd_en <= 0; 43 | @(posedge memory_vif.clk); 44 | req.rdata = memory_vif.rdata; 45 | `uvm_info(get_type_name(), $sformatf("RD: 0x%08X => 0x%08X", req.addr, req.rdata), UVM_LOW) 46 | end 47 | 48 | endtask : drive 49 | endclass : dccm_driver 50 | -------------------------------------------------------------------------------- /testbench/tests/pmp/pmp.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define PMP_LOCK (1<<7) 4 | #define PMP_OFF (0<<3) 5 | #define PMP_TOR (1<<3) 6 | #define PMP_NA4 (2<<3) 7 | #define PMP_NAPOT (3<<3) 8 | #define PMP_X (1<<2) 9 | #define PMP_W (1<<1) 10 | #define PMP_R (1<<0) 11 | 12 | #define PMP_MODE_MASK (3<<3) 13 | #define PMP_RWX_MASK (7) 14 | 15 | #define CSR_PMPCFG_BASE 0x3A0 16 | #define CSR_PMPADDR_BASE 0x3B0 17 | 18 | #define CSRR_READ(v, csr) \ 19 | /* CSRR_READ(v, csr): \ 20 | * csr: MUST be a compile time integer 12-bit constant (0-4095) \ 21 | */ \ 22 | __asm__ __volatile__ ("csrr %0, %1" \ 23 | : "=r" (v) \ 24 | : "n" (csr) \ 25 | : /* clobbers: none */ ) 26 | 27 | #define CSRR_WRITE(v, csr) \ 28 | /* CSRR_WRITE(v, csr): \ 29 | * csr: MUST be a compile time integer 12-bit constant (0-4095) \ 30 | */ \ 31 | __asm__ __volatile__ ("csrw %0, %1" \ 32 | : \ 33 | : "n" (csr), "rK" (v) \ 34 | : /* clobbers: none */ ) 35 | 36 | struct pmp_entry_s { 37 | uintptr_t addr; 38 | uint8_t cfg; 39 | }; 40 | 41 | int pmp_clear(); 42 | int pmp_read_pmpcfg(unsigned int offset, uintptr_t * dest); 43 | int pmp_read_pmpaddr(unsigned int offset, uintptr_t * dest); 44 | int pmp_write_pmpcfg(unsigned int offset, uintptr_t * src); 45 | int pmp_write_pmpaddr(unsigned int offset, uintptr_t * src); 46 | int pmp_entry_read(unsigned int id, struct pmp_entry_s * entry); 47 | int pmp_entry_write(unsigned int id, struct pmp_entry_s * entry); 48 | int pmp_is_cfg_legal(unsigned int cfg); 49 | -------------------------------------------------------------------------------- /testbench/asm/common.s: -------------------------------------------------------------------------------- 1 | #include "defines.h" 2 | #include "tb.h" 3 | 4 | .section .text 5 | .global _start 6 | _start: 7 | // Clear minstret 8 | csrw minstret, zero 9 | csrw minstreth, zero 10 | 11 | // Enable Caches in MRAC 12 | li x2, 0x5f555555 13 | csrw 0x7c0, x2 14 | 15 | // global interrupt enable 16 | csrr x2, mstatus 17 | ori x2, x2, 0x8 18 | csrw mstatus, x2 19 | 20 | // set up mtvec 21 | la x2, exc_int_handler 22 | csrw mtvec, x2 23 | 24 | // Set up NMI handler address 25 | li x3, STDOUT 26 | ori x2, x2, LOAD_NMI_ADDR 27 | sw x2, 0(x3) 28 | 29 | j main 30 | 31 | // Write 0xff to STDOUT for TB to terminate test. 32 | _finish: 33 | li x3, STDOUT 34 | addi x5, x0, 0xff 35 | sb x5, 0(x3) 36 | beq x0, x0, _finish 37 | .rept 100 38 | nop 39 | .endr 40 | 41 | // handler must be aligned to 256 bytes since it has to fit 42 | // in the upper 24 bits of nmi handler address set testbench command 43 | .balign 256 44 | exc_int_handler: 45 | // disable all interrupt sources 46 | csrw mie, zero 47 | // reenable signaling of NMIs for subsequent NMIs 48 | csrw 0xBC0, zero // mdeau 49 | // compare CSRs with expected values 50 | csrr x2, mcause 51 | bne x2, x4, fail 52 | csrr x2, 0x7FF // mscause 53 | bne x2, x5, fail 54 | // set mepc to return from the test once we leave the handler 55 | la x2, ok 56 | csrw mepc, x2 57 | mret 58 | 59 | // used for making sure we fail if we didn't jump to the exception/NMI handler 60 | fail_if_not_serviced: 61 | .rept 15 62 | nop 63 | .endr 64 | // fail if interrupt didn't get serviced 65 | j fail 66 | 67 | fail: 68 | // write 0x01 to STDOUT for TB to fail the test 69 | li x3, STDOUT 70 | addi x5, x0, 0x01 71 | sb x5, 0(x3) 72 | j fail 73 | 74 | ok: 75 | ret -------------------------------------------------------------------------------- /tools/picolibc.mk: -------------------------------------------------------------------------------- 1 | GCC_PREFIX ?= riscv64-unknown-elf 2 | MAKEFILE_PATH = $(shell dirname $(realpath $(firstword $(MAKEFILE_LIST)))) 3 | PICOLIBC_PATH = $(abspath $(MAKEFILE_PATH)/../third_party/picolibc) 4 | BUILD_PATH = $(PICOLIBC_PATH)/build 5 | INSTALL_PATH = $(PICOLIBC_PATH)/install 6 | 7 | ifeq ($(CCACHE), ) 8 | MESON_CROSS_CC = '$(GCC_PREFIX)-gcc' 9 | else 10 | MESON_CROSS_CC = ['$(CCACHE)', '$(GCC_PREFIX)-gcc'] 11 | endif 12 | 13 | define CROSSFILE 14 | [binaries] 15 | c = $(MESON_CROSS_CC) 16 | ar = '$(GCC_PREFIX)-gcc-ar' 17 | as = '$(GCC_PREFIX)-as' 18 | nm = '$(GCC_PREFIX)-gcc-nm' 19 | strip = '$(GCC_PREFIX)-strip' 20 | 21 | [host_machine] 22 | system = 'unknown' 23 | cpu_family = 'riscv64' 24 | cpu = 'riscv' 25 | endian = 'little' 26 | 27 | [properties] 28 | # this uses shorter but slower function entry code 29 | c_args = [ '-msave-restore' ] 30 | # default multilib is 64 bit 31 | c_args_ = [ '-mcmodel=medany' ] 32 | endef 33 | 34 | export CROSSFILE 35 | 36 | $(BUILD_PATH): 37 | mkdir -p $@ 38 | 39 | $(BUILD_PATH)/cross.txt: | $(BUILD_PATH) 40 | @echo "$$CROSSFILE" > $@ 41 | 42 | $(INSTALL_PATH)/picolibc.specs: $(BUILD_PATH)/cross.txt | $(BUILD_PATH) 43 | 44 | cd $(PICOLIBC_PATH) && meson $(BUILD_PATH) \ 45 | -Dmultilib=true \ 46 | -Dmultilib-list=rv32imac/ilp32 \ 47 | -Dpicocrt=false \ 48 | -Datomic-ungetc=false \ 49 | -Dthread-local-storage=false \ 50 | -Dio-long-long=true \ 51 | -Dformat-default=integer \ 52 | -Dincludedir=picolibc/$(GCC_PREFIX)/include \ 53 | -Dlibdir=picolibc/$(GCC_PREFIX)/lib \ 54 | -Dprefix=$(INSTALL_PATH) \ 55 | -Dspecsdir=$(INSTALL_PATH) \ 56 | --cross-file $(BUILD_PATH)/cross.txt 57 | 58 | cd $(BUILD_PATH) && meson install 59 | 60 | all: $(INSTALL_PATH)/picolibc.specs 61 | 62 | clean: 63 | rm -rf $(BUILD_PATH) 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /testbench/uvm/mem/hdl/dccm_monitor.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2023 Antmicro 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | class dccm_monitor extends uvm_monitor; 5 | 6 | virtual dccm_interface memory_vif; 7 | uvm_analysis_port #(dccm_transaction_sequence_item) transaction_analisys_port; 8 | dccm_transaction_sequence_item transaction; 9 | 10 | `uvm_component_utils(dccm_monitor) 11 | 12 | function new(string name, uvm_component parent); 13 | super.new(name, parent); 14 | transaction = new(); 15 | transaction_analisys_port = new("trensaction_analisys_port", this); 16 | endfunction : new 17 | 18 | function void build_phase(uvm_phase phase); 19 | super.build_phase(phase); 20 | if (!uvm_config_db#(virtual dccm_interface)::get(this, "", "memory_vif", memory_vif)) 21 | `uvm_fatal("NOVIF", {"virtual interface must be set for: ", get_full_name(), ".memory_vif"}); 22 | endfunction : build_phase 23 | 24 | virtual task run_phase(uvm_phase phase); 25 | forever begin 26 | @(posedge memory_vif.clk); 27 | wait (memory_vif.wr_en || memory_vif.rd_en); 28 | // store control signals and address 29 | transaction.addr = memory_vif.addr; 30 | transaction.wdata = memory_vif.wdata; 31 | transaction.rd_en = memory_vif.rd_en; 32 | if (memory_vif.wr_en) begin 33 | // store write data 34 | transaction.wr_en = memory_vif.wr_en; 35 | @(posedge memory_vif.clk); 36 | end 37 | if (memory_vif.rd_en) begin 38 | // it takes 2 clocks to get the data on the output port 39 | @(posedge memory_vif.clk); 40 | @(posedge memory_vif.clk); 41 | // store read data 42 | transaction.rdata = memory_vif.rdata; 43 | end 44 | transaction_analisys_port.write(transaction); 45 | end 46 | endtask : run_phase 47 | 48 | endclass : dccm_monitor 49 | --------------------------------------------------------------------------------