├── .github └── workflows │ └── sim.yml ├── .gitignore ├── README.md ├── cores ├── cast_to_enum.patch ├── litedram │ ├── litedram.core │ ├── litedram.xdc │ ├── litedram_core.init │ ├── litedram_core.v │ ├── litedram_top.v │ └── mem_1.init ├── veer_eh1.core └── veer_el2.core ├── data ├── agilex5.sdc ├── agilex5.tcl ├── veerwolf.rdl ├── veerwolf_arty.xdc ├── veerwolf_arty_debug.cfg ├── veerwolf_arty_program.cfg ├── veerwolf_arty_write_flash.cfg ├── veerwolf_basys3.xdc ├── veerwolf_basys_debug.cfg ├── veerwolf_basys_program.cfg ├── veerwolf_basys_write_flash.cfg ├── veerwolf_nexys.xdc ├── veerwolf_nexys_debug.cfg ├── veerwolf_nexys_program.cfg ├── veerwolf_nexys_video.xdc ├── veerwolf_nexys_video_debug.cfg ├── veerwolf_nexys_video_program.cfg ├── veerwolf_nexys_video_write_flash.cfg ├── veerwolf_nexys_write_flash.cfg ├── veerwolf_sim.cfg ├── verilator_waiver.vlt └── vivado_waiver.tcl ├── riscv-target └── veer │ ├── compliance_io.h │ ├── compliance_test.h │ ├── device │ └── rv32i │ │ └── Makefile.include │ ├── link.ld │ └── makehex.py ├── rtl ├── axi2wb.v ├── axi_ram.v ├── bscan_tap.sv ├── clk_gen_agilex.v ├── clk_gen_arty.v ├── clk_gen_basys3.v ├── clk_gen_nexys.v ├── dpram64.v ├── veer_eh1_wrapper.sv ├── veer_el2_wrapper.sv ├── veerwolf_agilex.v ├── veerwolf_arty.v ├── veerwolf_basys3.v ├── veerwolf_core.v ├── veerwolf_nexys.v ├── veerwolf_nexys_video.v ├── veerwolf_syscon.v └── wb_mem_wrapper.v ├── sw ├── Makefile ├── blinky.S ├── blinky.vh ├── boot_main.S ├── bootloader.vh ├── count_switches.S ├── hello.S ├── hello.ubvh ├── hello.vh ├── hello_uart.S ├── hello_uart.vh ├── hexloader.S ├── link.ld ├── makehex.py ├── memtest.S ├── memtest.vh ├── spi_uimage_loader.S ├── veerwolf_zephyr_demo │ ├── CMakeLists.txt │ └── src │ │ └── main.c ├── zephyr_hello.vh └── zephyr_philosophers.vh ├── tb ├── s25fl128s.v ├── tb.cpp ├── uart_decoder.v ├── veerwolf_core_tb.v ├── veerwolf_nexys_tb.v └── veerwolf_spi_tb.v ├── veerwolf.core ├── veerwolf_basys3.png ├── veerwolf_core.png ├── veerwolf_irq.png ├── veerwolf_nexys.png ├── veerwolf_sim.png ├── west.yml └── zephyr ├── CMakeLists.txt ├── Kconfig ├── boards └── riscv │ └── veerwolf_nexys │ ├── CMakeLists.txt │ ├── Kconfig.board │ ├── Kconfig.defconfig │ ├── board.h │ ├── veerwolf_nexys.dts │ ├── veerwolf_nexys.yaml │ └── veerwolf_nexys_defconfig ├── drivers ├── CMakeLists.txt ├── Kconfig └── gpio │ ├── CMakeLists.txt │ ├── Kconfig │ └── gpio_veerwolf.c ├── dts ├── bindings │ └── gpio │ │ └── veerwolf,gpio.yaml └── riscv │ └── riscv32-veer.dtsi ├── module.yml └── soc ├── Kconfig └── riscv └── veerwolf ├── CMakeLists.txt ├── Kconfig.defconfig ├── Kconfig.soc ├── dts_fixup.h ├── irq.c ├── linker.ld ├── soc.c ├── soc.h ├── soc_common.h ├── soc_irq.S └── vector.S /.github/workflows/sim.yml: -------------------------------------------------------------------------------- 1 | name: Run basic testbench 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | lint: 7 | runs-on: ubuntu-latest 8 | name: Basic testbench 9 | env: 10 | REPO : VeeRwolf 11 | VLNV : veerwolf 12 | steps: 13 | - name: Checkout repo 14 | uses: actions/checkout@v4 15 | with: 16 | fetch-depth: 0 17 | path: VeeRwolf 18 | - run: sudo apt install verilator 19 | - run: pip3 install fusesoc 20 | - run: fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores 21 | - run: fusesoc library add $REPO $GITHUB_WORKSPACE/$REPO 22 | - run: fusesoc run --target=sim $VLNV --timeout=20000 23 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | sw/veerwolf_zephyr_demo/build 2 | -------------------------------------------------------------------------------- /cores/cast_to_enum.patch: -------------------------------------------------------------------------------- 1 | From 241ad18e259462da2643941c8b5c5319c1633a2b Mon Sep 17 00:00:00 2001 2 | From: Dawid Zimonczyk 3 | Date: Thu, 2 Apr 2020 15:48:17 +0200 4 | Subject: [PATCH] fix for assignment to enum variable from expression of 5 | different type 6 | 7 | --- 8 | design/ifu/ifu_ifc_ctl.sv | 8 ++++---- 9 | 1 file changed, 4 insertions(+), 4 deletions(-) 10 | 11 | diff --git a/design/ifu/ifu_ifc_ctl.sv b/design/ifu/ifu_ifc_ctl.sv 12 | index e382e68..7d856de 100644 13 | --- a/design/ifu/ifu_ifc_ctl.sv 14 | +++ b/design/ifu/ifu_ifc_ctl.sv 15 | @@ -185,11 +185,11 @@ module ifu_ifc_ctl 16 | //11 0-10- 01 17 | //11 0-00- 11 18 | 19 | - assign next_state[1] = (~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) | 20 | - (state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle); 21 | + assign next_state[1] = state_t'((~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) | 22 | + (state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle)); 23 | 24 | - assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle) | 25 | - (reset_delayed); 26 | + assign next_state[0] = state_t'((~goto_idle & leave_idle) | (state[0] & ~goto_idle) | 27 | + (reset_delayed)); 28 | 29 | assign flush_fb = exu_flush_final; 30 | 31 | -------------------------------------------------------------------------------- /cores/litedram/litedram.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : :veerwolf:litedram:0 4 | 5 | filesets: 6 | common: 7 | files: 8 | - litedram_top.v 9 | file_type : verilogSource 10 | 11 | core: 12 | files: 13 | - litedram_core.init : {file_type : user, copyto: litedram_core.init} 14 | - mem_1.init : {file_type : user, copyto: mem_1.init} 15 | - litedram_core.v 16 | file_type : verilogSource 17 | depend : [">=::serv:1.0.2"] 18 | 19 | xdc: {files : [litedram.xdc : {file_type : xdc}]} 20 | tb: 21 | files: 22 | - $(XILINX_VIVADO)/data/verilog/src/glbl.v 23 | - sim/ddr2_model_parameters.vh : {is_include_file : true} 24 | - sim/ddr2_model.v 25 | - litedram_tb.v 26 | file_type : verilogSource 27 | 28 | targets: 29 | default: 30 | filesets : [common, core, xdc] 31 | 32 | sim: 33 | default_tool : xsim 34 | filesets : [core, tb] 35 | tools: 36 | xsim: 37 | xelab_options : [-d, x1Gb, -d, sg25E, -d, x16, -L, unisims_ver, -L secureip, --timescale, 1ns/1ns] 38 | toplevel : [glbl, litedram_tb] 39 | -------------------------------------------------------------------------------- /cores/litedram/litedram_top.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Wrapper for LiteDRAM DDR2 controller 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | `timescale 1ps / 1ps 25 | `default_nettype none 26 | 27 | module litedram_top 28 | #(parameter ID_WIDTH = 0) 29 | ( 30 | output reg serial_tx, 31 | input wire serial_rx, 32 | input wire clk100, 33 | input wire rst_n, 34 | output wire pll_locked, 35 | output wire user_clk, 36 | output wire user_rst, 37 | output wire [12:0] ddram_a, 38 | output wire [2:0] ddram_ba, 39 | output wire ddram_ras_n, 40 | output wire ddram_cas_n, 41 | output wire ddram_we_n, 42 | output wire ddram_cs_n, 43 | output wire [1:0] ddram_dm, 44 | inout wire [15:0] ddram_dq, 45 | output wire [1:0] ddram_dqs_p, 46 | output wire [1:0] ddram_dqs_n, 47 | output wire ddram_clk_p, 48 | output wire ddram_clk_n, 49 | output wire ddram_cke, 50 | output wire ddram_odt, 51 | 52 | output reg init_done, 53 | output reg init_error, 54 | input wire [ID_WIDTH-1:0] i_awid, 55 | input wire [26:0] i_awaddr, 56 | input wire [7:0] i_awlen, 57 | input wire [3:0] i_awsize, 58 | input wire [1:0] i_awburst, 59 | input wire i_awvalid, 60 | output wire o_awready, 61 | 62 | input wire [ID_WIDTH-1:0] i_arid, 63 | input wire [26:0] i_araddr, 64 | input wire [7:0] i_arlen, 65 | input wire [3:0] i_arsize, 66 | input wire [1:0] i_arburst, 67 | input wire i_arvalid, 68 | output wire o_arready, 69 | 70 | input wire [63:0] i_wdata, 71 | input wire [7:0] i_wstrb, 72 | input wire i_wlast, 73 | input wire i_wvalid, 74 | output wire o_wready, 75 | 76 | output wire [ID_WIDTH-1:0] o_bid, 77 | output wire [1:0] o_bresp, 78 | output wire o_bvalid, 79 | input wire i_bready, 80 | 81 | output wire [ID_WIDTH-1:0] o_rid, 82 | output wire [63:0] o_rdata, 83 | output wire [1:0] o_rresp, 84 | output wire o_rlast, 85 | output wire o_rvalid, 86 | input wire i_rready); 87 | 88 | reg serial_rx_int; 89 | wire serial_tx_int; 90 | 91 | wire init_done_int; 92 | wire init_error_int; 93 | reg init_done_int_r; 94 | reg init_error_int_r; 95 | 96 | always @(posedge user_clk) begin 97 | serial_rx_int <= serial_rx; 98 | serial_tx <= serial_tx_int; 99 | init_done_int_r <= init_done_int; 100 | init_done <= init_done_int_r; 101 | init_error_int_r <= init_error_int; 102 | init_error <= init_error_int_r; 103 | end 104 | 105 | litedram_core ldc 106 | ( 107 | .serial_tx (serial_tx_int), 108 | .serial_rx (serial_rx_int), 109 | .clk (clk100), 110 | .rst (!rst_n), 111 | .pll_locked (pll_locked), 112 | .ddram_a (ddram_a), 113 | .ddram_ba (ddram_ba), 114 | .ddram_ras_n (ddram_ras_n), 115 | .ddram_cas_n (ddram_cas_n), 116 | .ddram_we_n (ddram_we_n), 117 | .ddram_cs_n (ddram_cs_n), 118 | .ddram_dm (ddram_dm ), 119 | .ddram_dq (ddram_dq ), 120 | .ddram_dqs_p (ddram_dqs_p), 121 | .ddram_dqs_n (ddram_dqs_n), 122 | .ddram_clk_p (ddram_clk_p), 123 | .ddram_clk_n (ddram_clk_n), 124 | .ddram_cke (ddram_cke ), 125 | .ddram_odt (ddram_odt ), 126 | .ddram_reset_n (), 127 | .init_done (init_done_int), 128 | .init_error (init_error_int), 129 | .user_clk (user_clk), 130 | .user_rst (user_rst), 131 | .user_port_axi_0_awaddr (i_awaddr), 132 | .user_port_axi_0_awburst (i_awburst), 133 | .user_port_axi_0_awlen (i_awlen), 134 | .user_port_axi_0_awsize (i_awsize), 135 | .user_port_axi_0_awid (i_awid), 136 | .user_port_axi_0_awvalid (i_awvalid), 137 | .user_port_axi_0_awready (o_awready), 138 | .user_port_axi_0_wdata (i_wdata), 139 | .user_port_axi_0_wstrb (i_wstrb), 140 | .user_port_axi_0_wlast (i_wlast), 141 | .user_port_axi_0_wvalid (i_wvalid), 142 | .user_port_axi_0_wready (o_wready), 143 | .user_port_axi_0_bresp (o_bresp), 144 | .user_port_axi_0_bid (o_bid), 145 | .user_port_axi_0_bvalid (o_bvalid), 146 | .user_port_axi_0_bready (i_bready), 147 | .user_port_axi_0_araddr (i_araddr), 148 | .user_port_axi_0_arburst (i_arburst), 149 | .user_port_axi_0_arlen (i_arlen), 150 | .user_port_axi_0_arsize (i_arsize), 151 | .user_port_axi_0_arid (i_arid), 152 | .user_port_axi_0_arvalid (i_arvalid), 153 | .user_port_axi_0_arready (o_arready), 154 | .user_port_axi_0_rdata (o_rdata), 155 | .user_port_axi_0_rresp (o_rresp), 156 | .user_port_axi_0_rlast (o_rlast), 157 | .user_port_axi_0_rid (o_rid), 158 | .user_port_axi_0_rvalid (o_rvalid), 159 | .user_port_axi_0_rready (i_rready)); 160 | 161 | endmodule 162 | `default_nettype wire 163 | -------------------------------------------------------------------------------- /cores/litedram/mem_1.init: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/VeeRwolf/9a91980562fcaadd748404af05d2a23361632378/cores/litedram/mem_1.init -------------------------------------------------------------------------------- /cores/veer_eh1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : chipsalliance.org:cores:VeeR_EH1:1.9 4 | description : VeeR EH1 RISC-V Core 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - design/include/veer_types.sv 10 | - design/lib/beh_lib.sv 11 | - design/mem.sv 12 | - design/pic_ctrl.sv 13 | - design/dma_ctrl.sv 14 | - design/ifu/ifu_aln_ctl.sv 15 | - design/ifu/ifu_compress_ctl.sv 16 | - design/ifu/ifu_ifc_ctl.sv 17 | - design/ifu/ifu_bp_ctl.sv 18 | - design/ifu/ifu_ic_mem.sv 19 | - design/ifu/ifu_mem_ctl.sv 20 | - design/ifu/ifu_iccm_mem.sv 21 | - design/ifu/ifu.sv 22 | - design/dec/dec_decode_ctl.sv 23 | - design/dec/dec_gpr_ctl.sv 24 | - design/dec/dec_ib_ctl.sv 25 | - design/dec/dec_tlu_ctl.sv 26 | - design/dec/dec_trigger.sv 27 | - design/dec/dec.sv 28 | - design/exu/exu_alu_ctl.sv 29 | - design/exu/exu_mul_ctl.sv 30 | - design/exu/exu_div_ctl.sv 31 | - design/exu/exu.sv 32 | - design/lsu/lsu.sv 33 | - design/lsu/lsu_bus_buffer.sv 34 | - design/lsu/lsu_clkdomain.sv 35 | - design/lsu/lsu_addrcheck.sv 36 | - design/lsu/lsu_lsc_ctl.sv 37 | - design/lsu/lsu_stbuf.sv 38 | - design/lsu/lsu_bus_intf.sv 39 | - design/lsu/lsu_ecc.sv 40 | - design/lsu/lsu_dccm_mem.sv 41 | - design/lsu/lsu_dccm_ctl.sv 42 | - design/lsu/lsu_trigger.sv 43 | - design/dbg/dbg.sv 44 | - design/dmi/dmi_wrapper.v 45 | - design/dmi/dmi_jtag_to_core_sync.v 46 | - design/dmi/rvjtag_tap.sv 47 | - design/lib/mem_lib.sv 48 | - design/lib/ahb_to_axi4.sv 49 | - design/lib/axi4_to_ahb.sv 50 | - design/veer.sv 51 | - design/veer_wrapper.sv 52 | file_type : systemVerilogSource 53 | 54 | includes: 55 | files: 56 | - design/include/build.h : {is_include_file : true} 57 | - design/include/global.h : {is_include_file : true} 58 | file_type : systemVerilogSource 59 | 60 | mem_init: 61 | files: 62 | - testbench/hex/data.hex : {copyto : data.hex} 63 | - testbench/hex/program.hex : {copyto : program.hex} 64 | file_type : user 65 | 66 | tb: 67 | files: [testbench/ahb_sif.sv, testbench/tb_top.sv] 68 | file_type : systemVerilogSource 69 | 70 | verilator_tb: 71 | files : [testbench/test_tb_top.cpp : {file_type : cppSource}] 72 | 73 | vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]} 74 | 75 | targets: 76 | default: 77 | filesets : 78 | - includes 79 | - rtl 80 | - "tool_vivado ? (vivado_tcl)" 81 | lint: 82 | default_tool: verilator 83 | filesets : [includes, rtl] 84 | generate : [veer_default_config] 85 | tools: 86 | verilator : 87 | mode : lint-only 88 | toplevel : veer_wrapper 89 | 90 | sim: 91 | default_tool : verilator 92 | filesets : 93 | - includes 94 | - rtl 95 | - mem_init 96 | - tb 97 | - "tool_verilator? (verilator_tb)" 98 | 99 | generate : [veer_ahb_config] 100 | tools: 101 | modelsim: 102 | vlog_options : 103 | - -mfcu 104 | - -cuautoname=du 105 | - config/common_defines.vh 106 | rivierapro: 107 | vlog_options : 108 | - config/common_defines.vh 109 | - "-err VCP2694 W1" 110 | compilation_mode : common 111 | verilator: 112 | verilator_options : [--trace, -Wno-fatal] 113 | toplevel : tb_top 114 | 115 | synth: 116 | default_tool : vivado 117 | filesets : [includes, rtl, "tool_vivado? (vivado_tcl)"] 118 | generate : [veer_fpga_config] 119 | tools: 120 | vivado: 121 | part : xc7a100tcsg324-1 122 | pnr : none 123 | toplevel : veer_wrapper 124 | 125 | generate: 126 | veer_ahb_config: 127 | generator: veer_eh1_config 128 | position : first 129 | parameters: 130 | args : ['-ahb_lite', -unset=assert_on] 131 | 132 | veer_default_config: 133 | generator: veer_eh1_config 134 | position : first 135 | parameters: 136 | args : [-unset=assert_on] 137 | 138 | veer_fpga_config: 139 | generator: veer_eh1_config 140 | position : first 141 | parameters: 142 | args : [-unset=assert_on, -set=fpga_optimize=1] 143 | 144 | generators: 145 | veer_eh1_config: 146 | interpreter: python3 147 | command: configs/veer_config_gen.py 148 | description : Create a VeeR configuration. Note! Only supports the default config 149 | 150 | provider: 151 | name : github 152 | user : chipsalliance 153 | repo : Cores-VeeR-EH1 154 | version : 915fb34a5b38ef14c5d5c05431765ad8b912bc3 155 | -------------------------------------------------------------------------------- /cores/veer_el2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : chipsalliance.org:cores:VeeR_EL2:1.4 4 | description : VeeR EL2 RISC-V Core 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - design/include/el2_def.sv 10 | - design/lib/el2_lib.sv 11 | - design/lib/beh_lib.sv 12 | - design/el2_mem.sv 13 | - design/el2_pic_ctrl.sv 14 | - design/el2_dma_ctrl.sv 15 | - design/ifu/el2_ifu_aln_ctl.sv 16 | - design/ifu/el2_ifu_compress_ctl.sv 17 | - design/ifu/el2_ifu_ifc_ctl.sv 18 | - design/ifu/el2_ifu_bp_ctl.sv 19 | - design/ifu/el2_ifu_ic_mem.sv 20 | - design/ifu/el2_ifu_mem_ctl.sv 21 | - design/ifu/el2_ifu_iccm_mem.sv 22 | - design/ifu/el2_ifu.sv 23 | - design/dec/el2_dec_decode_ctl.sv 24 | - design/dec/el2_dec_gpr_ctl.sv 25 | - design/dec/el2_dec_ib_ctl.sv 26 | - design/dec/el2_dec_tlu_ctl.sv 27 | - design/dec/el2_dec_trigger.sv 28 | - design/dec/el2_dec.sv 29 | - design/exu/el2_exu_alu_ctl.sv 30 | - design/exu/el2_exu_mul_ctl.sv 31 | - design/exu/el2_exu_div_ctl.sv 32 | - design/exu/el2_exu.sv 33 | - design/lsu/el2_lsu.sv 34 | - design/lsu/el2_lsu_bus_buffer.sv 35 | - design/lsu/el2_lsu_clkdomain.sv 36 | - design/lsu/el2_lsu_addrcheck.sv 37 | - design/lsu/el2_lsu_lsc_ctl.sv 38 | - design/lsu/el2_lsu_stbuf.sv 39 | - design/lsu/el2_lsu_bus_intf.sv 40 | - design/lsu/el2_lsu_ecc.sv 41 | - design/lsu/el2_lsu_dccm_mem.sv 42 | - design/lsu/el2_lsu_dccm_ctl.sv 43 | - design/lsu/el2_lsu_trigger.sv 44 | - design/dbg/el2_dbg.sv 45 | - design/dmi/dmi_wrapper.v 46 | - design/dmi/dmi_jtag_to_core_sync.v 47 | - design/dmi/rvjtag_tap.v 48 | - design/lib/mem_lib.sv 49 | - design/el2_veer.sv 50 | - design/el2_veer_wrapper.sv 51 | file_type : systemVerilogSource 52 | 53 | vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]} 54 | 55 | targets: 56 | default: 57 | filesets : 58 | - rtl 59 | - "tool_vivado ? (vivado_tcl)" 60 | lint: 61 | default_tool: verilator 62 | filesets : [rtl] 63 | generate : [veer_default_config] 64 | tools: 65 | verilator : 66 | mode : lint-only 67 | toplevel : el2_veer_wrapper 68 | 69 | synth: 70 | default_tool : vivado 71 | filesets : [rtl, vivado_tcl] 72 | generate : [veer_default_config] 73 | parameters : [RV_FPGA_OPTIMIZE] 74 | tools: 75 | vivado: 76 | part : xc7a100tcsg324-1 77 | pnr : none 78 | toplevel : el2_veer_wrapper 79 | 80 | generate: 81 | veer_default_config: 82 | generator: veer_el2_config 83 | position : first 84 | parameters: 85 | args : [-unset=assert_on] 86 | 87 | generators: 88 | veer_el2_config: 89 | interpreter: python3 90 | command: configs/veer_config_gen.py 91 | description : Create a VeeR EL2 configuration. Note! Only supports the default config 92 | 93 | parameters: 94 | RV_FPGA_OPTIMIZE: 95 | datatype : bool 96 | default : true 97 | description : Minimize clock gating to map better to FPGAs 98 | paramtype : vlogdefine 99 | 100 | provider: 101 | name : github 102 | user : chipsalliance 103 | repo : Cores-VeeR-EL2 104 | version : 882027cc538bf7ef11c763d499877efdb5c827d8 105 | -------------------------------------------------------------------------------- /data/agilex5.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; 2 | 3 | # main system clock (25 Mhz) 4 | create_generated_clock -name "clk25MHz" -multiply_by 8 -divide_by 32 -source [get_ports {clk}] [get_nets {clk_gen|o_clk_pll}] 5 | 6 | # JTAG clock (10 MHz) 7 | create_clock -name tck_dmi -period 100.00 [get_ports i_jtag_tck]; 8 | -------------------------------------------------------------------------------- /data/agilex5.tcl: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_CU_MODE MFCU 2 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 3 | * 4 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 5 | set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" 6 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 7 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 8 | 9 | set_global_assignment -name GENERATE_COMPRESSED_SOF ON 10 | set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF 11 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" 12 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF 13 | set_global_assignment -name USE_CONF_DONE SDM_IO12 14 | set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7 15 | set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ 16 | set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL 17 | 18 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 19 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 20 | set_global_assignment -name RTL_SDC_FILE src/veerwolf_0.7.5/data/agilex5.sdc 21 | 22 | # Clock 23 | set_location_assignment PIN_D8 -to clk -comment IOBANK_6C 24 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk -entity veerwolf_agilex 25 | 26 | # Reset PB SW11 HPS_COLD_RESETn Bank 5B 3.3V 27 | set_location_assignment PIN_BM109 -to rstn -comment IOBANK_5B 28 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rstn -entity veerwolf_agilex 29 | 30 | # UART RX 31 | set_location_assignment PIN_CJ2 -to i_uart_rx -comment IOBANK_6B 32 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_uart_rx -entity veerwolf_agilex 33 | 34 | # UART TX 35 | set_location_assignment PIN_CK4 -to o_uart_tx -comment IOBANK_6B 36 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to o_uart_tx -entity veerwolf_agilex 37 | 38 | # SPI Flash J9 FPGA USER IO 1-4 Bank 6A 3.3V 39 | set_location_assignment PIN_BU28 -to o_flash_cs_n -comment IOBANK_6A 40 | set_location_assignment PIN_BP31 -to o_flash_mosi -comment IOBANK_6A 41 | set_location_assignment PIN_BR28 -to i_flash_miso -comment IOBANK_6A 42 | set_location_assignment PIN_BR31 -to o_flash_sclk -comment IOBANK_6A 43 | 44 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to o_flash_cs_n -entity veerwolf_agilex 45 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to o_flash_mosi -entity veerwolf_agilex 46 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_flash_miso -entity veerwolf_agilex 47 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to o_flash_sclk -entity veerwolf_agilex 48 | 49 | # JTAG J9 FPGA USER IO 5-7 Bank 6 3.3V 50 | set_location_assignment PIN_BU31 -to i_jtag_tck -comment IOBANK_6A 51 | set_location_assignment PIN_BM28 -to i_jtag_tms -comment IOBANK_6A 52 | set_location_assignment PIN_BF21 -to i_jtag_tdi -comment IOBANK_6B 53 | set_location_assignment PIN_BM31 -to o_jtag_tdo -comment IOBANK_6A 54 | 55 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_jtag_tck -entity veerwolf_agilex 56 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_jtag_tms -entity veerwolf_agilex 57 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_jtag_tdi -entity veerwolf_agilex 58 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to o_jtag_tdo -entity veerwolf_agilex 59 | 60 | # GPIO (inputs) 61 | # User PB Bank 6A 3.3V 62 | set_location_assignment PIN_BK31 -to i_sw[0] -comment IOBANK_6A 63 | set_location_assignment PIN_BP22 -to i_sw[1] -comment IOBANK_6A 64 | set_location_assignment PIN_BK28 -to i_sw[2] -comment IOBANK_6A 65 | set_location_assignment PIN_BR22 -to i_sw[3] -comment IOBANK_6A 66 | # User SW Bank 6A 3.3V 67 | set_location_assignment PIN_CH12 -to i_sw[4] -comment IOBANK_6A 68 | set_location_assignment PIN_BU22 -to i_sw[5] -comment IOBANK_6A 69 | set_location_assignment PIN_BW19 -to i_sw[6] -comment IOBANK_6A 70 | set_location_assignment PIN_BH28 -to i_sw[7] -comment IOBANK_6A 71 | # MAX SPARE Bank 5A 3.3V 72 | set_location_assignment PIN_CD134 -to i_sw[8] -comment IOBANK_5A 73 | set_location_assignment PIN_CD135 -to i_sw[9] -comment IOBANK_5A 74 | set_location_assignment PIN_CG134 -to i_sw[10] -comment IOBANK_5A 75 | set_location_assignment PIN_CH132 -to i_sw[11] -comment IOBANK_5A 76 | # HSIO SW24 Bank 2AT 1.1V 77 | set_location_assignment PIN_BE93 -to i_sw[12] -comment IOBANK_2A_T 78 | set_location_assignment PIN_BE79 -to i_sw[13] -comment IOBANK_2A_T 79 | set_location_assignment PIN_BF83 -to i_sw[14] -comment IOBANK_2A_T 80 | set_location_assignment PIN_BE83 -to i_sw[15] -comment IOBANK_2A_T 81 | 82 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[0] -entity veerwolf_agilex 83 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[1] -entity veerwolf_agilex 84 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[2] -entity veerwolf_agilex 85 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[3] -entity veerwolf_agilex 86 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[4] -entity veerwolf_agilex 87 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[5] -entity veerwolf_agilex 88 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[6] -entity veerwolf_agilex 89 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[7] -entity veerwolf_agilex 90 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[8] -entity veerwolf_agilex 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[9] -entity veerwolf_agilex 92 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[10] -entity veerwolf_agilex 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[11] -entity veerwolf_agilex 94 | set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[12] -entity veerwolf_agilex 95 | set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[13] -entity veerwolf_agilex 96 | set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[14] -entity veerwolf_agilex 97 | set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[15] -entity veerwolf_agilex 98 | 99 | 100 | # GPIO (outputs) 101 | # User LED Bank 2AT 1.1V 102 | set_location_assignment PIN_BM59 -to o_led[0] -comment IOBANK_2A_T 103 | set_location_assignment PIN_BH59 -to o_led[1] -comment IOBANK_2A_T 104 | set_location_assignment PIN_BH62 -to o_led[2] -comment IOBANK_2A_T 105 | set_location_assignment PIN_BK59 -to o_led[3] -comment IOBANK_2A_T 106 | # FMC LA Bank 3BT 1.2V 107 | set_location_assignment PIN_B42 -to o_led[4] -comment IOBANK_3B_B 108 | set_location_assignment PIN_A45 -to o_led[5] -comment IOBANK_3B_B 109 | set_location_assignment PIN_A48 -to o_led[6] -comment IOBANK_3B_B 110 | set_location_assignment PIN_B45 -to o_led[7] -comment IOBANK_3B_B 111 | set_location_assignment PIN_A51 -to o_led[8] -comment IOBANK_3B_B 112 | set_location_assignment PIN_B51 -to o_led[9] -comment IOBANK_3B_B 113 | set_location_assignment PIN_B54 -to o_led[10] -comment IOBANK_3B_B 114 | set_location_assignment PIN_A54 -to o_led[11] -comment IOBANK_3B_B 115 | set_location_assignment PIN_B60 -to o_led[12] -comment IOBANK_3B_B 116 | set_location_assignment PIN_A63 -to o_led[13] -comment IOBANK_3B_B 117 | set_location_assignment PIN_A60 -to o_led[14] -comment IOBANK_3B_B 118 | set_location_assignment PIN_B56 -to o_led[15] -comment IOBANK_3B_B 119 | 120 | set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[0] -entity veerwolf_agilex 121 | set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[1] -entity veerwolf_agilex 122 | set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[2] -entity veerwolf_agilex 123 | set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[3] -entity veerwolf_agilex 124 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex 125 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex 126 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex 127 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex 128 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex 129 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[9] -entity veerwolf_agilex 130 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[10] -entity veerwolf_agilex 131 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[11] -entity veerwolf_agilex 132 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[12] -entity veerwolf_agilex 133 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[13] -entity veerwolf_agilex 134 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[14] -entity veerwolf_agilex 135 | set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[15] -entity veerwolf_agilex -------------------------------------------------------------------------------- /data/veerwolf.rdl: -------------------------------------------------------------------------------- 1 | addrmap veerwolf { 2 | name = "VeeRwolf core"; 3 | desc = " 4 | The core of VeeRwolf consists of the VeeR CPU with a boot ROM, AXI4 interconnect, UART, SPI, RISC-V timer and GPIO. The core doesn't include any RAM but instead exposes a memory bus that the target-specific wrapper will connect to an appropriate memory controller. Other external connections are clock, reset, UART, GPIO, SPI and DMI (Debug Module Interface)."; 5 | /* mem ram { 6 | mementries = 0x08ffffff; 7 | memwidth = 8; 8 | };*/ 9 | regfile { 10 | name = "System controller"; 11 | desc = "The system controller contains common system functionality such as keeping register with the SoC version information, RAM initialization status and the RISC-V machine timer."; 12 | reg { 13 | field { sw=r;hw=na; } patch[8]; 14 | field { sw=r;hw=na; } minor[8]; 15 | field { sw=r;hw=na; } major[8]; 16 | field { sw=r;hw=na; } rev[7]; 17 | field { sw=r;hw=na; } dirty; 18 | } version; 19 | reg { field {sw=r;hw=na;} sha[32]; } sha; 20 | reg { 21 | regwidth=8; 22 | field { 23 | desc="Outputs a character in simulation. No effect on hardware"; 24 | sw=w;hw=r; 25 | } sim_print[8]; 26 | } sim_print; 27 | reg { 28 | regwidth=8; 29 | field { 30 | desc="Exits a simulation. No effect on hardware"; 31 | sw=w;hw=r; 32 | } sim_exit[8]; 33 | } sim_exit; 34 | reg { 35 | regwidth=8; 36 | field { 37 | desc="RAM initialization complete"; 38 | sw=r;hw=w; 39 | } ram_init_done; 40 | field { 41 | desc="RAM initialization reported errors"; 42 | sw=r;hw=w; 43 | } ram_init_error; 44 | } init_status; 45 | reg { 46 | name="Software-controlled external interrupts"; 47 | desc="This register allows configuration and assertion of IRQ line 3 and 4, for testing the VeeR PIC or having two extra software-controllable interrupt sources. Interrupts can be triggered by writing to the sw_irq*n* bits when the timer bit is set to 0, or by a timeout of the irq_timer, when the timer bit is set to one. If both sw_irq3_timer and sw_irq4_timer are set to 0, the IRQ timer instead asserts an NMI when it reaches 0. 48 | 49 | If sw_irq3_timer or sw_irq4_timer are asserted, the interrupt trigger is connected to 50 | 51 | ![VeeRwolf IRQ](veerwolf_irq.png) 52 | "; 53 | regwidth=8; 54 | field { 55 | desc=" 56 | 0 = IRQ3 is triggered by sw_irq3, 57 | 58 | 1 = IRQ3 is triggered by irq_timer timeout"; 59 | sw=rw;hw=r; 60 | } sw_irq3_timer; 61 | field { 62 | desc="IRQ3 polarity. 0 = Active high, 1 = active low"; 63 | sw=rw;hw=r; 64 | } sw_irq3_pol; 65 | field { 66 | desc="0 = IRQ3 is asserted until sw_irq3 is cleared, 1 = Writing to sw_irq3 only asserts IRQ3 for one clock cycle"; 67 | sw=rw;hw=r; 68 | } sw_irq3_edge; 69 | field { 70 | desc="Trigger IRQ line 3"; 71 | sw=rw;hw=rw; 72 | } sw_irq3; 73 | field { 74 | desc=" 75 | 0 = IRQ4 is triggered by sw_irq4, 76 | 77 | 1 = IRQ4 is triggered by irq_timer timeout"; 78 | sw=rw;hw=r; 79 | } sw_irq4_timer; 80 | field { 81 | desc="IRQ4 polarity. 0 = Active high, 1 = active low"; 82 | sw=rw;hw=r; 83 | } sw_irq4_pol; 84 | field { 85 | desc="0 = IRQ4 is asserted until sw_irq4 is cleared, 1 = Writing to sw_irq4 only asserts IRQ4 for one clock cycle"; 86 | sw=rw;hw=r; 87 | } sw_irq4_edge; 88 | field { 89 | desc="Trigger IRQ line 4"; 90 | sw=rw;hw=rw; 91 | } sw_irq4; 92 | } sw_irq; 93 | reg { 94 | name="Interrupt vector for NMI"; 95 | field {sw=rw;hw=r;} nmi_vec[32]; } nmi_vec; 96 | /* 97 | */ 98 | } syscon @ 0x80001000; 99 | 100 | }; 101 | 102 | -------------------------------------------------------------------------------- /data/veerwolf_arty.xdc: -------------------------------------------------------------------------------- 1 | create_clock -add -name sys_clk_pin -period 10.0 -waveform {0 5} [get_ports {clk}]; 2 | create_clock -add -name tck_dmi -period 100.00 [get_pins tap/tap_dmi/TCK]; 3 | create_clock -add -name tck_dtmcs -period 100.00 [get_pins tap/tap_dtmcs/TCK]; 4 | create_clock -add -name tck_idcode -period 100.00 [get_pins tap/tap_idcode/DRCK]; 5 | 6 | #FIXME: Improve this later but hopefully ok for now. 7 | #Since the JTAG clock is slow and bits 0 and 1 are properly synced, we can be a bit careless about the rest 8 | set_false_path -from [get_cells -regexp {tap/dtmcs_r_reg\[([2-9]|[1-9][0-9])\]}] 9 | 10 | set_false_path -from [get_cells ddr2/serial_tx_reg] 11 | 12 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; 13 | 14 | set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { rstn }]; 15 | 16 | set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports i_uart_rx] 17 | set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 18 | 19 | 20 | set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports o_flash_mosi]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 21 | set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports i_flash_miso]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 22 | #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 23 | #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 24 | set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports o_flash_cs_n]; 25 | 26 | set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }] 27 | set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }] 28 | set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }] 29 | set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }] 30 | 31 | set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }] 32 | set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }] 33 | set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }] 34 | set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }] 35 | 36 | set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }] 37 | set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }] 38 | set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }] 39 | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }] 40 | 41 | set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { o_led[4] }] 42 | set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { o_led[5] }] 43 | set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { o_led[6] }] 44 | set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { o_led[7] }] 45 | set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { o_led[8] }] 46 | set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { o_led[9] }] 47 | set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { o_led[10] }] 48 | set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { o_led[11] }] 49 | set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { o_led[12] }] 50 | set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { o_led[13] }] 51 | set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { o_led[14] }] 52 | set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { o_led[15] }] 53 | -------------------------------------------------------------------------------- /data/veerwolf_arty_debug.cfg: -------------------------------------------------------------------------------- 1 | # JTAG adapter configuration (on-board USB-JTAG adapter on Digilent Nexys A7) 2 | interface ftdi 3 | ftdi_device_desc "Digilent USB Device" 4 | ftdi_vid_pid 0x0403 0x6010 5 | ftdi_channel 0 6 | ftdi_layout_init 0x0088 0x008b 7 | reset_config none 8 | adapter_khz 10000 9 | 10 | transport select jtag 11 | 12 | # Configure JTAG chain and the target processor 13 | set _CHIPNAME riscv 14 | 15 | jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x03631093 -ignore-version 16 | set _TARGETNAME $_CHIPNAME.cpu 17 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 18 | 19 | # No MMU on VeeR (do not attempt virt2phys address translation) 20 | riscv set_enable_virt2phys off 21 | 22 | # Configure memory access method 23 | # Utilize "abstract access" to allow to reach VeeR's ICCM, DCCM and PIC core-local memories. 24 | # Note: Requires VeeR EH1 1.8+ and recent riscv-openocd (commit 22d771d20 from Sep 14, 2020, or newer). 25 | riscv set_mem_access abstract 26 | 27 | # Alternate memory access configuration - via "system bus" 28 | # Caution: ICCM, DCCM and PIC cannot be reached. 29 | # riscv set_mem_access sysbus 30 | 31 | # Custom numbers for RISC-V Debug JTAG registers 32 | # (needed due to JTAG tunneling via Xilinx BSCAN cell) 33 | riscv set_ir idcode 0x9 34 | riscv set_ir dmi 0x22 35 | riscv set_ir dtmcs 0x23 36 | 37 | # Expose custom VeeR's CSR dmst (csr1988) 38 | riscv expose_csrs 1988 39 | 40 | # Custom event hooks to flush VeeR ICACHE prior to step/resume 41 | proc veer_eh1_execute_fence {} { 42 | # Execute fence + fence.i via "dmst" register 43 | reg csr1988 0x3 44 | } 45 | 46 | $_TARGETNAME configure -event resume-start { 47 | veer_eh1_execute_fence 48 | } 49 | 50 | $_TARGETNAME configure -event step-start { 51 | veer_eh1_execute_fence 52 | } 53 | 54 | # Conclude OpenOCD configuration 55 | init 56 | 57 | # Halt the target 58 | halt 59 | -------------------------------------------------------------------------------- /data/veerwolf_arty_program.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | 13 | if { [info exists BITFILE] } { 14 | set _BITFILE $BITFILE 15 | } else { 16 | set _BITFILE build/veerwolf_0/nexys_a7-vivado/veerwolf_0.bit 17 | } 18 | 19 | init 20 | pld load 0 $_BITFILE 21 | shutdown 22 | -------------------------------------------------------------------------------- /data/veerwolf_arty_write_flash.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | source [find cpld/jtagspi.cfg] 13 | 14 | if { [info exists BINFILE] } { 15 | set _BINFILE $BINFILE 16 | } else { 17 | set _BINFILE boot.bin 18 | } 19 | 20 | init 21 | jtagspi_init 0 bscan_spi_xc7a35t.bit 22 | jtagspi_program $_BINFILE 0x0 23 | shutdown 24 | 25 | -------------------------------------------------------------------------------- /data/veerwolf_basys3.xdc: -------------------------------------------------------------------------------- 1 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; 2 | create_clock -add -name tck_dmi -period 100.00 [get_pins tap/tap_dmi/TCK]; 3 | create_clock -add -name tck_dtmcs -period 100.00 [get_pins tap/tap_dtmcs/TCK]; 4 | create_clock -add -name tck_idcode -period 100.00 [get_pins tap/tap_idcode/DRCK]; 5 | 6 | #FIXME: Improve this later but hopefully ok for now. 7 | #Since the JTAG clock is slow and bits 0 and 1 are properly synced, we can be a bit careless about the rest 8 | #set_false_path -from [get_cells -regexp {tap/dtmcs_r_reg\[([2-9]|[1-9][0-9])\]}] 9 | 10 | set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { clk }]; 11 | 12 | #set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rstn }]; 13 | 14 | set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports i_uart_rx] 15 | set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 16 | 17 | 18 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports o_flash_mosi]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 19 | set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports i_flash_miso]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 20 | #set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 21 | #set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 22 | set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports o_flash_cs_n]; 23 | 24 | set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }] 25 | set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }] 26 | set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }] 27 | set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }] 28 | set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[4] }] 29 | set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[5] }] 30 | set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { i_sw[6] }] 31 | set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[7] }] 32 | set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { i_sw[8] }] 33 | set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { i_sw[9] }] 34 | set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { i_sw[10] }] 35 | set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { i_sw[11] }] 36 | set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports { i_sw[12] }] 37 | set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { i_sw[13] }] 38 | set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { i_sw[14] }] 39 | set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { i_sw[15] }] 40 | 41 | set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }] 42 | set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }] 43 | set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }] 44 | set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }] 45 | set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { o_led[4] }] 46 | set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { o_led[5] }] 47 | set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { o_led[6] }] 48 | set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { o_led[7] }] 49 | set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { o_led[8] }] 50 | set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { o_led[9] }] 51 | set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { o_led[10] }] 52 | set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { o_led[11] }] 53 | set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { o_led[12] }] 54 | set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { o_led[13] }] 55 | set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { o_led[14] }] 56 | set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { o_led[15] }] 57 | 58 | set_property CONFIG_VOLTAGE 3.3 [current_design] 59 | set_property CFGBVS VCCO [current_design] 60 | -------------------------------------------------------------------------------- /data/veerwolf_basys_debug.cfg: -------------------------------------------------------------------------------- 1 | # JTAG adapter configuration (on-board USB-JTAG adapter on Digilent Nexys A7) 2 | interface ftdi 3 | ftdi_device_desc "Digilent USB Device" 4 | ftdi_vid_pid 0x0403 0x6010 5 | ftdi_channel 0 6 | ftdi_layout_init 0x0088 0x008b 7 | reset_config none 8 | adapter_khz 10000 9 | 10 | transport select jtag 11 | 12 | # Configure JTAG chain and the target processor 13 | set _CHIPNAME riscv 14 | 15 | jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x03631093 -ignore-version 16 | set _TARGETNAME $_CHIPNAME.cpu 17 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 18 | 19 | # No MMU on VeeR (do not attempt virt2phys address translation) 20 | riscv set_enable_virt2phys off 21 | 22 | # Configure memory access method 23 | # Utilize "abstract access" to allow to reach VeeR's ICCM, DCCM and PIC core-local memories. 24 | # Note: Requires VeeR EH1 1.8+ and recent riscv-openocd (commit 22d771d20 from Sep 14, 2020, or newer). 25 | riscv set_mem_access abstract 26 | 27 | # Alternate memory access configuration - via "system bus" 28 | # Caution: ICCM, DCCM and PIC cannot be reached. 29 | # riscv set_mem_access sysbus 30 | 31 | # Custom numbers for RISC-V Debug JTAG registers 32 | # (needed due to JTAG tunneling via Xilinx BSCAN cell) 33 | riscv set_ir idcode 0x9 34 | riscv set_ir dmi 0x22 35 | riscv set_ir dtmcs 0x23 36 | 37 | # Expose custom VeeR's CSR dmst (csr1988) 38 | riscv expose_csrs 1988 39 | 40 | # Custom event hooks to flush VeeR ICACHE prior to step/resume 41 | proc veer_eh1_execute_fence {} { 42 | # Execute fence + fence.i via "dmst" register 43 | reg csr1988 0x3 44 | } 45 | 46 | $_TARGETNAME configure -event resume-start { 47 | veer_eh1_execute_fence 48 | } 49 | 50 | $_TARGETNAME configure -event step-start { 51 | veer_eh1_execute_fence 52 | } 53 | 54 | # Conclude OpenOCD configuration 55 | init 56 | 57 | # Halt the target 58 | halt 59 | -------------------------------------------------------------------------------- /data/veerwolf_basys_program.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | 13 | if { [info exists BITFILE] } { 14 | set _BITFILE $BITFILE 15 | } else { 16 | set _BITFILE build/veerwolf_0/nexys_a7-vivado/veerwolf_0.bit 17 | } 18 | 19 | init 20 | pld load 0 $_BITFILE 21 | shutdown 22 | -------------------------------------------------------------------------------- /data/veerwolf_basys_write_flash.cfg: -------------------------------------------------------------------------------- 1 | adapter driver ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter speed 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | source [find cpld/jtagspi.cfg] 13 | 14 | if { [info exists BINFILE] } { 15 | set _BINFILE $BINFILE 16 | } else { 17 | set _BINFILE boot.bin 18 | } 19 | 20 | init 21 | jtagspi_init 0 bscan_spi_xc7a35t.bit 22 | jtagspi_program $_BINFILE 0x0 23 | shutdown 24 | 25 | -------------------------------------------------------------------------------- /data/veerwolf_nexys.xdc: -------------------------------------------------------------------------------- 1 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; 2 | create_clock -add -name tck_dmi -period 100.00 [get_pins tap/tap_dmi/TCK]; 3 | create_clock -add -name tck_dtmcs -period 100.00 [get_pins tap/tap_dtmcs/TCK]; 4 | create_clock -add -name tck_idcode -period 100.00 [get_pins tap/tap_idcode/DRCK]; 5 | 6 | #FIXME: Improve this later but hopefully ok for now. 7 | #Since the JTAG clock is slow and bits 0 and 1 are properly synced, we can be a bit careless about the rest 8 | set_false_path -from [get_cells -regexp {tap/dtmcs_r_reg\[([2-9]|[1-9][0-9])\]}] 9 | 10 | set_false_path -from [get_cells ddr2/serial_tx_reg] 11 | 12 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; 13 | 14 | set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rstn }]; 15 | 16 | set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports i_uart_rx] 17 | set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 18 | 19 | 20 | set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports o_flash_mosi]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 21 | set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports i_flash_miso]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 22 | #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 23 | #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 24 | set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports o_flash_cs_n]; 25 | 26 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }] 27 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }] 28 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }] 29 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }] 30 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { i_sw[4] }] 31 | set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { i_sw[5] }] 32 | set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { i_sw[6] }] 33 | set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[7] }] 34 | set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { i_sw[8] }] 35 | set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { i_sw[9] }] 36 | set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { i_sw[10] }] 37 | set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { i_sw[11] }] 38 | set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { i_sw[12] }] 39 | set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { i_sw[13] }] 40 | set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { i_sw[14] }] 41 | set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[15] }] 42 | 43 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }] 44 | set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }] 45 | set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }] 46 | set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }] 47 | set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { o_led[4] }] 48 | set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { o_led[5] }] 49 | set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { o_led[6] }] 50 | set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { o_led[7] }] 51 | set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { o_led[8] }] 52 | set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { o_led[9] }] 53 | set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { o_led[10] }] 54 | set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { o_led[11] }] 55 | set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { o_led[12] }] 56 | set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { o_led[13] }] 57 | set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { o_led[14] }] 58 | set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { o_led[15] }] 59 | -------------------------------------------------------------------------------- /data/veerwolf_nexys_debug.cfg: -------------------------------------------------------------------------------- 1 | # JTAG adapter configuration (on-board USB-JTAG adapter on Digilent Nexys A7) 2 | interface ftdi 3 | ftdi_device_desc "Digilent USB Device" 4 | ftdi_vid_pid 0x0403 0x6010 5 | ftdi_channel 0 6 | ftdi_layout_init 0x0088 0x008b 7 | reset_config none 8 | adapter_khz 10000 9 | 10 | transport select jtag 11 | 12 | # Configure JTAG chain and the target processor 13 | set _CHIPNAME riscv 14 | 15 | jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x03631093 -ignore-version 16 | set _TARGETNAME $_CHIPNAME.cpu 17 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 18 | 19 | # No MMU on VeeR (do not attempt virt2phys address translation) 20 | riscv set_enable_virt2phys off 21 | 22 | # Configure memory access method 23 | # Utilize "abstract access" to allow to reach VeeR's ICCM, DCCM and PIC core-local memories. 24 | # Note: Requires VeeR EH1 1.8+ and recent riscv-openocd (commit 22d771d20 from Sep 14, 2020, or newer). 25 | riscv set_mem_access abstract 26 | 27 | # Alternate memory access configuration - via "system bus" 28 | # Caution: ICCM, DCCM and PIC cannot be reached. 29 | # riscv set_mem_access sysbus 30 | 31 | # Custom numbers for RISC-V Debug JTAG registers 32 | # (needed due to JTAG tunneling via Xilinx BSCAN cell) 33 | riscv set_ir idcode 0x9 34 | riscv set_ir dmi 0x22 35 | riscv set_ir dtmcs 0x23 36 | 37 | # Expose custom VeeR's CSR dmst (csr1988) 38 | riscv expose_csrs 1988 39 | 40 | # Custom event hooks to flush VeeR ICACHE prior to step/resume 41 | proc veer_eh1_execute_fence {} { 42 | # Execute fence + fence.i via "dmst" register 43 | reg csr1988 0x3 44 | } 45 | 46 | $_TARGETNAME configure -event resume-start { 47 | veer_eh1_execute_fence 48 | } 49 | 50 | $_TARGETNAME configure -event step-start { 51 | veer_eh1_execute_fence 52 | } 53 | 54 | # Conclude OpenOCD configuration 55 | init 56 | 57 | # Halt the target 58 | halt 59 | -------------------------------------------------------------------------------- /data/veerwolf_nexys_program.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | 13 | if { [info exists BITFILE] } { 14 | set _BITFILE $BITFILE 15 | } else { 16 | set _BITFILE build/veerwolf_0/nexys_a7-vivado/veerwolf_0.bit 17 | } 18 | 19 | init 20 | pld load 0 $_BITFILE 21 | shutdown 22 | -------------------------------------------------------------------------------- /data/veerwolf_nexys_video_debug.cfg: -------------------------------------------------------------------------------- 1 | # JTAG adapter configuration (on-board USB-JTAG adapter on Digilent Nexys A7) 2 | interface ftdi 3 | ftdi_device_desc "Digilent USB Device" 4 | ftdi_vid_pid 0x0403 0x6010 5 | ftdi_channel 1 6 | ftdi_layout_init 0x0088 0x008b 7 | reset_config none 8 | adapter_khz 10000 9 | 10 | transport select jtag 11 | 12 | # Configure JTAG chain and the target processor 13 | set _CHIPNAME riscv 14 | 15 | jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x03631093 -ignore-version 16 | set _TARGETNAME $_CHIPNAME.cpu 17 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 18 | 19 | # No MMU on VeeR (do not attempt virt2phys address translation) 20 | riscv set_enable_virt2phys off 21 | 22 | # Configure memory access method 23 | # Utilize "abstract access" to allow to reach VeeR's ICCM, DCCM and PIC core-local memories. 24 | # Note: Requires VeeR EH1 1.8+ and recent riscv-openocd (commit 22d771d20 from Sep 14, 2020, or newer). 25 | riscv set_mem_access abstract 26 | 27 | # Alternate memory access configuration - via "system bus" 28 | # Caution: ICCM, DCCM and PIC cannot be reached. 29 | # riscv set_mem_access sysbus 30 | 31 | # Custom numbers for RISC-V Debug JTAG registers 32 | # (needed due to JTAG tunneling via Xilinx BSCAN cell) 33 | riscv set_ir idcode 0x9 34 | riscv set_ir dmi 0x22 35 | riscv set_ir dtmcs 0x23 36 | 37 | # Expose custom VeeR's CSR dmst (csr1988) 38 | riscv expose_csrs 1988 39 | 40 | # Custom event hooks to flush VeeR ICACHE prior to step/resume 41 | proc veer_eh1_execute_fence {} { 42 | # Execute fence + fence.i via "dmst" register 43 | reg csr1988 0x3 44 | } 45 | 46 | $_TARGETNAME configure -event resume-start { 47 | veer_eh1_execute_fence 48 | } 49 | 50 | $_TARGETNAME configure -event step-start { 51 | veer_eh1_execute_fence 52 | } 53 | 54 | # Conclude OpenOCD configuration 55 | init 56 | 57 | # Halt the target 58 | halt 59 | -------------------------------------------------------------------------------- /data/veerwolf_nexys_video_program.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 1 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | 13 | if { [info exists BITFILE] } { 14 | set _BITFILE $BITFILE 15 | } else { 16 | set _BITFILE build/veerwolf_0.7.5/nexys_video-vivado/veerwolf_0.7.5.bit 17 | } 18 | 19 | init 20 | pld load 0 $_BITFILE 21 | shutdown 22 | -------------------------------------------------------------------------------- /data/veerwolf_nexys_video_write_flash.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 1 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | source [find cpld/jtagspi.cfg] 13 | 14 | if { [info exists BINFILE] } { 15 | set _BINFILE $BINFILE 16 | } else { 17 | set _BINFILE boot.bin 18 | } 19 | 20 | init 21 | jtagspi_init 0 bscan_spi_xc7a200t.bit 22 | jtagspi_program $_BINFILE 0x0 23 | shutdown 24 | -------------------------------------------------------------------------------- /data/veerwolf_nexys_write_flash.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x0088 0x008b 6 | reset_config none 7 | adapter_khz 10000 8 | 9 | transport select jtag 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | source [find cpld/jtagspi.cfg] 13 | 14 | if { [info exists BINFILE] } { 15 | set _BINFILE $BINFILE 16 | } else { 17 | set _BINFILE boot.bin 18 | } 19 | 20 | init 21 | jtagspi_init 0 bscan_spi_xc7a100t.bit 22 | jtagspi_program $_BINFILE 0x0 23 | shutdown 24 | 25 | -------------------------------------------------------------------------------- /data/veerwolf_sim.cfg: -------------------------------------------------------------------------------- 1 | # JTAG adapter configuration 2 | # jtag_vpi == TCP-based "virtual" JTAG for connection to RTL simulations 3 | source [find interface/jtag_vpi.cfg] 4 | 5 | # Configure JTAG chain and the target processor 6 | set _CHIPNAME riscv 7 | 8 | jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x01 9 | 10 | set _TARGETNAME $_CHIPNAME.cpu 11 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 12 | 13 | # No MMU on VeeR (do not attempt virt2phys address translation) 14 | riscv set_enable_virt2phys off 15 | 16 | # Configure memory access method 17 | # Utilize "abstract access" to allow to reach VeeR's ICCM, DCCM and PIC core-local memories. 18 | # Note: Requires VeeR EH1 1.8+ and recent riscv-openocd (commit 22d771d20 from Sep 14, 2020, or newer). 19 | riscv set_mem_access abstract 20 | 21 | # Alternate memory access configuration - via "system bus" 22 | # Caution: ICCM, DCCM and PIC cannot be reached. 23 | # riscv set_mem_access sysbus 24 | 25 | # Expose custom VeeR's CSR dmst (csr1988) 26 | riscv expose_csrs 1988 27 | 28 | # Custom event hooks to flush VeeR ICACHE prior to step/resume 29 | proc veer_eh1_execute_fence {} { 30 | # Execute fence + fence.i via "dmst" register 31 | reg csr1988 0x3 32 | } 33 | 34 | $_TARGETNAME configure -event resume-start { 35 | veer_eh1_execute_fence 36 | } 37 | 38 | $_TARGETNAME configure -event step-start { 39 | veer_eh1_execute_fence 40 | } 41 | 42 | # Conclude OpenOCD configuration 43 | init 44 | 45 | # Halt the target 46 | halt 47 | -------------------------------------------------------------------------------- /data/verilator_waiver.vlt: -------------------------------------------------------------------------------- 1 | `verilator_config 2 | 3 | //These non-critical warnings must be fixed upstream. In the meantime they are waived to easier spot other warnings 4 | 5 | //pulp-platform.org::axi:0.25.0 6 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv" -lines 85-86 7 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv" -lines 93-94 8 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_demux.sv" -lines 460 9 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_demux.sv" -lines 467 10 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_demux.sv" -lines 479 11 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv" -lines 126 12 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv" -lines 162-163 13 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv" -lines 174 14 | lint_off -rule WIDTH -file "*/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv" -lines 182 15 | lint_off -rule CASEINCOMPLETE -file "*/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv" -lines 216 16 | lint_off -rule CASEINCOMPLETE -file "*/pulp-platform.org__axi_0.25.0/src/axi_pkg.sv" -lines 234 17 | lint_off -rule UNOPTFLAT -file "*/pulp-platform.org__axi_0.25.0/src/axi_demux.sv" -lines 48-49 18 | 19 | 20 | //pulp-platform.org::common_cells:1.20.0 21 | lint_off -rule UNOPTFLAT -file "*/pulp-platform.org__common_cells_1.20.0/src/lzc.sv" -lines 59-61 22 | lint_off -rule UNSIGNED -file "*/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv" -lines 208-209 23 | 24 | //::simple_spi:1.6-r1 25 | lint_off -rule CASEINCOMPLETE -file "*/simple_spi_1.6/rtl/verilog/simple_spi_top.v" -lines 244 26 | 27 | //chipsalliance.org:cores:VeeR_EH1:1.9 28 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EH1_1.9/design/pic_ctrl.sv" -lines 467-468 29 | 30 | //chipsalliance.org:cores:VeeR_EL2:1.4 31 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv" -lines 345-346 32 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv" -lines 144-145 33 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv" -lines 1346-1347 34 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv" -lines 211-212 35 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv" -lines 394-395 36 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv" -lines 225-226 37 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv" -lines 83-84 38 | lint_off -rule UNOPTFLAT -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv" -lines 543-544 39 | 40 | //There are 349 width warnings in VeeR EL2 which is too much to handle individually at this point 41 | lint_off -rule WIDTH -file "*/chipsalliance.org_cores_VeeR_EL2_1.4/design/*" 42 | 43 | //This is needed to silence a warning in a file included by el2_wrapper 44 | lint_off -rule WIDTH -file "*/veer_el2_wrapper.sv" -lines 28-29 45 | -------------------------------------------------------------------------------- /data/vivado_waiver.tcl: -------------------------------------------------------------------------------- 1 | #LiteDRAM warnings 2 | set_msg_config -id "Synth 8-350" -string "OSERDESE2 litedram_core" -suppress 3 | set_msg_config -id "Synth 8-350" -string "litedram_core.v ISERDESE2" -suppress 4 | set_msg_config -id "Synth 8-350" -string "litedram_core.v IDELAYCTRL" -suppress 5 | set_msg_config -id "Synth 8-350" -string "litedram_core.v IDELAYE2" -suppress 6 | set_msg_config -id "Synth 8-350" -string "litedram_core.v PLLE2_ADV" -suppress 7 | set_msg_config -id "Synth 8-4446" -string "litedram_core.v" -suppress 8 | set_msg_config -id "Synth 8-6014" -string "litedram_core.v" -suppress 9 | set_msg_config -id "Synth 8-3936" -string "memdat_2_reg" -suppress 10 | set_msg_config -id "Synth 8-3936" -string "memdat_4_reg" -suppress 11 | set_msg_config -id "Synth 8-3936" -string "memdat_18_reg" -suppress 12 | set_msg_config -id "Synth 8-7023" -string "litedram_core.v IDELAYE2" -suppress 13 | set_msg_config -id "Synth 8-7023" -string "litedram_core.v IDELAYCTRL" -suppress 14 | set_msg_config -id "Synth 8-7023" -string "litedram_core.v ISERDESE2" -suppress 15 | set_msg_config -id "Synth 8-7023" -string "litedram_core.v OSERDESE2" -suppress 16 | set_msg_config -id "Synth 8-7023" -string "litedram_core.v PLLE2_ADV" -suppress 17 | set_msg_config -id "DRC REQP-1839" -string "ddr2/ldc/storage" -suppress 18 | set_msg_config -id "DRC REQP-1840" -string "ddr2/ldc/storage" -suppress 19 | 20 | #VexRiscv warnings 21 | set_msg_config -id "Synth 8-6014" -string "VexRiscv.v" -suppress 22 | set_msg_config -id "Synth 8-3936" -string "memory_to_writeBack_MUL_HH_reg" -suppress 23 | 24 | #VeeR warnings 25 | set_msg_config -id "DRC REQP-1840" -string "rvtop/mem/Gen_dccm_enable.dccm/mem_bank" -suppress 26 | 27 | #VeeRwolf warning 28 | set_msg_config -id "Synth 8-4446" -string "veerwolf_nexys.v STARTUPE2" -suppress 29 | -------------------------------------------------------------------------------- /riscv-target/veer/compliance_io.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance IO Test Header File 2 | 3 | /* 4 | * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 15 | * either express or implied. 16 | * 17 | * See the License for the specific language governing permissions and 18 | * limitations under the License. 19 | * 20 | */ 21 | 22 | #ifndef _COMPLIANCE_IO_H 23 | #define _COMPLIANCE_IO_H 24 | 25 | //----------------------------------------------------------------------- 26 | // RV IO Macros (Non functional) 27 | //----------------------------------------------------------------------- 28 | 29 | #define RVTEST_IO_INIT 30 | #define RVTEST_IO_WRITE_STR(_SP, _STR) 31 | #define RVTEST_IO_CHECK() 32 | #define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) 33 | #define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) 34 | #define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) 35 | 36 | #endif // _COMPLIANCE_IO_H 37 | -------------------------------------------------------------------------------- /riscv-target/veer/compliance_test.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance Test Header File 2 | // Copyright (c) 2017, Codasip Ltd. All Rights Reserved. 3 | // See LICENSE for license details. 4 | // 5 | // Description: Common header file for RV32I tests 6 | 7 | #ifndef _COMPLIANCE_TEST_H 8 | #define _COMPLIANCE_TEST_H 9 | 10 | //----------------------------------------------------------------------- 11 | // RV Compliance Macros 12 | //----------------------------------------------------------------------- 13 | 14 | #define RV_COMPLIANCE_HALT \ 15 | la a0, data_begin; \ 16 | la a1, data_end; \ 17 | li a2, 0x80001008; \ 18 | compliance_halt_loop: \ 19 | beq a0, a1, compliance_halt_break; \ 20 | addi a3, a0, 4; \ 21 | compliance_halt_loop2: \ 22 | addi a3, a3, -1; \ 23 | \ 24 | lb a4, 0 (a3); \ 25 | srai a5, a4, 4; \ 26 | andi a5, a5, 0xF; \ 27 | li a6, 10; \ 28 | blt a5, a6, notLetter; \ 29 | addi a5, a5, 39; \ 30 | notLetter: \ 31 | addi a5, a5, 0x30; \ 32 | sb a5, 0 (a2); \ 33 | \ 34 | srai a5, a4, 0; \ 35 | andi a5, a5, 0xF; \ 36 | li a6, 10; \ 37 | blt a5, a6, notLetter2; \ 38 | addi a5, a5, 39; \ 39 | notLetter2: \ 40 | addi a5, a5, 0x30; \ 41 | sb a5, 0 (a2); \ 42 | bne a0, a3,compliance_halt_loop2; \ 43 | addi a0, a0, 4; \ 44 | \ 45 | li a4, '\n'; \ 46 | sb a4, 0 (a2); \ 47 | j compliance_halt_loop; \ 48 | j compliance_halt_break; \ 49 | compliance_halt_break:; \ 50 | li a0,0x80001009; \ 51 | sb a3,0(a0); 52 | 53 | #define RV_COMPLIANCE_RV32M 54 | 55 | #define RV_COMPLIANCE_CODE_BEGIN \ 56 | .section .text.init; \ 57 | .align 4; \ 58 | .globl _start; \ 59 | _start: \ 60 | 61 | #define RV_COMPLIANCE_CODE_END 62 | 63 | #define RV_COMPLIANCE_DATA_BEGIN .align 4; .global data_begin; data_begin: 64 | 65 | #define RV_COMPLIANCE_DATA_END .align 4; .global data_end; data_end: 66 | 67 | #endif 68 | -------------------------------------------------------------------------------- /riscv-target/veer/device/rv32i/Makefile.include: -------------------------------------------------------------------------------- 1 | TARGET_SIM ?= $(TARGETDIR)/$(RISCV_TARGET)/Vveerwolf_core_tb 2 | ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) 3 | $(error Target simulator executable '$(TARGET_SIM)` not found) 4 | endif 5 | 6 | RUN_TARGET=\ 7 | $(TARGET_SIM) \ 8 | +signature=$(*).signature.output \ 9 | +ram_init_file=$(<).hex \ 10 | +timeout=900000 \ 11 | 2> $@ 12 | 13 | RISCV_PREFIX ?= riscv32-unknown-elf- 14 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 15 | RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy 16 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 17 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 18 | 19 | COMPILE_TARGET=\ 20 | $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ 21 | -I$(ROOTDIR)/riscv-test-env/ \ 22 | -I$(TARGETDIR)/$(RISCV_TARGET)/ \ 23 | -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld $$< \ 24 | -o $$@; \ 25 | $$(RISCV_OBJCOPY) -O binary $$@ $$@.bin; \ 26 | $$(RISCV_OBJDUMP) -D $$@ > $$@.objdump; \ 27 | python3 $(TARGETDIR)/$(RISCV_TARGET)/makehex.py $$@.bin > $$@.hex; 28 | -------------------------------------------------------------------------------- /riscv-target/veer/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x0; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | /* . = 0x80000;*/ 14 | .data : { *(.data) } 15 | .data.string : { *(.data.string)} 16 | .bss : { *(.bss) } 17 | _end = .; 18 | } 19 | 20 | -------------------------------------------------------------------------------- /riscv-target/veer/makehex.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | with open(sys.argv[1], "rb") as f: 4 | data = f.read(4) 5 | while data: 6 | w2 = "{:02X}{:02X}{:02X}{:02X}".format(data[3], 7 | data[2], 8 | data[1], 9 | data[0]) 10 | try: 11 | data = f.read(4) 12 | w1 = "{:02X}{:02X}{:02X}{:02X}".format(data[3], 13 | data[2], 14 | data[1], 15 | data[0]) 16 | except: 17 | w1 = "00000000" 18 | print("{}{}".format(w1,w2)) 19 | data = f.read(4) 20 | -------------------------------------------------------------------------------- /rtl/bscan_tap.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License 15 | `default_nettype none 16 | module bscan_tap 17 | #( 18 | parameter AWIDTH = 7 19 | ) 20 | ( 21 | input wire clk, 22 | input wire rst, 23 | output wire [31:0] dmi_reg_wdata, 24 | output wire [AWIDTH-1:0] dmi_reg_addr, 25 | output wire dmi_reg_wr_en, 26 | output wire dmi_reg_en, 27 | 28 | input wire [31:0] dmi_reg_rdata, 29 | input wire [1:0] rd_status, 30 | 31 | output reg dmi_hard_reset, 32 | input wire [2:0] idle, 33 | input wire [1:0] dmi_stat, 34 | input wire [31:1] jtag_id, 35 | input wire [3:0] version); 36 | 37 | wire idcode_capture; 38 | wire idcode_tck; 39 | wire idcode_sel; 40 | wire idcode_shift; 41 | reg [31:0] idcode; 42 | 43 | BSCANE2 44 | #(.JTAG_CHAIN(2)) 45 | tap_idcode 46 | (.CAPTURE (idcode_capture), 47 | .DRCK (idcode_tck), 48 | .RESET (), 49 | .RUNTEST (), 50 | .SEL (idcode_sel), 51 | .SHIFT (idcode_shift), 52 | .TCK (), 53 | .TDI (), 54 | .TMS (), 55 | .TDO (idcode[0]), 56 | .UPDATE ()); 57 | 58 | always @(posedge idcode_tck) begin 59 | if (idcode_sel) 60 | if (idcode_capture) 61 | idcode <= {jtag_id, 1'b1}; 62 | else 63 | idcode <= {1'b0,idcode[31:1]}; 64 | end 65 | 66 | wire dmi_capture; 67 | wire dmi_tck; 68 | reg [31:0] dmi; 69 | wire dmi_sel; 70 | wire dmi_shift; 71 | wire dmi_tdi; 72 | wire dmi_update; 73 | 74 | BSCANE2 75 | #(.JTAG_CHAIN(4)) 76 | tap_dmi 77 | (.CAPTURE (dmi_capture), 78 | .DRCK (), 79 | .RESET (), 80 | .RUNTEST (), 81 | .SEL (dmi_sel), 82 | .SHIFT (dmi_shift), 83 | .TCK (dmi_tck), 84 | .TDI (dmi_tdi), 85 | .TMS (), 86 | .TDO (dmi[0]), 87 | .UPDATE (dmi_update)); 88 | 89 | always @(posedge dmi_tck) begin 90 | if (dmi_sel) 91 | if (dmi_capture) 92 | dmi <= {17'd0, idle, dmi_stat, AWIDTH[5:0], version}; 93 | else if (dmi_shift) 94 | dmi <= {dmi_tdi,dmi[31:1]}; 95 | dmi_hard_reset <= 1'b0; 96 | if (dmi_update & dmi_sel) 97 | dmi_hard_reset <= dmi[17]; 98 | end 99 | 100 | reg [40:0] dtmcs; 101 | reg [40:0] dtmcs_r; 102 | wire dtmcs_capture; 103 | wire dtmcs_tck; 104 | wire dtmcs_sel; 105 | wire dtmcs_shift; 106 | wire dtmcs_tdi; 107 | wire dtmcs_update; 108 | 109 | BSCANE2 110 | #(.JTAG_CHAIN(3)) 111 | tap_dtmcs 112 | (.CAPTURE (dtmcs_capture), 113 | .DRCK (), 114 | .RESET (), 115 | .RUNTEST (), 116 | .SEL (dtmcs_sel), 117 | .SHIFT (dtmcs_shift), 118 | .TCK (dtmcs_tck), 119 | .TDI (dtmcs_tdi), 120 | .TMS (), 121 | .TDO (dtmcs[0]), 122 | .UPDATE (dtmcs_update)); 123 | 124 | always @(posedge dtmcs_tck) begin 125 | if (dtmcs_sel) 126 | if (dtmcs_capture) 127 | dtmcs <= {7'd0, dmi_reg_rdata, rd_status}; 128 | else if (dtmcs_shift) 129 | dtmcs <= {dtmcs_tdi,dtmcs[40:1]}; 130 | dtmcs_r[1:0] <= 2'b00; 131 | if (dtmcs_update & dtmcs_sel) 132 | dtmcs_r <= dtmcs; 133 | end 134 | 135 | wire wr_en, rd_en; 136 | 137 | assign {dmi_reg_addr, dmi_reg_wdata, wr_en, rd_en} = dtmcs_r; 138 | 139 | 140 | 141 | reg [2:0] rden, wren; 142 | 143 | wire c_rd_en = rden[1] & ~rden[2]; 144 | wire c_wr_en = wren[1] & ~wren[2]; 145 | 146 | always @ ( posedge clk or posedge rst) begin 147 | if(rst) begin 148 | rden <= '0; 149 | wren <= '0; 150 | end else begin 151 | rden <= {rden[1:0], rd_en}; 152 | wren <= {wren[1:0], wr_en}; 153 | end 154 | end 155 | 156 | assign dmi_reg_en = c_wr_en | c_rd_en; 157 | assign dmi_reg_wr_en = c_wr_en; 158 | 159 | endmodule 160 | -------------------------------------------------------------------------------- /rtl/clk_gen_agilex.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: VeeRwolf Altera Agilex clock generation 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | module clk_gen_agilex 25 | (input wire i_clk, 26 | input wire i_rst, 27 | output wire o_clk_core, 28 | output wire o_rst_core); 29 | 30 | parameter CPU_TYPE = ""; 31 | 32 | wire o_clk_pll; 33 | wire locked; 34 | wire ninit_done; 35 | reg rst_reg1; 36 | reg rst_reg2; 37 | 38 | assign o_rst_core = rst_reg2; 39 | assign o_clk_core = o_clk_pll; 40 | 41 | // ================================================================ 42 | // Synchronize Reset 43 | // ================================================================ 44 | always @(posedge o_clk_pll) begin 45 | if (!locked || i_rst) begin 46 | rst_reg1 <= 1'b1; 47 | rst_reg2 <= 1'b1; 48 | end else begin 49 | rst_reg1 <= 1'b0; 50 | rst_reg2 <= rst_reg1; 51 | end 52 | end 53 | 54 | // ================================================================ 55 | // Agilex Reset Release 56 | // ================================================================ 57 | altera_agilex_config_reset_release_endpoint config_reset_release_endpoint( 58 | .conf_reset(ninit_done) 59 | ); 60 | 61 | ipm_iopll_basic #( 62 | .REFERENCE_CLOCK_FREQUENCY ("100.0 MHz"), 63 | .N_CNT (1), // divide factor of N-counter 64 | .M_CNT (8), // multiply factor of M-counter 65 | .C0_CNT ((CPU_TYPE == "EL2") ? 32 : 16), // divide factor for the output clock 66 | .C1_CNT (1), 67 | .C2_CNT (1), 68 | .C3_CNT (1), 69 | .C4_CNT (1), 70 | .C5_CNT (1), 71 | .C6_CNT (1), 72 | .PLL_SIM_MODEL ("") 73 | ) my_pll ( 74 | .refclk (i_clk), //input, width = 1 75 | .reset (ninit_done), //input, width = 1 76 | .outclk0 (o_clk_pll), //output, width = 1 77 | .outclk1 (), //output, width = 1 78 | .outclk2 (), //output, width = 1 79 | .outclk3 (), //output, width = 1 80 | .outclk4 (), //output, width = 1 81 | .outclk5 (), //output, width = 1 82 | .outclk6 (), //output, width = 1 83 | .locked (locked) //output, width = 1 84 | ); 85 | endmodule 86 | -------------------------------------------------------------------------------- /rtl/clk_gen_arty.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: VeeRwolf Basys3 clock generation 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | module clk_gen_arty 25 | (input wire i_clk, 26 | input wire i_rst, 27 | output wire o_clk_core, 28 | output reg o_rst_core); 29 | 30 | wire clkfb; 31 | wire locked; 32 | reg locked_r; 33 | 34 | PLLE2_BASE 35 | #(.BANDWIDTH("OPTIMIZED"), 36 | .CLKFBOUT_MULT(16), 37 | .CLKIN1_PERIOD(10.0), // 100 MHz 38 | .CLKOUT0_DIVIDE(64), // 25 MHz 39 | .DIVCLK_DIVIDE(1), 40 | .STARTUP_WAIT("FALSE")) 41 | PLLE2_BASE_inst 42 | (.CLKOUT0(o_clk_core), 43 | .CLKOUT1(), 44 | .CLKOUT2(), 45 | .CLKOUT3(), 46 | .CLKOUT4(), 47 | .CLKOUT5(), 48 | .CLKFBOUT(clkfb), 49 | .LOCKED(locked), 50 | .CLKIN1(i_clk), 51 | .PWRDWN(1'b0), 52 | .RST(i_rst), 53 | .CLKFBIN(clkfb)); 54 | 55 | always @(posedge o_clk_core) begin 56 | locked_r <= locked; 57 | o_rst_core <= !locked_r; 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /rtl/clk_gen_basys3.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: VeeRwolf Basys3 clock generation 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | module clk_gen_basys3 25 | (input wire i_clk, 26 | input wire i_rst, 27 | output wire o_clk_core, 28 | output reg o_rst_core); 29 | 30 | wire clkfb; 31 | wire locked; 32 | reg locked_r; 33 | 34 | PLLE2_BASE 35 | #(.BANDWIDTH("OPTIMIZED"), 36 | .CLKFBOUT_MULT(16), 37 | .CLKIN1_PERIOD(10.0), //100MHz 38 | .CLKOUT0_DIVIDE(64), 39 | .DIVCLK_DIVIDE(1), 40 | .STARTUP_WAIT("FALSE")) 41 | PLLE2_BASE_inst 42 | (.CLKOUT0(o_clk_core), 43 | .CLKOUT1(), 44 | .CLKOUT2(), 45 | .CLKOUT3(), 46 | .CLKOUT4(), 47 | .CLKOUT5(), 48 | .CLKFBOUT(clkfb), 49 | .LOCKED(locked), 50 | .CLKIN1(i_clk), 51 | .PWRDWN(1'b0), 52 | .RST(i_rst), 53 | .CLKFBIN(clkfb)); 54 | 55 | always @(posedge o_clk_core) begin 56 | locked_r <= locked; 57 | o_rst_core <= !locked_r; 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /rtl/clk_gen_nexys.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: VeeRwolf Nexys A7 clock generation 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | module clk_gen_nexys 25 | (input i_clk, 26 | input i_rst, 27 | output o_clk_core, 28 | output reg o_rst_core); 29 | 30 | parameter CPU_TYPE = ""; 31 | 32 | wire clkfb; 33 | wire locked; 34 | reg locked_r; 35 | 36 | PLLE2_BASE 37 | #(.BANDWIDTH("OPTIMIZED"), 38 | .CLKFBOUT_MULT(16), 39 | .CLKIN1_PERIOD(10.0), //100MHz 40 | .CLKOUT0_DIVIDE((CPU_TYPE == "EL2") ? 64 : 32), 41 | .DIVCLK_DIVIDE(1), 42 | .STARTUP_WAIT("FALSE")) 43 | PLLE2_BASE_inst 44 | (.CLKOUT0(o_clk_core), 45 | .CLKOUT1(), 46 | .CLKOUT2(), 47 | .CLKOUT3(), 48 | .CLKOUT4(), 49 | .CLKOUT5(), 50 | .CLKFBOUT(clkfb), 51 | .LOCKED(locked), 52 | .CLKIN1(i_clk), 53 | .PWRDWN(1'b0), 54 | .RST(i_rst), 55 | .CLKFBIN(clkfb)); 56 | 57 | always @(posedge o_clk_core) begin 58 | locked_r <= locked; 59 | o_rst_core <= !locked_r; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /rtl/dpram64.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Basic RAM model with separate read/write ports and byte-wise write enable 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | module dpram64 25 | #(parameter SIZE=0, 26 | parameter mem_clear = 0, 27 | parameter memfile = "") 28 | (input wire clk, 29 | input wire [7:0] we, 30 | input wire [63:0] din, 31 | input wire [$clog2(SIZE)-1:0] waddr, 32 | input wire [$clog2(SIZE)-1:0] raddr, 33 | output reg [63:0] dout); 34 | 35 | localparam AW = $clog2(SIZE); 36 | 37 | reg [63:0] mem [0:SIZE/8-1] /* verilator public */; 38 | 39 | integer i; 40 | wire [AW-4:0] wadd = waddr[AW-1:3]; 41 | 42 | always @(posedge clk) begin 43 | if (we[0]) mem[wadd][ 7: 0] <= din[ 7: 0]; 44 | if (we[1]) mem[wadd][15: 8] <= din[15: 8]; 45 | if (we[2]) mem[wadd][23:16] <= din[23:16]; 46 | if (we[3]) mem[wadd][31:24] <= din[31:24]; 47 | if (we[4]) mem[wadd][39:32] <= din[39:32]; 48 | if (we[5]) mem[wadd][47:40] <= din[47:40]; 49 | if (we[6]) mem[wadd][55:48] <= din[55:48]; 50 | if (we[7]) mem[wadd][63:56] <= din[63:56]; 51 | dout <= mem[raddr[AW-1:3]]; 52 | end 53 | 54 | generate 55 | initial begin 56 | if (mem_clear) 57 | for (i=0;i= mtimecmp); 250 | 251 | if (i_rst) begin 252 | mtime <= 64'd0; 253 | mtimecmp <= 64'd0; 254 | o_wb_ack <= 1'b0; 255 | end 256 | end 257 | endmodule 258 | -------------------------------------------------------------------------------- /rtl/wb_mem_wrapper.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Wrapper for on-chip memory instantiations 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | `default_nettype none 25 | module wb_mem_wrapper 26 | #(parameter MEM_SIZE = 0, 27 | parameter mem_clear = 0, 28 | parameter INIT_FILE = "") 29 | ( 30 | input wire i_clk, 31 | input wire i_rst, 32 | input wire [$clog2(MEM_SIZE)-1:2] i_wb_adr, 33 | input wire [31:0] i_wb_dat, 34 | input wire [3:0] i_wb_sel, 35 | input wire i_wb_we , 36 | input wire i_wb_cyc, 37 | input wire i_wb_stb, 38 | output reg o_wb_ack, 39 | output wire [31:0] o_wb_rdt); 40 | 41 | wire [31:0] mem_addr; 42 | wire [63:0] mem_wdata; 43 | wire [63:0] mem_rdata; 44 | 45 | wire [7:0] mem_we; 46 | 47 | assign mem_we[3:0] = (i_wb_cyc & i_wb_stb & i_wb_we & !i_wb_adr[2]) ? i_wb_sel : 4'd0; 48 | assign mem_we[7:4] = (i_wb_cyc & i_wb_stb & i_wb_we & i_wb_adr[2]) ? i_wb_sel : 4'd0; 49 | 50 | assign mem_wdata = {i_wb_dat, i_wb_dat}; 51 | 52 | assign o_wb_rdt = i_wb_adr[2] ? mem_rdata[63:32] : mem_rdata[31:0]; 53 | 54 | always @(posedge i_clk) begin 55 | o_wb_ack <= i_wb_cyc & i_wb_stb & !o_wb_ack; 56 | if (i_rst) 57 | o_wb_ack <= 1'b0; 58 | end 59 | 60 | dpram64 61 | #(.SIZE (MEM_SIZE), 62 | .mem_clear (mem_clear), 63 | .memfile (INIT_FILE)) 64 | ram 65 | (.clk (i_clk), 66 | .we (mem_we), 67 | .din (mem_wdata), 68 | .waddr ({i_wb_adr[$clog2(MEM_SIZE)-1:3],3'b000}), 69 | .raddr ({i_wb_adr[$clog2(MEM_SIZE)-1:3],3'b000}), 70 | .dout (mem_rdata)); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | TOOLCHAIN_PREFIX ?= riscv64-unknown-elf- 2 | RESET_VECTOR ?= 0 3 | FLASH_ADDR ?= 0x0 4 | 5 | bootloader.elf: boot_main.S spi_uimage_loader.S hexloader.S 6 | $(TOOLCHAIN_PREFIX)gcc -nostartfiles -march=rv32im_zicsr -mabi=ilp32 -Tlink.ld -o$@ $^ 7 | %.elf: %.S 8 | $(TOOLCHAIN_PREFIX)gcc -nostartfiles -march=rv32im_zicsr -mabi=ilp32 -Tlink.ld -o$@ $< 9 | %.vh: %.bin 10 | python3 makehex.py $< > $@ 11 | %.bin: %.elf 12 | $(TOOLCHAIN_PREFIX)objcopy -O binary $< $@ 13 | %.ihex: %.elf 14 | $(TOOLCHAIN_PREFIX)objcopy -O ihex $< $@ 15 | %.ub: %.bin 16 | mkimage \ 17 | -A riscv \ 18 | -C none \ 19 | -T standalone \ 20 | -a 0x0 \ 21 | -e $(RESET_VECTOR) \ 22 | -n '$@' \ 23 | -d $< \ 24 | $@ 25 | 26 | %.ubvh: %.ub 27 | objcopy --change-addresses $(FLASH_ADDR) -I binary -O verilog $< $@ 28 | 29 | clean: 30 | rm -f *.elf *.bin *.vh 31 | -------------------------------------------------------------------------------- /sw/blinky.S: -------------------------------------------------------------------------------- 1 | /* 2 | * LED Blinker 3 | * Assuming that GPIO_BASE is mapped to a GPIO core, which in turn is 4 | * connected to LEDs, this will light the LEDs one at a time. 5 | * Useful as smoke test to see that serv is running correctly 6 | */ 7 | #define GPIO_BASE 0x80001010 8 | #ifndef GPIO_BASE 9 | #define GPIO_BASE 0x40000000 10 | #endif 11 | 12 | #ifndef DELAY 13 | #define DELAY 0x100000 /* Loop 100000 times before inverting the LED */ 14 | #endif 15 | 16 | /* 17 | a0 = GPIO Base address 18 | t0 = Value 19 | t1 = Timer max value 20 | t2 = Current timer value 21 | 22 | */ 23 | 24 | .globl _start 25 | _start: 26 | /* Load GPIO base address to a0 */ 27 | lui a0, %hi(GPIO_BASE) 28 | addi a0, a0, %lo(GPIO_BASE) 29 | 30 | /* Set timer value to control blink speed */ 31 | li t1, DELAY 32 | 33 | bl1: 34 | /* Write to LEDs */ 35 | sb t0, 0(a0) 36 | 37 | /* invert LED */ 38 | xori t0, t0, 1 39 | 40 | /* Reset timer */ 41 | and t2, zero, zero 42 | 43 | /* Delay loop */ 44 | time1: 45 | addi t2, t2, 1 46 | bne t1, t2, time1 47 | j bl1 48 | -------------------------------------------------------------------------------- /sw/blinky.vh: -------------------------------------------------------------------------------- 1 | 0105051380001537 2 | 0055002300100337 3 | 000073B30012C293 4 | FE731EE300138393 5 | 00000000FEDFF06F 6 | -------------------------------------------------------------------------------- /sw/boot_main.S: -------------------------------------------------------------------------------- 1 | /* Base address of the GPIO controller used for DIP switches and LED */ 2 | #ifndef GPIO_BASE 3 | #define GPIO_BASE 0x80001010 4 | #endif 5 | 6 | #define RAM_INIT_DONE 0x8000100A 7 | #define CLK_FREQ_HZ 0x8000103C 8 | #define UART_BASE 0x80002000 9 | 10 | #define BAUD_RATE 115200 11 | 12 | #define REG_BRDL (4*0x00) /* Baud rate divisor (LSB) */ 13 | #define REG_IER (4*0x01) /* Interrupt enable reg. */ 14 | #define REG_FCR (4*0x02) /* FIFO control reg. */ 15 | #define REG_LCR (4*0x03) /* Line control reg. */ 16 | #define REG_LSR (4*0x05) /* Line status reg. */ 17 | #define LCR_CS8 0x03 /* 8 bits data size */ 18 | #define LCR_1_STB 0x00 /* 1 stop bit */ 19 | #define LCR_PDIS 0x00 /* parity disable */ 20 | 21 | #define LSR_THRE 0x20 22 | #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */ 23 | #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */ 24 | #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */ 25 | #define FCR_MODE0 0x00 /* set receiver in mode 0 */ 26 | #define FCR_MODE1 0x08 /* set receiver in mode 1 */ 27 | #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */ 28 | 29 | /* Registers used 30 | a4 = UART base 31 | a5 = String to print 32 | */ 33 | 34 | .globl _start 35 | .globl boot_fail 36 | _start: 37 | /* Setup mrac CSR 38 | 39 | Mark lower half of 32-bit address space as 40 | non-cacheable without side effects (mapped to RAM) 41 | and upper half as non-cacheable with side-effects 42 | (device memory). 43 | 44 | Bit pattern 1010101010101010_0000000000000000 45 | 46 | */ 47 | li t0, 0xAAAA0000 48 | csrw 0x7c0, t0 49 | 50 | jal uart_init 51 | 52 | la a5, boot_msg 53 | jal uart_writestr 54 | 55 | /* Wait until RAM initialization is done */ 56 | li t1, RAM_INIT_DONE 57 | 1: lbu t2, 0(t1) 58 | beqz t2, 1b 59 | la a5, ram_ok 60 | jal uart_writestr 61 | 62 | /* Read DIP switches to select boot mode 63 | 64 | Switch 15:14 determine boot mode 65 | 00 = boot from SPI Flash 66 | 01 = boot from serial 67 | 10 = boot from RAM (jump to address 0) 68 | 11 = Not defined 69 | 70 | */ 71 | li t1, GPIO_BASE 72 | lhu t2, 2(t1) 73 | srli t2, t2, 14 74 | 75 | /* Boot mode 0 */ 76 | addi t3, zero, 0 77 | beq t2, t3, prepare_spi_boot 78 | 79 | /* Boot mode 1 */ 80 | addi t3, t3, 1 81 | beq t2, t3, prepare_serial_boot 82 | 83 | /* Boot mode 2 */ 84 | addi t3, t3, 1 85 | beq t2, t3, ram_boot 86 | 87 | la a5, boot_mode_fail_str 88 | jal uart_writestr 89 | j boot_fail 90 | 91 | prepare_spi_boot: 92 | la a5, spi_boot_str 93 | jal uart_writestr 94 | j spi_boot 95 | 96 | prepare_serial_boot: 97 | la a5, serial_boot_str 98 | jal uart_writestr 99 | j serial_boot 100 | 101 | ram_boot: 102 | la a5, ram_boot_str 103 | jal uart_writestr 104 | jr zero 105 | 106 | /* Spin here on boot failures */ 107 | boot_fail: j boot_fail 108 | 109 | uart_init: 110 | /* Init UART */ 111 | li a4, UART_BASE 112 | 113 | /* Set DLAB bit in LCR */ 114 | li t3, 0x80 115 | sb t3, REG_LCR(a4) 116 | 117 | /* Set divisor regs */ 118 | li t3, CLK_FREQ_HZ 119 | lw t4, 0(t3) 120 | li t3, BAUD_RATE 121 | divu t3, t4, t3 122 | srli t4, t3, 4 123 | sb t4, REG_BRDL(a4) 124 | 125 | /* 8 data bits, 1 stop bit, no parity, clear DLAB */ 126 | li t3, LCR_CS8 | LCR_1_STB | LCR_PDIS 127 | sb t3, REG_LCR(a4) 128 | 129 | li t3, FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR 130 | sb t3, REG_FCR(a4) 131 | 132 | /* disable interrupts */ 133 | sb zero, REG_IER(a4) 134 | ret 135 | 136 | uart_writestr: /* Write string at a5 */ 137 | 138 | /* Load first byte */ 139 | lb t0, 0(a5) 140 | 141 | nextchar: 142 | /* Write to console and load next char until we get \0 */ 143 | putchar: 144 | /* Check for space in UART FIFO */ 145 | lb t6, REG_LSR(a4) 146 | andi t6, t6, LSR_THRE 147 | beqz t6, putchar 148 | 149 | /* Write byte */ 150 | sb t0, 0(a4) 151 | 152 | addi a5, a5, 1 153 | lb t0, 0(a5) 154 | bne t0, zero, nextchar 155 | 156 | ret 157 | 158 | boot_msg: 159 | .string "Booting VeeRwolf...\r\n" 160 | ram_ok: 161 | .string "RAM OK\r\n" 162 | spi_boot_str: 163 | .string "Booting from SPI Flash\r\n" 164 | serial_boot_str: 165 | .string "Booting from serial\r\n" 166 | ram_boot_str: 167 | .string "Booting from RAM\r\n" 168 | boot_mode_fail_str: 169 | .string "Unknown boot mode\r\n" 170 | -------------------------------------------------------------------------------- /sw/bootloader.vh: -------------------------------------------------------------------------------- 1 | 7C029073AAAA02B7 2 | 00000797098000EF 3 | 0D0000EF0FC78793 4 | 00A3031380001337 5 | FE038EE300034383 6 | 0F67879300000797 7 | 800013370B4000EF 8 | 0023538301030313 9 | 00000E1300E3D393 10 | 001E0E1303C38263 11 | 001E0E1303C38663 12 | 0000079703C38A63 13 | 080000EF10D78793 14 | 000007970340006F 15 | 070000EF0BB78793 16 | 000007971080006F 17 | 060000EF0C478793 18 | 000007972200006F 19 | 050000EF0CA78793 20 | 0000006F00000067 21 | 08000E1380002737 22 | 80001E3701C70623 23 | 000E2E8303CE0E13 24 | 200E0E130001CE37 25 | 004E5E9303CEDE33 26 | 00300E1301D70023 27 | 08700E1301C70623 28 | 0007022301C70423 29 | 0007828300008067 30 | 020FFF9301470F83 31 | 00570023FE0F8CE3 32 | 0007828300178793 33 | 00008067FE0294E3 34 | 20676E69746F6F42 35 | 666C6F7752656556 36 | 4152000A0D2E2E2E 37 | 42000A0D4B4F204D 38 | 6620676E69746F6F 39 | 20495053206D6F72 40 | 000A0D6873616C46 41 | 20676E69746F6F42 42 | 726573206D6F7266 43 | 6F42000A0D6C6169 44 | 726620676E69746F 45 | 0A0D4D4152206D6F 46 | 6E776F6E6B6E5500 47 | 6F6D20746F6F6220 48 | 000000000A0D6564 49 | 000073B32BC00313 50 | FE731EE300138393 51 | 04018193800011B7 52 | 0201802300300993 53 | 0061802304100313 54 | 0261802300100313 55 | 0C0000EF00300513 56 | FFF989930BC000EF 57 | ED9FF06F00099463 58 | 5273031356190337 59 | 0A0000EFFCB316E3 60 | 098000EF09C000EF 61 | 00060413064000EF 62 | 058000EF08C000EF 63 | 080000EF00060493 64 | 0006091304C000EF 65 | 070000EF074000EF 66 | 068000EF06C000EF 67 | 060000EF064000EF 68 | 058000EF05C000EF 69 | 050000EF054000EF 70 | 048000EF00000A13 71 | 00B3202301448333 72 | FF4458E3004A0A13 73 | 0185961300090067 74 | 0FF373130085D313 75 | 0066663301031313 76 | 0FF373130105D313 77 | 0066663300831313 78 | 006666330185D313 79 | 0040029300008067 80 | 0081C30300A18823 81 | FE031CE300137313 82 | 0101C3030085D593 83 | 0065E5B301831313 84 | FFF2829300855513 85 | 00008067FC029CE3 86 | 00000F9300000F13 87 | 0000019300000613 88 | 00058E03800025B7 89 | 0000043303A00313 90 | FE651EE30F0002EF 91 | 088000EF001F8F93 92 | 080000EF00050213 93 | 078000EF00851113 94 | 070000EF00A16133 95 | FFF5051302050C63 96 | 0940006F00050463 97 | 01E5802304700F13 98 | 06F00F130FF0000F 99 | 0FF0000F01E58023 100 | 01E5802302100F13 101 | 000600670FF0000F 102 | 0041023300218133 103 | 00A1002302C000EF 104 | FE221AE300110113 105 | 0FF4741301C000EF 106 | 02E00F1304041463 107 | 0FF0000F01E58023 108 | 05C002EFF71FF06F 109 | FF95051300654463 110 | 00451393FD050513 111 | 00654463048002EF 112 | FD050513FF950513 113 | 0FF5751300756533 114 | 0000806700A40433 115 | 01E5802304500F13 116 | 01E5802307200F13 117 | 06F00F1301E58023 118 | 07200F1301E58023 119 | FDDFF06F01E58023 120 | 0015751301458503 121 | 00058503FE050CE3 122 | 0000000000028067 123 | -------------------------------------------------------------------------------- /sw/count_switches.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Switch counter 3 | * Assuming that GPIO_BASE is mapped to a GPIO core, which in turn is 4 | * connected to LEDs and switches, this will count the number of switches 5 | * in the "on" position and light the same LEDs. 6 | */ 7 | #define GPIO_BASE 0x80001010 8 | 9 | /* 10 | a0 = GPIO Base address 11 | t0 = Value of switches 12 | t1 = Number of active switches (kind of) 13 | t2 = Value of currently evaluated switch 14 | 15 | */ 16 | 17 | .globl _start 18 | _start: 19 | /* Load GPIO base address to a0 */ 20 | li a0, GPIO_BASE 21 | 22 | /* Read switches */ 23 | lhu t0, 2(a0) 24 | 25 | /* Set t1 to one. */ 26 | addi t1, zero, 1 27 | 28 | /* Mask out lowest bit */ 29 | l1: andi t2, t0, 1 30 | 31 | /* If bit is set, left shift t1 one step */ 32 | beqz t2, l2 33 | slli t1, t1, 1 34 | 35 | /* Shift out next bit from t0 and repeat until t0 is empty */ 36 | l2: srli t0, t0, 1 37 | bnez t0, l1 38 | 39 | /* 40 | This changes the bit in t1 to indicate the number of steps it has 41 | been shifted 42 | */ 43 | addi t1, t1,-1 44 | 45 | /* Write to LEDs */ 46 | sh t1, 0(a0) 47 | 48 | j _start 49 | -------------------------------------------------------------------------------- /sw/hello.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Hello world for VeeRwolf 3 | * 4 | * Prints a fancy string and exits afterwards 5 | * 6 | */ 7 | #define CONSOLE_ADDR 0x80001008 8 | #define HALT_ADDR 0x80001009 9 | 10 | /* 11 | a0 = Console address 12 | a1 = String address 13 | t0 = Character to write 14 | */ 15 | 16 | .globl _start 17 | _start: 18 | /* Load console address to a0 */ 19 | li a0, CONSOLE_ADDR 20 | 21 | /* Load string address to a0 */ 22 | la a1, str 23 | 24 | /* Load first byte */ 25 | lb t0, 0(a1) 26 | next: 27 | /* Write to console and load next char until we get \0 */ 28 | sb t0, 0(a0) 29 | addi a1, a1, 1 30 | lb t0, 0(a1) 31 | bne t0, zero, next 32 | 33 | /* Halt simulation */ 34 | li a1, HALT_ADDR 35 | sb zero, 0(a1) 36 | str: 37 | .section .data 38 | .string "VeeR+FuseSoC rocks\n" 39 | -------------------------------------------------------------------------------- /sw/hello.ubvh: -------------------------------------------------------------------------------- 1 | @00000000 2 | 27 05 19 56 41 16 DC 33 64 7A 11 F2 00 00 00 44 3 | 00 00 00 00 00 00 00 00 AC 27 0A 14 05 1A 01 00 4 | 68 65 6C 6C 6F 2E 75 62 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 37 15 00 80 13 05 85 00 97 05 00 00 93 85 85 02 7 | 83 82 05 00 23 00 55 00 93 85 15 00 83 82 05 00 8 | E3 9A 02 FE B7 15 00 80 93 85 95 00 23 80 05 00 9 | 56 65 65 52 2B 46 75 73 65 53 6F 43 20 72 6F 63 10 | 6B 73 0A 00 11 | -------------------------------------------------------------------------------- /sw/hello.vh: -------------------------------------------------------------------------------- 1 | 0085051380001537 2 | 0285859300000597 3 | 0055002300058283 4 | 0005828300158593 5 | 800015B7FE029AE3 6 | 0005802300958593 7 | 7375462B52656556 8 | 636F7220436F5365 9 | 00000000000A736B 10 | -------------------------------------------------------------------------------- /sw/hello_uart.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Hello world for VeeRwolf 3 | * 4 | * Prints a fancy string using the UART and exits afterwards 5 | * 6 | */ 7 | #define CONSOLE_ADDR 0x80001008 8 | #define HALT_ADDR 0x80001009 9 | #define UART_BASE 0x80002000 10 | 11 | #define REG_BRDL (4*0x00) /* Baud rate divisor (LSB) */ 12 | #define REG_IER (4*0x01) /* Interrupt enable reg. */ 13 | #define REG_FCR (4*0x02) /* FIFO control reg. */ 14 | #define REG_LCR (4*0x03) /* Line control reg. */ 15 | #define REG_LSR (4*0x05) /* Line status reg. */ 16 | #define LCR_CS8 0x03 /* 8 bits data size */ 17 | #define LCR_1_STB 0x00 /* 1 stop bit */ 18 | #define LCR_PDIS 0x00 /* parity disable */ 19 | 20 | #define LSR_THRE 0x20 21 | #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */ 22 | #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */ 23 | #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */ 24 | #define FCR_MODE0 0x00 /* set receiver in mode 0 */ 25 | #define FCR_MODE1 0x08 /* set receiver in mode 1 */ 26 | #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */ 27 | 28 | /* 29 | a0 = UART address 30 | a1 = String address 31 | t0 = Character to write 32 | */ 33 | 34 | .globl _start 35 | _start: 36 | /* Init UART */ 37 | li a0, UART_BASE 38 | 39 | /* Set DLAB bit in LCR */ 40 | li t3, 0x80 41 | sb t3, REG_LCR(a0) 42 | 43 | /* Set divisor regs */ 44 | li t4, 27 45 | sb t4, REG_BRDL(a0) 46 | 47 | /* 8 data bits, 1 stop bit, no parity, clear DLAB */ 48 | li t3, LCR_CS8 | LCR_1_STB | LCR_PDIS 49 | sb t3, REG_LCR(a0) 50 | 51 | li t3, FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR 52 | sb t3, REG_FCR(a0) 53 | 54 | /* disable interrupts */ 55 | sb zero, REG_IER(a0) 56 | 57 | /* Load string address to a0 */ 58 | la a1, str 59 | 60 | /* Load first byte */ 61 | lb t0, 0(a1) 62 | next: 63 | /* Write to console and load next char until we get \0 */ 64 | jal put_byte 65 | addi a1, a1, 1 66 | lb t0, 0(a1) 67 | bne t0, zero, next 68 | 69 | loop: j loop 70 | /* Halt simulation */ 71 | li a1, HALT_ADDR 72 | //sw zero, 0(a1) 73 | 74 | put_byte: 75 | /* Check for space in UART FIFO */ 76 | lb t6, REG_LSR(a0) 77 | andi t6, t6, LSR_THRE 78 | beqz t6, put_byte 79 | 80 | sb t0, 0(a0) 81 | ret 82 | 83 | .section .data 84 | str: 85 | .string "VeeR+FuseSoC rocks\n" 86 | -------------------------------------------------------------------------------- /sw/hello_uart.vh: -------------------------------------------------------------------------------- 1 | 08000E1380002537 2 | 01B00E9301C50623 3 | 00300E1301D50023 4 | 08700E1301C50623 5 | 0005022301C50423 6 | 0005828306000593 7 | 0015859301C000EF 8 | FE029AE300058283 9 | 800015B70000006F 10 | 01450F8300958593 11 | FE0F8CE3020FFF93 12 | 0000806700550023 13 | 7375462B52656556 14 | 636F7220436F5365 15 | 00000000000A736B 16 | -------------------------------------------------------------------------------- /sw/hexloader.S: -------------------------------------------------------------------------------- 1 | #define UART_BASE 0x80002000 2 | /* 3 | x1 : ra = return address for other calls 4 | x2 : sp = start address 5 | x3 : gp = base address 6 | x4 : tp = record length 7 | x5 : t0 = return address for getc 8 | x6 : t1 = ':' 9 | x7 : t2 = parsebyte temp 10 | x8 : s0 = crc 11 | x9 : s1 = record type 12 | x10 : a0 = call/return value 13 | x11 : a1 = UART base address 14 | x12 : a2 = Program entry point 15 | */ 16 | #define REG_BRDL (4*0x00) /* Baud rate divisor (LSB) */ 17 | #define REG_BRDH (4*0x01) /* Baud rate divisor (MSB) */ 18 | #define REG_RDR (4*0x00) /* Receiver data reg. */ 19 | #define REG_MDC (4*0x04) /* Modem control reg. */ 20 | #define REG_IER (4*0x01) /* Interrupt enable reg. */ 21 | #define REG_IIR (4*0x02) /* Interrupt ID reg. */ 22 | #define REG_FCR (4*0x02) /* FIFO control reg. */ 23 | #define REG_LCR (4*0x03) /* Line control reg. */ 24 | #define REG_MDC (4*0x04) /* Modem control reg. */ 25 | #define REG_LSR (4*0x05) /* Line status reg. */ 26 | #define REG_MSR (4*0x06) /* Modem status reg. */ 27 | #define REG_DLF (4*0xC0) /* Divisor Latch Fraction */ 28 | 29 | #define LCR_CS8 0x03 /* 8 bits data size */ 30 | #define LCR_1_STB 0x00 /* 1 stop bit */ 31 | #define LCR_PDIS 0x00 /* parity disable */ 32 | 33 | #define MCR_DTR 0x01 /* dtr output */ 34 | #define MCR_RTS 0x02 /* rts output */ 35 | #define MCR_OUT2 0x08 /* output #2 */ 36 | 37 | #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */ 38 | #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */ 39 | #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */ 40 | #define FCR_MODE0 0x00 /* set receiver in mode 0 */ 41 | #define FCR_MODE1 0x08 /* set receiver in mode 1 */ 42 | #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */ 43 | 44 | .globl serial_boot 45 | serial_boot: 46 | addi t5, zero, 0 47 | addi t6, zero, 0 48 | addi a2, zero, 0 49 | addi gp, zero, 0 50 | li a1, UART_BASE 51 | 52 | /* clear the port */ 53 | lb t3, REG_RDR(a1) 54 | 55 | li t1, ':' 56 | 57 | /* Clear CRC */ 58 | add s0, zero, zero 59 | 60 | /* Find start of new record by looking for ':' */ 61 | findrecord: 62 | jal t0, get_byte 63 | /* get_byte returns byte in a0 */ 64 | bne a0, t1, findrecord 65 | addi t6, t6, 1 66 | 67 | /* Get record length */ 68 | jal ra, parsebyte 69 | addi tp, a0, 0 70 | 71 | /* Get start address */ 72 | jal ra, parsebyte 73 | slli sp, a0, 8 74 | 75 | jal ra, parsebyte 76 | or sp, sp, a0 77 | 78 | /* Get record type */ 79 | jal ra, parsebyte 80 | 81 | /* Record type 0 == data record */ 82 | beqz a0, datarecord 83 | 84 | addi a0, a0, -1 85 | /* Record type 1 == end of file record */ 86 | beqz a0, eofrecord 87 | 88 | /* Abort on non-supported record types for now */ 89 | j error 90 | 91 | eofrecord: 92 | li t5, 'G' 93 | sb t5, 0(a1) 94 | fence 95 | li t5, 'o' 96 | sb t5, 0(a1) 97 | fence 98 | li t5, '!' 99 | sb t5, 0(a1) 100 | fence 101 | jr a2 102 | 103 | datarecord: 104 | add sp, gp, sp /* Base address + record offset */ 105 | add tp, sp, tp /* Base address + record offset + record length */ 106 | 1: 107 | jal parsebyte 108 | sb a0, 0(sp) 109 | addi sp, sp, 1 110 | bne tp, sp, 1b 111 | 112 | crc: 113 | jal parsebyte 114 | andi s0, s0, 0xff 115 | bnez s0, error 116 | 117 | li t5, '.' 118 | sb t5, 0(a1) 119 | fence 120 | 121 | j findrecord 122 | 123 | /* 124 | Read two hex chars and combine to byte 125 | */ 126 | parsebyte: 127 | /* Get first nibble */ 128 | jal t0, get_byte 129 | blt a0, t1, 1f 130 | addi a0, a0, -7 131 | 1: addi a0, a0, -48 132 | 133 | slli t2, a0, 4 134 | 135 | /* Get second nibble */ 136 | jal t0, get_byte 137 | blt a0, t1, 2f 138 | addi a0, a0, -7 139 | 2: addi a0, a0, -48 140 | 141 | or a0, a0, t2 142 | andi a0, a0, 0xff 143 | 144 | /* Update CRC */ 145 | add s0, s0, a0 146 | 147 | ret 148 | 149 | error: 150 | li t5, 'E' 151 | sb t5, 0(a1) 152 | li t5, 'r' 153 | sb t5, 0(a1) 154 | sb t5, 0(a1) 155 | li t5, 'o' 156 | sb t5, 0(a1) 157 | li t5, 'r' 158 | sb t5, 0(a1) 159 | 160 | /* Nothing to do. Spin here */ 161 | j error 162 | 163 | get_byte: 164 | /* Read line status reg and check data available bit */ 165 | lb a0, REG_LSR(a1) 166 | andi a0, a0, 1 167 | beqz a0, get_byte 168 | 169 | /* Get character */ 170 | lb a0, REG_RDR(a1) 171 | jr t0 172 | -------------------------------------------------------------------------------- /sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0; 7 | .text : { *(.text) } 8 | .data : { *(.data) } 9 | .bss : { *(.bss) } 10 | } 11 | -------------------------------------------------------------------------------- /sw/makehex.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | with open(sys.argv[1], "rb") as f: 4 | cnt = 7 5 | s = ["00"]*8 6 | while True: 7 | data = f.read(1) 8 | if not data: 9 | print(''.join(s)) 10 | exit(0) 11 | s[cnt] = "{:02X}".format(data[0]) 12 | if cnt == 0: 13 | print(''.join(s)) 14 | s = ["00"]*8 15 | cnt = 8 16 | cnt -= 1 17 | -------------------------------------------------------------------------------- /sw/memtest.S: -------------------------------------------------------------------------------- 1 | #define GPIO_BASE 0x80001010 2 | #define DELAY 0x1000 /*0000*/ /* Loop 100000 times before inverting the LED */ 3 | #define MEM_START 0 4 | #define MEM_END 0x1FF 5 | 6 | .globl _start 7 | _start: 8 | li x1, 0x03020100 //Word 1 9 | li x2, 0x07060504 //Word 2 10 | li x8, 0x0B0A0908 //Word 3 11 | li x9, 0x0F0E0D0C //Word 4 12 | 13 | li x3, MEM_START //Address base pointer 14 | li x7, MEM_END 15 | 16 | addi x10, x0, 16 17 | wordloop: 18 | add x4, x0, x0 //Offset pointer 19 | sw x1, 0(x3) 20 | sw x2, 4(x3) 21 | sw x8, 8(x3) 22 | sw x9, 12(x3) 23 | byteloop: 24 | add x5, x3, x4 //Byte address pointer 25 | lb x6, 0(x5) //Loaded byte 26 | bne x4, x6, error 27 | 28 | addi x4, x4, 1 29 | bne x4, x10, byteloop 30 | 31 | /* Destroy written memory */ 32 | sw x0, 0(x3) 33 | sw x0, 4(x3) 34 | sw x0, 8(x3) 35 | sw x0, 12(x3) 36 | 37 | addi x3, x3, 16 38 | blt x3, x7, wordloop 39 | 40 | 41 | li a0, GPIO_BASE 42 | addi t0, x0, 1 43 | sb t0, 0(a0) 44 | 45 | done: 46 | j done 47 | 48 | error: 49 | li a0, GPIO_BASE 50 | li t1, DELAY 51 | 52 | bl1: 53 | sb t0, 0(a0) 54 | xori t0, t0, 1 55 | and t2, zero, zero 56 | time1: 57 | addi t2, t2, 1 58 | bne t1, t2, time1 59 | j bl1 60 | -------------------------------------------------------------------------------- /sw/memtest.vh: -------------------------------------------------------------------------------- 1 | 10008093030200B7 2 | 5041011307060137 3 | 908404130B0A1437 4 | D0C484930F0E14B7 5 | 1FF0039300000193 6 | 0000023301000513 7 | 0021A2230011A023 8 | 0091A6230081A423 9 | 00028303004182B3 10 | 0012021302621C63 11 | 0001A023FEA218E3 12 | 0001A4230001A223 13 | 010181930001A623 14 | 80001537FC71C2E3 15 | 0010029301050513 16 | 0000006F00550023 17 | 0105051380001537 18 | 0055002300001337 19 | 000073B30012C293 20 | FE731EE300138393 21 | 00000000FEDFF06F 22 | -------------------------------------------------------------------------------- /sw/spi_uimage_loader.S: -------------------------------------------------------------------------------- 1 | /* Assembly program to go into the boot ROM 2 | For use with the simple_spi core and standard SPI flash 3 | interface-compatible parts (ST M25P16 for example.) 4 | 5 | Loads an image in the U-boot uimage format from SPI Flash 6 | in the the RAM at the address specified in the uimage header. 7 | After loading is completed, it will jump to the entry point 8 | address specified in the uimage header. 9 | 10 | To keep it simple, only basic sanity checks are made on the image 11 | */ 12 | 13 | /* Base address of the SPI controller used to communicate with the Flash */ 14 | #ifndef SPI_BASE 15 | #define SPI_BASE 0x80001040 16 | #endif 17 | 18 | /* Base address of the GPIO controller used to blink LED */ 19 | #ifndef GPIO_BASE 20 | #define GPIO_BASE 0x80001010 21 | #endif 22 | 23 | /* 24-bit address in SPI Flash where application image is stored */ 24 | #ifndef BOOTROM_ADDR 25 | #define BOOTROM_ADDR 0x000000 26 | #endif 27 | 28 | /* Flash needs 300 us to warm up from power-on. In practice, this is only an 29 | issue in simulations as FPGA boot is far longer than 300 us 30 | */ 31 | #ifndef INIT_DELAY 32 | #define INIT_DELAY 700 33 | #endif 34 | 35 | #define RETRIES 3 36 | 37 | #define SPI_SPCR 0x00 38 | #define SPI_SPSR 0x08 39 | #define SPI_SPDR 0x10 40 | #define SPI_SPER 0x18 41 | #define SPI_SPSS 0x20 42 | 43 | #define SPI_SPSS_INIT 0x1 44 | #define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/ 45 | 46 | /* Registers used 47 | ra link register 48 | t1 temp register 49 | t2 temp register 50 | s0 Image size 51 | s1 Load address 52 | s2 Reset vector 53 | s3 Retry counter 54 | gp SPI master base address 55 | a3 get_rx_data return value 56 | t3 temp register 57 | */ 58 | 59 | .globl spi_boot 60 | spi_boot: 61 | 62 | #if INIT_DELAY 63 | li t1, INIT_DELAY 64 | and t2, zero, zero 65 | 1: addi t2,t2,1 66 | bne t1, t2, 1b 67 | #endif 68 | 69 | /* Load SPI base address to gp */ 70 | li gp, SPI_BASE 71 | 72 | li s3, RETRIES 73 | spi_init: 74 | /* Clear slave selects */ 75 | sb zero, SPI_SPSS(gp) 76 | 77 | /* Set clock divider to 4 (arbitrarily chosen value) 78 | and enable controller */ 79 | addi t1, zero, 0x40 | 0x01 80 | sb t1, SPI_SPCR(gp) 81 | 82 | /* Set appropriate slave select */ 83 | addi t1, zero, 1 84 | sb t1, SPI_SPSS(gp) 85 | 86 | /* Set command to READ at BOOTROM_ADDR */ 87 | li a0, ((BOOTROM_ADDR & 0xFF) <<24) | ((BOOTROM_ADDR & 0xFF00) << 8) | ((BOOTROM_ADDR & 0xFF0000) >> 8) | 0x3 88 | jal spi_xfer 89 | 90 | /* Get magic word */ 91 | jal spi_xfer 92 | 93 | /* Verify that magic word is (endian-swapped) 0x27051956 94 | Retry a couple of times before we give up */ 95 | addi s3, s3, -1 96 | beqz s3, boot_fail 97 | li t1, 0x56190527 98 | bne t1, a1, spi_init 99 | 100 | 101 | read_header: 102 | /* Dummy read two words */ 103 | jal spi_xfer 104 | jal spi_xfer 105 | 106 | /* Load image size to s0 */ 107 | jal spi_xfer 108 | jal endian_swap 109 | mv s0, a2 110 | 111 | /* Load RAM base address to s1 */ 112 | jal spi_xfer 113 | jal endian_swap 114 | mv s1, a2 115 | 116 | /* Load reset vector to s2 */ 117 | jal spi_xfer 118 | jal endian_swap 119 | mv s2, a2 120 | 121 | /* Dummy read rest of header */ 122 | jal spi_xfer //dcrc 123 | jal spi_xfer //os, arch, type, comp 124 | 125 | jal spi_xfer 126 | jal spi_xfer 127 | jal spi_xfer 128 | jal spi_xfer 129 | jal spi_xfer 130 | jal spi_xfer 131 | jal spi_xfer 132 | jal spi_xfer 133 | 134 | /* Clear number of copied bytes */ 135 | addi s4, zero, 0 136 | copy_to_ram: 137 | jal spi_xfer 138 | 139 | /* Set memory store address */ 140 | add t1, s1, s4 141 | 142 | /* Write word to RAM */ 143 | sw a1, 0(t1) 144 | 145 | /* Increase counter */ 146 | addi s4, s4, 4 147 | 148 | /* Check if file is completely copied */ 149 | bgt s0, s4, copy_to_ram 150 | 151 | /* Jump to entry point */ 152 | goto_reset: 153 | jr s2 154 | 155 | /* Reads ddccbbaa from a1, stores aabbccdd to a2 */ 156 | endian_swap: 157 | slli a2, a1, 24 // a2 = aa000000 158 | srli t1, a1, 8 // t1 = 00ddccbb 159 | andi t1, t1, 0xff // t1 = 000000bb 160 | slli t1, t1, 16 // t1 = 00bb0000 161 | or a2, a2, t1 // a2 = aabb0000 162 | 163 | srli t1, a1, 16 // t1 = 0000ddcc 164 | andi t1, t1, 0xff // t1 = 000000cc 165 | slli t1, t1, 8 // t1 = 0000cc00 166 | or a2, a2, t1 // a2 = aabbcc00 167 | 168 | srli t1, a1, 24 // t1 = 000000dd 169 | or a2, a2, t1 // a2 = aabbccdd 170 | 171 | ret 172 | 173 | spi_xfer: 174 | /* Loop four times */ 175 | addi t0, zero, 4 176 | 177 | spi_xfer_loop: 178 | /* Send data in a0[7:0] */ 179 | sb a0, SPI_SPDR(gp) 180 | 181 | spi_xfer_poll: 182 | /* Wait for data in RX FIFO */ 183 | lbu t1, SPI_SPSR(gp) 184 | andi t1, t1, SPI_SPSR_RX_CHECK 185 | bnez t1, spi_xfer_poll 186 | 187 | srli a1, a1, 8 188 | lbu t1, SPI_SPDR(gp) 189 | slli t1, t1, 24 190 | or a1, a1, t1 191 | 192 | srli a0, a0, 8 193 | addi t0, t0, -1 194 | bnez t0, spi_xfer_loop 195 | 196 | ret 197 | -------------------------------------------------------------------------------- /sw/veerwolf_zephyr_demo/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | cmake_minimum_required(VERSION 3.13.1) 4 | 5 | include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) 6 | project(veerwolf_demo) 7 | 8 | target_sources(app PRIVATE src/main.c) 9 | -------------------------------------------------------------------------------- /sw/veerwolf_zephyr_demo/src/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019 Western Digital Corporation or its affiliates 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #include 8 | #include 9 | 10 | void main(void) 11 | { 12 | uint8_t ver_patch = sys_read8(0x80001000); 13 | uint8_t ver_minor = sys_read8(0x80001001); 14 | uint8_t ver_major = sys_read8(0x80001002); 15 | uint8_t ver_misc = sys_read8(0x80001003); 16 | 17 | uint32_t ver_sha = sys_read32(0x80001004); 18 | 19 | printk("\nVeeRwolf version %d.%d.%d.%d (SHA %08x)\n", 20 | ver_major, 21 | ver_minor, 22 | ver_patch, 23 | ver_misc & 0x7F, 24 | ver_sha); 25 | 26 | printk(" __\n"); 27 | printk(" [] []-o CHIPS\n"); 28 | printk(" o-[] []\n"); 29 | printk(" [] []-o ALLIANCE\n"); 30 | printk(" o-[]__[]\n\n"); 31 | 32 | if (ver_misc & 0x80) 33 | printk("Warning! VeeRwolf was built from a modified source tree\n"); 34 | 35 | uint8_t mem_status = sys_read8(0x8000100a); 36 | if (mem_status & 0x1) 37 | printk("Memory test completed %s\n", (mem_status & 2) ? "with errors" : "successfully"); 38 | else 39 | printk("Warning! Memory test did not complete\n"); 40 | 41 | printk("CPU type: "); 42 | uint32_t marchid; 43 | __asm__ volatile ("csrr %0, marchid" : "=r" (marchid)); 44 | switch (marchid) { 45 | case 11 : printk("EH1\n"); break; 46 | case 16 : printk("EL2\n"); break; 47 | default : printk("Unknown (marchid=%d)\n", marchid); 48 | } 49 | 50 | printk("Clock frequency: %d MHz\n", sys_read32(0x8000103c)/1000000); 51 | 52 | //Exit simulation. No effect on hardware 53 | sys_write8(1, 0x80001009); 54 | 55 | printk("Now proceeding to blink the LED\n"); 56 | 57 | uint16_t leds = 1; 58 | uint16_t gpio_old = sys_read16(0x80001012); 59 | uint16_t gpio_new = sys_read16(0x80001012); 60 | while (1) { 61 | sys_write16(leds, 0x80001010); 62 | leds = (leds << 1) | (leds >> 15); 63 | gpio_new = sys_read16(0x80001012); 64 | if (gpio_old != gpio_new) { 65 | printk("GPIO is now %04x\n", gpio_new); 66 | gpio_old = gpio_new; 67 | } 68 | k_msleep(100); 69 | } 70 | } 71 | -------------------------------------------------------------------------------- /tb/tb.cpp: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Verilator testbench for VeeRwolf 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | #include 25 | #include 26 | 27 | #include 28 | 29 | #include "verilated_vcd_c.h" 30 | #include "Vveerwolf_core_tb.h" 31 | 32 | using namespace std; 33 | 34 | static bool done; 35 | 36 | const int JTAG_VPI_SERVER_PORT = 5555; 37 | const int JTAG_VPI_USE_ONLY_LOOPBACK = true; 38 | 39 | vluint64_t main_time = 0; // Current simulation time 40 | // This is a 64-bit integer to reduce wrap over issues and 41 | // allow modulus. You can also use a double, if you wish. 42 | 43 | double sc_time_stamp () { // Called by $time in Verilog 44 | return main_time; // converts to double, to match 45 | // what SystemC does 46 | } 47 | 48 | void INThandler(int signal) 49 | { 50 | printf("\nCaught ctrl-c\n"); 51 | done = true; 52 | } 53 | 54 | typedef struct { 55 | uint8_t state; 56 | char ch; 57 | uint32_t baud_t; 58 | vluint64_t last_update; 59 | } uart_context_t; 60 | 61 | void uart_init(uart_context_t *context, uint32_t baud_rate) { 62 | context->baud_t = 1000*1000*1000/baud_rate; 63 | context->state = 0; 64 | } 65 | 66 | int do_uart(uart_context_t *context, bool rx) { 67 | if (context->state == 0) { 68 | if (rx) 69 | context->state++; 70 | } 71 | else if (context->state == 1) { 72 | if (!rx) { 73 | context->last_update = main_time + context->baud_t/2; 74 | context->state++; 75 | } 76 | } 77 | else if(context->state == 2) { 78 | if (main_time > context->last_update) { 79 | context->last_update += context->baud_t; 80 | context->ch = 0; 81 | context->state++; 82 | } 83 | } 84 | else if (context->state < 11) { 85 | if (main_time > context->last_update) { 86 | context->last_update += context->baud_t; 87 | context->ch |= rx << (context->state-3); 88 | context->state++; 89 | } 90 | } 91 | else { 92 | if (main_time > context->last_update) { 93 | context->last_update += context->baud_t; 94 | context->state=1; 95 | return 1; 96 | } 97 | } 98 | return 0; 99 | } 100 | 101 | int main(int argc, char **argv, char **env) 102 | { 103 | Verilated::commandArgs(argc, argv); 104 | bool gpio0 = false; 105 | Vveerwolf_core_tb* top = new Vveerwolf_core_tb; 106 | 107 | VerilatedVcdC * tfp = 0; 108 | const char *vcd = Verilated::commandArgsPlusMatch("vcd="); 109 | if (vcd[0]) { 110 | Verilated::traceEverOn(true); 111 | tfp = new VerilatedVcdC; 112 | top->trace (tfp, 99); 113 | tfp->open ("trace.vcd"); 114 | } 115 | 116 | const char *arg_jtag = Verilated::commandArgsPlusMatch("jtag_vpi_enable="); 117 | VerilatorJtagServer* jtag = NULL; 118 | if (arg_jtag[0]) { 119 | jtag = new VerilatorJtagServer(10); /* Jtag clock is 10 period */ 120 | if (jtag->init_jtag_server(JTAG_VPI_SERVER_PORT, JTAG_VPI_USE_ONLY_LOOPBACK) 121 | != VerilatorJtagServer::SUCCESS) { 122 | printf("Could not initialize jtag_vpi server. Ending simulation.\n"); 123 | exit(1); 124 | } 125 | } 126 | 127 | uart_context_t uart_context; 128 | int baud_rate = 115200; 129 | uart_init(&uart_context, baud_rate); 130 | vluint64_t timeout = 0; 131 | const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout="); 132 | if (arg_timeout[0]) 133 | timeout = atoi(arg_timeout+9); 134 | 135 | signal(SIGINT, INThandler); 136 | 137 | top->clk = 1; 138 | top->rst = 1; 139 | while (!(done || Verilated::gotFinish())) { 140 | if (main_time == 100) { 141 | printf("Releasing reset\n"); 142 | top->rst = 0; 143 | } 144 | if (main_time == 200) 145 | top->i_jtag_trst_n = true; 146 | 147 | top->eval(); 148 | if (tfp) 149 | tfp->dump(main_time); 150 | if (baud_rate && do_uart(&uart_context, top->o_uart_tx)) 151 | putchar(uart_context.ch); 152 | if (jtag && (main_time > 300)) { 153 | int ret = jtag->doJTAG(main_time/20, //doJtag requires t to only increment by one 154 | &top->i_jtag_tms, 155 | &top->i_jtag_tdi, 156 | &top->i_jtag_tck, 157 | top->o_jtag_tdo); 158 | if (ret != VerilatorJtagServer::SUCCESS) { 159 | if (ret == VerilatorJtagServer::CLIENT_DISCONNECTED) { 160 | printf("Ending simulation. Reason: jtag_vpi client disconnected.\n"); 161 | done = true; 162 | } 163 | else { 164 | printf("Ending simulation. Reason: jtag_vpi error encountered.\n"); 165 | done = true; 166 | } 167 | } 168 | } 169 | if (gpio0 != (top->o_gpio & 0x1)) { 170 | gpio0 = top->o_gpio & 0x1; 171 | printf("%lu: gpio0 is %s\n", main_time, gpio0 ? "on" : "off"); 172 | } 173 | if (timeout && (main_time >= timeout)) { 174 | printf("Timeout: Exiting at time %lu\n", main_time); 175 | done = true; 176 | } 177 | top->clk = !top->clk; 178 | main_time+=10; 179 | } 180 | 181 | if (tfp) 182 | tfp->close(); 183 | 184 | exit(0); 185 | } 186 | -------------------------------------------------------------------------------- /tb/uart_decoder.v: -------------------------------------------------------------------------------- 1 | module uart_decoder 2 | #(parameter BAUD_RATE = 0) 3 | (input rx); 4 | 5 | localparam T = 1000000000/BAUD_RATE; 6 | 7 | integer i; 8 | reg [7:0] ch; 9 | 10 | initial forever begin 11 | @(negedge rx); 12 | #(T/2) ch = 0; 13 | for (i=0;i<8;i=i+1) 14 | #T ch[i] = rx; 15 | $write("%c",ch); 16 | $fflush; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /tb/veerwolf_core_tb.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Verilog testbench for VeeRwolf 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | `default_nettype none 25 | module veerwolf_core_tb 26 | #(parameter bootrom_file = "") 27 | `ifdef VERILATOR 28 | (input wire clk, 29 | input wire rst, 30 | input wire i_jtag_tck, 31 | input wire i_jtag_tms, 32 | input wire i_jtag_tdi, 33 | input wire i_jtag_trst_n, 34 | output wire o_jtag_tdo, 35 | output wire o_uart_tx, 36 | input wire [31:0] i_gpio, 37 | output wire [15:0] o_gpio) 38 | `endif 39 | ; 40 | 41 | localparam RAM_SIZE = 32'h100000; 42 | 43 | `ifndef VERILATOR 44 | reg clk = 1'b0; 45 | reg rst = 1'b1; 46 | always #10 clk <= !clk; 47 | initial #100 rst <= 1'b0; 48 | wire [31:0] i_gpio; 49 | wire [15:0] o_gpio; 50 | wire i_jtag_tck = 1'b0; 51 | wire i_jtag_tms = 1'b0; 52 | wire i_jtag_tdi = 1'b0; 53 | wire i_jtag_trst_n = 1'b0; 54 | wire o_jtag_tdo; 55 | wire o_uart_tx; 56 | 57 | uart_decoder #(115200) uart_decoder (o_uart_tx); 58 | 59 | `endif 60 | 61 | reg [1023:0] ram_init_file; 62 | 63 | initial begin 64 | if (|$test$plusargs("jtag_vpi_enable")) 65 | $display("JTAG VPI enabled. Not loading RAM"); 66 | else if ($value$plusargs("ram_init_file=%s", ram_init_file)) begin 67 | $display("Loading RAM contents from %0s", ram_init_file); 68 | $readmemh(ram_init_file, ram.mem); 69 | end 70 | end 71 | 72 | reg [1023:0] rom_init_file; 73 | 74 | initial begin 75 | if ($value$plusargs("rom_init_file=%s", rom_init_file)) begin 76 | $display("Loading ROM contents from %0s", rom_init_file); 77 | $readmemh(rom_init_file, veerwolf.bootrom.ram.mem); 78 | end else if (!(|bootrom_file)) begin 79 | /* 80 | Set mrac to 0xAAAA0000 and jump to address 0 81 | if no bootloader is selected 82 | 0: aaaa02b7 lui t0,0xaaaa0 83 | 4: 7c029073 csrw 0x7c0,t0 84 | 8: 00000067 jr zero 85 | */ 86 | veerwolf.bootrom.ram.mem[0] = 64'h7c029073aaaa02b7; 87 | veerwolf.bootrom.ram.mem[1] = 64'h0000000000000067; 88 | end 89 | end 90 | 91 | wire [63:0] gpio_out; 92 | assign o_gpio = gpio_out[15:0]; 93 | 94 | wire [5:0] ram_awid; 95 | wire [31:0] ram_awaddr; 96 | wire [7:0] ram_awlen; 97 | wire [2:0] ram_awsize; 98 | wire [1:0] ram_awburst; 99 | wire ram_awlock; 100 | wire [3:0] ram_awcache; 101 | wire [2:0] ram_awprot; 102 | wire [3:0] ram_awregion; 103 | wire [3:0] ram_awqos; 104 | wire ram_awvalid; 105 | wire ram_awready; 106 | wire [5:0] ram_arid; 107 | wire [31:0] ram_araddr; 108 | wire [7:0] ram_arlen; 109 | wire [2:0] ram_arsize; 110 | wire [1:0] ram_arburst; 111 | wire ram_arlock; 112 | wire [3:0] ram_arcache; 113 | wire [2:0] ram_arprot; 114 | wire [3:0] ram_arregion; 115 | wire [3:0] ram_arqos; 116 | wire ram_arvalid; 117 | wire ram_arready; 118 | wire [63:0] ram_wdata; 119 | wire [7:0] ram_wstrb; 120 | wire ram_wlast; 121 | wire ram_wvalid; 122 | wire ram_wready; 123 | wire [5:0] ram_bid; 124 | wire [1:0] ram_bresp; 125 | wire ram_bvalid; 126 | wire ram_bready; 127 | wire [5:0] ram_rid; 128 | wire [63:0] ram_rdata; 129 | wire [1:0] ram_rresp; 130 | wire ram_rlast; 131 | wire ram_rvalid; 132 | wire ram_rready; 133 | 134 | wire dmi_reg_en; 135 | wire [6:0] dmi_reg_addr; 136 | wire dmi_reg_wr_en; 137 | wire [31:0] dmi_reg_wdata; 138 | wire [31:0] dmi_reg_rdata; 139 | wire dmi_hard_reset; 140 | 141 | axi_ram 142 | #(.DATA_WIDTH (64), 143 | .ADDR_WIDTH ($clog2(RAM_SIZE)), 144 | .ID_WIDTH (6)) 145 | ram 146 | (.clk (clk), 147 | .rst (rst), 148 | .s_axi_awid (ram_awid), 149 | .s_axi_awaddr (ram_awaddr[$clog2(RAM_SIZE)-1:0]), 150 | .s_axi_awlen (ram_awlen), 151 | .s_axi_awsize (ram_awsize), 152 | .s_axi_awburst (ram_awburst), 153 | .s_axi_awlock (1'd0), 154 | .s_axi_awcache (4'd0), 155 | .s_axi_awprot (3'd0), 156 | .s_axi_awvalid (ram_awvalid), 157 | .s_axi_awready (ram_awready), 158 | 159 | .s_axi_arid (ram_arid), 160 | .s_axi_araddr (ram_araddr[$clog2(RAM_SIZE)-1:0]), 161 | .s_axi_arlen (ram_arlen), 162 | .s_axi_arsize (ram_arsize), 163 | .s_axi_arburst (ram_arburst), 164 | .s_axi_arlock (1'd0), 165 | .s_axi_arcache (4'd0), 166 | .s_axi_arprot (3'd0), 167 | .s_axi_arvalid (ram_arvalid), 168 | .s_axi_arready (ram_arready), 169 | 170 | .s_axi_wdata (ram_wdata), 171 | .s_axi_wstrb (ram_wstrb), 172 | .s_axi_wlast (ram_wlast), 173 | .s_axi_wvalid (ram_wvalid), 174 | .s_axi_wready (ram_wready), 175 | 176 | .s_axi_bid (ram_bid), 177 | .s_axi_bresp (ram_bresp), 178 | .s_axi_bvalid (ram_bvalid), 179 | .s_axi_bready (ram_bready), 180 | 181 | .s_axi_rid (ram_rid), 182 | .s_axi_rdata (ram_rdata), 183 | .s_axi_rresp (ram_rresp), 184 | .s_axi_rlast (ram_rlast), 185 | .s_axi_rvalid (ram_rvalid), 186 | .s_axi_rready (ram_rready)); 187 | 188 | dmi_wrapper dmi_wrapper 189 | (.trst_n (i_jtag_trst_n), 190 | .tck (i_jtag_tck), 191 | .tms (i_jtag_tms), 192 | .tdi (i_jtag_tdi), 193 | .tdo (o_jtag_tdo), 194 | .tdoEnable (), 195 | // Processor Signals 196 | .core_rst_n (!rst), 197 | .core_clk (clk), 198 | .jtag_id (31'd0), 199 | .rd_data (dmi_reg_rdata), 200 | .reg_wr_data (dmi_reg_wdata), 201 | .reg_wr_addr (dmi_reg_addr), 202 | .reg_en (dmi_reg_en), 203 | .reg_wr_en (dmi_reg_wr_en), 204 | .dmi_hard_reset (dmi_hard_reset)); 205 | 206 | veerwolf_core 207 | #(.bootrom_file (bootrom_file), 208 | .clk_freq_hz (32'd50_000_000)) 209 | veerwolf 210 | (.clk (clk), 211 | .rstn (!rst), 212 | .dmi_reg_rdata (dmi_reg_rdata), 213 | .dmi_reg_wdata (dmi_reg_wdata), 214 | .dmi_reg_addr (dmi_reg_addr), 215 | .dmi_reg_en (dmi_reg_en), 216 | .dmi_reg_wr_en (dmi_reg_wr_en), 217 | .dmi_hard_reset (dmi_hard_reset), 218 | .o_flash_sclk (), 219 | .o_flash_cs_n (), 220 | .o_flash_mosi (), 221 | .i_flash_miso (1'b0), 222 | .i_uart_rx (1'b1), 223 | .o_uart_tx (o_uart_tx), 224 | .o_ram_awid (ram_awid), 225 | .o_ram_awaddr (ram_awaddr), 226 | .o_ram_awlen (ram_awlen), 227 | .o_ram_awsize (ram_awsize), 228 | .o_ram_awburst (ram_awburst), 229 | .o_ram_awlock (ram_awlock), 230 | .o_ram_awcache (ram_awcache), 231 | .o_ram_awprot (ram_awprot), 232 | .o_ram_awregion (ram_awregion), 233 | .o_ram_awqos (ram_awqos), 234 | .o_ram_awvalid (ram_awvalid), 235 | .i_ram_awready (ram_awready), 236 | .o_ram_arid (ram_arid), 237 | .o_ram_araddr (ram_araddr), 238 | .o_ram_arlen (ram_arlen), 239 | .o_ram_arsize (ram_arsize), 240 | .o_ram_arburst (ram_arburst), 241 | .o_ram_arlock (ram_arlock), 242 | .o_ram_arcache (ram_arcache), 243 | .o_ram_arprot (ram_arprot), 244 | .o_ram_arregion (ram_arregion), 245 | .o_ram_arqos (ram_arqos), 246 | .o_ram_arvalid (ram_arvalid), 247 | .i_ram_arready (ram_arready), 248 | .o_ram_wdata (ram_wdata), 249 | .o_ram_wstrb (ram_wstrb), 250 | .o_ram_wlast (ram_wlast), 251 | .o_ram_wvalid (ram_wvalid), 252 | .i_ram_wready (ram_wready), 253 | .i_ram_bid (ram_bid), 254 | .i_ram_bresp (ram_bresp), 255 | .i_ram_bvalid (ram_bvalid), 256 | .o_ram_bready (ram_bready), 257 | .i_ram_rid (ram_rid), 258 | .i_ram_rdata (ram_rdata), 259 | .i_ram_rresp (ram_rresp), 260 | .i_ram_rlast (ram_rlast), 261 | .i_ram_rvalid (ram_rvalid), 262 | .o_ram_rready (ram_rready), 263 | .i_ram_init_done (1'b1), 264 | .i_ram_init_error (1'b0), 265 | .i_gpio ({32'd0, i_gpio}), 266 | .o_gpio (gpio_out)); 267 | 268 | endmodule 269 | -------------------------------------------------------------------------------- /tb/veerwolf_nexys_tb.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Verilog testbench for VeeRwolf for Nexys A7 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | `default_nettype none 25 | module veerwolf_nexys_tb 26 | #(parameter bootrom_file = "jumptoram.vh") 27 | ; 28 | 29 | localparam RAM_SIZE = 32'h10000; 30 | 31 | reg clk = 1'b0; 32 | reg rst = 1'b1; 33 | always #5 clk <= !clk; 34 | initial #100 rst <= 1'b0; 35 | wire o_gpio; 36 | 37 | reg [1023:0] ram_init_file; 38 | 39 | initial begin 40 | if ($value$plusargs("ram_init_file=%s", ram_init_file)) begin 41 | $display("Loading RAM contents from %0s", ram_init_file); 42 | $readmemh(ram_init_file, ram.ram.mem); 43 | end 44 | end 45 | 46 | reg [1023:0] rom_init_file; 47 | 48 | initial begin 49 | if ($value$plusargs("rom_init_file=%s", rom_init_file)) begin 50 | $display("Loading ROM contents from %0s", rom_init_file); 51 | $readmemh(rom_init_file, veerwolf.bootrom.ram.mem); 52 | end 53 | end 54 | 55 | veerwolf_nexys 56 | #(.bootrom_file (bootrom_file), 57 | .ram_init_file ("")) 58 | veerwolf 59 | (.clk (clk), 60 | .rstn (!rst), 61 | .ddram_a (), 62 | .ddram_ba (), 63 | .ddram_ras_n (), 64 | .ddram_cas_n (), 65 | .ddram_we_n (), 66 | .ddram_cs_n (), 67 | .ddram_dm (), 68 | .ddram_dq (16'dz), 69 | .ddram_dqs_p (), 70 | .ddram_dqs_n (), 71 | .ddram_clk_p (), 72 | .ddram_clk_n (), 73 | .ddram_cke (), 74 | .ddram_odt (), 75 | .o_serial_tx (serial), 76 | .i_serial_rx (1'b1), 77 | .led0 (), 78 | .led1 (), 79 | .led2 (), 80 | .led3 (), 81 | .led4 ()); 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /tb/veerwolf_spi_tb.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | //******************************************************************************** 17 | // $Id$ 18 | // 19 | // Function: Verilog testbench for VeeRwolf with SPI Flash 20 | // Comments: 21 | // 22 | //******************************************************************************** 23 | 24 | `default_nettype none 25 | module veerwolf_spi_tb 26 | #(parameter bootrom_file = "bootloader.vh", 27 | parameter flash_init_file = "hello.ubvh", 28 | parameter mem_clear = 0); 29 | 30 | localparam RAM_SIZE = 32'h10000; 31 | 32 | reg clk = 1'b0; 33 | reg rst = 1'b1; 34 | always #10 clk <= !clk; 35 | initial #100 rst <= 1'b0; 36 | wire [63:0] o_gpio; 37 | wire o_uart_tx; 38 | wire flash_sclk; 39 | wire flash_cs_n; 40 | wire flash_mosi; 41 | wire flash_miso; 42 | 43 | reg [1023:0] ram_init_file; 44 | 45 | initial begin 46 | if ($value$plusargs("ram_init_file=%s", ram_init_file)) begin 47 | $display("Loading RAM contents from %0s", ram_init_file); 48 | $readmemh(ram_init_file, ram.mem); 49 | end 50 | end 51 | 52 | reg [1023:0] rom_init_file; 53 | 54 | initial begin 55 | if ($value$plusargs("rom_init_file=%s", rom_init_file)) begin 56 | $display("Loading ROM contents from %0s", rom_init_file); 57 | $readmemh(rom_init_file, veerwolf.bootrom.ram.mem); 58 | end 59 | end 60 | 61 | wire [5:0] ram_awid; 62 | wire [31:0] ram_awaddr; 63 | wire [7:0] ram_awlen; 64 | wire [2:0] ram_awsize; 65 | wire [1:0] ram_awburst; 66 | wire ram_awlock; 67 | wire [3:0] ram_awcache; 68 | wire [2:0] ram_awprot; 69 | wire [3:0] ram_awregion; 70 | wire [3:0] ram_awqos; 71 | wire ram_awvalid; 72 | wire ram_awready; 73 | wire [5:0] ram_arid; 74 | wire [31:0] ram_araddr; 75 | wire [7:0] ram_arlen; 76 | wire [2:0] ram_arsize; 77 | wire [1:0] ram_arburst; 78 | wire ram_arlock; 79 | wire [3:0] ram_arcache; 80 | wire [2:0] ram_arprot; 81 | wire [3:0] ram_arregion; 82 | wire [3:0] ram_arqos; 83 | wire ram_arvalid; 84 | wire ram_arready; 85 | wire [63:0] ram_wdata; 86 | wire [7:0] ram_wstrb; 87 | wire ram_wlast; 88 | wire ram_wvalid; 89 | wire ram_wready; 90 | wire [5:0] ram_bid; 91 | wire [1:0] ram_bresp; 92 | wire ram_bvalid; 93 | wire ram_bready; 94 | wire [5:0] ram_rid; 95 | wire [63:0] ram_rdata; 96 | wire [1:0] ram_rresp; 97 | wire ram_rlast; 98 | wire ram_rvalid; 99 | wire ram_rready; 100 | 101 | axi_ram 102 | #(.DATA_WIDTH (64), 103 | .ADDR_WIDTH ($clog2(RAM_SIZE)), 104 | .ID_WIDTH (`RV_LSU_BUS_TAG+2)) 105 | ram 106 | (.clk (clk), 107 | .rst (rst), 108 | .s_axi_awid (ram_awid), 109 | .s_axi_awaddr (ram_awaddr[$clog2(RAM_SIZE)-1:0]), 110 | .s_axi_awlen (ram_awlen), 111 | .s_axi_awsize (ram_awsize), 112 | .s_axi_awburst (ram_awburst), 113 | .s_axi_awlock (1'd0), 114 | .s_axi_awcache (4'd0), 115 | .s_axi_awprot (3'd0), 116 | .s_axi_awvalid (ram_awvalid), 117 | .s_axi_awready (ram_awready), 118 | 119 | .s_axi_arid (ram_arid), 120 | .s_axi_araddr (ram_araddr[$clog2(RAM_SIZE)-1:0]), 121 | .s_axi_arlen (ram_arlen), 122 | .s_axi_arsize (ram_arsize), 123 | .s_axi_arburst (ram_arburst), 124 | .s_axi_arlock (1'd0), 125 | .s_axi_arcache (4'd0), 126 | .s_axi_arprot (3'd0), 127 | .s_axi_arvalid (ram_arvalid), 128 | .s_axi_arready (ram_arready), 129 | 130 | .s_axi_wdata (ram_wdata), 131 | .s_axi_wstrb (ram_wstrb), 132 | .s_axi_wlast (ram_wlast), 133 | .s_axi_wvalid (ram_wvalid), 134 | .s_axi_wready (ram_wready), 135 | 136 | .s_axi_bid (ram_bid), 137 | .s_axi_bresp (ram_bresp), 138 | .s_axi_bvalid (ram_bvalid), 139 | .s_axi_bready (ram_bready), 140 | 141 | .s_axi_rid (ram_rid), 142 | .s_axi_rdata (ram_rdata), 143 | .s_axi_rresp (ram_rresp), 144 | .s_axi_rlast (ram_rlast), 145 | .s_axi_rvalid (ram_rvalid), 146 | .s_axi_rready (ram_rready)); 147 | 148 | uart_decoder #(115200) uart_decoder (o_uart_tx); 149 | 150 | reg flash_cs_n_r; 151 | 152 | //Deglitch flash_cs_n 153 | always @(posedge clk) 154 | flash_cs_n_r <= flash_cs_n; 155 | 156 | s25fl128s 157 | #(.mem_file_name (flash_init_file), 158 | .AddrRANGE (24'h0000FF)) 159 | flash 160 | ( 161 | .SCK (flash_sclk), 162 | .SI (flash_mosi), 163 | .CSNeg (flash_cs_n_r), 164 | .HOLDNeg (), //Internal pull-up 165 | .WPNeg (), //Internal pull-up 166 | .SO (flash_miso), 167 | .RSTNeg (1'b1)); 168 | 169 | veerwolf_core 170 | #(.bootrom_file (bootrom_file), 171 | .clk_freq_hz (32'd50_000_000)) 172 | veerwolf 173 | (.clk (clk), 174 | .rstn (!rst), 175 | .dmi_reg_rdata (), 176 | .dmi_reg_wdata (32'd0), 177 | .dmi_reg_addr (7'd0), 178 | .dmi_reg_en (1'b0), 179 | .dmi_reg_wr_en (1'b0), 180 | .dmi_hard_reset (1'b0), 181 | .o_flash_sclk (flash_sclk), 182 | .o_flash_cs_n (flash_cs_n), 183 | .o_flash_mosi (flash_mosi), 184 | .i_flash_miso (flash_miso), 185 | .i_uart_rx (1'b1), 186 | .o_uart_tx (o_uart_tx), 187 | .o_ram_awid (ram_awid), 188 | .o_ram_awaddr (ram_awaddr), 189 | .o_ram_awlen (ram_awlen), 190 | .o_ram_awsize (ram_awsize), 191 | .o_ram_awburst (ram_awburst), 192 | .o_ram_awlock (ram_awlock), 193 | .o_ram_awcache (ram_awcache), 194 | .o_ram_awprot (ram_awprot), 195 | .o_ram_awregion (ram_awregion), 196 | .o_ram_awqos (ram_awqos), 197 | .o_ram_awvalid (ram_awvalid), 198 | .i_ram_awready (ram_awready), 199 | .o_ram_arid (ram_arid), 200 | .o_ram_araddr (ram_araddr), 201 | .o_ram_arlen (ram_arlen), 202 | .o_ram_arsize (ram_arsize), 203 | .o_ram_arburst (ram_arburst), 204 | .o_ram_arlock (ram_arlock), 205 | .o_ram_arcache (ram_arcache), 206 | .o_ram_arprot (ram_arprot), 207 | .o_ram_arregion (ram_arregion), 208 | .o_ram_arqos (ram_arqos), 209 | .o_ram_arvalid (ram_arvalid), 210 | .i_ram_arready (ram_arready), 211 | .o_ram_wdata (ram_wdata), 212 | .o_ram_wstrb (ram_wstrb), 213 | .o_ram_wlast (ram_wlast), 214 | .o_ram_wvalid (ram_wvalid), 215 | .i_ram_wready (ram_wready), 216 | .i_ram_bid (ram_bid), 217 | .i_ram_bresp (ram_bresp), 218 | .i_ram_bvalid (ram_bvalid), 219 | .o_ram_bready (ram_bready), 220 | .i_ram_rid (ram_rid), 221 | .i_ram_rdata (ram_rdata), 222 | .i_ram_rresp (ram_rresp), 223 | .i_ram_rlast (ram_rlast), 224 | .i_ram_rvalid (ram_rvalid), 225 | .o_ram_rready (ram_rready), 226 | .i_ram_init_done (1'b1), 227 | .i_ram_init_error (1'b0), 228 | .i_gpio (64'd0), 229 | .o_gpio (o_gpio)); 230 | 231 | endmodule 232 | -------------------------------------------------------------------------------- /veerwolf_basys3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/VeeRwolf/9a91980562fcaadd748404af05d2a23361632378/veerwolf_basys3.png -------------------------------------------------------------------------------- /veerwolf_core.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/VeeRwolf/9a91980562fcaadd748404af05d2a23361632378/veerwolf_core.png -------------------------------------------------------------------------------- /veerwolf_irq.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/VeeRwolf/9a91980562fcaadd748404af05d2a23361632378/veerwolf_irq.png -------------------------------------------------------------------------------- /veerwolf_nexys.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/VeeRwolf/9a91980562fcaadd748404af05d2a23361632378/veerwolf_nexys.png -------------------------------------------------------------------------------- /veerwolf_sim.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/VeeRwolf/9a91980562fcaadd748404af05d2a23361632378/veerwolf_sim.png -------------------------------------------------------------------------------- /west.yml: -------------------------------------------------------------------------------- 1 | manifest: 2 | remotes: 3 | - name: zephyrproject-rtos 4 | url-base: https://github.com/zephyrproject-rtos 5 | projects: 6 | - name: zephyr 7 | remote: zephyrproject-rtos 8 | revision: v2.7.4 9 | import: true 10 | -------------------------------------------------------------------------------- /zephyr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Olof Kindgren 2 | # 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | add_subdirectory(drivers) 6 | -------------------------------------------------------------------------------- /zephyr/Kconfig: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Olof Kindgren 2 | # 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | menu "VeeRwolf" 6 | 7 | rsource "drivers/Kconfig" 8 | 9 | endmenu 10 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) 2 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/Kconfig.board: -------------------------------------------------------------------------------- 1 | config BOARD_VEERWOLF_NEXYS 2 | bool "VeeRwolf for Nexys A7" 3 | depends on SOC_RISCV32_VEERWOLF 4 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/Kconfig.defconfig: -------------------------------------------------------------------------------- 1 | 2 | config BOARD 3 | default "veerwolf_nexys" 4 | depends on BOARD_VEERWOLF_NEXYS 5 | if FLASH 6 | 7 | config SPI_NOR 8 | def_bool y 9 | 10 | endif 11 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/board.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018 Antmicro 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef __INC_BOARD_H 8 | #define __INC_BOARD_H 9 | 10 | #include 11 | 12 | 13 | 14 | #endif /* __INC_BOARD_H */ 15 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/veerwolf_nexys.dts: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | /dts-v1/; 4 | 5 | #include 6 | 7 | / { 8 | model = "ChipsAlliance Veerwolf-Nexys"; 9 | compatible = "ChipsAlliance,Veerwolf-Nexys"; 10 | aliases { 11 | led0 = &led_0; 12 | }; 13 | 14 | chosen { 15 | zephyr,console = &uart0; 16 | zephyr,shell-uart = &uart0; 17 | zephyr,sram = &sram; 18 | }; 19 | 20 | sram: memory@0 { 21 | compatible = "mmio-sram"; 22 | reg = <0x00000000 0x00800000>; 23 | }; 24 | leds { 25 | compatible = "gpio-leds"; 26 | led_0: led { 27 | gpios = <&gpio_led0 0 GPIO_ACTIVE_HIGH>; 28 | label = "Red LED"; 29 | }; 30 | }; 31 | 32 | }; 33 | 34 | &gpio_led0 { 35 | status = "okay"; 36 | }; 37 | &uart0 { 38 | status = "okay"; 39 | current-speed = <115200>; 40 | clock-frequency = <50000000>; 41 | }; 42 | 43 | &spi0 { 44 | status = "okay"; 45 | 46 | flash0: flash@0 { 47 | compatible = "jedec,spi-nor"; 48 | label = "FLASH0"; 49 | jedec-id = [01 20 18]; 50 | size = <0x1000000>; 51 | reg = <0>; 52 | spi-max-frequency = <2000000>; 53 | }; 54 | }; 55 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/veerwolf_nexys.yaml: -------------------------------------------------------------------------------- 1 | identifier: veerwolf_nexys 2 | name: VeeRwolf for Nexys A7 3 | type: mcu 4 | arch: riscv32 5 | toolchain: 6 | - zephyr 7 | ram: 128 8 | testing: 9 | ignore_tags: 10 | - net 11 | - bluetooth 12 | -------------------------------------------------------------------------------- /zephyr/boards/riscv/veerwolf_nexys/veerwolf_nexys_defconfig: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2020 Olof Kindgren 3 | # 4 | # SPDX-License-Identifier: Apache-2.0 5 | # 6 | 7 | CONFIG_SOC_RISCV32_VEERWOLF=y 8 | CONFIG_BOARD_VEERWOLF_NEXYS=y 9 | CONFIG_CONSOLE=y 10 | CONFIG_SERIAL=y 11 | 12 | CONFIG_GPIO_VEERWOLF=y 13 | CONFIG_UART_CONSOLE=y 14 | CONFIG_PLIC=n 15 | CONFIG_XIP=n 16 | CONFIG_BOOT_BANNER=y 17 | CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 18 | -------------------------------------------------------------------------------- /zephyr/drivers/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Olof Kindgren 2 | # 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | add_subdirectory_ifdef(CONFIG_GPIO gpio) 6 | -------------------------------------------------------------------------------- /zephyr/drivers/Kconfig: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Olof Kindgren 2 | # 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | menu "Device Drivers" 6 | 7 | rsource "gpio/Kconfig" 8 | 9 | endmenu 10 | -------------------------------------------------------------------------------- /zephyr/drivers/gpio/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Olof Kindgren 2 | # 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | set(ZEPHYR_CURRENT_LIBRARY drivers__gpio) 6 | 7 | zephyr_library_sources_ifdef(CONFIG_GPIO_VEERWOLF gpio_veerwolf.c) 8 | 9 | -------------------------------------------------------------------------------- /zephyr/drivers/gpio/Kconfig: -------------------------------------------------------------------------------- 1 | # VeeRwolf GPIO configuration options 2 | 3 | # Copyright (c) 2020 Olof Kindgren 4 | # SPDX-License-Identifier: Apache-2.0 5 | 6 | config GPIO_VEERWOLF 7 | bool "VeeRwolf GPIO driver" 8 | select GPIO 9 | depends on SOC_RISCV32_VEERWOLF 10 | help 11 | Enable VeeRwolf GPIO driver. 12 | -------------------------------------------------------------------------------- /zephyr/drivers/gpio/gpio_veerwolf.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2020 Olof Kindgren 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #define DT_DRV_COMPAT veerwolf_gpio 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | #define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL 18 | LOG_MODULE_REGISTER(gpio_veerwolf); 19 | 20 | struct gpio_veerwolf_cfg { 21 | volatile uint32_t *reg_addr; 22 | int nr_gpios; 23 | bool port_is_output; 24 | }; 25 | 26 | struct gpio_veerwolf_data { 27 | struct gpio_driver_data common; 28 | }; 29 | 30 | /* Helper macros for GPIO */ 31 | 32 | #define DEV_GPIO_CFG(dev) \ 33 | ((const struct gpio_veerwolf_cfg *)(dev)->config) 34 | 35 | #define DEV_GPIO_ADDR(dev) \ 36 | ((mem_addr_t)DEV_GPIO_CFG(dev)->reg_addr) 37 | 38 | /* Driver functions */ 39 | 40 | static int gpio_veerwolf_init(const struct device *dev) 41 | { 42 | return 0; 43 | } 44 | 45 | static int gpio_veerwolf_configure(const struct device *dev, 46 | gpio_pin_t pin, gpio_flags_t flags) 47 | { 48 | return 0; 49 | } 50 | 51 | static int gpio_veerwolf_port_get_raw(const struct device *dev, 52 | gpio_port_value_t *value) 53 | { 54 | mem_addr_t addr = DEV_GPIO_ADDR(dev); 55 | 56 | *value = sys_read32(addr); 57 | return 0; 58 | } 59 | 60 | static int gpio_veerwolf_port_set_masked_raw(const struct device *dev, 61 | gpio_port_pins_t mask, 62 | gpio_port_value_t value) 63 | { 64 | mem_addr_t addr = DEV_GPIO_ADDR(dev); 65 | uint32_t port_val; 66 | 67 | port_val = sys_read32(addr); 68 | port_val = (port_val & ~mask) | (value & mask); 69 | sys_write32(port_val, addr); 70 | 71 | return 0; 72 | } 73 | 74 | static int gpio_veerwolf_port_set_bits_raw(const struct device *dev, 75 | gpio_port_pins_t pins) 76 | { 77 | mem_addr_t addr = DEV_GPIO_ADDR(dev); 78 | uint32_t port_val; 79 | 80 | port_val = sys_read32(addr) | pins; 81 | sys_write32(port_val, addr); 82 | 83 | return 0; 84 | } 85 | 86 | static int gpio_veerwolf_port_clear_bits_raw(const struct device *dev, 87 | gpio_port_pins_t pins) 88 | { 89 | mem_addr_t addr = DEV_GPIO_ADDR(dev); 90 | uint32_t port_val; 91 | 92 | port_val = sys_read32(addr) & ~pins; 93 | sys_write32(port_val, addr); 94 | 95 | return 0; 96 | } 97 | 98 | static int gpio_veerwolf_port_toggle_bits(const struct device *dev, 99 | gpio_port_pins_t pins) 100 | { 101 | mem_addr_t addr = DEV_GPIO_ADDR(dev); 102 | uint32_t port_val; 103 | 104 | port_val = sys_read32(addr) ^ pins; 105 | sys_write32(port_val, addr); 106 | 107 | return 0; 108 | } 109 | 110 | static int gpio_veerwolf_pin_interrupt_configure(const struct device *dev, 111 | gpio_pin_t pin, 112 | enum gpio_int_mode mode, 113 | enum gpio_int_trig trig) 114 | { 115 | int ret = 0; 116 | 117 | if (mode != GPIO_INT_MODE_DISABLED) { 118 | ret = -ENOTSUP; 119 | } 120 | return ret; 121 | } 122 | 123 | static const struct gpio_driver_api gpio_veerwolf_driver_api = { 124 | .pin_configure = gpio_veerwolf_configure, 125 | .port_get_raw = gpio_veerwolf_port_get_raw, 126 | .port_set_masked_raw = gpio_veerwolf_port_set_masked_raw, 127 | .port_set_bits_raw = gpio_veerwolf_port_set_bits_raw, 128 | .port_clear_bits_raw = gpio_veerwolf_port_clear_bits_raw, 129 | .port_toggle_bits = gpio_veerwolf_port_toggle_bits, 130 | .pin_interrupt_configure = gpio_veerwolf_pin_interrupt_configure, 131 | }; 132 | 133 | /* Device Instantiation */ 134 | 135 | #define GPIO_VEERWOLF_INIT(n) \ 136 | static const struct gpio_veerwolf_cfg gpio_veerwolf_cfg_##n = { \ 137 | .reg_addr = \ 138 | (volatile uint32_t *) DT_INST_REG_ADDR(n), \ 139 | .nr_gpios = DT_INST_PROP(n, ngpios), \ 140 | }; \ 141 | static struct gpio_veerwolf_data gpio_veerwolf_data_##n; \ 142 | \ 143 | DEVICE_DEFINE(veerwolf_gpio_##n, \ 144 | DT_INST_LABEL(n), \ 145 | gpio_veerwolf_init, \ 146 | NULL, \ 147 | &gpio_veerwolf_data_##n, \ 148 | &gpio_veerwolf_cfg_##n, \ 149 | POST_KERNEL, \ 150 | CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ 151 | &gpio_veerwolf_driver_api \ 152 | ); 153 | 154 | DT_INST_FOREACH_STATUS_OKAY(GPIO_VEERWOLF_INIT) 155 | -------------------------------------------------------------------------------- /zephyr/dts/bindings/gpio/veerwolf,gpio.yaml: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2020 Olof Kindgren 3 | # 4 | # SPDX-License-Identifier: Apache-2.0 5 | # 6 | 7 | description: VeeRwolf GPIO 8 | 9 | compatible: "veerwolf,gpio" 10 | 11 | include: [gpio-controller.yaml, base.yaml] 12 | 13 | properties: 14 | reg: 15 | required: true 16 | 17 | label: 18 | required: true 19 | 20 | ngpios: 21 | required: true 22 | 23 | "#gpio-cells": 24 | const: 2 25 | 26 | gpio-cells: 27 | - pin 28 | - flags 29 | -------------------------------------------------------------------------------- /zephyr/dts/riscv/riscv32-veer.dtsi: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: Apache-2.0 */ 2 | 3 | #include 4 | 5 | / { 6 | #address-cells = <1>; 7 | #size-cells = <1>; 8 | compatible = "ChipsAlliance,VeeRwolf-dev"; 9 | model = "ChipsAlliance,VeeRwolf"; 10 | cpus { 11 | #address-cells = <1>; 12 | #size-cells = <0>; 13 | cpu@0 { 14 | clock-frequency = <0>; 15 | compatible = "ChipsAlliance,VeeR-EH1-v1.2", "riscv"; 16 | device_type = "cpu"; 17 | reg = <0>; 18 | riscv,isa = "rv32imac"; 19 | status = "okay"; 20 | timebase-frequency = <32768>; 21 | }; 22 | }; 23 | soc { 24 | #address-cells = <1>; 25 | #size-cells = <1>; 26 | compatible = "ChipsAlliance,VeeRwolf-soc", "simple-bus"; 27 | ranges; 28 | 29 | pic: interrupt-controller@f00c0000 { 30 | #interrupt-cells = <2>; 31 | compatible = "swerv,pic"; 32 | interrupt-controller; 33 | reg = <0xf00c0000 0x2000>; 34 | reg-names = "reg"; 35 | riscv,max-priority = <15>; 36 | }; 37 | 38 | uart0: uart@80002000 { 39 | compatible = "ns16550"; 40 | clock-frequency = <50000000>; 41 | reg = <0x80002000 0x1000>; 42 | reg-names = "control"; 43 | label = "uart0"; 44 | interrupt-parent = <&pic>; 45 | interrupts = <12 15>; 46 | status = "disabled"; 47 | }; 48 | 49 | spi0: spi@80001040 { 50 | compatible = "opencores,spi-simple"; 51 | reg = <0x80001040 0x40>; 52 | reg-names = "control"; 53 | label = "SPI0"; 54 | status = "disabled"; 55 | #address-cells = <1>; 56 | #size-cells = <0>; 57 | }; 58 | gpio_led0: gpio@80001010 { 59 | compatible = "veerwolf,gpio"; 60 | reg = <0x80001010 0x10>; 61 | gpio-controller; 62 | #gpio-cells = <2>; 63 | ngpios = <32>; 64 | label = "LED0"; 65 | }; 66 | 67 | }; 68 | }; 69 | -------------------------------------------------------------------------------- /zephyr/module.yml: -------------------------------------------------------------------------------- 1 | build: 2 | settings: 3 | board_root: zephyr 4 | dts_root: zephyr 5 | soc_root: zephyr 6 | arch_root: zephyr 7 | -------------------------------------------------------------------------------- /zephyr/soc/Kconfig: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | choice 4 | prompt "SoC/CPU/Configuration Selection" 5 | 6 | source "$(SOC_DIR)/$(ARCH)/*/Kconfig.soc" 7 | 8 | endchoice 9 | 10 | menu "Hardware Configuration" 11 | osource "$(SOC_DIR)/$(ARCH)/Kconfig" 12 | osource "$(SOC_DIR)/$(ARCH)/*/Kconfig" 13 | 14 | 15 | module = SOC 16 | module-str = SOC 17 | source "subsys/logging/Kconfig.template.log_config" 18 | 19 | endmenu 20 | 21 | # The helper symbols below are put here due to an unusual setup: The simulated 22 | # nrf52_bsim board uses the POSIX arch, but is compatible with Nordic ARM 23 | # boards 24 | 25 | config SOC_COMPATIBLE_NRF 26 | bool 27 | 28 | config SOC_COMPATIBLE_NRF52X 29 | bool 30 | 31 | config SOC_COMPATIBLE_NRF52832 32 | bool 33 | 34 | # 35 | # SOC_*_LD: SoC specific Linker script additions 36 | # 37 | 38 | if ARC || ARM || X86 || NIOS2 || RISCV 39 | 40 | config SOC_NOINIT_LD 41 | bool 42 | help 43 | Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. 44 | Include an SoC specific linker script fragment named soc-noinit.ld 45 | for inserting additional data and linker directives into 46 | the noinit section. 47 | 48 | This only has effect if the SoC uses the common linker script 49 | under include/arch/. 50 | 51 | config SOC_RODATA_LD 52 | bool 53 | help 54 | Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. 55 | Include an SoC specific linker script fragment named soc-rodata.ld 56 | for inserting additional data and linker directives into 57 | the rodata section. 58 | 59 | This only has effect if the SoC uses the common linker script 60 | under include/arch/. 61 | 62 | config SOC_RWDATA_LD 63 | bool 64 | help 65 | Note: This is deprecated, use Cmake function zephyr_linker_sources() instead. 66 | Include an SoC specific linker script fragment named soc-rwdata.ld 67 | for inserting additional data and linker directives into 68 | the data section. 69 | 70 | This only has effect if the SoC uses the common linker script 71 | under include/arch/. 72 | 73 | endif # ARC || ARM || X86 || NIOS2 || RISCV 74 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | zephyr_sources( 2 | soc_irq.S 3 | vector.S 4 | irq.c 5 | soc.c) 6 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/Kconfig.defconfig: -------------------------------------------------------------------------------- 1 | if SOC_RISCV32_VEERWOLF 2 | 3 | config SOC 4 | def_string "veerwolf" 5 | 6 | #Not used but must be defined 7 | config SYS_CLOCK_HW_CYCLES_PER_SEC 8 | def_int 50000000 9 | 10 | config TIMER_READS_ITS_FREQUENCY_AT_RUNTIME 11 | def_bool y 12 | 13 | config RISCV_SOC_INTERRUPT_INIT 14 | def_bool y 15 | 16 | config RISCV_HAS_CPU_IDLE 17 | def_bool n 18 | 19 | config RISCV_HAS_PLIC 20 | def_bool n 21 | 22 | config SWERV_PIC 23 | def_bool y 24 | 25 | config NUM_IRQS 26 | def_int 64 27 | 28 | if SERIAL 29 | 30 | config UART_NS16550 31 | def_bool y 32 | 33 | config UART_NS16550_PORT_0 34 | def_bool y 35 | 36 | endif # SERIAL 37 | 38 | if GPIO 39 | 40 | config GPIO_MMIO32 41 | def_bool y 42 | 43 | endif # GPIO 44 | 45 | if SPI 46 | 47 | config SPI_OC_SIMPLE 48 | def_bool y 49 | 50 | config SPI_OC_SIMPLE_BUS_WIDTH 51 | def_int 64 52 | 53 | endif # SPI 54 | 55 | config XIP 56 | def_bool n 57 | 58 | config RISCV_MACHINE_TIMER 59 | def_bool y 60 | 61 | config RISCV_ROM_BASE_ADDR 62 | def_hex 0x00000000 63 | 64 | config RISCV_ROM_SIZE 65 | def_hex 0x0 66 | 67 | endif # SOC_RISCV32_VEERWOLF 68 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/Kconfig.soc: -------------------------------------------------------------------------------- 1 | config SOC_RISCV32_VEERWOLF 2 | bool "VeeRwolf - VeeR EH1-based SoC" 3 | select RISCV 4 | select ATOMIC_OPERATIONS_C 5 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/dts_fixup.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019 Western Digital Corporation or its affiliates 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | /* UART 0 */ 8 | #define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80002000_BASE_ADDRESS 9 | #define DT_UART_NS16550_PORT_0_CURRENT_SPEED DT_NS16550_80002000_CURRENT_SPEED 10 | #define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_80002000_IRQ_0 11 | #define DT_UART_NS16550_PORT_0_LABEL DT_NS16550_80002000_LABEL 12 | #define DT_UART_NS16550_PORT_0_SIZE DT_NS16550_80002000_SIZE 13 | #define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80002000_CLOCK_FREQUENCY 14 | #define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80002000_LABEL 15 | #define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80002000_CURRENT_SPEED 16 | 17 | 18 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/irq.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017 Jean-Paul Etienne 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | /** 8 | * @file 9 | * @brief interrupt management code for riscv SOCs supporting the riscv 10 | privileged architecture specification 11 | */ 12 | #include 13 | 14 | #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) 15 | void soc_interrupt_init(void) 16 | { 17 | /* ensure that all interrupts are disabled */ 18 | (void)irq_lock(); 19 | 20 | __asm__ volatile ("csrwi mie, 0\n" 21 | "csrwi mip, 0\n"); 22 | } 23 | #endif 24 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/linker.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018 Antmicro 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #include 8 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/soc.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019 Western Digital Corporation or its affiliates 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #include 8 | #include "soc.h" 9 | 10 | GPIO_MMIO32_INIT(DT_ALIAS(led0), 11 | DT_ALIAS_LED0_GPIOS_ADDRESS, 12 | DT_ALIAS_LED0_GPIOS_MASK); 13 | 14 | /* The VeeRwolf SoC can run at various CPU clock frequencies depending on which 15 | CPU is used and which hardware it runs on. The actual clock frequency is 16 | stored at synthesis time in register 0x8000103C. This value is used to set 17 | e.g. timer frequency but unfortunately the Zephyr UART driver does not handle 18 | dynamic clock frequencies and instead always reads the value from the device 19 | tree. 20 | 21 | This function works around this by setting a baud rate based on the actual 22 | clock frequency after the UART driver has initialized. This however has the 23 | limitation that the UART base address (and clock freq reg) is hard-coded. 24 | Long-term solution is to fix this limitation in the Zephyr UART driver. 25 | */ 26 | static int fix_baud_rate(const struct device *arg) 27 | { 28 | ARG_UNUSED(arg); 29 | 30 | uint32_t divisor; /* baud rate divisor */ 31 | uint8_t lcr_cache; 32 | 33 | uint32_t UART_BASE = 0x80002000; 34 | uint32_t REG_LCR = UART_BASE+4*3; 35 | uint8_t LCR_DLAB = 0x80; 36 | uint32_t REG_BRDL = UART_BASE+4*0; 37 | uint32_t REG_BRDH = UART_BASE+4*1; 38 | uint32_t baud_rate = DT_PROP(DT_PATH(soc, uart_80002000), current_speed); 39 | uint32_t sys_clk_freq = sys_read32(0x8000103c); 40 | 41 | /* 42 | * calculate baud rate divisor. a variant of 43 | * (uint32_t)(dev_cfg->sys_clk_freq / (16.0 * baud_rate) + 0.5) 44 | */ 45 | divisor = ((sys_clk_freq + (baud_rate << 3)) 46 | / baud_rate) >> 4; 47 | 48 | /* set the DLAB to access the baud rate divisor registers */ 49 | lcr_cache = sys_read8(REG_LCR); 50 | sys_write8(lcr_cache | LCR_DLAB, REG_LCR); 51 | sys_write8( divisor & 0xff, REG_BRDL); 52 | sys_write8((divisor >> 8) & 0xff, REG_BRDH); 53 | 54 | sys_write8(lcr_cache, REG_LCR); 55 | 56 | return 0; 57 | } 58 | 59 | SYS_INIT(fix_baud_rate, POST_KERNEL, 0); 60 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/soc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019 Western Digital Corporation or its affiliates 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef __RISCV32_VEERWOLF_SOC_H_ 8 | #define __RISCV32_VEERWOLF_SOC_H_ 9 | 10 | #include "soc_common.h" 11 | #include 12 | 13 | #define DT_ALIAS_LED0_GPIOS_CONTROLLER "LED0" 14 | #define DT_ALIAS_LED0_GPIOS_PIN 0 15 | #define DT_ALIAS_LED0_GPIOS_ADDRESS 0x80001010 16 | #define DT_ALIAS_LED0_GPIOS_MASK 0x00000001 17 | 18 | #define RISCV_MTIME_BASE 0x80001020 19 | #define RISCV_MTIMECMP_BASE 0x80001028 20 | 21 | /* lib-c hooks required RAM defined variables */ 22 | #define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS 23 | #define RISCV_RAM_SIZE KB(DT_SRAM_SIZE) 24 | 25 | #endif /* __RISCV32_SERV_SOC_H_ */ 26 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/soc_common.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017 Jean-Paul Etienne 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | /** 8 | * @file configuration macros for riscv SOCs supporting the riscv 9 | * privileged architecture specification 10 | */ 11 | 12 | #ifndef __SOC_COMMON_H_ 13 | #define __SOC_COMMON_H_ 14 | 15 | /* IRQ numbers */ 16 | #define RISCV_MACHINE_SOFT_IRQ 3 /* Machine Software Interrupt */ 17 | #define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */ 18 | #define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */ 19 | 20 | #define RISCV_MAX_GENERIC_IRQ 11 /* Max Generic Interrupt */ 21 | 22 | /* Exception numbers */ 23 | #define RISCV_MACHINE_ECALL_EXP 11 /* Machine ECALL instruction */ 24 | 25 | /* 26 | * SOC-specific MSTATUS related info 27 | */ 28 | /* MSTATUS register to save/restore upon interrupt/exception/context switch */ 29 | #define SOC_MSTATUS_REG mstatus 30 | 31 | #define SOC_MSTATUS_IEN (1 << 3) /* Machine Interrupt Enable bit */ 32 | 33 | /* Previous Privilege Mode - Machine Mode */ 34 | #define SOC_MSTATUS_MPP_M_MODE (3 << 11) 35 | /* Interrupt Enable Bit in Previous Privilege Mode */ 36 | #define SOC_MSTATUS_MPIE (1 << 7) 37 | 38 | /* 39 | * Default MSTATUS register value to restore from stack 40 | * upon scheduling a thread for the first time 41 | */ 42 | #define SOC_MSTATUS_DEF_RESTORE (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE) 43 | 44 | 45 | /* SOC-specific MCAUSE bitfields */ 46 | #ifdef CONFIG_64BIT 47 | /* Interrupt Mask */ 48 | #define SOC_MCAUSE_IRQ_MASK (1 << 63) 49 | /* Exception code Mask */ 50 | #define SOC_MCAUSE_EXP_MASK 0x7FFFFFFFFFFFFFFF 51 | #else 52 | /* Interrupt Mask */ 53 | #define SOC_MCAUSE_IRQ_MASK (1 << 31) 54 | /* Exception code Mask */ 55 | #define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF 56 | #endif 57 | /* ECALL exception number */ 58 | #define SOC_MCAUSE_ECALL_EXP RISCV_MACHINE_ECALL_EXP 59 | 60 | /* SOC-Specific EXIT ISR command */ 61 | #define SOC_ERET mret 62 | 63 | #ifndef _ASMLANGUAGE 64 | 65 | #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) 66 | void soc_interrupt_init(void); 67 | #endif 68 | 69 | #if defined(CONFIG_RISCV_HAS_PLIC) 70 | void riscv_plic_irq_enable(u32_t irq); 71 | void riscv_plic_irq_disable(u32_t irq); 72 | int riscv_plic_irq_is_enabled(u32_t irq); 73 | void riscv_plic_set_priority(u32_t irq, u32_t priority); 74 | int riscv_plic_get_irq(void); 75 | #endif 76 | 77 | #endif /* !_ASMLANGUAGE */ 78 | 79 | #endif /* __SOC_COMMON_H_ */ 80 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/soc_irq.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017 Jean-Paul Etienne 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | /* 8 | * common interrupt management code for riscv SOCs supporting the riscv 9 | * privileged architecture specification 10 | */ 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | /* exports */ 18 | GTEXT(__soc_handle_irq) 19 | 20 | /* 21 | * SOC-specific function to handle pending IRQ number generating the interrupt. 22 | * Exception number is given as parameter via register a0. 23 | */ 24 | SECTION_FUNC(exception.other, __soc_handle_irq) 25 | /* Clear exception number from CSR mip register */ 26 | li t1, 1 27 | sll t0, t1, a0 28 | csrrc t1, mip, t0 29 | 30 | /* Return */ 31 | jalr x0, ra 32 | 33 | /* 34 | * __soc_is_irq is defined as .weak to allow re-implementation by 35 | * SOCs that does not truly follow the riscv privilege specification. 36 | */ 37 | WTEXT(__soc_is_irq) 38 | 39 | /* 40 | * SOC-specific function to determine if the exception is the result of a 41 | * an interrupt or an exception 42 | * return 1 (interrupt) or 0 (exception) 43 | * 44 | */ 45 | SECTION_FUNC(exception.other, __soc_is_irq) 46 | /* Read mcause and check if interrupt bit is set */ 47 | csrr t0, mcause 48 | li t1, SOC_MCAUSE_IRQ_MASK 49 | and t0, t0, t1 50 | 51 | /* If interrupt bit is not set, return with 0 */ 52 | addi a0, x0, 0 53 | beqz t0, not_interrupt 54 | addi a0, a0, 1 55 | 56 | not_interrupt: 57 | /* return */ 58 | jalr x0, ra 59 | -------------------------------------------------------------------------------- /zephyr/soc/riscv/veerwolf/vector.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017 Jean-Paul Etienne 3 | * Contributors: 2018 Antmicro 4 | * 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | #include 9 | 10 | /* exports */ 11 | GTEXT(__start) 12 | 13 | /* imports */ 14 | GTEXT(__initialize) 15 | GTEXT(__irq_wrapper) 16 | 17 | SECTION_FUNC(vectors, __start) 18 | .option norvc; 19 | 20 | /* 21 | * Set mtvec (Machine Trap-Vector Base-Address Register) 22 | * to __irq_wrapper. 23 | */ 24 | la t0, __irq_wrapper 25 | csrw mtvec, t0 26 | /* 27 | * To avoid having to hardcode the main clock frequency, 28 | * we read the actual value from register 0x8000103c 29 | * and store to z_clock_hw_cycles_per_sec 30 | */ 31 | li t0, 0x80001000 32 | lw t1, 0x3c(t0) 33 | la t0, z_clock_hw_cycles_per_sec 34 | sw t1, 0(t0) 35 | 36 | /* Jump to __initialize */ 37 | tail __initialize 38 | --------------------------------------------------------------------------------