├── CHIPS Alliance - CCLA v7.pdf ├── LICENSE ├── README.md ├── axi4-mm ├── .gitignore ├── README.txt ├── axi_lite_a32_d32 │ ├── axi_lite_a32_d32_info.txt │ ├── axi_lite_a32_d32_master.f │ ├── axi_lite_a32_d32_master_concat.sv │ ├── axi_lite_a32_d32_master_name.sv │ ├── axi_lite_a32_d32_master_top.sv │ ├── axi_lite_a32_d32_slave.f │ ├── axi_lite_a32_d32_slave_concat.sv │ ├── axi_lite_a32_d32_slave_name.sv │ └── axi_lite_a32_d32_slave_top.sv ├── axi_mm_a32_d128 │ ├── axi_mm_a32_d128_info.txt │ ├── axi_mm_a32_d128_master.f │ ├── axi_mm_a32_d128_master_concat.sv │ ├── axi_mm_a32_d128_master_name.sv │ ├── axi_mm_a32_d128_master_top.sv │ ├── axi_mm_a32_d128_slave.f │ ├── axi_mm_a32_d128_slave_concat.sv │ ├── axi_mm_a32_d128_slave_name.sv │ └── axi_mm_a32_d128_slave_top.sv ├── axi_mm_a32_d128_packet │ ├── axi_mm_a32_d128_packet_info.txt │ ├── axi_mm_a32_d128_packet_master.f │ ├── axi_mm_a32_d128_packet_master_concat.sv │ ├── axi_mm_a32_d128_packet_master_name.sv │ ├── axi_mm_a32_d128_packet_master_top.sv │ ├── axi_mm_a32_d128_packet_slave.f │ ├── axi_mm_a32_d128_packet_slave_concat.sv │ ├── axi_mm_a32_d128_packet_slave_name.sv │ └── axi_mm_a32_d128_packet_slave_top.sv ├── axi_mm_a32_d128_packet_gen1 │ ├── axi_mm_a32_d128_packet_gen1_info.txt │ ├── axi_mm_a32_d128_packet_gen1_master.f │ ├── axi_mm_a32_d128_packet_gen1_master_concat.sv │ ├── axi_mm_a32_d128_packet_gen1_master_name.sv │ ├── axi_mm_a32_d128_packet_gen1_master_top.sv │ ├── axi_mm_a32_d128_packet_gen1_slave.f │ ├── axi_mm_a32_d128_packet_gen1_slave_concat.sv │ ├── axi_mm_a32_d128_packet_gen1_slave_name.sv │ └── axi_mm_a32_d128_packet_gen1_slave_top.sv ├── axi_mm_multi │ ├── axi_mm_master.f │ ├── axi_mm_master_top.sv │ ├── axi_mm_slave.f │ ├── axi_mm_slave_top.sv │ ├── aximm_ll_multi_tier1 │ │ ├── aximm_ll_multi_tier1_info.txt │ │ ├── aximm_ll_multi_tier1_master.f │ │ ├── aximm_ll_multi_tier1_master_concat.sv │ │ ├── aximm_ll_multi_tier1_master_name.sv │ │ ├── aximm_ll_multi_tier1_master_top.sv │ │ ├── aximm_ll_multi_tier1_slave.f │ │ ├── aximm_ll_multi_tier1_slave_concat.sv │ │ ├── aximm_ll_multi_tier1_slave_name.sv │ │ └── aximm_ll_multi_tier1_slave_top.sv │ ├── aximm_ll_multi_tier2 │ │ ├── aximm_ll_multi_tier2_info.txt │ │ ├── aximm_ll_multi_tier2_master.f │ │ ├── aximm_ll_multi_tier2_master_concat.sv │ │ ├── aximm_ll_multi_tier2_master_name.sv │ │ ├── aximm_ll_multi_tier2_master_top.sv │ │ ├── aximm_ll_multi_tier2_slave.f │ │ ├── aximm_ll_multi_tier2_slave_concat.sv │ │ ├── aximm_ll_multi_tier2_slave_name.sv │ │ └── aximm_ll_multi_tier2_slave_top.sv │ ├── build.sh │ └── compile.sh ├── build_examples.sh ├── cfg │ ├── axi_lite_a32_d32.cfg │ ├── axi_mm_a32_d128.cfg │ ├── axi_mm_a32_d128_packet.cfg │ ├── axi_mm_a32_d128_packet_gen1.cfg │ ├── axi_mm_a48_d512_packet.cfg │ ├── aximm_ll_multi_tier1.cfg │ └── aximm_ll_multi_tier2.cfg ├── doc │ └── README.txt ├── dv │ ├── axi_mm_a32_d128_packet_gen1_tb │ │ ├── Makefile │ │ ├── axi_mm_a32_d128_packet_gen1_tb.f │ │ ├── axi_mm_a32_d128_packet_gen1_tb.sv │ │ └── run_axi_mm_a32_d128_packet_gen1_tb │ ├── axi_mm_a32_d128_packet_tb │ │ ├── Makefile │ │ ├── axi_mm_a32_d128_packet_tb.f │ │ ├── axi_mm_a32_d128_packet_tb.sv │ │ └── run_axi_mm_a32_d128_packet_tb │ └── axi_mm_a32_d128_tb │ │ ├── Makefile │ │ ├── axi_mm_a32_d128_tb.f │ │ ├── axi_mm_a32_d128_tb.sv │ │ └── run_axi_mm_a32_d128_tb ├── full_examples │ ├── common │ │ ├── agent.sv │ │ ├── axi_mm_csr.v │ │ ├── axi_mm_patchkr_top.v │ │ ├── axi_mm_patgen_top.v │ │ ├── aximm_aib_top.v │ │ ├── aximm_d128_h2h_wrapper_top.v │ │ ├── aximm_follower_app.v │ │ ├── aximm_incr_gen.v │ │ ├── aximm_leader_app.v │ │ ├── aximm_rand_gen.v │ │ ├── aximm_wr_ctrl.v │ │ ├── jtag2avmm_bridge.v │ │ ├── mm_csr_ctrl.v │ │ ├── test.inc │ │ └── top_aib.sv │ ├── flist │ │ ├── axi_mm_d128_h2h.f │ │ └── tb_rtl.cf │ └── sims │ │ ├── tb_mh2.1_sh1_d128 │ │ ├── README.txt │ │ ├── aximm_ll.cfg │ │ ├── makefile │ │ └── top_tb.v │ │ └── tb_mh2.1_sh1_d64 │ │ ├── README.txt │ │ ├── aximm_ll.cfg │ │ ├── makefile │ │ └── top_tb.v └── full_examples_gpio │ ├── common │ ├── axi_mm_csr.v │ ├── axi_mm_patchkr_top.v │ ├── axi_mm_patgen_top.v │ ├── aximm_d128_gpiophy_dual_wrapper_top.v │ ├── aximm_d128_gpiophy_wrapper_top.v │ ├── aximm_follower_app.v │ ├── aximm_gpiophy_dual_top.v │ ├── aximm_gpiophy_top.v │ ├── aximm_incr_gen.v │ ├── aximm_leader_app.v │ ├── aximm_rand_gen.v │ ├── aximm_wr_ctrl.v │ ├── jtag2avmm_bridge.v │ └── mm_csr_ctrl.v │ ├── flist │ ├── axi_mm_d128_gpio.f │ ├── axi_mm_d128_gpio_dual.f │ └── tb_gpio_rtl.cf │ └── sims │ ├── tb_20bit_gpio_d128 │ ├── README.txt │ ├── aximm_ll.cfg │ ├── makefile │ └── top_tb.v │ ├── tb_20bit_gpio_d128_dual │ ├── README.txt │ ├── aximm_ll.cfg │ ├── makefile │ └── top_tb.v │ └── tb_40bit_gpio_d128 │ ├── README.txt │ ├── aximm_ll.cfg │ ├── makefile │ └── top_tb.v ├── axi4-st-duplex ├── README.txt ├── axi_dual_st_d256_multichannel │ ├── axi_dual_st_d256_multichannel_full_info.txt │ ├── axi_dual_st_d256_multichannel_full_master.f │ ├── axi_dual_st_d256_multichannel_full_master_concat.sv │ ├── axi_dual_st_d256_multichannel_full_master_name.sv │ ├── axi_dual_st_d256_multichannel_full_master_top.sv │ ├── axi_dual_st_d256_multichannel_full_slave.f │ ├── axi_dual_st_d256_multichannel_full_slave_concat.sv │ ├── axi_dual_st_d256_multichannel_full_slave_name.sv │ ├── axi_dual_st_d256_multichannel_full_slave_top.sv │ ├── axi_dual_st_d256_multichannel_half_info.txt │ ├── axi_dual_st_d256_multichannel_half_master.f │ ├── axi_dual_st_d256_multichannel_half_master_concat.sv │ ├── axi_dual_st_d256_multichannel_half_master_name.sv │ ├── axi_dual_st_d256_multichannel_half_master_top.sv │ ├── axi_dual_st_d256_multichannel_half_slave.f │ ├── axi_dual_st_d256_multichannel_half_slave_concat.sv │ ├── axi_dual_st_d256_multichannel_half_slave_name.sv │ └── axi_dual_st_d256_multichannel_half_slave_top.sv ├── axi_dual_st_d64 │ ├── axi_dual_st_d64_info.txt │ ├── axi_dual_st_d64_master.f │ ├── axi_dual_st_d64_master_concat.sv │ ├── axi_dual_st_d64_master_name.sv │ ├── axi_dual_st_d64_master_top.sv │ ├── axi_dual_st_d64_slave.f │ ├── axi_dual_st_d64_slave_concat.sv │ ├── axi_dual_st_d64_slave_name.sv │ └── axi_dual_st_d64_slave_top.sv ├── build_examples.sh ├── cfg │ ├── axi_dual_st_d256_multichannel.cfg │ └── axi_dual_st_d64.cfg ├── doc │ └── llink_duplex_ug.pdf ├── dv │ └── README.txt └── full_examples │ └── README.txt ├── axi4-st ├── .gitignore ├── README.txt ├── axi_st_d256_gen1_gen2 │ ├── axi_st_d256_gen1_gen2_info.txt │ ├── axi_st_d256_gen1_gen2_master.f │ ├── axi_st_d256_gen1_gen2_master_concat.sv │ ├── axi_st_d256_gen1_gen2_master_name.sv │ ├── axi_st_d256_gen1_gen2_master_top.sv │ ├── axi_st_d256_gen1_gen2_slave.f │ ├── axi_st_d256_gen1_gen2_slave_concat.sv │ ├── axi_st_d256_gen1_gen2_slave_name.sv │ └── axi_st_d256_gen1_gen2_slave_top.sv ├── axi_st_d256_gen2_only │ ├── axi_st_d256_gen2_only_info.txt │ ├── axi_st_d256_gen2_only_master.f │ ├── axi_st_d256_gen2_only_master_concat.sv │ ├── axi_st_d256_gen2_only_master_name.sv │ ├── axi_st_d256_gen2_only_master_top.sv │ ├── axi_st_d256_gen2_only_slave.f │ ├── axi_st_d256_gen2_only_slave_concat.sv │ ├── axi_st_d256_gen2_only_slave_name.sv │ └── axi_st_d256_gen2_only_slave_top.sv ├── axi_st_d256_multichannel │ ├── axi_st_d256_multichannel_full_info.txt │ ├── axi_st_d256_multichannel_full_master.f │ ├── axi_st_d256_multichannel_full_master_concat.sv │ ├── axi_st_d256_multichannel_full_master_name.sv │ ├── axi_st_d256_multichannel_full_master_top.sv │ ├── axi_st_d256_multichannel_full_slave.f │ ├── axi_st_d256_multichannel_full_slave_concat.sv │ ├── axi_st_d256_multichannel_full_slave_name.sv │ ├── axi_st_d256_multichannel_full_slave_top.sv │ ├── axi_st_d256_multichannel_half_info.txt │ ├── axi_st_d256_multichannel_half_master.f │ ├── axi_st_d256_multichannel_half_master_concat.sv │ ├── axi_st_d256_multichannel_half_master_name.sv │ ├── axi_st_d256_multichannel_half_master_top.sv │ ├── axi_st_d256_multichannel_half_slave.f │ ├── axi_st_d256_multichannel_half_slave_concat.sv │ ├── axi_st_d256_multichannel_half_slave_name.sv │ └── axi_st_d256_multichannel_half_slave_top.sv ├── axi_st_d64 │ ├── axi_st_d64_info.txt │ ├── axi_st_d64_master.f │ ├── axi_st_d64_master_concat.sv │ ├── axi_st_d64_master_name.sv │ ├── axi_st_d64_master_top.sv │ ├── axi_st_d64_slave.f │ ├── axi_st_d64_slave_concat.sv │ ├── axi_st_d64_slave_name.sv │ └── axi_st_d64_slave_top.sv ├── axi_st_d64_nordy │ ├── axi_st_d64_nordy_info.txt │ ├── axi_st_d64_nordy_master.f │ ├── axi_st_d64_nordy_master_concat.sv │ ├── axi_st_d64_nordy_master_name.sv │ ├── axi_st_d64_nordy_master_top.sv │ ├── axi_st_d64_nordy_slave.f │ ├── axi_st_d64_nordy_slave_concat.sv │ ├── axi_st_d64_nordy_slave_name.sv │ └── axi_st_d64_nordy_slave_top.sv ├── build_examples.sh ├── cfg │ ├── axi_st_d256_gen1_gen2.cfg │ ├── axi_st_d256_multichannel.cfg │ ├── axi_st_d256_norm.cfg │ ├── axi_st_d64.cfg │ └── axi_st_d64_nordy.cfg ├── doc │ ├── axi4_latency_rx_buffer_sizing_guide.pdf │ └── llink_ug.pdf ├── dv │ ├── axi_st_d256_gen1_gen2_tb │ │ ├── Makefile │ │ ├── axi_st_d256_gen1_gen2_tb.f │ │ ├── axi_st_d256_gen1_gen2_tb.sv │ │ └── run_st_d256_gen1_gen2 │ ├── axi_st_d256_multichannel_f2h_tb │ │ ├── Makefile │ │ ├── axi_st_d256_multichannel_f2h_tb.f │ │ ├── axi_st_d256_multichannel_f2h_tb.sv │ │ └── run_axi_st_d256_multichannel_f2h_tb │ ├── axi_st_d64_nordy_tb │ │ ├── Makefile │ │ ├── axi_st_d64_nordy_tb.f │ │ ├── axi_st_d64_nordy_tb.sv │ │ └── run_axi_st_d64_nordy_tb │ └── axi_st_d64_tb │ │ ├── Makefile │ │ ├── axi_st_d64_tb.f │ │ ├── axi_st_d64_tb.sv │ │ └── run_axi_st_d64_tb ├── full_examples │ ├── common │ │ ├── agent.sv │ │ ├── axi_st_csr.v │ │ ├── axi_st_d256_multichannel_f2h_dual_top.sv │ │ ├── axi_st_d256_multichannel_f2h_simplex_top.sv │ │ ├── axi_st_h2h_csr.v │ │ ├── axi_st_h2h_patchkr_top.v │ │ ├── axi_st_h2h_patgen_top.v │ │ ├── axi_st_multichannel_h2h_simplex_top.sv │ │ ├── axi_st_patchkr_f2h_top.v │ │ ├── axi_st_patchkr_h2f_top.v │ │ ├── axi_st_patchkr_top.v │ │ ├── axi_st_patgen_dual_top.v │ │ ├── axi_st_patgen_top.v │ │ ├── axi_st_wr_ctrl.v │ │ ├── axist_aib_dual_top.v │ │ ├── axist_aib_h2h_top.v │ │ ├── axist_aib_top.v │ │ ├── axist_incr_gen.v │ │ ├── axist_rand_gen.v │ │ ├── csr_ctrl.v │ │ ├── csr_ctrl_h2h.v │ │ ├── jtag2avmm_bridge.v │ │ ├── reset_control.v │ │ ├── test.inc │ │ ├── test_h2h.inc │ │ ├── top_aib.sv │ │ └── top_h2h_aib.sv │ ├── flist │ │ ├── axi_st_d256_multichannel_f2h_dual.f │ │ ├── axi_st_d256_multichannel_f2h_simplex.f │ │ ├── axi_st_d256_multichannel_h2h_simplex.f │ │ ├── axi_st_d64_multichannel_h2h_simplex.f │ │ ├── tb_dual_rtl.cf │ │ ├── tb_rtl.cf │ │ └── tb_rtl_h2h.cf │ └── sims │ │ ├── tb_mf2.1_sh1_d256 │ │ ├── README.txt │ │ ├── axi_st_d256_multichannel.cfg │ │ ├── makefile │ │ └── top_tb.v │ │ ├── tb_mf2.1_sh1_d256_dual │ │ ├── README.txt │ │ ├── axi_st_d256_dual_multichannel.cfg │ │ ├── makefile │ │ └── top_tb.v │ │ ├── tb_mh2.1_sh1_d256 │ │ ├── README.txt │ │ ├── axist_ll.cfg │ │ ├── makefile │ │ └── top_tb.v │ │ └── tb_mh2.1_sh1_d64 │ │ ├── README.txt │ │ ├── axist_ll.cfg │ │ ├── makefile │ │ └── top_tb.v └── full_examples_gpio │ ├── common │ ├── axi_st_h2h_csr.v │ ├── axi_st_h2h_patchkr_top.v │ ├── axi_st_h2h_patgen_top.v │ ├── axi_st_simplex_gpio_phy_top.sv │ ├── axi_st_wr_ctrl.v │ ├── axist_gpiophy_top.v │ ├── axist_incr_gen.v │ ├── axist_rand_gen.v │ ├── csr_ctrl_h2h.v │ ├── jtag2avmm_bridge.v │ └── reset_control.v │ ├── flist │ ├── tb_axist_gpio_phy.cf │ └── tb_rtl.cf │ └── sims │ └── tb_40bit_gpio_d256 │ ├── README.txt │ ├── axist_ll.cfg │ ├── makefile │ └── top_tb.v ├── backup └── spi │ ├── doc │ ├── spi_ug.pdf │ └── spi_ug_v08p3.pdf │ ├── fpga │ ├── spim │ │ ├── spim_wrap.qpf │ │ ├── spim_wrap.qsf │ │ ├── spim_wrap.sdc │ │ └── spim_wrap.sv │ └── spis │ │ ├── spis_wrap.qpf │ │ ├── spis_wrap.qsf │ │ ├── spis_wrap.sdc │ │ └── spis_wrap.sv │ └── rtl │ ├── README │ ├── spim │ ├── clk_gate_beh.sv │ ├── pulse_sync.sv │ ├── spi.vh │ ├── spim.f │ ├── spim_intf.sv │ ├── spim_reg.sv │ ├── spim_reg_top.sv │ ├── spim_top.sv │ └── spimavb.sv │ └── spis │ ├── pulse_sync.sv │ ├── spi.vh │ ├── spis.f │ ├── spis_intf.sv │ ├── spis_miso_buf.sv │ ├── spis_reg.sv │ ├── spis_reg_top.sv │ ├── spis_top.sv │ └── spisavb.sv ├── ca ├── README ├── doc │ └── ca_ug.pdf ├── dv │ ├── .gitignore │ ├── README │ ├── aib.f │ ├── ca_cov_refine_summary.txt │ ├── ca_no_shm.tcl │ ├── ca_pkg.svh │ ├── ca_shm.tcl │ ├── cfg_list │ │ ├── README │ │ └── ca_gen_cfg.py │ ├── examples │ │ ├── CH10_GEN2_Q2Q_FIFO32_ASYNC_sailrock_cfg.txt │ │ ├── CH11_GEN1_F2F_FIFO16_SYNC_sailrock_cfg.txt │ │ ├── CH12_GEN1_H2H_FIFO32_ASYNC_sailrock_cfg.txt │ │ ├── CH13_GEN1_F2F_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH14_GEN1_H2H_FIFO16_ASYNC_sailrock_cfg.txt │ │ ├── CH15_GEN2_H2H_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH16_GEN2_Q2Q_FIFO32_ASYNC_sailrock_cfg.txt │ │ ├── CH17_GEN1_F2F_FIFO16_SYNC_sailrock_cfg.txt │ │ ├── CH18_GEN1_H2H_FIFO8_ASYNC_sailrock_cfg.txt │ │ ├── CH19_GEN2_F2F_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH20_GEN2_F2F_FIFO32_ASYNC_sailrock_cfg.txt │ │ ├── CH21_GEN2_H2H_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH22_GEN2_Q2Q_FIFO16_ASYNC_sailrock_cfg.txt │ │ ├── CH23_GEN1_H2H_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH2_GEN2_F2F_FIFO16_ASYNC_sailrock_cfg.txt │ │ ├── CH3_GEN2_H2H_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH4_GEN2_Q2Q_FIFO8_ASYNC_sailrock_cfg.txt │ │ ├── CH5_GEN2_F2F_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── CH6_GEN2_H2H_FIFO16_ASYNC_sailrock_cfg.txt │ │ ├── CH7_GEN2_Q2Q_FIFO8_SYNC_sailrock_cfg.txt │ │ ├── CH8_GEN2_F2F_FIFO32_ASYNC_sailrock_cfg.txt │ │ ├── CH9_GEN2_H2H_FIFO32_SYNC_sailrock_cfg.txt │ │ ├── GEN1_f2f_sailrock_cfg.txt │ │ ├── GEN1_f2h_sailrock_cfg.txt │ │ ├── GEN1_h2f_sailrock_cfg.txt │ │ ├── GEN1_h2h_sailrock_cfg.txt │ │ ├── M2S1_GEN1_F2H_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_ALIGN_FLY1_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_align_error_fifo16_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_align_error_fifo32_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_align_error_fifo8_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_fifo_depth16_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_no_ch_delay_async_fifo_afly_x_xz_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_no_ch_delay_sync_fifo_afly_x_xz_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_rden_dly2_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_rden_dly4_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_rden_dly6_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2F_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2H_sailrock_cfg.txt │ │ ├── M2S2_GEN2_F2Q_sailrock_cfg.txt │ │ ├── M2S2_GEN2_H2F_sailrock_cfg.txt │ │ ├── M2S2_GEN2_H2H_sailrock_cfg.txt │ │ ├── M2S2_GEN2_H2Q_sailrock_cfg.txt │ │ ├── M2S2_GEN2_Q2F_sailrock_cfg.txt │ │ ├── M2S2_GEN2_Q2H_sailrock_cfg.txt │ │ ├── M2S2_GEN2_Q2Q_CH24_sailrock_cfg.txt │ │ ├── M2S2_GEN2_Q2Q_MARKER_78_sailrock_cfg.txt │ │ ├── M2S2_GEN2_Q2Q_sailrock_cfg.txt │ │ ├── delay_00000015_sailrock_cfg.txt │ │ ├── delay_01010101_sailrock_cfg.txt │ │ ├── delay_015151515_sailrock_cfg.txt │ │ ├── delay_0_sailrock_cfg.txt │ │ ├── full_pfull_ch0_sailrock_cfg.txt │ │ ├── full_pfull_ch7_sailrock_cfg.txt │ │ ├── full_pfull_sailrock_cfg.txt │ │ ├── inter_ch_skew15_32_ch0_sailrock_cfg.txt │ │ ├── inter_ch_skew15_32_sailrock_cfg.txt │ │ ├── m2s1_f2h_noskew_ch_sailrock_cfg.txt │ │ ├── m2s1_f2h_sailrock_cfg.txt │ │ ├── num_ch2_sailrock_cfg.txt │ │ ├── sync_fifo0_afly1_sailrock_cfg.txt │ │ └── sync_fifo0_sailrock_cfg.txt │ ├── export_src │ │ ├── ca_coverage.sv │ │ ├── ca_data_pkg.svh │ │ ├── ca_reset_agent │ │ │ ├── .ca_reset_agent.sv.swp │ │ │ ├── ca_reset_agent.sv │ │ │ ├── ca_reset_cfg.sv │ │ │ ├── ca_reset_drv.sv │ │ │ ├── ca_reset_if.sv │ │ │ ├── ca_reset_mon.sv │ │ │ ├── ca_reset_pkg.svh │ │ │ ├── ca_reset_seq.sv │ │ │ ├── ca_reset_seq_item.sv │ │ │ └── ca_reset_seqr.sv │ │ ├── ca_rx_tb_in_agent.sv │ │ ├── ca_rx_tb_in_cfg.sv │ │ ├── ca_rx_tb_in_drv.sv │ │ ├── ca_rx_tb_in_if.sv │ │ ├── ca_rx_tb_in_mon.sv │ │ ├── ca_rx_tb_in_pkg.svh │ │ ├── ca_rx_tb_in_seqr.sv │ │ ├── ca_scoreboard.sv │ │ ├── ca_seq_item.sv │ │ ├── ca_tx_tb_in_agent.sv │ │ ├── ca_tx_tb_in_cfg.sv │ │ ├── ca_tx_tb_in_drv.sv │ │ ├── ca_tx_tb_in_if.sv │ │ ├── ca_tx_tb_in_mon.sv │ │ ├── ca_tx_tb_in_pkg.svh │ │ ├── ca_tx_tb_in_seqr.sv │ │ ├── ca_tx_tb_out_agent.sv │ │ ├── ca_tx_tb_out_cfg.sv │ │ ├── ca_tx_tb_out_drv.sv │ │ ├── ca_tx_tb_out_if.sv │ │ ├── ca_tx_tb_out_mon.sv │ │ ├── ca_tx_tb_out_pkg.svh │ │ ├── ca_tx_tb_out_seqr.sv │ │ └── chan_delay_agent │ │ │ ├── chan_delay_agent.sv │ │ │ ├── chan_delay_cfg.sv │ │ │ ├── chan_delay_drv.sv │ │ │ ├── chan_delay_if.sv │ │ │ ├── chan_delay_mon.sv │ │ │ ├── chan_delay_pkg.svh │ │ │ ├── chan_delay_seq_item.sv │ │ │ └── chan_delay_seqr.sv │ ├── imc.cmd │ ├── local_src │ │ └── ca_gen_if.sv │ ├── run_nightly.sh │ ├── run_regression.sh │ ├── run_smoke.sh │ ├── scripts │ │ ├── aib_cfg_default.txt │ │ ├── aib_gen_config │ │ ├── aib_gen_parser.py │ │ ├── ca_cfg_default.txt │ │ ├── ca_gen_parser.pl │ │ ├── ca_gen_parser.py │ │ ├── makefile │ │ ├── readme │ │ ├── run_all_sim.py │ │ ├── run_change_makefile.py │ │ ├── run_sim │ │ ├── sailrock_cfg.txt │ │ └── target_cfg.txt │ ├── seqs │ │ ├── ca_rx_traffic_seq.sv │ │ ├── ca_seq_lib.sv │ │ ├── ca_traffic_seq.sv │ │ ├── ca_tx_traffic_seq.sv │ │ └── virt_seqr.sv │ ├── submit_group.pl │ ├── tb │ │ ├── aib_tb_tasks.svi │ │ ├── ca_AIB2g2_full_AIB2g2_half.svh │ │ ├── ca_DUT_wrapper.sv │ │ ├── ca_GENERATED_defines.svh │ │ ├── ca_top_env.sv │ │ ├── ca_top_tb.f │ │ └── ca_top_tb.sv │ └── tests │ │ ├── base_ca_test.sv │ │ ├── ca_afly1_stb_incorrect_intv_test.sv │ │ ├── ca_afly1_stb_intv_variations_test.sv │ │ ├── ca_afly_toggling_test.sv │ │ ├── ca_align_error_test.sv │ │ ├── ca_all_wd_sel_39th_bit_sel_test.sv │ │ ├── ca_aln_err_afly0_by_incorrect_stb_test.sv │ │ ├── ca_aln_err_by_incorrect_stb_test.sv │ │ ├── ca_basic_afly1_test.sv │ │ ├── ca_basic_test.sv │ │ ├── ca_cfg.sv │ │ ├── ca_delay_x_xz_values_test.sv │ │ ├── ca_fifo_ptr_values_variations_test.sv │ │ ├── ca_knobs.sv │ │ ├── ca_no_external_strobes_test.sv │ │ ├── ca_rden_dly_test.sv │ │ ├── ca_reset_during_traffic_test.sv │ │ ├── ca_stb_all_bit_sel_test.sv │ │ ├── ca_stb_en0_aft_aln_done_test.sv │ │ ├── ca_stb_enb_high_low_high_test.sv │ │ ├── ca_stb_intv_stb_pos_test.sv │ │ ├── ca_stb_intv_walking_ones_test.sv │ │ ├── ca_stb_rcvr_aft_aln_done_test.sv │ │ ├── ca_stb_rcvr_enb_test.sv │ │ ├── ca_stb_wd_sel_Q2Q_test.sv │ │ ├── ca_stb_wd_sel_bit_sel_test.sv │ │ ├── ca_stb_wd_sel_test.sv │ │ ├── ca_strobe_error_test.sv │ │ ├── ca_toggle_cover_test.sv │ │ ├── ca_traffic_reset_traffic_test.sv │ │ ├── ca_tx_rx_online_test.sv │ │ ├── ca_wd_bit_sel_ones_cover_test.sv │ │ └── ca_with_external_strobes_test.sv ├── fpga │ ├── ca_wrap.qpf │ ├── ca_wrap.qsf │ ├── ca_wrap.sdc │ └── ca_wrap.sv └── rtl │ ├── ca.f │ ├── ca.sv │ ├── ca_rx_align.sv │ ├── ca_rx_align_fifo.sv │ ├── ca_tx_mux.sv │ └── ca_tx_strb.sv ├── common ├── README ├── dv │ ├── .gitignore │ ├── axi_ready_xactor.sv │ ├── chan_delay_agent │ │ ├── chan_delay_agent.sv │ │ ├── chan_delay_cfg.sv │ │ ├── chan_delay_drv.sv │ │ ├── chan_delay_if.sv │ │ ├── chan_delay_mon.sv │ │ ├── chan_delay_pkg.svh │ │ ├── chan_delay_seq_item.sv │ │ └── chan_delay_seqr.sv │ ├── marker_gen.sv │ ├── p2p_lite.sv │ ├── reset_agent │ │ ├── reset_agent.sv │ │ ├── reset_cfg.sv │ │ ├── reset_drv.sv │ │ ├── reset_if.sv │ │ ├── reset_mon.sv │ │ ├── reset_pkg.svh │ │ ├── reset_seq.sv │ │ ├── reset_seq_item.sv │ │ └── reset_seqr.sv │ └── strobe_gen.sv └── rtl │ ├── README │ ├── asyncfifo.sv │ ├── common.f │ ├── level_delay.sv │ ├── levelsync.sv │ ├── levelsync_sr.sv │ ├── rrarb.sv │ ├── rst_regen_low.sv │ ├── strobe_gen_w_delay.sv │ ├── syncfifo.sv │ ├── syncfifo_mem1r1w.sv │ ├── syncfifo_ram.sv │ └── syncfifo_reg.sv ├── llink ├── fpga │ ├── .gitignore │ ├── README.txt │ ├── dv │ │ ├── .gitignore │ │ ├── axi_mm_a32_d128_packet_tb.f │ │ ├── axi_mm_a32_d128_packet_tb.sv │ │ └── run_mm_a32_d128_packet │ ├── fake_phy.sv │ ├── top.sv │ ├── two_axi_mm_chiplet.qpf │ ├── two_axi_mm_chiplet.qsf │ ├── two_axi_mm_chiplet.sdc │ └── two_axi_mm_chiplet.sv ├── rtl │ ├── .gitignore │ ├── build.sh │ ├── ll_auto_sync.sv │ ├── ll_receive.sv │ ├── ll_rx_ctrl.sv │ ├── ll_rx_push.sv │ ├── ll_transmit.sv │ ├── ll_tx_cred.sv │ ├── ll_tx_ctrl.sv │ └── llink.f └── script │ ├── .gitignore │ ├── README.txt │ ├── build_premade_examples.sh │ ├── cfg │ ├── axi_fourchan_a32_d32.cfg │ ├── axi_fourchan_a32_d32_packet.cfg │ ├── axi_fourchan_tier1_a32_d32_packet.cfg │ ├── axi_fourchan_tier2.cfg │ ├── axi_lite_a32_d32.cfg │ ├── axi_mm_a32_d128.cfg │ ├── axi_mm_a32_d128_packet.cfg │ ├── axi_mm_a32_d128_packet_gen1.cfg │ ├── axi_mm_a32_d128_packet_up_rv_2_mem.cfg │ ├── axi_mm_a48_d512_packet.cfg │ ├── axi_mm_a48_d512_packet_variant1.cfg │ ├── axi_mm_a48_d512_packet_variant2.cfg │ ├── axi_mm_a48_d512_packet_variant3.cfg │ ├── axi_st_d128_asym.cfg │ ├── axi_st_d256_dm_drng_2_up.cfg │ ├── axi_st_d256_gen1_gen2.cfg │ ├── axi_st_d256_norm.cfg │ └── axi_st_d64.cfg │ ├── dual_axist_llink_gen.py │ ├── dual_galt.py │ ├── galt.py │ ├── global_struct.py │ ├── gpio_llink_gen.py │ ├── llink_dv_packet_postproc.py │ ├── llink_gen.py │ ├── packetization.py │ └── premade_examples │ ├── axi_fourchan_a32_d32 │ ├── axi_fourchan_a32_d32_info.txt │ ├── axi_fourchan_a32_d32_master.f │ ├── axi_fourchan_a32_d32_master_concat.sv │ ├── axi_fourchan_a32_d32_master_name.sv │ ├── axi_fourchan_a32_d32_master_top.sv │ ├── axi_fourchan_a32_d32_slave.f │ ├── axi_fourchan_a32_d32_slave_concat.sv │ ├── axi_fourchan_a32_d32_slave_name.sv │ └── axi_fourchan_a32_d32_slave_top.sv │ ├── axi_fourchan_a32_d32_packet │ ├── axi_fourchan_a32_d32_packet_info.txt │ ├── axi_fourchan_a32_d32_packet_master.f │ ├── axi_fourchan_a32_d32_packet_master_concat.sv │ ├── axi_fourchan_a32_d32_packet_master_name.sv │ ├── axi_fourchan_a32_d32_packet_master_top.sv │ ├── axi_fourchan_a32_d32_packet_slave.f │ ├── axi_fourchan_a32_d32_packet_slave_concat.sv │ ├── axi_fourchan_a32_d32_packet_slave_name.sv │ └── axi_fourchan_a32_d32_packet_slave_top.sv │ ├── axi_fourchan_tier1_a32_d32_packet │ ├── axi_fourchan_tier1_a32_d32_packet_info.txt │ ├── axi_fourchan_tier1_a32_d32_packet_master.f │ ├── axi_fourchan_tier1_a32_d32_packet_master_concat.sv │ ├── axi_fourchan_tier1_a32_d32_packet_master_name.sv │ ├── axi_fourchan_tier1_a32_d32_packet_master_top.sv │ ├── axi_fourchan_tier1_a32_d32_packet_slave.f │ ├── axi_fourchan_tier1_a32_d32_packet_slave_concat.sv │ ├── axi_fourchan_tier1_a32_d32_packet_slave_name.sv │ └── axi_fourchan_tier1_a32_d32_packet_slave_top.sv │ ├── axi_fourchan_tier2 │ ├── axi_fourchan_tier2_info.txt │ ├── axi_fourchan_tier2_master.f │ ├── axi_fourchan_tier2_master_concat.sv │ ├── axi_fourchan_tier2_master_name.sv │ ├── axi_fourchan_tier2_master_top.sv │ ├── axi_fourchan_tier2_slave.f │ ├── axi_fourchan_tier2_slave_concat.sv │ ├── axi_fourchan_tier2_slave_name.sv │ └── axi_fourchan_tier2_slave_top.sv │ ├── axi_fourchan_tier_top │ ├── axi_fourchan_tier_master_top.f │ ├── axi_fourchan_tier_master_top.sv │ ├── axi_fourchan_tier_master_top.sv~ │ ├── axi_fourchan_tier_slave_top.f │ ├── axi_fourchan_tier_slave_top.sv │ ├── axi_fourchan_tier_slave_top.sv~ │ └── axi_fourchan_tier_top.sv~ │ ├── axi_lite_a32_d32 │ ├── axi_lite_a32_d32_info.txt │ ├── axi_lite_a32_d32_master.f │ ├── axi_lite_a32_d32_master_concat.sv │ ├── axi_lite_a32_d32_master_name.sv │ ├── axi_lite_a32_d32_master_top.sv │ ├── axi_lite_a32_d32_slave.f │ ├── axi_lite_a32_d32_slave_concat.sv │ ├── axi_lite_a32_d32_slave_name.sv │ └── axi_lite_a32_d32_slave_top.sv │ ├── axi_mm_a32_d128 │ ├── axi_mm_a32_d128_info.txt │ ├── axi_mm_a32_d128_master.f │ ├── axi_mm_a32_d128_master_concat.sv │ ├── axi_mm_a32_d128_master_name.sv │ ├── axi_mm_a32_d128_master_top.sv │ ├── axi_mm_a32_d128_slave.f │ ├── axi_mm_a32_d128_slave_concat.sv │ ├── axi_mm_a32_d128_slave_name.sv │ └── axi_mm_a32_d128_slave_top.sv │ ├── axi_mm_a32_d128_packet │ ├── axi_mm_a32_d128_packet_info.txt │ ├── axi_mm_a32_d128_packet_master.f │ ├── axi_mm_a32_d128_packet_master_concat.sv │ ├── axi_mm_a32_d128_packet_master_name.sv │ ├── axi_mm_a32_d128_packet_master_top.sv │ ├── axi_mm_a32_d128_packet_slave.f │ ├── axi_mm_a32_d128_packet_slave_concat.sv │ ├── axi_mm_a32_d128_packet_slave_name.sv │ └── axi_mm_a32_d128_packet_slave_top.sv │ ├── axi_mm_a32_d128_packet_up_rv_2_mem │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_info.txt │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_master.f │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_master_concat.sv │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_master_name.sv │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_master_top.sv │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_slave.f │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_slave_concat.sv │ ├── axi_mm_a32_d128_packet_up_rv_2_mem_slave_name.sv │ └── axi_mm_a32_d128_packet_up_rv_2_mem_slave_top.sv │ ├── axi_mm_a48_d512_packet │ ├── axi_mm_a48_d512_packet_info.txt │ ├── axi_mm_a48_d512_packet_master.f │ ├── axi_mm_a48_d512_packet_master_concat.sv │ ├── axi_mm_a48_d512_packet_master_name.sv │ ├── axi_mm_a48_d512_packet_master_top.sv │ ├── axi_mm_a48_d512_packet_slave.f │ ├── axi_mm_a48_d512_packet_slave_concat.sv │ ├── axi_mm_a48_d512_packet_slave_name.sv │ └── axi_mm_a48_d512_packet_slave_top.sv │ ├── axi_st_d128_asym │ ├── axi_st_d128_asym_full_info.txt │ ├── axi_st_d128_asym_full_master.f │ ├── axi_st_d128_asym_full_master_concat.sv │ ├── axi_st_d128_asym_full_master_name.sv │ ├── axi_st_d128_asym_full_master_top.sv │ ├── axi_st_d128_asym_full_slave.f │ ├── axi_st_d128_asym_full_slave_concat.sv │ ├── axi_st_d128_asym_full_slave_name.sv │ ├── axi_st_d128_asym_full_slave_top.sv │ ├── axi_st_d128_asym_half_info.txt │ ├── axi_st_d128_asym_half_master.f │ ├── axi_st_d128_asym_half_master_concat.sv │ ├── axi_st_d128_asym_half_master_name.sv │ ├── axi_st_d128_asym_half_master_top.sv │ ├── axi_st_d128_asym_half_slave.f │ ├── axi_st_d128_asym_half_slave_concat.sv │ ├── axi_st_d128_asym_half_slave_name.sv │ ├── axi_st_d128_asym_half_slave_top.sv │ ├── axi_st_d128_asym_quarter_info.txt │ ├── axi_st_d128_asym_quarter_master.f │ ├── axi_st_d128_asym_quarter_master_concat.sv │ ├── axi_st_d128_asym_quarter_master_name.sv │ ├── axi_st_d128_asym_quarter_master_top.sv │ ├── axi_st_d128_asym_quarter_slave.f │ ├── axi_st_d128_asym_quarter_slave_concat.sv │ ├── axi_st_d128_asym_quarter_slave_name.sv │ └── axi_st_d128_asym_quarter_slave_top.sv │ ├── axi_st_d256_dm_drng_2_up │ ├── axi_st_d256_dm_drng_2_up_full_info.txt │ ├── axi_st_d256_dm_drng_2_up_full_master.f │ ├── axi_st_d256_dm_drng_2_up_full_master_concat.sv │ ├── axi_st_d256_dm_drng_2_up_full_master_name.sv │ ├── axi_st_d256_dm_drng_2_up_full_master_top.sv │ ├── axi_st_d256_dm_drng_2_up_full_slave.f │ ├── axi_st_d256_dm_drng_2_up_full_slave_concat.sv │ ├── axi_st_d256_dm_drng_2_up_full_slave_name.sv │ ├── axi_st_d256_dm_drng_2_up_full_slave_top.sv │ ├── axi_st_d256_dm_drng_2_up_half_info.txt │ ├── axi_st_d256_dm_drng_2_up_half_master.f │ ├── axi_st_d256_dm_drng_2_up_half_master_concat.sv │ ├── axi_st_d256_dm_drng_2_up_half_master_name.sv │ ├── axi_st_d256_dm_drng_2_up_half_master_top.sv │ ├── axi_st_d256_dm_drng_2_up_half_slave.f │ ├── axi_st_d256_dm_drng_2_up_half_slave_concat.sv │ ├── axi_st_d256_dm_drng_2_up_half_slave_name.sv │ └── axi_st_d256_dm_drng_2_up_half_slave_top.sv │ ├── axi_st_d256_gen1_gen2 │ ├── axi_st_d256_gen1_gen2_info.txt │ ├── axi_st_d256_gen1_gen2_master.f │ ├── axi_st_d256_gen1_gen2_master_concat.sv │ ├── axi_st_d256_gen1_gen2_master_name.sv │ ├── axi_st_d256_gen1_gen2_master_top.sv │ ├── axi_st_d256_gen1_gen2_slave.f │ ├── axi_st_d256_gen1_gen2_slave_concat.sv │ ├── axi_st_d256_gen1_gen2_slave_name.sv │ └── axi_st_d256_gen1_gen2_slave_top.sv │ └── axi_st_d64 │ ├── axi_st_d64_info.txt │ ├── axi_st_d64_master.f │ ├── axi_st_d64_master_concat.sv │ ├── axi_st_d64_master_name.sv │ ├── axi_st_d64_master_top.sv │ ├── axi_st_d64_slave.f │ ├── axi_st_d64_slave_concat.sv │ ├── axi_st_d64_slave_name.sv │ └── axi_st_d64_slave_top.sv ├── lpif ├── README ├── doc │ └── lpif_adapter_ug.pdf ├── fpga │ ├── README │ ├── lpif_wrap.qpf │ ├── lpif_wrap.qsf │ ├── lpif_wrap.qws │ ├── lpif_wrap.sdc │ └── lpif_wrap.sv ├── full_examples │ ├── common │ │ ├── agent.sv │ │ ├── data_checker.v │ │ ├── device_lpif_intf.v │ │ ├── host_lpif_intf.v │ │ ├── jtag2avmm_bridge.v │ │ ├── lpif_aib_top.v │ │ ├── lpif_csr.v │ │ ├── lpif_csr_intf.v │ │ ├── lpif_ed_defines.v │ │ ├── test.inc │ │ └── top_aib.sv │ ├── flist │ │ ├── lpif.f │ │ └── tb_rtl.cf │ └── sims │ │ └── tb_mh2_sh2_d128 │ │ ├── README.txt │ │ ├── makefile │ │ └── tb_top.sv └── rtl │ ├── README │ ├── cfg │ ├── lpif_x16_asym1.cfg │ ├── lpif_x16_asym2.cfg │ ├── lpif_x16_f1.cfg │ ├── lpif_x16_f2.cfg │ ├── lpif_x16_h1.cfg │ ├── lpif_x16_h2.cfg │ ├── lpif_x16_q2.cfg │ ├── lpif_x1_asym1.cfg │ ├── lpif_x1_f1.cfg │ ├── lpif_x1_h1.cfg │ ├── lpif_x2_asym1.cfg │ ├── lpif_x2_f1.cfg │ ├── lpif_x2_h1.cfg │ ├── lpif_x4_asym1.cfg │ ├── lpif_x4_asym2.cfg │ ├── lpif_x4_f1.cfg │ ├── lpif_x4_f2.cfg │ ├── lpif_x4_h1.cfg │ ├── lpif_x4_h2.cfg │ ├── lpif_x4_q2.cfg │ ├── lpif_x8_asym1.cfg │ ├── lpif_x8_asym2.cfg │ ├── lpif_x8_f1.cfg │ ├── lpif_x8_f2.cfg │ ├── lpif_x8_h1.cfg │ ├── lpif_x8_h2.cfg │ └── lpif_x8_q2.cfg │ ├── lpif.f │ ├── lpif.sv │ ├── lpif_configs.svh │ ├── lpif_ctl.sv │ ├── lpif_lpbk.sv │ ├── lpif_lsm.sv │ ├── lpif_pipe_stage.sv │ ├── lpif_pipeline.sv │ ├── lpif_prot_neg.sv │ ├── lpif_txrx.sv │ ├── lpif_txrx │ ├── lpif_txrx_x16_f1_info.txt │ ├── lpif_txrx_x16_f1_master.f │ ├── lpif_txrx_x16_f1_master_concat.sv │ ├── lpif_txrx_x16_f1_master_name.sv │ ├── lpif_txrx_x16_f1_master_top.sv │ ├── lpif_txrx_x16_f1_slave.f │ ├── lpif_txrx_x16_f1_slave_concat.sv │ ├── lpif_txrx_x16_f1_slave_name.sv │ ├── lpif_txrx_x16_f1_slave_top.sv │ ├── lpif_txrx_x16_f2_info.txt │ ├── lpif_txrx_x16_f2_master.f │ ├── lpif_txrx_x16_f2_master_concat.sv │ ├── lpif_txrx_x16_f2_master_name.sv │ ├── lpif_txrx_x16_f2_master_top.sv │ ├── lpif_txrx_x16_f2_slave.f │ ├── lpif_txrx_x16_f2_slave_concat.sv │ ├── lpif_txrx_x16_f2_slave_name.sv │ ├── lpif_txrx_x16_f2_slave_top.sv │ ├── lpif_txrx_x16_h1_info.txt │ ├── lpif_txrx_x16_h1_master.f │ ├── lpif_txrx_x16_h1_master_concat.sv │ ├── lpif_txrx_x16_h1_master_name.sv │ ├── lpif_txrx_x16_h1_master_top.sv │ ├── lpif_txrx_x16_h1_slave.f │ ├── lpif_txrx_x16_h1_slave_concat.sv │ ├── lpif_txrx_x16_h1_slave_name.sv │ ├── lpif_txrx_x16_h1_slave_top.sv │ ├── lpif_txrx_x16_h2_info.txt │ ├── lpif_txrx_x16_h2_master.f │ ├── lpif_txrx_x16_h2_master_concat.sv │ ├── lpif_txrx_x16_h2_master_name.sv │ ├── lpif_txrx_x16_h2_master_top.sv │ ├── lpif_txrx_x16_h2_slave.f │ ├── lpif_txrx_x16_h2_slave_concat.sv │ ├── lpif_txrx_x16_h2_slave_name.sv │ ├── lpif_txrx_x16_h2_slave_top.sv │ ├── lpif_txrx_x16_q2_info.txt │ ├── lpif_txrx_x16_q2_master.f │ ├── lpif_txrx_x16_q2_master_concat.sv │ ├── lpif_txrx_x16_q2_master_name.sv │ ├── lpif_txrx_x16_q2_master_top.sv │ ├── lpif_txrx_x16_q2_slave.f │ ├── lpif_txrx_x16_q2_slave_concat.sv │ ├── lpif_txrx_x16_q2_slave_name.sv │ ├── lpif_txrx_x16_q2_slave_top.sv │ ├── lpif_txrx_x1_f1_info.txt │ ├── lpif_txrx_x1_f1_master.f │ ├── lpif_txrx_x1_f1_master_concat.sv │ ├── lpif_txrx_x1_f1_master_name.sv │ ├── lpif_txrx_x1_f1_master_top.sv │ ├── lpif_txrx_x1_f1_slave.f │ ├── lpif_txrx_x1_f1_slave_concat.sv │ ├── lpif_txrx_x1_f1_slave_name.sv │ ├── lpif_txrx_x1_f1_slave_top.sv │ ├── lpif_txrx_x1_h1_info.txt │ ├── lpif_txrx_x1_h1_master.f │ ├── lpif_txrx_x1_h1_master_concat.sv │ ├── lpif_txrx_x1_h1_master_name.sv │ ├── lpif_txrx_x1_h1_master_top.sv │ ├── lpif_txrx_x1_h1_slave.f │ ├── lpif_txrx_x1_h1_slave_concat.sv │ ├── lpif_txrx_x1_h1_slave_name.sv │ ├── lpif_txrx_x1_h1_slave_top.sv │ ├── lpif_txrx_x2_f1_info.txt │ ├── lpif_txrx_x2_f1_master.f │ ├── lpif_txrx_x2_f1_master_concat.sv │ ├── lpif_txrx_x2_f1_master_name.sv │ ├── lpif_txrx_x2_f1_master_top.sv │ ├── lpif_txrx_x2_f1_slave.f │ ├── lpif_txrx_x2_f1_slave_concat.sv │ ├── lpif_txrx_x2_f1_slave_name.sv │ ├── lpif_txrx_x2_f1_slave_top.sv │ ├── lpif_txrx_x2_h1_info.txt │ ├── lpif_txrx_x2_h1_master.f │ ├── lpif_txrx_x2_h1_master_concat.sv │ ├── lpif_txrx_x2_h1_master_name.sv │ ├── lpif_txrx_x2_h1_master_top.sv │ ├── lpif_txrx_x2_h1_slave.f │ ├── lpif_txrx_x2_h1_slave_concat.sv │ ├── lpif_txrx_x2_h1_slave_name.sv │ ├── lpif_txrx_x2_h1_slave_top.sv │ ├── lpif_txrx_x4_f1_info.txt │ ├── lpif_txrx_x4_f1_master.f │ ├── lpif_txrx_x4_f1_master_concat.sv │ ├── lpif_txrx_x4_f1_master_name.sv │ ├── lpif_txrx_x4_f1_master_top.sv │ ├── lpif_txrx_x4_f1_slave.f │ ├── lpif_txrx_x4_f1_slave_concat.sv │ ├── lpif_txrx_x4_f1_slave_name.sv │ ├── lpif_txrx_x4_f1_slave_top.sv │ ├── lpif_txrx_x4_f2_info.txt │ ├── lpif_txrx_x4_f2_master.f │ ├── lpif_txrx_x4_f2_master_concat.sv │ ├── lpif_txrx_x4_f2_master_name.sv │ ├── lpif_txrx_x4_f2_master_top.sv │ ├── lpif_txrx_x4_f2_slave.f │ ├── lpif_txrx_x4_f2_slave_concat.sv │ ├── lpif_txrx_x4_f2_slave_name.sv │ ├── lpif_txrx_x4_f2_slave_top.sv │ ├── lpif_txrx_x4_h1_info.txt │ ├── lpif_txrx_x4_h1_master.f │ ├── lpif_txrx_x4_h1_master_concat.sv │ ├── lpif_txrx_x4_h1_master_name.sv │ ├── lpif_txrx_x4_h1_master_top.sv │ ├── lpif_txrx_x4_h1_slave.f │ ├── lpif_txrx_x4_h1_slave_concat.sv │ ├── lpif_txrx_x4_h1_slave_name.sv │ ├── lpif_txrx_x4_h1_slave_top.sv │ ├── lpif_txrx_x4_h2_info.txt │ ├── lpif_txrx_x4_h2_master.f │ ├── lpif_txrx_x4_h2_master_concat.sv │ ├── lpif_txrx_x4_h2_master_name.sv │ ├── lpif_txrx_x4_h2_master_top.sv │ ├── lpif_txrx_x4_h2_slave.f │ ├── lpif_txrx_x4_h2_slave_concat.sv │ ├── lpif_txrx_x4_h2_slave_name.sv │ ├── lpif_txrx_x4_h2_slave_top.sv │ ├── lpif_txrx_x4_q2_info.txt │ ├── lpif_txrx_x4_q2_master.f │ ├── lpif_txrx_x4_q2_master_concat.sv │ ├── lpif_txrx_x4_q2_master_name.sv │ ├── lpif_txrx_x4_q2_master_top.sv │ ├── lpif_txrx_x4_q2_slave.f │ ├── lpif_txrx_x4_q2_slave_concat.sv │ ├── lpif_txrx_x4_q2_slave_name.sv │ ├── lpif_txrx_x4_q2_slave_top.sv │ ├── lpif_txrx_x8_f1_info.txt │ ├── lpif_txrx_x8_f1_master.f │ ├── lpif_txrx_x8_f1_master_concat.sv │ ├── lpif_txrx_x8_f1_master_name.sv │ ├── lpif_txrx_x8_f1_master_top.sv │ ├── lpif_txrx_x8_f1_slave.f │ ├── lpif_txrx_x8_f1_slave_concat.sv │ ├── lpif_txrx_x8_f1_slave_name.sv │ ├── lpif_txrx_x8_f1_slave_top.sv │ ├── lpif_txrx_x8_f2_info.txt │ ├── lpif_txrx_x8_f2_master.f │ ├── lpif_txrx_x8_f2_master_concat.sv │ ├── lpif_txrx_x8_f2_master_name.sv │ ├── lpif_txrx_x8_f2_master_top.sv │ ├── lpif_txrx_x8_f2_slave.f │ ├── lpif_txrx_x8_f2_slave_concat.sv │ ├── lpif_txrx_x8_f2_slave_name.sv │ ├── lpif_txrx_x8_f2_slave_top.sv │ ├── lpif_txrx_x8_h1_info.txt │ ├── lpif_txrx_x8_h1_master.f │ ├── lpif_txrx_x8_h1_master_concat.sv │ ├── lpif_txrx_x8_h1_master_name.sv │ ├── lpif_txrx_x8_h1_master_top.sv │ ├── lpif_txrx_x8_h1_slave.f │ ├── lpif_txrx_x8_h1_slave_concat.sv │ ├── lpif_txrx_x8_h1_slave_name.sv │ ├── lpif_txrx_x8_h1_slave_top.sv │ ├── lpif_txrx_x8_h2_info.txt │ ├── lpif_txrx_x8_h2_master.f │ ├── lpif_txrx_x8_h2_master_concat.sv │ ├── lpif_txrx_x8_h2_master_name.sv │ ├── lpif_txrx_x8_h2_master_top.sv │ ├── lpif_txrx_x8_h2_slave.f │ ├── lpif_txrx_x8_h2_slave_concat.sv │ ├── lpif_txrx_x8_h2_slave_name.sv │ ├── lpif_txrx_x8_h2_slave_top.sv │ ├── lpif_txrx_x8_q2_info.txt │ ├── lpif_txrx_x8_q2_master.f │ ├── lpif_txrx_x8_q2_master_concat.sv │ ├── lpif_txrx_x8_q2_master_name.sv │ ├── lpif_txrx_x8_q2_master_top.sv │ ├── lpif_txrx_x8_q2_slave.f │ ├── lpif_txrx_x8_q2_slave_concat.sv │ ├── lpif_txrx_x8_q2_slave_name.sv │ └── lpif_txrx_x8_q2_slave_top.sv │ └── lpif_txrx_asym │ ├── lpif_txrx_x16_asym1_full_info.txt │ ├── lpif_txrx_x16_asym1_full_master.f │ ├── lpif_txrx_x16_asym1_full_master_concat.sv │ ├── lpif_txrx_x16_asym1_full_master_name.sv │ ├── lpif_txrx_x16_asym1_full_master_top.sv │ ├── lpif_txrx_x16_asym1_full_slave.f │ ├── lpif_txrx_x16_asym1_full_slave_concat.sv │ ├── lpif_txrx_x16_asym1_full_slave_name.sv │ ├── lpif_txrx_x16_asym1_full_slave_top.sv │ ├── lpif_txrx_x16_asym1_half_info.txt │ ├── lpif_txrx_x16_asym1_half_master.f │ ├── lpif_txrx_x16_asym1_half_master_concat.sv │ ├── lpif_txrx_x16_asym1_half_master_name.sv │ ├── lpif_txrx_x16_asym1_half_master_top.sv │ ├── lpif_txrx_x16_asym1_half_slave.f │ ├── lpif_txrx_x16_asym1_half_slave_concat.sv │ ├── lpif_txrx_x16_asym1_half_slave_name.sv │ ├── lpif_txrx_x16_asym1_half_slave_top.sv │ ├── lpif_txrx_x16_asym2_full_info.txt │ ├── lpif_txrx_x16_asym2_full_master.f │ ├── lpif_txrx_x16_asym2_full_master_concat.sv │ ├── lpif_txrx_x16_asym2_full_master_name.sv │ ├── lpif_txrx_x16_asym2_full_master_top.sv │ ├── lpif_txrx_x16_asym2_full_slave.f │ ├── lpif_txrx_x16_asym2_full_slave_concat.sv │ ├── lpif_txrx_x16_asym2_full_slave_name.sv │ ├── lpif_txrx_x16_asym2_full_slave_top.sv │ ├── lpif_txrx_x16_asym2_half_info.txt │ ├── lpif_txrx_x16_asym2_half_master.f │ ├── lpif_txrx_x16_asym2_half_master_concat.sv │ ├── lpif_txrx_x16_asym2_half_master_name.sv │ ├── lpif_txrx_x16_asym2_half_master_top.sv │ ├── lpif_txrx_x16_asym2_half_slave.f │ ├── lpif_txrx_x16_asym2_half_slave_concat.sv │ ├── lpif_txrx_x16_asym2_half_slave_name.sv │ ├── lpif_txrx_x16_asym2_half_slave_top.sv │ ├── lpif_txrx_x16_asym2_quarter_info.txt │ ├── lpif_txrx_x16_asym2_quarter_master.f │ ├── lpif_txrx_x16_asym2_quarter_master_concat.sv │ ├── lpif_txrx_x16_asym2_quarter_master_name.sv │ ├── lpif_txrx_x16_asym2_quarter_master_top.sv │ ├── lpif_txrx_x16_asym2_quarter_slave.f │ ├── lpif_txrx_x16_asym2_quarter_slave_concat.sv │ ├── lpif_txrx_x16_asym2_quarter_slave_name.sv │ ├── lpif_txrx_x16_asym2_quarter_slave_top.sv │ ├── lpif_txrx_x1_asym1_full_info.txt │ ├── lpif_txrx_x1_asym1_full_master.f │ ├── lpif_txrx_x1_asym1_full_master_concat.sv │ ├── lpif_txrx_x1_asym1_full_master_name.sv │ ├── lpif_txrx_x1_asym1_full_master_top.sv │ ├── lpif_txrx_x1_asym1_full_slave.f │ ├── lpif_txrx_x1_asym1_full_slave_concat.sv │ ├── lpif_txrx_x1_asym1_full_slave_name.sv │ ├── lpif_txrx_x1_asym1_full_slave_top.sv │ ├── lpif_txrx_x1_asym1_half_info.txt │ ├── lpif_txrx_x1_asym1_half_master.f │ ├── lpif_txrx_x1_asym1_half_master_concat.sv │ ├── lpif_txrx_x1_asym1_half_master_name.sv │ ├── lpif_txrx_x1_asym1_half_master_top.sv │ ├── lpif_txrx_x1_asym1_half_slave.f │ ├── lpif_txrx_x1_asym1_half_slave_concat.sv │ ├── lpif_txrx_x1_asym1_half_slave_name.sv │ ├── lpif_txrx_x1_asym1_half_slave_top.sv │ ├── lpif_txrx_x2_asym1_full_info.txt │ ├── lpif_txrx_x2_asym1_full_master.f │ ├── lpif_txrx_x2_asym1_full_master_concat.sv │ ├── lpif_txrx_x2_asym1_full_master_name.sv │ ├── lpif_txrx_x2_asym1_full_master_top.sv │ ├── lpif_txrx_x2_asym1_full_slave.f │ ├── lpif_txrx_x2_asym1_full_slave_concat.sv │ ├── lpif_txrx_x2_asym1_full_slave_name.sv │ ├── lpif_txrx_x2_asym1_full_slave_top.sv │ ├── lpif_txrx_x2_asym1_half_info.txt │ ├── lpif_txrx_x2_asym1_half_master.f │ ├── lpif_txrx_x2_asym1_half_master_concat.sv │ ├── lpif_txrx_x2_asym1_half_master_name.sv │ ├── lpif_txrx_x2_asym1_half_master_top.sv │ ├── lpif_txrx_x2_asym1_half_slave.f │ ├── lpif_txrx_x2_asym1_half_slave_concat.sv │ ├── lpif_txrx_x2_asym1_half_slave_name.sv │ ├── lpif_txrx_x2_asym1_half_slave_top.sv │ ├── lpif_txrx_x4_asym1_full_info.txt │ ├── lpif_txrx_x4_asym1_full_master.f │ ├── lpif_txrx_x4_asym1_full_master_concat.sv │ ├── lpif_txrx_x4_asym1_full_master_name.sv │ ├── lpif_txrx_x4_asym1_full_master_top.sv │ ├── lpif_txrx_x4_asym1_full_slave.f │ ├── lpif_txrx_x4_asym1_full_slave_concat.sv │ ├── lpif_txrx_x4_asym1_full_slave_name.sv │ ├── lpif_txrx_x4_asym1_full_slave_top.sv │ ├── lpif_txrx_x4_asym1_half_info.txt │ ├── lpif_txrx_x4_asym1_half_master.f │ ├── lpif_txrx_x4_asym1_half_master_concat.sv │ ├── lpif_txrx_x4_asym1_half_master_name.sv │ ├── lpif_txrx_x4_asym1_half_master_top.sv │ ├── lpif_txrx_x4_asym1_half_slave.f │ ├── lpif_txrx_x4_asym1_half_slave_concat.sv │ ├── lpif_txrx_x4_asym1_half_slave_name.sv │ ├── lpif_txrx_x4_asym1_half_slave_top.sv │ ├── lpif_txrx_x4_asym2_full_info.txt │ ├── lpif_txrx_x4_asym2_full_master.f │ ├── lpif_txrx_x4_asym2_full_master_concat.sv │ ├── lpif_txrx_x4_asym2_full_master_name.sv │ ├── lpif_txrx_x4_asym2_full_master_top.sv │ ├── lpif_txrx_x4_asym2_full_slave.f │ ├── lpif_txrx_x4_asym2_full_slave_concat.sv │ ├── lpif_txrx_x4_asym2_full_slave_name.sv │ ├── lpif_txrx_x4_asym2_full_slave_top.sv │ ├── lpif_txrx_x4_asym2_half_info.txt │ ├── lpif_txrx_x4_asym2_half_master.f │ ├── lpif_txrx_x4_asym2_half_master_concat.sv │ ├── lpif_txrx_x4_asym2_half_master_name.sv │ ├── lpif_txrx_x4_asym2_half_master_top.sv │ ├── lpif_txrx_x4_asym2_half_slave.f │ ├── lpif_txrx_x4_asym2_half_slave_concat.sv │ ├── lpif_txrx_x4_asym2_half_slave_name.sv │ ├── lpif_txrx_x4_asym2_half_slave_top.sv │ ├── lpif_txrx_x4_asym2_quarter_info.txt │ ├── lpif_txrx_x4_asym2_quarter_master.f │ ├── lpif_txrx_x4_asym2_quarter_master_concat.sv │ ├── lpif_txrx_x4_asym2_quarter_master_name.sv │ ├── lpif_txrx_x4_asym2_quarter_master_top.sv │ ├── lpif_txrx_x4_asym2_quarter_slave.f │ ├── lpif_txrx_x4_asym2_quarter_slave_concat.sv │ ├── lpif_txrx_x4_asym2_quarter_slave_name.sv │ ├── lpif_txrx_x4_asym2_quarter_slave_top.sv │ ├── lpif_txrx_x8_asym1_full_info.txt │ ├── lpif_txrx_x8_asym1_full_master.f │ ├── lpif_txrx_x8_asym1_full_master_concat.sv │ ├── lpif_txrx_x8_asym1_full_master_name.sv │ ├── lpif_txrx_x8_asym1_full_master_top.sv │ ├── lpif_txrx_x8_asym1_full_slave.f │ ├── lpif_txrx_x8_asym1_full_slave_concat.sv │ ├── lpif_txrx_x8_asym1_full_slave_name.sv │ ├── lpif_txrx_x8_asym1_full_slave_top.sv │ ├── lpif_txrx_x8_asym1_half_info.txt │ ├── lpif_txrx_x8_asym1_half_master.f │ ├── lpif_txrx_x8_asym1_half_master_concat.sv │ ├── lpif_txrx_x8_asym1_half_master_name.sv │ ├── lpif_txrx_x8_asym1_half_master_top.sv │ ├── lpif_txrx_x8_asym1_half_slave.f │ ├── lpif_txrx_x8_asym1_half_slave_concat.sv │ ├── lpif_txrx_x8_asym1_half_slave_name.sv │ ├── lpif_txrx_x8_asym1_half_slave_top.sv │ ├── lpif_txrx_x8_asym2_full_info.txt │ ├── lpif_txrx_x8_asym2_full_master.f │ ├── lpif_txrx_x8_asym2_full_master_concat.sv │ ├── lpif_txrx_x8_asym2_full_master_name.sv │ ├── lpif_txrx_x8_asym2_full_master_top.sv │ ├── lpif_txrx_x8_asym2_full_slave.f │ ├── lpif_txrx_x8_asym2_full_slave_concat.sv │ ├── lpif_txrx_x8_asym2_full_slave_name.sv │ ├── lpif_txrx_x8_asym2_full_slave_top.sv │ ├── lpif_txrx_x8_asym2_half_info.txt │ ├── lpif_txrx_x8_asym2_half_master.f │ ├── lpif_txrx_x8_asym2_half_master_concat.sv │ ├── lpif_txrx_x8_asym2_half_master_name.sv │ ├── lpif_txrx_x8_asym2_half_master_top.sv │ ├── lpif_txrx_x8_asym2_half_slave.f │ ├── lpif_txrx_x8_asym2_half_slave_concat.sv │ ├── lpif_txrx_x8_asym2_half_slave_name.sv │ ├── lpif_txrx_x8_asym2_half_slave_top.sv │ ├── lpif_txrx_x8_asym2_quarter_info.txt │ ├── lpif_txrx_x8_asym2_quarter_master.f │ ├── lpif_txrx_x8_asym2_quarter_master_concat.sv │ ├── lpif_txrx_x8_asym2_quarter_master_name.sv │ ├── lpif_txrx_x8_asym2_quarter_master_top.sv │ ├── lpif_txrx_x8_asym2_quarter_slave.f │ ├── lpif_txrx_x8_asym2_quarter_slave_concat.sv │ ├── lpif_txrx_x8_asym2_quarter_slave_name.sv │ └── lpif_txrx_x8_asym2_quarter_slave_top.sv ├── run_smoke.sh └── spi-aib ├── README.txt ├── doc ├── Chiplet_SPI_User_Guide_v1_0.pdf └── SPI_User_guide_0_8.pptx ├── dv ├── flist │ ├── aib2.cf │ ├── maib.cf │ ├── ms_v1.cf │ ├── spi_rtl.cf │ └── tb_rtl.cf ├── interface │ ├── avalon_mm_if.sv │ ├── dut_app_reg.inc │ ├── dut_emib1.inc │ ├── dut_emib2.inc │ ├── dut_if_mac.sv │ ├── dut_ms1_port.inc │ ├── dut_ms2_port.inc │ ├── dut_mspi_port_ch.inc │ ├── dut_sl1_port.inc │ ├── dut_sl2_port.inc │ ├── dut_sl_gen1.inc │ ├── dut_sspi_1_port_ch.inc │ ├── dut_sspi_port_ch.inc │ └── spi_if.sv ├── sims │ ├── README.txt │ ├── run_compile │ └── test.inc ├── tb │ ├── top_tb.sv │ └── top_tb_declare.inc └── test │ ├── data │ └── maib_prog.inc │ ├── task │ ├── agent.sv │ └── spi_task.sv │ └── test_cases │ ├── app_reg_test.inc │ ├── basic_spi_test.inc │ ├── fifo2x_test.inc │ ├── non_auto_test.inc │ └── wrap_around_test.inc ├── rtl ├── app_avmm_csr.sv ├── mspi_avmm_csr.sv ├── mspi_avmm_intf.sv ├── mspi_intf.sv ├── reg_avmm_csr.sv ├── spi_bitsync.sv ├── spi_buf_ram.sv ├── spi_master.sv ├── spi_rstnsync.sv ├── spi_slave.sv ├── sspi_avmm_csr.sv ├── sspi_avmm_intf.sv └── sspi_intf.sv └── syn └── quartus ├── sdc_files ├── spi_master.sdc └── spi_slave.sdc ├── spi_master.qpf ├── spi_master.qsf ├── spi_slave.qpf └── spi_slave.qsf /CHIPS Alliance - CCLA v7.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/CHIPS Alliance - CCLA v7.pdf -------------------------------------------------------------------------------- /axi4-mm/.gitignore: -------------------------------------------------------------------------------- 1 | .simvision/ 2 | *.history 3 | *.log 4 | dut/ 5 | waves.shm/ 6 | xcelium.d/ 7 | xmverilog.key 8 | archive* 9 | *_rawdata_map.svi 10 | -------------------------------------------------------------------------------- /axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_master_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_master_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_slave_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_slave_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_lite_a32_d32/axi_lite_a32_d32_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_master_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_master_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_slave_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_slave_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_master_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_master_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_slave_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_slave_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/axi_mm_master.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/axi_mm_master_top.sv 2 | // Generated Files 3 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master_top.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master_concat.sv 5 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master_name.sv 6 | 7 | // Generated Files 8 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master_top.sv 9 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master_concat.sv 10 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master_name.sv 11 | 12 | // Logic Link files 13 | -f ${PROJ_DIR}/llink/rtl/llink.f 14 | 15 | // Common Files 16 | -f ${PROJ_DIR}/common/rtl/common.f 17 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/axi_mm_slave.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/axi_mm_slave_top.sv 2 | // Generated Files 3 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave_top.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave_concat.sv 5 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave_name.sv 6 | 7 | // Generated Files 8 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave_top.sv 9 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave_concat.sv 10 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave_name.sv 11 | 12 | // Logic Link files 13 | -f ${PROJ_DIR}/llink/rtl/llink.f 14 | 15 | // Common Files 16 | -f ${PROJ_DIR}/common/rtl/common.f 17 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1/aximm_ll_multi_tier1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave_top.sv 3 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave_concat.sv 4 | ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2/aximm_ll_multi_tier2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/build.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/bash 2 | 3 | /usr/bin/emacs -batch axi_mm_master_top.sv -f verilog-auto -f save-buffer 4 | /usr/bin/emacs -batch axi_mm_slave_top.sv -f verilog-auto -f save-buffer 5 | -------------------------------------------------------------------------------- /axi4-mm/axi_mm_multi/compile.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/bash 2 | 3 | xmverilog \ 4 | -f ${PROJ_DIR}/axi4-mm/axi_mm_multi/axi_mm_master.f \ 5 | -f ${PROJ_DIR}/axi4-mm/axi_mm_multi/axi_mm_slave.f 6 | 7 | -------------------------------------------------------------------------------- /axi4-mm/build_examples.sh: -------------------------------------------------------------------------------- 1 | 2 | ## Build DUT 3 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-mm/cfg/axi_lite_a32_d32.cfg 4 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-mm/cfg/axi_mm_a32_d128.cfg 5 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-mm/cfg/axi_mm_a32_d128_packet.cfg 6 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-mm/cfg/axi_mm_a32_d128_packet_gen1.cfg 7 | 8 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-mm/cfg/aximm_ll_multi_tier1.cfg --odir ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier1 9 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-mm/cfg/aximm_ll_multi_tier2.cfg --odir ${PROJ_DIR}/axi4-mm/axi_mm_multi/aximm_ll_multi_tier2 10 | cd ${PROJ_DIR}/axi4-mm/axi_mm_multi; ./build.sh; cd ~- 11 | -------------------------------------------------------------------------------- /axi4-mm/cfg/aximm_ll_multi_tier1.cfg: -------------------------------------------------------------------------------- 1 | MODULE aximm_ll_multi_tier1 2 | 3 | 4 | // PHY and AIB Configuration 5 | NUM_CHAN 1 6 | CHAN_TYPE Tiered //Gen1Only, Gen2Only, Gen2, AIBO 7 | 8 | // Packetization 9 | TX_ENABLE_PACKETIZATION True 10 | RX_ENABLE_PACKETIZATION True 11 | TX_PACKET_MAX_SIZE 79 // Number of bits to packetize to. 12 | RX_PACKET_MAX_SIZE 79 // Number of bits to packetize to. 13 | 14 | PACKETIZATION_PACKING_EN True // If True, enable packing which makes better use of the BW 15 | 16 | llink AR 17 | { 18 | TX_FIFO_DEPTH 1 19 | RX_FIFO_DEPTH 8 20 | 21 | output user_arid 4 22 | output user_arsize 3 23 | output user_arlen 8 24 | output user_arburst 2 25 | output user_araddr 32 26 | output user_arvalid valid 27 | input user_arready ready 28 | } 29 | 30 | llink AW 31 | { 32 | TX_FIFO_DEPTH 1 33 | RX_FIFO_DEPTH 8 34 | 35 | output user_awid 4 36 | output user_awsize 3 37 | output user_awlen 8 38 | output user_awburst 2 39 | output user_awaddr 32 40 | output user_awvalid valid 41 | input user_awready ready 42 | } 43 | 44 | llink W 45 | { 46 | TX_FIFO_DEPTH 1 47 | RX_FIFO_DEPTH 8 48 | 49 | output user_wid 4 50 | output user_wdata 64 51 | output user_wstrb 8 52 | output user_wlast 53 | output user_wvalid valid 54 | input user_wready ready 55 | } 56 | 57 | llink R 58 | { 59 | TX_FIFO_DEPTH 1 60 | RX_FIFO_DEPTH 8 61 | 62 | input user_rid 4 63 | input user_rdata 64 64 | input user_rlast 65 | input user_rresp 2 66 | input user_rvalid valid 67 | output user_rready ready 68 | } 69 | llink B 70 | { 71 | TX_FIFO_DEPTH 1 72 | RX_FIFO_DEPTH 8 73 | 74 | input user_bid 4 75 | input user_bresp 2 76 | input user_bvalid valid 77 | output user_bready ready 78 | } 79 | -------------------------------------------------------------------------------- /axi4-mm/doc/README.txt: -------------------------------------------------------------------------------- 1 | The axi4-mm and axi4-st are documented in the same userguide. 2 | It is here: 3 | 4 | ../../axi4-st/doc/llink_ug.pdf 5 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_packet_gen1_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_packet_gen1_tb/axi_mm_a32_d128_packet_gen1_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_mm_a32_d128_packet_gen1_tb.sv 3 | ${PROJ_DIR}/common/dv/p2p_lite.sv 4 | +libverbose 5 | +libext+.v 6 | +define+FOR_SIM_ONLY 7 | -f ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_master.f 8 | -f ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet_gen1/axi_mm_a32_d128_packet_gen1_slave.f 9 | -f ${PROJ_DIR}/ca/rtl/ca.f 10 | -y . 11 | -l axi_mm_a32_d128_packet_gen1_tb.log 12 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_packet_gen1_tb/run_axi_mm_a32_d128_packet_gen1_tb: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | 4 | #Run Sim 5 | xmverilog -f axi_mm_a32_d128_packet_gen1_tb.f $* 6 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_packet_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_packet_tb/axi_mm_a32_d128_packet_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_mm_a32_d128_packet_tb.sv 3 | +libverbose 4 | +libext+.v 5 | +define+FOR_SIM_ONLY 6 | -f ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master.f 7 | -f ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave.f 8 | -y . 9 | -l axi_mm_a32_d128_packet_tb.log 10 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_packet_tb/run_axi_mm_a32_d128_packet_tb: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | #Run Sim 4 | xmverilog -f axi_mm_a32_d128_packet_tb.f $* 5 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_tb/axi_mm_a32_d128_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_mm_a32_d128_tb.sv 3 | +libverbose 4 | +libext+.v 5 | +define+FOR_SIM_ONLY 6 | -f ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_master.f 7 | -f ${PROJ_DIR}/axi4-mm/axi_mm_a32_d128/axi_mm_a32_d128_slave.f 8 | -y . 9 | -l axi_mm_a32_d128_tb.log 10 | -------------------------------------------------------------------------------- /axi4-mm/dv/axi_mm_a32_d128_tb/run_axi_mm_a32_d128_tb: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | #Run Sim 4 | xmverilog -f axi_mm_a32_d128_tb.f $* 5 | -------------------------------------------------------------------------------- /axi4-mm/full_examples/flist/axi_mm_d128_h2h.f: -------------------------------------------------------------------------------- 1 | ${SIM_DIR}/../common/aximm_aib_top.v 2 | ${SIM_DIR}/../common/top_aib.sv 3 | ${SIM_DIR}/../common/aximm_d128_h2h_wrapper_top.v 4 | #${SIM_DIR}/../common/aximm_app.v 5 | ${SIM_DIR}/../common/aximm_rand_gen.v 6 | ${SIM_DIR}/../common/axi_mm_patgen_top.v 7 | ${SIM_DIR}/../common/axi_mm_patchkr_top.v 8 | ${SIM_DIR}/../common/aximm_wr_ctrl.v 9 | ${SIM_DIR}/../common/aximm_incr_gen.v 10 | ${SIM_DIR}/../common/mm_csr_ctrl.v 11 | ${SIM_DIR}/../common/axi_mm_csr.v 12 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 13 | ${SIM_DIR}/../common/aximm_follower_app.v 14 | ${SIM_DIR}/../common/aximm_leader_app.v 15 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 16 | +libverbose 17 | +libext+.v 18 | -f ${tbench_dir}/axi_mm/axi_mm_slave.f 19 | -f ${tbench_dir}/axi_mm/axi_mm_master.f 20 | -f ${PROJ_DIR}/ca/rtl/ca.f 21 | -------------------------------------------------------------------------------- /axi4-mm/full_examples/flist/tb_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | +incdir+${AIB_ROOT}/dv/tb 5 | +incdir+${AIB_ROOT}/dv/interface 6 | +incdir+${AIB_ROOT}/dv/test/task 7 | ${RTL_ROOT}/../dv/emib/emib_ch_m1s2.sv 8 | ${RTL_ROOT}/../dv/emib/emib_ch_m2s2.sv 9 | ${RTL_ROOT}/../dv/emib/emib_m1s2.sv 10 | ${RTL_ROOT}/../dv/emib/aliasv.sv 11 | ${RTL_ROOT}/../dv/emib/emib_ch_m2s1.sv 12 | ${RTL_ROOT}/../dv/emib/emib_m2s1.sv 13 | ${RTL_ROOT}/../dv/emib/emib_m2s2.sv 14 | ${RTL_ROOT}/../dv/interface/dut_if_mac.sv 15 | ${RTL_ROOT}/../dv/interface/avalon_mm_if.sv 16 | 17 | ${tbench_dir}/top_tb.v 18 | -------------------------------------------------------------------------------- /axi4-mm/full_examples_gpio/flist/axi_mm_d128_gpio.f: -------------------------------------------------------------------------------- 1 | ${SIM_DIR}/../common/aximm_gpiophy_top.v 2 | ${SIM_DIR}/../common/aximm_d128_gpiophy_wrapper_top.v 3 | ${SIM_DIR}/../common/aximm_rand_gen.v 4 | ${SIM_DIR}/../common/axi_mm_patgen_top.v 5 | ${SIM_DIR}/../common/axi_mm_patchkr_top.v 6 | ${SIM_DIR}/../common/aximm_wr_ctrl.v 7 | ${SIM_DIR}/../common/aximm_incr_gen.v 8 | ${SIM_DIR}/../common/mm_csr_ctrl.v 9 | ${SIM_DIR}/../common/axi_mm_csr.v 10 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 11 | ${SIM_DIR}/../common/aximm_follower_app.v 12 | ${SIM_DIR}/../common/aximm_leader_app.v 13 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 14 | +libverbose 15 | +libext+.v 16 | -f ${tbench_dir}/aximm_ll_dut_new/axi_mm_slave.f 17 | -f ${tbench_dir}/aximm_ll_dut_new/axi_mm_master.f 18 | -f ${PROJ_DIR}/ca/rtl/ca.f 19 | -------------------------------------------------------------------------------- /axi4-mm/full_examples_gpio/flist/axi_mm_d128_gpio_dual.f: -------------------------------------------------------------------------------- 1 | ${SIM_DIR}/../common/aximm_gpiophy_dual_top.v 2 | ${SIM_DIR}/../common/aximm_d128_gpiophy_dual_wrapper_top.v 3 | ${SIM_DIR}/../common/aximm_rand_gen.v 4 | ${SIM_DIR}/../common/axi_mm_patgen_top.v 5 | ${SIM_DIR}/../common/axi_mm_patchkr_top.v 6 | ${SIM_DIR}/../common/aximm_wr_ctrl.v 7 | ${SIM_DIR}/../common/aximm_incr_gen.v 8 | ${SIM_DIR}/../common/mm_csr_ctrl.v 9 | ${SIM_DIR}/../common/axi_mm_csr.v 10 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 11 | ${SIM_DIR}/../common/aximm_follower_app.v 12 | ${SIM_DIR}/../common/aximm_leader_app.v 13 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 14 | +libverbose 15 | +libext+.v 16 | -f ${tbench_dir}/aximm_ll_dut_new/axi_mm_slave.f 17 | -f ${tbench_dir}/aximm_ll_dut_new/axi_mm_master.f 18 | -f ${PROJ_DIR}/ca/rtl/ca.f 19 | -------------------------------------------------------------------------------- /axi4-mm/full_examples_gpio/flist/tb_gpio_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | 5 | ${tbench_dir}/top_tb.v 6 | -------------------------------------------------------------------------------- /axi4-st-duplex/README.txt: -------------------------------------------------------------------------------- 1 | Script code has been tested with standard Python v2.7.5 and Python v3.7.5 2 | 3 | Example invocations: 4 | python ../llink/script/dual_axist_llink_gen.py --cfg cfg/axi_dual_st_d64.cfg 5 | python ../llink/script/dual_axist_llink_gen.py --cfg cfg/axi_dual_st_d256_multichannel.cfg 6 | 7 | --cfg points to a configuration file. This can be customized but the cfg 8 | directory has examples 9 | 10 | --odir generated files are placed in the odir directory. 11 | (Optional, if not present default is "./") 12 | 13 | 14 | This will generated several files in the odir. The names depend on the module field in the 15 | cfg file. They will be: 16 | _info.txt - Text based info file. 17 | 18 | _master.f - list files. File paths are prepended ${PROJ_DIR}/llink/script/odir 19 | _master_top.sv - top level master module 20 | _master_name.sv - user interface module 21 | _master_concat.sv - phy interface module 22 | 23 | _slave.f - list files. File paths are prepended ${PROJ_DIR}/llink/script/odir 24 | _slave_top.sv - top level slave module 25 | _slave_name.sv - user interface module 26 | _slave_concat.sv - phy interface module 27 | 28 | The configuration file has many options. Note that everything is coded from the Master's 29 | perspective so that the Master's TX is necessarily the Slave's RX and the Master's RX is 30 | necessarily the Slave's TX. 31 | 32 | 33 | List of CFG: 34 | 35 | axi_dual_st_d64.cfg - Basic, simple AXI ST with 64 bit data. 1 Full AIB2.0 Channel. 36 | axi_dual_st_d256_multichannel.cfg - Basic, simple AXI ST with 256 bit data bits running on two channel AIB2.0 Gen2 Half Rate. 37 | 38 | -------------------------------------------------------------------------------- /axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_master_top.sv 3 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_master_concat.sv 4 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_slave_top.sv 3 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_slave_concat.sv 4 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_master_top.sv 3 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_master_concat.sv 4 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_slave_top.sv 3 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_slave_concat.sv 4 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d256_multichannel/axi_dual_st_d256_multichannel_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_master_top.sv 3 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_master_concat.sv 4 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_slave_top.sv 3 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_slave_concat.sv 4 | /nfs/sc/disks/swuser_work_ndoraira/csprs/cerium/aib_protocols_try/axi4-st-duplex/axi_dual_st_d64/axi_dual_st_d64_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st-duplex/build_examples.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh -f 2 | 3 | if [ -z "${PROJ_DIR}" ]; then 4 | export PROJ_DIR=`pwd`/.. 5 | fi 6 | 7 | 8 | ## Build DUT 9 | python ${PROJ_DIR}/llink/script/dual_axist_llink_gen.py --cfg ${PROJ_DIR}/axi4-st-duplex/cfg/axi_dual_st_d256_multichannel.cfg 10 | python ${PROJ_DIR}/llink/script/dual_axist_llink_gen.py --cfg ${PROJ_DIR}/axi4-st-duplex/cfg/axi_dual_st_d64.cfg 11 | 12 | -------------------------------------------------------------------------------- /axi4-st-duplex/doc/llink_duplex_ug.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/axi4-st-duplex/doc/llink_duplex_ug.pdf -------------------------------------------------------------------------------- /axi4-st-duplex/dv/README.txt: -------------------------------------------------------------------------------- 1 | modular TB for axi_dual_st_d64 and axi_dual_st_d256_multichannel. 2 | 3 | Leader and follower axi4-st-duplex connected back to back. 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /axi4-st-duplex/full_examples/README.txt: -------------------------------------------------------------------------------- 1 | example is located in axi4-st/full_examples/sims/tb_mf2.1_sh1_d256_dual cd to this area and do make run 2 | -------------------------------------------------------------------------------- /axi4-st/.gitignore: -------------------------------------------------------------------------------- 1 | .simvision/ 2 | *.history 3 | *.log 4 | dut/ 5 | waves.shm/ 6 | xcelium.d/ 7 | xmverilog.key 8 | archive* 9 | *_rawdata_map.svi 10 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_master_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_master_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_slave_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_slave_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_gen2_only/axi_st_d256_gen2_only_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d256_multichannel_full_master_name ( 19 | 20 | // st channel 21 | input logic [ 255: 0] user_tdata , 22 | input logic user_tvalid , 23 | output logic user_tready , 24 | 25 | // Logic Link Interfaces 26 | output logic user_st_vld , 27 | output logic [ 255: 0] txfifo_st_data , 28 | input logic user_st_ready , 29 | 30 | input logic m_gen2_mode 31 | 32 | ); 33 | 34 | // Connect Data 35 | 36 | assign user_st_vld = user_tvalid ; 37 | assign user_tready = user_st_ready ; 38 | assign txfifo_st_data [ 0 +: 256] = user_tdata [ 0 +: 256] ; 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_slave_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_slave_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_slave_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d256_multichannel_full_slave_name ( 19 | 20 | // st channel 21 | output logic [ 255: 0] user_tdata , 22 | output logic user_tvalid , 23 | input logic user_tready , 24 | output logic [ 0: 0] user_enable , 25 | 26 | // Logic Link Interfaces 27 | input logic user_st_vld , 28 | input logic [ 256: 0] rxfifo_st_data , 29 | output logic user_st_ready , 30 | 31 | input logic m_gen2_mode 32 | 33 | ); 34 | 35 | // Connect Data 36 | 37 | assign user_tvalid = user_st_vld ; 38 | assign user_st_ready = user_tready ; 39 | assign user_tdata [ 0 +: 256] = rxfifo_st_data [ 0 +: 256] ; 40 | assign user_enable [ 0 +: 1] = rxfifo_st_data [ 256 +: 1] ; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_master_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_master_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_master_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d256_multichannel_half_master_name ( 19 | 20 | // st channel 21 | input logic [ 511: 0] user_tdata , 22 | input logic user_tvalid , 23 | output logic user_tready , 24 | 25 | // Logic Link Interfaces 26 | output logic user_st_vld , 27 | output logic [ 511: 0] txfifo_st_data , 28 | input logic user_st_ready , 29 | 30 | input logic m_gen2_mode 31 | 32 | ); 33 | 34 | // Connect Data 35 | 36 | assign user_st_vld = user_tvalid ; 37 | assign user_tready = user_st_ready ; 38 | assign txfifo_st_data [ 0 +: 256] = user_tdata [ 0 +: 256] ; 39 | assign txfifo_st_data [ 256 +: 256] = user_tdata [ 256 +: 256] ; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d64/axi_st_d64_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_master_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_master_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d64/axi_st_d64_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_slave_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_slave_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_master_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_master_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_master_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d64_nordy_master_name ( 19 | 20 | // st channel 21 | input logic [ 7: 0] user_tkeep , 22 | input logic [ 63: 0] user_tdata , 23 | input logic user_tlast , 24 | input logic user_tvalid , 25 | 26 | // Logic Link Interfaces 27 | output logic [ 73: 0] txfifo_st_data , 28 | 29 | input logic rx_online , 30 | input logic m_gen2_mode 31 | 32 | ); 33 | 34 | // Connect Data 35 | 36 | assign user_st_vld = 1'b1 ; // user_st_vld is unused 37 | assign txfifo_st_data [ 0 +: 8] = user_tkeep [ 0 +: 8] ; 38 | assign txfifo_st_data [ 8 +: 64] = user_tdata [ 0 +: 64] ; 39 | assign txfifo_st_data [ 72 +: 1] = user_tlast ; 40 | assign txfifo_st_data [ 73 +: 1] = user_tvalid ; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_slave_top.sv 3 | ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_slave_concat.sv 4 | ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_slave_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d64_nordy_slave_name ( 19 | 20 | // st channel 21 | output logic [ 7: 0] user_tkeep , 22 | output logic [ 63: 0] user_tdata , 23 | output logic user_tlast , 24 | output logic user_tvalid , 25 | 26 | // Logic Link Interfaces 27 | input logic [ 73: 0] rxfifo_st_data , 28 | 29 | input logic rx_online , 30 | input logic m_gen2_mode 31 | 32 | ); 33 | 34 | // Connect Data 35 | 36 | // user_st_vld is unused 37 | assign user_tkeep [ 0 +: 8] = rxfifo_st_data [ 0 +: 8] ; 38 | assign user_tdata [ 0 +: 64] = rxfifo_st_data [ 8 +: 64] ; 39 | assign user_tlast = rxfifo_st_data [ 72 +: 1] ; 40 | assign user_tvalid = rx_online & rxfifo_st_data [ 73 +: 1] ; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /axi4-st/build_examples.sh: -------------------------------------------------------------------------------- 1 | 2 | ## Build DUT 3 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-st/cfg/axi_st_d64.cfg 4 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-st/cfg/axi_st_d64_nordy.cfg 5 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-st/cfg/axi_st_d256_gen1_gen2.cfg 6 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-st/cfg/axi_st_d256_multichannel.cfg 7 | python ${PROJ_DIR}/llink/script/llink_gen.py --cfg ${PROJ_DIR}/axi4-st/cfg/axi_st_d256_norm.cfg 8 | -------------------------------------------------------------------------------- /axi4-st/doc/axi4_latency_rx_buffer_sizing_guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/axi4-st/doc/axi4_latency_rx_buffer_sizing_guide.pdf -------------------------------------------------------------------------------- /axi4-st/doc/llink_ug.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/axi4-st/doc/llink_ug.pdf -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d256_gen1_gen2_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d256_gen1_gen2_tb/axi_st_d256_gen1_gen2_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_st_d256_gen1_gen2_tb.sv 3 | +libverbose 4 | +libext+.v 5 | +define+FOR_SIM_ONLY 6 | -f ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master.f 7 | -f ${PROJ_DIR}/axi4-st/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave.f 8 | -y . 9 | -l axi_st_d256_gen1_gen2_tb.log 10 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d256_gen1_gen2_tb/run_st_d256_gen1_gen2: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | #Run Sim 4 | xmverilog -f axi_st_d256_gen1_gen2_tb.f $* 5 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d256_multichannel_f2h_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d256_multichannel_f2h_tb/axi_st_d256_multichannel_f2h_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_st_d256_multichannel_f2h_tb.sv 3 | ${PROJ_DIR}/common/dv/p2p_lite.sv 4 | ${PROJ_DIR}/common/dv/marker_gen.sv 5 | +libverbose 6 | +libext+.v 7 | +define+FOR_SIM_ONLY 8 | -f ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master.f 9 | -f ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave.f 10 | -f ${PROJ_DIR}/ca/rtl/ca.f 11 | -y . 12 | -l axi_st_d256_multichannel_f2h_tb.log 13 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d256_multichannel_f2h_tb/run_axi_st_d256_multichannel_f2h_tb: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | #Run Sim 4 | xmverilog -f axi_st_d256_multichannel_f2h_tb.f $* 5 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d64_nordy_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d64_nordy_tb/axi_st_d64_nordy_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_st_d64_nordy_tb.sv 3 | +libverbose 4 | +libext+.v 5 | +define+FOR_SIM_ONLY 6 | -f ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_master.f 7 | -f ${PROJ_DIR}/axi4-st/axi_st_d64_nordy/axi_st_d64_nordy_slave.f 8 | -y . 9 | -l axi_st_d64_nordy_tb.log 10 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d64_nordy_tb/run_axi_st_d64_nordy_tb: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | #Run Sim 4 | xmverilog -f axi_st_d64_nordy_tb.f $* 5 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d64_tb/Makefile: -------------------------------------------------------------------------------- 1 | ifndef PROJ_DIR 2 | PWD = $(shell pwd) 3 | export PROJ_DIR=${PWD}/../.. 4 | endif 5 | 6 | TOP = $(shell basename $(CURDIR)) 7 | SVTB = -f ${TOP}.f 8 | SEED = 1 9 | default: test_xcellium 10 | 11 | vcs: compile_verdi run_verdi 12 | test_verdi: compile_verdi run_verdi 13 | 14 | compile_verdi: 15 | echo Running VCS for TB $(TOP) 16 | vcs +lint=TFIPC-L -sverilog -l vcs.log -kdb -debug_access+all +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+SHM_OVERRIDE_OFF +define+VCS+BEHAVIORAL+TIMESCALE_EN $(SVTB) -top ${TOP} 17 | 18 | run_verdi: 19 | ./simv -l sim.log -verdi +ntb_random_seed=$(SEED) 20 | 21 | test_xcellium: 22 | echo Running Xcellium for TB $(TOP) 23 | xmverilog $(SVTB) +xmtop+${TOP} 24 | 25 | clean: 26 | @rm -Rf xcelium.d/ 27 | @rm -Rf waves.shm/ 28 | @rm -Rf .simvision/ 29 | @rm -Rf *.history *.log 30 | @rm -Rf vcs.log 31 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d64_tb/axi_st_d64_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_st_d64_tb.sv 3 | +libverbose 4 | +libext+.v 5 | +define+FOR_SIM_ONLY 6 | -f ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_master.f 7 | -f ${PROJ_DIR}/axi4-st/axi_st_d64/axi_st_d64_slave.f 8 | -y . 9 | -l axi_st_d64_tb.log 10 | -------------------------------------------------------------------------------- /axi4-st/dv/axi_st_d64_tb/run_axi_st_d64_tb: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | #Run Sim 4 | xmverilog -f axi_st_d64_tb.f $* 5 | -------------------------------------------------------------------------------- /axi4-st/full_examples/common/reset_control.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (C) 2021 Intel Corporation. 3 | ///////////////////////////////////////////////////////////////////////////////////////// 4 | //-------------------------------------------------------------------------------------- 5 | // Description: Reset control module 6 | // 7 | // 8 | // Change log 9 | // 10 | ///////////////////////////////////////////////////////////////////////////////////////// 11 | 12 | module reset_control ( 13 | input clk, 14 | input rst_n, 15 | output reg reset_out, 16 | output reg reset_out_n 17 | ); 18 | 19 | always@(posedge clk or negedge rst_n) 20 | begin 21 | if(rst_n == 1'b0) 22 | begin 23 | reset_out <= 1'b1; 24 | reset_out_n <= 1'b0; 25 | end 26 | else 27 | begin 28 | reset_out <= 1'b0; 29 | reset_out_n <= 1'b1; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/axi_st_d256_multichannel_f2h_dual.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | #${PROJ_DIR}/axi4-st/dv/axi_st_d256_multichannel_f2h_tb/axi_st_d256_multichannel_f2h_tb_modified.sv 3 | ${SIM_DIR}/../common/axi_st_d256_multichannel_f2h_dual_top.sv 4 | #${PROJ_DIR}/common/dv/p2p_lite.sv 5 | ${PROJ_DIR}/common/dv/marker_gen.sv 6 | ${PROJ_DIR}/common/dv/strobe_gen.sv 7 | ${SIM_DIR}/../common/axist_rand_gen.v 8 | ${SIM_DIR}/../common/axi_st_patgen_dual_top.v 9 | ${SIM_DIR}/../common/axi_st_wr_ctrl.v 10 | ${SIM_DIR}/../common/axi_st_patchkr_f2h_top.v 11 | ${SIM_DIR}/../common/axi_st_patchkr_h2f_top.v 12 | ${SIM_DIR}/../common/axist_incr_gen.v 13 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 14 | ${SIM_DIR}/../common/axi_st_csr.v 15 | ${SIM_DIR}/../common/csr_ctrl.v 16 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 17 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 18 | +libverbose 19 | +libext+.v 20 | +define+FOR_SIM_ONLY 21 | -f ${tbench_dir}/axi_st_d256_dual_multichannel/axi_st_d256_dual_multichannel_full_master.f 22 | #-f ${SIM_DIR}/../flist/axi_st_d256_multichannel_full_master.f 23 | #-f ${PROJ_DIR}/axi4-st/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave.f 24 | -f ${tbench_dir}/axi_st_d256_dual_multichannel/axi_st_d256_dual_multichannel_half_slave.f 25 | -f ${PROJ_DIR}/ca/rtl/ca.f 26 | -y . 27 | -l axi_st_d256_dual_multichannel_f2h_tb.log 28 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/axi_st_d256_multichannel_f2h_simplex.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | ${SIM_DIR}/../common/axi_st_d256_multichannel_f2h_simplex_top.sv 3 | #${PROJ_DIR}/common/dv/p2p_lite.sv 4 | ${PROJ_DIR}/common/dv/marker_gen.sv 5 | ${PROJ_DIR}/common/dv/strobe_gen.sv 6 | ${SIM_DIR}/../common/axist_rand_gen.v 7 | ${SIM_DIR}/../common/axi_st_patgen_top.v 8 | ${SIM_DIR}/../common/axi_st_wr_ctrl.v 9 | ${SIM_DIR}/../common/axi_st_patchkr_top.v 10 | ${SIM_DIR}/../common/axist_incr_gen.v 11 | ${SIM_DIR}/../common/axi_st_csr.v 12 | ${SIM_DIR}/../common/csr_ctrl.v 13 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 14 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 15 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 16 | +libverbose 17 | +libext+.v 18 | +define+FOR_SIM_ONLY 19 | -f ${tbench_dir}/axi_st_d256_multichannel/axi_st_d256_multichannel_full_master.f 20 | -f ${tbench_dir}/axi_st_d256_multichannel/axi_st_d256_multichannel_half_slave.f 21 | -f ${PROJ_DIR}/ca/rtl/ca.f 22 | -y . 23 | -l axi_st_d256_multichannel_f2h_simplex.log 24 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/axi_st_d256_multichannel_h2h_simplex.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | ${SIM_DIR}/../common/axi_st_multichannel_h2h_simplex_top.sv 3 | #${PROJ_DIR}/common/dv/p2p_lite.sv 4 | ${PROJ_DIR}/common/dv/marker_gen.sv 5 | ${PROJ_DIR}/common/dv/strobe_gen.sv 6 | ${SIM_DIR}/../common/axist_rand_gen.v 7 | ${SIM_DIR}/../common/axi_st_h2h_patgen_top.v 8 | ${SIM_DIR}/../common/axi_st_wr_ctrl.v 9 | ${SIM_DIR}/../common/axi_st_h2h_patchkr_top.v 10 | ${SIM_DIR}/../common/axist_incr_gen.v 11 | ${SIM_DIR}/../common/axi_st_h2h_csr.v 12 | ${SIM_DIR}/../common/csr_ctrl_h2h.v 13 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 14 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 15 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 16 | +libverbose 17 | +libext+.v 18 | +define+FOR_SIM_ONLY 19 | -f ${tbench_dir}/axi_st/axi_st_master.f 20 | -f ${tbench_dir}/axi_st/axi_st_slave.f 21 | -f ${PROJ_DIR}/ca/rtl/ca.f 22 | -y . 23 | -l axi_st_multichannel_h2h_simplex.log 24 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/axi_st_d64_multichannel_h2h_simplex.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | ${SIM_DIR}/../common/axi_st_multichannel_h2h_simplex_top.sv 3 | #${PROJ_DIR}/common/dv/p2p_lite.sv 4 | ${PROJ_DIR}/common/dv/marker_gen.sv 5 | ${PROJ_DIR}/common/dv/strobe_gen.sv 6 | ${SIM_DIR}/../common/axist_rand_gen.v 7 | ${SIM_DIR}/../common/axi_st_h2h_patgen_top.v 8 | ${SIM_DIR}/../common/axi_st_wr_ctrl.v 9 | ${SIM_DIR}/../common/axi_st_h2h_patchkr_top.v 10 | ${SIM_DIR}/../common/axist_incr_gen.v 11 | ${SIM_DIR}/../common/axi_st_h2h_csr.v 12 | ${SIM_DIR}/../common/csr_ctrl_h2h.v 13 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 14 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 15 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 16 | +libverbose 17 | +libext+.v 18 | +define+FOR_SIM_ONLY 19 | -f ${tbench_dir}/axi_st/axi_st_master.f 20 | -f ${tbench_dir}/axi_st/axi_st_slave.f 21 | -f ${PROJ_DIR}/ca/rtl/ca.f 22 | -y . 23 | -l axi_st_multichannel_h2h_simplex.log 24 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/tb_dual_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | +incdir+${AIB_ROOT}/dv/tb 5 | +incdir+${AIB_ROOT}/dv/interface 6 | +incdir+${AIB_ROOT}/dv/test/task 7 | ${AIBV1_DV_ROOT}/emib/aliasv.sv 8 | ${AIBV1_DV_ROOT}/emib/emib_ch_m1s2.sv 9 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s1.sv 10 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s2.sv 11 | ${AIBV1_DV_ROOT}/emib/emib_m1s2.sv 12 | ${AIBV1_DV_ROOT}/emib/emib_m2s1.sv 13 | ${AIBV1_DV_ROOT}/emib/emib_m2s2.sv 14 | ${AIBV1_DV_ROOT}/interface/dut_if_mac.sv 15 | ${AIBV1_DV_ROOT}/interface/avalon_mm_if.sv 16 | ${SIM_DIR}/../common/top_aib.sv 17 | 18 | ${SIM_DIR}/../common/reset_control.v 19 | ${SIM_DIR}/../common/axist_aib_dual_top.v 20 | ${tbench_dir}/top_tb.v 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/tb_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | +incdir+${AIB_ROOT}/dv/tb 5 | +incdir+${AIB_ROOT}/dv/interface 6 | +incdir+${AIB_ROOT}/dv/test/task 7 | ${AIBV1_DV_ROOT}/emib/aliasv.sv 8 | ${AIBV1_DV_ROOT}/emib/emib_ch_m1s2.sv 9 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s1.sv 10 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s2.sv 11 | ${AIBV1_DV_ROOT}/emib/emib_m1s2.sv 12 | ${AIBV1_DV_ROOT}/emib/emib_m2s1.sv 13 | ${AIBV1_DV_ROOT}/emib/emib_m2s2.sv 14 | ${AIBV1_DV_ROOT}/interface/dut_if_mac.sv 15 | ${AIBV1_DV_ROOT}/interface/avalon_mm_if.sv 16 | 17 | ${SIM_DIR}/../common/top_aib.sv 18 | 19 | ${SIM_DIR}/../common/reset_control.v 20 | ${SIM_DIR}/../common/axist_aib_top.v 21 | ${tbench_dir}/top_tb.v 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /axi4-st/full_examples/flist/tb_rtl_h2h.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | +incdir+${AIB_ROOT}/dv/tb 5 | +incdir+${AIB_ROOT}/dv/interface 6 | +incdir+${AIB_ROOT}/dv/test/task 7 | ${AIBV1_DV_ROOT}/emib/aliasv.sv 8 | ${AIBV1_DV_ROOT}/emib/emib_ch_m1s2.sv 9 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s1.sv 10 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s2.sv 11 | ${AIBV1_DV_ROOT}/emib/emib_m1s2.sv 12 | ${AIBV1_DV_ROOT}/emib/emib_m2s1.sv 13 | ${AIBV1_DV_ROOT}/emib/emib_m2s2.sv 14 | ${AIBV1_DV_ROOT}/interface/dut_if_mac.sv 15 | ${AIBV1_DV_ROOT}/interface/avalon_mm_if.sv 16 | 17 | ${SIM_DIR}/../common/top_h2h_aib.sv 18 | 19 | ${SIM_DIR}/../common/axist_aib_h2h_top.v 20 | ${SIM_DIR}/../common/reset_control.v 21 | ${tbench_dir}/top_tb.v 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /axi4-st/full_examples_gpio/common/reset_control.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (C) 2021 Intel Corporation. 3 | ///////////////////////////////////////////////////////////////////////////////////////// 4 | //-------------------------------------------------------------------------------------- 5 | // Description: Reset control module 6 | // 7 | // 8 | // Change log 9 | // 10 | ///////////////////////////////////////////////////////////////////////////////////////// 11 | 12 | module reset_control ( 13 | input clk, 14 | input rst_n, 15 | output reg reset_out, 16 | output reg reset_out_n 17 | ); 18 | 19 | always@(posedge clk or negedge rst_n) 20 | begin 21 | if(rst_n == 1'b0) 22 | begin 23 | reset_out <= 1'b1; 24 | reset_out_n <= 1'b0; 25 | end 26 | else 27 | begin 28 | reset_out <= 1'b0; 29 | reset_out_n <= 1'b1; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /axi4-st/full_examples_gpio/flist/tb_axist_gpio_phy.cf: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | ${SIM_DIR}/../common/axi_st_simplex_gpio_phy_top.sv 3 | ${SIM_DIR}/../common/axist_rand_gen.v 4 | ${SIM_DIR}/../common/axi_st_h2h_patgen_top.v 5 | ${SIM_DIR}/../common/axi_st_wr_ctrl.v 6 | ${SIM_DIR}/../common/axi_st_h2h_patchkr_top.v 7 | ${SIM_DIR}/../common/axist_incr_gen.v 8 | ${SIM_DIR}/../common/axi_st_h2h_csr.v 9 | ${SIM_DIR}/../common/csr_ctrl_h2h.v 10 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 11 | ${PROJ_DIR}common/rtl/asyncfifo.sv 12 | ${PROJ_DIR}common/rtl/syncfifo_mem1r1w.sv 13 | ${SIM_DIR}/../common/axist_gpiophy_top.v 14 | ${SIM_DIR}/../common/reset_control.v 15 | +libverbose 16 | +libext+.v 17 | +define+FOR_SIM_ONLY 18 | -f ${tbench_dir}/axist_ll_dut_new/axi_st_master.f 19 | -f ${tbench_dir}/axist_ll_dut_new/axi_st_slave.f 20 | -y . 21 | -l axi_st_multichannel_h2h_simplex.log 22 | -------------------------------------------------------------------------------- /axi4-st/full_examples_gpio/flist/tb_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | ${tbench_dir}/top_tb.v 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /backup/spi/doc/spi_ug.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/backup/spi/doc/spi_ug.pdf -------------------------------------------------------------------------------- /backup/spi/doc/spi_ug_v08p3.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/backup/spi/doc/spi_ug_v08p3.pdf -------------------------------------------------------------------------------- /backup/spi/fpga/spim/spim_wrap.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 08:47:25 April 02, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "08:47:25 April 02, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "spim_wrap" 32 | -------------------------------------------------------------------------------- /backup/spi/fpga/spim/spim_wrap.sdc: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_clock -name sclk_in -period 8.000 -waveform { 0.000 4.000 } [get_ports sclk_in] 4 | 5 | create_generated_clock -name spim_top.i_spim_intf.sclk_inv -source [get_ports {sclk_in}] -divide_by 1 -invert 6 | 7 | create_clock -name m_avmm_clk -period 4.000 -waveform { 0.000 2.000 } [get_ports m_avmm_clk] 8 | 9 | 10 | set_false_path -from [get_clocks sclk_in] -to [get_clocks m_avmm_clk] 11 | set_false_path -from [get_clocks m_avmm_clk] -to [get_clocks sclk_in] 12 | 13 | 14 | -------------------------------------------------------------------------------- /backup/spi/fpga/spis/spis_wrap.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 08:47:25 April 02, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "08:47:25 April 02, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "spis_wrap" 32 | -------------------------------------------------------------------------------- /backup/spi/fpga/spis/spis_wrap.sdc: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_clock -name sclk -period 8.000 -waveform { 0.000 4.000 } [get_ports {sclk}] 4 | create_generated_clock -name spis_top.i_spis_intf.sclk_inv -source [get_ports {sclk}] -divide_by 1 -invert 5 | create_clock -name s_avmm_clk -period 4.000 -waveform { 0.000 2.000 } [get_ports s_avmm_clk] 6 | 7 | 8 | set_false_path -from [get_clocks sclk] -to [get_clocks s_avmm_clk] 9 | set_false_path -from [get_clocks s_avmm_clk] -to [get_clocks sclk] 10 | 11 | 12 | -------------------------------------------------------------------------------- /backup/spi/rtl/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/backup/spi/rtl/README -------------------------------------------------------------------------------- /backup/spi/rtl/spim/clk_gate_beh.sv: -------------------------------------------------------------------------------- 1 | module clk_gate ( 2 | input clkin, 3 | input clken, 4 | output gatedclk 5 | ); 6 | 7 | logic clken_latched; 8 | 9 | always_latch begin 10 | if (!clkin) begin 11 | clken_latched = clken; 12 | end 13 | end 14 | 15 | assign gatedclk = clkin & clken_latched; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /backup/spi/rtl/spim/spi.vh: -------------------------------------------------------------------------------- 1 | // Protocol Definitions 2 | `define SPI_CMD_HIGH_BIT 0 3 | `define SPI_CMD_LOW_BIT 7 4 | 5 | `define SPI_LC_HIGH_BIT 8 6 | `define SPI_LC_LOW_BIT 15 7 | 8 | `define SPI_ADDR_HIGH_BIT 16 9 | `define SPI_ADDR_LOW_BIT 31 10 | 11 | `define SPI_ADDR `SPI_ADDR_HIGH_BIT:`SPI_ADDR_LOW_BIT 12 | `define SPI_LC `SPI_LC_HIGH_BIT:`SPI_LC_LOW_BIT 13 | `define SPI_CMD `SPI_CMD_HIGH_BIT:`SPI_CMD_LOW_BIT 14 | 15 | `define TERM_COUNT 5'b11111 16 | `define ZERO_COUNT 5'b00000 17 | -------------------------------------------------------------------------------- /backup/spi/rtl/spim/spim.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/spi/rtl/spim/spi.vh 2 | ${PROJ_DIR}/spi/rtl/spim/spim_intf.sv 3 | ${PROJ_DIR}/spi/rtl/spim/spim_reg_top.sv 4 | ${PROJ_DIR}/spi/rtl/spim/spim_reg.sv 5 | ${PROJ_DIR}/spi/rtl/spim/spimavb.sv 6 | ${PROJ_DIR}/spi/rtl/spim/spim_top.sv 7 | ${PROJ_DIR}/spi/rtl/spim/clk_gate_beh.sv 8 | ${PROJ_DIR}/spi/rtl/spim/pulse_sync.sv 9 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 10 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 11 | ${PROJ_DIR}/common/rtl/levelsync.sv 12 | ${PROJ_DIR}/common/rtl/levelsync_sr.sv 13 | ${PROJ_DIR}/common/rtl/rst_regen_low.sv 14 | 15 | -------------------------------------------------------------------------------- /backup/spi/rtl/spis/spi.vh: -------------------------------------------------------------------------------- 1 | // Protocol Definitions 2 | `define SPI_CMD_HIGH_BIT 0 3 | `define SPI_CMD_LOW_BIT 7 4 | 5 | `define SPI_LC_HIGH_BIT 8 6 | `define SPI_LC_LOW_BIT 15 7 | 8 | `define SPI_ADDR_HIGH_BIT 16 9 | `define SPI_ADDR_LOW_BIT 31 10 | 11 | `define SPI_ADDR `SPI_ADDR_HIGH_BIT:`SPI_ADDR_LOW_BIT 12 | `define SPI_LC `SPI_LC_HIGH_BIT:`SPI_LC_LOW_BIT 13 | `define SPI_CMD `SPI_CMD_HIGH_BIT:`SPI_CMD_LOW_BIT 14 | 15 | `define TERM_COUNT 5'b11111 16 | `define ZERO_COUNT 5'b00000 17 | -------------------------------------------------------------------------------- /backup/spi/rtl/spis/spis.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/spi/rtl/spis/spi.vh 2 | ${PROJ_DIR}/spi/rtl/spis/spis_intf.sv 3 | ${PROJ_DIR}/spi/rtl/spis/spis_reg_top.sv 4 | ${PROJ_DIR}/spi/rtl/spis/spis_reg.sv 5 | ${PROJ_DIR}/spi/rtl/spis/spisavb.sv 6 | ${PROJ_DIR}/spi/rtl/spis/spis_miso_buf.sv 7 | ${PROJ_DIR}/spi/rtl/spis/spis_top.sv 8 | -v ${PROJ_DIR}/spi/rtl/spis/pulse_sync.sv 9 | -v ${PROJ_DIR}/common/rtl/asyncfifo.sv 10 | -v ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 11 | -v ${PROJ_DIR}/common/rtl/levelsync.sv 12 | -v ${PROJ_DIR}/common/rtl/levelsync_sr.sv 13 | -v ${PROJ_DIR}/common/rtl/rst_regen_low.sv 14 | -------------------------------------------------------------------------------- /backup/spi/rtl/spis/spis_miso_buf.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // All Rights Reserved 5 | // 6 | // This entire notice must be reproduced on all copies of this file 7 | // and copies of this file may only be made by a person if such person is 8 | // permitted to do so under the terms of a subsisting license agreement 9 | // from Eximius Design 10 | // 11 | // Licensed under the Apache License, Version 2.0 (the "License"); 12 | // you may not use this file except in compliance with the License. 13 | // You may obtain a copy of the License at 14 | // 15 | // http://www.apache.org/licenses/LICENSE-2.0 16 | // 17 | // Unless required by applicable law or agreed to in writing, software 18 | // distributed under the License is distributed on an "AS IS" BASIS, 19 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 | // See the License for the specific language governing permissions and 21 | // limitations under the License. 22 | // 23 | //Functional Descript: 24 | // 25 | // 26 | // 27 | //////////////////////////////////////////////////////////// 28 | // spis_top - top level module for SPI Slave 29 | // 30 | 31 | module spis_miso_buf ( 32 | input logic sel, 33 | input logic data_in, 34 | output logic data_out 35 | ); 36 | 37 | assign data_out = (~sel) ? data_in : 1'bz; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /ca/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/ca/README -------------------------------------------------------------------------------- /ca/doc/ca_ug.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/ca/doc/ca_ug.pdf -------------------------------------------------------------------------------- /ca/dv/.gitignore: -------------------------------------------------------------------------------- 1 | 64/ 2 | aib_channel_delay.txt 3 | aib_config.txt 4 | AN.DB/ 5 | ca_config_define.svi 6 | config_aib_0.hex 7 | csrc_debug/ 8 | .fsm.sch.verilog.xml 9 | llink_config_define.svi 10 | logs/ 11 | master_0_config_aib.dat 12 | simv* 13 | simv.daidir/ 14 | simv.vdb/ 15 | slave_0_config_aib.dat 16 | smoke.txt 17 | ucli.key 18 | vcdplus.vpd 19 | vc_hdrs.h 20 | vcs.log 21 | work.lib++/ 22 | ca_tb.history 23 | ca_tb.log 24 | waves.shm/ 25 | xcelium.d/ 26 | smoke_log.txt 27 | -------------------------------------------------------------------------------- /ca/dv/ca_no_shm.tcl: -------------------------------------------------------------------------------- 1 | run 2 | -------------------------------------------------------------------------------- /ca/dv/ca_shm.tcl: -------------------------------------------------------------------------------- 1 | database -open waves -shm 2 | probe -create ca_top_tb -depth all -all -shm -database waves 3 | run 4 | exit 5 | -------------------------------------------------------------------------------- /ca/dv/cfg_list/README: -------------------------------------------------------------------------------- 1 | This generates an array of randomly generated tests that 2 | target speciifc sequences and randomize other fields. 3 | 4 | Run: 5 | 6 | python ca_gen_cfg.py 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_coverage.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_COVERAGE_ 25 | `define _CA_COVERAGE_ 26 | ////////////////////////////////////////////////////////////////// 27 | 28 | covergroup ca_cfg_covergroup with function sample(ca_cfg_c ca_cfg); 29 | 30 | endgroup : ca_cfg_covergroup 31 | 32 | ////////////////////////////////////////////////////////////////// 33 | `endif 34 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_data_pkg.svh: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_DATA_PKG_ 25 | `define _CA_DATA_PKG_ 26 | //////////////////////////////////////////////////////////////////// 27 | package ca_data_pkg; 28 | 29 | import uvm_pkg::*; 30 | `include "uvm_macros.svh" 31 | 32 | `include "./ca_seq_item.sv" 33 | 34 | //////////////////////////////////////////////////////////////////// 35 | endpackage : ca_data_pkg 36 | `endif 37 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_reset_agent/.ca_reset_agent.sv.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/ca/dv/export_src/ca_reset_agent/.ca_reset_agent.sv.swp -------------------------------------------------------------------------------- /ca/dv/export_src/ca_reset_agent/ca_reset_if.sv: -------------------------------------------------------------------------------- 1 | `ifndef _CA_RESET_IF_ 2 | `define _CA_RESET_IF_ 3 | ///////////////////////////////////////////////////////// 4 | 5 | `include "uvm_macros.svh" 6 | 7 | interface ca_reset_if (input clk); 8 | 9 | logic reset_l; 10 | 11 | //--------------------------------------------------- 12 | modport drv ( 13 | input clk, 14 | output reset_l 15 | ); 16 | 17 | modport mon ( 18 | input clk, 19 | input reset_l 20 | ); 21 | 22 | endinterface : ca_reset_if 23 | 24 | ///////////////////////////////////////////////////////// 25 | `endif 26 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_reset_agent/ca_reset_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef _CA_RESET_PKG_ 2 | `define _CA_RESET_PKG_ 3 | //////////////////////////////////////////////////////////////////// 4 | package ca_reset_pkg; 5 | 6 | import uvm_pkg::*; 7 | `include "uvm_macros.svh" 8 | 9 | `include "./ca_reset_seq_item.sv" 10 | `include "./ca_reset_cfg.sv" 11 | `include "./ca_reset_drv.sv" 12 | `include "./ca_reset_mon.sv" 13 | `include "./ca_reset_seq.sv" 14 | `include "./ca_reset_seqr.sv" 15 | //`include "./ca_reset_fcov_mon.sv" 16 | `include "./ca_reset_agent.sv" 17 | 18 | //////////////////////////////////////////////////////////////////// 19 | endpackage : ca_reset_pkg 20 | `endif 21 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_reset_agent/ca_reset_seq.sv: -------------------------------------------------------------------------------- 1 | `ifndef _CA_RESET_SEQ_ 2 | `define _CA_RESET_SEQ_ 3 | //////////////////////////////////////////////////////////// 4 | 5 | class ca_reset_seq_c extends uvm_sequence #(ca_reset_seq_item_c); 6 | 7 | int active_cycle_cnt ; 8 | int post_cycle_cnt ; 9 | `uvm_object_utils(ca_reset_seq_c) 10 | 11 | extern function new(string name = "ca_reset_seq"); 12 | extern task body(); 13 | 14 | endclass : ca_reset_seq_c 15 | 16 | //////////////////////////////////////////////////////////// 17 | 18 | //------------------------------------------ 19 | function ca_reset_seq_c::new(string name = "ca_reset_seq"); 20 | super.new(name); 21 | endfunction : new 22 | 23 | //------------------------------------------ 24 | // body 25 | //------------------------------------------ 26 | task ca_reset_seq_c::body(); 27 | 28 | ca_reset_seq_item_c reset_trig; 29 | 30 | `uvm_info("body", "START reset seq...", UVM_LOW); 31 | 32 | reset_trig = ca_reset_seq_item_c::type_id::create("reset_trig"); 33 | 34 | reset_trig.active_cycle_cnt = this.active_cycle_cnt; 35 | reset_trig.post_cycle_cnt = this.post_cycle_cnt; 36 | 37 | `uvm_info("body", "Sending reset trigger", UVM_MEDIUM); 38 | start_item(reset_trig); 39 | finish_item(reset_trig); 40 | 41 | `uvm_info("body", "END reset seq...\n", UVM_LOW); 42 | 43 | endtask : body 44 | //////////////////////////////////////////////////////////// 45 | `endif 46 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_reset_agent/ca_reset_seq_item.sv: -------------------------------------------------------------------------------- 1 | `ifndef _CA_RESET_SEQ_ITEM_ 2 | `define _CA_RESET_SEQ_ITEM_ 3 | ////////////////////////////////////////////////////////// 4 | class ca_reset_seq_item_c extends uvm_sequence_item ; 5 | 6 | 7 | //------------------------------------------ 8 | // Data Members 9 | //------------------------------------------ 10 | 11 | int active_cycle_cnt ; 12 | int post_cycle_cnt ; 13 | 14 | //------------------------------------------ 15 | // UVM Factory Registration Macro 16 | //------------------------------------------ 17 | `uvm_object_utils_begin(ca_reset_seq_item_c) 18 | `uvm_field_int(active_cycle_cnt, UVM_DEFAULT); 19 | `uvm_field_int(post_cycle_cnt, UVM_DEFAULT); 20 | `uvm_object_utils_end 21 | //------------------------------------------ 22 | // Sideband Data Members 23 | //------------------------------------------ 24 | 25 | //------------------------------------------ 26 | // constraints 27 | //------------------------------------------ 28 | //constraint c_active_cycle_cnt { active_cycle_cnt >= 10 ; active_cycle_cnt <= 20; } 29 | constraint c_active_cycle_cnt { active_cycle_cnt == 200 ; active_cycle_cnt == 200; } 30 | constraint c_post_cyce_cnt { post_cycle_cnt >= 0 ; post_cycle_cnt <= 5; } 31 | 32 | // Standard UVM Methods: 33 | extern function new(string name = "ca_reset_seq_item"); 34 | 35 | endclass : ca_reset_seq_item_c 36 | 37 | //////////////////////////////////////////////////////////// 38 | 39 | //-------------------------------------------------- 40 | function ca_reset_seq_item_c::new (string name = "ca_reset_seq_item"); 41 | super.new(name); 42 | endfunction : new 43 | 44 | ////////////////////////////////////////////////////////// 45 | `endif 46 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_reset_agent/ca_reset_seqr.sv: -------------------------------------------------------------------------------- 1 | `ifndef _CA_RESET_SEQR_ 2 | `define _CA_RESET_SEQR_ 3 | 4 | //////////////////////////////////////////////////////////// 5 | 6 | class ca_reset_seqr_c extends uvm_sequencer #(ca_reset_seq_item_c, ca_reset_seq_item_c); 7 | 8 | // UVM Factory Registration Macro 9 | `uvm_component_utils(ca_reset_seqr_c) 10 | 11 | // Standard UVM Methods: 12 | extern function new(string name="ca_reset_seqr", uvm_component parent = null); 13 | 14 | endclass: ca_reset_seqr_c 15 | //////////////////////////////////////////////////////////// 16 | //--------------------------------------- 17 | function ca_reset_seqr_c::new(string name="ca_reset_seqr", uvm_component parent = null); 18 | super.new(name, parent); 19 | endfunction : new 20 | 21 | //////////////////////////////////////////////////////////// 22 | `endif 23 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_rx_tb_in_pkg.svh: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_RX_TB_IN_PKG_ 25 | `define _CA_RX_TB_IN_PKG_ 26 | //////////////////////////////////////////////////////////////////// 27 | package ca_rx_tb_in_pkg; 28 | 29 | import uvm_pkg::*; 30 | `include "uvm_macros.svh" 31 | 32 | `include "./ca_seq_item.sv" 33 | `include "./ca_rx_tb_in_cfg.sv" 34 | `include "./ca_rx_tb_in_drv.sv" 35 | `include "./ca_rx_tb_in_mon.sv" 36 | `include "./ca_rx_tb_in_seqr.sv" 37 | //`include "./ca_rx_tb_in_fcov_mon.sv" 38 | `include "./ca_rx_tb_in_agent.sv" 39 | 40 | //////////////////////////////////////////////////////////////////// 41 | endpackage : ca_rx_tb_in_pkg 42 | `endif 43 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_rx_tb_in_seqr.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_RX_TB_IN_SEQR_ 25 | `define _CA_RX_TB_IN_SEQR_ 26 | 27 | //////////////////////////////////////////////////////////// 28 | 29 | class ca_rx_tb_in_seqr_c extends uvm_sequencer #(ca_data_pkg::ca_seq_item_c, ca_data_pkg::ca_seq_item_c); 30 | 31 | // UVM Factory Registration Macro 32 | `uvm_component_utils(ca_rx_tb_in_seqr_c) 33 | 34 | // Standard UVM Methods: 35 | extern function new(string name="ca_rx_tb_in_seqr", uvm_component parent = null); 36 | 37 | endclass: ca_rx_tb_in_seqr_c 38 | //////////////////////////////////////////////////////////// 39 | //--------------------------------------- 40 | function ca_rx_tb_in_seqr_c::new(string name="ca_rx_tb_in_seqr", uvm_component parent = null); 41 | super.new(name, parent); 42 | endfunction : new 43 | 44 | //////////////////////////////////////////////////////////// 45 | `endif 46 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_tx_tb_in_pkg.svh: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_TX_TB_IN_PKG_ 25 | `define _CA_TX_TB_IN_PKG_ 26 | //////////////////////////////////////////////////////////////////// 27 | package ca_tx_tb_in_pkg; 28 | 29 | import uvm_pkg::*; 30 | `include "uvm_macros.svh" 31 | 32 | `include "./ca_seq_item.sv" 33 | `include "./ca_tx_tb_in_cfg.sv" 34 | `include "./ca_tx_tb_in_drv.sv" 35 | `include "./ca_tx_tb_in_mon.sv" 36 | `include "./ca_tx_tb_in_seqr.sv" 37 | //`include "./ca_tx_tb_in_fcov_mon.sv" 38 | `include "./ca_tx_tb_in_agent.sv" 39 | 40 | //////////////////////////////////////////////////////////////////// 41 | endpackage : ca_tx_tb_in_pkg 42 | `endif 43 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_tx_tb_in_seqr.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_TX_TB_IN_SEQR_ 25 | `define _CA_TX_TB_IN_SEQR_ 26 | 27 | //////////////////////////////////////////////////////////// 28 | 29 | class ca_tx_tb_in_seqr_c extends uvm_sequencer #(ca_data_pkg::ca_seq_item_c, ca_data_pkg::ca_seq_item_c); 30 | 31 | // UVM Factory Registration Macro 32 | `uvm_component_utils(ca_tx_tb_in_seqr_c) 33 | 34 | // Standard UVM Methods: 35 | extern function new(string name="ca_tx_tb_in_seqr", uvm_component parent = null); 36 | 37 | endclass: ca_tx_tb_in_seqr_c 38 | //////////////////////////////////////////////////////////// 39 | //--------------------------------------- 40 | function ca_tx_tb_in_seqr_c::new(string name="ca_tx_tb_in_seqr", uvm_component parent = null); 41 | super.new(name, parent); 42 | endfunction : new 43 | 44 | //////////////////////////////////////////////////////////// 45 | `endif 46 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_tx_tb_out_pkg.svh: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_TX_TB_OUT_PKG_ 25 | `define _CA_TX_TB_OUT_PKG_ 26 | //////////////////////////////////////////////////////////////////// 27 | package ca_tx_tb_out_pkg; 28 | 29 | import uvm_pkg::*; 30 | `include "uvm_macros.svh" 31 | 32 | // `include "./ca_seq_item.sv" 33 | `include "./ca_tx_tb_out_cfg.sv" 34 | `include "./ca_tx_tb_out_drv.sv" 35 | `include "./ca_tx_tb_out_mon.sv" 36 | `include "./ca_tx_tb_out_seqr.sv" 37 | //`include "./ca_tx_tb_out_fcov_mon.sv" 38 | `include "./ca_tx_tb_out_agent.sv" 39 | 40 | //////////////////////////////////////////////////////////////////// 41 | endpackage : ca_tx_tb_out_pkg 42 | `endif 43 | -------------------------------------------------------------------------------- /ca/dv/export_src/ca_tx_tb_out_seqr.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CA_TX_TB_OUT_SEQR_ 25 | `define _CA_TX_TB_OUT_SEQR_ 26 | 27 | //////////////////////////////////////////////////////////// 28 | 29 | class ca_tx_tb_out_seqr_c extends uvm_sequencer #(ca_data_pkg::ca_seq_item_c, ca_data_pkg::ca_seq_item_c); 30 | 31 | // UVM Factory Registration Macro 32 | `uvm_component_utils(ca_tx_tb_out_seqr_c) 33 | 34 | // Standard UVM Methods: 35 | extern function new(string name="ca_tx_tb_out_seqr", uvm_component parent = null); 36 | 37 | endclass: ca_tx_tb_out_seqr_c 38 | //////////////////////////////////////////////////////////// 39 | //--------------------------------------- 40 | function ca_tx_tb_out_seqr_c::new(string name="ca_tx_tb_out_seqr", uvm_component parent = null); 41 | super.new(name, parent); 42 | endfunction : new 43 | 44 | //////////////////////////////////////////////////////////// 45 | `endif 46 | -------------------------------------------------------------------------------- /ca/dv/export_src/chan_delay_agent/chan_delay_pkg.svh: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CHAN_DELAY_PKG_ 25 | `define _CHAN_DELAY_PKG_ 26 | //////////////////////////////////////////////////////////////////// 27 | package chan_delay_pkg; 28 | 29 | import uvm_pkg::*; 30 | `include "uvm_macros.svh" 31 | 32 | `include "./chan_delay_seq_item.sv" 33 | `include "./chan_delay_cfg.sv" 34 | `include "./chan_delay_drv.sv" 35 | `include "./chan_delay_mon.sv" 36 | `include "./chan_delay_seqr.sv" 37 | //`include "./chan_delay_fcov_mon.sv" 38 | `include "./chan_delay_agent.sv" 39 | 40 | //////////////////////////////////////////////////////////////////// 41 | endpackage : chan_delay_pkg 42 | `endif 43 | -------------------------------------------------------------------------------- /ca/dv/export_src/chan_delay_agent/chan_delay_seqr.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright (C) 2021 Eximius Design 4 | // 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the "License"); 7 | // you may not use this file except in compliance with the License. 8 | // You may obtain a copy of the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in writing, software 13 | // distributed under the License is distributed on an "AS IS" BASIS, 14 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | // See the License for the specific language governing permissions and 16 | // limitations under the License. 17 | // 18 | // Functional Descript: Channel Alignment Testbench File 19 | // 20 | // 21 | // 22 | //////////////////////////////////////////////////////////////////////////////////////////////////// 23 | 24 | `ifndef _CHAN_DELAY_SEQR_ 25 | `define _CHAN_DELAY_SEQR_ 26 | 27 | //////////////////////////////////////////////////////////// 28 | 29 | class chan_delay_seqr_c extends uvm_sequencer #(chan_delay_seq_item_c, chan_delay_seq_item_c); 30 | 31 | // UVM Factory Registration Macro 32 | `uvm_component_utils(chan_delay_seqr_c) 33 | 34 | // Standard UVM Methods: 35 | extern function new(string name="chan_delay_seqr", uvm_component parent = null); 36 | 37 | endclass: chan_delay_seqr_c 38 | //////////////////////////////////////////////////////////// 39 | //--------------------------------------- 40 | function chan_delay_seqr_c::new(string name="chan_delay_seqr", uvm_component parent = null); 41 | super.new(name, parent); 42 | endfunction : new 43 | 44 | //////////////////////////////////////////////////////////// 45 | `endif 46 | -------------------------------------------------------------------------------- /ca/dv/imc.cmd: -------------------------------------------------------------------------------- 1 | merge test_*/cov_work/scope/test*/ -out cov_report 2 | load -run cov_report 3 | #report_metrics -out cov_html 4 | quit 5 | -------------------------------------------------------------------------------- /ca/dv/run_smoke.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd ../../ 4 | echo `pwd` 5 | cd - 6 | 7 | LOG=$PROJ_DIR/ca/dv/RUN_SMOKE_TEST/ca_tb.log 8 | 9 | d_cfg=./scripts/sailrock_cfg.txt 10 | 11 | if [ -d RUN_SMOKE_TEST ]; then 12 | rm -rf RUN_SMOKE_TEST 13 | fi 14 | 15 | cd ./scripts 16 | python3 run_all_sim.py copy -d RUN_SMOKE_TEST -cfg $d_cfg 17 | 18 | cd ../RUN_SMOKE_TEST 19 | 20 | ./run_sim ####alternatively ./run_sim [ca_basic_test_c] [nowaves/cov_nowaves/cov_waves] 21 | 22 | # Move log file into a fixed location 23 | if [ -d logs ]; then 24 | cp logs/ca_tb.log ./ca_tb.log 25 | fi 26 | 27 | grep -e "UVM_ERROR :" -e "UVM_FATAL :" $LOG > smoke_log.txt 28 | 29 | if `grep -qE "UVM_ERROR\s*:\s*0\s*$" $LOG` && `grep -qE "UVM_FATAL\s*:\s*0\s*$" $LOG`; then 30 | echo " " 31 | echo -------------------------------------------------------------------------------------------------------- 32 | echo ----------------------------------------- CA smoke test PASSED ----------------------------------------- 33 | echo -------------------------------------------------------------------------------------------------------- 34 | echo " " 35 | else 36 | echo " " 37 | echo -------------------------------------------------------------------------------------------------------- 38 | echo ----------------------------------------- CA smoke test FAILED ----------------------------------------- 39 | echo -------------------------------------------------------------------------------------------------------- 40 | grep -E "UVM_ERROR" $LOG 41 | grep -E "UVM_FATAL" $LOG 42 | fi 43 | -------------------------------------------------------------------------------- /ca/dv/scripts/aib_cfg_default.txt: -------------------------------------------------------------------------------- 1 | aib_ver 2 | aib_GEN2_MODE 3 | aib_NUM_OF_CHANNEL 4 | aib_channel_enable 5 | aib_reg_to_reg_channel 6 | aib_tx_bit_per_channel 7 | aib_rx_bit_per_channel 8 | aib_TX_MODE 9 | aib_RX_MODE 10 | aib_TX_WMARKER_EN 11 | aib_rx_walign_en 12 | aib_tx_rd_delay 13 | aib_rx_rd_delay 14 | aib_TX_DBI_EN 15 | aib_RX_DBI_EN 16 | aib_tx_swap_en 17 | aib_rx_swap_en 18 | aib_TX_MARKER_LOC 19 | aib_RX_MARKER_LOC 20 | aib_loop_back_mode 21 | -------------------------------------------------------------------------------- /ca/dv/scripts/ca_cfg_default.txt: -------------------------------------------------------------------------------- 1 | CA_ALIGN_FLY 2 | CA_TX_STB_EN 3 | CA_RDEN_DLY 4 | CA_FIFO_FULL 5 | CA_FIFO_PFULL 6 | CA_FIFO_EMPTY 7 | CA_FIFO_PEMPTY 8 | CA_TX_STB_WD_SEL 9 | CA_TX_STB_BIT_SEL 10 | CA_TX_STB_INTV 11 | CA_RX_STB_WD_SEL 12 | CA_RX_STB_BIT_SEL 13 | CA_RX_STB_INTV 14 | -------------------------------------------------------------------------------- /ca/dv/scripts/readme: -------------------------------------------------------------------------------- 1 | 2 | python3 run_all_sim.py copy -d sim_copy -cfg sailrock_cfg.txt 3 | python3 run_all_sim.py regression -d sim_regress -t target_cfg.txt -cfg sailrock_cfg.txt 4 | python3 run_all_sim.py random -rn 3 -d sim_random -t target_cfg.txt -cfg sailrock_cfg.txt 5 | python3 run_all_sim.py good -d sim_good 6 | -------------------------------------------------------------------------------- /ca/dv/scripts/run_change_makefile.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import os 3 | import re 4 | import argparse 5 | import fileinput 6 | import csv 7 | import numpy as np 8 | import array as ack_array 9 | 10 | default_mname = "makefile_default" 11 | out_mname ="makefile" 12 | 13 | def replaceAll(file,searchExp,replaceExp): 14 | for line in fileinput.input(file, inplace=1): 15 | if searchExp in line: 16 | ## line = line.replace(searchExp,replaceExp) 17 | line = replaceExp 18 | sys.stdout.write(line) 19 | 20 | 21 | parser = argparse.ArgumentParser() 22 | parser.add_argument("--filename","-f", type=str, required=False, action="store", default = default_mname, help = " Input filename") 23 | parser.add_argument("--dirname","-d", type=str, required=True, action="store", help = " Directory Name") 24 | args = parser.parse_args() 25 | 26 | 27 | if args.filename is not None: 28 | make_file = os.path.join(os.getcwd(), args.filename) 29 | else: 30 | print("=======================================================================") 31 | print(" Error: Please specify input file name ") 32 | print("=======================================================================") 33 | parser.print_help() 34 | sys.exit() 35 | 36 | three_up = os.path.normpath(os.path.join(os.getcwd(), *([".."] * 4)) ) 37 | old_string = 'PROJ_DIR = ' 38 | new_string = old_string + three_up + '\n' 39 | print(new_string) 40 | replaceAll(make_file,old_string,new_string) 41 | -------------------------------------------------------------------------------- /ca/dv/scripts/target_cfg.txt: -------------------------------------------------------------------------------- 1 | aib_ver 2 | tx_rd_delay 3 | -------------------------------------------------------------------------------- /ca/fpga/ca_wrap.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 08:47:25 April 02, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "08:47:25 April 02, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "ca_wrap" 32 | -------------------------------------------------------------------------------- /ca/fpga/ca_wrap.sdc: -------------------------------------------------------------------------------- 1 | # this is for SYNC_FIFO = 1 mode 2 | 3 | create_clock -name com_clk -period 2.000 -waveform { 0.000 1.000 } [get_ports com_clk] 4 | 5 | # use these for SYNC_FIFO = 0 mode 6 | 7 | #create_clock -name lane_clk[0] -period 2.000 -waveform { 0.000 1.000 } [get_ports lane_clk[0]] 8 | #create_clock -name lane_clk[1] -period 2.000 -waveform { 0.000 1.000 } [get_ports lane_clk[1]] 9 | #create_clock -name lane_clk[2] -period 2.000 -waveform { 0.000 1.000 } [get_ports lane_clk[2]] 10 | #create_clock -name lane_clk[3] -period 2.000 -waveform { 0.000 1.000 } [get_ports lane_clk[3]] 11 | 12 | # These are pseudo-static signals 13 | 14 | set_false_path -from [get_keepers -no_duplicates {align_fly}] 15 | set_false_path -from [get_keepers -no_duplicates {tx_stb_en}] 16 | set_false_path -from [get_keepers -no_duplicates {tx_stb_rcvr}] 17 | set_false_path -from [get_keepers -no_duplicates {rden_dly*}] 18 | 19 | set_false_path -from [get_keepers -no_duplicates {count_x[*]}] 20 | set_false_path -from [get_keepers -no_duplicates {count_xz[*]}] 21 | 22 | set_false_path -from [get_keepers -no_duplicates {fifo_empty_val*}] 23 | set_false_path -from [get_keepers -no_duplicates {fifo_pempty_val*}] 24 | set_false_path -from [get_keepers -no_duplicates {fifo_full_val*}] 25 | set_false_path -from [get_keepers -no_duplicates {fifo_pfull_val*}] 26 | 27 | set_false_path -from [get_keepers -no_duplicates {rx_stb_bit_sel[*]}] 28 | set_false_path -from [get_keepers -no_duplicates {rx_stb_intv[*]}] 29 | set_false_path -from [get_keepers -no_duplicates {rx_stb_wd_sel[*]}] 30 | 31 | set_false_path -from [get_keepers -no_duplicates {tx_stb_bit_sel[*]}] 32 | set_false_path -from [get_keepers -no_duplicates {tx_stb_intv[*]}] 33 | set_false_path -from [get_keepers -no_duplicates {tx_stb_wd_sel[*]}] 34 | -------------------------------------------------------------------------------- /ca/rtl/ca.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/ca/rtl/ca.sv 2 | ${PROJ_DIR}/ca/rtl/ca_tx_strb.sv 3 | ${PROJ_DIR}/ca/rtl/ca_rx_align.sv 4 | ${PROJ_DIR}/ca/rtl/ca_rx_align_fifo.sv 5 | ${PROJ_DIR}/ca/rtl/ca_tx_mux.sv 6 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 7 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 8 | ${PROJ_DIR}/common/rtl/levelsync.sv 9 | ${PROJ_DIR}/common/rtl/level_delay.sv 10 | ${PROJ_DIR}/common/rtl/rst_regen_low.sv 11 | ${PROJ_DIR}/common/rtl/syncfifo.sv 12 | ${PROJ_DIR}/common/rtl/syncfifo_reg.sv 13 | ${PROJ_DIR}/common/rtl/syncfifo_ram.sv 14 | -------------------------------------------------------------------------------- /common/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/common/README -------------------------------------------------------------------------------- /common/dv/.gitignore: -------------------------------------------------------------------------------- 1 | DVEfiles 2 | xcelium.d 3 | waves.shm 4 | *.history 5 | *.log 6 | -------------------------------------------------------------------------------- /common/dv/chan_delay_agent/chan_delay_if.sv: -------------------------------------------------------------------------------- 1 | `ifndef _CHAN_DELAY_IF_ 2 | `define _CHAN_DELAY_IF_ 3 | ///////////////////////////////////////////////////////// 4 | 5 | `include "uvm_macros.svh" 6 | 7 | interface chan_delay_if #(int BUS_BIT_WIDTH=80) (input clk, rst_n); 8 | 9 | // signal declaration... 10 | //--------------------------------------------------- 11 | logic [BUS_BIT_WIDTH-1:0] din; 12 | logic [BUS_BIT_WIDTH-1:0] dout; 13 | 14 | // modports... 15 | //--------------------------------------------------- 16 | modport mon ( 17 | input clk, 18 | input rst_n, 19 | // 20 | input dout, 21 | input din 22 | ); 23 | //--------------------------------------------------- 24 | modport drv ( 25 | input clk, 26 | input rst_n, 27 | // 28 | output dout, 29 | input din 30 | ); 31 | 32 | endinterface : chan_delay_if 33 | ///////////////////////////////////////////////////////// 34 | `endif 35 | -------------------------------------------------------------------------------- /common/dv/chan_delay_agent/chan_delay_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef _CHAN_DELAY_PKG_ 2 | `define _CHAN_DELAY_PKG_ 3 | //////////////////////////////////////////////////////////////////// 4 | package chan_delay_pkg; 5 | 6 | import uvm_pkg::*; 7 | `include "uvm_macros.svh" 8 | 9 | `include "./chan_delay_seq_item.sv" 10 | `include "./chan_delay_cfg.sv" 11 | `include "./chan_delay_drv.sv" 12 | `include "./chan_delay_mon.sv" 13 | `include "./chan_delay_seqr.sv" 14 | //`include "./chan_delay_fcov_mon.sv" 15 | `include "./chan_delay_agent.sv" 16 | 17 | //////////////////////////////////////////////////////////////////// 18 | endpackage : chan_delay_pkg 19 | `endif 20 | -------------------------------------------------------------------------------- /common/dv/chan_delay_agent/chan_delay_seqr.sv: -------------------------------------------------------------------------------- 1 | `ifndef _CHAN_DELAY_SEQR_ 2 | `define _CHAN_DELAY_SEQR_ 3 | 4 | //////////////////////////////////////////////////////////// 5 | 6 | class chan_delay_seqr_c extends uvm_sequencer #(chan_delay_seq_item_c, chan_delay_seq_item_c); 7 | 8 | // UVM Factory Registration Macro 9 | `uvm_component_utils(chan_delay_seqr_c) 10 | 11 | // Standard UVM Methods: 12 | extern function new(string name="chan_delay_seqr", uvm_component parent = null); 13 | 14 | endclass: chan_delay_seqr_c 15 | //////////////////////////////////////////////////////////// 16 | //--------------------------------------- 17 | function chan_delay_seqr_c::new(string name="chan_delay_seqr", uvm_component parent = null); 18 | super.new(name, parent); 19 | endfunction : new 20 | 21 | //////////////////////////////////////////////////////////// 22 | `endif 23 | -------------------------------------------------------------------------------- /common/dv/reset_agent/reset_cfg.sv: -------------------------------------------------------------------------------- 1 | `ifndef _RESET_CFG_ 2 | `define _RESET_CFG_ 3 | /////////////////////////////////////////////////////////// 4 | 5 | class reset_cfg_c extends uvm_object; 6 | 7 | // UVM Factory Registration Macro 8 | `uvm_object_utils(reset_cfg_c) 9 | 10 | //------------------------------------------ 11 | // Data Members 12 | //------------------------------------------ 13 | 14 | uvm_active_passive_enum active = UVM_ACTIVE; 15 | bit has_func_cov = 0; 16 | 17 | //------------------------------------------ 18 | // constraints 19 | //------------------------------------------ 20 | 21 | //------------------------------------------ 22 | // Methods 23 | //------------------------------------------ 24 | // Standard UVM Methods: 25 | extern function new(string name = "reset_cfg"); 26 | extern function void build_phase( uvm_phase phase ); 27 | extern function void connect_phase( uvm_phase phase ); 28 | extern virtual function void configure( ); 29 | 30 | endclass: reset_cfg_c 31 | 32 | /////////////////////////////////////////////////////////// 33 | function reset_cfg_c::new(string name = "reset_cfg"); 34 | 35 | super.new(name); 36 | 37 | endfunction 38 | 39 | //------------------------------------------ 40 | function void reset_cfg_c::build_phase( uvm_phase phase ); 41 | // 42 | 43 | endfunction: build_phase 44 | //------------------------------------------ 45 | function void reset_cfg_c::connect_phase( uvm_phase phase ); 46 | // 47 | 48 | endfunction: connect_phase 49 | 50 | //------------------------------------------ 51 | function void reset_cfg_c::configure( ); 52 | 53 | active = UVM_ACTIVE; 54 | has_func_cov = 0; 55 | 56 | endfunction: configure 57 | 58 | ////////////////////////////////////////////////////////// 59 | `endif 60 | -------------------------------------------------------------------------------- /common/dv/reset_agent/reset_if.sv: -------------------------------------------------------------------------------- 1 | `ifndef _RESET_IF_ 2 | `define _RESET_IF_ 3 | ///////////////////////////////////////////////////////// 4 | 5 | `include "uvm_macros.svh" 6 | 7 | interface reset_if (input clk); 8 | 9 | logic reset_l; 10 | 11 | //--------------------------------------------------- 12 | modport drv ( 13 | input clk, 14 | output reset_l 15 | ); 16 | 17 | modport mon ( 18 | input clk, 19 | input reset_l 20 | ); 21 | 22 | endinterface : reset_if 23 | 24 | ///////////////////////////////////////////////////////// 25 | `endif 26 | -------------------------------------------------------------------------------- /common/dv/reset_agent/reset_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef _RESET_PKG_ 2 | `define _RESET_PKG_ 3 | //////////////////////////////////////////////////////////////////// 4 | package reset_pkg; 5 | 6 | import uvm_pkg::*; 7 | `include "uvm_macros.svh" 8 | 9 | `include "./reset_seq_item.sv" 10 | `include "./reset_cfg.sv" 11 | `include "./reset_drv.sv" 12 | `include "./reset_mon.sv" 13 | `include "./reset_seq.sv" 14 | `include "./reset_seqr.sv" 15 | //`include "./reset_fcov_mon.sv" 16 | `include "./reset_agent.sv" 17 | 18 | //////////////////////////////////////////////////////////////////// 19 | endpackage : reset_pkg 20 | `endif 21 | -------------------------------------------------------------------------------- /common/dv/reset_agent/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `ifndef _RESET_SEQ_ 2 | `define _RESET_SEQ_ 3 | //////////////////////////////////////////////////////////// 4 | 5 | class reset_seq_c extends uvm_sequence #(reset_seq_item_c); 6 | 7 | `uvm_object_utils(reset_seq_c) 8 | 9 | extern function new(string name = "reset_seq"); 10 | extern task body(); 11 | 12 | endclass : reset_seq_c 13 | 14 | //////////////////////////////////////////////////////////// 15 | 16 | //------------------------------------------ 17 | function reset_seq_c::new(string name = "reset_seq"); 18 | super.new(name); 19 | endfunction : new 20 | 21 | //------------------------------------------ 22 | // body 23 | //------------------------------------------ 24 | task reset_seq_c::body(); 25 | 26 | reset_seq_item_c reset_trig; 27 | 28 | `uvm_info("body", "START reset seq...", UVM_LOW); 29 | 30 | reset_trig = reset_seq_item_c::type_id::create("reset_trig"); 31 | 32 | `uvm_info("body", "Sending reset trigger", UVM_MEDIUM); 33 | start_item(reset_trig); 34 | finish_item(reset_trig); 35 | 36 | `uvm_info("body", "END reset seq...\n", UVM_LOW); 37 | 38 | endtask : body 39 | //////////////////////////////////////////////////////////// 40 | `endif 41 | -------------------------------------------------------------------------------- /common/dv/reset_agent/reset_seq_item.sv: -------------------------------------------------------------------------------- 1 | `ifndef _RESET_SEQ_ITEM_ 2 | `define _RESET_SEQ_ITEM_ 3 | ////////////////////////////////////////////////////////// 4 | class reset_seq_item_c extends uvm_sequence_item ; 5 | 6 | `uvm_object_utils(reset_seq_item_c) 7 | 8 | //------------------------------------------ 9 | // Data Members 10 | //------------------------------------------ 11 | 12 | bit [15:0] active_cycle_cnt = 10; 13 | bit [15:0] post_cycle_cnt = 5; 14 | 15 | //------------------------------------------ 16 | // Sideband Data Members 17 | //------------------------------------------ 18 | 19 | //------------------------------------------ 20 | // constraints 21 | //------------------------------------------ 22 | constraint c_active_cycle_cnt { active_cycle_cnt >= 10 ; active_cycle_cnt <= 20; } 23 | constraint c_post_cyce_cnt { post_cycle_cnt >= 0 ; post_cycle_cnt <= 5; } 24 | 25 | // Standard UVM Methods: 26 | extern function new(string name = "reset_seq_item"); 27 | 28 | endclass : reset_seq_item_c 29 | 30 | //////////////////////////////////////////////////////////// 31 | 32 | //-------------------------------------------------- 33 | function reset_seq_item_c::new (string name = "reset_seq_item"); 34 | super.new(name); 35 | endfunction : new 36 | 37 | ////////////////////////////////////////////////////////// 38 | `endif 39 | -------------------------------------------------------------------------------- /common/dv/reset_agent/reset_seqr.sv: -------------------------------------------------------------------------------- 1 | `ifndef _RESET_SEQR_ 2 | `define _RESET_SEQR_ 3 | 4 | //////////////////////////////////////////////////////////// 5 | 6 | class reset_seqr_c extends uvm_sequencer #(reset_seq_item_c, reset_seq_item_c); 7 | 8 | // UVM Factory Registration Macro 9 | `uvm_component_utils(reset_seqr_c) 10 | 11 | // Standard UVM Methods: 12 | extern function new(string name="reset_seqr", uvm_component parent = null); 13 | 14 | endclass: reset_seqr_c 15 | //////////////////////////////////////////////////////////// 16 | //--------------------------------------- 17 | function reset_seqr_c::new(string name="reset_seqr", uvm_component parent = null); 18 | super.new(name, parent); 19 | endfunction : new 20 | 21 | //////////////////////////////////////////////////////////// 22 | `endif 23 | -------------------------------------------------------------------------------- /common/rtl/README: -------------------------------------------------------------------------------- 1 | These are library files created by John Archambeault in the beginning of 2007. 2 | 3 | They are (from lowest level to highest). 4 | 5 | rrarb.v - round robin arbiter 6 | 7 | syncfifo_mem1r1w.v - RTL encoding of a 1 read 1 write RAM. Can be 8 | replaced with RAM equivalent (FPGA or ASIC). 9 | 10 | syncfifo_reg.v - Generic synchronous (rd clk = wr clk) FIFO. FF Based. 11 | syncfifo_ram.v - Generic synchronous (rd clk = wr clk) FIFO. RAM Based 12 | syncfifo.v - Synchronous FIFO that supports a small syncfifo_reg.sv for Head and a deeper syncfifo_ram.sv 13 | 14 | levelsync.v - Simple double FF for single signals crossing clock domains. 15 | Has a reset value. 16 | 17 | levelsync_sr.v - Same as levelsync, but with reset and set. 18 | 19 | asyncfifo.v - Async FIFO. RAM Based 20 | -------------------------------------------------------------------------------- /common/rtl/common.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/common/rtl/asyncfifo.sv 2 | ${PROJ_DIR}/common/rtl/levelsync_sr.sv 3 | ${PROJ_DIR}/common/rtl/levelsync.sv 4 | ${PROJ_DIR}/common/rtl/rrarb.sv 5 | ${PROJ_DIR}/common/rtl/syncfifo_mem1r1w.sv 6 | ${PROJ_DIR}/common/rtl/syncfifo.sv 7 | ${PROJ_DIR}/common/rtl/level_delay.sv 8 | ${PROJ_DIR}/common/rtl/syncfifo_reg.sv 9 | ${PROJ_DIR}/common/rtl/syncfifo_ram.sv 10 | ${PROJ_DIR}/common/rtl/rst_regen_low.sv 11 | -------------------------------------------------------------------------------- /common/rtl/rst_regen_low.sv: -------------------------------------------------------------------------------- 1 | `ifndef _COMMON_RST_REGEN_LOW_SV 2 | `define _COMMON_RST_REGEN_LOW_SV 3 | //////////////////////////////////////////////////////////// 4 | // 5 | // Copyright (C) 2021 Eximius Design 6 | // 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the "License"); 9 | // you may not use this file except in compliance with the License. 10 | // You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, software 15 | // distributed under the License is distributed on an "AS IS" BASIS, 16 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | // See the License for the specific language governing permissions and 18 | // limitations under the License. 19 | // 20 | //////////////////////////////////////////////////////////// 21 | module rst_regen_low 22 | ( 23 | clk, 24 | async_rst_n, rst_n 25 | ); 26 | 27 | input clk; // Clock 28 | input async_rst_n; // Asynchronous Reset Signal Input (active-low) 29 | output rst_n; // Synchronized Reset Signal Output (active-low) 30 | 31 | levelsync 32 | #( 33 | .RESET_VALUE(1'b0) 34 | ) levelsync_i 35 | ( 36 | .clk_dest (clk), 37 | .rst_dest_n (async_rst_n), 38 | .src_data (1'b1), 39 | .dest_data (rst_n) 40 | ); 41 | 42 | endmodule // rst_regen_low 43 | 44 | `endif 45 | -------------------------------------------------------------------------------- /llink/fpga/.gitignore: -------------------------------------------------------------------------------- 1 | dut_rtl/ 2 | output_files/ 3 | qdb/ 4 | stderr.log 5 | synth_dumps/ 6 | tmp-clearbox/ 7 | -------------------------------------------------------------------------------- /llink/fpga/README.txt: -------------------------------------------------------------------------------- 1 | Run these commands: 2 | 3 | ./setup.sh 4 | 5 | rm -Rf qdb 6 | rm -Rf synth_dumps 7 | rm -Rf tmp-clearbox 8 | 9 | qsub -V -cwd -b y -o /dev/null -e stderr.log quartus two_axi_mm_chiplet & 10 | -------------------------------------------------------------------------------- /llink/fpga/dv/.gitignore: -------------------------------------------------------------------------------- 1 | *.history 2 | *.log 3 | waves.shm 4 | xcelium.d 5 | -------------------------------------------------------------------------------- /llink/fpga/dv/axi_mm_a32_d128_packet_tb.f: -------------------------------------------------------------------------------- 1 | +access+rwc 2 | axi_mm_a32_d128_packet_tb.sv 3 | +libverbose 4 | +libext+.v 5 | +define+FOR_SIM_ONLY 6 | ../two_axi_mm_chiplet.sv 7 | ../fake_phy.sv 8 | -f ../dut_rtl/axi_mm_a32_d128_packet_master.f 9 | -f ../dut_rtl/axi_mm_a32_d128_packet_slave.f 10 | -y . 11 | -l axi_mm_a32_d128_packet_tb.log 12 | -------------------------------------------------------------------------------- /llink/fpga/dv/run_mm_a32_d128_packet: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | 4 | 5 | 6 | ## Build TB 7 | /usr/bin/emacs -batch axi_mm_a32_d128_packet_tb.sv -f verilog-auto -f save-buffer 8 | perl -pi -e '$VARIABLE=1 if (/AUTOREGINPUT/); $VARIABLE=0 if ($VARIABLE&&/End of automatics/); s/;/=0;/ if ($VARIABLE);' axi_mm_a32_d128_packet_tb.sv 9 | 10 | 11 | #Run Sim 12 | xmverilog -f axi_mm_a32_d128_packet_tb.f $* 13 | -------------------------------------------------------------------------------- /llink/fpga/fake_phy.sv: -------------------------------------------------------------------------------- 1 | module fake_phy ( 2 | input logic clk_wr, 3 | 4 | input logic [79:0] tx_phy_master_0, 5 | input logic [79:0] tx_phy_master_1, 6 | input logic [79:0] tx_phy_master_2, 7 | input logic [79:0] tx_phy_master_3, 8 | input logic [79:0] tx_phy_slave_0, 9 | input logic [79:0] tx_phy_slave_1, 10 | input logic [79:0] tx_phy_slave_2, 11 | input logic [79:0] tx_phy_slave_3, 12 | 13 | output logic [79:0] rx_phy_slave_0, 14 | output logic [79:0] rx_phy_slave_1, 15 | output logic [79:0] rx_phy_slave_2, 16 | output logic [79:0] rx_phy_slave_3, 17 | output logic [79:0] rx_phy_master_0, 18 | output logic [79:0] rx_phy_master_1, 19 | output logic [79:0] rx_phy_master_2, 20 | output logic [79:0] rx_phy_master_3 21 | ); 22 | 23 | 24 | always @(posedge clk_wr) 25 | begin 26 | rx_phy_slave_0 <= tx_phy_master_0 ; 27 | rx_phy_slave_1 <= tx_phy_master_1 ; 28 | rx_phy_slave_2 <= tx_phy_master_2 ; 29 | rx_phy_slave_3 <= tx_phy_master_3 ; 30 | rx_phy_master_0 <= tx_phy_slave_0 ; 31 | rx_phy_master_1 <= tx_phy_slave_1 ; 32 | rx_phy_master_2 <= tx_phy_slave_2 ; 33 | rx_phy_master_3 <= tx_phy_slave_3 ; 34 | 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /llink/fpga/two_axi_mm_chiplet.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 08:47:25 April 02, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "08:47:25 April 02, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "two_axi_mm_chiplet" 32 | -------------------------------------------------------------------------------- /llink/fpga/two_axi_mm_chiplet.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -name clk_wr -period 2.000 -waveform { 0.000 1.000 } [get_ports {clk_wr}] 3 | create_clock -name clk_wr_virt -period 2.000 -waveform { 0.000 1.000 } 4 | 5 | -------------------------------------------------------------------------------- /llink/rtl/.gitignore: -------------------------------------------------------------------------------- 1 | xcelium.d/ 2 | xmverilog.history 3 | xmverilog.log 4 | -------------------------------------------------------------------------------- /llink/rtl/build.sh: -------------------------------------------------------------------------------- 1 | /usr/bin/emacs -batch ll_transmit.sv -f verilog-auto -f save-buffer 2 | /usr/bin/emacs -batch ll_receive.sv -f verilog-auto -f save-buffer 3 | -------------------------------------------------------------------------------- /llink/rtl/ll_rx_push.sv: -------------------------------------------------------------------------------- 1 | `ifndef _COMMON_LL_RX_PUSH_SV 2 | `define _COMMON_LL_RX_PUSH_SV 3 | //////////////////////////////////////////////////////////// 4 | // 5 | // Copyright (C) 2021 Eximius Design 6 | // 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the "License"); 9 | // you may not use this file except in compliance with the License. 10 | // You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, software 15 | // distributed under the License is distributed on an "AS IS" BASIS, 16 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | // See the License for the specific language governing permissions and 18 | // limitations under the License. 19 | // 20 | //Functional Descript: 21 | // 22 | // Receive push logic. 23 | // 24 | //////////////////////////////////////////////////////////// 25 | 26 | module ll_rx_push ( 27 | // Control Logic 28 | input logic rx_online , 29 | input logic rx_i_push_ovrd , 30 | 31 | // From Upstream 32 | input logic rx_i_pushbit , 33 | 34 | // To FIFO 35 | output logic rxfifo_i_push 36 | ); 37 | 38 | 39 | assign rxfifo_i_push = rx_i_pushbit & (!rx_i_push_ovrd) & rx_online; 40 | 41 | 42 | endmodule 43 | `endif 44 | 45 | -------------------------------------------------------------------------------- /llink/rtl/ll_tx_ctrl.sv: -------------------------------------------------------------------------------- 1 | `ifndef _COMMON_LL_TX_CTRL_SV 2 | `define _COMMON_LL_TX_CTRL_SV 3 | //////////////////////////////////////////////////////////// 4 | // 5 | // Copyright (C) 2021 Eximius Design 6 | // 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the "License"); 9 | // you may not use this file except in compliance with the License. 10 | // You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, software 15 | // distributed under the License is distributed on an "AS IS" BASIS, 16 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | // See the License for the specific language governing permissions and 18 | // limitations under the License. 19 | // 20 | //Functional Descript: 21 | // 22 | // Transmit control block. 23 | // 24 | //////////////////////////////////////////////////////////// 25 | 26 | module ll_tx_ctrl ( 27 | 28 | output logic txfifo_i_push, 29 | input logic txfifo_i_full, 30 | input logic txfifo_i_pop , 31 | 32 | input logic user_i_valid, 33 | output logic user_i_ready, 34 | 35 | input logic tx_online 36 | 37 | ); 38 | 39 | logic txfifo_i_has_space; 40 | 41 | // Guranteed to have credit if we are popping an entry. 42 | assign txfifo_i_has_space = (~txfifo_i_full) | txfifo_i_pop; 43 | assign user_i_ready = txfifo_i_has_space & tx_online; 44 | assign txfifo_i_push = user_i_valid & user_i_ready; 45 | 46 | endmodule 47 | `endif 48 | -------------------------------------------------------------------------------- /llink/rtl/llink.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/llink/rtl/ll_receive.sv 2 | ${PROJ_DIR}/llink/rtl/ll_rx_ctrl.sv 3 | ${PROJ_DIR}/llink/rtl/ll_rx_push.sv 4 | ${PROJ_DIR}/llink/rtl/ll_transmit.sv 5 | ${PROJ_DIR}/llink/rtl/ll_tx_cred.sv 6 | ${PROJ_DIR}/llink/rtl/ll_tx_ctrl.sv 7 | ${PROJ_DIR}/llink/rtl/ll_auto_sync.sv 8 | -------------------------------------------------------------------------------- /llink/script/.gitignore: -------------------------------------------------------------------------------- 1 | galt.pyc 2 | global_struct.pyc 3 | llink_dv_packet_postproc.pyc 4 | llink_gen.pyc 5 | packetization.pyc 6 | __pycache__ 7 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32/axi_fourchan_a32_d32_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_a32_d32_packet/axi_fourchan_a32_d32_packet_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_tier_top/axi_fourchan_tier_master_top.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_top.sv 2 | // Generated Files 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master_top.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master_concat.sv 5 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_master_name.sv 6 | 7 | // Logic Link files 8 | -f ${PROJ_DIR}/llink/rtl/llink.f 9 | 10 | // Common Files 11 | -f ${PROJ_DIR}/common/rtl/common.f 12 | // Generated Files 13 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_top.sv 14 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_concat.sv 15 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_master_name.sv 16 | 17 | // Logic Link files 18 | -f ${PROJ_DIR}/llink/rtl/llink.f 19 | 20 | // Common Files 21 | -f ${PROJ_DIR}/common/rtl/common.f 22 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_fourchan_tier_top/axi_fourchan_tier_slave_top.f: -------------------------------------------------------------------------------- 1 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_top.sv 2 | // Generated Files 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave_top.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave_concat.sv 5 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier1_a32_d32_packet/axi_fourchan_tier1_a32_d32_packet_slave_name.sv 6 | 7 | // Logic Link files 8 | -f ${PROJ_DIR}/llink/rtl/llink.f 9 | 10 | // Common Files 11 | -f ${PROJ_DIR}/common/rtl/common.f 12 | // Generated Files 13 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_top.sv 14 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_concat.sv 15 | ${PROJ_DIR}/llink/script/premade_examples/axi_fourchan_tier2/axi_fourchan_tier2_slave_name.sv 16 | 17 | // Logic Link files 18 | -f ${PROJ_DIR}/llink/rtl/llink.f 19 | 20 | // Common Files 21 | -f ${PROJ_DIR}/common/rtl/common.f 22 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_lite_a32_d32/axi_lite_a32_d32_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128/axi_mm_a32_d128_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet/axi_mm_a32_d128_packet_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a32_d128_packet_up_rv_2_mem/axi_mm_a32_d128_packet_up_rv_2_mem_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_mm_a48_d512_packet/axi_mm_a48_d512_packet_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d128_asym/axi_st_d128_asym_quarter_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_master_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d256_dm_drng_2_up_full_master_name ( 19 | 20 | // st channel 21 | input logic [ 255: 0] user_tdata , 22 | input logic user_tvalid , 23 | output logic user_tready , 24 | 25 | // Logic Link Interfaces 26 | output logic user_st_vld , 27 | output logic [ 255: 0] txfifo_st_data , 28 | input logic user_st_ready , 29 | 30 | input logic m_gen2_mode 31 | 32 | ); 33 | 34 | // Connect Data 35 | 36 | assign user_st_vld = user_tvalid ; 37 | assign user_tready = user_st_ready ; 38 | assign txfifo_st_data [ 0 +: 256] = user_tdata [ 0 +: 256] ; 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_full_slave_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d256_dm_drng_2_up_full_slave_name ( 19 | 20 | // st channel 21 | output logic [ 255: 0] user_tdata , 22 | output logic user_tvalid , 23 | input logic user_tready , 24 | output logic [ 0: 0] user_enable , 25 | 26 | // Logic Link Interfaces 27 | input logic user_st_vld , 28 | input logic [ 256: 0] rxfifo_st_data , 29 | output logic user_st_ready , 30 | 31 | input logic m_gen2_mode 32 | 33 | ); 34 | 35 | // Connect Data 36 | 37 | assign user_tvalid = user_st_vld ; 38 | assign user_st_ready = user_tready ; 39 | assign user_tdata [ 0 +: 256] = rxfifo_st_data [ 0 +: 256] ; 40 | assign user_enable [ 0 +: 1] = rxfifo_st_data [ 256 +: 1] ; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_master_name.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////// 2 | // 3 | // (C) Copyright 2021 Eximius Design 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | //////////////////////////////////////////////////////////// 17 | 18 | module axi_st_d256_dm_drng_2_up_half_master_name ( 19 | 20 | // st channel 21 | input logic [ 511: 0] user_tdata , 22 | input logic user_tvalid , 23 | output logic user_tready , 24 | 25 | // Logic Link Interfaces 26 | output logic user_st_vld , 27 | output logic [ 511: 0] txfifo_st_data , 28 | input logic user_st_ready , 29 | 30 | input logic m_gen2_mode 31 | 32 | ); 33 | 34 | // Connect Data 35 | 36 | assign user_st_vld = user_tvalid ; 37 | assign user_tready = user_st_ready ; 38 | assign txfifo_st_data [ 0 +: 256] = user_tdata [ 0 +: 256] ; 39 | assign txfifo_st_data [ 256 +: 256] = user_tdata [ 256 +: 256] ; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_dm_drng_2_up/axi_st_d256_dm_drng_2_up_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d256_gen1_gen2/axi_st_d256_gen1_gen2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d64/axi_st_d64_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d64/axi_st_d64_master_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d64/axi_st_d64_master_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d64/axi_st_d64_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /llink/script/premade_examples/axi_st_d64/axi_st_d64_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d64/axi_st_d64_slave_top.sv 3 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d64/axi_st_d64_slave_concat.sv 4 | ${PROJ_DIR}/llink/script/premade_examples/axi_st_d64/axi_st_d64_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/lpif/README -------------------------------------------------------------------------------- /lpif/doc/lpif_adapter_ug.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/lpif/doc/lpif_adapter_ug.pdf -------------------------------------------------------------------------------- /lpif/fpga/README: -------------------------------------------------------------------------------- 1 | rm -rf output_files/ qdb synth_dumps/ tmp-clearbox/ 2 | qsub -V -cwd -b y -o /dev/null -e stderr.log quartus_sh --flow compile lpif_wrap & 3 | 4 | or this for GUI 5 | 6 | qsub -V -cwd -b y -o /dev/null -e stderr.log quartus lpif_wrap & 7 | -------------------------------------------------------------------------------- /lpif/fpga/lpif_wrap.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 08:47:25 April 02, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "08:47:25 April 02, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "lpif_wrap" 32 | -------------------------------------------------------------------------------- /lpif/fpga/lpif_wrap.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/lpif/fpga/lpif_wrap.qws -------------------------------------------------------------------------------- /lpif/fpga/lpif_wrap.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name lclk -period 2.000 -waveform { 0.000 1.000 } [get_ports lclk] 2 | -------------------------------------------------------------------------------- /lpif/full_examples/flist/tb_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | +incdir+${AIB_ROOT}/dv/tb 5 | +incdir+${AIB_ROOT}/dv/interface 6 | +incdir+${AIB_ROOT}/dv/test/task 7 | ${AIBV1_DV_ROOT}/emib/aliasv.sv 8 | ${AIBV1_DV_ROOT}/emib/emib_ch_m1s2.sv 9 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s1.sv 10 | ${AIBV1_DV_ROOT}/emib/emib_ch_m2s2.sv 11 | ${AIBV1_DV_ROOT}/emib/emib_m1s2.sv 12 | ${AIBV1_DV_ROOT}/emib/emib_m2s1.sv 13 | ${AIBV1_DV_ROOT}/emib/emib_m2s2.sv 14 | ${AIBV1_DV_ROOT}/interface/dut_if_mac.sv 15 | ${AIBV1_DV_ROOT}/interface/avalon_mm_if.sv 16 | 17 | ${SIM_DIR}/../common/top_aib.sv 18 | ${SIM_DIR}/../common/device_lpif_intf.v 19 | ${SIM_DIR}/../common/host_lpif_intf.v 20 | ${SIM_DIR}/../common/lpif_csr_intf.v 21 | ${SIM_DIR}/../common/lpif_csr.v 22 | ${SIM_DIR}/../common/jtag2avmm_bridge.v 23 | ${SIM_DIR}/../common/data_checker.v 24 | ${SIM_DIR}/../common/lpif_aib_top.v 25 | -f ${PROJ_DIR}/ca/rtl/ca.f 26 | ${tbench_dir}/tb_top.sv 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_f2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_h2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x16_q2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_f1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x1_h1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_f1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x2_h1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_f2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_h2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x4_q2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_f2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h1_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_h2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx/lpif_txrx_x8_q2_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym1_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x16_asym2_quarter_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x1_asym1_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x2_asym1_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym1_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x4_asym2_quarter_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym1_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_full_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_half_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_master.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_master_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_master_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_master_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_slave.f: -------------------------------------------------------------------------------- 1 | // Generated Files 2 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_slave_top.sv 3 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_slave_concat.sv 4 | ${PROJ_DIR}/lpif/rtl/lpif_txrx_asym/lpif_txrx_x8_asym2_quarter_slave_name.sv 5 | 6 | // Logic Link files 7 | -f ${PROJ_DIR}/llink/rtl/llink.f 8 | 9 | // Common Files 10 | -f ${PROJ_DIR}/common/rtl/common.f 11 | -------------------------------------------------------------------------------- /spi-aib/doc/Chiplet_SPI_User_Guide_v1_0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/spi-aib/doc/Chiplet_SPI_User_Guide_v1_0.pdf -------------------------------------------------------------------------------- /spi-aib/doc/SPI_User_guide_0_8.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/aib-protocols/9e308bfbc95b56f41af8aa34376d4122edec001e/spi-aib/doc/SPI_User_guide_0_8.pptx -------------------------------------------------------------------------------- /spi-aib/dv/flist/aib2.cf: -------------------------------------------------------------------------------- 1 | +incdir+${AIB2_RTL_ROOT} 2 | ${AIB2_RTL_ROOT}/aib_dcc.v 3 | ${AIB2_RTL_ROOT}/aib_aux_channel.v 4 | ${AIB2_RTL_ROOT}/aib_aliasd.v 5 | ${AIB2_RTL_ROOT}/aib_bitsync.v 6 | ${AIB2_RTL_ROOT}/aib_bsr_red_wrap.v 7 | ${AIB2_RTL_ROOT}/aib_buffx1_top.v 8 | ${AIB2_RTL_ROOT}/aib_io_buffer.sv 9 | ${AIB2_RTL_ROOT}/aib_ioring.v 10 | ${AIB2_RTL_ROOT}/aib_jtag_bscan.v 11 | ${AIB2_RTL_ROOT}/aib_mux21.v 12 | #${AIB2_RTL_ROOT}/aib_osc_clk.sv 13 | ${AIB2_RTL_ROOT}/aib_redundancy.v 14 | ${AIB2_RTL_ROOT}/aib_rstnsync.v 15 | ${AIB2_RTL_ROOT}/aib_sm.v 16 | ${AIB2_RTL_ROOT}/aib_sr_ms.v 17 | ${AIB2_RTL_ROOT}/aib_sr_sl.v 18 | ${AIB2_RTL_ROOT}/dll.sv 19 | ${AIB2_RTL_ROOT}/aib_adapt_rxchnl.v 20 | ${AIB2_RTL_ROOT}/aib_adapt_txchnl.v 21 | ${AIB2_RTL_ROOT}/aib_adaptrxdbi_rxdp.v 22 | ${AIB2_RTL_ROOT}/aib_adaptrxdp_async_fifo.v 23 | ${AIB2_RTL_ROOT}/aib_adaptrxdp_fifo.v 24 | ${AIB2_RTL_ROOT}/aib_adaptrxdp_fifo_ptr.v 25 | ${AIB2_RTL_ROOT}/aib_adaptrxdp_fifo_ram.v 26 | ${AIB2_RTL_ROOT}/aib_adapttxdbi_txdp.v 27 | ${AIB2_RTL_ROOT}/aib_adapttxdp_async_fifo.v 28 | ${AIB2_RTL_ROOT}/aib_adapttxdp_fifo.v 29 | ${AIB2_RTL_ROOT}/aib_adapttxdp_fifo_ptr.v 30 | ${AIB2_RTL_ROOT}/aib_adapttxdp_fifo_ram.v 31 | ${AIB2_RTL_ROOT}/aib_adapt_2doto.v 32 | ${AIB2_RTL_ROOT}/aib_avmm_rdl_intf.sv 33 | ${AIB2_RTL_ROOT}/aib_avmm_adapt_csr.v 34 | ${AIB2_RTL_ROOT}/aib_avmm_io_csr.v 35 | ${AIB2_RTL_ROOT}/aib_avmm.v 36 | ${AIB2_RTL_ROOT}/aib_channel.v 37 | ${AIB2_RTL_ROOT}/aib_model_top.v 38 | -------------------------------------------------------------------------------- /spi-aib/dv/flist/spi_rtl.cf: -------------------------------------------------------------------------------- 1 | +incdir+${SPI_ROOT} 2 | ${SPI_ROOT}/mspi_avmm_csr.sv 3 | ${SPI_ROOT}/reg_avmm_csr.sv 4 | ${SPI_ROOT}/app_avmm_csr.sv 5 | ${SPI_ROOT}/mspi_intf.sv 6 | ${SPI_ROOT}/spi_buf_ram.sv 7 | ${SPI_ROOT}/spi_rstnsync.sv 8 | ${SPI_ROOT}/mspi_avmm_intf.sv 9 | ${SPI_ROOT}/spi_bitsync.sv 10 | ${SPI_ROOT}/spi_master.sv 11 | ${SPI_ROOT}/sspi_intf.sv 12 | ${SPI_ROOT}/sspi_avmm_intf.sv 13 | ${SPI_ROOT}/sspi_avmm_csr.sv 14 | ${SPI_ROOT}/spi_slave.sv 15 | -------------------------------------------------------------------------------- /spi-aib/dv/flist/tb_rtl.cf: -------------------------------------------------------------------------------- 1 | # #################################################################### 2 | # tb files 3 | # #################################################################### 4 | +incdir+../tb 5 | +incdir+../interface 6 | +incdir+../test/task 7 | $AIB_DV/emib/aliasv.sv 8 | $AIB_DV/emib/emib_ch_m1s2.sv 9 | $AIB_DV/emib/emib_ch_m2s1.sv 10 | $AIB_DV/emib/emib_ch_m2s2.sv 11 | $AIB_DV/emib/emib_m1s2.sv 12 | $AIB_DV/emib/emib_m2s1.sv 13 | $AIB_DV/emib/emib_m2s2.sv 14 | ../interface/dut_if_mac.sv 15 | ../interface/spi_if.sv 16 | ../interface/avalon_mm_if.sv 17 | ../tb/top_tb.sv 18 | -------------------------------------------------------------------------------- /spi-aib/dv/interface/dut_app_reg.inc: -------------------------------------------------------------------------------- 1 | .user_status(user_status), 2 | .user_csr(user_csr), 3 | 4 | .avmm_rstn(avmm_rstn), 5 | .avmm_clk(avmm_if_sspi0.clk), 6 | .avmm_addr(avmm_if_sspi0.address), 7 | .avmm_byte_en(avmm_if_sspi0.byteenable), 8 | .avmm_read(avmm_if_sspi0.read), 9 | .avmm_write(avmm_if_sspi0.write), 10 | .avmm_wdata(avmm_if_sspi0.writedata), 11 | .avmm_rdatavld(avmm_if_sspi0.readdatavalid), 12 | .avmm_rdata(avmm_if_sspi0.readdata), 13 | .avmm_waitreq(avmm_if_sspi0.waitrequest) 14 | 15 | -------------------------------------------------------------------------------- /spi-aib/dv/interface/dut_mspi_port_ch.inc: -------------------------------------------------------------------------------- 1 | .spi_clk_in(spi_clk), 2 | .sclk(spi_if.sclk), 3 | .ss_n(spi_if.ss_n), 4 | .mosi(spi_if.mosi), 5 | .miso(spi_if.miso), 6 | .rst_n(avmm_rstn), //Make sure drive this signal for init. 7 | //AVMM interface 8 | .avmm_clk(avmm_if_mspi.clk), 9 | // .avmm_rst_n(avmm_if_mspi.rst_n), 10 | .avmm_addr(avmm_if_mspi.address), 11 | .avmm_byte_en(avmm_if_mspi.byteenable), 12 | .avmm_read(avmm_if_mspi.read), 13 | .avmm_write(avmm_if_mspi.write), 14 | .avmm_wdata(avmm_if_mspi.writedata), 15 | 16 | .avmm_rdatavld(avmm_if_mspi.readdatavalid), 17 | .avmm_rdata(avmm_if_mspi.readdata), 18 | .avmm_waitreq(avmm_if_mspi.waitrequest), 19 | .spi_inta(mspi_inta) 20 | 21 | 22 | -------------------------------------------------------------------------------- /spi-aib/dv/interface/dut_sspi_1_port_ch.inc: -------------------------------------------------------------------------------- 1 | .sclk(spi_if.sclk), 2 | .ss_n(spi_if.ss_n[1]), 3 | .mosi(spi_if.mosi), 4 | .miso(spi_if.miso[1]), 5 | .rst_n(avmm_rstn), //Terry:Make sure you drive this signal. 6 | // 7 | //AVMM interface 8 | .avmm_clk(avmm_if_sspi0.clk), 9 | .avmm0_addr(), 10 | .avmm0_byte_en(), 11 | .avmm0_read(), 12 | .avmm0_write(), 13 | .avmm0_wdata(), 14 | .avmm0_rdatavld(1'b0), 15 | .avmm0_rdata(32'h0), 16 | .avmm0_waitreq(1'b0), 17 | .avmm1_addr(), 18 | .avmm1_byte_en(), 19 | .avmm1_read(), 20 | .avmm1_write(), 21 | .avmm1_wdata(), 22 | .avmm1_rdatavld(1'b0), 23 | .avmm1_rdata(32'h0), 24 | .avmm1_waitreq(1'b0), 25 | .avmm2_addr(), 26 | .avmm2_byte_en(), 27 | .avmm2_read(), 28 | .avmm2_write(), 29 | .avmm2_wdata(), 30 | .avmm2_rdatavld(1'b0), 31 | .avmm2_rdata(32'h0), 32 | .avmm2_waitreq(1'b0) 33 | 34 | -------------------------------------------------------------------------------- /spi-aib/dv/interface/dut_sspi_port_ch.inc: -------------------------------------------------------------------------------- 1 | .sclk(spi_if.sclk), 2 | .ss_n(spi_if.ss_n[0]), 3 | .mosi(spi_if.mosi), 4 | .miso(spi_if.miso[0]), 5 | .rst_n(avmm_rstn), //Terry:Make sure you drive this signal. 6 | // 7 | //AVMM interface 8 | .avmm_clk(avmm_if_sspi0.clk), 9 | .avmm0_addr(avmm_if_sspi0.address), 10 | .avmm0_byte_en(avmm_if_sspi0.byteenable), 11 | .avmm0_read(avmm_if_sspi0.read), 12 | .avmm0_write(avmm_if_sspi0.write), 13 | .avmm0_wdata(avmm_if_sspi0.writedata), 14 | .avmm0_rdatavld(avmm_if_sspi0.readdatavalid), 15 | .avmm0_rdata(avmm_if_sspi0.readdata), 16 | .avmm0_waitreq(avmm_if_sspi0.waitrequest), 17 | .avmm1_addr(avmm_if_sspi1.address), 18 | .avmm1_byte_en(avmm_if_sspi1.byteenable), 19 | .avmm1_read(avmm_if_sspi1.read), 20 | .avmm1_write(avmm_if_sspi1.write), 21 | .avmm1_wdata(avmm_if_sspi1.writedata), 22 | .avmm1_rdatavld(avmm_if_sspi1.readdatavalid), 23 | .avmm1_rdata(avmm_if_sspi1.readdata), 24 | .avmm1_waitreq(avmm_if_sspi1.waitrequest), 25 | .avmm2_addr(avmm_if_sspi2.address), 26 | .avmm2_byte_en(avmm_if_sspi2.byteenable), 27 | .avmm2_read(avmm_if_sspi2.read), 28 | .avmm2_write(avmm_if_sspi2.write), 29 | .avmm2_wdata(avmm_if_sspi2.writedata), 30 | .avmm2_rdatavld(avmm_if_sspi2.readdatavalid), 31 | .avmm2_rdata(avmm_if_sspi2.readdata), 32 | .avmm2_waitreq(avmm_if_sspi2.waitrequest) 33 | 34 | -------------------------------------------------------------------------------- /spi-aib/dv/interface/spi_if.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (C) 2019 Intel Corporation. All rights reserved 3 | 4 | `timescale 1ps/1ps 5 | interface spi_if; 6 | 7 | logic sclk; 8 | logic [3:0] ss_n; 9 | logic mosi; 10 | wire [3:0] miso; //Sepearte miso pin, get rid of tristate. 11 | 12 | endinterface : spi_if 13 | -------------------------------------------------------------------------------- /spi-aib/dv/sims/run_compile: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export AIB_PHY="$(pwd)/../../../../aib-phy-hardware-master" 4 | export AIB2_RTL_ROOT="$AIB_PHY/v2.0/rev1/rtl" 5 | export MAIB_RTL_ROOT="$AIB_PHY/v1.0/rev2/rtl/v1_slave" 6 | export SPI_ROOT="$(pwd)/../../rtl" 7 | export AIB_DV="$AIB_PHY/v2.0/rev1/dv" 8 | 9 | vlogan -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps +define+VCS -f ../flist/aib2.cf -l compile_aib2.log 10 | 11 | vlogan -sverilog +v2k -full64 -timescale=1ps/1ps +define+TIMESCALE_EN+VCS+BEHAVIORAL+MAIB_PIN96+ALTR_HPS_INTEL_MACROS_OFF -f ../flist/maib.cf -l compile_maib.log 12 | 13 | vlogan -sverilog +v2k -full64 +vcs+vcdpluson -timescale=1ps/1ps -f ../flist/spi_rtl.cf -l compile_spi.log 14 | 15 | vlogan -sverilog +v2k -full64 -timescale=1ps/1ps -f ../flist/tb_rtl.cf -l compile_tb.log 16 | 17 | vcs -debug_acc+all -full64 +lint=TFIPC-L +error+100 +lint=PCWM -top top_tb -l vcs.log -lca -cm line+cond+tgl+fsm+path+branch+assert 18 | 19 | ./simv -cm line+cond+tgl+fsm+path+branch+assert 20 | 21 | -------------------------------------------------------------------------------- /spi-aib/rtl/spi_bitsync.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (C) 2019 Intel Corporation. 3 | // Standard bit/multi-bit synchronizer. 4 | // User may need to replace this module with technology library synchronizer. 5 | module spi_bitsync 6 | #( 7 | parameter DWIDTH = 1'b1, // Sync Data input 8 | parameter RESET_VAL = 1'b0 // Reset value 9 | ) 10 | ( 11 | input logic clk, // clock 12 | input logic rst_n, // async reset 13 | input logic [DWIDTH-1:0] data_in, // data in 14 | output logic [DWIDTH-1:0] data_out // data out 15 | ); 16 | 17 | 18 | // End users may pass in RESET_VAL with a width exceeding 1 bit 19 | // Evaluate the value first and use 1 bit value 20 | localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1; 21 | 22 | logic [DWIDTH-1:0] dff2; 23 | logic [DWIDTH-1:0] dff1; 24 | 25 | always @(posedge clk or negedge rst_n) 26 | if (!rst_n) begin 27 | dff2 <= {DWIDTH{RESET_VAL_1B}}; 28 | dff1 <= {DWIDTH{RESET_VAL_1B}}; 29 | end 30 | else begin 31 | dff2 <= dff1; 32 | dff1 <= data_in; 33 | end 34 | 35 | assign data_out = dff2; 36 | 37 | 38 | endmodule // aib_bitsync 39 | 40 | -------------------------------------------------------------------------------- /spi-aib/rtl/spi_rstnsync.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright (C) 2019 Intel Corporation. 3 | //--------------------------------------------------------------------------------------- 4 | // Description: For rst_n, asynchronously assertion and sychronously de-assertion (AASD) 5 | // Assumptions: i_rst_n is assumed to be bypassed with scan_clk during scan_mode 6 | //--------------------------------------------------------------------------------------- 7 | 8 | module spi_rstnsync 9 | ( 10 | input logic clk, // Destination clock of reset to be synced 11 | input logic i_rst_n, // Asynchronous reset input 12 | input logic scan_mode, // Scan bypass for reset 13 | output logic sync_rst_n // Synchronized reset output 14 | 15 | ); 16 | 17 | logic first_stg_rst_n; 18 | logic prescan_sync_rst_n; 19 | 20 | always @(posedge clk or negedge i_rst_n) 21 | if (!i_rst_n) 22 | first_stg_rst_n <= 1'b0; 23 | else 24 | first_stg_rst_n <= 1'b1; 25 | 26 | spi_bitsync 27 | #(.DWIDTH(1), .RESET_VAL(0) ) 28 | i_sync_rst_n 29 | ( 30 | .clk (clk ), 31 | .rst_n (i_rst_n ), 32 | .data_in (first_stg_rst_n ), 33 | .data_out (prescan_sync_rst_n) 34 | ); 35 | 36 | assign sync_rst_n = scan_mode ? i_rst_n : prescan_sync_rst_n; 37 | 38 | 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /spi-aib/syn/quartus/spi_master.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 16:49:25 July 21, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "16:49:25 July 21, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "spi_master" 32 | -------------------------------------------------------------------------------- /spi-aib/syn/quartus/spi_slave.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.4.0 Build 72 12/14/2020 SC Pro Edition 22 | # Date created = 16:49:25 July 21, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.4" 27 | DATE = "16:49:25 July 21, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "spi_slave" 32 | --------------------------------------------------------------------------------