├── .github ├── CODEOWNERS ├── ISSUE_TEMPLATE │ ├── bug-report.md │ └── feature-request.md ├── PULL_REQUEST_TEMPLATE.md ├── configs │ └── mergify_config.yml ├── mergify │ └── gen-config.sc ├── scripts │ ├── check-maven-for-llvm-firtool-version.sh │ ├── chisel-example.scala │ └── generate-scala-cli-example.sh └── workflows │ ├── backport-fixup.yml │ ├── build-scala-cli-example.yml │ ├── build-slang │ └── action.yml │ ├── cd-circt.yml │ ├── ci-circt-nightly.yml │ ├── ci.yml │ ├── config │ └── release-notes.json │ ├── enable-bincompat-checking.yml │ ├── install-espresso │ └── action.yml │ ├── install-filecheck │ └── action.yml │ ├── release-notes.yml │ ├── require-label.yml │ ├── scala-cli-example.yml │ ├── setup-oss-cad-suite │ └── action.yml │ └── test.yml ├── .gitignore ├── .mergify.yml ├── .mill-jvm-opts ├── .mill-version ├── .scala-steward.conf ├── .scalafix.conf ├── .scalafmt.conf ├── CONTRIBUTING.md ├── LICENSE ├── PROJECT_CHARTER.md ├── README.md ├── ROADMAP.md ├── SETUP.md ├── benchmark ├── package.mill └── src │ └── main │ └── scala │ └── chisel3 │ └── benchmark │ └── Benchmark.scala ├── build.mill ├── circtpanamabinding ├── includeConstants.txt ├── includeFunctions.txt ├── includeStructs.txt ├── includeTypedefs.txt ├── includeUnions.txt ├── includeVars.txt ├── jextract-headers.h ├── linkLibraries.txt └── package.mill ├── core ├── package.mill └── src │ └── main │ ├── scala-2 │ └── chisel3 │ │ ├── AggregateIntf.scala │ │ ├── BitsIntf.scala │ │ ├── ChiselEnumIntf.scala │ │ ├── ClockIntf.scala │ │ ├── DataIntf.scala │ │ ├── DisableIntf.scala │ │ ├── FormalContractIntf.scala │ │ ├── MemIntf.scala │ │ ├── ModuleIntf.scala │ │ ├── MuxIntf.scala │ │ ├── NumIntf.scala │ │ ├── PrintfIntf.scala │ │ ├── PrintfMacros.scala │ │ ├── SimLogIntf.scala │ │ ├── VerificationStatementIntf.scala │ │ ├── VerificationStatementMacros.scala │ │ ├── experimental │ │ ├── SerializableModuleGenerator.scala │ │ ├── SourceInfoIntf.scala │ │ ├── dataview │ │ │ ├── ChiselSubtypeOf.scala │ │ │ └── InvertibleDataView.scala │ │ └── hierarchy │ │ │ ├── HierarchyPackage.scala │ │ │ ├── InstantiateIntf.scala │ │ │ └── IsA.scala │ │ ├── internal │ │ ├── SourceInfoFileResolver.scala │ │ └── SourceInfoMacro.scala │ │ ├── probe │ │ ├── PackageIntf.scala │ │ ├── Probe.scala │ │ └── ProbeValue.scala │ │ └── properties │ │ └── ObjectIntf.scala │ ├── scala-3 │ └── chisel3 │ │ ├── AggregateIntf.scala │ │ ├── BitsIntf.scala │ │ ├── ChiselEnumIntf.scala │ │ ├── ClockIntf.scala │ │ ├── DataIntf.scala │ │ ├── DisableIntf.scala │ │ ├── FormalContractIntf.scala │ │ ├── MemIntf.scala │ │ ├── ModuleIntf.scala │ │ ├── MuxIntf.scala │ │ ├── NumIntf.scala │ │ ├── PrintfIntf.scala │ │ ├── SimLogIntf.scala │ │ ├── SourceInfoDoc.scala │ │ ├── VerificationStatementIntf.scala │ │ ├── VerificationStatementMacros.scala │ │ ├── experimental │ │ ├── SourceInfoIntf.scala │ │ ├── dataview │ │ │ ├── ChiselSubtypeOf.scala │ │ │ └── InvertibleDataView.scala │ │ └── hierarchy │ │ │ ├── HierarchyMarker.scala │ │ │ ├── InstantiateIntf.scala │ │ │ └── IsA.scala │ │ ├── probe │ │ ├── PackageIntf.scala │ │ ├── Probe.scala │ │ └── ProbeValue.scala │ │ └── properties │ │ └── ObjectIntf.scala │ └── scala │ └── chisel3 │ ├── Aggregate.scala │ ├── Annotation.scala │ ├── Bits.scala │ ├── BlackBox.scala │ ├── BoolFactory.scala │ ├── ChiselEnum.scala │ ├── Clock.scala │ ├── Const.scala │ ├── Data.scala │ ├── Disable.scala │ ├── ElaboratedCircuit.scala │ ├── Element.scala │ ├── FormalContract.scala │ ├── FormalTest.scala │ ├── IO.scala │ ├── Intrinsic.scala │ ├── Layer.scala │ ├── Mem.scala │ ├── Module.scala │ ├── MultiClock.scala │ ├── Mux.scala │ ├── Num.scala │ ├── Placeholder.scala │ ├── Printable.scala │ ├── Printf.scala │ ├── Public.scala │ ├── RawModule.scala │ ├── Reg.scala │ ├── SIntFactory.scala │ ├── SeqUtils.scala │ ├── SimLog.scala │ ├── SramTarget.scala │ ├── UIntFactory.scala │ ├── VerificationStatement.scala │ ├── When.scala │ ├── Width.scala │ ├── choice │ └── package.scala │ ├── connectable │ ├── Alignment.scala │ ├── Connectable.scala │ ├── Connection.scala │ └── package.scala │ ├── dontTouch.scala │ ├── experimental │ ├── Analog.scala │ ├── Attach.scala │ ├── HasAutoTypename.scala │ ├── HasTypeAlias.scala │ ├── IntrinsicModule.scala │ ├── OpaqueType.scala │ ├── SourceInfo.scala │ ├── Targetable.scala │ ├── Trace.scala │ ├── VerificationIntrinsics.scala │ ├── dataview │ │ ├── DataProduct.scala │ │ ├── DataView.scala │ │ └── package.scala │ ├── hierarchy │ │ ├── DefinitionClone.scala │ │ ├── InstanceClone.scala │ │ ├── InstantiableClone.scala │ │ ├── Instantiate.scala │ │ ├── LibraryHooks.scala │ │ ├── ModuleClone.scala │ │ ├── core │ │ │ ├── Definition.scala │ │ │ ├── Hierarchy.scala │ │ │ ├── Instance.scala │ │ │ ├── IsClone.scala │ │ │ ├── IsInstantiable.scala │ │ │ ├── IsLookupable.scala │ │ │ ├── Lookupable.scala │ │ │ └── Underlying.scala │ │ └── package.scala │ ├── package.scala │ └── prefix.scala │ ├── internal │ ├── BiConnect.scala │ ├── Binding.scala │ ├── Builder.scala │ ├── BuilderContextCache.scala │ ├── CIRCTConverter.scala │ ├── CIRCTOM.scala │ ├── CIRCTPassManager.scala │ ├── Error.scala │ ├── InlineTestIncluder.scala │ ├── MonoConnect.scala │ ├── Namer.scala │ ├── Warning.scala │ ├── firrtl │ │ ├── Converter.scala │ │ ├── IR.scala │ │ ├── Serializer.scala │ │ └── package.scala │ ├── package.scala │ └── plugin │ │ └── package.scala │ ├── layers │ ├── Layers.scala │ └── package.scala │ ├── naming │ └── Identifier.scala │ ├── package.scala │ ├── probe │ ├── ProbeBase.scala │ ├── ProbeValueBase.scala │ └── package.scala │ ├── properties │ ├── Class.scala │ ├── Object.scala │ ├── Path.scala │ ├── Property.scala │ └── package.scala │ ├── reflect │ └── DataMirror.scala │ └── util │ └── Naming.scala ├── docs-target └── src │ └── main │ ├── resources │ └── META-INF │ │ └── services │ │ └── mdoc.PostModifier │ └── scala │ └── chisel3 │ └── docs │ ├── VerilogMdocModifier.scala │ └── package.scala ├── docs ├── Contributors.mill ├── FirtoolVersionsTable.mill ├── README.md ├── Releases.mill ├── Version.mill ├── package.mill └── src │ ├── appendix.md │ ├── appendix │ ├── experimental-features.md │ ├── migrating-from-chiseltest.md │ ├── upgrading-from-chisel-3-4.md │ ├── upgrading-from-scala-2-11.md │ └── versioning.md │ ├── cookbooks.md │ ├── cookbooks │ ├── cookbook.md │ ├── dataview.md │ ├── hierarchy.md │ ├── naming.md │ ├── objectmodel.md │ ├── serialization.md │ ├── testing.md │ └── troubleshooting.md │ ├── developers.md │ ├── developers │ ├── lit-test.md │ ├── scaladoc.md │ ├── style.md │ └── test-coverage.md │ ├── explanations.md │ ├── explanations │ ├── annotations.md │ ├── blackboxes.md │ ├── bundles-and-vecs.md │ ├── chisel-enum.md │ ├── chisel-type-vs-scala-type.md │ ├── combinational-circuits.md │ ├── connectable.md │ ├── connection-operators.md │ ├── data-types.md │ ├── dataview.md │ ├── decoder.md │ ├── functional-abstraction.md │ ├── functional-module-creation.md │ ├── instchoice.md │ ├── interfaces-and-connections.md │ ├── intrinsics.md │ ├── layers.md │ ├── memories.md │ ├── moduleprefix.md │ ├── modules.md │ ├── motivation.md │ ├── multi-clock.md │ ├── muxes-and-input-selection.md │ ├── naming.md │ ├── operators.md │ ├── polymorphism-and-parameterization.md │ ├── ports.md │ ├── printing.md │ ├── probes.md │ ├── properties.md │ ├── reset.md │ ├── sequential-circuits.md │ ├── source-locators.md │ ├── supported-hardware.md │ ├── testing.md │ ├── unconnected-wires.md │ ├── warnings.md │ └── width-inference.md │ ├── images │ ├── Makefile │ ├── chisel_01.png │ ├── chisel_logo.png │ ├── chisel_logo.svg │ ├── connection-operators-experiment.svg │ ├── fir_filter.svg │ ├── type_hierarchy.dot │ ├── type_hierarchy.png │ ├── type_hierarchy.svg │ └── vec-forall.svg │ ├── index.md │ ├── installation.md │ ├── resources.md │ └── resources │ └── faqs.md ├── etc ├── README.md └── circt.json ├── firrtl ├── .gitignore ├── README.md ├── benchmark │ ├── scripts │ │ ├── benchmark_cold_compile.py │ │ ├── find_heap_bound.py │ │ └── monitor_job.py │ └── src │ │ └── main │ │ └── scala │ │ └── firrtl │ │ └── benchmark │ │ ├── hot │ │ ├── PassBenchmark.scala │ │ ├── SerializationBenchmark.scala │ │ ├── TransformBenchmark.scala │ │ └── util │ │ │ └── package.scala │ │ └── util │ │ └── package.scala ├── doc │ └── images │ │ ├── firrtl_logo.png │ │ └── firrtl_logo.svg ├── package.mill └── src │ ├── main │ └── scala │ │ ├── firrtl │ │ ├── AttributeAnnotation.scala │ │ ├── Compiler.scala │ │ ├── Emitter.scala │ │ ├── FirrtlException.scala │ │ ├── Parser.scala │ │ ├── PrimOps.scala │ │ ├── RenameMap.scala │ │ ├── Utils.scala │ │ ├── WIR.scala │ │ ├── annotations │ │ │ ├── Annotation.scala │ │ │ ├── AnnotationUtils.scala │ │ │ ├── JsonProtocol.scala │ │ │ ├── LoadMemoryAnnotation.scala │ │ │ ├── MemoryInitAnnotation.scala │ │ │ ├── Target.scala │ │ │ └── TargetToken.scala │ │ ├── graph │ │ │ └── DiGraph.scala │ │ ├── ir │ │ │ ├── IR.scala │ │ │ └── Serializer.scala │ │ ├── options │ │ │ ├── DependencyManager.scala │ │ │ ├── Exceptions.scala │ │ │ ├── ExitCodes.scala │ │ │ ├── OptionParser.scala │ │ │ ├── OptionsView.scala │ │ │ ├── Phase.scala │ │ │ ├── Registration.scala │ │ │ ├── Shell.scala │ │ │ ├── Stage.scala │ │ │ ├── StageAnnotations.scala │ │ │ ├── StageOptions.scala │ │ │ ├── StageUtils.scala │ │ │ ├── internal │ │ │ │ └── WritableCircuitAnnotation.scala │ │ │ ├── package.scala │ │ │ └── phases │ │ │ │ ├── AddDefaults.scala │ │ │ │ ├── Checks.scala │ │ │ │ ├── GetIncludes.scala │ │ │ │ └── WriteOutputAnnotations.scala │ │ ├── package.scala │ │ ├── passes │ │ │ ├── CheckTypes.scala │ │ │ ├── Inline.scala │ │ │ ├── memlib │ │ │ │ ├── MemUtils.scala │ │ │ │ └── ReplaceMemTransform.scala │ │ │ └── wiring │ │ │ │ └── WiringTransform.scala │ │ ├── stage │ │ │ ├── FirrtlAnnotations.scala │ │ │ ├── FirrtlOptions.scala │ │ │ ├── package.scala │ │ │ └── phases │ │ │ │ ├── AddDefaults.scala │ │ │ │ └── Checks.scala │ │ └── transforms │ │ │ ├── BlackBoxSourceHelper.scala │ │ │ ├── Dedup.scala │ │ │ ├── Flatten.scala │ │ │ ├── MustDedup.scala │ │ │ └── OptimizationAnnotations.scala │ │ └── logger │ │ ├── Logger.scala │ │ ├── LoggerAnnotations.scala │ │ ├── LoggerOptions.scala │ │ ├── package.scala │ │ └── phases │ │ ├── AddDefaults.scala │ │ └── Checks.scala │ └── test │ ├── resources │ ├── META-INF │ │ └── services │ │ │ └── firrtl.options.RegisteredLibrary │ └── annotations │ │ └── SampleAnnotations.anno.json │ └── scala │ ├── firrtl │ ├── JsonProtocolSpec.scala │ └── testutils │ │ └── FirrtlSpec.scala │ ├── firrtlTests │ ├── ExtModuleTests.scala │ ├── SerializerSpec.scala │ ├── StringSpec.scala │ ├── annotationTests │ │ ├── AttributeAnnotationSpec.scala │ │ ├── JsonProtocolSpec.scala │ │ ├── LoadMemoryAnnotationSpec.scala │ │ ├── TargetSpec.scala │ │ └── UnrecognizedAnnotationSpec.scala │ ├── graph │ │ └── DiGraphTests.scala │ ├── options │ │ ├── OptionParserSpec.scala │ │ ├── OptionsViewSpec.scala │ │ ├── PhaseManagerSpec.scala │ │ ├── RegistrationSpec.scala │ │ ├── ShellSpec.scala │ │ └── phases │ │ │ ├── AddDefaultsSpec.scala │ │ │ ├── ChecksSpec.scala │ │ │ ├── GetIncludesSpec.scala │ │ │ └── WriteOutputAnnotationsSpec.scala │ └── stage │ │ ├── FirrtlOptionsViewSpec.scala │ │ └── phases │ │ ├── AddDefaultsSpec.scala │ │ └── ChecksSpec.scala │ └── loggertests │ └── LoggerSpec.scala ├── flake.lock ├── flake.nix ├── integration-tests ├── package.mill └── src │ └── test │ └── scala-2 │ └── chiselTest │ ├── LFSRSpec.scala │ ├── MixedVecIntegrationSpec.scala │ ├── QueueFlushSpec.scala │ ├── QueueSpec.scala │ ├── ShiftRegisterMemSpec.scala │ ├── VecIntegrationSpec.scala │ └── util │ ├── SparseVecSpec.scala │ └── experimental │ ├── PlaSpec.scala │ └── TapSpec.scala ├── lit ├── package.mill ├── tests │ ├── Converter │ │ ├── Circuit.sc │ │ ├── Debug.sc │ │ └── Module.sc │ ├── Property │ │ ├── Bad.sc │ │ ├── DocExample.sc │ │ └── Good.sc │ ├── SmokeTest.sc │ ├── lit.cfg.py │ └── lit.site.cfg.py.in └── utility │ ├── package.mill │ └── src │ └── package.scala ├── macros ├── package.mill └── src │ └── main │ └── scala │ └── chisel3 │ ├── SourceInfoDoc.scala │ └── internal │ ├── InstantiableMacro.scala │ ├── RangeTransform.scala │ ├── RuntimeDeprecationTransform.scala │ ├── naming │ ├── Identifier.scala │ └── NamingAnnotations.scala │ └── sourceinfo │ └── SourceInfoTransform.scala ├── mill ├── nix └── sources.json ├── overlay.nix ├── panamaconverter ├── package.mill └── src │ ├── Convert.scala │ ├── PanamaCIRCTConverter.scala │ └── PanamaCIRCTPassManager.scala ├── panamalib ├── package.mill └── src │ ├── FirtoolOptions.scala │ ├── PanamaCIRCT.scala │ └── PanamaFirtoolOption.scala ├── panamaom ├── package.mill └── src │ └── PanamaCIRCTOM.scala ├── plugin ├── README.md ├── package.mill └── src │ └── main │ ├── resources │ ├── plugin.properties │ └── scalac-plugin.xml │ ├── scala-2 │ └── chisel3 │ │ └── internal │ │ ├── plugin │ │ ├── BundleComponent.scala │ │ ├── ChiselComponent.scala │ │ ├── ChiselPlugin.scala │ │ ├── ChiselUtils.scala │ │ └── IdentifierComponent.scala │ │ └── sourceinfo │ │ └── SourceInfoFileResolver.scala │ └── scala-3 │ └── chisel3 │ └── internal │ └── plugin │ ├── ChiselComponent.scala │ └── ChiselComponentHelpers.scala ├── release.mill ├── root-doc.txt ├── src ├── main │ ├── resources │ │ └── chisel3 │ │ │ ├── Makefile │ │ │ └── top.cpp │ ├── scala-2 │ │ └── chisel3 │ │ │ ├── FixedIOModule.scala │ │ │ ├── aop │ │ │ └── Select.scala │ │ │ ├── choice │ │ │ └── ModuleChoiceIntf.scala │ │ │ ├── experimental │ │ │ └── util │ │ │ │ └── SerializableModuleElaborator.scala │ │ │ ├── interface │ │ │ └── Interface.scala │ │ │ ├── ltl │ │ │ └── LTL.scala │ │ │ └── util │ │ │ ├── BitPatIntf.scala │ │ │ ├── BitwiseIntf.scala │ │ │ ├── CatIntf.scala │ │ │ ├── MuxIntf.scala │ │ │ ├── RegIntf.scala │ │ │ ├── SRAM.scala │ │ │ ├── Switch.scala │ │ │ ├── circt │ │ │ └── LTLIntrinsics.scala │ │ │ └── util.scala │ ├── scala-3 │ │ └── chisel3 │ │ │ ├── FixedIOModule.scala │ │ │ ├── choice │ │ │ └── ModuleChoiceIntf.scala │ │ │ └── util │ │ │ ├── BitPatIntf.scala │ │ │ ├── BitwiseIntf.scala │ │ │ ├── CatIntf.scala │ │ │ ├── MuxIntf.scala │ │ │ ├── RegIntf.scala │ │ │ └── Switch.scala │ └── scala │ │ ├── chisel3 │ │ ├── UnitTest.scala │ │ ├── UnitTestMain.scala │ │ ├── choice │ │ │ └── ModuleChoice.scala │ │ ├── experimental │ │ │ ├── conversions │ │ │ │ └── package.scala │ │ │ ├── inlinetest │ │ │ │ └── InlineTest.scala │ │ │ └── util │ │ │ │ └── algorithm │ │ │ │ └── Bitwise.scala │ │ ├── simulator │ │ │ ├── ControlAPI.scala │ │ │ ├── EphemeralSimulator.scala │ │ │ ├── HasSimulator.scala │ │ │ ├── LayerControl.scala │ │ │ ├── OptionsModifications.scala │ │ │ ├── PeekPokeAPI.scala │ │ │ ├── Randomization.scala │ │ │ ├── Settings.scala │ │ │ ├── Simulator.scala │ │ │ ├── SimulatorAPI.scala │ │ │ ├── package.scala │ │ │ ├── scalatest │ │ │ │ ├── Cli.scala │ │ │ │ ├── HasCliOptions.scala │ │ │ │ └── package.scala │ │ │ └── stimulus │ │ │ │ ├── ResetProcedure.scala │ │ │ │ ├── RunUntilFinished.scala │ │ │ │ ├── RunUntilSuccess.scala │ │ │ │ └── Stimulus.scala │ │ ├── stage │ │ │ ├── ChiselAnnotations.scala │ │ │ ├── ChiselOptions.scala │ │ │ ├── package.scala │ │ │ └── phases │ │ │ │ ├── AddDedupGroupAnnotations.scala │ │ │ │ ├── AddImplicitOutputAnnotationFile.scala │ │ │ │ ├── AddImplicitOutputFile.scala │ │ │ │ ├── AddSerializationAnnotations.scala │ │ │ │ ├── Checks.scala │ │ │ │ ├── Convert.scala │ │ │ │ ├── Elaborate.scala │ │ │ │ └── Emitter.scala │ │ ├── testing │ │ │ ├── FileCheck.scala │ │ │ ├── HasTestingDirectory.scala │ │ │ └── scalatest │ │ │ │ ├── HasConfigMap.scala │ │ │ │ ├── WithTestingDirectory.scala │ │ │ │ └── package.scala │ │ ├── util │ │ │ ├── Arbiter.scala │ │ │ ├── AttributeAnnotation.scala │ │ │ ├── BitPat.scala │ │ │ ├── Bitwise.scala │ │ │ ├── BlackBoxUtils.scala │ │ │ ├── Cat.scala │ │ │ ├── CircuitMath.scala │ │ │ ├── Conditional.scala │ │ │ ├── Counter.scala │ │ │ ├── Decoupled.scala │ │ │ ├── Enum.scala │ │ │ ├── ExtModuleUtils.scala │ │ │ ├── GrayCode.scala │ │ │ ├── ImplicitConversions.scala │ │ │ ├── Irrevocable.scala │ │ │ ├── Lookup.scala │ │ │ ├── Math.scala │ │ │ ├── MixedVec.scala │ │ │ ├── Mux.scala │ │ │ ├── OneHot.scala │ │ │ ├── Pipe.scala │ │ │ ├── Queue.scala │ │ │ ├── ReadyValidIO.scala │ │ │ ├── Reg.scala │ │ │ ├── SparseVec.scala │ │ │ ├── Valid.scala │ │ │ ├── circt │ │ │ │ ├── ClockGate.scala │ │ │ │ ├── DPI.scala │ │ │ │ ├── IsX.scala │ │ │ │ ├── PlusArgsTest.scala │ │ │ │ ├── PlusArgsValue.scala │ │ │ │ ├── SizeOf.scala │ │ │ │ └── Synthesis.scala │ │ │ ├── experimental │ │ │ │ ├── AutoBlackBox.scala │ │ │ │ ├── BoringUtils.scala │ │ │ │ ├── CIRCTSRAMInterface.scala │ │ │ │ ├── ForceNames.scala │ │ │ │ ├── Inline.scala │ │ │ │ ├── LoadMemoryTransform.scala │ │ │ │ ├── SlangUtils.scala │ │ │ │ ├── decode │ │ │ │ │ ├── DecodeTableAnnotation.scala │ │ │ │ │ ├── DecoderBundle.scala │ │ │ │ │ ├── EspressoMinimizer.scala │ │ │ │ │ ├── Minimizer.scala │ │ │ │ │ ├── QMCMinimizer.scala │ │ │ │ │ ├── TruthTable.scala │ │ │ │ │ └── decoder.scala │ │ │ │ └── getAnnotations.scala │ │ │ ├── pla.scala │ │ │ └── random │ │ │ │ ├── FibonacciLFSR.scala │ │ │ │ ├── GaloisLFSR.scala │ │ │ │ ├── LFSR.scala │ │ │ │ └── PRNG.scala │ │ └── verilog.scala │ │ └── circt │ │ ├── Convention.scala │ │ ├── Implicits.scala │ │ ├── OutputDirAnnotation.scala │ │ └── stage │ │ ├── Annotations.scala │ │ ├── CIRCTOptions.scala │ │ ├── ChiselStage.scala │ │ ├── Shell.scala │ │ ├── package.scala │ │ └── phases │ │ ├── AddImplicitOutputFile.scala │ │ ├── CIRCT.scala │ │ └── Checks.scala └── test │ ├── resources │ └── chisel3 │ │ ├── AnalogBlackBox.v │ │ ├── BlackBoxTest.v │ │ ├── VerilogVendingMachine.v │ │ ├── simulator │ │ ├── Baz.sv │ │ └── Qux.sv │ │ ├── sourceroot1 │ │ └── Foo │ │ └── sourceroot2 │ │ └── Foo │ └── scala-2 │ ├── chisel3 │ ├── PlaceholderSpec.scala │ ├── SelectSpec.scala │ ├── TypeEquivalenceSpec.scala │ ├── experimental │ │ └── dataview │ │ │ └── ReifySpec.scala │ ├── internal │ │ ├── ContainsProbeSpec.scala │ │ ├── IdentifierSpec.scala │ │ ├── NameCollisionSpec.scala │ │ └── NamespaceSpec.scala │ ├── stage │ │ └── ChiselOptionsViewSpec.scala │ ├── testers │ │ └── TestUtils.scala │ └── util │ │ ├── BitPatSpec.scala │ │ └── experimental │ │ └── decode │ │ └── TruthTableSpec.scala │ ├── chiselTests │ ├── AdderTree.scala │ ├── AnalogIntegrationSpec.scala │ ├── AnalogSpec.scala │ ├── AnnotatingDiamondSpec.scala │ ├── AnnotationInlineSpec.scala │ ├── AnnotationNoDedup.scala │ ├── AsTypeOfTester.scala │ ├── Assert.scala │ ├── AsyncResetSpec.scala │ ├── AutoClonetypeSpec.scala │ ├── AutoNestedCloneSpec.scala │ ├── BetterNamingTests.scala │ ├── BitwiseOps.scala │ ├── BlackBox.scala │ ├── BlackBoxImpl.scala │ ├── BoolSpec.scala │ ├── BoringUtilsSpec.scala │ ├── BoringUtilsTapSpec.scala │ ├── BulkConnectSpec.scala │ ├── BundleElementsSpec.scala │ ├── BundleLiteralSpec.scala │ ├── BundleSpec.scala │ ├── BundleWire.scala │ ├── ChiselEnum.scala │ ├── ChiselTestUtilitiesSpec.scala │ ├── ClockSpec.scala │ ├── CloneModuleSpec.scala │ ├── ComplexAssign.scala │ ├── ConnectSpec.scala │ ├── ConnectableSpec.scala │ ├── ConstSpec.scala │ ├── Counter.scala │ ├── CustomBundle.scala │ ├── DPISpec.scala │ ├── DataEqualitySpec.scala │ ├── DataPrint.scala │ ├── Decoder.scala │ ├── DecoupledSpec.scala │ ├── DedupSpec.scala │ ├── Direction.scala │ ├── DisableSpec.scala │ ├── DontTouchSpec.scala │ ├── EnableShiftRegister.scala │ ├── EnumSpec.scala │ ├── ExtModule.scala │ ├── ExtModuleImpl.scala │ ├── FixedIOModuleSpec.scala │ ├── FormalContractSpec.scala │ ├── GCD.scala │ ├── IOCompatibility.scala │ ├── IllegalRefSpec.scala │ ├── ImplicitConversionsSpec.scala │ ├── InlineSpec.scala │ ├── InstanceNameSpec.scala │ ├── IntegerMathSpec.scala │ ├── IntrinsicModule.scala │ ├── IntrinsicSpec.scala │ ├── InvalidateAPISpec.scala │ ├── LTLSpec.scala │ ├── LayerSpec.scala │ ├── LazyCloneSpec.scala │ ├── LiteralExtractorSpec.scala │ ├── LiteralToTargetSpec.scala │ ├── LoadMemoryFromFileSpec.scala │ ├── LogUtils.scala │ ├── Math.scala │ ├── Mem.scala │ ├── MemorySearch.scala │ ├── MixedVecSpec.scala │ ├── ModuleChoiceSpec.scala │ ├── ModulePrefixSpec.scala │ ├── ModuleSpec.scala │ ├── MulLookup.scala │ ├── MultiAssign.scala │ ├── MultiClockSpec.scala │ ├── MuxSpec.scala │ ├── NamedModuleTester.scala │ ├── NewAnnotationsSpec.scala │ ├── OneHotMuxSpec.scala │ ├── OptionBundle.scala │ ├── Padding.scala │ ├── ParameterizedModule.scala │ ├── PopCount.scala │ ├── PortSpec.scala │ ├── PrintableSpec.scala │ ├── Printf.scala │ ├── ProbeSpec.scala │ ├── PropertyUtils.scala │ ├── PublicModuleSpec.scala │ ├── RawModuleSpec.scala │ ├── ReadOnlySpec.scala │ ├── RebindingSpec.scala │ ├── RecordSpec.scala │ ├── ReduceTreeSpec.scala │ ├── RegSpec.scala │ ├── ResetSpec.scala │ ├── Risc.scala │ ├── SIntOps.scala │ ├── SimLogSpec.scala │ ├── SourceLocatorSpec.scala │ ├── Stack.scala │ ├── Stop.scala │ ├── SwitchSpec.scala │ ├── Tbl.scala │ ├── ToTargetSpec.scala │ ├── TypeAliasSpec.scala │ ├── UIntOps.scala │ ├── UnitTestMainSpec.scala │ ├── Util.scala │ ├── ValidSpec.scala │ ├── Vec.scala │ ├── VecLiteralSpec.scala │ ├── VecToTargetSpec.scala │ ├── VectorPacketIO.scala │ ├── VerificationSpec.scala │ ├── WarningSpec.scala │ ├── WhenSpec.scala │ ├── WidthSpec.scala │ ├── WireSpec.scala │ ├── aop │ │ └── SelectSpec.scala │ ├── experimental │ │ ├── AutoBlackBoxSpec.scala │ │ ├── AutoTypenameSpec.scala │ │ ├── CIRCTSRAMInterfaceSpec.scala │ │ ├── DataView.scala │ │ ├── DataViewIntegrationSpec.scala │ │ ├── DataViewTargetSpec.scala │ │ ├── ExtensionMethods.scala │ │ ├── FlatIOSpec.scala │ │ ├── ForceNames.scala │ │ ├── InlineTestSpec.scala │ │ ├── ModuleDataProductSpec.scala │ │ ├── OpaqueTypeSpec.scala │ │ ├── ProgrammaticPortsSpec.scala │ │ ├── SerializableModuleElaboratorSpec.scala │ │ ├── SerializableModuleGeneratorSpec.scala │ │ ├── TraceSpec.scala │ │ ├── Tuple.scala │ │ └── hierarchy │ │ │ ├── Annotations.scala │ │ │ ├── DefinitionSpec.scala │ │ │ ├── Examples.scala │ │ │ ├── InstanceSpec.scala │ │ │ ├── InstantiateSpec.scala │ │ │ ├── SeparateElaborationSpec.scala │ │ │ └── Utils.scala │ ├── interface │ │ ├── Drivers.scala │ │ ├── InterfaceSpec.scala │ │ ├── ParametricInterfaceSpec.scala │ │ └── TappedInterfaceSpec.scala │ ├── naming │ │ ├── IdentifierProposerSpec.scala │ │ ├── NamePluginSpec.scala │ │ ├── PrefixSpec.scala │ │ └── TypenameSpec.scala │ ├── properties │ │ ├── ClassSpec.scala │ │ ├── ObjectSpec.scala │ │ └── PropertySpec.scala │ ├── reflect │ │ ├── CheckTypeEquivalenceSpec.scala │ │ └── DataMirrorSpec.scala │ ├── simulator │ │ ├── EphemeralSimulatorSpec.scala │ │ ├── GCD.scala │ │ ├── HasSimulatorSpec.scala │ │ ├── LayerControlSpec.scala │ │ ├── OptionalIOModule.scala │ │ ├── SimulatorSpec.scala │ │ └── scalatest │ │ │ ├── ChiselSimSpec.scala │ │ │ └── HasCliOptionsSpec.scala │ ├── stage │ │ ├── ChiselAnnotationsSpec.scala │ │ ├── WarningConfigurationSpec.scala │ │ └── phases │ │ │ ├── AddImplicitOutputAnnotationFileSpec.scala │ │ │ ├── AddImplicitOutputFileSpec.scala │ │ │ ├── AddSerializationAnnotationsSpec.scala │ │ │ ├── ChecksSpec.scala │ │ │ ├── ConvertSpec.scala │ │ │ ├── ElaborateSpec.scala │ │ │ └── EmitterSpec.scala │ ├── testing │ │ ├── FileCheckSpec.scala │ │ ├── HasTestingDirectorySpec.scala │ │ └── scalatest │ │ │ ├── HasConfigMapSpec.scala │ │ │ └── TestingDirectorySpec.scala │ └── util │ │ ├── AttributeAnnotationSpec.scala │ │ ├── BitSetSpec.scala │ │ ├── BitwiseSpec.scala │ │ ├── CatSpec.scala │ │ ├── PipeSpec.scala │ │ ├── PriorityMuxSpec.scala │ │ ├── RegSpec.scala │ │ ├── SRAMSpec.scala │ │ ├── circt │ │ ├── ClockGate.scala │ │ ├── IsXSpec.scala │ │ ├── PlusArgsTestSpec.scala │ │ ├── PlusArgsValueSpec.scala │ │ ├── SizeOfSpec.scala │ │ └── Synthesis.scala │ │ ├── experimental │ │ └── DecoderTableSpec.scala │ │ └── random │ │ └── PRNGSpec.scala │ ├── circtTests │ ├── ConventionSpec.scala │ ├── OutputDirAnnotationSpec.scala │ └── stage │ │ ├── ChiselMainSpec.scala │ │ ├── ChiselStageSpec.scala │ │ └── phases │ │ └── AddImplicitOutputFileSpec.scala │ ├── cookbook │ ├── Bundle2UInt.scala │ ├── CookbookSpec.scala │ ├── FSM.scala │ ├── RegOfVec.scala │ ├── UInt2Bundle.scala │ ├── UInt2VecOfBool.scala │ └── VecOfBool2UInt.scala │ └── examples │ ├── ImplicitStateVendingMachine.scala │ ├── SimpleVendingMachine.scala │ ├── VendingMachineGenerator.scala │ └── VendingMachineUtils.scala ├── stdlib ├── package.mill └── src │ └── main │ └── scala │ └── chisel3 │ └── std │ └── BarrelShifter.scala ├── svsim ├── .clang-format ├── README.md ├── package.mill └── src │ ├── main │ ├── resources │ │ └── simulation-driver.cpp │ └── scala │ │ ├── Backend.scala │ │ ├── Simulation.scala │ │ ├── Workspace.scala │ │ ├── vcs │ │ └── Backend.scala │ │ └── verilator │ │ └── Backend.scala │ └── test │ ├── resources │ ├── Finish.sv │ ├── GCD.sv │ ├── Initial.sv │ ├── PlusArg.sv │ └── SIntTest.sv │ └── scala │ ├── BackendSpec.scala │ └── Resources.scala └── website ├── .gitignore ├── Makefile ├── README.md ├── babel.config.js ├── blog ├── 2025 │ ├── 01-07-restarting-the-blog │ │ └── index.md │ └── 05-05-latch-up │ │ └── index.md ├── authors.yml └── tags.yml ├── docusaurus.config.js ├── package.json ├── sidebars.js ├── src ├── components │ └── HomepageFeatures │ │ ├── index.js │ │ └── styles.module.css ├── css │ └── custom.css └── pages │ ├── api.md │ ├── api │ └── chisel3 │ │ └── latest.js │ ├── community.md │ ├── index.js │ └── index.module.css └── static ├── .nojekyll ├── CNAME ├── img ├── chips-alliance.svg ├── chisel-tool-icon.svg ├── chisel-tool.svg ├── firrtl-tech.svg ├── firrtl_logo.svg └── scala.svg └── robots.txt /.github/CODEOWNERS: -------------------------------------------------------------------------------- 1 | * @freechipsproject/chisel-reviewers 2 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug-report.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Bug Report 3 | about: Report a problem you experienced with chisel3 4 | --- 5 | 6 | 7 | 10 | **Type of issue**: Bug Report 11 | 12 | **Please provide the steps to reproduce the problem:** 13 | 14 | **What is the current behavior?** 15 | 16 | **What is the expected behavior?** 17 | 18 | **Please tell us about your environment:** 19 | 23 | 24 | **Other Information** 25 | 26 | 27 | **What is the use case for changing the behavior?** 28 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/feature-request.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Feature Request 3 | about: Request a new feature or change in functionality in chisel3 4 | --- 5 | 6 | 7 | 8 | **Type of issue**: Feature Request 9 | 10 | **Is your feature request related to a problem? Please describe.** 11 | A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] 12 | 13 | **Describe the solution you'd like** 14 | A clear and concise description of what you want to happen. 15 | 16 | **Describe alternatives you've considered** 17 | A clear and concise description of any alternative solutions or features you've considered. 18 | 19 | **Additional context** 20 | Include detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, eg. Stack Overflow, gitter, [Scastie](https://scastie.scala-lang.org/KtzZQ3nFTea9KoNh0tRqtg). 21 | 22 | **What is the use case for implementing this feature?** 23 | -------------------------------------------------------------------------------- /.github/configs/mergify_config.yml: -------------------------------------------------------------------------------- 1 | # Configuration for generating .mergify.yml 2 | conditions: 3 | - status-success=all tests passed 4 | branches: 5 | - 3.6.x 6 | - 5.x 7 | - 6.x 8 | -------------------------------------------------------------------------------- /.github/scripts/check-maven-for-llvm-firtool-version.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Strip firtool- prefix from argument 4 | VERSION=${1#firtool-} 5 | 6 | POM="https://repo1.maven.org/maven2/org/chipsalliance/llvm-firtool/$VERSION/llvm-firtool-$VERSION.pom" 7 | 8 | # Return 1 if not found 9 | curl -o/dev/null -sfIL "$POM" || false 10 | -------------------------------------------------------------------------------- /.github/scripts/chisel-example.scala: -------------------------------------------------------------------------------- 1 | //> using repository "sonatype-s01:snapshots" 2 | //> using scala "2.13.16" 3 | //> using dep "org.chipsalliance::chisel:@VERSION@" 4 | //> using plugin "org.chipsalliance:::chisel-plugin:@VERSION@" 5 | //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations" 6 | 7 | import chisel3._ 8 | // _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._ 9 | import _root_.circt.stage.ChiselStage 10 | 11 | class Foo extends Module { 12 | val a, b, c = IO(Input(Bool())) 13 | val d, e, f = IO(Input(Bool())) 14 | val foo, bar = IO(Input(UInt(8.W))) 15 | val out = IO(Output(UInt(8.W))) 16 | 17 | val myReg = RegInit(0.U(8.W)) 18 | out := myReg 19 | 20 | when(a && b && c) { 21 | myReg := foo 22 | } 23 | when(d && e && f) { 24 | myReg := bar 25 | } 26 | } 27 | 28 | object Main extends App { 29 | println( 30 | ChiselStage.emitSystemVerilog( 31 | gen = new Foo, 32 | firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable") 33 | ) 34 | ) 35 | } 36 | -------------------------------------------------------------------------------- /.github/scripts/generate-scala-cli-example.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | if [ "$#" -ne 1 ]; then 4 | echo "Error: This script requires exactly 1 argument." 5 | echo "Usage: $0 " 6 | exit 1 7 | fi 8 | 9 | THISDIR=$(dirname "$0") 10 | VERSION=$1 11 | 12 | sed "s/@VERSION@/$VERSION/g" $THISDIR/chisel-example.scala 13 | -------------------------------------------------------------------------------- /.github/workflows/build-slang/action.yml: -------------------------------------------------------------------------------- 1 | name: Build Slang 2 | 3 | inputs: 4 | version: 5 | description: 'version to install' 6 | required: false 7 | default: '7.0' 8 | 9 | runs: 10 | using: composite 11 | steps: 12 | - id: cache-slang 13 | uses: actions/cache@v4 14 | with: 15 | path: /usr/local/bin/slang 16 | key: slang-${{ runner.os }}-${{ inputs.version }} 17 | - name: Build from source 18 | shell: bash 19 | if: steps.cache-slang.outputs.cache-hit != 'true' 20 | run: | 21 | cd /tmp 22 | wget -q https://github.com/MikePopoloski/slang/archive/refs/tags/v${{ inputs.version }}.tar.gz -O slang.tar.gz 23 | tar xf slang.tar.gz 24 | cd slang-${{ inputs.version }} 25 | cmake -B build 26 | cmake --build build 27 | cd build && ctest --output-on-failure 28 | cp bin/slang /usr/local/bin/slang 29 | slang || true 30 | -------------------------------------------------------------------------------- /.github/workflows/cd-circt.yml: -------------------------------------------------------------------------------- 1 | name: 'CD (firtool)' 2 | 3 | on: 4 | workflow_dispatch: 5 | # Run every 15 minutes. 6 | schedule: 7 | - cron: '*/15 * * * *' 8 | 9 | jobs: 10 | cd-circt: 11 | name: 'Check Version, Create PR' 12 | runs-on: ubuntu-24.04 13 | steps: 14 | - name: 'circt/update-circt' 15 | uses: circt/update-circt@eacb8963f4f0872649ef5bb3245894929ddebe58 # v1.1.1 16 | with: 17 | user: chiselbot 18 | email: chiselbot@users.noreply.github.com 19 | pr-labels: | 20 | Dependency Update 21 | pr-reviewers: | 22 | seldridge 23 | jackkoenig 24 | should-create-pr: '.github/scripts/check-maven-for-llvm-firtool-version.sh' 25 | github-token: ${{ secrets.CHISEL_BOT_TOKEN }} 26 | -------------------------------------------------------------------------------- /.github/workflows/install-espresso/action.yml: -------------------------------------------------------------------------------- 1 | name: Install Espresso 2 | 3 | inputs: 4 | version: 5 | description: 'version to install' 6 | required: false 7 | default: '2.4' 8 | 9 | runs: 10 | using: composite 11 | steps: 12 | - id: cache-espresso 13 | uses: actions/cache@v4 14 | with: 15 | path: /usr/local/bin/espresso 16 | key: espresso-${{ runner.os }}-${{ inputs.version }} 17 | 18 | - shell: bash 19 | if: steps.cache-espresso.outputs.cache-hit != 'true' 20 | run: | 21 | cd /tmp 22 | wget -q https://github.com/chipsalliance/espresso/releases/download/v${{ inputs.version }}/x86_64-linux-gnu-espresso 23 | chmod +x x86_64-linux-gnu-espresso 24 | sudo mv x86_64-linux-gnu-espresso /usr/local/bin/espresso 25 | espresso || true 26 | -------------------------------------------------------------------------------- /.github/workflows/install-filecheck/action.yml: -------------------------------------------------------------------------------- 1 | name: Install FileCheck 2 | 3 | inputs: 4 | version: 5 | description: 'version to install' 6 | required: false 7 | default: 'FileCheck-16.0.6-test' 8 | 9 | runs: 10 | using: composite 11 | steps: 12 | - id: cache-filecheck 13 | uses: actions/cache@v3 14 | with: 15 | path: FileCheck 16 | key: filecheck-${{ runner.os }}-${{ inputs.version }} 17 | 18 | - shell: bash 19 | if: steps.cache-filecheck.outputs.cache-hit != 'true' 20 | run: | 21 | mkdir -p filecheck/bin 22 | wget -q https://github.com/jackkoenig/FileCheck/releases/download/${{ inputs.version }}/FileCheck-linux-x64 23 | chmod +x FileCheck-linux-x64 24 | mv FileCheck-linux-x64 filecheck/bin/FileCheck 25 | 26 | - shell: bash 27 | run: echo "$(pwd)/filecheck/bin" >> $GITHUB_PATH 28 | -------------------------------------------------------------------------------- /.github/workflows/require-label.yml: -------------------------------------------------------------------------------- 1 | name: Require Release Notes Label 2 | 3 | on: 4 | pull_request: 5 | branches: 6 | - main 7 | types: 8 | - opened 9 | - synchronize 10 | - reopened 11 | - labeled 12 | - unlabeled 13 | 14 | jobs: 15 | check_labels: 16 | name: Check Labels 17 | runs-on: ubuntu-24.04 18 | steps: 19 | - uses: docker://agilepathway/pull-request-label-checker:v1.6.32 20 | with: 21 | one_of: Feature,Performance,API Modification,Deprecation,Backend Code Generation,Bugfix,Documentation,Dependency Update,Internal,Scala 3,No Release Notes 22 | repo_token: ${{ secrets.GITHUB_TOKEN }} 23 | -------------------------------------------------------------------------------- /.github/workflows/scala-cli-example.yml: -------------------------------------------------------------------------------- 1 | name: Generate Chisel Scala CLI Example 2 | 3 | on: 4 | release: 5 | types: [created] 6 | workflow_dispatch: 7 | 8 | jobs: 9 | generate_scala_cli_example: 10 | name: Generate Scala CLI Example 11 | uses: ./.github/workflows/build-scala-cli-example.yml 12 | 13 | publish_example: 14 | name: Generate Chisel Scala CLI Example 15 | needs: [generate_scala_cli_example] 16 | runs-on: ubuntu-24.04 17 | permissions: 18 | contents: write 19 | 20 | steps: 21 | - name: Download Generated CLI Example 22 | uses: actions/download-artifact@v4 23 | with: 24 | name: chisel-example.scala 25 | - name: Display Example 26 | run: | 27 | echo '```scala' >> $GITHUB_STEP_SUMMARY 28 | cat chisel-example.scala >> $GITHUB_STEP_SUMMARY 29 | echo '```' >> $GITHUB_STEP_SUMMARY 30 | - name: Upload To Release Page 31 | if: github.event_name == 'release' 32 | uses: softprops/action-gh-release@01570a1f39cb168c169c802c3bceb9e93fb10974 # v2.1.0 33 | with: 34 | files: chisel-example.scala 35 | -------------------------------------------------------------------------------- /.github/workflows/setup-oss-cad-suite/action.yml: -------------------------------------------------------------------------------- 1 | name: Setup OSS CAD Suite 2 | 3 | inputs: 4 | version: 5 | description: 'version to install' 6 | required: false 7 | default: '2023-06-21' 8 | 9 | runs: 10 | using: composite 11 | steps: 12 | - id: cache-oss-cad-suite 13 | uses: actions/cache@v4 14 | with: 15 | path: oss-cad-suite 16 | key: oss-cad-suite-${{ runner.os }}-${{ inputs.version }} 17 | 18 | - shell: bash 19 | if: steps.cache-oss-cad-suite.outputs.cache-hit != 'true' 20 | run: | 21 | VERSION=${{ inputs.version }} 22 | ARTIFACT=oss-cad-suite-linux-x64-$(echo $VERSION | tr -d '-') 23 | wget -q -O - https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${VERSION}/${ARTIFACT}.tgz | tar -zx 24 | 25 | # Add the CAD Suite to the PATH 26 | - shell: bash 27 | run: echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH 28 | 29 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | out/ 2 | generated/ 3 | /lib/firrtl.jar 4 | .classpath 5 | .idea 6 | .idea_modules/ 7 | .direnv/ 8 | .envrc 9 | .project 10 | target/ 11 | *.iml 12 | *.swp 13 | *.fir 14 | *.v 15 | test_run_dir 16 | build/ 17 | *~ 18 | \#*\# 19 | .\#* 20 | .vscode 21 | .metals 22 | .bloop 23 | .scala-build 24 | metals.sbt 25 | version.txt 26 | latest-version.txt 27 | .bsp 28 | -------------------------------------------------------------------------------- /.mill-jvm-opts: -------------------------------------------------------------------------------- 1 | -Dchisel.project.root=${PWD} 2 | -------------------------------------------------------------------------------- /.mill-version: -------------------------------------------------------------------------------- 1 | 0.12.7 2 | -------------------------------------------------------------------------------- /.scala-steward.conf: -------------------------------------------------------------------------------- 1 | pullRequests.frequency = "14 days" 2 | 3 | # upickle 4+ only supports Scala 3.4+ so we cannot use it until we bump past Scala 3.3. 4 | updates.ignore = [ { groupId = "com.lihaoyi", artifactId = "upickle" } ] 5 | -------------------------------------------------------------------------------- /.scalafix.conf: -------------------------------------------------------------------------------- 1 | rules = [ 2 | # DisableSyntax 3 | # ExplicitResultTypes 4 | #LeakingImplicitClassVal 5 | RemoveUnused 6 | #NoAutoTupling 7 | #NoValInForComprehension 8 | #ProcedureSyntax 9 | ] 10 | 11 | -------------------------------------------------------------------------------- /.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 3.8.5 2 | 3 | runner.dialect = scala213source3 4 | fileOverride { 5 | "glob:**/scala-3/**" { 6 | runner.dialect = scala3 7 | } 8 | } 9 | maxColumn = 120 10 | align = most 11 | continuationIndent.defnSite = 2 12 | assumeStandardLibraryStripMargin = true 13 | # TODO eventually enable, but audit handling of @define and @example {{{ (curly brace on same line) 14 | docstrings.style = keep 15 | lineEndings = preserve 16 | includeCurlyBraceInSelectChains = false 17 | danglingParentheses.preset = true 18 | 19 | align.tokens."+" = [ 20 | { 21 | code = ":" 22 | } 23 | ] 24 | 25 | newlines.beforeCurlyLambdaParams = never 26 | newlines.forceBeforeMultilineAssign = never 27 | newlines.implicitParamListModifierPrefer = before 28 | newlines.sometimesBeforeColonInMethodReturnType = true 29 | 30 | optIn.annotationNewlines = true 31 | 32 | rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix] 33 | -------------------------------------------------------------------------------- /benchmark/package.mill: -------------------------------------------------------------------------------- 1 | package build.benchmark 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import $ivy.`com.lihaoyi::mill-contrib-jmh:` 7 | import mill.contrib.jmh.JmhModule 8 | 9 | import build._ 10 | 11 | object `package` extends RootModule with ScalaModule with JmhModule with ScalafmtModule { 12 | def scalaVersion = v.scalaVersion 13 | def jmhCoreVersion = v.jmhVersion 14 | 15 | override def moduleDeps = Seq(chisel(v.scalaVersion)) 16 | } 17 | -------------------------------------------------------------------------------- /benchmark/src/main/scala/chisel3/benchmark/Benchmark.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.benchmark 4 | 5 | import java.util.concurrent.TimeUnit 6 | import org.openjdk.jmh.annotations._ 7 | import org.openjdk.jmh.infra.Blackhole 8 | 9 | import chisel3._ 10 | import chisel3.util.BitPat 11 | 12 | // Run with: 13 | // ./mill benchmark.runJmh 14 | class ChiselBenchmark { 15 | 16 | // This is just an example, copy-paste and modify as appropriate 17 | // Typically 10 iterations for both warmup and measurement is better 18 | @Benchmark 19 | @OutputTimeUnit(TimeUnit.MICROSECONDS) 20 | @Warmup(iterations = 3) 21 | @Measurement(iterations = 3) 22 | @Fork(value = 1) 23 | @Threads(value = 1) 24 | def BitPatFromUInt(blackHole: Blackhole): BitPat = { 25 | val x = BitPat(0xdeadbeefL.U) 26 | // Blackhole consuming the value prevents certain JVM optimizations 27 | blackHole.consume(x) 28 | // Returning the value is usually a good idea as well 29 | x 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /circtpanamabinding/includeStructs.txt: -------------------------------------------------------------------------------- 1 | MlirContext 2 | MlirDialectHandle 3 | MlirStringRef 4 | MlirType 5 | MlirValue 6 | MlirLocation 7 | MlirAttribute 8 | MlirIdentifier 9 | MlirModule 10 | MlirBlock 11 | MlirRegion 12 | MlirOperation 13 | MlirOperationState 14 | MlirNamedAttribute 15 | MlirPassManager 16 | MlirOpPassManager 17 | MlirPass 18 | MlirLogicalResult 19 | FIRRTLBundleField 20 | FIRRTLClassElement 21 | CirctFirtoolFirtoolOptions 22 | OMEvaluator 23 | OMEvaluatorValue 24 | HWInstanceGraph 25 | HWInstanceGraphNode 26 | -------------------------------------------------------------------------------- /circtpanamabinding/includeTypedefs.txt: -------------------------------------------------------------------------------- 1 | MlirStringCallback 2 | HWInstanceGraphNodeCallback 3 | -------------------------------------------------------------------------------- /circtpanamabinding/includeUnions.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/circtpanamabinding/includeUnions.txt -------------------------------------------------------------------------------- /circtpanamabinding/includeVars.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/circtpanamabinding/includeVars.txt -------------------------------------------------------------------------------- /circtpanamabinding/jextract-headers.h: -------------------------------------------------------------------------------- 1 | #ifndef JEXTRACT_HEADERS_H 2 | #define JEXTRACT_HEADERS_H 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | #endif // JEXTRACT_HEADERS_H 18 | -------------------------------------------------------------------------------- /circtpanamabinding/linkLibraries.txt: -------------------------------------------------------------------------------- 1 | MLIRCAPIIR 2 | CIRCTCAPIFIRRTL 3 | CIRCTCAPICHIRRTL 4 | CIRCTCAPIHW 5 | CIRCTCAPISV 6 | CIRCTCAPISeq 7 | CIRCTCAPIEmit 8 | CIRCTCAPIOM 9 | CIRCTCAPIFirtool 10 | CIRCTCAPIExportFIRRTL 11 | CIRCTCAPIExportVerilog 12 | CIRCTFIRRTL 13 | CIRCTHW 14 | CIRCTExportFIRRTL 15 | CIRCTExportVerilog 16 | MLIRCAPIRegisterEverything 17 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/ClockIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import scala.language.experimental.macros 6 | import chisel3.experimental.SourceInfo 7 | import chisel3.internal.sourceinfo.SourceInfoTransform 8 | 9 | private[chisel3] trait ClockIntf { self: Clock => 10 | 11 | /** Returns the contents of the clock wire as a [[Bool]]. */ 12 | final def asBool: Bool = macro SourceInfoTransform.noArg 13 | 14 | def do_asBool(implicit sourceInfo: SourceInfo): Bool = _asBoolImpl 15 | } 16 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/DisableIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.internal._ 6 | import chisel3.experimental.{OpaqueType, SourceInfo} 7 | import chisel3.internal.sourceinfo.SourceInfoTransform 8 | 9 | import scala.language.experimental.macros 10 | import scala.collection.immutable.ListMap 11 | 12 | private[chisel3] trait DisableIntf { self: Disable => 13 | 14 | /** Logical not 15 | * 16 | * @return invert the logical value of this `Disable` 17 | * @group Bitwise 18 | */ 19 | final def unary_! : Disable = macro SourceInfoTransform.noArg 20 | 21 | /** @group SourceInfoTransformMacro */ 22 | def do_unary_!(implicit sourceInfo: SourceInfo): Disable = _impl_unary_! 23 | } 24 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/ModuleIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import scala.language.experimental.macros 6 | 7 | import chisel3.experimental.{BaseModule, SourceInfo} 8 | import chisel3.internal.sourceinfo.InstTransform 9 | 10 | private[chisel3] trait Module$Intf extends SourceInfoDoc { self: Module.type => 11 | 12 | /** A wrapper method that all Module instantiations must be wrapped in 13 | * (necessary to help Chisel track internal state). 14 | * 15 | * @param bc the Module being created 16 | * 17 | * @return the input module `m` with Chisel metadata properly set 18 | */ 19 | def apply[T <: BaseModule](bc: => T): T = macro InstTransform.apply[T] 20 | 21 | /** @group SourceInfoTransformMacro */ 22 | def do_apply[T <: BaseModule](bc: => T)(implicit sourceInfo: SourceInfo): T = _applyImpl(bc) 23 | } 24 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/MuxIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import scala.language.experimental.macros 6 | 7 | import chisel3.experimental.SourceInfo 8 | import chisel3.internal.sourceinfo.MuxTransform 9 | 10 | private[chisel3] trait Mux$Intf extends SourceInfoDoc { self: Mux.type => 11 | 12 | /** Creates a mux, whose output is one of the inputs depending on the 13 | * value of the condition. 14 | * 15 | * @param cond condition determining the input to choose 16 | * @param con the value chosen when `cond` is true 17 | * @param alt the value chosen when `cond` is false 18 | * @example 19 | * {{{ 20 | * val muxOut = Mux(data_in === 3.U, 3.U(4.W), 0.U(4.W)) 21 | * }}} 22 | */ 23 | def apply[T <: Data](cond: Bool, con: T, alt: T): T = macro MuxTransform.apply[T] 24 | 25 | /** @group SourceInfoTransformMacro */ 26 | def do_apply[T <: Data]( 27 | cond: Bool, 28 | con: T, 29 | alt: T 30 | )( 31 | implicit sourceInfo: SourceInfo 32 | ): T = _applyImpl(cond, con, alt) 33 | } 34 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/experimental/SourceInfoIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | // This file contains macros for adding source locators at the point of invocation. 4 | // 5 | // This is not part of coreMacros to disallow this macro from being implicitly invoked in Chisel 6 | // frontend (and generating source locators in Chisel core), which is almost certainly a bug. 7 | // 8 | // Note: While these functions and definitions are not private (macros can't be 9 | // private), these are NOT meant to be part of the public API (yet) and no 10 | // forward compatibility guarantees are made. 11 | // A future revision may stabilize the source locator API to allow library 12 | // writers to append source locator information at the point of a library 13 | // function invocation. 14 | 15 | package chisel3.experimental 16 | 17 | import scala.language.experimental.macros 18 | import scala.reflect.macros.blackbox.Context 19 | import chisel3.internal.sourceinfo.SourceInfoMacro 20 | 21 | private[chisel3] trait SourceInfo$Intf { self: SourceInfo.type => 22 | implicit def materialize: SourceInfo = macro SourceInfoMacro.generate_source_info 23 | } 24 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/internal/SourceInfoFileResolver.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.internal.sourceinfo 4 | 5 | import scala.language.experimental.macros 6 | import scala.reflect.macros.blackbox.Context 7 | 8 | /////////////////////////////////////////////////////// 9 | // WARNING!! // 10 | // This file is soft-linked into the compiler plugin // 11 | // so that the logic stays consistent // 12 | /////////////////////////////////////////////////////// 13 | 14 | /** Scala compile-time function for determine the String used to represent a source file path in SourceInfos */ 15 | private[internal] object SourceInfoFileResolver { 16 | def resolve(source: scala.reflect.internal.util.SourceFile): String = { 17 | val userDir = sys.props.get("user.dir") // Figure out what to do if not provided 18 | val projectRoot = sys.props.get("chisel.project.root") 19 | val root = projectRoot.orElse(userDir) 20 | 21 | val path = root.map(r => source.file.canonicalPath.stripPrefix(r)).getOrElse(source.file.name) 22 | val pathNoStartingSlash = if (path(0) == '/') path.tail else path 23 | pathNoStartingSlash 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/internal/SourceInfoMacro.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.internal.sourceinfo 4 | 5 | import scala.language.experimental.macros 6 | import scala.reflect.macros.blackbox.Context 7 | 8 | import chisel3.internal.sourceinfo.SourceInfoFileResolver 9 | 10 | /** Provides a macro that returns the source information at the invocation point. 11 | */ 12 | @deprecated("Public APIs in chisel3.internal are deprecated", "Chisel 3.6") 13 | private[chisel3] object SourceInfoMacro { 14 | def generate_source_info(c: Context): c.Tree = { 15 | import c.universe._ 16 | val p = c.enclosingPosition 17 | val path = SourceInfoFileResolver.resolve(p.source) 18 | 19 | q"_root_.chisel3.experimental.SourceLine($path, ${p.line}, ${p.column})" 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/probe/PackageIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.probe 4 | 5 | import chisel3._ 6 | import chisel3.experimental.SourceInfo 7 | 8 | import scala.language.experimental.macros 9 | 10 | private[chisel3] trait Probe$Intf extends SourceInfoDoc { 11 | 12 | /** Access the value of a probe. 13 | * 14 | * @param source probe whose value is getting accessed 15 | */ 16 | def read[T <: Data](source: T): T = macro chisel3.internal.sourceinfo.ProbeTransform.sourceRead[T] 17 | 18 | /** @group SourceInfoTransformMacro */ 19 | def do_read[T <: Data](source: T)(implicit sourceInfo: SourceInfo): T = probe._readImpl(source) 20 | } 21 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/probe/ProbeValue.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.probe 4 | 5 | import chisel3.{Data, SourceInfoDoc} 6 | import chisel3.experimental.SourceInfo 7 | 8 | import scala.language.experimental.macros 9 | 10 | object ProbeValue extends ProbeValueBase with SourceInfoDoc { 11 | 12 | /** Create a read-only probe expression. */ 13 | def apply[T <: Data](source: T): T = macro chisel3.internal.sourceinfo.ProbeTransform.sourceApply[T] 14 | 15 | /** @group SourceInfoTransformMacro */ 16 | def do_apply[T <: Data](source: T)(implicit sourceInfo: SourceInfo): T = super.apply(source, writable = false) 17 | } 18 | 19 | object RWProbeValue extends ProbeValueBase with SourceInfoDoc { 20 | 21 | /** Create a read/write probe expression. */ 22 | def apply[T <: Data](source: T): T = macro chisel3.internal.sourceinfo.ProbeTransform.sourceApply[T] 23 | 24 | /** @group SourceInfoTransformMacro */ 25 | def do_apply[T <: Data](source: T)(implicit sourceInfo: SourceInfo): T = super.apply(source, writable = true) 26 | } 27 | -------------------------------------------------------------------------------- /core/src/main/scala-2/chisel3/properties/ObjectIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.properties 4 | 5 | import scala.language.experimental.macros 6 | 7 | import chisel3.experimental.SourceInfo 8 | import chisel3.internal.sourceinfo.InstTransform 9 | 10 | private[chisel3] trait DynamicObject$Intf { self: DynamicObject.type => 11 | 12 | /** A wrapper method to wrap Class instantiations and return a DynamicObject. 13 | * 14 | * This is necessary to help Chisel track internal state. This can be used instead of `Definition.apply` if a 15 | * DynamicObject is required. If possible, it is safer to user `Definition.apply` and StaticObject. 16 | * 17 | * @param bc the Class being created 18 | * 19 | * @return a DynamicObject representing an instance of the Class 20 | */ 21 | def apply[T <: Class](bc: => T): DynamicObject = macro InstTransform.apply[T] 22 | 23 | /** @group SourceInfoTransformMacro */ 24 | def do_apply[T <: Class](bc: => T)(implicit sourceInfo: SourceInfo): DynamicObject = _applyImpl(bc) 25 | } 26 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/ChiselEnumIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.SourceInfo 6 | 7 | private[chisel3] trait EnumTypeIntf { self: EnumType => 8 | 9 | final def ===(that: EnumType)(using SourceInfo): Bool = _impl_===(that) 10 | final def =/=(that: EnumType)(using SourceInfo): Bool = _impl_=/=(that) 11 | final def <(that: EnumType)(using SourceInfo): Bool = _impl_<(that) 12 | final def <=(that: EnumType)(using SourceInfo): Bool = _impl_>(that) 13 | final def >(that: EnumType)(using SourceInfo): Bool = _impl_<=(that) 14 | final def >=(that: EnumType)(using SourceInfo): Bool = _impl_>=(that) 15 | } 16 | 17 | private[chisel3] trait ChiselEnumIntf { self: ChiselEnum => 18 | // TODO macros 19 | } 20 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/ClockIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.SourceInfo 6 | 7 | private[chisel3] trait ClockIntf { self: Clock => 8 | 9 | /** Returns the contents of the clock wire as a [[Bool]]. */ 10 | def asBool(using SourceInfo): Bool = _asBoolImpl 11 | } 12 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/DataIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.SourceInfo 6 | 7 | private[chisel3] trait DataIntf { self: Data => 8 | 9 | /** Does a reinterpret cast of the bits in this node into the format that provides. 10 | * Returns a new Wire of that type. Does not modify existing nodes. 11 | * 12 | * x.asTypeOf(that) performs the inverse operation of x := that.toBits. 13 | * 14 | * @note bit widths are NOT checked, may pad or drop bits from input 15 | * @note that should have known widths 16 | */ 17 | def asTypeOf[T <: Data](that: T)(using SourceInfo): T = _asTypeOfImpl(that) 18 | 19 | /** Reinterpret cast to UInt. 20 | * 21 | * @note value not guaranteed to be preserved: for example, a SInt of width 22 | * 3 and value -1 (0b111) would become an UInt with value 7 23 | * @note Aggregates are recursively packed with the first element appearing 24 | * in the least-significant bits of the result. 25 | */ 26 | def asUInt: UInt = _asUIntImpl 27 | } 28 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/DisableIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.internal._ 6 | import chisel3.experimental.SourceInfo 7 | 8 | private[chisel3] trait DisableIntf { self: Disable => 9 | 10 | /** Logical not 11 | * 12 | * @return invert the logical value of this `Disable` 13 | * @group Bitwise 14 | */ 15 | def unary_!(using SourceInfo): Disable = _impl_unary_! 16 | } 17 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/ModuleIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.{BaseModule, SourceInfo} 6 | 7 | private[chisel3] trait Module$Intf extends SourceInfoDoc { self: Module.type => 8 | 9 | /** A wrapper method that all Module instantiations must be wrapped in 10 | * (necessary to help Chisel track internal state). 11 | * 12 | * @param bc the Module being created 13 | * 14 | * @return the input module `m` with Chisel metadata properly set 15 | */ 16 | // TODO(adkian-sifive) the callsite here explicitly passes 17 | // sourceInfo so it cannot be a contextual parameter 18 | def apply[T <: BaseModule](bc: => T): T = _applyImpl(bc) 19 | } 20 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/MuxIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.SourceInfo 6 | 7 | private[chisel3] trait Mux$Intf extends SourceInfoDoc { self: Mux.type => 8 | 9 | /** Creates a mux, whose output is one of the inputs depending on the 10 | * value of the condition. 11 | * 12 | * @param cond condition determining the input to choose 13 | * @param con the value chosen when `cond` is true 14 | * @param alt the value chosen when `cond` is false 15 | * @example 16 | * {{{ 17 | * val muxOut = Mux(data_in === 3.U, 3.U(4.W), 0.U(4.W)) 18 | * }}} 19 | */ 20 | def apply[T <: Data]( 21 | cond: Bool, 22 | con: T, 23 | alt: T 24 | )( 25 | using SourceInfo 26 | ): T = _applyImpl(cond, con, alt) 27 | } 28 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/PrintfIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import scala.language.experimental.macros 6 | 7 | private[chisel3] trait PrintfIntf { self: printf.type => 8 | // TODO add printf with format String macro 9 | } 10 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/SimLogIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | private[chisel3] trait SimLogIntf { self: SimLog => 6 | // TODO implement macro for Scala 3 7 | } 8 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/SourceInfoDoc.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | /** Does nothing */ 6 | trait SourceInfoDoc 7 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/VerificationStatementIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | private[chisel3] trait Assert$Intf { self: assert.type => 6 | // TODO implement 7 | } 8 | 9 | private[chisel3] trait Assume$Intf { self: assume.type => 10 | // TODO implement 11 | } 12 | 13 | private[chisel3] trait Cover$Impl { self: cover.type => 14 | // TODO implement 15 | } 16 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/VerificationStatementMacros.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.SourceInfo 6 | import chisel3.internal._ 7 | 8 | import scala.annotation.nowarn 9 | 10 | object VerifStmtMacrosCompat { 11 | 12 | type SourceLineInfo = (String, Int) 13 | 14 | def formatFailureMessage( 15 | kind: String, 16 | lineInfo: SourceLineInfo, 17 | cond: Bool, 18 | message: Option[Printable] 19 | )( 20 | using SourceInfo 21 | ): Printable = { 22 | val (filename, line) = lineInfo 23 | val lineMsg = s"$filename:$line".replaceAll("%", "%%") 24 | message match { 25 | case Some(msg) => 26 | p"$kind failed: $msg\n" 27 | case None => p"$kind failed at $lineMsg\n" 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/experimental/SourceInfoIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | // This file contains macros for adding source locators at the point of invocation. 4 | // 5 | // This is not part of coreMacros to disallow this macro from being implicitly invoked in Chisel 6 | // frontend (and generating source locators in Chisel core), which is almost certainly a bug. 7 | // 8 | // Note: While these functions and definitions are not private (macros can't be 9 | // private), these are NOT meant to be part of the public API (yet) and no 10 | // forward compatibility guarantees are made. 11 | // A future revision may stabilize the source locator API to allow library 12 | // writers to append source locator information at the point of a library 13 | // function invocation. 14 | 15 | package chisel3.experimental 16 | 17 | private[chisel3] trait SourceInfo$Intf { self: SourceInfo.type => 18 | implicit def materialize: SourceInfo = UnlocatableSourceInfo 19 | } 20 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/experimental/dataview/ChiselSubtypeOf.scala: -------------------------------------------------------------------------------- 1 | package chisel3.experimental 2 | 3 | import chisel3._ 4 | 5 | sealed trait ChiselSubtypeOf[A, B] 6 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/experimental/dataview/InvertibleDataView.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.dataview 4 | 5 | import chisel3._ 6 | 7 | private[chisel3] trait InvertibleDataView 8 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/experimental/hierarchy/HierarchyMarker.scala: -------------------------------------------------------------------------------- 1 | package chisel3.experimental 2 | 3 | trait Markers 4 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/experimental/hierarchy/InstantiateIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.hierarchy 4 | 5 | private[chisel3] trait InstantiateIntf { self: Instantiate.type => 6 | // TODO implement 7 | } 8 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/probe/PackageIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.probe 4 | 5 | import chisel3._ 6 | import chisel3.experimental.SourceInfo 7 | 8 | // Empty olyfill for trait needed by Scala 2 9 | private[chisel3] trait Probe$Intf 10 | 11 | /** Access the value of a probe. 12 | * 13 | * @param source probe whose value is getting accessed 14 | */ 15 | def read[T <: Data](source: T)(using SourceInfo): T = _readImpl(source) 16 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/probe/Probe.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.probe 4 | 5 | import chisel3._ 6 | import chisel3.experimental.SourceInfo 7 | 8 | object Probe extends ProbeBase { 9 | 10 | /** Mark a Chisel type with a probe modifier. 11 | */ 12 | def apply[T <: Data](source: => T)(using SourceInfo): T = 13 | super.apply(source, false, None) 14 | 15 | /** Mark a Chisel type with a probe modifier and layer color. 16 | */ 17 | def apply[T <: Data](source: => T, color: layer.Layer)(using SourceInfo): T = 18 | super.apply(source, false, Some(color)) 19 | } 20 | 21 | object RWProbe extends ProbeBase with SourceInfoDoc { 22 | 23 | /** Mark a Chisel type with a writable probe modifier. 24 | */ 25 | def apply[T <: Data](source: => T)(using SourceInfo): T = 26 | super.apply(source, true, None) 27 | 28 | /** Mark a Chisel type with a wirtable probe modifier and layer color. 29 | */ 30 | def apply[T <: Data](source: => T, color: layer.Layer)(using SourceInfo): T = 31 | super.apply(source, true, Some(color)) 32 | } 33 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/probe/ProbeValue.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.probe 4 | 5 | import chisel3.{Data, SourceInfoDoc} 6 | import chisel3.experimental.SourceInfo 7 | 8 | object ProbeValue extends ProbeValueBase with SourceInfoDoc { 9 | 10 | /** Create a read-only probe expression. */ 11 | def apply[T <: Data](source: T)(using SourceInfo): T = super.apply(source, writable = false) 12 | } 13 | 14 | object RWProbeValue extends ProbeValueBase with SourceInfoDoc { 15 | 16 | /** Create a read/write probe expression. */ 17 | def apply[T <: Data](source: T)(using SourceInfo): T = super.apply(source, writable = true) 18 | } 19 | -------------------------------------------------------------------------------- /core/src/main/scala-3/chisel3/properties/ObjectIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.properties 4 | 5 | private[chisel3] trait DynamicObject$Intf { self: DynamicObject.type => 6 | // TODO implement 7 | } 8 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/BoolFactory.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.internal.firrtl.ir.ULit 6 | 7 | trait BoolFactory { 8 | 9 | /** Creates an empty Bool. 10 | */ 11 | def apply(): Bool = new Bool() 12 | 13 | /** Creates Bool literal. 14 | */ 15 | protected[chisel3] def Lit(x: Boolean): Bool = { 16 | val result = new Bool() 17 | val lit = ULit(if (x) 1 else 0, Width(1)) 18 | // Ensure we have something capable of generating a name. 19 | lit.bindLitArg(result) 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/Const.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3._ 6 | import chisel3.internal.{requireNoProbeTypeModifier, Builder} 7 | import chisel3.experimental.{requireIsChiselType, SourceInfo} 8 | 9 | /** Create a constant type in FIRRTL, which is guaranteed to take a single 10 | * constant value. 11 | */ 12 | object Const { 13 | def apply[T <: Data](source: => T)(implicit sourceInfo: SourceInfo): T = { 14 | val prevId = Builder.idGen.value 15 | val data = source // should only evaluate source once 16 | requireIsChiselType(data) 17 | requireNoProbeTypeModifier(data, "Cannot create Const of a Probe.") 18 | val ret = if (!data.mustClone(prevId)) data else data.cloneType.asInstanceOf[T] 19 | ret.isConst = true 20 | ret 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/FormalTest.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.experimental.{BaseModule, Param} 6 | import chisel3.internal.Builder 7 | import chisel3.internal.firrtl.ir._ 8 | import chisel3.internal.throwException 9 | import chisel3.experimental.{SourceInfo, UnlocatableSourceInfo} 10 | 11 | object FormalTest { 12 | def apply( 13 | module: BaseModule, 14 | params: MapTestParam = MapTestParam(Map.empty), 15 | name: String = "" 16 | )(implicit sourceInfo: SourceInfo): Unit = { 17 | val proposedName = if (name != "") { 18 | name 19 | } else { 20 | module._proposedName 21 | } 22 | val sanitizedName = Builder.globalNamespace.name(proposedName) 23 | Builder.components += DefFormalTest(sanitizedName, module, params, sourceInfo) 24 | } 25 | } 26 | 27 | /** Parameters for test declarations. */ 28 | sealed abstract class TestParam 29 | case class IntTestParam(value: BigInt) extends TestParam 30 | case class DoubleTestParam(value: Double) extends TestParam 31 | case class StringTestParam(value: String) extends TestParam 32 | case class ArrayTestParam(value: Seq[TestParam]) extends TestParam 33 | case class MapTestParam(value: Map[String, TestParam]) extends TestParam 34 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/Mux.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.internal._ 6 | import chisel3.internal.Builder.pushOp 7 | import chisel3.experimental.{requireIsHardware, SourceInfo} 8 | import chisel3.internal.firrtl.ir._ 9 | import chisel3.internal.firrtl.ir.PrimOp._ 10 | 11 | object Mux extends Mux$Intf { 12 | 13 | protected def _applyImpl[T <: Data]( 14 | cond: Bool, 15 | con: T, 16 | alt: T 17 | )( 18 | implicit sourceInfo: SourceInfo 19 | ): T = { 20 | requireIsHardware(cond, "mux condition") 21 | requireIsHardware(con, "mux true value") 22 | requireIsHardware(alt, "mux false value") 23 | val d = cloneSupertype(Seq(con, alt), "Mux") 24 | val conRef = con match { // this matches chisel semantics (DontCare as object) to firrtl semantics (invalidate) 25 | case DontCare => 26 | val dcWire = Wire(d) 27 | dcWire := DontCare 28 | dcWire.ref 29 | case _ => con.ref 30 | } 31 | val altRef = alt match { 32 | case DontCare => 33 | val dcWire = Wire(d) 34 | dcWire := DontCare 35 | dcWire.ref 36 | case _ => alt.ref 37 | } 38 | pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, conRef, altRef)) 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/Public.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | /** A trait that can be mixed into a Chisel module to indicate that a module has external users. 6 | * 7 | * This will result in a public FIRRTL module being produced. 8 | */ 9 | trait Public { this: RawModule => 10 | 11 | override private[chisel3] def _isPublic = isPublic 12 | 13 | /** Is this module public? 14 | * 15 | * Users can override this if they need more control over when outputs of this Module should 16 | * be considered public 17 | */ 18 | def isPublic: Boolean = true 19 | } 20 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/SIntFactory.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.internal.firrtl.ir.SLit 6 | 7 | trait SIntFactory { 8 | 9 | /** Create an SInt type with inferred width. */ 10 | def apply(): SInt = apply(Width()) 11 | 12 | /** Create a SInt type or port with fixed width. */ 13 | def apply(width: Width): SInt = new SInt(width) 14 | 15 | /** Create an SInt literal with specified width. */ 16 | protected[chisel3] def Lit(value: BigInt, width: Width): SInt = { 17 | val lit = SLit(value, width) 18 | val result = new SInt(lit.width) 19 | lit.bindLitArg(result) 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/SramTarget.scala: -------------------------------------------------------------------------------- 1 | package chisel3 2 | 3 | import chisel3.internal.NamedComponent 4 | 5 | /** Provides an underlying target-able class for SRAM. 6 | */ 7 | private[chisel3] final class SramTarget extends NamedComponent { 8 | _parent.foreach(_.addId(this)) 9 | } 10 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/UIntFactory.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.internal.firrtl.ir.ULit 6 | import firrtl.Utils 7 | 8 | // This is currently a factory because both Bits and UInt inherit it. 9 | trait UIntFactory { 10 | 11 | /** Create a UInt type with inferred width. */ 12 | def apply(): UInt = apply(Width()) 13 | 14 | /** Create a UInt port with specified width. */ 15 | def apply(width: Width): UInt = new UInt(width) 16 | 17 | /** Create a UInt literal with specified width. */ 18 | protected[chisel3] def Lit(value: BigInt, width: Width): UInt = { 19 | val lit = ULit(value, width) 20 | val result = new UInt(lit.width) 21 | // Bind result to being an Literal 22 | lit.bindLitArg(result) 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/VerificationIntrinsics.scala: -------------------------------------------------------------------------------- 1 | package chisel3.util.circt 2 | 3 | import chisel3._ 4 | import chisel3.internal._ 5 | import chisel3.experimental.{fromStringToStringParam, BaseModule, SourceInfo} 6 | 7 | /** Create an `ifelsefatal` style assertion. 8 | */ 9 | private[chisel3] object IfElseFatalIntrinsic { 10 | def apply( 11 | id: BaseModule, 12 | format: Printable, 13 | label: String, 14 | clock: Clock, 15 | predicate: Bool, 16 | enable: Bool, 17 | data: Data* 18 | )( 19 | implicit sourceInfo: SourceInfo 20 | ): Unit = { 21 | Intrinsic( 22 | "circt_chisel_ifelsefatal", 23 | "format" -> chisel3.experimental.PrintableParam(format, id), 24 | "label" -> label 25 | )((Seq(clock, predicate, enable) ++ data): _*) 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/hierarchy/InstantiableClone.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.hierarchy 4 | 5 | import chisel3.experimental.BaseModule 6 | 7 | /** @note If we are cloning a non-module, we need another object which has the proper _parent set! 8 | */ 9 | trait InstantiableClone[T <: IsInstantiable] extends core.IsClone[T] { 10 | private[chisel3] def _innerContext: Hierarchy[_] 11 | private[chisel3] def getInnerContext: Option[BaseModule] = _innerContext.getInnerDataContext 12 | } 13 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/hierarchy/core/IsClone.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.hierarchy.core 4 | 5 | /** Represents a clone of an underlying object. This is used to support CloneModuleAsRecord and Instance/Definition. 6 | * 7 | * @note We don't actually "clone" anything in the traditional sense but is a placeholder so we lazily clone internal state 8 | */ 9 | trait IsClone[+T] { 10 | // Underlying object of which this is a clone of 11 | private[chisel3] def getProto: T 12 | 13 | /** Determines whether another object is a clone of the same underlying proto 14 | * 15 | * @param a 16 | */ 17 | def hasSameProto(a: Any): Boolean = { 18 | val aProto = a match { 19 | case x: IsClone[_] => x.getProto 20 | case o => o 21 | } 22 | this == aProto || getProto == aProto 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/hierarchy/core/IsInstantiable.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.hierarchy.core 4 | 5 | /** While this is public, it is not recommended for users to extend directly. 6 | * Instead, use the [[instantiable]] annotation on your trait or class. 7 | * 8 | * This trait indicates whether a class can be returned from an Instance. 9 | */ 10 | trait IsInstantiable 11 | 12 | object IsInstantiable { 13 | implicit class IsInstantiableExtensions[T <: IsInstantiable](i: T) { 14 | @deprecated( 15 | "Use of @instantiable on user-defined types is deprecated. Implement Lookupable for your type instead.", 16 | "Chisel 7.0.0" 17 | ) 18 | def toInstance: Instance[T] = new Instance(Proto(i)) 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/hierarchy/core/IsLookupable.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.hierarchy.core 4 | 5 | /** A User-extendable trait to mark metadata-containers, e.g. parameter case classes, as valid to return unchanged 6 | * from an instance. 7 | * 8 | * This should only be true of the metadata returned is identical for ALL instances! 9 | * 10 | * @example For instances of the same proto, metadata or other construction parameters 11 | * may be useful to access outside of the instance construction. For parameters that are 12 | * the same for all instances, we should mark it as IsLookupable 13 | * {{{ 14 | * case class Params(debugMessage: String) extends IsLookupable 15 | * class MyModule(p: Params) extends Module { 16 | * printf(p.debugMessage) 17 | * } 18 | * val myParams = Params("Hello World") 19 | * val definition = Definition(new MyModule(myParams)) 20 | * val i0 = Instance(definition) 21 | * val i1 = Instance(definition) 22 | * require(i0.p == i1.p) // p is only accessable because it extends IsLookupable 23 | * }}} 24 | */ 25 | trait IsLookupable 26 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/hierarchy/core/Underlying.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.experimental.hierarchy.core 4 | 5 | /** Represents the underlying implementation of a Definition or Instance */ 6 | sealed trait Underlying[+T] 7 | 8 | /** A clone of a real implementation */ 9 | final case class Clone[+T](isClone: IsClone[T]) extends Underlying[T] 10 | 11 | /** An actual implementation */ 12 | final case class Proto[+T](proto: T) extends Underlying[T] 13 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/experimental/hierarchy/package.scala: -------------------------------------------------------------------------------- 1 | package chisel3.experimental 2 | 3 | package object hierarchy { 4 | type Instance[P] = core.Instance[P] 5 | val Instance = core.Instance 6 | type Definition[P] = core.Definition[P] 7 | val Definition = core.Definition 8 | type Hierarchy[P] = core.Hierarchy[P] 9 | val Hierarchy = core.Hierarchy 10 | type IsInstantiable = core.IsInstantiable 11 | type IsLookupable = core.IsLookupable 12 | type Lookupable[P] = core.Lookupable[P] 13 | val Lookupable = core.Lookupable 14 | } 15 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/internal/CIRCTOM.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.internal 4 | 5 | @deprecated("There no CIRCTOM anymore, use circtpanamaom directly", "Chisel 6.0") 6 | abstract class CIRCTOM { 7 | def evaluator(): CIRCTOMEvaluator 8 | 9 | def newBasePathEmpty(): CIRCTOMEvaluatorValue 10 | } 11 | 12 | @deprecated("There no CIRCTOMEvaluator anymore, use circtpanamaom directly", "Chisel 6.0") 13 | abstract class CIRCTOMEvaluator { 14 | def instantiate(name: String, actualParams: Seq[CIRCTOMEvaluatorValue]): CIRCTOMObject 15 | } 16 | 17 | @deprecated("There no CIRCTOMEvaluatorValue anymore, use circtpanamaom directly", "Chisel 6.0") 18 | abstract class CIRCTOMEvaluatorValue {} 19 | 20 | @deprecated("There no CIRCTOMObject anymore, use circtpanamaom directly", "Chisel 6.0") 21 | abstract class CIRCTOMObject { 22 | def field(name: String): CIRCTOMEvaluatorValue 23 | } 24 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/internal/CIRCTPassManager.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.internal 4 | 5 | @deprecated("There no CIRCTPassManager anymore, use circtpanamaconverter directly", "Chisel 6.0") 6 | abstract class CIRCTPassManager { 7 | def populatePreprocessTransforms(): Boolean 8 | def populateCHIRRTLToLowFIRRTL(): Boolean 9 | def populateLowFIRRTLToHW(): Boolean 10 | def populateLowHWToSV(): Boolean 11 | def populateExportVerilog(callback: String => Unit): Boolean 12 | def populateExportSplitVerilog(directory: String): Boolean 13 | def populateFinalizeIR(): Boolean 14 | 15 | def run(): Boolean; 16 | } 17 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/internal/firrtl/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.internal 4 | 5 | package object firrtl { 6 | @deprecated("This type has moved to package chisel3", "Chisel 6.0") 7 | type Width = chisel3.Width 8 | @deprecated("This type has moved to package chisel3", "Chisel 6.0") 9 | val Width = chisel3.Width 10 | 11 | @deprecated("This type has moved to package chisel3", "Chisel 6.0") 12 | type UnknownWidth = chisel3.UnknownWidth.type 13 | @deprecated("This type has moved to package chisel3", "Chisel 6.0") 14 | val UnknownWidth = chisel3.UnknownWidth 15 | 16 | @deprecated("This type has moved to package chisel3", "Chisel 6.0") 17 | type KnownWidth = chisel3.KnownWidth 18 | @deprecated("This type has moved to package chisel3", "Chisel 6.0") 19 | val KnownWidth = chisel3.KnownWidth 20 | } 21 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/internal/plugin/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.internal 4 | 5 | package object plugin { 6 | 7 | /** Used by Chisel's compiler plugin to automatically name signals 8 | * DO NOT USE in your normal Chisel code!!! 9 | * 10 | * @param name The name to use 11 | * @param nameMe The thing to be named 12 | * @tparam T The type of the thing to be named 13 | * @return The thing, but now named 14 | */ 15 | @deprecated("Use chisel3.withName instead", "Chisel 7.0.0") 16 | def autoNameRecursively[T <: Any](name: String)(nameMe: => T): T = chisel3.withName[T](name)(nameMe) 17 | 18 | /** Used by Chisel's compiler plugin to automatically name signals 19 | * DO NOT USE in your normal Chisel code!!! 20 | * 21 | * @param names The names to use corresponding to interesting fields of the Product 22 | * @param nameMe The [[scala.Product]] to be named 23 | * @tparam T The type of the thing to be named 24 | * @return The thing, but with each member named 25 | */ 26 | @deprecated("Use chisel3.withName instead", "Chisel 7.0.0") 27 | def autoNameRecursivelyProduct[T <: Product](names: List[Option[String]])(nameMe: => T): T = 28 | chisel3.withNames(names.map(_.getOrElse("")): _*)(nameMe) 29 | } 30 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/layers/Layers.scala: -------------------------------------------------------------------------------- 1 | package chisel3.layers 2 | 3 | import chisel3.experimental.UnlocatableSourceInfo 4 | import chisel3.layer.{CustomOutputDir, Layer, LayerConfig} 5 | import java.nio.file.Paths 6 | 7 | /** The root [[chisel3.layer.Layer]] for all shared verification collateral. */ 8 | object Verification 9 | extends Layer(LayerConfig.Extract(CustomOutputDir(Paths.get("verification"))))( 10 | _parent = Layer.Root, 11 | _sourceInfo = UnlocatableSourceInfo 12 | ) { 13 | 14 | /** The [[chisel3.layer.Layer]] where all assertions will be placed. */ 15 | object Assert 16 | extends Layer(LayerConfig.Extract(CustomOutputDir(Paths.get("verification", "assert"))))( 17 | _parent = Verification, 18 | _sourceInfo = UnlocatableSourceInfo 19 | ) 20 | 21 | /** The [[chisel3.layer.Layer]] where all assumptions will be placed. */ 22 | object Assume 23 | extends Layer(LayerConfig.Extract(CustomOutputDir(Paths.get("verification", "assume"))))( 24 | _parent = Verification, 25 | _sourceInfo = UnlocatableSourceInfo 26 | ) 27 | 28 | /** The [[chisel3.layer.Layer]] where all covers will be placed. */ 29 | object Cover 30 | extends Layer(LayerConfig.Extract(CustomOutputDir(Paths.get("verification", "cover"))))( 31 | _parent = Verification, 32 | _sourceInfo = UnlocatableSourceInfo 33 | ) 34 | } 35 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/layers/package.scala: -------------------------------------------------------------------------------- 1 | package chisel3 2 | 3 | /** This package contains common [[layer.Layer]]s used by Chisel generators. */ 4 | package object layers { 5 | 6 | /** This is a list of layers that will _always_ be included in the design. This 7 | * is done to provide predictability of what layers will be availble. 8 | * 9 | * This list is not user-extensible. If a user wants to have similar behavior 10 | * for their design, then they should use [[chisel3.layer.addLayer]] API to 11 | * add the layers that they always want to see in their output. 12 | */ 13 | val defaultLayers: Seq[layer.Layer] = Seq( 14 | Verification, 15 | Verification.Assert, 16 | Verification.Assume, 17 | Verification.Cover 18 | ) 19 | 20 | } 21 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/probe/ProbeValueBase.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.probe 4 | 5 | import chisel3.Data 6 | import chisel3.internal.Builder 7 | import chisel3.internal.binding.OpBinding 8 | import chisel3.internal.firrtl.ir.{ProbeExpr, RWProbeExpr} 9 | import chisel3.experimental.{requireIsHardware, SourceInfo} 10 | 11 | private[chisel3] trait ProbeValueBase { 12 | protected def apply[T <: Data](source: T, writable: Boolean)(implicit sourceInfo: SourceInfo): T = { 13 | requireIsHardware(source) 14 | // construct probe to return with cloned info 15 | val clone = if (writable) RWProbe(source.cloneType) else Probe(source.cloneType) 16 | clone.bind(OpBinding(Builder.forcedUserModule, Builder.currentBlock)) 17 | if (writable) { 18 | if (source.isLit) { 19 | Builder.error("Cannot get a probe value from a literal.") 20 | } 21 | clone.setRef(RWProbeExpr(source.ref)) 22 | } else { 23 | val ref = if (source.isLit) { 24 | val intermed = chisel3.Wire(source.cloneType) 25 | intermed := source 26 | intermed.suggestName("lit_probe_val") 27 | intermed.ref 28 | } else { source.ref } 29 | clone.setRef(ProbeExpr(ref)) 30 | } 31 | clone 32 | } 33 | } 34 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/properties/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | /** The properties package includes functionality related to non-hardware data. 6 | * 7 | * This entire package is currently very experimental, so expect some rough 8 | * edges and rapid API evolution. 9 | */ 10 | package object properties {} 11 | -------------------------------------------------------------------------------- /core/src/main/scala/chisel3/util/Naming.scala: -------------------------------------------------------------------------------- 1 | package chisel3.util 2 | 3 | /* Generates a safe 'simple class name' from the given class, avoiding `Malformed class name` exceptions from `getClass.getSimpleName` 4 | * when Java 8 is used. 5 | */ 6 | object simpleClassName { 7 | 8 | def apply[T](clazz: Class[T]): String = { 9 | /* The default class name is derived from the Java reflection derived class name. */ 10 | val baseName = clazz.getName 11 | 12 | /* A sequence of string filters applied to the name */ 13 | val filters: Seq[String => String] = 14 | Seq( 15 | ((a: String) => raw"\$$+anon".r.replaceAllIn(a, "_Anon")) // Merge the "$$anon" name with previous name 16 | ) 17 | 18 | filters 19 | .foldLeft(baseName) { case (str, filter) => filter(str) } // 1. Apply filters to baseName 20 | .split("\\.|\\$") // 2. Split string at '.' or '$' 21 | .filterNot(_.forall(_.isDigit)) // 3. Drop purely numeric names 22 | .last // 4. Use the last name 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /docs-target/src/main/resources/META-INF/services/mdoc.PostModifier: -------------------------------------------------------------------------------- 1 | chisel3.docs.VerilogMdocModifier 2 | -------------------------------------------------------------------------------- /docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala: -------------------------------------------------------------------------------- 1 | package chisel3.docs 2 | 3 | import java.nio.file.Files 4 | import java.nio.file.Paths 5 | import mdoc._ 6 | import scala.meta.inputs.Position 7 | 8 | /** Custom modifier for rendering Chisel-generated Verilog 9 | * 10 | * See chisel3/docs/README.md for use 11 | */ 12 | class VerilogMdocModifier extends PostModifier { 13 | val name = "verilog" 14 | def process(ctx: PostModifierContext): String = { 15 | val result = 16 | ctx.variables.foldLeft(Option("")) { 17 | case (Some(acc), variable) if variable.staticType == "String" => 18 | Some(acc + variable.runtimeValue) 19 | case (Some(_), badVar) => 20 | ctx.reporter.error( 21 | badVar.pos, 22 | s"""type mismatch: 23 | |expected: String 24 | |received: ${badVar.runtimeValue}""".stripMargin 25 | ) 26 | None 27 | case (None, _) => None 28 | } 29 | result match { 30 | case Some(content) => s"```verilog\n$content```\n" 31 | case None => "" 32 | } 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /docs-target/src/main/scala/chisel3/docs/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import circt.stage.ChiselStage 6 | 7 | /** Useful utility methods for generating docs */ 8 | package object docs { 9 | def emitSystemVerilog(gen: => RawModule): String = { 10 | val prettyArgs = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable") 11 | ChiselStage.emitSystemVerilog(gen, firtoolOpts = prettyArgs) 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /docs/Contributors.mill: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package build.docs 4 | 5 | import github4s.Github 6 | import github4s.Github._ 7 | import github4s.domain.User 8 | 9 | import java.util.concurrent.Executors 10 | 11 | import cats.effect.IO 12 | import org.http4s.client.{Client, JavaNetClientBuilder} 13 | 14 | import cats.effect.unsafe.implicits.global 15 | 16 | import Version.GitHubRepository 17 | 18 | val httpClient: Client[IO] = JavaNetClientBuilder[IO].create 19 | 20 | val token: Option[String] = sys.env.get("GITHUB_TOKEN") 21 | 22 | def contributors(repo: GitHubRepository): List[User] = 23 | Github[IO](httpClient, token).repos 24 | .listContributors(repo.owner, repo.repo) 25 | .unsafeRunSync() 26 | .result match { 27 | case Left(e) => 28 | throw new Exception( 29 | s"Unable to fetch contributors for ${repo.serialize}. Did you misspell it? Did the repository move?" + 30 | s" Is access token defined: ${token.isDefined}? Original exception: ${e.getMessage}" 31 | ) 32 | case Right(r) => r 33 | } 34 | 35 | def contributorsMarkdown(contributors: Seq[(String, String)]): String = 36 | contributors 37 | .sortBy(_._1.toLowerCase) 38 | .map { case (login, html_url) => s"- [`@${login}`](${html_url})" } 39 | .mkString("\n") 40 | -------------------------------------------------------------------------------- /docs/src/appendix.md: -------------------------------------------------------------------------------- 1 | # Appendix 2 | 3 | This section covers some less-common Chisel topics. 4 | 5 | * [Experimental Features](appendix/experimental-features) 6 | * [Upgrading from Scala 2.11](appendix/upgrading-from-scala-2-11) 7 | * [Upgrading from Chisel 3.4](appendix/upgrading-from-chisel-3-4) 8 | * [Versioning](appendix/versioning) 9 | -------------------------------------------------------------------------------- /docs/src/cookbooks.md: -------------------------------------------------------------------------------- 1 | # Cookbooks 2 | 3 | Welcome to the Chisel Cookbooks, where we capture frequently-used design patterns or troubleshooting questions. 4 | If you have any requests or examples to share, 5 | please [file an issue](https://github.com/chipsalliance/chisel3/issues/new) and let us know! 6 | 7 | * [General Cookbooks](cookbooks/cookbook) 8 | * [Naming Cookbook](cookbooks/naming) 9 | * [Troubleshooting Guide](cookbooks/troubleshooting) 10 | * [Hierarchy Cookbook](cookbooks/hierarchy) 11 | * [DataView Cookbook](cookbooks/dataview) 12 | -------------------------------------------------------------------------------- /docs/src/cookbooks/objectmodel.md: -------------------------------------------------------------------------------- 1 | --- 2 | sidebar_position: 5 3 | --- 4 | 5 | # ObjectModel Cookbook 6 | 7 | import TOCInline from '@theme/TOCInline'; 8 | 9 | 10 | 11 | ## Example of accessing data from OM class 12 | 13 | ```scala 14 | import chisel3._ 15 | import chisel3.properties._ 16 | import chisel3.panamaom._ 17 | 18 | class IntPropTest extends RawModule { 19 | val intProp = IO(Output(Property[Int]())) 20 | intProp := Property(123) 21 | } 22 | 23 | val converter = Seq( 24 | new chisel3.stage.phases.Elaborate, 25 | chisel3.panamaconverter.stage.Convert 26 | ).foldLeft( 27 | firrtl.AnnotationSeq(Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new IntPropTest))) 28 | ) { case (annos, phase) => phase.transform(annos) } 29 | .collectFirst { 30 | case chisel3.panamaconverter.stage.PanamaCIRCTConverterAnnotation(converter) => converter 31 | } 32 | .get 33 | 34 | val pm = converter.passManager() 35 | assert(pm.populatePreprocessTransforms()) 36 | assert(pm.populateCHIRRTLToLowFIRRTL()) 37 | assert(pm.populateLowFIRRTLToHW()) 38 | assert(pm.populateFinalizeIR()) 39 | assert(pm.run()) 40 | 41 | val om = converter.om() 42 | val evaluator = om.evaluator() 43 | val obj = evaluator.instantiate("PropertyTest_Class", Seq(om.newBasePathEmpty)).get 44 | 45 | val value = obj.field("intProp").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer 46 | assert(value === 123) 47 | ``` 48 | -------------------------------------------------------------------------------- /docs/src/cookbooks/testing.md: -------------------------------------------------------------------------------- 1 | --- 2 | sidebar_position: 6 3 | --- 4 | 5 | # Testing Cookbook 6 | 7 | import TOCInline from '@theme/TOCInline'; 8 | 9 | 10 | 11 | ## How do I change the default testing directory? 12 | 13 | Override the `buildDir` method. 14 | 15 | The example below changes the testing directory to `test/`: 16 | 17 | ``` scala mdoc:reset:silent 18 | import chisel3._ 19 | import chisel3.simulator.scalatest.ChiselSim 20 | import java.nio.file.Paths 21 | import org.scalatest.funspec.AnyFunSpec 22 | 23 | class FooSpec extends FunSpec with ChiselSim { 24 | 25 | override def buildDir: Path = Paths.get("test") 26 | 27 | } 28 | 29 | ``` 30 | 31 | ## How do I enable waveforms for a simulation? 32 | 33 | If using Scalatest and ChiselSim, pass the `-DemitVcd=1` argument to Scalatest, e.g.: 34 | 35 | ``` shell 36 | ./mill 'chisel[2.13.16].test.testOnly' chiselTests.ShiftRegistersSpec -- -DemitVcd=1 37 | ``` 38 | 39 | ## How do I see what options a ChiselSim Scalatest test supports? 40 | 41 | Pass `-Dhelp=1` to Scalatest, e.g.: 42 | 43 | ``` shell 44 | ./mill 'chisel[2.13.16].test.testOnly' chiselTests.ShiftRegistersSpec -- -Dhelp=1 45 | ``` 46 | -------------------------------------------------------------------------------- /docs/src/developers.md: -------------------------------------------------------------------------------- 1 | # Developer Documentation 2 | 3 | Tips and tricks for Chisel developers: 4 | 5 | * [ScalaDoc](developers/scaladoc) 6 | * [Test Coverage](developers/test-coverage) 7 | * [Developers Style Guide](developers/style) 8 | -------------------------------------------------------------------------------- /docs/src/developers/scaladoc.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Scaladoc" 4 | section: "chisel3" 5 | --- 6 | 7 | ## Scaladoc 8 | 9 | We write inline documentation of code and public APIs using ScalaDoc. 10 | 11 | When creating a new feature, you can view the documentation you've written by building the ScalaDoc locally with `sbt`: 12 | 13 | ``` 14 | sbt:chisel> unipublish / doc 15 | ``` 16 | 17 | This will build the documentation in `unipublish/target/scala-2.13/unidoc`, and you can view it by opening `unidoc/index.html` in your browser. 18 | -------------------------------------------------------------------------------- /docs/src/developers/test-coverage.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Test Coverage" 4 | section: "chisel3" 5 | --- 6 | 7 | # Test Coverage 8 | 9 | ## Test Coverage Setup 10 | 11 | Chisel's sbt build instructions contain the requisite plug-in (sbt-scoverage) for generating test coverage information. Please see the [sbt-scoverage web page](https://github.com/scoverage/sbt-scoverage) for details on the plug-in. 12 | The tests themselves are found in `src/test/scala`. 13 | 14 | ## Generating A Test Coverage Report 15 | 16 | Use the following sequence of sbt commands to generate a test coverage report: 17 | ``` 18 | sbt clean coverage test 19 | sbt coverageReport 20 | ``` 21 | The coverage reports should be found in `target/scala-x.yy/scoverage-report/{scoverage.xml,index.html}` where `x.yy` corresponds to the version of Scala used to compile Firrtl and the tests. 22 | `scoverage.xml` is useful if you want to analyze the results programmatically. 23 | `index.html` is designed for navigation with a web browser, allowing one to drill down to invidual statements covered (or not) by the tests. 24 | -------------------------------------------------------------------------------- /docs/src/explanations/annotations.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Annotations" 4 | section: "chisel3" 5 | --- 6 | 7 | # Annotations 8 | 9 | `Annotation`s are metadata containers associated with zero or more "things" in a FIRRTL circuit. 10 | Commonly, `Annotation`s are used to communicate information from Chisel to a specific, known FIRRTL `Transform`. 11 | In this way `Annotation`s can be viewed as the "arguments" that a specific `Transform` consumes. 12 | 13 | `Annotation`s are intended to be an implementation detail of Chisel and are not 14 | meant to be manually constructed or interacted with directly by users. Instead, 15 | they are intended to be used through existing or new Chisel APIs. E.g., the 16 | `dontTouch` API provides a way for a user to indicate that a wire or port should 17 | not be optimized. This API is backed by a `DontTouchAnnotation`, but this is 18 | hidden from Chisel users. 19 | 20 | A list of all supported `Annotation`s is maintained [as part of documentation of 21 | the FIRRTL Dialect on 22 | circt.llvm.org](https://circt.llvm.org/docs/Dialects/FIRRTL/FIRRTLAnnotations/). 23 | -------------------------------------------------------------------------------- /docs/src/explanations/functional-abstraction.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Functional Abstraction" 4 | section: "chisel3" 5 | --- 6 | 7 | # Functional Abstraction 8 | 9 | We can define functions to factor out a repeated piece of logic that 10 | we later reuse multiple times in a design. For example, we can wrap 11 | up our earlier example of a simple combinational logic block as 12 | follows: 13 | 14 | ```scala mdoc:invisible 15 | import chisel3._ 16 | ``` 17 | 18 | ```scala mdoc:silent 19 | def clb(a: UInt, b: UInt, c: UInt, d: UInt): UInt = 20 | (a & b) | (~c & d) 21 | ``` 22 | 23 | where ```clb``` is the function which takes ```a```, ```b```, 24 | ```c```, ```d``` as arguments and returns a wire to the output of a 25 | boolean circuit. The ```def``` keyword is part of Scala and 26 | introduces a function definition, with each argument followed by a colon then 27 | its type, and the function return type given after the colon following the 28 | argument list. The equals (`=`) sign separates the function argument list 29 | from the function definition. 30 | 31 | We can then use the block in another circuit as follows: 32 | ```scala mdoc:silent 33 | val out = clb(a,b,c,d) 34 | ``` 35 | -------------------------------------------------------------------------------- /docs/src/explanations/intrinsics.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Intrinsics" 4 | section: "chisel3" 5 | --- 6 | 7 | # Intrinsics 8 | 9 | Chisel *Intrinsics* are used to express implementation defined functionality. 10 | Intrinsics provide a way for specific compilers to extend the capabilities of 11 | the language in ways which are not implementable with library code. 12 | 13 | Intrinsics will be typechecked by the implementation. What intrinsics are 14 | available is documented by an implementation. 15 | 16 | The `Intrinsic` and `IntrinsicExpr` can be used to create intrinsic statements 17 | and expressions. 18 | 19 | ### Parameterization 20 | 21 | Parameters can be passed as an argument to the IntModule constructor. 22 | 23 | ### Intrinsic Expression Example 24 | 25 | This following creates an intrinsic for the intrinsic named "MyIntrinsic". 26 | It takes a parameter named "STRING" and has several inputs. 27 | 28 | ```scala mdoc:invisible 29 | import chisel3._ 30 | // Below is required for scala 3 migration 31 | import chisel3.experimental.fromStringToStringParam 32 | ``` 33 | 34 | ```scala mdoc:compile-only 35 | class Foo extends RawModule { 36 | val myresult = IntrinsicExpr("MyIntrinsic", UInt(32.W), "STRING" -> "test")(3.U, 5.U) 37 | } 38 | ``` 39 | -------------------------------------------------------------------------------- /docs/src/explanations/source-locators.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Source Locators" 4 | section: "chisel3" 5 | --- 6 | 7 | # Source Locators 8 | 9 | When elaborating a Chisel design and emitting a FIRRTL file or Verilog file, Chisel will automatically 10 | add source locators which refer back to the Scala file containing the corresponding Chisel code. 11 | 12 | In a FIRRTL file, it looks like this: 13 | 14 | ``` 15 | wire w : UInt<3> @[src/main/scala/MyProject/MyFile.scala 1210:21] 16 | ``` 17 | 18 | In a Verilog file, it looks like this: 19 | 20 | ```verilog 21 | wire [2:0] w; // @[src/main/scala/MyProject/MyFile.scala 1210:21] 22 | ``` 23 | 24 | By default, the file's relative path to where the JVM is invoked is included. 25 | To change where the relative path is computed, set the Java system property `-Dchisel.project.root=/absolute/path/to/root`. 26 | This option can be directly passed to sbt (`sbt -Dchisel.project.root=/absolute/path/to/root`). 27 | Setting the value in the `build.sbt` file won't work because it needs to be passed to the JVM that invokes sbt (not the other way around). 28 | We expect this only relevant for publishing versions which may want more customization. 29 | -------------------------------------------------------------------------------- /docs/src/explanations/supported-hardware.md: -------------------------------------------------------------------------------- 1 | --- 2 | layout: docs 3 | title: "Supported Hardware" 4 | section: "chisel3" 5 | --- 6 | 7 | # Supported Hardware 8 | 9 | While Chisel focuses on binary logic, Chisel can support analog and tri-state wires with the `Analog` type - see [Datatypes in Chisel](data-types). 10 | 11 | We focus on binary logic designs as they constitute the vast majority of designs in practice. Tri-state logic are poorly supported standard industry flows and require special/controlled hard macros in order to be done. 12 | -------------------------------------------------------------------------------- /docs/src/images/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | 3 | sources = \ 4 | type_hierarchy.dot 5 | 6 | all: $(sources:%.dot=%.svg) $(sources:%.dot=%.png) 7 | 8 | %.svg: %.dot 9 | dot -Tsvg $< -o $@ 10 | 11 | %.png: %.dot 12 | dot -Tpng $< -o $@ 13 | -------------------------------------------------------------------------------- /docs/src/images/chisel_01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/docs/src/images/chisel_01.png -------------------------------------------------------------------------------- /docs/src/images/chisel_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/docs/src/images/chisel_logo.png -------------------------------------------------------------------------------- /docs/src/images/type_hierarchy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/docs/src/images/type_hierarchy.png -------------------------------------------------------------------------------- /docs/src/resources.md: -------------------------------------------------------------------------------- 1 | # Chisel Resources 2 | 3 | The *best resource* to learn about Chisel is the [**online Chisel Bootcamp**](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master). This runs in your browser and assumes no prior Scala knowledge. (You may also run this locally via the [backing chisel-bootcamp GitHub repository](https://github.com/freechipsproject/chisel-bootcamp).) 4 | 5 | When you're ready to build your own circuits in Chisel, **we recommend starting from the [Chisel Template](https://github.com/chipsalliance/chisel-template) repository**, which provides a pre-configured project, example design, and testbench. Follow the [chisel-template readme](https://github.com/chipsalliance/chisel-template) to get started. 6 | 7 | The following additional resources and references may be useful: 8 | 9 | - [Chisel Cheatsheet](https://github.com/freechipsproject/chisel-cheatsheet/releases/latest/download/chisel_cheatsheet.pdf) 10 | - [Digital Design With Chisel](https://github.com/schoeberl/chisel-book) 11 | - [Frequently Asked Questions](resources/faqs) 12 | -------------------------------------------------------------------------------- /etc/README.md: -------------------------------------------------------------------------------- 1 | This directory contains metadata and configuration information related to 2 | Chisel. This information is kept separate from the `.github/` directory to 3 | enable automatic updating of metadata and configuration information by GitHub 4 | Actions which, by default, cannot update the `.github/` directory without 5 | elevated permissions. 6 | -------------------------------------------------------------------------------- /etc/circt.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "firtool-1.120.0" 3 | } 4 | -------------------------------------------------------------------------------- /firrtl/.gitignore: -------------------------------------------------------------------------------- 1 | .DS_STORE 2 | */*.DS_STORE 3 | */*/*.DS_STORE 4 | */*/*/*.DS_STORE 5 | */*/*/*/*.DS_STORE 6 | *.tmp 7 | */*.temp 8 | */*/*.temp 9 | */*/*/*.temp 10 | *.swp 11 | */*.swp 12 | */*/*.swp 13 | */*/*/*.swp 14 | */*.flo 15 | */*.v 16 | */*.out 17 | */*/*.flo 18 | */*/*.v 19 | */*/*.out 20 | */*/Output 21 | */*/*/*.flo 22 | */*/*/*.v 23 | */*/*/*.out 24 | */*/*/Output 25 | src/lib/stanzam 26 | src/lib/stanza 27 | src/*/__MACOSX 28 | src/main/stanza/firrtl-main 29 | utils/bin/firrtl 30 | utils/bin/stanza 31 | utils/bin/firrtl-scala 32 | utils/bin/firrtl-stanza 33 | utils/bin/firrtl.jar 34 | utils/bin/firrtl-test.jar 35 | utils/bin/FileCheck 36 | spec/spec.aux 37 | spec/spec.log 38 | spec/spec.toc 39 | spec/spec.out 40 | spec/spec.synctex.gz 41 | notes/*.docx 42 | test_run_dir 43 | __pycache__ 44 | 45 | .project 46 | 47 | # sbt specific 48 | .cache 49 | .history 50 | .lib/ 51 | dist/* 52 | target/ 53 | lib_managed/ 54 | src_managed/ 55 | project/boot/ 56 | project/plugins/project/ 57 | .idea/ 58 | .idea_modules/ 59 | gen/ 60 | project/project/ 61 | /bin/ 62 | out/ 63 | .bloop 64 | .metals 65 | .bsp 66 | project/metals.sbt 67 | 68 | *~ 69 | *#*# 70 | .vscode 71 | -------------------------------------------------------------------------------- /firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/PassBenchmark.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package firrtl 3 | package benchmark 4 | package hot 5 | 6 | import firrtl.passes._ 7 | import firrtl.stage.TransformManager 8 | 9 | import firrtl.benchmark.util._ 10 | 11 | abstract class PassBenchmark(passFactory: () => Pass) extends App { 12 | val inputFile = args(0) 13 | val warmup = args(1).toInt 14 | val runs = args(2).toInt 15 | 16 | val input = filenameToCircuit(inputFile) 17 | val inputState = CircuitState(input, ChirrtlForm) 18 | 19 | val manager = new TransformManager(passFactory().prerequisites) 20 | val preState = manager.execute(inputState) 21 | 22 | hot.util.benchmark(warmup, runs)(passFactory().run(preState.circuit)) 23 | } 24 | 25 | object ResolveKindsBenchmark extends PassBenchmark(() => ResolveKinds) 26 | 27 | object CheckHighFormBenchmark extends PassBenchmark(() => CheckHighForm) 28 | 29 | object CheckWidthsBenchmark extends PassBenchmark(() => CheckWidths) 30 | 31 | object InferBinaryPointsBenchmark extends PassBenchmark(() => new InferBinaryPoints) 32 | -------------------------------------------------------------------------------- /firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package firrtl 3 | package benchmark 4 | package hot 5 | 6 | import firrtl._ 7 | import firrtl.passes.LowerTypes 8 | import firrtl.stage.TransformManager 9 | import firrtl.benchmark.util._ 10 | import firrtl.transforms.DedupModules 11 | 12 | abstract class TransformBenchmark(factory: () => Transform) extends App { 13 | val inputFile = args(0) 14 | val warmup = args(1).toInt 15 | val runs = args(2).toInt 16 | 17 | val input = filenameToCircuit(inputFile) 18 | val inputState = CircuitState(input, ChirrtlForm) 19 | 20 | val manager = new TransformManager(factory().prerequisites) 21 | val preState = manager.execute(inputState) 22 | 23 | hot.util.benchmark(warmup, runs)(factory().transform(preState)) 24 | } 25 | 26 | object LowerTypesBenchmark extends TransformBenchmark(() => LowerTypes) 27 | 28 | object DedupBenchmark extends TransformBenchmark(() => new DedupModules()) -------------------------------------------------------------------------------- /firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala: -------------------------------------------------------------------------------- 1 | 2 | package firrtl.benchmark.hot 3 | 4 | import firrtl.Utils.time 5 | import firrtl.benchmark.util._ 6 | 7 | package object util { 8 | def benchmark(nWarmup: Int, nRun: Int)(f: => Unit): Unit = { 9 | // Warmup 10 | for (i <- 0 until nWarmup) { 11 | val (t, res) = time(f) 12 | println(f"Warmup run $i took $t%.1f ms") 13 | } 14 | 15 | // Benchmark 16 | val times: Array[Double] = Array.fill(nRun)(0.0) 17 | for (i <- 0 until nRun) { 18 | System.gc 19 | val (t, res) = time(f) 20 | times(i) = t 21 | println(f"Benchmark run $i took $t%.1f ms") 22 | } 23 | 24 | println(f"Mean: ${mean(times)}%.1f ms") 25 | println(f"Median: ${median(times)}%.1f ms") 26 | println(f"Stddev: ${stdDev(times)}%.1f ms") 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /firrtl/benchmark/src/main/scala/firrtl/benchmark/util/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | package benchmark 5 | 6 | import firrtl.ir.Circuit 7 | import scala.util.control.NonFatal 8 | 9 | package object util { 10 | def filenameToCircuit(filename: String): Circuit = try { 11 | proto.FromProto.fromFile(filename) 12 | } catch { 13 | case NonFatal(_) => Parser.parseFile(filename, Parser.IgnoreInfo) 14 | } 15 | 16 | def mean(xs: Iterable[Double]): Double = xs.sum / xs.size 17 | 18 | def median(xs: Iterable[Double]): Double = { 19 | val size = xs.size 20 | val sorted = xs.toSeq.sorted 21 | if (size % 2 == 1) sorted(size / 2) 22 | else { 23 | val a = sorted(size / 2) 24 | val b = sorted((size / 2) - 1) 25 | (a + b) / 2 26 | } 27 | } 28 | 29 | def variance(xs: Iterable[Double]): Double = { 30 | val avg = mean(xs) 31 | xs.map(a => math.pow(a - avg, 2)).sum / xs.size 32 | } 33 | 34 | def stdDev(xs: Iterable[Double]): Double = math.sqrt(variance(xs)) 35 | } 36 | -------------------------------------------------------------------------------- /firrtl/doc/images/firrtl_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/firrtl/doc/images/firrtl_logo.png -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/AttributeAnnotation.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package firrtl 3 | 4 | import firrtl.annotations.{Named, SingleTargetAnnotation} 5 | 6 | /** Firrtl implementation for verilog attributes 7 | * @param target target component to tag with attribute 8 | * @param description Attribute string to add to target 9 | */ 10 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 11 | case class AttributeAnnotation(target: Named, description: String) extends SingleTargetAnnotation[Named] { 12 | def duplicate(n: Named): AttributeAnnotation = this.copy(target = n, description = description) 13 | } 14 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/Compiler.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | 5 | import firrtl.annotations._ 6 | 7 | /** Container of all annotations for a Firrtl compiler */ 8 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 9 | class AnnotationSeq private (underlying: Seq[Annotation]) { 10 | def toSeq: Seq[Annotation] = underlying 11 | } 12 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 13 | object AnnotationSeq { 14 | def apply(xs: Seq[Annotation]): AnnotationSeq = new AnnotationSeq(xs) 15 | } 16 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/FirrtlException.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | 5 | import scala.util.control.NoStackTrace 6 | 7 | /** Exception indicating user error 8 | * 9 | * These exceptions indicate a problem due to bad input and thus do not include a stack trace. 10 | * This can be extended by custom transform writers. 11 | */ 12 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 13 | class FirrtlUserException(message: String, cause: Throwable = null) 14 | extends RuntimeException(message, cause) 15 | with NoStackTrace 16 | 17 | /** Exception indicating something went wrong *within* Firrtl itself 18 | * 19 | * These exceptions indicate a problem inside the compiler and include a stack trace to help 20 | * developers debug the issue. 21 | * 22 | * This class is private because these are issues within Firrtl itself. Exceptions thrown in custom 23 | * transforms are treated differently and should thus have their own structure 24 | */ 25 | private[firrtl] class FirrtlInternalException(message: String, cause: Throwable = null) 26 | extends Exception(message, cause) 27 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/Parser.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | 5 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 6 | object Parser { 7 | 8 | sealed abstract class InfoMode 9 | 10 | case object IgnoreInfo extends InfoMode 11 | 12 | case object UseInfo extends InfoMode 13 | 14 | case class GenInfo(filename: String) extends InfoMode 15 | 16 | case class AppendInfo(filename: String) extends InfoMode 17 | 18 | } 19 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl.annotations 4 | 5 | /** 6 | * Represents the initial value of the annotated memory. 7 | * While not supported on normal ASIC flows, it can be useful for simulation and FPGA flows. 8 | * This annotation is consumed by the verilog emitter. 9 | */ 10 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 11 | sealed trait MemoryInitAnnotation extends SingleTargetAnnotation[ReferenceTarget] { 12 | def isRandomInit: Boolean 13 | } 14 | 15 | /** Initialize the `target` memory with inline readmem[hb] statement. */ 16 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 17 | case class MemoryFileInlineAnnotation( 18 | target: ReferenceTarget, 19 | filename: String, 20 | hexOrBinary: MemoryLoadFileType.FileType = MemoryLoadFileType.Hex 21 | ) extends MemoryInitAnnotation { 22 | require(filename.trim.nonEmpty, "empty filename not allowed in MemoryFileInlineAnnotation") 23 | override def duplicate(n: ReferenceTarget): Annotation = copy(n) 24 | override def isRandomInit: Boolean = false 25 | } 26 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/options/ExitCodes.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl.options 4 | 5 | /** The supertype of all exit codes */ 6 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 7 | sealed trait ExitCode { val number: Int } 8 | 9 | /** [[ExitCode]] indicating success */ 10 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 11 | object ExitSuccess extends ExitCode { val number = 0 } 12 | 13 | /** An [[ExitCode]] indicative of failure. This must be non-zero and should not conflict with a reserved exit code. */ 14 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 15 | sealed trait ExitFailure extends ExitCode 16 | 17 | /** An exit code indicating a general, non-specific error */ 18 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 19 | object GeneralError extends ExitFailure { val number = 1 } 20 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/options/internal/WritableCircuitAnnotation.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl.options.internal 4 | 5 | import firrtl.options.CustomFileEmission 6 | import firrtl.annotations.Annotation 7 | 8 | import java.io.File 9 | 10 | // Hack for enabling special emission of the ChiselCircuitAnnotation in WriteOutputAnnotations 11 | @deprecated("This trait is for internal use only. Do not use it.", "Chisel 5.0") 12 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 13 | trait WriteableCircuitAnnotation extends Annotation with CustomFileEmission { 14 | 15 | protected def writeToFileImpl(file: File, annos: Seq[Annotation]): Unit 16 | 17 | private[firrtl] final def writeToFile(file: File, annos: Seq[Annotation]): Unit = writeToFileImpl(file, annos) 18 | } 19 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/options/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | 5 | package object options { 6 | 7 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 8 | implicit object StageOptionsView extends OptionsView[StageOptions] { 9 | def view(options: AnnotationSeq): StageOptions = options.collect { case a: StageOption => a } 10 | .foldLeft(new StageOptions())((c, x) => 11 | x match { 12 | case TargetDirAnnotation(a) => c.copy(targetDir = a) 13 | /* Insert input files at the head of the Seq for speed and because order shouldn't matter */ 14 | case InputAnnotationFileAnnotation(a) => c.copy(annotationFilesIn = a +: c.annotationFilesIn) 15 | case OutputAnnotationFileAnnotation(a) => c.copy(annotationFileOut = Some(a)) 16 | /* Do NOT reorder program args. The order may matter. */ 17 | case ProgramArgsAnnotation(a) => c.copy(programArgs = c.programArgs :+ a) 18 | } 19 | ) 20 | } 21 | 22 | } 23 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/options/phases/AddDefaults.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl.options.phases 4 | 5 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 6 | import firrtl.options.{Dependency, Phase, TargetDirAnnotation} 7 | 8 | /** Add default annotations for a [[Stage]] 9 | * 10 | * This currently only adds a [[TargetDirAnnotation]]. This isn't necessary for a [[StageOptionsView]], but downstream 11 | * tools may expect a [[TargetDirAnnotation]] to exist. 12 | */ 13 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 14 | class AddDefaults extends Phase { 15 | 16 | override def prerequisites = Seq(Dependency[GetIncludes]) 17 | 18 | override def optionalPrerequisiteOf = Seq.empty 19 | 20 | override def invalidates(a: Phase) = false 21 | 22 | def transform(annotations: AnnotationSeq): AnnotationSeq = { 23 | val td = annotations.collectFirst { case a: TargetDirAnnotation => a }.isEmpty 24 | 25 | (if (td) Seq(TargetDirAnnotation()) else Seq()) ++ 26 | annotations 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | import firrtl.annotations.Annotation 4 | 5 | package object firrtl { 6 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 7 | implicit def seqToAnnoSeq(xs: Seq[Annotation]): AnnotationSeq = AnnotationSeq(xs) 8 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 9 | implicit def annoSeqToSeq(as: AnnotationSeq): Seq[Annotation] = as.toSeq 10 | } 11 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/passes/Inline.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | package passes 5 | 6 | import firrtl.annotations._ 7 | import firrtl.options.{HasShellOptions, ShellOption} 8 | 9 | /** Indicates that something should be inlined */ 10 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 11 | case class InlineAnnotation(target: Named) extends SingleTargetAnnotation[Named] { 12 | def duplicate(n: Named) = InlineAnnotation(n) 13 | } 14 | 15 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 16 | object InlineAnnotation extends HasShellOptions { 17 | 18 | override val options = Seq( 19 | new ShellOption[Seq[String]]( 20 | longOption = "inline", 21 | toAnnotationSeq = (a: Seq[String]) => 22 | a.map { value => 23 | value.split('.') match { 24 | case Array(circuit, module) => 25 | InlineAnnotation(ModuleName(module)) 26 | case Array(circuit, module, inst) => 27 | InlineAnnotation(ComponentName(inst, ModuleName(module))) 28 | } 29 | }, 30 | helpText = "Inline selected modules", 31 | shortOption = Some("fil"), 32 | helpValueName = Some("[.[.]][,...]") 33 | ) 34 | ) 35 | 36 | } 37 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/passes/wiring/WiringTransform.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl.passes 4 | package wiring 5 | 6 | import firrtl.annotations._ 7 | 8 | /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */ 9 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 10 | case class SourceAnnotation(target: ComponentName, pin: String) extends SingleTargetAnnotation[ComponentName] { 11 | def duplicate(n: ComponentName) = this.copy(target = n) 12 | } 13 | 14 | /** A module, e.g. ExtModule etc., that should add the input pin */ 15 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 16 | case class SinkAnnotation(target: Named, pin: String) extends SingleTargetAnnotation[Named] { 17 | def duplicate(n: Named) = this.copy(target = n) 18 | } 19 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/stage/FirrtlOptions.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl.stage 4 | 5 | import firrtl.ir.Circuit 6 | 7 | /** Internal options used to control the FIRRTL compiler stage. 8 | * @param outputFileName output file, default: `targetDir/topName.SUFFIX` with `SUFFIX` as determined by the compiler 9 | * @param infoModeName the policy for generating [[firrtl.ir Info]] when processing FIRRTL (default: "append") 10 | * @param firrtlCircuit a [[firrtl.ir Circuit]] 11 | */ 12 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 13 | class FirrtlOptions private[stage] ( 14 | val outputFileName: Option[String] = None, 15 | val infoModeName: String = InfoModeAnnotation().modeName, 16 | val firrtlCircuit: Option[Circuit] = None 17 | ) { 18 | 19 | private[stage] def copy( 20 | outputFileName: Option[String] = outputFileName, 21 | infoModeName: String = infoModeName, 22 | firrtlCircuit: Option[Circuit] = firrtlCircuit 23 | ): FirrtlOptions = { 24 | 25 | new FirrtlOptions(outputFileName = outputFileName, infoModeName = infoModeName, firrtlCircuit = firrtlCircuit) 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/stage/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | 5 | import firrtl.options.OptionsView 6 | import logger.LazyLogging 7 | 8 | /** The [[stage]] package provides Stage/Phase infrastructure for FIRRTL compilers: 9 | * - A number of support [[options.Phase Phase]]s 10 | * - [[FirrtlOptions]], a class representing options common to FIRRTL compilers 11 | * - [[FirrtlOptionsView]], a utility that constructs an [[options.OptionsView OptionsView]] of [[FirrtlOptions]] 12 | * from an [[AnnotationSeq]] 13 | */ 14 | package object stage { 15 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 16 | implicit object FirrtlOptionsView extends OptionsView[FirrtlOptions] with LazyLogging { 17 | 18 | /** 19 | * @todo custom transforms are appended as discovered, can this be prepended safely? 20 | */ 21 | def view(options: AnnotationSeq): FirrtlOptions = options.collect { case a: FirrtlOption => a } 22 | .foldLeft(new FirrtlOptions()) { (c, x) => 23 | x match { 24 | case OutputFileAnnotation(f) => c.copy(outputFileName = Some(f)) 25 | case InfoModeAnnotation(i) => c.copy(infoModeName = i) 26 | case FirrtlCircuitAnnotation(cir) => c.copy(firrtlCircuit = Some(cir)) 27 | case AllowUnrecognizedAnnotations => c 28 | } 29 | } 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/transforms/Dedup.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | package transforms 5 | 6 | import firrtl.annotations._ 7 | 8 | /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */ 9 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 10 | case class NoDedupAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] { 11 | def duplicate(n: ModuleTarget): NoDedupAnnotation = NoDedupAnnotation(n) 12 | } 13 | 14 | /** Assign the targeted module to a dedup group. Only modules in the same group may be deduplicated. */ 15 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 16 | case class DedupGroupAnnotation(target: ModuleTarget, group: String) extends SingleTargetAnnotation[ModuleTarget] { 17 | def duplicate(n: ModuleTarget): DedupGroupAnnotation = DedupGroupAnnotation(n, group) 18 | } 19 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/transforms/Flatten.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | package transforms 5 | 6 | import firrtl.annotations._ 7 | 8 | /** Tags an annotation to be consumed by this transform */ 9 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 10 | case class FlattenAnnotation(target: Named) extends SingleTargetAnnotation[Named] { 11 | def duplicate(n: Named) = FlattenAnnotation(n) 12 | } 13 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/transforms/MustDedup.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package firrtl.transforms 4 | 5 | import firrtl._ 6 | import firrtl.annotations._ 7 | 8 | /** Marks modules as "must deduplicate" */ 9 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 10 | case class MustDeduplicateAnnotation(modules: Seq[IsModule]) extends Annotation { 11 | 12 | def update(renames: RenameMap): Seq[MustDeduplicateAnnotation] = { 13 | val newModules: Seq[IsModule] = modules.flatMap { m => 14 | renames.get(m) match { 15 | case None => Seq(m) 16 | case Some(Seq()) => Seq() 17 | case Some(Seq(one: IsModule)) => Seq(one) 18 | case Some(many) => 19 | val msg = "Something went wrong! This anno's targets should only rename to IsModules! " + 20 | s"Got: ${m.serialize} -> ${many.map(_.serialize).mkString(", ")}" 21 | throw new Exception(msg) 22 | } 23 | } 24 | if (newModules.isEmpty) Seq() else Seq(this.copy(newModules)) 25 | } 26 | } 27 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/firrtl/transforms/OptimizationAnnotations.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtl 4 | package transforms 5 | 6 | import firrtl.annotations._ 7 | 8 | /** A component that should be preserved 9 | * 10 | * DCE treats the component as a top-level sink of the circuit 11 | */ 12 | @deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0") 13 | case class DontTouchAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] { 14 | def targets = Seq(target) 15 | def duplicate(n: ReferenceTarget) = this.copy(n) 16 | } 17 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/logger/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | import firrtl.{annoSeqToSeq, AnnotationSeq} 4 | import firrtl.options.OptionsView 5 | 6 | package object logger { 7 | 8 | implicit object LoggerOptionsView extends OptionsView[LoggerOptions] { 9 | def view(options: AnnotationSeq): LoggerOptions = options 10 | .foldLeft(new LoggerOptions()) { (c, x) => 11 | x match { 12 | case LogLevelAnnotation(logLevel) => c.copy(globalLogLevel = logLevel) 13 | case ClassLogLevelAnnotation(name, level) => c.copy(classLogLevels = c.classLogLevels + (name -> level)) 14 | case LogFileAnnotation(f) => c.copy(logFileName = f) 15 | case LogClassNamesAnnotation => c.copy(logClassNames = true) 16 | case _ => c 17 | } 18 | } 19 | } 20 | 21 | } 22 | -------------------------------------------------------------------------------- /firrtl/src/main/scala/logger/phases/AddDefaults.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package logger.phases 4 | 5 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 6 | import firrtl.options.Phase 7 | 8 | import logger.{LogLevelAnnotation, LoggerOption} 9 | 10 | /** Add default logger [[Annotation]]s */ 11 | private[logger] class AddDefaults extends Phase { 12 | 13 | override def prerequisites = Seq.empty 14 | override def optionalPrerequisiteOf = Seq.empty 15 | override def invalidates(a: Phase) = false 16 | 17 | /** Add missing default [[Logger]] [[Annotation]]s to an [[AnnotationSeq]] 18 | * @param annotations input annotations 19 | * @return output annotations with defaults 20 | */ 21 | def transform(annotations: AnnotationSeq): AnnotationSeq = { 22 | var ll = true 23 | annotations.collect { case a: LoggerOption => a }.map { 24 | case _: LogLevelAnnotation => ll = false 25 | case _ => 26 | } 27 | annotations ++ 28 | (if (ll) Seq(LogLevelAnnotation()) else Seq()) 29 | } 30 | 31 | } 32 | -------------------------------------------------------------------------------- /firrtl/src/test/resources/META-INF/services/firrtl.options.RegisteredLibrary: -------------------------------------------------------------------------------- 1 | firrtlTests.options.BarLibrary -------------------------------------------------------------------------------- /firrtl/src/test/resources/annotations/SampleAnnotations.anno.json: -------------------------------------------------------------------------------- 1 | [ 2 | { 3 | "class":"firrtl.passes.InlineAnnotation", 4 | "target":"Top.Foo" 5 | }, 6 | { 7 | "class":"firrtl.passes.InlineAnnotation", 8 | "target":"Top.Bar" 9 | }, 10 | { 11 | "class":"firrtl.passes.InlineAnnotation", 12 | "target":"Top.Foo.x" 13 | }, 14 | { 15 | "class":"firrtl.passes.InlineAnnotation", 16 | "target":"Top.Foo.y" 17 | }, 18 | { 19 | "class":"firrtl.passes.InlineAnnotation", 20 | "target":"Top" 21 | }, 22 | { 23 | "class":"firrtl.passes.InlineAnnotation", 24 | "target":"OtherTop" 25 | }, 26 | { 27 | "class":"firrtl.passes.InlineAnnotation", 28 | "target":"OtherTop.Foo.x" 29 | }, 30 | { 31 | "class":"firrtl.passes.InlineAnnotation", 32 | "target":"OtherTop.Bar" 33 | }, 34 | { 35 | "class":"firrtl.passes.InlineAnnotation", 36 | "target":"OtherTop.Foo.y" 37 | } 38 | ] 39 | 40 | -------------------------------------------------------------------------------- /firrtl/src/test/scala/firrtlTests/annotationTests/AttributeAnnotationSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtlTests.annotationTests 4 | 5 | import firrtl.AttributeAnnotation 6 | import firrtl.annotations._ 7 | import org.scalatest.freespec.AnyFreeSpec 8 | import org.scalatest.matchers.should.Matchers 9 | import org.json4s.convertToJsonInput 10 | 11 | class AttributeAnnotationSpec extends AnyFreeSpec with Matchers { 12 | "AttributeAnnotation should be correctly parsed from a string" in { 13 | val attribAnno = new AttributeAnnotation( 14 | ComponentName("attrib", ModuleName("ModuleAttrib")), 15 | "X_INTERFACE_INFO = \"some:interface:type:1.0 SIGNAL\"" 16 | ) 17 | 18 | val annoString = JsonProtocol.serializeTry(Seq(attribAnno)).get 19 | val loadedAnnos = JsonProtocol.deserializeTry(annoString).get 20 | attribAnno should equal(loadedAnnos.head) 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /firrtl/src/test/scala/firrtlTests/options/RegistrationSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtlTests.options 4 | 5 | import org.scalatest.flatspec.AnyFlatSpec 6 | import org.scalatest.matchers.should.Matchers 7 | import java.util.ServiceLoader 8 | 9 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 10 | import firrtl.options.{RegisteredLibrary, ShellOption} 11 | import firrtl.ir.Circuit 12 | import firrtl.annotations.NoTargetAnnotation 13 | import org.scalatest.flatspec.AnyFlatSpec 14 | import org.scalatest.matchers.should.Matchers 15 | 16 | case object HelloAnnotation extends NoTargetAnnotation 17 | 18 | class BarLibrary extends RegisteredLibrary { 19 | def name: String = "Bar" 20 | 21 | val options = Seq( 22 | new ShellOption[Unit](longOption = "world", toAnnotationSeq = _ => Seq(HelloAnnotation), helpText = "World option") 23 | ) 24 | } 25 | 26 | class RegistrationSpec extends AnyFlatSpec with Matchers { 27 | 28 | behavior.of("RegisteredLibrary") 29 | 30 | it should "BarLibrary be discovered by Java.util.ServiceLoader" in { 31 | val iter = ServiceLoader.load(classOf[RegisteredLibrary]).iterator() 32 | val transforms = scala.collection.mutable.ArrayBuffer[RegisteredLibrary]() 33 | while (iter.hasNext) { 34 | transforms += iter.next() 35 | } 36 | transforms.map(_.getClass.getName) should contain("firrtlTests.options.BarLibrary") 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /firrtl/src/test/scala/firrtlTests/options/phases/AddDefaultsSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package firrtlTests.options.phases 4 | 5 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 6 | import firrtl.options.{Phase, TargetDirAnnotation} 7 | import firrtl.options.phases.AddDefaults 8 | import org.scalatest.flatspec.AnyFlatSpec 9 | import org.scalatest.matchers.should.Matchers 10 | 11 | class AddDefaultsSpec extends AnyFlatSpec with Matchers { 12 | 13 | class Fixture { 14 | val phase: Phase = new AddDefaults 15 | val targetDir = TargetDirAnnotation("foo") 16 | val defaultDir = TargetDirAnnotation(".") 17 | } 18 | 19 | behavior.of(classOf[AddDefaults].toString) 20 | 21 | it should "add a TargetDirAnnotation if it does not exist" in new Fixture { 22 | phase.transform(Seq.empty).toSeq should be(Seq(defaultDir)) 23 | } 24 | 25 | it should "don't add a TargetDirAnnotation if it exists" in new Fixture { 26 | phase.transform(Seq(targetDir)).toSeq should be(Seq(targetDir)) 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /flake.nix: -------------------------------------------------------------------------------- 1 | { 2 | description = "chisel"; 3 | 4 | inputs = { 5 | nixpkgs.url = "github:NixOS/nixpkgs/master"; 6 | flake-utils.url = "github:numtide/flake-utils"; 7 | }; 8 | 9 | outputs = { self, nixpkgs, flake-utils }@inputs: 10 | let 11 | overlay = import ./overlay.nix; 12 | in 13 | flake-utils.lib.eachDefaultSystem 14 | (system: 15 | let 16 | pkgs = import nixpkgs { inherit system; overlays = [ overlay ]; }; 17 | deps = with pkgs; [ 18 | jdk21 19 | mill 20 | circt 21 | jextract-21 22 | lit 23 | scala-cli 24 | llvm 25 | verilator 26 | ]; 27 | in 28 | { 29 | legacyPackages = pkgs; 30 | devShell = pkgs.mkShell { 31 | buildInputs = deps; 32 | env = { 33 | CIRCT_INSTALL_PATH = pkgs.circt-all; 34 | JEXTRACT_INSTALL_PATH = pkgs.jextract-21; 35 | }; 36 | }; 37 | } 38 | ) // { inherit inputs; overlays.default = overlay; }; 39 | } 40 | -------------------------------------------------------------------------------- /integration-tests/package.mill: -------------------------------------------------------------------------------- 1 | package build.`integration-tests` 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | 10 | object `package` extends RootModule { 11 | // https://github.com/com-lihaoyi/mill/issues/3693 12 | object cross extends Cross[IntegrationTests](v.scalaCrossVersions) 13 | } 14 | 15 | trait IntegrationTests extends CrossSbtModule with HasScalaPlugin with HasCommonOptions with ScalafmtModule { 16 | def pluginModule = plugin.cross() 17 | def millSourcePath = super.millSourcePath / os.up 18 | 19 | // TODO enable 20 | override def xsource3 = false 21 | 22 | object test extends CrossSbtTests with TestModule.ScalaTest with ScalafmtModule { 23 | override def moduleDeps = super.moduleDeps :+ chisel().test 24 | def ivyDeps = Agg(v.scalatest, v.scalacheck) 25 | 26 | override def testForkGrouping = discoveredTestClasses().grouped(8).toSeq 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /integration-tests/src/test/scala-2/chiselTest/ShiftRegisterMemSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import chisel3.util.{Counter, ShiftRegister} 9 | import org.scalacheck.{Gen, Shrink} 10 | import org.scalatest.propspec.AnyPropSpec 11 | 12 | class ShiftMemTester(n: Int, dp_mem: Boolean) extends Module { 13 | val (cntVal, done) = Counter(true.B, n) 14 | val start = 23.U 15 | val sr = ShiftRegister.mem(cntVal + start, n, true.B, dp_mem, Some("simple_sr")) 16 | when(RegNext(done)) { 17 | assert(sr === start) 18 | stop() 19 | } 20 | } 21 | 22 | class ShiftRegisterMemSpec extends AnyPropSpec with PropertyUtils with ChiselSim { 23 | 24 | implicit val nonNegIntShrinker: Shrink[Int] = Shrink.shrinkIntegral[Int].suchThat(_ >= 0) 25 | 26 | property("ShiftRegister with dual-port SRAM should shift") { 27 | forAll(Gen.choose(0, 4)) { (shift: Int) => 28 | simulate { new ShiftMemTester(shift, true) }(RunUntilFinished(shift + 2)) 29 | } 30 | } 31 | 32 | property("ShiftRegister with single-port SRAM should shift") { 33 | forAll(Gen.choose(0, 6).suchThat(_ % 2 == 0)) { (shift: Int) => 34 | simulate { new ShiftMemTester(shift, false) }(RunUntilFinished(shift + 2)) 35 | } 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /lit/tests/Converter/Circuit.sc: -------------------------------------------------------------------------------- 1 | // RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s -check-prefix=FIRRTL 2 | // SPDX-License-Identifier: Apache-2.0 3 | 4 | import chisel3._ 5 | import chisel3.util.circt.IsX 6 | 7 | 8 | // FIRRTL-LABEL: circuit FooModule : 9 | // FIRRTL-NEXT: extmodule FooBlackbox : 10 | // FIRRTL-NEXT: output o : UInt<1> 11 | // FIRRTL-NEXT: defname = FooBlackbox 12 | class FooBlackbox extends BlackBox { 13 | val io = IO(new Bundle{ 14 | val o = Output(Bool()) 15 | }) 16 | } 17 | 18 | // FIRRTL: public module FooModule : 19 | // FIRRTL-NEXT: input clock : Clock 20 | // FIRRTL-NEXT: input reset : UInt<1> 21 | // FIRRTL-NEXT: output o : UInt<1> 22 | class FooModule extends Module { 23 | val o = IO(Output(Bool())) 24 | 25 | // FIRRTL: inst bb of FooBlackbox 26 | val bb = Module(new FooBlackbox) 27 | 28 | // FIRRTL-NEXT: connect o, intrinsic(circt_isX : UInt<1>, bb.o) 29 | o := IsX(bb.io.o) 30 | } 31 | 32 | println(lit.utility.panamaconverter.firrtlString(new FooModule)) 33 | -------------------------------------------------------------------------------- /lit/tests/Property/Bad.sc: -------------------------------------------------------------------------------- 1 | // RUN: not scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" %s -- 2>&1 | FileCheck %s 2 | 3 | import chisel3.properties._ 4 | 5 | class MyLit 6 | // CHECK: error: unsupported Property type Bad.MyLit 7 | val badPropLiteral = Property(new MyLit) 8 | 9 | // CHECK: error: unsupported Property type Bad.MyTpe 10 | class MyTpe 11 | val badPropType = Property[MyTpe]() 12 | -------------------------------------------------------------------------------- /lit/tests/lit.cfg.py: -------------------------------------------------------------------------------- 1 | import platform 2 | import lit.formats 3 | from lit.llvm import llvm_config 4 | from lit.llvm.subst import ToolSubst 5 | 6 | config.name = 'CHISEL' 7 | config.test_format = lit.formats.ShTest(True) 8 | config.suffixes = [".sc"] 9 | config.substitutions = [ 10 | ('%SCALAVERSION', config.scala_version), 11 | ('%RUNCLASSPATH', ':'.join(config.run_classpath)), 12 | ('%SCALAPLUGINJARS', ':'.join(config.scala_plugin_jars)), 13 | ('%JAVAHOME', config.java_home), 14 | ('%JAVALIBRARYPATH', ':'.join(config.java_library_path)) 15 | ] 16 | config.test_source_root = os.path.dirname(__file__) 17 | -------------------------------------------------------------------------------- /lit/tests/lit.site.cfg.py.in: -------------------------------------------------------------------------------- 1 | import sys 2 | config.scala_version = "@SCALA_VERSION@" 3 | config.run_classpath = "@RUN_CLASSPATH@".split(",") 4 | config.scala_plugin_jars = "@SCALA_PLUGIN_JARS@".split(",") 5 | config.java_home = "@JAVA_HOME@" 6 | config.java_library_path = "@JAVA_LIBRARY_PATH@".split(",") 7 | config.chisel_lit_dir = "@CHISEL_LIT_DIR@".split(",") 8 | config.test_exec_root = os.path.dirname(__file__) 9 | lit_config.load_config(config, "@CHISEL_LIT_DIR@/tests/lit.cfg.py") 10 | -------------------------------------------------------------------------------- /lit/utility/package.mill: -------------------------------------------------------------------------------- 1 | package build.lit.utility 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | 10 | object `package` extends RootModule { 11 | // https://github.com/com-lihaoyi/mill/issues/3693 12 | object cross extends Cross[LitUtility](v.scalaCrossVersions) 13 | } 14 | 15 | trait LitUtility 16 | extends ScalaModule 17 | with HasPanamaConverterModule 18 | with HasPanamaOMModule 19 | with CrossModuleBase 20 | with HasScalaPlugin 21 | with ScalafmtModule { 22 | override def scalacOptions = Task { Seq("-Ymacro-annotations") } 23 | override def circtPanamaBindingModule = panamaConverterModule.circtPanamaBindingModule 24 | 25 | def chiselModule = chisel(crossScalaVersion) 26 | def pluginModule = plugin.cross(crossScalaVersion) 27 | def millSourcePath = super.millSourcePath / os.up 28 | def panamaConverterModule = panamaconverter.cross(crossScalaVersion) 29 | def panamaOMModule = panamaom.cross(crossScalaVersion) 30 | 31 | override def moduleDeps = super.moduleDeps ++ Some(chiselModule) 32 | } 33 | -------------------------------------------------------------------------------- /macros/package.mill: -------------------------------------------------------------------------------- 1 | package build.macros 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | 10 | object `package` extends RootModule { 11 | // https://github.com/com-lihaoyi/mill/issues/3693 12 | object cross extends Cross[Macros](v.scalaCrossVersions) 13 | } 14 | 15 | trait Macros extends CrossSbtModule with HasScala2MacroAnno with HasCommonOptions with ScalafmtModule { 16 | def millSourcePath = super.millSourcePath / os.up 17 | 18 | override def ivyDeps = 19 | if (!v.isScala3(crossScalaVersion)) { 20 | super.ivyDeps() ++ Seq(v.scalaReflect(crossScalaVersion)) 21 | } else { 22 | super.ivyDeps() 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /nix/sources.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "1.1.2", 3 | "assets": { 4 | "aarch64-darwin": { 5 | "asset": "scala-cli-aarch64-apple-darwin.gz", 6 | "sha256": "1m5ac0pkp68k446xd8p21hc8caaahpyd3vm5pn1i1cc176f6fm8b" 7 | }, 8 | "aarch64-linux": { 9 | "asset": "scala-cli-aarch64-pc-linux.gz", 10 | "sha256": "1aqw8xmim7rmh8h98h10dlhm0hzl9bs89a51mbd3d99yxa5dq4z0" 11 | }, 12 | "x86_64-darwin": { 13 | "asset": "scala-cli-x86_64-apple-darwin.gz", 14 | "sha256": "06473l04z3nfadi72klk3aw4i39qkyzl3qp7kb1ysn5wx58ci51w" 15 | }, 16 | "x86_64-linux": { 17 | "asset": "scala-cli-x86_64-pc-linux.gz", 18 | "sha256": "1khdzv0s9l6wcb47hnv96prvzgzwcw0db34j6525bdgakj62fhf3" 19 | } 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /overlay.nix: -------------------------------------------------------------------------------- 1 | final: prev: 2 | { 3 | mill = (prev.mill.overrideAttrs (oldAttrs: rec { 4 | version = "0.12.5"; 5 | src = prev.fetchurl { 6 | url = "https://github.com/com-lihaoyi/mill/releases/download/${version}/${version}-assembly"; 7 | hash = "sha256-DHslQS/uzwbZVdATQY3pqQgM51W+26x2AckQnDPVoFc="; 8 | }; 9 | })).override { 10 | jre = final.openjdk21; 11 | }; 12 | # This script can be used for override circt for debuging. 13 | # circt = prev.circt.overrideAttrs (old: rec { 14 | # version = "nightly"; 15 | # src = final.fetchFromGitHub { 16 | # owner = "llvm"; 17 | # repo = "circt"; 18 | # rev = "57372957e8365b34ca469299b8c864d830e836a1"; 19 | # sha256 = "sha256-gExhWkhVhIpTKRCfF26pZnrcrf//ASQJDxEKbYc570s="; 20 | # fetchSubmodules = true; 21 | # }; 22 | # preConfigure = '' 23 | # find ./test -name '*.mlir' -exec sed -i 's|/usr/bin/env|${final.coreutils}/bin/env|g' {} \; 24 | # substituteInPlace cmake/modules/GenVersionFile.cmake --replace "unknown git version" "nightly" 25 | # ''; 26 | # }); 27 | circt-all = final.symlinkJoin { 28 | name = "circt-all"; 29 | paths = with final; [ 30 | circt 31 | circt.dev 32 | circt.lib 33 | circt.llvm 34 | circt.llvm.dev 35 | circt.llvm.lib 36 | ]; 37 | }; 38 | } 39 | -------------------------------------------------------------------------------- /panamaconverter/package.mill: -------------------------------------------------------------------------------- 1 | package build.panamaconverter 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | import build_.release 10 | 11 | object `package` extends RootModule { 12 | // https://github.com/com-lihaoyi/mill/issues/3693 13 | object cross extends Cross[PanamaConverter](v.scalaCrossVersions) 14 | } 15 | 16 | trait PanamaConverter 17 | extends ScalaModule 18 | with HasPanamaOMModule 19 | with CrossModuleBase 20 | with HasScalaPlugin 21 | with ScalafmtModule 22 | with release.ChiselPublishModule { 23 | def millSourcePath = super.millSourcePath / os.up 24 | 25 | def panamaOMModule = panamaom.cross(crossScalaVersion) 26 | def chiselModule = chisel(crossScalaVersion) 27 | def pluginModule = plugin.cross(crossScalaVersion) 28 | 29 | // use to be propagated to downstream modules 30 | override def moduleDeps = super.moduleDeps ++ Some(unipublish) 31 | 32 | override def compileClasspath = Task { super.compileClasspath() ++ unipublish.localClasspath() } 33 | } 34 | -------------------------------------------------------------------------------- /panamalib/package.mill: -------------------------------------------------------------------------------- 1 | package build.panamalib 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | import build_.release 10 | 11 | object `package` extends RootModule { 12 | // https://github.com/com-lihaoyi/mill/issues/3693 13 | object cross extends Cross[PanamaLib](v.scalaCrossVersions) 14 | } 15 | 16 | // The Scala API for PanamaBinding, API here is experimentally public to all developers 17 | trait PanamaLib 18 | extends ScalaModule 19 | with HasCIRCTPanamaBindingModule 20 | with CrossModuleBase 21 | with ScalafmtModule 22 | with release.ChiselPublishModule { 23 | def millSourcePath = super.millSourcePath / os.up 24 | 25 | def circtPanamaBindingModule = circtpanamabinding 26 | } 27 | -------------------------------------------------------------------------------- /panamaom/package.mill: -------------------------------------------------------------------------------- 1 | package build.panamaom 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | import build_.release 10 | 11 | object `package` extends RootModule { 12 | // https://github.com/com-lihaoyi/mill/issues/3693 13 | object cross extends Cross[PanamaOM](v.scalaCrossVersions) 14 | } 15 | 16 | trait PanamaOM 17 | extends ScalaModule 18 | with HasPanamaLibModule 19 | with CrossModuleBase 20 | with ScalafmtModule 21 | with release.ChiselPublishModule { 22 | def millSourcePath = super.millSourcePath / os.up 23 | 24 | def panamaLibModule = panamalib.cross(crossScalaVersion) 25 | } 26 | -------------------------------------------------------------------------------- /plugin/src/main/resources/plugin.properties: -------------------------------------------------------------------------------- 1 | pluginClass=chisel3.internal.plugin.ChiselComponent -------------------------------------------------------------------------------- /plugin/src/main/resources/scalac-plugin.xml: -------------------------------------------------------------------------------- 1 | 2 | chiselplugin 3 | chisel3.internal.plugin.ChiselPlugin 4 | 5 | -------------------------------------------------------------------------------- /plugin/src/main/scala-2/chisel3/internal/sourceinfo/SourceInfoFileResolver.scala: -------------------------------------------------------------------------------- 1 | ../../../../../../../core/src/main/scala-2/chisel3/internal/SourceInfoFileResolver.scala -------------------------------------------------------------------------------- /root-doc.txt: -------------------------------------------------------------------------------- 1 | This is the documentation for Chisel. 2 | 3 | == Package structure == 4 | 5 | The [[chisel3]] package presents the public API of Chisel. 6 | It contains the concrete core types [[chisel3.UInt `UInt`]], [[chisel3.SInt `SInt`]], [[chisel3.Bool `Bool`]], [[chisel3.Clock `Clock`]], and [[chisel3.Reg `Reg`]], 7 | the abstract types [[chisel3.Bits `Bits`]], [[chisel3.Aggregate `Aggregate`]], and [[chisel3.Data `Data`]], 8 | and the aggregate types [[chisel3.Bundle `Bundle`]] and [[chisel3.Vec `Vec`]]. 9 | 10 | The [[Chisel]] package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3. 11 | 12 | Utility objects and methods are found in the [[chisel3.util `util`]] package. 13 | 14 | The [[chisel3.testers `testers`]] package defines the basic interface for chisel testers. 15 | -------------------------------------------------------------------------------- /src/main/resources/chisel3/Makefile: -------------------------------------------------------------------------------- 1 | # Chisel parallel make template. 2 | 3 | HFILES = @HFILES@ 4 | ONCEONLY = @ONCEONLY@ 5 | UNOPTIMIZED = @UNOPTIMIZED@ 6 | OPTIMIZED = @OPTIMIZED@ 7 | 8 | EXEC = @EXEC@ 9 | OPTIM0 = @OPTIM0@ 10 | OPTIM1 = @OPTIM1@ 11 | OPTIM2 = @OPTIM2@ 12 | CPPFLAGS = @CPPFLAGS@ 13 | CXXFLAGS = @CXXFLAGS@ 14 | LDFLAGS = @LDFLAGS@ 15 | CXX = @CXX@ 16 | 17 | default: $(EXEC) 18 | 19 | clean: 20 | $(RM) $(EXEC) $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) 21 | 22 | $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED): $(HFILES) 23 | 24 | $(EXEC): $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) Makefile 25 | $(CXX) -o $@ $(filter-out Makefile,$^) 26 | 27 | $(ONCEONLY): %.o: %.cpp 28 | $(CXX) -c -o $@ $(OPTIM0) $(CPPFLAGS) $(CXXFLAGS) $< 29 | 30 | $(UNOPTIMIZED): %.o: %.cpp 31 | $(CXX) -c -o $@ $(OPTIM1) $(CPPFLAGS) $(CXXFLAGS) $< 32 | 33 | $(OPTIMIZED): %.o: %.cpp 34 | $(CXX) -c -o $@ $(OPTIM2) $(CPPFLAGS) $(CXXFLAGS) $< 35 | -------------------------------------------------------------------------------- /src/main/scala-2/chisel3/util/CatIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package chisel3.util 3 | 4 | import chisel3._ 5 | 6 | import chisel3.experimental.SourceInfo 7 | import chisel3.internal.sourceinfo.SourceInfoTransform 8 | 9 | import scala.language.experimental.macros 10 | 11 | private[chisel3] trait CatIntf { self: Cat.type => 12 | 13 | /** Concatenates the argument data elements, in argument order, together. The first argument 14 | * forms the most significant bits, while the last argument forms the least significant bits. 15 | */ 16 | def apply[T <: Bits](a: T, r: T*): UInt = macro SourceInfoTransform.arArg 17 | 18 | /** @group SourceInfoTransformMacro */ 19 | def do_apply[T <: Bits](a: T, r: T*)(implicit sourceInfo: SourceInfo): UInt = _applyImpl(a, r: _*) 20 | 21 | /** Concatenates the data elements of the input sequence, in reverse sequence order, together. 22 | * The first element of the sequence forms the most significant bits, while the last element 23 | * in the sequence forms the least significant bits. 24 | * 25 | * Equivalent to r(0) ## r(1) ## ... ## r(n-1). 26 | * @note This returns a `0.U` if applied to a zero-element `Vec`. 27 | */ 28 | def apply[T <: Bits](r: Seq[T]): UInt = macro SourceInfoTransform.rArg 29 | 30 | /** @group SourceInfoTransformMacro */ 31 | def do_apply[T <: Bits](r: Seq[T])(implicit sourceInfo: SourceInfo): UInt = _applyImpl(r) 32 | } 33 | -------------------------------------------------------------------------------- /src/main/scala-2/chisel3/util/util.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | /** The util package provides extensions to core chisel for common hardware components and utility 6 | * functions 7 | */ 8 | package object util { 9 | 10 | /** Synonyms, moved from main package object - maintain scope. */ 11 | type ValidIO[+T <: Data] = chisel3.util.Valid[T] 12 | val ValidIO = chisel3.util.Valid 13 | val DecoupledIO = chisel3.util.Decoupled 14 | } 15 | -------------------------------------------------------------------------------- /src/main/scala-3/chisel3/choice/ModuleChoiceIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.choice 4 | 5 | import chisel3.{Data, FixedIOBaseModule} 6 | import chisel3.experimental.SourceInfo 7 | 8 | private[chisel3] trait ModuleChoice$Intf { self: ModuleChoice.type => 9 | 10 | /** A wrapper method for Module instantiation based on option choices. 11 | * (necessary to help Chisel track internal state). 12 | * @see [[chisel3.choice.Group]] on how to declare the options for the alternatives. 13 | * 14 | * Example: 15 | * ``` 16 | * val module = ModuleChoice(new DefaultModule)(Seq( 17 | * Platform.FPGA -> new FPGATarget, 18 | * Platform.ASIC -> new ASICTarget 19 | * )) 20 | * ``` 21 | * 22 | * @param default the Module to instantiate if no module is specified 23 | * @param choices the mapping from cases to module generators 24 | * 25 | * @return the input module `m` with Chisel metadata properly set 26 | * 27 | * @throws java.lang.IllegalArgumentException if the cases do not belong to the same option. 28 | */ 29 | def apply[T <: Data]( 30 | default: => FixedIOBaseModule[T], 31 | choices: Seq[(Case, () => FixedIOBaseModule[T])] 32 | )( 33 | using SourceInfo 34 | ): T = _applyImpl(default, choices) 35 | } 36 | -------------------------------------------------------------------------------- /src/main/scala-3/chisel3/util/BitPatIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util 4 | 5 | import chisel3._ 6 | import chisel3.experimental.SourceInfo 7 | import scala.collection.mutable 8 | import scala.util.hashing.MurmurHash3 9 | 10 | private[chisel3] trait BitPat$Intf { self: BitPat.type => 11 | implicit class fromUIntToBitPatComparable(x: UInt) { 12 | def ===(that: BitPat)(using SourceInfo): Bool = that === x 13 | def =/=(that: BitPat)(using SourceInfo): Bool = that =/= x 14 | } 15 | } 16 | 17 | private[chisel3] trait BitPatIntf extends SourceInfoDoc { self: BitPat => 18 | import chisel3.util.experimental.BitSet 19 | def terms = Set(this) 20 | 21 | def apply(x: Int)(using SourceInfo): BitPat = _applyImpl(x) 22 | def apply(x: Int, y: Int)(using SourceInfo): BitPat = _applyImpl(x, y) 23 | def ===(that: UInt)(using SourceInfo): Bool = _impl_===(that) 24 | def =/=(that: UInt)(using SourceInfo): Bool = _impl_=/=(that) 25 | def ##(that: BitPat)(using SourceInfo): BitPat = _impl_##(that) 26 | } 27 | -------------------------------------------------------------------------------- /src/main/scala-3/chisel3/util/CatIntf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package chisel3.util 3 | 4 | import chisel3._ 5 | import chisel3.experimental.SourceInfo 6 | 7 | private[chisel3] trait CatIntf { self: Cat.type => 8 | 9 | /** Concatenates the argument data elements, in argument order, together. The first argument 10 | * forms the most significant bits, while the last argument forms the least significant bits. 11 | */ 12 | def apply[T <: Bits](a: T, r: T*)(using SourceInfo): UInt = _applyImpl(a, r: _*) 13 | 14 | /** Concatenates the data elements of the input sequence, in reverse sequence order, together. 15 | * The first element of the sequence forms the most significant bits, while the last element 16 | * in the sequence forms the least significant bits. 17 | * 18 | * Equivalent to r(0) ## r(1) ## ... ## r(n-1). 19 | * @note This returns a `0.U` if applied to a zero-element `Vec`. 20 | */ 21 | def apply[T <: Bits](r: Seq[T])(using SourceInfo): UInt = _applyImpl(r) 22 | } 23 | -------------------------------------------------------------------------------- /src/main/scala-3/chisel3/util/Switch.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | /** Conditional blocks. 4 | */ 5 | 6 | package chisel3.util 7 | 8 | import chisel3._ 9 | 10 | object switch { 11 | def apply[T <: Element](cond: T)(x: => Any): Unit = println("Not supported yet") 12 | } 13 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/simulator/ControlAPI.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.simulator 4 | 5 | trait ControlAPI { 6 | 7 | /** Enable waveform dumping 8 | * 9 | * This control function will enable waveforms from the moment it is applied. 10 | * A simulator must be compiled with waveform dumping support for this to 11 | * have an effect. 12 | * 13 | * Example usage: 14 | * {{{ 15 | * enableWaves() 16 | * }}} 17 | */ 18 | def enableWaves(): Unit = { 19 | AnySimulatedModule.current.controller.setTraceEnabled(true) 20 | } 21 | 22 | /** Enable waveform dumping 23 | * 24 | * This control function will disable waveforms from the moment it is 25 | * applied. A simulator must be compiled with waveform dumping support for 26 | * this to have an effect. 27 | * 28 | * Example usage: 29 | * {{{ 30 | * disableWaves() 31 | * }}} 32 | */ 33 | def disableWaves(): Unit = { 34 | AnySimulatedModule.current.controller.setTraceEnabled(false) 35 | } 36 | 37 | } 38 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/simulator/EphemeralSimulator.scala: -------------------------------------------------------------------------------- 1 | package chisel3.simulator 2 | 3 | import svsim._ 4 | import chisel3.RawModule 5 | import chisel3.testing.HasTestingDirectory 6 | import java.nio.file.Files 7 | import java.io.File 8 | 9 | /** Provides a simple API for "ephemeral" invocations (where you don't care about the artifacts after the invocation completes) to 10 | * simulate Chisel modules. To keep things really simple, `EphemeralSimulator` simulations can only be controlled using the 11 | * peek/poke API, which provides enough control while hiding some of the lower-level svsim complexity. 12 | * @example 13 | * {{{ 14 | * import chisel3.simulator.EphemeralSimulator._ 15 | * ... 16 | * simulate(new MyChiselModule()) { module => ... } 17 | * }}} 18 | */ 19 | object EphemeralSimulator extends PeekPokeAPI { 20 | 21 | private val chiselSim = new ChiselSim {} 22 | 23 | def simulate[T <: RawModule]( 24 | module: => T, 25 | layerControl: LayerControl.Type = LayerControl.EnableAll 26 | )(body: (T) => Unit): Unit = { 27 | implicit val temporary: HasTestingDirectory = HasTestingDirectory.temporary(deleteOnExit = true) 28 | chiselSim.simulateRaw( 29 | module, 30 | settings = Settings.defaultRaw[T].copy(verilogLayers = layerControl) 31 | )(body) 32 | } 33 | 34 | } 35 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/simulator/OptionsModifications.scala: -------------------------------------------------------------------------------- 1 | package chisel3.simulator 2 | 3 | /** Changes that ChiselSim should make to Chisel command line options 4 | * 5 | * This follows a type class pattern with a low-priority default of identity. 6 | */ 7 | trait ChiselOptionsModifications extends (Array[String] => Array[String]) 8 | 9 | object ChiselOptionsModifications { 10 | 11 | /** Low-priority default of identity (no opotions modifications) */ 12 | implicit def unmodified: ChiselOptionsModifications = identity(_) 13 | 14 | } 15 | 16 | /** Changes that ChiselSim should make to `firtool` command line options 17 | * 18 | * This follows a type class pattern with a low-priority default of identity. 19 | */ 20 | trait FirtoolOptionsModifications extends (Array[String] => Array[String]) 21 | 22 | object FirtoolOptionsModifications { 23 | 24 | /** Low-priority default of identity (no opotions modifications) */ 25 | implicit def unmodified: FirtoolOptionsModifications = identity(_) 26 | 27 | } 28 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/simulator/scalatest/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.simulator 4 | 5 | import chisel3.testing.scalatest.{HasConfigMap, TestingDirectory} 6 | import org.scalatest.TestSuite 7 | 8 | package object scalatest { 9 | 10 | /** A trait that provides ChiselSim APIs and integration with Scalatest. 11 | * 12 | * Example usage: 13 | * {{{ 14 | * import chisel3.simulator.scalatestChiselSim 15 | * import org.scalatest.funspec.AnyFunSpec 16 | * import org.scalatest.matches.should.Matchers 17 | * 18 | * class Foo extends AnyFunSpec with Matchers with ChiselSim { 19 | * /** This has access to all ChiselSim APIs like `simulate`, `peek`, and `poke`. */ 20 | * } 21 | * }}} 22 | * 23 | * @see [[chisel3.simulator.ChiselSim]] 24 | */ 25 | trait ChiselSim 26 | extends HasCliOptions 27 | with HasConfigMap 28 | with Cli.ChiselOpts 29 | with Cli.EmitVcd 30 | with Cli.FirtoolOpts 31 | with TestingDirectory 32 | with chisel3.simulator.ChiselSim { 33 | self: TestSuite => 34 | } 35 | 36 | } 37 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/simulator/stimulus/Stimulus.scala: -------------------------------------------------------------------------------- 1 | package chisel3.simulator.stimulus 2 | 3 | /** Types and utility functions related to the [[stimulus]] package. */ 4 | object Stimulus { 5 | 6 | /** The type of stimulus. This takes a type and applies some stimulus to it. Nothing is returned. */ 7 | type Type[A] = (A) => Unit 8 | 9 | } 10 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.stage.phases 4 | 5 | import chisel3.stage.ChiselCircuitAnnotation 6 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 7 | import firrtl.options.{Dependency, OutputAnnotationFileAnnotation, Phase} 8 | 9 | /** Adds an [[firrtl.options.OutputAnnotationFileAnnotation]] if one does not exist. This replicates old behavior where 10 | * an output annotation file was always written. 11 | */ 12 | class AddImplicitOutputAnnotationFile extends Phase { 13 | 14 | override def prerequisites = Seq(Dependency[Elaborate]) 15 | override def optionalPrerequisites = Seq.empty 16 | override def optionalPrerequisiteOf = Seq.empty 17 | override def invalidates(a: Phase) = false 18 | 19 | def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.collectFirst { 20 | case _: OutputAnnotationFileAnnotation => annotations 21 | }.getOrElse { 22 | 23 | // We are assuming these annotations are in sync 24 | val x: Option[AnnotationSeq] = annotations.collectFirst { case a: ChiselCircuitAnnotation => 25 | OutputAnnotationFileAnnotation(a.elaboratedCircuit.name) +: annotations 26 | } 27 | 28 | x.getOrElse(annotations) 29 | } 30 | 31 | } 32 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.stage.phases 4 | 5 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 6 | import firrtl.options.{Dependency, Phase} 7 | 8 | import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation} 9 | 10 | /** Add a output file for a Chisel circuit, derived from the top module in the circuit, if no 11 | * [[ChiselOutputFileAnnotation]] already exists. 12 | */ 13 | class AddImplicitOutputFile extends Phase { 14 | 15 | override def prerequisites = Seq(Dependency[Elaborate]) 16 | override def optionalPrerequisites = Seq.empty 17 | override def optionalPrerequisiteOf = Seq.empty 18 | override def invalidates(a: Phase) = false 19 | 20 | def transform(annotations: AnnotationSeq): AnnotationSeq = 21 | annotations.collectFirst { case _: ChiselOutputFileAnnotation => annotations }.getOrElse { 22 | 23 | val x: Option[AnnotationSeq] = annotations.collectFirst { case a: ChiselCircuitAnnotation => 24 | ChiselOutputFileAnnotation(a.elaboratedCircuit.name) +: annotations 25 | } 26 | 27 | x.getOrElse(annotations) 28 | } 29 | 30 | } 31 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.stage.phases 4 | 5 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 6 | import firrtl.options.{Dependency, Phase} 7 | import firrtl.options.Viewer.view 8 | 9 | import chisel3.stage._ 10 | import chisel3.stage.CircuitSerializationAnnotation._ 11 | import chisel3.ChiselException 12 | 13 | /** Adds [[stage.CircuitSerializationAnnotation]]s based on [[ChiselOutputFileAnnotation]] 14 | */ 15 | class AddSerializationAnnotations extends Phase { 16 | 17 | override def prerequisites = Seq(Dependency[Elaborate], Dependency[AddImplicitOutputFile]) 18 | override def optionalPrerequisites = Seq.empty 19 | override def optionalPrerequisiteOf = Seq.empty 20 | override def invalidates(a: Phase) = false 21 | 22 | def transform(annotations: AnnotationSeq): AnnotationSeq = { 23 | val chiselOptions = view[ChiselOptions](annotations) 24 | val circuit = chiselOptions.elaboratedCircuit.getOrElse { 25 | throw new ChiselException( 26 | s"Unable to locate the elaborated circuit, did ${classOf[Elaborate].getName} run correctly" 27 | ) 28 | } 29 | val filename = chiselOptions.outputFile.getOrElse(circuit.name).stripSuffix(".fir") 30 | CircuitSerializationAnnotation(circuit, filename) +: annotations 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/testing/scalatest/package.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.testing 4 | 5 | import chisel3.testing.scalatest.TestingDirectory 6 | import org.scalatest.TestSuite 7 | 8 | package object scalatest { 9 | 10 | /** A trait that provides FileCheck APIs and integration with Scalatest. 11 | * 12 | * Example usage: 13 | * {{{ 14 | * import chisel3.testing.scalatest.FileCheck.scalatest 15 | * import org.scalatest.flatspec.AnyFlatSpec 16 | * import org.scalatest.matches.should.Matchers 17 | * 18 | * class Foo extends AnyFlatSpec with Matchers with FileCheck { 19 | * /** This has access to all FileCheck APIs like `fileCheck`. */ 20 | * } 21 | * }}} 22 | * 23 | * @see [[chisel3.testing.FileCheck]] 24 | */ 25 | trait FileCheck extends chisel3.testing.FileCheck with TestingDirectory { self: TestSuite => } 26 | 27 | } 28 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/AttributeAnnotation.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package chisel3.util 3 | 4 | import firrtl.AttributeAnnotation 5 | import firrtl.annotations.Named 6 | 7 | import chisel3.Data 8 | import chisel3.experimental.{annotate, requireIsAnnotatable} 9 | 10 | /** Helper Object for applying Attribute Annotations */ 11 | object addAttribute { 12 | 13 | /** Add attribute annotation to a chisel target. 14 | * 15 | * == Example == 16 | * {{{ 17 | * import chisel3._ 18 | * import chisel3.util.addAttribute 19 | * class AttributeExample extends Module { 20 | * val io = IO(new Bundle { 21 | * val input = Input(UInt(8.W)) 22 | * val output = Output(UInt(8.W)) 23 | * }) 24 | * 25 | * val reg = RegNext(io.input) 26 | * 27 | * addAttribute(reg, "synthesis translate_off") 28 | * 29 | * io.output := reg 30 | * } 31 | * 32 | * }}} 33 | * 34 | * @param target Chisel target. Must be Reg, Wire, or RawModule type. 35 | * @param annoString attribute string to add to target. 36 | */ 37 | def apply(target: Data, annoString: String): Unit = { 38 | annotate(target)(Seq(AttributeAnnotation(target.toNamed, annoString))) 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/Cat.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | package chisel3.util 3 | 4 | import chisel3._ 5 | 6 | import chisel3.experimental.SourceInfo 7 | 8 | /** Concatenates elements of the input, in order, together. 9 | * 10 | * @example {{{ 11 | * Cat("b101".U, "b11".U) // equivalent to "b101 11".U 12 | * Cat(myUIntWire0, myUIntWire1) 13 | * 14 | * Cat(Seq("b101".U, "b11".U)) // equivalent to "b101 11".U 15 | * Cat(mySeqOfBits) 16 | * }}} 17 | */ 18 | object Cat extends CatIntf { 19 | 20 | protected def _applyImpl[T <: Bits](a: T, r: T*)(implicit sourceInfo: SourceInfo): UInt = 21 | _applyImpl(a :: r.toList) 22 | 23 | protected def _applyImpl[T <: Bits](r: Seq[T])(implicit sourceInfo: SourceInfo): UInt = 24 | SeqUtils.asUInt(r.reverse) 25 | } 26 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/CircuitMath.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | /** Circuit-land math operations. 4 | */ 5 | 6 | package chisel3.util 7 | 8 | import chisel3._ 9 | 10 | /** Returns the base-2 integer logarithm of an UInt. 11 | * 12 | * @note The result is truncated, so e.g. Log2(13.U) === 3.U 13 | * 14 | * @example {{{ 15 | * Log2(8.U) // evaluates to 3.U 16 | * Log2(13.U) // evaluates to 3.U (truncation) 17 | * Log2(myUIntWire) 18 | * }}} 19 | */ 20 | object Log2 { 21 | 22 | /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt. 23 | */ 24 | def apply(x: Bits, width: Int): UInt = { 25 | if (width < 2) { 26 | 0.U 27 | } else if (width == 2) { 28 | x(1) 29 | } else if (width <= divideAndConquerThreshold) { 30 | Mux(x(width - 1), (width - 1).asUInt, apply(x, width - 1)) 31 | } else { 32 | val mid = 1 << (log2Ceil(width) - 1) 33 | val hi = x(width - 1, mid) 34 | val lo = x(mid - 1, 0) 35 | val useHi = hi.orR 36 | Cat(useHi, Mux(useHi, Log2(hi, width - mid), Log2(lo, mid))) 37 | } 38 | } 39 | 40 | def apply(x: Bits): UInt = apply(x, x.getWidth) 41 | 42 | private def divideAndConquerThreshold = 4 43 | } 44 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/Enum.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | /** Enum generators, allowing circuit constants to have more meaningful names. 4 | */ 5 | 6 | package chisel3.util 7 | 8 | import chisel3._ 9 | 10 | /** Defines a set of unique UInt constants 11 | * 12 | * Unpack with a list to specify an enumeration. Usually used with [[switch]] to describe a finite 13 | * state machine. 14 | * 15 | * @example {{{ 16 | * val state_on :: state_off :: Nil = Enum(2) 17 | * val current_state = WireDefault(state_off) 18 | * switch (current_state) { 19 | * is (state_on) { 20 | * ... 21 | * } 22 | * is (state_off) { 23 | * ... 24 | * } 25 | * } 26 | * }}} 27 | */ 28 | trait Enum { 29 | 30 | /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ 31 | protected def createValues(n: Int): Seq[UInt] = 32 | (0 until n).map(_.U((1.max(log2Ceil(n))).W)) 33 | 34 | /** Returns n unique UInt values 35 | * 36 | * @param n Number of unique UInt constants to enumerate 37 | * @return Enumerated constants 38 | */ 39 | def apply(n: Int): List[UInt] = createValues(n).toList 40 | } 41 | 42 | object Enum extends Enum 43 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/GrayCode.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util 4 | 5 | import chisel3._ 6 | 7 | object BinaryToGray { 8 | 9 | /** Turns a binary number into gray code. */ 10 | def apply(in: UInt): UInt = in ^ (in >> 1) 11 | } 12 | 13 | object GrayToBinary { 14 | 15 | /** Inverts the [[BinaryToGray]] operation. */ 16 | def apply(in: UInt, width: Int): UInt = apply(in(width - 1, 0)) 17 | 18 | /** Inverts the [[BinaryToGray]] operation. */ 19 | def apply(in: UInt): UInt = if (in.getWidth < 2) { in } 20 | else { 21 | val bits = in.getWidth - 2 to 0 by -1 22 | Cat(bits.scanLeft(in.head(1)) { case (prev, ii) => prev ^ in(ii) }) 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/ImplicitConversions.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util 4 | 5 | import chisel3._ 6 | 7 | import scala.language.implicitConversions 8 | 9 | /** Implicit conversions to automatically convert [[scala.Boolean]] and [[scala.Int]] to [[Bool]] 10 | * and [[UInt]] respectively 11 | */ 12 | object ImplicitConversions { 13 | // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and 14 | // UInt.asUInt. 15 | implicit def intToUInt(x: Int): UInt = chisel3.fromIntToLiteral(x).asUInt 16 | implicit def booleanToBool(x: Boolean): Bool = x.B 17 | } 18 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/circt/ClockGate.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.internal.Builder 7 | 8 | object ClockGate { 9 | 10 | /** Creates an intrinsic which enables and disables a clock safely, without 11 | * glitches, based on a boolean enable value. If the enable input is 1, the 12 | * output clock produced by the clock gate is identical to the input clock. 13 | * If the enable input is 0, the output clock is a constant zero. 14 | * 15 | * @example {{{ 16 | * gateClock := ClockGate(clock, enable) 17 | * }}} 18 | */ 19 | def apply(input: Clock, enable: Bool): Clock = { 20 | IntrinsicExpr("circt_clock_gate", Clock())(input, enable) 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/circt/IsX.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.internal.Builder 7 | 8 | object IsX { 9 | 10 | /** Creates an intrinsic which returns whether the input is a verilog 'x'. 11 | * 12 | * @example {{{ 13 | * b := IsX(a) 14 | * }}} 15 | */ 16 | def apply[T <: Data](gen: T): Bool = { 17 | IntrinsicExpr("circt_isX", Bool())(gen) 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/circt/PlusArgsTest.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.experimental.fromStringToStringParam 7 | import chisel3.internal.Builder 8 | 9 | object PlusArgsTest { 10 | 11 | /** Creates an intrinsic which calls \$test\$plusargs to test for the existence of the string str in the simulator command line. 12 | * 13 | * @example {{{ 14 | * b := PlusArgsTest("FOO") 15 | * }}} 16 | */ 17 | def apply(str: String): Bool = { 18 | IntrinsicExpr("circt_plusargs_test", Bool(), "FORMAT" -> str)() 19 | } 20 | 21 | @deprecated("use PlusArgsTest(str) instead") 22 | def apply[T <: Data](gen: T, str: String): Bool = apply(str) 23 | } 24 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/circt/SizeOf.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util.circt 4 | 5 | import chisel3._ 6 | object SizeOf { 7 | 8 | /** Creates an intrinsic which returns the size of a type. The returned size 9 | * is after width inference, so you can use this to compute expressions based 10 | * on the inferred size of types. 11 | * 12 | * @example {{{ 13 | * val a = Wire(UInt()) 14 | * a := 1 << (SizeOf(a) - 1) 15 | * }}} 16 | */ 17 | def apply[T <: Data](gen: T): Data = { 18 | IntrinsicExpr("circt_sizeof", UInt(32.W))(gen) 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/experimental/AutoBlackBox.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util.experimental 4 | 5 | import chisel3._ 6 | 7 | import scala.collection.immutable.SeqMap 8 | import chisel3.experimental.SourceInfo 9 | 10 | class AutoBlackBox( 11 | val verilog: String, 12 | val signalFilter: String => Boolean = _ => true 13 | )(implicit val __sourceInfo: SourceInfo) 14 | extends FixedIOExtModule( 15 | ioGenerator = new AutoBundleFromVerilog( 16 | SeqMap.from(SlangUtils.verilogModuleIO(SlangUtils.getVerilogAst(verilog))) 17 | )(signalFilter) 18 | ) { 19 | override def desiredName = SlangUtils.verilogModuleName(SlangUtils.getVerilogAst(verilog)) 20 | override def _sourceInfo = __sourceInfo 21 | } 22 | 23 | class AutoBundleFromVerilog( 24 | allElements: SeqMap[String, Data] 25 | )(signalFilter: String => Boolean) 26 | extends Record { 27 | val elements: SeqMap[String, Data] = allElements.filter(n => signalFilter(n._1)).map { case (k, v) => 28 | k -> chisel3.reflect.DataMirror.internal.chiselTypeClone(v) 29 | } 30 | def apply(data: String) = elements.getOrElse( 31 | data, 32 | throw new ChiselException( 33 | s"$data not found in Verilog IO: \n ${allElements.keys.mkString("\n")}" 34 | ) 35 | ) 36 | } 37 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/experimental/decode/DecodeTableAnnotation.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.util.experimental.decode 4 | 5 | import firrtl.annotations.{Annotation, ReferenceTarget, SingleTargetAnnotation} 6 | 7 | /** DecodeTableAnnotation used to store a decode result for a specific [[TruthTable]]. 8 | * This is useful for saving large [[TruthTable]] during a elaboration time. 9 | * 10 | * @note user should manage the correctness of [[minimizedTable]]. 11 | * 12 | * @param target output wire of a decoder. 13 | * @param truthTable input [[TruthTable]] encoded in a serialized [[TruthTable]]. 14 | * @param minimizedTable minimized [[truthTable]] encoded in a serialized [[TruthTable]]. 15 | */ 16 | case class DecodeTableAnnotation(target: ReferenceTarget, truthTable: String, minimizedTable: String) 17 | extends SingleTargetAnnotation[ReferenceTarget] { 18 | override def duplicate(n: ReferenceTarget): Annotation = this.copy(target = n) 19 | } 20 | -------------------------------------------------------------------------------- /src/main/scala/chisel3/util/experimental/getAnnotations.scala: -------------------------------------------------------------------------------- 1 | package chisel3.util.experimental 2 | 3 | import chisel3.internal.Builder 4 | import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq} 5 | 6 | object getAnnotations { 7 | 8 | /** Returns the global Annotations */ 9 | def apply(): AnnotationSeq = Builder.annotationSeq 10 | } 11 | -------------------------------------------------------------------------------- /src/main/scala/circt/Implicits.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package circt 4 | 5 | /** A collection of implicit classes to provide additional methods to existing types */ 6 | object Implicits { 7 | 8 | /** Helpers for working with Boolean */ 9 | implicit class BooleanImplicits(a: Boolean) { 10 | 11 | /** Construct an Option from a Boolean. */ 12 | def option[A](b: => A): Option[A] = 13 | if (a) 14 | Some(b) 15 | else 16 | None 17 | } 18 | 19 | } 20 | -------------------------------------------------------------------------------- /src/main/scala/circt/OutputDirAnnotation.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package circt 4 | 5 | import chisel3.experimental.{annotate, BaseModule} 6 | import firrtl.annotations.{ModuleTarget, SingleTargetAnnotation} 7 | import firrtl.FirrtlUserException 8 | 9 | /** Annotation to specify a module's output directory. 10 | */ 11 | case class OutputDirAnnotation(target: ModuleTarget, dirname: String) extends SingleTargetAnnotation[ModuleTarget] { 12 | override def duplicate(target: ModuleTarget): OutputDirAnnotation = 13 | OutputDirAnnotation(target, dirname) 14 | } 15 | 16 | /** Utilities for specifying the output directory for a public module. 17 | * @example {{{ 18 | * class Inner extends Module with Public { 19 | * val io = IO(new Bundle{}) 20 | * } 21 | * 22 | * class Top extends Module { 23 | * val inner = outputDir(Module(new Inner), "foo") 24 | * } 25 | * }}} 26 | */ 27 | object outputDir { 28 | def apply[T <: BaseModule](data: T, dirname: String): T = { 29 | annotate(data)(Seq(OutputDirAnnotation(data.toTarget, dirname))) 30 | data 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /src/test/resources/chisel3/AnalogBlackBox.v: -------------------------------------------------------------------------------- 1 | 2 | module AnalogReaderBlackBox( 3 | inout [31:0] bus, 4 | output [31:0] out 5 | ); 6 | assign bus = 32'dz; 7 | assign out = bus; 8 | endmodule 9 | 10 | module AnalogWriterBlackBox( 11 | inout [31:0] bus, 12 | input [31:0] in 13 | ); 14 | assign bus = in; 15 | endmodule 16 | 17 | module AnalogBlackBox #( 18 | parameter index=0 19 | ) ( 20 | inout [31:0] bus, 21 | input port_0_in_valid, 22 | input [31:0] port_0_in_bits, 23 | output [31:0] port_0_out 24 | ); 25 | assign port_0_out = bus; 26 | assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ; 27 | endmodule 28 | -------------------------------------------------------------------------------- /src/test/resources/chisel3/VerilogVendingMachine.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | // A simple Verilog FSM vending machine implementation 4 | module VerilogVendingMachine( 5 | input clock, 6 | input reset, 7 | input nickel, 8 | input dime, 9 | output dispense 10 | ); 11 | parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4; 12 | reg [2:0] state; 13 | 14 | assign dispense = (state == sOk) ? 1'd1 : 1'd0; 15 | 16 | always @(posedge clock) begin 17 | if (reset) begin 18 | state <= sIdle; 19 | end else begin 20 | case (state) 21 | sIdle: begin 22 | if (nickel) state <= s5; 23 | else if (dime) state <= s10; 24 | else state <= state; 25 | end 26 | s5: begin 27 | if (nickel) state <= s10; 28 | else if (dime) state <= s15; 29 | else state <= state; 30 | end 31 | s10: begin 32 | if (nickel) state <= s15; 33 | else if (dime) state <= sOk; 34 | else state <= state; 35 | end 36 | s15: begin 37 | if (nickel) state <= sOk; 38 | else if (dime) state <= sOk; 39 | else state <= state; 40 | end 41 | sOk: begin 42 | state <= sIdle; 43 | end 44 | default: begin 45 | assert(1'b0) else $error("illegal state"); 46 | end 47 | endcase 48 | end 49 | end 50 | endmodule 51 | -------------------------------------------------------------------------------- /src/test/resources/chisel3/simulator/Baz.sv: -------------------------------------------------------------------------------- 1 | module Baz(output a); 2 | assign a = 1'b1; 3 | endmodule 4 | -------------------------------------------------------------------------------- /src/test/resources/chisel3/simulator/Qux.sv: -------------------------------------------------------------------------------- 1 | module Qux(output a); 2 | assign a = 1'b1; 3 | endmodule 4 | -------------------------------------------------------------------------------- /src/test/resources/chisel3/sourceroot1/Foo: -------------------------------------------------------------------------------- 1 | This is a fake source file 2 | It is used to test errors with a caret 3 | I am the file in sourceroot1 4 | -------------------------------------------------------------------------------- /src/test/resources/chisel3/sourceroot2/Foo: -------------------------------------------------------------------------------- 1 | This is a fake source file 2 | It is used to test errors with a caret 3 | I am the file in sourceroot2 4 | -------------------------------------------------------------------------------- /src/test/scala-2/chisel3/SelectSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3 4 | 5 | import chisel3.aop.Select 6 | import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation} 7 | import org.scalatest.flatspec.AnyFlatSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | class SelectSpec extends AnyFlatSpec with Matchers { 11 | 12 | "Placeholders" should "be examined" in { 13 | class Foo extends RawModule { 14 | val placeholder = new Placeholder() 15 | val a = Wire(Bool()) 16 | val b = placeholder.append { 17 | Wire(Bool()) 18 | } 19 | } 20 | val design = ChiselGeneratorAnnotation(() => { 21 | new Foo 22 | }).elaborate(1).asInstanceOf[DesignAnnotation[Foo]].design 23 | Select.wires(design).size should be(2) 24 | } 25 | 26 | } 27 | -------------------------------------------------------------------------------- /src/test/scala-2/chisel3/stage/ChiselOptionsViewSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.stage 4 | 5 | import firrtl.options.Viewer.view 6 | import firrtl.RenameMap 7 | 8 | import chisel3.ElaboratedCircuit 9 | import chisel3.stage._ 10 | import chisel3.internal.firrtl.ir.Circuit 11 | import org.scalatest.flatspec.AnyFlatSpec 12 | import org.scalatest.matchers.should.Matchers 13 | 14 | class ChiselOptionsViewSpec extends AnyFlatSpec with Matchers { 15 | 16 | behavior.of(ChiselOptionsView.getClass.getName) 17 | 18 | it should "construct a view from an AnnotationSeq" in { 19 | val bar = Circuit("bar", Seq.empty, Seq.empty, RenameMap("bar"), Seq.empty, Seq.empty, Seq.empty) 20 | val circuit = ElaboratedCircuit(bar, Seq.empty) 21 | val annotations = Seq( 22 | PrintFullStackTraceAnnotation, 23 | ChiselOutputFileAnnotation("foo"), 24 | ChiselCircuitAnnotation(circuit) 25 | ) 26 | val out = view[ChiselOptions](annotations) 27 | 28 | info("printFullStackTrace was set to true") 29 | out.printFullStackTrace should be(true) 30 | 31 | info("outputFile was set to 'foo'") 32 | out.outputFile should be(Some("foo")) 33 | 34 | info("elaboratedCircuit was set to circuit 'circuit'") 35 | out.elaboratedCircuit should be(Some(circuit)) 36 | 37 | } 38 | 39 | } 40 | -------------------------------------------------------------------------------- /src/test/scala-2/chisel3/testers/TestUtils.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chisel3.testers 4 | 5 | import chisel3.experimental.SourceInfo 6 | import chisel3.internal.{Builder, Warning, WarningID} 7 | 8 | object TestUtils { 9 | 10 | /** Helper for checking warnings, not really valid in normal Chisel */ 11 | def warn(id: Int, msg: String)(implicit sourceInfo: SourceInfo): Unit = Builder.warning(Warning(WarningID(1), msg)) 12 | 13 | } 14 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/AdderTree.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import org.scalatest.propspec.AnyPropSpec 9 | 10 | class AdderTree[T <: Bits with Num[T]](genType: T, vecSize: Int) extends Module { 11 | val io = IO(new Bundle { 12 | val numIn = Input(Vec(vecSize, genType)) 13 | val numOut = Output(genType) 14 | }) 15 | io.numOut := io.numIn.reduceTree((a: T, b: T) => (a + b)) 16 | } 17 | 18 | class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends Module { 19 | val genType = UInt(bitWidth.W) 20 | val dut = Module(new AdderTree(genType, numsToAdd.size)) 21 | dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W))) 22 | val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W) 23 | assert(sumCorrect) 24 | stop() 25 | } 26 | 27 | class AdderTreeSpec extends AnyPropSpec with PropertyUtils with ChiselSim { 28 | property("All numbers should be added correctly by an Adder Tree") { 29 | forAll(safeUIntN(20)) { 30 | case (w: Int, v: List[Int]) => { 31 | whenever(v.size > 0 && w > 0) { 32 | simulate { new AdderTreeTester(w, v.map(x => math.abs(x) % (1 << w)).toList) }(RunUntilFinished(2)) 33 | } 34 | } 35 | } 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/BitwiseOps.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import org.scalatest.propspec.AnyPropSpec 9 | 10 | class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends Module { 11 | val mask = (1 << w) - 1 12 | val a = _a.asUInt(w.W) 13 | val b = _b.asUInt(w.W) 14 | assert(~a === (mask & ~_a).asUInt) 15 | assert((a & b) === (_a & _b).asUInt) 16 | assert((a | b) === (_a | _b).asUInt) 17 | assert((a ^ b) === (_a ^ _b).asUInt) 18 | assert((a.orR) === (_a != 0).asBool) 19 | assert((a.andR) === (s"%${w}s".format(BigInt(_a).toString(2)).foldLeft(true)(_ && _ == '1')).asBool) 20 | stop() 21 | } 22 | 23 | class BitwiseOpsSpec extends AnyPropSpec with PropertyUtils with ChiselSim { 24 | property("All bit-wise ops should return the correct result") { 25 | forAll(safeUIntPair) { case (w: Int, a: Int, b: Int) => 26 | simulate { new BitwiseOpsTester(w, a, b) }(RunUntilFinished(2)) 27 | } 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/BoolSpec.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import org.scalatest.flatspec.AnyFlatSpec 9 | 10 | class BoolSpec extends AnyFlatSpec with ChiselSim { 11 | 12 | "implication" should "work in RTL" in { 13 | 14 | val truthTable = Seq( 15 | ((0, 0), 1), 16 | ((0, 1), 1), 17 | ((1, 0), 0), 18 | ((1, 1), 1) 19 | ) 20 | 21 | simulateRaw( 22 | new RawModule { 23 | val a, b = IO(Input(Bool())) 24 | val c = IO(Output(Bool())) 25 | c :<= a.implies(b) 26 | } 27 | ) { dut => 28 | truthTable.foreach { case ((a, b), c) => 29 | info(s"$a -> $b == $c") 30 | dut.a.poke(a) 31 | dut.b.poke(b) 32 | dut.c.expect(c) 33 | } 34 | } 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/CustomBundle.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.experimental.requireIsChiselType 7 | import chisel3.reflect.DataMirror 8 | import scala.collection.immutable.ListMap 9 | 10 | // An example of how Record might be extended 11 | // In this case, CustomBundle is a Record constructed from a Tuple of (String, Data) 12 | // it is a possible implementation of a programmatic "Bundle" 13 | // (and can by connected to MyBundle below) 14 | final class CustomBundle(elts: (String, Data)*) extends Record { 15 | val elements = ListMap(elts.map { case (field, elt) => 16 | requireIsChiselType(elt) 17 | field -> DataMirror.internal.chiselTypeClone(elt) 18 | }: _*) 19 | def apply(elt: String): Data = elements(elt) 20 | } 21 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/EnumSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import chisel3.util.Enum 9 | import org.scalatest.flatspec.AnyFlatSpec 10 | import org.scalatest.matchers.should.Matchers 11 | 12 | class EnumSpec extends AnyFlatSpec with ChiselSim { 13 | 14 | "1-entry Enums" should "work" in { 15 | simulate(new Module { 16 | val onlyState :: Nil = Enum(1) 17 | val wire = WireDefault(onlyState) 18 | chisel3.assert(wire === onlyState) 19 | stop() 20 | })(RunUntilFinished(3)) 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/IntegerMathSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import org.scalatest.propspec.AnyPropSpec 9 | 10 | class IntegerMathTester extends Module { 11 | 12 | // TODO: Add more operators 13 | 14 | /* absolute values tests */ 15 | 16 | val uint = 3.U(4.W) 17 | val sint = (-3).S 18 | val sintpos = 3.S 19 | val wrongSIntPos = 4.S 20 | 21 | assert(uint.abs === uint) 22 | assert(sint.abs === sintpos) 23 | assert(sintpos.abs === sintpos) 24 | 25 | assert(sint.abs =/= wrongSIntPos) 26 | 27 | stop() 28 | } 29 | 30 | class IntegerMathSpec extends AnyPropSpec with ChiselSim { 31 | property("All integer ops should return the correct result") { 32 | simulate { new IntegerMathTester }(RunUntilFinished(3)) 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/LiteralToTargetSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import circt.stage.ChiselStage 7 | import org.scalatest.freespec.AnyFreeSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | class LiteralToTargetSpec extends AnyFreeSpec with Matchers { 11 | 12 | "Literal Data should fail to be converted to ReferenceTarget" in { 13 | 14 | (the[ChiselException] thrownBy { 15 | 16 | class Bar extends RawModule { 17 | val a = 1.U 18 | } 19 | 20 | class Foo extends RawModule { 21 | val bar = Module(new Bar) 22 | bar.a.toTarget 23 | } 24 | 25 | ChiselStage.emitCHIRRTL(new Foo) 26 | } should have).message("Illegal component name: UInt<1>(0h1) (note: literals are illegal)") 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/MulLookup.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import org.scalatest.propspec.AnyPropSpec 9 | 10 | class MulLookup(val w: Int) extends Module { 11 | val io = IO(new Bundle { 12 | val x = Input(UInt(w.W)) 13 | val y = Input(UInt(w.W)) 14 | val z = Output(UInt((2 * w).W)) 15 | }) 16 | val tbl = VecInit( 17 | for { 18 | i <- 0 until 1 << w 19 | j <- 0 until 1 << w 20 | } yield (i * j).asUInt((2 * w).W) 21 | ) 22 | io.z := tbl(((io.x << w) | io.y)) 23 | } 24 | 25 | class MulLookupTester(w: Int, x: Int, y: Int) extends Module { 26 | val dut = Module(new MulLookup(w)) 27 | dut.io.x := x.asUInt 28 | dut.io.y := y.asUInt 29 | assert(dut.io.z === (x * y).asUInt) 30 | stop() 31 | } 32 | 33 | class MulLookupSpec extends AnyPropSpec with PropertyUtils with ChiselSim { 34 | 35 | property("Mul lookup table should return the correct result") { 36 | forAll(smallPosInts, smallPosInts) { (x: Int, y: Int) => 37 | simulate { new MulLookupTester(3, x, y) }(RunUntilFinished(3)) 38 | } 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/Padding.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import circt.stage.ChiselStage 7 | import org.scalatest.matchers.should.Matchers 8 | import org.scalatest.propspec.AnyPropSpec 9 | 10 | class Padder extends Module { 11 | val io = IO(new Bundle { 12 | val a = Input(UInt(4.W)) 13 | val asp = Output(SInt(8.W)) 14 | val aup = Output(UInt(8.W)) 15 | }) 16 | io.asp := io.a.asSInt 17 | io.aup := io.a.asUInt 18 | } 19 | 20 | /* 21 | class PadsTester(c: Pads) extends Tester(c) { 22 | def pads(x: BigInt, s: Int, w: Int) = { 23 | val sign = (x & (1 << (s-1))) 24 | val wmask = (1 << w) - 1 25 | val bmask = (1 << s) - 1 26 | if (sign == 0) x else ((~bmask | x) & wmask) 27 | } 28 | for (t <- 0 until 16) { 29 | val test_a = rnd.nextInt(1 << 4) 30 | poke(c.io.a, test_a) 31 | step(1) 32 | expect(c.io.asp, pads(test_a, 4, 8)) 33 | expect(c.io.aup, test_a) 34 | } 35 | } 36 | */ 37 | 38 | class PadderSpec extends AnyPropSpec with Matchers { 39 | 40 | property("Padder should elaborate") { 41 | ChiselStage.emitCHIRRTL { new Padder } 42 | } 43 | 44 | ignore("PadderTester should return the correct result") {} 45 | } 46 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/PopCount.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import chisel3.util.PopCount 9 | import org.scalatest.propspec.AnyPropSpec 10 | import org.scalatest.matchers.should.Matchers 11 | 12 | class PopCountTester(n: Int) extends Module { 13 | val x = RegInit(0.U(n.W)) 14 | x := x + 1.U 15 | when(RegNext(x === ~0.U(n.W))) { stop() } 16 | 17 | val result = PopCount(x.asBools) 18 | val expected = x.asBools.foldLeft(0.U)(_ +& _) 19 | assert(result === expected) 20 | 21 | require(result.getWidth == BigInt(n).bitLength) 22 | } 23 | 24 | class PopCountSpec extends AnyPropSpec with PropertyUtils with ChiselSim { 25 | property("Mul lookup table should return the correct result") { 26 | forAll(smallPosInts) { (n: Int) => simulate(new PopCountTester(n))(RunUntilFinished(math.pow(2, n).toInt + 2)) } 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/RebindingSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import circt.stage.ChiselStage 7 | import org.scalatest.flatspec.AnyFlatSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | class RebindingSpec extends AnyFlatSpec with Matchers { 11 | "Rebinding a literal" should "fail" in { 12 | a[BindingException] should be thrownBy { 13 | ChiselStage.emitCHIRRTL { 14 | new Module { 15 | val io = IO(new Bundle { 16 | val a = 4.U 17 | }) 18 | } 19 | } 20 | } 21 | } 22 | 23 | "Rebinding a hardware type" should "fail" in { 24 | a[BindingException] should be thrownBy { 25 | ChiselStage.emitCHIRRTL { 26 | new Module { 27 | val io = IO(new Bundle { 28 | val a = Reg(UInt(32.W)) 29 | }) 30 | } 31 | } 32 | } 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/Util.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | // Useful utilities for tests 4 | 5 | package chiselTests 6 | 7 | import chisel3._ 8 | import chisel3.internal.firrtl.Width 9 | import _root_.firrtl.{ir => firrtlir} 10 | 11 | class PassthroughModuleIO extends Bundle { 12 | val in = Input(UInt(32.W)) 13 | val out = Output(UInt(32.W)) 14 | } 15 | 16 | trait AbstractPassthroughModule extends RawModule { 17 | val io = IO(new PassthroughModuleIO) 18 | io.out := io.in 19 | } 20 | 21 | class PassthroughModule extends Module with AbstractPassthroughModule 22 | class PassthroughMultiIOModule extends Module with AbstractPassthroughModule 23 | class PassthroughRawModule extends RawModule with AbstractPassthroughModule 24 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/WarningSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import chisel3.util.Counter 7 | import circt.stage.ChiselStage 8 | import org.scalatest.flatspec.AnyFlatSpec 9 | import org.scalatest.matchers.should.Matchers 10 | 11 | class WarningSpec extends AnyFlatSpec with Matchers with LogUtils { 12 | behavior.of("Warnings") 13 | 14 | object MyEnum extends ChiselEnum { 15 | val e0, e1, e2 = Value 16 | } 17 | 18 | class MyModule extends Module { 19 | val in = IO(Input(UInt(2.W))) 20 | val out1 = IO(Output(MyEnum())) 21 | val out2 = IO(Output(MyEnum())) 22 | def func(out: EnumType): Unit = { 23 | out := MyEnum(in) 24 | } 25 | func(out1) 26 | func(out2) 27 | } 28 | 29 | "Warnings" should "be de-duplicated" in { 30 | val (log, _) = grabLog(ChiselStage.emitCHIRRTL(new MyModule)) 31 | def countSubstring(s: String, sub: String) = 32 | s.sliding(sub.length).count(_ == sub) 33 | countSubstring(log, "Casting non-literal UInt") should be(1) 34 | } 35 | 36 | "Warnings" should "be treated as errors with warningsAsErrors" in { 37 | a[ChiselException] should be thrownBy { 38 | val args = Array("--warnings-as-errors") 39 | ChiselStage.emitCHIRRTL(new MyModule, args) 40 | } 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/WireSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests 4 | 5 | import chisel3._ 6 | import circt.stage.ChiselStage 7 | import org.scalatest.flatspec.AnyFlatSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | class WireSpec extends AnyFlatSpec with Matchers { 11 | "WireDefault.apply" should "work" in { 12 | assertCompiles("WireDefault(UInt(4.W), 2.U)") 13 | } 14 | it should "allow DontCare" in { 15 | assertCompiles("WireDefault(UInt(4.W), DontCare)") 16 | } 17 | it should "not allow DontCare to affect type inference" in { 18 | assertCompiles("val x: UInt = WireDefault(UInt(4.W), DontCare)") 19 | } 20 | it should "not allow init argument to affect type inference" in { 21 | assertDoesNotCompile("val x: UInt = WireDefault(UInt(4.W), 2.S)") 22 | } 23 | it should "have source locator information on wires" in { 24 | class Dummy extends chisel3.Module { 25 | val in = IO(Input(Bool())) 26 | val out = IO(Output(Bool())) 27 | 28 | val wire = WireInit(Bool(), true.B) 29 | val wire2 = Wire(Bool()) 30 | wire2 := in 31 | out := in & wire & wire2 32 | } 33 | 34 | val chirrtl = ChiselStage.emitCHIRRTL(new Dummy) 35 | chirrtl should include("wire wire : UInt<1>") 36 | chirrtl should include("wire wire2 : UInt<1>") 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/experimental/ExtensionMethods.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.experimental 4 | 5 | import chisel3.RawModule 6 | import circt.stage.ChiselStage 7 | 8 | /** Object that contains various extension methods for all the [[experimental]] package. */ 9 | private[experimental] object ExtensionMethods { 10 | 11 | /** Extension methods for [[ChiselStage]]. */ 12 | implicit class ChiselStageHelpers(obj: ChiselStage.type) { 13 | 14 | /** Construct a module and return it. This has a _very_ narrow use case and 15 | * should not be generally used for writing tests of Chisel. 16 | */ 17 | def getModule[A <: RawModule](gen: => A): A = { 18 | var res: Any = null 19 | obj.elaborate { 20 | res = gen 21 | res.asInstanceOf[A] 22 | } 23 | res.asInstanceOf[A] 24 | } 25 | 26 | } 27 | 28 | } 29 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/experimental/hierarchy/Annotations.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.experimental.hierarchy 4 | 5 | import _root_.firrtl.annotations._ 6 | import chisel3.experimental.{annotate, BaseModule, Targetable} 7 | import chisel3.{Data, HasTarget, MemBase} 8 | import chisel3.experimental.hierarchy.{Definition, Hierarchy, Instance} 9 | 10 | // These annotations exist purely for testing purposes 11 | private[hierarchy] object Annotations { 12 | case class MarkAnnotation(target: IsMember, tag: String) extends SingleTargetAnnotation[IsMember] { 13 | def duplicate(n: IsMember): Annotation = this.copy(target = n) 14 | } 15 | def mark(d: Data, tag: String): Unit = annotate(d)(Seq(MarkAnnotation(d.toTarget, tag))) 16 | def mark[T <: Data](d: MemBase[T], tag: String): Unit = annotate(d)(Seq(MarkAnnotation(d.toTarget, tag))) 17 | def mark(d: HasTarget, tag: String): Unit = annotate(d)(Seq(MarkAnnotation(d.toTarget, tag))) 18 | def mark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(d)(Seq(MarkAnnotation(d.toTarget, tag))) 19 | def amark(d: Data, tag: String): Unit = annotate(d)(Seq(MarkAnnotation(d.toAbsoluteTarget, tag))) 20 | def amark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(d)(Seq(MarkAnnotation(d.toTarget, tag))) 21 | } 22 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/experimental/hierarchy/Utils.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.experimental.hierarchy 4 | 5 | import firrtl.annotations.{InstanceTarget, ModuleTarget, ReferenceTarget, Target} 6 | 7 | trait Utils { 8 | // TODO promote to standard API (in FIRRTL) and perhaps even implement with a macro 9 | implicit class Str2RefTarget(str: String) { 10 | def rt: ReferenceTarget = Target.deserialize(str).asInstanceOf[ReferenceTarget] 11 | def it: InstanceTarget = Target.deserialize(str).asInstanceOf[InstanceTarget] 12 | def mt: ModuleTarget = Target.deserialize(str).asInstanceOf[ModuleTarget] 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/naming/IdentifierProposerSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.naming 4 | 5 | import chisel3._ 6 | import chisel3.naming.{HasCustomIdentifier, IdentifierProposer} 7 | import org.scalatest.funspec.AnyFunSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | case class Blah(i: Int) 11 | 12 | class Foo(val i: Int) extends HasCustomIdentifier { 13 | protected val customDefinitionIdentifierProposal = s"A_Different_Name_for_Foo" 14 | } 15 | 16 | class Baz(val i: Int) 17 | 18 | class IdentifierProposerSpec extends AnyFunSpec with Matchers { 19 | it("(0): getProposal works on a variety of object types") { 20 | IdentifierProposer.getProposal("Hi") should be("Hi") 21 | IdentifierProposer.getProposal(1) should be("1") 22 | IdentifierProposer.getProposal(Blah(1)) should be("Blah_1") 23 | IdentifierProposer.getProposal(new Bundle {}) should be("AnonymousBundle") 24 | IdentifierProposer.getProposal(new Foo(1)) should be("A_Different_Name_for_Foo") 25 | IdentifierProposer.getProposal(new Baz(2)) should be("chiselTests_naming_Baz") 26 | IdentifierProposer.getProposal(Seq(1, 2, 3)) should be("1_2_3") 27 | IdentifierProposer.getProposal(List(1, 2, 3)) should be("1_2_3") 28 | IdentifierProposer.getProposal((1, 2)) should be("1_2") 29 | IdentifierProposer.getProposal(()) should be("") 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/simulator/GCD.scala: -------------------------------------------------------------------------------- 1 | package chiselTests.simulator 2 | 3 | import chisel3._ 4 | 5 | /** A simple module useful for testing Chisel generation and testing */ 6 | class GCD extends Module { 7 | val io = IO(new Bundle { 8 | val a = Input(UInt(32.W)) 9 | val b = Input(UInt(32.W)) 10 | val loadValues = Input(Bool()) 11 | val result = Output(UInt(32.W)) 12 | val resultIsValid = Output(Bool()) 13 | }) 14 | val x = Reg(UInt(32.W)) 15 | val y = Reg(UInt(32.W)) 16 | when(x > y) { x := x -% y }.otherwise { y := y -% x } 17 | when(io.loadValues) { x := io.a; y := io.b } 18 | io.result := x 19 | io.resultIsValid := y === 0.U 20 | } 21 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/simulator/OptionalIOModule.scala: -------------------------------------------------------------------------------- 1 | package chiselTests.simulator 2 | 3 | import chisel3._ 4 | 5 | class OptionalIOModule(n: Int) extends Module { 6 | val a, b, c = IO(Input(Bool())) 7 | val d, e, f = IO(Input(Bool())) 8 | val foo, bar = IO(Input(UInt(n.W))) 9 | val emptyBundle = IO(Input(new Bundle {})) 10 | val bundle = IO(Input(new Bundle { val x = foo.cloneType })) 11 | val out = IO(Output(UInt(n.W))) 12 | 13 | val myReg = RegInit(0.U(n.W)) 14 | 15 | out := myReg 16 | 17 | when(a && b && c) { 18 | myReg := foo 19 | } 20 | when(d && e && f) { 21 | myReg := bar 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.simulator.scalatest 4 | 5 | import chisel3.simulator.HasSimulator 6 | import chisel3.simulator.scalatest.{Cli, HasCliOptions} 7 | import chisel3.testing.scalatest.HasConfigMap 8 | import org.scalatest.TestSuite 9 | import org.scalatest.flatspec.AnyFlatSpec 10 | import org.scalatest.matchers.should.Matchers 11 | 12 | class HasCliOptionsSpec extends AnyFlatSpec with Matchers with HasCliOptions with Cli.Simulator { 13 | 14 | override protected def defaultCliSimulator: Option[HasSimulator] = None 15 | 16 | behavior of "Cli.Simulator" 17 | 18 | it should "should be capable of forcing a user to specify a simulator" in { 19 | 20 | intercept[IllegalArgumentException] { 21 | implicitly[HasSimulator] 22 | }.getMessage should include("a simulator must be provided to this test using '-Dsimulator='") 23 | 24 | } 25 | 26 | } 27 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/testing/FileCheckSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.testing.scalatest 4 | 5 | import chisel3.testing.FileCheck.Exceptions 6 | import chisel3.testing.scalatest.FileCheck 7 | import org.scalatest.flatspec.AnyFlatSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | class FileCheckSpec extends AnyFlatSpec with Matchers with FileCheck { 11 | 12 | behavior of ("FileCheck") 13 | 14 | it should "check an input string and suceed" in { 15 | "Hello world!".fileCheck()( 16 | """|CHECK: Hello 17 | |CHECK-SAME: world 18 | |""".stripMargin 19 | ) 20 | "Hello world!".fileCheck()("CHECK: Hello world!") 21 | } 22 | 23 | it should "throw a NonZeroExitCode exception on failure" in { 24 | intercept[Exceptions.NonZeroExitCode] { 25 | "Hello world!".fileCheck()("CHECK: no match") 26 | } 27 | } 28 | 29 | it should "allow for a user to pass additional options" in { 30 | "Hello world!".fileCheck("--check-prefix=FOO")("FOO:Hello world!") 31 | } 32 | 33 | } 34 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/testing/scalatest/HasConfigMapSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.testing.scalatest 4 | 5 | import chisel3.testing.scalatest.HasConfigMap 6 | import org.scalatest.flatspec.AnyFlatSpec 7 | import org.scalatest.matchers.should.Matchers 8 | 9 | class HasConfigMapSpec extends AnyFlatSpec with Matchers with HasConfigMap { 10 | 11 | behavior of "HasConfigMap" 12 | 13 | it should "be accessible inside a test" in { 14 | configMap 15 | } 16 | 17 | val outsideTestException = intercept[Exception] { 18 | configMap 19 | } 20 | 21 | it should "throw a RuntimeException if used outside a test" in { 22 | outsideTestException shouldBe a[RuntimeException] 23 | outsideTestException.getMessage should include("configMap may only be accessed inside a Scalatest test") 24 | } 25 | 26 | } 27 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/util/AttributeAnnotationSpec.scala: -------------------------------------------------------------------------------- 1 | package chiselTests.util 2 | 3 | import _root_.circt.stage.ChiselStage 4 | import chisel3._ 5 | import chisel3.util.addAttribute 6 | import org.scalatest.flatspec.AnyFlatSpec 7 | import org.scalatest.matchers.should.Matchers 8 | 9 | class AttributeAnnotationSpec extends AnyFlatSpec with Matchers { 10 | class AttributeExample extends Module { 11 | val io = IO(new Bundle { 12 | val input = Input(UInt(8.W)) 13 | val output = Output(UInt(8.W)) 14 | }) 15 | 16 | val reg = RegNext(io.input) 17 | 18 | addAttribute(reg, "synthesis translate_off") 19 | 20 | io.output := reg 21 | } 22 | 23 | it should "generate corresponding SystemVerilog attributes" in { 24 | val verilog = ChiselStage.emitSystemVerilog(new AttributeExample) 25 | 26 | verilog should include("(* synthesis translate_off *)") 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/util/circt/ClockGate.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.util.circt.ClockGate 7 | import circt.stage.ChiselStage 8 | 9 | import org.scalatest.flatspec.AnyFlatSpec 10 | import org.scalatest.matchers.should.Matchers 11 | 12 | import scala.io.Source 13 | 14 | private class ClockGateTop extends RawModule { 15 | val clock = IO(Input(Clock())) 16 | val enable = IO(Input(Bool())) 17 | val gatedClock = IO(Output(Clock())) 18 | gatedClock := ClockGate(clock, enable) 19 | } 20 | 21 | class ClockGateSpec extends AnyFlatSpec with Matchers { 22 | it should "produce gate clock intrinsic" in { 23 | val fir = ChiselStage.emitCHIRRTL(new ClockGateTop) 24 | fir.split('\n').map(_.takeWhile(_ != '@').trim) should contain( 25 | "node _gatedClock_T = intrinsic(circt_clock_gate : Clock, clock, enable)" 26 | ) 27 | } 28 | it should "compile to SV" in { 29 | ChiselStage.emitSystemVerilog(new ClockGateTop) 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/util/circt/IsXSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.stage.ChiselGeneratorAnnotation 7 | import chisel3.util.circt.IsX 8 | import circt.stage.ChiselStage 9 | 10 | import org.scalatest.flatspec.AnyFlatSpec 11 | import org.scalatest.matchers.should.Matchers 12 | 13 | import scala.io.Source 14 | 15 | private class IsXBundle extends Bundle { 16 | val a = UInt() 17 | val b = SInt() 18 | } 19 | 20 | private class IsXTop extends Module { 21 | val w = IO(Input(UInt(65.W))) 22 | val x = IO(Input(new IsXBundle)) 23 | val y = IO(Input(UInt(65.W))) 24 | val outw = IO(Output(UInt(1.W))) 25 | val outx = IO(Output(UInt(1.W))) 26 | val outy = IO(Output(UInt(1.W))) 27 | outw := IsX(w) 28 | outx := IsX(x) 29 | outy := IsX(y) 30 | } 31 | 32 | class IsXSpec extends AnyFlatSpec with Matchers { 33 | it should "generate expected FIRRTL" in { 34 | val fir = ChiselStage.emitCHIRRTL(new IsXTop) 35 | (fir.split('\n').map(_.takeWhile(_ != '@').trim) should contain).allOf( 36 | "node _outw_T = intrinsic(circt_isX : UInt<1>, w)", 37 | "node _outx_T = intrinsic(circt_isX : UInt<1>, x)", 38 | "node _outy_T = intrinsic(circt_isX : UInt<1>, y)" 39 | ) 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/util/circt/PlusArgsTestSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.util.circt.PlusArgsTest 7 | import circt.stage.ChiselStage 8 | import org.scalatest.flatspec.AnyFlatSpec 9 | import org.scalatest.matchers.should.Matchers 10 | import scala.io.Source 11 | 12 | private class PlusArgsTestTop extends Module { 13 | val w = IO(Output(UInt(1.W))) 14 | val x = IO(Output(UInt(1.W))) 15 | w := PlusArgsTest("FOO") 16 | x := PlusArgsTest("BAR") 17 | } 18 | 19 | class PlusArgsTestSpec extends AnyFlatSpec with Matchers { 20 | it should "generate expected FIRRTL" in { 21 | val fir = ChiselStage.emitCHIRRTL(new PlusArgsTestTop) 22 | (fir.split('\n').map(_.takeWhile(_ != '@').trim) should contain).allOf( 23 | """node _w_T = intrinsic(circt_plusargs_test : UInt<1>)""", 24 | """node _x_T = intrinsic(circt_plusargs_test : UInt<1>)""" 25 | ) 26 | } 27 | it should "compile to SV" in { 28 | ChiselStage.emitSystemVerilog(new PlusArgsTestTop) 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /src/test/scala-2/chiselTests/util/circt/SizeOfSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package chiselTests.util.circt 4 | 5 | import chisel3._ 6 | import chisel3.util.circt.SizeOf 7 | import circt.stage.ChiselStage 8 | 9 | import org.scalatest.flatspec.AnyFlatSpec 10 | import org.scalatest.matchers.should.Matchers 11 | 12 | import scala.io.Source 13 | 14 | private class SizeOfBundle extends Bundle { 15 | val a = UInt() 16 | val b = SInt() 17 | } 18 | 19 | private class SizeOfTop extends Module { 20 | val w = IO(Input(UInt(65.W))) 21 | val x = IO(Input(new SizeOfBundle)) 22 | val outw = IO(Output(UInt(32.W))) 23 | val outx = IO(Output(UInt(32.W))) 24 | outw := SizeOf(w) 25 | outx := SizeOf(x) 26 | } 27 | 28 | class SizeOfSpec extends AnyFlatSpec with Matchers { 29 | it should "work for types" in { 30 | val fir = ChiselStage.emitCHIRRTL(new SizeOfTop) 31 | (fir.split('\n').map(_.takeWhile(_ != '@').trim) should contain) 32 | .allOf( 33 | "node _outw_T = intrinsic(circt_sizeof : UInt<32>, w)", 34 | "node _outx_T = intrinsic(circt_sizeof : UInt<32>, x)" 35 | ) 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /src/test/scala-2/circtTests/OutputDirAnnotationSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package circtTests 4 | 5 | import chisel3._ 6 | import circt.outputDir 7 | import circt.stage.ChiselStage 8 | import org.scalatest.funspec.AnyFunSpec 9 | import org.scalatest.matchers.should.Matchers 10 | import chiselTests.experimental.hierarchy.Utils 11 | 12 | class OutputDirAnnotationSpec extends AnyFunSpec with Matchers { 13 | describe("output directory annotation works") { 14 | it("should put module where requested") { 15 | class TestModule extends RawModule with Public {} 16 | class ParentModule extends RawModule { 17 | val test = outputDir(Module(new TestModule), "foo") 18 | } 19 | 20 | val chirrtl = ChiselStage.emitCHIRRTL(new ParentModule) 21 | (chirrtl.split('\n').map(_.takeWhile(_ != '@').trim) should contain).allOf( 22 | """"class":"circt.OutputDirAnnotation",""", 23 | """"target":"~|TestModule",""", 24 | """"dirname":"foo"""" 25 | ) 26 | 27 | val sv = ChiselStage.emitSystemVerilog(new ParentModule) 28 | sv should include(""""foo/TestModule.sv"""") 29 | } 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /src/test/scala-2/cookbook/Bundle2UInt.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package cookbook 4 | 5 | import chisel3._ 6 | import chisel3.simulator.stimulus.RunUntilFinished 7 | 8 | /* ### How do I create a UInt from an instance of a Bundle? 9 | * 10 | * Call asUInt on the Bundle instance 11 | */ 12 | class Bundle2UInt extends CookbookTester(1) { 13 | // Example 14 | class MyBundle extends Bundle { 15 | val foo = UInt(4.W) 16 | val bar = UInt(4.W) 17 | } 18 | val bundle = Wire(new MyBundle) 19 | bundle.foo := 0xc.U 20 | bundle.bar := 0x3.U 21 | val uint = bundle.asUInt 22 | printf(p"$uint") // 195 23 | 24 | // Test 25 | assert(uint === 0xc3.U) 26 | } 27 | 28 | class Bundle2UIntSpec extends CookbookSpec { 29 | "Bundle2UInt" should "work" in { 30 | simulate(new Bundle2UInt)(RunUntilFinished(3)) 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /src/test/scala-2/cookbook/CookbookSpec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package cookbook 4 | 5 | import chisel3._ 6 | import chisel3.util.Counter 7 | import chisel3.simulator.scalatest.ChiselSim 8 | import org.scalatest.flatspec.AnyFlatSpec 9 | import org.scalatest.matchers.should.Matchers 10 | 11 | /** Tester for concise cookbook tests 12 | * 13 | * Provides a length of test after which the test will pass 14 | */ 15 | abstract class CookbookTester(length: Int) extends Module { 16 | require(length >= 0, "Simulation length must be non-negative!") 17 | 18 | val (cycle, done) = Counter(true.B, length + 1) // + 1 cycle because done is actually wrap 19 | when(done) { stop() } 20 | } 21 | 22 | abstract class CookbookSpec extends AnyFlatSpec with Matchers with ChiselSim 23 | -------------------------------------------------------------------------------- /src/test/scala-2/cookbook/RegOfVec.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package cookbook 4 | 5 | import chisel3._ 6 | import chisel3.simulator.stimulus.RunUntilFinished 7 | 8 | /* ### How do I create a Reg of type Vec? 9 | * 10 | * For information, please see the API documentation for Vec 11 | * (https://chisel.eecs.berkeley.edu/api/index.html#chisel3.Vec) 12 | */ 13 | class RegOfVec extends CookbookTester(2) { 14 | // Reg of Vec of 32-bit UInts without initialization 15 | val regOfVec = Reg(Vec(4, UInt(32.W))) 16 | regOfVec(0) := 123.U // a couple of assignments 17 | regOfVec(2) := regOfVec(0) 18 | 19 | // Reg of Vec of 32-bit UInts initialized to zero 20 | // Note that Seq.fill constructs 4 32-bit UInt literals with the value 0 21 | // Vec(...) then constructs a Wire of these literals 22 | // The Reg is then initialized to the value of the Wire (which gives it the same type) 23 | val initRegOfVec = RegInit(VecInit(Seq.fill(4)(0.U(32.W)))) 24 | 25 | // Simple test (cycle comes from superclass) 26 | when(cycle === 2.U) { assert(regOfVec(2) === 123.U) } 27 | for (elt <- initRegOfVec) { assert(elt === 0.U) } 28 | } 29 | 30 | class RegOfVecSpec extends CookbookSpec { 31 | "RegOfVec" should "work" in { 32 | simulate(new RegOfVec)(RunUntilFinished(4)) 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /src/test/scala-2/cookbook/UInt2Bundle.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package cookbook 4 | 5 | import chisel3._ 6 | import chisel3.simulator.stimulus.RunUntilFinished 7 | 8 | /* ### How do I create a Bundle from a UInt? 9 | * 10 | * On an instance of the Bundle, call the method fromBits with the UInt as the argument 11 | */ 12 | class UInt2Bundle extends CookbookTester(1) { 13 | // Example 14 | class MyBundle extends Bundle { 15 | val foo = UInt(4.W) 16 | val bar = UInt(4.W) 17 | } 18 | val uint = 0xb4.U 19 | val bundle = uint.asTypeOf(new MyBundle) 20 | printf(p"$bundle") // Bundle(foo -> 11, bar -> 4) 21 | 22 | // Test 23 | assert(bundle.foo === 0xb.U) 24 | assert(bundle.bar === 0x4.U) 25 | } 26 | 27 | class UInt2BundleSpec extends CookbookSpec { 28 | "UInt2Bundle" should "work" in { 29 | simulate(new UInt2Bundle)(RunUntilFinished(3)) 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /src/test/scala-2/cookbook/UInt2VecOfBool.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package cookbook 4 | 5 | import chisel3._ 6 | import chisel3.simulator.stimulus.RunUntilFinished 7 | 8 | /* ### How do I create a Vec of Bools from a UInt? 9 | * 10 | * Use the builtin function [[chisel3.Bits.asBools]] to create a Scala Seq of Bool, 11 | * then wrap the resulting Seq in Vec(...) 12 | */ 13 | class UInt2VecOfBool extends CookbookTester(1) { 14 | // Example 15 | val uint = 0xc.U 16 | val vec = VecInit(uint.asBools) 17 | printf(p"$vec") // Vec(0, 0, 1, 1) 18 | 19 | // Test 20 | assert(vec(0) === false.B) 21 | assert(vec(1) === false.B) 22 | assert(vec(2) === true.B) 23 | assert(vec(3) === true.B) 24 | } 25 | 26 | class UInt2VecOfBoolSpec extends CookbookSpec { 27 | "UInt2VecOfBool" should "work" in { 28 | simulate(new UInt2VecOfBool)(RunUntilFinished(3)) 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /src/test/scala-2/cookbook/VecOfBool2UInt.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package cookbook 4 | 5 | import chisel3._ 6 | import chisel3.simulator.stimulus.RunUntilFinished 7 | 8 | /* ### How do I create a UInt from a Vec of Bool? 9 | * 10 | * Use the builtin function asUInt 11 | */ 12 | class VecOfBool2UInt extends CookbookTester(1) { 13 | // Example 14 | val vec = VecInit(true.B, false.B, true.B, true.B) 15 | val uint = vec.asUInt 16 | printf(p"$uint") // 13 17 | 18 | /* Test 19 | * 20 | * (remember leftmost Bool in Vec is low order bit) 21 | */ 22 | assert(0xd.U === uint) 23 | } 24 | 25 | class VecOfBool2UIntSpec extends CookbookSpec { 26 | "VecOfBool2UInt" should "work" in { 27 | simulate(new VecOfBool2UInt)(RunUntilFinished(3)) 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /src/test/scala-2/examples/ImplicitStateVendingMachine.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package examples 4 | 5 | import chisel3._ 6 | import chisel3.simulator.scalatest.ChiselSim 7 | import chisel3.simulator.stimulus.RunUntilFinished 8 | import org.scalatest.flatspec.AnyFlatSpec 9 | import org.scalatest.matchers.should.Matchers 10 | 11 | // Vending machine implemented with an implicit state machine 12 | class ImplicitStateVendingMachine extends SimpleVendingMachine { 13 | // We let the value of nickel be 1 and dime be 2 for efficiency reasons 14 | val value = RegInit(0.asUInt(3.W)) 15 | val incValue = WireDefault(0.asUInt(3.W)) 16 | val doDispense = value >= 4.U // 4 * nickel as 1 == $0.20 17 | 18 | when(doDispense) { 19 | value := 0.U // No change given 20 | }.otherwise { 21 | value := value + incValue 22 | } 23 | 24 | when(io.nickel) { incValue := 1.U } 25 | when(io.dime) { incValue := 2.U } 26 | 27 | io.dispense := doDispense 28 | } 29 | 30 | class ImplicitStateVendingMachineSpec extends AnyFlatSpec with Matchers with ChiselSim { 31 | "An vending machine implemented with implicit state" should "work" in { 32 | simulate { new SimpleVendingMachineTester(new ImplicitStateVendingMachine) }(RunUntilFinished(11)) 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /src/test/scala-2/examples/VendingMachineUtils.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | package examples 4 | 5 | import scala.collection.mutable 6 | 7 | /* Useful utilities for testing vending machines */ 8 | object VendingMachineUtils { 9 | abstract class Coin(val name: String, val value: Int) 10 | // US Coins 11 | case object Penny extends Coin("penny", 1) 12 | case object Nickel extends Coin("nickel", 5) 13 | case object Dime extends Coin("dime", 10) 14 | case object Quarter extends Coin("quarter", 25) 15 | 16 | // Harry Potter Coins 17 | case object Knut extends Coin("knut", Penny.value * 2) // Assuming 1 Knut is worth $0.02 18 | case object Sickle extends Coin("sickle", Knut.value * 29) 19 | case object Galleon extends Coin("galleon", Sickle.value * 17) 20 | 21 | def getExpectedResults(inputs: Seq[Option[Coin]], sodaCost: Int): Seq[Boolean] = { 22 | var value = 0 23 | val outputs = mutable.ArrayBuffer.empty[Boolean] 24 | for (input <- inputs) { 25 | val incValue = input match { 26 | case Some(coin) => coin.value 27 | case None => 0 28 | } 29 | if (value >= sodaCost) { 30 | outputs.append(true) 31 | value = 0 32 | } else { 33 | outputs.append(false) 34 | value += incValue 35 | } 36 | } 37 | outputs.toSeq 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /stdlib/package.mill: -------------------------------------------------------------------------------- 1 | package build.stdlib 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | 10 | object `package` extends RootModule { 11 | // https://github.com/com-lihaoyi/mill/issues/3693 12 | object cross extends Cross[Stdlib](v.scalaCrossVersions) 13 | } 14 | 15 | trait Stdlib extends CrossSbtModule with HasScalaPlugin with HasCommonOptions with ScalafmtModule { 16 | def millSourcePath = super.millSourcePath / os.up 17 | def chiselModule = chisel(crossScalaVersion) 18 | def pluginModule = plugin.cross(crossScalaVersion) 19 | 20 | override def moduleDeps = Seq(chiselModule, pluginModule) 21 | } 22 | -------------------------------------------------------------------------------- /svsim/.clang-format: -------------------------------------------------------------------------------- 1 | BasedOnStyle: LLVM 2 | AlwaysBreakTemplateDeclarations: Yes 3 | -------------------------------------------------------------------------------- /svsim/package.mill: -------------------------------------------------------------------------------- 1 | package build.svsim 2 | 3 | import mill._ 4 | import mill.scalalib._ 5 | import mill.scalalib.scalafmt._ 6 | import mill.define.Cross 7 | 8 | import build._ 9 | 10 | object `package` extends RootModule { 11 | // https://github.com/com-lihaoyi/mill/issues/3693 12 | object cross extends Cross[Svsim](v.scalaCrossVersions) 13 | } 14 | 15 | trait Svsim extends CrossSbtModule with HasCommonOptions with ScalafmtModule { 16 | def millSourcePath = super.millSourcePath / os.up 17 | 18 | override def scalacOptions = Task { 19 | super.scalacOptions() ++ 20 | Option.when(!v.isScala3(crossScalaVersion))( 21 | "-Xsource-features:case-apply-copy-access" 22 | ) 23 | } 24 | 25 | object test extends SbtTests with TestModule.ScalaTest with ScalafmtModule { 26 | def ivyDeps = Agg(v.scalatest, v.scalacheck) 27 | } 28 | 29 | def clangFormatConfig = Task.Source { 30 | Task.workspace / "svsim" / ".clang-format" 31 | } 32 | 33 | def cppSources = Task.Sources { 34 | Task.workspace / "svsim" / "src" / "main" / "resources" / "simulation-driver.cpp" 35 | } 36 | 37 | def clangformat(args: String*) = Task.Command { 38 | os.proc( 39 | "clang-format", 40 | "-i", 41 | "--verbose", 42 | s"--style=file:${clangFormatConfig().path}", 43 | cppSources() 44 | ).call(cwd = Task.dest) 45 | } 46 | 47 | } 48 | -------------------------------------------------------------------------------- /svsim/src/test/resources/Finish.sv: -------------------------------------------------------------------------------- 1 | module Finish(input clock); 2 | 3 | always @ (posedge clock) 4 | $finish; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /svsim/src/test/resources/GCD.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module GCD( 4 | input signed [62:0] a, 5 | input signed [62:0] b, 6 | input clock, 7 | input loadValues, 8 | output isValid, 9 | output [62:0] result); 10 | 11 | reg signed [62:0] x; 12 | reg signed [62:0] y; 13 | wire isValid_internal; 14 | always @(posedge clock) begin 15 | if (loadValues) begin 16 | if (a > 0) 17 | x <= a; 18 | else 19 | x <= -a; 20 | 21 | if (b > 0) 22 | y <= b; 23 | else 24 | y <= -b; 25 | end 26 | else if (x > y) 27 | x <= x - y; 28 | else 29 | y <= y - x; 30 | end 31 | assign result = x; 32 | assign isValid_internal = y == 'h0; 33 | assign isValid = isValid_internal; 34 | 35 | always @loadValues begin 36 | if (loadValues) begin 37 | $display("Calculating GCD of %X and %X.", a, b); 38 | end 39 | end 40 | always @isValid_internal begin 41 | if (isValid_internal) begin 42 | $display("Calculated GCD to be %X.", x); 43 | end 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /svsim/src/test/resources/Initial.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module Initial(output b); 4 | 5 | reg a = 1'b0; 6 | 7 | assign b = a; 8 | 9 | initial 10 | a = 1'b1; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /svsim/src/test/resources/PlusArg.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module PlusArg(output reg value, output reg test); 4 | 5 | initial begin 6 | value = 0; 7 | test = 0; 8 | $value$plusargs("value=%d", value); 9 | if ($test$plusargs("test")) 10 | test = 1; 11 | end 12 | 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /svsim/src/test/resources/SIntTest.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module SIntWire #(parameter WIDTH = 32) 4 | ( 5 | input [WIDTH-1:0] in, 6 | output [WIDTH-1:0] out 7 | ); 8 | assign out = in; 9 | endmodule 10 | 11 | // We are testing low-level APIs, no support for parameterized modules 12 | module SIntTest 13 | ( 14 | input [7:0] in_8, 15 | output [7:0] out_8, 16 | input [30:0] in_31, 17 | output [30:0] out_31, 18 | input [31:0] in_32, 19 | output [31:0] out_32, 20 | input [32:0] in_33, 21 | output [32:0] out_33, 22 | output [7:0] out_const_8, 23 | output [30:0] out_const_31, 24 | output [31:0] out_const_32, 25 | output [32:0] out_const_33 26 | ); 27 | 28 | SIntWire #(8) wire_8(.in(in_8), .out(out_8)); 29 | SIntWire #(31) wire_31(.in(in_31), .out(out_31)); 30 | SIntWire #(32) wire_32(.in(in_32), .out(out_32)); 31 | SIntWire #(33) wire_33(.in(in_33), .out(out_33)); 32 | assign out_const_8 = 8'h80; 33 | assign out_const_31 = 31'b1000000000000000000000000000000; 34 | assign out_const_32 = 32'b10000000000000000000000000000000; 35 | assign out_const_33 = 33'b100000000000000000000000000000000; 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /website/.gitignore: -------------------------------------------------------------------------------- 1 | # Dependencies 2 | /node_modules 3 | 4 | # Production 5 | /build 6 | /build.timestamp 7 | 8 | # Generated files 9 | .docusaurus 10 | .cache-loader 11 | /docs 12 | generated 13 | /static/api/latest 14 | /static/releases 15 | # Debatable if this should be included or not 16 | package-lock.json 17 | 18 | # Misc 19 | .DS_Store 20 | .env.local 21 | .env.development.local 22 | .env.test.local 23 | .env.production.local 24 | 25 | npm-debug.log* 26 | yarn-debug.log* 27 | yarn-error.log* 28 | -------------------------------------------------------------------------------- /website/babel.config.js: -------------------------------------------------------------------------------- 1 | module.exports = { 2 | presets: [require.resolve('@docusaurus/core/lib/babel/preset')], 3 | }; 4 | -------------------------------------------------------------------------------- /website/blog/2025/01-07-restarting-the-blog/index.md: -------------------------------------------------------------------------------- 1 | --- 2 | authors: 3 | - seldridge 4 | tags: [miscellaneous] 5 | slug: restarting-the-blog 6 | description: After a long hiatus, the Chisel developers are restarting the Chisel blog. 7 | --- 8 | 9 | # Restarting the Blog 10 | 11 | It's been many years since the Chisel project had a blog. In the spirit of New 12 | Year's resolutions (and more pragmatically as a means to better communicate with 13 | the open source community about Chisel), the Chisel developers are restarting 14 | the blog. 15 | 16 | In the future look for posts by Chisel users and developers about new features, 17 | the rationale behind existing features, and more communication about the broad 18 | direction of Chisel. 19 | -------------------------------------------------------------------------------- /website/blog/authors.yml: -------------------------------------------------------------------------------- 1 | seldridge: 2 | name: Schuyler Eldridge 3 | title: Principal Engineer at SiFive 4 | url: https://seldridge.dev 5 | image_url: https://github.com/seldridge.png 6 | page: true 7 | socials: 8 | x: theSchuyler 9 | github: seldridge 10 | linkedin: schuylereldridge 11 | jackkoenig: 12 | name: Jack Koenig 13 | title: Senior Staff Engineer at SiFive 14 | image_url: https://github.com/jackkoenig.png 15 | page: true 16 | socials: 17 | x: jackakattack 18 | github: jackkoenig 19 | linkedin: koenigjack 20 | -------------------------------------------------------------------------------- /website/blog/tags.yml: -------------------------------------------------------------------------------- 1 | miscellaneous: 2 | description: "Miscellaneous posts" 3 | release: 4 | description: "Blog posts about new Chisel releases" 5 | talk: 6 | label: "Talk/Publication" 7 | description: "Blog posts referring to talks or other publications" 8 | -------------------------------------------------------------------------------- /website/package.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "chisel-lang", 3 | "private": true, 4 | "scripts": { 5 | "docusaurus": "docusaurus", 6 | "start": "docusaurus start", 7 | "build": "docusaurus build", 8 | "swizzle": "docusaurus swizzle", 9 | "deploy": "docusaurus deploy", 10 | "clear": "docusaurus clear", 11 | "serve": "docusaurus serve", 12 | "write-translations": "docusaurus write-translations", 13 | "write-heading-ids": "docusaurus write-heading-ids" 14 | }, 15 | "dependencies": { 16 | "@docusaurus/core": "3.5.2", 17 | "@docusaurus/plugin-client-redirects": "3.5.2", 18 | "@docusaurus/preset-classic": "3.5.2", 19 | "@mdx-js/react": "^3.0.0", 20 | "clsx": "^2.0.0", 21 | "prism-react-renderer": "^2.3.0", 22 | "react": "^18.0.0", 23 | "react-dom": "^18.0.0" 24 | }, 25 | "devDependencies": { 26 | "@docusaurus/module-type-aliases": "3.5.2", 27 | "@docusaurus/types": "3.5.2" 28 | }, 29 | "browserslist": { 30 | "production": [ 31 | ">0.5%", 32 | "not dead", 33 | "not op_mini all" 34 | ], 35 | "development": [ 36 | "last 3 chrome version", 37 | "last 3 firefox version", 38 | "last 5 safari version" 39 | ] 40 | }, 41 | "engines": { 42 | "node": ">=18.0" 43 | } 44 | } 45 | -------------------------------------------------------------------------------- /website/src/components/HomepageFeatures/styles.module.css: -------------------------------------------------------------------------------- 1 | .features { 2 | display: flex; 3 | align-items: center; 4 | padding: 2rem 0; 5 | width: 100%; 6 | } 7 | 8 | .featureSvg { 9 | height: 200px; 10 | width: 200px; 11 | } 12 | -------------------------------------------------------------------------------- /website/src/pages/api.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: API Docs 3 | --- 4 | 5 | import ScalaDoc from './generated/scaladoc_links.md' 6 | 7 | ## Chisel API Documentation 8 | 9 | Please see the page about [Versioning](docs/appendix/versioning) for more information about major and minor versioning and binary compatibility. 10 | 11 | 12 | -------------------------------------------------------------------------------- /website/src/pages/api/chisel3/latest.js: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | import React from 'react'; 3 | import Layout from '@theme/Layout'; 4 | import BrowserOnly from '@docusaurus/BrowserOnly'; 5 | import useBaseUrl from '@docusaurus/useBaseUrl'; 6 | 7 | // This is a manual redirect. 8 | // We cannot use @docusaurus/plugin-client-redirects because it only redirects 9 | // to pages known to Docusaurus while the generated ScalaDoc is just a blob of 10 | // static HTML. 11 | export default function Redirect() { 12 | return ( 13 | Loading...}> 14 | {() => { 15 | window.location.replace(useBaseUrl('/api/latest')); 16 | }} 17 | 18 | ); 19 | } 20 | -------------------------------------------------------------------------------- /website/src/pages/index.js: -------------------------------------------------------------------------------- 1 | import React from 'react'; 2 | import clsx from 'clsx'; 3 | import Link from '@docusaurus/Link'; 4 | import useDocusaurusContext from '@docusaurus/useDocusaurusContext'; 5 | import Layout from '@theme/Layout'; 6 | import HomepageFeatures from '@site/src/components/HomepageFeatures'; 7 | 8 | import styles from './index.module.css'; 9 | 10 | function HomepageHeader() { 11 | const {siteConfig} = useDocusaurusContext(); 12 | return ( 13 |
14 |
15 |

{siteConfig.title}

16 |

{siteConfig.tagline}

17 |
18 | 21 | Getting Started 22 | 23 |
24 |
25 |
26 | ); 27 | } 28 | 29 | export default function Home() { 30 | const {siteConfig} = useDocusaurusContext(); 31 | return ( 32 | 35 | 36 |
37 | 38 |
39 | 40 | ); 41 | } 42 | -------------------------------------------------------------------------------- /website/src/pages/index.module.css: -------------------------------------------------------------------------------- 1 | /** 2 | * CSS files with the .module.css suffix will be treated as CSS modules 3 | * and scoped locally. 4 | */ 5 | 6 | .heroBanner { 7 | padding: 4rem 0; 8 | text-align: center; 9 | position: relative; 10 | overflow: hidden; 11 | } 12 | 13 | @media screen and (max-width: 996px) { 14 | .heroBanner { 15 | padding: 2rem; 16 | } 17 | } 18 | 19 | .buttons { 20 | display: flex; 21 | align-items: center; 22 | justify-content: center; 23 | } 24 | -------------------------------------------------------------------------------- /website/static/.nojekyll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/chisel/2f256a835c4f02f53b62f9026f66355216cd6a85/website/static/.nojekyll -------------------------------------------------------------------------------- /website/static/CNAME: -------------------------------------------------------------------------------- 1 | www.chisel-lang.org 2 | -------------------------------------------------------------------------------- /website/static/robots.txt: -------------------------------------------------------------------------------- 1 | # Algolia-Crawler-Verif: BF10E85101F030BF 2 | 3 | User-agent: * 4 | Allow: / 5 | Sitemap: https://www.chisel-lang.org/sitemap.xml 6 | --------------------------------------------------------------------------------