├── .github └── workflows │ └── ci.yml ├── .gitignore ├── .readthedocs.yml ├── LICENSE ├── README.md ├── cmake └── cxx_static │ └── CMakeLists.txt ├── docs ├── Makefile ├── _static │ ├── favicon.svg │ ├── img │ │ ├── eos_slice.png │ │ ├── eos_slice.png-057.png │ │ ├── eos_slice_mux4x2.png │ │ ├── eos_slice_mux8x3.png │ │ ├── frac_lut4.png │ │ ├── frac_lut4_a.png │ │ ├── frac_lut4_b.png │ │ ├── highlight_bottom_lut6.png │ │ ├── highlight_muxf5.png │ │ ├── highlight_muxf5_muxf6.png │ │ ├── highlight_top_lut6.png │ │ ├── site_pip_usage.svg │ │ ├── stratix10_highlight_lut5.png │ │ ├── stratix10_highlight_lut6.png │ │ ├── stratix10_highlight_muxf5_muxf6.png │ │ ├── stratix10_slice.png-11.png │ │ ├── stratix2_slice.png-026.png │ │ ├── stratix2_slice.png-026_rotate.png │ │ ├── versal_lut4.png │ │ ├── versal_lut5.png │ │ ├── versal_lut6.png │ │ ├── versal_luts.png │ │ ├── versal_row.png │ │ └── versal_slice.png-12.png │ └── logo.svg ├── bel_and_site_design.md ├── conf.py ├── device_resources.md ├── environment.yml ├── index.rst ├── pseudo_cells.md └── requirements.txt └── interchange ├── DeviceResources.capnp ├── LogicalNetlist.capnp ├── PhysicalNetlist.capnp └── References.capnp /.github/workflows/ci.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/fpga-interchange-schema/HEAD/.github/workflows/ci.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/fpga-interchange-schema/HEAD/.gitignore -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/fpga-interchange-schema/HEAD/.readthedocs.yml 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