├── doc ├── .gitignore ├── requirements.txt ├── source │ ├── img │ │ ├── i3c_phy.png │ │ ├── ext_cap_ibi.png │ │ ├── i3c_csr_rd.png │ │ ├── i3c_csr_wr.png │ │ ├── recovery_handler.png │ │ ├── ext_cap_ibi_timing.png │ │ ├── ext_cap_pwrite_timing.png │ │ ├── recovery_handler_bd.png │ │ ├── recovery_handler_flow.png │ │ ├── ext_cap_pwrite_overrun.png │ │ └── recovery_handler_with_bypass.png │ ├── requirements.txt │ ├── registers.md │ ├── index.md │ ├── Makefile │ ├── known_limitations.md │ └── introduction.md └── Makefile ├── tools ├── nox_utils │ ├── src │ │ └── __init__.py │ └── pyproject.toml ├── cocotb_helpers │ ├── src │ │ └── __init__.py │ └── pyproject.toml ├── timing │ ├── README.md │ └── utils.py ├── reg_gen │ ├── peakrdl_uvm_templates │ │ └── dsim_caliptra │ │ │ ├── cov │ │ │ ├── uvm_reg.sv │ │ │ ├── main.sv │ │ │ └── top_pkg.sv │ │ │ ├── smp │ │ │ ├── uvm_reg.sv │ │ │ ├── main.sv │ │ │ └── top_pkg.sv │ │ │ └── uvm │ │ │ └── main.sv │ └── README.md ├── vcd2pulseview │ ├── src │ │ ├── i3c_from_vcd.tcl │ │ └── pulseview.cfg │ ├── pyproject.toml │ └── README.md ├── i3c_config │ ├── templates │ │ └── defines.txt │ └── py2svh.py ├── uvm │ └── install-uvm.sh ├── verible-scripts │ ├── README.md │ ├── run.sh │ └── stats_lint.py ├── sim_repeater.sh └── simulators │ ├── Makefile.verilator │ ├── Makefile.questa │ └── Makefile.dsim ├── verification ├── cocotb │ ├── __init__.py │ ├── top │ │ ├── i3c_axi │ │ │ ├── test_ccc.py │ │ │ ├── test_bypass.py │ │ │ ├── test_csr_access.py │ │ │ ├── test_i3c_target.py │ │ │ ├── test_interrupts.py │ │ │ ├── test_recovery.py │ │ │ ├── test_target_reset.py │ │ │ ├── test_enter_exit_hdr_mode.py │ │ │ └── Makefile │ │ ├── i3c_ahb │ │ │ ├── test_bypass.py │ │ │ ├── test_csr_access.py │ │ │ ├── test_i3c_target.py │ │ │ ├── test_interrupts.py │ │ │ ├── test_recovery.py │ │ │ ├── test_target_reset.py │ │ │ ├── test_enter_exit_hdr_mode.py │ │ │ └── Makefile │ │ ├── top_common.mk │ │ └── lib_i3c_top │ │ │ ├── i3c_bus_harness.sv │ │ │ ├── interface.py │ │ │ └── test_enter_exit_hdr_mode.py │ ├── block │ │ ├── ahb_if │ │ │ ├── test_csr_sw_access.py │ │ │ └── Makefile │ │ ├── hci_queues_ahb │ │ │ ├── test_clear_hci.py │ │ │ ├── test_empty_hci.py │ │ │ ├── test_threshold_hci.py │ │ │ └── test_read_write_ports_hci.py │ │ ├── hci_queues_axi │ │ │ ├── test_clear_hci.py │ │ │ ├── test_empty_hci.py │ │ │ ├── test_threshold_hci.py │ │ │ ├── test_read_write_ports_hci.py │ │ │ └── test_burst.py │ │ ├── tti_queues_ahb │ │ │ ├── test_empty_tti.py │ │ │ ├── test_threshold_tti.py │ │ │ └── test_read_write_ports_tti.py │ │ ├── tti_queues_axi │ │ │ ├── test_empty_tti.py │ │ │ ├── test_threshold_tti.py │ │ │ ├── test_read_write_ports_tti.py │ │ │ └── test_burst.py │ │ ├── axi_adapter │ │ │ ├── test_csr_sw_access.py │ │ │ └── Makefile │ │ ├── block_common.mk │ │ ├── ctrl_descriptor_rx │ │ │ ├── Makefile │ │ │ └── test_descriptor_rx.py │ │ ├── ctrl_descriptor_tx │ │ │ ├── Makefile │ │ │ └── test_descriptor_tx.py │ │ ├── axi_adapter_id_filter │ │ │ ├── i3c_cfg.yaml │ │ │ └── Makefile │ │ ├── recovery_pec │ │ │ └── Makefile │ │ ├── ctrl_bus_timers │ │ │ ├── Makefile │ │ │ └── test_bus_timers.py │ │ ├── ctrl_edge_detector │ │ │ └── Makefile │ │ ├── bus_tx │ │ │ ├── Makefile │ │ │ └── bus_tx_test_wrapper.sv │ │ ├── width_converter_8toN │ │ │ └── Makefile │ │ ├── width_converter_Nto8 │ │ │ └── Makefile │ │ ├── flow_standby_i3c │ │ │ └── Makefile │ │ ├── bus_rx_flow │ │ │ ├── Makefile │ │ │ └── bus_rx_flow_test_wrapper.sv │ │ ├── bus_tx_flow │ │ │ ├── Makefile │ │ │ └── bus_tx_flow_test_wrapper.sv │ │ ├── i3c_target_fsm │ │ │ └── Makefile │ │ ├── flow_standby_i2c │ │ │ └── Makefile │ │ ├── i2c_target_fsm │ │ │ └── Makefile │ │ ├── ccc │ │ │ └── Makefile │ │ ├── i2c_controller_fsm │ │ │ └── Makefile │ │ ├── ctrl_bus_monitor │ │ │ └── Makefile │ │ ├── i2c_standby_controller │ │ │ └── Makefile │ │ ├── ctrl_i3c_bus_monitor │ │ │ ├── Makefile │ │ │ └── i3c_bus_monitor_wrapper.sv │ │ └── lib_hci_queues │ │ │ ├── test_empty_hci.py │ │ │ └── test_empty_tti.py │ ├── pyproject.toml │ ├── .flake8 │ └── caliptra_common.mk ├── uvm_i3c │ ├── i3c_core │ │ ├── i3c_vseqs │ │ │ └── i3c_vseq_list.sv │ │ ├── i3c_test_pkg.sv │ │ ├── i3c_env_pkg.sv │ │ ├── i3c_core_sim.scr │ │ ├── i3c_virtual_sequencer.sv │ │ ├── i3c_env_cfg.sv │ │ ├── tb_i3c_core.sv │ │ └── i3c_env.sv │ ├── i3c_core_UVM_env.png │ ├── dv_i3c │ │ ├── i3c_agent_unit_tests │ │ │ ├── i3c_sequence_test_pkg.sv │ │ │ ├── i3c_sequence_env_pkg.sv │ │ │ ├── i3c_sequence_vseqs │ │ │ │ ├── i3c_sequence_vseq_list.sv │ │ │ │ ├── direct_vseq.sv │ │ │ │ ├── direct_i2c_vseq.sv │ │ │ │ ├── broadcast_followed_by_data_vseq.sv │ │ │ │ ├── direct_with_rstart_vseq.sv │ │ │ │ ├── broadcast_followed_by_i2c_data_vseq.sv │ │ │ │ ├── direct_i2c_with_rstart_vseq.sv │ │ │ │ ├── broadcast_followed_by_data_with_rstart_vseq.sv │ │ │ │ └── broadcast_followed_by_i2c_data_with_rstart_vseq.sv │ │ │ ├── i3c_sim.scr │ │ │ ├── i3c_sequence_virtual_sequencer.sv │ │ │ ├── tb_sequencer.sv │ │ │ └── i3c_sequence_env_cfg.sv │ │ ├── i3c_test_pkg.sv │ │ ├── seq_lib │ │ │ ├── i3c_seq_list.sv │ │ │ ├── i2c_direct_data_with_rstart_seq.sv │ │ │ └── i3c_direct_data_with_rstart_seq.sv │ │ ├── i3c_sequencer.sv │ │ └── i3c_agent.sv │ ├── questa_sim.tcl │ └── testplan_ec.hjson ├── uvm_i2c │ ├── sec_cm_prim_count_bind.sv │ ├── dv_i2c │ │ ├── seq_lib │ │ │ ├── i2c_seq_list.sv │ │ │ ├── i2c_target_base_seq.sv │ │ │ └── i2c_target_may_nack_seq.sv │ │ ├── i2c_sequencer.sv │ │ ├── i2c_agent_cov.sv │ │ ├── vseqs │ │ │ ├── i2c_target_stress_rd_vseq.sv │ │ │ ├── i2c_target_stress_wr_vseq.sv │ │ │ ├── i2c_target_stretch_vseq.sv │ │ │ ├── i2c_host_timeout_vseq.sv │ │ │ ├── i2c_host_smoke_vseq.sv │ │ │ ├── i2c_common_vseq.sv │ │ │ ├── i2c_target_ack_stop_vseq.sv │ │ │ ├── i2c_target_perf_vseq.sv │ │ │ ├── i2c_host_fifo_fmt_empty_vseq.sv │ │ │ └── i2c_vseq_list.sv │ │ └── i2c_agent.sv │ ├── push_pull_seq_list.sv │ ├── sec_cm_prim_double_lfsr_bind.sv │ ├── mem_model_pkg.sv │ ├── alert_esc_sequencer.sv │ ├── dv_base │ │ ├── dv_base_reg_map.sv │ │ ├── dv_base_agent_cov.sv │ │ ├── dv_base_virtual_sequencer.sv │ │ ├── dv_base_seq.sv │ │ ├── dv_base_shadowed_field_cov.sv │ │ ├── dv_lib_pkg.sv │ │ ├── dv_base_driver.sv │ │ ├── dv_base_env_cov.sv │ │ ├── dv_base_sequencer.sv │ │ └── dv_base_agent_cfg.sv │ ├── dv_tlul │ │ ├── tl_seq_list.sv │ │ ├── tl_sequencer.sv │ │ ├── tl_host_custom_seq.sv │ │ ├── tl_host_protocol_err_seq.sv │ │ ├── tl_if.sv │ │ └── tl_agent.sv │ ├── i2c_dv_if.sv │ ├── cip_lib │ │ ├── cip_seq_list.sv │ │ ├── cip_mubi_cov_if.sv │ │ ├── cip_mubi_cov_wrapper.sv │ │ ├── cip_lc_tx_cov_if.sv │ │ ├── cip_base_virtual_sequencer.sv │ │ ├── cip_tl_host_single_seq.sv │ │ ├── cip_tl_device_seq.sv │ │ └── cip_base_test.sv │ ├── sec_cm_prim_sparse_fsm_flop_bind.sv │ ├── common_ifs_pkg.sv │ ├── sec_cm_base_if_proxy.sv │ ├── seq_lib │ │ ├── esc_receiver_esc_rsp_seq.sv │ │ ├── alert_receiver_seq.sv │ │ ├── alert_sender_seq.sv │ │ ├── alert_receiver_base_seq.sv │ │ ├── alert_sender_base_seq.sv │ │ ├── esc_receiver_base_seq.sv │ │ └── alert_receiver_alert_rsp_seq.sv │ ├── sec_cm_prim_onehot_check_bind.sv │ ├── i2c_test_pkg.sv │ ├── questa_sim.tcl │ ├── i2c_port_conv.sv │ ├── push_pull_sequencer.sv │ ├── tlul │ │ ├── tlul_data_integ_enc.sv │ │ ├── tlul_data_integ_dec.sv │ │ └── tlul_assert_multiple.sv │ ├── prim_lib │ │ ├── prim_esc_pkg.sv │ │ ├── prim_secded_inv_39_32_enc.sv │ │ └── prim_secded_inv_64_57_enc.sv │ ├── i2c_bind.sv │ ├── top_pkg.sv │ ├── i2c_virtual_sequencer.sv │ ├── clk_if.sv │ ├── alert_esc_probe_if.sv │ ├── push_pull_host_seq.sv │ ├── rst_shadowed_if.sv │ ├── i2c_base_test.sv │ ├── esc_sender_driver.sv │ └── push_pull_base_seq.sv └── testplan │ ├── block │ ├── pec.hjson │ ├── drivers.hjson │ ├── descriptor_rx.hjson │ ├── ccc.hjson │ ├── bus_timers.hjson │ ├── flow_standby_i3c.hjson │ ├── bus_monitor.hjson │ ├── descriptor_tx.hjson │ ├── bus_rx_flow.hjson │ ├── width_converter_8toN.hjson │ ├── width_converter_Nto8.hjson │ ├── i3c_bus_monitor.hjson │ └── csr_sw_access.hjson │ ├── top │ ├── target_hdr.hjson │ └── target_reset.hjson │ └── source-maps.yml ├── .ci.yml ├── install.sh ├── src ├── ctrl │ ├── i3c_target_fsm.f │ ├── i3c_controller_fsm.sv │ ├── controller_standby_i3c.f │ ├── controller_standby.f │ └── stable_high_detector.sv ├── phy │ ├── bufs.sv │ ├── buf_pp.sv │ └── i3c_phy.sv ├── libs │ ├── mem │ │ ├── prim_ram_1p_pkg.sv │ │ └── prim_ram_1p.sv │ ├── serializer.sv │ └── counter_template.sv ├── i3c_defines.svh └── rdl │ ├── DCT_structure.rdl │ └── controller_config.rdl ├── .gitmodules ├── .gitignore ├── activate.sh ├── testbench └── Makefile ├── violations.waiver └── i3c_core_configs.yaml /doc/.gitignore: -------------------------------------------------------------------------------- 1 | .venv 2 | -------------------------------------------------------------------------------- /tools/nox_utils/src/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /verification/cocotb/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /tools/cocotb_helpers/src/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /tools/timing/README.md: -------------------------------------------------------------------------------- 1 | # Timing 2 | 3 | TBD 4 | -------------------------------------------------------------------------------- /.ci.yml: -------------------------------------------------------------------------------- 1 | include: chipsalliance-ci-scripts@main:i3c-core.yaml 2 | -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_ccc.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_ccc.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_bypass.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_bypass.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_bypass.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_bypass.py -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/cov/uvm_reg.sv: -------------------------------------------------------------------------------- 1 | ../uvm/uvm_reg.sv -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/smp/uvm_reg.sv: -------------------------------------------------------------------------------- 1 | ../uvm/uvm_reg.sv -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_csr_access.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_csr_access.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_i3c_target.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_i3c_target.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_interrupts.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_interrupts.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_recovery.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_recovery.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_csr_access.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_csr_access.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_i3c_target.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_i3c_target.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_interrupts.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_interrupts.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_recovery.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_recovery.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_target_reset.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_target_reset.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_target_reset.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_target_reset.py -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_vseqs/i3c_vseq_list.sv: -------------------------------------------------------------------------------- 1 | `include "i3c_base_vseq.sv" 2 | -------------------------------------------------------------------------------- /verification/cocotb/block/ahb_if/test_csr_sw_access.py: -------------------------------------------------------------------------------- 1 | ../lib_adapter/test_csr_sw_access.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_ahb/test_clear_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_clear_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_ahb/test_empty_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_empty_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_axi/test_clear_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_clear_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_axi/test_empty_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_empty_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_ahb/test_empty_tti.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_empty_tti.py -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_axi/test_empty_tti.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_empty_tti.py -------------------------------------------------------------------------------- /verification/cocotb/block/axi_adapter/test_csr_sw_access.py: -------------------------------------------------------------------------------- 1 | ../lib_adapter/test_csr_sw_access.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_ahb/test_threshold_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_threshold_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_axi/test_threshold_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_threshold_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_ahb/test_threshold_tti.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_threshold_tti.py -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_axi/test_threshold_tti.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_threshold_tti.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/test_enter_exit_hdr_mode.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_enter_exit_hdr_mode.py -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/test_enter_exit_hdr_mode.py: -------------------------------------------------------------------------------- 1 | ../lib_i3c_top/test_enter_exit_hdr_mode.py -------------------------------------------------------------------------------- /doc/requirements.txt: -------------------------------------------------------------------------------- 1 | Sphinx>=8.0,<8.2 2 | https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip 3 | -------------------------------------------------------------------------------- /doc/source/img/i3c_phy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/i3c_phy.png -------------------------------------------------------------------------------- /doc/source/img/ext_cap_ibi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/ext_cap_ibi.png -------------------------------------------------------------------------------- /doc/source/img/i3c_csr_rd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/i3c_csr_rd.png -------------------------------------------------------------------------------- /doc/source/img/i3c_csr_wr.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/i3c_csr_wr.png -------------------------------------------------------------------------------- /doc/source/requirements.txt: -------------------------------------------------------------------------------- 1 | Sphinx>=8.0 2 | https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip 3 | -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_ahb/test_read_write_ports_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_read_write_ports_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_axi/test_read_write_ports_hci.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_read_write_ports_hci.py -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_ahb/test_read_write_ports_tti.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_read_write_ports_tti.py -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_axi/test_read_write_ports_tti.py: -------------------------------------------------------------------------------- 1 | ../lib_hci_queues/test_read_write_ports_tti.py -------------------------------------------------------------------------------- /doc/source/img/recovery_handler.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/recovery_handler.png -------------------------------------------------------------------------------- /doc/source/img/ext_cap_ibi_timing.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/ext_cap_ibi_timing.png -------------------------------------------------------------------------------- /doc/source/img/ext_cap_pwrite_timing.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/ext_cap_pwrite_timing.png -------------------------------------------------------------------------------- /doc/source/img/recovery_handler_bd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/recovery_handler_bd.png -------------------------------------------------------------------------------- /doc/source/img/recovery_handler_flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/recovery_handler_flow.png -------------------------------------------------------------------------------- /doc/source/img/ext_cap_pwrite_overrun.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/ext_cap_pwrite_overrun.png -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core_UVM_env.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/verification/uvm_i3c/i3c_core_UVM_env.png -------------------------------------------------------------------------------- /doc/source/img/recovery_handler_with_bypass.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/i3c-core/HEAD/doc/source/img/recovery_handler_with_bypass.png -------------------------------------------------------------------------------- /doc/source/registers.md: -------------------------------------------------------------------------------- 1 | # Register descriptions 2 | 3 | This chapter provides auto-generated register descriptions for the core. 4 | 5 | ```{include} ../../src/rdl/docs/README.md 6 | ``` -------------------------------------------------------------------------------- /install.sh: -------------------------------------------------------------------------------- 1 | #!/bin/env bash 2 | 3 | if [ -d ~/.pyenv ]; then 4 | echo ":::Skipping installation, pyenv is already installed." 5 | else 6 | curl https://pyenv.run | bash 7 | fi 8 | -------------------------------------------------------------------------------- /src/ctrl/i3c_target_fsm.f: -------------------------------------------------------------------------------- 1 | +incdir+${I3C_ROOT_DIR}/src 2 | ${I3C_ROOT_DIR}/src/ctrl/controller_pkg.sv 3 | ${I3C_ROOT_DIR}/src/i3c_pkg.sv 4 | ${I3C_ROOT_DIR}/src/ctrl/i3c_target_fsm.sv 5 | -------------------------------------------------------------------------------- /verification/cocotb/top/top_common.mk: -------------------------------------------------------------------------------- 1 | TOP_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 2 | export PYTHONPATH := $(PYTHONPATH):$(TOP_DIR)/lib_i3c_top 3 | 4 | include $(TOP_DIR)/../common.mk 5 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_test_pkg.sv: -------------------------------------------------------------------------------- 1 | package i3c_test_pkg; 2 | // dep packages 3 | import uvm_pkg::*; 4 | import i3c_env_pkg::*; 5 | 6 | `include "i3c_base_test.sv" 7 | 8 | endpackage 9 | 10 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_test_pkg.sv: -------------------------------------------------------------------------------- 1 | package i3c_sequence_test_pkg; 2 | import uvm_pkg::*; 3 | import i3c_sequence_env_pkg::*; 4 | 5 | `include "i3c_sequence_test.sv" 6 | endpackage 7 | -------------------------------------------------------------------------------- /doc/source/index.md: -------------------------------------------------------------------------------- 1 | # {{project}} 2 | 3 | ```{toctree} 4 | :maxdepth: 2 5 | 6 | introduction 7 | overview 8 | phy 9 | dv 10 | ext_cap 11 | recovery_flow 12 | axi_id_filtering 13 | axi_recovery_flow 14 | registers 15 | ``` 16 | -------------------------------------------------------------------------------- /verification/cocotb/block/block_common.mk: -------------------------------------------------------------------------------- 1 | BLOCK_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 2 | export PYTHONPATH := $(PYTHONPATH):$(BLOCK_DIR)/lib_hci_queues:$(BLOCK_DIR)/lib_adapter 3 | 4 | include $(BLOCK_DIR)/../common.mk 5 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_test_pkg.sv: -------------------------------------------------------------------------------- 1 | package i3c_test_pkg; 2 | // dep packages 3 | import uvm_pkg::*; 4 | import i3c_env_pkg::*; 5 | 6 | `include "uvm_macros.svh" 7 | 8 | `include "i3c_base_test.sv" 9 | 10 | endpackage 11 | 12 | -------------------------------------------------------------------------------- /tools/vcd2pulseview/src/i3c_from_vcd.tcl: -------------------------------------------------------------------------------- 1 | # Add signals to the waveform 2 | set sig_list [list] 3 | lappend sig_list "sda_o" 4 | lappend sig_list "scl_o" 5 | gtkwave::addSignalsFromList $sig_list 6 | 7 | gtkwave::/File/Export/Write_VCD_File_As dump_pulseview.vcd 8 | gtkwave::/File/Quit 9 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_env_pkg.sv: -------------------------------------------------------------------------------- 1 | package i3c_env_pkg; 2 | import uvm_pkg::*; 3 | import i3c_agent_pkg::*; 4 | 5 | typedef class i3c_virtual_sequencer; 6 | `include "i3c_env_cfg.sv" 7 | `include "i3c_virtual_sequencer.sv" 8 | `include "i3c_env.sv" 9 | `include "i3c_vseq_list.sv" 10 | endpackage 11 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | SPHINXOPTS ?= 2 | SPHINXBUILD ?= sphinx-build 3 | SOURCEDIR = source 4 | BUILDDIR = build 5 | 6 | # Catch-all target: route all unknown targets to Sphinx using the "make mode" option. 7 | # $(O) is meant as a shortcut for $(SPHINXOPTS). 8 | %: 9 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 10 | -------------------------------------------------------------------------------- /verification/uvm_i2c/sec_cm_prim_count_bind.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | module sec_cm_prim_count_bind (); 6 | bind prim_count prim_count_if #(.Width(Width)) u_prim_count_if (.*); 7 | endmodule 8 | -------------------------------------------------------------------------------- /doc/source/Makefile: -------------------------------------------------------------------------------- 1 | SPHINXOPTS ?= 2 | SPHINXBUILD ?= sphinx-build 3 | SOURCEDIR = source 4 | BUILDDIR = build 5 | 6 | # Catch-all target: route all unknown targets to Sphinx using the "make mode" option. 7 | # $(O) is meant as a shortcut for $(SPHINXOPTS). 8 | %: 9 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 10 | -------------------------------------------------------------------------------- /verification/cocotb/block/hci_queues_axi/test_burst.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | # TODO: Add AXI <-> HCI QUEUES test cases to utilize burst functionality 4 | 5 | # E.g. Enqueue X elements onto Q queue by issuing a FIXED burst 6 | # of size X and verify by reading from Q 7 | 8 | # E.g. Verify behavior when burst is intermitted with reset / soft reset 9 | -------------------------------------------------------------------------------- /verification/cocotb/block/tti_queues_axi/test_burst.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | # TODO: Add AXI <-> HCI QUEUES test cases to utilize burst functionality 4 | 5 | # E.g. Enqueue X elements onto Q queue by issuing a FIXED burst 6 | # of size X and verify by reading from Q 7 | 8 | # E.g. Verify behavior when burst is intermitted with reset / soft reset 9 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/seq_lib/i2c_seq_list.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | `include "i2c_base_seq.sv" 6 | `include "i2c_device_response_seq.sv" 7 | `include "i2c_target_base_seq.sv" 8 | `include "i2c_target_may_nack_seq.sv" 9 | -------------------------------------------------------------------------------- /verification/uvm_i2c/push_pull_seq_list.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | `include "push_pull_base_seq.sv" 6 | `include "push_pull_host_seq.sv" 7 | `include "push_pull_indefinite_host_seq.sv" 8 | `include "push_pull_device_seq.sv" 9 | -------------------------------------------------------------------------------- /verification/uvm_i2c/sec_cm_prim_double_lfsr_bind.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | module sec_cm_prim_double_lfsr_bind (); 6 | bind prim_double_lfsr prim_double_lfsr_if #(.Width(LfsrDw)) u_prim_double_lfsr_if (.*); 7 | endmodule 8 | -------------------------------------------------------------------------------- /verification/testplan/block/pec.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: pec 3 | testpoints: 4 | [ 5 | { 6 | name: pec 7 | desc: 8 | ''' 9 | Pushes random bytes through the recovery_pec module, compares 10 | its computed checksum with its correspondent computed in software. 11 | ''' 12 | tests: ["pec"] 13 | tags: ["pec"] 14 | } 15 | ] 16 | } -------------------------------------------------------------------------------- /verification/uvm_i2c/mem_model_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | package mem_model_pkg; 6 | 7 | import uvm_pkg::*; 8 | 9 | `include "uvm_macros.svh" 10 | `include "dv_macros.svh" 11 | `include "mem_model.sv" 12 | 13 | endpackage 14 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_env_pkg.sv: -------------------------------------------------------------------------------- 1 | package i3c_sequence_env_pkg; 2 | import uvm_pkg::*; 3 | import i3c_agent_pkg::*; 4 | 5 | typedef class i3c_sequence_virtual_sequencer; 6 | `include "i3c_sequence_env_cfg.sv" 7 | `include "i3c_sequence_virtual_sequencer.sv" 8 | `include "i3c_sequence_env.sv" 9 | `include "i3c_sequence_vseq_list.sv" 10 | endpackage 11 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "third_party/caliptra-rtl"] 2 | path = third_party/caliptra-rtl 3 | url = https://github.com/chipsalliance/caliptra-rtl.git 4 | [submodule "third_party/cocotbext-i3c"] 5 | path = third_party/cocotbext-i3c 6 | url = https://github.com/antmicro/cocotbext-i3c.git 7 | [submodule "third_party/axi-vip"] 8 | path = third_party/axi-vip 9 | url = https://github.com/antmicro/axi-vip.git 10 | -------------------------------------------------------------------------------- /tools/i3c_config/templates/defines.txt: -------------------------------------------------------------------------------- 1 | {# templates/defines.txt #}// SPDX-License-Identifier: Apache-2.0 2 | 3 | // The following file is autogenerated with {{ generator_tool_name }} tool. 4 | 5 | `ifndef {{ cfg_guard }} 6 | `define {{ cfg_guard }} 7 | {% for name, val in defines.items() %} 8 | `define {{ name.ljust(just_level) }} {{ val }} 9 | {%- endfor %} 10 | 11 | `endif // {{ cfg_guard }} 12 | 13 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/i2c_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_sequencer extends dv_base_sequencer#(i2c_item, i2c_agent_cfg); 6 | `uvm_component_utils(i2c_sequencer) 7 | `uvm_component_new 8 | 9 | endclass : i2c_sequencer 10 | -------------------------------------------------------------------------------- /verification/uvm_i2c/alert_esc_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class alert_esc_sequencer extends dv_base_sequencer#(alert_esc_seq_item, alert_esc_agent_cfg); 6 | `uvm_component_utils(alert_esc_sequencer) 7 | 8 | `uvm_component_new 9 | 10 | endclass 11 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_reg_map.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // base register reg class which will be used to generate the reg map 6 | class dv_base_reg_map extends uvm_reg_map; 7 | `uvm_object_utils(dv_base_reg_map) 8 | `uvm_object_new 9 | endclass 10 | -------------------------------------------------------------------------------- /src/phy/bufs.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module bufs ( 4 | input logic phy_data_i, 5 | output wire phy_data_o 6 | ); 7 | 8 | logic phy_data_i_z; 9 | 10 | assign phy_data_i_z = ~phy_data_i; 11 | 12 | // Model of a Push-Pull driver 13 | buf_pp xbuf_pp ( 14 | .pull_up_en(phy_data_i), 15 | .pull_down_en(phy_data_i_z), 16 | .buf_pp_o(phy_data_o) 17 | ); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /verification/testplan/block/drivers.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: drivers 3 | testpoints: 4 | [ 5 | { 6 | name: test_drivers 7 | desc: 8 | ''' 9 | Tests the I3C PHY module. Loops through all possible states of 10 | SDA/SCL for OD and PP mode. Checks if driven data matches the 11 | bus state. 12 | ''' 13 | tests: ["drivers"] 14 | tags: ["drivers"] 15 | } 16 | ] 17 | } -------------------------------------------------------------------------------- /verification/cocotb/pyproject.toml: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | [tool.black] 4 | line-length = 100 5 | exclude = ''' 6 | ( 7 | /( 8 | | \.git 9 | | \.gitignore 10 | | \.gitmodules 11 | | \.github 12 | | \.nox 13 | | \.pytest_cache 14 | | __pycache__ 15 | | venv 16 | )/ 17 | | doc/source/conf.py 18 | ) 19 | ''' 20 | 21 | [tool.isort] 22 | profile = "black" 23 | multi_line_output = 3 24 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_tlul/tl_seq_list.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | `include "tl_host_base_seq.sv" 6 | `include "tl_host_seq.sv" 7 | `include "tl_host_single_seq.sv" 8 | `include "tl_host_custom_seq.sv" 9 | `include "tl_host_protocol_err_seq.sv" 10 | `include "tl_device_seq.sv" 11 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_agent_cov.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class dv_base_agent_cov #(type CFG_T = dv_base_agent_cfg) extends uvm_component; 6 | `uvm_component_param_utils(dv_base_agent_cov #(CFG_T)) 7 | 8 | CFG_T cfg; 9 | 10 | `uvm_component_new 11 | 12 | endclass 13 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/seq_lib/i3c_seq_list.sv: -------------------------------------------------------------------------------- 1 | `include "i3c_direct_data_seq.sv" 2 | `include "i3c_direct_data_with_rstart_seq.sv" 3 | `include "i3c_broadcast_followed_by_data_seq.sv" 4 | `include "i3c_broadcast_followed_by_data_with_rstart_seq.sv" 5 | `include "i2c_direct_data_seq.sv" 6 | `include "i2c_direct_data_with_rstart_seq.sv" 7 | `include "i3c_broadcast_followed_by_i2c_data_seq.sv" 8 | `include "i3c_broadcast_followed_by_i2c_data_with_rstart_seq.sv" 9 | -------------------------------------------------------------------------------- /doc/source/known_limitations.md: -------------------------------------------------------------------------------- 1 | # Known limitations 2 | 3 | ## Release v1p1 4 | 5 | * I3C 1.1.1 Basic specification Errata 16 and 17 are not supported - the core will accept `SETDASA` and `SETAASA` CCCs even if dynamic address is set 6 | * `SETAASA` sets only dynamic address for the main device (recovery device dynamic address is not set) 7 | * Inferred latch on the `resp_desc` signal in `flow_active.sv`. This piece of code is not used in the Caliptra configuration 8 | -------------------------------------------------------------------------------- /verification/uvm_i2c/i2c_dv_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | interface i2c_dv_if ( 6 | input logic clk, 7 | input logic rst_n 8 | ); 9 | 10 | logic [5:0] i2c_state; 11 | bit got_state; 12 | 13 | clocking cb @(posedge clk); 14 | default input #1step output #2; 15 | endclocking 16 | endinterface 17 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_sequencer.sv: -------------------------------------------------------------------------------- 1 | class i3c_sequencer extends uvm_sequencer #(.REQ(i3c_seq_item), .RSP(i3c_seq_item)); 2 | `uvm_component_utils(i3c_sequencer) 3 | 4 | i3c_agent_cfg cfg; 5 | 6 | function new (string name="", uvm_component parent=null); 7 | super.new(name, parent); 8 | endfunction : new 9 | 10 | function void build_phase(uvm_phase phase); 11 | super.build_phase(phase); 12 | endfunction : build_phase 13 | 14 | endclass : i3c_sequencer 15 | -------------------------------------------------------------------------------- /tools/reg_gen/README.md: -------------------------------------------------------------------------------- 1 | # Register generation 2 | 3 | SystemRDL description of registers is kept in [src/rdl/](../../src/rdl/) directory. Top level [registers.rdl](../../src/rdl/registers.rdl) file is an argument to the [reg_gen.py](reg_gen.py) script, which: 4 | * reads and elaborates SystemRDL files 5 | * produces SystemVerilog, C header, Markdown and HTML collateral 6 | 7 | Script [rdl_post_process.py](rdl_post_process.py) is used to add keyword `packed` to structs that should be of this type. 8 | -------------------------------------------------------------------------------- /verification/cocotb/.flake8: -------------------------------------------------------------------------------- 1 | ; Copyright (C) 2024 Antmicro 2 | ; SPDX-License-Identifier: Apache-2.0 3 | [flake8] 4 | ignore = E203, E501, W503, F403, F405 5 | max-line-length = 100 6 | max-complexity = 27 7 | select = B,C,E,F,W,T4,B9 8 | exclude = 9 | .git, 10 | .gitignore, 11 | .gitmodules, 12 | .github, 13 | .nox, 14 | .pytest_cache, 15 | __pycache__, 16 | doc/source/conf.py, 17 | venv, 18 | count = True 19 | show-source = True 20 | statistics = True 21 | -------------------------------------------------------------------------------- /verification/testplan/top/target_hdr.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: Enter and exit HDR mode 3 | testpoints: 4 | [ 5 | { 6 | name: Enter and exit HDR mode 7 | desc: 8 | ''' 9 | Issues ENTHDR0 CCC to the target, verifies that the target FSM 10 | is in IdleHDR state. Issues HDR exit pattern, verifies that 11 | the target FSM is back in Idle state. 12 | ''' 13 | tests: ["enter_exit_hdr_mode"] 14 | tags: ["top"] 15 | } 16 | ] 17 | } -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_seq_list.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // customized tl_seq_item for cmd integrity 6 | `include "cip_tl_seq_item.sv" 7 | 8 | // customized tl sequences to address integrity 9 | `include "cip_tl_host_single_seq.sv" 10 | `include "cip_tl_device_seq.sv" 11 | 12 | // vseqs 13 | `include "cip_base_vseq.sv" 14 | -------------------------------------------------------------------------------- /verification/uvm_i2c/sec_cm_prim_sparse_fsm_flop_bind.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | module sec_cm_prim_sparse_fsm_flop_bind (); 6 | `ifndef GATE_LEVEL 7 | bind prim_sparse_fsm_flop prim_sparse_fsm_flop_if #( 8 | .Width(Width), 9 | .CustomForceName(CustomForceName) 10 | ) u_prim_sparse_fsm_flop_if (.*); 11 | `endif 12 | endmodule 13 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/i3c_sequence_vseq_list.sv: -------------------------------------------------------------------------------- 1 | `include "base_vseq.sv" 2 | `include "direct_vseq.sv" 3 | `include "direct_with_rstart_vseq.sv" 4 | `include "broadcast_followed_by_data_vseq.sv" 5 | `include "broadcast_followed_by_data_with_rstart_vseq.sv" 6 | `include "direct_i2c_vseq.sv" 7 | `include "direct_i2c_with_rstart_vseq.sv" 8 | `include "broadcast_followed_by_i2c_data_vseq.sv" 9 | `include "broadcast_followed_by_i2c_data_with_rstart_vseq.sv" 10 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_core_sim.scr: -------------------------------------------------------------------------------- 1 | +incdir+verification/uvm_i3c/ 2 | +incdir+verification/uvm_i3c/i3c_core/ 3 | +incdir+verification/uvm_i3c/i3c_core/i3c_vseqs/ 4 | +incdir+verification/uvm_i3c/dv_inc/ 5 | +incdir+verification/uvm_i3c/dv_i3c/ 6 | +incdir+verification/uvm_i3c/dv_i3c/seq_lib/ 7 | 8 | verification/uvm_i3c/dv_i3c/i3c_agent_pkg.sv 9 | verification/uvm_i3c/dv_i3c/i3c_if.sv 10 | verification/uvm_i3c/i3c_core/i3c_env_pkg.sv 11 | verification/uvm_i3c/i3c_core/i3c_test_pkg.sv 12 | -------------------------------------------------------------------------------- /verification/testplan/block/descriptor_rx.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: descriptor_rx 3 | testpoints: 4 | [ 5 | { 6 | name: descriptor_rx 7 | desc: 8 | ''' 9 | Tests the descriptor_rx module responsible for generating TTI RX 10 | descriptors. The test sends N bytes to the module and verifies 11 | that it emits a valid descriptor with data length set to N. 12 | ''' 13 | tests: ["descriptor_rx"] 14 | tags: ["descriptor_rx"] 15 | } 16 | ] 17 | } -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/cov/main.sv: -------------------------------------------------------------------------------- 1 | {% import 'uvm_reg.sv' as uvm_reg with context %} 2 | {%- macro top() %} 3 | {%- for node in top_node.descendants(in_post_order=True) -%} 4 | {{child_cg(node)}} 5 | {%- endfor -%} 6 | {% endmacro -%} 7 | 8 | {% macro child_cg(node) -%} 9 | {%- if isinstance(node, RegNode) -%} 10 | {%- if not node.is_virtual -%} 11 | {{uvm_reg.cg_definition(node)}} 12 | {%- endif -%} 13 | {%- endif -%} 14 | {%- endmacro %} 15 | -------------------------------------------------------------------------------- /verification/testplan/block/ccc.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: ccc 3 | testpoints: 4 | [ 5 | { 6 | name: ccc 7 | desc: 8 | ''' 9 | Instructs the ccc module to begin servicing GETSTATUS CCC. Feeds 10 | data bytes and bits to the module via its bus_tx/bus_rx interfaces 11 | to mimic actual I3C transaction. Checks if data bytes received 12 | correspond to correct GETSTATUS CCC response. 13 | ''' 14 | tests: ["ccc"] 15 | tags: ["ccc"] 16 | } 17 | ] 18 | } -------------------------------------------------------------------------------- /verification/uvm_i2c/common_ifs_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | package common_ifs_pkg; 6 | // dep packages 7 | import uvm_pkg::*; 8 | 9 | // Enum representing reset scheme 10 | typedef enum bit [1:0] { 11 | RstAssertSyncDeassertSync, 12 | RstAssertAsyncDeassertSync, 13 | RstAssertAsyncDeassertASync 14 | } rst_scheme_e; 15 | endpackage 16 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/i2c_agent_cov.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_agent_cov extends dv_base_agent_cov #(i2c_agent_cfg); 6 | `uvm_component_utils(i2c_agent_cov) 7 | 8 | //TODO: instantiate all covergroups here 9 | function new(string name, uvm_component parent); 10 | super.new(name, parent); 11 | endfunction : new 12 | 13 | endclass 14 | -------------------------------------------------------------------------------- /verification/testplan/block/bus_timers.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: bus_timers 3 | testpoints: 4 | [ 5 | { 6 | name: get_status 7 | desc: 8 | ''' 9 | Tests the bus_timers module responsible for tracking bus free, 10 | idle and available states. Triggers the module and verifies if 11 | the signals corresponding to bus states get asserted after the 12 | required time period. 13 | ''' 14 | tests: ["bus_timers"] 15 | tags: ["bus_timers"] 16 | } 17 | ] 18 | } -------------------------------------------------------------------------------- /verification/testplan/block/flow_standby_i3c.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: flow_standby_i3c 3 | testpoints: 4 | [ 5 | { 6 | name: rx 7 | desc: 8 | ''' 9 | Tests basic operation of the flow_standby_i3c module. The test 10 | instantiates two tasks serving as BFMs for RX and TX queues. 11 | Then it simulates bus start condition followed by data reception 12 | ended by bus stop condition. 13 | ''' 14 | tests: ["rx"] 15 | tags: ["flow_standby_i3c"] 16 | } 17 | ] 18 | } -------------------------------------------------------------------------------- /verification/cocotb/caliptra_common.mk: -------------------------------------------------------------------------------- 1 | CALIPTRA_SOURCES = \ 2 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_pkg.sv \ 3 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv \ 4 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_assert.sv \ 5 | $(CALIPTRA_ROOT)/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv \ 6 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_flop.sv \ 7 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv 8 | 9 | VERILOG_SOURCES += $(CALIPTRA_SOURCES) 10 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_virtual_sequencer.sv: -------------------------------------------------------------------------------- 1 | class i3c_virtual_sequencer extends uvm_sequencer; 2 | i3c_env_cfg cfg; 3 | i3c_sequencer m_i3c_sequencer; 4 | // TODO: add AXI sequencer 5 | 6 | `uvm_component_utils(i3c_virtual_sequencer) 7 | 8 | function new (string name="", uvm_component parent=null); 9 | super.new(name, parent); 10 | endfunction : new 11 | 12 | function void build_phase(uvm_phase phase); 13 | super.build_phase(phase); 14 | endfunction 15 | 16 | endclass : i3c_virtual_sequencer 17 | -------------------------------------------------------------------------------- /verification/uvm_i2c/sec_cm_base_if_proxy.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This is the base proxy class for all the sec_cm interfaces. 6 | virtual class sec_cm_base_if_proxy extends uvm_object; 7 | sec_cm_type_e sec_cm_type; 8 | string path; 9 | 10 | `uvm_object_new 11 | 12 | pure virtual task automatic inject_fault(); 13 | pure virtual task automatic restore_fault(); 14 | endclass 15 | -------------------------------------------------------------------------------- /src/libs/mem/prim_ram_1p_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | 6 | package prim_ram_1p_pkg; 7 | 8 | typedef struct packed { 9 | logic cfg_en; 10 | logic [3:0] cfg; 11 | } cfg_t; 12 | 13 | typedef struct packed { 14 | cfg_t ram_cfg; // configuration for ram 15 | cfg_t rf_cfg; // configuration for regfile 16 | } ram_1p_cfg_t; 17 | 18 | endpackage // prim_ram_1p_pkg 19 | -------------------------------------------------------------------------------- /src/ctrl/i3c_controller_fsm.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module i3c_controller_fsm 4 | import controller_pkg::*; 5 | import i3c_pkg::*; 6 | ( 7 | input logic clk_i, 8 | input logic rst_ni, 9 | 10 | // Interface to SDA/SCL 11 | input logic ctrl_scl_i, 12 | input logic ctrl_sda_i, 13 | output logic ctrl_scl_o, 14 | output logic ctrl_sda_o 15 | ); 16 | 17 | // TODO: Implement, skipped in first round 18 | always_comb begin 19 | ctrl_sda_o = '1; 20 | ctrl_scl_o = '1; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_descriptor_rx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = descriptor_rx 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/descriptor_rx.sv 17 | 18 | include $(TEST_DIR)/../block_common.mk 19 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_descriptor_tx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = descriptor_tx 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/descriptor_tx.sv 17 | 18 | include $(TEST_DIR)/../block_common.mk 19 | -------------------------------------------------------------------------------- /verification/testplan/top/target_reset.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: target_peripheral_reset 3 | testpoints: 4 | [ 5 | { 6 | name: target_peripheral_reset 7 | desc: Issues I3C target reset pattern and verifies successful peripheral reset. 8 | tests: ["target_peripheral_reset"] 9 | tags: ["top"] 10 | } 11 | { 12 | name: target_escalated_reset 13 | desc: Issues I3C target reset patterns and verifies successful reset escalation. 14 | tests: ["target_escalated_reset"] 15 | tags: ["top"] 16 | } 17 | ] 18 | } 19 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_virtual_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class dv_base_virtual_sequencer #(type CFG_T = dv_base_env_cfg, 6 | type COV_T = dv_base_env_cov) extends uvm_sequencer; 7 | `uvm_component_param_utils(dv_base_virtual_sequencer #(CFG_T, COV_T)) 8 | 9 | CFG_T cfg; 10 | COV_T cov; 11 | 12 | `uvm_component_new 13 | 14 | endclass 15 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sim.scr: -------------------------------------------------------------------------------- 1 | +incdir+verification/uvm_i3c/dv_inc/ 2 | +incdir+verification/uvm_i3c/dv_i3c/ 3 | +incdir+verification/uvm_i3c/dv_i3c/seq_lib/ 4 | +incdir+verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/ 5 | +incdir+verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/ 6 | 7 | verification/uvm_i3c/dv_i3c/i3c_agent_pkg.sv 8 | verification/uvm_i3c/dv_i3c/i3c_if.sv 9 | verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_env_pkg.sv 10 | verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_test_pkg.sv 11 | -------------------------------------------------------------------------------- /verification/cocotb/block/axi_adapter_id_filter/i3c_cfg.yaml: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | axi: 4 | CmdFifoDepth: 64 5 | RxFifoDepth: 64 6 | TxFifoDepth: 64 7 | RespFifoDepth: 64 8 | IbiFifoDepth: 64 9 | IbiFifoExtSize: False 10 | DatDepth: 128 11 | DctDepth: 128 12 | FrontendBusInterface: "AXI" 13 | FrontendBusAddrWidth: 12 14 | FrontendBusDataWidth: 32 15 | FrontendBusUserWidth: 32 16 | FrontendBusIdWidth: 8 17 | FrontendBusIdFiltering: True 18 | NumPrivIds: 4 19 | DisableInputFF: True 20 | ControllerSupport: False 21 | TargetSupport: True -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/esc_receiver_esc_rsp_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this sequence responses to escalation pins by sending the resp pins 6 | class esc_receiver_esc_rsp_seq extends esc_receiver_base_seq; 7 | 8 | `uvm_object_utils(esc_receiver_esc_rsp_seq) 9 | `uvm_object_new 10 | 11 | constraint esc_receiver_esc_rsp_seq_c { 12 | r_esc_rsp == 1; 13 | } 14 | 15 | endclass : esc_receiver_esc_rsp_seq 16 | -------------------------------------------------------------------------------- /verification/cocotb/block/recovery_pec/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2024 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | null := 5 | space := $(null) # 6 | comma := , 7 | 8 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 9 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 10 | 11 | TEST_FILES = $(sort $(wildcard test_*.py)) 12 | 13 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 14 | TOPLEVEL = recovery_pec 15 | 16 | VERILOG_SOURCES = \ 17 | $(SRC_DIR)/recovery/recovery_pec.sv 18 | 19 | include $(TEST_DIR)/../block_common.mk 20 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_bus_timers/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = bus_timers 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 17 | $(SRC_DIR)/ctrl/bus_timers.sv \ 18 | 19 | include $(TEST_DIR)/../block_common.mk 20 | -------------------------------------------------------------------------------- /verification/testplan/block/bus_monitor.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: bus_monitor 3 | testpoints: 4 | [ 5 | { 6 | name: bus_monitor 7 | desc: 8 | ''' 9 | Tests operation of the bus_monitor module along with its sub-modules. 10 | Performs a number of I3C transactions between a simulated controller 11 | and a simulated target. Counts start, repeated start and stop events 12 | reported by bus_monitor. Verifies that the counts match what's expected. 13 | ''' 14 | tests: ["bus_monitor"] 15 | tags: ["bus_monitor"] 16 | } 17 | ] 18 | } -------------------------------------------------------------------------------- /verification/uvm_i2c/sec_cm_prim_onehot_check_bind.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | module sec_cm_prim_onehot_check_bind (); 6 | `ifndef GATE_LEVEL 7 | bind caliptra_prim_onehot_check prim_onehot_check_if #( 8 | .AddrWidth (AddrWidth), 9 | .OneHotWidth(OneHotWidth), 10 | .AddrCheck (AddrCheck), 11 | .EnableCheck(EnableCheck), 12 | .StrictCheck(StrictCheck) 13 | ) u_prim_onehot_check_if (.*); 14 | `endif 15 | endmodule 16 | -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/alert_receiver_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this sequence send ping_p and ping_n to trigger ping signals 6 | class alert_receiver_seq extends alert_receiver_base_seq; 7 | 8 | `uvm_object_utils(alert_receiver_seq) 9 | 10 | `uvm_object_new 11 | 12 | constraint alert_receiver_seq_c { 13 | r_alert_ping_send == 1; 14 | r_alert_rsp == 0; 15 | } 16 | 17 | endclass : alert_receiver_seq 18 | -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/alert_sender_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this sequence send the alert pins to the receiver 6 | class alert_sender_seq extends alert_sender_base_seq; 7 | 8 | `uvm_object_utils(alert_sender_seq) 9 | `uvm_object_new 10 | 11 | constraint alert_sender_seq_c { 12 | s_alert_send == 1; 13 | s_alert_ping_rsp == 0; 14 | ping_timeout == 0; 15 | } 16 | 17 | endclass : alert_sender_seq 18 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_edge_detector/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = edge_detector 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 17 | $(SRC_DIR)/ctrl/edge_detector.sv 18 | 19 | include $(TEST_DIR)/../block_common.mk 20 | -------------------------------------------------------------------------------- /verification/cocotb/block/bus_tx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = bus_tx_test_wrapper 14 | 15 | EXTRA_ARGS += 16 | 17 | VERILOG_SOURCES = \ 18 | $(SRC_DIR)/ctrl/bus_tx.sv \ 19 | $(TEST_DIR)/bus_tx_test_wrapper.sv 20 | 21 | include $(TEST_DIR)/../block_common.mk 22 | -------------------------------------------------------------------------------- /verification/cocotb/block/width_converter_8toN/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2024 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | null := 5 | space := $(null) # 6 | comma := , 7 | 8 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 9 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 10 | 11 | TEST_FILES = $(sort $(wildcard test_*.py)) 12 | 13 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 14 | TOPLEVEL = width_converter_8toN 15 | 16 | VERILOG_SOURCES = \ 17 | $(SRC_DIR)/ctrl/width_converter_8toN.sv 18 | 19 | include $(TEST_DIR)/../block_common.mk 20 | -------------------------------------------------------------------------------- /verification/cocotb/block/width_converter_Nto8/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2024 Antmicro 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | null := 5 | space := $(null) # 6 | comma := , 7 | 8 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 9 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 10 | 11 | TEST_FILES = $(sort $(wildcard test_*.py)) 12 | 13 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 14 | TOPLEVEL = width_converter_Nto8 15 | 16 | VERILOG_SOURCES = \ 17 | $(SRC_DIR)/ctrl/width_converter_Nto8.sv 18 | 19 | include $(TEST_DIR)/../block_common.mk 20 | -------------------------------------------------------------------------------- /verification/uvm_i2c/i2c_test_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | package i2c_test_pkg; 6 | // dep packages 7 | import uvm_pkg::*; 8 | import dv_utils_pkg::*; 9 | import cip_base_pkg::*; 10 | import i2c_env_pkg::*; 11 | 12 | // macro includes 13 | `include "uvm_macros.svh" 14 | `include "dv_macros.svh" 15 | 16 | // local types 17 | 18 | // functions 19 | 20 | // package sources 21 | `include "i2c_base_test.sv" 22 | 23 | endpackage 24 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_virtual_sequencer.sv: -------------------------------------------------------------------------------- 1 | class i3c_sequence_virtual_sequencer extends uvm_sequencer; 2 | i3c_sequence_env_cfg m_cfg; 3 | i3c_sequencer m_i3c_sequencer_dev; 4 | i3c_sequencer m_i3c_sequencer_host; 5 | 6 | `uvm_component_utils(i3c_sequence_virtual_sequencer) 7 | 8 | function new (string name="", uvm_component parent=null); 9 | super.new(name, parent); 10 | endfunction : new 11 | 12 | function void build_phase(uvm_phase phase); 13 | super.build_phase(phase); 14 | endfunction 15 | 16 | endclass : i3c_sequence_virtual_sequencer 17 | -------------------------------------------------------------------------------- /tools/uvm/install-uvm.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Directories created with this script should be removed with `make clean` 4 | # TODO: Connect to Makefiles' installation directory variable, 5 | # so that user can select installation directory 6 | install(){ 7 | NAME=$1 8 | URL=$2 9 | wget -O uvm-1.2.tar.gz $URL 10 | tar -xf uvm-1.2.tar.gz --strip-components=1 --one-top-level=$NAME/ 11 | rm -f uvm-1.2.tar.gz 12 | } 13 | 14 | install generic https://www.accellera.org/images/downloads/standards/uvm/uvm-1.2.tar.gz 15 | install verilator https://github.com/antmicro/uvm-verilator/archive/refs/heads/current-patches.tar.gz 16 | -------------------------------------------------------------------------------- /tools/verible-scripts/README.md: -------------------------------------------------------------------------------- 1 | # Verible scripts 2 | 3 | [verible.py](verible.py) is a python wrapper for executing [formatter]((https://github.com/chipsalliance/verible/blob/master/verilog/tools/formatter/README.md)) and [linter]((https://github.com/chipsalliance/verible/blob/master/verilog/tools/lint/README.md)) from the Verible project. 4 | 5 | [stats_lint.py](stats_lint.py) is a python script to process log file created from the linting process. 6 | 7 | [run.sh](run.sh) is a BASH script, which defines usage of the Verible tools in this project. This script is meant to be run from the root directory of this project via `make lint-rtl`. 8 | 9 | -------------------------------------------------------------------------------- /verification/cocotb/block/flow_standby_i3c/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = flow_standby_i3c 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 17 | $(SRC_DIR)/i3c_pkg.sv \ 18 | $(SRC_DIR)/ctrl/flow_standby_i3c.sv 19 | 20 | include $(TEST_DIR)/../block_common.mk 21 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_target_stress_rd_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_target_stress_rd_vseq extends i2c_target_smoke_vseq; 6 | `uvm_object_utils(i2c_target_stress_rd_vseq) 7 | `uvm_object_new 8 | 9 | constraint num_trans_c { num_trans inside {[1 : 5]}; } 10 | 11 | virtual task pre_start(); 12 | super.pre_start(); 13 | cfg.min_data = 100; 14 | cfg.max_data = 200; 15 | cfg.wr_pct = 0; 16 | cfg.slow_txq = 1; 17 | endtask 18 | endclass 19 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_target_stress_wr_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_target_stress_wr_vseq extends i2c_target_smoke_vseq; 6 | `uvm_object_utils(i2c_target_stress_wr_vseq) 7 | `uvm_object_new 8 | 9 | constraint num_trans_c { num_trans inside {[1 : 5]}; } 10 | 11 | virtual task pre_start(); 12 | super.pre_start(); 13 | cfg.min_data = 80; 14 | cfg.max_data = 200; 15 | cfg.rd_pct = 0; 16 | cfg.slow_acq = 1; 17 | endtask 18 | endclass 19 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_tlul/tl_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class tl_sequencer extends dv_base_sequencer#(tl_seq_item, tl_agent_cfg); 6 | `uvm_component_utils(tl_sequencer) 7 | 8 | uvm_tlm_analysis_fifo#(tl_seq_item) a_chan_req_fifo; 9 | 10 | `uvm_component_new 11 | 12 | function void build_phase(uvm_phase phase); 13 | super.build_phase(phase); 14 | a_chan_req_fifo = new("a_chan_req_fifo", this); 15 | endfunction : build_phase 16 | 17 | endclass : tl_sequencer 18 | -------------------------------------------------------------------------------- /tools/cocotb_helpers/pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools"] 3 | build-backend = "setuptools.build_meta" 4 | 5 | [project] 6 | name = "cocotb-helpers" 7 | version = "0.1.0" 8 | dependencies = [ 9 | "cocotb", 10 | ] 11 | requires-python = ">=3.11" 12 | 13 | authors = [ 14 | {name = "Antmicro", email = "contact@antmicro.com"} 15 | ] 16 | 17 | description = "Utilities for running tests with cocotb" 18 | readme = "README.md" 19 | license = {file = "LICENSE.txt"} 20 | 21 | keywords = ["cocotb", "tools", "utilities"] 22 | 23 | classifiers = [ 24 | "Development Status :: 3 - Alpha", 25 | "Programming Language :: Python" 26 | ] 27 | -------------------------------------------------------------------------------- /verification/testplan/block/descriptor_tx.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: descriptor_tx 3 | testpoints: 4 | [ 5 | { 6 | name: descriptor_tx 7 | desc: 8 | ''' 9 | Tests the descriptor_tx module responsible for processing TTI TX 10 | descriptors and controlling TTI data flow during I3C private 11 | reads. Sends a descriptor to the module followed with the right 12 | amount of data. Verifies that the module accepted the descriptor 13 | and allowed the right amount of data bytes to pass through it. 14 | ''' 15 | tests: ["descriptor_tx"] 16 | tags: ["descriptor_tx"] 17 | } 18 | ] 19 | } -------------------------------------------------------------------------------- /verification/uvm_i2c/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors (OpenTitan project). 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | 6 | # Remove leading "# " from the front of log file lines and run the test if not in gui mode. 7 | # This provides compatibility for log file error checking with other supported simulators within Opentitan. 8 | set gui 0 9 | if {[info exists ::env(GUI)]} { 10 | set gui "$::env(GUI)" 11 | } 12 | 13 | if {$gui == 0} { 14 | set PrefMain(LinePrefix) "" 15 | run -all 16 | quit 17 | } else { 18 | set PrefMain(LinePrefix) "" 19 | } 20 | -------------------------------------------------------------------------------- /verification/uvm_i3c/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors (OpenTitan project). 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | 6 | # Remove leading "# " from the front of log file lines and run the test if not in gui mode. 7 | # This provides compatibility for log file error checking with other supported simulators within Opentitan. 8 | set gui 0 9 | if {[info exists ::env(GUI)]} { 10 | set gui "$::env(GUI)" 11 | } 12 | 13 | if {$gui == 0} { 14 | set PrefMain(LinePrefix) "" 15 | run -all 16 | quit 17 | } else { 18 | set PrefMain(LinePrefix) "" 19 | } 20 | 21 | -------------------------------------------------------------------------------- /verification/cocotb/block/bus_rx_flow/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = bus_rx_flow_test_wrapper 14 | 15 | EXTRA_ARGS += 16 | 17 | VERILOG_SOURCES = \ 18 | $(SRC_DIR)/libs/i3c_sva.svh \ 19 | $(SRC_DIR)/ctrl/bus_rx_flow.sv \ 20 | $(TEST_DIR)/bus_rx_flow_test_wrapper.sv 21 | 22 | include $(TEST_DIR)/../block_common.mk 23 | -------------------------------------------------------------------------------- /verification/cocotb/block/bus_tx_flow/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = bus_tx_flow_test_wrapper 14 | 15 | EXTRA_ARGS += 16 | 17 | VERILOG_SOURCES = \ 18 | $(SRC_DIR)/ctrl/bus_tx.sv \ 19 | $(SRC_DIR)/ctrl/bus_tx_flow.sv \ 20 | $(TEST_DIR)/bus_tx_flow_test_wrapper.sv 21 | 22 | include $(TEST_DIR)/../block_common.mk 23 | -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/smp/main.sv: -------------------------------------------------------------------------------- 1 | {%- import 'uvm_reg.sv' as uvm_reg with context -%} 2 | {%- macro top() -%} 3 | {%- for node in top_node.descendants(in_post_order=True) -%} 4 | {{child_smp(node)}} 5 | {%- endfor -%} 6 | {%- endmacro -%} 7 | 8 | {%- macro child_smp(node) -%} 9 | {%- if isinstance(node, RegNode) -%} 10 | {% if not node.is_virtual %} 11 | {{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"SAMPLE FUNCTIONS -----------------------*/"}} 12 | {{uvm_reg.function_sample_def(node)}} 13 | {{uvm_reg.function_sample_values_def(node)}} 14 | {%- endif %} 15 | {%- endif -%} 16 | {%- endmacro %} 17 | -------------------------------------------------------------------------------- /tools/vcd2pulseview/src/pulseview.cfg: -------------------------------------------------------------------------------- 1 | # Minimal config for PulseView to load I2C decoder while keeping the waveform 2 | # on the screen 3 | 4 | # Allow enabling the I2C decoder and align the view 5 | [General] 6 | decode_signals=1 7 | views=1 8 | 9 | # Enable the I2C decoder 10 | [decode_signal0] 11 | channel0\assigned_signal_name=scl_o 12 | channel0\initial_pin_state=2 13 | channel0\name=SCL 14 | channel1\assigned_signal_name=sda_o 15 | channel1\initial_pin_state=2 16 | channel1\name=SDA 17 | channels=2 18 | decoder0\id=i2c 19 | decoders=1 20 | enabled=true 21 | name=I\xb2\x43 22 | 23 | # Center and zoom the waveform 24 | [view0] 25 | scale=2e-09 26 | v_offset=-100 27 | -------------------------------------------------------------------------------- /verification/uvm_i2c/i2c_port_conv.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Convert i2c's o/oe signaling to an inout port for easier integration 6 | module i2c_port_conv ( 7 | input scl_oe_i, 8 | input sda_oe_i, 9 | output logic scl_o, 10 | output logic sda_o, 11 | inout wire scl_io, 12 | inout wire sda_io 13 | ); 14 | 15 | assign scl_o = scl_io; 16 | assign sda_o = sda_io; 17 | assign scl_io = scl_oe_i ? 1'b0 : 1'bz; 18 | assign sda_io = sda_oe_i ? 1'b0 : 1'bz; 19 | 20 | endmodule // i2c_port_conv 21 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_target_stretch_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_target_stretch_vseq extends i2c_target_smoke_vseq; 6 | `uvm_object_utils(i2c_target_stretch_vseq) 7 | `uvm_object_new 8 | 9 | constraint num_trans_c { num_trans inside {[1 : 5]}; } 10 | 11 | virtual task pre_start(); 12 | super.pre_start(); 13 | cfg.min_data = 100; 14 | cfg.max_data = 200; 15 | cfg.slow_acq = 1; 16 | cfg.slow_txq = 1; 17 | endtask 18 | endclass // i2c_target_stretch_vseq 19 | -------------------------------------------------------------------------------- /verification/uvm_i2c/push_pull_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class push_pull_sequencer #(parameter int HostDataWidth = 32, 6 | parameter int DeviceDataWidth = HostDataWidth) 7 | extends dv_base_sequencer #( 8 | .ITEM_T (push_pull_item#(HostDataWidth, DeviceDataWidth)), 9 | .CFG_T (push_pull_agent_cfg#(HostDataWidth, DeviceDataWidth)) 10 | ); 11 | `uvm_component_param_utils(push_pull_sequencer#(HostDataWidth, DeviceDataWidth)) 12 | `uvm_component_new 13 | 14 | endclass 15 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__ 2 | !*.schema.json 3 | .nox/ 4 | .pre-commit-config.yaml 5 | *.csv 6 | *.dat 7 | *.egg-info 8 | *.exe 9 | *.info 10 | *.ipynb 11 | *.json 12 | *.log 13 | *.rpt 14 | *.swp 15 | *.sym 16 | *.vcd 17 | *.vpd 18 | *.xml 19 | build/ 20 | configs/ 21 | dsim_metrics.db 22 | dsim_work/ 23 | dsim-build 24 | dsim.env 25 | i3cPHYsim_icarus 26 | i3cPHYsim_verilator 27 | obj_dir/ 28 | program.hex 29 | questa_work/ 30 | results.xml 31 | sim_build/ 32 | sim/ 33 | src/csr/html/ 34 | src/csr/md/ 35 | src/rdl/docs/html* 36 | sw/ 37 | tools/uvm/generic 38 | tools/uvm/verilator 39 | uvm-1.2*/ 40 | vcs_work/ 41 | venv/ 42 | verification/tools/i3c_defines.svh 43 | work/ 44 | ucli.key 45 | -------------------------------------------------------------------------------- /tools/timing/utils.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | import logging 4 | import math 5 | 6 | 7 | def setup_logger(level=logging.INFO, filename="log.log"): 8 | logging.basicConfig( 9 | level=level, handlers=[logging.FileHandler(filename), logging.StreamHandler()] 10 | ) 11 | 12 | 13 | def f2T(freq): 14 | T = 1 / freq 15 | return T 16 | 17 | 18 | def T2f(T): 19 | freq = 1 / T 20 | return freq 21 | 22 | 23 | def f2halfT(freq): 24 | T = f2T(freq) 25 | return 0.5 * T 26 | 27 | 28 | def norm_ceil(val, period): 29 | return math.ceil(val / period) 30 | 31 | 32 | def cycles2seconds(val, period): 33 | return val * period 34 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_mubi_cov_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | interface cip_mubi_cov_if #(parameter int Width = 4) (input [Width-1:0] mubi, input rst_ni); 6 | import uvm_pkg::*; 7 | import dv_base_reg_pkg::*; 8 | 9 | dv_base_mubi_cov mubi_cov; 10 | initial begin 11 | mubi_cov = dv_base_mubi_cov::type_id::create($sformatf("%m")); 12 | mubi_cov.create_cov(Width); 13 | forever begin 14 | @(mubi or rst_ni); 15 | if (rst_ni === 1) mubi_cov.sample(mubi); 16 | end 17 | end 18 | endinterface 19 | -------------------------------------------------------------------------------- /verification/cocotb/block/i3c_target_fsm/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = i3c_target_fsm_test_wrapper 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/i3c_pkg.sv \ 17 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 18 | $(SRC_DIR)/ctrl/i3c_target_fsm.sv \ 19 | $(TEST_DIR)/i3c_target_fsm_test_wrapper.sv 20 | 21 | include $(TEST_DIR)/../block_common.mk 22 | -------------------------------------------------------------------------------- /tools/nox_utils/pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools"] 3 | build-backend = "setuptools.build_meta" 4 | 5 | [project] 6 | name = "nox-utils" 7 | version = "0.1.0" 8 | dependencies = [ 9 | "nox", 10 | ] 11 | requires-python = ">=3.11" 12 | 13 | authors = [ 14 | {name = "Michal Czyz", email = "mczyz@antmicro.com"}, 15 | {name = "Antmicro", email = "contact@antmicro.com"} 16 | ] 17 | 18 | description = "Utilities for running tests with nox" 19 | readme = "README.md" 20 | license = {file = "LICENSE.txt"} 21 | 22 | keywords = ["nox", "cocotb", "tools", "utilities"] 23 | 24 | classifiers = [ 25 | "Development Status :: 3 - Alpha", 26 | "Programming Language :: Python" 27 | ] 28 | -------------------------------------------------------------------------------- /verification/cocotb/block/flow_standby_i2c/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = flow_standby_i2c_harness 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 17 | $(SRC_DIR)/i3c_pkg.sv \ 18 | $(SRC_DIR)/ctrl/flow_standby_i2c.sv \ 19 | $(TEST_DIR)/flow_standby_i2c_harness.sv 20 | 21 | 22 | include $(TEST_DIR)/../block_common.mk 23 | -------------------------------------------------------------------------------- /verification/uvm_i2c/tlul/tlul_data_integ_enc.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | `include "caliptra_prim_assert.sv" 6 | 7 | /** 8 | * Data integrity encoder for bus integrity scheme 9 | */ 10 | 11 | module tlul_data_integ_enc import tlul_pkg::*; ( 12 | // TL-UL interface 13 | input [DataMaxWidth-1:0] data_i, 14 | output logic [DataMaxWidth+DataIntgWidth-1:0] data_intg_o 15 | ); 16 | 17 | prim_secded_inv_39_32_enc u_data_gen ( 18 | .data_i, 19 | .data_o(data_intg_o) 20 | ); 21 | 22 | endmodule : tlul_data_integ_enc 23 | -------------------------------------------------------------------------------- /verification/cocotb/block/i2c_target_fsm/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = i2c_target_fsm_harness 14 | 15 | EXTRA_ARGS += -Wno-WIDTHTRUNC -Wno-WIDTHEXPAND 16 | 17 | VERILOG_SOURCES = \ 18 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 19 | $(SRC_DIR)/ctrl/i2c_target_fsm.sv \ 20 | $(TEST_DIR)/i2c_target_fsm_harness.sv 21 | 22 | include $(TEST_DIR)/../block_common.mk 23 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_mubi_cov_wrapper.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This is a wrapper module for IPs to bind an array of mubi types port. 6 | module cip_mubi_cov_wrapper 7 | #( 8 | parameter int NumMubis = 1, 9 | parameter int Width = 4 // parameter for cip_mubi_cov_if module 10 | ) ( 11 | input [NumMubis-1:0][Width-1:0] mubis, 12 | input rst_ni 13 | ); 14 | 15 | for (genvar k = 0; k < NumMubis; k++) begin : gen_mubi_cov_if 16 | cip_mubi_cov_if#(Width) mubi_cov_if(.mubi(mubis[k]), .rst_ni(rst_ni)); 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /verification/cocotb/block/ccc/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = ccc 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/i3c_pkg.sv \ 17 | $(SRC_DIR)/csr/I3CCSR_pkg.sv \ 18 | $(SRC_DIR)/csr/I3CCSR.sv \ 19 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 20 | $(SRC_DIR)/ctrl/ccc_entdaa.sv \ 21 | $(SRC_DIR)/ctrl/ccc.sv 22 | 23 | include $(TEST_DIR)/../block_common.mk 24 | -------------------------------------------------------------------------------- /src/i3c_defines.svh: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | // The following file is autogenerated with py2svh.py tool. 4 | 5 | `ifndef I3C_CONFIG 6 | `define I3C_CONFIG 7 | 8 | `define CMD_FIFO_DEPTH 64 9 | `define RX_FIFO_DEPTH 64 10 | `define TX_FIFO_DEPTH 64 11 | `define RESP_FIFO_DEPTH 64 12 | `define IBI_FIFO_DEPTH 64 13 | `define DAT_DEPTH 128 14 | `define DCT_DEPTH 128 15 | `define I3C_USE_AXI 1 16 | `define AXI_ADDR_WIDTH 12 17 | `define AXI_DATA_WIDTH 32 18 | `define AXI_USER_WIDTH 32 19 | `define AXI_ID_WIDTH 8 20 | `define AXI_ID_FILTERING 1 21 | `define NUM_PRIV_IDS 4 22 | `define TARGET_SUPPORT 1 23 | 24 | `endif // I3C_CONFIG 25 | -------------------------------------------------------------------------------- /verification/uvm_i2c/prim_lib/prim_esc_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | package prim_esc_pkg; 6 | 7 | typedef struct packed { 8 | logic esc_p; 9 | logic esc_n; 10 | } esc_tx_t; 11 | 12 | typedef struct packed { 13 | logic resp_p; 14 | logic resp_n; 15 | } esc_rx_t; 16 | 17 | parameter esc_tx_t ESC_TX_DEFAULT = '{esc_p: 1'b0, 18 | esc_n: 1'b1}; 19 | 20 | parameter esc_rx_t ESC_RX_DEFAULT = '{resp_p: 1'b0, 21 | resp_n: 1'b1}; 22 | 23 | endpackage : prim_esc_pkg 24 | -------------------------------------------------------------------------------- /src/phy/buf_pp.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | /* 4 | Model of a Push-Pull Driver 5 | 6 | | pu | pd | out | 7 | ----------------- 8 | | 0 | 0| x | 9 | | 0 | 1| 0 | 10 | | 1 | 0| 1 | 11 | | 1 | 1| x | 12 | 13 | */ 14 | module buf_pp ( 15 | input logic pull_up_en, 16 | input logic pull_down_en, 17 | output logic buf_pp_o 18 | ); 19 | 20 | always_comb begin : drive_push_pull 21 | case ({ 22 | pull_up_en, pull_down_en 23 | }) 24 | 2'b00: buf_pp_o = 1'bx; 25 | 2'b01: buf_pp_o = 1'b0; 26 | 2'b10: buf_pp_o = 1'b1; 27 | 2'b11: buf_pp_o = 1'bx; 28 | default: buf_pp_o = 1'bx; 29 | endcase 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /verification/cocotb/block/i2c_controller_fsm/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = i2c_controller_fsm 14 | 15 | VERILOG_SOURCES = \ 16 | ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh \ 17 | ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_assert.sv \ 18 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 19 | $(SRC_DIR)/ctrl/i2c_controller_fsm.sv 20 | 21 | 22 | include $(TEST_DIR)/../block_common.mk 23 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_lc_tx_cov_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | interface cip_lc_tx_cov_if(input [3:0] val, input rst_ni); 6 | import uvm_pkg::*; 7 | import dv_base_reg_pkg::*; 8 | 9 | typedef mubi_cov #(.Width(4), 10 | .ValueTrue(lc_ctrl_pkg::On), 11 | .ValueFalse(lc_ctrl_pkg::Off)) lc_tx_cov; 12 | lc_tx_cov cov; 13 | initial begin 14 | cov = lc_tx_cov::type_id::create($sformatf("%m")); 15 | forever begin 16 | @(val or rst_ni); 17 | if (rst_ni === 1) cov.sample(val); 18 | end 19 | end 20 | endinterface 21 | -------------------------------------------------------------------------------- /verification/cocotb/top/lib_i3c_top/i3c_bus_harness.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | /* 4 | I3C Bus Harness 5 | 6 | Model the tristate bus. 7 | Number of controllers and targets is configurable. 8 | 9 | Verilator does not simulate 'x' and 'z' natively. 10 | All inputs of the bus are ANDed to simulate the Open-Drain Driver behavior. 11 | 12 | */ 13 | module i3c_bus_harness #( 14 | parameter int unsigned NumDevices = 3 // Joint number of Controller and Target devices 15 | ) ( 16 | input wire [NumDevices-1:0] sda_i, 17 | input wire [NumDevices-1:0] scl_i, 18 | 19 | output wire sda_o, 20 | output wire scl_o 21 | ); 22 | 23 | assign sda_o = &sda_i; 24 | assign scl_o = &scl_i; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_bus_monitor/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = bus_monitor_wrapper 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/i3c_pkg.sv \ 17 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 18 | $(SRC_DIR)/ctrl/edge_detector.sv \ 19 | $(SRC_DIR)/ctrl/stable_high_detector.sv \ 20 | $(SRC_DIR)/ctrl/bus_monitor.sv \ 21 | $(TEST_DIR)/bus_monitor_wrapper.sv 22 | 23 | include $(TEST_DIR)/../block_common.mk 24 | -------------------------------------------------------------------------------- /tools/verible-scripts/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | ROOT_DIR=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." &>/dev/null && pwd) 6 | 7 | echo "[LINT] See exec_lint.log" 8 | python tools/verible-scripts/verible.py --tool=lint --root_dir="${ROOT_DIR}"/src &> exec_lint.log 9 | python tools/verible-scripts/verible.py --tool=lint --root_dir="${ROOT_DIR}"/verification/block &>> exec_lint.log 10 | 11 | echo "[FORMAT] See exec_format.log" 12 | python tools/verible-scripts/verible.py --tool=format --root_dir="${ROOT_DIR}"/src &> exec_format.log 13 | python tools/verible-scripts/verible.py --tool=format --root_dir="${ROOT_DIR}"/verification/block &>> exec_format.log 14 | 15 | echo "[LINT STATS] See lint.rpt" 16 | python tools/verible-scripts/stats_lint.py &> lint.rpt 17 | 18 | cat lint.rpt 19 | -------------------------------------------------------------------------------- /verification/cocotb/block/i2c_standby_controller/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = controller_standby_i2c_harness 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 17 | $(SRC_DIR)/i3c_pkg.sv \ 18 | ${SRC_DIR}/ctrl/i2c_target_fsm.sv \ 19 | ${SRC_DIR}/ctrl/flow_standby_i2c.sv \ 20 | ${SRC_DIR}/ctrl/controller_standby_i2c.sv \ 21 | $(TEST_DIR)/controller_standby_i2c_harness.sv 22 | 23 | include $(TEST_DIR)/../block_common.mk 24 | -------------------------------------------------------------------------------- /src/libs/serializer.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | module serializer 4 | import i3c_ctrl_pkg::*; 5 | #( 6 | parameter int DATA_W = 9 7 | ) ( 8 | input logic clk, 9 | input logic rst_n, 10 | input logic load, 11 | input logic enable, 12 | input logic [DATA_W-1:0] data, 13 | output logic q 14 | ); 15 | 16 | logic [DATA_W-1:0] sr; 17 | 18 | always_ff @(posedge clk or negedge rst_n) begin : proc_fsm 19 | if (!rst_n) begin 20 | sr <= '0; 21 | end else begin 22 | if (load) begin 23 | sr <= data; 24 | end else begin 25 | if (enable) begin 26 | sr[DATA_W-1] <= '0; 27 | sr[DATA_W-2:0] <= sr[DATA_W-1:1]; 28 | end 29 | end 30 | end 31 | end 32 | 33 | assign q = sr[0]; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /verification/testplan/block/bus_rx_flow.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: bus_rx_flow 3 | testpoints: 4 | [ 5 | { 6 | name: multiple_bit_reads 7 | desc: 8 | ''' 9 | Drives SCL line with a steady clock, issues multiple bit read 10 | requests, verifies that the module returns correct data sampled 11 | from the SDA line. 12 | ''' 13 | tests: ["multiple_bit_reads"] 14 | tags: ["bus_rx_flow"] 15 | } 16 | { 17 | name: multiple_byte_reads 18 | desc: 19 | ''' 20 | Drives SCL line with a steady clock, issues multiple byte read 21 | requests, verifies that the module returns correct data sampled 22 | from the SDA line. 23 | ''' 24 | tests: ["multiple_byte_reads"] 25 | tags: ["bus_rx_flow"] 26 | } 27 | ] 28 | } -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_tlul/tl_host_custom_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Disable TL protocol related constraint on a_chan to create a fully customized tl_item for error 6 | // cases 7 | class tl_host_custom_seq #(type REQ_T = tl_seq_item) extends tl_host_single_seq #(REQ_T); 8 | 9 | `uvm_object_param_utils(tl_host_custom_seq #(REQ_T)) 10 | `uvm_object_new 11 | 12 | virtual function void randomize_req(REQ req, int idx); 13 | control_addr_alignment = 1; 14 | control_rand_size = 1; 15 | control_rand_opcode = 1; 16 | req.disable_a_chan_protocol_constraint(); 17 | super.randomize_req(req, idx); 18 | endfunction 19 | 20 | endclass 21 | -------------------------------------------------------------------------------- /verification/uvm_i2c/tlul/tlul_data_integ_dec.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | `include "caliptra_prim_assert.sv" 6 | 7 | /** 8 | * Data integrity decoder for bus integrity scheme 9 | */ 10 | 11 | module tlul_data_integ_dec import tlul_pkg::*; ( 12 | // TL-UL interface 13 | input [DataMaxWidth+DataIntgWidth-1:0] data_intg_i, 14 | output logic data_err_o 15 | ); 16 | 17 | logic [1:0] data_err; 18 | prim_secded_inv_39_32_dec u_data_chk ( 19 | .data_i(data_intg_i), 20 | .data_o(), 21 | .syndrome_o(), 22 | .err_o(data_err) 23 | ); 24 | 25 | assign data_err_o = |data_err; 26 | 27 | endmodule : tlul_data_integ_dec 28 | -------------------------------------------------------------------------------- /verification/uvm_i2c/i2c_bind.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | module i2c_bind; 6 | 7 | bind i2c tlul_assert #( 8 | .EndpointType("Device") 9 | ) tlul_assert_device ( 10 | .clk_i, 11 | .rst_ni, 12 | .h2d (tl_i), 13 | .d2h (tl_o) 14 | ); 15 | 16 | bind i2c i2c_csr_assert_fpv i2c_csr_assert ( 17 | .clk_i, 18 | .rst_ni, 19 | .h2d (tl_i), 20 | .d2h (tl_o) 21 | ); 22 | 23 | bind i2c i2c_protocol_cov u_i2c_protocol_cov( 24 | .clk (clk_i), 25 | .rst_n (rst_ni), 26 | .scl (cio_scl_i), 27 | .sda (cio_sda_i), 28 | .intr_cmd_complete (intr_cmd_complete_o), 29 | .intr_tx_stretch (intr_tx_stretch_o) 30 | ); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /verification/uvm_i2c/top_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | 6 | package top_pkg; 7 | 8 | localparam int TL_AW=32; 9 | localparam int TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two 10 | localparam int TL_AIW=8; // a_source, d_source 11 | localparam int TL_DIW=1; // d_sink 12 | localparam int TL_AUW=21; // a_user 13 | localparam int TL_DUW=14; // d_user 14 | localparam int TL_DBW=(TL_DW>>3); 15 | localparam int TL_SZW=$clog2($clog2(TL_DBW)+1); 16 | 17 | // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE 18 | // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED FOR 19 | // PRODUCTION DEVICES. 20 | localparam int SecVolatileRawUnlockEn = 0; 21 | 22 | endpackage 23 | -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_ahb/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | FILELIST ?= $(I3C_ROOT_DIR)/src/i3c.f 10 | 11 | TEST_FILES = $(sort $(wildcard test_*.py)) 12 | 13 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 14 | TOPLEVEL = i3c_test_wrapper 15 | override CFG_NAME = ahb 16 | 17 | # Set appropriate bus interface via Cocotb's PLUSARGS: 18 | override PLUSARGS := $(strip +FrontendBusInterface=AHB $(PLUSARGS)) 19 | 20 | EXTRA_ARGS += -f $(FILELIST) $(I3C_ROOT_DIR)/verification/cocotb/top/lib_i3c_top/i3c_bus_harness.sv $(I3C_ROOT_DIR)/verification/cocotb/top/lib_i3c_top/i3c_test_wrapper.sv 21 | 22 | include $(TEST_DIR)/../top_common.mk 23 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_tlul/tl_host_protocol_err_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This seq will send an item that triggers d_error due to protocol violation 6 | class tl_host_protocol_err_seq #(type REQ_T = tl_seq_item) extends tl_host_single_seq #(REQ_T); 7 | 8 | `uvm_object_param_utils(tl_host_protocol_err_seq #(REQ_T)) 9 | `uvm_object_new 10 | 11 | // forever randomize the item until we find one that violates the TL protocol 12 | virtual function void randomize_req(REQ req, int idx); 13 | req.a_valid_delay = $urandom_range(min_req_delay, max_req_delay); 14 | req.a_valid_delay.rand_mode(0); 15 | req.randomize_a_chan_with_protocol_error(); 16 | endfunction 17 | 18 | endclass 19 | -------------------------------------------------------------------------------- /verification/cocotb/top/i3c_axi/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | FILELIST ?= $(I3C_ROOT_DIR)/src/i3c.f 10 | 11 | TEST_FILES = $(sort $(wildcard test_*.py)) 12 | 13 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 14 | TOPLEVEL = i3c_test_wrapper 15 | override CFG_NAME = axi_bypass 16 | 17 | # Set appropriate bus interface via Cocotb's PLUSARGS: 18 | override PLUSARGS := $(strip +FrontendBusInterface=AXI $(PLUSARGS)) 19 | 20 | EXTRA_ARGS += -f $(FILELIST) $(I3C_ROOT_DIR)/verification/cocotb/top/lib_i3c_top/i3c_bus_harness.sv $(I3C_ROOT_DIR)/verification/cocotb/top/lib_i3c_top/i3c_test_wrapper.sv 21 | 22 | include $(TEST_DIR)/../top_common.mk 23 | -------------------------------------------------------------------------------- /src/ctrl/controller_standby_i3c.f: -------------------------------------------------------------------------------- 1 | +incdir+${I3C_ROOT_DIR}/src 2 | ${I3C_ROOT_DIR}/src/ctrl/controller_pkg.sv 3 | ${I3C_ROOT_DIR}/src/i3c_pkg.sv 4 | ${I3C_ROOT_DIR}/src/ctrl/bus_monitor.sv 5 | ${I3C_ROOT_DIR}/src/ctrl/bus_rx_flow.sv 6 | ${I3C_ROOT_DIR}/src/ctrl/bus_tx.sv 7 | ${I3C_ROOT_DIR}/src/ctrl/bus_tx_flow.sv 8 | ${I3C_ROOT_DIR}/src/ctrl/edge_detector.sv 9 | ${I3C_ROOT_DIR}/src/ctrl/stable_high_detector.sv 10 | ${I3C_ROOT_DIR}/src/ctrl/target_reset_detector.sv 11 | ${I3C_ROOT_DIR}/src/ctrl/i3c_bus_monitor.sv 12 | ${I3C_ROOT_DIR}/src/ctrl/bus_timers.sv 13 | ${I3C_ROOT_DIR}/src/ctrl/addr_match.sv 14 | ${I3C_ROOT_DIR}/src/ctrl/descriptor_rx.sv 15 | ${I3C_ROOT_DIR}/src/ctrl/descriptor_tx.sv 16 | ${I3C_ROOT_DIR}/src/ctrl/descriptor_ibi.sv 17 | ${I3C_ROOT_DIR}/src/ctrl/i3c_target_fsm.sv 18 | ${I3C_ROOT_DIR}/src/ctrl/ccc.sv 19 | ${I3C_ROOT_DIR}/src/ctrl/controller_standby_i3c.sv 20 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/seq_lib/i2c_direct_data_with_rstart_seq.sv: -------------------------------------------------------------------------------- 1 | class i2c_direct_data_with_rstart_seq extends i2c_direct_data_seq; 2 | `uvm_object_utils(i2c_direct_data_with_rstart_seq) 3 | `uvm_object_new 4 | 5 | int num_trans; 6 | 7 | virtual task send_host_mode_txn(); 8 | // get seq for agent running in Host mode 9 | `uvm_info(get_full_name(), $sformatf("\nNumber of transactions: %d", num_trans), UVM_LOW) 10 | for (int curr_trans = 0; curr_trans < num_trans; curr_trans++) begin 11 | host_direct_phase((curr_trans < num_trans-1)); 12 | `uvm_info(get_full_name(), $sformatf("\nHost recived:\n%s", rsp.sprint()), UVM_LOW) 13 | end 14 | endtask 15 | 16 | virtual task seq_stop(); 17 | stop = 1'b1; 18 | wait_for_sequence_state(UVM_FINISHED); 19 | endtask : seq_stop 20 | 21 | endclass : i2c_direct_data_with_rstart_seq 22 | 23 | -------------------------------------------------------------------------------- /activate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/env bash 2 | 3 | export PYENV_ROOT="$HOME/.pyenv" 4 | [[ -d $PYENV_ROOT/bin ]] && export PATH="$PYENV_ROOT/bin:$PATH" 5 | eval "$(pyenv init -)" 6 | eval "$(pyenv virtualenv-init -)" 7 | 8 | if [ -n "$ZSH_VERSION" ]; then 9 | script_path="${(%):-%N}" 10 | else 11 | script_path="${BASH_SOURCE[0]}" 12 | fi 13 | 14 | # Useful for running tests directly in verification/block 15 | export I3C_ROOT_DIR=$( cd "$( dirname "$script_path" )" &> /dev/null && pwd ) 16 | export CALIPTRA_ROOT=${I3C_ROOT_DIR}/third_party/caliptra-rtl 17 | 18 | # Pyenv 19 | PYTHON_VERSION=3.11.0 20 | VENV_NAME=i3c 21 | 22 | pyenv install ${PYTHON_VERSION} --skip-existing 23 | pyenv virtualenv ${PYTHON_VERSION} ${VENV_NAME} || true 24 | pyenv shell ${VENV_NAME} 25 | python --version 26 | pip install --upgrade pip 27 | python -m pip install -r "$(pwd)"/requirements.txt 28 | pyenv rehash 29 | -------------------------------------------------------------------------------- /verification/cocotb/block/ahb_if/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | # Set appropriate bus interface via Cocotb's PLUSARGS: 13 | override PLUSARGS := $(strip +FrontendBusInterface=AHB $(PLUSARGS)) 14 | 15 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 16 | TOPLEVEL = ahb_if_wrapper 17 | override CFG_NAME = ahb 18 | 19 | VERILOG_SOURCES = \ 20 | $(CALIPTRA_ROOT)/src/libs/rtl/ahb_defines_pkg.sv \ 21 | $(SRC_DIR)/csr/I3CCSR_pkg.sv \ 22 | $(SRC_DIR)/csr/I3CCSR.sv \ 23 | $(SRC_DIR)/hci/ahb_if.sv \ 24 | $(TEST_DIR)/ahb_if_wrapper.sv 25 | 26 | include $(TEST_DIR)/../block_common.mk 27 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_i3c_bus_monitor/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 13 | TOPLEVEL = i3c_bus_monitor_wrapper 14 | 15 | VERILOG_SOURCES = \ 16 | $(SRC_DIR)/i3c_pkg.sv \ 17 | $(SRC_DIR)/ctrl/controller_pkg.sv \ 18 | $(SRC_DIR)/ctrl/edge_detector.sv \ 19 | $(SRC_DIR)/ctrl/stable_high_detector.sv \ 20 | $(SRC_DIR)/ctrl/target_reset_detector.sv \ 21 | $(SRC_DIR)/ctrl/bus_monitor.sv \ 22 | $(SRC_DIR)/ctrl/i3c_bus_monitor.sv \ 23 | $(TEST_DIR)/i3c_bus_monitor_wrapper.sv 24 | 25 | include $(TEST_DIR)/../block_common.mk 26 | -------------------------------------------------------------------------------- /verification/cocotb/block/bus_rx_flow/bus_rx_flow_test_wrapper.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | module bus_rx_flow_test_wrapper ( 3 | input logic clk_i, 4 | input logic rst_ni, 5 | 6 | input scl_i, // Additional signal for SCL bus mock 7 | 8 | // I3C bus timings 9 | input logic [12:0] t_r_i, // rise time of both SDA and SCL in clock units 10 | input logic [12:0] t_f_i, // rise time of both SDA and SCL in clock units 11 | 12 | // Begin reading in data. 13 | // From now on, each SCL negedge is a data bit 14 | input logic scl_posedge_i, 15 | input logic scl_stable_high_i, 16 | input logic sda_i, 17 | 18 | input logic rx_req_bit_i, 19 | input logic rx_req_byte_i, 20 | output logic [7:0] rx_data_o, 21 | output logic rx_done_o, 22 | output logic rx_idle_o 23 | ); 24 | bus_rx_flow xbus_rx_flow (.*); 25 | endmodule 26 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class dv_base_seq #(type REQ = uvm_sequence_item, 6 | type RSP = REQ, 7 | type CFG_T = dv_base_agent_cfg, 8 | type SEQUENCER_T = dv_base_sequencer) extends uvm_sequence#(REQ, RSP); 9 | `uvm_object_param_utils(dv_base_seq #(REQ, RSP, CFG_T, SEQUENCER_T)) 10 | `uvm_declare_p_sequencer(SEQUENCER_T) 11 | 12 | CFG_T cfg; 13 | 14 | `uvm_object_new 15 | 16 | task pre_start(); 17 | super.pre_start(); 18 | cfg = p_sequencer.cfg; 19 | endtask 20 | 21 | task body(); 22 | `uvm_fatal(`gtn, "Need to override this when you extend from this class!") 23 | endtask : body 24 | 25 | endclass 26 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/i2c_agent.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_agent extends dv_base_agent #( 6 | .CFG_T (i2c_agent_cfg), 7 | .DRIVER_T (i2c_driver), 8 | .SEQUENCER_T (i2c_sequencer), 9 | .MONITOR_T (i2c_monitor), 10 | .COV_T (i2c_agent_cov) 11 | ); 12 | 13 | `uvm_component_utils(i2c_agent) 14 | 15 | `uvm_component_new 16 | 17 | function void build_phase(uvm_phase phase); 18 | super.build_phase(phase); 19 | if (!uvm_config_db#(virtual i2c_if)::get(this, "", "vif", cfg.vif)) begin 20 | `uvm_fatal(`gfn, "failed to get i2c_if handle from uvm_config_db") 21 | end 22 | cfg.has_req_fifo = 1; 23 | endfunction : build_phase 24 | 25 | endclass 26 | -------------------------------------------------------------------------------- /src/libs/counter_template.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | // This is a sample implementation of a counter 4 | // q is high if we count down from init value to 0 5 | // q is always low in reset state 6 | 7 | module counter_template 8 | import i3c_ctrl_pkg::*; 9 | #( 10 | parameter int CNTR_W = 9 11 | ) ( 12 | input logic clk, 13 | input logic rst_n, 14 | input logic load, 15 | input logic [CNTR_W-1:0] init_value, 16 | output logic q 17 | ); 18 | 19 | logic [DATA_W-1:0] counter; 20 | 21 | always_ff @(posedge clk or negedge rst_n) begin : proc_fsm 22 | if (!rst_n) begin 23 | counter <= '0; 24 | end else begin 25 | if (load) begin 26 | counter <= init_value; 27 | end else begin 28 | counter <= counter - 1'b1; 29 | end 30 | end 31 | 32 | end 33 | 34 | assign q = (rst_n) & (counter == '0); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /verification/uvm_i2c/prim_lib/prim_secded_inv_39_32_enc.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // SECDED encoder generated by util/design/secded_gen.py 6 | 7 | module prim_secded_inv_39_32_enc ( 8 | input [31:0] data_i, 9 | output logic [38:0] data_o 10 | ); 11 | 12 | always_comb begin : p_encode 13 | data_o = 39'(data_i); 14 | data_o[32] = ^(data_o & 39'h002606BD25); 15 | data_o[33] = ^(data_o & 39'h00DEBA8050); 16 | data_o[34] = ^(data_o & 39'h00413D89AA); 17 | data_o[35] = ^(data_o & 39'h0031234ED1); 18 | data_o[36] = ^(data_o & 39'h00C2C1323B); 19 | data_o[37] = ^(data_o & 39'h002DCC624C); 20 | data_o[38] = ^(data_o & 39'h0098505586); 21 | data_o ^= 39'h2A00000000; 22 | end 23 | 24 | endmodule : prim_secded_inv_39_32_enc 25 | -------------------------------------------------------------------------------- /verification/uvm_i2c/i2c_virtual_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_virtual_sequencer extends cip_base_virtual_sequencer #(.CFG_T(i2c_env_cfg), 6 | .COV_T(i2c_env_cov)); 7 | i2c_sequencer i2c_sequencer_h; 8 | uvm_analysis_port #(i2c_item) target_mode_wr_exp_port; 9 | uvm_analysis_port #(i2c_item) target_mode_rd_exp_port; 10 | 11 | `uvm_component_utils(i2c_virtual_sequencer) 12 | `uvm_component_new 13 | 14 | function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | target_mode_wr_exp_port = new("target_mode_wr_exp_port", this); 17 | target_mode_rd_exp_port = new("target_mode_rd_exp_port", this); 18 | endfunction 19 | endclass : i2c_virtual_sequencer 20 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_env_cfg.sv: -------------------------------------------------------------------------------- 1 | class i3c_env_cfg extends uvm_object; 2 | 3 | bit is_active = 1; 4 | bit en_scb = 1; 5 | 6 | local bit will_reset = 0; 7 | bit under_reset = 0; 8 | bit is_initialized; 9 | 10 | // i3c agent cfg 11 | i3c_agent_cfg m_i3c_agent_cfg; 12 | // TODO: add AXI agent cfg 13 | 14 | `uvm_object_utils_begin(i3c_env_cfg) 15 | `uvm_field_int (is_active, UVM_DEFAULT) 16 | `uvm_field_int (en_scb, UVM_DEFAULT) 17 | `uvm_field_object(m_i3c_agent_cfg, UVM_DEFAULT) 18 | `uvm_object_utils_end 19 | 20 | function new (string name=""); 21 | super.new(name); 22 | endfunction : new 23 | 24 | virtual function void initialize(); 25 | is_initialized = 1'b1; 26 | m_i3c_agent_cfg = i3c_agent_cfg::type_id::create("m_i3c_agent_cfg"); 27 | // TODO: add AXI config initialization 28 | endfunction 29 | 30 | endclass : i3c_env_cfg 31 | -------------------------------------------------------------------------------- /verification/uvm_i2c/tlul/tlul_assert_multiple.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Protocol checker for multiple TL-UL ports 6 | 7 | module tlul_assert_multiple #( 8 | parameter int unsigned N = 2, 9 | parameter EndpointType = "Device" // can be "Device" or "Host" 10 | ) ( 11 | input clk_i, 12 | input rst_ni, 13 | 14 | // tile link ports 15 | input tlul_pkg::tl_h2d_t h2d [N], 16 | input tlul_pkg::tl_d2h_t d2h [N] 17 | ); 18 | 19 | // instantiate N tlul_assert modules 20 | for (genvar ii = 0; ii < N; ii++) begin : gen_assert 21 | tlul_assert #( 22 | .EndpointType(EndpointType) 23 | ) tlul_assert ( 24 | .clk_i, 25 | .rst_ni, 26 | // TL-UL ports 27 | .h2d (h2d[ii]), 28 | .d2h (d2h[ii]) 29 | ); 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/smp/top_pkg.sv: -------------------------------------------------------------------------------- 1 | {%- import 'main.sv' as main with context -%} 2 | {%- raw -%} 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | {% endraw %} 17 | {{ "`ifndef" }} {{top_node.get_path()|upper}}_SAMPLE 18 | {{ "`define" }} {{top_node.get_path()|upper}}_SAMPLE 19 | {{main.top()|indent}} 20 | {{ "`endif" }} 21 | -------------------------------------------------------------------------------- /tools/sim_repeater.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | SIM_TRIES="${SIM_TRIES:-3}" 4 | RETRY_COOLDOWN=10 5 | TEMP_LOGS="$(mktemp -d)" 6 | 7 | function cleanup { 8 | rm -rf "${TEMP_LOGS}" 9 | } 10 | 11 | trap cleanup EXIT 12 | 13 | # Needed to propagate the exit code through the pipe to `tee` 14 | set -o pipefail 15 | 16 | for (( i=1; i<="${SIM_TRIES}"; i++ )); do 17 | echo "$@" 18 | "$@" 2>&1 | tee "${TEMP_LOGS}/${i}" 19 | RESULT=$? 20 | 21 | if [[ -n "${SIM_RETRY_CONDITION}" && ( $RESULT != 0 || $SIM_RETRY_IGNORE_EXIT_CODE = 1 ) ]]; then 22 | if grep -E "${SIM_RETRY_CONDITION}" "${TEMP_LOGS}/${i}" &> /dev/null; then 23 | echo "Retry condition encountered. Retrying in ${RETRY_COOLDOWN}s" 24 | echo '' 25 | sleep "${RETRY_COOLDOWN}" 26 | continue 27 | fi 28 | fi 29 | 30 | exit $RESULT 31 | done 32 | 33 | echo "Limit of ${SIM_TRIES} tries exceeded. Exiting" 34 | exit 1 35 | -------------------------------------------------------------------------------- /src/rdl/DCT_structure.rdl: -------------------------------------------------------------------------------- 1 | reg DCT_structure { 2 | regwidth = 128; 3 | field { 4 | name = "DYNAMIC_ADDRESS"; 5 | desc = "Device I3C Dynamic Address after ENTDAA"; 6 | sw = r; 7 | hw = rw; 8 | } DYNAMIC_ADDRESS[103:96]; 9 | field { 10 | name = "BCR"; 11 | desc = "Value of the I3C device's Bus Characteristics Register"; 12 | sw = r; 13 | hw = rw; 14 | } BCR[79:72]; 15 | field { 16 | name = "DCR"; 17 | desc = "Value of the I3C device's Device Characteristics Register"; 18 | sw = r; 19 | hw = rw; 20 | } DCR[71:64]; 21 | field { 22 | name = "PID_LO"; 23 | desc = "Device Provisional ID Low"; 24 | sw = r; 25 | hw = rw; 26 | } PID_LO[47:32]; 27 | field { 28 | name = "PID_HI"; 29 | desc = "Device Provisional ID High"; 30 | sw = r; 31 | hw = rw; 32 | } PID_HI[31:0]; 33 | }; 34 | -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/cov/top_pkg.sv: -------------------------------------------------------------------------------- 1 | {%- import 'main.sv' as main with context -%} 2 | {%- raw -%} 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | {% endraw %} 17 | {{ "`ifndef" }} {{top_node.get_path()|upper}}_COVERGROUPS 18 | {{ "`define" }} {{top_node.get_path()|upper}}_COVERGROUPS 19 | {{main.top()|indent}} 20 | {{ "`endif" }} 21 | -------------------------------------------------------------------------------- /verification/testplan/block/width_converter_8toN.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: width_converter_8toN 3 | testpoints: 4 | [ 5 | { 6 | name: converter 7 | desc: 8 | ''' 9 | Pushes random byte stream to the converter module. After each 10 | byte waits at random. Simultaneously receives N-bit data words 11 | and generates pushback (deasserts ready) at random. Verifies if 12 | the output data matches the input. 13 | ''' 14 | tests: ["width_converter_8ton_converter"] 15 | tags: ["width_converter_8toN"] 16 | } 17 | { 18 | name: flush 19 | desc: 20 | ''' 21 | Feeds M bytes to the module where M is in [1, 2, 3]. Asserts the 22 | sink_flush_i signal, receives the output word and checks if it 23 | matches the input data. 24 | ''' 25 | tests: ["width_converter_8ton_flush"] 26 | tags: ["width_converter_8toN"] 27 | } 28 | ] 29 | } 30 | -------------------------------------------------------------------------------- /verification/uvm_i2c/clk_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | //----------------------------- DESCRIPTION ------------------------------------ 6 | // 7 | // Generic clock interface for clock events in various utilities 8 | // 9 | //------------------------------------------------------------------------------ 10 | 11 | interface clk_if(input logic clk); 12 | 13 | clocking cb @(posedge clk); 14 | endclocking 15 | 16 | clocking cbn @(negedge clk); 17 | endclocking 18 | 19 | // Wait for 'n' clocks based of postive clock edge 20 | task automatic wait_clks(int num_clks); 21 | repeat (num_clks) @cb; 22 | endtask 23 | 24 | // Wait for 'n' clocks based of negative clock edge 25 | task automatic wait_n_clks(int num_clks); 26 | repeat (num_clks) @cbn; 27 | endtask 28 | 29 | endinterface 30 | -------------------------------------------------------------------------------- /testbench/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | VCS = vcs 4 | BUILD_DIR = $(I3C_ROOT_DIR)/testbench/build 5 | 6 | BUILD_ARGS += -full64 -sverilog +lint=TFIPC-L 7 | BUILD_ARGS += +libext+.sv +libext+.v 8 | BUILD_ARGS += $(foreach dir,$(VERILOG_INCLUDE_DIRS),-y $(dir)) 9 | BUILD_ARGS += -debug_access+all +memcbk -timescale=1ns/1ps -assert svaext 10 | 11 | SIM_ARGS += +dumpon 12 | EXTRA_ARGS += +vcs+vcdpluson +vpdfile+dump.vpd +warn=noLINX_KRNL 13 | 14 | ifneq ($(COVERAGE_TYPE),) 15 | EXTRA_ARGS += -cm line+cond+fsm+tgl+branch 16 | endif 17 | 18 | .PHONY: all vcs-build vcs-sim clean 19 | all: vcs-sim 20 | 21 | vcs-build: 22 | mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ 23 | $(VCS) $(BUILD_ARGS) $(EXTRA_ARGS) -f $(I3C_ROOT_DIR)/src/i3c_target.f $(I3C_ROOT_DIR)/testbench/tb.sv 24 | 25 | vcs-sim: vcs-build 26 | $(BUILD_DIR)/simv $(SIM_ARGS) $(EXTRA_ARGS) && vpd2vcd -full64 dump.vpd dump.vcd +splitpacked 27 | 28 | clean: 29 | rm -rf $(BUILD_DIR) 30 | -------------------------------------------------------------------------------- /verification/testplan/block/width_converter_Nto8.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: width_converter_Nto8 3 | testpoints: 4 | [ 5 | { 6 | name: converter 7 | desc: 8 | ''' 9 | Pushes random N-bit word stream to the converter module. After each 10 | word waits at random. Simultaneously receives bytes and generates 11 | pushback (deasserts ready) at random. Verifies if the output data 12 | matches the input. 13 | ''' 14 | tests: ["width_converter_nto8_converter"] 15 | tags: ["width_converter_Nto8"] 16 | } 17 | { 18 | name: flush 19 | desc: 20 | ''' 21 | Feeds an N-bit word to the module. Receives M bytes where M is in 22 | [1, 2, 3] and asserts source_flush_i. Verifies that the module 23 | ceases to output data as expected. 24 | ''' 25 | tests: ["width_converter_nto8_flush"] 26 | tags: ["width_converter_Nto8"] 27 | } 28 | ] 29 | } 30 | -------------------------------------------------------------------------------- /verification/uvm_i2c/prim_lib/prim_secded_inv_64_57_enc.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // SECDED encoder generated by util/design/secded_gen.py 6 | 7 | module prim_secded_inv_64_57_enc ( 8 | input [56:0] data_i, 9 | output logic [63:0] data_o 10 | ); 11 | 12 | always_comb begin : p_encode 13 | data_o = 64'(data_i); 14 | data_o[57] = ^(data_o & 64'h0103FFF800007FFF); 15 | data_o[58] = ^(data_o & 64'h017C1FF801FF801F); 16 | data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1); 17 | data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22); 18 | data_o[61] = ^(data_o & 64'h01EF76CDB2C93244); 19 | data_o[62] = ^(data_o & 64'h01F7BB56D5525488); 20 | data_o[63] = ^(data_o & 64'h01FBDDA769A46910); 21 | data_o ^= 64'h5400000000000000; 22 | end 23 | 24 | endmodule : prim_secded_inv_64_57_enc 25 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_i3c_bus_monitor/i3c_bus_monitor_wrapper.sv: -------------------------------------------------------------------------------- 1 | module i3c_bus_monitor_wrapper 2 | import i3c_pkg::*; 3 | ( 4 | input logic clk_i, 5 | input logic rst_ni, 6 | 7 | input logic enable_i, // Enable 8 | 9 | input logic scl_i, // Bus SCL 10 | input logic sda_i, // Bus SDA 11 | 12 | input logic [19:0] t_hd_dat_i, // Data hold time 13 | input logic [19:0] t_r_i, // Rise time 14 | input logic [19:0] t_f_i, // Fall time 15 | 16 | input logic is_in_hdr_mode_i, // Module is in HDR mode 17 | output logic hdr_exit_detect_o, // Detected HDR exit condition (see: 5.2.1.1.1 of the base spec) 18 | output logic target_reset_detect_o // Detected Target Reset condtition 19 | ); 20 | 21 | bus_state_t state; 22 | 23 | bus_monitor xmonitor ( 24 | .state_o (state), 25 | .* 26 | ); 27 | 28 | i3c_bus_monitor xi3c_monitor( 29 | .bus_i (state), 30 | .* 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /verification/uvm_i3c/testplan_ec.hjson: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | { 3 | testpoints: [ 4 | { 5 | name: extended_capability_list 6 | desc: ''' 7 | Discover extended capability list through HCI provided 8 | mechanism. 9 | 10 | - If EXT_CAPS_SECTION_OFFSET non zero, it should be possible 11 | to access all extended capabilities registers starting at 12 | EXT_CAPS_SECTION_OFFSET offset and following EXTCAP_HEADER 13 | - Extended capabilities list ends when EXTCAP_HEADER CAP_ID 14 | is 0x00, other wise next entry is CAP_LENGTH from current 15 | register 16 | - Extended capabilities list cannot have multiple entries 17 | with the same CAP_ID 18 | ''' 19 | stage: "" 20 | tests: ["ec_list_discovery"] 21 | } 22 | ] 23 | } 24 | -------------------------------------------------------------------------------- /verification/cocotb/block/lib_hci_queues/test_empty_hci.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | from common_methods import should_be_empty_after_rst 4 | from cocotb.handle import SimHandleBase 5 | from utils import controller_test 6 | 7 | 8 | @controller_test() 9 | async def test_cmd_capacity_status(dut: SimHandleBase): 10 | await should_be_empty_after_rst(dut, "hci", "cmd") 11 | 12 | 13 | @controller_test() 14 | async def test_rx_capacity_status(dut: SimHandleBase): 15 | await should_be_empty_after_rst(dut, "hci", "rx") 16 | 17 | 18 | @controller_test() 19 | async def test_resp_capacity_status(dut: SimHandleBase): 20 | await should_be_empty_after_rst(dut, "hci", "resp") 21 | 22 | 23 | @controller_test() 24 | async def test_tx_capacity_status(dut: SimHandleBase): 25 | await should_be_empty_after_rst(dut, "hci", "tx") 26 | 27 | 28 | @controller_test() 29 | async def test_ibi_capacity_status(dut: SimHandleBase): 30 | await should_be_empty_after_rst(dut, "hci", "ibi") 31 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/tb_sequencer.sv: -------------------------------------------------------------------------------- 1 | module tb; 2 | import i3c_sequence_test_pkg::*; 3 | import uvm_pkg::*; 4 | 5 | wire scl, sda; 6 | 7 | logic clk_i; 8 | logic rst_ni; 9 | 10 | initial begin 11 | rst_ni = 1'b0; 12 | clk_i = 1'b0; 13 | fork 14 | begin 15 | for(int i=0; i<100; i++) 16 | @(posedge clk_i) 17 | rst_ni = 1'b1; 18 | end 19 | forever begin 20 | clk_i = 1'b0; 21 | #(2ns); 22 | clk_i = 1'b1; 23 | #(2ns); 24 | end 25 | join 26 | end 27 | 28 | i3c_if i3c_bus( 29 | .clk_i(clk_i), 30 | .rst_ni(rst_ni), 31 | .scl_io(scl), 32 | .sda_io(sda) 33 | ); 34 | 35 | // For true I3C test add DUT here and change clock to be system clock 36 | 37 | initial begin 38 | uvm_config_db#(virtual i3c_if)::set(null, "*.m_top_env.m_i3c_agent*", "vif", i3c_bus); 39 | $timeformat(-12, 0, " ps", 12); 40 | run_test(); 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_host_timeout_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // timeout test vseq 6 | // this sequence sets timeout enable and value in timeout control reg 7 | // runs random i2c transactions agent is configured to pull down clock 8 | // host will trigger an interrupt stretch timeout when count exceeds the programmed 9 | // value in timeout control reg 10 | class i2c_host_timeout_vseq extends i2c_rx_tx_vseq; 11 | `uvm_object_utils(i2c_host_timeout_vseq) 12 | `uvm_object_new 13 | 14 | // increase num_trans to cover all transaction types 15 | constraint num_trans_c { num_trans inside {[50 : 100]}; } 16 | 17 | // constraints for i2c timing registers 18 | constraint t_timeout_c { t_timeout == cfg.seq_cfg.i2c_max_timing; } 19 | constraint e_timeout_c { e_timeout == 1'b1; } 20 | 21 | endclass : i2c_host_timeout_vseq 22 | -------------------------------------------------------------------------------- /verification/cocotb/block/lib_hci_queues/test_empty_tti.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | from common_methods import should_be_empty_after_rst 4 | 5 | from cocotb.handle import SimHandleBase 6 | from utils import target_test 7 | 8 | 9 | @target_test() 10 | async def test_tti_tx_desc_capacity_status(dut: SimHandleBase): 11 | await should_be_empty_after_rst(dut, "tti", "tx_desc") 12 | 13 | 14 | @target_test() 15 | async def test_tti_rx_capacity_status(dut: SimHandleBase): 16 | await should_be_empty_after_rst(dut, "tti", "rx") 17 | 18 | 19 | @target_test() 20 | async def test_tti_rx_desc_capacity_status(dut: SimHandleBase): 21 | await should_be_empty_after_rst(dut, "tti", "rx_desc") 22 | 23 | 24 | @target_test() 25 | async def test_tti_tx_capacity_status(dut: SimHandleBase): 26 | await should_be_empty_after_rst(dut, "tti", "tx") 27 | 28 | 29 | @target_test() 30 | async def test_tti_ibi_capacity_status(dut: SimHandleBase): 31 | await should_be_empty_after_rst(dut, "tti", "ibi") 32 | -------------------------------------------------------------------------------- /src/ctrl/controller_standby.f: -------------------------------------------------------------------------------- 1 | +incdir+${I3C_ROOT_DIR}/src 2 | ${I3C_ROOT_DIR}/src/ctrl/controller_pkg.sv 3 | ${I3C_ROOT_DIR}/src/i3c_pkg.sv 4 | // ${I3C_ROOT_DIR}/src/ctrl/ibi.sv 5 | ${I3C_ROOT_DIR}/src/ctrl/bus_tx.sv 6 | ${I3C_ROOT_DIR}/src/ctrl/bus_tx_flow.sv 7 | ${I3C_ROOT_DIR}/src/ctrl/bus_rx_flow.sv 8 | ${I3C_ROOT_DIR}/src/ctrl/bus_timers.sv 9 | ${I3C_ROOT_DIR}/src/ctrl/target_reset_detector.sv 10 | ${I3C_ROOT_DIR}/src/ctrl/stable_high_detector.sv 11 | ${I3C_ROOT_DIR}/src/ctrl/bus_monitor.sv 12 | ${I3C_ROOT_DIR}/src/ctrl/ccc.sv 13 | ${I3C_ROOT_DIR}/src/ctrl/addr_match.sv 14 | ${I3C_ROOT_DIR}/src/ctrl/edge_detector.sv 15 | ${I3C_ROOT_DIR}/src/ctrl/descriptor_rx.sv 16 | ${I3C_ROOT_DIR}/src/ctrl/descriptor_tx.sv 17 | ${I3C_ROOT_DIR}/src/ctrl/descriptor_ibi.sv 18 | ${I3C_ROOT_DIR}/src/ctrl/i2c_target_fsm.sv 19 | ${I3C_ROOT_DIR}/src/ctrl/i3c_target_fsm.sv 20 | ${I3C_ROOT_DIR}/src/ctrl/flow_standby_i2c.sv 21 | ${I3C_ROOT_DIR}/src/ctrl/controller_standby_i2c.sv 22 | ${I3C_ROOT_DIR}/src/ctrl/controller_standby_i3c.sv 23 | ${I3C_ROOT_DIR}/src/ctrl/controller_standby.sv 24 | -------------------------------------------------------------------------------- /verification/testplan/block/i3c_bus_monitor.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: i3c_bus_monitor 3 | testpoints: 4 | [ 5 | { 6 | name: bus_monitor_hdr_exit 7 | desc: 8 | ''' 9 | Verifies that the i3c_bus_monitor module correctly detects HDR 10 | exit pattern. Sends the HDR exit pattern and verifies that the 11 | module does not react - initially the bus is in SDR mode. Instructs 12 | the module that the bus has entered HDR mode, issues the HDR exit 13 | pattern and counts the number of times the module reported HDR 14 | exit. Checks if it reported exactly one HDR exit event. 15 | ''' 16 | tests: ["bus_monitor_hdr_exit"] 17 | tags: ["i3c_bus_monitor"] 18 | } 19 | { 20 | name: target_reset_detection 21 | desc: 22 | ''' 23 | Issues a target reset pattern to the I3C bus, verifies that the 24 | i3c_bus_monitor correctly report it detected. 25 | ''' 26 | tests: ["target_reset_detection"] 27 | tags: ["i3c_bus_monitor"] 28 | } 29 | ] 30 | } -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/seq_lib/i3c_direct_data_with_rstart_seq.sv: -------------------------------------------------------------------------------- 1 | class i3c_direct_data_with_rstart_seq extends i3c_direct_data_seq; 2 | `uvm_object_utils(i3c_direct_data_with_rstart_seq) 3 | `uvm_object_new 4 | 5 | int num_trans; 6 | int curr_trans; 7 | 8 | constraint transfer_i3c_end_c { 9 | if (curr_trans < num_trans-1) 10 | transfer.end_with_rstart dist {1 := 7, 0 := 3}; 11 | else 12 | transfer.end_with_rstart == 0; 13 | } 14 | 15 | virtual task send_host_mode_txn(); 16 | // get seq for agent running in Host mode 17 | `uvm_info(get_full_name(), $sformatf("\nNumber of transactions: %d", num_trans), UVM_LOW) 18 | for (curr_trans = 0; curr_trans < num_trans; curr_trans++) begin 19 | host_direct_phase(); 20 | `uvm_info(get_full_name(), $sformatf("\nHost recived:\n%s", rsp.sprint()), UVM_LOW) 21 | end 22 | endtask 23 | 24 | virtual task seq_stop(); 25 | stop = 1'b1; 26 | wait_for_sequence_state(UVM_FINISHED); 27 | endtask : seq_stop 28 | 29 | endclass : i3c_direct_data_with_rstart_seq 30 | 31 | -------------------------------------------------------------------------------- /src/rdl/controller_config.rdl: -------------------------------------------------------------------------------- 1 | // I3C controller register map based on MIPI HCI 1.2 2 | 3 | regfile ControllerConfigRegisters #( 4 | boolean controller_support 5 | ){ 6 | name = "Controller Config"; 7 | default regwidth = 32; 8 | reg { 9 | regwidth = 32; 10 | field { 11 | name = "CAP_LENGTH"; 12 | desc = "Capability Structure Length in DWORDs"; 13 | sw = r; 14 | hw = r; 15 | reset = 16'h0002; 16 | } CAP_LENGTH[23:8]; 17 | field { 18 | name = "CAP_ID"; 19 | desc = "Extended Capability ID"; 20 | sw = r; 21 | hw = r; 22 | reset = 8'h02; 23 | } CAP_ID[7:0]; 24 | } EXTCAP_HEADER; 25 | reg { 26 | name = "Controller Config"; 27 | field { 28 | name = "Operation Mode"; 29 | desc = ""; 30 | sw = r; 31 | hw = rw; 32 | we = true; 33 | reset = 2'h1; 34 | } OPERATION_MODE[5:4]; 35 | } CONTROLLER_CONFIG ; 36 | }; 37 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_base_virtual_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class cip_base_virtual_sequencer #(type CFG_T = cip_base_env_cfg, 6 | type COV_T = cip_base_env_cov) 7 | extends dv_base_virtual_sequencer #(CFG_T, COV_T); 8 | `uvm_component_param_utils(cip_base_virtual_sequencer #(CFG_T, COV_T)) 9 | 10 | // similar to (ral, ral_models) and (m_tl_agent_cfg, m_tl_agent_cfgs) 11 | // if the block supports only one RAL, just use tl_sequencer_h 12 | // if there are multiple RALs, `tl_sequencer_h` is the default one for RAL with type `RAL_T` 13 | tl_sequencer tl_sequencer_h; 14 | tl_sequencer tl_sequencer_hs[string]; 15 | 16 | alert_esc_sequencer alert_esc_sequencer_h[string]; 17 | push_pull_sequencer#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_pull_sequencer_h; 18 | 19 | `uvm_component_new 20 | 21 | endclass 22 | -------------------------------------------------------------------------------- /violations.waiver: -------------------------------------------------------------------------------- 1 | waive --rule=line-length --location="src/ctrl/i2c_controller_fsm.sv" 2 | waive --rule=line-length --location="src/ctrl/i2c_target_fsm.sv" 3 | waive --rule=line-length --location="src/ctrl/bus_monitor.sv" 4 | waive --rule=line-length --location="src/i2c_phy_integration.sv" 5 | waive --rule=line-length --location="verification/block/i2c_phy_integration/i2c_phy_integration_wrapper.sv" 6 | waive --rule=line-length --location="src/csr/I3CCSR_covergroups.svh" 7 | waive --rule=line-length --location="src/csr/I3CCSR_sample.svh" 8 | waive --rule=line-length --location="src/csr/I3CCSR_uvm.sv" 9 | waive --rule=line-length --location="src/hci/configuration.sv" 10 | waive --rule=line-length --location="src/hci/hci.sv" 11 | waive --rule=line-length --location="src/hci/tti.sv" 12 | waive --rule=line-length --location="src/recovery/recovery_handler.sv" 13 | waive --rule=line-length --location="src/recovery/recovery_pec.sv" 14 | waive --rule=line-length --location="src/recovery/recovery_executor.sv" 15 | waive --rule=case-missing-default --location="src/recovery/recovery_executor.sv" 16 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_tl_host_single_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Extends tl_host_single_seq to enable control over command integrity fields. 6 | // 7 | // This is useful to set up integrity error sequences, 8 | // test execution of Instr/Data transactions, etc... 9 | class cip_tl_host_single_seq extends tl_host_single_seq #(cip_tl_seq_item); 10 | 11 | `uvm_object_utils(cip_tl_host_single_seq) 12 | `uvm_object_new 13 | 14 | mubi4_t instr_type = MuBi4False; 15 | tl_intg_err_e tl_intg_err_type = TlIntgErrNone; 16 | 17 | virtual function void randomize_req(REQ req, int idx); 18 | super.randomize_req(req, idx); 19 | 20 | // set tl_intg_err_type first, as set_instr_type will trigger re-calculating integrity based on 21 | // the TLUL info and err_type 22 | req.tl_intg_err_type = tl_intg_err_type; 23 | req.set_instr_type(instr_type); 24 | endfunction 25 | 26 | endclass 27 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_shadowed_field_cov.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // coverage object of shadowed errors - update and storage errors. 6 | 7 | class dv_base_shadowed_field_cov extends uvm_object; 8 | `uvm_object_utils(dv_base_shadowed_field_cov) 9 | 10 | covergroup shadow_field_errs_cg(string name) with function sample(bit update_err = 0, 11 | bit storage_err = 0); 12 | option.per_instance = 1; 13 | option.name = name; 14 | 15 | cp_update_err: coverpoint update_err { 16 | bins update_err = {1}; 17 | } 18 | 19 | cp_storage_err: coverpoint storage_err { 20 | bins storage_err = {1}; 21 | } 22 | endgroup 23 | 24 | // use reg_field name as this name 25 | function new(string name = ""); 26 | shadow_field_errs_cg = new($sformatf("%0s_shadowed_errs_cov", name)); 27 | endfunction : new 28 | 29 | endclass 30 | -------------------------------------------------------------------------------- /tools/simulators/Makefile.verilator: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | ifeq (, $(shell which verilator)) 4 | $(warning WARNING: SIMULATOR: verilator is not in PATH.) 5 | endif 6 | 7 | UVM_TB_FILES ?= $(I3C_ROOT_DIR)/verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sim.scr \ 8 | $(I3C_ROOT_DIR)/verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/tb_sequencer.sv 9 | UVM_TESTNAME ?= i3c_sequence_test 10 | UVM_VSEQ_TEST ?= direct_vseq 11 | EXTRA_BUILD_ARGS ?= OPT_FAST="-Os" 12 | EXTRA_RUN_ARGS ?= 13 | 14 | VERILATOR = verilator 15 | 16 | BUILD_ARGS = --cc --main --timing --timescale 1ns/1ps --trace 17 | RUN_ARGS = 18 | 19 | ifdef DEBUG 20 | DEBUG_OPTS = --trace --trace-structs 21 | endif 22 | 23 | verilator-build: 24 | $(VERILATOR) $(BUILD_ARGS) \ 25 | +incdir+$(UVM_DIR)/src \ 26 | $(UVM_DIR)/src/uvm.sv \ 27 | -f $(UVM_TB_FILES) 28 | $(MAKE) -j -e -C obj_dir/ -f Vi3c_monitor_test_from_csv.mk $(EXTRA_BUILD_ARGS) 29 | 30 | # VM_PARALLEL_BUILDS=1 31 | # --top-module i3c_monitor_test_from_csv 32 | 33 | verilator: verilator-build 34 | ./obj_dir/Vtb_top 35 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/seq_lib/i2c_target_base_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_target_base_seq extends i2c_base_seq; 6 | `uvm_object_utils(i2c_target_base_seq) 7 | `uvm_object_new 8 | 9 | virtual task body(); 10 | // i2c_item needs more test specific parameters for proper randomization. 11 | // Rather than keeping duplicate parameters in i2c_agent_cfg and i2c_seq_cfg, 12 | // use i2c_seq_cfg parameters to simplify implementation. 13 | // So, instead of randomizing i2c_item here, assuming i2c_item is randomized in 14 | // vseq and fed to req_q here. 15 | `DV_SPINWAIT_EXIT(wait (req_q.size() > 0); 16 | while (req_q.size() > 0) begin 17 | req = req_q.pop_front(); 18 | start_item(req); 19 | finish_item(req); 20 | end 21 | , wait (stop);) 22 | endtask : body 23 | 24 | endclass : i2c_target_base_seq 25 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/tb_i3c_core.sv: -------------------------------------------------------------------------------- 1 | module tb; 2 | import i3c_test_pkg::*; 3 | import uvm_pkg::*; 4 | 5 | wire scl, sda; 6 | 7 | logic clk_i; 8 | logic rst_ni; 9 | 10 | initial begin 11 | rst_ni = 1'b0; 12 | clk_i = 1'b0; 13 | fork 14 | begin 15 | for(int i=0; i<100; i++) 16 | @(posedge clk_i) 17 | rst_ni = 1'b1; 18 | end 19 | forever begin 20 | clk_i = 1'b0; 21 | #(1ns); 22 | clk_i = 1'b1; 23 | #(1ns); 24 | end 25 | join 26 | end 27 | 28 | i3c_if i3c_bus( 29 | .clk_i(clk_i), 30 | .rst_ni(rst_ni), 31 | .scl_io(scl), 32 | .sda_io(sda) 33 | ); 34 | 35 | // TODO: add AXI interface 36 | 37 | i3c_wrapper dut( 38 | .clk_i(clk_i), 39 | .rst_ni(rst_ni), 40 | // TODO: add AXI connections 41 | .i3c_scl_io(scl), 42 | .i3c_sda_io(sda) 43 | ); 44 | 45 | initial begin 46 | uvm_config_db#(virtual i3c_if)::set(null, "*.env.m_i3c_agent", "vif", i3c_bus); 47 | // TODO: add AXI interface to environment 48 | $timeformat(-12, 0, " ps", 12); 49 | run_test(); 50 | end 51 | endmodule 52 | -------------------------------------------------------------------------------- /verification/uvm_i2c/alert_esc_probe_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this is a probing interface for signal "esc_en_i": 6 | // "esc_en_i" is one of the input signal for "prim_esc_sender" 7 | // "esc_en_i" needs to be probed because: in esc_sig_integrity_fail cases, "esc_en_i" gated if next 8 | // state the expected resp_p should be high or not. However, from the esc_receiver interface, we 9 | // can only see "esc_p/n", which follows "esc_en_i" with one clock cycle delay. 10 | // Thus we need to probe this signal to accurately predict the signal integrity fail count. 11 | interface alert_esc_probe_if ( 12 | input clk, 13 | input rst_n 14 | ); 15 | 16 | wire esc_en; 17 | 18 | clocking monitor_cb @(posedge clk); 19 | input rst_n; 20 | input esc_en; 21 | endclocking 22 | 23 | function automatic logic get_esc_en(); 24 | return monitor_cb.esc_en; 25 | endfunction 26 | 27 | task automatic wait_esc_en(); 28 | while (esc_en !== 1'b1) @(monitor_cb); 29 | endtask 30 | 31 | endinterface 32 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_host_smoke_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // basic smoke test vseq 6 | class i2c_host_smoke_vseq extends i2c_rx_tx_vseq; 7 | `uvm_object_utils(i2c_host_smoke_vseq) 8 | `uvm_object_new 9 | 10 | // increase num_trans to cover all transaction types 11 | constraint num_trans_c { num_trans inside {[50 : 100]}; } 12 | 13 | virtual task body(); 14 | bit do_interrupt = 1'b1; 15 | initialization(); 16 | `uvm_info(`gfn, "\n--> start of sequence", UVM_DEBUG) 17 | fork 18 | begin 19 | while (!cfg.under_reset && do_interrupt) process_interrupts(); 20 | end 21 | begin 22 | host_send_trans(.max_trans(num_trans), 23 | .trans_type(ReadOnly), 24 | .read(1)); 25 | do_interrupt = 1'b0; // gracefully stop process_interrupts 26 | end 27 | join 28 | `uvm_info(`gfn, "\n--> end of sequence", UVM_DEBUG) 29 | endtask : body 30 | 31 | 32 | endclass : i2c_host_smoke_vseq 33 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/direct_vseq.sv: -------------------------------------------------------------------------------- 1 | class direct_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(direct_vseq) 7 | 8 | i3c_direct_data_seq dev; 9 | i3c_direct_data_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i3c_direct_data_seq::type_id::create("dev"); 17 | host = i3c_direct_data_seq::type_id::create("host"); 18 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_dev.i3c_target0), 19 | .t1(m_cfg.m_i3c_agent_cfg_dev.i3c_target1)); 20 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_host.i3c_target0), 21 | .t1(m_cfg.m_i3c_agent_cfg_host.i3c_target1)); 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.start(p_sequencer.m_i3c_sequencer_host); 27 | #(100*1us); 28 | end 29 | join_any 30 | disable fork; 31 | join 32 | endtask: body 33 | 34 | endclass : direct_vseq 35 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/direct_i2c_vseq.sv: -------------------------------------------------------------------------------- 1 | class direct_i2c_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(direct_i2c_vseq) 7 | 8 | i2c_direct_data_seq dev; 9 | i2c_direct_data_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i2c_direct_data_seq::type_id::create("dev"); 17 | host = i2c_direct_data_seq::type_id::create("host"); 18 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr0 = i2c_addr0; 19 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr1 = i2c_addr1; 20 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr0 = i2c_addr0; 21 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr1 = i2c_addr1; 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.start(p_sequencer.m_i3c_sequencer_host); 27 | #(100*1us); 28 | end 29 | join_any 30 | disable fork; 31 | join 32 | endtask: body 33 | 34 | endclass : direct_i2c_vseq 35 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_common_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_common_vseq extends i2c_base_vseq; 6 | `uvm_object_utils(i2c_common_vseq) 7 | `uvm_object_new 8 | 9 | constraint num_trans_c { num_trans inside {[1:2]}; } 10 | 11 | // for this vseq, $value$plusargs "+en_scb=0" is defined in i2c_sim_cfg.hjson 12 | // disable i2c_monitor and i2c_scoreboard since they can not handle this test 13 | 14 | virtual task body(); 15 | `uvm_info(`gfn, "\n--> start of i2c_common_vseq", UVM_DEBUG) 16 | run_common_vseq_wrapper(num_trans); 17 | `uvm_info(`gfn, "\n--> end of i2c_common_vseq", UVM_DEBUG) 18 | endtask : body 19 | 20 | virtual task post_start(); 21 | // if csr test, clean up i2c.OVRD to avoid spurious interrupt caused by 22 | // un-intended scl/sda output 23 | // default: csr_rw 24 | if (common_seq_type == "") begin 25 | // clear i2c.OVRDEN 26 | ral.ovrd.txovrden.set(1'b0); 27 | csr_update(ral.ovrd); 28 | end 29 | super.post_start(); 30 | endtask 31 | endclass : i2c_common_vseq 32 | -------------------------------------------------------------------------------- /doc/source/introduction.md: -------------------------------------------------------------------------------- 1 | # Introduction 2 | 3 | This document summarizes the current state of the I3C core developed by Antmicro for Caliptra within CHIPS Alliance. 4 | 5 | The implementation follows the Errata 01 for MIPI I3C Basic Specification Version 1.1.1 dated 11.03.2022. 6 | 7 | ## Documentation structure 8 | 9 | This documentation comprises the following chapters: 10 | 11 | * {doc}`overview` - summarizes the main notions of the project 12 | * {doc}`ccc` - provides an overview of the CCCs implemented by the core 13 | * {doc}`phy` - provides a description of the I3C PHY Layer logic 14 | * {doc}`dv` - describes verification tooling and testplans 15 | * {doc}`ext_cap` - provides a description of Target Transaction Interface 16 | * {doc}`i3c_recovery_flow` - describes the I3C-based Recovery mode workflow 17 | * {doc}`axi_id_filtering` - provides information about the AXI transactions filtering feature 18 | * {doc}`axi_recovery_flow` - describes the alternative, optional, recovery flow where the recovery data is transferred to the core over the AXI bus 19 | * {doc}`registers` - provides auto-generated register descriptions 20 | * {doc}`known_limitations` - provides information about known core limitaions in specific releases 21 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_target_ack_stop_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_target_ack_stop_vseq extends i2c_target_smoke_vseq; 6 | `uvm_object_utils(i2c_target_ack_stop_vseq) 7 | `uvm_object_new 8 | 9 | virtual task pre_start(); 10 | super.pre_start(); 11 | expected_intr[UnexpStop] = 1; 12 | cfg.m_i2c_agent_cfg.allow_ack_stop = 1; 13 | endtask 14 | 15 | virtual task body(); 16 | fork begin 17 | fork 18 | super.body(); 19 | begin 20 | cfg.clk_rst_vif.wait_for_reset(.wait_negedge(0)); 21 | wait(cfg.sent_ack_stop > 0); 22 | 23 | forever begin 24 | wait(cfg.m_i2c_agent_cfg.ack_stop_det); 25 | `uvm_info("ack_stop_seq", $sformatf("assa ack_stop rcvd %0d", cfg.rcvd_ack_stop), 26 | UVM_MEDIUM) 27 | clear_interrupt(UnexpStop); 28 | cfg.m_i2c_agent_cfg.ack_stop_det = 0; 29 | cfg.rcvd_ack_stop++; 30 | end 31 | end 32 | join_any 33 | disable fork; 34 | end join 35 | endtask 36 | endclass 37 | -------------------------------------------------------------------------------- /verification/cocotb/block/bus_tx_flow/bus_tx_flow_test_wrapper.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | module bus_tx_flow_test_wrapper ( 3 | input logic clk_i, 4 | input logic rst_ni, 5 | 6 | input scl_i, // Additional signal for SCL bus mock 7 | 8 | // I3C bus timings 9 | input logic [19:0] t_r_i, // rise time of both SDA and SCL in clock units 10 | input logic [12:0] t_f_i, // rise time of both SDA and SCL in clock units 11 | input logic [19:0] t_su_dat_i, // data setup time in clock units 12 | input logic [19:0] t_hd_dat_i, // data hold time in clock units 13 | 14 | // Input I3C Bus events 15 | input logic scl_negedge_i, 16 | input logic scl_posedge_i, 17 | input logic scl_stable_low_i, 18 | 19 | // Bus flow control 20 | input logic req_byte_i, 21 | input logic req_bit_i, 22 | input logic [7:0] req_value_i, 23 | output logic bus_tx_done_o, 24 | output logic bus_tx_idle_o, 25 | output logic req_error_o, 26 | output logic bus_error_o, 27 | 28 | // Open Drain / Push Pull 29 | input logic sel_od_pp_i, 30 | output logic sel_od_pp_o, 31 | 32 | output logic sda_o // Output I3C SDA bus line 33 | ); 34 | bus_tx_flow xbus_tx_flow (.*); 35 | endmodule 36 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_lib_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | package dv_lib_pkg; 6 | // dep packages 7 | import uvm_pkg::*; 8 | import bus_params_pkg::*; 9 | import dv_utils_pkg::*; 10 | import csr_utils_pkg::*; 11 | import dv_base_reg_pkg::*; 12 | 13 | // macro includes 14 | `include "uvm_macros.svh" 15 | `include "dv_macros.svh" 16 | 17 | // package variables 18 | string msg_id = "dv_lib_pkg"; 19 | 20 | // package sources 21 | // base agent 22 | `include "dv_base_agent_cfg.sv" 23 | `include "dv_base_agent_cov.sv" 24 | `include "dv_base_monitor.sv" 25 | `include "dv_base_sequencer.sv" 26 | `include "dv_base_driver.sv" 27 | `include "dv_base_agent.sv" 28 | 29 | // base seq 30 | `include "dv_base_seq.sv" 31 | 32 | // base env 33 | `include "dv_base_env_cfg.sv" 34 | `include "dv_base_env_cov.sv" 35 | `include "dv_base_virtual_sequencer.sv" 36 | `include "dv_base_scoreboard.sv" 37 | `include "dv_base_env.sv" 38 | 39 | // base test vseq 40 | `include "dv_base_vseq.sv" 41 | 42 | // base test 43 | `include "dv_base_test.sv" 44 | 45 | endpackage 46 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_env_cfg.sv: -------------------------------------------------------------------------------- 1 | class i3c_sequence_env_cfg extends uvm_object; 2 | 3 | bit is_active = 1; 4 | bit en_scb = 1; 5 | 6 | local bit will_reset = 0; 7 | bit under_reset = 0; 8 | bit is_initialized; 9 | 10 | // i3c agent cfg 11 | i3c_agent_cfg m_i3c_agent_cfg_dev; 12 | i3c_agent_cfg m_i3c_agent_cfg_host; 13 | 14 | `uvm_object_utils_begin(i3c_sequence_env_cfg) 15 | `uvm_field_int (is_active, UVM_DEFAULT) 16 | `uvm_field_int (en_scb, UVM_DEFAULT) 17 | `uvm_field_object(m_i3c_agent_cfg_dev, UVM_DEFAULT) 18 | `uvm_field_object(m_i3c_agent_cfg_host, UVM_DEFAULT) 19 | `uvm_object_utils_end 20 | 21 | function new (string name=""); 22 | super.new(name); 23 | endfunction : new 24 | 25 | virtual function void initialize(); 26 | is_initialized = 1'b1; 27 | // create i2c_agent_cfg 28 | m_i3c_agent_cfg_dev = i3c_agent_cfg::type_id::create("m_i3c_agent_cfg_dev"); 29 | m_i3c_agent_cfg_host = i3c_agent_cfg::type_id::create("m_i3c_agent_cfg_host"); 30 | // set agent to Device mode 31 | m_i3c_agent_cfg_dev.if_mode = Device; 32 | m_i3c_agent_cfg_host.if_mode = Host; 33 | endfunction 34 | 35 | endclass : i3c_sequence_env_cfg 36 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_driver.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class dv_base_driver #(type ITEM_T = uvm_sequence_item, 6 | type CFG_T = dv_base_agent_cfg, 7 | type RSP_ITEM_T = ITEM_T) 8 | extends uvm_driver #(.REQ(ITEM_T), .RSP(RSP_ITEM_T)); 9 | 10 | `uvm_component_param_utils(dv_base_driver #(.ITEM_T (ITEM_T), 11 | .CFG_T (CFG_T), 12 | .RSP_ITEM_T (RSP_ITEM_T))) 13 | 14 | bit under_reset; 15 | CFG_T cfg; 16 | 17 | `uvm_component_new 18 | 19 | virtual task run_phase(uvm_phase phase); 20 | fork 21 | reset_signals(); 22 | get_and_drive(); 23 | join 24 | endtask 25 | 26 | // reset signals 27 | virtual task reset_signals(); 28 | `uvm_fatal(`gfn, "this is implemented as pure virtual task - please extend") 29 | endtask 30 | 31 | // drive trans received from sequencer 32 | virtual task get_and_drive(); 33 | `uvm_fatal(`gfn, "this is implemented as pure virtual task - please extend") 34 | endtask 35 | 36 | endclass 37 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_target_perf_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // targetmode performance test vseq 6 | class i2c_target_perf_vseq extends i2c_target_smoke_vseq; 7 | `uvm_object_utils(i2c_target_perf_vseq) 8 | `uvm_object_new 9 | 10 | // Fast timing values programmed to registers 11 | // See constraint minimum in i2c_target_smoke_vseq 12 | constraint timing_val_c { 13 | t_r == 1; 14 | t_f == 1; 15 | thd_sta == 3; 16 | tsu_sto == 1; 17 | tsu_dat == 1; 18 | thd_dat == 1; 19 | t_timeout == 1; 20 | e_timeout == 1; 21 | tsu_sta == 1; 22 | 23 | thigh == 3; 24 | tlow == 8; 25 | // tHoldStop must be at least 2 cycles which implies, t_r + t_buf - tsu_sta >= 2 26 | // in order for stop condition to propogate to internal FSM via prim flop 27 | t_buf >= tsu_sta - t_r + 2; 28 | // In addition, t_buf > thd_dat + 1 to satisfy the Start/Stop decoder, 29 | // which rejects decoding Start/Stop symbols if SCL changes after SDA within 30 | // thd_dat cycles (+1 for CDC skew) 31 | t_buf == thd_dat + 2; 32 | } 33 | 34 | endclass 35 | -------------------------------------------------------------------------------- /src/ctrl/stable_high_detector.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | 3 | /* 4 | Detect that signal line_i is stable and HIGH for at 5 | least delay_count_i cycles. 6 | */ 7 | module stable_high_detector 8 | import controller_pkg::*; 9 | #( 10 | parameter int CNTR_W = 20 11 | ) ( 12 | input logic clk_i, 13 | input logic rst_ni, 14 | input logic line_i, 15 | input logic [CNTR_W-1:0] delay_count_i, 16 | output logic stable_o 17 | ); 18 | logic [CNTR_W-1:0] count; 19 | logic do_count; 20 | logic line; 21 | logic stable_internal; 22 | 23 | assign stable_o = (delay_count_i == 0) ? line_i : stable_internal; 24 | always_ff @(posedge clk_i or negedge rst_ni) begin 25 | if (!rst_ni) begin 26 | line <= '0; 27 | end else begin 28 | line <= line_i; 29 | end 30 | end 31 | 32 | always_ff @(posedge clk_i or negedge rst_ni) begin 33 | if (!rst_ni) begin 34 | count <= '0; 35 | end else if (line && do_count) begin 36 | count <= count + 1'b1; 37 | end else if (!line) begin 38 | count <= '0; 39 | end 40 | end 41 | 42 | always_comb begin 43 | do_count = '1; 44 | stable_internal = '0; 45 | if (count > delay_count_i) begin 46 | do_count = '0; 47 | stable_internal = line; 48 | end 49 | end 50 | endmodule 51 | -------------------------------------------------------------------------------- /verification/testplan/source-maps.yml: -------------------------------------------------------------------------------- 1 | testplans: 2 | - name: Recovery mode tests 3 | source: verification/cocotb/top/lib_i3c_top/test_recovery.py 4 | - name: "Enter and exit HDR mode" 5 | source: verification/cocotb/top/lib_i3c_top/test_enter_exit_hdr_mode.py 6 | - name: target_interrupts 7 | source: verification/cocotb/top/lib_i3c_top/test_interrupts.py 8 | - name: target_peripheral_reset 9 | source: verification/cocotb/top/lib_i3c_top/test_target_reset.py 10 | - name: pec 11 | source: verification/cocotb/block/recovery_pec/test_pec.py 12 | - name: CCC handling 13 | source: verification/cocotb/top/lib_i3c_top/test_ccc.py 14 | - name: width_converter_[N8]to[N8] 15 | source: verification/cocotb/block/{name}/test_converter.py 16 | - name: Target 17 | source: verification/cocotb/top/lib_i3c_top/test_i3c_target.py 18 | - name: Recovery bypass 19 | source: verification/cocotb/top/lib_i3c_top/test_bypass.py 20 | - name: "csr_sw_access" 21 | source: "verification/cocotb/block/lib_adapter/test_csr_sw_access.py" 22 | - filename: ".*/verification/testplan/(.*)/(.*).hjson" 23 | source: "verification/cocotb/{{regex_groups['testplan'][0]}}/**/test_{{testplan}}.py" 24 | - filename: ".*" 25 | docs_html: "dv.html#{{testplan.lower().replace('_', '-').replace(' ', '-')}}" 26 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/broadcast_followed_by_data_vseq.sv: -------------------------------------------------------------------------------- 1 | class broadcast_followed_by_data_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(broadcast_followed_by_data_vseq) 7 | 8 | i3c_broadcast_followed_by_data_seq dev; 9 | i3c_broadcast_followed_by_data_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i3c_broadcast_followed_by_data_seq::type_id::create("dev"); 17 | host = i3c_broadcast_followed_by_data_seq::type_id::create("host"); 18 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_dev.i3c_target0), 19 | .t1(m_cfg.m_i3c_agent_cfg_dev.i3c_target1)); 20 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_host.i3c_target0), 21 | .t1(m_cfg.m_i3c_agent_cfg_host.i3c_target1)); 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.start(p_sequencer.m_i3c_sequencer_host); 27 | #(100*1us); 28 | end 29 | join_any 30 | disable fork; 31 | join 32 | endtask: body 33 | 34 | endclass : broadcast_followed_by_data_vseq 35 | -------------------------------------------------------------------------------- /verification/cocotb/block/bus_tx/bus_tx_test_wrapper.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | module bus_tx_test_wrapper ( 3 | input logic clk_i, 4 | input logic rst_ni, 5 | 6 | input scl_i, // Additional signal for SCL bus mock 7 | 8 | // I3C bus timings 9 | input logic [19:0] t_r_i, // rise time of both SDA and SCL in clock units 10 | input logic [12:0] t_f_i, // rise time of both SDA and SCL in clock units 11 | input logic [19:0] t_su_dat_i, // data setup time in clock units 12 | input logic [19:0] t_hd_dat_i, // data hold time in clock units 13 | 14 | input logic drive_i, // Driving the bus, it should neve come later than (t_low-t_hd_dat) after 15 | // SCL falling edge if SCL is in stable LOW state 16 | input logic drive_value_i, // Requested value to drive 17 | 18 | // Input I3C Bus events 19 | input logic scl_posedge_i, 20 | input logic scl_negedge_i, 21 | input logic scl_stable_high_i, 22 | input logic scl_stable_low_i, 23 | 24 | // Open Drain / Push Pull 25 | input logic sel_od_pp_i, 26 | 27 | output logic tx_idle_o, 28 | output logic tx_done_o, // Indicate finished bit write 29 | 30 | output logic sel_od_pp_o, 31 | output logic sda_o // Output I3C SDA bus line 32 | ); 33 | bus_tx xbus_tx (.*); 34 | endmodule 35 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_tl_device_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Extends the tl_device_seq to handle integrity of the response channel. 6 | class cip_tl_device_seq extends tl_device_seq #(cip_tl_seq_item); 7 | 8 | `uvm_object_utils(cip_tl_device_seq) 9 | `uvm_object_new 10 | 11 | int d_chan_intg_err_pct = 0; 12 | 13 | rand bit inject_d_chan_intg_err; 14 | constraint inject_d_chan_intg_err_c { 15 | inject_d_chan_intg_err dist { 16 | 1 :/ d_chan_intg_err_pct, 17 | 0 :/ 100 - d_chan_intg_err_pct 18 | }; 19 | } 20 | 21 | rand tl_intg_err_e tl_intg_err_type; 22 | constraint tl_intg_err_type_c { 23 | (d_chan_intg_err_pct > 0) -> (tl_intg_err_type != TlIntgErrNone); 24 | } 25 | 26 | virtual function void randomize_rsp(cip_tl_seq_item rsp); 27 | super.randomize_rsp(rsp); 28 | `DV_CHECK_MEMBER_RANDOMIZE_FATAL(inject_d_chan_intg_err) 29 | `DV_CHECK_MEMBER_RANDOMIZE_FATAL(tl_intg_err_type) 30 | rsp.d_user = rsp.compute_d_user(); 31 | if (inject_d_chan_intg_err) begin 32 | rsp.tl_intg_err_type = tl_intg_err_type; 33 | rsp.inject_d_chan_intg_err(); 34 | end 35 | endfunction 36 | 37 | endclass 38 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/direct_with_rstart_vseq.sv: -------------------------------------------------------------------------------- 1 | class direct_with_rstart_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(direct_with_rstart_vseq) 7 | 8 | i3c_direct_data_seq dev; 9 | i3c_direct_data_with_rstart_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i3c_direct_data_seq::type_id::create("dev"); 17 | host = i3c_direct_data_with_rstart_seq::type_id::create("host"); 18 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_dev.i3c_target0), 19 | .t1(m_cfg.m_i3c_agent_cfg_dev.i3c_target1)); 20 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_host.i3c_target0), 21 | .t1(m_cfg.m_i3c_agent_cfg_host.i3c_target1)); 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.num_trans = num_trans; 27 | host.start(p_sequencer.m_i3c_sequencer_host); 28 | #(100*1us); 29 | this.randomize(num_trans); 30 | end 31 | join_any 32 | disable fork; 33 | join 34 | endtask: body 35 | 36 | endclass : direct_with_rstart_vseq 37 | -------------------------------------------------------------------------------- /verification/uvm_i3c/i3c_core/i3c_env.sv: -------------------------------------------------------------------------------- 1 | class i3c_env extends uvm_env; 2 | `uvm_component_utils(i3c_env) 3 | 4 | i3c_env_cfg cfg; 5 | 6 | i3c_agent m_i3c_agent; 7 | // TODO: add AXI agent 8 | i3c_virtual_sequencer m_vsequencer; 9 | 10 | function new (string name="", uvm_component parent=null); 11 | super.new(name, parent); 12 | endfunction : new 13 | 14 | function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | 17 | if (!uvm_config_db#(i3c_env_cfg)::get(this, "", "cfg", cfg)) begin 18 | `uvm_fatal(get_full_name(), $sformatf("failed to get %s from uvm_config_db", cfg.get_type_name())) 19 | end 20 | 21 | if (cfg.is_active) begin 22 | m_vsequencer = i3c_virtual_sequencer::type_id::create("m_vsequence", this); 23 | m_vsequencer.cfg = cfg; 24 | end 25 | 26 | m_i3c_agent = i3c_agent::type_id::create("m_i3c_agent", this); 27 | uvm_config_db#(i3c_agent_cfg)::set(this, "m_i3c_agent", "cfg", cfg.m_i3c_agent_cfg); 28 | cfg.m_i3c_agent_cfg.en_monitor = 1'b1; 29 | endfunction : build_phase 30 | 31 | function void connect_phase(uvm_phase phase); 32 | super.connect_phase(phase); 33 | m_vsequencer.m_i3c_sequencer = m_i3c_agent.sequencer; 34 | //TODO: add AXI sequencer 35 | endfunction 36 | 37 | endclass : i3c_env 38 | 39 | -------------------------------------------------------------------------------- /tools/verible-scripts/stats_lint.py: -------------------------------------------------------------------------------- 1 | import os 2 | import sys 3 | from collections import Counter 4 | 5 | error_codes = [] 6 | run_cmds = [] 7 | syntax_errors = [] 8 | 9 | 10 | if not os.path.isfile("exec_lint.log"): 11 | print("File does not exist") 12 | sys.exit(1) 13 | 14 | f = open("exec_lint.log", "r") 15 | lines = f.readlines() 16 | for line in lines: 17 | if line.strip() is None: 18 | continue 19 | 20 | # Remove [RUN CMD] lines 21 | if line.startswith("[RUN CMD]"): 22 | run_cmds.append(line.strip()) 23 | continue 24 | 25 | # Remove syntax errors 26 | if "syntax error" in line: 27 | syntax_errors.append(line.strip()) 28 | continue 29 | 30 | # Error type is hidden in 2 last square brackets 31 | line = line.split("[") 32 | error_code = "[" + line[-2].strip() + " [" + line[-1].strip() 33 | error_codes.append(error_code) 34 | 35 | dd = dict(Counter(error_codes)) 36 | total = 0 37 | print("=" * 20 + " Error statistics " + "=" * 20) 38 | for k in dd.keys(): 39 | print(k, dd[k]) 40 | total += dd[k] 41 | print(f"Total = {total}") 42 | 43 | print("=" * 20 + " Syntax errors " + "=" * 20) 44 | for syntax_error in syntax_errors: 45 | print(syntax_error) 46 | 47 | print("=" * 20 + " Used run cmds " + "=" * 20) 48 | for run_cmd in run_cmds: 49 | print(run_cmd) 50 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/broadcast_followed_by_i2c_data_vseq.sv: -------------------------------------------------------------------------------- 1 | class broadcast_followed_by_i2c_data_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(broadcast_followed_by_i2c_data_vseq) 7 | 8 | i3c_broadcast_followed_by_i2c_data_seq dev; 9 | i3c_broadcast_followed_by_i2c_data_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i3c_broadcast_followed_by_i2c_data_seq::type_id::create("dev"); 17 | host = i3c_broadcast_followed_by_i2c_data_seq::type_id::create("host"); 18 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr0 = i2c_addr0; 19 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr1 = i2c_addr1; 20 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr0 = i2c_addr0; 21 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr1 = i2c_addr1; 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.start(p_sequencer.m_i3c_sequencer_host); 27 | #(100*1us); 28 | end 29 | join_any 30 | disable fork; 31 | join 32 | endtask: body 33 | 34 | endclass : broadcast_followed_by_i2c_data_vseq 35 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/direct_i2c_with_rstart_vseq.sv: -------------------------------------------------------------------------------- 1 | class direct_i2c_with_rstart_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(direct_i2c_with_rstart_vseq) 7 | 8 | i2c_direct_data_seq dev; 9 | i2c_direct_data_with_rstart_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i2c_direct_data_seq::type_id::create("dev"); 17 | host = i2c_direct_data_with_rstart_seq::type_id::create("host"); 18 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr0 = i2c_addr0; 19 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr1 = i2c_addr1; 20 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr0 = i2c_addr0; 21 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr1 = i2c_addr1; 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.num_trans = num_trans; 27 | host.start(p_sequencer.m_i3c_sequencer_host); 28 | #(100*1us); 29 | this.randomize(num_trans); 30 | end 31 | join_any 32 | disable fork; 33 | join 34 | endtask: body 35 | 36 | endclass : direct_i2c_with_rstart_vseq 37 | -------------------------------------------------------------------------------- /tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/uvm/main.sv: -------------------------------------------------------------------------------- 1 | {% import 'uvm_reg.sv' as uvm_reg with context %} 2 | {% import 'uvm_vreg.sv' as uvm_vreg with context %} 3 | {% import 'uvm_reg_block-mem.sv' as uvm_reg_block_mem with context %} 4 | {% import 'uvm_reg_block.sv' as uvm_reg_block with context %} 5 | 6 | 7 | {% macro top() -%} 8 | {{include_covergroups(top_node)}} 9 | {%- for node in top_node.descendants(in_post_order=True) -%} 10 | {{child_def(node)}} 11 | {%- endfor -%} 12 | {{child_def(top_node)}} 13 | {{include_sample(top_node)}} 14 | {%- endmacro %} 15 | 16 | 17 | {% macro child_def(node) -%} 18 | {%- if isinstance(node, RegNode) -%} 19 | {%- if node.is_virtual -%} 20 | {{uvm_vreg.class_definition(node)}} 21 | {%- else -%} 22 | {{uvm_reg.class_definition(node)}} 23 | {%- endif -%} 24 | {%- elif isinstance(node, (RegfileNode, AddrmapNode)) -%} 25 | {{uvm_reg_block.class_definition(node)}} 26 | {%- elif isinstance(node, MemNode) -%} 27 | {{uvm_reg_block_mem.class_definition(node)}} 28 | {%- endif -%} 29 | {%- endmacro %} 30 | 31 | {% macro include_covergroups(node) -%} 32 | `include "{{get_class_name(node)}}_covergroups.svh" 33 | {%- endmacro %} 34 | 35 | {% macro include_sample(node) -%} 36 | `include "{{get_class_name(node)}}_sample.svh" 37 | {%- endmacro %} 38 | -------------------------------------------------------------------------------- /tools/vcd2pulseview/pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools"] 3 | build-backend = "setuptools.build_meta" 4 | 5 | [project] 6 | name = "vcd2pulseview" 7 | version = "0.1.0" 8 | requires-python = ">=3.6" 9 | 10 | authors = [ 11 | {name = "Antmicro", email = "contact@antmicro.com"}, 12 | {name = "Robert Szczepanski", email = "rszczepanski@antmicro.com"}, 13 | ] 14 | description = "Run a compatible waveform from the simulation generated VCD in a PulseView with the enabled decoder" 15 | readme = "README.md" 16 | license = {file = "LICENSE"} 17 | keywords = [ 18 | "tool", "pulseview", "gtkwave", "generator", "waveform", "viewer", "software", 19 | ] 20 | classifiers = [ 21 | "Development Status :: 3 - Alpha", 22 | "Programming Language :: Python", 23 | "Programming Language :: Python :: 3", 24 | "Programming Language :: Python :: 3.6", 25 | "Programming Language :: Python :: 3.7", 26 | "Programming Language :: Python :: 3.8", 27 | "Programming Language :: Python :: 3.9", 28 | "Programming Language :: Python :: 3.10", 29 | "Programming Language :: Python :: 3.11", 30 | "Programming Language :: Python :: 3.12", 31 | "Programming Language :: Python :: 3 :: Only", 32 | "Intended Audience :: Developers", 33 | "Operating System :: OS Independent", 34 | ] 35 | 36 | [project.scripts] 37 | vcd2pulseview = "vcd2pulseview:main" 38 | -------------------------------------------------------------------------------- /verification/uvm_i2c/push_pull_host_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Request sequence for Push and Pull protocols. 6 | // This sequence will send num_trans requests to the DUT. 7 | 8 | class push_pull_host_seq #(parameter int HostDataWidth = 32, 9 | parameter int DeviceDataWidth = HostDataWidth) 10 | extends push_pull_base_seq #(HostDataWidth, DeviceDataWidth); 11 | 12 | `uvm_object_param_utils(push_pull_host_seq#(HostDataWidth, DeviceDataWidth)) 13 | 14 | `uvm_object_new 15 | 16 | // Default to send 1 transactions. 17 | // Can be overridden at a higher layer. 18 | int unsigned num_trans = 1; 19 | 20 | // Randomizes the host req. 21 | virtual function void randomize_item(push_pull_item #(HostDataWidth, DeviceDataWidth) item); 22 | super.randomize_item(item); 23 | // If user-provided data is available, use it. 24 | if (cfg.has_h_user_data()) item.h_data = cfg.get_h_user_data(); 25 | endfunction 26 | 27 | virtual task body(); 28 | repeat (num_trans) begin : send_req 29 | `uvm_create(req) 30 | start_item(req); 31 | randomize_item(req); 32 | finish_item(req); 33 | get_response(rsp); 34 | end : send_req 35 | endtask 36 | 37 | endclass 38 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_env_cov.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class bit_toggle_cg_wrap; 6 | 7 | // Covergroup: bit_toggle_cg 8 | // Generic covergroup definition 9 | covergroup bit_toggle_cg(string name, string path = "", bit toggle_cov_en = 1) with function 10 | sample(bit value); 11 | option.per_instance = 1; 12 | option.name = (path == "") ? name : {path, "::", name}; 13 | 14 | cp_value: coverpoint value; 15 | cp_transitions: coverpoint value { 16 | option.weight = toggle_cov_en; 17 | bins rising = (0 => 1); 18 | bins falling = (1 => 0); 19 | } 20 | endgroup : bit_toggle_cg 21 | 22 | // Function: new 23 | function new(string name = "bit_toggle_cg_wrap", string path = "", bit toggle_cov_en = 1); 24 | bit_toggle_cg = new(name, path, toggle_cov_en); 25 | endfunction : new 26 | 27 | // Function: sample 28 | function void sample(bit value); 29 | bit_toggle_cg.sample(value); 30 | endfunction : sample 31 | 32 | endclass : bit_toggle_cg_wrap 33 | 34 | class dv_base_env_cov #(type CFG_T = dv_base_env_cfg) extends uvm_component; 35 | `uvm_component_param_utils(dv_base_env_cov #(CFG_T)) 36 | 37 | CFG_T cfg; 38 | 39 | `uvm_component_new 40 | 41 | endclass 42 | -------------------------------------------------------------------------------- /verification/uvm_i2c/rst_shadowed_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // 6 | // Interface: rst_shadowed_if 7 | // An interface to drive rst_shadowed_n pin 8 | // By default, the `rst_shadowed_n` pin is directly connected to `rst_n` pin from the IP. 9 | // This interface provide methods to drive `rst_shadowed_n` pin when `drive_shadow_rst_pin()` task is 10 | // called, and can use `reconnect_shadowed_rst_n_to_rst_n()` to reconnect to `rst_n` pin. 11 | interface rst_shadowed_if ( 12 | input rst_n, 13 | output rst_shadowed_n 14 | ); 15 | 16 | `ifndef VERILATOR 17 | // include macros and import pkgs 18 | `include "dv_macros.svh" 19 | `include "uvm_macros.svh" 20 | import uvm_pkg::*; 21 | `endif 22 | 23 | bit drive_shadowed_rst_en; 24 | logic shadowed_rst_n; 25 | 26 | // If set `drive_shadowed_rst_en` bit to 0, the `rst_shadowed_n` output will be the same as IP 27 | // level reset pin. 28 | function automatic void reconnect_shadowed_rst_n_to_rst_n(); 29 | drive_shadowed_rst_en = 0; 30 | endfunction 31 | 32 | task automatic drive_shadow_rst_pin(logic val); 33 | shadowed_rst_n = val; 34 | drive_shadowed_rst_en = 1; 35 | endtask 36 | 37 | assign rst_shadowed_n = drive_shadowed_rst_en ? shadowed_rst_n : rst_n; 38 | 39 | endinterface 40 | -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/alert_receiver_base_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this is a base sequence for alert_receiver side 6 | class alert_receiver_base_seq extends dv_base_seq #( 7 | .REQ (alert_esc_seq_item), 8 | .CFG_T (alert_esc_agent_cfg), 9 | .SEQUENCER_T (alert_esc_sequencer) 10 | ); 11 | 12 | `uvm_object_utils(alert_receiver_base_seq) 13 | 14 | `uvm_object_new 15 | 16 | rand bit r_alert_ping_send; 17 | rand bit r_alert_rsp; 18 | 19 | task body(); 20 | `uvm_info(`gfn, $sformatf("starting alert receiver transfer"), UVM_HIGH) 21 | req = alert_esc_seq_item::type_id::create("req"); 22 | start_item(req); 23 | `DV_CHECK_RANDOMIZE_WITH_FATAL(req, 24 | r_alert_ping_send == local::r_alert_ping_send; 25 | r_alert_rsp == local::r_alert_rsp; 26 | int_err == 0; // This agent do not support alert_receiver int_err 27 | ) 28 | `uvm_info(`gfn, $sformatf("seq_item: ping_send=%0b alert_rsp=%0b int_err=%0b", 29 | req.r_alert_ping_send, req.r_alert_rsp, req.int_err), UVM_MEDIUM) 30 | finish_item(req); 31 | get_response(rsp); 32 | `uvm_info(`gfn, "alert receiver transfer done", UVM_HIGH) 33 | endtask : body 34 | 35 | endclass : alert_receiver_base_seq 36 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_descriptor_rx/test_descriptor_rx.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | from cocotb_helpers import cycle, reset_n 4 | 5 | import cocotb 6 | from cocotb.clock import Clock 7 | from cocotb.handle import SimHandleBase 8 | from cocotb.triggers import ClockCycles 9 | 10 | 11 | async def setup(dut): 12 | """ """ 13 | dut.tti_rx_queue_full_i.value = 0 14 | await ClockCycles(dut.clk_i, 10) 15 | 16 | 17 | async def send_byte(dut, value): 18 | """ """ 19 | dut.rx_byte_i = value 20 | await cycle(dut.clk_i, dut.rx_byte_valid_i) 21 | 22 | 23 | @cocotb.test() 24 | async def test_descriptor_rx(dut: SimHandleBase): 25 | """ 26 | Test RX descriptor: 27 | - no errors 28 | - RX FIFO is never full 29 | """ 30 | cocotb.log.setLevel("INFO") 31 | clk = dut.clk_i 32 | rst_n = dut.rst_ni 33 | 34 | clock = Clock(clk, 2, units="ns") 35 | cocotb.start_soon(clock.start()) 36 | 37 | await setup(dut) 38 | await reset_n(clk, rst_n, cycles=5) 39 | 40 | assert dut.rx_byte_ready_o.value == 1 41 | 42 | # Send 5 bytes and wait for the RX descriptor 43 | for i in range(5): 44 | await send_byte(dut, i) 45 | await cycle(dut.clk_i, dut.rx_byte_last_i) 46 | 47 | await ClockCycles(dut.clk_i, 1) 48 | assert dut.tti_rx_desc_queue_wvalid_o.value == 1 49 | assert dut.tti_rx_desc_queue_wdata_o.value == 5 50 | 51 | await ClockCycles(dut.clk_i, 3) 52 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_descriptor_tx/test_descriptor_tx.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | from cocotb_helpers import cycle, reset_n 4 | 5 | import cocotb 6 | from cocotb.clock import Clock 7 | from cocotb.handle import SimHandleBase 8 | from cocotb.triggers import ClockCycles 9 | 10 | 11 | async def setup(dut): 12 | """ """ 13 | await ClockCycles(dut.clk_i, 10) 14 | 15 | 16 | @cocotb.test() 17 | async def test_descriptor_tx(dut: SimHandleBase): 18 | """ """ 19 | cocotb.log.setLevel("INFO") 20 | clk = dut.clk_i 21 | rst_n = dut.rst_ni 22 | 23 | clock = Clock(clk, 2, units="ns") 24 | cocotb.start_soon(clock.start()) 25 | 26 | await setup(dut) 27 | await reset_n(clk, rst_n, cycles=5) 28 | 29 | # Send descriptor 30 | 31 | dut.tti_tx_desc_queue_rdata_i.value = 0x5 32 | await cycle(dut.clk_i, dut.tti_tx_desc_queue_rvalid_i) 33 | 34 | # Send data 35 | dut.tti_tx_queue_rvalid_i.value = 1 36 | 37 | dut.tti_tx_queue_depth_i.value = 5 38 | data = [i for i in range(6)] 39 | data_id = 0 40 | dut.tti_tx_queue_rdata_i.value = data[data_id] 41 | 42 | for _ in range(5): 43 | await cycle(dut.clk_i, dut.tx_byte_ready_i) 44 | await ClockCycles(dut.clk_i, 3) 45 | data_id += 1 46 | dut.tti_tx_queue_rdata_i.value = data[data_id] 47 | 48 | print(dut.tx_byte_o.value) 49 | print(dut.tx_byte_last_o.value) 50 | print(dut.tx_byte_valid_o.value) 51 | -------------------------------------------------------------------------------- /verification/uvm_i2c/i2c_base_test.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class i2c_base_test extends cip_base_test #(.ENV_T(i2c_env), 6 | .CFG_T(i2c_env_cfg)); 7 | `uvm_component_utils(i2c_base_test) 8 | `uvm_component_new 9 | 10 | // the base class dv_base_test creates the following instances: 11 | // i2c_env_cfg: cfg 12 | // i2c_env: env 13 | 14 | // the base class also looks up UVM_TEST_SEQ plusarg to create and 15 | // run that seq in the run_phase; as such, nothing more needs to be done 16 | 17 | virtual function void build_phase(uvm_phase phase); 18 | if_mode_e mode = Device; 19 | test_timeout_ns = 600_000_000; // 600ms 20 | super.build_phase(phase); 21 | `DV_GET_ENUM_PLUSARG(if_mode_e, mode, i2c_agent_mode) 22 | `uvm_info(`gfn, $sformatf("set i2c agent mode to %s", mode.name), UVM_MEDIUM) 23 | cfg.m_i2c_agent_cfg.if_mode = mode; 24 | void'($value$plusargs("use_intr_handler=%0b", cfg.use_intr_handler)); 25 | void'($value$plusargs("slow_acq=%0b", cfg.slow_acq)); 26 | void'($value$plusargs("i2c_wr_pct=%0d", cfg.wr_pct)); 27 | void'($value$plusargs("i2c_rd_pct=%0d", cfg.rd_pct)); 28 | void'($value$plusargs("i2c_bad_addr_pct=%0d", cfg.bad_addr_pct)); 29 | endfunction : build_phase 30 | 31 | endclass : i2c_base_test 32 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/broadcast_followed_by_data_with_rstart_vseq.sv: -------------------------------------------------------------------------------- 1 | class broadcast_followed_by_data_with_rstart_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(broadcast_followed_by_data_with_rstart_vseq) 7 | 8 | i3c_broadcast_followed_by_data_seq dev; 9 | i3c_broadcast_followed_by_data_with_rstart_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i3c_broadcast_followed_by_data_seq::type_id::create("dev"); 17 | host = i3c_broadcast_followed_by_data_with_rstart_seq::type_id::create("host"); 18 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_dev.i3c_target0), 19 | .t1(m_cfg.m_i3c_agent_cfg_dev.i3c_target1)); 20 | prep_cfg(.t0(m_cfg.m_i3c_agent_cfg_host.i3c_target0), 21 | .t1(m_cfg.m_i3c_agent_cfg_host.i3c_target1)); 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.num_trans = num_trans; 27 | host.start(p_sequencer.m_i3c_sequencer_host); 28 | #(100*1us); 29 | this.randomize(num_trans); 30 | end 31 | join_any 32 | disable fork; 33 | join 34 | endtask: body 35 | 36 | endclass : broadcast_followed_by_data_with_rstart_vseq 37 | -------------------------------------------------------------------------------- /src/phy/i3c_phy.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | /* 3 | This module provides double flip-flop synchronization to the system clock. 4 | */ 5 | module i3c_phy ( 6 | input logic clk_i, 7 | input logic rst_ni, 8 | 9 | // I3C bus IO 10 | input logic scl_i, 11 | output logic scl_o, 12 | 13 | input logic sda_i, 14 | output logic sda_o, 15 | 16 | // I3C controller IO 17 | input logic ctrl_scl_i, 18 | input logic ctrl_sda_i, 19 | 20 | output logic ctrl_scl_o, 21 | output logic ctrl_sda_o, 22 | 23 | // Open-Drain / Push-Pull control 24 | input logic sel_od_pp_i, 25 | output logic sel_od_pp_o 26 | ); 27 | 28 | `ifndef DISABLE_INPUT_FF 29 | 30 | // Synchronize SCL to system clock 31 | caliptra_prim_flop_2sync #( 32 | .Width(1), 33 | .ResetValue(1) 34 | ) scl_synchronizer ( 35 | .clk_i(clk_i), 36 | .rst_ni(rst_ni), 37 | .d_i(scl_i), 38 | .q_o(ctrl_scl_o) 39 | ); 40 | 41 | // Synchronize SDA to system clock 42 | caliptra_prim_flop_2sync #( 43 | .Width(1), 44 | .ResetValue(1) 45 | ) sda_synchronizer ( 46 | .clk_i(clk_i), 47 | .rst_ni(rst_ni), 48 | .d_i(sda_i), 49 | .q_o(ctrl_sda_o) 50 | ); 51 | 52 | `else 53 | 54 | assign ctrl_sda_o = sda_i; 55 | assign ctrl_scl_o = scl_i; 56 | 57 | `endif 58 | 59 | assign sda_o = ctrl_sda_i; 60 | assign scl_o = ctrl_scl_i; 61 | assign sel_od_pp_o = sel_od_pp_i; 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_tlul/tl_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // --------------------------------------------- 6 | // TileLink interface 7 | // --------------------------------------------- 8 | interface tl_if(input clk, input rst_n); 9 | 10 | wire tlul_pkg::tl_h2d_t h2d; // req 11 | wire tlul_pkg::tl_d2h_t d2h; // rsp 12 | 13 | tlul_pkg::tl_h2d_t h2d_int; // req (internal) 14 | tlul_pkg::tl_d2h_t d2h_int; // rsp (internal) 15 | 16 | dv_utils_pkg::if_mode_e if_mode; // interface mode - Host or Device 17 | 18 | modport dut_host_mp(output h2d_int, input d2h_int); 19 | modport dut_device_mp(input h2d_int, output d2h_int); 20 | 21 | clocking host_cb @(posedge clk); 22 | input rst_n; 23 | output h2d_int; 24 | input d2h; 25 | endclocking 26 | modport host_mp(clocking host_cb); 27 | 28 | clocking device_cb @(posedge clk); 29 | input rst_n; 30 | input h2d; 31 | output d2h_int; 32 | endclocking 33 | modport device_mp(clocking device_cb); 34 | 35 | clocking mon_cb @(posedge clk); 36 | input rst_n; 37 | input h2d; 38 | input d2h; 39 | endclocking 40 | modport mon_mp(clocking mon_cb); 41 | 42 | assign h2d = (if_mode == dv_utils_pkg::Host) ? h2d_int : 'z; 43 | assign d2h = (if_mode == dv_utils_pkg::Device) ? d2h_int : 'z; 44 | 45 | endinterface : tl_if 46 | -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/alert_sender_base_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this is a base sequence for alert sender side 6 | class alert_sender_base_seq extends dv_base_seq #( 7 | .REQ (alert_esc_seq_item), 8 | .CFG_T (alert_esc_agent_cfg), 9 | .SEQUENCER_T (alert_esc_sequencer) 10 | ); 11 | 12 | `uvm_object_utils(alert_sender_base_seq) 13 | `uvm_object_new 14 | 15 | rand bit s_alert_send; 16 | rand bit s_alert_ping_rsp; 17 | rand bit int_err; 18 | rand bit ping_timeout; 19 | 20 | virtual task body(); 21 | `uvm_info(`gfn, $sformatf("starting alert sender transfer"), UVM_HIGH) 22 | req = alert_esc_seq_item::type_id::create("req"); 23 | start_item(req); 24 | `DV_CHECK_RANDOMIZE_WITH_FATAL(req, 25 | s_alert_send == local::s_alert_send; 26 | s_alert_ping_rsp == local::s_alert_ping_rsp; 27 | int_err == local::int_err; 28 | ping_timeout == local::ping_timeout; 29 | ) 30 | `uvm_info(`gfn, $sformatf("seq_item: send_alert=%0b, ping_rsp=%0b, int_err=%0b", 31 | req.s_alert_send, req.s_alert_ping_rsp, req.int_err), UVM_MEDIUM) 32 | finish_item(req); 33 | get_response(rsp); 34 | `uvm_info(`gfn, "alert sender transfer done", UVM_HIGH) 35 | endtask : body 36 | 37 | endclass : alert_sender_base_seq 38 | -------------------------------------------------------------------------------- /tools/simulators/Makefile.questa: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | # TODO: Confirm that this Makefile works 4 | ifeq (, $(shell which qrun)) 5 | $(warning WARNING: SIMULATOR: Questa is not in PATH.) 6 | endif 7 | 8 | QUESTA_ROOT := $(abspath $(shell which qrun)/../../) 9 | UVM_TB_FILES ?= $(I3C_ROOT_DIR)/verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sim.scr \ 10 | $(I3C_ROOT_DIR)/verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/tb_sequencer.sv 11 | UVM_TESTNAME ?= i3c_sequence_test 12 | UVM_VSEQ_TEST ?= direct_vseq 13 | EXTRA_BUILD_ARGS ?= 14 | EXTRA_RUN_ARGS ?= 15 | 16 | QUESTA = qrun 17 | QUESTA_WORKDIR = questa_work 18 | 19 | BUILD_ARGS = -optimize +define+VW_QSTA -sv -timescale 1ns/1ps -uvm \ 20 | +incdir+$(QUESTA_ROOT)/verilog_src/uvm-1.2/src/ \ 21 | -uvmhome $(QUESTA_ROOT)/verilog_src/uvm-1.2 22 | RUN_ARGS = +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES \ 23 | +UVM_VERBOSITY=UVM_LOW -suppress vsim-8323 -64 24 | 25 | # If need to use external uvm 26 | # -uvmexthome $(QUESTA_ROOT)/verilog_src/questa_uvm_pkg-1.2 27 | 28 | questa-build: 29 | $(QUESTA) $(BUILD_ARGS) \ 30 | -outdir $(QUESTA_WORKDIR) \ 31 | -mfcu -f $(UVM_TB_FILES) \ 32 | -voptargs="+acc=nr" $(EXTRA_BUILD_ARGS) 33 | 34 | questa: questa-build 35 | $(QUESTA) -simulate \ 36 | -outdir $(QUESTA_WORKDIR) \ 37 | +UVM_TESTNAME=$(UVM_TESTNAME) \ 38 | +UVM_TEST_SEQ=$(UVM_TEST_SEQ) \ 39 | -log $(QUESTA_WORKDIR)/run.log \ 40 | $(EXTRA_RUN_ARGS) 41 | -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/esc_receiver_base_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this is a base sequence for esc_receiver side 6 | class esc_receiver_base_seq extends dv_base_seq #( 7 | .REQ (alert_esc_seq_item), 8 | .CFG_T (alert_esc_agent_cfg), 9 | .SEQUENCER_T (alert_esc_sequencer) 10 | ); 11 | 12 | `uvm_object_utils(esc_receiver_base_seq) 13 | `uvm_object_new 14 | 15 | rand bit int_err; 16 | rand bit r_esc_rsp; 17 | rand bit standalone_int_err; 18 | rand bit ping_timeout; 19 | 20 | virtual task body(); 21 | `uvm_info(`gfn, $sformatf("starting escalator receiver transfer"), UVM_HIGH) 22 | req = alert_esc_seq_item::type_id::create("req"); 23 | start_item(req); 24 | `DV_CHECK_RANDOMIZE_WITH_FATAL(req, 25 | r_esc_rsp == local::r_esc_rsp; 26 | int_err == local::int_err; 27 | standalone_int_err == local::standalone_int_err; 28 | ping_timeout == local::ping_timeout; 29 | ) 30 | `uvm_info(`gfn, $sformatf("seq_item: esc_rsp=%0b, int_err=%0b, ping_timeout=%0b", 31 | req.r_esc_rsp, req.int_err, req.ping_timeout), UVM_MEDIUM) 32 | finish_item(req); 33 | get_response(rsp); 34 | `uvm_info(`gfn, "escalator receiver transfer done", UVM_HIGH) 35 | endtask : body 36 | 37 | endclass : esc_receiver_base_seq 38 | -------------------------------------------------------------------------------- /verification/cocotb/block/axi_adapter/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | # Set appropriate bus interface via Cocotb's PLUSARGS: 13 | override PLUSARGS := $(strip +FrontendBusInterface=AXI $(PLUSARGS)) 14 | 15 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 16 | TOPLEVEL = axi_adapter_wrapper 17 | override CFG_NAME = axi 18 | 19 | VERILOG_SOURCES = \ 20 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_pkg.sv \ 21 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv \ 22 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_count_pkg.sv \ 23 | $(SRC_DIR)/i3c_pkg.sv \ 24 | $(CALIPTRA_ROOT)/src/axi/rtl/axi_pkg.sv \ 25 | $(CALIPTRA_ROOT)/src/axi/rtl/axi_if.sv \ 26 | $(CALIPTRA_ROOT)/src/axi/rtl/axi_addr.v \ 27 | $(CALIPTRA_ROOT)/src/libs/rtl/skidbuffer.v \ 28 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub_wr.sv \ 29 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub_arb.sv \ 30 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub_rd.sv \ 31 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub.sv \ 32 | $(SRC_DIR)/csr/I3CCSR_pkg.sv \ 33 | $(SRC_DIR)/csr/I3CCSR.sv \ 34 | $(SRC_DIR)/hci/axi_adapter.sv \ 35 | $(TEST_DIR)/../lib_adapter/axi_adapter_wrapper.sv 36 | 37 | include $(TEST_DIR)/../block_common.mk 38 | -------------------------------------------------------------------------------- /verification/testplan/block/csr_sw_access.hjson: -------------------------------------------------------------------------------- 1 | { 2 | name: csr_sw_access 3 | testpoints: 4 | [ 5 | { 6 | name: read_hci_version_csr 7 | desc: Reads the HCI version CSR and verifies its content. 8 | tests: ["read_hci_version_csr"] 9 | tags: ["adapter"] 10 | } 11 | { 12 | name: read_pio_section_offset 13 | desc: Reads the PIO_SECTION_OFFSET CSR and verifies its content. 14 | tests: ["read_pio_section_offset"] 15 | tags: ["adapter"] 16 | } 17 | { 18 | name: write_to_controller_device_addr 19 | desc: "Writes to the CONTROLLER_DEVICE_ADDR CSR and verifies if the write was successful." 20 | tests: ["write_to_controller_device_addr"] 21 | tags: ["adapter"] 22 | } 23 | { 24 | name: write_should_not_affect_ro_csr 25 | desc: 26 | ''' 27 | Writes to the HC_CAPABILITIES CSR which is read-only for software. 28 | Verifies that the write did not succeed. 29 | ''' 30 | tests: ["write_should_not_affect_ro_csr"] 31 | tags: ["adapter"] 32 | } 33 | { 34 | name: sequence_csr_read 35 | desc: Performs a sequence of CSR reads. Verifies that each one succeeds. 36 | tests: ["sequence_csr_read"] 37 | tags: ["adapter"] 38 | } 39 | { 40 | name: sequence_csr_write 41 | desc: Performs a sequence of CSR writes. Verifies that each one succeeds. 42 | tests: ["sequence_csr_write"] 43 | tags: ["adapter"] 44 | } 45 | ] 46 | } 47 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sequence_vseqs/broadcast_followed_by_i2c_data_with_rstart_vseq.sv: -------------------------------------------------------------------------------- 1 | class broadcast_followed_by_i2c_data_with_rstart_vseq extends base_vseq #( 2 | .CFG_T (i3c_sequence_env_cfg), 3 | .VIRTUAL_SEQUENCER_T (i3c_sequence_virtual_sequencer) 4 | ); 5 | 6 | `uvm_object_utils(broadcast_followed_by_i2c_data_with_rstart_vseq) 7 | 8 | i3c_broadcast_followed_by_i2c_data_seq dev; 9 | i3c_broadcast_followed_by_i2c_data_with_rstart_seq host; 10 | 11 | function new (string name=""); 12 | super.new(name); 13 | endfunction : new 14 | 15 | task body(); 16 | dev = i3c_broadcast_followed_by_i2c_data_seq::type_id::create("dev"); 17 | host = i3c_broadcast_followed_by_i2c_data_with_rstart_seq::type_id::create("host"); 18 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr0 = i2c_addr0; 19 | m_cfg.m_i3c_agent_cfg_dev.i2c_target_addr1 = i2c_addr1; 20 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr0 = i2c_addr0; 21 | m_cfg.m_i3c_agent_cfg_host.i2c_target_addr1 = i2c_addr1; 22 | fork 23 | fork 24 | dev.start(p_sequencer.m_i3c_sequencer_dev); 25 | for (int i=0; i < num_runs; i++) begin 26 | host.num_trans = num_trans; 27 | host.start(p_sequencer.m_i3c_sequencer_host); 28 | #(100*1us); 29 | this.randomize(num_trans); 30 | end 31 | join_any 32 | disable fork; 33 | join 34 | endtask: body 35 | 36 | endclass : broadcast_followed_by_i2c_data_with_rstart_vseq 37 | -------------------------------------------------------------------------------- /tools/simulators/Makefile.dsim: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | ifeq (, $(shell which dsim)) 4 | $(warning WARNING: SIMULATOR: dsim is not in PATH.) 5 | endif 6 | 7 | UVM_TB_FILES ?= $(I3C_ROOT_DIR)/verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/i3c_sim.scr \ 8 | $(I3C_ROOT_DIR)/verification/uvm_i3c/dv_i3c/i3c_agent_unit_tests/tb_sequencer.sv 9 | UVM_TESTNAME ?= i3c_sequence_test 10 | UVM_VSEQ_TEST ?= direct_vseq 11 | EXTRA_BUILD_ARGS ?= 12 | EXTRA_RUN_ARGS ?= 13 | 14 | IMAGE = i3c 15 | DSIM = dsim 16 | DSIM_WORKDIR = dsim_work 17 | DSIM_METRICS = dsim_metrics.db 18 | DSIM_DEBUG_RUN = -waves sim.vcd 19 | 20 | BUILD_ARGS = -sv +acc+b -uvm 1.2 -timescale 1ns/1ps -all-class-spec -all-pkgs -j $(NUM_PROC) 21 | RUN_ARGS = +acc+rwb -uvm 1.2 -waves dump.vcd 22 | 23 | EXTRA_REG_GEN_ARGS := $(EXTRA_REG_GEN_ARGS) \ 24 | --ral-template $(I3C_ROOT_DIR)/tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/uvm \ 25 | --cov-template $(I3C_ROOT_DIR)/tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/cov \ 26 | --smp-template $(I3C_ROOT_DIR)/tools/reg_gen/peakrdl_uvm_templates/dsim_caliptra/smp 27 | 28 | dsim-build: 29 | $(DSIM) -genimage $(IMAGE) -work $(DSIM_WORKDIR) $(BUILD_ARGS) \ 30 | -f $(UVM_TB_FILES) $(EXTRA_BUILD_ARGS) 31 | 32 | dsim: dsim-build 33 | $(DSIM) -image $(IMAGE) -work $(DSIM_WORKDIR) $(RUN_ARGS) \ 34 | -cov-db $(DSIM_WORKDIR)/$(DSIM_METRICS) \ 35 | +UVM_TESTNAME=$(UVM_TESTNAME) \ 36 | +UVM_TEST_SEQ=$(UVM_VSEQ_TEST) \ 37 | $(EXTRA_RUN_ARGS) 38 | -------------------------------------------------------------------------------- /verification/uvm_i2c/esc_sender_driver.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | 6 | // --------------------------------------------- 7 | // Esc sender driver 8 | // --------------------------------------------- 9 | class esc_sender_driver extends alert_esc_base_driver; 10 | 11 | `uvm_component_utils(esc_sender_driver) 12 | 13 | `uvm_component_new 14 | 15 | virtual task reset_signals(); 16 | do_reset(); 17 | forever begin 18 | @(negedge cfg.vif.rst_n); 19 | under_reset = 1; 20 | do_reset(); 21 | @(posedge cfg.vif.rst_n); 22 | under_reset = 0; 23 | end 24 | endtask 25 | 26 | virtual task get_and_drive(); 27 | // LC_CTRL uses virtual interface to directly drive escalation requests. 28 | // Other escalation handshakes are checked in prim_esc direct sequence. 29 | // So the following task is not implemented. 30 | drive_esc(); 31 | endtask : get_and_drive 32 | 33 | virtual task drive_esc(); 34 | // LC_CTRL uses virtual interface to directly drive escalation requests. 35 | // Other escalation handshakes are checked in prim_esc direct sequence. 36 | // So this task is not implemented. 37 | wait(!under_reset); 38 | endtask 39 | 40 | virtual task do_reset(); 41 | cfg.vif.esc_tx_int.esc_p <= 1'b0; 42 | cfg.vif.esc_tx_int.esc_n <= 1'b1; 43 | endtask 44 | endclass : esc_sender_driver 45 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_sequencer.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class dv_base_sequencer #(type ITEM_T = uvm_sequence_item, 6 | type CFG_T = dv_base_agent_cfg, 7 | type RSP_ITEM_T = ITEM_T) 8 | extends uvm_sequencer #(.REQ(ITEM_T), .RSP(RSP_ITEM_T)); 9 | 10 | `uvm_component_param_utils(dv_base_sequencer #(.ITEM_T (ITEM_T), 11 | .CFG_T (CFG_T), 12 | .RSP_ITEM_T (RSP_ITEM_T))) 13 | 14 | // These fifos collects items when req/rsp is received, which are used to communicate between 15 | // monitor and sequences. These fifos are optional 16 | // When device is re-active, it gets items from req_analysis_fifo and send rsp to driver 17 | // When this is a high-level agent, monitors put items to these 2 fifos for high-level seq 18 | uvm_tlm_analysis_fifo #(ITEM_T) req_analysis_fifo; 19 | uvm_tlm_analysis_fifo #(RSP_ITEM_T) rsp_analysis_fifo; 20 | 21 | CFG_T cfg; 22 | 23 | `uvm_component_new 24 | 25 | function void build_phase(uvm_phase phase); 26 | super.build_phase(phase); 27 | if (cfg.has_req_fifo) req_analysis_fifo = new("req_analysis_fifo", this); 28 | if (cfg.has_rsp_fifo) rsp_analysis_fifo = new("rsp_analysis_fifo", this); 29 | endfunction : build_phase 30 | 31 | endclass 32 | -------------------------------------------------------------------------------- /verification/cocotb/top/lib_i3c_top/interface.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | from bus2csr import get_frontend_bus_if 4 | from cocotb_helpers import reset_n 5 | from reg_map import reg_map 6 | 7 | import cocotb 8 | from cocotb.handle import SimHandleBase 9 | 10 | 11 | class I3CTopTestInterface: 12 | 13 | def __init__(self, dut: SimHandleBase) -> None: 14 | self.dut = dut 15 | self.bus_if_cls = get_frontend_bus_if() 16 | self.reg_map = reg_map 17 | 18 | self.busIf = self.bus_if_cls(dut) 19 | self.clk = self.busIf.clk 20 | self.rst_n = self.busIf.rst_n 21 | self.read_csr = self.busIf.read_csr 22 | self.write_csr = self.busIf.write_csr 23 | self.read_csr_field = self.busIf.read_csr_field 24 | self.write_csr_field = self.busIf.write_csr_field 25 | 26 | async def setup(self, fclk=500.0): 27 | 28 | # Limit the requested clock frequency if a limit is set via cocotb 29 | # plusargs 30 | fmin = cocotb.plusargs.get("MinSystemClockFrequency", None) 31 | if fmin is not None: 32 | fmin = float(fmin) 33 | if fclk < fmin: 34 | self.dut._log.warning(f"Enforcing min. system clock frequency of {fmin:.3f} MHz") 35 | fclk = fmin 36 | 37 | if hasattr(self.dut, "disable_id_filtering_i"): 38 | self.dut.disable_id_filtering_i.value = 1 39 | 40 | await self.busIf.register_test_interfaces(fclk) 41 | await reset_n(self.clk, self.rst_n, cycles=5) 42 | -------------------------------------------------------------------------------- /src/libs/mem/prim_ram_1p.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Abstract primitives wrapper. 6 | // 7 | // This file is a stop-gap until the DV file list is generated by FuseSoC. 8 | // Its contents are taken from the file which would be generated by FuseSoC. 9 | // https://github.com/lowRISC/ibex/issues/893 10 | 11 | module prim_ram_1p import prim_ram_1p_pkg::*; 12 | 13 | #( 14 | 15 | parameter int Width = 32, // bit 16 | parameter int Depth = 128, 17 | parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask 18 | parameter MemInitFile = "", // VMEM file to initialize the memory width 19 | 20 | localparam int Aw = $clog2(Depth) // derived parameter 21 | 22 | ) ( 23 | input logic clk_i, 24 | input ram_1p_cfg_t cfg_i, 25 | 26 | input logic req_i, 27 | input logic write_i, 28 | input logic [Aw-1:0] addr_i, 29 | input logic [Width-1:0] wdata_i, 30 | input logic [Width-1:0] wmask_i, 31 | output logic [Width-1:0] rdata_o // Read data. Data is returned one cycle after req_i is high. 32 | ); 33 | 34 | if (1) begin : gen_generic 35 | prim_generic_ram_1p #( 36 | .Depth(Depth), 37 | .MemInitFile(MemInitFile), 38 | .Width(Width), 39 | .DataBitsPerMask(DataBitsPerMask) 40 | ) u_impl_generic ( 41 | .* 42 | ); 43 | 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /verification/cocotb/block/axi_adapter_id_filter/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | null := 4 | space := $(null) # 5 | comma := , 6 | 7 | TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) 8 | SRC_DIR := $(abspath $(TEST_DIR)../../../../../src) 9 | 10 | TEST_FILES = $(sort $(wildcard test_*.py)) 11 | 12 | # Set appropriate bus interface via Cocotb's PLUSARGS: 13 | override PLUSARGS := $(strip +FrontendBusInterface=AXI $(PLUSARGS)) 14 | 15 | MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) 16 | TOPLEVEL = axi_adapter_wrapper 17 | override CFG_NAME = axi 18 | override CFG_FILE = $(TEST_DIR)/i3c_cfg.yaml 19 | 20 | VERILOG_SOURCES = \ 21 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_pkg.sv \ 22 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv \ 23 | $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_count_pkg.sv \ 24 | $(SRC_DIR)/i3c_pkg.sv \ 25 | $(CALIPTRA_ROOT)/src/axi/rtl/axi_pkg.sv \ 26 | $(CALIPTRA_ROOT)/src/axi/rtl/axi_if.sv \ 27 | $(CALIPTRA_ROOT)/src/axi/rtl/axi_addr.v \ 28 | $(CALIPTRA_ROOT)/src/libs/rtl/skidbuffer.v \ 29 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub_wr.sv \ 30 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub_arb.sv \ 31 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub_rd.sv \ 32 | $(SRC_DIR)/libs/axi_sub/i3c_axi_sub.sv \ 33 | $(SRC_DIR)/csr/I3CCSR_pkg.sv \ 34 | $(SRC_DIR)/csr/I3CCSR.sv \ 35 | $(SRC_DIR)/hci/axi_adapter.sv \ 36 | $(TEST_DIR)/../lib_adapter/axi_adapter_wrapper.sv 37 | 38 | include $(TEST_DIR)/../block_common.mk 39 | -------------------------------------------------------------------------------- /verification/cocotb/block/ctrl_bus_timers/test_bus_timers.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | from cocotb_helpers import cycle, reset_n 4 | 5 | import cocotb 6 | from cocotb.clock import Clock 7 | from cocotb.handle import SimHandleBase 8 | from cocotb.triggers import ClockCycles 9 | 10 | 11 | async def setup(dut): 12 | """ 13 | Happy path testing: 14 | - t_bus_available_i > t_bus_free_i 15 | - t_bus_idle_i >> t_bus_available_i 16 | - t_bus_idle_i >> t_bus_free_i 17 | """ 18 | dut.t_bus_free_i.value = 5 19 | dut.t_bus_available_i.value = 10 20 | dut.t_bus_idle_i.value = 50 21 | dut.restart_counter_i.value = 0 22 | 23 | 24 | @cocotb.test() 25 | async def test_bus_timers(dut: SimHandleBase): 26 | """ 27 | Test bus timers 28 | """ 29 | # Start clock 30 | clock = Clock(dut.clk_i, 2, units="ns") 31 | cocotb.start_soon(clock.start()) 32 | 33 | clk = dut.clk_i 34 | rst_n = dut.rst_ni 35 | 36 | await setup(dut) 37 | await reset_n(clk, rst_n, cycles=5) 38 | 39 | # Enable counter 40 | dut.enable_i.value = 1 41 | 42 | for _ in range(3): 43 | await cycle(dut.clk_i, dut.restart_counter_i) 44 | await ClockCycles(dut.clk_i, 1) 45 | assert dut.bus_free_o.value == 0 46 | assert dut.bus_available_o.value == 0 47 | assert dut.bus_idle_o.value == 0 48 | await ClockCycles(dut.clk_i, 75) 49 | assert dut.bus_free_o.value == 1 50 | assert dut.bus_available_o.value == 1 51 | assert dut.bus_idle_o.value == 1 52 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_host_fifo_fmt_empty_vseq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // i2c_fifo_reset_fmt test vseq 6 | // this sequence fills fmt fifo with random bytes and resets fmt fifo. 7 | // checks for fifo empty high 8 | class i2c_host_fifo_fmt_empty_vseq extends i2c_rx_tx_vseq; 9 | `uvm_object_utils(i2c_host_fifo_fmt_empty_vseq) 10 | `uvm_object_new 11 | 12 | i2c_item fmt_item; 13 | 14 | virtual task pre_start(); 15 | super.pre_start(); 16 | print_seq_cfg_vars("pre-start"); 17 | endtask : pre_start 18 | 19 | virtual task body(); 20 | bit do_interrupt; 21 | initialization(); 22 | `uvm_info(`gfn, "\n--> start of sequence", UVM_DEBUG) 23 | fork 24 | begin 25 | while (!cfg.under_reset && do_interrupt) process_interrupts(); 26 | end 27 | begin 28 | for (uint i = 1; i <= num_trans; i++) begin 29 | do_interrupt = 1'b1; 30 | host_send_trans(.max_trans(1), .trans_type(WriteOnly), .read(0), .stopbyte(1)); 31 | do_interrupt = 1'b0; // gracefully stop process_interrupts 32 | csr_rd_check(.ptr(ral.status.fmtempty), .compare_value(1)); 33 | `DV_CHECK_EQ(cfg.lastbyte, 8'hee) 34 | cfg.lastbyte = 8'h00; 35 | end 36 | end 37 | join 38 | `uvm_info(`gfn, "\n--> end of sequence", UVM_DEBUG) 39 | endtask : body 40 | 41 | endclass : i2c_host_fifo_fmt_empty_vseq 42 | -------------------------------------------------------------------------------- /tools/vcd2pulseview/README.md: -------------------------------------------------------------------------------- 1 | # VCD to PulseView 2 | 3 | This tool converts VCD to contain just signals specifiec by the TCL script provided for the GTKWave. 4 | The generated VCD is then loaded to PulseView with a provided configuration file. 5 | It provides additional flags and default setup. 6 | 7 | # Prerequisites 8 | 9 | In order to succesfully use this tool, first install: 10 | * Python 3 11 | * GTKWave with TCL support (<= [0bc00e1](https://github.com/gtkwave/gtkwave/tree/0bc00e129123278313d3e042250cb5004cb66d09)) 12 | * PulseView 13 | 14 | # Usage 15 | ```bash 16 | vcd2pulseview --waveform waves.vcd 17 | ``` 18 | 19 | The default script run will extract SCL and SDA signals from the provided VCD and will run PulseView with the I2C analyzer enabled. 20 | There are multiple arguments to alter the default behavior: 21 | * `--no-vcd-update` - omits generating new VCD file, useful if you want to run PulseView with the analyzer on old VCD 22 | * `--no-run-pulseview` - omits running PulseView, useful to just regenerate VCD which can be reloaded in the PulseView GUI 23 | * `--pulseview-config config.cfg` - provides a custom config file for the PulseView which might be used to load different decoder or alter the view 24 | * `--gtkwave-config` - provides a custom TCL script for GTKWave which might be used to extract different signals from the generated VCD 25 | 26 | **Note:** In case of the default GTKWave TCL script, it will extract SDA and SCL signals properly but since they might be extracted from a hierarchy, they might require manual adding to the analyzer in PulseView. 27 | -------------------------------------------------------------------------------- /verification/uvm_i2c/cip_lib/cip_base_test.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class cip_base_test #(type CFG_T = cip_base_env_cfg, 6 | type ENV_T = cip_base_env) extends dv_base_test #(CFG_T, ENV_T); 7 | `uvm_component_param_utils(cip_base_test #(CFG_T, ENV_T)) 8 | 9 | `uvm_component_new 10 | 11 | virtual function void add_message_demotes(dv_report_catcher catcher); 12 | string msg; 13 | bit create_jtag_riscv_map; 14 | super.add_message_demotes(catcher); 15 | 16 | // Cannot use `cfg` because it has not been created. 17 | void'($value$plusargs("create_jtag_riscv_map=%0b", create_jtag_riscv_map)); 18 | if (create_jtag_riscv_map) begin 19 | // Demote address maps warnings 20 | msg = "\s*map .* does not seem to be initialized correctly.*"; 21 | catcher.add_change_sev("RegModel", msg, UVM_INFO); 22 | end 23 | endfunction 24 | 25 | virtual task run_phase(uvm_phase phase); 26 | // Disable random delays in specific `prim_cdc_rand_delay`s even if CDC instrumentation is 27 | // enabled. (See `cip_base_env_cfg` for details.) 28 | foreach (cfg.disabled_prim_cdc_rand_delays[i]) begin 29 | string path = {cfg.disabled_prim_cdc_rand_delays[i], 30 | ".gen_enable.cdc_instrumentation_enabled"}; 31 | `DV_CHECK(uvm_hdl_force(path, 1'b0)); 32 | end 33 | super.run_phase(phase); 34 | endtask 35 | 36 | endclass : cip_base_test 37 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/vseqs/i2c_vseq_list.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | `include "i2c_base_vseq.sv" 6 | `include "i2c_common_vseq.sv" 7 | `include "i2c_rx_tx_vseq.sv" 8 | `include "i2c_host_smoke_vseq.sv" 9 | 10 | `include "i2c_host_override_vseq.sv" 11 | `include "i2c_host_fifo_watermark_vseq.sv" 12 | `include "i2c_host_fifo_overflow_vseq.sv" 13 | `include "i2c_host_fifo_reset_fmt_vseq.sv" 14 | `include "i2c_host_fifo_fmt_empty_vseq.sv" 15 | `include "i2c_host_fifo_reset_rx_vseq.sv" 16 | `include "i2c_host_timeout_vseq.sv" 17 | `include "i2c_host_rx_oversample_vseq.sv" 18 | `include "i2c_host_fifo_full_vseq.sv" 19 | `include "i2c_host_perf_vseq.sv" 20 | `include "i2c_host_stretch_timeout_vseq.sv" 21 | `include "i2c_host_error_intr_vseq.sv" 22 | `include "i2c_host_stress_all_vseq.sv" 23 | `include "i2c_target_smoke_vseq.sv" 24 | `include "i2c_target_perf_vseq.sv" 25 | `include "i2c_target_runtime_base_vseq.sv" 26 | `include "i2c_target_stress_wr_vseq.sv" 27 | `include "i2c_target_stress_rd_vseq.sv" 28 | `include "i2c_target_stretch_vseq.sv" 29 | `include "i2c_target_timeout_vseq.sv" 30 | `include "i2c_target_ack_stop_vseq.sv" 31 | `include "i2c_target_fifo_reset_acq_vseq.sv" 32 | `include "i2c_target_fifo_reset_tx_vseq.sv" 33 | `include "i2c_target_stress_all_vseq.sv" 34 | `include "i2c_target_hrst_vseq.sv" 35 | `include "i2c_host_mode_toggle_vseq.sv" 36 | `include "i2c_glitch_vseq.sv" 37 | `include "i2c_host_may_nack_vseq.sv" 38 | -------------------------------------------------------------------------------- /tools/i3c_config/py2svh.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | import os 4 | 5 | from common import I3CCoreConfig, I3CGenericConfig 6 | from jinja2 import Environment, FileSystemLoader 7 | 8 | 9 | # Traverse I3CCoreConfig and pass it to the SVH configuration template 10 | class DefinesSVH: 11 | """ 12 | 'I3CCoreConfig' to svh adapter. 13 | Traverses 'I3CCoreConfig' and applies its member to jinja template, 14 | adjusting the types if necessary. 15 | """ 16 | 17 | _defines = {} # List of parameters to be defined in the defines.svh 18 | _just_level = 10 # left justification level for the parameter definitions 19 | 20 | def __init__(self, cfg: I3CGenericConfig): 21 | self._defines = I3CCoreConfig(cfg)._defines 22 | self._just_level = max([len(n) for n in self._defines]) 23 | 24 | def save_to_file(self, file: os.path = "i3c_defines.svh"): 25 | template_path = os.path.join(os.path.dirname(__file__), "templates/") 26 | env = Environment(loader=FileSystemLoader(template_path)) 27 | template = env.get_template("defines.txt") 28 | 29 | file_content = template.render( 30 | generator_tool_name="py2svh.py", 31 | cfg_guard="I3C_CONFIG", 32 | defines=self._defines, 33 | just_level=self._just_level, 34 | ) 35 | with open(file, mode="w", encoding="utf-8") as out: 36 | out.write(file_content) 37 | 38 | 39 | def cfg2svh(config: I3CGenericConfig, file: os.path = "i3c_defines.svh") -> None: 40 | DefinesSVH(config).save_to_file(file) 41 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_tlul/tl_agent.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // --------------------------------------------- 6 | // TileLink agent 7 | // --------------------------------------------- 8 | class tl_agent extends dv_base_agent#( 9 | .CFG_T (tl_agent_cfg), 10 | .DRIVER_T (tl_base_driver), 11 | .HOST_DRIVER_T (tl_host_driver), 12 | .DEVICE_DRIVER_T (tl_device_driver), 13 | .SEQUENCER_T (tl_sequencer), 14 | .MONITOR_T (tl_monitor), 15 | .COV_T (tl_agent_cov) 16 | ); 17 | 18 | `uvm_component_utils(tl_agent) 19 | 20 | `uvm_component_new 21 | 22 | function void build_phase(uvm_phase phase); 23 | super.build_phase(phase); 24 | // get tl_if handle 25 | if (!uvm_config_db#(virtual tl_if)::get(this, "", "vif", cfg.vif)) begin 26 | `uvm_fatal(`gfn, "failed to get tl_if handle from uvm_config_db") 27 | end 28 | cfg.vif.if_mode = cfg.if_mode; 29 | endfunction 30 | 31 | function void connect_phase(uvm_phase phase); 32 | super.connect_phase(phase); 33 | if (cfg.if_mode == dv_utils_pkg::Device) begin 34 | if (cfg.device_can_rsp_on_same_cycle) begin 35 | monitor.a_chan_same_cycle_rsp_port.connect(sequencer.a_chan_req_fifo.analysis_export); 36 | end else begin 37 | monitor.a_chan_port.connect(sequencer.a_chan_req_fifo.analysis_export); 38 | end 39 | end 40 | endfunction 41 | endclass : tl_agent 42 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_base/dv_base_agent_cfg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class dv_base_agent_cfg extends uvm_object; 6 | 7 | // agent cfg knobs 8 | bit is_active = 1'b1; // active driver/sequencer or passive monitor 9 | bit en_cov = 1'b1; // enable coverage 10 | if_mode_e if_mode; // interface mode - Host or Device 11 | 12 | // indicate to create and connet driver to sequencer or not 13 | // if this is a high-level agent, we may just call lower-level agent to send item in seq, then 14 | // driver isn't needed 15 | bit has_driver = 1'b1; 16 | // indicate if these fifo and ports exist or not 17 | bit has_req_fifo = 1'b0; 18 | bit has_rsp_fifo = 1'b0; 19 | 20 | // use for phase_ready_to_end to add additional delay after ok_to_end is set 21 | int ok_to_end_delay_ns = 1000; 22 | 23 | // Indicates that the interface is under reset. The derived monitor detects and maintains it. 24 | bit in_reset; 25 | 26 | bit en_monitor = 1'b1; 27 | 28 | `uvm_object_utils_begin(dv_base_agent_cfg) 29 | `uvm_field_int (is_active, UVM_DEFAULT) 30 | `uvm_field_int (en_cov, UVM_DEFAULT) 31 | `uvm_field_enum(if_mode_e, if_mode, UVM_DEFAULT) 32 | `uvm_field_int (has_req_fifo, UVM_DEFAULT) 33 | `uvm_field_int (has_rsp_fifo, UVM_DEFAULT) 34 | `uvm_object_utils_end 35 | 36 | `uvm_object_new 37 | 38 | endclass 39 | -------------------------------------------------------------------------------- /i3c_core_configs.yaml: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | # ===================================== 4 | # * SUPPORTED I3C CORE CONFIGURATIONS * 5 | # ===================================== 6 | 7 | ahb: 8 | CmdFifoDepth: 64 9 | RxFifoDepth: 64 10 | TxFifoDepth: 64 11 | RespFifoDepth: 64 12 | IbiFifoDepth: 64 13 | IbiFifoExtSize: False 14 | DatDepth: 128 15 | DctDepth: 128 16 | FrontendBusInterface: "AHB" 17 | FrontendBusAddrWidth: 18 18 | FrontendBusDataWidth: 64 19 | DisableInputFF: False 20 | ControllerSupport: False 21 | TargetSupport: True 22 | 23 | axi: 24 | CmdFifoDepth: 64 25 | RxFifoDepth: 64 26 | TxFifoDepth: 64 27 | RespFifoDepth: 64 28 | IbiFifoDepth: 64 29 | IbiFifoExtSize: False 30 | DatDepth: 128 31 | DctDepth: 128 32 | FrontendBusInterface: "AXI" 33 | FrontendBusAddrWidth: 12 34 | FrontendBusDataWidth: 32 35 | FrontendBusUserWidth: 32 36 | FrontendBusIdWidth: 8 37 | FrontendBusIdFiltering: True 38 | NumPrivIds: 4 39 | DisableInputFF: False 40 | DisableLoopback: True 41 | ControllerSupport: False 42 | TargetSupport: True 43 | 44 | axi_bypass: 45 | CmdFifoDepth: 64 46 | RxFifoDepth: 64 47 | TxFifoDepth: 64 48 | RespFifoDepth: 64 49 | IbiFifoDepth: 64 50 | IbiFifoExtSize: False 51 | DatDepth: 128 52 | DctDepth: 128 53 | FrontendBusInterface: "AXI" 54 | FrontendBusAddrWidth: 12 55 | FrontendBusDataWidth: 32 56 | FrontendBusUserWidth: 32 57 | FrontendBusIdWidth: 8 58 | FrontendBusIdFiltering: True 59 | NumPrivIds: 4 60 | DisableInputFF: False 61 | ControllerSupport: False 62 | TargetSupport: True 63 | -------------------------------------------------------------------------------- /verification/uvm_i3c/dv_i3c/i3c_agent.sv: -------------------------------------------------------------------------------- 1 | class i3c_agent extends uvm_agent; 2 | `uvm_component_utils(i3c_agent) 3 | 4 | i3c_agent_cfg cfg; 5 | i3c_driver driver; 6 | i3c_sequencer sequencer; 7 | i3c_monitor monitor; 8 | 9 | function new (string name="", uvm_component parent=null); 10 | super.new(name, parent); 11 | endfunction : new 12 | 13 | 14 | function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | // get CFG_T object from uvm_config_db 17 | if (!uvm_config_db#(i3c_agent_cfg)::get(this, "", "cfg", cfg)) begin 18 | `uvm_fatal(get_full_name(), $sformatf("failed to get %s from uvm_config_db", cfg.get_type_name())) 19 | end 20 | `uvm_info(get_full_name(), $sformatf("\n%0s", cfg.sprint()), UVM_HIGH) 21 | 22 | monitor = i3c_monitor::type_id::create("monitor", this); 23 | monitor.cfg = cfg; 24 | 25 | if (cfg.is_active) begin 26 | sequencer = i3c_sequencer::type_id::create("sequencer", this); 27 | sequencer.cfg = cfg; 28 | 29 | if (cfg.has_driver) begin 30 | driver = i3c_driver::type_id::create("driver", this); 31 | driver.cfg = cfg; 32 | end 33 | end 34 | if (!uvm_config_db#(virtual i3c_if)::get(this, "", "vif", cfg.vif)) begin 35 | `uvm_fatal(`gfn, "failed to get i3c_if handle from uvm_config_db") 36 | end 37 | endfunction 38 | 39 | function void connect_phase(uvm_phase phase); 40 | super.connect_phase(phase); 41 | if (cfg.is_active && cfg.has_driver) begin 42 | driver.seq_item_port.connect(sequencer.seq_item_export); 43 | end 44 | endfunction 45 | endclass 46 | 47 | -------------------------------------------------------------------------------- /verification/cocotb/top/lib_i3c_top/test_enter_exit_hdr_mode.py: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: Apache-2.0 2 | 3 | import logging 4 | 5 | from boot import boot_init 6 | from cocotbext_i3c.i3c_controller import I3cController 7 | from cocotbext_i3c.i3c_target import I3CTarget 8 | from interface import I3CTopTestInterface 9 | 10 | import cocotb 11 | from cocotb.triggers import ClockCycles 12 | 13 | 14 | @cocotb.test() 15 | async def test_enter_exit_hdr_mode(dut): 16 | ENTHDR0 = 0x20 17 | cocotb.log.setLevel(logging.DEBUG) 18 | 19 | i3c_controller = I3cController( 20 | sda_i=dut.bus_sda, 21 | sda_o=dut.sda_sim_ctrl_i, 22 | scl_i=dut.bus_scl, 23 | scl_o=dut.scl_sim_ctrl_i, 24 | debug_state_o=None, 25 | speed=12.5e6, 26 | ) 27 | 28 | i3c_target = I3CTarget( # noqa 29 | sda_i=dut.bus_sda, 30 | sda_o=dut.sda_sim_target_i, 31 | scl_i=dut.bus_scl, 32 | scl_o=dut.scl_sim_target_i, 33 | debug_state_o=None, 34 | speed=12.5e6, 35 | ) 36 | 37 | tb = I3CTopTestInterface(dut) 38 | await tb.setup() 39 | await ClockCycles(tb.clk, 50) 40 | await boot_init(tb) 41 | 42 | await i3c_controller.i3c_ccc_write(ENTHDR0, broadcast_data=[]) 43 | 44 | assert ( 45 | dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.u_i3c_target_fsm.state_d 46 | == 0xA0 47 | ) # IdleHDR 48 | 49 | await i3c_controller.send_hdr_exit() 50 | 51 | assert ( 52 | dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.u_i3c_target_fsm.state_d 53 | == 0 54 | ) # Idle 55 | -------------------------------------------------------------------------------- /verification/uvm_i2c/dv_i2c/seq_lib/i2c_target_may_nack_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // I2C Agent sequence which behaves as an I2C TARGET. 6 | // 7 | // - Receives seq_items from req_analysis_fifo which are sent onto the driver. 8 | // - If the item is requesting to drive an ACK, 50/50 to change this to a NACK instead. 9 | // 10 | class i2c_target_may_nack_seq extends i2c_base_seq; 11 | `uvm_object_utils(i2c_target_may_nack_seq) 12 | `uvm_object_new 13 | 14 | virtual task body(); 15 | case (cfg.if_mode) 16 | Device: send_device_mode_txn(); 17 | Host: `uvm_fatal(`gfn, "This sequence is for the agent in TARGET-Mode only!") 18 | default: `uvm_fatal(`gfn, "Invalid cfg.if_mode!") 19 | endcase 20 | endtask : body 21 | 22 | virtual task send_device_mode_txn(); 23 | bit [7:0] rdata; 24 | forever begin 25 | p_sequencer.req_analysis_fifo.get(req); 26 | // If it's a read type response, create randomized return data 27 | if (req.drv_type == RdData) begin 28 | `DV_CHECK_STD_RANDOMIZE_FATAL(rdata) 29 | req.rdata = rdata; 30 | end 31 | // Convert some of the 'DevAck' items from the monitor into NACKs 32 | if (req.drv_type == DevAck) begin 33 | if ($urandom_range(0, 1)) begin 34 | `uvm_info(`gfn, "Converting an ACK to a NACK!", UVM_LOW) 35 | req.drv_type = DevNack; 36 | end 37 | end 38 | start_item(req); 39 | finish_item(req); 40 | end 41 | endtask 42 | 43 | endclass : i2c_target_may_nack_seq 44 | -------------------------------------------------------------------------------- /verification/uvm_i2c/push_pull_base_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | class push_pull_base_seq #(parameter int HostDataWidth = 32, 6 | parameter int DeviceDataWidth = HostDataWidth) 7 | extends dv_base_seq #( 8 | .REQ (push_pull_item#(HostDataWidth, DeviceDataWidth)), 9 | .CFG_T (push_pull_agent_cfg#(HostDataWidth, DeviceDataWidth)), 10 | .SEQUENCER_T (push_pull_sequencer#(HostDataWidth, DeviceDataWidth)) 11 | ); 12 | `uvm_object_param_utils(push_pull_base_seq#(HostDataWidth, DeviceDataWidth)) 13 | 14 | `uvm_object_new 15 | 16 | // Randomizes the req or response. 17 | // 18 | // Regardless of agent or item type, we can apply the same set of limits. 19 | virtual function void randomize_item(push_pull_item #(HostDataWidth, DeviceDataWidth) item); 20 | `DV_CHECK_RANDOMIZE_WITH_FATAL(item, 21 | if (cfg.zero_delays) { 22 | host_delay == 0; 23 | device_delay == 0; 24 | req_lo_delay == 0; 25 | ack_lo_delay == 0; 26 | } else { 27 | host_delay inside {[cfg.host_delay_min : cfg.host_delay_max]}; 28 | device_delay inside {[cfg.device_delay_min : cfg.device_delay_max]}; 29 | req_lo_delay inside {[cfg.req_lo_delay_min : cfg.req_lo_delay_max]}; 30 | ack_lo_delay inside {[cfg.ack_lo_delay_min : cfg.ack_lo_delay_max]}; 31 | } 32 | ) 33 | endfunction 34 | 35 | virtual task body(); 36 | `uvm_fatal(`gtn, "Need to override this when you extend from this class!") 37 | endtask 38 | 39 | endclass 40 | -------------------------------------------------------------------------------- /verification/uvm_i2c/seq_lib/alert_receiver_alert_rsp_seq.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors (OpenTitan project). 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // this sequence responses to alert pins by sending the ack pins 6 | class alert_receiver_alert_rsp_seq extends alert_receiver_base_seq; 7 | 8 | `uvm_object_utils(alert_receiver_alert_rsp_seq) 9 | `uvm_object_new 10 | 11 | constraint alert_receiver_alert_rsp_seq_c { 12 | r_alert_ping_send == 0; 13 | r_alert_rsp == 1; 14 | } 15 | 16 | virtual task body(); 17 | if (cfg.start_default_rsp_seq) begin 18 | default_rsp_thread(); 19 | end else begin 20 | super.body(); 21 | end 22 | endtask 23 | 24 | // Sends alert rsps back to host. 25 | virtual task default_rsp_thread(); 26 | alert_esc_seq_item req_q[$]; 27 | fork 28 | forever begin : get_req 29 | p_sequencer.req_analysis_fifo.get(req); 30 | if (req.alert_esc_type == AlertEscSigTrans) req_q.push_back(req); 31 | end : get_req 32 | forever begin : send_rsp 33 | if (cfg.in_reset) begin 34 | req_q.delete(); 35 | wait (!cfg.in_reset); 36 | end 37 | wait (req_q.size()); 38 | rsp = req_q.pop_front(); 39 | start_item(rsp); 40 | `DV_CHECK_RANDOMIZE_WITH_FATAL(req, 41 | r_alert_ping_send == 0; 42 | r_alert_rsp == 1; 43 | int_err == 0; 44 | ) 45 | finish_item(rsp); 46 | get_response(rsp); 47 | end : send_rsp 48 | join 49 | endtask 50 | 51 | endclass : alert_receiver_alert_rsp_seq 52 | --------------------------------------------------------------------------------