├── .flake8 ├── .github ├── scripts │ ├── code_fixup.py │ └── parse_testlist.py └── workflows │ ├── build-spike.yml │ └── run-tests.yml ├── .gitignore ├── .metrics.json ├── .travis.yml ├── CONTRIBUTING.md ├── LICENSE.txt ├── MANIFEST.in ├── README.md ├── __init__.py ├── cov.py ├── docs ├── Makefile ├── build │ ├── doctrees │ │ ├── appendix.doctree │ │ ├── class_reference.doctree │ │ ├── cmd_line_reference.doctree │ │ ├── configuration.doctree │ │ ├── coverage_model.doctree │ │ ├── customize_extend_generator.doctree │ │ ├── end_to_end_simulation.doctree │ │ ├── environment.pickle │ │ ├── extension_support.doctree │ │ ├── generator_flow.doctree │ │ ├── getting_started.doctree │ │ ├── handshake.doctree │ │ ├── index.doctree │ │ └── overview.doctree │ └── singlehtml │ │ ├── .buildinfo │ │ ├── _images │ │ └── trace_csv.png │ │ ├── _static │ │ ├── ajax-loader.gif │ │ ├── basic.css │ │ ├── comment-bright.png │ │ ├── comment-close.png │ │ ├── comment.png │ │ ├── css │ │ │ ├── badge_only.css │ │ │ ├── fonts │ │ │ │ ├── Roboto-Slab-Bold.woff │ │ │ │ ├── Roboto-Slab-Bold.woff2 │ │ │ │ ├── Roboto-Slab-Regular.woff │ │ │ │ ├── Roboto-Slab-Regular.woff2 │ │ │ │ ├── fontawesome-webfont.eot │ │ │ │ ├── fontawesome-webfont.svg │ │ │ │ ├── fontawesome-webfont.ttf │ │ │ │ ├── fontawesome-webfont.woff │ │ │ │ ├── fontawesome-webfont.woff2 │ │ │ │ ├── lato-bold-italic.woff │ │ │ │ ├── lato-bold-italic.woff2 │ │ │ │ ├── lato-bold.woff │ │ │ │ ├── lato-bold.woff2 │ │ │ │ ├── lato-normal-italic.woff │ │ │ │ ├── lato-normal-italic.woff2 │ │ │ │ ├── lato-normal.woff │ │ │ │ └── lato-normal.woff2 │ │ │ └── theme.css │ │ ├── doctools.js │ │ ├── documentation_options.js │ │ ├── down-pressed.png │ │ ├── down.png │ │ ├── file.png │ │ ├── fonts │ │ │ ├── FontAwesome.otf │ │ │ ├── Inconsolata-Bold.ttf │ │ │ ├── Inconsolata-Regular.ttf │ │ │ ├── Inconsolata.ttf │ │ │ ├── Lato-Bold.ttf │ │ │ ├── Lato-Regular.ttf │ │ │ ├── Lato │ │ │ │ ├── lato-bold.eot │ │ │ │ ├── lato-bold.ttf │ │ │ │ ├── lato-bold.woff │ │ │ │ ├── lato-bold.woff2 │ │ │ │ ├── lato-bolditalic.eot │ │ │ │ ├── lato-bolditalic.ttf │ │ │ │ ├── lato-bolditalic.woff │ │ │ │ ├── lato-bolditalic.woff2 │ │ │ │ ├── lato-italic.eot │ │ │ │ ├── lato-italic.ttf │ │ │ │ ├── lato-italic.woff │ │ │ │ ├── lato-italic.woff2 │ │ │ │ ├── lato-regular.eot │ │ │ │ ├── lato-regular.ttf │ │ │ │ ├── lato-regular.woff │ │ │ │ └── lato-regular.woff2 │ │ │ ├── Roboto-Slab-Bold.woff │ │ │ ├── Roboto-Slab-Bold.woff2 │ │ │ ├── Roboto-Slab-Light.woff │ │ │ ├── Roboto-Slab-Light.woff2 │ │ │ ├── Roboto-Slab-Regular.woff │ │ │ ├── Roboto-Slab-Regular.woff2 │ │ │ ├── Roboto-Slab-Thin.woff │ │ │ ├── Roboto-Slab-Thin.woff2 │ │ │ ├── RobotoSlab-Bold.ttf │ │ │ ├── RobotoSlab-Regular.ttf │ │ │ ├── RobotoSlab │ │ │ │ ├── roboto-slab-v7-bold.eot │ │ │ │ ├── roboto-slab-v7-bold.ttf │ │ │ │ ├── roboto-slab-v7-bold.woff │ │ │ │ ├── roboto-slab-v7-bold.woff2 │ │ │ │ ├── roboto-slab-v7-regular.eot │ │ │ │ ├── roboto-slab-v7-regular.ttf │ │ │ │ ├── roboto-slab-v7-regular.woff │ │ │ │ └── roboto-slab-v7-regular.woff2 │ │ │ ├── fontawesome-webfont.eot │ │ │ ├── fontawesome-webfont.svg │ │ │ ├── fontawesome-webfont.ttf │ │ │ ├── fontawesome-webfont.woff │ │ │ ├── fontawesome-webfont.woff2 │ │ │ ├── lato-bold-italic.woff │ │ │ ├── lato-bold-italic.woff2 │ │ │ ├── lato-bold.woff │ │ │ ├── lato-bold.woff2 │ │ │ ├── lato-normal-italic.woff │ │ │ ├── lato-normal-italic.woff2 │ │ │ ├── lato-normal.woff │ │ │ └── lato-normal.woff2 │ │ ├── jquery-3.4.1.js │ │ ├── jquery.js │ │ ├── js │ │ │ ├── badge_only.js │ │ │ ├── html5shiv-printshiv.min.js │ │ │ ├── html5shiv.min.js │ │ │ ├── modernizr.min.js │ │ │ └── theme.js │ │ ├── language_data.js │ │ ├── minus.png │ │ ├── plus.png │ │ ├── pygments.css │ │ ├── searchtools.js │ │ ├── underscore-1.3.1.js │ │ ├── underscore.js │ │ ├── up-pressed.png │ │ ├── up.png │ │ └── websupport.js │ │ ├── index.html │ │ └── objects.inv ├── make.bat └── source │ ├── appendix.rst │ ├── class_reference.rst │ ├── cmd_line_reference.rst │ ├── conf.py │ ├── configuration.rst │ ├── coverage_model.rst │ ├── customize_extend_generator.rst │ ├── end_to_end_simulation.rst │ ├── extension_support.rst │ ├── generator_flow.rst │ ├── getting_started.rst │ ├── handshake.rst │ ├── index.rst │ ├── overview.rst │ └── trace_csv.png ├── euvm ├── README.md ├── build │ └── makefile └── riscv │ ├── gen │ ├── isa │ │ ├── custom │ │ │ ├── riscv_custom_instr.d │ │ │ └── riscv_custom_instr_enum.d │ │ ├── package.d │ │ ├── riscv_amo_instr.d │ │ ├── riscv_b_instr.d │ │ ├── riscv_compressed_instr.d │ │ ├── riscv_floating_point_instr.d │ │ ├── riscv_instr.d │ │ ├── riscv_instr_register.d │ │ ├── riscv_vector_instr.d │ │ ├── riscv_zba_instr.d │ │ ├── riscv_zbb_instr.d │ │ ├── riscv_zbc_instr.d │ │ ├── riscv_zbs_instr.d │ │ ├── rv128c_instr.d │ │ ├── rv32a_instr.d │ │ ├── rv32b_instr.d │ │ ├── rv32c_instr.d │ │ ├── rv32d_instr.d │ │ ├── rv32dc_instr.d │ │ ├── rv32f_instr.d │ │ ├── rv32fc_instr.d │ │ ├── rv32i_instr.d │ │ ├── rv32m_instr.d │ │ ├── rv32v_instr.d │ │ ├── rv32zba_instr.d │ │ ├── rv32zbb_instr.d │ │ ├── rv32zbc_instr.d │ │ ├── rv32zbs_instr.d │ │ ├── rv64a_instr.d │ │ ├── rv64b_instr.d │ │ ├── rv64c_instr.d │ │ ├── rv64d_instr.d │ │ ├── rv64f_instr.d │ │ ├── rv64i_instr.d │ │ ├── rv64m_instr.d │ │ ├── rv64zba_instr.d │ │ └── rv64zbb_instr.d │ ├── package.d │ ├── riscv_amo_instr_lib.d │ ├── riscv_asm_program_gen.d │ ├── riscv_callstack_gen.d │ ├── riscv_custom_instr_enum.d │ ├── riscv_data_page_gen.d │ ├── riscv_debug_rom_gen.d │ ├── riscv_defines.d │ ├── riscv_directed_instr_lib.d │ ├── riscv_illegal_instr.d │ ├── riscv_instr_gen_config.d │ ├── riscv_instr_pkg.d │ ├── riscv_instr_registry.d │ ├── riscv_instr_sequence.d │ ├── riscv_instr_stream.d │ ├── riscv_load_store_instr_lib.d │ ├── riscv_loop_instr.d │ ├── riscv_page_table.d │ ├── riscv_page_table_entry.d │ ├── riscv_page_table_exception_cfg.d │ ├── riscv_page_table_list.d │ ├── riscv_pmp_cfg.d │ ├── riscv_privil_reg.d │ ├── riscv_privileged_common_seq.d │ ├── riscv_pseudo_instr.d │ ├── riscv_reg.d │ ├── riscv_signature_pkg.d │ ├── riscv_vector_cfg.d │ └── target │ │ ├── ml │ │ └── riscv_core_setting.d │ │ ├── multi_harts │ │ └── riscv_core_setting.d │ │ ├── package.d │ │ ├── rv32i │ │ └── riscv_core_setting.d │ │ ├── rv32imafdc │ │ └── riscv_core_setting.d │ │ ├── rv32imc │ │ └── riscv_core_setting.d │ │ ├── rv32imc_sv32 │ │ └── riscv_core_setting.d │ │ ├── rv32imcb │ │ └── riscv_core_setting.d │ │ ├── rv64gc │ │ └── riscv_core_setting.d │ │ ├── rv64gcv │ │ └── riscv_core_setting.d │ │ ├── rv64imc │ │ └── riscv_core_setting.d │ │ └── rv64imcb │ │ └── riscv_core_setting.d │ └── test │ ├── riscv_instr_base_test.d │ ├── riscv_instr_gen.d │ ├── riscv_instr_test.d │ └── riscv_instr_test_lib.d ├── files.f ├── pygen ├── experimental │ ├── README.md │ ├── riscv_asm_program_gen.py │ ├── riscv_callstack_gen.py │ ├── riscv_data_page_gen.py │ ├── riscv_directed_instr_lib.py │ ├── riscv_instr_base.py │ ├── riscv_instr_sequence.py │ ├── riscv_instr_stream.py │ ├── riscv_load_store_instr_lib.py │ ├── riscv_rand_instr.py │ └── utils.py └── pygen_src │ ├── README.md │ ├── isa │ ├── riscv_amo_instr.py │ ├── riscv_b_instr.py │ ├── riscv_compressed_instr.py │ ├── riscv_cov_instr.py │ ├── riscv_floating_point_instr.py │ ├── riscv_instr.py │ ├── rv32a_instr.py │ ├── rv32b_instr.py │ ├── rv32c_instr.py │ ├── rv32d_instr.py │ ├── rv32dc_instr.py │ ├── rv32f_instr.py │ ├── rv32fc_instr.py │ ├── rv32i_instr.py │ ├── rv32m_instr.py │ ├── rv64a_instr.py │ ├── rv64c_instr.py │ ├── rv64d_instr.py │ ├── rv64f_instr.py │ ├── rv64i_instr.py │ └── rv64m_instr.py │ ├── riscv_amo_instr_lib.py │ ├── riscv_asm_program_gen.py │ ├── riscv_callstack_gen.py │ ├── riscv_data_page_gen.py │ ├── riscv_defines.py │ ├── riscv_directed_instr_lib.py │ ├── riscv_illegal_instr.py │ ├── riscv_instr_cover_group.py │ ├── riscv_instr_gen_config.py │ ├── riscv_instr_pkg.py │ ├── riscv_instr_sequence.py │ ├── riscv_instr_stream.py │ ├── riscv_load_store_instr_lib.py │ ├── riscv_loop_instr.py │ ├── riscv_privil_reg.py │ ├── riscv_privileged_common_seq.py │ ├── riscv_pseudo_instr.py │ ├── riscv_reg.py │ ├── riscv_signature_pkg.py │ ├── riscv_utils.py │ ├── target │ ├── multi_harts │ │ ├── riscvOVPsim.ic │ │ └── riscv_core_setting.py │ ├── rv32i │ │ ├── riscvOVPsim.ic │ │ └── riscv_core_setting.py │ ├── rv32imafdc │ │ ├── riscvOVPsim.ic │ │ └── riscv_core_setting.py │ ├── rv32imc │ │ ├── riscvOVPsim.ic │ │ └── riscv_core_setting.py │ ├── rv32imcb │ │ ├── riscvOVPsim.ic │ │ └── riscv_core_setting.py │ ├── rv64imafdc │ │ └── riscv_core_setting.py │ └── rv64imc │ │ └── riscv_core_setting.py │ └── test │ ├── riscv_instr_base_test.py │ ├── riscv_instr_cov_test.py │ └── riscv_rand_instr_test.py ├── qrun_option.f ├── questa_sim.tcl ├── requirements.txt ├── riviera_sim.tcl ├── run.py ├── sample └── sample_rv32imc_test.tar.gz ├── scripts ├── check-status ├── deprecated │ ├── instr_trace_compare.py │ ├── ovpsim_log_to_trace_csv.py │ ├── riscv_trace_csv.py │ └── spike_log_to_trace_csv.py ├── genMetricsList.py ├── gen_csr_test.py ├── instr_trace_compare.py ├── lib.py ├── link.ld ├── metrics-regress.py ├── ovpsim_log_to_trace_csv.py ├── renode_log_to_trace_csv.py ├── renode_wrapper.py ├── riscv_trace_csv.py ├── sail_log_to_trace_csv.py ├── spike_log_to_trace_csv.py └── whisper_log_trace_csv.py ├── setup.cfg ├── setup.py ├── src ├── dv_defines.svh ├── isa │ ├── custom │ │ ├── riscv_custom_instr.sv │ │ ├── riscv_custom_instr_enum.sv │ │ ├── rv32x_instr.sv │ │ └── rv64x_instr.sv │ ├── riscv_amo_instr.sv │ ├── riscv_b_instr.sv │ ├── riscv_compressed_instr.sv │ ├── riscv_csr_instr.sv │ ├── riscv_floating_point_instr.sv │ ├── riscv_instr.sv │ ├── riscv_instr_cov.svh │ ├── riscv_vector_instr.sv │ ├── riscv_zba_instr.sv │ ├── riscv_zbb_instr.sv │ ├── riscv_zbc_instr.sv │ ├── riscv_zbs_instr.sv │ ├── rv128c_instr.sv │ ├── rv32a_instr.sv │ ├── rv32b_instr.sv │ ├── rv32c_instr.sv │ ├── rv32d_instr.sv │ ├── rv32dc_instr.sv │ ├── rv32f_instr.sv │ ├── rv32fc_instr.sv │ ├── rv32i_instr.sv │ ├── rv32m_instr.sv │ ├── rv32v_instr.sv │ ├── rv32zba_instr.sv │ ├── rv32zbb_instr.sv │ ├── rv32zbc_instr.sv │ ├── rv32zbs_instr.sv │ ├── rv64a_instr.sv │ ├── rv64b_instr.sv │ ├── rv64c_instr.sv │ ├── rv64d_instr.sv │ ├── rv64f_instr.sv │ ├── rv64i_instr.sv │ ├── rv64m_instr.sv │ ├── rv64zba_instr.sv │ └── rv64zbb_instr.sv ├── riscv_amo_instr_lib.sv ├── riscv_asm_program_gen.sv ├── riscv_callstack_gen.sv ├── riscv_data_page_gen.sv ├── riscv_debug_rom_gen.sv ├── riscv_defines.svh ├── riscv_directed_instr_lib.sv ├── riscv_illegal_instr.sv ├── riscv_instr_cover_group.sv ├── riscv_instr_gen_config.sv ├── riscv_instr_pkg.sv ├── riscv_instr_sequence.sv ├── riscv_instr_stream.sv ├── riscv_load_store_instr_lib.sv ├── riscv_loop_instr.sv ├── riscv_page_table.sv ├── riscv_page_table_entry.sv ├── riscv_page_table_exception_cfg.sv ├── riscv_page_table_list.sv ├── riscv_pmp_cfg.sv ├── riscv_privil_reg.sv ├── riscv_privileged_common_seq.sv ├── riscv_pseudo_instr.sv ├── riscv_reg.sv ├── riscv_signature_pkg.sv └── riscv_vector_cfg.sv ├── target ├── ml │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── multi_harts │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv32i │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv32imafdc │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv32imc │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv32imc_sv32 │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv32imcb │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv64gc │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv64gcv │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv64imafdc │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── rv64imc │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml └── rv64imcb │ ├── riscvOVPsim.ic │ ├── riscv_core_setting.sv │ └── testlist.yaml ├── test ├── riscv_instr_base_test.sv ├── riscv_instr_cov_test.sv ├── riscv_instr_gen_tb_top.sv ├── riscv_instr_test.sv ├── riscv_instr_test_lib.sv └── riscv_instr_test_pkg.sv ├── user_extension ├── user_define.h ├── user_extension.svh └── user_init.s ├── vcs.compile.option.f ├── verilog_style ├── build-verible.sh ├── exclude_filelist.f └── run.sh └── yaml ├── base_testlist.yaml ├── cov_testlist.yaml ├── csr_template.yaml ├── iss.yaml ├── simulator.yaml └── whisper.json /.flake8: -------------------------------------------------------------------------------- 1 | [flake8] 2 | 3 | # Maximum line length 4 | max-line-length = 100 5 | 6 | ignore = 7 | # Ignore unexpected spaces around keyword / parameter equals 8 | E251, 9 | # Do not complain about line breaks after operators 10 | W504 11 | -------------------------------------------------------------------------------- /.github/scripts/parse_testlist.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from json import dumps 3 | from yaml import load, Loader 4 | from typing import Generator 5 | 6 | 7 | def parse_yaml(path: str) -> Generator[str, None, None]: 8 | with open(path, 'rb') as fd: 9 | tests = load(fd, Loader=Loader) 10 | for test in tests: 11 | if 'import' in test: 12 | import_path = test['import'].split('/', 1)[1] 13 | yield from parse_yaml(import_path) 14 | elif 'test' in test: 15 | yield test['test'] 16 | 17 | 18 | if __name__ == "__main__": 19 | if len(sys.argv) == 2: 20 | testlist = parse_yaml(f'target/{sys.argv[1]}/testlist.yaml') 21 | else: 22 | testlist = parse_yaml('yaml/base_testlist.yaml') 23 | testlist = list(testlist) 24 | # remove, will cause incomplete sim, need customized RTL 25 | testlist.remove("riscv_csr_test") 26 | print(dumps(testlist)) 27 | -------------------------------------------------------------------------------- /.github/workflows/build-spike.yml: -------------------------------------------------------------------------------- 1 | # https://github.com/chipsalliance/Cores-VeeR-EL2/blob/774510e43f5408ec2b818db8f865027bc9be97b8/.github/workflows/build-spike.yml 2 | 3 | name: Spike Build 4 | 5 | on: 6 | workflow_call: 7 | 8 | jobs: 9 | verilator: 10 | name: Build Spike 11 | runs-on: ubuntu-latest 12 | env: 13 | TOOL_NAME: spike 14 | TOOL_VERSION: d70ea67d 15 | DEBIAN_FRONTEND: "noninteractive" 16 | 17 | steps: 18 | - name: Setup Cache Metadata 19 | id: cache_metadata 20 | run: | 21 | cache_date=$(date +"%Y_%m_%d") 22 | cache_name=cache_${{ env.TOOL_NAME }}_${{ env.TOOL_VERSION }} 23 | echo "Cache date: "$cache_date 24 | echo "Cache name: "$cache_name 25 | echo "cache_date=$cache_date" >> "$GITHUB_ENV" 26 | echo "cache_name=$cache_name" >> "$GITHUB_ENV" 27 | 28 | - name: Setup cache 29 | uses: actions/cache@v3 30 | id: cache 31 | timeout-minutes: 60 32 | with: 33 | path: | 34 | /opt/spike 35 | /opt/spike/.cache 36 | key: ${{ env.cache_name }}_${{ env.cache_date }} 37 | restore-keys: ${{ env.cache_name }}_ 38 | 39 | - name: Install prerequisites 40 | if: ${{ steps.cache.outputs.cache-hit != 'true' }} 41 | run: | 42 | sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ 43 | git build-essential cmake ccache device-tree-compiler 44 | 45 | - name: Build Spike 46 | if: ${{ steps.cache.outputs.cache-hit != 'true' }} 47 | run: | 48 | export CCACHE_DIR=/opt/spike/.cache 49 | ccache --show-config | grep cache_dir 50 | git clone https://github.com/riscv-software-src/riscv-isa-sim spike 51 | export CC="ccache gcc" 52 | export CXX="ccache g++" 53 | pushd spike 54 | git checkout ${{ env.TOOL_VERSION }} 55 | mkdir build 56 | cd build 57 | ../configure --prefix=/opt/spike 58 | make -j`nproc` 59 | make install 60 | popd 61 | rm -rf /opt/spike/include # Remove include and lib to save space 62 | rm -rf /opt/spike/lib 63 | 64 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.ini 2 | *.bin 3 | *out_*/ 4 | work/ 5 | *.pyc 6 | /.cproject 7 | /.project 8 | /outdir/ 9 | ucli.key 10 | qrun.out/ 11 | qrun.log 12 | *.ucdb 13 | *.vstf 14 | riscv_dv.egg-info 15 | pygen/pygen_src/test/out/* 16 | !.gitkeep 17 | 18 | -------------------------------------------------------------------------------- /.metrics.json: -------------------------------------------------------------------------------- 1 | { 2 | "builds": { 3 | "list": [{ 4 | "name": "rv32imc", 5 | "image": "ibex-toolchain:v2", 6 | "memory" : "1", 7 | "cmd": "python3 run.py --test riscv_arithmetic_basic_test --simulator dsim --output out --verbose --co", 8 | "wavesCmd": "python3 run.py --test riscv_arithmetic_basic_test --simulator dsim --output out --verbose --co" 9 | }] 10 | }, 11 | "regressions": [{ 12 | "name": "riscv-dv_sanity", 13 | "description": "Basic test generated by Google riscv-dv instruction generator", 14 | "tests": { 15 | "builds": ["rv32imc"], 16 | "resultsDir" : "/mux-flow/build/repo/out", 17 | "memory" : "1", 18 | "list": [ 19 | { 20 | "name": "riscv_arithmetic_basic_test", 21 | "build": "rv32imc", 22 | "iterations": 2, 23 | "cmd": "cd /mux-flow/results; python3 /run.py --test riscv_arithmetic_basic_test --seed --simulator dsim --iss spike --so --out /out --verbose; /scripts/check-status $?; rm -fr /out/dsim", 24 | "wavesCmd": "python3 /run.py --test riscv_arithmetic_basic_test --seed --simulator dsim --iss spike --so --out /out --verbose; /scripts/check-status $?; rm -rf out/dsim", 25 | "logFile": "simulation.log", 26 | "metricsFile": "metrics.db", 27 | "isPass": "Test passed", 28 | "seed": "random" 29 | } 30 | ] 31 | } 32 | }, 33 | { 34 | "name" : "riscv-dv_regression", 35 | "description": "Tests generated by Google riscv-dv instruction generator", 36 | "tests": { 37 | "resultsDir": "/mux-flow/build/repo/out", 38 | "builds": ["rv32imc"], 39 | "memory": "1", 40 | "listCmd": "/scripts/genMetricsList.py", 41 | "listFile": "/regression_list.json" 42 | } 43 | } 44 | ] 45 | } 46 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | language: python 2 | dist: xenial 3 | matrix: 4 | include: 5 | - python: 3.6 6 | env: TOX_ENV=py36 7 | - python: 3.7 8 | env: TOX_ENV=py37 9 | install: 10 | # Install riscv-dv using pip to ensure dependencies are downloaded correctly. 11 | - pip install -r requirements.txt 12 | - pip install . 13 | script: 14 | - sphinx-build -E -W -b linkcheck docs/source build 15 | - pip uninstall -y riscv-dv 16 | - flake8 --show-source pygen/pygen_src/ --config=.flake8 17 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # How to Contribute 2 | 3 | We'd love to accept your patches and contributions to this project. There are 4 | just a few small guidelines you need to follow. 5 | 6 | ## Contributor License Agreement 7 | 8 | Contributions to this project must be accompanied by a Contributor License 9 | Agreement. You (or your employer) retain the copyright to your contribution; 10 | this simply gives us permission to use and redistribute your contributions as 11 | part of the project. Head over to to see 12 | your current agreements on file or to sign a new one. 13 | 14 | You generally only need to submit a CLA once, so if you've already submitted one 15 | (even if it was for a different project), you probably don't need to do it 16 | again. 17 | 18 | ## Code reviews 19 | 20 | All submissions, including submissions by project members, require review. We 21 | use GitHub pull requests for this purpose. Consult 22 | [GitHub Help](https://help.github.com/articles/about-pull-requests/) for more 23 | information on using pull requests. 24 | 25 | ## Community Guidelines 26 | 27 | This project follows 28 | [Google's Open Source Community Guidelines](https://opensource.google.com/conduct/). 29 | -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- 1 | include sample/* 2 | include scripts/* 3 | include src/* 4 | include target/* 5 | include test/* 6 | include user_extension/* 7 | include yaml/* 8 | include README.md 9 | include LICENSE.txt 10 | include HANDSHAKE.md 11 | include files.f 12 | include qrun_option.f 13 | include questa_sim.tcl 14 | include riviera_sim.tcl 15 | include run.py 16 | include requirements.txt 17 | include vcs.compile.option.f 18 | -------------------------------------------------------------------------------- /__init__.py: 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/riscv-dv/7e54b678ab7499040336255550cdbd99ae887431/docs/build/singlehtml/objects.inv -------------------------------------------------------------------------------- /docs/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | set SPHINXOPTS="-html_theme classic" 13 | 14 | if "%1" == "" goto help 15 | 16 | %SPHINXBUILD% >NUL 2>NUL 17 | if errorlevel 9009 ( 18 | echo. 19 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 20 | echo.installed, then set the SPHINXBUILD environment variable to point 21 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 22 | echo.may add the Sphinx directory to PATH. 23 | echo. 24 | echo.If you don't have Sphinx installed, grab it from 25 | echo.http://sphinx-doc.org/ 26 | exit /b 1 27 | ) 28 | 29 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 30 | goto end 31 | 32 | :help 33 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 34 | 35 | :end 36 | popd 37 | -------------------------------------------------------------------------------- /docs/source/appendix.rst: -------------------------------------------------------------------------------- 1 | Appendix 2 | ======== 3 | 4 | Trace CSV format 5 | ---------------- 6 | 7 | A standard CSV format is defined for the instruction execution trace. It's used for co-simulation result comparison and functional coverage collection. 8 | 9 | .. image:: trace_csv.png 10 | 11 | **The CSV format includes the following fields:** 12 | 13 | - pc : Program counter (instruction memory address) 14 | - instr: Instruction name 15 | - gpr: General purpose register updated by the instruction (rd, fd, vd etc.) 16 | 17 | - Format: : 18 | - GPR can be any integer/floating point/vector register 19 | - If more than one general purpose registers are updated, separate them with semicolon 20 | - csr: Privileged CSR updated by the instruction 21 | 22 | - The same format as the GPR field 23 | - binary: Instruction binary 24 | - instr_str: Instruction in assembly format 25 | - operand: Instruction operands 26 | - pad: Unused 27 | 28 | **Here's a sample of the CSV trace file:** 29 | 30 | .. code-block:: verilog 31 | 32 | pc,instr,gpr,csr,binary,mode,instr_str,operand,pad 33 | ffffffff8000000c,c.addi,ra:daab700e,,000000b9,3,"c.addi ra, 14","ra,14", 34 | ffffffff8000000e,lui,sp:ff8e6000,,ff8e6137,3,"lui sp, 0xff8e6","sp,0xff8e6", 35 | ffffffff80000012,addi,sp:ff8e6541,,54110113,3,"addi sp, sp, 1345","sp,sp,1345", 36 | ffffffff80000016,c.li,gp:00000000,,00004181,3,"c.li gp, 0","gp,0", 37 | ffffffff80000018,lui,tp:80000000,,80000237,3,"lui tp, 0x80000","tp,0x80000", 38 | ffffffff8000001c,lui,t0:f999d000,,f999d2b7,3,"lui t0, 0xf999d","t0,0xf999d", 39 | ffffffff80000020,addi,t0:f999cbf0,,bf028293,3,"addi t0, t0, -1040","t0,t0,-1040", 40 | ffffffff80000024,lui,t1:0416b000,,0416b337,3,"lui t1, 0x416b","t1,0x416b", 41 | ffffffff80000028,addi,t1:0416b6ee,,6ee30313,3,"addi t1, t1, 1774","t1,t1,1774", 42 | ffffffff8000002c,lui,t2:e6420000,,e64203b7,3,"lui t2, 0xe6420","t2,0xe6420", 43 | ... 44 | 45 | To integrate a new ISS or processor with the co-simualtion or coverage flow, user must implement a 46 | python script to convert the custom trace log format to this CSV format. You can find a sample 47 | script `here`_. 48 | 49 | .. _here: https://github.com/google/riscv-dv/blob/master/scripts/spike_log_to_trace_csv.py 50 | -------------------------------------------------------------------------------- /docs/source/class_reference.rst: -------------------------------------------------------------------------------- 1 | Class Reference 2 | =============== 3 | -------------------------------------------------------------------------------- /docs/source/cmd_line_reference.rst: -------------------------------------------------------------------------------- 1 | Command Line Reference 2 | ====================== 3 | -------------------------------------------------------------------------------- /docs/source/conf.py: -------------------------------------------------------------------------------- 1 | # Configuration file for the Sphinx documentation builder. 2 | # 3 | # This file only contains a selection of the most common options. For a full 4 | # list see the documentation: 5 | # https://www.sphinx-doc.org/en/master/usage/configuration.html 6 | 7 | # -- Path setup -------------------------------------------------------------- 8 | 9 | # If extensions (or modules to document with autodoc) are in another directory, 10 | # add these directories to sys.path here. If the directory is relative to the 11 | # documentation root, use os.path.abspath to make it absolute, like shown here. 12 | # 13 | # import os 14 | # import sys 15 | # sys.path.insert(0, os.path.abspath('.')) 16 | from pallets_sphinx_themes import ProjectLink 17 | import sphinx_rtd_theme 18 | 19 | # -- Project information ----------------------------------------------------- 20 | 21 | project = 'riscv-dv' 22 | copyright = '2020, Google, Inc.' 23 | author = 'Google, Inc.' 24 | 25 | 26 | # -- General configuration --------------------------------------------------- 27 | 28 | # Add any Sphinx extension module names here, as strings. They can be 29 | # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom 30 | # ones. 31 | master_doc = "index" 32 | extensions = [ 33 | "sphinx.ext.autodoc", 34 | "sphinx.ext.intersphinx", 35 | "pallets_sphinx_themes", 36 | "sphinxcontrib.log_cabinet", 37 | "sphinx_issues", 38 | "rst2pdf.pdfbuilder", 39 | 'sphinx_rtd_theme', 40 | ] 41 | 42 | # Add any paths that contain templates here, relative to this directory. 43 | templates_path = ['_templates'] 44 | 45 | # List of patterns, relative to source directory, that match files and 46 | # directories to ignore when looking for source files. 47 | # This pattern also affects html_static_path and html_extra_path. 48 | exclude_patterns = [] 49 | 50 | 51 | # -- Options for HTML output ------------------------------------------------- 52 | 53 | # The theme to use for HTML and HTML Help pages. See the documentation for 54 | # a list of builtin themes. 55 | # 56 | html_theme = "sphinx_rtd_theme" 57 | #html_theme_options = {"index_sidebar_logo": False} 58 | # 59 | #html_context = { 60 | # "project_links": [ 61 | # ProjectLink("Source Code", "https://github.com/google/riscv-dv.git"), 62 | # ProjectLink("Issue Tracker", "https://github.com/google/riscv-dv/issues"), 63 | # ] 64 | #} 65 | # 66 | #html_sidebars = { 67 | # "index": ["project.html", "localtoc.html", "searchbox.html"], 68 | # "**": ["localtoc.html", "relations.html", "searchbox.html"], 69 | #} 70 | 71 | # -- For PDF output --------------------------------------------------------- 72 | pdf_documents = [('index', u'riscv-dv', u'RISCV-DV', u'Google, Inc'),] 73 | 74 | -------------------------------------------------------------------------------- /docs/source/coverage_model.rst: -------------------------------------------------------------------------------- 1 | Coverage Model 2 | ============== 3 | 4 | Functional coverage (work in progress) 5 | -------------------------------------- 6 | 7 | This flow extracts functional coverage information from the 8 | instruction trace generated by ISS. It's independent of the instruction generation 9 | flow and does not require a tracer implementation in the RTL. You can use this 10 | flow as long as your program can be run with an ISS supported in this flow. The 11 | flow parses the instruction trace log and converts it to a CSV trace format. After 12 | that, a SV test is run to process the CSV trace files and sample functional 13 | coverage from there. 14 | 15 | The functional covergroup is defined in `riscv_instr_cover_group.sv`_. 16 | It includes below major categories: 17 | 18 | - Cover all operands for each instruction 19 | - Hazard conditions 20 | - Corner cases like overflow, underflow, divide by zero 21 | - Aligned/unaligned load/store 22 | - Positive/negative immediate value 23 | - Forward/backward branches, branch hit history 24 | - Hint instruction 25 | - Illegal instruction 26 | - All compressed and non-compressed opcode 27 | - Access to all implemened privileged CSR 28 | - Exception and interrupt 29 | 30 | .. _riscv_instr_cover_group.sv: https://github.com/google/riscv-dv/blob/master/src/riscv_instr_cover_group.sv 31 | 32 | The functional covergroup is still under active development. Please feel free to 33 | add anything you are interested or file a bug for any feature request. 34 | 35 | Before start, please check the you have modified `riscv_core_setting.sv`_ to reflect your processor capabilities. The covergroup is selectively instantiated based on this setting so that you don't need to deal with excluding unrelated coverpoints later. You also need to get the Spike ISS or riscvOVPsim ISS (riscv-ovpsim) setup before running this flow:: 36 | 37 | # Process spike simulation log and collect functional coverage 38 | cov --dir out/spike_sim 39 | 40 | # Get the command reference 41 | cov --help 42 | 43 | # Run the coverage flow with predefined targets 44 | cov --dir out/spike_sim --target rv32imc 45 | 46 | The coverage sampling from the CSV could be time consuming if you have a large 47 | number of log to process. You can split them to small batches and run with LSF 48 | in parallel:: 49 | 50 | # Split the run to process 5 CSV at a time, and run with LSF 51 | cov --dir out/spike_sim --lsf_cmd "bsub ....." -bz 5 52 | 53 | .. _riscv_core_setting.sv: https://github.com/google/riscv-dv/blob/master/target/rv32imc/riscv_core_setting.sv 54 | 55 | -------------------------------------------------------------------------------- /docs/source/customize_extend_generator.rst: -------------------------------------------------------------------------------- 1 | Customize and Extend Generator 2 | ============================== 3 | 4 | Add custom instructions 5 | ----------------------- 6 | 7 | 1. Add the new instruction enum to `riscv_custom_instr_enum.sv`_ 8 | 9 | .. code-block:: verilog 10 | 11 | CUSTOM_ADD, 12 | CUSTOM_SUB, 13 | ... 14 | 15 | 2. Add custom instruction definition to `rv32x_instr.sv`_/`rv64x_instr.sv`_ 16 | 17 | .. code-block:: verilog 18 | 19 | `DEFINE_CUSTOM_INSTR(CUSTOM_ADD, R_FORMAT, ARITHMETIC, RV32X) 20 | `DEFINE_CUSTOM_INSTR(CUSTOM_SUB, R_FORMAT, ARITHMETIC, RV32X) 21 | ... 22 | 23 | 3. Extend `riscv_custom_instr.sv`_ and implement key functions like get_instr_name, convert2asm 24 | 4. Add RV32X/RV64X to supported_isa in riscv_core_setting.sv 25 | 26 | .. _riscv_custom_instr_enum.sv: https://github.com/google/riscv-dv/blob/master/src/isa/custom/riscv_custom_instr_enum.sv 27 | .. _riscv_custom_instr.sv: https://github.com/google/riscv-dv/blob/master/src/isa/custom/riscv_custom_instr.sv 28 | .. _rv32x_instr.sv: https://github.com/google/riscv-dv/blob/master/src/isa/custom/rv32x_instr.sv 29 | .. _rv64x_instr.sv: https://github.com/google/riscv-dv/blob/master/src/isa/custom/rv64x_instr.sv 30 | -------------------------------------------------------------------------------- /docs/source/end_to_end_simulation.rst: -------------------------------------------------------------------------------- 1 | End to End Simulation Flow 2 | ========================== 3 | 4 | We have collaborated with lowRISC to apply this flow for `Ibex RISC-V core verification`_. 5 | You can use it as a reference to setup end-to-end co-simulation flow. 6 | This repo is still under active development, this is the recommended approach to 7 | customize the instruction generator while keeping the effort of merging 8 | upstream changes to a minimum. 9 | 10 | 1. Do not modify the upstream classes directly. When possible, extend from 11 | the upstream classses and implement your own functionalities. 12 | 13 | 2. Add your extensions under user_extension directory, and add the files to 14 | user_extension/user_extension.svh. If you prefer to put your extensions in a 15 | different directory, you can use "-ext " to override the 16 | user extension path. 17 | 18 | 3. Create a new target directory and customize the setting and testlist 19 | 20 | 4. Run the generator with ``--custom_target --isa --mabi `` 21 | 22 | 5. Use command line type override to use your extended classes. 23 | ``--sim_opts="+uvm_set_type_override=,"`` 24 | 25 | 6. If extending ``riscv_asm_program_gen`` class is desired, must use this command 26 | line override: 27 | ``--sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,,'uvm_test_top.asm_gen'"`` 29 | 30 | You can refer to `riscv-dv extension for Ibex`_ for a working example. 31 | 32 | We have plan to open-source the end-to-end environments of other advanced RISC-V 33 | processors. Stay tuned! 34 | 35 | .. _Ibex RISC-V core verification: https://github.com/lowRISC/ibex/blob/master/doc/03_reference/verification.rst 36 | .. _riscv-dv extension for Ibex: https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/Makefile#L110 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /docs/source/generator_flow.rst: -------------------------------------------------------------------------------- 1 | Generator Flow 2 | ============== 3 | -------------------------------------------------------------------------------- /docs/source/index.rst: -------------------------------------------------------------------------------- 1 | .. riscv-dv documentation master file, created by 2 | sphinx-quickstart on Sun Jan 5 08:04:09 2020. 3 | You can adapt this file completely to your liking, but it should at least 4 | contain the root `toctree` directive. 5 | 6 | Welcome to riscv-dv's documentation! 7 | ==================================== 8 | 9 | .. toctree:: 10 | :maxdepth: 2 11 | :caption: Contents: 12 | 13 | overview 14 | getting_started 15 | configuration 16 | extension_support 17 | end_to_end_simulation 18 | generator_flow 19 | coverage_model 20 | customize_extend_generator 21 | class_reference 22 | cmd_line_reference 23 | handshake 24 | appendix 25 | 26 | 27 | 28 | Indices and tables 29 | ================== 30 | 31 | * :ref:`genindex` 32 | * :ref:`modindex` 33 | * :ref:`search` 34 | -------------------------------------------------------------------------------- /docs/source/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | ======== 3 | 4 | RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V 5 | processor verification. It currently supports the following features: 6 | 7 | - Supported instruction set: RV32IMAFDC, RV64IMAFDC 8 | - Supported privileged mode: machine mode, supervisor mode, user mode 9 | - Page table randomization and exception 10 | - Privileged CSR setup randomization 11 | - Privileged CSR test suite 12 | - Trap/interrupt handling 13 | - Test suite to stress test MMU 14 | - Sub-program generation and random program calls 15 | - Illegal instruction and HINT instruction generation 16 | - Random forward/backward branch instructions 17 | - Supports mixing directed instructions with random instruction stream 18 | - Debug mode support, with fully randomized debug ROM 19 | - Instruction generation coverage model 20 | - Communication of information to any integrated SV testbench 21 | - Co-simulation with multiple ISS : spike, riscv-ovpsim 22 | 23 | A CSR test generation script written in Python is also provided, to generate a 24 | directed test suite that stresses all CSR instructions on all of the CSRs that 25 | the core implements. 26 | -------------------------------------------------------------------------------- /docs/source/trace_csv.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/riscv-dv/7e54b678ab7499040336255550cdbd99ae887431/docs/source/trace_csv.png -------------------------------------------------------------------------------- /euvm/README.md: -------------------------------------------------------------------------------- 1 | ## About eUVM 2 | 3 | eUVM is an opensource implementation of IEEE UVM-1800.2-2020 standard in the D Programming Language. 4 | 5 | ## About the RISCV-DV eUVM port 6 | 7 | The RISCV-DV eUVM port is a line-by-line translation of the RISCV-DV SystemVerilog implementation. Except for functional coverage (a work in progress), all other RISCV-DV features have been implemented in eUVM port. 8 | 9 | ## Downloading and Installing eUVM 10 | 11 | If you want to build/use the eUVM port, you need an eUVM installation. Please follow the instructions on https://github.com/coverify/euvm/releases to install and setup eUVM. 12 | 13 | ## Building eUVM port of RISCV-DV 14 | 15 | A makefile to build and run the eUVM port is available in the euvm/build folder. To build the code, use the following commands (assuming bash shell): 16 | 17 | ```bash 18 | cd euvm/build 19 | make -j $(nproc) 20 | ``` 21 | 22 | Makefile builds RISCV-DV for RV64IMC architecture by default. If you want to build for an alternate architecture, you need to pass that to make command as TARGET parameter: 23 | 24 | ```bash 25 | cd euvm/build 26 | make clean 27 | make -j $(nproc) TARGET=RV64IMCB 28 | ``` 29 | 30 | Remember to make clean before switching to a new target. 31 | 32 | ## Generating RISCV-DV tests 33 | 34 | ```bash 35 | cd euvm/build 36 | make run 37 | ``` 38 | 39 | You can change the number of instructions to be generated by passsing INSTRCOUNT parameter to the make command: 40 | 41 | ```bash 42 | make run INSTRCOUNT=1000000 43 | ``` 44 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/custom/riscv_custom_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | // Custom instruction class 19 | 20 | module riscv.gen.isa.custom.riscv_custom_instr; 21 | 22 | import riscv.gen.riscv_instr_pkg: riscv_instr_group_t, 23 | riscv_instr_name_t, MAX_INSTR_STR_LEN, riscv_fpr_t, 24 | riscv_instr_format_t, riscv_instr_category_t, 25 | format_string, f_rounding_mode_t; 26 | import riscv.gen.isa.riscv_instr: riscv_instr; 27 | import std.string: toUpper, toLower; 28 | import std.format: format; 29 | import std.algorithm: canFind; 30 | 31 | import esdl.rand: rand; 32 | import esdl.data.bvec: ubvec; 33 | import uvm; 34 | 35 | class riscv_custom_instr: riscv_instr 36 | { 37 | // TODO: Add custom operands here, example: 38 | // rand riscv_reg_t rs3; 39 | 40 | mixin uvm_object_utils; 41 | this(string name = "") { 42 | super(name); 43 | } 44 | 45 | override string get_instr_name() { 46 | import std.conv: to; 47 | return instr_name.to!string(); 48 | // TODO: Add custom instruction name encoding here 49 | } 50 | 51 | // Convert the instruction to assembly code 52 | override string convert2asm(string prefix = "") { 53 | string asm_str; 54 | asm_str = format_string("nop", MAX_INSTR_STR_LEN); 55 | /* TODO: Convert custom instruction to assembly format. Example: 56 | asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); 57 | case (instr_name) 58 | CUSTOM_1: asm_str = $sformatf("%0s %0s, (%0s)", asm_str, rd.name(), rs1.name()); 59 | CUSTOM_2: asm_str = $sformatf("%0s %0s", asm_str, r3.name()); 60 | endcase 61 | */ 62 | comment = get_instr_name() ~ " " ~ comment; 63 | if (comment != "") { 64 | asm_str ~= " #" ~ comment; 65 | } 66 | return asm_str.toLower(); 67 | } 68 | } 69 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/custom/riscv_custom_instr_enum.d: -------------------------------------------------------------------------------- 1 | module riscv.gen.isa.custom.riscv_custom_instr_enum; 2 | 3 | //TODO custom instruction added 4 | // CUSTOM_i, 5 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/package.d: -------------------------------------------------------------------------------- 1 | module riscv.gen.isa; 2 | 3 | public import riscv.gen.isa.riscv_amo_instr; 4 | public import riscv.gen.isa.riscv_b_instr; 5 | public import riscv.gen.isa.riscv_zba_instr; 6 | public import riscv.gen.isa.riscv_zbb_instr; 7 | public import riscv.gen.isa.riscv_zbc_instr; 8 | public import riscv.gen.isa.riscv_zbs_instr; 9 | public import riscv.gen.isa.riscv_compressed_instr; 10 | public import riscv.gen.isa.riscv_floating_point_instr; 11 | public import riscv.gen.isa.riscv_instr; 12 | public import riscv.gen.isa.riscv_vector_instr; 13 | public import riscv.gen.isa.riscv_instr_register; 14 | 15 | public import riscv.gen.isa.rv128c_instr; 16 | public import riscv.gen.isa.rv32a_instr; 17 | public import riscv.gen.isa.rv32b_instr; 18 | public import riscv.gen.isa.rv32c_instr; 19 | public import riscv.gen.isa.rv32dc_instr; 20 | public import riscv.gen.isa.rv32d_instr; 21 | public import riscv.gen.isa.rv32fc_instr; 22 | public import riscv.gen.isa.rv32f_instr; 23 | public import riscv.gen.isa.rv32i_instr; 24 | public import riscv.gen.isa.rv32m_instr; 25 | public import riscv.gen.isa.rv32v_instr; 26 | public import riscv.gen.isa.rv64a_instr; 27 | public import riscv.gen.isa.rv64b_instr; 28 | public import riscv.gen.isa.rv64c_instr; 29 | public import riscv.gen.isa.rv64d_instr; 30 | public import riscv.gen.isa.rv64f_instr; 31 | public import riscv.gen.isa.rv64i_instr; 32 | public import riscv.gen.isa.rv64m_instr; 33 | public import riscv.gen.isa.rv64zba_instr; 34 | public import riscv.gen.isa.rv64zbb_instr; 35 | public import riscv.gen.isa.rv32zba_instr; 36 | public import riscv.gen.isa.rv32zbb_instr; 37 | public import riscv.gen.isa.rv32zbc_instr; 38 | public import riscv.gen.isa.rv32zbs_instr; 39 | 40 | public import riscv.gen.isa.custom.riscv_custom_instr; 41 | public import riscv.gen.isa.custom.riscv_custom_instr_enum; 42 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv128c_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv128c_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | mixin (riscv_c_instr_mixin(C_SRLI64, CB_FORMAT, SHIFT, RV128C, NZUIMM)); 26 | mixin (riscv_c_instr_mixin(C_SRAI64, CB_FORMAT, SHIFT, RV128C, NZUIMM)); 27 | mixin (riscv_c_instr_mixin(C_SLLI64, CI_FORMAT, SHIFT, RV128C, NZUIMM)); 28 | mixin (riscv_c_instr_mixin(C_LQ, CL_FORMAT, LOAD, RV32DC, UIMM)); 29 | mixin (riscv_c_instr_mixin(C_SQ, CS_FORMAT, STORE, RV32DC, UIMM)); 30 | mixin (riscv_c_instr_mixin(C_LQSP, CI_FORMAT, LOAD, RV32DC, UIMM)); 31 | mixin (riscv_c_instr_mixin(C_SQSP, CSS_FORMAT, STORE, RV32DC, UIMM)); 32 | } 33 | else { 34 | class riscv_C_SRLI64_instr: riscv_compressed_instr 35 | { mixin RISCV_INSTR_MIXIN!(C_SRLI64, CB_FORMAT, SHIFT, RV128C, NZUIMM); } 36 | class riscv_C_SRAI64_instr: riscv_compressed_instr 37 | { mixin RISCV_INSTR_MIXIN!(C_SRAI64, CB_FORMAT, SHIFT, RV128C, NZUIMM); } 38 | class riscv_C_SLLI64_instr: riscv_compressed_instr 39 | { mixin RISCV_INSTR_MIXIN!(C_SLLI64, CI_FORMAT, SHIFT, RV128C, NZUIMM); } 40 | class riscv_C_LQ_instr: riscv_compressed_instr 41 | { mixin RISCV_INSTR_MIXIN!(C_LQ, CL_FORMAT, LOAD, RV32DC, UIMM); } 42 | class riscv_C_SQ_instr: riscv_compressed_instr 43 | { mixin RISCV_INSTR_MIXIN!(C_SQ, CS_FORMAT, STORE, RV32DC, UIMM); } 44 | class riscv_C_LQSP_instr: riscv_compressed_instr 45 | { mixin RISCV_INSTR_MIXIN!(C_LQSP, CI_FORMAT, LOAD, RV32DC, UIMM); } 46 | class riscv_C_SQSP_instr: riscv_compressed_instr 47 | { mixin RISCV_INSTR_MIXIN!(C_SQSP, CSS_FORMAT, STORE, RV32DC, UIMM); } 48 | } 49 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv32dc_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv32dc_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | mixin (riscv_fc_instr_mixin(C_FLD, CL_FORMAT, LOAD, RV32DC, UIMM)); 26 | mixin (riscv_fc_instr_mixin(C_FSD, CS_FORMAT, STORE, RV32DC, UIMM)); 27 | mixin (riscv_fc_instr_mixin(C_FLDSP, CI_FORMAT, LOAD, RV32DC, UIMM)); 28 | mixin (riscv_fc_instr_mixin(C_FSDSP, CSS_FORMAT, STORE, RV32DC, UIMM)); 29 | } 30 | else { 31 | class riscv_C_FLD_INSTR: riscv_compressed_instr 32 | { mixin RISCV_INSTR_MIXIN!(C_FLD, CL_FORMAT, LOAD, RV32DC, UIMM); } 33 | class riscv_C_FSD_INSTR: riscv_compressed_instr 34 | { mixin RISCV_INSTR_MIXIN!(C_FSD, CS_FORMAT, STORE, RV32DC, UIMM); } 35 | class riscv_C_FLDSP_INSTR: riscv_compressed_instr 36 | { mixin RISCV_INSTR_MIXIN!(C_FLDSP, CI_FORMAT, LOAD, RV32DC, UIMM); } 37 | class riscv_C_FSDSP_INSTR: riscv_compressed_instr 38 | { mixin RISCV_INSTR_MIXIN!(C_FSDSP, CSS_FORMAT, STORE, RV32DC, UIMM); } 39 | } 40 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv32fc_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv32fc_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | 25 | version (RISCV_INSTR_STRING_MIXIN) { 26 | mixin (riscv_fc_instr_mixin(C_FLW, CL_FORMAT, LOAD, RV32FC, UIMM)); 27 | mixin (riscv_fc_instr_mixin(C_FSW, CS_FORMAT, STORE, RV32FC, UIMM)); 28 | mixin (riscv_fc_instr_mixin(C_FLWSP, CI_FORMAT, LOAD, RV32FC, UIMM)); 29 | mixin (riscv_fc_instr_mixin(C_FSWSP, CSS_FORMAT, STORE, RV32FC, UIMM)); 30 | } 31 | else { 32 | class riscv_C_FLW_instr: riscv_compressed_instr 33 | { mixin RISCV_INSTR_MIXIN!(C_FLW, CL_FORMAT, LOAD, RV32FC, UIMM); } 34 | class riscv_C_FSW_instr: riscv_compressed_instr 35 | { mixin RISCV_INSTR_MIXIN!(C_FSW, CS_FORMAT, STORE, RV32FC, UIMM); } 36 | class riscv_C_FLWSP_instr: riscv_compressed_instr 37 | { mixin RISCV_INSTR_MIXIN!(C_FLWSP, CI_FORMAT, LOAD, RV32FC, UIMM); } 38 | class riscv_C_FSWSP_instr: riscv_compressed_instr 39 | { mixin RISCV_INSTR_MIXIN!(C_FSWSP, CSS_FORMAT, STORE, RV32FC, UIMM); } 40 | } 41 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv32m_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | module riscv.gen.isa.rv32m_instr; 18 | 19 | import riscv.gen.riscv_defines; 20 | 21 | import uvm; 22 | 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | //////////// RV32M instructions ////////////// 26 | mixin (riscv_instr_mixin(MUL, R_FORMAT, ARITHMETIC, RV32M)); 27 | mixin (riscv_instr_mixin(MULH, R_FORMAT, ARITHMETIC, RV32M)); 28 | mixin (riscv_instr_mixin(MULHSU, R_FORMAT, ARITHMETIC, RV32M)); 29 | mixin (riscv_instr_mixin(MULHU, R_FORMAT, ARITHMETIC, RV32M)); 30 | mixin (riscv_instr_mixin(DIV, R_FORMAT, ARITHMETIC, RV32M)); 31 | mixin (riscv_instr_mixin(DIVU, R_FORMAT, ARITHMETIC, RV32M)); 32 | mixin (riscv_instr_mixin(REM, R_FORMAT, ARITHMETIC, RV32M)); 33 | mixin (riscv_instr_mixin(REMU, R_FORMAT, ARITHMETIC, RV32M)); 34 | } 35 | else { 36 | //////////// RV32M instructions ////////////// 37 | class riscv_MUL_instr: riscv_instr 38 | { mixin RISCV_INSTR_MIXIN!(MUL, R_FORMAT, ARITHMETIC, RV32M); } 39 | class riscv_MULH_instr: riscv_instr 40 | { mixin RISCV_INSTR_MIXIN!(MULH, R_FORMAT, ARITHMETIC, RV32M); } 41 | class riscv_MULHSU_instr: riscv_instr 42 | { mixin RISCV_INSTR_MIXIN!(MULHSU, R_FORMAT, ARITHMETIC, RV32M); } 43 | class riscv_MULHU_instr: riscv_instr 44 | { mixin RISCV_INSTR_MIXIN!(MULHU, R_FORMAT, ARITHMETIC, RV32M); } 45 | class riscv_DIV_instr: riscv_instr 46 | { mixin RISCV_INSTR_MIXIN!(DIV, R_FORMAT, ARITHMETIC, RV32M); } 47 | class riscv_DIVU_instr: riscv_instr 48 | { mixin RISCV_INSTR_MIXIN!(DIVU, R_FORMAT, ARITHMETIC, RV32M); } 49 | class riscv_REM_instr: riscv_instr 50 | { mixin RISCV_INSTR_MIXIN!(REM, R_FORMAT, ARITHMETIC, RV32M); } 51 | class riscv_REMU_instr: riscv_instr 52 | { mixin RISCV_INSTR_MIXIN!(REMU, R_FORMAT, ARITHMETIC, RV32M); } 53 | } 54 | 55 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv32zba_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * Copyright 2022 Coverify Systems Technology 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | module riscv.gen.isa.rv32zba_instr; 20 | 21 | import riscv.gen.riscv_defines; 22 | 23 | import uvm; 24 | 25 | version (RISCV_INSTR_STRING_MIXIN) { 26 | mixin (riscv_zba_instr_mixin(SH1ADD, R_FORMAT, ARITHMETIC, RV32ZBA)); 27 | mixin (riscv_zba_instr_mixin(SH2ADD, R_FORMAT, ARITHMETIC, RV32ZBA)); 28 | mixin (riscv_zba_instr_mixin(SH3ADD, R_FORMAT, ARITHMETIC, RV32ZBA)); 29 | } 30 | else { 31 | class riscv_SH1ADD_instr: riscv_zba_instr 32 | { mixin RISCV_INSTR_MIXIN!(SH1ADD, R_FORMAT, ARITHMETIC, RV32ZBA); } 33 | class riscv_SH2ADD_instr: riscv_zba_instr 34 | { mixin RISCV_INSTR_MIXIN!(SH2ADD, R_FORMAT, ARITHMETIC, RV32ZBA); } 35 | class riscv_SH3ADD_instr: riscv_zba_instr 36 | { mixin RISCV_INSTR_MIXIN!(SH3ADD, R_FORMAT, ARITHMETIC, RV32ZBA); } 37 | } 38 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv32zbc_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * Copyright 2022 Coverify Systems Technology 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | module riscv.gen.isa.rv32zbc_instr; 20 | 21 | import riscv.gen.riscv_defines; 22 | 23 | import uvm; 24 | 25 | version (RISCV_INSTR_STRING_MIXIN) { 26 | mixin (riscv_zbc_instr_mixin(CLMUL, R_FORMAT, ARITHMETIC, RV32ZBC)); 27 | mixin (riscv_zbc_instr_mixin(CLMULH, R_FORMAT, ARITHMETIC, RV32ZBC)); 28 | mixin (riscv_zbc_instr_mixin(CLMULR, R_FORMAT, ARITHMETIC, RV32ZBC)); 29 | } 30 | else { 31 | class riscv_CLMUL_instr: riscv_zbc_instr 32 | { mixin RISCV_INSTR_MIXIN!(CLMUL, R_FORMAT, ARITHMETIC, RV32ZBC); } 33 | class riscv_CLMULH_instr: riscv_zbc_instr 34 | { mixin RISCV_INSTR_MIXIN!(CLMULH, R_FORMAT, ARITHMETIC, RV32ZBC); } 35 | class riscv_CLMULR_instr: riscv_zbc_instr 36 | { mixin RISCV_INSTR_MIXIN!(CLMULR, R_FORMAT, ARITHMETIC, RV32ZBC); } 37 | } 38 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv32zbs_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * Copyright 2022 Coverify Systems Technology 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | module riscv.gen.isa.rv32zbs_instr; 20 | 21 | import riscv.gen.riscv_defines; 22 | 23 | import uvm; 24 | 25 | version (RISCV_INSTR_STRING_MIXIN) { 26 | mixin (riscv_zbs_instr_mixin(BCLR, R_FORMAT, SHIFT, RV32ZBS)); 27 | mixin (riscv_zbs_instr_mixin(BCLRI, I_FORMAT, SHIFT, RV32ZBS, UIMM)); 28 | mixin (riscv_zbs_instr_mixin(BEXT, R_FORMAT, SHIFT, RV32ZBS)); 29 | mixin (riscv_zbs_instr_mixin(BEXTI, I_FORMAT, SHIFT, RV32ZBS, UIMM)); 30 | mixin (riscv_zbs_instr_mixin(BINV, R_FORMAT, SHIFT, RV32ZBS)); 31 | mixin (riscv_zbs_instr_mixin(BINVI, I_FORMAT, SHIFT, RV32ZBS, UIMM)); 32 | mixin (riscv_zbs_instr_mixin(BSET, R_FORMAT, SHIFT, RV32ZBS)); 33 | mixin (riscv_zbs_instr_mixin(BSETI, I_FORMAT, SHIFT, RV32ZBS, UIMM)); 34 | } 35 | else { 36 | class riscv_BCLR_instr: riscv_zbs_instr 37 | { mixin RISCV_INSTR_MIXIN!(BCLR, R_FORMAT, SHIFT, RV32ZBS); } 38 | class riscv_BCLRI_instr: riscv_zbs_instr 39 | { mixin RISCV_INSTR_MIXIN!(BCLRI, I_FORMAT, SHIFT, RV32ZBS, UIMM); } 40 | class riscv_BEXT_instr: riscv_zbs_instr 41 | { mixin RISCV_INSTR_MIXIN!(BEXT, R_FORMAT, SHIFT, RV32ZBS); } 42 | class riscv_BEXTI_instr: riscv_zbs_instr 43 | { mixin RISCV_INSTR_MIXIN!(BEXTI, I_FORMAT, SHIFT, RV32ZBS, UIMM); } 44 | class riscv_BINV_instr: riscv_zbs_instr 45 | { mixin RISCV_INSTR_MIXIN!(BINV, R_FORMAT, SHIFT, RV32ZBS); } 46 | class riscv_BINVI_instr: riscv_zbs_instr 47 | { mixin RISCV_INSTR_MIXIN!(BINVI, I_FORMAT, SHIFT, RV32ZBS, UIMM); } 48 | class riscv_BSET_instr: riscv_zbs_instr 49 | { mixin RISCV_INSTR_MIXIN!(BSET, R_FORMAT, SHIFT, RV32ZBS); } 50 | class riscv_BSETI_instr: riscv_zbs_instr 51 | { mixin RISCV_INSTR_MIXIN!(BSETI, I_FORMAT, SHIFT, RV32ZBS, UIMM); } 52 | } 53 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv64c_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv64c_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | mixin (riscv_c_instr_mixin(C_ADDIW, CI_FORMAT, ARITHMETIC, RV64C)); 26 | mixin (riscv_c_instr_mixin(C_SUBW, CA_FORMAT, ARITHMETIC, RV64C)); 27 | mixin (riscv_c_instr_mixin(C_ADDW, CA_FORMAT, ARITHMETIC, RV64C)); 28 | mixin (riscv_c_instr_mixin(C_LD, CL_FORMAT, LOAD, RV64C, UIMM)); 29 | mixin (riscv_c_instr_mixin(C_SD, CS_FORMAT, STORE, RV64C, UIMM)); 30 | mixin (riscv_c_instr_mixin(C_LDSP, CI_FORMAT, LOAD, RV64C, UIMM)); 31 | mixin (riscv_c_instr_mixin(C_SDSP, CSS_FORMAT, STORE, RV64C, UIMM)); 32 | } 33 | else { 34 | class riscv_C_ADDIW_instr: riscv_compressed_instr 35 | { mixin RISCV_INSTR_MIXIN!(C_ADDIW, CI_FORMAT, ARITHMETIC, RV64C); } 36 | class riscv_C_SUBW_instr: riscv_compressed_instr 37 | { mixin RISCV_INSTR_MIXIN!(C_SUBW, CA_FORMAT, ARITHMETIC, RV64C); } 38 | class riscv_C_ADDW_instr: riscv_compressed_instr 39 | { mixin RISCV_INSTR_MIXIN!(C_ADDW, CA_FORMAT, ARITHMETIC, RV64C); } 40 | class riscv_C_LD_instr: riscv_compressed_instr 41 | { mixin RISCV_INSTR_MIXIN!(C_LD, CL_FORMAT, LOAD, RV64C, UIMM); } 42 | class riscv_C_SD_instr: riscv_compressed_instr 43 | { mixin RISCV_INSTR_MIXIN!(C_SD, CS_FORMAT, STORE, RV64C, UIMM); } 44 | class riscv_C_LDSP_instr: riscv_compressed_instr 45 | { mixin RISCV_INSTR_MIXIN!(C_LDSP, CI_FORMAT, LOAD, RV64C, UIMM); } 46 | class riscv_C_SDSP_instr: riscv_compressed_instr 47 | { mixin RISCV_INSTR_MIXIN!(C_SDSP, CSS_FORMAT, STORE, RV64C, UIMM); } 48 | } 49 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv64d_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv64d_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | mixin (riscv_fp_instr_mixin(FMV_X_D, I_FORMAT, ARITHMETIC, RV64D)); 26 | mixin (riscv_fp_instr_mixin(FMV_D_X, I_FORMAT, ARITHMETIC, RV64D)); 27 | mixin (riscv_fp_instr_mixin(FCVT_L_D, I_FORMAT, ARITHMETIC, RV64D)); 28 | mixin (riscv_fp_instr_mixin(FCVT_LU_D, I_FORMAT, ARITHMETIC, RV64D)); 29 | mixin (riscv_fp_instr_mixin(FCVT_D_L, I_FORMAT, ARITHMETIC, RV64D)); 30 | mixin (riscv_fp_instr_mixin(FCVT_D_LU, I_FORMAT, ARITHMETIC, RV64D)); 31 | } 32 | else { 33 | class riscv_FMV_X_D_instr: riscv_floating_point_instr 34 | { mixin RISCV_INSTR_MIXIN!(FMV_X_D, I_FORMAT, ARITHMETIC, RV64D); } 35 | class riscv_FMV_D_X_instr: riscv_floating_point_instr 36 | { mixin RISCV_INSTR_MIXIN!(FMV_D_X, I_FORMAT, ARITHMETIC, RV64D); } 37 | class riscv_FCVT_L_D_instr: riscv_floating_point_instr 38 | { mixin RISCV_INSTR_MIXIN!(FCVT_L_D, I_FORMAT, ARITHMETIC, RV64D); } 39 | class riscv_FCVT_LU_D_instr: riscv_floating_point_instr 40 | { mixin RISCV_INSTR_MIXIN!(FCVT_LU_D, I_FORMAT, ARITHMETIC, RV64D); } 41 | class riscv_FCVT_D_L_instr: riscv_floating_point_instr 42 | { mixin RISCV_INSTR_MIXIN!(FCVT_D_L, I_FORMAT, ARITHMETIC, RV64D); } 43 | class riscv_FCVT_D_LU_instr: riscv_floating_point_instr 44 | { mixin RISCV_INSTR_MIXIN!(FCVT_D_LU, I_FORMAT, ARITHMETIC, RV64D); } 45 | } 46 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv64f_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv64f_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | mixin (riscv_fp_instr_mixin(FCVT_L_S, I_FORMAT, ARITHMETIC, RV64F)); 26 | mixin (riscv_fp_instr_mixin(FCVT_LU_S, I_FORMAT, ARITHMETIC, RV64F)); 27 | mixin (riscv_fp_instr_mixin(FCVT_S_L, I_FORMAT, ARITHMETIC, RV64F)); 28 | mixin (riscv_fp_instr_mixin(FCVT_S_LU, I_FORMAT, ARITHMETIC, RV64F)); 29 | } 30 | else { 31 | class riscv_FCVT_L_S_instr: riscv_floating_point_instr 32 | { mixin RISCV_INSTR_MIXIN!(FCVT_L_S, I_FORMAT, ARITHMETIC, RV64F); } 33 | class riscv_FCVT_LU_S_instr: riscv_floating_point_instr 34 | { mixin RISCV_INSTR_MIXIN!(FCVT_LU_S, I_FORMAT, ARITHMETIC, RV64F); } 35 | class riscv_FCVT_S_L_instr: riscv_floating_point_instr 36 | { mixin RISCV_INSTR_MIXIN!(FCVT_S_L, I_FORMAT, ARITHMETIC, RV64F); } 37 | class riscv_FCVT_S_LU_instr: riscv_floating_point_instr 38 | { mixin RISCV_INSTR_MIXIN!(FCVT_S_LU, I_FORMAT, ARITHMETIC, RV64F); } 39 | } 40 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv64m_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.isa.rv64m_instr; 19 | 20 | import riscv.gen.riscv_defines; 21 | 22 | import uvm; 23 | 24 | version (RISCV_INSTR_STRING_MIXIN) { 25 | mixin (riscv_instr_mixin(MULW, R_FORMAT, ARITHMETIC, RV64M)); 26 | mixin (riscv_instr_mixin(DIVW, R_FORMAT, ARITHMETIC, RV64M)); 27 | mixin (riscv_instr_mixin(DIVUW, R_FORMAT, ARITHMETIC, RV64M)); 28 | mixin (riscv_instr_mixin(REMW, R_FORMAT, ARITHMETIC, RV64M)); 29 | mixin (riscv_instr_mixin(REMUW, R_FORMAT, ARITHMETIC, RV64M)); 30 | } 31 | else { 32 | class riscv_MULW_instr: riscv_instr 33 | { mixin RISCV_INSTR_MIXIN!(MULW, R_FORMAT, ARITHMETIC, RV64M); } 34 | class riscv_DIVW_instr: riscv_instr 35 | { mixin RISCV_INSTR_MIXIN!(DIVW, R_FORMAT, ARITHMETIC, RV64M); } 36 | class riscv_DIVUW_instr: riscv_instr 37 | { mixin RISCV_INSTR_MIXIN!(DIVUW, R_FORMAT, ARITHMETIC, RV64M); } 38 | class riscv_REMW_instr: riscv_instr 39 | { mixin RISCV_INSTR_MIXIN!(REMW, R_FORMAT, ARITHMETIC, RV64M); } 40 | class riscv_REMUW_instr: riscv_instr 41 | { mixin RISCV_INSTR_MIXIN!(REMUW, R_FORMAT, ARITHMETIC, RV64M); } 42 | } 43 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv64zba_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * Copyright 2022 Coverify Systems Technology 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | module riscv.gen.isa.rv64zba_instr; 20 | 21 | import riscv.gen.riscv_defines; 22 | 23 | import uvm; 24 | 25 | version (RISCV_INSTR_STRING_MIXIN) { 26 | mixin (riscv_zba_instr_mixin(ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA)); 27 | mixin (riscv_zba_instr_mixin(SH1ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA)); 28 | mixin (riscv_zba_instr_mixin(SH2ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA)); 29 | mixin (riscv_zba_instr_mixin(SH3ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA)); 30 | mixin (riscv_zba_instr_mixin(SLLI_UW, I_FORMAT, SHIFT, RV64ZBA, UIMM)); 31 | } 32 | else { 33 | class riscv_ADD_UW_instr: riscv_zba_instr 34 | { mixin RISCV_INSTR_MIXIN!(ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); } 35 | class riscv_SH1ADD_UW_instr: riscv_zba_instr 36 | { mixin RISCV_INSTR_MIXIN!(SH1ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); } 37 | class riscv_SH2ADD_UW_instr: riscv_zba_instr 38 | { mixin RISCV_INSTR_MIXIN!(SH2ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); } 39 | class riscv_SH3ADD_UW_instr: riscv_zba_instr 40 | { mixin RISCV_INSTR_MIXIN!(SH3ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); } 41 | class riscv_SLLI_UW_instr: riscv_zba_instr 42 | { mixin RISCV_INSTR_MIXIN!(SLLI_UW, I_FORMAT, SHIFT, RV64ZBA, UIMM); } 43 | } 44 | -------------------------------------------------------------------------------- /euvm/riscv/gen/isa/rv64zbb_instr.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * Copyright 2022 Coverify Systems Technology 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | module riscv.gen.isa.rv64zbb_instr; 20 | 21 | import riscv.gen.riscv_defines; 22 | 23 | import uvm; 24 | 25 | version (RISCV_INSTR_STRING_MIXIN) { 26 | mixin (riscv_zbb_instr_mixin(CLZW, I_FORMAT, ARITHMETIC, RV64ZBB)); 27 | mixin (riscv_zbb_instr_mixin(CPOPW, I_FORMAT, ARITHMETIC, RV64ZBB)); 28 | mixin (riscv_zbb_instr_mixin(CTZW, I_FORMAT, ARITHMETIC, RV64ZBB)); 29 | mixin (riscv_zbb_instr_mixin(ROLW, R_FORMAT, SHIFT, RV64ZBB)); 30 | mixin (riscv_zbb_instr_mixin(RORW, R_FORMAT, SHIFT, RV64ZBB)); 31 | mixin (riscv_zbb_instr_mixin(RORIW, I_FORMAT, SHIFT, RV64ZBB, UIMM)); 32 | } 33 | else { 34 | class riscv_CLZW_instr: riscv_zbb_instr 35 | { mixin RISCV_INSTR_MIXIN!(CLZW, I_FORMAT, ARITHMETIC, RV64ZBB); } 36 | class riscv_CPOPW_instr: riscv_zbb_instr 37 | { mixin RISCV_INSTR_MIXIN!(CPOPW, I_FORMAT, ARITHMETIC, RV64ZBB); } 38 | class riscv_CTZW_instr: riscv_zbb_instr 39 | { mixin RISCV_INSTR_MIXIN!(CTZW, I_FORMAT, ARITHMETIC, RV64ZBB); } 40 | class riscv_ROLW_instr: riscv_zbb_instr 41 | { mixin RISCV_INSTR_MIXIN!(ROLW, R_FORMAT, SHIFT, RV64ZBB); } 42 | class riscv_RORW_instr: riscv_zbb_instr 43 | { mixin RISCV_INSTR_MIXIN!(RORW, R_FORMAT, SHIFT, RV64ZBB); } 44 | class riscv_RORIW_instr: riscv_zbb_instr 45 | { mixin RISCV_INSTR_MIXIN!(RORIW, I_FORMAT, SHIFT, RV64ZBB, UIMM); } 46 | } 47 | -------------------------------------------------------------------------------- /euvm/riscv/gen/package.d: -------------------------------------------------------------------------------- 1 | module riscv.gen; 2 | 3 | public import riscv.gen.isa; 4 | public import riscv.gen.target; 5 | 6 | public import riscv.gen.riscv_amo_instr_lib; 7 | public import riscv.gen.riscv_asm_program_gen; 8 | public import riscv.gen.riscv_callstack_gen; 9 | public import riscv.gen.riscv_custom_instr_enum; 10 | public import riscv.gen.riscv_data_page_gen; 11 | public import riscv.gen.riscv_debug_rom_gen; 12 | public import riscv.gen.riscv_directed_instr_lib; 13 | public import riscv.gen.riscv_illegal_instr; 14 | public import riscv.gen.riscv_instr_gen_config; 15 | public import riscv.gen.riscv_instr_pkg; 16 | public import riscv.gen.riscv_instr_registry; 17 | public import riscv.gen.riscv_instr_sequence; 18 | public import riscv.gen.riscv_instr_stream; 19 | public import riscv.gen.riscv_load_store_instr_lib; 20 | public import riscv.gen.riscv_loop_instr; 21 | public import riscv.gen.riscv_page_table; 22 | public import riscv.gen.riscv_page_table_entry; 23 | public import riscv.gen.riscv_page_table_exception_cfg; 24 | public import riscv.gen.riscv_page_table_list; 25 | public import riscv.gen.riscv_pmp_cfg; 26 | public import riscv.gen.riscv_privileged_common_seq; 27 | public import riscv.gen.riscv_privil_reg; 28 | public import riscv.gen.riscv_pseudo_instr; 29 | public import riscv.gen.riscv_reg; 30 | public import riscv.gen.riscv_signature_pkg; 31 | public import riscv.gen.riscv_vector_cfg; 32 | public import riscv.gen.riscv_defines; 33 | -------------------------------------------------------------------------------- /euvm/riscv/gen/riscv_custom_instr_enum.d: -------------------------------------------------------------------------------- 1 | //TODO custom instruction added 2 | // CUSTOM_i, 3 | module riscv.gen.riscv_custom_instr_enum; 4 | -------------------------------------------------------------------------------- /euvm/riscv/gen/riscv_signature_pkg.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2019 Google LLC 3 | * Copyright 2022 Coverify Systems Technology 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | module riscv.gen.riscv_signature_pkg; 19 | 20 | // Will be the lowest 8 bits of the data word 21 | enum signature_type_t: byte { 22 | // Information sent to the core relating its current status. 23 | // Bits [12:8] of the data word will be the core_status_t value 24 | // corresponding to the current core status. 25 | CORE_STATUS, 26 | // Information sent to the core conveying the uvm simulation result. 27 | // Bit [8] of the data word will be the test_result_t value. 28 | TEST_RESULT, 29 | // Sent to the core to indicate a dump of GPRs to testbench. 30 | // Will be followed by 32 writes of registers x0-x32. 31 | WRITE_GPR, 32 | // Sent to the core to indicate a write of a CSR's data. 33 | // Bits [19:8] of the data word will be the CSR address. 34 | // Will be followed by a second write of the actual data from the CSR. 35 | WRITE_CSR 36 | } 37 | 38 | enum core_status_t: byte { 39 | INITIALIZED, 40 | IN_DEBUG_MODE, 41 | IN_MACHINE_MODE, 42 | IN_HYPERVISOR_MODE, 43 | IN_SUPERVISOR_MODE, 44 | IN_USER_MODE, 45 | HANDLING_IRQ, 46 | FINISHED_IRQ, 47 | HANDLING_EXCEPTION, 48 | INSTR_FAULT_EXCEPTION, 49 | ILLEGAL_INSTR_EXCEPTION, 50 | LOAD_FAULT_EXCEPTION, 51 | STORE_FAULT_EXCEPTION, 52 | EBREAK_EXCEPTION 53 | } 54 | 55 | enum test_result_t: bool { 56 | TEST_PASS, 57 | TEST_FAIL 58 | } 59 | -------------------------------------------------------------------------------- /euvm/riscv/gen/target/package.d: -------------------------------------------------------------------------------- 1 | module riscv.gen.target; 2 | 3 | version(RV32IMCB) { 4 | pragma (msg, "Using target: RV32IMCB"); 5 | public import riscv.gen.target.rv32imcb.riscv_core_setting; 6 | } 7 | else version(RV64GCV) { 8 | pragma (msg, "Using target: RV64GCV"); 9 | public import riscv.gen.target.rv64gcv.riscv_core_setting; 10 | } 11 | else version(RV64GC) { 12 | pragma (msg, "Using target: RV64GC"); 13 | public import riscv.gen.target.rv64gc.riscv_core_setting; 14 | } 15 | else version(RV64IMCB) { 16 | pragma (msg, "Using target: RV64IMCB"); 17 | public import riscv.gen.target.rv64imcb.riscv_core_setting; 18 | } 19 | else version(RV32IMAFDC) { 20 | pragma (msg, "Using target: RV32IMAFDC"); 21 | public import riscv.gen.target.rv32imafdc.riscv_core_setting; 22 | } 23 | else version(ML) { 24 | pragma (msg, "Using target: ML"); 25 | public import riscv.gen.target.ml.riscv_core_setting; 26 | } 27 | else version(MULTI_HARTS) { 28 | pragma (msg, "Using target: MULTI_HARTS"); 29 | public import riscv.gen.target.multi_harts.riscv_core_setting; 30 | } 31 | else version(RV32IMC_SV32) { 32 | pragma (msg, "Using target: RV32IMC_SV32"); 33 | public import riscv.gen.target.rv32imc_sv32.riscv_core_setting; 34 | } 35 | else version(RV32I) { 36 | pragma (msg, "Using target: RV32I"); 37 | public import riscv.gen.target.rv32i.riscv_core_setting; 38 | } 39 | else version(RV64IMC) { 40 | pragma (msg, "Using target: RV64IMC"); 41 | public import riscv.gen.target.rv64imc.riscv_core_setting; 42 | } 43 | else version(RV32IMC) { 44 | pragma (msg, "Using target: RV32IMC"); 45 | public import riscv.gen.target.rv32imc.riscv_core_setting; 46 | } 47 | else { 48 | pragma (msg, "Using Default target: RV64IMC"); 49 | public import riscv.gen.target.rv64imc.riscv_core_setting; 50 | } 51 | -------------------------------------------------------------------------------- /euvm/riscv/test/riscv_instr_gen.d: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2022 Coverify Systems Technology 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | import uvm; 18 | import esdl; 19 | 20 | int main(string[] args) { 21 | import std.stdio: writeln; 22 | 23 | uint random_seed; 24 | uint thread_index; 25 | uint thread_count; 26 | 27 | CommandLine cmdl = new CommandLine(args); 28 | 29 | if (cmdl.plusArgs("random_seed=" ~ "%d", random_seed)) 30 | writeln("Using random_seed: ", random_seed); 31 | else random_seed = 1; 32 | 33 | if (! cmdl.plusArgs("thread_index=" ~ "%d", thread_index)) 34 | thread_index = 0; 35 | if (! cmdl.plusArgs("thread_count=" ~ "%d", thread_count)) 36 | thread_count = 1; 37 | 38 | auto testbench = new uvm_testbench; 39 | 40 | testbench.multicore(thread_index, thread_count); 41 | testbench.elaborate("test", args); 42 | testbench.set_seed(random_seed); 43 | testbench.set_async_mode(); 44 | 45 | return testbench.start(); 46 | } 47 | -------------------------------------------------------------------------------- /files.f: -------------------------------------------------------------------------------- 1 | // Copyright 2018 Google LLC 2 | // 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | // 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | // 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | // HEADERS 16 | +incdir+${RISCV_DV_ROOT}/src 17 | +incdir+${RISCV_DV_ROOT}/test 18 | 19 | // SOURCES 20 | ${RISCV_DV_ROOT}/src/riscv_signature_pkg.sv 21 | ${RISCV_DV_ROOT}/src/riscv_instr_pkg.sv 22 | ${RISCV_DV_ROOT}/test/riscv_instr_test_pkg.sv 23 | ${RISCV_DV_ROOT}/test/riscv_instr_gen_tb_top.sv 24 | -------------------------------------------------------------------------------- /pygen/experimental/README.md: -------------------------------------------------------------------------------- 1 | ### Overview 2 | 3 | This directory contains the proof-of-concept work of python based RISC-V random 4 | instruction generator. The class structure can be directly mapped to the 5 | existing SV/UVM verison. The constraint part is implemented based on 6 | [python-constraint](https://labix.org/python-constraint). 7 | 8 | The work here is just experimental. We plan to take a fresh look of the 9 | framework and build a scalable python based generator in the near future. 10 | 11 | ### Install required packages 12 | 13 | ```bash 14 | pip3 install python-constraint 15 | pip3 install numpy 16 | pip3 install bitstring 17 | ``` 18 | 19 | ### Generate a simple test 20 | 21 | ```bash 22 | python3 riscv_asm_program_gen.py 23 | ``` 24 | -------------------------------------------------------------------------------- /pygen/experimental/riscv_data_page_gen.py: -------------------------------------------------------------------------------- 1 | """Copyright 2020 Google LLC 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | 15 | """ 16 | 17 | import utils 18 | import random 19 | from bitstring import BitArray, BitStream 20 | 21 | 22 | # ----------------------------------------------------------------------------------------- 23 | # RISC-V assmebly program data section generator 24 | # There can be user mode and supervisor(kernel) mode data pages 25 | # ----------------------------------------------------------------------------------------- 26 | class riscv_data_page_gen: 27 | 28 | def __init__(self): 29 | self.data_page_str = [] 30 | # TO DO: cfg 31 | # cfg... 32 | 33 | # The data section can be initialized with different data pattern: 34 | # Random value, incremental value, all zeros 35 | def gen_data(self, idx, pattern, num_of_bytes): 36 | data = [None] * num_of_bytes 37 | for i in range(len(data)): 38 | if pattern == "RAND_DATA": 39 | temp_data = random.randint(0, 255) 40 | # data[i] = temp_data 41 | data[i] = BitArray(uint=temp_data, length=8) 42 | elif pattern == "INCR_VAL": 43 | # data[i] = (idx+i) % 256 44 | data[i] = BitArray(uint=(idx + i) % 256, length=8) 45 | return data 46 | 47 | # Generate the assembly code for the data section 48 | def gen_data_page(self, pattern, is_kernel=0): 49 | self.data_page_str.clear() 50 | # TO DO: need to embed num_of_kernel_data_pages, num_of_data_pages, etc. in the riscv_core_setting 51 | page_cnt = 1 if is_kernel else 2 52 | page_size = 4096 53 | for section_idx in range(page_cnt): 54 | if is_kernel: 55 | self.data_page_str.append("kernel_data_page_{}:".format(section_idx)) 56 | else: 57 | self.data_page_str.append("data_page_{}:".format(section_idx)) 58 | # TO DO: need to embed data_page_alignment in the core_setting 59 | self.data_page_str.append(".align 12") 60 | for i in range(0, page_size, 32): 61 | tmp_data = self.gen_data(i, pattern, 32) 62 | tmp_str = ".word {:{}}".format( 63 | utils.format_data(tmp_data), utils.length) 64 | self.data_page_str.append(tmp_str) 65 | -------------------------------------------------------------------------------- /pygen/experimental/riscv_rand_instr.py: -------------------------------------------------------------------------------- 1 | """Copyright 2020 Google LLC 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | """ 15 | 16 | import riscv_instr_base 17 | import utils 18 | 19 | 20 | class riscv_rand_instr(riscv_instr_base.riscv_instr_base): 21 | 22 | def __init__(self): 23 | # Calling the super constructor 24 | riscv_instr_base.riscv_instr_base.__init__(self) 25 | # TODO: TO DO config 26 | # Some additional reserved registers 27 | self.reserved_rd = [] 28 | 29 | def problem_definition(self, 30 | no_branch=0, 31 | no_load_store=1, 32 | enable_hint_instr=0): 33 | # Calling the super problem_definition, to apply all the constraints to the base object 34 | super().problem_definition(no_branch, no_load_store, enable_hint_instr) 35 | 36 | # TO DO: need to complete it when we support compressed instructions 37 | def instr_c(category, rd, rs1): 38 | cond1 = category in [ 39 | "LOAD", "STORE", "SHIFT", "ARITHMETIC", "LOGICAL", "BRANCH", 40 | "COMPARE", "CSR", "SYSTEM", "SYNCH" 41 | ] 42 | cond2 = rs1 not in [self.reserved_rd, "ZERO" 43 | ] if category in ["LOAD", "STORE"] else True 44 | cond3 = rd not in self.reserved_rd if len(self.reserved_rd) > 0 else True 45 | # TO DO: Compressed instruction may use the same CSR for both rs1 and rd 46 | if cond1 and cond2 and cond3: 47 | return True 48 | 49 | # TO DO: Registers specified by the three-bit rs1’, rs2’, and rd’ fields of the CIW, CL, CS, 50 | # and CB formats 51 | def rvc_csr_c(): 52 | pass 53 | 54 | def constraint_cfg_knob_c(name): 55 | # TO DO: cfg for no_ebreak, no_wfi, no_load_store, and no_branch_jump 56 | if name not in ["ECALL", "URET", "SRET", "MRET"]: 57 | return True 58 | 59 | self.problem.addConstraint( 60 | instr_c, [self.instr_category, self.instr_rd, self.instr_src1]) 61 | self.problem.addConstraint(constraint_cfg_knob_c, [self.instr_name]) 62 | return 63 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv32a_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | """ 13 | 14 | from pygen_src.riscv_defines import DEFINE_AMO_INSTR 15 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 16 | riscv_instr_category_t, riscv_instr_group_t) 17 | 18 | 19 | DEFINE_AMO_INSTR(riscv_instr_name_t.LR_W, riscv_instr_format_t.R_FORMAT, 20 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32A, g=globals()) 21 | DEFINE_AMO_INSTR(riscv_instr_name_t.SC_W, riscv_instr_format_t.R_FORMAT, 22 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV32A, g=globals()) 23 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOSWAP_W, riscv_instr_format_t.R_FORMAT, 24 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 25 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOADD_W, riscv_instr_format_t.R_FORMAT, 26 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 27 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOAND_W, riscv_instr_format_t.R_FORMAT, 28 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 29 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOOR_W, riscv_instr_format_t.R_FORMAT, 30 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 31 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOXOR_W, riscv_instr_format_t.R_FORMAT, 32 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 33 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMIN_W, riscv_instr_format_t.R_FORMAT, 34 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 35 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMAX_W, riscv_instr_format_t.R_FORMAT, 36 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 37 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMINU_W, riscv_instr_format_t.R_FORMAT, 38 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 39 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMAXU_W, riscv_instr_format_t.R_FORMAT, 40 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV32A, g=globals()) 41 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv32dc_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | 13 | """ 14 | 15 | from pygen_src.riscv_defines import DEFINE_FC_INSTR 16 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 17 | riscv_instr_category_t, riscv_instr_group_t, imm_t) 18 | 19 | 20 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FLD, riscv_instr_format_t.CL_FORMAT, 21 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32DC, imm_t.UIMM, g=globals()) 22 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FSD, riscv_instr_format_t.CS_FORMAT, 23 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV32DC, imm_t.UIMM, g=globals()) 24 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FLDSP, riscv_instr_format_t.CI_FORMAT, 25 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32DC, imm_t.UIMM, g=globals()) 26 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FSDSP, riscv_instr_format_t.CSS_FORMAT, 27 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV32DC, imm_t.UIMM, g=globals()) 28 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv32fc_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | 13 | """ 14 | 15 | from pygen_src.riscv_defines import DEFINE_FC_INSTR 16 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 17 | riscv_instr_category_t, riscv_instr_group_t, imm_t) 18 | 19 | 20 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FLW, riscv_instr_format_t.CL_FORMAT, 21 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32FC, imm_t.UIMM, g=globals()) 22 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FSW, riscv_instr_format_t.CS_FORMAT, 23 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV32FC, imm_t.UIMM, g=globals()) 24 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FLWSP, riscv_instr_format_t.CI_FORMAT, 25 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32FC, imm_t.UIMM, g=globals()) 26 | DEFINE_FC_INSTR(riscv_instr_name_t.C_FSWSP, riscv_instr_format_t.CSS_FORMAT, 27 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV32FC, imm_t.UIMM, g=globals()) 28 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv32m_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | 13 | """ 14 | 15 | from pygen_src.riscv_defines import DEFINE_INSTR 16 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 17 | riscv_instr_category_t, riscv_instr_group_t) 18 | 19 | # Multiplication and Division Instructions 20 | DEFINE_INSTR(riscv_instr_name_t.MUL, riscv_instr_format_t.R_FORMAT, 21 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 22 | DEFINE_INSTR(riscv_instr_name_t.MULH, riscv_instr_format_t.R_FORMAT, 23 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 24 | DEFINE_INSTR(riscv_instr_name_t.MULHSU, riscv_instr_format_t.R_FORMAT, 25 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 26 | DEFINE_INSTR(riscv_instr_name_t.MULHU, riscv_instr_format_t.R_FORMAT, 27 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 28 | DEFINE_INSTR(riscv_instr_name_t.DIV, riscv_instr_format_t.R_FORMAT, 29 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 30 | DEFINE_INSTR(riscv_instr_name_t.DIVU, riscv_instr_format_t.R_FORMAT, 31 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 32 | DEFINE_INSTR(riscv_instr_name_t.REM, riscv_instr_format_t.R_FORMAT, 33 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV32M, g=globals()) 34 | DEFINE_INSTR(riscv_instr_name_t.REMU, riscv_instr_format_t.R_FORMAT, 35 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32M, g=globals()) 36 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv64a_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | """ 13 | 14 | from pygen_src.riscv_defines import DEFINE_AMO_INSTR 15 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 16 | riscv_instr_category_t, riscv_instr_group_t) 17 | 18 | DEFINE_AMO_INSTR(riscv_instr_name_t.LR_D, riscv_instr_format_t.R_FORMAT, 19 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64A, g=globals()) 20 | DEFINE_AMO_INSTR(riscv_instr_name_t.SC_D, riscv_instr_format_t.R_FORMAT, 21 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV64A, g=globals()) 22 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOSWAP_D, riscv_instr_format_t.R_FORMAT, 23 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 24 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOADD_D, riscv_instr_format_t.R_FORMAT, 25 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 26 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOAND_D, riscv_instr_format_t.R_FORMAT, 27 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 28 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOOR_D, riscv_instr_format_t.R_FORMAT, 29 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 30 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOXOR_D, riscv_instr_format_t.R_FORMAT, 31 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 32 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMIN_D, riscv_instr_format_t.R_FORMAT, 33 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 34 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMAX_D, riscv_instr_format_t.R_FORMAT, 35 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 36 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMINU_D, riscv_instr_format_t.R_FORMAT, 37 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 38 | DEFINE_AMO_INSTR(riscv_instr_name_t.AMOMAXU_D, riscv_instr_format_t.R_FORMAT, 39 | riscv_instr_category_t.AMO, riscv_instr_group_t.RV64A, g=globals()) 40 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv64c_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | 13 | """ 14 | 15 | from pygen_src.riscv_defines import DEFINE_C_INSTR 16 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 17 | riscv_instr_category_t, riscv_instr_group_t) 18 | 19 | 20 | DEFINE_C_INSTR(riscv_instr_name_t.C_ADDIW, riscv_instr_format_t.CI_FORMAT, 21 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals()) 22 | DEFINE_C_INSTR(riscv_instr_name_t.C_SUBW, riscv_instr_format_t.CA_FORMAT, 23 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals()) 24 | DEFINE_C_INSTR(riscv_instr_name_t.C_ADDW, riscv_instr_format_t.CA_FORMAT, 25 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals()) 26 | DEFINE_C_INSTR(riscv_instr_name_t.C_LD, riscv_instr_format_t.CL_FORMAT, 27 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals()) 28 | DEFINE_C_INSTR(riscv_instr_name_t.C_SD, riscv_instr_format_t.CS_FORMAT, 29 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV64C, g=globals()) 30 | DEFINE_C_INSTR(riscv_instr_name_t.C_LDSP, riscv_instr_format_t.CI_FORMAT, 31 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals()) 32 | DEFINE_C_INSTR(riscv_instr_name_t.C_SDSP, riscv_instr_format_t.CSS_FORMAT, 33 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV64C, g=globals()) 34 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv64d_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | """ 13 | 14 | from pygen_src.riscv_defines import DEFINE_FP_INSTR 15 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 16 | riscv_instr_category_t, riscv_instr_group_t) 17 | 18 | DEFINE_FP_INSTR(riscv_instr_name_t.FMV_X_D, riscv_instr_format_t.I_FORMAT, 19 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64D, g=globals()) 20 | DEFINE_FP_INSTR(riscv_instr_name_t.FMV_D_X, riscv_instr_format_t.I_FORMAT, 21 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64D, g=globals()) 22 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_L_D, riscv_instr_format_t.I_FORMAT, 23 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64D, g=globals()) 24 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_LU_D, riscv_instr_format_t.I_FORMAT, 25 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64D, g=globals()) 26 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_D_L, riscv_instr_format_t.I_FORMAT, 27 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64D, g=globals()) 28 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_D_LU, riscv_instr_format_t.I_FORMAT, 29 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64D, g=globals()) 30 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv64f_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | """ 13 | 14 | from pygen_src.riscv_defines import DEFINE_FP_INSTR 15 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 16 | riscv_instr_category_t, riscv_instr_group_t) 17 | 18 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_L_S, riscv_instr_format_t.I_FORMAT, 19 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64F, g=globals()) 20 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_LU_S, riscv_instr_format_t.I_FORMAT, 21 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64F, g=globals()) 22 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_S_L, riscv_instr_format_t.I_FORMAT, 23 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64F, g=globals()) 24 | DEFINE_FP_INSTR(riscv_instr_name_t.FCVT_S_LU, riscv_instr_format_t.I_FORMAT, 25 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64F, g=globals()) 26 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv64i_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | 13 | """ 14 | 15 | from pygen_src.riscv_defines import DEFINE_INSTR 16 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 17 | riscv_instr_category_t, riscv_instr_group_t) 18 | 19 | 20 | DEFINE_INSTR(riscv_instr_name_t.LWU, riscv_instr_format_t.I_FORMAT, 21 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64I, g=globals()) 22 | DEFINE_INSTR(riscv_instr_name_t.LD, riscv_instr_format_t.I_FORMAT, 23 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64I, g=globals()) 24 | DEFINE_INSTR(riscv_instr_name_t.SD, riscv_instr_format_t.S_FORMAT, 25 | riscv_instr_category_t.STORE, riscv_instr_group_t.RV64I, g=globals()) 26 | # SHIFT intructions 27 | DEFINE_INSTR(riscv_instr_name_t.SLLW, riscv_instr_format_t.R_FORMAT, 28 | riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals()) 29 | DEFINE_INSTR(riscv_instr_name_t.SLLIW, riscv_instr_format_t.I_FORMAT, 30 | riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals()) 31 | DEFINE_INSTR(riscv_instr_name_t.SRLW, riscv_instr_format_t.R_FORMAT, 32 | riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals()) 33 | DEFINE_INSTR(riscv_instr_name_t.SRLIW, riscv_instr_format_t.I_FORMAT, 34 | riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals()) 35 | DEFINE_INSTR(riscv_instr_name_t.SRAW, riscv_instr_format_t.R_FORMAT, 36 | riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals()) 37 | DEFINE_INSTR(riscv_instr_name_t.SRAIW, riscv_instr_format_t.I_FORMAT, 38 | riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals()) 39 | # ARITHMETIC intructions 40 | DEFINE_INSTR(riscv_instr_name_t.ADDW, riscv_instr_format_t.R_FORMAT, 41 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64I, g=globals()) 42 | DEFINE_INSTR(riscv_instr_name_t.ADDIW, riscv_instr_format_t.I_FORMAT, 43 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64I, g=globals()) 44 | DEFINE_INSTR(riscv_instr_name_t.SUBW, riscv_instr_format_t.R_FORMAT, 45 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64I, g=globals()) 46 | -------------------------------------------------------------------------------- /pygen/pygen_src/isa/rv64m_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | 13 | """ 14 | 15 | from pygen_src.riscv_defines import DEFINE_INSTR 16 | from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t, 17 | riscv_instr_category_t, riscv_instr_group_t) 18 | 19 | 20 | DEFINE_INSTR(riscv_instr_name_t.MULW, riscv_instr_format_t.R_FORMAT, 21 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals()) 22 | DEFINE_INSTR(riscv_instr_name_t.DIVW, riscv_instr_format_t.R_FORMAT, 23 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals()) 24 | DEFINE_INSTR(riscv_instr_name_t.DIVUW, riscv_instr_format_t.R_FORMAT, 25 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals()) 26 | DEFINE_INSTR(riscv_instr_name_t.REMW, riscv_instr_format_t.R_FORMAT, 27 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals()) 28 | DEFINE_INSTR(riscv_instr_name_t.REMUW, riscv_instr_format_t.R_FORMAT, 29 | riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals()) 30 | -------------------------------------------------------------------------------- /pygen/pygen_src/riscv_pseudo_instr.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | Unless required by applicable law or agreed to in writing, software 9 | distributed under the License is distributed on an "AS IS" BASIS, 10 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 | """ 12 | 13 | import vsc 14 | from pygen_src.isa.riscv_instr import riscv_instr 15 | from pygen_src.riscv_instr_pkg import (riscv_pseudo_instr_name_t, riscv_instr_format_t, 16 | riscv_instr_category_t, riscv_instr_group_t, pkg_ins) 17 | # from pygen_src.riscv_defines import add_pseudo_instr 18 | 19 | 20 | # Psuedo instructions are used to simplify assembly program writing 21 | @vsc.randobj 22 | class riscv_pseudo_instr(riscv_instr): 23 | def __init__(self): 24 | super().__init__() 25 | self.process_load_store = 0 26 | self.format = riscv_instr_format_t.I_FORMAT 27 | self.pseudo_instr_name = vsc.rand_enum_t(riscv_pseudo_instr_name_t) 28 | 29 | ''' 30 | TODO 31 | add_pseudo_instr(self, riscv_pseudo_instr_name_t.LI, riscv_instr_format_t.I_FORMAT, 32 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32I) 33 | add_pseudo_instr(self, riscv_pseudo_instr_name_t.LA, riscv_instr_format_t.I_FORMAT, 34 | riscv_instr_category_t.LOAD, riscv_instr_group_t.RV32I) 35 | ''' 36 | 37 | # Convert the instruction to assembly code 38 | def convert2asm(self, prefix = ""): 39 | asm_str = pkg_ins.format_string(self.get_instr_name(), pkg_ins.MAX_INSTR_STR_LEN) 40 | # instr rd,imm 41 | asm_str = "{}{}, {}".format(asm_str, self.rd.name, self.get_imm()) 42 | if self.comment != "": 43 | asm_str = "{} #{}".format(asm_str, self.comment) 44 | return asm_str.lower() 45 | 46 | def get_instr_name(self): 47 | return self.pseudo_instr_name.name 48 | -------------------------------------------------------------------------------- /pygen/pygen_src/riscv_signature_pkg.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | Unless required by applicable law or agreed to in writing, software 9 | distributed under the License is distributed on an "AS IS" BASIS, 10 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 | """ 12 | 13 | from enum import IntEnum, auto 14 | 15 | 16 | # Will be the lowest 8 bits of the data word 17 | class signature_type_t(IntEnum): 18 | ''' 19 | Information sent to the core relating its current status. 20 | Bits [12:8] of the data word will be the core_status_t value 21 | corresponding to the current core status. 22 | ''' 23 | CORE_STATUS = 0 24 | ''' 25 | Information sent to the core conveying the uvm simulation result. 26 | Bit [8] of the data word will be the test_result_t value. 27 | ''' 28 | TEST_RESULT = auto() 29 | ''' 30 | Sent to the core to indicate a dump of GPRs to testbench. 31 | Will be followed by 32 writes of registers x0-x32. 32 | ''' 33 | WRITE_GPR = auto() 34 | ''' 35 | Sent to the core to indicate a write of a CSR's data. 36 | Bits [19:8] of the data word will be the CSR address. 37 | Will be followed by a second write of the actual data from the CSR. 38 | ''' 39 | WRITE_CSR = auto() 40 | 41 | 42 | class core_status_t(IntEnum): 43 | INITIALIZED = 0 44 | IN_DEBUG_MODE = auto() 45 | IN_MACHINE_MODE = auto() 46 | IN_HYPERVISOR_MODE = auto() 47 | IN_SUPERVISOR_MODE = auto() 48 | IN_USER_MODE = auto() 49 | HANDLING_IRQ = auto() 50 | FINISHED_IRQ = auto() 51 | HANDLING_EXCEPTION = auto() 52 | INSTR_FAULT_EXCEPTION = auto() 53 | ILLEGAL_INSTR_EXCEPTION = auto() 54 | LOAD_FAULT_EXCEPTION = auto() 55 | STORE_FAULT_EXCEPTION = auto() 56 | EBREAK_EXCEPTION = auto() 57 | 58 | 59 | class test_result_t(IntEnum): 60 | TEST_PASS = 0 61 | TEST_FAIL = auto() 62 | -------------------------------------------------------------------------------- /pygen/pygen_src/target/multi_harts/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MCA 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /pygen/pygen_src/target/rv32i/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/misa_MXL=1 4 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 5 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/unaligned=T 7 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 8 | --override riscvOVPsim/cpu/user_version=2.3 9 | --override riscvOVPsim/cpu/priv_version=1.11 10 | --override riscvOVPsim/cpu/mvendorid=0 11 | --override riscvOVPsim/cpu/marchid=0 12 | --override riscvOVPsim/cpu/mimpid=0 13 | --override riscvOVPsim/cpu/mhartid=0 14 | --override riscvOVPsim/cpu/cycle_undefined=F 15 | --override riscvOVPsim/cpu/instret_undefined=F 16 | --override riscvOVPsim/cpu/time_undefined=T 17 | --override riscvOVPsim/cpu/reset_address=0x80000000 18 | --override riscvOVPsim/cpu/simulateexceptions=T 19 | --override riscvOVPsim/cpu/defaultsemihost=F 20 | --override riscvOVPsim/cpu/wfi_is_nop=T 21 | --exitonsymbol _exit 22 | -------------------------------------------------------------------------------- /pygen/pygen_src/target/rv32imafdc/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64GC 3 | --override riscvOVPsim/cpu/misa_MXL=2 4 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 5 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/unaligned=T 7 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 8 | --override riscvOVPsim/cpu/user_version=2.3 9 | --override riscvOVPsim/cpu/priv_version=1.11 10 | --override riscvOVPsim/cpu/mvendorid=0 11 | --override riscvOVPsim/cpu/marchid=0 12 | --override riscvOVPsim/cpu/mimpid=0 13 | --override riscvOVPsim/cpu/mhartid=0 14 | --override riscvOVPsim/cpu/cycle_undefined=F 15 | --override riscvOVPsim/cpu/instret_undefined=F 16 | --override riscvOVPsim/cpu/time_undefined=T 17 | --override riscvOVPsim/cpu/reset_address=0x80000000 18 | --override riscvOVPsim/cpu/simulateexceptions=T 19 | --override riscvOVPsim/cpu/defaultsemihost=F 20 | --override riscvOVPsim/cpu/wfi_is_nop=T 21 | --exitonsymbol _exit 22 | -------------------------------------------------------------------------------- /pygen/pygen_src/target/rv32imc/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MC 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /pygen/pygen_src/target/rv32imcb/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MCB 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /pygen/pygen_src/test/riscv_rand_instr_test.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | Unless required by applicable law or agreed to in writing, software 9 | distributed under the License is distributed on an "AS IS" BASIS, 10 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 | """ 12 | 13 | import sys 14 | import time 15 | import logging 16 | sys.path.append("pygen/") 17 | from pygen_src.test.riscv_instr_base_test import riscv_instr_base_test 18 | from pygen_src.riscv_instr_gen_config import cfg 19 | from pygen_src.riscv_utils import gen_config_table 20 | 21 | 22 | class riscv_rand_instr_test(riscv_instr_base_test): 23 | def __init__(self): 24 | super().__init__() 25 | 26 | def randomize_cfg(self): 27 | cfg.instr_cnt = 10000 28 | cfg.num_of_sub_program = 5 29 | cfg.randomize() 30 | logging.info("riscv_instr_gen_config is randomized") 31 | gen_config_table() 32 | 33 | def apply_directed_instr(self): 34 | # Mix below directed instruction streams with the random instructions 35 | self.asm.add_directed_instr_stream("riscv_load_store_rand_instr_stream", 4) 36 | # self.asm.add_directed_instr_stream("riscv_loop_instr", 3) 37 | self.asm.add_directed_instr_stream("riscv_jal_instr", 4) 38 | # self.asm.add_directed_instr_stream("riscv_hazard_instr_stream", 4) 39 | self.asm.add_directed_instr_stream("riscv_load_store_hazard_instr_stream", 4) 40 | # self.asm.add_directed_instr_stream("riscv_multi_page_load_store_instr_stream", 4) 41 | # self.asm.add_directed_instr_stream("riscv_mem_region_stress_test", 4) 42 | 43 | 44 | start_time = time.time() 45 | riscv_rand_test_ins = riscv_rand_instr_test() 46 | riscv_rand_test_ins.run() 47 | end_time = time.time() 48 | logging.info("Total execution time: {}s".format(round(end_time - start_time))) 49 | -------------------------------------------------------------------------------- /qrun_option.f: -------------------------------------------------------------------------------- 1 | -64 2 | -uvmhome uvm-1.2 3 | -sv 4 | -access=rwc+/. 5 | -mfcu 6 | -cuname design_cuname 7 | +define+UVM_REGEX_NO_DPI 8 | -debug 9 | +designfile 10 | -o design_opt 11 | -optimize 12 | -------------------------------------------------------------------------------- /questa_sim.tcl: -------------------------------------------------------------------------------- 1 | coverage save -onexit riscv.ucdb 2 | run -all ; quit 3 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | PyYAML 2 | bitstring 3 | Sphinx 4 | Pallets-Sphinx-Themes 5 | sphinxcontrib-log-cabinet 6 | sphinx-issues 7 | sphinx_rtd_theme 8 | rst2pdf 9 | flake8 10 | pyvsc 11 | tabulate 12 | pandas 13 | -------------------------------------------------------------------------------- /riviera_sim.tcl: -------------------------------------------------------------------------------- 1 | run -all; endsim; quit -force 2 | -------------------------------------------------------------------------------- /sample/sample_rv32imc_test.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chipsalliance/riscv-dv/7e54b678ab7499040336255550cdbd99ae887431/sample/sample_rv32imc_test.tar.gz -------------------------------------------------------------------------------- /scripts/check-status: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Check the return code of run.py in order to give a pass/fail indication to Metrics 4 | echo "run.py return code:" $1 5 | 6 | if [ $1 == 0 ]; then 7 | echo "Test passed"; 8 | else 9 | echo "Test failed"; 10 | fi 11 | -------------------------------------------------------------------------------- /scripts/genMetricsList.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | ## Summary: 4 | ## This Python script will create regression_list.json file which was referred by by .metrics.json 5 | ## Limitation: 6 | ## Only generate tests targeted for build "rv32imc" 7 | ## 8 | ## Note: Currently available testlists 9 | ## /yaml/base_testlist.yaml 10 | ## /yaml/cov_testlist.yaml 11 | ## /target/rv64gcv/testlist.yaml 12 | ## /target/rv64gc/testlist.yaml 13 | ## /target/rv32imcb/testlist.yaml 14 | ## /target/multi_harts/testlist.yaml 15 | ## /target/rv64imc/testlist.yaml 16 | ## /target/rv32imc/testlist.yaml 17 | ## /target/rv64imcb/testlist.yaml 18 | ## /target/ml/testlist.yaml 19 | ## /target/rv32i/testlist.yaml 20 | 21 | import json 22 | 23 | runCmdBase = "cd /mux-flow/results; python3 /run.py --test TESTNAME --simulator dsim --iss spike --seed --so --out /out --verbose; /scripts/check-status $?; rm -fr /out/dsim" 24 | 25 | ## Based on testlist located in /yaml/base_testlist.yaml 26 | base_testList = ["riscv_arithmetic_basic_test", 27 | "riscv_rand_instr_test", 28 | "riscv_jump_stress_test", 29 | "riscv_loop_test", 30 | "riscv_rand_jump_test", 31 | "riscv_mmu_stress_test", 32 | "riscv_no_fence_test", 33 | "riscv_illegal_instr_test", 34 | "riscv_ebreak_test", 35 | "riscv_ebreak_debug_mode_test", 36 | "riscv_full_interrupt_test", 37 | ## remove, will cause incomplete sim, need customized RTL 38 | ##"riscv_csr_test", 39 | "riscv_unaligned_load_store_test"] 40 | 41 | ## Based on testlist located in /target/rv32imc/testlist.yaml 42 | rv32imc_testList = [ 43 | "riscv_non_compressed_instr_test", 44 | "riscv_hint_instr_test", 45 | "riscv_pmp_test" 46 | ] 47 | 48 | metricsList = [] 49 | 50 | ## Note: Build is targeting rv32imc only. 51 | for testName in base_testList + rv32imc_testList: 52 | test = {} 53 | test["name"] = testName 54 | test["build"] = "rv32imc" 55 | test["cmd"] = runCmdBase.replace("TESTNAME", testName) 56 | test["wavesCmd"] = test["cmd"] 57 | test["logFile"] = "simulation.log" 58 | test["isPass"] = "Test passed" 59 | test["metricsFile"] = "metrics.db" 60 | test["seed"] = "random" 61 | 62 | metricsList.append(test) 63 | 64 | with open("regression_list.json", "w") as f: 65 | json.dump(metricsList, f) 66 | -------------------------------------------------------------------------------- /scripts/link.ld: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Google LLC 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http:*www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | OUTPUT_ARCH( "riscv" ) 17 | ENTRY(_start) 18 | 19 | SECTIONS 20 | { 21 | . = 0x80000000; 22 | .text : { *(.text) } 23 | . = ALIGN(0x1000); 24 | .tohost : { *(.tohost) } 25 | . = ALIGN(0x1000); 26 | .page_table : { *(.page_table) } 27 | .data : { *(.data) } 28 | .user_stack : { *(.user_stack) } 29 | .kernel_data : { *(.kernel_data) } 30 | .kernel_stack : { *(.kernel_stack) } 31 | .bss : { *(.bss) } 32 | _end = .; 33 | } 34 | -------------------------------------------------------------------------------- /setup.cfg: -------------------------------------------------------------------------------- 1 | [metadata] 2 | name = riscv-dv 3 | description = "RISCV-DV is a SV/UVM instruction generator for RISC-V processor verification." 4 | long_description = file: README.md 5 | version = 1.0 6 | author = Google, Inc. 7 | author_email = riscv_dv_dev@google.com. 8 | license = LICENSE.txt 9 | url = https://github.com/google/riscv-dv.git 10 | 11 | [options] 12 | # Automatically find all files beneath the riscv-dv directory and include them. 13 | packages = find: 14 | # Parse the MANIFEST.in file and include those files. 15 | include_package_data = True 16 | # Let pip install dependencies automatically. 17 | install_requires = PyYAML 18 | bitstring 19 | python_requires = >=3 20 | 21 | [options.entry_points] 22 | # Set up an executable script that calls the main() function in riscv-dv 23 | console_scripts = 24 | run = run:main 25 | cov = cov:main 26 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | """ 3 | Copyright 2019 Google LLC 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | 9 | http://www.apache.org/licenses/LICENSE-2.0 10 | 11 | Unless required by applicable law or agreed to in writing, software 12 | distributed under the License is distributed on an "AS IS" BASIS, 13 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | See the License for the specific language governing permissions and 15 | limitations under the License. 16 | 17 | Regression script for RISC-V random instruction generator 18 | """ 19 | from setuptools import setup 20 | 21 | setup() 22 | -------------------------------------------------------------------------------- /src/isa/custom/riscv_custom_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | // Custom instruction class 18 | 19 | class riscv_custom_instr extends riscv_instr; 20 | 21 | // TODO: Add custom operands here, example: 22 | // rand riscv_reg_t rs3; 23 | 24 | `uvm_object_utils(riscv_custom_instr) 25 | `uvm_object_new 26 | 27 | virtual function string get_instr_name(); 28 | get_instr_name = instr_name.name(); 29 | // TODO: Add custom instruction name encoding here 30 | return get_instr_name; 31 | endfunction : get_instr_name 32 | 33 | // Convert the instruction to assembly code 34 | virtual function string convert2asm(string prefix = ""); 35 | string asm_str; 36 | asm_str = format_string("nop", MAX_INSTR_STR_LEN); 37 | /* TODO: Convert custom instruction to assembly format. Example: 38 | asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); 39 | case (instr_name) 40 | CUSTOM_1: asm_str = $sformatf("%0s %0s, (%0s)", asm_str, rd.name(), rs1.name()); 41 | CUSTOM_2: asm_str = $sformatf("%0s %0s", asm_str, r3.name()); 42 | endcase 43 | */ 44 | comment = {get_instr_name(), " ", comment}; 45 | if (comment != "") begin 46 | asm_str = {asm_str, " #",comment}; 47 | end 48 | return asm_str.tolower(); 49 | endfunction : convert2asm 50 | 51 | endclass : riscv_custom_instr 52 | -------------------------------------------------------------------------------- /src/isa/custom/riscv_custom_instr_enum.sv: -------------------------------------------------------------------------------- 1 | // TODO: Add custom instruction name enum 2 | CUSTOM_1, 3 | -------------------------------------------------------------------------------- /src/isa/custom/rv32x_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | // TODO: Add custom RV32X instruction. Example: 18 | `DEFINE_CUSTOM_INSTR(CUSTOM_1, R_FORMAT, ARITHMETIC, RV32X) 19 | -------------------------------------------------------------------------------- /src/isa/custom/rv64x_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | // TODO: Add custom RV32X instruction. Example: 18 | // `DEFINE_CUSTOM_INSTR(CUSTOM1, R_FORMAT, LOAD, RV64X) 19 | -------------------------------------------------------------------------------- /src/isa/riscv_zbc_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | class riscv_zbc_instr extends riscv_instr; 18 | `uvm_object_utils(riscv_zbc_instr) 19 | 20 | function new(string name = ""); 21 | super.new(name); 22 | endfunction : new 23 | 24 | function void pre_randomize(); 25 | super.pre_randomize(); 26 | endfunction : pre_randomize 27 | 28 | function bit[6:0] get_opcode(); 29 | case (instr_name) inside 30 | CLMUL, 31 | CLMULH, 32 | CLMULR : get_opcode = 7'b011_0011; 33 | default : get_opcode = super.get_opcode(); 34 | endcase 35 | endfunction : get_opcode 36 | 37 | function bit [2:0] get_func3(); 38 | case (instr_name) inside 39 | CLMUL : get_func3 = 3'b001; 40 | CLMULH : get_func3 = 3'b011; 41 | CLMULR : get_func3 = 3'b010; 42 | default : get_func3 = super.get_func3(); 43 | endcase 44 | endfunction : get_func3 45 | 46 | function bit [6:0] get_func7(); 47 | case (instr_name) inside 48 | CLMUL : get_func7 = 7'b000_0101; 49 | CLMULH : get_func7 = 7'b000_0101; 50 | CLMULR : get_func7 = 7'b000_0101; 51 | default : get_func7 = super.get_func7(); 52 | endcase 53 | endfunction : get_func7 54 | 55 | virtual function string convert2bin(string prefix = ""); 56 | string binary = ""; 57 | if (instr_name inside {CLMUL, CLMULH, CLMULR}) begin 58 | binary = $sformatf("%8h", {get_func7(), rs2, rs1, get_func3(), rd, get_opcode()}); 59 | end 60 | else begin 61 | binary = super.convert2bin(prefix); 62 | end 63 | endfunction : convert2bin 64 | 65 | virtual function bit is_supported(riscv_instr_gen_config cfg); 66 | return (cfg.enable_zbc_extension && 67 | (RV32ZBC inside { supported_isa } || RV64ZBC inside { supported_isa }) && 68 | instr_name inside { 69 | CLMUL, CLMULH, CLMULR 70 | }); 71 | endfunction : is_supported 72 | 73 | endclass : riscv_zbc_instr 74 | -------------------------------------------------------------------------------- /src/isa/rv128c_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_C_INSTR(C_SRLI64, CB_FORMAT, SHIFT, RV128C, NZUIMM) 18 | `DEFINE_C_INSTR(C_SRAI64, CB_FORMAT, SHIFT, RV128C, NZUIMM) 19 | `DEFINE_C_INSTR(C_SLLI64, CI_FORMAT, SHIFT, RV128C, NZUIMM) 20 | `DEFINE_C_INSTR(C_LQ, CL_FORMAT, LOAD, RV32DC, UIMM) 21 | `DEFINE_C_INSTR(C_SQ, CS_FORMAT, STORE, RV32DC, UIMM) 22 | `DEFINE_C_INSTR(C_LQSP, CI_FORMAT, LOAD, RV32DC, UIMM) 23 | `DEFINE_C_INSTR(C_SQSP, CSS_FORMAT, STORE, RV32DC, UIMM) 24 | -------------------------------------------------------------------------------- /src/isa/rv32a_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_AMO_INSTR(LR_W, R_FORMAT, LOAD, RV32A) 18 | `DEFINE_AMO_INSTR(SC_W, R_FORMAT, STORE, RV32A) 19 | `DEFINE_AMO_INSTR(AMOSWAP_W, R_FORMAT, AMO, RV32A) 20 | `DEFINE_AMO_INSTR(AMOADD_W, R_FORMAT, AMO, RV32A) 21 | `DEFINE_AMO_INSTR(AMOAND_W, R_FORMAT, AMO, RV32A) 22 | `DEFINE_AMO_INSTR(AMOOR_W, R_FORMAT, AMO, RV32A) 23 | `DEFINE_AMO_INSTR(AMOXOR_W, R_FORMAT, AMO, RV32A) 24 | `DEFINE_AMO_INSTR(AMOMIN_W, R_FORMAT, AMO, RV32A) 25 | `DEFINE_AMO_INSTR(AMOMAX_W, R_FORMAT, AMO, RV32A) 26 | `DEFINE_AMO_INSTR(AMOMINU_W, R_FORMAT, AMO, RV32A) 27 | `DEFINE_AMO_INSTR(AMOMAXU_W, R_FORMAT, AMO, RV32A) 28 | -------------------------------------------------------------------------------- /src/isa/rv32c_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_C_INSTR(C_LW, CL_FORMAT, LOAD, RV32C, UIMM) 18 | `DEFINE_C_INSTR(C_SW, CS_FORMAT, STORE, RV32C, UIMM) 19 | `DEFINE_C_INSTR(C_LWSP, CI_FORMAT, LOAD, RV32C, UIMM) 20 | `DEFINE_C_INSTR(C_SWSP, CSS_FORMAT, STORE, RV32C, UIMM) 21 | `DEFINE_C_INSTR(C_ADDI4SPN, CIW_FORMAT, ARITHMETIC, RV32C, NZUIMM) 22 | `DEFINE_C_INSTR(C_ADDI, CI_FORMAT, ARITHMETIC, RV32C, NZIMM) 23 | `DEFINE_C_INSTR(C_ADDI16SP, CI_FORMAT, ARITHMETIC, RV32C, NZIMM) 24 | `DEFINE_C_INSTR(C_LI, CI_FORMAT, ARITHMETIC, RV32C) 25 | `DEFINE_C_INSTR(C_LUI, CI_FORMAT, ARITHMETIC, RV32C, NZIMM) 26 | `DEFINE_C_INSTR(C_SUB, CA_FORMAT, ARITHMETIC, RV32C) 27 | `DEFINE_C_INSTR(C_ADD, CR_FORMAT, ARITHMETIC, RV32C) 28 | `DEFINE_C_INSTR(C_NOP, CI_FORMAT, ARITHMETIC, RV32C) 29 | `DEFINE_C_INSTR(C_MV, CR_FORMAT, ARITHMETIC, RV32C) 30 | `DEFINE_C_INSTR(C_ANDI, CB_FORMAT, LOGICAL, RV32C) 31 | `DEFINE_C_INSTR(C_XOR, CA_FORMAT, LOGICAL, RV32C) 32 | `DEFINE_C_INSTR(C_OR, CA_FORMAT, LOGICAL, RV32C) 33 | `DEFINE_C_INSTR(C_AND, CA_FORMAT, LOGICAL, RV32C) 34 | `DEFINE_C_INSTR(C_BEQZ, CB_FORMAT, BRANCH, RV32C) 35 | `DEFINE_C_INSTR(C_BNEZ, CB_FORMAT, BRANCH, RV32C) 36 | `DEFINE_C_INSTR(C_SRLI, CB_FORMAT, SHIFT, RV32C, NZUIMM) 37 | `DEFINE_C_INSTR(C_SRAI, CB_FORMAT, SHIFT, RV32C, NZUIMM) 38 | `DEFINE_C_INSTR(C_SLLI, CI_FORMAT, SHIFT, RV32C, NZUIMM) 39 | `DEFINE_C_INSTR(C_J, CJ_FORMAT, JUMP, RV32C) 40 | `DEFINE_C_INSTR(C_JAL, CJ_FORMAT, JUMP, RV32C) 41 | `DEFINE_C_INSTR(C_JR, CR_FORMAT, JUMP, RV32C) 42 | `DEFINE_C_INSTR(C_JALR, CR_FORMAT, JUMP, RV32C) 43 | `DEFINE_C_INSTR(C_EBREAK, CI_FORMAT, SYSTEM, RV32C) 44 | -------------------------------------------------------------------------------- /src/isa/rv32d_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_FP_INSTR(FLD, I_FORMAT, LOAD, RV32D) 18 | `DEFINE_FP_INSTR(FSD, S_FORMAT, STORE, RV32D) 19 | `DEFINE_FP_INSTR(FMADD_D, R4_FORMAT, ARITHMETIC, RV32D) 20 | `DEFINE_FP_INSTR(FMSUB_D, R4_FORMAT, ARITHMETIC, RV32D) 21 | `DEFINE_FP_INSTR(FNMSUB_D, R4_FORMAT, ARITHMETIC, RV32D) 22 | `DEFINE_FP_INSTR(FNMADD_D, R4_FORMAT, ARITHMETIC, RV32D) 23 | `DEFINE_FP_INSTR(FADD_D, R_FORMAT, ARITHMETIC, RV32D) 24 | `DEFINE_FP_INSTR(FSUB_D, R_FORMAT, ARITHMETIC, RV32D) 25 | `DEFINE_FP_INSTR(FMUL_D, R_FORMAT, ARITHMETIC, RV32D) 26 | `DEFINE_FP_INSTR(FDIV_D, R_FORMAT, ARITHMETIC, RV32D) 27 | `DEFINE_FP_INSTR(FSQRT_D, I_FORMAT, ARITHMETIC, RV32D) 28 | `DEFINE_FP_INSTR(FSGNJ_D, R_FORMAT, ARITHMETIC, RV32D) 29 | `DEFINE_FP_INSTR(FSGNJN_D, R_FORMAT, ARITHMETIC, RV32D) 30 | `DEFINE_FP_INSTR(FSGNJX_D, R_FORMAT, ARITHMETIC, RV32D) 31 | `DEFINE_FP_INSTR(FMIN_D, R_FORMAT, ARITHMETIC, RV32D) 32 | `DEFINE_FP_INSTR(FMAX_D, R_FORMAT, ARITHMETIC, RV32D) 33 | `DEFINE_FP_INSTR(FCVT_S_D, I_FORMAT, ARITHMETIC, RV32D) 34 | `DEFINE_FP_INSTR(FCVT_D_S, I_FORMAT, ARITHMETIC, RV32D) 35 | `DEFINE_FP_INSTR(FEQ_D, R_FORMAT, COMPARE, RV32D) 36 | `DEFINE_FP_INSTR(FLT_D, R_FORMAT, COMPARE, RV32D) 37 | `DEFINE_FP_INSTR(FLE_D, R_FORMAT, COMPARE, RV32D) 38 | `DEFINE_FP_INSTR(FCLASS_D, R_FORMAT, ARITHMETIC, RV32D) 39 | `DEFINE_FP_INSTR(FCVT_W_D, I_FORMAT, ARITHMETIC, RV32D) 40 | `DEFINE_FP_INSTR(FCVT_WU_D, I_FORMAT, ARITHMETIC, RV32D) 41 | `DEFINE_FP_INSTR(FCVT_D_W, I_FORMAT, ARITHMETIC, RV32D) 42 | `DEFINE_FP_INSTR(FCVT_D_WU, I_FORMAT, ARITHMETIC, RV32D) 43 | -------------------------------------------------------------------------------- /src/isa/rv32dc_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_FC_INSTR(C_FLD, CL_FORMAT, LOAD, RV32DC, UIMM) 18 | `DEFINE_FC_INSTR(C_FSD, CS_FORMAT, STORE, RV32DC, UIMM) 19 | `DEFINE_FC_INSTR(C_FLDSP, CI_FORMAT, LOAD, RV32DC, UIMM) 20 | `DEFINE_FC_INSTR(C_FSDSP, CSS_FORMAT, STORE, RV32DC, UIMM) 21 | -------------------------------------------------------------------------------- /src/isa/rv32f_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_FP_INSTR(FLW, I_FORMAT, LOAD, RV32F) 18 | `DEFINE_FP_INSTR(FSW, S_FORMAT, STORE, RV32F) 19 | `DEFINE_FP_INSTR(FMADD_S, R4_FORMAT, ARITHMETIC, RV32F) 20 | `DEFINE_FP_INSTR(FMSUB_S, R4_FORMAT, ARITHMETIC, RV32F) 21 | `DEFINE_FP_INSTR(FNMSUB_S, R4_FORMAT, ARITHMETIC, RV32F) 22 | `DEFINE_FP_INSTR(FNMADD_S, R4_FORMAT, ARITHMETIC, RV32F) 23 | `DEFINE_FP_INSTR(FADD_S, R_FORMAT, ARITHMETIC, RV32F) 24 | `DEFINE_FP_INSTR(FSUB_S, R_FORMAT, ARITHMETIC, RV32F) 25 | `DEFINE_FP_INSTR(FMUL_S, R_FORMAT, ARITHMETIC, RV32F) 26 | `DEFINE_FP_INSTR(FDIV_S, R_FORMAT, ARITHMETIC, RV32F) 27 | `DEFINE_FP_INSTR(FSQRT_S, I_FORMAT, ARITHMETIC, RV32F) 28 | `DEFINE_FP_INSTR(FSGNJ_S, R_FORMAT, ARITHMETIC, RV32F) 29 | `DEFINE_FP_INSTR(FSGNJN_S, R_FORMAT, ARITHMETIC, RV32F) 30 | `DEFINE_FP_INSTR(FSGNJX_S, R_FORMAT, ARITHMETIC, RV32F) 31 | `DEFINE_FP_INSTR(FMIN_S, R_FORMAT, ARITHMETIC, RV32F) 32 | `DEFINE_FP_INSTR(FMAX_S, R_FORMAT, ARITHMETIC, RV32F) 33 | `DEFINE_FP_INSTR(FCVT_W_S, I_FORMAT, ARITHMETIC, RV32F) 34 | `DEFINE_FP_INSTR(FCVT_WU_S, I_FORMAT, ARITHMETIC, RV32F) 35 | `DEFINE_FP_INSTR(FMV_X_W, I_FORMAT, ARITHMETIC, RV32F) 36 | `DEFINE_FP_INSTR(FEQ_S, R_FORMAT, COMPARE, RV32F) 37 | `DEFINE_FP_INSTR(FLT_S, R_FORMAT, COMPARE, RV32F) 38 | `DEFINE_FP_INSTR(FLE_S, R_FORMAT, COMPARE, RV32F) 39 | `DEFINE_FP_INSTR(FCLASS_S, R_FORMAT, ARITHMETIC, RV32F) 40 | `DEFINE_FP_INSTR(FCVT_S_W, I_FORMAT, ARITHMETIC, RV32F) 41 | `DEFINE_FP_INSTR(FCVT_S_WU, I_FORMAT, ARITHMETIC, RV32F) 42 | `DEFINE_FP_INSTR(FMV_W_X, I_FORMAT, ARITHMETIC, RV32F) 43 | -------------------------------------------------------------------------------- /src/isa/rv32fc_instr.sv: -------------------------------------------------------------------------------- 1 | `DEFINE_FC_INSTR(C_FLW, CL_FORMAT, LOAD, RV32FC, UIMM) 2 | `DEFINE_FC_INSTR(C_FSW, CS_FORMAT, STORE, RV32FC, UIMM) 3 | `DEFINE_FC_INSTR(C_FLWSP, CI_FORMAT, LOAD, RV32FC, UIMM) 4 | `DEFINE_FC_INSTR(C_FSWSP, CSS_FORMAT, STORE, RV32FC, UIMM) 5 | -------------------------------------------------------------------------------- /src/isa/rv32m_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | //////////// RV32M instructions ////////////// 18 | `DEFINE_INSTR(MUL, R_FORMAT, ARITHMETIC, RV32M) 19 | `DEFINE_INSTR(MULH, R_FORMAT, ARITHMETIC, RV32M) 20 | `DEFINE_INSTR(MULHSU, R_FORMAT, ARITHMETIC, RV32M) 21 | `DEFINE_INSTR(MULHU, R_FORMAT, ARITHMETIC, RV32M) 22 | `DEFINE_INSTR(DIV, R_FORMAT, ARITHMETIC, RV32M) 23 | `DEFINE_INSTR(DIVU, R_FORMAT, ARITHMETIC, RV32M) 24 | `DEFINE_INSTR(REM, R_FORMAT, ARITHMETIC, RV32M) 25 | `DEFINE_INSTR(REMU, R_FORMAT, ARITHMETIC, RV32M) 26 | -------------------------------------------------------------------------------- /src/isa/rv32zba_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | `DEFINE_ZBA_INSTR(SH1ADD, R_FORMAT, ARITHMETIC, RV32ZBA); 19 | `DEFINE_ZBA_INSTR(SH2ADD, R_FORMAT, ARITHMETIC, RV32ZBA); 20 | `DEFINE_ZBA_INSTR(SH3ADD, R_FORMAT, ARITHMETIC, RV32ZBA); 21 | -------------------------------------------------------------------------------- /src/isa/rv32zbb_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | `DEFINE_ZBB_INSTR(ANDN, R_FORMAT, LOGICAL, RV32ZBB); 19 | `DEFINE_ZBB_INSTR(CLZ, I_FORMAT, ARITHMETIC, RV32ZBB); 20 | `DEFINE_ZBB_INSTR(CPOP, I_FORMAT, ARITHMETIC, RV32ZBB); 21 | `DEFINE_ZBB_INSTR(CTZ, I_FORMAT, ARITHMETIC, RV32ZBB); 22 | `DEFINE_ZBB_INSTR(MAX, R_FORMAT, ARITHMETIC, RV32ZBB); 23 | `DEFINE_ZBB_INSTR(MAXU, R_FORMAT, ARITHMETIC, RV32ZBB); 24 | `DEFINE_ZBB_INSTR(MIN, R_FORMAT, ARITHMETIC, RV32ZBB); 25 | `DEFINE_ZBB_INSTR(MINU, R_FORMAT, ARITHMETIC, RV32ZBB); 26 | `DEFINE_ZBB_INSTR(ORC_B, I_FORMAT, LOGICAL, RV32ZBB); 27 | `DEFINE_ZBB_INSTR(ORN, R_FORMAT, LOGICAL, RV32ZBB); 28 | `DEFINE_ZBB_INSTR(REV8, I_FORMAT, SHIFT, RV32ZBB); 29 | `DEFINE_ZBB_INSTR(ROL, R_FORMAT, SHIFT, RV32ZBB); 30 | `DEFINE_ZBB_INSTR(ROR, R_FORMAT, SHIFT, RV32ZBB); 31 | `DEFINE_ZBB_INSTR(RORI, I_FORMAT, SHIFT, RV32ZBB, UIMM); 32 | `DEFINE_ZBB_INSTR(SEXT_B, I_FORMAT, ARITHMETIC, RV32ZBB); 33 | `DEFINE_ZBB_INSTR(SEXT_H, I_FORMAT, ARITHMETIC, RV32ZBB); 34 | `DEFINE_ZBB_INSTR(XNOR, R_FORMAT, LOGICAL, RV32ZBB); 35 | `DEFINE_ZBB_INSTR(ZEXT_H, R_FORMAT, ARITHMETIC, RV32ZBB); 36 | -------------------------------------------------------------------------------- /src/isa/rv32zbc_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | `DEFINE_ZBC_INSTR(CLMUL, R_FORMAT, ARITHMETIC, RV32ZBC) 19 | `DEFINE_ZBC_INSTR(CLMULH, R_FORMAT, ARITHMETIC, RV32ZBC) 20 | `DEFINE_ZBC_INSTR(CLMULR, R_FORMAT, ARITHMETIC, RV32ZBC) 21 | -------------------------------------------------------------------------------- /src/isa/rv32zbs_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | `DEFINE_ZBS_INSTR(BCLR, R_FORMAT, SHIFT, RV32ZBS) 19 | `DEFINE_ZBS_INSTR(BCLRI, I_FORMAT, SHIFT, RV32ZBS, UIMM) 20 | `DEFINE_ZBS_INSTR(BEXT, R_FORMAT, SHIFT, RV32ZBS) 21 | `DEFINE_ZBS_INSTR(BEXTI, I_FORMAT, SHIFT, RV32ZBS, UIMM) 22 | `DEFINE_ZBS_INSTR(BINV, R_FORMAT, SHIFT, RV32ZBS) 23 | `DEFINE_ZBS_INSTR(BINVI, I_FORMAT, SHIFT, RV32ZBS, UIMM) 24 | `DEFINE_ZBS_INSTR(BSET, R_FORMAT, SHIFT, RV32ZBS) 25 | `DEFINE_ZBS_INSTR(BSETI, I_FORMAT, SHIFT, RV32ZBS, UIMM) 26 | -------------------------------------------------------------------------------- /src/isa/rv64a_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_AMO_INSTR(LR_D, R_FORMAT, LOAD, RV64A) 18 | `DEFINE_AMO_INSTR(SC_D, R_FORMAT, STORE, RV64A) 19 | `DEFINE_AMO_INSTR(AMOSWAP_D, R_FORMAT, AMO, RV64A) 20 | `DEFINE_AMO_INSTR(AMOADD_D, R_FORMAT, AMO, RV64A) 21 | `DEFINE_AMO_INSTR(AMOAND_D, R_FORMAT, AMO, RV64A) 22 | `DEFINE_AMO_INSTR(AMOOR_D, R_FORMAT, AMO, RV64A) 23 | `DEFINE_AMO_INSTR(AMOXOR_D, R_FORMAT, AMO, RV64A) 24 | `DEFINE_AMO_INSTR(AMOMIN_D, R_FORMAT, AMO, RV64A) 25 | `DEFINE_AMO_INSTR(AMOMAX_D, R_FORMAT, AMO, RV64A) 26 | `DEFINE_AMO_INSTR(AMOMINU_D, R_FORMAT, AMO, RV64A) 27 | `DEFINE_AMO_INSTR(AMOMAXU_D, R_FORMAT, AMO, RV64A) 28 | -------------------------------------------------------------------------------- /src/isa/rv64b_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2019 Google LLC 3 | * Copyright 2019 Mellanox Technologies Ltd 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). 19 | 20 | // ARITHMETIC intructions 21 | `DEFINE_B_INSTR(BMATOR, R_FORMAT, ARITHMETIC, RV64B) 22 | `DEFINE_B_INSTR(BMATXOR, R_FORMAT, ARITHMETIC, RV64B) 23 | `DEFINE_B_INSTR(BMATFLIP, R_FORMAT, ARITHMETIC, RV64B) 24 | `DEFINE_B_INSTR(CRC32_D, R_FORMAT, ARITHMETIC, RV64B) 25 | `DEFINE_B_INSTR(CRC32C_D, R_FORMAT, ARITHMETIC, RV64B) 26 | `DEFINE_B_INSTR(SHFLW, R_FORMAT, ARITHMETIC, RV64B) 27 | `DEFINE_B_INSTR(UNSHFLW, R_FORMAT, ARITHMETIC, RV64B) 28 | `DEFINE_B_INSTR(BCOMPRESSW, R_FORMAT, ARITHMETIC, RV64B) 29 | `DEFINE_B_INSTR(BDECOMPRESSW, R_FORMAT, ARITHMETIC, RV64B) 30 | `DEFINE_B_INSTR(BFPW, R_FORMAT, ARITHMETIC, RV64B) 31 | // SHIFT intructions 32 | `DEFINE_B_INSTR(SLOW, R_FORMAT, SHIFT, RV64B) 33 | `DEFINE_B_INSTR(SROW, R_FORMAT, SHIFT, RV64B) 34 | `DEFINE_B_INSTR(SLOIW, I_FORMAT, SHIFT, RV64B, UIMM) 35 | `DEFINE_B_INSTR(SROIW, I_FORMAT, SHIFT, RV64B, UIMM) 36 | `DEFINE_B_INSTR(GREVW, R_FORMAT, SHIFT, RV64B) 37 | `DEFINE_B_INSTR(GREVIW, I_FORMAT, SHIFT, RV64B, UIMM) 38 | `DEFINE_B_INSTR(FSLW, R4_FORMAT, SHIFT, RV64B) 39 | `DEFINE_B_INSTR(FSRW, R4_FORMAT, SHIFT, RV64B) 40 | `DEFINE_B_INSTR(FSRIW, I_FORMAT, SHIFT, RV64B, UIMM) 41 | // LOGICAL instructions 42 | `DEFINE_B_INSTR(GORCW, R_FORMAT, LOGICAL, RV64B) 43 | `DEFINE_B_INSTR(GORCIW, I_FORMAT, LOGICAL, RV64B, UIMM) 44 | `DEFINE_B_INSTR(PACKW, R_FORMAT, LOGICAL, RV64B) 45 | `DEFINE_B_INSTR(PACKUW, R_FORMAT, LOGICAL, RV64B) 46 | `DEFINE_B_INSTR(XPERM_W, R_FORMAT, LOGICAL, RV64B) 47 | -------------------------------------------------------------------------------- /src/isa/rv64c_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_C_INSTR(C_ADDIW, CI_FORMAT, ARITHMETIC, RV64C) 18 | `DEFINE_C_INSTR(C_SUBW, CA_FORMAT, ARITHMETIC, RV64C) 19 | `DEFINE_C_INSTR(C_ADDW, CA_FORMAT, ARITHMETIC, RV64C) 20 | `DEFINE_C_INSTR(C_LD, CL_FORMAT, LOAD, RV64C, UIMM) 21 | `DEFINE_C_INSTR(C_SD, CS_FORMAT, STORE, RV64C, UIMM) 22 | `DEFINE_C_INSTR(C_LDSP, CI_FORMAT, LOAD, RV64C, UIMM) 23 | `DEFINE_C_INSTR(C_SDSP, CSS_FORMAT, STORE, RV64C, UIMM) 24 | -------------------------------------------------------------------------------- /src/isa/rv64d_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_FP_INSTR(FMV_X_D, I_FORMAT, ARITHMETIC, RV64D) 18 | `DEFINE_FP_INSTR(FMV_D_X, I_FORMAT, ARITHMETIC, RV64D) 19 | `DEFINE_FP_INSTR(FCVT_L_D, I_FORMAT, ARITHMETIC, RV64D) 20 | `DEFINE_FP_INSTR(FCVT_LU_D, I_FORMAT, ARITHMETIC, RV64D) 21 | `DEFINE_FP_INSTR(FCVT_D_L, I_FORMAT, ARITHMETIC, RV64D) 22 | `DEFINE_FP_INSTR(FCVT_D_LU, I_FORMAT, ARITHMETIC, RV64D) 23 | -------------------------------------------------------------------------------- /src/isa/rv64f_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_FP_INSTR(FCVT_L_S, I_FORMAT, ARITHMETIC, RV64F) 18 | `DEFINE_FP_INSTR(FCVT_LU_S, I_FORMAT, ARITHMETIC, RV64F) 19 | `DEFINE_FP_INSTR(FCVT_S_L, I_FORMAT, ARITHMETIC, RV64F) 20 | `DEFINE_FP_INSTR(FCVT_S_LU, I_FORMAT, ARITHMETIC, RV64F) 21 | -------------------------------------------------------------------------------- /src/isa/rv64i_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_INSTR(LWU, I_FORMAT, LOAD, RV64I) 18 | `DEFINE_INSTR(LD, I_FORMAT, LOAD, RV64I) 19 | `DEFINE_INSTR(SD, S_FORMAT, STORE, RV64I) 20 | // SHIFT intructions 21 | `DEFINE_INSTR(SLLW, R_FORMAT, SHIFT, RV64I) 22 | `DEFINE_INSTR(SLLIW, I_FORMAT, SHIFT, RV64I) 23 | `DEFINE_INSTR(SRLW, R_FORMAT, SHIFT, RV64I) 24 | `DEFINE_INSTR(SRLIW, I_FORMAT, SHIFT, RV64I) 25 | `DEFINE_INSTR(SRAW, R_FORMAT, SHIFT, RV64I) 26 | `DEFINE_INSTR(SRAIW, I_FORMAT, SHIFT, RV64I) 27 | // ARITHMETIC intructions 28 | `DEFINE_INSTR(ADDW, R_FORMAT, ARITHMETIC, RV64I) 29 | `DEFINE_INSTR(ADDIW, I_FORMAT, ARITHMETIC, RV64I) 30 | `DEFINE_INSTR(SUBW, R_FORMAT, ARITHMETIC, RV64I) 31 | -------------------------------------------------------------------------------- /src/isa/rv64m_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | `DEFINE_INSTR(MULW, R_FORMAT, ARITHMETIC, RV64M) 18 | `DEFINE_INSTR(DIVW, R_FORMAT, ARITHMETIC, RV64M) 19 | `DEFINE_INSTR(DIVUW, R_FORMAT, ARITHMETIC, RV64M) 20 | `DEFINE_INSTR(REMW, R_FORMAT, ARITHMETIC, RV64M) 21 | `DEFINE_INSTR(REMUW, R_FORMAT, ARITHMETIC, RV64M) 22 | -------------------------------------------------------------------------------- /src/isa/rv64zba_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | `DEFINE_ZBA_INSTR(ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); 19 | `DEFINE_ZBA_INSTR(SH1ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); 20 | `DEFINE_ZBA_INSTR(SH2ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); 21 | `DEFINE_ZBA_INSTR(SH3ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); 22 | `DEFINE_ZBA_INSTR(SLLI_UW, I_FORMAT, SHIFT, RV64ZBA, UIMM); 23 | -------------------------------------------------------------------------------- /src/isa/rv64zbb_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * Copyright 2021 Silicon Labs, Inc. 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | `DEFINE_ZBB_INSTR(CLZW, I_FORMAT, ARITHMETIC, RV64ZBB); 19 | `DEFINE_ZBB_INSTR(CPOPW, I_FORMAT, ARITHMETIC, RV64ZBB); 20 | `DEFINE_ZBB_INSTR(CTZW, I_FORMAT, ARITHMETIC, RV64ZBB); 21 | `DEFINE_ZBB_INSTR(ROLW, R_FORMAT, SHIFT, RV64ZBB); 22 | `DEFINE_ZBB_INSTR(RORW, R_FORMAT, SHIFT, RV64ZBB); 23 | `DEFINE_ZBB_INSTR(RORIW, I_FORMAT, SHIFT, RV64ZBB, UIMM); 24 | -------------------------------------------------------------------------------- /src/riscv_pseudo_instr.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2019 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | // Psuedo instructions are used to simplify assembly program writing 18 | class riscv_pseudo_instr extends riscv_instr; 19 | 20 | rand riscv_pseudo_instr_name_t pseudo_instr_name; 21 | 22 | `add_pseudo_instr(LI, I_FORMAT, LOAD, RV32I) 23 | `add_pseudo_instr(LA, I_FORMAT, LOAD, RV32I) 24 | 25 | `uvm_object_utils(riscv_pseudo_instr) 26 | 27 | function new(string name = ""); 28 | super.new(name); 29 | process_load_store = 0; 30 | this.format = I_FORMAT; 31 | endfunction 32 | 33 | // Convert the instruction to assembly code 34 | virtual function string convert2asm(string prefix = ""); 35 | string asm_str; 36 | asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); 37 | // instr rd,imm 38 | asm_str = $sformatf("%0s%0s, %0s", asm_str, rd.name(), get_imm()); 39 | if(comment != "") 40 | asm_str = {asm_str, " #",comment}; 41 | return asm_str.tolower(); 42 | endfunction 43 | 44 | virtual function string get_instr_name(); 45 | return pseudo_instr_name.name(); 46 | endfunction 47 | 48 | endclass 49 | -------------------------------------------------------------------------------- /src/riscv_signature_pkg.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2019 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | package riscv_signature_pkg; 18 | 19 | // Will be the lowest 8 bits of the data word 20 | typedef enum bit[7:0] { 21 | // Information sent to the core relating its current status. 22 | // Bits [12:8] of the data word will be the core_status_t value 23 | // corresponding to the current core status. 24 | CORE_STATUS, 25 | // Information sent to the core conveying the uvm simulation result. 26 | // Bit [8] of the data word will be the test_result_t value. 27 | TEST_RESULT, 28 | // Sent to the core to indicate a dump of GPRs to testbench. 29 | // Will be followed by 32 writes of registers x0-x32. 30 | WRITE_GPR, 31 | // Sent to the core to indicate a write of a CSR's data. 32 | // Bits [19:8] of the data word will be the CSR address. 33 | // Will be followed by a second write of the actual data from the CSR. 34 | WRITE_CSR 35 | } signature_type_t; 36 | 37 | typedef enum bit[4:0] { 38 | INITIALIZED, 39 | IN_DEBUG_MODE, 40 | IN_MACHINE_MODE, 41 | IN_HYPERVISOR_MODE, 42 | IN_SUPERVISOR_MODE, 43 | IN_USER_MODE, 44 | HANDLING_IRQ, 45 | FINISHED_IRQ, 46 | HANDLING_EXCEPTION, 47 | INSTR_FAULT_EXCEPTION, 48 | ILLEGAL_INSTR_EXCEPTION, 49 | LOAD_FAULT_EXCEPTION, 50 | STORE_FAULT_EXCEPTION, 51 | EBREAK_EXCEPTION 52 | } core_status_t; 53 | 54 | typedef enum bit { 55 | TEST_PASS, 56 | TEST_FAIL 57 | } test_result_t; 58 | 59 | endpackage 60 | -------------------------------------------------------------------------------- /target/ml/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64I 3 | --override riscvOVPsim/cpu/add_Extensions=MC 4 | --override riscvOVPsim/cpu/misa_MXL=2 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/multi_harts/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MCA 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv32i/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/misa_MXL=1 4 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 5 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/unaligned=T 7 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 8 | --override riscvOVPsim/cpu/user_version=2.3 9 | --override riscvOVPsim/cpu/priv_version=1.11 10 | --override riscvOVPsim/cpu/mvendorid=0 11 | --override riscvOVPsim/cpu/marchid=0 12 | --override riscvOVPsim/cpu/mimpid=0 13 | --override riscvOVPsim/cpu/mhartid=0 14 | --override riscvOVPsim/cpu/cycle_undefined=F 15 | --override riscvOVPsim/cpu/instret_undefined=F 16 | --override riscvOVPsim/cpu/time_undefined=T 17 | --override riscvOVPsim/cpu/reset_address=0x80000000 18 | --override riscvOVPsim/cpu/simulateexceptions=T 19 | --override riscvOVPsim/cpu/defaultsemihost=F 20 | --override riscvOVPsim/cpu/wfi_is_nop=T 21 | --exitonsymbol _exit 22 | -------------------------------------------------------------------------------- /target/rv32i/testlist.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # ================================================================================ 16 | # Regression test list format 17 | # -------------------------------------------------------------------------------- 18 | # test : Assembly test name 19 | # description : Description of this test 20 | # gen_opts : Instruction generator options 21 | # iterations : Number of iterations of this test 22 | # no_iss : Enable/disable ISS simulator (Optional) 23 | # gen_test : Test name used by the instruction generator 24 | # asm_tests : Path to directed, hand-coded assembly test file or directory 25 | # rtl_test : RTL simulation test name 26 | # cmp_opts : Compile options passed to the instruction generator 27 | # sim_opts : Simulation options passed to the instruction generator 28 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 29 | # compare_opts : Options for the RTL & ISS trace comparison 30 | # gcc_opts : gcc compile options 31 | # -------------------------------------------------------------------------------- 32 | 33 | - import: /yaml/base_testlist.yaml 34 | 35 | - test: riscv_misaligned_instr_test 36 | description: > 37 | Test misaligned instruction exception by JALR to an address with addr[0] = 1 38 | iterations: 2 39 | gen_test: riscv_instr_base_test 40 | gen_opts: > 41 | +instr_cnt=4000 42 | +num_of_sub_program=8 43 | +enable_misaligned_instr=1 44 | rtl_test: core_base_test 45 | -------------------------------------------------------------------------------- /target/rv32imc/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MC 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv32imc_sv32/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MC 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv32imc_sv32/testlist.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # ================================================================================ 16 | # Regression test list format 17 | # -------------------------------------------------------------------------------- 18 | # test : Assembly test name 19 | # description : Description of this test 20 | # gen_opts : Instruction generator options 21 | # iterations : Number of iterations of this test 22 | # no_iss : Enable/disable ISS simulator (Optional) 23 | # gen_test : Test name used by the instruction generator 24 | # asm_tests : Path to directed, hand-coded assembly test file or directory 25 | # rtl_test : RTL simulation test name 26 | # cmp_opts : Compile options passed to the instruction generator 27 | # sim_opts : Simulation options passed to the instruction generator 28 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 29 | # compare_opts : Options for the RTL & ISS trace comparison 30 | # gcc_opts : gcc compile options 31 | # -------------------------------------------------------------------------------- 32 | 33 | - import: /target/rv32imc/testlist.yaml 34 | 35 | - test: riscv_u_mode_rand_test 36 | description: > 37 | Random previliged mode test 38 | iterations: 2 39 | gen_test: riscv_instr_base_test 40 | gen_opts: > 41 | +instr_cnt=10000 42 | +num_of_sub_program=5 43 | +boot_mode=u 44 | rtl_test: core_base_test 45 | -------------------------------------------------------------------------------- /target/rv32imcb/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV32I 3 | --override riscvOVPsim/cpu/add_Extensions=MCB 4 | --override riscvOVPsim/cpu/misa_MXL=1 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv32imcb/testlist.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # ================================================================================ 16 | # Regression test list format 17 | # -------------------------------------------------------------------------------- 18 | # test : Assembly test name 19 | # description : Description of this test 20 | # gen_opts : Instruction generator options 21 | # iterations : Number of iterations of this test 22 | # no_iss : Enable/disable ISS simulator (Optional) 23 | # gen_test : Test name used by the instruction generator 24 | # asm_tests : Path to directed, hand-coded assembly test file or directory 25 | # rtl_test : RTL simulation test name 26 | # cmp_opts : Compile options passed to the instruction generator 27 | # sim_opts : Simulation options passed to the instruction generator 28 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 29 | # compare_opts : Options for the RTL & ISS trace comparison 30 | # gcc_opts : gcc compile options 31 | # -------------------------------------------------------------------------------- 32 | 33 | - import: /target/rv32imc/testlist.yaml 34 | 35 | - test: riscv_b_ext_test 36 | description: > 37 | Random instruction test with b extension 38 | iterations: 1 39 | gen_test: riscv_rand_instr_test 40 | gen_opts: > 41 | +enable_b_extension=1 42 | rtl_test: core_base_test 43 | 44 | - test: riscv_zbb_zbt_test 45 | description: > 46 | Random instruction test with zbb and zbt groups in b extension 47 | iterations: 1 48 | gen_test: riscv_rand_instr_test 49 | gen_opts: > 50 | +enable_b_extension=1 51 | +enable_bitmanip_groups=zbb,zbt 52 | rtl_test: core_base_test 53 | -------------------------------------------------------------------------------- /target/rv64gc/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64GC 3 | --override riscvOVPsim/cpu/misa_MXL=2 4 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 5 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/unaligned=T 7 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 8 | --override riscvOVPsim/cpu/user_version=2.3 9 | --override riscvOVPsim/cpu/priv_version=1.11 10 | --override riscvOVPsim/cpu/mvendorid=0 11 | --override riscvOVPsim/cpu/marchid=0 12 | --override riscvOVPsim/cpu/mimpid=0 13 | --override riscvOVPsim/cpu/mhartid=0 14 | --override riscvOVPsim/cpu/cycle_undefined=F 15 | --override riscvOVPsim/cpu/instret_undefined=F 16 | --override riscvOVPsim/cpu/time_undefined=T 17 | --override riscvOVPsim/cpu/reset_address=0x80000000 18 | --override riscvOVPsim/cpu/simulateexceptions=T 19 | --override riscvOVPsim/cpu/defaultsemihost=F 20 | --override riscvOVPsim/cpu/wfi_is_nop=T 21 | --exitonsymbol _exit 22 | -------------------------------------------------------------------------------- /target/rv64gcv/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64GCV 3 | --override riscvOVPsim/cpu/misa_MXL=2 4 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 5 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/unaligned=T 7 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 8 | --override riscvOVPsim/cpu/user_version=2.3 9 | --override riscvOVPsim/cpu/priv_version=1.11 10 | --override riscvOVPsim/cpu/vector_version=0.9 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv64imafdc/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64GC 3 | --override riscvOVPsim/cpu/misa_MXL=2 4 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 5 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/unaligned=T 7 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 8 | --override riscvOVPsim/cpu/user_version=2.3 9 | --override riscvOVPsim/cpu/priv_version=1.11 10 | --override riscvOVPsim/cpu/mvendorid=0 11 | --override riscvOVPsim/cpu/marchid=0 12 | --override riscvOVPsim/cpu/mimpid=0 13 | --override riscvOVPsim/cpu/mhartid=0 14 | --override riscvOVPsim/cpu/cycle_undefined=F 15 | --override riscvOVPsim/cpu/instret_undefined=F 16 | --override riscvOVPsim/cpu/time_undefined=T 17 | --override riscvOVPsim/cpu/reset_address=0x80000000 18 | --override riscvOVPsim/cpu/simulateexceptions=T 19 | --override riscvOVPsim/cpu/defaultsemihost=F 20 | --override riscvOVPsim/cpu/wfi_is_nop=T 21 | --exitonsymbol _exit 22 | -------------------------------------------------------------------------------- /target/rv64imc/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64I 3 | --override riscvOVPsim/cpu/add_Extensions=MC 4 | --override riscvOVPsim/cpu/misa_MXL=2 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv64imc/testlist.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # ================================================================================ 16 | # Regression test list format 17 | # -------------------------------------------------------------------------------- 18 | # test : Assembly test name 19 | # description : Description of this test 20 | # gen_opts : Instruction generator options 21 | # iterations : Number of iterations of this test 22 | # no_iss : Enable/disable ISS simulator (Optional) 23 | # gen_test : Test name used by the instruction generator 24 | # asm_tests : Path to directed, hand-coded assembly test file or directory 25 | # rtl_test : RTL simulation test name 26 | # cmp_opts : Compile options passed to the instruction generator 27 | # sim_opts : Simulation options passed to the instruction generator 28 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 29 | # compare_opts : Options for the RTL & ISS trace comparison 30 | # gcc_opts : gcc compile options 31 | # -------------------------------------------------------------------------------- 32 | 33 | - import: /target/rv32imc/testlist.yaml 34 | -------------------------------------------------------------------------------- /target/rv64imcb/riscvOVPsim.ic: -------------------------------------------------------------------------------- 1 | # riscOVPsim configuration file converted from YAML 2 | --variant RV64I 3 | --override riscvOVPsim/cpu/add_Extensions=MCB 4 | --override riscvOVPsim/cpu/misa_MXL=2 5 | --override riscvOVPsim/cpu/misa_MXL_mask=0x0 # 0 6 | --override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0 7 | --override riscvOVPsim/cpu/unaligned=T 8 | --override riscvOVPsim/cpu/mtvec_mask=0x0 # 0 9 | --override riscvOVPsim/cpu/user_version=2.3 10 | --override riscvOVPsim/cpu/priv_version=1.11 11 | --override riscvOVPsim/cpu/mvendorid=0 12 | --override riscvOVPsim/cpu/marchid=0 13 | --override riscvOVPsim/cpu/mimpid=0 14 | --override riscvOVPsim/cpu/mhartid=0 15 | --override riscvOVPsim/cpu/cycle_undefined=F 16 | --override riscvOVPsim/cpu/instret_undefined=F 17 | --override riscvOVPsim/cpu/time_undefined=T 18 | --override riscvOVPsim/cpu/reset_address=0x80000000 19 | --override riscvOVPsim/cpu/simulateexceptions=T 20 | --override riscvOVPsim/cpu/defaultsemihost=F 21 | --override riscvOVPsim/cpu/wfi_is_nop=T 22 | --exitonsymbol _exit 23 | -------------------------------------------------------------------------------- /target/rv64imcb/testlist.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # ================================================================================ 16 | # Regression test list format 17 | # -------------------------------------------------------------------------------- 18 | # test : Assembly test name 19 | # description : Description of this test 20 | # gen_opts : Instruction generator options 21 | # iterations : Number of iterations of this test 22 | # no_iss : Enable/disable ISS simulator (Optional) 23 | # gen_test : Test name used by the instruction generator 24 | # asm_tests : Path to directed, hand-coded assembly test file or directory 25 | # rtl_test : RTL simulation test name 26 | # cmp_opts : Compile options passed to the instruction generator 27 | # sim_opts : Simulation options passed to the instruction generator 28 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 29 | # compare_opts : Options for the RTL & ISS trace comparison 30 | # gcc_opts : gcc compile options 31 | # -------------------------------------------------------------------------------- 32 | 33 | - import: /target/rv32imcb/testlist.yaml 34 | -------------------------------------------------------------------------------- /test/riscv_instr_gen_tb_top.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | module riscv_instr_gen_tb_top; 18 | 19 | import uvm_pkg::*; 20 | import riscv_instr_test_pkg::*; 21 | 22 | initial begin 23 | run_test(); 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /test/riscv_instr_test.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2019 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | // Sanity test for riscv_instr_test class 18 | class riscv_instr_test extends riscv_instr_base_test; 19 | 20 | `uvm_component_utils(riscv_instr_test) 21 | `uvm_component_new 22 | 23 | task run_phase(uvm_phase phase); 24 | int fd; 25 | riscv_instr instr; 26 | riscv_instr_name_t instr_name; 27 | string test_name = $sformatf("%0s_0.S", asm_file_name); 28 | fd = $fopen(test_name,"w"); 29 | `uvm_info(`gfn, "Creating instruction list", UVM_LOW) 30 | riscv_instr::create_instr_list(cfg); 31 | riscv_csr_instr::create_csr_filter(cfg); 32 | `uvm_info(`gfn, "Randomizing instruction list now...", UVM_LOW) 33 | repeat (10000) begin 34 | instr = riscv_instr::get_rand_instr(); 35 | `DV_CHECK_RANDOMIZE_FATAL(instr); 36 | $fwrite(fd, {instr.convert2asm(),"\n"}); 37 | end 38 | repeat (10000) begin 39 | instr = riscv_instr::get_rand_instr(.include_category({LOAD, STORE})); 40 | `DV_CHECK_RANDOMIZE_FATAL(instr); 41 | $fwrite(fd, {instr.convert2asm(),"\n"}); 42 | end 43 | repeat (10000) begin 44 | instr = riscv_instr::get_rand_instr(.exclude_category({LOAD, STORE , BRANCH}), 45 | .include_group({RV32I, RV32M})); 46 | `DV_CHECK_RANDOMIZE_FATAL(instr); 47 | $fwrite(fd, {instr.convert2asm(),"\n"}); 48 | end 49 | $fclose(fd); 50 | `uvm_info(get_full_name(), $sformatf("%0s is generated", test_name), UVM_LOW) 51 | endtask 52 | 53 | virtual function void randomize_cfg(); 54 | `DV_CHECK_RANDOMIZE_FATAL(cfg); 55 | `uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s", 56 | cfg.sprint()), UVM_LOW) 57 | endfunction 58 | 59 | endclass 60 | -------------------------------------------------------------------------------- /test/riscv_instr_test_lib.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | 18 | class riscv_rand_instr_test extends riscv_instr_base_test; 19 | 20 | `uvm_component_utils(riscv_rand_instr_test) 21 | `uvm_component_new 22 | 23 | virtual function void randomize_cfg(); 24 | cfg.instr_cnt = 10000; 25 | cfg.num_of_sub_program = 5; 26 | `DV_CHECK_RANDOMIZE_FATAL(cfg) 27 | `uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s", 28 | cfg.sprint()), UVM_LOW) 29 | endfunction 30 | 31 | virtual function void apply_directed_instr(); 32 | // Mix below directed instruction streams with the random instructions 33 | asm_gen.add_directed_instr_stream("riscv_load_store_rand_instr_stream", 4); 34 | asm_gen.add_directed_instr_stream("riscv_loop_instr", 3); 35 | asm_gen.add_directed_instr_stream("riscv_jal_instr", 4); 36 | asm_gen.add_directed_instr_stream("riscv_hazard_instr_stream", 4); 37 | asm_gen.add_directed_instr_stream("riscv_load_store_hazard_instr_stream", 4); 38 | asm_gen.add_directed_instr_stream("riscv_multi_page_load_store_instr_stream", 4); 39 | asm_gen.add_directed_instr_stream("riscv_mem_region_stress_test", 4); 40 | endfunction 41 | 42 | endclass 43 | 44 | class riscv_ml_test extends riscv_instr_base_test; 45 | 46 | `uvm_component_utils(riscv_ml_test) 47 | `uvm_component_new 48 | 49 | virtual function void randomize_cfg(); 50 | cfg.addr_translaction_rnd_order_c.constraint_mode(0); 51 | `DV_CHECK_RANDOMIZE_FATAL(cfg) 52 | cfg.addr_translaction_rnd_order_c.constraint_mode(1); 53 | `uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s", 54 | cfg.sprint()), UVM_LOW) 55 | endfunction 56 | 57 | endclass 58 | -------------------------------------------------------------------------------- /test/riscv_instr_test_pkg.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 Google LLC 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | package riscv_instr_test_pkg; 18 | 19 | import uvm_pkg::*; 20 | import riscv_instr_pkg::*; 21 | 22 | `include "riscv_instr_base_test.sv" 23 | `include "riscv_instr_test_lib.sv" 24 | `include "riscv_instr_cov_test.sv" 25 | 26 | endpackage 27 | -------------------------------------------------------------------------------- /user_extension/user_define.h: -------------------------------------------------------------------------------- 1 | # Add user macros, routines in this file 2 | -------------------------------------------------------------------------------- /user_extension/user_extension.svh: -------------------------------------------------------------------------------- 1 | // Add your custom extensions, you can list all your local extended SV files here 2 | -------------------------------------------------------------------------------- /user_extension/user_init.s: -------------------------------------------------------------------------------- 1 | # Add custom initialization assembly code here 2 | # This file will be included at the very beginning of the program 3 | -------------------------------------------------------------------------------- /vcs.compile.option.f: -------------------------------------------------------------------------------- 1 | // Copyright 2018 Google LLC 2 | // 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | // 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | // 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | -sverilog 16 | -ntb_opts uvm-1.2 17 | -lca 18 | +define+UVM_REGEX_NO_DPI 19 | -timescale=1ns/10ps 20 | -------------------------------------------------------------------------------- /verilog_style/build-verible.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # Copyright 2019 Google LLC 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | VERIBLE_VERSION=751d4d8e57741ab22806f91982f59c71ecf37d9d 18 | INSTALL_DIR=/tools/verible 19 | 20 | # this requires the bazel build system and GCC7 21 | # see https://docs.bazel.build/versions/master/install-ubuntu.html 22 | 23 | echo "checking whether bazel is installed..." 24 | if which bazel; then 25 | echo "OK" 26 | else 27 | echo "bazel is not installed. installing bazel..." 28 | sudo apt install curl -y 29 | curl https://bazel.build/bazel-release.pub.gpg | sudo apt-key add - 30 | echo "deb [arch=amd64] https://storage.googleapis.com/bazel-apt stable jdk1.8" \ 31 | | sudo tee /etc/apt/sources.list.d/bazel.list 32 | sudo apt update && sudo apt install bazel -y 33 | fi 34 | 35 | # upgrade to GCC7 36 | # TODO: check whether we need to maintain the default symlinks here 37 | # for gcc -> GCC-5* such that other tools still work. 38 | echo "checking whether GCC7 is installed..." 39 | if which gcc-7; then 40 | echo "OK" 41 | else 42 | echo "Error: GCC7 is not installed. Exit and Verible isn't installed" 43 | exit 0 44 | fi 45 | 46 | # get verible and install under /tools/verible 47 | # note: you may add $INSTALL_DIR to the PATH, but it is not 48 | # required for the run scripts to work. 49 | echo "Installing Verible ($VERIBLE_VERSION)..." 50 | 51 | mkdir -p build && cd build 52 | git clone https://github.com/google/verible.git 53 | cd verible 54 | git pull origin master 55 | git checkout $VERIBLE_VERSION 56 | 57 | bazel build --cxxopt='-std=c++17' //... 58 | bazel test --cxxopt='-std=c++17' //... 59 | 60 | sudo mkdir -p $INSTALL_DIR 61 | 62 | sudo install bazel-bin/verilog/tools/syntax/verilog_syntax $INSTALL_DIR 63 | sudo install bazel-bin/verilog/tools/formatter/verilog_format $INSTALL_DIR 64 | sudo install bazel-bin/verilog/tools/lint/verilog_lint $INSTALL_DIR 65 | 66 | echo "done" 67 | 68 | 69 | -------------------------------------------------------------------------------- /verilog_style/exclude_filelist.f: -------------------------------------------------------------------------------- 1 | # Current Verible can not support some syntax used in following files. List them here to exclude 2 | # from Verilog style check 3 | # tool does not support macro very well. Issue at github.com/google/verible/issues/102 4 | riscv_instr_cover_group.sv 5 | riscv_instr_pkg.sv 6 | # tool does not support included file very well. Issue at github.com/google/verible/issues/178 7 | riscv_custom_instr_enum.sv 8 | isa/riscv_instr_cov.svh 9 | -------------------------------------------------------------------------------- /verilog_style/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # Copyright 2019 Google LLC 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | find src/ -type f \( -name "*.sv" -o -name "*.svh" \) \ 18 | | grep -vFf ./verilog_style/exclude_filelist.f \ 19 | | xargs /tools/verible/verilog_lint --rules=-macro-name-style 20 | -------------------------------------------------------------------------------- /yaml/cov_testlist.yaml: -------------------------------------------------------------------------------- 1 | - test: riscv_instr_cov_test 2 | description: > 3 | Parse the instruction information from the CSV trace log, sample functional 4 | coverage from the instruction trace. 5 | iterations: 1 6 | gen_test: riscv_instr_cov_test 7 | no_iss: 1 8 | no_gcc: 1 9 | no_post_compare: 1 10 | 11 | - test: exp_riscv_instr_cov_test 12 | description: > 13 | Parse the instruction information from the CSV trace log, sample functional 14 | coverage from the instruction trace. 15 | iterations: 1 16 | gen_test: exp_riscv_instr_cov_test 17 | no_iss: 1 18 | no_gcc: 1 19 | no_post_compare: 1 20 | -------------------------------------------------------------------------------- /yaml/iss.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | - iss: spike 16 | path_var: SPIKE_PATH 17 | cmd: > 18 | /spike --log-commits --isa= --priv= --misaligned -l 19 | 20 | - iss: ovpsim 21 | path_var: OVPSIM_PATH 22 | cmd: > 23 | /riscvOVPsimPlus.exe 24 | --controlfile /riscvOVPsim.ic 25 | --objfilenoentry 26 | --override riscvOVPsim/cpu/simulateexceptions=T 27 | --trace --tracechange --traceshowicount --tracemode --traceregs 28 | --finishafter 1000000 29 | 30 | - iss: sail 31 | path_var: SAIL_RISCV 32 | cmd: > 33 | /riscv_ocaml_sim_RV 34 | 35 | - iss: whisper 36 | path_var: WHISPER_ISS 37 | cmd: > 38 | --log --xlen --isa --configfile /whisper.json --iccmrw 39 | 40 | - iss: renode 41 | path_var: RENODE_PATH 42 | cmd: > 43 | python3 /renode_wrapper.py --renode "" --elf --isa --priv= --mem-size 0x80000000 44 | -------------------------------------------------------------------------------- /yaml/whisper.json: -------------------------------------------------------------------------------- 1 | { 2 | "iccm": { 3 | "region": "0", 4 | "size": "0x80000000", 5 | "offset": "0x80000000" 6 | } 7 | } 8 | --------------------------------------------------------------------------------