├── .github └── workflows │ └── test.yml ├── .gitignore ├── LICENSE ├── README.md ├── altera ├── common │ └── tcl │ │ └── quartus.tcl └── trenz_datastorm │ └── tcl │ ├── board.tcl │ └── datastorm_uniphy.tcl ├── build.wake ├── microsemi ├── common │ └── tcl │ │ └── libero.tcl ├── polarfireevalkit │ └── constraints │ │ ├── PF_EvalKit_DDR3_fp.pdc │ │ ├── PF_EvalKit_DDR3_io.pdc │ │ ├── PF_EvalKit_PCIe_fp.pdc │ │ ├── PF_EvalKit_PCIe_io.pdc │ │ ├── PF_EvalKit_base_io.pdc │ │ ├── PF_EvalKit_fp.pdc │ │ ├── chiplink_io.pdc │ │ └── clock_groups.sdc └── vera │ ├── constraints │ ├── false_paths.sdc │ ├── floor_plan.pdc │ └── pin_constraints.pdc │ └── tcl │ └── board.tcl ├── src └── main │ └── scala │ ├── clocks │ └── PLLFactory.scala │ ├── devices │ ├── altera │ │ └── alteradatastormuniphy │ │ │ └── AlteraDatastormUniphy.scala │ ├── microsemi │ │ ├── polarfire_ddr3 │ │ │ ├── MicrosemiPolarFireDDR3.scala │ │ │ └── MicrosemiPolarFireDDR3Periphery.scala │ │ ├── polarfire_ddr4 │ │ │ ├── MicrosemiPolarFireDDR4.scala │ │ │ └── MicrosemiPolarFireDDR4Periphery.scala │ │ └── polarfire_pcie │ │ │ ├── PolarFireEvalKitPCIeX4.scala │ │ │ └── PolarFireEvalKitPCIeX4Periphery.scala │ └── xilinx │ │ ├── allinxaxku040mig │ │ └── AlinxAxku040MIG.scala │ │ ├── ethernet │ │ └── ethernet.scala │ │ ├── xdma │ │ ├── XDMA.scala │ │ └── package.scala │ │ ├── xilinxarty100tmig │ │ └── XilinxArty100TMIG.scala │ │ ├── xilinxnexysvideomig │ │ └── XilinxNexysVideoMIG.scala │ │ ├── xilinxvc707mig │ │ ├── XilinxVC707MIG.scala │ │ └── XilinxVC707MIGPeriphery.scala │ │ ├── xilinxvc707pciex1 │ │ ├── XilinxVC707PCIeX1.scala │ │ └── XilinxVC707PCIeX1Periphery.scala │ │ ├── xilinxvcu118mig │ │ ├── XilinxVCU118MIG.scala │ │ └── XilinxVCU118MIGPeriphery.scala │ │ └── xilinxzcu102mig │ │ ├── XilinxZCU102MIG.scala │ │ └── XilinxZCU102MIGPeriphery.scala │ ├── ip │ ├── altera │ │ ├── alterapll.scala │ │ └── datastorm_uniphy │ │ │ └── datastorm_uniphy.scala │ ├── microsemi │ │ ├── corejtagdebug │ │ │ └── corejtagdebug.scala │ │ ├── polarfire.scala │ │ ├── polarfire_ccc │ │ │ └── PolarFireCCC.scala │ │ ├── polarfire_clock_divider │ │ │ └── PolarFireClockDivider.scala │ │ ├── polarfire_ddr3 │ │ │ └── PolarFireDDR3.scala │ │ ├── polarfire_ddr4 │ │ │ └── PolarFireDDR4.scala │ │ ├── polarfire_dll │ │ │ └── PolarFireDLL.scala │ │ ├── polarfire_glitchless_mux │ │ │ └── PolarFireGlitchlessMux.scala │ │ ├── polarfire_init_monitor │ │ │ └── PolarFireInitMonitor.scala │ │ ├── polarfire_oscillator │ │ │ └── PolarFireOscillator.scala │ │ ├── polarfire_pcie_rootport │ │ │ └── PolarFirePCIeRootPort.scala │ │ ├── polarfire_reset │ │ │ └── PolarFireReset.scala │ │ ├── polarfire_tx_pll │ │ │ └── PolarFireTxPLL.scala │ │ └── polarfire_xcvr_refclk │ │ │ └── PolarFireTransceiverRefClk.scala │ └── xilinx │ │ ├── Unisim.scala │ │ ├── Xilinx.scala │ │ ├── alinx_axku040mig │ │ └── axku040mig.scala │ │ ├── arty100tmig │ │ └── arty100tmig.scala │ │ ├── bscan │ │ └── bscan.scala │ │ ├── ibufds_gte2 │ │ └── ibufds_gte2.scala │ │ ├── nexysvideomig │ │ └── nexysvideomig.scala │ │ ├── vc707axi_to_pcie_x1 │ │ └── vc707axi_to_pcie_x1.scala │ │ ├── vc707mig │ │ └── vc707mig.scala │ │ ├── vcu118mig │ │ └── vcu118mig.scala │ │ ├── xdma │ │ └── xdma.scala │ │ ├── xxv_ethernet │ │ ├── nfmac10g.scala │ │ └── xxv_ethernet.scala │ │ └── zcu102mig │ │ └── zcu102mig.scala │ └── shell │ ├── ButtonOverlay.scala │ ├── CTSResetOverlay.scala │ ├── ChipLinkOverlay.scala │ ├── ClockOverlay.scala │ ├── DDROverlay.scala │ ├── Ethernet.scala │ ├── GPIOOverlay.scala │ ├── GPIOPMODOverlay.scala │ ├── I2COverlay.scala │ ├── IOShell.scala │ ├── JTAGDebugBScanOverlay.scala │ ├── JTAGDebugOverlay.scala │ ├── LEDOverlay.scala │ ├── PCIeOverlay.scala │ ├── PMODOverlay.scala │ ├── PWMOverlay.scala │ ├── PinOverlay.scala │ ├── PorGenOverlay.scala │ ├── SPIFlashOverlay.scala │ ├── SPIOverlay.scala │ ├── Shell.scala │ ├── SwitchOverlay.scala │ ├── TracePMODOverlay.scala │ ├── UARTOverlay.scala │ ├── Util.scala │ ├── altera │ ├── AlteraPLLFactory.scala │ ├── AlteraSDC.scala │ ├── AlteraShell.scala │ ├── ClockOverlay.scala │ ├── DatastormShell.scala │ └── LEDOverlay.scala │ ├── cJTAGDebugOverlay.scala │ ├── microsemi │ ├── ChipLinkOverlay.scala │ ├── ClockOverlay.scala │ ├── LEDOverlay.scala │ ├── PolarFireEvalKitShell.scala │ ├── PolarFireShell.scala │ └── VeraShell.scala │ ├── package.scala │ └── xilinx │ ├── AlinxAxku040Shell.scala │ ├── Arty100TShell.scala │ ├── ArtyShell.scala │ ├── ButtonOverlay.scala │ ├── ChipLinkOverlay.scala │ ├── ClockOverlay.scala │ ├── GPIOPMODXilinxOverlay.scala │ ├── GPIOXilinxOverlay.scala │ ├── I2COverlay.scala │ ├── JTAGDebugBScanOverlay.scala │ ├── JTAGDebugOverlay.scala │ ├── LEDOverlay.scala │ ├── NexysVideoShell.scala │ ├── PMODOverlay.scala │ ├── PWMOverlay.scala │ ├── PeripheralsVC707Shell.scala │ ├── PeripheralsVCU118Shell.scala │ ├── PinXilinxOverlay.scala │ ├── SDIOOverlay.scala │ ├── SPIFlashXilinxOverlay.scala │ ├── SwitchOverlay.scala │ ├── TracePMODOverlay.scala │ ├── UARTOverlay.scala │ ├── UltraScaleShell.scala │ ├── VC707NewShell.scala │ ├── VC707Shell.scala │ ├── VCU118NewShell.scala │ ├── VCU118Shell.scala │ ├── XilinxShell.scala │ ├── ZCU102NewShell.scala │ └── cJTAGDebugOverlay.scala ├── vsrc └── nfmac10g │ ├── axis2xgmii.v │ ├── nfmac10g.v │ ├── padding_ctrl.v │ ├── rst_mod.v │ ├── rx.v │ ├── tx.v │ ├── xgmii2axis.v │ └── xgmii_includes.vh ├── wit-manifest.json └── xilinx ├── Makefile ├── alinx_axku040 ├── constraints │ └── alinx_axku040.xdc └── tcl │ └── board.tcl ├── arty ├── constraints │ ├── arty-config.xdc │ └── arty-master.xdc └── tcl │ ├── board.tcl │ └── ip.tcl ├── arty_a7_100 ├── constraints │ ├── arty-config.xdc │ └── arty-master.xdc └── tcl │ ├── board.tcl │ └── ip.tcl ├── common └── tcl │ ├── bitstream.tcl │ ├── boards.tcl │ ├── init.tcl │ ├── opt.tcl │ ├── place.tcl │ ├── prologue.tcl │ ├── report.tcl │ ├── route.tcl │ ├── synth-only.tcl │ ├── synth.tcl │ ├── util.tcl │ ├── vivado.tcl │ └── write_cfgmem.tcl ├── nexys_video ├── constraints │ ├── nexys-video-config.xdc │ └── nexys-video-master.xdc └── tcl │ ├── board.tcl │ └── ip.tcl ├── vc707 ├── constraints │ └── vc707-master.xdc ├── tcl │ ├── board.tcl │ ├── clocks.tcl │ └── ios.tcl └── vsrc │ ├── sdio.v │ └── vc707reset.v ├── vcu118 ├── constraints │ └── vcu118-master.xdc ├── tcl │ └── board.tcl └── vsrc │ ├── sdio.v │ └── vcu118reset.v └── zcu102 ├── constraints └── zcu102-master.xdc ├── tcl └── board.tcl └── vsrc ├── sdio.v └── zcu102reset.v /.github/workflows/test.yml: -------------------------------------------------------------------------------- 1 | name: Test 2 | 3 | on: 4 | push: 5 | branches: 6 | - master 7 | pull_request: 8 | branches: 9 | - master 10 | 11 | jobs: 12 | test: 13 | name: Scala compile 14 | runs-on: ubuntu-latest 15 | 16 | steps: 17 | - name: Wit Init 18 | uses: sifive/wit/actions/init@v0.13.2 19 | with: 20 | additional_packages: git@github.com:sifive/environment-blockci-sifive.git::0.7.0 21 | 22 | - name: Run wake scala compile 23 | uses: sifive/environment-blockci-sifive/actions/wake@0.7.0 24 | with: 25 | command: -x 'compileScalaModule fpgaShellsScalaModule | getPathResult' 26 | 27 | lint: 28 | name: Lint 29 | runs-on: ubuntu-latest 30 | 31 | steps: 32 | - uses: actions/checkout@v2 33 | 34 | - name: Run lint check 35 | run: | 36 | set +e # GitHub defaults to -e, but we want to do our own error handling 37 | 38 | if matching_files=$(grep --files-with-matches '\s\+$' *); then 39 | echo "Trailing whitespace detected. Please remove trailing whitespace in the following files:" 40 | echo 41 | echo "$matching_files" 42 | exit 1 43 | fi 44 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /target/ 2 | -------------------------------------------------------------------------------- /altera/common/tcl/quartus.tcl: -------------------------------------------------------------------------------- 1 | package require ::quartus::flow 2 | 3 | set top_model [lindex $argv 0] 4 | set board [lindex $argv 1] 5 | set proj_longname [lindex $argv 2] 6 | 7 | set ip_tcls [lindex $argv 3] 8 | 9 | project_new -overwrite -revision $top_model $top_model 10 | # Setup board specific quartus settings 11 | set scriptdir [file dirname [info script]] 12 | set boarddir [file join [file dirname [file dirname $scriptdir]] $board] 13 | 14 | source [file join $boarddir tcl board.tcl] 15 | 16 | # Setup common quartus lanugage settings 17 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 18 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 19 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 20 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 21 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 22 | set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF 23 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=" 24 | 25 | # Generate and add all IP 26 | if {$ip_tcls ne {}} { 27 | 28 | set ip_tcls [regexp -inline -all -- {\S+} $ip_tcls] 29 | 30 | foreach ip_tcl $ip_tcls { 31 | source $ip_tcl 32 | } 33 | } 34 | 35 | # Add synthesis fileset to quartus 36 | set sl [open $proj_longname.vsrcs.f r] 37 | set files [lsearch -not -exact -all -inline [split [read $sl] "\n"] {}] 38 | 39 | foreach path $files { 40 | if {![string match {#*} $path]} { 41 | if {[string match {*.v} $path]} { 42 | set_global_assignment -name VERILOG_FILE $path 43 | } elseif {[string match {*.sv} $path]} { 44 | set_global_assignment -name SYSTEMVERILOG_FILE $path 45 | } 46 | } 47 | } 48 | 49 | # Add pin assignments and clock constraints 50 | source $proj_longname.assign.tcl 51 | set_global_assignment -name SDC_FILE $proj_longname.shell.sdc 52 | 53 | export_assignments 54 | 55 | execute_flow -compile 56 | project_close 57 | 58 | -------------------------------------------------------------------------------- /altera/trenz_datastorm/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | set_global_assignment -name FAMILY "Cyclone V" 2 | set_global_assignment -name DEVICE 5CSEMA5F31C8 3 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 4 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 5 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 6 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 7 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 8 | set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON 9 | set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON 10 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON 11 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" 12 | set_global_assignment -name ECO_REGENERATE_REPORT ON 13 | set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO 14 | set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON 15 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON 16 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 17 | set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON 18 | set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON 19 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF 20 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" -------------------------------------------------------------------------------- /build.wake: -------------------------------------------------------------------------------- 1 | global def fpgaShellsRoot = here 2 | 3 | def scalacOpts = 4 | "-deprecation", 5 | "-feature", 6 | "-unchecked", 7 | "-language:reflectiveCalls", 8 | "-Xsource:2.11", 9 | Nil 10 | 11 | global def fpgaShellsScalaModule = 12 | def scalaVersion = rocketchipScalaModule.getScalaModuleScalaVersion 13 | makeScalaModule "fpga-shells" here scalaVersion 14 | | setScalaModuleDeps (sifiveBlocksScalaModule, rocketchipScalaModule, Nil) 15 | | setScalaModuleScalacOptions scalacOpts 16 | | addMacrosParadiseCompilerPlugin 17 | -------------------------------------------------------------------------------- /microsemi/polarfireevalkit/constraints/PF_EvalKit_DDR3_fp.pdc: -------------------------------------------------------------------------------- 1 | # Microsemi Physical design constraints file 2 | 3 | # Version: PolarFire v2.0 12.200.0.20 4 | 5 | # Design Name: U500PolarFireEvalKitFPGAChip 6 | 7 | # Input Netlist Format: EDIF 8 | 9 | # Family: PolarFire , Die: MPF300TS_ES , Package: FCG1152 , Speed grade: -1 10 | 11 | # Date generated: Mon Jan 8 10:19:51 2018 12 | 13 | 14 | # 15 | # Local clock constraints 16 | # 17 | 18 | 19 | # 20 | # Region constraints 21 | # 22 | 23 | 24 | # 25 | # Core cell constraints 26 | # 27 | 28 | set_location -inst_name iofpga/polarfireddr/island/blackbox/DDRPHY_BLK_0/LANE_0_CTRL/I_LANECTRL -fixed true -x 1967 -y 378 29 | set_location -inst_name iofpga/polarfireddr/island/blackbox/DDRPHY_BLK_0/IOD_BCLK_TRAINING/I_IOD_0 -fixed true -x 2388 -y 378 30 | set_location -inst_name iofpga/polarfireddr/island/blackbox/DDRPHY_BLK_0/LANE_1_CTRL/I_LANECTRL -fixed true -x 1823 -y 378 31 | set_location -inst_name iofpga/polarfireddr/island/blackbox/DDRPHY_BLK_0/LANE_1_IOD_READ_TRAINING/I_IOD_0 -fixed true -x 1812 -y 378 32 | set_location -inst_name iofpga/polarfireddr/island/blackbox/DDRPHY_BLK_0/LANE_0_IOD_READ_TRAINING/I_IOD_0 -fixed true -x 1956 -y 378 33 | set_location -inst_name iofpga/polarfireddr/island/blackbox/CCC_0/pll_inst_0 -fixed true -x 2460 -y 377 34 | 35 | -------------------------------------------------------------------------------- /microsemi/polarfireevalkit/constraints/PF_EvalKit_PCIe_fp.pdc: -------------------------------------------------------------------------------- 1 | # Microsemi Physical design constraints file 2 | 3 | # Version: PolarFire v2.0 12.200.0.20 4 | 5 | # Design Name: U500PolarFireEvalKitFPGAChip 6 | 7 | # Input Netlist Format: EDIF 8 | 9 | # Family: PolarFire , Die: MPF300TS_ES , Package: FCG1152 , Speed grade: -1 10 | 11 | # Date generated: Mon Jan 8 10:19:51 2018 12 | 13 | 14 | # 15 | # Local clock constraints 16 | # 17 | 18 | 19 | # 20 | # Region constraints 21 | # 22 | 23 | 24 | # 25 | # Core cell constraints 26 | # 27 | 28 | set_location -inst_name pf_xcvr_ref_clk/transceiver_refclk_0/I_IO -fixed true -x 2468 -y 236 29 | set_location -inst_name pf_tx_pll/transmit_pll_0/txpll_isnt_0 -fixed true -x 2466 -y 239 30 | -------------------------------------------------------------------------------- /microsemi/polarfireevalkit/constraints/PF_EvalKit_PCIe_io.pdc: -------------------------------------------------------------------------------- 1 | # Microsemi I/O Physical Design Constraints file 2 | 3 | # User I/O Constraints file 4 | 5 | # Version: PolarFire v2.1 12.200.10.7 6 | 7 | # Family: PolarFire , Die: MPF300TS_ES , Package: FCG1152 8 | 9 | # Date generated: Fri Feb 9 16:31:44 2018 10 | 11 | # 12 | # User Locked I/O Bank Settings 13 | # 14 | 15 | # 16 | # Unlocked I/O Bank Settings 17 | # The I/O Bank Settings can be locked by directly editing this file 18 | # or by making changes in the I/O Attribute Editor 19 | # 20 | 21 | # 22 | # User Locked I/O settings 23 | # 24 | 25 | 26 | 27 | # 28 | # Dedicated Peripheral I/O Settings 29 | # 30 | 31 | 32 | # 33 | # Unlocked I/O settings 34 | # The I/Os in this section are unplaced or placed but are not locked 35 | # the other listed attributes have been applied 36 | # 37 | 38 | 39 | # 40 | #Ports using Dedicated Pins 41 | 42 | # 43 | 44 | set_io -port_name pcie_PCIESS_LANE_RXD0_N \ 45 | -pin_name V30 \ 46 | -DIRECTION INPUT 47 | 48 | 49 | set_io -port_name pcie_PCIESS_LANE_RXD0_P \ 50 | -pin_name V29 \ 51 | -DIRECTION INPUT 52 | 53 | 54 | set_io -port_name pcie_PCIESS_LANE_RXD1_N \ 55 | -pin_name W32 \ 56 | -DIRECTION INPUT 57 | 58 | 59 | set_io -port_name pcie_PCIESS_LANE_RXD1_P \ 60 | -pin_name W31 \ 61 | -DIRECTION INPUT 62 | 63 | 64 | set_io -port_name pcie_PCIESS_LANE_RXD2_N \ 65 | -pin_name Y30 \ 66 | -DIRECTION INPUT 67 | 68 | 69 | set_io -port_name pcie_PCIESS_LANE_RXD2_P \ 70 | -pin_name Y29 \ 71 | -DIRECTION INPUT 72 | 73 | 74 | set_io -port_name pcie_PCIESS_LANE_RXD3_N \ 75 | -pin_name AB30 \ 76 | -DIRECTION INPUT 77 | 78 | 79 | set_io -port_name pcie_PCIESS_LANE_RXD3_P \ 80 | -pin_name AB29 \ 81 | -DIRECTION INPUT 82 | 83 | 84 | set_io -port_name pcie_PCIESS_LANE_TXD0_N \ 85 | -pin_name V34 \ 86 | -DIRECTION OUTPUT 87 | 88 | 89 | set_io -port_name pcie_PCIESS_LANE_TXD0_P \ 90 | -pin_name V33 \ 91 | -DIRECTION OUTPUT 92 | 93 | 94 | set_io -port_name pcie_PCIESS_LANE_TXD1_N \ 95 | -pin_name Y34 \ 96 | -DIRECTION OUTPUT 97 | 98 | 99 | set_io -port_name pcie_PCIESS_LANE_TXD1_P \ 100 | -pin_name Y33 \ 101 | -DIRECTION OUTPUT 102 | 103 | 104 | set_io -port_name pcie_PCIESS_LANE_TXD2_N \ 105 | -pin_name AA32 \ 106 | -DIRECTION OUTPUT 107 | 108 | 109 | set_io -port_name pcie_PCIESS_LANE_TXD2_P \ 110 | -pin_name AA31 \ 111 | -DIRECTION OUTPUT 112 | 113 | 114 | set_io -port_name pcie_PCIESS_LANE_TXD3_N \ 115 | -pin_name AB34 \ 116 | -DIRECTION OUTPUT 117 | 118 | 119 | set_io -port_name pcie_PCIESS_LANE_TXD3_P \ 120 | -pin_name AB33 \ 121 | -DIRECTION OUTPUT 122 | 123 | 124 | set_io -port_name ref_clk_pad_n \ 125 | -pin_name W28 \ 126 | -DIRECTION INPUT 127 | 128 | 129 | set_io -port_name ref_clk_pad_p \ 130 | -pin_name W27 \ 131 | -DIRECTION INPUT 132 | 133 | 134 | -------------------------------------------------------------------------------- /microsemi/polarfireevalkit/constraints/PF_EvalKit_fp.pdc: -------------------------------------------------------------------------------- 1 | 2 | set_location -inst_name hart_clk_ccc/hart_clk_ccc_0/pll_inst_0 -fixed true -x 2461 -y 377 3 | set_location -inst_name ddr3_clk_ccc/ddr3_clk_ccc_0/pll_inst_0 -fixed true -x 2460 -y 5 4 | -------------------------------------------------------------------------------- /microsemi/polarfireevalkit/constraints/clock_groups.sdc: -------------------------------------------------------------------------------- 1 | #set_clock_groups -name {Coreplex} -logically_exclusive -group [ get_clocks { hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT0 } ] 2 | set_clock_groups -name {PCIe_AXI} -logically_exclusive -group [ get_clocks { hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT1 } ] 3 | set_clock_groups -name {DDR_subsystem} -logically_exclusive -group [ get_clocks { iofpga/polarfireddr/island/blackbox/CCC_0/pll_inst_0/OUT1 } ] 4 | 5 | 6 | -------------------------------------------------------------------------------- /microsemi/vera/constraints/false_paths.sdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [ get_ports { ereset_n }] 2 | create_clock -name {chiplink_b2c_clk} -period 8 [ get_ports { chiplink_b2c_clk } ] 3 | 4 | # The c2b_clk comes from a phase-shifted output of the PLL 5 | create_generated_clock -name {chiplink_c2b_clk} \ 6 | -divide_by 1 -phase 0 \ 7 | -source [ get_pins { hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT2 } ] \ 8 | [ get_ports { chiplink_c2b_clk } ] 9 | 10 | set_clock_groups -asynchronous \ 11 | -group [ get_clocks { chiplink_b2c_clk \ 12 | iofpga/chiplink_rx_pll/chiplink_rx_pll_0/pll_inst_0/OUT1 } ] \ 13 | -group [ get_clocks { ref_clk0 \ 14 | hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT1 \ 15 | hart_clk_ccc/hart_clk_ccc_0/pll_inst_0/OUT2 \ 16 | chiplink_c2b_clk } ] \ 17 | -group [ get_clocks { osc_rc160mhz } ] \ 18 | -group [ get_clocks { ref_clk_pad_p } ] \ 19 | -group [ get_clocks { iofpga/pf_ddr4/island/blackbox/CCC_0/pll_inst_0/OUT1 } ] 20 | 21 | # RX side: want to latch almost anywhere except on the rising edge of the clock 22 | # The data signals coming from Aloe have: clock - 1.2 <= transition <= clock + 0.8 23 | # HFU500 Expansion board has 200mil delta between clock and data 24 | # Let's add 0.1ns of safety for trace jitter+skew on both sides: 25 | # min = hold = -1.2 - 0.1 26 | # max = period - setup = 0.8 + 0.1 27 | set_input_delay -min -1.3 -clock {chiplink_b2c_clk} [ get_ports { chiplink_b2c_data* chiplink_b2c_rst chiplink_b2c_send } ] 28 | set_input_delay -max 0.9 -clock {chiplink_b2c_clk} [ get_ports { chiplink_b2c_data* chiplink_b2c_rst chiplink_b2c_send } ] 29 | 30 | # TX side: want to transition almost anywhere except on the rising edge of the clock 31 | # The data signals going to Aloe must have: clock - 1.85 <= NO transition <= clock + 0.65 32 | # Let's add 0.6ns of safey for trace jitter+skew on both sides: 33 | # min = -hold = -0.65 - 0.6 34 | # max = setup = 1.85 + 0.6 35 | set_output_delay -min -1.25 -clock {chiplink_c2b_clk} [ get_ports { chiplink_c2b_data* chiplink_c2b_rst chiplink_c2b_send } ] 36 | set_output_delay -max 2.45 -clock {chiplink_c2b_clk} [ get_ports { chiplink_c2b_data* chiplink_c2b_rst chiplink_c2b_send } ] 37 | # phase = 31.5 -> 0.55ns setup slack, 0.45ns hold slack 38 | 39 | #retiming is required 40 | set_false_path -from [ get_pins { iofpga/link/ResetCatchAndSync_d3_1/AsyncResetSynchronizerShiftReg_w1_d3_i0/sync_2/reg_0/q/CLK } ] -to [ get_ports { chiplink_c2b_rst } ] 41 | set_false_path -from [ get_ports { chiplink_b2c_rst } ] -to [ get_pins { iofpga/link/AsyncResetReg/q/D } ] 42 | -------------------------------------------------------------------------------- /microsemi/vera/constraints/floor_plan.pdc: -------------------------------------------------------------------------------- 1 | # Constraints 2 | 3 | set_location -inst_name corePLL/corePLL_0/pll_inst_0 -fixed true -x 1 -y 377 4 | set_location -inst_name rxPLL/rxPLL_0/pll_inst_0 -fixed true -x 0 -y 377 5 | -------------------------------------------------------------------------------- /microsemi/vera/constraints/pin_constraints.pdc: -------------------------------------------------------------------------------- 1 | # 2 | # User Locked I/O Bank Settings 3 | # 4 | 5 | set_iobank -bank_name Bank0 -vcci 1.80 -fixed true 6 | set_iobank -bank_name Bank1 -vcci 1.20 -fixed true 7 | set_iobank -bank_name Bank2 -vcci 3.30 -fixed true 8 | set_iobank -bank_name Bank4 -vcci 1.80 -fixed true 9 | set_iobank -bank_name Bank5 -vcci 3.30 -fixed true 10 | set_iobank -bank_name Bank6 -vcci 1.80 -fixed true 11 | set_iobank -bank_name Bank7 -vcci 1.80 -fixed true 12 | -------------------------------------------------------------------------------- /microsemi/vera/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | #Device Selection 2 | set family {PolarFire} 3 | set die {MPF300TS_ES} 4 | set package {FCG1152} 5 | set speed {-1} 6 | set die_voltage {1.0} 7 | set part_range {EXT} 8 | 9 | #Device Settings 10 | set IOTech {LVCMOS 1.8V} 11 | set ResProbe {1} 12 | set ResSPI {0} 13 | -------------------------------------------------------------------------------- /src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireDDR3Periphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.microsemi.polarfireddr3 2 | 3 | import org.chipsalliance.cde.config._ 4 | import freechips.rocketchip.diplomacy.{AddressRange, LazyModule, LazyModuleImp} 5 | import freechips.rocketchip.subsystem.{BaseSubsystem, MBUS} 6 | import freechips.rocketchip.tilelink.TLWidthWidget 7 | 8 | case object MemoryMicrosemiDDR3Key extends Field[PolarFireEvalKitDDR3Params] 9 | 10 | //trait HasMemoryPolarFireEvalKitDDR3 extends HasMemoryBus { 11 | trait HasMemoryPolarFireEvalKitDDR3 { this: BaseSubsystem => 12 | val module: HasMemoryPolarFireEvalKitDDR3ModuleImp 13 | 14 | val polarfireddrsubsys = LazyModule(new PolarFireEvalKitDDR3(p(MemoryMicrosemiDDR3Key))) 15 | 16 | private val mbus = locateTLBusWrapper(MBUS) 17 | mbus.coupleTo("PolarFireDDR") { polarfireddrsubsys.node := TLWidthWidget(mbus.beatBytes) := _ } 18 | } 19 | 20 | trait HasMemoryPolarFireEvalKitDDR3Bundle { 21 | val polarfireddrsubsys: PolarFireEvalKitDDR3IO 22 | def connectPolarFireEValKitDDR3ToPads(pads: PolarFireEvalKitDDR3Pads) { 23 | pads <> polarfireddrsubsys 24 | } 25 | } 26 | 27 | trait HasMemoryPolarFireEvalKitDDR3ModuleImp extends LazyModuleImp 28 | with HasMemoryPolarFireEvalKitDDR3Bundle { 29 | val outer: HasMemoryPolarFireEvalKitDDR3 30 | val ranges = AddressRange.fromSets(p(MemoryMicrosemiDDR3Key).address) 31 | require (ranges.size == 1, "DDR range must be contiguous") 32 | val depth = ranges.head.size 33 | val polarfireddrsubsys = IO(new PolarFireEvalKitDDR3IO(depth)) 34 | 35 | polarfireddrsubsys <> outer.polarfireddrsubsys.module.io.port 36 | } 37 | 38 | /* 39 | Copyright 2016 SiFive, Inc. 40 | 41 | Licensed under the Apache License, Version 2.0 (the "License"); 42 | you may not use this file except in compliance with the License. 43 | You may obtain a copy of the License at 44 | 45 | http://www.apache.org/licenses/LICENSE-2.0 46 | 47 | Unless required by applicable law or agreed to in writing, software 48 | distributed under the License is distributed on an "AS IS" BASIS, 49 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 50 | See the License for the specific language governing permissions and 51 | limitations under the License. 52 | */ 53 | -------------------------------------------------------------------------------- /src/main/scala/devices/microsemi/polarfire_ddr4/MicrosemiPolarFireDDR4Periphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.microsemi.polarfireddr4 2 | 3 | import org.chipsalliance.cde.config._ 4 | import freechips.rocketchip.diplomacy.{AddressRange, LazyModule, LazyModuleImp} 5 | import freechips.rocketchip.subsystem.{BaseSubsystem, MBUS} 6 | import freechips.rocketchip.tilelink.TLWidthWidget 7 | 8 | case object MemoryMicrosemiDDR4Key extends Field[PolarFireEvalKitDDR4Params] 9 | 10 | //trait HasMemoryPolarFireEvalKitDDR4 extends HasMemoryBus { 11 | trait HasMemoryPolarFireEvalKitDDR4 { this: BaseSubsystem => 12 | val module: HasMemoryPolarFireEvalKitDDR4ModuleImp 13 | 14 | val polarfireddrsubsys = LazyModule(new PolarFireEvalKitDDR4(p(MemoryMicrosemiDDR4Key))) 15 | 16 | private val mbus = locateTLBusWrapper(MBUS) 17 | mbus.coupleTo("PolarFireDDR") { polarfireddrsubsys.node := TLWidthWidget(mbus.beatBytes) := _ } 18 | } 19 | 20 | trait HasMemoryPolarFireEvalKitDDR4Bundle { 21 | val polarfireddrsubsys: PolarFireEvalKitDDR4IO 22 | def connectPolarFireEValKitDDR4ToPads(pads: PolarFireEvalKitDDR4Pads) { 23 | pads <> polarfireddrsubsys 24 | } 25 | } 26 | 27 | trait HasMemoryPolarFireEvalKitDDR4ModuleImp extends LazyModuleImp 28 | with HasMemoryPolarFireEvalKitDDR4Bundle { 29 | val outer: HasMemoryPolarFireEvalKitDDR4 30 | val ranges = AddressRange.fromSets(p(MemoryMicrosemiDDR4Key).address) 31 | require (ranges.size == 1, "DDR range must be contiguous") 32 | val depth = ranges.head.size 33 | val polarfireddrsubsys = IO(new PolarFireEvalKitDDR4IO(depth)) 34 | 35 | polarfireddrsubsys <> outer.polarfireddrsubsys.module.io.port 36 | } 37 | 38 | /* 39 | Copyright 2016 SiFive, Inc. 40 | 41 | Licensed under the Apache License, Version 2.0 (the "License"); 42 | you may not use this file except in compliance with the License. 43 | You may obtain a copy of the License at 44 | 45 | http://www.apache.org/licenses/LICENSE-2.0 46 | 47 | Unless required by applicable law or agreed to in writing, software 48 | distributed under the License is distributed on an "AS IS" BASIS, 49 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 50 | See the License for the specific language governing permissions and 51 | limitations under the License. 52 | */ 53 | -------------------------------------------------------------------------------- /src/main/scala/devices/microsemi/polarfire_pcie/PolarFireEvalKitPCIeX4.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.microsemi.polarfireevalkitpciex4 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.amba.axi4._ 5 | //import freechips.rocketchip.coreplex.CacheBlockBytes 6 | import freechips.rocketchip.diplomacy._ 7 | import freechips.rocketchip.prci._ 8 | import freechips.rocketchip.interrupts._ 9 | import freechips.rocketchip.subsystem.{CacheBlockBytes, HasCrossing} 10 | import freechips.rocketchip.tilelink._ 11 | import freechips.rocketchip.util._ 12 | import org.chipsalliance.cde.config.Parameters 13 | import sifive.fpgashells.ip.microsemi.polarfirepcierootport._ 14 | 15 | trait PolarFireEvalKitPCIeRefClk extends Bundle{ 16 | //TODO: bring reference clock connection in here 17 | val REFCLK_rxp = Input(Bool()) 18 | val REFCLK_rxn = Input(Bool()) 19 | } 20 | 21 | class PolarFireEvalKitPCIeX4Pads extends Bundle 22 | with PolarFirePCIeIOSerial 23 | with PolarFireEvalKitPCIeRefClk 24 | 25 | class PolarFireEvalKitPCIeX4IO extends Bundle 26 | with PolarFireEvalKitPCIeRefClk 27 | with PolarFirePCIeIOSerial 28 | with PolarFirePCIeIODebug 29 | with PolarFirePCIeIOClocksReset { 30 | val axi_ctl_aresetn = Input(Bool()) 31 | } 32 | 33 | class PolarFireEvalKitPCIeX4(implicit p: Parameters) extends LazyModule with HasCrossing { 34 | val crossing = SynchronousCrossing() 35 | val axi_to_pcie = LazyModule(new PolarFirePCIeX4) 36 | 37 | val slave: TLInwardNode = 38 | (axi_to_pcie.slave 39 | := AXI4Buffer() 40 | := AXI4UserYanker() 41 | := AXI4Deinterleaver(p(CacheBlockBytes)) 42 | := AXI4IdIndexer(idBits=4) 43 | := TLToAXI4(adapterName = Some("pcie-slave"))) 44 | 45 | val control: TLInwardNode = 46 | (axi_to_pcie.control 47 | := TLToAPB(false) 48 | := TLBuffer() 49 | := TLFragmenter(4, p(CacheBlockBytes))) 50 | 51 | val master: TLOutwardNode = 52 | (TLWidthWidget(8) 53 | := AXI4ToTL() 54 | := AXI4UserYanker(capMaxFlight=Some(8)) 55 | := AXI4Fragmenter() 56 | := AXI4IdIndexer(idBits=2) 57 | := AXI4Buffer() 58 | := axi_to_pcie.master) 59 | 60 | val TLScope = LazyModule(new SimpleLazyModule with LazyScope) 61 | val intnode: IntOutwardNode = IntSyncAsyncCrossingSink() := TLScope { 62 | IntSyncCrossingSource(alreadyRegistered = true) := axi_to_pcie.intnode 63 | } 64 | 65 | lazy val module = new Impl 66 | class Impl extends LazyModuleImp(this) { 67 | val io = IO(new Bundle { 68 | val port = new PolarFireEvalKitPCIeX4IO 69 | }) 70 | 71 | io.port <> axi_to_pcie.module.io.port 72 | TLScope.module.clock := io.port.PCIE_1_TL_CLK_125MHz 73 | TLScope.module.reset := ResetCatchAndSync(io.port.PCIE_1_TL_CLK_125MHz, reset.asBool) 74 | } 75 | } 76 | 77 | /* 78 | Copyright 2016 SiFive, Inc. 79 | 80 | Licensed under the Apache License, Version 2.0 (the "License"); 81 | you may not use this file except in compliance with the License. 82 | You may obtain a copy of the License at 83 | 84 | http://www.apache.org/licenses/LICENSE-2.0 85 | 86 | Unless required by applicable law or agreed to in writing, software 87 | distributed under the License is distributed on an "AS IS" BASIS, 88 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 89 | See the License for the specific language governing permissions and 90 | limitations under the License. 91 | */ 92 | -------------------------------------------------------------------------------- /src/main/scala/devices/microsemi/polarfire_pcie/PolarFireEvalKitPCIeX4Periphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.microsemi.polarfireevalkitpciex4 2 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 3 | import freechips.rocketchip.subsystem.{BaseSubsystem, SBUS} 4 | import freechips.rocketchip.tilelink._ 5 | 6 | //trait HasSystemPolarFireEvalKitPCIeX4 extends HasSystemBus with HasInterruptBus { 7 | trait HasSystemPolarFireEvalKitPCIeX4 { this: BaseSubsystem => 8 | val pf_eval_kit_pcie = LazyModule(new PolarFireEvalKitPCIeX4) 9 | private val cname = "polarfirepcie" 10 | private val sbus = locateTLBusWrapper(SBUS) 11 | sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* pf_eval_kit_pcie.crossTLOut(pf_eval_kit_pcie.master) } 12 | sbus.coupleTo(s"slave_named_$cname") { pf_eval_kit_pcie.crossTLIn(pf_eval_kit_pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } 13 | sbus.coupleTo(s"controller_named_$cname") { pf_eval_kit_pcie.crossTLIn(pf_eval_kit_pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } 14 | ibus.fromSync := pf_eval_kit_pcie.crossIntOut(pf_eval_kit_pcie.intnode) 15 | } 16 | 17 | trait HasSystemPolarFireEvalKitPCIeX4Bundle { 18 | val pf_eval_kit_pcie: PolarFireEvalKitPCIeX4IO 19 | def connectPolarFireEvalKitPCIeX4ToPads(pads: PolarFireEvalKitPCIeX4Pads) { 20 | pads <> pf_eval_kit_pcie 21 | } 22 | } 23 | 24 | trait HasSystemPolarFireEvalKitPCIeX4ModuleImp extends LazyModuleImp 25 | with HasSystemPolarFireEvalKitPCIeX4Bundle { 26 | val outer: HasSystemPolarFireEvalKitPCIeX4 27 | val pf_eval_kit_pcie = IO(new PolarFireEvalKitPCIeX4IO) 28 | 29 | pf_eval_kit_pcie <> outer.pf_eval_kit_pcie.module.io.port 30 | 31 | outer.pf_eval_kit_pcie.module.clock := outer.pf_eval_kit_pcie.module.io.port.AXI_CLK 32 | } 33 | 34 | /* 35 | Copyright 2016 SiFive, Inc. 36 | 37 | Licensed under the Apache License, Version 2.0 (the "License"); 38 | you may not use this file except in compliance with the License. 39 | You may obtain a copy of the License at 40 | 41 | http://www.apache.org/licenses/LICENSE-2.0 42 | 43 | Unless required by applicable law or agreed to in writing, software 44 | distributed under the License is distributed on an "AS IS" BASIS, 45 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 46 | See the License for the specific language governing permissions and 47 | limitations under the License. 48 | */ 49 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xdma/XDMA.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx.xdma 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.amba.axi4._ 5 | import freechips.rocketchip.diplomacy._ 6 | import freechips.rocketchip.prci._ 7 | import freechips.rocketchip.interrupts._ 8 | import freechips.rocketchip.subsystem.{CacheBlockBytes, CrossesToOnlyOneClockDomain} 9 | import freechips.rocketchip.tilelink._ 10 | import org.chipsalliance.cde.config.Parameters 11 | import sifive.fpgashells.ip.xilinx.xdma._ 12 | 13 | class XDMA(c: XDMAParams)(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) 14 | extends LazyModule with CrossesToOnlyOneClockDomain 15 | { 16 | val imp = LazyModule(new DiplomaticXDMA(c)) 17 | 18 | val slave: TLInwardNode = 19 | (imp.slave 20 | := AXI4Buffer() 21 | := AXI4UserYanker() 22 | := AXI4Deinterleaver(p(CacheBlockBytes)) 23 | := AXI4IdIndexer(idBits=c.sIDBits) 24 | := TLToAXI4(adapterName = Some("pcie-slave"))) 25 | 26 | val control: TLInwardNode = 27 | (imp.control 28 | := AXI4Buffer() 29 | := AXI4UserYanker(capMaxFlight = Some(2)) 30 | := TLToAXI4() 31 | := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) 32 | 33 | val master: TLOutwardNode = 34 | (TLWidthWidget(c.busBytes) 35 | := AXI4ToTL() 36 | := AXI4UserYanker(capMaxFlight=Some(16)) 37 | := AXI4Fragmenter() 38 | := AXI4IdIndexer(idBits=2) 39 | := imp.master) 40 | 41 | val intnode: IntOutwardNode = imp.intnode 42 | 43 | lazy val module = new Impl 44 | class Impl extends LazyModuleImp(this) { 45 | val io = IO(new Bundle { 46 | val pads = new XDMAPads(c.lanes) 47 | val clocks = new XDMAClocks 48 | }) 49 | 50 | io.pads <> imp.module.io.pads 51 | io.clocks <> imp.module.io.clocks 52 | } 53 | } 54 | 55 | /* 56 | Copyright 2016 SiFive, Inc. 57 | 58 | Licensed under the Apache License, Version 2.0 (the "License"); 59 | you may not use this file except in compliance with the License. 60 | You may obtain a copy of the License at 61 | 62 | http://www.apache.org/licenses/LICENSE-2.0 63 | 64 | Unless required by applicable law or agreed to in writing, software 65 | distributed under the License is distributed on an "AS IS" BASIS, 66 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 67 | See the License for the specific language governing permissions and 68 | limitations under the License. 69 | */ 70 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xdma/package.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx 2 | 3 | package object xdma 4 | { 5 | type XDMAPads = sifive.fpgashells.ip.xilinx.xdma.XDMAPads 6 | type XDMAClocks = sifive.fpgashells.ip.xilinx.xdma.XDMAClocks 7 | type XDMAParams = sifive.fpgashells.ip.xilinx.xdma.XDMAParams 8 | val XDMAParams = sifive.fpgashells.ip.xilinx.xdma.XDMAParams 9 | } 10 | 11 | /* 12 | Copyright 2016 SiFive, Inc. 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx.xilinxvc707mig 2 | 3 | import freechips.rocketchip.diplomacy.{AddressRange, LazyModule, LazyModuleImp} 4 | import freechips.rocketchip.subsystem.{BaseSubsystem, MBUS} 5 | import freechips.rocketchip.tilelink.TLWidthWidget 6 | import org.chipsalliance.cde.config._ 7 | 8 | case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams] 9 | 10 | trait HasMemoryXilinxVC707MIG { this: BaseSubsystem => 11 | val module: HasMemoryXilinxVC707MIGModuleImp 12 | 13 | val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey))) 14 | 15 | private val mbus = locateTLBusWrapper(MBUS) 16 | mbus.coupleTo("xilinxvc707mig") { xilinxvc707mig.node := TLWidthWidget(mbus.beatBytes) := _ } 17 | } 18 | 19 | trait HasMemoryXilinxVC707MIGBundle { 20 | val xilinxvc707mig: XilinxVC707MIGIO 21 | def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) { 22 | pads <> xilinxvc707mig 23 | } 24 | } 25 | 26 | trait HasMemoryXilinxVC707MIGModuleImp extends LazyModuleImp 27 | with HasMemoryXilinxVC707MIGBundle { 28 | val outer: HasMemoryXilinxVC707MIG 29 | val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) 30 | require (ranges.size == 1, "DDR range must be contiguous") 31 | val depth = ranges.head.size 32 | val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth)) 33 | 34 | xilinxvc707mig <> outer.xilinxvc707mig.module.io.port 35 | } 36 | 37 | /* 38 | Copyright 2016 SiFive, Inc. 39 | 40 | Licensed under the Apache License, Version 2.0 (the "License"); 41 | you may not use this file except in compliance with the License. 42 | You may obtain a copy of the License at 43 | 44 | http://www.apache.org/licenses/LICENSE-2.0 45 | 46 | Unless required by applicable law or agreed to in writing, software 47 | distributed under the License is distributed on an "AS IS" BASIS, 48 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 49 | See the License for the specific language governing permissions and 50 | limitations under the License. 51 | */ 52 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.amba.axi4._ 5 | import freechips.rocketchip.diplomacy._ 6 | import freechips.rocketchip.prci._ 7 | import freechips.rocketchip.interrupts._ 8 | import freechips.rocketchip.subsystem.{CacheBlockBytes, CrossesToOnlyOneClockDomain} 9 | import freechips.rocketchip.tilelink._ 10 | import org.chipsalliance.cde.config.Parameters 11 | import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 12 | import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial} 13 | 14 | trait VC707AXIToPCIeRefClk extends Bundle{ 15 | val REFCLK_rxp = Input(Bool()) 16 | val REFCLK_rxn = Input(Bool()) 17 | } 18 | 19 | class XilinxVC707PCIeX1Pads extends Bundle 20 | with VC707AXIToPCIeX1IOSerial 21 | with VC707AXIToPCIeRefClk 22 | 23 | class XilinxVC707PCIeX1IO extends Bundle 24 | with VC707AXIToPCIeRefClk 25 | with VC707AXIToPCIeX1IOSerial 26 | with VC707AXIToPCIeX1IOClocksReset { 27 | val axi_ctl_aresetn = Input(Bool()) 28 | } 29 | 30 | class XilinxVC707PCIeX1(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) 31 | extends LazyModule with CrossesToOnlyOneClockDomain 32 | { 33 | val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) 34 | 35 | val slave: TLInwardNode = 36 | (axi_to_pcie_x1.slave 37 | := AXI4Buffer() 38 | := AXI4UserYanker() 39 | := AXI4Deinterleaver(p(CacheBlockBytes)) 40 | := AXI4IdIndexer(idBits=4) 41 | := TLToAXI4(adapterName = Some("pcie-slave"))) 42 | 43 | val control: TLInwardNode = 44 | (axi_to_pcie_x1.control 45 | := AXI4Buffer() 46 | := AXI4UserYanker(capMaxFlight = Some(2)) 47 | := TLToAXI4() 48 | := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) 49 | 50 | val master: TLOutwardNode = 51 | (TLWidthWidget(8) 52 | := AXI4ToTL() 53 | := AXI4UserYanker(capMaxFlight=Some(8)) 54 | := AXI4Fragmenter() 55 | := axi_to_pcie_x1.master) 56 | 57 | val intnode: IntOutwardNode = axi_to_pcie_x1.intnode 58 | 59 | lazy val module = new Impl 60 | class Impl extends LazyRawModuleImp(this) { 61 | val io = IO(new Bundle { 62 | val port = new XilinxVC707PCIeX1IO 63 | }) 64 | override def provideImplicitClockToLazyChildren = true 65 | childClock := io.port.axi_aclk_out 66 | childReset := ~io.port.axi_aresetn 67 | 68 | io.port <> axi_to_pcie_x1.module.io.port 69 | 70 | //PCIe Reference Clock 71 | val ibufds_gte2 = Module(new IBUFDS_GTE2) 72 | axi_to_pcie_x1.module.io.REFCLK := ibufds_gte2.io.O 73 | ibufds_gte2.io.CEB := 0.U 74 | ibufds_gte2.io.I := io.port.REFCLK_rxp 75 | ibufds_gte2.io.IB := io.port.REFCLK_rxn 76 | } 77 | } 78 | 79 | /* 80 | Copyright 2016 SiFive, Inc. 81 | 82 | Licensed under the Apache License, Version 2.0 (the "License"); 83 | you may not use this file except in compliance with the License. 84 | You may obtain a copy of the License at 85 | 86 | http://www.apache.org/licenses/LICENSE-2.0 87 | 88 | Unless required by applicable law or agreed to in writing, software 89 | distributed under the License is distributed on an "AS IS" BASIS, 90 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 91 | See the License for the specific language governing permissions and 92 | limitations under the License. 93 | */ 94 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1 2 | 3 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 4 | import freechips.rocketchip.subsystem.{BaseSubsystem, SBUS} 5 | import freechips.rocketchip.tilelink._ 6 | 7 | trait HasSystemXilinxVC707PCIeX1 { this: BaseSubsystem => 8 | val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) 9 | private val cname = "xilinxvc707pcie" 10 | private val sbus = locateTLBusWrapper(SBUS) 11 | sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* xilinxvc707pcie.crossTLOut(xilinxvc707pcie.master) } 12 | sbus.coupleTo(s"slave_named_$cname") { xilinxvc707pcie.crossTLIn(xilinxvc707pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } 13 | sbus.coupleTo(s"controller_named_$cname") { xilinxvc707pcie.crossTLIn(xilinxvc707pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } 14 | ibus.fromSync := xilinxvc707pcie.crossIntOut(xilinxvc707pcie.intnode) 15 | } 16 | 17 | trait HasSystemXilinxVC707PCIeX1Bundle { 18 | val xilinxvc707pcie: XilinxVC707PCIeX1IO 19 | def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) { 20 | pads <> xilinxvc707pcie 21 | } 22 | } 23 | 24 | trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyModuleImp 25 | with HasSystemXilinxVC707PCIeX1Bundle { 26 | val outer: HasSystemXilinxVC707PCIeX1 27 | val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO) 28 | 29 | xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port 30 | } 31 | 32 | /* 33 | Copyright 2016 SiFive, Inc. 34 | 35 | Licensed under the Apache License, Version 2.0 (the "License"); 36 | you may not use this file except in compliance with the License. 37 | You may obtain a copy of the License at 38 | 39 | http://www.apache.org/licenses/LICENSE-2.0 40 | 41 | Unless required by applicable law or agreed to in writing, software 42 | distributed under the License is distributed on an "AS IS" BASIS, 43 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 44 | See the License for the specific language governing permissions and 45 | limitations under the License. 46 | */ 47 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xilinxvcu118mig/XilinxVCU118MIGPeriphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx.xilinxvcu118mig 2 | 3 | import freechips.rocketchip.diplomacy.{AddressRange, LazyModule, LazyModuleImp} 4 | import freechips.rocketchip.subsystem.{BaseSubsystem, MBUS} 5 | import freechips.rocketchip.tilelink.TLWidthWidget 6 | import org.chipsalliance.cde.config._ 7 | 8 | case object MemoryXilinxDDRKey extends Field[XilinxVCU118MIGParams] 9 | 10 | trait HasMemoryXilinxVCU118MIG { this: BaseSubsystem => 11 | val module: HasMemoryXilinxVCU118MIGModuleImp 12 | 13 | val xilinxvcu118mig = LazyModule(new XilinxVCU118MIG(p(MemoryXilinxDDRKey))) 14 | 15 | private val mbus = locateTLBusWrapper(MBUS) 16 | mbus.coupleTo("xilinxvcu118mig") { xilinxvcu118mig.node := TLWidthWidget(mbus.beatBytes) := _ } 17 | } 18 | 19 | trait HasMemoryXilinxVCU118MIGBundle { 20 | val xilinxvcu118mig: XilinxVCU118MIGIO 21 | def connectXilinxVCU118MIGToPads(pads: XilinxVCU118MIGPads) { 22 | pads <> xilinxvcu118mig 23 | } 24 | } 25 | 26 | trait HasMemoryXilinxVCU118MIGModuleImp extends LazyModuleImp 27 | with HasMemoryXilinxVCU118MIGBundle { 28 | val outer: HasMemoryXilinxVCU118MIG 29 | val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) 30 | require (ranges.size == 1, "DDR range must be contiguous") 31 | val depth = ranges.head.size 32 | val xilinxvcu118mig = IO(new XilinxVCU118MIGIO(depth)) 33 | 34 | xilinxvcu118mig <> outer.xilinxvcu118mig.module.io.port 35 | } 36 | 37 | /* 38 | Copyright 2016 SiFive, Inc. 39 | 40 | Licensed under the Apache License, Version 2.0 (the "License"); 41 | you may not use this file except in compliance with the License. 42 | You may obtain a copy of the License at 43 | 44 | http://www.apache.org/licenses/LICENSE-2.0 45 | 46 | Unless required by applicable law or agreed to in writing, software 47 | distributed under the License is distributed on an "AS IS" BASIS, 48 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 49 | See the License for the specific language governing permissions and 50 | limitations under the License. 51 | */ 52 | -------------------------------------------------------------------------------- /src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.devices.xilinx.xilinxzcu102mig 2 | 3 | import chisel3._ 4 | import org.chipsalliance.cde.config._ 5 | import freechips.rocketchip.subsystem.{BaseSubsystem, MBUS} 6 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressRange} 7 | import freechips.rocketchip.tilelink.{TLWidthWidget} 8 | case object MemoryXilinxDDRKey extends Field[XilinxZCU102MIGParams] 9 | 10 | trait HasMemoryXilinxZCU102MIG { this: BaseSubsystem => 11 | val module: HasMemoryXilinxZCU102MIGModuleImp 12 | 13 | val xilinxzcu102mig = LazyModule(new XilinxZCU102MIG(p(MemoryXilinxDDRKey))) 14 | 15 | private val mbus = locateTLBusWrapper(MBUS) 16 | mbus.coupleTo("xilinxzcu102mig") { xilinxzcu102mig.node := TLWidthWidget(mbus.beatBytes) := _ } 17 | } 18 | 19 | trait HasMemoryXilinxZCU102MIGBundle { 20 | val xilinxzcu102mig: XilinxZCU102MIGIO 21 | def connectXilinxZCU102MIGToPads(pads: XilinxZCU102MIGPads): Unit = { 22 | pads <> xilinxzcu102mig 23 | } 24 | } 25 | 26 | trait HasMemoryXilinxZCU102MIGModuleImp extends LazyModuleImp 27 | with HasMemoryXilinxZCU102MIGBundle { 28 | val outer: HasMemoryXilinxZCU102MIG 29 | val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) 30 | require (ranges.size == 1, "DDR range must be contiguous") 31 | val depth = ranges.head.size 32 | val xilinxzcu102mig = IO(new XilinxZCU102MIGIO(depth)) 33 | 34 | xilinxzcu102mig <> outer.xilinxzcu102mig.module.io.port 35 | } 36 | 37 | /* 38 | Copyright 2016 SiFive, Inc. 39 | 40 | Licensed under the Apache License, Version 2.0 (the "License"); 41 | you may not use this file except in compliance with the License. 42 | You may obtain a copy of the License at 43 | 44 | http://www.apache.org/licenses/LICENSE-2.0 45 | 46 | Unless required by applicable law or agreed to in writing, software 47 | distributed under the License is distributed on an "AS IS" BASIS, 48 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 49 | See the License for the specific language governing permissions and 50 | limitations under the License. 51 | */ 52 | -------------------------------------------------------------------------------- /src/main/scala/ip/altera/alterapll.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.altera 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import chisel3.util.HasBlackBoxInline 6 | import freechips.rocketchip.util.ElaborationArtefacts 7 | import sifive.fpgashells.clocks._ 8 | 9 | class AlteraPLL(c : PLLParameters) extends BlackBox with PLLInstance { 10 | val io = IO(new Bundle { 11 | val refclk = Input(Clock()) 12 | val outclk_0 = if (c.req.size >= 1) Some(Output(Clock())) else None 13 | val outclk_1 = if (c.req.size >= 2) Some(Output(Clock())) else None 14 | val outclk_2 = if (c.req.size >= 3) Some(Output(Clock())) else None 15 | val outclk_3 = if (c.req.size >= 4) Some(Output(Clock())) else None 16 | val outclk_4 = if (c.req.size >= 5) Some(Output(Clock())) else None 17 | val outclk_5 = if (c.req.size >= 6) Some(Output(Clock())) else None 18 | val outclk_6 = if (c.req.size >= 7) Some(Output(Clock())) else None 19 | val outclk_7 = if (c.req.size >= 8) Some(Output(Clock())) else None 20 | val outclk_8 = if (c.req.size >= 9) Some(Output(Clock())) else None 21 | val rst = Input(Bool()) 22 | val locked = Output(Bool()) 23 | }) 24 | 25 | val moduleName = c.name 26 | override def desiredName = c.name 27 | 28 | def getClocks = Seq() ++ io.outclk_0 ++ io.outclk_1 ++ 29 | io.outclk_2 ++ io.outclk_3 ++ 30 | io.outclk_4 ++ io.outclk_5 ++ 31 | io.outclk_6 ++ io.outclk_7 ++ 32 | io.outclk_8 33 | def getInput = io.refclk 34 | def getReset = Some(io.rst) 35 | def getLocked = io.locked 36 | 37 | def getClockNames = Seq.tabulate (c.req.size) { i => 38 | s"${c.name}/${c.name}_0/pll_inst_0/OUT${i}" 39 | } 40 | 41 | val outputs = c.req.zipWithIndex.map { case (r, i) => 42 | s""" \"--component-param=gui_output_clock_frequency${i}=${r.freqMHz}\" \\ 43 | | \"--component-param=gui_phase_shift${i}=${r.phaseDeg}\" \\ 44 | | \"--component-param=gui_duty_cycle${i}=${r.dutyCycle}\" \\""".stripMargin 45 | }.mkString 46 | 47 | ElaborationArtefacts.add(s"${moduleName}.quartus.tcl", 48 | s"""exec -ignorestderr ip-generate \"--output-directory=.\" \\ 49 | | \"--file-set=QUARTUS_SYNTH\" \\ 50 | | \"--component-name=altera_pll\" \\ 51 | | \"--output-name=${c.name}\" \\ 52 | | \"--system-info=DEVICE_FAMILY=Cyclone V\" \\ 53 | | \"--component-param=gui_number_of_clocks=${c.req.size.toString}\" \\ 54 | | \"--component-param=gui_reference_clock_frequency=${c.input.freqMHz.toString}\" \\ 55 | |${outputs} 56 | | 57 | |set_global_assignment -name QIP_FILE ${c.name}.qip 58 | |set_global_assignment -name VERILOG_FILE ${c.name}.v""".stripMargin) 59 | } 60 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/corejtagdebug/corejtagdebug.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.corejtagdebug 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi DirectCore IP block Actel:DirectCore:COREJTAGDEBUG:2.0.100 8 | 9 | trait CoreJtagDebugIOJTAGPads extends Bundle { 10 | 11 | val TCK = Input(Clock()) 12 | val TDI = Input(Bool()) 13 | val TMS = Input(Bool()) 14 | val TRSTB = Input(Bool()) 15 | val TDO = Output(Bool()) 16 | } 17 | 18 | trait CoreJtagDebugIOTarget extends Bundle { 19 | 20 | val TGT_TCK = Output(Clock()) 21 | val TGT_TDI = Output(Bool()) 22 | val TGT_TMS = Output(Bool()) 23 | val TGT_TRST = Output(Bool()) 24 | val TGT_TDO = Input(Bool()) 25 | } 26 | 27 | //scalastyle:off 28 | //turn off linter: blackbox name must match verilog module 29 | class CoreJtagDebugBlock(implicit val p:Parameters) extends BlackBox 30 | { 31 | override def desiredName = "corejtagdebug_wrapper" 32 | 33 | val io = IO(new CoreJtagDebugIOJTAGPads with CoreJtagDebugIOTarget { 34 | // chain inputs 35 | val UTDO_IN_0 = Input(Bool()) 36 | val UTDO_IN_1 = Input(Bool()) 37 | val UTDO_IN_2 = Input(Bool()) 38 | val UTDO_IN_3 = Input(Bool()) 39 | val UTDODRV_0 = Input(Bool()) 40 | val UTDODRV_1 = Input(Bool()) 41 | val UTDODRV_2 = Input(Bool()) 42 | val UTDODRV_3 = Input(Bool()) 43 | 44 | // chain outputs 45 | val UTDI_OUT = Output(Bool()) 46 | val URSTB_OUT = Output(Bool()) 47 | val UIREG_OUT = Output(Bits(8.W)) 48 | val UDRUPD_OUT = Output(Bool()) 49 | val UDRSH_OUT = Output(Bool()) 50 | val UDRCK_OUT = Output(Bool()) 51 | val UDRCAP_OUT = Output(Bool()) 52 | }) 53 | 54 | ElaborationArtefacts.add( 55 | "Libero.corejtagdebug.tcl", 56 | """ 57 | create_design -id Actel:DirectCore:COREJTAGDEBUG:2.0.100 -design_name {corejtagdebug_wrapper} -config_file {} -params {} -inhibit_configurator 0 58 | open_smartdesign -design {corejtagdebug_wrapper} 59 | configure_design -component {corejtagdebug_wrapper} -library {} 60 | configure_vlnv_instance -component {corejtagdebug_wrapper} -library {} -name {corejtagdebug_wrapper_0} -params {"IR_CODE:0x55" "ACTIVE_HIGH_TGT_RESET:1"} -validate_rules 0 61 | fix_vlnv_instance -component {corejtagdebug_wrapper} -library {} -name {corejtagdebug_wrapper_0} 62 | open_smartdesign -design {corejtagdebug_wrapper} 63 | configure_design -component {corejtagdebug_wrapper} -library {} 64 | """ 65 | ) 66 | 67 | } 68 | //scalastyle:on 69 | 70 | /* 71 | Copyright 2016 SiFive, Inc. 72 | 73 | Licensed under the Apache License, Version 2.0 (the "License"); 74 | you may not use this file except in compliance with the License. 75 | You may obtain a copy of the License at 76 | 77 | http://www.apache.org/licenses/LICENSE-2.0 78 | 79 | Unless required by applicable law or agreed to in writing, software 80 | distributed under the License is distributed on an "AS IS" BASIS, 81 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 82 | See the License for the specific language governing permissions and 83 | limitations under the License. 84 | */ 85 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi 2 | 3 | import chisel3._ 4 | 5 | 6 | //======================================================================== 7 | // This file contains common devices for Microsemi PolarFire FPGAs. 8 | //======================================================================== 9 | 10 | //------------------------------------------------------------------------- 11 | // Clock network macro 12 | //------------------------------------------------------------------------- 13 | 14 | class CLKBUF() extends BlackBox 15 | { 16 | val io = IO(new Bundle{ 17 | val PAD = Input(Clock()) 18 | val Y = Output(Clock()) 19 | }) 20 | } 21 | 22 | class CLKINT() extends BlackBox 23 | { 24 | val io = IO(new Bundle{ 25 | val A = Input(Clock()) 26 | val Y = Output(Clock()) 27 | }) 28 | } 29 | 30 | class ICB_CLKINT() extends BlackBox 31 | { 32 | val io = IO(new Bundle{ 33 | val A = Input(Clock()) 34 | val Y = Output(Clock()) 35 | }) 36 | } 37 | 38 | /* 39 | Copyright 2016 SiFive, Inc. 40 | 41 | Licensed under the Apache License, Version 2.0 (the "License"); 42 | you may not use this file except in compliance with the License. 43 | You may obtain a copy of the License at 44 | 45 | http://www.apache.org/licenses/LICENSE-2.0 46 | 47 | Unless required by applicable law or agreed to in writing, software 48 | distributed under the License is distributed on an "AS IS" BASIS, 49 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 50 | See the License for the specific language governing permissions and 51 | limitations under the License. 52 | */ 53 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_ccc/PolarFireCCC.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfireccc 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import sifive.fpgashells.clocks._ 6 | 7 | case class PolarFireCCCParameters( 8 | name: String, 9 | pll_in_freq: Double = 50, 10 | gl0Enabled: Boolean = false, 11 | gl1Enabled: Boolean = false, 12 | gl2Enabled: Boolean = false, 13 | gl3Enabled: Boolean = false, 14 | gl0_0_out_freq: Double = 111.111, 15 | gl1_0_out_freq: Double = 111.111, 16 | gl2_0_out_freq: Double = 111.111, 17 | gl3_0_out_freq: Double = 111.111, 18 | gl0_0_pll_phase: Double = 0, 19 | gl1_0_pll_phase: Double = 0, 20 | gl2_0_pll_phase: Double = 0, 21 | gl3_0_pll_phase: Double = 0, 22 | feedback: Boolean = false 23 | ) 24 | 25 | // Black Box for Microsemi PolarFire Clock Conditioning Circuit (CCC) Actel:SgCore:PF_CCC:1.0.112 26 | class PolarFireCCCIOPads(c : PLLParameters) extends Bundle { 27 | val REF_CLK_0 = Input(Clock()) 28 | val OUT0_FABCLK_0 = if (c.req.size >= 1) Some(Output(Clock())) else None 29 | val OUT1_FABCLK_0 = if (c.req.size >= 2) Some(Output(Clock())) else None 30 | val OUT2_FABCLK_0 = if (c.req.size >= 3) Some(Output(Clock())) else None 31 | val OUT3_FABCLK_0 = if (c.req.size >= 4) Some(Output(Clock())) else None 32 | val PLL_LOCK_0 = Output(Bool()) 33 | } 34 | 35 | //scalastyle:off 36 | //turn off linter: blackbox name must match verilog module 37 | class PolarFireCCC(c : PLLParameters) extends BlackBox with PLLInstance { 38 | val moduleName = c.name 39 | override def desiredName = c.name 40 | 41 | val io = IO(new PolarFireCCCIOPads(c)) 42 | def getInput = io.REF_CLK_0 43 | def getReset = None 44 | def getLocked = io.PLL_LOCK_0 45 | def getClocks = Seq() ++ io.OUT0_FABCLK_0 ++ io.OUT1_FABCLK_0 ++ 46 | io.OUT2_FABCLK_0 ++ io.OUT3_FABCLK_0 47 | 48 | def getClockNames = Seq.tabulate (c.req.size) { i => 49 | s"${c.name}/${c.name}_0/pll_inst_0/OUT${i}" 50 | } 51 | 52 | val used = Seq.tabulate(4) { i => 53 | s" GL${i}_0_IS_USED:${i < c.req.size} \\\n" 54 | }.mkString 55 | 56 | val outputs = c.req.zipWithIndex.map { case (req, i) => 57 | s""" GL${i}_0_OUT_FREQ:${req.freqMHz} \\ 58 | | GL${i}_0_PLL_PHASE:${req.phaseDeg} \\ 59 | |""".stripMargin 60 | }.mkString 61 | 62 | // !!! work-around libero bug 63 | // val feedback = if (c.input.feedback) "External" else "Post-VCO" 64 | val feedback = "Post-VCO" 65 | 66 | ElaborationArtefacts.add(s"${moduleName}.libero.tcl", 67 | s"""create_design -id Actel:SgCore:PF_CCC:1.0.115 -design_name {${moduleName}} -config_file {} -params {} -inhibit_configurator 0 68 | |open_smartdesign -design {${moduleName}} 69 | |configure_design -component {${moduleName}} -library {} 70 | |configure_vlnv_instance -component {${moduleName}} -library {} -name {${moduleName}_0} -validate_rules 0 -params { \\ 71 | | PLL_IN_FREQ_0:${c.input.freqMHz} \\ 72 | | PLL_FEEDBACK_MODE_0:${feedback} \\ 73 | |${used}${outputs}} 74 | |fix_vlnv_instance -component {${moduleName}} -library {} -name {${moduleName}_0} 75 | |open_smartdesign -design {${moduleName}} 76 | |configure_design -component {${moduleName}} -library {} 77 | |""".stripMargin) 78 | } 79 | 80 | /* 81 | Copyright 2016 SiFive, Inc. 82 | 83 | Licensed under the Apache License, Version 2.0 (the "License"); 84 | you may not use this file except in compliance with the License. 85 | You may obtain a copy of the License at 86 | 87 | http://www.apache.org/licenses/LICENSE-2.0 88 | 89 | Unless required by applicable law or agreed to in writing, software 90 | distributed under the License is distributed on an "AS IS" BASIS, 91 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 92 | See the License for the specific language governing permissions and 93 | limitations under the License. 94 | */ 95 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_clock_divider/PolarFireClockDivider.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfireclockdivider 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Actel:SgCore:PF_CLK_DIV:1.0.101 8 | 9 | trait PolarFireClockDividerIOPads extends Bundle { 10 | 11 | val CLK_OUT = Output(Clock()) 12 | val CLK_IN = Input(Clock()) 13 | } 14 | 15 | //scalastyle:off 16 | //turn off linter: blackbox name must match verilog module 17 | class PolarFireClockDivider(implicit val p:Parameters) extends BlackBox 18 | { 19 | override def desiredName = "pf_clk_divider" 20 | 21 | val io = IO(new PolarFireClockDividerIOPads {}) 22 | 23 | ElaborationArtefacts.add( 24 | "Libero.polarfire_clock_divider.libero.tcl", 25 | """ 26 | create_design -id Actel:SgCore:PF_CLK_DIV:1.0.101 -design_name {pf_clk_divider} -config_file {} -params {} -inhibit_configurator 0 27 | open_smartdesign -design {pf_clk_divider} 28 | configure_design -component {pf_clk_divider} -library {} 29 | configure_vlnv_instance -component {pf_clk_divider} -library {} -name {pf_clk_divider_0} -params {"DIVIDER:2"} -validate_rules 0 30 | fix_vlnv_instance -component {pf_clk_divider} -library {} -name {pf_clk_divider_0} 31 | open_smartdesign -design {pf_clk_divider} 32 | configure_design -component {pf_clk_divider} -library {} 33 | """ 34 | ) 35 | } 36 | //scalastyle:on 37 | 38 | /* 39 | Copyright 2016 SiFive, Inc. 40 | 41 | Licensed under the Apache License, Version 2.0 (the "License"); 42 | you may not use this file except in compliance with the License. 43 | You may obtain a copy of the License at 44 | 45 | http://www.apache.org/licenses/LICENSE-2.0 46 | 47 | Unless required by applicable law or agreed to in writing, software 48 | distributed under the License is distributed on an "AS IS" BASIS, 49 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 50 | See the License for the specific language governing permissions and 51 | limitations under the License. 52 | */ 53 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_dll/PolarFireDLL.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfiredll 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi PolarFire Delay Locked Loop (DLL) Actel:SgCore:PF_CCC:1.0.112 8 | 9 | class PolarFireDLLIOPads extends Bundle { 10 | 11 | val DLL_FB_CLK = Input(Clock()) 12 | val DLL_REF_CLK = Input(Clock()) 13 | val DLL_CLK_0_FABCLK = Output(Clock()) 14 | val DLL_LOCK = Output(Bool()) 15 | } 16 | 17 | //scalastyle:off 18 | //turn off linter: blackbox name must match verilog module 19 | class PolarFireDLL(name: String)(implicit val p:Parameters) extends BlackBox 20 | { 21 | val modulename = name 22 | override def desiredName = name 23 | 24 | val io = IO(new PolarFireDLLIOPads) 25 | 26 | ElaborationArtefacts.add( 27 | "AddIPInstance." ++ modulename ++".libero.tcl", 28 | """ 29 | create_design -id Actel:SgCore:PF_CCC:1.0.115 -design_name {""" ++ modulename ++"""} -config_file {} -params {} -inhibit_configurator 0 30 | open_smartdesign -design {""" ++ modulename ++"""} 31 | configure_design -component {""" ++ modulename ++"""} -library {} 32 | configure_vlnv_instance -component {""" ++ modulename ++"""} -library {} -name {""" ++ modulename ++"""_0} \ 33 | -params {"DLL_ONLY_EN:true" \ 34 | "DLL_IN:125" \ 35 | "DLL_MODE:INJECTION_REM_MODE" \ 36 | "DLL_CLK_0_FABCLK_EN:true" \ 37 | } -validate_rules 0 38 | fix_vlnv_instance -component {""" ++ modulename ++"""} -library {} -name {""" ++ modulename ++"""_0} 39 | open_smartdesign -design {""" ++ modulename ++"""} 40 | configure_design -component {""" ++ modulename ++"""} -library {}""" 41 | ) 42 | } 43 | //scalastyle:on 44 | 45 | /* 46 | Copyright 2016 SiFive, Inc. 47 | 48 | Licensed under the Apache License, Version 2.0 (the "License"); 49 | you may not use this file except in compliance with the License. 50 | You may obtain a copy of the License at 51 | 52 | http://www.apache.org/licenses/LICENSE-2.0 53 | 54 | Unless required by applicable law or agreed to in writing, software 55 | distributed under the License is distributed on an "AS IS" BASIS, 56 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 57 | See the License for the specific language governing permissions and 58 | limitations under the License. 59 | */ 60 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_glitchless_mux/PolarFireGlitchlessMux.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfireglitchlessmux 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box forMicrosemi PolarFire glitchless mux Actel:SgCore:PF_NGMUX:1.0.101 8 | 9 | trait PolarFireGlitchlessMuxIOPads extends Bundle { 10 | 11 | val CLK_OUT = Output(Clock()) 12 | val CLK0 = Input(Clock()) 13 | val CLK1 = Input(Clock()) 14 | val SEL = Input(Bool()) 15 | } 16 | 17 | //scalastyle:off 18 | //turn off linter: blackbox name must match verilog module 19 | class PolarFireGlitchlessMux(implicit val p:Parameters) extends BlackBox 20 | { 21 | override def desiredName = "pf_glitchless_mux" 22 | 23 | val io = IO(new PolarFireGlitchlessMuxIOPads {}) 24 | 25 | ElaborationArtefacts.add( 26 | "Libero.polarfire_glitchless_mux.libero.tcl", 27 | """ 28 | create_design -id Actel:SgCore:PF_NGMUX:1.0.101 -design_name {pf_glitchless_mux} -config_file {} -params {} -inhibit_configurator 0 29 | open_smartdesign -design {pf_glitchless_mux} 30 | configure_design -component {pf_glitchless_mux} -library {} 31 | fix_vlnv_instance -component {pf_glitchless_mux} -library {} -name {pf_glitchless_mux_0} 32 | open_smartdesign -design {pf_glitchless_mux} 33 | configure_design -component {pf_glitchless_mux} -library {} 34 | """ 35 | ) 36 | } 37 | //scalastyle:on 38 | 39 | /* 40 | Copyright 2016 SiFive, Inc. 41 | 42 | Licensed under the Apache License, Version 2.0 (the "License"); 43 | you may not use this file except in compliance with the License. 44 | You may obtain a copy of the License at 45 | 46 | http://www.apache.org/licenses/LICENSE-2.0 47 | 48 | Unless required by applicable law or agreed to in writing, software 49 | distributed under the License is distributed on an "AS IS" BASIS, 50 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 51 | See the License for the specific language governing permissions and 52 | limitations under the License. 53 | */ 54 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_init_monitor/PolarFireInitMonitor.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfireinitmonitor 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi PolarFire Clock Conditioning Circuit (CCC) Actel:SgCore:PF_INIT_MONITOR:2.0.103 8 | 9 | trait PolarFireInitMonitorIOPads { 10 | val DEVICE_INIT_DONE = Output(Bool()) 11 | val FABRIC_POR_N = Output(Bool()) 12 | val PCIE_INIT_DONE = Output(Bool()) 13 | val SRAM_INIT_DONE = Output(Bool()) 14 | val USRAM_INIT_DONE = Output(Bool()) 15 | } 16 | 17 | class PolarFireInitMonitor(implicit val p:Parameters) extends BlackBox 18 | { 19 | override def desiredName = "polarfire_init_monitor" 20 | 21 | val io = IO(new Bundle with PolarFireInitMonitorIOPads) 22 | 23 | ElaborationArtefacts.add(s"${desiredName}.libero.tcl", 24 | s"""create_design -id Actel:SgCore:PF_INIT_MONITOR:2.0.103 -design_name {polarfire_init_monitor} -config_file {} -params {} -inhibit_configurator 0 25 | |open_smartdesign -design {polarfire_init_monitor} 26 | |configure_design -component {polarfire_init_monitor} -library {} 27 | |fix_vlnv_instance -component {polarfire_init_monitor} -library {} -name {polarfire_init_monitor_0} 28 | |open_smartdesign -design {polarfire_init_monitor} 29 | |configure_design -component {polarfire_init_monitor} -library {} 30 | |""".stripMargin) 31 | } 32 | 33 | /* 34 | Copyright 2016 SiFive, Inc. 35 | 36 | Licensed under the Apache License, Version 2.0 (the "License"); 37 | you may not use this file except in compliance with the License. 38 | You may obtain a copy of the License at 39 | 40 | http://www.apache.org/licenses/LICENSE-2.0 41 | 42 | Unless required by applicable law or agreed to in writing, software 43 | distributed under the License is distributed on an "AS IS" BASIS, 44 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 45 | See the License for the specific language governing permissions and 46 | limitations under the License. 47 | */ 48 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_oscillator/PolarFireOscillator.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfire_oscillator 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi PolarFire internal oscillator Actel:SgCore:PF_OSC:1.0.102 8 | 9 | trait PolarFireOscillatorIOPads extends Bundle { 10 | 11 | val RCOSC_160MHZ_GL = Output(Clock()) 12 | } 13 | 14 | //scalastyle:off 15 | //turn off linter: blackbox name must match verilog module 16 | class PolarFireOscillator(implicit val p:Parameters) extends BlackBox 17 | { 18 | override def desiredName = "pf_oscillator" 19 | 20 | val io = IO(new PolarFireOscillatorIOPads {}) 21 | 22 | ElaborationArtefacts.add( 23 | "Libero.polarfire_oscillator.libero.tcl", 24 | """ 25 | create_design -id Actel:SgCore:PF_OSC:1.0.102 -design_name {pf_oscillator} -config_file {} -params {} -inhibit_configurator 0 26 | open_smartdesign -design {pf_oscillator} 27 | configure_design -component {pf_oscillator} -library {} 28 | fix_vlnv_instance -component {pf_oscillator} -library {} -name {pf_oscillator_0} 29 | open_smartdesign -design {pf_oscillator} 30 | configure_design -component {pf_oscillator} -library {} """ 31 | ) 32 | } 33 | //scalastyle:on 34 | 35 | /* 36 | Copyright 2016 SiFive, Inc. 37 | 38 | Licensed under the Apache License, Version 2.0 (the "License"); 39 | you may not use this file except in compliance with the License. 40 | You may obtain a copy of the License at 41 | 42 | http://www.apache.org/licenses/LICENSE-2.0 43 | 44 | Unless required by applicable law or agreed to in writing, software 45 | distributed under the License is distributed on an "AS IS" BASIS, 46 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 47 | See the License for the specific language governing permissions and 48 | limitations under the License. 49 | */ 50 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_reset/PolarFireReset.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfirereset 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi PolarFire IP block Actel:DirectCore:CORERESET_PF:2.1.100 8 | 9 | trait PolarFireResetIOPads extends Bundle { 10 | 11 | val CLK = Input(Clock()) 12 | val EXT_RST_N = Input(Bool()) 13 | val FF_US_RESTORE = Input(Bool()) 14 | val INIT_DONE = Input(Bool()) 15 | val PLL_LOCK = Input(Bool()) 16 | val SS_BUSY = Input(Bool()) 17 | val FABRIC_RESET_N = Output(Bool()) 18 | } 19 | 20 | //scalastyle:off 21 | //turn off linter: blackbox name must match verilog module 22 | class PolarFireReset(implicit val p:Parameters) extends BlackBox 23 | { 24 | override def desiredName = "polarfire_reset" 25 | 26 | val io = IO(new PolarFireResetIOPads {}) 27 | 28 | 29 | ElaborationArtefacts.add( 30 | "Libero.polarfire_reset.libero.tcl", 31 | """ 32 | create_design -id Actel:DirectCore:CORERESET_PF:2.1.100 -design_name {polarfire_reset} -config_file {} -params {} -inhibit_configurator 0 33 | open_smartdesign -design {polarfire_reset} 34 | configure_design -component {polarfire_reset} -library {} 35 | fix_vlnv_instance -component {polarfire_reset} -library {} -name {polarfire_reset_0} 36 | open_smartdesign -design {polarfire_reset} 37 | configure_design -component {polarfire_reset} -library {}""" 38 | ) 39 | } 40 | //scalastyle:on 41 | 42 | /* 43 | Copyright 2016 SiFive, Inc. 44 | 45 | Licensed under the Apache License, Version 2.0 (the "License"); 46 | you may not use this file except in compliance with the License. 47 | You may obtain a copy of the License at 48 | 49 | http://www.apache.org/licenses/LICENSE-2.0 50 | 51 | Unless required by applicable law or agreed to in writing, software 52 | distributed under the License is distributed on an "AS IS" BASIS, 53 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 54 | See the License for the specific language governing permissions and 55 | limitations under the License. 56 | */ 57 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_tx_pll/PolarFireTxPLL.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfiretxpll 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi:SgCore:PF_TX_PLL:1.0.109 8 | 9 | trait PolarFireTxPLLIOPads extends Bundle { 10 | 11 | val REF_CLK = Input(Clock()) 12 | val BIT_CLK = Output(Clock()) 13 | val CLK_125 = Output(Clock()) 14 | val REF_CLK_TO_LANE = Output(Clock()) 15 | val LOCK = Output(Bool()) 16 | val PLL_LOCK = Output(Bool()) 17 | } 18 | 19 | //scalastyle:off 20 | //turn off linter: blackbox name must match verilog module 21 | class PolarFireTxPLL(implicit val p:Parameters) extends BlackBox 22 | { 23 | override def desiredName = "transmit_pll" 24 | 25 | val io = IO(new PolarFireTxPLLIOPads {}) 26 | 27 | ElaborationArtefacts.add( 28 | "Libero.polarfire_tx_pll.libero.tcl", 29 | """ 30 | create_design -id Actel:SgCore:PF_TX_PLL:2.0.002 -design_name {transmit_pll} -config_file {} -params {} -inhibit_configurator 0 31 | open_smartdesign -design {transmit_pll} 32 | configure_design -component {transmit_pll} -library {} 33 | configure_vlnv_instance -component {transmit_pll} -library {} -name {transmit_pll_0} -params {"TxPLL_REF:100" "TxPLL_OUT:2500"} -validate_rules 0 34 | fix_vlnv_instance -component {transmit_pll} -library {} -name {transmit_pll_0} 35 | open_smartdesign -design {transmit_pll} 36 | configure_design -component {transmit_pll} -library {} 37 | """ 38 | ) 39 | 40 | } 41 | //scalastyle:on 42 | 43 | /* 44 | Copyright 2016 SiFive, Inc. 45 | 46 | Licensed under the Apache License, Version 2.0 (the "License"); 47 | you may not use this file except in compliance with the License. 48 | You may obtain a copy of the License at 49 | 50 | http://www.apache.org/licenses/LICENSE-2.0 51 | 52 | Unless required by applicable law or agreed to in writing, software 53 | distributed under the License is distributed on an "AS IS" BASIS, 54 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 55 | See the License for the specific language governing permissions and 56 | limitations under the License. 57 | */ 58 | -------------------------------------------------------------------------------- /src/main/scala/ip/microsemi/polarfire_xcvr_refclk/PolarFireTransceiverRefClk.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.microsemi.polarfirexcvrrefclk 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.util.ElaborationArtefacts 5 | import org.chipsalliance.cde.config._ 6 | 7 | // Black Box for Microsemi:SgCore:PF_XCVR_REF_CLK:1.0.103 8 | 9 | trait PolarFireTransceiverRefClkIOPads extends Bundle { 10 | 11 | val REF_CLK_PAD_P = Input(Bool()) 12 | val REF_CLK_PAD_N = Input(Bool()) 13 | val REF_CLK = Output(Clock()) 14 | val FAB_REF_CLK = Output(Clock()) 15 | } 16 | 17 | //scalastyle:off 18 | //turn off linter: blackbox name must match verilog module 19 | class PolarFireTransceiverRefClk(implicit val p:Parameters) extends BlackBox 20 | { 21 | override def desiredName = "transceiver_refclk" 22 | 23 | val io = IO(new PolarFireTransceiverRefClkIOPads {}) 24 | 25 | ElaborationArtefacts.add( 26 | "Libero.polarfire_xcvr_refclk.libero.tcl", 27 | """ 28 | create_design -id Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -design_name {transceiver_refclk} -config_file {} -params {} -inhibit_configurator 0 29 | open_smartdesign -design {transceiver_refclk} 30 | configure_design -component {transceiver_refclk} -library {} 31 | configure_vlnv_instance -component {transceiver_refclk} -library {} -name {transceiver_refclk_0} \ 32 | -params {"ENABLE_FAB_CLK_0:1" \ 33 | } -validate_rules 0 34 | 35 | fix_vlnv_instance -component {transceiver_refclk} -library {} -name {transceiver_refclk_0} 36 | open_smartdesign -design {transceiver_refclk} 37 | configure_design -component {transceiver_refclk} -library {} 38 | """ 39 | ) 40 | 41 | } 42 | //scalastyle:on 43 | 44 | /* 45 | Copyright 2016 SiFive, Inc. 46 | 47 | Licensed under the Apache License, Version 2.0 (the "License"); 48 | you may not use this file except in compliance with the License. 49 | You may obtain a copy of the License at 50 | 51 | http://www.apache.org/licenses/LICENSE-2.0 52 | 53 | Unless required by applicable law or agreed to in writing, software 54 | distributed under the License is distributed on an "AS IS" BASIS, 55 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 56 | See the License for the specific language governing permissions and 57 | limitations under the License. 58 | */ 59 | -------------------------------------------------------------------------------- /src/main/scala/ip/xilinx/bscan/bscan.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.xilinx.bscan2 2 | import chisel3._ 3 | import chisel3.experimental.ExtModule 4 | import chisel3.util._ 5 | 6 | object JTAGTUNNEL { 7 | def apply (DUT_TCK: Bool, DUT_TMS: Bool, DUT_TDI: Bool, DUT_TDO:Bool, DUT_TDO_en: Bool): Unit = { 8 | val inst_jtag_tunnel = Module(new JTAGTUNNEL()) 9 | DUT_TCK := inst_jtag_tunnel.jtag_tck.asBool 10 | DUT_TMS := inst_jtag_tunnel.jtag_tms 11 | DUT_TDI := inst_jtag_tunnel.jtag_tdi 12 | inst_jtag_tunnel.jtag_tdo := DUT_TDO 13 | inst_jtag_tunnel.jtag_tdo_en := DUT_TDO_en 14 | } 15 | } 16 | 17 | class BUFGCE extends ExtModule { 18 | val O = IO(Output(Bool())) 19 | val CE = IO(Input(Bool())) 20 | val I = IO(Input(Bool())) 21 | } 22 | 23 | class BSCANE2 extends ExtModule(Map("JTAG_CHAIN" -> 4)) { 24 | val TDO = IO(Input(Bool())) 25 | val CAPTURE = IO(Output(Bool())) 26 | val DRCK = IO(Output(Bool())) 27 | val RESET = IO(Output(Bool())) 28 | val RUNTEST = IO(Output(Bool())) 29 | val SEL = IO(Output(Bool())) 30 | val SHIFT = IO(Output(Bool())) 31 | val TCK = IO(Output(Bool())) 32 | val TDI = IO(Output(Bool())) 33 | val TMS = IO(Output(Bool())) 34 | val UPDATE = IO(Output(Bool())) 35 | } 36 | 37 | class JTAGTUNNEL extends Module { 38 | val jtag_tck: Clock = IO(Output(Clock())) 39 | val jtag_tms: Bool = IO(Output(Bool())) 40 | val jtag_tdi: Bool = IO(Output(Bool())) 41 | val jtag_tdo: Bool = IO(Input(Bool())) 42 | val jtag_tdo_en: Bool = IO(Input(Bool())) 43 | 44 | val bscane2: BSCANE2 = Module(new BSCANE2) 45 | jtag_tdi := bscane2.TDI 46 | bscane2.TDO := Mux(jtag_tdo_en, jtag_tdo, true.B) 47 | val bufgce = Module(new BUFGCE) 48 | bufgce.I := bscane2.TCK 49 | bufgce.CE := bscane2.SEL 50 | jtag_tck := bufgce.O.asClock 51 | 52 | val posClock: Clock = bscane2.TCK.asClock 53 | val negClock: Clock = (!bscane2.TCK).asClock 54 | 55 | val tdiRegisterWire = Wire(Bool()) 56 | val shiftCounterWire = Wire(UInt(7.W)) 57 | withReset(!bscane2.SHIFT) { 58 | withClock(posClock) { 59 | val shiftCounter = RegInit(0.U(7.W)) 60 | val posCounter = RegInit(0.U(8.W)) 61 | val tdiRegister = RegInit(false.B) 62 | posCounter := posCounter + 1.U 63 | when(posCounter >= 1.U && posCounter <= 7.U) { 64 | shiftCounter := Cat(bscane2.TDI, shiftCounter.head(6)) 65 | } 66 | when(posCounter === 0.U) { 67 | tdiRegister := !bscane2.TDI 68 | } 69 | tdiRegisterWire := tdiRegister 70 | shiftCounterWire := shiftCounter 71 | } 72 | withClock(negClock) { 73 | val negCounter = RegInit(0.U(8.W)) 74 | negCounter := negCounter + 1.U 75 | jtag_tms := MuxLookup(negCounter, false.B)(Array( 76 | 4.U -> tdiRegisterWire, 77 | 5.U -> true.B, 78 | shiftCounterWire + 7.U -> true.B, 79 | shiftCounterWire + 8.U -> true.B) 80 | ) 81 | } 82 | } 83 | } 84 | 85 | /* 86 | Copyright 2016 SiFive, Inc. 87 | 88 | Licensed under the Apache License, Version 2.0 (the "License"); 89 | you may not use this file except in compliance with the License. 90 | You may obtain a copy of the License at 91 | 92 | http://www.apache.org/licenses/LICENSE-2.0 93 | 94 | Unless required by applicable law or agreed to in writing, software 95 | distributed under the License is distributed on an "AS IS" BASIS, 96 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 97 | See the License for the specific language governing permissions and 98 | limitations under the License. 99 | */ 100 | -------------------------------------------------------------------------------- /src/main/scala/ip/xilinx/ibufds_gte2/ibufds_gte2.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.xilinx.ibufds_gte2 2 | 3 | import chisel3._ 4 | 5 | //IP : xilinx unisim IBUFDS_GTE2 6 | //Differential Signaling Input Buffer 7 | //unparameterized 8 | 9 | class IBUFDS_GTE2 extends BlackBox { 10 | val io = IO(new Bundle { 11 | val O = Output(Bool()) 12 | val ODIV2 = Output(Bool()) 13 | val CEB = Input(Bool()) 14 | val I = Input(Bool()) 15 | val IB = Input(Bool()) 16 | }) 17 | } 18 | 19 | /* 20 | Copyright 2016 SiFive, Inc. 21 | 22 | Licensed under the Apache License, Version 2.0 (the "License"); 23 | you may not use this file except in compliance with the License. 24 | You may obtain a copy of the License at 25 | 26 | http://www.apache.org/licenses/LICENSE-2.0 27 | 28 | Unless required by applicable law or agreed to in writing, software 29 | distributed under the License is distributed on an "AS IS" BASIS, 30 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | See the License for the specific language governing permissions and 32 | limitations under the License. 33 | */ 34 | -------------------------------------------------------------------------------- /src/main/scala/ip/xilinx/xxv_ethernet/nfmac10g.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.ip.xilinx.xxv_ethernet 2 | 3 | import chisel3._ 4 | 5 | class nfmac10g extends BlackBox { 6 | val io = IO(new Bundle { 7 | val tx_clk0 = Input(Clock()) 8 | val rx_clk0 = Input(Clock()) 9 | val reset = Input(Reset()) 10 | val tx_dcm_locked = Input(Bool()) 11 | val rx_dcm_locked = Input(Bool()) 12 | 13 | // XGMII 14 | val xgmii_txd = Output(UInt(64.W)) 15 | val xgmii_txc = Output(UInt(8.W)) 16 | val xgmii_rxd = Input (UInt(64.W)) 17 | val xgmii_rxc = Input (UInt(8.W)) 18 | 19 | // Tx AXIS 20 | val tx_axis_aresetn = Input (Reset()) 21 | val tx_axis_tready = Output(Bool()) 22 | val tx_axis_tvalid = Input (Bool()) 23 | val tx_axis_tlast = Input (Bool()) 24 | val tx_axis_tdata = Input (UInt(64.W)) 25 | val tx_axis_tkeep = Input (UInt(8.W)) 26 | val tx_axis_tuser = Input (UInt(1.W)) 27 | 28 | // Rx AXIS 29 | val rx_axis_aresetn = Input (Reset()) 30 | val rx_axis_tvalid = Output(Bool()) 31 | val rx_axis_tlast = Output(Bool()) 32 | val rx_axis_tdata = Output(UInt(64.W)) 33 | val rx_axis_tkeep = Output(UInt(8.W)) 34 | val rx_axis_tuser = Output(UInt(1.W)) 35 | 36 | // Unused by nfmac10g 37 | val tx_ifg_delay = Input(UInt(8.W)) 38 | val pause_val = Input(UInt(16.W)) 39 | val pause_req = Input(Bool()) 40 | val tx_configuration_vector = Input(UInt(80.W)) 41 | val rx_configuration_vector = Input(UInt(80.W)) 42 | val status_vector = Output(UInt(2.W)) 43 | val tx_statistics_vector = Output(UInt(26.W)) 44 | val tx_statistics_valid = Output(Bool()) 45 | val rx_statistics_vector = Output(UInt(30.W)) 46 | val rx_statistics_valid = Output(Bool()) 47 | }) 48 | } 49 | 50 | /* 51 | Copyright 2016 SiFive, Inc. 52 | 53 | Licensed under the Apache License, Version 2.0 (the "License"); 54 | you may not use this file except in compliance with the License. 55 | You may obtain a copy of the License at 56 | 57 | http://www.apache.org/licenses/LICENSE-2.0 58 | 59 | Unless required by applicable law or agreed to in writing, software 60 | distributed under the License is distributed on an "AS IS" BASIS, 61 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 62 | See the License for the specific language governing permissions and 63 | limitations under the License. 64 | */ 65 | -------------------------------------------------------------------------------- /src/main/scala/shell/ButtonOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import org.chipsalliance.cde.config._ 6 | 7 | case class ButtonShellInput( 8 | header: String = "", 9 | number: Int = 0) 10 | 11 | case class ButtonDesignInput()(implicit val p: Parameters) 12 | case class ButtonOverlayOutput(but: ModuleValue[Bool]) 13 | case object ButtonOverlayKey extends Field[Seq[DesignPlacer[ButtonDesignInput, ButtonShellInput, ButtonOverlayOutput]]](Nil) 14 | trait ButtonShellPlacer[Shell] extends ShellPlacer[ButtonDesignInput, ButtonShellInput, ButtonOverlayOutput] 15 | 16 | abstract class ButtonPlacedOverlay( 17 | val name: String, val di: ButtonDesignInput, si:ButtonShellInput) 18 | extends IOPlacedOverlay[Bool, ButtonDesignInput, ButtonShellInput, ButtonOverlayOutput] 19 | { 20 | implicit val p = di.p 21 | 22 | def ioFactory = Input(Bool()) 23 | 24 | val buttonWire = shell { InModuleBody(Wire(Bool())) } 25 | def overlayOutput = ButtonOverlayOutput(but = buttonWire) 26 | } 27 | 28 | /* 29 | Copyright 2016 SiFive, Inc. 30 | 31 | Licensed under the Apache License, Version 2.0 (the "License"); 32 | you may not use this file except in compliance with the License. 33 | You may obtain a copy of the License at 34 | 35 | http://www.apache.org/licenses/LICENSE-2.0 36 | 37 | Unless required by applicable law or agreed to in writing, software 38 | distributed under the License is distributed on an "AS IS" BASIS, 39 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | See the License for the specific language governing permissions and 41 | limitations under the License. 42 | */ 43 | -------------------------------------------------------------------------------- /src/main/scala/shell/CTSResetOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import org.chipsalliance.cde.config._ 5 | 6 | //Core-To-Shell Reset Overlay: No IOs, but passes a Bool into the shell to be orred into the pllReset, allowing core signals to reset the shell 7 | 8 | case class CTSResetShellInput() 9 | case class CTSResetDesignInput(rst: Bool)(implicit val p: Parameters) 10 | case class CTSResetOverlayOutput() 11 | case object CTSResetOverlayKey extends Field[Seq[DesignPlacer[CTSResetDesignInput, CTSResetShellInput, CTSResetOverlayOutput]]](Nil) 12 | trait CTSResetShellPlacer[Shell] extends ShellPlacer[CTSResetDesignInput, CTSResetShellInput, CTSResetOverlayOutput] 13 | 14 | abstract class CTSResetPlacedOverlay( 15 | val name: String, val di: CTSResetDesignInput, si: CTSResetShellInput) 16 | extends PlacedOverlay[CTSResetDesignInput, CTSResetShellInput, CTSResetOverlayOutput] 17 | { 18 | implicit val p = di.p 19 | 20 | def overlayOutput = CTSResetOverlayOutput() 21 | } 22 | 23 | /* 24 | Copyright 2016 SiFive, Inc. 25 | 26 | Licensed under the Apache License, Version 2.0 (the "License"); 27 | you may not use this file except in compliance with the License. 28 | You may obtain a copy of the License at 29 | 30 | http://www.apache.org/licenses/LICENSE-2.0 31 | 32 | Unless required by applicable law or agreed to in writing, software 33 | distributed under the License is distributed on an "AS IS" BASIS, 34 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 35 | See the License for the specific language governing permissions and 36 | limitations under the License. 37 | */ 38 | -------------------------------------------------------------------------------- /src/main/scala/shell/ChipLinkOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import freechips.rocketchip.tilelink._ 5 | import freechips.rocketchip.prci._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.chiplink._ 8 | import sifive.fpgashells.clocks._ 9 | 10 | case class ChipLinkShellInput( 11 | fmc: String = "") 12 | 13 | case class ChipLinkDesignInput( 14 | di: ChipLinkParams, 15 | txGroup: ClockGroupingNode, 16 | txData: ClockSinkNode, 17 | wrangler: ClockAdapterNode)( 18 | implicit val p: Parameters) 19 | 20 | case class ChipLinkOverlayOutput(node: TLNode) 21 | case object ChipLinkOverlayKey extends Field[Seq[DesignPlacer[ChipLinkDesignInput, ChipLinkShellInput, ChipLinkOverlayOutput]]](Nil) 22 | trait ChipLinkShellPlacer[Shell] extends ShellPlacer[ChipLinkDesignInput, ChipLinkShellInput, ChipLinkOverlayOutput] 23 | 24 | abstract class ChipLinkPlacedOverlay( 25 | val name: String, 26 | val di: ChipLinkDesignInput, 27 | val si: ChipLinkShellInput, 28 | val rxPhase: Double, 29 | val txPhase: Double) 30 | extends IOPlacedOverlay[WideDataLayerPort, ChipLinkDesignInput, ChipLinkShellInput, ChipLinkOverlayOutput] 31 | { 32 | implicit val p = di.p 33 | val freqMHz = di.txData.portParams.head.take.get.freqMHz 34 | val phaseDeg = di.txData.portParams.head.phaseDeg 35 | 36 | def fpgaReset = false 37 | val link = LazyModule(new ChipLink(di.di.copy(fpgaReset = fpgaReset))) 38 | val rxPLL = p(PLLFactoryKey)(feedback = true) 39 | val ioSink = shell { link.ioNode.makeSink() } 40 | val rxI = shell { ClockSourceNode(freqMHz = freqMHz, jitterPS = 100) } 41 | val rxGroup = shell { ClockGroup() } 42 | val rxO = shell { ClockSinkNode(freqMHz = freqMHz, phaseDeg = rxPhase) } 43 | val txClock = shell { ClockSinkNode(freqMHz = freqMHz, phaseDeg = phaseDeg + txPhase) } 44 | 45 | rxO := di.wrangler := rxGroup := rxPLL := rxI 46 | txClock := di.wrangler := di.txGroup 47 | 48 | def overlayOutput = ChipLinkOverlayOutput(node = link.node) 49 | def ioFactory = new WideDataLayerPort(ChipLinkParams(Nil,Nil)) 50 | 51 | shell { InModuleBody { 52 | val (rxOut, _) = rxO.in(0) 53 | val port = ioSink.bundle 54 | io <> port 55 | port.b2c.clk := rxOut.clock 56 | } } 57 | } 58 | 59 | /* 60 | Copyright 2016 SiFive, Inc. 61 | 62 | Licensed under the Apache License, Version 2.0 (the "License"); 63 | you may not use this file except in compliance with the License. 64 | You may obtain a copy of the License at 65 | 66 | http://www.apache.org/licenses/LICENSE-2.0 67 | 68 | Unless required by applicable law or agreed to in writing, software 69 | distributed under the License is distributed on an "AS IS" BASIS, 70 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 71 | See the License for the specific language governing permissions and 72 | limitations under the License. 73 | */ 74 | -------------------------------------------------------------------------------- /src/main/scala/shell/ClockOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.prci._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.fpgashells.clocks._ 8 | 9 | case class ClockInputShellInput() 10 | case class ClockOutputShellInput() 11 | case class ClockInputDesignInput()(implicit val p: Parameters) 12 | case class ClockOutputDesignInput()(implicit val p: Parameters) 13 | case class ClockInputOverlayOutput(node: ClockSourceNode) 14 | case class ClockOutputOverlayOutput(clock: ClockSinkNode) 15 | 16 | trait ClockInputShellPlacer[Shell] extends ShellPlacer[ClockInputDesignInput, ClockInputShellInput, ClockInputOverlayOutput] 17 | trait ClockOutputShellPlacer[Shell] extends ShellPlacer[ClockOutputDesignInput, ClockOutputShellInput, ClockOutputOverlayOutput] 18 | 19 | case object ClockInputOverlayKey extends Field[Seq[DesignPlacer[ClockInputDesignInput, ClockInputShellInput, ClockInputOverlayOutput]]](Nil) 20 | case object ClockOutputOverlayKey extends Field[Seq[DesignPlacer[ClockOutputDesignInput, ClockOutputShellInput, ClockOutputOverlayOutput]]](Nil) 21 | 22 | class LVDSClock extends Bundle 23 | { 24 | val p = Clock() 25 | val n = Clock() 26 | } 27 | 28 | abstract class LVDSClockInputPlacedOverlay( 29 | val name: String, val di: ClockInputDesignInput, val si: ClockInputShellInput) 30 | extends IOPlacedOverlay[LVDSClock, ClockInputDesignInput, ClockInputShellInput, ClockInputOverlayOutput] 31 | { 32 | implicit val p = di.p 33 | def node: ClockSourceNode 34 | 35 | def ioFactory = Input(new LVDSClock) 36 | 37 | val clock = shell { InModuleBody { 38 | val (bundle, edge) = node.out.head 39 | shell.sdc.addClock(name, io.p, edge.clock.get.freqMHz) 40 | bundle.clock 41 | } } 42 | def overlayOutput = ClockInputOverlayOutput(node) 43 | } 44 | 45 | 46 | abstract class SingleEndedClockInputPlacedOverlay( 47 | val name: String, val di: ClockInputDesignInput, val si: ClockInputShellInput) 48 | extends IOPlacedOverlay[Clock, ClockInputDesignInput, ClockInputShellInput, ClockInputOverlayOutput] 49 | { 50 | implicit val p = di.p 51 | def node: ClockSourceNode 52 | 53 | def ioFactory = Input(Clock()) 54 | 55 | val clock = shell { InModuleBody { 56 | val (bundle, edge) = node.out.head 57 | shell.sdc.addClock(name, io:Clock, edge.clock.get.freqMHz) 58 | bundle.clock 59 | } } 60 | def overlayOutput = ClockInputOverlayOutput(node) 61 | } 62 | 63 | abstract class SingleEndedClockBundleInputPlacedOverlay( 64 | val name: String, val di: ClockInputDesignInput, val si: ClockInputShellInput) 65 | extends IOPlacedOverlay[ClockBundle, ClockInputDesignInput, ClockInputShellInput, ClockInputOverlayOutput] 66 | { 67 | implicit val p = di.p 68 | def node: ClockSourceNode 69 | 70 | def ioFactory = Input(new ClockBundle(ClockBundleParameters())) 71 | 72 | val clock = shell { InModuleBody { 73 | val (bundle, edge) = node.out.head 74 | bundle.clock 75 | } } 76 | val reset = shell { InModuleBody { 77 | val (bundle, edge) = node.out.head 78 | bundle.reset 79 | } } 80 | def overlayOutput = ClockInputOverlayOutput(node) 81 | } 82 | 83 | /* 84 | Copyright 2016 SiFive, Inc. 85 | 86 | Licensed under the Apache License, Version 2.0 (the "License"); 87 | you may not use this file except in compliance with the License. 88 | You may obtain a copy of the License at 89 | 90 | http://www.apache.org/licenses/LICENSE-2.0 91 | 92 | Unless required by applicable law or agreed to in writing, software 93 | distributed under the License is distributed on an "AS IS" BASIS, 94 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 95 | See the License for the specific language governing permissions and 96 | limitations under the License. 97 | */ 98 | -------------------------------------------------------------------------------- /src/main/scala/shell/DDROverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.tilelink._ 5 | import freechips.rocketchip.prci._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.fpgashells.clocks._ 8 | 9 | 10 | case class DDRShellInput() 11 | case class DDRDesignInput( 12 | baseAddress: BigInt, 13 | wrangler: ClockAdapterNode, 14 | corePLL: PLLNode, 15 | vc7074gbdimm: Boolean = false)( 16 | implicit val p: Parameters) 17 | case class DDROverlayOutput(ddr: TLInwardNode) 18 | trait DDRShellPlacer[Shell] extends ShellPlacer[DDRDesignInput, DDRShellInput, DDROverlayOutput] 19 | 20 | case object DDROverlayKey extends Field[Seq[DesignPlacer[DDRDesignInput, DDRShellInput, DDROverlayOutput]]](Nil) 21 | 22 | abstract class DDRPlacedOverlay[IO <: Data](val name: String, val di: DDRDesignInput, val si: DDRShellInput) 23 | extends IOPlacedOverlay[IO, DDRDesignInput, DDRShellInput, DDROverlayOutput] 24 | { 25 | implicit val p = di.p 26 | } 27 | 28 | /* 29 | Copyright 2016 SiFive, Inc. 30 | 31 | Licensed under the Apache License, Version 2.0 (the "License"); 32 | you may not use this file except in compliance with the License. 33 | You may obtain a copy of the License at 34 | 35 | http://www.apache.org/licenses/LICENSE-2.0 36 | 37 | Unless required by applicable law or agreed to in writing, software 38 | distributed under the License is distributed on an "AS IS" BASIS, 39 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | See the License for the specific language governing permissions and 41 | limitations under the License. 42 | */ 43 | -------------------------------------------------------------------------------- /src/main/scala/shell/Ethernet.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import org.chipsalliance.cde.config._ 6 | 7 | case class EthernetShellInput() 8 | case class EthernetDesignInput()(implicit val p: Parameters) 9 | case class EthernetOverlayOutput(eth: ModuleValue[EthernetPCS]) 10 | case object EthernetOverlayKey extends Field[Seq[DesignPlacer[EthernetDesignInput, EthernetShellInput, EthernetOverlayOutput]]](Nil) 11 | trait EthernetShellPlacer[Shell] extends ShellPlacer[EthernetDesignInput, EthernetShellInput, EthernetOverlayOutput] 12 | 13 | class EthernetPads extends Bundle { 14 | val tx_p = Output(Bool()) 15 | val tx_n = Output(Bool()) 16 | val rx_p = Input(Bool()) 17 | val rx_n = Input(Bool()) 18 | val refclk_p = Input(Clock()) 19 | val refclk_n = Input(Clock()) 20 | } 21 | 22 | class EthernetPCS extends Bundle { 23 | val rx_clock = Output(Clock()) 24 | val rx_reset = Output(Reset()) 25 | val rx_d = Output(UInt(64.W)) 26 | val rx_c = Output(UInt(8.W)) 27 | val tx_clock = Output(Clock()) 28 | val tx_reset = Output(Reset()) 29 | val tx_d = Input(UInt(64.W)) 30 | val tx_c = Input(UInt(8.W)) 31 | val loopback = Input(UInt(3.W)) 32 | val rx_lock = Output(Bool()) 33 | val sfp_detect = Output(Bool()) 34 | } 35 | 36 | abstract class EthernetPlacedOverlay( 37 | val name: String, val di: EthernetDesignInput, val si: EthernetShellInput) 38 | extends IOPlacedOverlay[EthernetPads, EthernetDesignInput, EthernetShellInput, EthernetOverlayOutput] 39 | { 40 | implicit val p = di.p 41 | 42 | val pcsPads = InModuleBody { Wire(new EthernetPCS) } 43 | 44 | def ioFactory = new EthernetPads 45 | def overlayOutput = EthernetOverlayOutput(eth = pcsPads) 46 | } 47 | 48 | /* 49 | Copyright 2016 SiFive, Inc. 50 | 51 | Licensed under the Apache License, Version 2.0 (the "License"); 52 | you may not use this file except in compliance with the License. 53 | You may obtain a copy of the License at 54 | 55 | http://www.apache.org/licenses/LICENSE-2.0 56 | 57 | Unless required by applicable law or agreed to in writing, software 58 | distributed under the License is distributed on an "AS IS" BASIS, 59 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 60 | See the License for the specific language governing permissions and 61 | limitations under the License. 62 | */ 63 | -------------------------------------------------------------------------------- /src/main/scala/shell/GPIOOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.gpio._ 8 | 9 | case class GPIOShellInput() 10 | case class GPIODesignInput(gpioParams: GPIOParams, node: BundleBridgeSource[GPIOPortIO])(implicit val p: Parameters) 11 | case class GPIOOverlayOutput() 12 | case object GPIOOverlayKey extends Field[Seq[DesignPlacer[GPIODesignInput, GPIOShellInput, GPIOOverlayOutput]]](Nil) 13 | trait GPIOShellPlacer[Shell] extends ShellPlacer[GPIODesignInput, GPIOShellInput, GPIOOverlayOutput] 14 | 15 | class ShellGPIOPortIO(val numGPIOs: Int = 4) extends Bundle { 16 | val gpio = Vec(numGPIOs, Analog(1.W)) 17 | } 18 | 19 | abstract class GPIOPlacedOverlay( 20 | val name: String, val di: GPIODesignInput, si: GPIOShellInput) 21 | extends IOPlacedOverlay[ShellGPIOPortIO, GPIODesignInput, GPIOShellInput, GPIOOverlayOutput] 22 | { 23 | implicit val p = di.p 24 | 25 | def ioFactory = new ShellGPIOPortIO(di.gpioParams.width) 26 | 27 | val tlgpioSink = sinkScope { di.node.makeSink } 28 | def overlayOutput = GPIOOverlayOutput() 29 | } 30 | 31 | /* 32 | Copyright 2016 SiFive, Inc. 33 | 34 | Licensed under the Apache License, Version 2.0 (the "License"); 35 | you may not use this file except in compliance with the License. 36 | You may obtain a copy of the License at 37 | 38 | http://www.apache.org/licenses/LICENSE-2.0 39 | 40 | Unless required by applicable law or agreed to in writing, software 41 | distributed under the License is distributed on an "AS IS" BASIS, 42 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 43 | See the License for the specific language governing permissions and 44 | limitations under the License. 45 | */ 46 | -------------------------------------------------------------------------------- /src/main/scala/shell/GPIOPMODOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | 8 | case class GPIOPMODShellInput() 9 | case class GPIOPMODDesignInput()(implicit val p: Parameters) 10 | case class GPIOPMODOverlayOutput(pmod: ModuleValue[GPIOPMODPortIO]) 11 | case object GPIOPMODOverlayKey extends Field[Seq[DesignPlacer[GPIOPMODDesignInput, GPIOPMODShellInput, GPIOPMODOverlayOutput]]](Nil) 12 | trait GPIOPMODShellPlacer[Shell] extends ShellPlacer[GPIOPMODDesignInput, GPIOPMODShellInput, GPIOPMODOverlayOutput] 13 | 14 | class GPIOPMODPortIO extends Bundle { 15 | val gpio_pmod_0 = Analog(1.W) 16 | val gpio_pmod_1 = Analog(1.W) 17 | val gpio_pmod_2 = Analog(1.W) 18 | val gpio_pmod_3 = Analog(1.W) 19 | val gpio_pmod_4 = Analog(1.W) 20 | val gpio_pmod_5 = Analog(1.W) 21 | val gpio_pmod_6 = Analog(1.W) 22 | val gpio_pmod_7 = Analog(1.W) 23 | } 24 | 25 | abstract class GPIOPMODPlacedOverlay( 26 | val name: String, val di: GPIOPMODDesignInput, val si: GPIOPMODShellInput) 27 | extends IOPlacedOverlay[GPIOPMODPortIO, GPIOPMODDesignInput, GPIOPMODShellInput, GPIOPMODOverlayOutput] 28 | { 29 | implicit val p = di.p 30 | 31 | def ioFactory = new GPIOPMODPortIO 32 | 33 | val pmodgpioSource = BundleBridgeSource(() => new GPIOPMODPortIO) 34 | val pmodgpioSink = shell { pmodgpioSource.makeSink } 35 | 36 | def overlayOutput = GPIOPMODOverlayOutput(pmod = InModuleBody { pmodgpioSource.bundle } ) 37 | 38 | shell { InModuleBody { 39 | io <> pmodgpioSink.bundle 40 | }} 41 | } 42 | 43 | /* 44 | Copyright 2016 SiFive, Inc. 45 | 46 | Licensed under the Apache License, Version 2.0 (the "License"); 47 | you may not use this file except in compliance with the License. 48 | You may obtain a copy of the License at 49 | 50 | http://www.apache.org/licenses/LICENSE-2.0 51 | 52 | Unless required by applicable law or agreed to in writing, software 53 | distributed under the License is distributed on an "AS IS" BASIS, 54 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 55 | See the License for the specific language governing permissions and 56 | limitations under the License. 57 | */ 58 | -------------------------------------------------------------------------------- /src/main/scala/shell/I2COverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.i2c._ 8 | 9 | case class I2CShellInput(index: Int = 0) 10 | case class I2CDesignInput(node: BundleBridgeSource[I2CPort])(implicit val p: Parameters) 11 | case class I2COverlayOutput() 12 | trait I2CShellPlacer[Shell] extends ShellPlacer[I2CDesignInput, I2CShellInput, I2COverlayOutput] 13 | 14 | case object I2COverlayKey extends Field[Seq[DesignPlacer[I2CDesignInput, I2CShellInput, I2COverlayOutput]]](Nil) 15 | 16 | class ShellI2CPortIO extends Bundle { 17 | val scl = Analog(1.W) 18 | val sda = Analog(1.W) 19 | } 20 | 21 | abstract class I2CPlacedOverlay( 22 | val name: String, val di: I2CDesignInput, val si: I2CShellInput) 23 | extends IOPlacedOverlay[ShellI2CPortIO, I2CDesignInput, I2CShellInput, I2COverlayOutput] 24 | { 25 | implicit val p = di.p 26 | 27 | def ioFactory = new ShellI2CPortIO 28 | 29 | val tli2cSink = sinkScope { di.node.makeSink } 30 | 31 | def overlayOutput = I2COverlayOutput() 32 | } 33 | 34 | /* 35 | Copyright 2016 SiFive, Inc. 36 | 37 | Licensed under the Apache License, Version 2.0 (the "License"); 38 | you may not use this file except in compliance with the License. 39 | You may obtain a copy of the License at 40 | 41 | http://www.apache.org/licenses/LICENSE-2.0 42 | 43 | Unless required by applicable law or agreed to in writing, software 44 | distributed under the License is distributed on an "AS IS" BASIS, 45 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 46 | See the License for the specific language governing permissions and 47 | limitations under the License. 48 | */ 49 | -------------------------------------------------------------------------------- /src/main/scala/shell/JTAGDebugBScanOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import org.chipsalliance.cde.config._ 5 | 6 | case class JTAGDebugBScanShellInput() 7 | case class JTAGDebugBScanDesignInput()(implicit val p: Parameters) 8 | case class JTAGDebugBScanOverlayOutput(jtag: ModuleValue[FlippedJTAGIO]) 9 | case object JTAGDebugBScanOverlayKey extends Field[Seq[DesignPlacer[JTAGDebugBScanDesignInput, JTAGDebugBScanShellInput, JTAGDebugBScanOverlayOutput]]](Nil) 10 | trait JTAGDebugBScanShellPlacer[Shell] extends ShellPlacer[JTAGDebugBScanDesignInput, JTAGDebugBScanShellInput, JTAGDebugBScanOverlayOutput] 11 | 12 | abstract class JTAGDebugBScanPlacedOverlay( 13 | val name: String, val di: JTAGDebugBScanDesignInput, val si: JTAGDebugBScanShellInput) 14 | extends PlacedOverlay[JTAGDebugBScanDesignInput, JTAGDebugBScanShellInput, JTAGDebugBScanOverlayOutput] 15 | { 16 | implicit val p = di.p 17 | def shell: Shell 18 | 19 | val jtagDebugSource = BundleBridgeSource(() => new FlippedJTAGIO()) 20 | val jtagDebugSink = shell { jtagDebugSource.makeSink } 21 | val jtout = InModuleBody { jtagDebugSource.bundle} 22 | def overlayOutput = JTAGDebugBScanOverlayOutput(jtag = jtout) 23 | } 24 | 25 | /* 26 | Copyright 2016 SiFive, Inc. 27 | 28 | Licensed under the Apache License, Version 2.0 (the "License"); 29 | you may not use this file except in compliance with the License. 30 | You may obtain a copy of the License at 31 | 32 | http://www.apache.org/licenses/LICENSE-2.0 33 | 34 | Unless required by applicable law or agreed to in writing, software 35 | distributed under the License is distributed on an "AS IS" BASIS, 36 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | See the License for the specific language governing permissions and 38 | limitations under the License. 39 | */ 40 | -------------------------------------------------------------------------------- /src/main/scala/shell/JTAGDebugOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import freechips.rocketchip.jtag._ 7 | import org.chipsalliance.cde.config._ 8 | 9 | case class JTAGDebugShellInput(location: Option[String] = None) 10 | case class JTAGDebugDesignInput()(implicit val p: Parameters) 11 | case class JTAGDebugOverlayOutput(jtag: ModuleValue[FlippedJTAGIO]) 12 | case object JTAGDebugOverlayKey extends Field[Seq[DesignPlacer[JTAGDebugDesignInput, JTAGDebugShellInput, JTAGDebugOverlayOutput]]](Nil) 13 | trait JTAGDebugShellPlacer[Shell] extends ShellPlacer[JTAGDebugDesignInput, JTAGDebugShellInput, JTAGDebugOverlayOutput] 14 | 15 | class ShellJTAGIO extends Bundle { 16 | // JTAG 17 | val jtag_TCK = Analog(1.W) 18 | val jtag_TMS = Analog(1.W) 19 | val jtag_TDI = Analog(1.W) 20 | val jtag_TDO = Analog(1.W) 21 | val srst_n = Analog(1.W) 22 | } 23 | 24 | // TODO: Fix interaction of BundleBridge/Flipped to get rid of this Bundle 25 | class FlippedJTAGIO extends Bundle { 26 | val TCK = Input(Clock()) 27 | val TMS = Input(Bool()) 28 | val TDI = Input(Bool()) 29 | val TDO = Output(new Tristate()) 30 | val srst_n = Input(Bool()) 31 | } 32 | 33 | abstract class JTAGDebugPlacedOverlay( 34 | val name: String, val di: JTAGDebugDesignInput, val si: JTAGDebugShellInput) 35 | extends IOPlacedOverlay[ShellJTAGIO, JTAGDebugDesignInput, JTAGDebugShellInput, JTAGDebugOverlayOutput] 36 | { 37 | implicit val p = di.p 38 | 39 | def ioFactory = new ShellJTAGIO 40 | 41 | val jtagDebugSource = BundleBridgeSource(() => new FlippedJTAGIO()) 42 | val jtagDebugSink = sinkScope { jtagDebugSource.makeSink } 43 | val jtout = InModuleBody { jtagDebugSource.bundle} 44 | def overlayOutput = JTAGDebugOverlayOutput(jtag = jtout) 45 | } 46 | 47 | /* 48 | Copyright 2016 SiFive, Inc. 49 | 50 | Licensed under the Apache License, Version 2.0 (the "License"); 51 | you may not use this file except in compliance with the License. 52 | You may obtain a copy of the License at 53 | 54 | http://www.apache.org/licenses/LICENSE-2.0 55 | 56 | Unless required by applicable law or agreed to in writing, software 57 | distributed under the License is distributed on an "AS IS" BASIS, 58 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 59 | See the License for the specific language governing permissions and 60 | limitations under the License. 61 | */ 62 | -------------------------------------------------------------------------------- /src/main/scala/shell/LEDOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import org.chipsalliance.cde.config._ 6 | 7 | case class LEDShellInput( 8 | color: String = "", 9 | header: String = "", 10 | rgb: Boolean = false, 11 | number: Int = 0) 12 | 13 | case class LEDDesignInput()(implicit val p: Parameters) 14 | case class LEDOverlayOutput(led: ModuleValue[Bool]) 15 | case object LEDOverlayKey extends Field[Seq[DesignPlacer[LEDDesignInput, LEDShellInput, LEDOverlayOutput]]](Nil) 16 | trait LEDShellPlacer[Shell] extends ShellPlacer[LEDDesignInput, LEDShellInput, LEDOverlayOutput] 17 | 18 | abstract class LEDPlacedOverlay( 19 | val name: String, val di: LEDDesignInput, si: LEDShellInput) 20 | extends IOPlacedOverlay[Bool, LEDDesignInput, LEDShellInput, LEDOverlayOutput] 21 | { 22 | implicit val p = di.p 23 | 24 | def ioFactory = Output(Bool()) 25 | 26 | val ledWire = shell { InModuleBody { Wire(Bool()) } } 27 | def overlayOutput = LEDOverlayOutput(ledWire) 28 | } 29 | 30 | /* 31 | Copyright 2016 SiFive, Inc. 32 | 33 | Licensed under the Apache License, Version 2.0 (the "License"); 34 | you may not use this file except in compliance with the License. 35 | You may obtain a copy of the License at 36 | 37 | http://www.apache.org/licenses/LICENSE-2.0 38 | 39 | Unless required by applicable law or agreed to in writing, software 40 | distributed under the License is distributed on an "AS IS" BASIS, 41 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 42 | See the License for the specific language governing permissions and 43 | limitations under the License. 44 | */ 45 | -------------------------------------------------------------------------------- /src/main/scala/shell/PCIeOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.interrupts._ 6 | import freechips.rocketchip.tilelink._ 7 | import freechips.rocketchip.prci._ 8 | import org.chipsalliance.cde.config._ 9 | import sifive.fpgashells.clocks._ 10 | 11 | case class PCIeShellInput() 12 | case class PCIeDesignInput( 13 | wrangler: ClockAdapterNode, 14 | bars: Seq[AddressSet] = Seq(AddressSet(0x40000000L, 0x1FFFFFFFL)), 15 | ecam: BigInt = 0x2000000000L, 16 | bases: Seq[BigInt] = Nil, // remap bars to these PCIe base addresses 17 | corePLL: PLLNode)( 18 | implicit val p: Parameters) 19 | 20 | case class PCIeOverlayOutput( 21 | pcieNode: TLNode, 22 | intNode: IntOutwardNode) 23 | trait PCIeShellPlacer[Shell] extends ShellPlacer[PCIeDesignInput, PCIeShellInput, PCIeOverlayOutput] 24 | 25 | case object PCIeOverlayKey extends Field[Seq[DesignPlacer[PCIeDesignInput, PCIeShellInput, PCIeOverlayOutput]]](Nil) 26 | 27 | abstract class PCIePlacedOverlay[IO <: Data]( 28 | val name: String, val di: PCIeDesignInput, val si: PCIeShellInput) 29 | extends IOPlacedOverlay[IO, PCIeDesignInput, PCIeShellInput, PCIeOverlayOutput] 30 | { 31 | implicit val p = di.p 32 | } 33 | 34 | /* 35 | Copyright 2016 SiFive, Inc. 36 | 37 | Licensed under the Apache License, Version 2.0 (the "License"); 38 | you may not use this file except in compliance with the License. 39 | You may obtain a copy of the License at 40 | 41 | http://www.apache.org/licenses/LICENSE-2.0 42 | 43 | Unless required by applicable law or agreed to in writing, software 44 | distributed under the License is distributed on an "AS IS" BASIS, 45 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 46 | See the License for the specific language governing permissions and 47 | limitations under the License. 48 | */ 49 | -------------------------------------------------------------------------------- /src/main/scala/shell/PMODOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | 8 | case class PMODShellInput(index: Int) 9 | case class PMODDesignInput()(implicit val p: Parameters) 10 | case class PMODOverlayOutput(pin: ModuleValue[PMODPortIO]) 11 | case object PMODOverlayKey extends Field[Seq[DesignPlacer[PMODDesignInput, PMODShellInput, PMODOverlayOutput]]](Nil) 12 | trait PMODShellPlacer[Shell] extends ShellPlacer[PMODDesignInput, PMODShellInput, PMODOverlayOutput] 13 | 14 | class PMODPortIO extends Bundle { 15 | val pins = Vec(8, Analog(1.W)) 16 | } 17 | 18 | abstract class PMODPlacedOverlay( 19 | val name: String, val di: PMODDesignInput, val si: PMODShellInput) 20 | extends IOPlacedOverlay[PMODPortIO, PMODDesignInput, PMODShellInput, PMODOverlayOutput] 21 | { 22 | implicit val p = di.p 23 | 24 | def ioFactory = new PMODPortIO 25 | 26 | val pinSource = BundleBridgeSource(() => new PMODPortIO) 27 | val pinSink = shell { pinSource.makeSink } 28 | 29 | def overlayOutput = PMODOverlayOutput(pin = InModuleBody { pinSource.bundle } ) 30 | 31 | shell { InModuleBody { 32 | io <> pinSink.bundle 33 | }} 34 | } 35 | 36 | /* 37 | Copyright 2016 SiFive, Inc. 38 | 39 | Licensed under the Apache License, Version 2.0 (the "License"); 40 | you may not use this file except in compliance with the License. 41 | You may obtain a copy of the License at 42 | 43 | http://www.apache.org/licenses/LICENSE-2.0 44 | 45 | Unless required by applicable law or agreed to in writing, software 46 | distributed under the License is distributed on an "AS IS" BASIS, 47 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 48 | See the License for the specific language governing permissions and 49 | limitations under the License. 50 | */ 51 | -------------------------------------------------------------------------------- /src/main/scala/shell/PWMOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.pwm._ 8 | 9 | case class PWMShellInput(index: Int = 0) 10 | case class PWMDesignInput(node: BundleBridgeSource[PWMPortIO])(implicit val p: Parameters) 11 | case class PWMOverlayOutput() 12 | case object PWMOverlayKey extends Field[Seq[DesignPlacer[PWMDesignInput, PWMShellInput, PWMOverlayOutput]]](Nil) 13 | trait PWMShellPlacer[Shell] extends ShellPlacer[PWMDesignInput, PWMShellInput, PWMOverlayOutput] 14 | 15 | class ShellPWMPortIO extends Bundle { 16 | val pwm_gpio = Vec(4, Analog(1.W)) 17 | } 18 | 19 | abstract class PWMPlacedOverlay( 20 | val name: String, val di: PWMDesignInput, val si: PWMShellInput) 21 | extends IOPlacedOverlay[ShellPWMPortIO, PWMDesignInput, PWMShellInput, PWMOverlayOutput] 22 | { 23 | implicit val p = di.p 24 | 25 | def ioFactory = new ShellPWMPortIO 26 | 27 | val tlpwmSink = sinkScope { di.node.makeSink } 28 | 29 | def overlayOutput = PWMOverlayOutput() 30 | } 31 | 32 | /* 33 | Copyright 2016 SiFive, Inc. 34 | 35 | Licensed under the Apache License, Version 2.0 (the "License"); 36 | you may not use this file except in compliance with the License. 37 | You may obtain a copy of the License at 38 | 39 | http://www.apache.org/licenses/LICENSE-2.0 40 | 41 | Unless required by applicable law or agreed to in writing, software 42 | distributed under the License is distributed on an "AS IS" BASIS, 43 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 44 | See the License for the specific language governing permissions and 45 | limitations under the License. 46 | */ 47 | -------------------------------------------------------------------------------- /src/main/scala/shell/PinOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | 8 | case class PinShellInput() 9 | case class PinDesignInput()(implicit val p: Parameters) 10 | case class PinOverlayOutput(pin: ModuleValue[PinPortIO]) 11 | case object PinOverlayKey extends Field[Seq[DesignPlacer[PinDesignInput, PinShellInput, PinOverlayOutput]]](Nil) 12 | trait PinShellPlacer[Shell] extends ShellPlacer[PinDesignInput, PinShellInput, PinOverlayOutput] 13 | 14 | class PinPortIO extends Bundle { 15 | val pins = Vec(8, Analog(1.W)) 16 | } 17 | 18 | abstract class PinPlacedOverlay( 19 | val name: String, val di: PinDesignInput, val si: PinShellInput) 20 | extends IOPlacedOverlay[PinPortIO, PinDesignInput, PinShellInput, PinOverlayOutput] 21 | { 22 | implicit val p = di.p 23 | 24 | def ioFactory = new PinPortIO 25 | 26 | val pinSource = BundleBridgeSource(() => new PinPortIO) 27 | val pinSink = shell { pinSource.makeSink } 28 | 29 | def overlayOutput = PinOverlayOutput(pin = InModuleBody { pinSource.bundle } ) 30 | 31 | shell { InModuleBody { 32 | io <> pinSink.bundle 33 | }} 34 | } 35 | 36 | /* 37 | Copyright 2016 SiFive, Inc. 38 | 39 | Licensed under the Apache License, Version 2.0 (the "License"); 40 | you may not use this file except in compliance with the License. 41 | You may obtain a copy of the License at 42 | 43 | http://www.apache.org/licenses/LICENSE-2.0 44 | 45 | Unless required by applicable law or agreed to in writing, software 46 | distributed under the License is distributed on an "AS IS" BASIS, 47 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 48 | See the License for the specific language governing permissions and 49 | limitations under the License. 50 | */ 51 | -------------------------------------------------------------------------------- /src/main/scala/shell/PorGenOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.porgen._ 8 | 9 | case class PorGenShellInput(index: Int = 0) 10 | case class PorGenDesignInput(node: BundleBridgeSource[PorGenPortIO])(implicit val p: Parameters) 11 | case class PorGenOverlayOutput() 12 | case object PorGenOverlayKey extends Field[Seq[DesignPlacer[PorGenDesignInput, PorGenShellInput, PorGenOverlayOutput]]](Nil) 13 | trait PorGenShellPlacer[Shell] extends ShellPlacer[PorGenDesignInput, PorGenShellInput, PorGenOverlayOutput] 14 | 15 | class ShellPorGenPortIO extends Bundle { 16 | val poreset_n = Analog(1.W) 17 | val ereset_n = Analog(1.W) 18 | } 19 | 20 | abstract class PorGenPlacedOverlay( 21 | val name: String, val di: PorGenDesignInput, val si: PorGenShellInput) 22 | extends IOPlacedOverlay[ShellPorGenPortIO, PorGenDesignInput, PorGenShellInput, PorGenOverlayOutput] 23 | { 24 | implicit val p = di.p 25 | 26 | def ioFactory = new ShellPorGenPortIO 27 | 28 | val tlporgenSink = sinkScope { di.node.makeSink } 29 | 30 | def overlayOutput = PorGenOverlayOutput() 31 | } 32 | 33 | /* 34 | Copyright 2016 SiFive, Inc. 35 | 36 | Licensed under the Apache License, Version 2.0 (the "License"); 37 | you may not use this file except in compliance with the License. 38 | You may obtain a copy of the License at 39 | 40 | http://www.apache.org/licenses/LICENSE-2.0 41 | 42 | Unless required by applicable law or agreed to in writing, software 43 | distributed under the License is distributed on an "AS IS" BASIS, 44 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 45 | See the License for the specific language governing permissions and 46 | limitations under the License. 47 | */ 48 | -------------------------------------------------------------------------------- /src/main/scala/shell/SPIFlashOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.spi._ 8 | 9 | //This one does controller also 10 | case class SPIFlashShellInput(index: Int = 0, vcu118SU: Boolean = false) 11 | case class SPIFlashDesignInput(node: BundleBridgeSource[SPIPortIO])(implicit val p: Parameters) 12 | case class SPIFlashOverlayOutput() 13 | case object SPIFlashOverlayKey extends Field[Seq[DesignPlacer[SPIFlashDesignInput, SPIFlashShellInput, SPIFlashOverlayOutput]]](Nil) 14 | trait SPIFlashShellPlacer[Shell] extends ShellPlacer[SPIFlashDesignInput, SPIFlashShellInput, SPIFlashOverlayOutput] 15 | 16 | 17 | class ShellSPIFlashPortIO extends Bundle { 18 | val qspi_sck = Analog(1.W) 19 | val qspi_cs = Analog(1.W) 20 | val qspi_dq = Vec(4, Analog(1.W)) 21 | } 22 | 23 | abstract class SPIFlashPlacedOverlay( 24 | val name: String, val di: SPIFlashDesignInput, val si: SPIFlashShellInput) 25 | extends IOPlacedOverlay[ShellSPIFlashPortIO, SPIFlashDesignInput, SPIFlashShellInput, SPIFlashOverlayOutput] 26 | { 27 | implicit val p = di.p 28 | 29 | def ioFactory = new ShellSPIFlashPortIO 30 | 31 | val tlqspiSink = sinkScope { di.node.makeSink } 32 | 33 | def overlayOutput = SPIFlashOverlayOutput() 34 | } 35 | 36 | /* 37 | Copyright 2016 SiFive, Inc. 38 | 39 | Licensed under the Apache License, Version 2.0 (the "License"); 40 | you may not use this file except in compliance with the License. 41 | You may obtain a copy of the License at 42 | 43 | http://www.apache.org/licenses/LICENSE-2.0 44 | 45 | Unless required by applicable law or agreed to in writing, software 46 | distributed under the License is distributed on an "AS IS" BASIS, 47 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 48 | See the License for the specific language governing permissions and 49 | limitations under the License. 50 | */ 51 | -------------------------------------------------------------------------------- /src/main/scala/shell/SPIOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.spi._ 8 | 9 | //This should not do the controller placement either 10 | case class SPIShellInput() 11 | case class SPIDesignInput(spiParam: SPIParams, node: BundleBridgeSource[SPIPortIO])(implicit val p: Parameters) 12 | case class SPIOverlayOutput() 13 | case object SPIOverlayKey extends Field[Seq[DesignPlacer[SPIDesignInput, SPIShellInput, SPIOverlayOutput]]](Nil) 14 | trait SPIShellPlacer[Shell] extends ShellPlacer[SPIDesignInput, SPIShellInput, SPIOverlayOutput] 15 | 16 | // SPI Port. Not sure how generic this is, it might need to move. 17 | class ShellSPIPortIO extends Bundle { 18 | val spi_clk = Analog(1.W) 19 | val spi_cs = Analog(1.W) 20 | val spi_dat = Vec(4, Analog(1.W)) 21 | } 22 | 23 | abstract class SPIPlacedOverlay( 24 | val name: String, val di: SPIDesignInput, val si: SPIShellInput) 25 | extends IOPlacedOverlay[ShellSPIPortIO, SPIDesignInput, SPIShellInput, SPIOverlayOutput] 26 | { 27 | implicit val p = di.p 28 | 29 | def ioFactory = new ShellSPIPortIO 30 | val tlspiSink = di.node.makeSink 31 | 32 | val spiSource = BundleBridgeSource(() => new SPIPortIO(di.spiParam)) 33 | val spiSink = sinkScope { spiSource.makeSink } 34 | def overlayOutput = SPIOverlayOutput() 35 | 36 | } 37 | 38 | /* 39 | Copyright 2016 SiFive, Inc. 40 | 41 | Licensed under the Apache License, Version 2.0 (the "License"); 42 | you may not use this file except in compliance with the License. 43 | You may obtain a copy of the License at 44 | 45 | http://www.apache.org/licenses/LICENSE-2.0 46 | 47 | Unless required by applicable law or agreed to in writing, software 48 | distributed under the License is distributed on an "AS IS" BASIS, 49 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 50 | See the License for the specific language governing permissions and 51 | limitations under the License. 52 | */ 53 | -------------------------------------------------------------------------------- /src/main/scala/shell/Shell.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import org.chipsalliance.cde.config._ 5 | 6 | case object DesignKey extends Field[Parameters => LazyModule] 7 | 8 | case object DesignKeyWithTestHarness extends Field[(Option[LazyScope], Parameters) => LazyModule] 9 | 10 | // Overlays are declared by the Shell and placed somewhere by the Design 11 | // ... they inject diplomatic code both where they were placed and in the shell 12 | // ... they are instantiated with DesignInput and return DesignOutput 13 | // placed overlay has been invoked by the design 14 | trait PlacedOverlay[DesignInput, ShellInput, OverlayOutput] { 15 | def name: String 16 | def designInput: DesignInput 17 | def shellInput: ShellInput 18 | def overlayOutput: OverlayOutput 19 | } 20 | 21 | trait ShellPlacer[DesignInput, ShellInput, OverlayOutput] { 22 | def valName: ValName 23 | def shellInput: ShellInput 24 | def place(di: DesignInput): PlacedOverlay[DesignInput, ShellInput, OverlayOutput] 25 | } 26 | 27 | trait DesignPlacer[DesignInput, ShellInput, OverlayOutput] { 28 | def isPlaced: Boolean 29 | def name: String 30 | def shellInput: ShellInput 31 | def place(di: DesignInput): PlacedOverlay[DesignInput, ShellInput, OverlayOutput] 32 | } 33 | 34 | trait ShellOverlayAccessor[DesignInput, ShellInput, OverlayOutput] { 35 | def get(): Option[PlacedOverlay[DesignInput, ShellInput, OverlayOutput]] 36 | } 37 | 38 | abstract class Shell()(implicit p: Parameters) extends LazyModule with LazyScope 39 | { 40 | private var overlays = Parameters.empty 41 | def designParameters: Parameters = overlays ++ p 42 | 43 | def Overlay[DesignInput, ShellInput, OverlayOutput]( 44 | key: Field[Seq[DesignPlacer[DesignInput, ShellInput, OverlayOutput]]], 45 | placer: ShellPlacer[DesignInput, ShellInput, OverlayOutput]): 46 | ShellOverlayAccessor[DesignInput, ShellInput, OverlayOutput] = { 47 | val thunk = new Object 48 | with ShellOverlayAccessor[DesignInput, ShellInput, OverlayOutput] 49 | with DesignPlacer[DesignInput, ShellInput, OverlayOutput] { 50 | var placedOverlay: Option[PlacedOverlay[DesignInput, ShellInput, OverlayOutput]] = None 51 | def get() = placedOverlay 52 | def isPlaced = !placedOverlay.isEmpty 53 | def name = placer.valName.name 54 | def shellInput = placer.shellInput 55 | def place(input: DesignInput): PlacedOverlay[DesignInput, ShellInput, OverlayOutput] = { 56 | require (!isPlaced, s"Overlay ${name} has already been placed by the design; cannot place again") 57 | val it = placer.place(input) 58 | placedOverlay = Some(it) 59 | it 60 | } 61 | } 62 | overlays = overlays ++ Parameters((site, here, up) => { 63 | case x: Field[_] if x eq key => { 64 | val tail = up(key) 65 | if (thunk.isPlaced) { tail } else { thunk +: tail } 66 | } 67 | }) 68 | thunk 69 | } 70 | 71 | // feel free to override this if necessary 72 | lazy val module = new LazyRawModuleImp(this) { 73 | // most children will have the implicit module.clock/reset explicitly set, 74 | // but we have to provide this anyways so diplomacy doesn't complain 75 | override def provideImplicitClockToLazyChildren: Boolean = true 76 | } 77 | } 78 | 79 | /* 80 | Copyright 2016 SiFive, Inc. 81 | 82 | Licensed under the Apache License, Version 2.0 (the "License"); 83 | you may not use this file except in compliance with the License. 84 | You may obtain a copy of the License at 85 | 86 | http://www.apache.org/licenses/LICENSE-2.0 87 | 88 | Unless required by applicable law or agreed to in writing, software 89 | distributed under the License is distributed on an "AS IS" BASIS, 90 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 91 | See the License for the specific language governing permissions and 92 | limitations under the License. 93 | */ 94 | -------------------------------------------------------------------------------- /src/main/scala/shell/SwitchOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import org.chipsalliance.cde.config._ 6 | 7 | case class SwitchShellInput(number: Int = 0) 8 | case class SwitchDesignInput()(implicit val p: Parameters) 9 | case class SwitchOverlayOutput(sw: ModuleValue[Bool]) 10 | case object SwitchOverlayKey extends Field[Seq[DesignPlacer[SwitchDesignInput, SwitchShellInput, SwitchOverlayOutput]]](Nil) 11 | trait SwitchShellPlacer[Shell] extends ShellPlacer[SwitchDesignInput, SwitchShellInput, SwitchOverlayOutput] 12 | 13 | abstract class SwitchPlacedOverlay( 14 | val name: String, val di: SwitchDesignInput, val si: SwitchShellInput) 15 | extends IOPlacedOverlay[Bool, SwitchDesignInput, SwitchShellInput, SwitchOverlayOutput] 16 | { 17 | implicit val p = di.p 18 | 19 | def ioFactory = Input(Bool()) 20 | 21 | val switchWire = shell { InModuleBody { Wire(Bool()) }} 22 | def overlayOutput = SwitchOverlayOutput(sw = switchWire) 23 | } 24 | 25 | /* 26 | Copyright 2016 SiFive, Inc. 27 | 28 | Licensed under the Apache License, Version 2.0 (the "License"); 29 | you may not use this file except in compliance with the License. 30 | You may obtain a copy of the License at 31 | 32 | http://www.apache.org/licenses/LICENSE-2.0 33 | 34 | Unless required by applicable law or agreed to in writing, software 35 | distributed under the License is distributed on an "AS IS" BASIS, 36 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 37 | See the License for the specific language governing permissions and 38 | limitations under the License. 39 | */ 40 | -------------------------------------------------------------------------------- /src/main/scala/shell/TracePMODOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import org.chipsalliance.cde.config._ 6 | 7 | case class TracePMODShellInput() 8 | case class TracePMODDesignInput()(implicit val p: Parameters) 9 | case class TracePMODOverlayOutput(trace: ModuleValue[UInt]) 10 | case object TracePMODOverlayKey extends Field[Seq[DesignPlacer[TracePMODDesignInput, TracePMODShellInput, TracePMODOverlayOutput]]](Nil) 11 | trait TracePMODShellPlacer[Shell] extends ShellPlacer[TracePMODDesignInput, TracePMODShellInput, TracePMODOverlayOutput] 12 | 13 | abstract class TracePMODPlacedOverlay( 14 | val name: String, val di: TracePMODDesignInput, val si: TracePMODShellInput) 15 | extends IOPlacedOverlay[UInt, TracePMODDesignInput, TracePMODShellInput, TracePMODOverlayOutput] 16 | { 17 | implicit val p = di.p 18 | 19 | def ioFactory = Output(UInt(8.W)) 20 | 21 | val pmodTraceSource = BundleBridgeSource(() => UInt(8.W)) 22 | val pmodTraceSink = shell { pmodTraceSource.makeSink } 23 | val traceout = InModuleBody { pmodTraceSource.out(0)._1 } 24 | def overlayOutput = TracePMODOverlayOutput(trace = traceout ) 25 | } 26 | 27 | /* 28 | Copyright 2016 SiFive, Inc. 29 | 30 | Licensed under the Apache License, Version 2.0 (the "License"); 31 | you may not use this file except in compliance with the License. 32 | You may obtain a copy of the License at 33 | 34 | http://www.apache.org/licenses/LICENSE-2.0 35 | 36 | Unless required by applicable law or agreed to in writing, software 37 | distributed under the License is distributed on an "AS IS" BASIS, 38 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 | See the License for the specific language governing permissions and 40 | limitations under the License. 41 | */ 42 | -------------------------------------------------------------------------------- /src/main/scala/shell/UARTOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.uart._ 8 | 9 | case class UARTShellInput(index: Int = 0) 10 | case class UARTDesignInput(node: BundleBridgeSource[UARTPortIO])(implicit val p: Parameters) 11 | case class UARTOverlayOutput() 12 | case object UARTOverlayKey extends Field[Seq[DesignPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]]](Nil) 13 | trait UARTShellPlacer[Shell] extends ShellPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput] 14 | 15 | // Tack on cts, rts signals available on some FPGAs. They are currently unused 16 | // by our designs. 17 | class ShellUARTPortIO(val flowControl: Boolean) extends Bundle { 18 | val txd = Analog(1.W) 19 | val rxd = Analog(1.W) 20 | val rtsn = if (flowControl) Some(Analog(1.W)) else None 21 | val ctsn = if (flowControl) Some(Analog(1.W)) else None 22 | } 23 | 24 | abstract class UARTPlacedOverlay( 25 | val name: String, val di: UARTDesignInput, val si: UARTShellInput, val flowControl: Boolean) 26 | extends IOPlacedOverlay[ShellUARTPortIO, UARTDesignInput, UARTShellInput, UARTOverlayOutput] 27 | { 28 | implicit val p = di.p 29 | 30 | def ioFactory = new ShellUARTPortIO(flowControl) 31 | 32 | val tluartSink = sinkScope { di.node.makeSink } 33 | 34 | def overlayOutput = UARTOverlayOutput() 35 | } 36 | 37 | /* 38 | Copyright 2016 SiFive, Inc. 39 | 40 | Licensed under the Apache License, Version 2.0 (the "License"); 41 | you may not use this file except in compliance with the License. 42 | You may obtain a copy of the License at 43 | 44 | http://www.apache.org/licenses/LICENSE-2.0 45 | 46 | Unless required by applicable law or agreed to in writing, software 47 | distributed under the License is distributed on an "AS IS" BASIS, 48 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 49 | See the License for the specific language governing permissions and 50 | limitations under the License. 51 | */ 52 | -------------------------------------------------------------------------------- /src/main/scala/shell/Util.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.{Analog, attach} 5 | import chisel3.util.HasBlackBoxInline 6 | import org.chipsalliance.cde.config.Field 7 | 8 | case object FPGAFrequencyKey extends Field[Double](100.0) 9 | 10 | class AnalogToUInt(w: Int = 1) extends BlackBox with HasBlackBoxInline { 11 | val io = IO(new Bundle { 12 | val a = Analog(w.W) 13 | val b = Output(UInt(w.W)) 14 | }) 15 | 16 | override def desiredName = s"AnalogToUInt_${w.toString}" 17 | 18 | setInline(s"AnalogToUInt_${w.toString}.v", 19 | s"""module AnalogToUInt_${w.toString} (a, b); 20 | | inout [${w - 1}:0] a; 21 | | output [${w - 1}:0] b; 22 | | assign b = a; 23 | |endmodule 24 | |""".stripMargin) 25 | } 26 | 27 | object AnalogToUInt { 28 | def apply(a: Analog): UInt = { 29 | val a2b = Module(new AnalogToUInt(w = a.getWidth)) 30 | attach(a, a2b.io.a) 31 | a2b.io.b 32 | } 33 | } 34 | 35 | class UIntToAnalog(w: Int = 1) extends BlackBox with HasBlackBoxInline { 36 | val io = IO(new Bundle { 37 | val a = Analog(w.W) 38 | val b = Input(UInt(w.W)) 39 | val b_en = Input(Bool()) 40 | }) 41 | 42 | override def desiredName = s"UIntToAnalog_${w.toString}" 43 | 44 | require(w >= 1) 45 | setInline(s"UIntToAnalog_${w.toString}.v", 46 | s"""module UIntToAnalog_${w.toString} (a, b, b_en); 47 | | inout [${w - 1}:0] a; 48 | | input [${w - 1}:0] b; 49 | | input b_en; 50 | | assign a = b_en ? b : $w'b${"z"*w}; 51 | |endmodule 52 | |""".stripMargin) 53 | } 54 | 55 | object UIntToAnalog { 56 | def apply(b: UInt, a: Analog, b_en: Bool): Unit = { 57 | val a2b = Module(new UIntToAnalog(w = a.getWidth)) 58 | attach(a, a2b.io.a) 59 | a2b.io.b := b 60 | a2b.io.b_en := b_en 61 | } 62 | } 63 | 64 | /* 65 | Copyright 2016 SiFive, Inc. 66 | 67 | Licensed under the Apache License, Version 2.0 (the "License"); 68 | you may not use this file except in compliance with the License. 69 | You may obtain a copy of the License at 70 | 71 | http://www.apache.org/licenses/LICENSE-2.0 72 | 73 | Unless required by applicable law or agreed to in writing, software 74 | distributed under the License is distributed on an "AS IS" BASIS, 75 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 76 | See the License for the specific language governing permissions and 77 | limitations under the License. 78 | */ 79 | -------------------------------------------------------------------------------- /src/main/scala/shell/altera/AlteraPLLFactory.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.altera 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.prci._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.fpgashells.shell._ 8 | import sifive.fpgashells.clocks._ 9 | 10 | case object AlteraPLLFactoryKey extends Field[PLLFactory] 11 | class AlteraPLLFactory(scope: IOShell, maxOutputs: Int, gen: PLLParameters => PLLInstance) extends PLLFactory(scope, maxOutputs, gen) 12 | { 13 | private var pllNodes: Seq[PLLNode] = Nil 14 | 15 | override def apply(feedback: Boolean = false)(implicit valName: ValName, p: Parameters): PLLNode = { 16 | val node = scope { PLLNode(feedback) } 17 | pllNodes = node +: pllNodes 18 | node 19 | } 20 | 21 | override val plls: ModuleValue[Seq[(PLLInstance, PLLNode)]] = scope { InModuleBody { 22 | val plls = pllNodes.flatMap { case node => 23 | require (node.in.size == 1) 24 | val (in, edgeIn) = node.in(0) 25 | val (out, edgeOut) = node.out.unzip 26 | 27 | val params = PLLParameters( 28 | name = node.valName.name, 29 | input = PLLInClockParameters( 30 | freqMHz = edgeIn.clock.get.freqMHz, 31 | jitter = edgeIn.source.jitterPS.getOrElse(50), 32 | feedback = node.feedback), 33 | req = edgeOut.flatMap(_.members).map { e => 34 | PLLOutClockParameters( 35 | freqMHz = e._2.clock.get.freqMHz, 36 | phaseDeg = e._2.sink.phaseDeg, 37 | dutyCycle = e._2.clock.get.dutyCycle, 38 | jitterPS = e._2.sink.jitterPS, 39 | freqErrorPPM = e._2.sink.freqErrorPPM, 40 | phaseErrorDeg = e._2.sink.phaseErrorDeg)}) 41 | 42 | val pll = gen(params) 43 | pll.getInput := in.clock 44 | pll.getReset.foreach { _ := in.reset } 45 | (out.flatMap(_.member.data) zip pll.getClocks) foreach { case (o, i) => 46 | o.clock := i 47 | o.reset := !pll.getLocked || in.reset.asBool 48 | } 49 | Some((pll, node)) 50 | } 51 | 52 | // Require all clock group names to be distinct 53 | val sdcGroups = plls.flatMap { case tuple => 54 | val (pll, node) = tuple 55 | val clkHierarchies = pll.getClockNames 56 | clkHierarchies.map { case clkName => 57 | val clkpath = clkName.split("/") 58 | val pllOutNum = ("""\d+""".r findAllIn clkpath(1)).next() 59 | s"${clkpath(0)}|altera_pll_i|general[${pllOutNum}].gpll~PLL_OUTPUT_COUNTER|divclk" 60 | } 61 | } 62 | println("Clocks:") 63 | println(sdcGroups) 64 | // Ensure there are no clock groups with the same name 65 | require (sdcGroups.size == pllNodes.map(_.edges.out.size).sum) 66 | sdcGroups.foreach { case clk_names => scope.sdc.addGroup(clocks = Seq(clk_names)) } 67 | 68 | plls 69 | } } 70 | } 71 | -------------------------------------------------------------------------------- /src/main/scala/shell/altera/AlteraSDC.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.util._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.fpgashells.shell._ 8 | 9 | 10 | class AlteraSDC(val sdc_name: String) extends SDC(sdc_name) 11 | { 12 | 13 | override def addGroup(clocks: => Seq[String] = Nil, pins: => Seq[IOPin] = Nil) { 14 | def thunk = { 15 | val clocksList = clocks 16 | val (pinsList, portsList) = pins.map(_.name).partition(_.contains("/")) 17 | val sep = " \\\n " 18 | val clocksStr = (" [get_clocks {" +: clocksList).mkString(sep) + " \\\n }]" 19 | val pinsStr = (" [get_clocks -of_objects [get_pins {" +: pinsList ).mkString(sep) + " \\\n }]]" 20 | val portsStr = (" [get_clocks -of_objects [get_ports {" +: portsList).mkString(sep) + " \\\n }]]" 21 | val str = s" -group [list${if (clocksList.isEmpty) "" else clocksStr}${if (pinsList.isEmpty) "" else pinsStr}${if (portsList.isEmpty) "" else portsStr}]" 22 | if (clocksList.isEmpty && pinsList.isEmpty && portsList.isEmpty) "" else str 23 | } 24 | addRawGroup(thunk) 25 | } 26 | 27 | override def addClock(name: => String, pin: => IOPin, freqMHz: => Double, jitterNs: => Double = 0.5) { 28 | addRawClock(s"create_clock -name ${name} -period ${1000/freqMHz} ${pin.sdcPin}") 29 | } 30 | private def flatten(x: Seq[() => String], sep: String = "\n") = x.map(_()).filter(_ != "").reverse.mkString(sep) 31 | 32 | // TODO: Hack, figure out how to add sdc directives more elegantly 33 | def addSDCDirective(command: => String) { addRawClock(command)} 34 | } -------------------------------------------------------------------------------- /src/main/scala/shell/altera/AlteraShell.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.altera 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.util._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.fpgashells.clocks._ 8 | import sifive.fpgashells.ip.altera._ 9 | import sifive.fpgashells.shell._ 10 | 11 | class IO_TCL(val name: String) 12 | { 13 | private var constraints: Seq[() => String] = Nil 14 | protected def addConstraint(command: => String) { constraints = (() => command) +: constraints } 15 | ElaborationArtefacts.add(name, constraints.map(_()).reverse.mkString("\n") + "\n") 16 | 17 | def addPackagePin(io: IOPin, pin: String) { 18 | addConstraint(s"set_location_assignment {${pin}} -to ${io.name}") 19 | } 20 | def addIOStandard(io: IOPin, standard: String) { 21 | addConstraint(s"set_instance_assignment -name IO_STANDARD {${standard}} -to ${io.name}") 22 | } 23 | // def addPullup(io: IOPin) { 24 | // addConstraint(s"set_property PULLUP {TRUE} ${io.sdcPin}") 25 | // } 26 | // def addSlew(io: IOPin, speed: String) { 27 | // addConstraint(s"set_property SLEW {${speed}} ${io.sdcPin}") 28 | // } 29 | // TODO: Add input/output termination 30 | // def addTermination(io: IOPin, kind: String) { 31 | // addConstraint(s"set_property OFFCHIP_TERM {${kind}} ${io.sdcPin}") 32 | // } 33 | def addDriveStrength(io: IOPin, drive: String) { 34 | addConstraint(s"set_instance_assignment -name CURRENT_STRENGTH_NEW {${drive}} -to ${io.name}") 35 | } 36 | } 37 | 38 | abstract class AlteraShell()(implicit p: Parameters) extends IOShell 39 | { 40 | val sdc = new AlteraSDC("shell.sdc") 41 | val io_tcl = new IO_TCL("assign.tcl") 42 | def pllReset: ModuleValue[Bool] 43 | 44 | val pllFactory = new AlteraPLLFactory(this, 9, p => Module(new AlteraPLL(p))) 45 | 46 | sdc.addSDCDirective("derive_pll_clocks") 47 | sdc.addSDCDirective("derive_clock_uncertainty") 48 | 49 | override def designParameters = super.designParameters.alterPartial { 50 | case PLLFactoryKey => pllFactory 51 | } 52 | } 53 | 54 | 55 | /* 56 | Copyright 2016 SiFive, Inc. 57 | 58 | Licensed under the Apache License, Version 2.0 (the "License"); 59 | you may not use this file except in compliance with the License. 60 | You may obtain a copy of the License at 61 | 62 | http://www.apache.org/licenses/LICENSE-2.0 63 | 64 | Unless required by applicable law or agreed to in writing, software 65 | distributed under the License is distributed on an "AS IS" BASIS, 66 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 67 | See the License for the specific language governing permissions and 68 | limitations under the License. 69 | */ 70 | -------------------------------------------------------------------------------- /src/main/scala/shell/altera/ClockOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.altera 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.ip.altera._ 6 | import sifive.fpgashells.shell._ 7 | 8 | abstract class SingleEndedClockInputAlteraPlacedOverlay(name: String, di: ClockInputDesignInput, si: ClockInputShellInput) 9 | extends SingleEndedClockInputPlacedOverlay(name, di, si) 10 | { 11 | def shell: AlteraShell 12 | 13 | shell { InModuleBody { 14 | val (c, _) = node.out(0) 15 | 16 | c.clock := io 17 | c.reset := shell.pllReset 18 | } } 19 | } 20 | 21 | /* 22 | Copyright 2016 SiFive, Inc. 23 | 24 | Licensed under the Apache License, Version 2.0 (the "License"); 25 | you may not use this file except in compliance with the License. 26 | You may obtain a copy of the License at 27 | 28 | http://www.apache.org/licenses/LICENSE-2.0 29 | 30 | Unless required by applicable law or agreed to in writing, software 31 | distributed under the License is distributed on an "AS IS" BASIS, 32 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 33 | See the License for the specific language governing permissions and 34 | limitations under the License. 35 | */ 36 | -------------------------------------------------------------------------------- /src/main/scala/shell/altera/LEDOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.altera 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class LEDAlteraPlacedOverlay(name: String, di: LEDDesignInput, si: LEDShellInput, packagePin: Option[String] = None, ioStandard: String = "3.3-V LVTTL") 7 | extends LEDPlacedOverlay(name, di, si) 8 | { 9 | def shell: AlteraShell 10 | 11 | shell { InModuleBody { 12 | io := ledWire // could/should put OBUFs here? 13 | 14 | val ios = IOPin.of(io) 15 | 16 | (packagePin.toSeq zip ios) foreach { case (pin, io) => 17 | shell.io_tcl.addPackagePin(io, pin) 18 | shell.io_tcl.addIOStandard(io, ioStandard) 19 | } 20 | } } 21 | } 22 | 23 | /* 24 | Copyright 2016 SiFive, Inc. 25 | 26 | Licensed under the Apache License, Version 2.0 (the "License"); 27 | you may not use this file except in compliance with the License. 28 | You may obtain a copy of the License at 29 | 30 | http://www.apache.org/licenses/LICENSE-2.0 31 | 32 | Unless required by applicable law or agreed to in writing, software 33 | distributed under the License is distributed on an "AS IS" BASIS, 34 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 35 | See the License for the specific language governing permissions and 36 | limitations under the License. 37 | */ 38 | -------------------------------------------------------------------------------- /src/main/scala/shell/cJTAGDebugOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell 2 | 3 | import chisel3._ 4 | import chisel3.experimental.Analog 5 | import freechips.rocketchip.diplomacy._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.blocks.devices.pinctrl._ 8 | import sifive.fpgashells.ip.xilinx._ 9 | 10 | case class cJTAGDebugShellInput( 11 | color: String = "", 12 | header: String = "", 13 | rgb: Bool = false.B, 14 | number: Int = 0) 15 | 16 | case class cJTAGDebugDesignInput()(implicit val p: Parameters) 17 | case class cJTAGDebugOverlayOutput(cjtag: FPGAcJTAGSignals) 18 | trait cJTAGDebugShellPlacer[Shell] extends ShellPlacer[cJTAGDebugDesignInput, cJTAGDebugShellInput, cJTAGDebugOverlayOutput] 19 | 20 | case object cJTAGDebugOverlayKey extends Field[Seq[DesignPlacer[cJTAGDebugDesignInput, cJTAGDebugShellInput, cJTAGDebugOverlayOutput]]](Nil) 21 | 22 | class FPGAcJTAGIO extends Bundle { 23 | // cJTAG 24 | val cjtag_TCKC = Analog(1.W) 25 | val cjtag_TMSC = Analog(1.W) 26 | val srst_n = Analog(1.W) 27 | } 28 | 29 | class FPGAcJTAGSignals extends Bundle { 30 | val tckc_pin = Input(Clock()) 31 | val tmsc_pin = new BasePin() 32 | val srst_n = Input(Bool()) 33 | } 34 | 35 | abstract class cJTAGDebugPlacedOverlay( 36 | val name: String, val di: cJTAGDebugDesignInput, val si: cJTAGDebugShellInput) 37 | extends IOPlacedOverlay[FPGAcJTAGIO, cJTAGDebugDesignInput, cJTAGDebugShellInput, cJTAGDebugOverlayOutput] 38 | { 39 | implicit val p = di.p 40 | def ioFactory = new FPGAcJTAGIO 41 | 42 | val cjtagDebugSource = BundleBridgeSource(() => new FPGAcJTAGSignals) 43 | val cjtagDebugSink = shell { cjtagDebugSource.makeSink } 44 | 45 | def overlayOutput = cJTAGDebugOverlayOutput(cjtag = cjtagDebugSource.bundle ) 46 | 47 | shell { InModuleBody { 48 | cjtagDebugSink.bundle.tckc_pin := AnalogToUInt(io.cjtag_TCKC).asBool.asClock 49 | IOBUF(io.cjtag_TMSC, cjtagDebugSink.bundle.tmsc_pin) 50 | KEEPER(io.cjtag_TMSC) 51 | cjtagDebugSink.bundle.srst_n := IOBUF(io.srst_n) 52 | } } 53 | } 54 | 55 | /* 56 | Copyright 2016 SiFive, Inc. 57 | 58 | Licensed under the Apache License, Version 2.0 (the "License"); 59 | you may not use this file except in compliance with the License. 60 | You may obtain a copy of the License at 61 | 62 | http://www.apache.org/licenses/LICENSE-2.0 63 | 64 | Unless required by applicable law or agreed to in writing, software 65 | distributed under the License is distributed on an "AS IS" BASIS, 66 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 67 | See the License for the specific language governing permissions and 68 | limitations under the License. 69 | */ 70 | -------------------------------------------------------------------------------- /src/main/scala/shell/microsemi/ClockOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.microsemi 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.ip.microsemi._ 6 | import sifive.fpgashells.shell._ 7 | 8 | abstract class ClockInputMicrosemiPlacedOverlay(name: String, di: ClockInputDesignInput, si: ClockInputShellInput) 9 | extends SingleEndedClockInputPlacedOverlay(name, di, si) 10 | { 11 | def shell: MicrosemiShell 12 | 13 | shell { InModuleBody { 14 | val (c, _) = node.out(0) 15 | val clkint = Module(new CLKINT) 16 | clkint.suggestName(s"${name}_clkint") 17 | 18 | clkint.io.A := io 19 | c.clock := clkint.io.Y 20 | c.reset := false.B 21 | } } 22 | } 23 | 24 | /* 25 | Copyright 2016 SiFive, Inc. 26 | 27 | Licensed under the Apache License, Version 2.0 (the "License"); 28 | you may not use this file except in compliance with the License. 29 | You may obtain a copy of the License at 30 | 31 | http://www.apache.org/licenses/LICENSE-2.0 32 | 33 | Unless required by applicable law or agreed to in writing, software 34 | distributed under the License is distributed on an "AS IS" BASIS, 35 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 36 | See the License for the specific language governing permissions and 37 | limitations under the License. 38 | */ 39 | -------------------------------------------------------------------------------- /src/main/scala/shell/microsemi/LEDOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.microsemi 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class LEDMicrosemiPlacedOverlay(name: String, di: LEDDesignInput, si: LEDShellInput, pins: Seq[String] = Nil) 7 | extends LEDPlacedOverlay(name, di, si) 8 | { 9 | def shell: MicrosemiShell 10 | val width = pins.size 11 | 12 | shell { InModuleBody { 13 | io := ledWire // could/should put OBUFs here? 14 | (pins zip IOPin.of(io)) foreach { case (pin, io) => shell.io_pdc.addPin(io, pin) } 15 | } } 16 | } 17 | 18 | /* 19 | Copyright 2016 SiFive, Inc. 20 | 21 | Licensed under the Apache License, Version 2.0 (the "License"); 22 | you may not use this file except in compliance with the License. 23 | You may obtain a copy of the License at 24 | 25 | http://www.apache.org/licenses/LICENSE-2.0 26 | 27 | Unless required by applicable law or agreed to in writing, software 28 | distributed under the License is distributed on an "AS IS" BASIS, 29 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | See the License for the specific language governing permissions and 31 | limitations under the License. 32 | */ 33 | -------------------------------------------------------------------------------- /src/main/scala/shell/microsemi/PolarFireShell.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.microsemi 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.util._ 6 | import org.chipsalliance.cde.config._ 7 | import sifive.fpgashells.clocks._ 8 | import sifive.fpgashells.ip.microsemi.polarfireccc._ 9 | import sifive.fpgashells.ip.microsemi.polarfireinitmonitor._ 10 | import sifive.fpgashells.shell._ 11 | 12 | class IO_PDC(val name: String) 13 | { 14 | private var constraints: Seq[() => String] = Nil 15 | protected def addConstraint(command: => String) { constraints = (() => command) +: constraints } 16 | ElaborationArtefacts.add(name, constraints.map(_()).reverse.mkString("\n") + "\n") 17 | 18 | def addPin(io: IOPin, pin: String, ioStandard: String = "") { 19 | def dir = if (io.isInput) { if (io.isOutput) "INOUT" else "INPUT" } else { "OUTPUT" } 20 | def ioSt = if (!ioStandard.isEmpty) { 21 | require(ioStandard == "LVCMOS33") 22 | "-io_std LVCMOS33" 23 | } else {""} 24 | addConstraint(s"set_io -port_name {${io.name}} -pin_name ${pin} -fixed true -DIRECTION ${dir} ${ioSt} ") 25 | } 26 | } 27 | 28 | abstract class MicrosemiShell()(implicit p: Parameters) extends IOShell 29 | { 30 | val sdc = new SDC("shell.sdc") 31 | val io_pdc = new IO_PDC("shell.io.pdc") 32 | } 33 | 34 | abstract class PolarFireShell()(implicit p: Parameters) extends MicrosemiShell 35 | { 36 | val initMonitor = InModuleBody { Module(new PolarFireInitMonitor) } 37 | val pllFactory = new PLLFactory(this, 7, p => Module(new PolarFireCCC(p))) 38 | override def designParameters = super.designParameters.alterPartial { 39 | case PLLFactoryKey => pllFactory 40 | } 41 | } 42 | 43 | /* 44 | Copyright 2016 SiFive, Inc. 45 | 46 | Licensed under the Apache License, Version 2.0 (the "License"); 47 | you may not use this file except in compliance with the License. 48 | You may obtain a copy of the License at 49 | 50 | http://www.apache.org/licenses/LICENSE-2.0 51 | 52 | Unless required by applicable law or agreed to in writing, software 53 | distributed under the License is distributed on an "AS IS" BASIS, 54 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 55 | See the License for the specific language governing permissions and 56 | limitations under the License. 57 | */ 58 | -------------------------------------------------------------------------------- /src/main/scala/shell/package.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells 2 | 3 | import chisel3._ 4 | 5 | import scala.language.implicitConversions 6 | 7 | package object shell { 8 | implicit def boolToIOPin(x: Bool): IOPin = IOPin(x, 0) 9 | implicit def clockToIOPin(x: Clock): IOPin = IOPin(x, 0) 10 | } 11 | 12 | /* 13 | Copyright 2016 SiFive, Inc. 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/ButtonOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.ip.xilinx._ 6 | import sifive.fpgashells.shell._ 7 | 8 | abstract class ButtonXilinxPlacedOverlay(name: String, di: ButtonDesignInput, si: ButtonShellInput, boardPin: Option[String] = None, packagePin: Option[String] = None, ioStandard: String = "LVCMOS33") 9 | extends ButtonPlacedOverlay(name, di, si) 10 | { 11 | def shell: XilinxShell 12 | 13 | shell { InModuleBody { 14 | val but = Wire(Bool()) 15 | buttonWire := but 16 | val ibuf = Module(new IBUF) 17 | ibuf.suggestName(s"button_ibuf_${si.number}") 18 | ibuf.io.I := io 19 | but := ibuf.io.O 20 | 21 | require((boardPin.isEmpty || packagePin.isEmpty), "can't provide both boardpin and packagepin, this is ambiguous") 22 | val cutAt = if(boardPin.isDefined) 1 else 0 23 | val ios = IOPin.of(io) 24 | val boardIO = ios.take(cutAt) 25 | val packageIO = ios.drop(cutAt) 26 | 27 | (boardPin.toSeq zip boardIO) foreach { case (pin, io) => shell.xdc.addBoardPin (io, pin) } 28 | (packagePin.toSeq zip packageIO) foreach { case (pin, io) => 29 | shell.xdc.addPackagePin(io, pin) 30 | shell.xdc.addIOStandard(io, ioStandard) 31 | } 32 | } } 33 | } 34 | 35 | /* 36 | Copyright 2016 SiFive, Inc. 37 | 38 | Licensed under the Apache License, Version 2.0 (the "License"); 39 | you may not use this file except in compliance with the License. 40 | You may obtain a copy of the License at 41 | 42 | http://www.apache.org/licenses/LICENSE-2.0 43 | 44 | Unless required by applicable law or agreed to in writing, software 45 | distributed under the License is distributed on an "AS IS" BASIS, 46 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 47 | See the License for the specific language governing permissions and 48 | limitations under the License. 49 | */ 50 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/ChipLinkOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import freechips.rocketchip.util._ 6 | import sifive.fpgashells.ip.xilinx._ 7 | import sifive.fpgashells.shell._ 8 | 9 | abstract class ChipLinkXilinxPlacedOverlay(name: String, di: ChipLinkDesignInput, si: ChipLinkShellInput, rxPhase: Double, txPhase: Double, rxMargin: Double, txMargin: Double) 10 | extends ChipLinkPlacedOverlay(name, di.copy(di = di.di.copy(fpgaReset = true))(di.p), si, rxPhase, txPhase) 11 | { 12 | def shell: XilinxShell 13 | 14 | override def fpgaReset = true 15 | 16 | InModuleBody { 17 | // Provide reset pulse to initialize b2c_reset (before RX PLL locks) 18 | link.module.io.fpga_reset.foreach { _ := PowerOnResetFPGAOnly(Module.clock) } 19 | } 20 | 21 | shell { InModuleBody { 22 | val (tx, _) = txClock.in(0) 23 | val (rx, _) = rxI.out(0) 24 | val rxEdge = rxI.edges.out(0) 25 | 26 | val oddr = Module(new ODDR(DDR_CLK_EDGE = "SAME_EDGE", SRTYPE = "ASYNC")) 27 | oddr.suggestName(s"${name}_tx_oddr") 28 | io.c2b.clk := oddr.io.Q.asClock 29 | oddr.io.C := tx.clock 30 | oddr.io.CE := true.B 31 | oddr.io.D1 := true.B 32 | oddr.io.D2 := false.B 33 | oddr.io.S := false.B 34 | // We can't use tx.reset here as it waits for all PLLs to lock, 35 | // including RX, which depends on this clock being driven. 36 | // tap.reset only waits for the TX PLL to lock. 37 | oddr.io.R := ResetCatchAndSync(tx.clock, PowerOnResetFPGAOnly(tx.clock)) 38 | 39 | val ibufg = Module(new IBUFG) 40 | ibufg.suggestName(s"${name}_rx_ibufg") 41 | ibufg.io.I := io.b2c.clk 42 | rx.clock := ibufg.io.O 43 | rx.reset := shell.pllReset 44 | 45 | IOPin.of(io).foreach { shell.xdc.addIOStandard(_, "LVCMOS18") } 46 | IOPin.of(io).filterNot(_.element eq io.b2c.clk).foreach { shell.xdc.addIOB(_) } 47 | IOPin.of(io).filter(_.isOutput).foreach { shell.xdc.addSlew(_, "FAST") } 48 | 49 | val timing = IOTiming( 50 | /* The data signals coming from Aloe have: clock - 1.2 <= transition <= clock + 0.8 51 | * min = hold = - 1.2 52 | * max = period - setup = 0.8 53 | */ 54 | minInput = -1.2 - rxMargin, 55 | maxInput = 0.8 + rxMargin, 56 | /* The data signals going to Aloe must have: clock - 1.85 <= NO transition <= clock + 0.65 57 | * min = -hold = -0.65 58 | * max = setup = 1.85 59 | */ 60 | minOutput = -0.65 - txMargin, 61 | maxOutput = 1.85 + txMargin) 62 | 63 | shell.sdc.addClock(s"${name}_b2c_clock", io.b2c.clk, rxEdge.clock.get.freqMHz, 0.3) 64 | shell.sdc.addDerivedClock(s"${name}_c2b_clock", oddr.io.C, io.c2b.clk) 65 | IOPin.of(io).filter(p => p.isInput && !(p.element eq io.b2c.clk)).foreach { e => 66 | shell.sdc.addIOTiming(e, s"${name}_b2c_clock", timing) 67 | } 68 | IOPin.of(io).filter(p => p.isOutput && !(p.element eq io.c2b.clk)).foreach { e => 69 | shell.sdc.addIOTiming(e, s"${name}_c2b_clock", timing) 70 | } 71 | } } 72 | } 73 | 74 | /* 75 | Copyright 2016 SiFive, Inc. 76 | 77 | Licensed under the Apache License, Version 2.0 (the "License"); 78 | you may not use this file except in compliance with the License. 79 | You may obtain a copy of the License at 80 | 81 | http://www.apache.org/licenses/LICENSE-2.0 82 | 83 | Unless required by applicable law or agreed to in writing, software 84 | distributed under the License is distributed on an "AS IS" BASIS, 85 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 86 | See the License for the specific language governing permissions and 87 | limitations under the License. 88 | */ 89 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/ClockOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.ip.xilinx._ 6 | import sifive.fpgashells.shell._ 7 | 8 | abstract class LVDSClockInputXilinxPlacedOverlay(name: String, di: ClockInputDesignInput, si: ClockInputShellInput) 9 | extends LVDSClockInputPlacedOverlay(name, di, si) 10 | { 11 | def shell: XilinxShell 12 | 13 | shell { InModuleBody { 14 | val ibufds = Module(new IBUFDS) 15 | ibufds.suggestName(s"${name}_ibufds") 16 | 17 | val (c, _) = node.out(0) 18 | ibufds.io.I := io.p 19 | ibufds.io.IB := io.n 20 | c.clock := ibufds.io.O 21 | c.reset := shell.pllReset 22 | } } 23 | } 24 | 25 | 26 | abstract class SingleEndedClockInputXilinxPlacedOverlay(name: String, di: ClockInputDesignInput, si: ClockInputShellInput) 27 | extends SingleEndedClockInputPlacedOverlay(name, di, si) 28 | { 29 | def shell: XilinxShell 30 | 31 | shell { InModuleBody { 32 | val ibuf = Module(new IBUFG) 33 | ibuf.suggestName(s"${name}_ibufg") 34 | 35 | val (c, _) = node.out(0) 36 | ibuf.io.I := io 37 | c.clock := ibuf.io.O 38 | c.reset := shell.pllReset 39 | } } 40 | } 41 | 42 | /* 43 | Copyright 2016 SiFive, Inc. 44 | 45 | Licensed under the Apache License, Version 2.0 (the "License"); 46 | you may not use this file except in compliance with the License. 47 | You may obtain a copy of the License at 48 | 49 | http://www.apache.org/licenses/LICENSE-2.0 50 | 51 | Unless required by applicable law or agreed to in writing, software 52 | distributed under the License is distributed on an "AS IS" BASIS, 53 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 54 | See the License for the specific language governing permissions and 55 | limitations under the License. 56 | */ 57 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/GPIOPMODXilinxOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import sifive.fpgashells.shell._ 4 | 5 | abstract class GPIOPMODXilinxPlacedOverlay(name: String, di: GPIOPMODDesignInput, si: GPIOPMODShellInput) 6 | extends GPIOPMODPlacedOverlay(name, di, si) 7 | { 8 | def shell: XilinxShell 9 | } 10 | 11 | /* 12 | Copyright 2016 SiFive, Inc. 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/GPIOXilinxOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) 7 | extends GPIOPlacedOverlay(name, di, si) 8 | { 9 | def shell: XilinxShell 10 | 11 | shell { InModuleBody { 12 | tlgpioSink.bundle.pins.zipWithIndex.foreach{ case (tlpin, idx) => { 13 | UIntToAnalog(tlpin.o.oval, io.gpio(idx), tlpin.o.oe) 14 | tlpin.i.ival := AnalogToUInt(io.gpio(idx)) 15 | } } 16 | } } 17 | } 18 | 19 | /* 20 | Copyright 2016 SiFive, Inc. 21 | 22 | Licensed under the Apache License, Version 2.0 (the "License"); 23 | you may not use this file except in compliance with the License. 24 | You may obtain a copy of the License at 25 | 26 | http://www.apache.org/licenses/LICENSE-2.0 27 | 28 | Unless required by applicable law or agreed to in writing, software 29 | distributed under the License is distributed on an "AS IS" BASIS, 30 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | See the License for the specific language governing permissions and 32 | limitations under the License. 33 | */ 34 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/I2COverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class I2CXilinxPlacedOverlay(name: String, di: I2CDesignInput, si: I2CShellInput) 7 | extends I2CPlacedOverlay(name, di, si) 8 | { 9 | def shell: XilinxShell 10 | 11 | shell { InModuleBody { 12 | UIntToAnalog(tli2cSink.bundle.scl.out, io.scl, tli2cSink.bundle.scl.oe) 13 | UIntToAnalog(tli2cSink.bundle.sda.out, io.sda, tli2cSink.bundle.sda.oe) 14 | 15 | tli2cSink.bundle.scl.in := AnalogToUInt(io.scl) 16 | tli2cSink.bundle.sda.in := AnalogToUInt(io.sda) 17 | } } 18 | } 19 | 20 | /* 21 | Copyright 2016 SiFive, Inc. 22 | 23 | Licensed under the Apache License, Version 2.0 (the "License"); 24 | you may not use this file except in compliance with the License. 25 | You may obtain a copy of the License at 26 | 27 | http://www.apache.org/licenses/LICENSE-2.0 28 | 29 | Unless required by applicable law or agreed to in writing, software 30 | distributed under the License is distributed on an "AS IS" BASIS, 31 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 32 | See the License for the specific language governing permissions and 33 | limitations under the License. 34 | */ 35 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/JTAGDebugBScanOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.ip.xilinx.bscan2._ 6 | import sifive.fpgashells.shell._ 7 | 8 | abstract class JTAGDebugBScanXilinxPlacedOverlay(name: String, di: JTAGDebugBScanDesignInput, si: JTAGDebugBScanShellInput) 9 | extends JTAGDebugBScanPlacedOverlay(name, di, si) 10 | { 11 | def shell: XilinxShell 12 | 13 | shell { InModuleBody { 14 | val tmp_tck = Wire(Bool()) 15 | val tmp_tms = Wire(Bool()) 16 | val tmp_tdi = Wire(Bool()) 17 | val tmp_tdo = Wire(Bool()) 18 | val tmp_tdo_en = Wire(Bool()) 19 | 20 | JTAGTUNNEL(tmp_tck, tmp_tms, tmp_tdi, tmp_tdo, tmp_tdo_en) 21 | 22 | jtagDebugSink.bundle.TCK := tmp_tck.asClock 23 | jtagDebugSink.bundle.TMS := tmp_tms 24 | jtagDebugSink.bundle.TDI := tmp_tdi 25 | tmp_tdo := jtagDebugSink.bundle.TDO.data 26 | tmp_tdo_en := jtagDebugSink.bundle.TDO.driven 27 | } } 28 | } 29 | 30 | /* 31 | Copyright 2016 SiFive, Inc. 32 | 33 | Licensed under the Apache License, Version 2.0 (the "License"); 34 | you may not use this file except in compliance with the License. 35 | You may obtain a copy of the License at 36 | 37 | http://www.apache.org/licenses/LICENSE-2.0 38 | 39 | Unless required by applicable law or agreed to in writing, software 40 | distributed under the License is distributed on an "AS IS" BASIS, 41 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 42 | See the License for the specific language governing permissions and 43 | limitations under the License. 44 | */ 45 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/JTAGDebugOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class JTAGDebugXilinxPlacedOverlay(name: String, di: JTAGDebugDesignInput, si: JTAGDebugShellInput) 7 | extends JTAGDebugPlacedOverlay(name, di, si) 8 | { 9 | def shell: XilinxShell 10 | 11 | shell { InModuleBody { 12 | jtagDebugSink.bundle.TCK := AnalogToUInt(io.jtag_TCK).asBool.asClock 13 | jtagDebugSink.bundle.TMS := AnalogToUInt(io.jtag_TMS) 14 | jtagDebugSink.bundle.TDI := AnalogToUInt(io.jtag_TDI) 15 | UIntToAnalog(jtagDebugSink.bundle.TDO.data,io.jtag_TDO,jtagDebugSink.bundle.TDO.driven) 16 | jtagDebugSink.bundle.srst_n := AnalogToUInt(io.srst_n) 17 | } } 18 | } 19 | 20 | /* 21 | Copyright 2016 SiFive, Inc. 22 | 23 | Licensed under the Apache License, Version 2.0 (the "License"); 24 | you may not use this file except in compliance with the License. 25 | You may obtain a copy of the License at 26 | 27 | http://www.apache.org/licenses/LICENSE-2.0 28 | 29 | Unless required by applicable law or agreed to in writing, software 30 | distributed under the License is distributed on an "AS IS" BASIS, 31 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 32 | See the License for the specific language governing permissions and 33 | limitations under the License. 34 | */ 35 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/LEDOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class LEDXilinxPlacedOverlay(name: String, di: LEDDesignInput, si: LEDShellInput, boardPin: Option[String] = None, packagePin: Option[String] = None, ioStandard: String = "LVCMOS33") 7 | extends LEDPlacedOverlay(name, di, si) 8 | { 9 | def shell: XilinxShell 10 | 11 | shell { InModuleBody { 12 | io := ledWire // could/should put OBUFs here? 13 | 14 | require((boardPin.isEmpty || packagePin.isEmpty), "can't provide both boardpin and packagepin, this is ambiguous") 15 | val cutAt = if(boardPin.isDefined) 1 else 0 16 | val ios = IOPin.of(io) 17 | val boardIO = ios.take(cutAt) 18 | val packageIO = ios.drop(cutAt) 19 | 20 | (boardPin.toSeq zip boardIO) foreach { case (pin, io) => shell.xdc.addBoardPin (io, pin) } 21 | (packagePin.toSeq zip packageIO) foreach { case (pin, io) => 22 | shell.xdc.addPackagePin(io, pin) 23 | shell.xdc.addIOStandard(io, ioStandard) 24 | } 25 | } } 26 | } 27 | 28 | /* 29 | Copyright 2016 SiFive, Inc. 30 | 31 | Licensed under the Apache License, Version 2.0 (the "License"); 32 | you may not use this file except in compliance with the License. 33 | You may obtain a copy of the License at 34 | 35 | http://www.apache.org/licenses/LICENSE-2.0 36 | 37 | Unless required by applicable law or agreed to in writing, software 38 | distributed under the License is distributed on an "AS IS" BASIS, 39 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | See the License for the specific language governing permissions and 41 | limitations under the License. 42 | */ 43 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/PMODOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class PMODXilinxPlacedOverlay(name: String, di: PMODDesignInput, si: PMODShellInput, boardPin: Seq[String] = Seq(), packagePin: Seq[String] = Seq(), ioStandard: String = "LVCMOS33") 7 | extends PMODPlacedOverlay(name, di, si) 8 | { 9 | def shell: XilinxShell 10 | 11 | shell { InModuleBody { 12 | require((boardPin.isEmpty || packagePin.isEmpty), "can't provide both boardpin and packagepin, this is ambiguous") 13 | val cutAt = boardPin.length 14 | val ios = IOPin.of(io) 15 | val boardIO = ios.take(cutAt) 16 | val packageIO = ios.drop(cutAt) 17 | 18 | (boardPin zip boardIO) foreach { case (pin, io) => shell.xdc.addBoardPin (io, pin) } 19 | (packagePin zip packageIO) foreach { case (pin, io) => 20 | shell.xdc.addPackagePin(io, pin) 21 | shell.xdc.addIOStandard(io, ioStandard) 22 | } 23 | } } 24 | } 25 | 26 | /* 27 | Copyright 2016 SiFive, Inc. 28 | 29 | Licensed under the Apache License, Version 2.0 (the "License"); 30 | you may not use this file except in compliance with the License. 31 | You may obtain a copy of the License at 32 | 33 | http://www.apache.org/licenses/LICENSE-2.0 34 | 35 | Unless required by applicable law or agreed to in writing, software 36 | distributed under the License is distributed on an "AS IS" BASIS, 37 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 38 | See the License for the specific language governing permissions and 39 | limitations under the License. 40 | */ 41 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/PWMOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.shell._ 6 | 7 | abstract class PWMXilinxPlacedOverlay(name: String, di: PWMDesignInput, si: PWMShellInput) 8 | extends PWMPlacedOverlay(name, di, si) 9 | { 10 | def shell: XilinxShell 11 | 12 | shell { InModuleBody { 13 | tlpwmSink.bundle.gpio.zip(io.pwm_gpio).foreach { case(design_pwm, io_pwm) => 14 | UIntToAnalog(design_pwm, io_pwm, true.B) 15 | } 16 | } } 17 | } 18 | 19 | /* 20 | Copyright 2016 SiFive, Inc. 21 | 22 | Licensed under the Apache License, Version 2.0 (the "License"); 23 | you may not use this file except in compliance with the License. 24 | You may obtain a copy of the License at 25 | 26 | http://www.apache.org/licenses/LICENSE-2.0 27 | 28 | Unless required by applicable law or agreed to in writing, software 29 | distributed under the License is distributed on an "AS IS" BASIS, 30 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | See the License for the specific language governing permissions and 32 | limitations under the License. 33 | */ 34 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/PinXilinxOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import sifive.fpgashells.shell._ 4 | 5 | abstract class PinXilinxPlacedOverlay(name: String, di: PinDesignInput, si: PinShellInput) 6 | extends PinPlacedOverlay(name, di, si) 7 | { 8 | def shell: XilinxShell 9 | } 10 | 11 | /* 12 | Copyright 2016 SiFive, Inc. 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/SDIOOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.shell._ 6 | 7 | abstract class SDIOXilinxPlacedOverlay(name: String, di: SPIDesignInput, si: SPIShellInput) 8 | extends SPIPlacedOverlay(name, di, si) 9 | { 10 | def shell: XilinxShell 11 | 12 | InModuleBody { 13 | val tlspiport = tlspiSink.bundle 14 | spiSource.bundle.sck := tlspiport.sck 15 | spiSource.bundle.dq.zip(tlspiport.dq).foreach { case(outerBundle, innerBundle) => 16 | outerBundle.o := innerBundle.o 17 | outerBundle.oe := innerBundle.oe 18 | innerBundle.i := RegNext(RegNext(outerBundle.i)) 19 | } 20 | spiSource.bundle.cs := tlspiport.cs 21 | } 22 | 23 | shell { InModuleBody { 24 | val sd_spi_sck = spiSink.bundle.sck 25 | val sd_spi_cs = spiSink.bundle.cs(0) 26 | 27 | val sd_spi_dq_i = Wire(Vec(4, Bool())) 28 | val sd_spi_dq_o = Wire(Vec(4, Bool())) 29 | 30 | spiSink.bundle.dq.zipWithIndex.foreach { 31 | case(pin, idx) => 32 | sd_spi_dq_o(idx) := pin.o 33 | pin.i := sd_spi_dq_i(idx) 34 | } 35 | 36 | UIntToAnalog(sd_spi_sck, io.spi_clk, true.B) 37 | UIntToAnalog(sd_spi_cs, io.spi_dat(3), true.B) 38 | UIntToAnalog(sd_spi_dq_o(0), io.spi_cs, true.B) 39 | sd_spi_dq_i := Seq(false.B, AnalogToUInt(io.spi_dat(0)).asBool, false.B, false.B) 40 | } } 41 | } 42 | 43 | /* 44 | Copyright 2016 SiFive, Inc. 45 | 46 | Licensed under the Apache License, Version 2.0 (the "License"); 47 | you may not use this file except in compliance with the License. 48 | You may obtain a copy of the License at 49 | 50 | http://www.apache.org/licenses/LICENSE-2.0 51 | 52 | Unless required by applicable law or agreed to in writing, software 53 | distributed under the License is distributed on an "AS IS" BASIS, 54 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 55 | See the License for the specific language governing permissions and 56 | limitations under the License. 57 | */ 58 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/SPIFlashXilinxOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import chisel3.util.Cat 5 | import freechips.rocketchip.diplomacy._ 6 | import sifive.fpgashells.ip.xilinx._ 7 | import sifive.fpgashells.shell._ 8 | 9 | abstract class SPIFlashXilinxPlacedOverlay(name: String, di: SPIFlashDesignInput, si: SPIFlashShellInput) 10 | extends SPIFlashPlacedOverlay(name, di, si) 11 | { 12 | def shell: XilinxShell 13 | 14 | //val dqiVec = VecInit.tabulate(4)(j =>tlqspiSink.bundle.dq(j)) 15 | shell { InModuleBody { 16 | if (!si.vcu118SU) { 17 | UIntToAnalog(tlqspiSink.bundle.sck , io.qspi_sck, true.B) 18 | UIntToAnalog(tlqspiSink.bundle.cs(0), io.qspi_cs , true.B) 19 | 20 | tlqspiSink.bundle.dq.zip(io.qspi_dq).foreach { case(design_dq, io_dq) => 21 | UIntToAnalog(design_dq.o, io_dq, design_dq.oe) 22 | design_dq.i := AnalogToUInt(io_dq) 23 | } 24 | } else { 25 | // If on vcu118, to communicate with Flash, STARTUPE3 primitive needs to be connected and hooked uo tp 26 | // spi, rather than a top level connection 27 | val se3 = Module(new STARTUPE3()) 28 | se3.io.USRDONEO := true.B 29 | se3.io.USRDONETS := true.B 30 | se3.io.USRCCLKO := tlqspiSink.bundle.sck.asClock 31 | se3.io.USRCCLKTS := false.B 32 | se3.io.FCSBO := tlqspiSink.bundle.cs(0) 33 | se3.io.FCSBTS := false.B 34 | se3.io.DO := Cat(tlqspiSink.bundle.dq.map(_.o)) 35 | se3.io.DTS := Cat(tlqspiSink.bundle.dq.map(_.oe)) 36 | tlqspiSink.bundle.dq(0).i := se3.io.DI(0) 37 | tlqspiSink.bundle.dq(1).i := se3.io.DI(1) 38 | tlqspiSink.bundle.dq(2).i := se3.io.DI(2) 39 | tlqspiSink.bundle.dq(3).i := se3.io.DI(3) 40 | se3.io.GSR := false.B 41 | se3.io.GTS := false.B 42 | se3.io.KEYCLEARB := false.B 43 | se3.io.PACK := false.B 44 | } 45 | } } 46 | } 47 | 48 | /* 49 | Copyright 2016 SiFive, Inc. 50 | 51 | Licensed under the Apache License, Version 2.0 (the "License"); 52 | you may not use this file except in compliance with the License. 53 | You may obtain a copy of the License at 54 | 55 | http://www.apache.org/licenses/LICENSE-2.0 56 | 57 | Unless required by applicable law or agreed to in writing, software 58 | distributed under the License is distributed on an "AS IS" BASIS, 59 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 60 | See the License for the specific language governing permissions and 61 | limitations under the License. 62 | */ 63 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/SwitchOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.ip.xilinx._ 6 | import sifive.fpgashells.shell._ 7 | 8 | abstract class SwitchXilinxPlacedOverlay(name: String, di: SwitchDesignInput, si: SwitchShellInput, boardPin: Option[String] = None, packagePin: Option[String] = None, ioStandard: String = "LVCMOS33") 9 | extends SwitchPlacedOverlay(name, di, si) 10 | { 11 | def shell: XilinxShell 12 | 13 | shell { InModuleBody { 14 | val bwire = Wire(Bool()) 15 | switchWire := bwire.asUInt 16 | val ibuf = Module(new IBUF) 17 | ibuf.suggestName(s"switch_ibuf_${si.number}") 18 | ibuf.io.I := io 19 | bwire := ibuf.io.O 20 | 21 | require((boardPin.isEmpty || packagePin.isEmpty), "can't provide both boardpin and packagepin, this is ambiguous") 22 | val cutAt = if(boardPin.isDefined) 1 else 0 23 | val ios = IOPin.of(io) 24 | val boardIO = ios.take(cutAt) 25 | val packageIO = ios.drop(cutAt) 26 | 27 | (boardPin.toSeq zip boardIO) foreach { case (pin, io) => shell.xdc.addBoardPin (io, pin) } 28 | (packagePin.toSeq zip packageIO) foreach { case (pin, io) => 29 | shell.xdc.addPackagePin(io, pin) 30 | shell.xdc.addIOStandard(io, ioStandard) 31 | } 32 | } } 33 | } 34 | 35 | /* 36 | Copyright 2016 SiFive, Inc. 37 | 38 | Licensed under the Apache License, Version 2.0 (the "License"); 39 | you may not use this file except in compliance with the License. 40 | You may obtain a copy of the License at 41 | 42 | http://www.apache.org/licenses/LICENSE-2.0 43 | 44 | Unless required by applicable law or agreed to in writing, software 45 | distributed under the License is distributed on an "AS IS" BASIS, 46 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 47 | See the License for the specific language governing permissions and 48 | limitations under the License. 49 | */ 50 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/TracePMODOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import freechips.rocketchip.diplomacy._ 4 | import sifive.fpgashells.shell._ 5 | 6 | abstract class TracePMODXilinxPlacedOverlay(name: String, di: TracePMODDesignInput, si: TracePMODShellInput, boardPins: Seq[String] = Nil, packagePins: Seq[String] = Nil, ioStandard: String = "LVCMOS33") 7 | extends TracePMODPlacedOverlay(name, di, si) 8 | { 9 | def shell: XilinxShell 10 | val width = boardPins.size + packagePins.size 11 | 12 | shell { InModuleBody { 13 | io := pmodTraceSink.bundle 14 | 15 | val cutAt = boardPins.size 16 | val ios = IOPin.of(io) 17 | val boardIOs = ios.take(cutAt) 18 | val packageIOs = ios.drop(cutAt) 19 | 20 | (boardPins zip boardIOs) foreach { case (pin, io) => shell.xdc.addBoardPin (io, pin) } 21 | (packagePins zip packageIOs) foreach { case (pin, io) => 22 | shell.xdc.addPackagePin(io, pin) 23 | shell.xdc.addIOStandard(io, ioStandard) 24 | } 25 | } } 26 | } 27 | 28 | /* 29 | Copyright 2016 SiFive, Inc. 30 | 31 | Licensed under the Apache License, Version 2.0 (the "License"); 32 | you may not use this file except in compliance with the License. 33 | You may obtain a copy of the License at 34 | 35 | http://www.apache.org/licenses/LICENSE-2.0 36 | 37 | Unless required by applicable law or agreed to in writing, software 38 | distributed under the License is distributed on an "AS IS" BASIS, 39 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 40 | See the License for the specific language governing permissions and 41 | limitations under the License. 42 | */ 43 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/UARTOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.diplomacy._ 5 | import sifive.fpgashells.shell._ 6 | 7 | abstract class UARTXilinxPlacedOverlay(name: String, di: UARTDesignInput, si: UARTShellInput, flowControl: Boolean) 8 | extends UARTPlacedOverlay(name, di, si, flowControl) 9 | { 10 | def shell: XilinxShell 11 | 12 | shell { InModuleBody { 13 | UIntToAnalog(tluartSink.bundle.txd, io.txd, true.B) 14 | tluartSink.bundle.rxd := AnalogToUInt(io.rxd) 15 | } } 16 | } 17 | 18 | /* 19 | Copyright 2016 SiFive, Inc. 20 | 21 | Licensed under the Apache License, Version 2.0 (the "License"); 22 | you may not use this file except in compliance with the License. 23 | You may obtain a copy of the License at 24 | 25 | http://www.apache.org/licenses/LICENSE-2.0 26 | 27 | Unless required by applicable law or agreed to in writing, software 28 | distributed under the License is distributed on an "AS IS" BASIS, 29 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30 | See the License for the specific language governing permissions and 31 | limitations under the License. 32 | */ 33 | -------------------------------------------------------------------------------- /src/main/scala/shell/xilinx/cJTAGDebugOverlay.scala: -------------------------------------------------------------------------------- 1 | package sifive.fpgashells.shell.xilinx 2 | 3 | import sifive.fpgashells.shell._ 4 | 5 | abstract class cJTAGDebugXilinxPlacedOverlay(name: String, di: cJTAGDebugDesignInput, si: cJTAGDebugShellInput) 6 | extends cJTAGDebugPlacedOverlay(name, di, si) 7 | { 8 | def shell: XilinxShell 9 | } 10 | 11 | /* 12 | Copyright 2016 SiFive, Inc. 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | -------------------------------------------------------------------------------- /vsrc/nfmac10g/rst_mod.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2016 University of Cambridge All rights reserved. 3 | // 4 | // Author: Marco Forconesi 5 | // 6 | // This software was developed with the support of 7 | // Prof. Gustavo Sutter and Prof. Sergio Lopez-Buedo and 8 | // University of Cambridge Computer Laboratory NetFPGA team. 9 | // 10 | // @NETFPGA_LICENSE_HEADER_START@ 11 | // 12 | // Licensed to NetFPGA C.I.C. (NetFPGA) under one or more 13 | // contributor license agreements. See the NOTICE file distributed with this 14 | // work for additional information regarding copyright ownership. NetFPGA 15 | // licenses this file to you under the NetFPGA Hardware-Software License, 16 | // Version 1.0 (the "License"); you may not use this file except in compliance 17 | // with the License. You may obtain a copy of the License at: 18 | // 19 | // http://www.netfpga-cic.org 20 | // 21 | // Unless required by applicable law or agreed to in writing, Work distributed 22 | // under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 23 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 24 | // specific language governing permissions and limitations under the License. 25 | // 26 | // @NETFPGA_LICENSE_HEADER_END@ 27 | 28 | ////////////////////////////////////////////////////////////////////////////// 29 | ////////////////////////////////////////////////////////////////////////////// 30 | `timescale 1ns / 1ps 31 | //`default_nettype none 32 | 33 | module rst_mod ( 34 | 35 | // Clks and resets 36 | input clk, 37 | input reset, 38 | input dcm_locked, 39 | 40 | // Output 41 | output reg rst 42 | ); 43 | 44 | // localparam 45 | localparam s0 = 8'b00000001; 46 | localparam s1 = 8'b00000010; 47 | localparam s2 = 8'b00000100; 48 | localparam s3 = 8'b00001000; 49 | localparam s4 = 8'b00010000; 50 | localparam s5 = 8'b00100000; 51 | localparam s6 = 8'b01000000; 52 | localparam s7 = 8'b10000000; 53 | 54 | //------------------------------------------------------- 55 | // Local gen_rst 56 | //------------------------------------------------------- 57 | reg [7:0] fsm = 'b1; 58 | 59 | //////////////////////////////////////////////// 60 | // gen_rst 61 | //////////////////////////////////////////////// 62 | always @(posedge clk or posedge reset) begin 63 | 64 | if (reset) begin // reset 65 | rst <= 1'b1; 66 | fsm <= s0; 67 | end 68 | 69 | else begin // not reset 70 | 71 | case (fsm) 72 | 73 | s0 : begin 74 | rst <= 1'b1; 75 | fsm <= s1; 76 | end 77 | 78 | s1 : fsm <= s2; 79 | s2 : fsm <= s3; 80 | s3 : fsm <= s4; 81 | 82 | s4 : begin 83 | if (dcm_locked) begin 84 | fsm <= s5; 85 | end 86 | end 87 | 88 | s5 : begin 89 | rst <= 1'b0; 90 | end 91 | 92 | default : begin 93 | fsm <= s0; 94 | end 95 | 96 | endcase 97 | end // not reset 98 | end //always 99 | 100 | endmodule // rst_mod 101 | 102 | ////////////////////////////////////////////////////////////////////////////// 103 | ////////////////////////////////////////////////////////////////////////////// -------------------------------------------------------------------------------- /wit-manifest.json: -------------------------------------------------------------------------------- 1 | [ 2 | { 3 | "commit": "6a0addc8e78bec308e2888f614fe3be6768c0d34", 4 | "name": "api-generator-sifive", 5 | "source": "git@github.com:sifive/api-generator-sifive.git" 6 | }, 7 | { 8 | "commit": "612ed01df3be83ad0198fb9bd7e367ea43df3d56", 9 | "name": "sifive-blocks", 10 | "source": "git@github.com:sifive/sifive-blocks.git" 11 | }, 12 | { 13 | "commit": "203d59b05677663ce69c68b6a0685604f1588f76", 14 | "name": "rocket-chip", 15 | "source": "git@github.com:chipsalliance/rocket-chip.git" 16 | } 17 | ] 18 | -------------------------------------------------------------------------------- /xilinx/Makefile: -------------------------------------------------------------------------------- 1 | VIVADO ?= vivado 2 | VIVADOFLAGS := \ 3 | -nojournal -mode batch \ 4 | -source $(fpga_board_script_dir)/board.tcl \ 5 | -source $(fpga_common_script_dir)/prologue.tcl 6 | 7 | # Path to a program in raw binary format to be flashed into the address that the 8 | # bootrom jumps to. 9 | # FIXME: This variable should probably be communicated by a higher-level Makefile 10 | FLASHED_PROGRAM ?= 11 | 12 | # Init project 13 | init = $(FPGA_BUILD_DIR)/.init 14 | $(init): $(fpga_common_script_dir)/init.tcl 15 | mkdir -p $(FPGA_BUILD_DIR) && \ 16 | cd $(FPGA_BUILD_DIR) && \ 17 | VSRCS="$(VSRCS)" IPVIVADOTCLS="$(IPVIVADOTCLS)" $(VIVADO) $(VIVADOFLAGS) -source $< 18 | 19 | .PHONY: init 20 | init: $(init) 21 | 22 | # Generate bitstream 23 | bit := $(FPGA_BUILD_DIR)/obj/$(FPGA_TOP_SYSTEM).bit 24 | $(bit): $(fpga_common_script_dir)/vivado.tcl $(init) 25 | cd $(FPGA_BUILD_DIR) && \ 26 | VSRCS="$(VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source $< 27 | 28 | .PHONY: bit 29 | bit: $(bit) 30 | 31 | # Generate mcs 32 | mcs := $(FPGA_BUILD_DIR)/obj/system.mcs 33 | $(mcs): $(bit) 34 | cd $(FPGA_BUILD_DIR) && \ 35 | $(VIVADO) $(VIVADOFLAGS) $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $^ $(FLASHED_PROGRAM) 36 | 37 | .PHONY: mcs 38 | mcs: $(mcs) 39 | 40 | .PHONY: clean 41 | clean:: 42 | rm -rf $(FPGA_BUILD_DIR) 43 | -------------------------------------------------------------------------------- /xilinx/alinx_axku040/constraints/alinx_axku040.xdc: -------------------------------------------------------------------------------- 1 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 2 | set_property CFGBVS VCCO [current_design] 3 | set_property CONFIG_VOLTAGE 3.3 [current_design] 4 | set_property CONFIG_MODE SPIx4 [current_design] 5 | -------------------------------------------------------------------------------- /xilinx/alinx_axku040/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | set name {alinx-axku040} 2 | set part_fpga {xcku040-ffva1156-2-i} 3 | set part_board {} 4 | -------------------------------------------------------------------------------- /xilinx/arty/constraints/arty-config.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict [list \ 2 | CONFIG_VOLTAGE {3.3} \ 3 | CFGBVS {VCCO} \ 4 | BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \ 5 | ] [current_design] 6 | -------------------------------------------------------------------------------- /xilinx/arty/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | set name {arty} 3 | set part_fpga {xc7a35ticsg324-1L} 4 | set part_board {digilentinc.com:arty:part0:1.1} 5 | set bootrom_inst {rom} 6 | -------------------------------------------------------------------------------- /xilinx/arty/tcl/ip.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force 4 | set_property -dict [list \ 5 | CONFIG.PRIMITIVE {MMCM} \ 6 | CONFIG.RESET_TYPE {ACTIVE_LOW} \ 7 | CONFIG.CLKOUT1_USED {true} \ 8 | CONFIG.CLKOUT2_USED {true} \ 9 | CONFIG.CLKOUT3_USED {true} \ 10 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \ 11 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \ 12 | CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {32.500} \ 13 | ] [get_ips mmcm] 14 | 15 | create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force 16 | set_property -dict [list \ 17 | CONFIG.C_EXT_RESET_HIGH {false} \ 18 | CONFIG.C_AUX_RESET_HIGH {false} \ 19 | CONFIG.C_NUM_BUS_RST {1} \ 20 | CONFIG.C_NUM_PERP_RST {1} \ 21 | CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \ 22 | CONFIG.C_NUM_PERP_ARESETN {1} \ 23 | ] [get_ips reset_sys] 24 | 25 | create_ip -vendor xilinx.com -library ip -name ila -module_name ila -dir $ipdir -force 26 | set_property -dict [list \ 27 | CONFIG.C_NUM_OF_PROBES {1} \ 28 | CONFIG.C_TRIGOUT_EN {false} \ 29 | CONFIG.C_TRIGIN_EN {false} \ 30 | CONFIG.C_MONITOR_TYPE {Native} \ 31 | CONFIG.C_ENABLE_ILA_AXI_MON {false} \ 32 | CONFIG.C_PROBE0_WIDTH {4} \ 33 | CONFIG.C_PROBE10_TYPE {1} \ 34 | CONFIG.C_PROBE10_WIDTH {32} \ 35 | CONFIG.C_PROBE11_TYPE {1} \ 36 | CONFIG.C_PROBE11_WIDTH {32} \ 37 | CONFIG.C_PROBE12_TYPE {1} \ 38 | CONFIG.C_PROBE12_WIDTH {64} \ 39 | CONFIG.C_PROBE13_TYPE {1} \ 40 | CONFIG.C_PROBE13_WIDTH {64} \ 41 | CONFIG.C_PROBE14_TYPE {1} \ 42 | CONFIG.C_PROBE14_WIDTH {97} \ 43 | ] [get_ips ila] 44 | 45 | -------------------------------------------------------------------------------- /xilinx/arty_a7_100/constraints/arty-config.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict [list \ 2 | CONFIG_VOLTAGE {3.3} \ 3 | CFGBVS {VCCO} \ 4 | BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \ 5 | ] [current_design] 6 | -------------------------------------------------------------------------------- /xilinx/arty_a7_100/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | set name {arty-a7-100} 3 | set part_fpga {xc7a100ticsg324-1L} 4 | set part_board {digilentinc.com:arty-a7-100:part0:1.1} 5 | set bootrom_inst {rom} 6 | -------------------------------------------------------------------------------- /xilinx/arty_a7_100/tcl/ip.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force 4 | set_property -dict [list \ 5 | CONFIG.PRIMITIVE {MMCM} \ 6 | CONFIG.RESET_TYPE {ACTIVE_LOW} \ 7 | CONFIG.CLKOUT1_USED {true} \ 8 | CONFIG.CLKOUT2_USED {true} \ 9 | CONFIG.CLKOUT3_USED {true} \ 10 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \ 11 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \ 12 | CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {32.500} \ 13 | ] [get_ips mmcm] 14 | 15 | create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force 16 | set_property -dict [list \ 17 | CONFIG.C_EXT_RESET_HIGH {false} \ 18 | CONFIG.C_AUX_RESET_HIGH {false} \ 19 | CONFIG.C_NUM_BUS_RST {1} \ 20 | CONFIG.C_NUM_PERP_RST {1} \ 21 | CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \ 22 | CONFIG.C_NUM_PERP_ARESETN {1} \ 23 | ] [get_ips reset_sys] 24 | 25 | create_ip -vendor xilinx.com -library ip -name ila -module_name ila -dir $ipdir -force 26 | set_property -dict [list \ 27 | CONFIG.C_NUM_OF_PROBES {1} \ 28 | CONFIG.C_TRIGOUT_EN {false} \ 29 | CONFIG.C_TRIGIN_EN {false} \ 30 | CONFIG.C_MONITOR_TYPE {Native} \ 31 | CONFIG.C_ENABLE_ILA_AXI_MON {false} \ 32 | CONFIG.C_PROBE0_WIDTH {4} \ 33 | CONFIG.C_PROBE10_TYPE {1} \ 34 | CONFIG.C_PROBE10_WIDTH {32} \ 35 | CONFIG.C_PROBE11_TYPE {1} \ 36 | CONFIG.C_PROBE11_WIDTH {32} \ 37 | CONFIG.C_PROBE12_TYPE {1} \ 38 | CONFIG.C_PROBE12_WIDTH {64} \ 39 | CONFIG.C_PROBE13_TYPE {1} \ 40 | CONFIG.C_PROBE13_WIDTH {64} \ 41 | CONFIG.C_PROBE14_TYPE {1} \ 42 | CONFIG.C_PROBE14_WIDTH {97} \ 43 | ] [get_ips ila] 44 | -------------------------------------------------------------------------------- /xilinx/common/tcl/bitstream.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Write a bitstream for the current design 4 | write_bitstream -force [file join $wrkdir "${top}.bit"] 5 | 6 | # Save the timing delays for cells in the design in SDF format 7 | write_sdf -force [file join $wrkdir "${top}.sdf"] 8 | 9 | # Export the current netlist in verilog format 10 | write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"] 11 | -------------------------------------------------------------------------------- /xilinx/common/tcl/boards.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | namespace eval ::program::boards {} 4 | 5 | set ::program::boards::spec [dict create \ 6 | arty [dict create iface spix4 size 16 bitaddr 0x0 memdev {n25q128-3.3v-spi-x1_x2_x4}] \ 7 | arty_a7_100 [dict create iface spix4 size 16 bitaddr 0x0 memdev {s25fl128sxxxxxx0-spi-x1_x2_x4}] \ 8 | nexys_video [dict create iface spix4 size 32 bitaddr 0x0 memdev {s25fl256sxxxxxx0-spi-x1_x2_x4}] \ 9 | vc707 [dict create iface bpix16 size 128 bitaddr 0x3000000 ] \ 10 | vcu118 [dict create iface spix8 size 256 bitaddr 0x0 memdev {mt25qu01g-spi-x1_x2_x4_x8}]] 11 | -------------------------------------------------------------------------------- /xilinx/common/tcl/init.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Include helper functions 4 | source [file join $scriptdir "util.tcl"] 5 | 6 | # Create the directory for IPs 7 | file mkdir $ipdir 8 | 9 | # Update the IP catalog 10 | update_ip_catalog -rebuild 11 | 12 | # Generate IP implementations. Vivado TCL emitted from Chisel Blackboxes 13 | foreach ip_vivado_tcl $ip_vivado_tcls { 14 | source $ip_vivado_tcl 15 | } 16 | # Optional board-specific ip script 17 | set boardiptcl [file join $boarddir tcl ip.tcl] 18 | if {[file exists $boardiptcl]} { 19 | source $boardiptcl 20 | } 21 | 22 | # AR 58526 23 | set xci_files [get_files -all {*.xci}] 24 | foreach xci_file $xci_files { 25 | set_property GENERATE_SYNTH_CHECKPOINT {false} -quiet $xci_file 26 | } 27 | 28 | # Get a list of IPs in the current design 29 | set obj [get_ips] 30 | 31 | # Generate target data for the included IPs in the design 32 | generate_target all $obj 33 | 34 | # Export the IP user files 35 | export_ip_user_files -of_objects $obj -no_script -force 36 | 37 | # Get the list of active source and constraint files 38 | set obj [current_fileset] 39 | 40 | #Xilinx bug workaround 41 | #scrape IP tree for directories containing .vh files 42 | #[get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip 43 | set property_include_dirs [get_property include_dirs $obj] 44 | 45 | # Include generated files for the IPs in the design 46 | set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]] 47 | set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]] 48 | set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]] 49 | -------------------------------------------------------------------------------- /xilinx/common/tcl/opt.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Optimize the netlist 4 | opt_design -directive Explore 5 | 6 | # Checkpoint the current design 7 | write_checkpoint -force [file join $wrkdir post_opt] 8 | -------------------------------------------------------------------------------- /xilinx/common/tcl/place.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Place the current design 4 | place_design -directive Explore 5 | 6 | # Optimize the current placed netlist 7 | phys_opt_design -directive Explore 8 | 9 | # Optimize dynamic power using intelligent clock gating 10 | power_opt_design 11 | 12 | # Checkpoint the current design 13 | write_checkpoint -force [file join $wrkdir post_place] 14 | -------------------------------------------------------------------------------- /xilinx/common/tcl/report.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Create a report directory 4 | set rptdir [file join $wrkdir report] 5 | file mkdir $rptdir 6 | 7 | # Create a datasheet for the current design 8 | report_datasheet -file [file join $rptdir datasheet.txt] 9 | 10 | # Report utilization of the current device 11 | set rptutil [file join $rptdir utilization.txt] 12 | report_utilization -hierarchical -file $rptutil 13 | 14 | # Report information about clock nets in the design 15 | report_clock_utilization -file $rptutil -append 16 | 17 | # Report the RAM resources utilized in the implemented design 18 | report_ram_utilization -file $rptutil -append -detail 19 | 20 | # Report timing summary for a max of 10 paths per group 21 | report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10 22 | 23 | # Report the highest fanout of nets in the implemented design 24 | report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25 25 | 26 | # Run DRC 27 | report_drc -file [file join $rptdir drc.txt] 28 | 29 | # Report details of the IO banks in the design 30 | report_io -file [file join $rptdir io.txt] 31 | 32 | # Report a table of all clocks in the design 33 | report_clocks -file [file join $rptdir clocks.txt] 34 | 35 | # Fail loudly if timing not met 36 | # 37 | # We would ideally elevate critical warning Route 35-39 to an error, but it is 38 | # currently not being emitted with our flow for some reason. 39 | # https://forums.xilinx.com/t5/Implementation/Making-timing-violations-fatal-to-the-Vivado-build/m-p/716957#M15979 40 | set timing_slack [get_property SLACK [get_timing_paths]] 41 | if {$timing_slack < 0} { 42 | puts "Failed to meet timing by $timing_slack, see [file join $rptdir timing.txt]" 43 | exit 1 44 | } 45 | -------------------------------------------------------------------------------- /xilinx/common/tcl/route.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Route the current design 4 | route_design -directive Explore 5 | 6 | # Optimize the current design post routing 7 | phys_opt_design -directive Explore 8 | 9 | # Checkpoint the current design 10 | write_checkpoint -force [file join $wrkdir post_route] 11 | -------------------------------------------------------------------------------- /xilinx/common/tcl/synth-only.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Set the variable for the directory that includes all scripts 4 | set scriptdir [file dirname [info script]] 5 | 6 | # Set up variables and Vivado objects 7 | source [file join $scriptdir "prologue.tcl"] 8 | 9 | # Initialize Vivado project files 10 | source [file join $scriptdir "init.tcl"] 11 | 12 | # Synthesize the design 13 | source [file join $scriptdir "synth.tcl"] 14 | -------------------------------------------------------------------------------- /xilinx/common/tcl/synth.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Read the specified list of IP files 4 | read_ip [glob -directory $ipdir [file join * {*.xci}]] 5 | 6 | # Synthesize the design 7 | synth_design -top $top -flatten_hierarchy rebuilt 8 | 9 | # Checkpoint the current design 10 | write_checkpoint -force [file join $wrkdir post_synth] 11 | -------------------------------------------------------------------------------- /xilinx/common/tcl/util.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Helper function that recursively includes files given a directory and a 4 | # pattern/suffix extensions 5 | proc recglob { basedir pattern } { 6 | set dirlist [glob -nocomplain -directory $basedir -type d *] 7 | set findlist [glob -nocomplain -directory $basedir $pattern] 8 | foreach dir $dirlist { 9 | set reclist [recglob $dir $pattern] 10 | set findlist [concat $findlist $reclist] 11 | } 12 | return $findlist 13 | } 14 | 15 | # Helper function to find all subdirectories containing ".vh" files 16 | proc findincludedir { basedir pattern } { 17 | set vhfiles [recglob $basedir $pattern] 18 | set vhdirs {} 19 | foreach match $vhfiles { 20 | lappend vhdirs [file dir $match] 21 | } 22 | set uniquevhdirs [lsort -unique $vhdirs] 23 | return $uniquevhdirs 24 | } 25 | -------------------------------------------------------------------------------- /xilinx/common/tcl/vivado.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | # Set the variable for the directory that includes all scripts 4 | set scriptdir [file dirname [info script]] 5 | 6 | # Set up variables and Vivado objects 7 | source [file join $scriptdir "prologue.tcl"] 8 | 9 | # Initialize Vivado project files 10 | source [file join $scriptdir "init.tcl"] 11 | 12 | # Synthesize the design 13 | source [file join $scriptdir "synth.tcl"] 14 | 15 | # Pre-implementation debug 16 | if {[info exists pre_impl_debug_tcl]} { 17 | source [file join $scriptdir $pre_impl_debug_tcl] 18 | } 19 | 20 | # Post synthesis optimization 21 | source [file join $scriptdir "opt.tcl"] 22 | 23 | # Post-opt debug 24 | if {[info exists post_opt_debug_tcl]} { 25 | source [file join $scriptdir $post_opt_debug_tcl] 26 | } 27 | 28 | # Place the design 29 | source [file join $scriptdir "place.tcl"] 30 | 31 | # Route the design 32 | source [file join $scriptdir "route.tcl"] 33 | 34 | # Generate bitstream and save verilog netlist 35 | source [file join $scriptdir "bitstream.tcl"] 36 | 37 | # Post-implementation debug 38 | if {[info exists post_impl_debug_tcl]} { 39 | source [file join $scriptdir $post_impl_debug_tcl] 40 | } 41 | 42 | # Create reports for the current implementation 43 | source [file join $scriptdir "report.tcl"] 44 | -------------------------------------------------------------------------------- /xilinx/common/tcl/write_cfgmem.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | # 3 | # Create an MCS-format memory configuration file from a bitstream and an 4 | # optional data file. 5 | 6 | set script_program_dir [file dirname [info script]] 7 | source [file join $script_program_dir {boards.tcl}] 8 | 9 | if {$argc < 3 || $argc > 4} { 10 | puts $argc 11 | puts {Error: Invalid number of arguments} 12 | puts {Usage: write_cfgmem.tcl board mcsfile bitfile [datafile]} 13 | exit 1 14 | } 15 | lassign $argv board mcsfile bitfile datafile 16 | 17 | if {![dict exists $::program::boards::spec $board]} { 18 | puts {Unsupported board} 19 | exit 1 20 | } 21 | set board [dict get $::program::boards::spec $board] 22 | 23 | write_cfgmem -format mcs -interface [dict get $board iface] -size [dict get $board size] \ 24 | -loadbit "up [dict get $board bitaddr] $bitfile" \ 25 | -loaddata [expr {$datafile ne "" ? "up 0x400000 $datafile" : ""}] \ 26 | -file $mcsfile -force 27 | -------------------------------------------------------------------------------- /xilinx/nexys_video/constraints/nexys-video-config.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict [list \ 2 | CONFIG_VOLTAGE {3.3} \ 3 | CFGBVS {VCCO} \ 4 | BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \ 5 | ] [current_design] 6 | -------------------------------------------------------------------------------- /xilinx/nexys_video/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | set name {nexys_video} 3 | set part_fpga {xc7a200tsbg484-1} 4 | set part_board {digilentinc.com:nexys_video:part0:1.1} 5 | set bootrom_inst {rom} 6 | -------------------------------------------------------------------------------- /xilinx/nexys_video/tcl/ip.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force 4 | set_property -dict [list \ 5 | CONFIG.PRIMITIVE {MMCM} \ 6 | CONFIG.RESET_TYPE {ACTIVE_LOW} \ 7 | CONFIG.CLKOUT1_USED {true} \ 8 | CONFIG.CLKOUT2_USED {true} \ 9 | CONFIG.CLKOUT3_USED {true} \ 10 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \ 11 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \ 12 | CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {32.500} \ 13 | ] [get_ips mmcm] 14 | 15 | create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force 16 | set_property -dict [list \ 17 | CONFIG.C_EXT_RESET_HIGH {false} \ 18 | CONFIG.C_AUX_RESET_HIGH {false} \ 19 | CONFIG.C_NUM_BUS_RST {1} \ 20 | CONFIG.C_NUM_PERP_RST {1} \ 21 | CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \ 22 | CONFIG.C_NUM_PERP_ARESETN {1} \ 23 | ] [get_ips reset_sys] 24 | 25 | create_ip -vendor xilinx.com -library ip -name ila -module_name ila -dir $ipdir -force 26 | set_property -dict [list \ 27 | CONFIG.C_NUM_OF_PROBES {1} \ 28 | CONFIG.C_TRIGOUT_EN {false} \ 29 | CONFIG.C_TRIGIN_EN {false} \ 30 | CONFIG.C_MONITOR_TYPE {Native} \ 31 | CONFIG.C_ENABLE_ILA_AXI_MON {false} \ 32 | CONFIG.C_PROBE0_WIDTH {4} \ 33 | CONFIG.C_PROBE10_TYPE {1} \ 34 | CONFIG.C_PROBE10_WIDTH {32} \ 35 | CONFIG.C_PROBE11_TYPE {1} \ 36 | CONFIG.C_PROBE11_WIDTH {32} \ 37 | CONFIG.C_PROBE12_TYPE {1} \ 38 | CONFIG.C_PROBE12_WIDTH {64} \ 39 | CONFIG.C_PROBE13_TYPE {1} \ 40 | CONFIG.C_PROBE13_WIDTH {64} \ 41 | CONFIG.C_PROBE14_TYPE {1} \ 42 | CONFIG.C_PROBE14_WIDTH {97} \ 43 | ] [get_ips ila] 44 | -------------------------------------------------------------------------------- /xilinx/vc707/constraints/vc707-master.xdc: -------------------------------------------------------------------------------- 1 | #-------------- MCS Generation ---------------------- 2 | set_property CFGBVS GND [current_design] 3 | set_property CONFIG_VOLTAGE 1.8 [current_design] 4 | 5 | set_property EXTRACT_ENABLE YES [get_cells dut_/spi_0_1/mac/phy/txd_reg*] 6 | set_property EXTRACT_ENABLE YES [get_cells dut_/spi_0_1/mac/phy/sck_reg] 7 | -------------------------------------------------------------------------------- /xilinx/vc707/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | set name {vc707} 3 | set part_fpga {xc7vx485tffg1761-2} 4 | set part_board {xilinx.com:vc707:part0:1.4} 5 | -------------------------------------------------------------------------------- /xilinx/vc707/tcl/clocks.tcl: -------------------------------------------------------------------------------- 1 | if { [llength [get_ports -quiet chiplink_b2c_clk]] > 0 } { 2 | create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk] 3 | create_generated_clock -name {chiplink_c2b_clock} \ 4 | -divide_by 1 \ 5 | -source [ get_pins { vc707_sys_clock_mmcm0/inst/mmcm_adv_inst/CLKOUT6 } ] \ 6 | [ get_ports { chiplink_c2b_clk } ] 7 | 8 | # RX side: want to latch almost anywhere except on the rising edge of the clock 9 | # The data signals coming from Aloe have: clock - 1.2 <= transition <= clock + 0.8 10 | # Let's add 0.6ns of safety for trace jitter+skew on both sides: 11 | # min = hold = - 1.2 - 0.6 12 | # max = period - setup = 0.8 + 0.6 13 | set_input_delay -min -1.8 -clock {chiplink_b2c_clock} [ get_ports { chiplink_b2c_data* chiplink_b2c_rst chiplink_b2c_send } ] 14 | set_input_delay -max 1.4 -clock {chiplink_b2c_clock} [ get_ports { chiplink_b2c_data* chiplink_b2c_rst chiplink_b2c_send } ] 15 | 16 | # TX side: want to transition almost anywhere except on the rising edge of the clock 17 | # The data signals going to Aloe must have: clock - 1.85 <= NO transition <= clock + 0.65 18 | # Let's add 1ns of safey for trace jitter+skew on both sides: 19 | # min = -hold = -0.65 - 0.6 20 | # max = setup = 1.85 + 0.6 21 | set_output_delay -min -1.25 -clock {chiplink_c2b_clock} [ get_ports { chiplink_c2b_data* chiplink_c2b_rst chiplink_c2b_send } ] 22 | set_output_delay -max 2.45 -clock {chiplink_c2b_clock} [ get_ports { chiplink_c2b_data* chiplink_c2b_rst chiplink_c2b_send } ] 23 | } 24 | 25 | set group_mem [get_clocks -quiet {clk_pll_i}] 26 | set group_sys [get_clocks -quiet {sys_diff_clk \ 27 | clk_out*_vc707_sys_clock_mmcm1 \ 28 | clk_out*_vc707_sys_clock_mmcm2 \ 29 | chiplink_c2b_clock}] 30 | set group_cl [get_clocks -quiet {chiplink_b2c_clock \ 31 | clk_out*_vc707_sys_clock_mmcm3}] 32 | set group_pci [get_clocks -quiet {userclk1 txoutclk}] 33 | 34 | create_clock -add -name JTCK -period 100 -waveform {0 50} [get_ports {jtag_TCK}] 35 | if { [llength [get_ports -quiet {ulpi_clk}]] > 0 } { create_clock -add -name ULPI_CLK -period 16.667 [get_ports {ulpi_clk}] } 36 | 37 | set group_jtag [get_clocks -quiet {JTCK}] 38 | 39 | if { [llength [get_ports -quiet {ulpi_clk}]] > 0 } { set group_ulpi [get_clocks -quiet {ULPI_CLK}] } 40 | else {set group_ulpi {} } 41 | 42 | puts "group_mem: $group_mem" 43 | puts "group_sys: $group_sys" 44 | puts "group_pci: $group_pci" 45 | puts "group_cl: $group_cl" 46 | puts "group_jtag: $group_jtag" 47 | puts "group_ulpi: $group_ulpi" 48 | 49 | set groups [list] 50 | if { [llength $group_mem] > 0 } { lappend groups -group $group_mem } 51 | if { [llength $group_sys] > 0 } { lappend groups -group $group_sys } 52 | if { [llength $group_pci] > 0 } { lappend groups -group $group_pci } 53 | if { [llength $group_cl] > 0 } { lappend groups -group $group_cl } 54 | if { [llength $group_jtag] > 0 } { lappend groups -group $group_jtag } 55 | if { [llength $group_ulpi] > 0 } { lappend groups -group $group_ulpi } 56 | 57 | puts "set_clock_groups -asynchronous $groups" 58 | set_clock_groups -asynchronous {*}$groups 59 | 60 | set_false_path -from [get_clocks JTCK] -to [get_clocks -of_objects [get_pins lazysys/xilinxvc707mig_1/island/blackbox/u_vc707mig4gb_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1]] 61 | -------------------------------------------------------------------------------- /xilinx/vc707/vsrc/sdio.v: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | `timescale 1ns/1ps 3 | `default_nettype none 4 | 5 | module sdio_spi_bridge ( 6 | input wire clk, 7 | input wire reset, 8 | // SDIO 9 | inout wire sd_cmd, 10 | inout wire [3:0] sd_dat, 11 | output wire sd_sck, 12 | // QUAD SPI 13 | input wire spi_sck, 14 | input wire [3:0] spi_dq_o, 15 | output wire [3:0] spi_dq_i, 16 | output wire spi_cs 17 | ); 18 | 19 | wire mosi, miso; 20 | (* extract_reset = "yes" *) reg miso_sync [1:0]; 21 | assign mosi = spi_dq_o[0]; 22 | assign spi_dq_i = {2'b00, miso_sync[1], 1'b0}; 23 | 24 | assign sd_sck = spi_sck; 25 | 26 | IOBUF buf_cmd ( 27 | .IO(sd_cmd), 28 | .I(mosi), 29 | .O(), 30 | .T(1'b0) 31 | ); 32 | 33 | IOBUF buf_dat0 ( 34 | .IO(sd_dat[0]), 35 | .I(), 36 | .O(miso), 37 | .T(1'b1) 38 | ); 39 | 40 | IOBUF buf_dat3 ( 41 | .IO(sd_dat[3]), 42 | .I(spi_cs), 43 | .O(), 44 | .T(1'b0) 45 | ); 46 | 47 | always @(posedge clk) begin 48 | if (reset) begin 49 | miso_sync[0] <= 1'b0; 50 | miso_sync[1] <= 1'b0; 51 | end else begin 52 | miso_sync[0] <= miso; 53 | miso_sync[1] <= miso_sync[0]; 54 | end 55 | end 56 | endmodule 57 | 58 | `default_nettype wire 59 | -------------------------------------------------------------------------------- /xilinx/vc707/vsrc/vc707reset.v: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | `timescale 1ns/1ps 3 | `default_nettype none 4 | `define RESET_SYNC 4 5 | `define DEBOUNCE_BITS 8 6 | 7 | module vc707reset( 8 | // Asynchronous reset input, should be held high until 9 | // all clocks are locked and power is stable. 10 | input wire areset, 11 | // Clock domains are brought up in increasing order 12 | // All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1) 13 | input wire clock1, 14 | output wire reset1, 15 | input wire clock2, 16 | output wire reset2, 17 | input wire clock3, 18 | output wire reset3, 19 | input wire clock4, 20 | output wire reset4 21 | ); 22 | sifive_reset_hold hold_clock0(areset, clock1, reset1); 23 | sifive_reset_sync sync_clock2(reset1, clock2, reset2); 24 | sifive_reset_sync sync_clock3(reset2, clock3, reset3); 25 | sifive_reset_sync sync_clock4(reset3, clock4, reset4); 26 | endmodule 27 | 28 | // Assumes that areset is held for more than one clock 29 | // Allows areset to be deasserted asynchronously 30 | module sifive_reset_sync( 31 | input wire areset, 32 | input wire clock, 33 | output wire reset 34 | ); 35 | reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}}; 36 | always @(posedge clock, posedge areset) begin 37 | if (areset) begin 38 | gen_reset <= {`RESET_SYNC{1'b1}}; 39 | end else begin 40 | gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]}; 41 | end 42 | end 43 | assign reset = gen_reset[0]; 44 | endmodule 45 | 46 | module sifive_reset_hold( 47 | input wire areset, 48 | input wire clock, 49 | output wire reset 50 | ); 51 | wire raw_reset; 52 | reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}}; 53 | reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}}; 54 | wire out_reset; 55 | 56 | // Captures reset even if clock is not running 57 | sifive_reset_sync capture(areset, clock, raw_reset); 58 | 59 | // Remove any glitches due to runt areset 60 | always @(posedge clock) begin 61 | sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]}; 62 | end 63 | 64 | // Debounce the reset 65 | assign out_reset = debounce_reset[`DEBOUNCE_BITS]; 66 | always @(posedge clock) begin 67 | if (sync_reset[0]) begin 68 | debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}}; 69 | end else begin 70 | debounce_reset <= debounce_reset - out_reset; 71 | end 72 | end 73 | 74 | assign reset = out_reset; 75 | 76 | endmodule 77 | 78 | `default_nettype wire 79 | -------------------------------------------------------------------------------- /xilinx/vcu118/constraints/vcu118-master.xdc: -------------------------------------------------------------------------------- 1 | #-------------- MCS Generation ---------------------- 2 | set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] 3 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 4 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] 5 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 6 | set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] 7 | set_property CFGBVS GND [current_design] 8 | set_property CONFIG_VOLTAGE 1.8 [current_design] 9 | set_property CONFIG_MODE SPIx8 [current_design] 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /xilinx/vcu118/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | set name {vcu118} 3 | set part_fpga {xcvu9p-flga2104-2L-e} 4 | # Board: xilinx.com:vcu118:part0:2.0 5 | # However, if we set this we cannot control PCIe locations 6 | set part_board {} 7 | -------------------------------------------------------------------------------- /xilinx/vcu118/vsrc/sdio.v: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | `timescale 1ns/1ps 3 | `default_nettype none 4 | 5 | module sdio_spi_bridge ( 6 | input wire clk, 7 | input wire reset, 8 | // SDIO 9 | inout wire sd_cmd, 10 | inout wire [3:0] sd_dat, 11 | output wire sd_sck, 12 | // QUAD SPI 13 | input wire spi_sck, 14 | input wire [3:0] spi_dq_o, 15 | output wire [3:0] spi_dq_i, 16 | output wire spi_cs 17 | ); 18 | 19 | wire mosi, miso; 20 | reg miso_sync [1:0]; 21 | 22 | assign mosi = spi_dq_o[0]; 23 | assign spi_dq_i = {2'b00, miso_sync[1], 1'b0}; 24 | 25 | assign sd_sck = spi_sck; 26 | 27 | IOBUF buf_cmd ( 28 | .IO(sd_cmd), 29 | .I(mosi), 30 | .O(), 31 | .T(1'b0) 32 | ); 33 | 34 | IOBUF buf_dat0 ( 35 | .IO(sd_dat[0]), 36 | .I(), 37 | .O(miso), 38 | .T(1'b1) 39 | ); 40 | 41 | IOBUF buf_dat3 ( 42 | .IO(sd_dat[3]), 43 | .I(spi_cs), 44 | .O(), 45 | .T(1'b0) 46 | ); 47 | 48 | always @(posedge clk) begin 49 | if (reset) begin 50 | miso_sync[0] <= 1'b0; 51 | miso_sync[1] <= 1'b0; 52 | end else begin 53 | miso_sync[0] <= miso; 54 | miso_sync[1] <= miso_sync[0]; 55 | end 56 | end 57 | endmodule 58 | 59 | `default_nettype wire 60 | -------------------------------------------------------------------------------- /xilinx/vcu118/vsrc/vcu118reset.v: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | `timescale 1ns/1ps 3 | `default_nettype none 4 | `define RESET_SYNC 4 5 | `define DEBOUNCE_BITS 8 6 | 7 | module vcu118reset( 8 | // Asynchronous reset input, should be held high until 9 | // all clocks are locked and power is stable. 10 | input wire areset, 11 | // Clock domains are brought up in increasing order 12 | // All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1) 13 | input wire clock1, 14 | output wire reset1, 15 | input wire clock2, 16 | output wire reset2, 17 | input wire clock3, 18 | output wire reset3, 19 | input wire clock4, 20 | output wire reset4 21 | ); 22 | sifive_reset_hold hold_clock0(areset, clock1, reset1); 23 | sifive_reset_sync sync_clock2(reset1, clock2, reset2); 24 | sifive_reset_sync sync_clock3(reset2, clock3, reset3); 25 | sifive_reset_sync sync_clock4(reset3, clock4, reset4); 26 | endmodule 27 | 28 | // Assumes that areset is held for more than one clock 29 | // Allows areset to be deasserted asynchronously 30 | module sifive_reset_sync( 31 | input wire areset, 32 | input wire clock, 33 | output wire reset 34 | ); 35 | reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}}; 36 | always @(posedge clock, posedge areset) begin 37 | if (areset) begin 38 | gen_reset <= {`RESET_SYNC{1'b1}}; 39 | end else begin 40 | gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]}; 41 | end 42 | end 43 | assign reset = gen_reset[0]; 44 | endmodule 45 | 46 | module sifive_reset_hold( 47 | input wire areset, 48 | input wire clock, 49 | output wire reset 50 | ); 51 | wire raw_reset; 52 | reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}}; 53 | reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}}; 54 | wire out_reset; 55 | 56 | // Captures reset even if clock is not running 57 | sifive_reset_sync capture(areset, clock, raw_reset); 58 | 59 | // Remove any glitches due to runt areset 60 | always @(posedge clock) begin 61 | sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]}; 62 | end 63 | 64 | // Debounce the reset 65 | assign out_reset = debounce_reset[`DEBOUNCE_BITS]; 66 | always @(posedge clock) begin 67 | if (sync_reset[0]) begin 68 | debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}}; 69 | end else begin 70 | debounce_reset <= debounce_reset - out_reset; 71 | end 72 | end 73 | 74 | assign reset = out_reset; 75 | 76 | endmodule 77 | 78 | `default_nettype wire 79 | -------------------------------------------------------------------------------- /xilinx/zcu102/tcl/board.tcl: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | set name {zcu102} 3 | #set part_fpga {xczu9eg-ffvb1156-2-e} 4 | #set part_board {xilinx.com:zcu102:part0:3.2} 5 | set part_fpga {xczu9eg-ffvb1156-2-e} 6 | set part_board {xilinx.com:zcu102:part0:3.4} 7 | -------------------------------------------------------------------------------- /xilinx/zcu102/vsrc/sdio.v: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | `timescale 1ns/1ps 3 | `default_nettype none 4 | 5 | module sdio_spi_bridge ( 6 | input wire clk, 7 | input wire reset, 8 | // SDIO 9 | inout wire sd_cmd, 10 | inout wire [3:0] sd_dat, 11 | output wire sd_sck, 12 | // QUAD SPI 13 | input wire spi_sck, 14 | input wire [3:0] spi_dq_o, 15 | output wire [3:0] spi_dq_i, 16 | output wire spi_cs 17 | ); 18 | 19 | wire mosi, miso; 20 | reg miso_sync [1:0]; 21 | 22 | assign mosi = spi_dq_o[0]; 23 | assign spi_dq_i = {2'b00, miso_sync[1], 1'b0}; 24 | 25 | assign sd_sck = spi_sck; 26 | 27 | IOBUF buf_cmd ( 28 | .IO(sd_cmd), 29 | .I(mosi), 30 | .O(), 31 | .T(1'b0) 32 | ); 33 | 34 | IOBUF buf_dat0 ( 35 | .IO(sd_dat[0]), 36 | .I(), 37 | .O(miso), 38 | .T(1'b1) 39 | ); 40 | 41 | IOBUF buf_dat3 ( 42 | .IO(sd_dat[3]), 43 | .I(spi_cs), 44 | .O(), 45 | .T(1'b0) 46 | ); 47 | 48 | always @(posedge clk) begin 49 | if (reset) begin 50 | miso_sync[0] <= 1'b0; 51 | miso_sync[1] <= 1'b0; 52 | end else begin 53 | miso_sync[0] <= miso; 54 | miso_sync[1] <= miso_sync[0]; 55 | end 56 | end 57 | endmodule 58 | 59 | `default_nettype wire 60 | -------------------------------------------------------------------------------- /xilinx/zcu102/vsrc/zcu102reset.v: -------------------------------------------------------------------------------- 1 | 2 | // See LICENSE for license details. 3 | `timescale 1ns/1ps 4 | `default_nettype none 5 | `define RESET_SYNC 4 6 | `define DEBOUNCE_BITS 8 7 | 8 | module zcu102reset( 9 | // Asynchronous reset input, should be held high until 10 | // all clocks are locked and power is stable. 11 | input wire areset, 12 | // Clock domains are brought up in increasing order 13 | // All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1) 14 | input wire clock1, 15 | output wire reset1, 16 | input wire clock2, 17 | output wire reset2, 18 | input wire clock3, 19 | output wire reset3, 20 | input wire clock4, 21 | output wire reset4 22 | ); 23 | sifive_reset_hold hold_clock0(areset, clock1, reset1); 24 | sifive_reset_sync sync_clock2(reset1, clock2, reset2); 25 | sifive_reset_sync sync_clock3(reset2, clock3, reset3); 26 | sifive_reset_sync sync_clock4(reset3, clock4, reset4); 27 | endmodule 28 | 29 | // Assumes that areset is held for more than one clock 30 | // Allows areset to be deasserted asynchronously 31 | module sifive_reset_sync( 32 | input wire areset, 33 | input wire clock, 34 | output wire reset 35 | ); 36 | reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}}; 37 | always @(posedge clock, posedge areset) begin 38 | if (areset) begin 39 | gen_reset <= {`RESET_SYNC{1'b1}}; 40 | end else begin 41 | gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]}; 42 | end 43 | end 44 | assign reset = gen_reset[0]; 45 | endmodule 46 | 47 | module sifive_reset_hold( 48 | input wire areset, 49 | input wire clock, 50 | output wire reset 51 | ); 52 | wire raw_reset; 53 | reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}}; 54 | reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}}; 55 | wire out_reset; 56 | 57 | // Captures reset even if clock is not running 58 | sifive_reset_sync capture(areset, clock, raw_reset); 59 | 60 | // Remove any glitches due to runt areset 61 | always @(posedge clock) begin 62 | sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]}; 63 | end 64 | 65 | // Debounce the reset 66 | assign out_reset = debounce_reset[`DEBOUNCE_BITS]; 67 | always @(posedge clock) begin 68 | if (sync_reset[0]) begin 69 | debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}}; 70 | end else begin 71 | debounce_reset <= debounce_reset - out_reset; 72 | end 73 | end 74 | 75 | assign reset = out_reset; 76 | 77 | endmodule 78 | 79 | `default_nettype wire 80 | --------------------------------------------------------------------------------