├── .gitmodules ├── README.md ├── dependencies.sh ├── install_ghdl.sh ├── install_yosys.sh ├── src └── accualu.vhd ├── synth_alu.sh └── test_synth.sh /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/.gitmodules -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/README.md -------------------------------------------------------------------------------- /dependencies.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/dependencies.sh -------------------------------------------------------------------------------- /install_ghdl.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/install_ghdl.sh -------------------------------------------------------------------------------- /install_yosys.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/install_yosys.sh -------------------------------------------------------------------------------- /src/accualu.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/src/accualu.vhd -------------------------------------------------------------------------------- /synth_alu.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/synth_alu.sh -------------------------------------------------------------------------------- /test_synth.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chiselverify/vhdl2verilog/HEAD/test_synth.sh --------------------------------------------------------------------------------