├── .gitmodules ├── README.md ├── dependencies.sh ├── install_ghdl.sh ├── install_yosys.sh ├── src └── accualu.vhd ├── synth_alu.sh └── test_synth.sh /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "yosys"] 2 | path = yosys 3 | url = https://github.com/YosysHQ/yosys.git 4 | [submodule "ghdl"] 5 | path = ghdl 6 | url = https://github.com/ghdl/ghdl.git 7 | [submodule "ghdl-yosys-plugin"] 8 | path = ghdl-yosys-plugin 9 | url = https://github.com/ghdl/ghdl-yosys-plugin.git 10 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # About 2 | This repository works as a toolset and guide for a free open-source way of converting VHDL to Verilog code using [yosys](https://github.com/YosysHQ/yosys) and [GHDL](https://github.com/ghdl/ghdl). 3 | 4 | 5 | # Installation instructions 6 | 7 | ## Dependencies 8 | The needed dependencies for a Ubuntu 20.04 Server is given in *dependencies.sh*. This can be done in a terminal `./dependencies.sh` 9 | 10 | ## Installing yosys and GHDL 11 | yosys and ghdl are added as submodules. Be sure to run `git submodule update --init` from within this folder. 12 | 13 | $ export MAKEFLAGS=-jn 14 | where n is the number of cores you want to use. This allows for using parallel compilation. 15 | 16 | $ ./install_yosys.sh 17 | $ ./install_ghdl.sh 18 | 19 | # Test 20 | Run `./test.synth.sh` to test a synthesis of a test example. This should generate a file called *synth.v* in the current folder. 21 | -------------------------------------------------------------------------------- /dependencies.sh: -------------------------------------------------------------------------------- 1 | sudo apt-get install build-essential clang bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev gnat 2 | -------------------------------------------------------------------------------- /install_ghdl.sh: -------------------------------------------------------------------------------- 1 | cd ghdl 2 | ./configure --prefix=/usr/local 3 | make 4 | sudo make install 5 | cd .. 6 | cd ghdl-yosys-plugin 7 | make 8 | sudo make install 9 | -------------------------------------------------------------------------------- /install_yosys.sh: -------------------------------------------------------------------------------- 1 | cd yosys 2 | make 3 | sudo make install 4 | -------------------------------------------------------------------------------- /src/accualu.vhd: -------------------------------------------------------------------------------- 1 | -- Code your design here 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | entity accualu is 7 | port ( 8 | clock: in std_logic; 9 | reset: in std_logic; 10 | op: in std_logic_vector(2 downto 0); 11 | din: in std_logic_vector(15 downto 0); 12 | enable: in std_logic; 13 | accu: out std_logic_vector(15 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture beh of accualu is 18 | 19 | signal accuReg: signed(15 downto 0); 20 | signal res: signed(15 downto 0); 21 | signal a, b: signed(15 downto 0); 22 | 23 | begin 24 | 25 | a <= signed(accuReg); 26 | b <= signed(din); 27 | 28 | --ALU Logic 29 | process(all) begin 30 | case (op) is 31 | when 3d"1" => res <= a + b; 32 | when 3d"2" => res <= a - b; 33 | when 3d"3" => res <= a and b; 34 | when 3d"4" => res <= a or b; 35 | when 3d"5" => res <= a XOR b; 36 | when 3d"6" => res <= b; 37 | when 3d"7" => res <= '0' & a(15 downto 1); 38 | when 3d"0" => res <= a; 39 | when others => res <= a; 40 | end case; 41 | end process; 42 | 43 | --Output register 44 | process(all) begin 45 | if rising_edge(clock) then 46 | if (reset='1') then 47 | accuReg <= (others => '0'); 48 | elsif (enable='1') then 49 | accuReg <= res; 50 | end if; 51 | end if; 52 | end process; 53 | 54 | accu <= std_logic_vector(accuReg); 55 | 56 | end beh; 57 | -------------------------------------------------------------------------------- /synth_alu.sh: -------------------------------------------------------------------------------- 1 | yosys -m ghdl -p 'ghdl --std=08 src/accualu.vhd -e accualu; write_verilog accualu_synth.v' 2 | -------------------------------------------------------------------------------- /test_synth.sh: -------------------------------------------------------------------------------- 1 | yosys -m ghdl -p 'ghdl ghdl-yosys-plugin/examples/icestick/leds/leds.vhdl ghdl-yosys-plugin/examples/icestick/leds/spin1.vhdl -e leds; synth -top leds; write_verilog synth.v' 2 | --------------------------------------------------------------------------------