├── .Benchmark └── _dummy.txt ├── .Validation └── _dummy.txt ├── LICENSE ├── Memory.Manager └── _dummy.txt ├── Parallel.RTL └── _dummy.txt ├── README.md ├── RTL └── _dummy.txt └── Runtime ├── UC64.CPUID.pas └── _dummy.txt /.Benchmark/_dummy.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chmichael/UltraCode/e98bda0832c2e76316361c0d374fd756a45ce621/.Benchmark/_dummy.txt -------------------------------------------------------------------------------- /.Validation/_dummy.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chmichael/UltraCode/e98bda0832c2e76316361c0d374fd756a45ce621/.Validation/_dummy.txt -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /Memory.Manager/_dummy.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chmichael/UltraCode/e98bda0832c2e76316361c0d374fd756a45ce621/Memory.Manager/_dummy.txt -------------------------------------------------------------------------------- /Parallel.RTL/_dummy.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chmichael/UltraCode/e98bda0832c2e76316361c0d374fd756a45ce621/Parallel.RTL/_dummy.txt -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # UltraCode 2 | Assembler & Parallel optimized RTL Replacement for Delphi/Free Pascal for Windows/Mac/Linux/iOS/Android 3 | 4 | CPU Tagets: 5 | PASCAL, SSE3, AVX, ARM 6 | 7 | Operating Systems: 8 | Windows, MacOS, Linux, IOS, Android 9 | 10 | GPU Targets: 11 | OpenCL, Vulkan 12 | 13 | Please use the following Structure for filenames for Single Thread Targets: 14 | UltraCode."Routine"."SIMD"."OS".pas = UltraCode.Pos.AVX.Win.pas, UltraCode.Pos.AVX.Mac.pas, UltraCode.Pos.AVX.Linux.pas 15 | 16 | Please use the following Structure for filenames for Parallel Thread Targets: 17 | UltraCodeP."Routine".Parallel."SIMD"."OS".pas = UltraCodeP.Pos.AVX.Win.pas, UltraCodeP.Pos.Parallel.AVX.Mac.pas, UltraCodeP.Pos.AVX.Linux.pas 18 | 19 | Please use the following Structure for filenames for GPU Targets: 20 | UltraCodeG."Routine".Parallel."SIMD"."OS".pas = UltraCodeG.Pos.AVX.Win.pas, UltraCodeG.Pos.Parallel.AVX.Mac.pas, UltraCodeG.Pos.AVX.Linux.pas 21 | -------------------------------------------------------------------------------- /RTL/_dummy.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chmichael/UltraCode/e98bda0832c2e76316361c0d374fd756a45ce621/RTL/_dummy.txt -------------------------------------------------------------------------------- /Runtime/UC64.CPUID.pas: -------------------------------------------------------------------------------- 1 | unit UC64.CPUID; 2 | 3 | {***** BEGIN LICENSE BLOCK ***** 4 | Version: MPL 1.1 5 | 6 | The contents of this file are subject to the Mozilla Public License Version 1.1 7 | (the "License"); you may not use this file except in compliance with the 8 | License. You may obtain a copy of the License at http://www.mozilla.org/MPL/ 9 | 10 | Software distributed under the License is distributed on an "AS IS" basis, 11 | WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for 12 | the specific language governing rights and limitations under the License. 13 | 14 | The Original Code is the FastCode CPUID code. 15 | 16 | The Initial Developer of the Original Code is 17 | Roelof Engelbrecht . Portions created by 18 | the Initial Developer are Copyright (C) 2004 by the Initial Developer. 19 | All Rights Reserved. 20 | 21 | Contributor(s): Dennis Passmore , 22 | Dennis Christensen , 23 | Jouni Turunen . 24 | Johan Bontes 25 | 26 | ***** END LICENSE BLOCK ***** 27 | 28 | Version Changes 29 | ------- ------ 30 | 3.0.3 23 Mar 2016 : Added x64 code and new CPUID features 31 | 3.0.2 27 Apr 2006 : AMD X2 text changed from 'AMD_64_SSE3' to 'AMD_64X2' 32 | 3.0.1 18 Apr 2006 : Bug in Yohan fctPMY target fixed, was incorrectly set to fctPMD 33 | 3.0.0 27 Feb 2006 : Added new 2006 computed targets. Added Yonah and Presler 34 | Removed Prescott, Banias, AMD XP (JT) 35 | 36 | } 37 | 38 | interface 39 | 40 | type 41 | TVendor = (cvUnknown, cvAMD, cvCentaur, cvCyrix, cvIntel, 42 | cvTransmeta, cvNexGen, cvRise, cvUMC, cvNSC, cvSiS, cvAMDEarly, 43 | cvTransMeta2, cvVIA, cvVortex, cvVM_KVM, cvVM_Microsoft, 44 | cvVM_Parallels, cvVM_VMWare, cvVM_XEN); 45 | {Note: when changing TVendor, also change VendorStr array below} 46 | 47 | TInstructions = 48 | (isFPU, {80x87} 49 | isTSC, {RDTSC} 50 | isCX8, {CMPXCHG8B} 51 | isSEP, {SYSENTER/SYSEXIT} 52 | isCMOV, {CMOVcc, and if isFPU, FCMOVcc/FCOMI} 53 | isMMX, {MMX} 54 | isFXSR, {FXSAVE/FXRSTOR} 55 | isSSE, {SSE} 56 | isSSE2, {SSE2} 57 | isSSE3, {SSE3*} 58 | isMONITOR, {MONITOR/MWAIT*} 59 | isCX16, {CMPXCHG16B*} 60 | isX64, {AMD AMD64* or Intel EM64T*} 61 | isExMMX, {MMX+ - AMD only} 62 | isEx3DNow, {3DNow!+ - AMD only} 63 | is3DNow, {3DNow! - AMD only} 64 | isSSSE3, {Supplemental SSE3} 65 | isSSE41, {SSE 4.1} 66 | isSSE42, {SSE 4.2} 67 | isAES, {AES support} 68 | isAVX, {AVX} 69 | isPopCnt, {Popcnt, lzcnt, tzcnt} 70 | isXSAVE, {XSAVE} 71 | isRDTSCP, {Read synchronized RDTSCP} 72 | isTBM, {Trailing bit manipulations} 73 | isFMA4, {4 operand FMA instructions support} 74 | isXOP, {XOP support} 75 | isSSE4A, {SSE 4a support, note that popcount has its own flag} 76 | isABM, {Advanced bit manipulation} 77 | isLAHF, {Lahf, Sahf support in 64-bit} 78 | isPCLMULQDQ,{PCLMULQDQ support} 79 | isFMA, {Fused multiply and add} 80 | isMOVBE, {move Big Endian} 81 | isF16C, {half precision FP support} 82 | isRDRAND, {Onchip random generator} 83 | isBMI1, {Bit manipulation instruction set 1} 84 | isAVX2, {Advanced vector instructions 2} 85 | isBMI2, {Bit manipulation instruction set 2} 86 | isERMS, {Enhanced REP MOVSB/STOSB} 87 | isINVPCID, {INVPCID instructions} 88 | isRTM, {Transactional Synchronization Extensions} 89 | isMPX, {Memory Protection Extensions} 90 | isAVX512f, {AVX-512 Foundation} 91 | isAVX512dq, {AVX-512 Doubleword and Quadword Instructions} 92 | isRDSEED, {RDSEED instruction} 93 | isADX, {Multi-Precision Add-Carry Instruction Extensions} 94 | isPCOMMIT, {PCOMMIT instruction} 95 | isCLFLUSHOPT,{CLFLUSHOPT instruction} 96 | isCLWB, {CLWB instruction} 97 | isAVX512pf, {AVX-512 Prefetch Instructions} 98 | isAVX512er, {AVX-512 Exponential and Reciprocal Instructions} 99 | isAVX512cd, {AVX-512 Conflict Detection Instructions} 100 | isSHA, {SHA extensions} 101 | isAVX512bw, {AVX-512 Byte and Word Instructions} 102 | isAVX512vl, {AVX-512 Vector Length Extensions} 103 | isPREFETCHWT1,{PREFETCHWT1 instruction} 104 | isAVX512vbmi {AVX-512 Vector Bit Manipulation Instructions} 105 | ); 106 | 107 | {Note: when changing TInstruction, also change InstructionSupportStr below 108 | * - instruction(s) not supported in Delphi 7 assembler} 109 | TInstructionSupport = set of TInstructions; 110 | 111 | TCPU = record 112 | Vendor: TVendor; 113 | Signature: Cardinal; 114 | EffFamily: Byte; {ExtendedFamily + Family} 115 | EffModel: Byte; {(ExtendedModel shl 4) + Model} 116 | EffModelBasic: Byte; {Just Model (not ExtendedModel shl 4) + Model)} 117 | CodeL1CacheSize, {KB or micro-ops for Pentium 4} 118 | DataL1CacheSize, {KB} 119 | L2CacheSize, {KB} 120 | L3CacheSize: Word; {KB} 121 | InstructionSupport: TInstructionSupport; 122 | end; 123 | 124 | TUltraCode64Target = 125 | (fctRTLReplacement, {not specific to any CPU} 126 | fctBlendedIA32, {not specific to any CPU, requires FPU and CMOV} 127 | fctBlendedMMX, {not specific to any CPU, requires FPU, MMX and CMOV "Old fctBlended target"} 128 | fctBlendedSSE, {not specific to any CPU, requires FPU, MMX, CMOV and SSE} 129 | fctBlendedSSE2, {not specific to any CPU, requires FPU, MMX, CMOV, SSE, SSE2} 130 | fctPMD, {Dothan} 131 | fctPMY, {Yonah} 132 | fctP4N, {Northwood} 133 | fctP4R, {Presler} 134 | fctAmd64, {AMD 64} 135 | fctAmd64_SSE3); {X2/Opteron/Athlon FX/Athlon 64 with SSE3} 136 | {Note: when changing TUltraCode64Target, also change UltraCode64TargetStr array 137 | below} 138 | 139 | const 140 | VendorStr: array[Low(TVendor)..High(TVendor)] of ShortString = 141 | ('Unknown', 'AMD', 'Centaur (VIA)', 'Cyrix', 'Intel', 'Transmeta', 142 | 'NexGen', 'Rise', 'UMC', 'National Semiconductor', 'SiS','AMD K5 engineering sample', 143 | 'TransMeta', 'VIA','Vortex', 'KVM_VM', 'Microsoft_VM', 144 | 'Parallels_VM', 'VMWare_VM', 'XEN_VM'); 145 | 146 | InstructionSupportStr: 147 | array[Low(TInstructions)..High(TInstructions)] of ShortString = 148 | ('FPU', 'TSC', 'CX8', 'SEP', 'CMOV', 'MMX', 'FXSR', 'SSE', 'SSE2', 'SSE3', 149 | 'MONITOR', 'CX16', 'X64', 'MMX+', '3DNow!+', '3DNow!','SSSE3','SSE4.1', 150 | 'SSE4.2','AES','AVX','PopCnt','XSAVE','RDTSCP','TBM','FMA4','XOP','SSE4A', 151 | 'ABM','LAHF','PCLMULQDQ','FMA','MOVBE','F16C','RDRAND','BMI1','AVX2','BMI2', 152 | 'ERMS','INVPCID','RTM','MPX', 'AVX512f','AVX512dq','RDSEED','ADX','PCOMMIT', 153 | 'CLFLUSHOPT','CLWB','AVX512pf','AVX512er','AVX512cd','SHA','AVX512bw','AVX512vl', 154 | 'PREFETCHWT1','AVX512vbmi' 155 | ); 156 | 157 | UltraCode64TargetStr: 158 | array[Low(TUltraCode64Target)..High(TUltraCode64Target)] of ShortString = 159 | ('RTLReplacement', 'Blended_IA32', 'Blended_MMX', 'Blended_SSE', 160 | 'Blended_SSE2', 'Dothan', 'Yonah', 'Northwood', 'Presler', 'AMD_64', 'AMD_64X2'); 161 | 162 | var 163 | CPU: TCPU; 164 | UltraCode64Target: TUltraCode64Target; 165 | 166 | implementation 167 | 168 | type 169 | TRegisters = record 170 | EAX, 171 | EBX, 172 | ECX, 173 | EDX: Cardinal; 174 | end; 175 | 176 | TVendorStr = string[12]; 177 | 178 | TCpuFeatures = 179 | ({in EDX} 180 | cfFPU, cfVME, cfDE, cfPSE, cfTSC, cfMSR, cfPAE, cfMCE, 181 | cfCX8, cfAPIC, cf_d10, cfSEP, cfMTRR, cfPGE, cfMCA, cfCMOV, 182 | cfPAT, cfPSE36, cfPSN, cfCLFSH, cf_d20, cfDS, cfACPI, cfMMX, 183 | cfFXSR, cfSSE, cfSSE2, cfSS, cfHyperThreading, cfTM, cfIA_64, cfPBE, 184 | {in ECX} 185 | cfSSE3, cfPCLMULQDQ, cf_c2, cfMON, cfDS_CPL, cf_c5, cf_c6, cfEIST, 186 | cfTM2, cfSSSE3, cfCID, cf_c11, cfFMA, cfCX16, cfxTPR, cf_c15, 187 | cf_c16, cf_c17, cf_c18, cfSSE41, cfSSE42, cf_c21, cfMovBE, cfPOPCNT, 188 | cf_c24, cfAES, cfXSAVE, cfOSXSAVE, cfAVX, cfF16C, cfRDRAND, cfRAZ); 189 | TCpuFeatureSet = set of TCpuFeatures; 190 | 191 | TCpuExtendedFeatures = 192 | ({in EDX} 193 | cefFPU, cefVME, cefDE, cefPSE, cefTSC, cefMSR, cefPAE, cefMCE, 194 | cefCX8, cefAPIC, cef_10, cefSEP, cefMTRR, cefPGE, cefMCA, cefCMOV, 195 | cefPAT, cefPSE36, cef_18, ceMPC, ceNX, cef_21, cefExMMX, cefMMX, 196 | cefFXSR, cefFFXSR, cefPage1GB, cefRDTSCP, cef_28, cefLM, cefEx3DNow, cef3DNow, 197 | {in ECX} 198 | cefLahfSahf, cefCmpLegacy, cefSVM, cefExtApicSpace, cefAltMovCR8, cefABM, cefSSE4A, cefMisAlignSSE, 199 | cef3DNOWPrefetch, cefOSVW, cefIBS, cefXOP, cefSKINIT, cefWDT, cef_c14, cefLWP, 200 | cefFMA4, cefTCE, cef_c18, cefNodeId, cef_c20, cefTBM, cefTopologyExtensions, cefPERFCTR_core, 201 | cefPERFCTR_nb, cef_c25, cefDBX, cefPERFTSC, cefPCX_l2i, cef_c29, cef_c30, cef_c31); 202 | TCpuExtendedFeatureSet = set of TCpuExtendedFeatures; 203 | 204 | TCPUExtendedFeatures7 = {EAX = 7, ECX = 0} 205 | ({in EBX} 206 | ce7FSGSbase, ce7TSC_Adjust, ce7SGX, ce7BMI1, ce7HLE, ce7AVX2, ce7_06, ce7SMEP, 207 | ce7BMI2, ce7ERMS, ce7INVPCID, ce7RTM, ce7PQM, ce7NoFPUcsds, ce7MPX, ce7PQE, 208 | ce7AVX512f, ce7AVX512dq, ce7RDSEED, ce7ADX, ce7SMAP, ce7AVX512ifma, ce7PCOMMIT, ce7CLFLUSHOPT, 209 | ce7CLWB, ce7ProcessorTrace, ce7AVX512pf, ce7AVX512er, ce7AVX512cd, ce7SHA, ce7AVX512bw, ce7AVX512vl, 210 | {in ECX} 211 | ce7cPREFETCHWT1, ce7cAVX512vbmi, ce7c_02, ce7c_03, ce7c_04, ce7c_05, ce7c_06, ce7c_07, 212 | ce7c_08, ce7c_09, ce7c_10, ce7c_11, ce7c_12, ce7c_13, ce7c_14, ce7c_15, 213 | ce7c_16, ce7c_17, ce7c_18, ce7c_19, ce7c_20, ce7c_21, ce7c_22, ce7c_23, 214 | ce7c_24, ce7c_25, ce7c_26, ce7c_27, ce7c_28, ce7c_29, ce7c_30, ce7c_31); 215 | TCpuExtendedFeature7Set = set of TCpuExtendedFeatures7; 216 | 217 | 218 | const 219 | VendorIDString: array[Low(TVendor)..High(TVendor)] of TVendorStr = 220 | ('', 221 | 'AuthenticAMD', 'CentaurHauls', 'CyrixInstead', 'GenuineIntel', 222 | 'GenuineTMx86', 'NexGenDriven', 'RiseRiseRise', 'UMC UMC UMC ', 223 | 'Geode by NSC', 'SiS SiS SiS ', 'AMDisbetter!', 'TransmetaCPU', 224 | 'VIA VIA VIA ', 'Vortex86 SoC', 'KVMKVMKVM ', 'Microsoft Hv', 225 | ' lrpepyh vr', 'VMwareVMware', 'XenVMMXenVMM'); 226 | 227 | {CPU signatures} 228 | 229 | IntelLowestSEPSupportSignature = $633; 230 | K7DuronA0Signature = $630; 231 | C3Samuel2EffModel = 7; 232 | C3EzraEffModel = 8; 233 | PMBaniasEffModel = 9; 234 | PMDothanEffModel = $D; 235 | PMYonahEffModel = $E; 236 | PMMeromEffModel = $F; 237 | PMPenrynEFFModel = $17; 238 | P3LowestEffModel = 7; 239 | 240 | function IsCPUID_Available: Boolean; register; 241 | asm 242 | {$IFDEF CPUx86} 243 | PUSHFD {save EFLAGS to stack} 244 | POP EAX {store EFLAGS in EAX} 245 | MOV EDX, EAX {save in EDX for later testing} 246 | XOR EAX, $200000; {flip ID bit in EFLAGS} 247 | PUSH EAX {save new EFLAGS value on stack} 248 | POPFD {replace current EFLAGS value} 249 | PUSHFD {get new EFLAGS} 250 | POP EAX {store new EFLAGS in EAX} 251 | XOR EAX, EDX {check if ID bit changed} 252 | JZ @exit {no, CPUID not available} 253 | MOV EAX, True {yes, CPUID is available} 254 | @exit: 255 | {$ELSE} 256 | MOV EAX, True {x64 always has CPUID} 257 | {$ENDIF} 258 | end; 259 | 260 | function IsFPU_Available: Boolean; 261 | {$IFDEF CPUX86} 262 | var 263 | _FCW, _FSW: Word; 264 | asm 265 | MOV EAX, False {initialize return register} 266 | MOV _FSW, $5A5A {store a non-zero value} 267 | FNINIT {must use non-wait form} 268 | FNSTSW _FSW {store the status} 269 | CMP _FSW, 0 {was the correct status read?} 270 | JNE @exit {no, FPU not available} 271 | FNSTCW _FCW {yes, now save control word} 272 | MOV DX, _FCW {get the control word} 273 | AND DX, $103F {mask the proper status bits} 274 | CMP DX, $3F {is a numeric processor installed?} 275 | JNE @exit {no, FPU not installed} 276 | MOV EAX, True {yes, FPU is installed} 277 | @exit: 278 | {$ELSE} 279 | asm 280 | MOV EAX, True {Every X64 has an FPU} 281 | {$ENDIF} 282 | end; 283 | 284 | procedure GetCPUID(Param: Cardinal; var Registers: TRegisters); 285 | asm 286 | {$ifdef cpux86} 287 | PUSH EBX {save affected registers} 288 | PUSH EDI 289 | MOV EDI, Registers 290 | XOR EBX, EBX {clear EBX register} 291 | XOR ECX, ECX {clear ECX register} 292 | XOR EDX, EDX {clear EDX register} 293 | DB $0F, $A2 {CPUID opcode} 294 | MOV TRegisters(EDI).&EAX, EAX {save EAX register} 295 | MOV TRegisters(EDI).&EBX, EBX {save EBX register} 296 | MOV TRegisters(EDI).&ECX, ECX {save ECX register} 297 | MOV TRegisters(EDI).&EDX, EDX {save EDX register} 298 | POP EDI {restore registers} 299 | POP EBX 300 | {$else X64} 301 | PUSH RBX 302 | PUSH RDI 303 | MOV RDI, Registers 304 | MOV EAX, ECX 305 | XOR EBX, EBX 306 | XOR ECX, ECX 307 | XOR EDX, EDX 308 | CPUID 309 | MOV TRegisters(RDI).&EAX, EAX 310 | MOV TRegisters(RDI).&EBX, EBX 311 | MOV TRegisters(RDI).&ECX, ECX 312 | MOV TRegisters(RDI).&EDX, EDX 313 | POP RDI 314 | POP RBX 315 | {$endif} 316 | end; 317 | 318 | procedure GetCPUVendor; 319 | var 320 | VendorStr: TVendorStr; 321 | Registers: TRegisters; 322 | begin 323 | {call CPUID function 0} 324 | GetCPUID(0, Registers); 325 | 326 | {get vendor string} 327 | SetLength(VendorStr, 12); 328 | Move(Registers.EBX, VendorStr[1], 4); 329 | Move(Registers.EDX, VendorStr[5], 4); 330 | Move(Registers.ECX, VendorStr[9], 4); 331 | 332 | {get CPU vendor from vendor string} 333 | CPU.Vendor:= High(TVendor); 334 | while (VendorStr <> VendorIDString[CPU.Vendor]) and (CPU.Vendor > Low(TVendor)) do begin 335 | Dec(CPU.Vendor); 336 | end; 337 | end; 338 | 339 | procedure GetCPUFeatures; 340 | {preconditions: 1. maximum CPUID must be at least $00000001 341 | 2. GetCPUVendor must have been called} 342 | type 343 | _Int64 = packed record 344 | Lo: Longword; 345 | Hi: Longword; 346 | end; 347 | var 348 | Registers: TRegisters; 349 | CpuFeatures: TCpuFeatureSet; 350 | begin 351 | {call CPUID function $00000001} 352 | GetCPUID($00000001, Registers); 353 | 354 | {get CPU signature} 355 | CPU.Signature:= Registers.EAX; 356 | 357 | {extract effective processor family and model} 358 | CPU.EffFamily:= CPU.Signature and $00000F00 shr 8; 359 | CPU.EffModel:= CPU.Signature and $000000F0 shr 4; 360 | CPU.EffModelBasic:= CPU.EffModel; 361 | if CPU.EffFamily = $F then begin 362 | CPU.EffFamily:= CPU.EffFamily + (CPU.Signature and $0FF00000 shr 20); 363 | CPU.EffModel:= CPU.EffModel + (CPU.Signature and $000F0000 shr 12); 364 | end; 365 | 366 | {get CPU features} 367 | Move(Registers.EDX, _Int64(CpuFeatures).Lo, 4); 368 | Move(Registers.ECX, _Int64(CpuFeatures).Hi, 4); 369 | 370 | {get instruction support} 371 | if cfFPU in CpuFeatures then Include(CPU.InstructionSupport, isFPU); 372 | if cfTSC in CpuFeatures then Include(CPU.InstructionSupport, isTSC); 373 | if cfCX8 in CpuFeatures then Include(CPU.InstructionSupport, isCX8); 374 | if cfSEP in CpuFeatures then begin 375 | Include(CPU.InstructionSupport, isSEP); 376 | {for Intel CPUs, qualify the processor family and model to ensure that the 377 | SYSENTER/SYSEXIT instructions are actually present - see Intel Application 378 | Note AP-485} 379 | if (CPU.Vendor = cvIntel) and (CPU.Signature and $0FFF3FFF < IntelLowestSEPSupportSignature) then 380 | Exclude(CPU.InstructionSupport, isSEP); 381 | end; 382 | if cfCMOV in CpuFeatures then Include(CPU.InstructionSupport, isCMOV); 383 | if cfFXSR in CpuFeatures then Include(CPU.InstructionSupport, isFXSR); 384 | if cfMMX in CpuFeatures then Include(CPU.InstructionSupport, isMMX); 385 | if cfSSE in CpuFeatures then Include(CPU.InstructionSupport, isSSE); 386 | if cfSSE2 in CpuFeatures then Include(CPU.InstructionSupport, isSSE2); 387 | if cfSSE3 in CpuFeatures then Include(CPU.InstructionSupport, isSSE3); 388 | if cfSSSE3 in CpuFeatures then Include(CPU.InstructionSupport, isSSSE3); 389 | if cfSSE41 in CpuFeatures then Include(CPU.InstructionSupport, isSSE41); 390 | if cfSSE42 in CpuFeatures then Include(CPU.InstructionSupport, isSSE42); 391 | if cfAES in CpuFeatures then Include(CPU.InstructionSupport, isAES); 392 | if cfAVX in CpuFeatures then Include(CPU.InstructionSupport, isAVX); 393 | if cfPOPCNT in CpuFeatures then Include(CPU.InstructionSupport, isPopCnt); 394 | if cfCX16 in CpuFeatures then Include(CPU.InstructionSupport, isCX16); 395 | if cfXSAVE in CpuFeatures then Include(CPU.InstructionSupport, isXSAVE); 396 | if cfPCLMULQDQ in CpuFeatures then Include(CPU.InstructionSupport, isPCLMULQDQ); 397 | if cfFMA in CpuFeatures then Include(CPU.InstructionSupport, isFMA); 398 | if cfMovBE in CpuFeatures then Include(CPU.InstructionSupport, isMovBE); 399 | if cfF16C in CpuFeatures then Include(CPU.InstructionSupport, isF16C); 400 | if cfRDRAND in CpuFeatures then Include(CPU.InstructionSupport, isRDRAND); 401 | 402 | if {(CPU.Vendor = cvIntel) and }(cfMON in CpuFeatures) then Include(CPU.InstructionSupport, isMONITOR); 403 | 404 | end; 405 | 406 | procedure GetCPUExtendedFeatures; 407 | {preconditions: maximum extended CPUID >= $80000001} 408 | type 409 | _Int64 = packed record 410 | Lo: Longword; 411 | Hi: Longword; 412 | end; 413 | var 414 | Registers: TRegisters; 415 | CpuExFeatures: TCpuExtendedFeatureSet; 416 | begin 417 | {call CPUID function $80000001} 418 | GetCPUID($80000001, Registers); 419 | 420 | {get CPU extended features} 421 | Move(Registers.EDX, _Int64(CpuExFeatures).Lo, 4); 422 | Move(Registers.ECX, _Int64(CpuExFeatures).Hi, 4); 423 | //CPUExFeatures:= TCPUExtendedFeatureSet(Registers.EDX); 424 | 425 | {get instruction support} 426 | if cefLM in CpuExFeatures then Include(CPU.InstructionSupport, isX64); 427 | if cefExMMX in CpuExFeatures then Include(CPU.InstructionSupport, isExMMX); 428 | if cefEx3DNow in CpuExFeatures then Include(CPU.InstructionSupport, isEx3DNow); 429 | if cef3DNow in CpuExFeatures then Include(CPU.InstructionSupport, is3DNow); 430 | if cefRDTSCP in CpuExFeatures then Include(CPU.InstructionSupport, isRDTSCP); 431 | if cefTBM in CpuExFeatures then Include(CPU.InstructionSupport, isTBM); 432 | if cefFMA4 in CpuExFeatures then Include(CPU.InstructionSupport, isFMA4); 433 | if cefXOP in CpuExFeatures then Include(CPU.InstructionSupport, isXOP); 434 | if cefSSE4A in CpuExFeatures then Include(CPU.InstructionSupport, isSSE4A); 435 | if cefABM in CpuExFeatures then Include(CPU.InstructionSupport, isABM); 436 | if cefLahfSahf in CpuExFeatures then Include(CPU.InstructionSupport, isLAHF); 437 | 438 | end; 439 | 440 | procedure GetCPUExtendedFeatures7; 441 | type 442 | _Int64 = packed record 443 | Lo: Longword; 444 | Hi: Longword; 445 | end; 446 | var 447 | Registers: TRegisters; 448 | Cpu7ExFeatures: TCpuExtendedFeature7Set; 449 | begin 450 | {call CPUID function $80000001} 451 | GetCPUID($7, Registers); 452 | 453 | {get CPU extended features} 454 | Move(Registers.EBX, _Int64(Cpu7ExFeatures).Lo, 4); 455 | Move(Registers.ECX, _Int64(Cpu7ExFeatures).Hi, 4); 456 | 457 | {get instruction support} 458 | if ce7BMI1 in Cpu7ExFeatures then Include(CPU.InstructionSupport, isBMI1); 459 | if ce7AVX2 in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX2); 460 | if ce7BMI2 in Cpu7ExFeatures then Include(CPU.InstructionSupport, isBMI2); 461 | if ce7ERMS in Cpu7ExFeatures then Include(CPU.InstructionSupport, isERMS); 462 | if ce7INVPCID in Cpu7ExFeatures then Include(CPU.InstructionSupport, isINVPCID); 463 | if ce7RTM in Cpu7ExFeatures then Include(CPU.InstructionSupport, isRTM); 464 | if ce7MPX in Cpu7ExFeatures then Include(CPU.InstructionSupport, isMPX); 465 | if ce7AVX512f in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512f); 466 | if ce7AVX512dq in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512dq); 467 | if ce7RDSEED in Cpu7ExFeatures then Include(CPU.InstructionSupport, isRDSEED); 468 | if ce7ADX in Cpu7ExFeatures then Include(CPU.InstructionSupport, isADX); 469 | if ce7PCOMMIT in Cpu7ExFeatures then Include(CPU.InstructionSupport, isPCOMMIT); 470 | if ce7CLFLUSHOPT in Cpu7ExFeatures then Include(CPU.InstructionSupport, isCLFLUSHOPT); 471 | if ce7CLWB in Cpu7ExFeatures then Include(CPU.InstructionSupport, isCLWB); 472 | if ce7AVX512pf in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512pf); 473 | if ce7AVX512er in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512er); 474 | if ce7AVX512cd in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512cd); 475 | if ce7SHA in Cpu7ExFeatures then Include(CPU.InstructionSupport, isSHA); 476 | if ce7AVX512bw in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512bw); 477 | if ce7AVX512vl in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512vl); 478 | if ce7cPREFETCHWT1 in Cpu7ExFeatures then Include(CPU.InstructionSupport, isPREFETCHWT1); 479 | if ce7cAVX512vbmi in Cpu7ExFeatures then Include(CPU.InstructionSupport, isAVX512vbmi); 480 | end; 481 | 482 | procedure GetProcessorCacheInfo; 483 | {preconditions: 1. maximum CPUID must be at least $00000002 484 | 2. GetCPUVendor must have been called} 485 | type 486 | TConfigDescriptor = packed array[0..15] of Byte; 487 | var 488 | Registers: TRegisters; 489 | i, j: Integer; 490 | QueryCount: Byte; 491 | begin 492 | {call CPUID function 2} 493 | GetCPUID($00000002, Registers); 494 | QueryCount := Registers.EAX and $FF; 495 | for i := 1 to QueryCount do 496 | begin 497 | for j := 1 to 15 do 498 | with CPU do 499 | {decode configuration descriptor byte} 500 | case TConfigDescriptor(Registers)[j] of 501 | $06: CodeL1CacheSize := 8; 502 | $08: CodeL1CacheSize := 16; 503 | $0A: DataL1CacheSize := 8; 504 | $0C: DataL1CacheSize := 16; 505 | $22: L3CacheSize := 512; 506 | $23: L3CacheSize := 1024; 507 | $25: L3CacheSize := 2048; 508 | $29: L3CacheSize := 4096; 509 | $2C: DataL1CacheSize := 32; 510 | $30: CodeL1CacheSize := 32; 511 | $39: L2CacheSize := 128; 512 | $3B: L2CacheSize := 128; 513 | $3C: L2CacheSize := 256; 514 | $40: {no 2nd-level cache or, if processor contains a valid 2nd-level 515 | cache, no 3rd-level cache} 516 | if L2CacheSize <> 0 then 517 | L3CacheSize := 0; 518 | $41: L2CacheSize := 128; 519 | $42: L2CacheSize := 256; 520 | $43: L2CacheSize := 512; 521 | $44: L2CacheSize := 1024; 522 | $45: L2CacheSize := 2048; 523 | $60: DataL1CacheSize := 16; 524 | $66: DataL1CacheSize := 8; 525 | $67: DataL1CacheSize := 16; 526 | $68: DataL1CacheSize := 32; 527 | $70: if not (CPU.Vendor in [cvCyrix, cvNSC]) then 528 | CodeL1CacheSize := 12; {K micro-ops} 529 | $71: CodeL1CacheSize := 16; {K micro-ops} 530 | $72: CodeL1CacheSize := 32; {K micro-ops} 531 | $78: L2CacheSize := 1024; 532 | $79: L2CacheSize := 128; 533 | $7A: L2CacheSize := 256; 534 | $7B: L2CacheSize := 512; 535 | $7C: L2CacheSize := 1024; 536 | $7D: L2CacheSize := 2048; 537 | $7F: L2CacheSize := 512; 538 | $80: if CPU.Vendor in [cvCyrix, cvNSC] then 539 | begin {Cyrix and NSC only - 16 KB unified L1 cache} 540 | CodeL1CacheSize := 8; 541 | DataL1CacheSize := 8; 542 | end; 543 | $82: L2CacheSize := 256; 544 | $83: L2CacheSize := 512; 545 | $84: L2CacheSize := 1024; 546 | $85: L2CacheSize := 2048; 547 | $86: L2CacheSize := 512; 548 | $87: L2CacheSize := 1024; 549 | end; 550 | if i < QueryCount then 551 | GetCPUID(2, Registers); 552 | end; 553 | end; 554 | 555 | procedure GetExtendedProcessorCacheInfo; 556 | {preconditions: 1. maximum extended CPUID must be at least $80000006 557 | 2. GetCPUVendor and GetCPUFeatures must have been called} 558 | var 559 | Registers: TRegisters; 560 | begin 561 | {call CPUID function $80000005} 562 | GetCPUID($80000005, Registers); 563 | 564 | {get L1 cache size} 565 | {Note: Intel does not support function $80000005 for L1 cache size, so ignore. 566 | Cyrix returns CPUID function 2 descriptors (already done), so ignore.} 567 | if not (CPU.Vendor in [cvIntel, cvCyrix]) then 568 | begin 569 | CPU.CodeL1CacheSize := Registers.EDX shr 24; 570 | CPU.DataL1CacheSize := Registers.ECX shr 24; 571 | end; 572 | 573 | {call CPUID function $80000006} 574 | GetCPUID($80000006, Registers); 575 | 576 | {get L2 cache size} 577 | if (CPU.Vendor = cvAMD) and (CPU.Signature and $FFF = K7DuronA0Signature) then 578 | {workaround for AMD Duron Rev A0 L2 cache size erratum - see AMD Technical 579 | Note TN-13} 580 | CPU.L2CacheSize := 64 581 | else if (CPU.Vendor = cvCentaur) and (CPU.EffFamily = 6) and 582 | (CPU.EffModel in [C3Samuel2EffModel, C3EzraEffModel]) then 583 | {handle VIA (Centaur) C3 Samuel 2 and Ezra non-standard encoding} 584 | CPU.L2CacheSize := Registers.ECX shr 24 585 | else {standard encoding} 586 | CPU.L2CacheSize := Registers.ECX shr 16; 587 | end; 588 | 589 | procedure VerifyOSSupportForXMMRegisters; 590 | {$ifdef CPUX86} 591 | begin 592 | {try a SSE instruction that operates on XMM registers} 593 | try 594 | asm 595 | DB $0F, $54, $C0 // ANDPS XMM0, XMM0 596 | end 597 | except 598 | begin 599 | {if it fails, assume that none of the SSE instruction sets are available} 600 | Exclude(CPU.InstructionSupport, isSSE); 601 | Exclude(CPU.InstructionSupport, isSSE2); 602 | Exclude(CPU.InstructionSupport, isSSE3); 603 | end; 604 | end; 605 | {$ELSE} 606 | begin 607 | {do nothing} 608 | {$ENDIF} 609 | end; 610 | 611 | procedure GetCPUInfo; 612 | var 613 | Registers: TRegisters; 614 | MaxCPUID: Cardinal; 615 | MaxExCPUID: Cardinal; 616 | begin 617 | {initialize - just to be sure} 618 | FillChar(CPU, SizeOf(CPU), 0); 619 | 620 | try 621 | if not IsCPUID_Available then begin 622 | if IsFPU_Available then Include(CPU.InstructionSupport, isFPU); 623 | end else begin 624 | {get maximum CPUID input value} 625 | GetCPUID($00000000, Registers); 626 | MaxCPUID:= Registers.EAX; 627 | 628 | {get CPU vendor - Max CPUID will always be >= 0} 629 | GetCPUVendor; 630 | 631 | {get CPU features if available} 632 | if MaxCPUID >= $00000001 then GetCPUFeatures; 633 | 634 | {get cache info if available} 635 | if MaxCPUID >= $00000002 then GetProcessorCacheInfo; 636 | 637 | if MaxCPUID >= $00000007 then GetCPUExtendedFeatures7; 638 | 639 | {get maximum extended CPUID input value} 640 | GetCPUID($80000000, Registers); 641 | MaxExCPUID:= Registers.EAX; 642 | 643 | {get CPU extended features if available} 644 | if MaxExCPUID >= $80000001 then GetCPUExtendedFeatures; 645 | 646 | {verify operating system support for XMM registers} 647 | if isSSE in CPU.InstructionSupport then VerifyOSSupportForXMMRegisters; 648 | 649 | {get extended cache features if available} 650 | {Note: ignore processors that only report L1 cache info, 651 | i.e. have a MaxExCPUID = $80000005} 652 | if MaxExCPUID >= $80000006 then GetExtendedProcessorCacheInfo; 653 | end; 654 | except 655 | {silent exception - should not occur, just ignore} 656 | end; 657 | end; 658 | 659 | procedure GetUltraCode64Target; 660 | {precondition: GetCPUInfo must have been called} 661 | begin 662 | UltraCode64Target := fctRTLReplacement; 663 | 664 | if (isSSE2 in CPU.InstructionSupport) then UltraCode64Target:= fctBlendedSSE2 665 | else if (isSSE in CPU.InstructionSupport) then UltraCode64Target:= fctBlendedSSE 666 | else if (isSSE in CPU.InstructionSupport) then UltraCode64Target:= fctBlendedSSE 667 | else if ([isFPU, isMMX, isCMOV] <= CPU.InstructionSupport) then UltraCode64Target:= fctBlendedMMX 668 | else if ([isFPU, isCMOV] <= CPU.InstructionSupport) then UltraCode64Target:= fctBlendedIA32; 669 | 670 | case CPU.Vendor of 671 | cvIntel: case CPU.EffFamily of 672 | 6: {Intel P6, P2, P3, PM} case CPU.EffModel of 673 | PMDothanEffModel: UltraCode64Target:= fctPMD; // Dothan 674 | PMYonahEffModel: UltraCode64Target:= fctPMY; // Yonah 675 | end; 676 | $F: {Intel P4} case CPU.EffModel of 677 | 0, 1, 2: UltraCode64Target:= fctP4N; // Northwood 678 | 6: UltraCode64Target:= fctP4R; // Presler 679 | end; 680 | end; 681 | cvAMD: case CPU.EffFamily of 682 | $F: {AMD K8} if ((CPU.EffModelBasic = $B) or (CPU.EffModelBasic = $3)) and (isSSE3 in CPU.InstructionSupport) then 683 | UltraCode64Target:= fctAmd64_SSE3 //AMD X2 dual core CPU 684 | else UltraCode64Target:= fctAmd64; 685 | end; 686 | end; 687 | end; 688 | 689 | initialization 690 | GetCPUInfo; 691 | GetUltraCode64Target; 692 | end. 693 | -------------------------------------------------------------------------------- /Runtime/_dummy.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chmichael/UltraCode/e98bda0832c2e76316361c0d374fd756a45ce621/Runtime/_dummy.txt --------------------------------------------------------------------------------