├── .gitattributes ├── 80003es2lan.c ├── 80003es2lan.h ├── 82571.c ├── 82571.h ├── AppleIntelE1000e.cpp ├── AppleIntelE1000e.h ├── AppleIntelE1000e.xcodeproj └── project.pbxproj ├── COPYING ├── Info.plist ├── InfoPlist.strings ├── ML.xcodeproj └── project.pbxproj ├── README.md ├── defines.h ├── e1000.c ├── e1000.h ├── hw.h ├── ich8lan.c ├── ich8lan.h ├── kcompat.c ├── kcompat.h ├── mac.c ├── mac.h ├── manage.c ├── manage.h ├── netdev.c ├── nvm.c ├── nvm.h ├── param.c ├── phy.c ├── phy.h ├── ptp.c ├── regs.h └── version.plist /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /80003es2lan.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_80003ES2LAN_H_ 23 | #define _E1000E_80003ES2LAN_H_ 24 | 25 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 26 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 27 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 28 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F 29 | 30 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 31 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 32 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 33 | 34 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 35 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 36 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 37 | 38 | #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C 39 | #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 40 | 41 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ 42 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 43 | 44 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 45 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 46 | 47 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 48 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ 49 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 50 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ 51 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ 52 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ 53 | 54 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ 55 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ 56 | 57 | /* MAC Specific Control Register (Page 2, Register 21) */ 58 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 59 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 60 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 61 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 62 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 63 | 64 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 65 | 66 | /* DSP Distance Register (Page 5, Register 26) 67 | * 0 = <50M 68 | * 1 = 50-80M 69 | * 2 = 80-100M 70 | * 3 = 110-140M 71 | * 4 = >140M 72 | */ 73 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 74 | 75 | /* Kumeran Mode Control Register (Page 193, Register 16) */ 76 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 77 | 78 | /* Max number of times Kumeran read/write should be validated */ 79 | #define GG82563_MAX_KMRN_RETRY 0x5 80 | 81 | /* Power Management Control Register (Page 193, Register 20) */ 82 | /* 1=Enable SERDES Electrical Idle */ 83 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 84 | 85 | /* In-Band Control Register (Page 194, Register 18) */ 86 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 87 | 88 | #endif 89 | -------------------------------------------------------------------------------- /82571.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_82571_H_ 23 | #define _E1000E_82571_H_ 24 | 25 | #define ID_LED_RESERVED_F746 0xF746 26 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ 27 | (ID_LED_OFF1_ON2 << 8) | \ 28 | (ID_LED_DEF1_DEF2 << 4) | \ 29 | (ID_LED_DEF1_DEF2)) 30 | 31 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 32 | #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ 33 | 34 | /* Intr Throttling - RW */ 35 | #define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n))) 36 | 37 | #define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */ 38 | #define E1000_EIAC_MASK_82574 0x01F00000 39 | 40 | #define E1000_IVAR_INT_ALLOC_VALID 0x8 41 | 42 | /* Manageability Operation Mode mask */ 43 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 44 | 45 | #define E1000_BASE1000T_STATUS 10 46 | #define E1000_IDLE_ERROR_COUNT_MASK 0xFF 47 | #define E1000_RECEIVE_ERROR_COUNTER 21 48 | #define E1000_RECEIVE_ERROR_MAX 0xFFFF 49 | bool e1000_check_phy_82574(struct e1000_hw *hw); 50 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw); 51 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); 52 | 53 | #endif 54 | -------------------------------------------------------------------------------- /AppleIntelE1000e.h: -------------------------------------------------------------------------------- 1 | #ifndef __INTEL_E1000E_H__ 2 | #define __INTEL_E1000E_H__ 3 | 4 | #define MBit 1000000 5 | 6 | enum { 7 | eePowerStateOff = 0, 8 | eePowerStateOn, 9 | eePowerStateCount 10 | }; 11 | 12 | enum { 13 | kFiveSeconds = 5000000 14 | }; 15 | 16 | 17 | enum 18 | { 19 | MEDIUM_INDEX_AUTO = 0, 20 | MEDIUM_INDEX_10HD, 21 | MEDIUM_INDEX_10FD, 22 | MEDIUM_INDEX_100HD, 23 | MEDIUM_INDEX_100FD, 24 | MEDIUM_INDEX_1000FD, 25 | MEDIUM_INDEX_COUNT 26 | }; 27 | 28 | enum 29 | { 30 | kActivationLevelNone = 0, /* adapter shut off */ 31 | kActivationLevelKDP, /* adapter partially up to support KDP */ 32 | kActivationLevelBSD /* adapter fully up to support KDP and BSD */ 33 | }; 34 | 35 | enum 36 | { 37 | kFullInitialization = 0, 38 | kResetChip = 1 39 | }; 40 | 41 | #define MAX_RX_SIZE (kIOEthernetAddressSize+kIOEthernetMaxPacketSize) 42 | #define SIZE_RING_DESC PAGE_SIZE 43 | #define NUM_RING_FRAME 256 44 | 45 | class AppleIntelE1000e: public IOEthernetController 46 | { 47 | 48 | OSDeclareDefaultStructors(AppleIntelE1000e); 49 | 50 | public: 51 | // -------------------------------------------------- 52 | // IOService (or its superclass) methods. 53 | // -------------------------------------------------- 54 | 55 | virtual bool start(IOService * provider); 56 | virtual void stop(IOService * provider); 57 | virtual bool init(OSDictionary *properties); 58 | virtual void free(); 59 | virtual IOService* probe(IOService* provider,SInt32* score ); 60 | 61 | // -------------------------------------------------- 62 | // Power Management Support 63 | // -------------------------------------------------- 64 | virtual IOReturn registerWithPolicyMaker(IOService* policyMaker); 65 | virtual IOReturn setPowerState( unsigned long powerStateOrdinal, IOService *policyMaker ); 66 | 67 | // -------------------------------------------------- 68 | // IONetworkController methods. 69 | // -------------------------------------------------- 70 | 71 | virtual IOReturn enable(IONetworkInterface * netif); 72 | virtual IOReturn disable(IONetworkInterface * netif); 73 | 74 | virtual UInt32 outputPacket(mbuf_t m, void * param); 75 | 76 | virtual void getPacketBufferConstraints(IOPacketBufferConstraints * constraints) const; 77 | 78 | virtual IOOutputQueue * createOutputQueue(); 79 | 80 | virtual const OSString * newVendorString() const; 81 | virtual const OSString * newModelString() const; 82 | 83 | virtual IOReturn selectMedium(const IONetworkMedium * medium); 84 | virtual bool configureInterface(IONetworkInterface * interface); 85 | 86 | virtual bool createWorkLoop(); 87 | virtual IOWorkLoop * getWorkLoop() const; 88 | 89 | //----------------------------------------------------------------------- 90 | // Methods inherited from IOEthernetController. 91 | //----------------------------------------------------------------------- 92 | 93 | virtual IOReturn getHardwareAddress(IOEthernetAddress * addr); 94 | virtual IOReturn setHardwareAddress(const IOEthernetAddress * addr); 95 | virtual IOReturn setPromiscuousMode(bool active); 96 | virtual IOReturn setMulticastMode(bool active); 97 | virtual IOReturn setMulticastList(IOEthernetAddress * addrs, UInt32 count); 98 | virtual IOReturn getChecksumSupport(UInt32 *checksumMask, UInt32 checksumFamily, bool isOutput); 99 | virtual IOReturn setMaxPacketSize (UInt32 maxSize); 100 | virtual IOReturn getMaxPacketSize (UInt32 *maxSize) const; 101 | virtual IOReturn getMinPacketSize (UInt32 *minSize) const; 102 | virtual IOReturn setWakeOnMagicPacket(bool active); 103 | virtual IOReturn getPacketFilters(const OSSymbol * group, UInt32 * filters) const; 104 | 105 | virtual UInt32 getFeatures() const; 106 | private: 107 | IOWorkLoop* workLoop; 108 | IOPCIDevice* pciDevice; 109 | OSDictionary * mediumDict; 110 | IONetworkMedium * mediumTable[MEDIUM_INDEX_COUNT]; 111 | IOOutputQueue * transmitQueue; 112 | 113 | IOInterruptEventSource * interruptSource; 114 | IOTimerEventSource * watchdogSource; 115 | IOTimerEventSource * resetSource; 116 | 117 | IOEthernetInterface * netif; 118 | IONetworkStats * netStats; 119 | IOEthernetStats * etherStats; 120 | 121 | IOMemoryMap * csrPCIAddress; 122 | IOMemoryMap * flashPCIAddress; 123 | 124 | IOMbufNaturalMemoryCursor * rxMbufCursor; 125 | IOMbufNaturalMemoryCursor * txMbufCursor; 126 | 127 | bool enabledForNetif; 128 | bool promiscusMode; 129 | bool multicastMode; 130 | bool stalled; 131 | bool useTSO; 132 | UInt32 mcCount; 133 | UInt32 preLinkStatus; 134 | UInt32 powerState; 135 | 136 | struct e1000_adapter priv_adapter; 137 | struct pci_dev priv_pdev; 138 | struct net_device priv_netdev; 139 | UInt32 netdev_features; 140 | 141 | private: 142 | void interruptOccurred(IOInterruptEventSource * src); 143 | void timeoutOccurred(IOTimerEventSource* src); 144 | void doReset(); 145 | 146 | bool addNetworkMedium(UInt32 type, UInt32 bps, UInt32 index); 147 | 148 | bool initEventSources( IOService* provider ); 149 | bool initPCIConfigSpace(IOPCIDevice* provider); 150 | 151 | void e1000_clean_rx_ring(); 152 | void e1000_clean_tx_ring(); 153 | void e1000e_free_tx_resources(); 154 | void e1000e_free_rx_resources(); 155 | void e1000e_enable_receives(); 156 | bool e1000_clean_tx_irq(); 157 | bool e1000_clean_rx_irq(); 158 | bool e1000_clean_jumbo_rx_irq(); 159 | void e1000_print_hw_hang(); 160 | 161 | void e1000_put_txbuf(e1000_buffer *buffer_info); 162 | void e1000_alloc_rx_buffers(int cleaned_count); 163 | void e1000_alloc_jumbo_rx_buffers(int cleaned_count); 164 | 165 | void e1000_configure_rx(); 166 | void e1000_setup_rctl(); 167 | void e1000_init_manageability_pt(); 168 | void e1000_configure_tx(); 169 | void e1000e_set_rx_mode(); 170 | bool e1000_tx_csum(mbuf_t skb); 171 | void e1000_rx_checksum(mbuf_t skb, u32 status); 172 | void e1000_receive_skb(mbuf_t skb, u32 length, u32 staterr, __le16 vlan); 173 | void e1000_configure(); 174 | void e1000e_up(); 175 | void e1000e_down(bool reset); 176 | void e1000_change_mtu(UInt32 maxSize); 177 | 178 | int __e1000_shutdown(bool runtime); 179 | 180 | bool getBoolOption(const char *name, bool defVal); 181 | int getIntOption(const char *name, int defVal, int maxVal, int minVal ); 182 | private: 183 | bool clean_rx_irq(); 184 | void alloc_rx_buf(int cleaned_count); 185 | 186 | public: 187 | static void interruptHandler(OSObject * target, 188 | IOInterruptEventSource * src, 189 | int count ); 190 | 191 | 192 | static void timeoutHandler(OSObject * target, IOTimerEventSource * src); 193 | static void resetHandler(OSObject * target, IOTimerEventSource * src); 194 | }; 195 | 196 | 197 | #endif //__INTEL_E1000E_H__ 198 | -------------------------------------------------------------------------------- /AppleIntelE1000e.xcodeproj/project.pbxproj: -------------------------------------------------------------------------------- 1 | // !$*UTF8*$! 2 | { 3 | archiveVersion = 1; 4 | classes = { 5 | }; 6 | objectVersion = 46; 7 | objects = { 8 | 9 | /* Begin PBXBuildFile section */ 10 | 32D94FC60562CBF700B6AF17 /* AppleIntelE1000e.h in Headers */ = {isa = PBXBuildFile; fileRef = 1A224C3EFF42367911CA2CB7 /* AppleIntelE1000e.h */; }; 11 | 32D94FCA0562CBF700B6AF17 /* AppleIntelE1000e.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 1A224C3FFF42367911CA2CB7 /* AppleIntelE1000e.cpp */; settings = {ATTRIBUTES = (); }; }; 12 | 4D0D81731179AD4B000A4C84 /* InfoPlist.strings in Resources */ = {isa = PBXBuildFile; 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390 | rootObject = 089C1669FE841209C02AAC07 /* Project object */; 391 | } 392 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | 2 | "This software program is licensed subject to the GNU General Public License 3 | (GPL). Version 2, June 1991, available at 4 | " 5 | 6 | GNU General Public License 7 | 8 | Version 2, June 1991 9 | 10 | Copyright (C) 1989, 1991 Free Software Foundation, Inc. 11 | 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 12 | 13 | Everyone is permitted to copy and distribute verbatim copies of this license 14 | document, but changing it is not allowed. 15 | 16 | Preamble 17 | 18 | The licenses for most software are designed to take away your freedom to 19 | share and change it. By contrast, the GNU General Public License is intended 20 | to guarantee your freedom to share and change free software--to make sure 21 | the software is free for all its users. This General Public License applies 22 | to most of the Free Software Foundation's software and to any other program 23 | whose authors commit to using it. (Some other Free Software Foundation 24 | software is covered by the GNU Library General Public License instead.) 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If you wish to incorporate parts of the Program into other free programs 251 | whose distribution conditions are different, write to the author to ask 252 | for permission. For software which is copyrighted by the Free Software 253 | Foundation, write to the Free Software Foundation; we sometimes make 254 | exceptions for this. Our decision will be guided by the two goals of 255 | preserving the free status of all derivatives of our free software and 256 | of promoting the sharing and reuse of software generally. 257 | 258 | NO WARRANTY 259 | 260 | 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY 261 | FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN 262 | OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES 263 | PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 264 | EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 265 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE 266 | ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH 267 | YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 268 | NECESSARY SERVICING, REPAIR OR CORRECTION. 269 | 270 | 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 271 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 272 | REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 273 | DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 274 | DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM 275 | (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED 276 | INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF 277 | THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR 278 | OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 279 | 280 | END OF TERMS AND CONDITIONS 281 | 282 | How to Apply These Terms to Your New Programs 283 | 284 | If you develop a new program, and you want it to be of the greatest 285 | possible use to the public, the best way to achieve this is to make it free 286 | software which everyone can redistribute and change under these terms. 287 | 288 | To do so, attach the following notices to the program. It is safest to 289 | attach them to the start of each source file to most effectively convey the 290 | exclusion of warranty; and each file should have at least the "copyright" 291 | line and a pointer to where the full notice is found. 292 | 293 | one line to give the program's name and an idea of what it does. 294 | Copyright (C) yyyy name of author 295 | 296 | This program is free software; you can redistribute it and/or modify it 297 | under the terms of the GNU General Public License as published by the Free 298 | Software Foundation; either version 2 of the License, or (at your option) 299 | any later version. 300 | 301 | This program is distributed in the hope that it will be useful, but WITHOUT 302 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 303 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 304 | more details. 305 | 306 | You should have received a copy of the GNU General Public License along with 307 | this program; if not, write to the Free Software Foundation, Inc., 59 308 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this when 313 | it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author Gnomovision comes 316 | with ABSOLUTELY NO WARRANTY; for details type 'show w'. This is free 317 | software, and you are welcome to redistribute it under certain conditions; 318 | type 'show c' for details. 319 | 320 | The hypothetical commands 'show w' and 'show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may be 322 | called something other than 'show w' and 'show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | 'Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | signature of Ty Coon, 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Library General Public 339 | License instead of this License. 340 | -------------------------------------------------------------------------------- /Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | CFBundleDevelopmentRegion 6 | English 7 | CFBundleExecutable 8 | ${EXECUTABLE_NAME} 9 | CFBundleIconFile 10 | 11 | CFBundleIdentifier 12 | com.insanelymac.driver.${PRODUCT_NAME} 13 | CFBundleInfoDictionaryVersion 14 | 6.0 15 | CFBundleName 16 | ${PRODUCT_NAME} 17 | CFBundlePackageType 18 | KEXT 19 | CFBundleShortVersionString 20 | 3.3.6 21 | CFBundleSignature 22 | ???? 23 | CFBundleVersion 24 | 3.3.6 25 | IOKitPersonalities 26 | 27 | e1000e 28 | 29 | CFBundleIdentifier 30 | com.insanelymac.driver.${PRODUCT_NAME} 31 | E1000_CTRL_TFCE 32 | 33 | E1000_DEFAULT_RXD 34 | 256 35 | E1000_DEFAULT_TXD 36 | 256 37 | IOClass 38 | ${PRODUCT_NAME} 39 | IOPCIClassMatch 40 | 0x02000000&0xffff0000 41 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com.insanelymac.driver.AppleIntelE1000e; 308 | MODULE_VERSION = 1.0.0d1; 309 | PRODUCT_BUNDLE_IDENTIFIER = "com.insanelymac.driver.${PRODUCT_NAME}"; 310 | PRODUCT_NAME = AppleIntelE1000e; 311 | SDKROOT = macosx; 312 | WRAPPER_EXTENSION = kext; 313 | }; 314 | name = Release; 315 | }; 316 | 1DEB91DE08733DB10010E9CD /* Debug */ = { 317 | isa = XCBuildConfiguration; 318 | buildSettings = { 319 | ENABLE_TESTABILITY = YES; 320 | GCC_CW_ASM_SYNTAX = NO; 321 | GCC_C_LANGUAGE_STANDARD = gnu99; 322 | GCC_ENABLE_CPP_EXCEPTIONS = NO; 323 | GCC_ENABLE_CPP_RTTI = NO; 324 | GCC_ENABLE_OBJC_EXCEPTIONS = NO; 325 | GCC_ENABLE_PASCAL_STRINGS = NO; 326 | GCC_FAST_OBJC_DISPATCH = NO; 327 | GCC_LINK_WITH_DYNAMIC_LIBRARIES = NO; 328 | GCC_ONE_BYTE_BOOL = YES; 329 | GCC_OPTIMIZATION_LEVEL = 0; 330 | GCC_PREPROCESSOR_DEFINITIONS = DEBUG; 331 | GCC_VERSION = ""; 332 | GCC_WARN_ABOUT_RETURN_TYPE = YES; 333 | GCC_WARN_UNUSED_VARIABLE = YES; 334 | MACOSX_DEPLOYMENT_TARGET = 10.8; 335 | ONLY_ACTIVE_ARCH = YES; 336 | SDKROOT = macosx; 337 | VALID_ARCHS = x86_64; 338 | }; 339 | name = Debug; 340 | }; 341 | 1DEB91DF08733DB10010E9CD /* Release */ = { 342 | isa = XCBuildConfiguration; 343 | buildSettings = { 344 | GCC_CW_ASM_SYNTAX = NO; 345 | GCC_C_LANGUAGE_STANDARD = gnu99; 346 | GCC_ENABLE_CPP_EXCEPTIONS = NO; 347 | GCC_ENABLE_CPP_RTTI = NO; 348 | GCC_ENABLE_OBJC_EXCEPTIONS = NO; 349 | GCC_ENABLE_PASCAL_STRINGS = NO; 350 | GCC_FAST_OBJC_DISPATCH = NO; 351 | GCC_LINK_WITH_DYNAMIC_LIBRARIES = NO; 352 | GCC_ONE_BYTE_BOOL = YES; 353 | GCC_PREPROCESSOR_DEFINITIONS = ""; 354 | GCC_VERSION = ""; 355 | GCC_WARN_ABOUT_RETURN_TYPE = YES; 356 | GCC_WARN_UNUSED_VARIABLE = YES; 357 | MACOSX_DEPLOYMENT_TARGET = 10.8; 358 | ONLY_ACTIVE_ARCH = YES; 359 | SDKROOT = macosx; 360 | VALID_ARCHS = x86_64; 361 | }; 362 | name = Release; 363 | }; 364 | /* End XCBuildConfiguration section */ 365 | 366 | /* Begin XCConfigurationList section */ 367 | 1DEB91D908733DB10010E9CD /* Build configuration list for PBXNativeTarget "AppleIntelE1000e" */ = { 368 | isa = XCConfigurationList; 369 | buildConfigurations = ( 370 | 1DEB91DA08733DB10010E9CD /* Debug */, 371 | 1DEB91DB08733DB10010E9CD /* Release */, 372 | ); 373 | defaultConfigurationIsVisible = 0; 374 | defaultConfigurationName = Release; 375 | }; 376 | 1DEB91DD08733DB10010E9CD /* Build configuration list for PBXProject "ML" */ = { 377 | isa = XCConfigurationList; 378 | buildConfigurations = ( 379 | 1DEB91DE08733DB10010E9CD /* Debug */, 380 | 1DEB91DF08733DB10010E9CD /* Release */, 381 | ); 382 | defaultConfigurationIsVisible = 0; 383 | defaultConfigurationName = Release; 384 | }; 385 | /* End XCConfigurationList section */ 386 | }; 387 | rootObject = 089C1669FE841209C02AAC07 /* Project object */; 388 | } 389 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # AppleIntelE1000e 2 | 3 | ### Intel Network Drivers for macOS 4 | 5 | #### This is a Fork of [hnak /osx86drivers](https://sourceforge.net/projects/osx86drivers/) 6 | 7 | 8 | ### ** Release VERSION ** 9 | 10 | - I added a release V-3.3.6 compilling in Xcode 4.5.2 working for Mac OS X Lion to macOS High Sierra 10.13.4. 11 | 12 | [Download ➤ AppleIntelE1000e (Release)](https://github.com/chris1111/AppleIntelE1000e/releases/tag/V3.3.6) 13 | 14 | - I added New Release V-3.3.7 compilling in Xcode 3.2 working for Mac OS X Snow Leopard to macOS Catalina 10.15.5 (19F101) 15 | 16 | [Download ➤ AppleIntelE1000e (Release V-3.3.7 10.6 to Big Sur 11)](https://github.com/chris1111/AppleIntelE1000e/releases/tag/V3.3.7) 17 | 18 | 19 | ## From my Dell Optiplex 790. 20 | 21 | ![Modular Image Creation](https://i62.servimg.com/u/f62/18/50/18/69/captu461.png) 22 | 23 | 24 | ## From my HP ProDesk Big Sur 11 25 | ![Screen Shot network](https://user-images.githubusercontent.com/6248794/90956818-e0060500-e457-11ea-9c3d-d86549345db1.png) 26 | 27 | 28 | -------------------------------------------------------------------------------- /e1000.c: -------------------------------------------------------------------------------- 1 | /* 2 | * e1000.c 3 | * AppleIntelE1000e 4 | * 5 | * 6 | */ 7 | 8 | 9 | #include "e1000.h" 10 | 11 | #define PCI_VDEVICE(ven,dev) (dev) 12 | #define INTEL 0x8086 13 | typedef struct pci_device_id { 14 | u16 devid; 15 | u16 boardid; 16 | } pci_device_id; 17 | 18 | static const struct pci_device_id e1000_pci_tbl[] = { 19 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 20 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 21 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 22 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 23 | board_82571 }, 24 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 25 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 26 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 27 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 28 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 29 | 30 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 31 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 32 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 33 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 34 | 35 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 36 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 37 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 38 | 39 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 40 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 41 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 42 | 43 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 44 | board_80003es2lan }, 45 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 46 | board_80003es2lan }, 47 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 48 | board_80003es2lan }, 49 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 50 | board_80003es2lan }, 51 | 52 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 53 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 54 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 55 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 56 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 57 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 58 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 59 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 60 | 61 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 62 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 63 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 70 | 71 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 72 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 73 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 74 | 75 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 76 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 77 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 78 | 79 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 83 | 84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 85 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 86 | 87 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 88 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 89 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 90 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 91 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 92 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 93 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 94 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 95 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 96 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 97 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 98 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 99 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 100 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 101 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 102 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 103 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 104 | 105 | { 0, 0 } /* terminate list */ 106 | }; 107 | 108 | static const struct e1000_info *e1000_info_tbl[] = { 109 | [board_82571] = &e1000_82571_info, 110 | [board_82572] = &e1000_82572_info, 111 | [board_82573] = &e1000_82573_info, 112 | [board_82574] = &e1000_82574_info, 113 | [board_82583] = &e1000_82583_info, 114 | [board_80003es2lan] = &e1000_es2_info, 115 | [board_ich8lan] = &e1000_ich8_info, 116 | [board_ich9lan] = &e1000_ich9_info, 117 | [board_ich10lan] = &e1000_ich10_info, 118 | [board_pchlan] = &e1000_pch_info, 119 | [board_pch2lan] = &e1000_pch2_info, 120 | [board_pch_lpt] = &e1000_pch_lpt_info, 121 | [board_pch_spt] = &e1000_pch_spt_info, 122 | }; 123 | 124 | 125 | const struct e1000_info* e1000_probe( u16 pci_dev_id ) 126 | { 127 | for(int k = 0; k < sizeof(e1000_pci_tbl)/sizeof(e1000_pci_tbl[0]); k++ ){ 128 | if(e1000_pci_tbl[k].devid == pci_dev_id ) 129 | return e1000_info_tbl[e1000_pci_tbl[k].boardid]; 130 | } 131 | return NULL; 132 | } 133 | 134 | s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 135 | { 136 | return -E1000_ERR_CONFIG; 137 | } 138 | 139 | /** 140 | * __ew32_prepare - prepare to write to MAC CSR register on certain parts 141 | * @hw: pointer to the HW structure 142 | * 143 | * When updating the MAC CSR registers, the Manageability Engine (ME) could 144 | * be accessing the registers at the same time. Normally, this is handled in 145 | * h/w by an arbiter but on some parts there is a bug that acknowledges Host 146 | * accesses later than it should which could result in the register to have 147 | * an incorrect value. Workaround this by checking the FWSM register which 148 | * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 149 | * and try again a number of times. 150 | **/ 151 | s32 __ew32_prepare(struct e1000_hw *hw) 152 | { 153 | s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 154 | 155 | while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 156 | udelay(50); 157 | 158 | return i; 159 | } 160 | 161 | void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 162 | { 163 | if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 164 | __ew32_prepare(hw); 165 | 166 | writel(val, hw->hw_addr + reg); 167 | } 168 | 169 | 170 | // Mutex used in ich8lan.c 171 | IOLock* swflag_mutex; 172 | IOLock* nvm_mutex; 173 | 174 | -------------------------------------------------------------------------------- /ich8lan.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_ICH8LAN_H_ 23 | #define _E1000E_ICH8LAN_H_ 24 | 25 | #define ICH_FLASH_GFPREG 0x0000 26 | #define ICH_FLASH_HSFSTS 0x0004 27 | #define ICH_FLASH_HSFCTL 0x0006 28 | #define ICH_FLASH_FADDR 0x0008 29 | #define ICH_FLASH_FDATA0 0x0010 30 | 31 | /* Requires up to 10 seconds when MNG might be accessing part. */ 32 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 33 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 34 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 35 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 36 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 37 | 38 | #define ICH_CYCLE_READ 0 39 | #define ICH_CYCLE_WRITE 2 40 | #define ICH_CYCLE_ERASE 3 41 | 42 | #define FLASH_GFPREG_BASE_MASK 0x1FFF 43 | #define FLASH_SECTOR_ADDR_SHIFT 12 44 | 45 | #define ICH_FLASH_SEG_SIZE_256 256 46 | #define ICH_FLASH_SEG_SIZE_4K 4096 47 | #define ICH_FLASH_SEG_SIZE_8K 8192 48 | #define ICH_FLASH_SEG_SIZE_64K 65536 49 | 50 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 51 | /* FW established a valid mode */ 52 | #define E1000_ICH_FWSM_FW_VALID 0x00008000 53 | #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 54 | #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 55 | 56 | #define E1000_ICH_MNG_IAMT_MODE 0x2 57 | 58 | #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 59 | #define E1000_FWSM_WLOCK_MAC_SHIFT 7 60 | #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ 61 | 62 | /* Shared Receive Address Registers */ 63 | #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 64 | #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 65 | 66 | #define E1000_H2ME 0x05B50 /* Host to ME */ 67 | #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ 68 | #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ 69 | 70 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 71 | (ID_LED_OFF1_OFF2 << 8) | \ 72 | (ID_LED_OFF1_ON2 << 4) | \ 73 | (ID_LED_DEF1_DEF2)) 74 | 75 | #define E1000_ICH_NVM_SIG_WORD 0x13 76 | #define E1000_ICH_NVM_SIG_MASK 0xC000 77 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 78 | #define E1000_ICH_NVM_SIG_VALUE 0x80 79 | 80 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 81 | 82 | /* FEXT register bit definition */ 83 | #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 84 | 85 | #define E1000_FEXTNVM_SW_CONFIG 1 86 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 87 | 88 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 89 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 90 | 91 | #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 92 | #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 93 | #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 94 | 95 | #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 96 | #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 97 | #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000 98 | /* bit for disabling packet buffer read */ 99 | #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000 100 | #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 101 | #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 102 | #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 103 | #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 104 | #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200 105 | #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 106 | 107 | /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */ 108 | #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000 109 | 110 | #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */ 111 | #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */ 112 | #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ 113 | #define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29) 114 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 115 | 116 | #define E1000_ICH_RAR_ENTRIES 7 117 | #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 118 | #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 119 | 120 | #define PHY_PAGE_SHIFT 5 121 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 122 | ((reg) & MAX_PHY_REG_ADDRESS)) 123 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 124 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 125 | 126 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 127 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 128 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 129 | 130 | /* PHY Wakeup Registers and defines */ 131 | #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 132 | #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 133 | #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 134 | #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 135 | #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 136 | #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 137 | #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 138 | #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 139 | #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 140 | #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 141 | 142 | #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 143 | #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 144 | #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 145 | #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 146 | #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 147 | #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 148 | #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 149 | 150 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 151 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 152 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 153 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 154 | #define HV_STATS_PAGE 778 155 | /* Half-duplex collision counts */ 156 | #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ 157 | #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 158 | #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ 159 | #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 160 | #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ 161 | #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 162 | #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ 163 | #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 164 | #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ 165 | #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 166 | #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 167 | #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 168 | #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 169 | #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 170 | 171 | #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 172 | 173 | #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 174 | #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 175 | #define K1_ENTRY_LATENCY 0 176 | #define K1_MIN_TIME 1 177 | 178 | /* SMBus Control Phy Register */ 179 | #define CV_SMB_CTRL PHY_REG(769, 23) 180 | #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 181 | 182 | /* I218 Ultra Low Power Configuration 1 Register */ 183 | #define I218_ULP_CONFIG1 PHY_REG(779, 16) 184 | #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 185 | #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 186 | #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 187 | #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 188 | #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 189 | #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ 190 | /* enable ULP even if when phy powered down via lanphypc */ 191 | #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 192 | /* disable clear of sticky ULP on PERST */ 193 | #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 194 | #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 195 | 196 | /* SMBus Address Phy Register */ 197 | #define HV_SMB_ADDR PHY_REG(768, 26) 198 | #define HV_SMB_ADDR_MASK 0x007F 199 | #define HV_SMB_ADDR_PEC_EN 0x0200 200 | #define HV_SMB_ADDR_VALID 0x0080 201 | #define HV_SMB_ADDR_FREQ_MASK 0x1100 202 | #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 203 | #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 204 | 205 | /* Strapping Option Register - RO */ 206 | #define E1000_STRAP 0x0000C 207 | #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 208 | #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 209 | #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 210 | #define E1000_STRAP_SMT_FREQ_SHIFT 12 211 | 212 | /* OEM Bits Phy Register */ 213 | #define HV_OEM_BITS PHY_REG(768, 25) 214 | #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 215 | #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 216 | #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 217 | 218 | /* KMRN Mode Control */ 219 | #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 220 | #define HV_KMRN_MDIO_SLOW 0x0400 221 | 222 | /* KMRN FIFO Control and Status */ 223 | #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 224 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 225 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 226 | 227 | /* PHY Power Management Control */ 228 | #define HV_PM_CTRL PHY_REG(770, 17) 229 | #define HV_PM_CTRL_K1_CLK_REQ 0x200 230 | #define HV_PM_CTRL_K1_ENABLE 0x4000 231 | 232 | #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) 233 | #define I217_PLL_CLOCK_GATE_MASK 0x07FF 234 | 235 | #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 236 | 237 | /* Inband Control */ 238 | #define I217_INBAND_CTRL PHY_REG(770, 18) 239 | #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 240 | #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 241 | 242 | /* Low Power Idle GPIO Control */ 243 | #define I217_LPI_GPIO_CTRL PHY_REG(772, 18) 244 | #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800 245 | 246 | /* PHY Low Power Idle Control */ 247 | #define I82579_LPI_CTRL PHY_REG(772, 20) 248 | #define I82579_LPI_CTRL_100_ENABLE 0x2000 249 | #define I82579_LPI_CTRL_1000_ENABLE 0x4000 250 | #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 251 | 252 | /* 82579 DFT Control */ 253 | #define I82579_DFT_CTRL PHY_REG(769, 20) 254 | #define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */ 255 | 256 | /* Extended Management Interface (EMI) Registers */ 257 | #define I82579_EMI_ADDR 0x10 258 | #define I82579_EMI_DATA 0x11 259 | #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 260 | #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 261 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 262 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 263 | #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 264 | #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */ 265 | #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ 266 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 267 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 268 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 269 | #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ 270 | #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ 271 | #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */ 272 | #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 273 | #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 274 | #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 275 | #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 276 | #define I217_RX_CONFIG 0xB20C /* Receive configuration */ 277 | 278 | #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 279 | #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 280 | 281 | /* Intel Rapid Start Technology Support */ 282 | #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 283 | #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 284 | #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) 285 | #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 286 | #define I217_CGFREG PHY_REG(772, 29) 287 | #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 288 | #define I217_MEMPWR PHY_REG(772, 26) 289 | #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 290 | 291 | /* Receive Address Initial CRC Calculation */ 292 | #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 293 | 294 | /* Latency Tolerance Reporting */ 295 | #define E1000_LTRV 0x000F8 296 | #define E1000_LTRV_SCALE_MAX 5 297 | #define E1000_LTRV_SCALE_FACTOR 5 298 | #define E1000_LTRV_REQ_SHIFT 15 299 | #define E1000_LTRV_NOSNOOP_SHIFT 16 300 | #define E1000_LTRV_SEND (1 << 30) 301 | 302 | /* Proprietary Latency Tolerance Reporting PCI Capability */ 303 | #define E1000_PCI_LTR_CAP_LPT 0xA8 304 | 305 | #define E1000_PCI_REVISION_ID_REG 0x08 306 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 307 | bool state); 308 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 309 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 310 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 311 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 312 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 313 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 314 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 315 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 316 | s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 317 | s32 e1000_set_eee_pchlan(struct e1000_hw *hw); 318 | s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); 319 | #endif /* _E1000E_ICH8LAN_H_ */ 320 | #ifdef DYNAMIC_LTR_SUPPORT 321 | void e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link); 322 | #endif /* DYNAMIC_LTR_SUPPORT */ 323 | -------------------------------------------------------------------------------- /kcompat.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | 3 | Macros to compile Intel PRO/1000 Linux driver almost-as-is for Mac OS X. 4 | 5 | *******************************************************************************/ 6 | 7 | #ifndef _KCOMPAT_H_ 8 | #define _KCOMPAT_H_ 9 | 10 | #define s64 __int64_t 11 | #define s32 __int32_t 12 | #define s16 __int16_t 13 | #define s8 __int8_t 14 | #define u64 __uint64_t 15 | #define u32 __uint32_t 16 | #define u16 __uint16_t 17 | #define u8 __uint8_t 18 | 19 | #ifndef __le16 20 | #define __le16 __uint16_t 21 | #endif 22 | #ifndef __le32 23 | #define __le32 __uint32_t 24 | #endif 25 | #ifndef __le64 26 | #define __le64 __uint64_t 27 | #endif 28 | #ifndef __be16 29 | #define __be16 __uint16_t 30 | #endif 31 | #ifndef __be32 32 | #define __be32 __uint32_t 33 | #endif 34 | #ifndef __be64 35 | #define __be64 __uint64_t 36 | #endif 37 | 38 | #define sk_buff __mbuf 39 | 40 | #define __iomem 41 | #define __devinit 42 | #define __always_unused 43 | 44 | #define dma_addr_t IOPhysicalAddress 45 | 46 | #define ____cacheline_aligned_in_smp 47 | 48 | #define true 1 49 | #define false 0 50 | 51 | #define min_t(type,x,y) \ 52 | ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 53 | 54 | #define max_t(type, x, y) \ 55 | ({ type __max1 = (x); type __max2 = (y); __max1 > __max2 ? __max1: __max2; }) 56 | 57 | #define cpu_to_le16(x) OSSwapHostToLittleConstInt16(x) 58 | #define cpu_to_le32(x) OSSwapHostToLittleConstInt32(x) 59 | #define cpu_to_le64(x) OSSwapHostToLittleConstInt64(x) 60 | #define le16_to_cpu(x) OSSwapLittleToHostInt16(x) 61 | #define le32_to_cpu(x) OSSwapLittleToHostInt32(x) 62 | #if defined(__BIG_ENDIAN__) 63 | #define le16_to_cpus(x) (*(x)=le16_to_cpu(*(x))) 64 | #else 65 | #define le16_to_cpus(x) 66 | #endif 67 | 68 | #define writel(val, reg) _OSWriteInt32(reg, 0, val) 69 | #define writew(val, reg) _OSWriteInt16(reg, 0, val) 70 | #define readl(reg) _OSReadInt32(reg, 0) 71 | #define readw(reg) _OSReadInt16(reg, 0) 72 | 73 | #define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) 74 | 75 | #define BITS_PER_LONG 32 76 | #ifndef BIT 77 | #define BIT(n) (1<<(n)) 78 | #endif 79 | 80 | #define BITS_TO_LONGS(bits) \ 81 | (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) 82 | 83 | /* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ 84 | #define GFP_ATOMIC 0 85 | 86 | struct net_device { 87 | u32 mtu; 88 | }; 89 | typedef struct pci_dev { 90 | u16 vendor; 91 | u16 device; 92 | void* provider; 93 | } pci_dev; 94 | 95 | struct net_device_stats { 96 | unsigned long rx_packets; /* total packets received */ 97 | unsigned long tx_packets; /* total packets transmitted */ 98 | unsigned long rx_bytes; /* total bytes received */ 99 | unsigned long tx_bytes; /* total bytes transmitted */ 100 | unsigned long rx_errors; /* bad packets received */ 101 | unsigned long tx_errors; /* packet transmit problems */ 102 | unsigned long rx_dropped; /* no space in linux buffers */ 103 | unsigned long tx_dropped; /* no space available in linux */ 104 | unsigned long multicast; /* multicast packets received */ 105 | unsigned long collisions; 106 | 107 | /* detailed rx_errors: */ 108 | unsigned long rx_length_errors; 109 | unsigned long rx_over_errors; /* receiver ring buff overflow */ 110 | unsigned long rx_crc_errors; /* recved pkt with crc error */ 111 | unsigned long rx_frame_errors; /* recv'd frame alignment error */ 112 | unsigned long rx_fifo_errors; /* recv'r fifo overrun */ 113 | unsigned long rx_missed_errors; /* receiver missed packet */ 114 | 115 | /* detailed tx_errors */ 116 | unsigned long tx_aborted_errors; 117 | unsigned long tx_carrier_errors; 118 | unsigned long tx_fifo_errors; 119 | unsigned long tx_heartbeat_errors; 120 | unsigned long tx_window_errors; 121 | 122 | /* for cslip etc */ 123 | unsigned long rx_compressed; 124 | unsigned long tx_compressed; 125 | }; 126 | 127 | struct list_head { 128 | struct list_head *next, *prev; 129 | }; 130 | 131 | struct timer_list { 132 | struct list_head entry; 133 | unsigned long expires; 134 | 135 | //spinlock_t lock; 136 | unsigned long magic; 137 | 138 | void (*function)(unsigned long); 139 | unsigned long data; 140 | 141 | //struct tvec_t_base_s *base; 142 | }; 143 | 144 | struct work_struct { 145 | void* src; // IOTimerEventSrc 146 | }; 147 | 148 | #define ADVERTISED_10baseT_Half (1 << 0) 149 | #define ADVERTISED_10baseT_Full (1 << 1) 150 | #define ADVERTISED_100baseT_Half (1 << 2) 151 | #define ADVERTISED_100baseT_Full (1 << 3) 152 | #define ADVERTISED_1000baseT_Half (1 << 4) 153 | #define ADVERTISED_1000baseT_Full (1 << 5) 154 | #define ADVERTISED_Autoneg (1 << 6) 155 | #define ADVERTISED_TP (1 << 7) 156 | #define ADVERTISED_MII (1 << 9) 157 | #define ADVERTISED_FIBRE (1 << 10) 158 | #define ADVERTISED_10000baseT_Full (1 << 12) 159 | #define ADVERTISED_2500baseX_Full (1 << 15) 160 | 161 | #define ADVERTISED_Default (\ 162 | ADVERTISED_10baseT_Half|ADVERTISED_10baseT_Full|\ 163 | ADVERTISED_100baseT_Full|ADVERTISED_100baseT_Half|\ 164 | ADVERTISED_1000baseT_Full|\ 165 | ADVERTISED_Autoneg|ADVERTISED_TP|ADVERTISED_MII) 166 | 167 | #define SPEED_10 10 168 | #define SPEED_100 100 169 | #define SPEED_1000 1000 170 | 171 | #define IFNAMSIZ 16 172 | 173 | #define ETH_ALEN 6 /* Octets in one ethernet addr */ 174 | #define ETH_HLEN 14 /* Total octets in header. */ 175 | #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ 176 | #define ETH_DATA_LEN 1500 /* Max. octets in payload */ 177 | #define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ 178 | #define ETH_FCS_LEN 4 /* Octets in the FCS */ 179 | 180 | #define ETH_P_IP 0x0800 181 | #define ETH_P_IPV6 0x86DD 182 | 183 | #define VLAN_HLEN 4 /* The additional bytes (on top of the Ethernet header) that VLAN requires. */ 184 | #define VLAN_ETH_ALEN 6 /* Octets in one ethernet addr */ 185 | #define VLAN_ETH_HLEN 18 /* Total octets in header. */ 186 | #define VLAN_ETH_ZLEN 64 /* Min. octets in frame sans FCS */ 187 | #define VLAN_ETH_FRAME_LEN 1518 /* Max. octets in frame sans FCS */ 188 | #define VLAN_N_VID 4096 189 | 190 | /* Generic MII registers. */ 191 | #define MII_BMCR 0x00 /* Basic mode control register */ 192 | #define MII_BMSR 0x01 /* Basic mode status register */ 193 | #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 194 | #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 195 | #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 196 | #define MII_LPA 0x05 /* Link partner ability reg */ 197 | #define MII_EXPANSION 0x06 /* Expansion register */ 198 | #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 199 | #define MII_STAT1000 0x0a /* 1000BASE-T status */ 200 | #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 201 | #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 202 | #define MII_ESTATUS 0x0f /* Extended Status */ 203 | #define MII_DCOUNTER 0x12 /* Disconnect counter */ 204 | #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 205 | #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 206 | #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 207 | #define MII_SREVISION 0x16 /* Silicon revision */ 208 | #define MII_RESV1 0x17 /* Reserved... */ 209 | #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 210 | #define MII_PHYADDR 0x19 /* PHY address */ 211 | #define MII_RESV2 0x1a /* Reserved... */ 212 | #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 213 | #define MII_NCONFIG 0x1c /* Network interface config */ 214 | 215 | /* Basic mode control register. */ 216 | #define BMCR_RESV 0x003f /* Unused... */ 217 | #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ 218 | #define BMCR_CTST 0x0080 /* Collision test */ 219 | #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 220 | #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 221 | #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ 222 | #define BMCR_PDOWN 0x0800 /* Enable low power state */ 223 | #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 224 | #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 225 | #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 226 | #define BMCR_RESET 0x8000 /* Reset to default state */ 227 | 228 | /* Basic mode status register. */ 229 | #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 230 | #define BMSR_JCD 0x0002 /* Jabber detected */ 231 | #define BMSR_LSTATUS 0x0004 /* Link status */ 232 | #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 233 | #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 234 | #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 235 | #define BMSR_RESV 0x00c0 /* Unused... */ 236 | #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ 237 | #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ 238 | #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ 239 | #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 240 | #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 241 | #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 242 | #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 243 | #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 244 | 245 | /* Advertisement control register. */ 246 | #define ADVERTISE_SLCT 0x001f /* Selector bits */ 247 | #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 248 | #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 249 | #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ 250 | #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 251 | #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ 252 | #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 253 | #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ 254 | #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 255 | #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ 256 | #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 257 | #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 258 | #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 259 | #define ADVERTISE_RESV 0x1000 /* Unused... */ 260 | #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 261 | #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 262 | #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 263 | 264 | /* Link partner ability register. */ 265 | #define LPA_SLCT 0x001f /* Same as advertise selector */ 266 | #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 267 | #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ 268 | #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 269 | #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ 270 | #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 271 | #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ 272 | #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 273 | #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ 274 | #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 275 | #define LPA_PAUSE_CAP 0x0400 /* Can pause */ 276 | #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 277 | #define LPA_RESV 0x1000 /* Unused... */ 278 | #define LPA_RFAULT 0x2000 /* Link partner faulted */ 279 | #define LPA_LPACK 0x4000 /* Link partner acked us */ 280 | #define LPA_NPAGE 0x8000 /* Next page bit */ 281 | 282 | #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 283 | #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 284 | 285 | #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 286 | #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 287 | #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 288 | #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 289 | #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 290 | #define EXPANSION_RESV 0xffe0 /* Unused... */ 291 | 292 | /* 1000BASE-T Control register */ 293 | #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 294 | #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 295 | #define CTL1000_AS_MASTER 0x0800 296 | #define CTL1000_ENABLE_MASTER 0x1000 297 | 298 | /* 1000BASE-T Status register */ 299 | #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ 300 | #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ 301 | #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ 302 | #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ 303 | 304 | /* EEE Supported/Advertisement/LP Advertisement registers. 305 | */ 306 | #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ 307 | #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ 308 | 309 | #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */ 310 | #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */ 311 | #define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ 312 | #define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ 313 | #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ 314 | #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ 315 | 316 | 317 | #define NET_IP_ALIGN 2 318 | #ifndef NETIF_F_RXFCS 319 | #define NETIF_F_RXFCS 0 320 | #endif /* NETIF_F_RXFCS */ 321 | #ifndef NETIF_F_RXALL 322 | #define NETIF_F_RXALL 0 323 | #endif /* NETIF_F_RXALL */ 324 | 325 | 326 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 327 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 328 | #define PCI_AF_CAP 3 329 | #define PCI_AF_CAP_FLR 0x02 330 | 331 | #define PCI_EXP_DEVCTL 8 332 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 333 | #define PCI_EXP_LNKCTL 16 334 | #define PCIE_LINK_STATE_L0S 1 335 | #define PCIE_LINK_STATE_L1 2 336 | #define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */ 337 | #define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */ 338 | 339 | #define PCI_LTR_MAX_SNOOP_LAT 0x4 340 | #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 341 | #define PCI_LTR_VALUE_MASK 0x000003ff 342 | #define PCI_LTR_SCALE_MASK 0x00001c00 343 | #define PCI_LTR_SCALE_SHIFT 10 344 | 345 | #define MAX_NUMNODES 1 346 | #define first_online_node 0 347 | #define node_online(node) ((node) == 0) 348 | #define ether_crc_le(length, data) _kc_ether_crc_le(length, data) 349 | #ifndef is_zero_ether_addr 350 | #define is_zero_ether_addr _kc_is_zero_ether_addr 351 | static inline int _kc_is_zero_ether_addr(const u8 *addr) 352 | { 353 | return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]); 354 | } 355 | #endif 356 | #ifndef is_multicast_ether_addr 357 | #define is_multicast_ether_addr _kc_is_multicast_ether_addr 358 | static inline int _kc_is_multicast_ether_addr(const u8 *addr) 359 | { 360 | return addr[0] & 0x01; 361 | } 362 | #endif /* is_multicast_ether_addr */ 363 | 364 | static inline unsigned int _kc_ether_crc_le(int length, unsigned char *data) 365 | { 366 | unsigned int crc = 0xffffffff; /* Initial value. */ 367 | while(--length >= 0) { 368 | unsigned char current_octet = *data++; 369 | int bit; 370 | for (bit = 8; --bit >= 0; current_octet >>= 1) { 371 | if ((crc ^ current_octet) & 1) { 372 | crc >>= 1; 373 | crc ^= 0xedb88320U; 374 | } else 375 | crc >>= 1; 376 | } 377 | } 378 | return crc; 379 | } 380 | 381 | #define EIO 5 382 | #define ENOMEM 12 383 | #define EBUSY 16 384 | /*****************************************************************************/ 385 | #define msleep(x) IOSleep(x) 386 | #define udelay(x) IODelay(x) 387 | #define might_sleep() 388 | 389 | #define mdelay(x) for(int i = 0; i < x; i++ )udelay(1000) 390 | #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) 391 | #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000)) 392 | 393 | 394 | /*****************************************************************************/ 395 | 396 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) 397 | 398 | /************** Ugly macros to compile ich8lan.c *****************************/ 399 | 400 | #define DEFINE_MUTEX(x) void x##_dummy(){} 401 | #define mutex_lock(x) IOLockLock(*x) 402 | #define mutex_unlock(x) IOLockUnlock(*x) 403 | 404 | #ifndef __cplusplus 405 | typedef void IOBufferMemoryDescriptor; 406 | #endif 407 | 408 | #define prefetch(x) 409 | #define unlikely(x) (x) 410 | #define likely(x) (x) 411 | #define BUG() 412 | #define BUG_ON(x) 413 | #define wmb() OSSynchronizeIO() 414 | #define mmiowb() OSSynchronizeIO() 415 | #define rmb() 416 | 417 | #ifndef BIT 418 | #define BIT(nr) (1UL << (nr)) 419 | #endif 420 | 421 | #define __MODULE_STRING(s) "x" 422 | #define synchronize_irq(x) 423 | 424 | static inline int test_bit(int nr, const volatile unsigned long * addr) { 425 | return (*addr & (1< 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_MAC_H_ 23 | #define _E1000E_MAC_H_ 24 | 25 | s32 e1000e_blink_led_generic(struct e1000_hw *hw); 26 | s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 27 | s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 28 | s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 29 | s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 30 | s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); 31 | s32 e1000e_disable_pcie_master(struct e1000_hw *hw); 32 | s32 e1000e_force_mac_fc(struct e1000_hw *hw); 33 | s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); 34 | s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); 35 | void e1000_set_lan_id_single_port(struct e1000_hw *hw); 36 | s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); 37 | s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 38 | u16 *duplex); 39 | s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, 40 | u16 *speed, u16 *duplex); 41 | s32 e1000e_id_led_init_generic(struct e1000_hw *hw); 42 | s32 e1000e_led_on_generic(struct e1000_hw *hw); 43 | s32 e1000e_led_off_generic(struct e1000_hw *hw); 44 | void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 45 | u8 *mc_addr_list, u32 mc_addr_count); 46 | s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); 47 | s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); 48 | s32 e1000e_setup_led_generic(struct e1000_hw *hw); 49 | s32 e1000e_setup_link_generic(struct e1000_hw *hw); 50 | s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw); 51 | s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw); 52 | 53 | void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); 54 | void e1000_clear_vfta_generic(struct e1000_hw *hw); 55 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 56 | void e1000e_put_hw_semaphore(struct e1000_hw *hw); 57 | s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); 58 | void e1000e_reset_adaptive(struct e1000_hw *hw); 59 | void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); 60 | void e1000e_update_adaptive(struct e1000_hw *hw); 61 | void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); 62 | 63 | void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 64 | u32 e1000e_rar_get_count_generic(struct e1000_hw *hw); 65 | int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 66 | void e1000e_config_collision_dist_generic(struct e1000_hw *hw); 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /manage.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #include "e1000.h" 23 | /** 24 | * e1000_calculate_checksum - Calculate checksum for buffer 25 | * @buffer: pointer to EEPROM 26 | * @length: size of EEPROM to calculate a checksum for 27 | * 28 | * Calculates the checksum for some buffer on a specified length. The 29 | * checksum calculated is returned. 30 | **/ 31 | static u8 e1000_calculate_checksum(u8 *buffer, u32 length) 32 | { 33 | u32 i; 34 | u8 sum = 0; 35 | 36 | if (!buffer) 37 | return 0; 38 | 39 | for (i = 0; i < length; i++) 40 | sum += buffer[i]; 41 | 42 | return (u8)(0 - sum); 43 | } 44 | 45 | /** 46 | * e1000_mng_enable_host_if - Checks host interface is enabled 47 | * @hw: pointer to the HW structure 48 | * 49 | * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND 50 | * 51 | * This function checks whether the HOST IF is enabled for command operation 52 | * and also checks whether the previous command is completed. It busy waits 53 | * in case of previous command is not completed. 54 | **/ 55 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) 56 | { 57 | u32 hicr; 58 | u8 i; 59 | 60 | if (!hw->mac.arc_subsystem_valid) { 61 | e_dbg("ARC subsystem not valid.\n"); 62 | return -E1000_ERR_HOST_INTERFACE_COMMAND; 63 | } 64 | 65 | /* Check that the host interface is enabled. */ 66 | hicr = er32(HICR); 67 | if (!(hicr & E1000_HICR_EN)) { 68 | e_dbg("E1000_HOST_EN bit disabled.\n"); 69 | return -E1000_ERR_HOST_INTERFACE_COMMAND; 70 | } 71 | /* check the previous command is completed */ 72 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 73 | hicr = er32(HICR); 74 | if (!(hicr & E1000_HICR_C)) 75 | break; 76 | mdelay(1); 77 | } 78 | 79 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 80 | e_dbg("Previous command timeout failed .\n"); 81 | return -E1000_ERR_HOST_INTERFACE_COMMAND; 82 | } 83 | 84 | return 0; 85 | } 86 | 87 | /** 88 | * e1000e_check_mng_mode_generic - Generic check management mode 89 | * @hw: pointer to the HW structure 90 | * 91 | * Reads the firmware semaphore register and returns true (>0) if 92 | * manageability is enabled, else false (0). 93 | **/ 94 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw) 95 | { 96 | u32 fwsm = er32(FWSM); 97 | 98 | return (fwsm & E1000_FWSM_MODE_MASK) == 99 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 100 | } 101 | 102 | /** 103 | * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx 104 | * @hw: pointer to the HW structure 105 | * 106 | * Enables packet filtering on transmit packets if manageability is enabled 107 | * and host interface is enabled. 108 | **/ 109 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) 110 | { 111 | struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; 112 | u32 *buffer = (u32 *)&hw->mng_cookie; 113 | u32 offset; 114 | s32 ret_val, hdr_csum, csum; 115 | u8 i, len; 116 | 117 | hw->mac.tx_pkt_filtering = true; 118 | 119 | /* No manageability, no filtering */ 120 | if (!hw->mac.ops.check_mng_mode(hw)) { 121 | hw->mac.tx_pkt_filtering = false; 122 | return hw->mac.tx_pkt_filtering; 123 | } 124 | 125 | /* If we can't read from the host interface for whatever 126 | * reason, disable filtering. 127 | */ 128 | ret_val = e1000_mng_enable_host_if(hw); 129 | if (ret_val) { 130 | hw->mac.tx_pkt_filtering = false; 131 | return hw->mac.tx_pkt_filtering; 132 | } 133 | 134 | /* Read in the header. Length and offset are in dwords. */ 135 | len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; 136 | offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; 137 | for (i = 0; i < len; i++) 138 | *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, 139 | offset + i); 140 | hdr_csum = hdr->checksum; 141 | hdr->checksum = 0; 142 | csum = e1000_calculate_checksum((u8 *)hdr, 143 | E1000_MNG_DHCP_COOKIE_LENGTH); 144 | /* If either the checksums or signature don't match, then 145 | * the cookie area isn't considered valid, in which case we 146 | * take the safe route of assuming Tx filtering is enabled. 147 | */ 148 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { 149 | hw->mac.tx_pkt_filtering = true; 150 | return hw->mac.tx_pkt_filtering; 151 | } 152 | 153 | /* Cookie area is valid, make the final check for filtering. */ 154 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) 155 | hw->mac.tx_pkt_filtering = false; 156 | 157 | return hw->mac.tx_pkt_filtering; 158 | } 159 | 160 | /** 161 | * e1000_mng_write_cmd_header - Writes manageability command header 162 | * @hw: pointer to the HW structure 163 | * @hdr: pointer to the host interface command header 164 | * 165 | * Writes the command header after does the checksum calculation. 166 | **/ 167 | static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, 168 | struct e1000_host_mng_command_header *hdr) 169 | { 170 | u16 i, length = sizeof(struct e1000_host_mng_command_header); 171 | 172 | /* Write the whole command header structure with new checksum. */ 173 | 174 | hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); 175 | 176 | length >>= 2; 177 | /* Write the relevant command block into the ram area. */ 178 | for (i = 0; i < length; i++) { 179 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i)); 180 | e1e_flush(); 181 | } 182 | 183 | return 0; 184 | } 185 | 186 | /** 187 | * e1000_mng_host_if_write - Write to the manageability host interface 188 | * @hw: pointer to the HW structure 189 | * @buffer: pointer to the host interface buffer 190 | * @length: size of the buffer 191 | * @offset: location in the buffer to write to 192 | * @sum: sum of the data (not checksum) 193 | * 194 | * This function writes the buffer content at the offset given on the host if. 195 | * It also does alignment considerations to do the writes in most efficient 196 | * way. Also fills up the sum of the buffer in *buffer parameter. 197 | **/ 198 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, 199 | u16 length, u16 offset, u8 *sum) 200 | { 201 | u8 *tmp; 202 | u8 *bufptr = buffer; 203 | u32 data = 0; 204 | u16 remaining, i, j, prev_bytes; 205 | 206 | /* sum = only sum of the data and it is not checksum */ 207 | 208 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) 209 | return -E1000_ERR_PARAM; 210 | 211 | tmp = (u8 *)&data; 212 | prev_bytes = offset & 0x3; 213 | offset >>= 2; 214 | 215 | if (prev_bytes) { 216 | data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset); 217 | for (j = prev_bytes; j < sizeof(u32); j++) { 218 | *(tmp + j) = *bufptr++; 219 | *sum += *(tmp + j); 220 | } 221 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data); 222 | length -= j - prev_bytes; 223 | offset++; 224 | } 225 | 226 | remaining = length & 0x3; 227 | length -= remaining; 228 | 229 | /* Calculate length in DWORDs */ 230 | length >>= 2; 231 | 232 | /* The device driver writes the relevant command block into the 233 | * ram area. 234 | */ 235 | for (i = 0; i < length; i++) { 236 | for (j = 0; j < sizeof(u32); j++) { 237 | *(tmp + j) = *bufptr++; 238 | *sum += *(tmp + j); 239 | } 240 | 241 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); 242 | } 243 | if (remaining) { 244 | for (j = 0; j < sizeof(u32); j++) { 245 | if (j < remaining) 246 | *(tmp + j) = *bufptr++; 247 | else 248 | *(tmp + j) = 0; 249 | 250 | *sum += *(tmp + j); 251 | } 252 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); 253 | } 254 | 255 | return 0; 256 | } 257 | 258 | /** 259 | * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface 260 | * @hw: pointer to the HW structure 261 | * @buffer: pointer to the host interface 262 | * @length: size of the buffer 263 | * 264 | * Writes the DHCP information to the host interface. 265 | **/ 266 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) 267 | { 268 | struct e1000_host_mng_command_header hdr; 269 | s32 ret_val; 270 | u32 hicr; 271 | 272 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; 273 | hdr.command_length = length; 274 | hdr.reserved1 = 0; 275 | hdr.reserved2 = 0; 276 | hdr.checksum = 0; 277 | 278 | /* Enable the host interface */ 279 | ret_val = e1000_mng_enable_host_if(hw); 280 | if (ret_val) 281 | return ret_val; 282 | 283 | /* Populate the host interface with the contents of "buffer". */ 284 | ret_val = e1000_mng_host_if_write(hw, buffer, length, 285 | sizeof(hdr), &(hdr.checksum)); 286 | if (ret_val) 287 | return ret_val; 288 | 289 | /* Write the manageability command header */ 290 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); 291 | if (ret_val) 292 | return ret_val; 293 | 294 | /* Tell the ARC a new command is pending. */ 295 | hicr = er32(HICR); 296 | ew32(HICR, hicr | E1000_HICR_C); 297 | 298 | return 0; 299 | } 300 | 301 | /** 302 | * e1000e_enable_mng_pass_thru - Check if management passthrough is needed 303 | * @hw: pointer to the HW structure 304 | * 305 | * Verifies the hardware needs to leave interface enabled so that frames can 306 | * be directed to and from the management interface. 307 | **/ 308 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) 309 | { 310 | u32 manc; 311 | u32 fwsm, factps; 312 | 313 | manc = er32(MANC); 314 | 315 | if (!(manc & E1000_MANC_RCV_TCO_EN)) 316 | return false; 317 | 318 | if (hw->mac.has_fwsm) { 319 | fwsm = er32(FWSM); 320 | factps = er32(FACTPS); 321 | 322 | if (!(factps & E1000_FACTPS_MNGCG) && 323 | ((fwsm & E1000_FWSM_MODE_MASK) == 324 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) 325 | return true; 326 | } else if ((hw->mac.type == e1000_82574) || 327 | (hw->mac.type == e1000_82583)) { 328 | u16 data; 329 | s32 ret_val; 330 | 331 | factps = er32(FACTPS); 332 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 333 | if (ret_val) 334 | return false; 335 | 336 | if (!(factps & E1000_FACTPS_MNGCG) && 337 | ((data & E1000_NVM_INIT_CTRL2_MNGM) == 338 | (e1000_mng_mode_pt << 13))) 339 | return true; 340 | } else if ((manc & E1000_MANC_SMBUS_EN) && 341 | !(manc & E1000_MANC_ASF_EN)) { 342 | return true; 343 | } 344 | 345 | return false; 346 | } 347 | -------------------------------------------------------------------------------- /manage.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_MANAGE_H_ 23 | #define _E1000E_MANAGE_H_ 24 | 25 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 26 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 27 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 28 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 29 | 30 | enum e1000_mng_mode { 31 | e1000_mng_mode_none = 0, 32 | e1000_mng_mode_asf, 33 | e1000_mng_mode_pt, 34 | e1000_mng_mode_ipmi, 35 | e1000_mng_mode_host_if_only 36 | }; 37 | 38 | #define E1000_FACTPS_MNGCG 0x20000000 39 | 40 | #define E1000_FWSM_MODE_MASK 0xE 41 | #define E1000_FWSM_MODE_SHIFT 1 42 | 43 | #define E1000_MNG_IAMT_MODE 0x3 44 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 45 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 46 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 47 | #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 48 | #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 49 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 50 | 51 | #define E1000_VFTA_ENTRY_SHIFT 5 52 | #define E1000_VFTA_ENTRY_MASK 0x7F 53 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 54 | 55 | #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 56 | /* Driver sets this bit when done to put command in RAM */ 57 | #define E1000_HICR_C 0x02 58 | #define E1000_HICR_SV 0x04 /* Status Validity */ 59 | #define E1000_HICR_FW_RESET_ENABLE 0x40 60 | #define E1000_HICR_FW_RESET 0x80 61 | 62 | /* Intel(R) Active Management Technology signature */ 63 | #define E1000_IAMT_SIGNATURE 0x544D4149 64 | 65 | #endif 66 | -------------------------------------------------------------------------------- /nvm.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #include "e1000.h" 23 | 24 | /** 25 | * e1000_raise_eec_clk - Raise EEPROM clock 26 | * @hw: pointer to the HW structure 27 | * @eecd: pointer to the EEPROM 28 | * 29 | * Enable/Raise the EEPROM clock bit. 30 | **/ 31 | static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 32 | { 33 | *eecd = *eecd | E1000_EECD_SK; 34 | ew32(EECD, *eecd); 35 | e1e_flush(); 36 | udelay(hw->nvm.delay_usec); 37 | } 38 | 39 | /** 40 | * e1000_lower_eec_clk - Lower EEPROM clock 41 | * @hw: pointer to the HW structure 42 | * @eecd: pointer to the EEPROM 43 | * 44 | * Clear/Lower the EEPROM clock bit. 45 | **/ 46 | static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 47 | { 48 | *eecd = *eecd & ~E1000_EECD_SK; 49 | ew32(EECD, *eecd); 50 | e1e_flush(); 51 | udelay(hw->nvm.delay_usec); 52 | } 53 | 54 | /** 55 | * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 56 | * @hw: pointer to the HW structure 57 | * @data: data to send to the EEPROM 58 | * @count: number of bits to shift out 59 | * 60 | * We need to shift 'count' bits out to the EEPROM. So, the value in the 61 | * "data" parameter will be shifted out to the EEPROM one bit at a time. 62 | * In order to do this, "data" must be broken down into bits. 63 | **/ 64 | static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 65 | { 66 | struct e1000_nvm_info *nvm = &hw->nvm; 67 | u32 eecd = er32(EECD); 68 | u32 mask; 69 | 70 | mask = 0x01 << (count - 1); 71 | if (nvm->type == e1000_nvm_eeprom_spi) 72 | eecd |= E1000_EECD_DO; 73 | 74 | do { 75 | eecd &= ~E1000_EECD_DI; 76 | 77 | if (data & mask) 78 | eecd |= E1000_EECD_DI; 79 | 80 | ew32(EECD, eecd); 81 | e1e_flush(); 82 | 83 | udelay(nvm->delay_usec); 84 | 85 | e1000_raise_eec_clk(hw, &eecd); 86 | e1000_lower_eec_clk(hw, &eecd); 87 | 88 | mask >>= 1; 89 | } while (mask); 90 | 91 | eecd &= ~E1000_EECD_DI; 92 | ew32(EECD, eecd); 93 | } 94 | 95 | /** 96 | * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 97 | * @hw: pointer to the HW structure 98 | * @count: number of bits to shift in 99 | * 100 | * In order to read a register from the EEPROM, we need to shift 'count' bits 101 | * in from the EEPROM. Bits are "shifted in" by raising the clock input to 102 | * the EEPROM (setting the SK bit), and then reading the value of the data out 103 | * "DO" bit. During this "shifting in" process the data in "DI" bit should 104 | * always be clear. 105 | **/ 106 | static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 107 | { 108 | u32 eecd; 109 | u32 i; 110 | u16 data; 111 | 112 | eecd = er32(EECD); 113 | 114 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 115 | data = 0; 116 | 117 | for (i = 0; i < count; i++) { 118 | data <<= 1; 119 | e1000_raise_eec_clk(hw, &eecd); 120 | 121 | eecd = er32(EECD); 122 | 123 | eecd &= ~E1000_EECD_DI; 124 | if (eecd & E1000_EECD_DO) 125 | data |= 1; 126 | 127 | e1000_lower_eec_clk(hw, &eecd); 128 | } 129 | 130 | return data; 131 | } 132 | 133 | /** 134 | * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion 135 | * @hw: pointer to the HW structure 136 | * @ee_reg: EEPROM flag for polling 137 | * 138 | * Polls the EEPROM status bit for either read or write completion based 139 | * upon the value of 'ee_reg'. 140 | **/ 141 | s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 142 | { 143 | u32 attempts = 100000; 144 | u32 i, reg = 0; 145 | 146 | for (i = 0; i < attempts; i++) { 147 | if (ee_reg == E1000_NVM_POLL_READ) 148 | reg = er32(EERD); 149 | else 150 | reg = er32(EEWR); 151 | 152 | if (reg & E1000_NVM_RW_REG_DONE) 153 | return 0; 154 | 155 | udelay(5); 156 | } 157 | 158 | return -E1000_ERR_NVM; 159 | } 160 | 161 | /** 162 | * e1000e_acquire_nvm - Generic request for access to EEPROM 163 | * @hw: pointer to the HW structure 164 | * 165 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. 166 | * Return successful if access grant bit set, else clear the request for 167 | * EEPROM access and return -E1000_ERR_NVM (-1). 168 | **/ 169 | s32 e1000e_acquire_nvm(struct e1000_hw *hw) 170 | { 171 | u32 eecd = er32(EECD); 172 | s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 173 | 174 | ew32(EECD, eecd | E1000_EECD_REQ); 175 | eecd = er32(EECD); 176 | 177 | while (timeout) { 178 | if (eecd & E1000_EECD_GNT) 179 | break; 180 | udelay(5); 181 | eecd = er32(EECD); 182 | timeout--; 183 | } 184 | 185 | if (!timeout) { 186 | eecd &= ~E1000_EECD_REQ; 187 | ew32(EECD, eecd); 188 | e_dbg("Could not acquire NVM grant\n"); 189 | return -E1000_ERR_NVM; 190 | } 191 | 192 | return 0; 193 | } 194 | 195 | /** 196 | * e1000_standby_nvm - Return EEPROM to standby state 197 | * @hw: pointer to the HW structure 198 | * 199 | * Return the EEPROM to a standby state. 200 | **/ 201 | static void e1000_standby_nvm(struct e1000_hw *hw) 202 | { 203 | struct e1000_nvm_info *nvm = &hw->nvm; 204 | u32 eecd = er32(EECD); 205 | 206 | if (nvm->type == e1000_nvm_eeprom_spi) { 207 | /* Toggle CS to flush commands */ 208 | eecd |= E1000_EECD_CS; 209 | ew32(EECD, eecd); 210 | e1e_flush(); 211 | udelay(nvm->delay_usec); 212 | eecd &= ~E1000_EECD_CS; 213 | ew32(EECD, eecd); 214 | e1e_flush(); 215 | udelay(nvm->delay_usec); 216 | } 217 | } 218 | 219 | /** 220 | * e1000_stop_nvm - Terminate EEPROM command 221 | * @hw: pointer to the HW structure 222 | * 223 | * Terminates the current command by inverting the EEPROM's chip select pin. 224 | **/ 225 | static void e1000_stop_nvm(struct e1000_hw *hw) 226 | { 227 | u32 eecd; 228 | 229 | eecd = er32(EECD); 230 | if (hw->nvm.type == e1000_nvm_eeprom_spi) { 231 | /* Pull CS high */ 232 | eecd |= E1000_EECD_CS; 233 | e1000_lower_eec_clk(hw, &eecd); 234 | } 235 | } 236 | 237 | /** 238 | * e1000e_release_nvm - Release exclusive access to EEPROM 239 | * @hw: pointer to the HW structure 240 | * 241 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. 242 | **/ 243 | void e1000e_release_nvm(struct e1000_hw *hw) 244 | { 245 | u32 eecd; 246 | 247 | e1000_stop_nvm(hw); 248 | 249 | eecd = er32(EECD); 250 | eecd &= ~E1000_EECD_REQ; 251 | ew32(EECD, eecd); 252 | } 253 | 254 | /** 255 | * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 256 | * @hw: pointer to the HW structure 257 | * 258 | * Setups the EEPROM for reading and writing. 259 | **/ 260 | static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 261 | { 262 | struct e1000_nvm_info *nvm = &hw->nvm; 263 | u32 eecd = er32(EECD); 264 | u8 spi_stat_reg; 265 | 266 | if (nvm->type == e1000_nvm_eeprom_spi) { 267 | u16 timeout = NVM_MAX_RETRY_SPI; 268 | 269 | /* Clear SK and CS */ 270 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 271 | ew32(EECD, eecd); 272 | e1e_flush(); 273 | udelay(1); 274 | 275 | /* Read "Status Register" repeatedly until the LSB is cleared. 276 | * The EEPROM will signal that the command has been completed 277 | * by clearing bit 0 of the internal status register. If it's 278 | * not cleared within 'timeout', then error out. 279 | */ 280 | while (timeout) { 281 | e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 282 | hw->nvm.opcode_bits); 283 | spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 284 | if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 285 | break; 286 | 287 | udelay(5); 288 | e1000_standby_nvm(hw); 289 | timeout--; 290 | } 291 | 292 | if (!timeout) { 293 | e_dbg("SPI NVM Status error\n"); 294 | return -E1000_ERR_NVM; 295 | } 296 | } 297 | 298 | return 0; 299 | } 300 | 301 | /** 302 | * e1000e_read_nvm_eerd - Reads EEPROM using EERD register 303 | * @hw: pointer to the HW structure 304 | * @offset: offset of word in the EEPROM to read 305 | * @words: number of words to read 306 | * @data: word read from the EEPROM 307 | * 308 | * Reads a 16 bit word from the EEPROM using the EERD register. 309 | **/ 310 | s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 311 | { 312 | struct e1000_nvm_info *nvm = &hw->nvm; 313 | u32 i, eerd = 0; 314 | s32 ret_val = 0; 315 | 316 | /* A check for invalid values: offset too large, too many words, 317 | * too many words for the offset, and not enough words. 318 | */ 319 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 320 | (words == 0)) { 321 | e_dbg("nvm parameter(s) out of bounds\n"); 322 | return -E1000_ERR_NVM; 323 | } 324 | 325 | for (i = 0; i < words; i++) { 326 | eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + 327 | E1000_NVM_RW_REG_START; 328 | 329 | ew32(EERD, eerd); 330 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 331 | if (ret_val) 332 | break; 333 | 334 | data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); 335 | } 336 | 337 | if (ret_val) 338 | e_dbg("NVM read error: %d\n", ret_val); 339 | 340 | return ret_val; 341 | } 342 | 343 | /** 344 | * e1000e_write_nvm_spi - Write to EEPROM using SPI 345 | * @hw: pointer to the HW structure 346 | * @offset: offset within the EEPROM to be written to 347 | * @words: number of words to write 348 | * @data: 16 bit word(s) to be written to the EEPROM 349 | * 350 | * Writes data to EEPROM at offset using SPI interface. 351 | * 352 | * If e1000e_update_nvm_checksum is not called after this function , the 353 | * EEPROM will most likely contain an invalid checksum. 354 | **/ 355 | s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 356 | { 357 | struct e1000_nvm_info *nvm = &hw->nvm; 358 | s32 ret_val = -E1000_ERR_NVM; 359 | u16 widx = 0; 360 | 361 | /* A check for invalid values: offset too large, too many words, 362 | * and not enough words. 363 | */ 364 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 365 | (words == 0)) { 366 | e_dbg("nvm parameter(s) out of bounds\n"); 367 | return -E1000_ERR_NVM; 368 | } 369 | 370 | while (widx < words) { 371 | u8 write_opcode = NVM_WRITE_OPCODE_SPI; 372 | 373 | ret_val = nvm->ops.acquire(hw); 374 | if (ret_val) 375 | return ret_val; 376 | 377 | ret_val = e1000_ready_nvm_eeprom(hw); 378 | if (ret_val) { 379 | nvm->ops.release(hw); 380 | return ret_val; 381 | } 382 | 383 | e1000_standby_nvm(hw); 384 | 385 | /* Send the WRITE ENABLE command (8 bit opcode) */ 386 | e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 387 | nvm->opcode_bits); 388 | 389 | e1000_standby_nvm(hw); 390 | 391 | /* Some SPI eeproms use the 8th address bit embedded in the 392 | * opcode 393 | */ 394 | if ((nvm->address_bits == 8) && (offset >= 128)) 395 | write_opcode |= NVM_A8_OPCODE_SPI; 396 | 397 | /* Send the Write command (8-bit opcode + addr) */ 398 | e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 399 | e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 400 | nvm->address_bits); 401 | 402 | /* Loop to allow for up to whole page write of eeprom */ 403 | while (widx < words) { 404 | u16 word_out = data[widx]; 405 | word_out = (word_out >> 8) | (word_out << 8); 406 | e1000_shift_out_eec_bits(hw, word_out, 16); 407 | widx++; 408 | 409 | if ((((offset + widx) * 2) % nvm->page_size) == 0) { 410 | e1000_standby_nvm(hw); 411 | break; 412 | } 413 | } 414 | usleep_range(10000, 20000); 415 | nvm->ops.release(hw); 416 | } 417 | 418 | return ret_val; 419 | } 420 | 421 | /** 422 | * e1000_read_pba_string_generic - Read device part number 423 | * @hw: pointer to the HW structure 424 | * @pba_num: pointer to device part number 425 | * @pba_num_size: size of part number buffer 426 | * 427 | * Reads the product board assembly (PBA) number from the EEPROM and stores 428 | * the value in pba_num. 429 | **/ 430 | s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 431 | u32 pba_num_size) 432 | { 433 | s32 ret_val; 434 | u16 nvm_data; 435 | u16 pba_ptr; 436 | u16 offset; 437 | u16 length; 438 | 439 | if (pba_num == NULL) { 440 | e_dbg("PBA string buffer was null\n"); 441 | return -E1000_ERR_INVALID_ARGUMENT; 442 | } 443 | 444 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 445 | if (ret_val) { 446 | e_dbg("NVM Read Error\n"); 447 | return ret_val; 448 | } 449 | 450 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 451 | if (ret_val) { 452 | e_dbg("NVM Read Error\n"); 453 | return ret_val; 454 | } 455 | 456 | /* if nvm_data is not ptr guard the PBA must be in legacy format which 457 | * means pba_ptr is actually our second data word for the PBA number 458 | * and we can decode it into an ascii string 459 | */ 460 | if (nvm_data != NVM_PBA_PTR_GUARD) { 461 | e_dbg("NVM PBA number is not stored as string\n"); 462 | 463 | /* make sure callers buffer is big enough to store the PBA */ 464 | if (pba_num_size < E1000_PBANUM_LENGTH) { 465 | e_dbg("PBA string buffer too small\n"); 466 | return E1000_ERR_NO_SPACE; 467 | } 468 | 469 | /* extract hex string from data and pba_ptr */ 470 | pba_num[0] = (nvm_data >> 12) & 0xF; 471 | pba_num[1] = (nvm_data >> 8) & 0xF; 472 | pba_num[2] = (nvm_data >> 4) & 0xF; 473 | pba_num[3] = nvm_data & 0xF; 474 | pba_num[4] = (pba_ptr >> 12) & 0xF; 475 | pba_num[5] = (pba_ptr >> 8) & 0xF; 476 | pba_num[6] = '-'; 477 | pba_num[7] = 0; 478 | pba_num[8] = (pba_ptr >> 4) & 0xF; 479 | pba_num[9] = pba_ptr & 0xF; 480 | 481 | /* put a null character on the end of our string */ 482 | pba_num[10] = '\0'; 483 | 484 | /* switch all the data but the '-' to hex char */ 485 | for (offset = 0; offset < 10; offset++) { 486 | if (pba_num[offset] < 0xA) 487 | pba_num[offset] += '0'; 488 | else if (pba_num[offset] < 0x10) 489 | pba_num[offset] += 'A' - 0xA; 490 | } 491 | 492 | return 0; 493 | } 494 | 495 | ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); 496 | if (ret_val) { 497 | e_dbg("NVM Read Error\n"); 498 | return ret_val; 499 | } 500 | 501 | if (length == 0xFFFF || length == 0) { 502 | e_dbg("NVM PBA number section invalid length\n"); 503 | return -E1000_ERR_NVM_PBA_SECTION; 504 | } 505 | /* check if pba_num buffer is big enough */ 506 | if (pba_num_size < (((u32)length * 2) - 1)) { 507 | e_dbg("PBA string buffer too small\n"); 508 | return -E1000_ERR_NO_SPACE; 509 | } 510 | 511 | /* trim pba length from start of string */ 512 | pba_ptr++; 513 | length--; 514 | 515 | for (offset = 0; offset < length; offset++) { 516 | ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); 517 | if (ret_val) { 518 | e_dbg("NVM Read Error\n"); 519 | return ret_val; 520 | } 521 | pba_num[offset * 2] = (u8)(nvm_data >> 8); 522 | pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 523 | } 524 | pba_num[offset * 2] = '\0'; 525 | 526 | return 0; 527 | } 528 | 529 | /** 530 | * e1000_read_mac_addr_generic - Read device MAC address 531 | * @hw: pointer to the HW structure 532 | * 533 | * Reads the device MAC address from the EEPROM and stores the value. 534 | * Since devices with two ports use the same EEPROM, we increment the 535 | * last bit in the MAC address for the second port. 536 | **/ 537 | s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 538 | { 539 | u32 rar_high; 540 | u32 rar_low; 541 | u16 i; 542 | 543 | rar_high = er32(RAH(0)); 544 | rar_low = er32(RAL(0)); 545 | 546 | for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 547 | hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8)); 548 | 549 | for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 550 | hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8)); 551 | 552 | for (i = 0; i < ETH_ALEN; i++) 553 | hw->mac.addr[i] = hw->mac.perm_addr[i]; 554 | 555 | return 0; 556 | } 557 | 558 | /** 559 | * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum 560 | * @hw: pointer to the HW structure 561 | * 562 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 563 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. 564 | **/ 565 | s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) 566 | { 567 | s32 ret_val; 568 | u16 checksum = 0; 569 | u16 i, nvm_data; 570 | 571 | for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 572 | ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 573 | if (ret_val) { 574 | e_dbg("NVM Read Error\n"); 575 | return ret_val; 576 | } 577 | checksum += nvm_data; 578 | } 579 | 580 | if (checksum != (u16)NVM_SUM) { 581 | e_dbg("NVM Checksum Invalid\n"); 582 | return -E1000_ERR_NVM; 583 | } 584 | 585 | return 0; 586 | } 587 | 588 | /** 589 | * e1000e_update_nvm_checksum_generic - Update EEPROM checksum 590 | * @hw: pointer to the HW structure 591 | * 592 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM 593 | * up to the checksum. Then calculates the EEPROM checksum and writes the 594 | * value to the EEPROM. 595 | **/ 596 | s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) 597 | { 598 | s32 ret_val; 599 | u16 checksum = 0; 600 | u16 i, nvm_data; 601 | 602 | for (i = 0; i < NVM_CHECKSUM_REG; i++) { 603 | ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 604 | if (ret_val) { 605 | e_dbg("NVM Read Error while updating checksum.\n"); 606 | return ret_val; 607 | } 608 | checksum += nvm_data; 609 | } 610 | checksum = (u16)NVM_SUM - checksum; 611 | ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 612 | if (ret_val) 613 | e_dbg("NVM Write Error while updating checksum.\n"); 614 | 615 | return ret_val; 616 | } 617 | 618 | /** 619 | * e1000e_reload_nvm_generic - Reloads EEPROM 620 | * @hw: pointer to the HW structure 621 | * 622 | * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 623 | * extended control register. 624 | **/ 625 | void e1000e_reload_nvm_generic(struct e1000_hw *hw) 626 | { 627 | u32 ctrl_ext; 628 | 629 | usleep_range(10, 20); 630 | ctrl_ext = er32(CTRL_EXT); 631 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; 632 | ew32(CTRL_EXT, ctrl_ext); 633 | e1e_flush(); 634 | } 635 | -------------------------------------------------------------------------------- /nvm.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_NVM_H_ 23 | #define _E1000E_NVM_H_ 24 | 25 | s32 e1000e_acquire_nvm(struct e1000_hw *hw); 26 | 27 | s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); 28 | s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); 29 | s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 30 | u32 pba_num_size); 31 | s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 32 | s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); 33 | s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); 34 | s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 35 | s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); 36 | void e1000e_release_nvm(struct e1000_hw *hw); 37 | 38 | #define E1000_STM_OPCODE 0xDB00 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /param.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifdef __APPLE__ 23 | #else 24 | #include 25 | #include 26 | #include 27 | #endif 28 | 29 | #include "e1000.h" 30 | 31 | /* This is the only thing that needs to be changed to adjust the 32 | * maximum number of ports that the driver can manage. 33 | */ 34 | #define E1000_MAX_NIC 32 35 | 36 | #define OPTION_UNSET -1 37 | #define OPTION_DISABLED 0 38 | #define OPTION_ENABLED 1 39 | 40 | #define COPYBREAK_DEFAULT 256 41 | unsigned int copybreak = COPYBREAK_DEFAULT; 42 | #ifndef __APPLE__ 43 | module_param(copybreak, uint, 0644); 44 | MODULE_PARM_DESC(copybreak, 45 | "Maximum size of packet that is copied to a new buffer on receive"); 46 | #endif 47 | /* All parameters are treated the same, as an integer array of values. 48 | * This macro just reduces the need to repeat the same declaration code 49 | * over and over (plus this helps to avoid typo bugs). 50 | */ 51 | #define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 52 | #ifndef module_param_array 53 | /* Module Parameters are always initialized to -1, so that the driver 54 | * can tell the difference between no user specified value or the 55 | * user asking for the default value. 56 | * The true default values are loaded in when e1000e_check_options is called. 57 | * 58 | * This is a GCC extension to ANSI C. 59 | * See the item "Labeled Elements in Initializers" in the section 60 | * "Extensions to the C Language Family" of the GCC documentation. 61 | */ 62 | #define E1000_PARAM(X, desc) \ 63 | static const int X[E1000_MAX_NIC+1] __devinitconst = E1000_PARAM_INIT; \ 64 | static unsigned int num_##X; \ 65 | MODULE_PARM(X, "1-" __MODULE_STRING(E1000_MAX_NIC) "i"); \ 66 | MODULE_PARM_DESC(X, desc); 67 | #elif defined(HAVE_CONFIG_HOTPLUG) 68 | #define E1000_PARAM(X, desc) \ 69 | static int X[E1000_MAX_NIC+1] __devinitdata \ 70 | = E1000_PARAM_INIT; \ 71 | static unsigned int num_##X; \ 72 | module_param_array_named(X, X, int, &num_##X, 0); \ 73 | MODULE_PARM_DESC(X, desc); 74 | #else 75 | #define E1000_PARAM(X, desc) \ 76 | static int X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 77 | static unsigned int num_##X; \ 78 | module_param_array_named(X, X, int, &num_##X, 0); \ 79 | MODULE_PARM_DESC(X, desc); 80 | #endif 81 | #ifdef __APPLE__ 82 | #undef E1000_PARAM 83 | #define E1000_PARAM(X, desc) static const int X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 84 | static unsigned int num_##X; 85 | #endif 86 | 87 | /* Transmit Interrupt Delay in units of 1.024 microseconds 88 | * Tx interrupt delay needs to typically be set to something non-zero 89 | * 90 | * Valid Range: 0-65535 91 | */ 92 | E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay"); 93 | #define DEFAULT_TIDV 8 94 | #define MAX_TXDELAY 0xFFFF 95 | #define MIN_TXDELAY 0 96 | 97 | /* Transmit Absolute Interrupt Delay in units of 1.024 microseconds 98 | * 99 | * Valid Range: 0-65535 100 | */ 101 | E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay"); 102 | #define DEFAULT_TADV 32 103 | #define MAX_TXABSDELAY 0xFFFF 104 | #define MIN_TXABSDELAY 0 105 | 106 | /* Receive Interrupt Delay in units of 1.024 microseconds 107 | * hardware will likely hang if you set this to anything but zero. 108 | * 109 | * Valid Range: 0-65535 110 | */ 111 | E1000_PARAM(RxIntDelay, "Receive Interrupt Delay"); 112 | #define MAX_RXDELAY 0xFFFF 113 | #define MIN_RXDELAY 0 114 | 115 | /* Receive Absolute Interrupt Delay in units of 1.024 microseconds 116 | * 117 | * Valid Range: 0-65535 118 | */ 119 | E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay"); 120 | #define MAX_RXABSDELAY 0xFFFF 121 | #define MIN_RXABSDELAY 0 122 | 123 | /* Interrupt Throttle Rate (interrupts/sec) 124 | * 125 | * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative 126 | */ 127 | E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); 128 | #define DEFAULT_ITR 3 129 | #define MAX_ITR 100000 130 | #define MIN_ITR 100 131 | 132 | /* IntMode (Interrupt Mode) 133 | * 134 | * Valid Range: varies depending on kernel configuration & hardware support 135 | * 136 | * legacy=0, MSI=1, MSI-X=2 137 | * 138 | * When MSI/MSI-X support is enabled in kernel- 139 | * Default Value: 2 (MSI-X) when supported by hardware, 1 (MSI) otherwise 140 | * When MSI/MSI-X support is not enabled in kernel- 141 | * Default Value: 0 (legacy) 142 | * 143 | * When a mode is specified that is not allowed/supported, it will be 144 | * demoted to the most advanced interrupt mode available. 145 | */ 146 | E1000_PARAM(IntMode, "Interrupt Mode"); 147 | #define MAX_INTMODE 2 148 | #define MIN_INTMODE 0 149 | 150 | /* Enable Smart Power Down of the PHY 151 | * 152 | * Valid Range: 0, 1 153 | * 154 | * Default Value: 0 (disabled) 155 | */ 156 | E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); 157 | 158 | /* Enable Kumeran Lock Loss workaround 159 | * 160 | * Valid Range: 0, 1 161 | * 162 | * Default Value: 1 (enabled) 163 | */ 164 | E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); 165 | 166 | /* Enable CRC Stripping 167 | * 168 | * Valid Range: 0, 1 169 | * 170 | * Default Value: 1 (enabled) 171 | */ 172 | E1000_PARAM(CrcStripping, 173 | "Enable CRC Stripping, disable if your BMC needs the CRC"); 174 | 175 | /* Enable/disable EEE (a.k.a. IEEE802.3az) 176 | * 177 | * Valid Range: 0, 1 178 | * 179 | * Default Value: 1 180 | */ 181 | E1000_PARAM(EEE, "Enable/disable on parts that support the feature"); 182 | 183 | /* Enable node specific allocation of all data structures, typically 184 | * specific to routing setups, not generally useful. 185 | * 186 | * Depends on: NUMA configuration 187 | * 188 | * Valid Range: -1, 0-32768 189 | * 190 | * Default Value: -1 (disabled, default to kernel choice of node) 191 | */ 192 | E1000_PARAM(Node, "[ROUTING] Node to allocate memory on, default -1"); 193 | 194 | struct e1000_option { 195 | enum { enable_option, range_option, list_option } type; 196 | const char *name; 197 | const char *err; 198 | int def; 199 | union { 200 | /* range_option info */ 201 | struct { 202 | int min; 203 | int max; 204 | } r; 205 | /* list_option info */ 206 | struct { 207 | int nr; 208 | struct e1000_opt_list { 209 | int i; 210 | char *str; 211 | } *p; 212 | } l; 213 | } arg; 214 | }; 215 | 216 | #ifdef HAVE_CONFIG_HOTPLUG 217 | static int __devinit e1000_validate_option(unsigned int *value, 218 | const struct e1000_option *opt, 219 | struct e1000_adapter *adapter) 220 | #else 221 | static int e1000_validate_option(unsigned int *value, 222 | const struct e1000_option *opt, 223 | struct e1000_adapter *adapter) 224 | #endif 225 | { 226 | if (*value == OPTION_UNSET) { 227 | *value = opt->def; 228 | return 0; 229 | } 230 | 231 | switch (opt->type) { 232 | case enable_option: 233 | switch (*value) { 234 | case OPTION_ENABLED: 235 | dev_info(pci_dev_to_dev(adapter->pdev), "%s Enabled\n", 236 | opt->name); 237 | return 0; 238 | case OPTION_DISABLED: 239 | dev_info(pci_dev_to_dev(adapter->pdev), "%s Disabled\n", 240 | opt->name); 241 | return 0; 242 | } 243 | break; 244 | case range_option: 245 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 246 | dev_info(pci_dev_to_dev(adapter->pdev), 247 | "%s set to %i\n", opt->name, *value); 248 | return 0; 249 | } 250 | break; 251 | case list_option: { 252 | int i; 253 | struct e1000_opt_list *ent; 254 | 255 | for (i = 0; i < opt->arg.l.nr; i++) { 256 | ent = &opt->arg.l.p[i]; 257 | if (*value == ent->i) { 258 | if (ent->str[0] != '\0') 259 | dev_info(pci_dev_to_dev(adapter->pdev), "%s\n", 260 | ent->str); 261 | return 0; 262 | } 263 | } 264 | } 265 | break; 266 | default: 267 | BUG(); 268 | } 269 | 270 | dev_info(pci_dev_to_dev(adapter->pdev), 271 | "Invalid %s value specified (%i) %s\n", opt->name, *value, 272 | opt->err); 273 | *value = opt->def; 274 | return -1; 275 | } 276 | 277 | /** 278 | * e1000e_check_options - Range Checking for Command Line Parameters 279 | * @adapter: board private structure 280 | * 281 | * This routine checks all command line parameters for valid user 282 | * input. If an invalid value is given, or if no user specified 283 | * value exists, a default value is used. The final value is stored 284 | * in a variable in the adapter structure. 285 | **/ 286 | #ifdef HAVE_CONFIG_HOTPLUG 287 | void __devinit e1000e_check_options(struct e1000_adapter *adapter) 288 | #else 289 | void e1000e_check_options(struct e1000_adapter *adapter) 290 | #endif 291 | { 292 | struct e1000_hw *hw = &adapter->hw; 293 | int bd = adapter->bd_number; 294 | 295 | if (bd >= E1000_MAX_NIC) { 296 | dev_notice(pci_dev_to_dev(adapter->pdev), 297 | "Warning: no configuration for board #%i\n", bd); 298 | dev_notice(pci_dev_to_dev(adapter->pdev), 299 | "Using defaults for all values\n"); 300 | } 301 | 302 | /* Transmit Interrupt Delay */ 303 | { 304 | static const struct e1000_option opt = { 305 | .type = range_option, 306 | .name = "Transmit Interrupt Delay", 307 | .err = "using default of " 308 | __MODULE_STRING(DEFAULT_TIDV), 309 | .def = DEFAULT_TIDV, 310 | .arg = { .r = { .min = MIN_TXDELAY, 311 | .max = MAX_TXDELAY } } 312 | }; 313 | 314 | if (num_TxIntDelay > bd) { 315 | adapter->tx_int_delay = TxIntDelay[bd]; 316 | e1000_validate_option(&adapter->tx_int_delay, &opt, 317 | adapter); 318 | } else { 319 | adapter->tx_int_delay = opt.def; 320 | } 321 | } 322 | /* Transmit Absolute Interrupt Delay */ 323 | { 324 | static const struct e1000_option opt = { 325 | .type = range_option, 326 | .name = "Transmit Absolute Interrupt Delay", 327 | .err = "using default of " 328 | __MODULE_STRING(DEFAULT_TADV), 329 | .def = DEFAULT_TADV, 330 | .arg = { .r = { .min = MIN_TXABSDELAY, 331 | .max = MAX_TXABSDELAY } } 332 | }; 333 | 334 | if (num_TxAbsIntDelay > bd) { 335 | adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 336 | e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 337 | adapter); 338 | } else { 339 | adapter->tx_abs_int_delay = opt.def; 340 | } 341 | } 342 | /* Receive Interrupt Delay */ 343 | { 344 | static struct e1000_option opt = { 345 | .type = range_option, 346 | .name = "Receive Interrupt Delay", 347 | .err = "using default of " 348 | __MODULE_STRING(DEFAULT_RDTR), 349 | .def = DEFAULT_RDTR, 350 | .arg = { .r = { .min = MIN_RXDELAY, 351 | .max = MAX_RXDELAY } } 352 | }; 353 | 354 | if (num_RxIntDelay > bd) { 355 | adapter->rx_int_delay = RxIntDelay[bd]; 356 | e1000_validate_option(&adapter->rx_int_delay, &opt, 357 | adapter); 358 | } else { 359 | adapter->rx_int_delay = opt.def; 360 | } 361 | } 362 | /* Receive Absolute Interrupt Delay */ 363 | { 364 | static const struct e1000_option opt = { 365 | .type = range_option, 366 | .name = "Receive Absolute Interrupt Delay", 367 | .err = "using default of " 368 | __MODULE_STRING(DEFAULT_RADV), 369 | .def = DEFAULT_RADV, 370 | .arg = { .r = { .min = MIN_RXABSDELAY, 371 | .max = MAX_RXABSDELAY } } 372 | }; 373 | 374 | if (num_RxAbsIntDelay > bd) { 375 | adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 376 | e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 377 | adapter); 378 | } else { 379 | adapter->rx_abs_int_delay = opt.def; 380 | } 381 | } 382 | /* Interrupt Throttling Rate */ 383 | { 384 | static const struct e1000_option opt = { 385 | .type = range_option, 386 | .name = "Interrupt Throttling Rate (ints/sec)", 387 | .err = "using default of " 388 | __MODULE_STRING(DEFAULT_ITR), 389 | .def = DEFAULT_ITR, 390 | .arg = { .r = { .min = MIN_ITR, 391 | .max = MAX_ITR } } 392 | }; 393 | 394 | if (num_InterruptThrottleRate > bd) { 395 | adapter->itr = InterruptThrottleRate[bd]; 396 | 397 | /* Make sure a message is printed for non-special 398 | * values. And in case of an invalid option, display 399 | * warning, use default and go through itr/itr_setting 400 | * adjustment logic below 401 | */ 402 | if ((adapter->itr > 4) && 403 | e1000_validate_option(&adapter->itr, &opt, adapter)) 404 | adapter->itr = opt.def; 405 | } else { 406 | /* If no option specified, use default value and go 407 | * through the logic below to adjust itr/itr_setting 408 | */ 409 | adapter->itr = opt.def; 410 | 411 | /* Make sure a message is printed for non-special 412 | * default values 413 | */ 414 | if (adapter->itr > 4) 415 | dev_info(pci_dev_to_dev(adapter->pdev), 416 | "%s set to default %d\n", opt.name, 417 | adapter->itr); 418 | } 419 | 420 | adapter->itr_setting = adapter->itr; 421 | switch (adapter->itr) { 422 | case 0: 423 | dev_info(pci_dev_to_dev(adapter->pdev), 424 | "%s turned off\n", opt.name); 425 | break; 426 | case 1: 427 | dev_info(pci_dev_to_dev(adapter->pdev), 428 | "%s set to dynamic mode\n", opt.name); 429 | adapter->itr = 20000; 430 | break; 431 | case 2: 432 | dev_info(pci_dev_to_dev(adapter->pdev), 433 | "%s Invalid mode - setting default\n", 434 | opt.name); 435 | adapter->itr_setting = opt.def; 436 | /* fall-through */ 437 | case 3: 438 | dev_info(pci_dev_to_dev(adapter->pdev), 439 | "%s set to dynamic conservative mode\n", 440 | opt.name); 441 | adapter->itr = 20000; 442 | break; 443 | case 4: 444 | dev_info(pci_dev_to_dev(adapter->pdev), 445 | "%s set to simplified (2000-8000 ints) mode\n", 446 | opt.name); 447 | break; 448 | default: 449 | /* Save the setting, because the dynamic bits 450 | * change itr. 451 | * 452 | * Clear the lower two bits because 453 | * they are used as control. 454 | */ 455 | adapter->itr_setting &= ~3; 456 | break; 457 | } 458 | } 459 | /* Interrupt Mode */ 460 | { 461 | static struct e1000_option opt = { 462 | .type = range_option, 463 | .name = "Interrupt Mode", 464 | #ifndef CONFIG_PCI_MSI 465 | .err = "defaulting to 0 (legacy)", 466 | .def = E1000E_INT_MODE_LEGACY, 467 | .arg = { .r = { .min = 0, 468 | .max = 0 } } 469 | #endif 470 | }; 471 | 472 | #ifdef CONFIG_PCI_MSI 473 | if (adapter->flags & FLAG_HAS_MSIX) { 474 | opt.err = kstrdup("defaulting to 2 (MSI-X)", 475 | GFP_KERNEL); 476 | opt.def = E1000E_INT_MODE_MSIX; 477 | opt.arg.r.max = E1000E_INT_MODE_MSIX; 478 | } else { 479 | opt.err = kstrdup("defaulting to 1 (MSI)", GFP_KERNEL); 480 | opt.def = E1000E_INT_MODE_MSI; 481 | opt.arg.r.max = E1000E_INT_MODE_MSI; 482 | } 483 | 484 | if (!opt.err) { 485 | dev_err(pci_dev_to_dev(adapter->pdev), 486 | "Failed to allocate memory\n"); 487 | return; 488 | } 489 | #endif 490 | 491 | if (num_IntMode > bd) { 492 | unsigned int int_mode = IntMode[bd]; 493 | 494 | e1000_validate_option(&int_mode, &opt, adapter); 495 | adapter->int_mode = int_mode; 496 | } else { 497 | adapter->int_mode = opt.def; 498 | } 499 | 500 | #ifdef CONFIG_PCI_MSI 501 | kfree(opt.err); 502 | #endif 503 | } 504 | /* Smart Power Down */ 505 | { 506 | static const struct e1000_option opt = { 507 | .type = enable_option, 508 | .name = "PHY Smart Power Down", 509 | .err = "defaulting to Disabled", 510 | .def = OPTION_DISABLED 511 | }; 512 | 513 | if (num_SmartPowerDownEnable > bd) { 514 | unsigned int spd = SmartPowerDownEnable[bd]; 515 | 516 | e1000_validate_option(&spd, &opt, adapter); 517 | if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && spd) 518 | adapter->flags |= FLAG_SMART_POWER_DOWN; 519 | } 520 | } 521 | /* CRC Stripping */ 522 | { 523 | static const struct e1000_option opt = { 524 | .type = enable_option, 525 | .name = "CRC Stripping", 526 | .err = "defaulting to Enabled", 527 | .def = OPTION_ENABLED 528 | }; 529 | 530 | if (num_CrcStripping > bd) { 531 | unsigned int crc_stripping = CrcStripping[bd]; 532 | 533 | e1000_validate_option(&crc_stripping, &opt, adapter); 534 | if (crc_stripping == OPTION_ENABLED) { 535 | adapter->flags2 |= FLAG2_CRC_STRIPPING; 536 | adapter->flags2 |= FLAG2_DFLT_CRC_STRIPPING; 537 | } 538 | } else { 539 | adapter->flags2 |= FLAG2_CRC_STRIPPING; 540 | adapter->flags2 |= FLAG2_DFLT_CRC_STRIPPING; 541 | } 542 | } 543 | /* Kumeran Lock Loss Workaround */ 544 | { 545 | static const struct e1000_option opt = { 546 | .type = enable_option, 547 | .name = "Kumeran Lock Loss Workaround", 548 | .err = "defaulting to Enabled", 549 | .def = OPTION_ENABLED 550 | }; 551 | bool enabled = opt.def; 552 | 553 | if (num_KumeranLockLoss > bd) { 554 | unsigned int kmrn_lock_loss = KumeranLockLoss[bd]; 555 | 556 | e1000_validate_option(&kmrn_lock_loss, &opt, adapter); 557 | enabled = kmrn_lock_loss; 558 | } 559 | 560 | if (hw->mac.type == e1000_ich8lan) 561 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 562 | enabled); 563 | } 564 | /* EEE for parts supporting the feature */ 565 | { 566 | static const struct e1000_option opt = { 567 | .type = enable_option, 568 | .name = "EEE Support", 569 | .err = "defaulting to Enabled (100T/1000T full)", 570 | .def = OPTION_ENABLED 571 | }; 572 | 573 | if (adapter->flags2 & FLAG2_HAS_EEE) { 574 | /* Currently only supported on 82579 and newer */ 575 | if (num_EEE > bd) { 576 | unsigned int eee = EEE[bd]; 577 | e1000_validate_option(&eee, &opt, adapter); 578 | hw->dev_spec.ich8lan.eee_disable = !eee; 579 | } else { 580 | hw->dev_spec.ich8lan.eee_disable = !opt.def; 581 | } 582 | } 583 | } 584 | /* configure node specific allocation */ 585 | { 586 | static struct e1000_option opt = { 587 | .type = range_option, 588 | .name = "Node used to allocate memory", 589 | .err = "defaulting to -1 (disabled)", 590 | #ifdef HAVE_EARLY_VMALLOC_NODE 591 | .def = 0, 592 | #else 593 | .def = -1, 594 | #endif 595 | .arg = { .r = { .min = 0, 596 | .max = MAX_NUMNODES - 1 } } 597 | }; 598 | int node = opt.def; 599 | 600 | /* if the default was zero then we need to set the 601 | * default value to an online node, which is not 602 | * necessarily zero, and the constant initializer 603 | * above can't take first_online_node 604 | */ 605 | if (node == 0) { 606 | /* must set opt.def for validate */ 607 | node = first_online_node; 608 | opt.def = node; 609 | } 610 | 611 | if (num_Node > bd) { 612 | node = Node[bd]; 613 | e1000_validate_option((unsigned int *)&node, &opt, 614 | adapter); 615 | if (node != OPTION_UNSET) 616 | e_info("node used for allocation: %d\n", node); 617 | } 618 | 619 | /* check sanity of the value */ 620 | if ((node != -1) && !node_online(node)) { 621 | e_info("ignoring node set to invalid value %d\n", node); 622 | node = opt.def; 623 | } 624 | 625 | adapter->node = node; 626 | } 627 | } 628 | -------------------------------------------------------------------------------- /phy.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_PHY_H_ 23 | #define _E1000E_PHY_H_ 24 | 25 | s32 e1000e_check_downshift(struct e1000_hw *hw); 26 | s32 e1000_check_polarity_m88(struct e1000_hw *hw); 27 | s32 e1000_check_polarity_igp(struct e1000_hw *hw); 28 | s32 e1000_check_polarity_ife(struct e1000_hw *hw); 29 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 30 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 31 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 32 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 33 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 34 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 35 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 36 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 37 | s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); 38 | s32 e1000e_get_phy_id(struct e1000_hw *hw); 39 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 40 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 41 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 42 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw); 43 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 44 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 45 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 46 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 47 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 48 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 49 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 50 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 51 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 52 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 53 | s32 e1000e_setup_copper_link(struct e1000_hw *hw); 54 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 55 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 56 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 57 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 58 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 59 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 60 | u32 usec_interval, bool *success); 61 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 62 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 63 | s32 e1000e_determine_phy_address(struct e1000_hw *hw); 64 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 65 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 66 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 67 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 68 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 69 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 70 | void e1000_power_up_phy_copper(struct e1000_hw *hw); 71 | void e1000_power_down_phy_copper(struct e1000_hw *hw); 72 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 73 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 74 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 75 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 76 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 77 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 78 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 79 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 80 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 81 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 82 | s32 e1000_check_polarity_82577(struct e1000_hw *hw); 83 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 84 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 85 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 86 | 87 | #define E1000_MAX_PHY_ADDR 8 88 | 89 | /* IGP01E1000 Specific Registers */ 90 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 91 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 92 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 93 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 94 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 95 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 96 | #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 97 | #define IGP_PAGE_SHIFT 5 98 | #define PHY_REG_MASK 0x1F 99 | 100 | /* BM/HV Specific Registers */ 101 | #define BM_PORT_CTRL_PAGE 769 102 | #define BM_WUC_PAGE 800 103 | #define BM_WUC_ADDRESS_OPCODE 0x11 104 | #define BM_WUC_DATA_OPCODE 0x12 105 | #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 106 | #define BM_WUC_ENABLE_REG 17 107 | #define BM_WUC_ENABLE_BIT (1 << 2) 108 | #define BM_WUC_HOST_WU_BIT (1 << 4) 109 | #define BM_WUC_ME_WU_BIT (1 << 5) 110 | 111 | #define PHY_UPPER_SHIFT 21 112 | #define BM_PHY_REG(page, reg) \ 113 | (((reg) & MAX_PHY_REG_ADDRESS) |\ 114 | (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 115 | (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 116 | #define BM_PHY_REG_PAGE(offset) \ 117 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 118 | #define BM_PHY_REG_NUM(offset) \ 119 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 120 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 121 | ~MAX_PHY_REG_ADDRESS))) 122 | 123 | #define HV_INTC_FC_PAGE_START 768 124 | #define I82578_ADDR_REG 29 125 | #define I82577_ADDR_REG 16 126 | #define I82577_CFG_REG 22 127 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 128 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ 129 | #define I82577_CTRL_REG 23 130 | 131 | /* 82577 specific PHY registers */ 132 | #define I82577_PHY_CTRL_2 18 133 | #define I82577_PHY_LBK_CTRL 19 134 | #define I82577_PHY_STATUS_2 26 135 | #define I82577_PHY_DIAG_STATUS 31 136 | 137 | /* I82577 PHY Status 2 */ 138 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 139 | #define I82577_PHY_STATUS2_MDIX 0x0800 140 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 141 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 142 | 143 | /* I82577 PHY Control 2 */ 144 | #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 145 | #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 146 | #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 147 | 148 | /* I82577 PHY Diagnostics Status */ 149 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 150 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 151 | 152 | #define E1000_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */ 153 | #define E1000_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */ 154 | #define E1000_MPHY_BUSY 0x00010000 /* busy bit */ 155 | #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */ 156 | #define E1000_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */ 157 | 158 | /* BM PHY Copper Specific Control 1 */ 159 | #define BM_CS_CTRL1 16 160 | 161 | /* BM PHY Copper Specific Status */ 162 | #define BM_CS_STATUS 17 163 | #define BM_CS_STATUS_LINK_UP 0x0400 164 | #define BM_CS_STATUS_RESOLVED 0x0800 165 | #define BM_CS_STATUS_SPEED_MASK 0xC000 166 | #define BM_CS_STATUS_SPEED_1000 0x8000 167 | 168 | /* 82577 Mobile Phy Status Register */ 169 | #define HV_M_STATUS 26 170 | #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 171 | #define HV_M_STATUS_SPEED_MASK 0x0300 172 | #define HV_M_STATUS_SPEED_1000 0x0200 173 | #define HV_M_STATUS_SPEED_100 0x0100 174 | #define HV_M_STATUS_LINK_UP 0x0040 175 | 176 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 177 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 178 | 179 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 180 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 181 | 182 | #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 183 | 184 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 185 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 186 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 187 | 188 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 189 | 190 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 191 | #define IGP01E1000_PSSR_MDIX 0x0800 192 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 193 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 194 | 195 | #define IGP02E1000_PHY_CHANNEL_NUM 4 196 | #define IGP02E1000_PHY_AGC_A 0x11B1 197 | #define IGP02E1000_PHY_AGC_B 0x12B1 198 | #define IGP02E1000_PHY_AGC_C 0x14B1 199 | #define IGP02E1000_PHY_AGC_D 0x18B1 200 | 201 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 202 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F 203 | #define IGP02E1000_AGC_RANGE 15 204 | 205 | #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 206 | 207 | #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 208 | #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 209 | #define E1000_KMRNCTRLSTA_REN 0x00200000 210 | #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 211 | #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 212 | #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 213 | #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 214 | #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 215 | #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 216 | #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 217 | #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ 218 | #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 219 | 220 | #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 221 | #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 222 | #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 223 | #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 224 | 225 | /* IFE PHY Extended Status Control */ 226 | #define IFE_PESC_POLARITY_REVERSED 0x0100 227 | 228 | /* IFE PHY Special Control */ 229 | #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 230 | #define IFE_PSC_FORCE_POLARITY 0x0020 231 | 232 | /* IFE PHY Special Control and LED Control */ 233 | #define IFE_PSCL_PROBE_MODE 0x0020 234 | #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 235 | #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 236 | 237 | /* IFE PHY MDIX Control */ 238 | #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 239 | #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 240 | #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 241 | 242 | #endif 243 | -------------------------------------------------------------------------------- /ptp.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | /* PTP 1588 Hardware Clock (PHC) 23 | * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb) 24 | * Copyright (C) 2011 Richard Cochran 25 | */ 26 | 27 | #include "e1000.h" 28 | 29 | #ifdef CONFIG_PTP_1588_CLOCK 30 | #include 31 | #include 32 | #include 33 | #endif 34 | 35 | /** 36 | * e1000e_phc_adjfreq - adjust the frequency of the hardware clock 37 | * @ptp: ptp clock structure 38 | * @delta: Desired frequency change in parts per billion 39 | * 40 | * Adjust the frequency of the PHC cycle counter by the indicated delta from 41 | * the base frequency. 42 | **/ 43 | static int e1000e_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta) 44 | { 45 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 46 | ptp_clock_info); 47 | struct e1000_hw *hw = &adapter->hw; 48 | bool neg_adj = false; 49 | unsigned long flags; 50 | u64 adjustment; 51 | u32 timinca, incvalue; 52 | s32 ret_val; 53 | 54 | if ((delta > ptp->max_adj) || (delta <= -1000000000)) 55 | return -EINVAL; 56 | 57 | if (delta < 0) { 58 | neg_adj = true; 59 | delta = -delta; 60 | } 61 | 62 | /* Get the System Time Register SYSTIM base frequency */ 63 | ret_val = e1000e_get_base_timinca(adapter, &timinca); 64 | if (ret_val) 65 | return ret_val; 66 | 67 | spin_lock_irqsave(&adapter->systim_lock, flags); 68 | 69 | incvalue = timinca & E1000_TIMINCA_INCVALUE_MASK; 70 | 71 | adjustment = incvalue; 72 | adjustment *= delta; 73 | adjustment = div_u64(adjustment, 1000000000); 74 | 75 | incvalue = neg_adj ? (incvalue - adjustment) : (incvalue + adjustment); 76 | 77 | timinca &= ~E1000_TIMINCA_INCVALUE_MASK; 78 | timinca |= incvalue; 79 | 80 | ew32(TIMINCA, timinca); 81 | adapter->ptp_delta = delta; 82 | 83 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 84 | 85 | return 0; 86 | } 87 | 88 | /** 89 | * e1000e_phc_adjtime - Shift the time of the hardware clock 90 | * @ptp: ptp clock structure 91 | * @delta: Desired change in nanoseconds 92 | * 93 | * Adjust the timer by resetting the timecounter structure. 94 | **/ 95 | static int e1000e_phc_adjtime(struct ptp_clock_info *ptp, s64 delta) 96 | { 97 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 98 | ptp_clock_info); 99 | unsigned long flags; 100 | 101 | #ifdef HAVE_INCLUDE_LINUX_TIMECOUNTER_H 102 | spin_lock_irqsave(&adapter->systim_lock, flags); 103 | timecounter_adjtime(&adapter->tc, delta); 104 | #else 105 | s64 now; 106 | 107 | spin_lock_irqsave(&adapter->systim_lock, flags); 108 | now = timecounter_read(&adapter->tc); 109 | now += delta; 110 | timecounter_init(&adapter->tc, &adapter->cc, now); 111 | #endif 112 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 113 | 114 | return 0; 115 | } 116 | 117 | #ifdef CONFIG_PTP_1588_CLOCK 118 | #define MAX_HW_WAIT_COUNT (3) 119 | 120 | /** 121 | * e1000e_phc_get_syncdevicetime - Callback given to timekeeping code reads 122 | * system/device registers 123 | * @device: current device time 124 | * @system: system counter value read synchronously with device time 125 | * @ctx: context provided by timekeeping code 126 | * 127 | * Read device and system (ART) clock simultaneously and return the corrected 128 | * clock values in ns. 129 | **/ 130 | static int e1000e_phc_get_syncdevicetime(ktime_t * device, 131 | struct system_counterval_t *system, 132 | void *ctx) 133 | { 134 | struct e1000_adapter *adapter = (struct e1000_adapter *)ctx; 135 | struct e1000_hw *hw = &adapter->hw; 136 | unsigned long flags; 137 | int i; 138 | u32 tsync_ctrl; 139 | u64 dev_cycles; 140 | u64 sys_cycles; 141 | 142 | tsync_ctrl = er32(TSYNCTXCTL); 143 | tsync_ctrl |= E1000_TSYNCTXCTL_START_SYNC | 144 | E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK; 145 | ew32(TSYNCTXCTL, tsync_ctrl); 146 | for (i = 0; i < MAX_HW_WAIT_COUNT; ++i) { 147 | udelay(1); 148 | tsync_ctrl = er32(TSYNCTXCTL); 149 | if (tsync_ctrl & E1000_TSYNCTXCTL_SYNC_COMP) 150 | break; 151 | } 152 | 153 | if (i == MAX_HW_WAIT_COUNT) 154 | return -ETIMEDOUT; 155 | 156 | dev_cycles = er32(SYSSTMPH); 157 | dev_cycles <<= 32; 158 | dev_cycles |= er32(SYSSTMPL); 159 | spin_lock_irqsave(&adapter->systim_lock, flags); 160 | *device = ns_to_ktime(timecounter_cyc2time(&adapter->tc, dev_cycles)); 161 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 162 | 163 | sys_cycles = er32(PLTSTMPH); 164 | sys_cycles <<= 32; 165 | sys_cycles |= er32(PLTSTMPL); 166 | *system = convert_art_to_tsc(sys_cycles); 167 | 168 | return 0; 169 | } 170 | 171 | /** 172 | * e1000e_phc_getsynctime - Reads the current system/device cross timestamp 173 | * @ptp: ptp clock structure 174 | * @cts: structure containing timestamp 175 | * 176 | * Read device and system (ART) clock simultaneously and return the scaled 177 | * clock values in ns. 178 | **/ 179 | static int e1000e_phc_getcrosststamp(struct ptp_clock_info *ptp, 180 | struct system_device_crosststamp *xtstamp) 181 | { 182 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 183 | ptp_clock_info); 184 | 185 | return get_device_system_crosststamp(e1000e_phc_get_syncdevicetime, 186 | adapter, NULL, xtstamp); 187 | } 188 | #endif /*CONFIG_PTP_1588_CLOCK */ 189 | 190 | /** 191 | * e1000e_phc_gettime - Reads the current time from the hardware clock 192 | * @ptp: ptp clock structure 193 | * @ts: timespec structure to hold the current time value 194 | * 195 | * Read the timecounter and return the correct value in ns after converting 196 | * it into a struct timespec. 197 | **/ 198 | static int e1000e_phc_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 199 | { 200 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 201 | ptp_clock_info); 202 | unsigned long flags; 203 | u64 ns; 204 | 205 | spin_lock_irqsave(&adapter->systim_lock, flags); 206 | ns = timecounter_read(&adapter->tc); 207 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 208 | 209 | *ts = ns_to_timespec64(ns); 210 | 211 | return 0; 212 | } 213 | 214 | /** 215 | * e1000e_phc_settime - Set the current time on the hardware clock 216 | * @ptp: ptp clock structure 217 | * @ts: timespec containing the new time for the cycle counter 218 | * 219 | * Reset the timecounter to use a new base value instead of the kernel 220 | * wall timer value. 221 | **/ 222 | static int e1000e_phc_settime(struct ptp_clock_info *ptp, 223 | const struct timespec64 *ts) 224 | { 225 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 226 | ptp_clock_info); 227 | unsigned long flags; 228 | u64 ns; 229 | 230 | ns = timespec64_to_ns(ts); 231 | 232 | /* reset the timecounter */ 233 | spin_lock_irqsave(&adapter->systim_lock, flags); 234 | timecounter_init(&adapter->tc, &adapter->cc, ns); 235 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 236 | 237 | return 0; 238 | } 239 | 240 | #ifndef HAVE_PTP_CLOCK_INFO_GETTIME64 241 | static int e1000e_phc_gettime32(struct ptp_clock_info *ptp, struct timespec *ts) 242 | { 243 | struct timespec64 ts64; 244 | int err; 245 | 246 | err = e1000e_phc_gettime(ptp, &ts64); 247 | if (err) 248 | return err; 249 | 250 | *ts = timespec64_to_timespec(ts64); 251 | 252 | return 0; 253 | } 254 | 255 | static int e1000e_phc_settime32(struct ptp_clock_info *ptp, 256 | const struct timespec *ts) 257 | { 258 | struct timespec64 ts64; 259 | 260 | ts64 = timespec_to_timespec64(*ts); 261 | return e1000e_phc_settime(ptp, &ts64); 262 | } 263 | #endif 264 | 265 | /** 266 | * e1000e_phc_enable - enable or disable an ancillary feature 267 | * @ptp: ptp clock structure 268 | * @request: Desired resource to enable or disable 269 | * @on: Caller passes one to enable or zero to disable 270 | * 271 | * Enable (or disable) ancillary features of the PHC subsystem. 272 | * Currently, no ancillary features are supported. 273 | **/ 274 | static int e1000e_phc_enable(struct ptp_clock_info __always_unused *ptp, 275 | struct ptp_clock_request __always_unused *request, 276 | int __always_unused on) 277 | { 278 | return -EOPNOTSUPP; 279 | } 280 | 281 | static void e1000e_systim_overflow_work(struct work_struct *work) 282 | { 283 | struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 284 | systim_overflow_work.work); 285 | struct e1000_hw *hw = &adapter->hw; 286 | struct timespec64 ts; 287 | 288 | e1000e_phc_gettime(&adapter->ptp_clock_info, &ts); 289 | 290 | e_dbg("SYSTIM overflow check at %lld.%09lu\n", 291 | (long long)ts.tv_sec, ts.tv_nsec); 292 | 293 | schedule_delayed_work(&adapter->systim_overflow_work, 294 | E1000_SYSTIM_OVERFLOW_PERIOD); 295 | } 296 | 297 | static const struct ptp_clock_info e1000e_ptp_clock_info = { 298 | .owner = THIS_MODULE, 299 | .n_alarm = 0, 300 | .n_ext_ts = 0, 301 | .n_per_out = 0, 302 | #ifdef HAVE_PTP_1588_CLOCK_PINS 303 | .n_pins = 0, 304 | #endif 305 | .pps = 0, 306 | .adjfreq = e1000e_phc_adjfreq, 307 | .adjtime = e1000e_phc_adjtime, 308 | #ifdef HAVE_PTP_CLOCK_INFO_GETTIME64 309 | .gettime64 = e1000e_phc_gettime, 310 | .settime64 = e1000e_phc_settime, 311 | #else 312 | .gettime = e1000e_phc_gettime32, 313 | .settime = e1000e_phc_settime32, 314 | #endif 315 | .enable = e1000e_phc_enable, 316 | }; 317 | 318 | /** 319 | * e1000e_ptp_init - initialize PTP for devices which support it 320 | * @adapter: board private structure 321 | * 322 | * This function performs the required steps for enabling PTP support. 323 | * If PTP support has already been loaded it simply calls the cyclecounter 324 | * init routine and exits. 325 | **/ 326 | void e1000e_ptp_init(struct e1000_adapter *adapter) 327 | { 328 | struct e1000_hw *hw = &adapter->hw; 329 | 330 | adapter->ptp_clock = NULL; 331 | 332 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 333 | return; 334 | 335 | adapter->ptp_clock_info = e1000e_ptp_clock_info; 336 | 337 | snprintf(adapter->ptp_clock_info.name, 338 | sizeof(adapter->ptp_clock_info.name), "%pm", 339 | adapter->netdev->perm_addr); 340 | 341 | switch (hw->mac.type) { 342 | case e1000_pch2lan: 343 | case e1000_pch_lpt: 344 | case e1000_pch_spt: 345 | if ((hw->mac.type < e1000_pch_lpt) || 346 | (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 347 | adapter->ptp_clock_info.max_adj = 24000000 - 1; 348 | break; 349 | } 350 | /* fall-through */ 351 | case e1000_82574: 352 | case e1000_82583: 353 | adapter->ptp_clock_info.max_adj = 600000000 - 1; 354 | break; 355 | default: 356 | break; 357 | } 358 | 359 | #ifdef CONFIG_PTP_1588_CLOCK 360 | /* CPU must have ART and GBe must be from Sunrise Point or greater */ 361 | if (hw->mac.type >= e1000_pch_spt && boot_cpu_has(X86_FEATURE_ART)) 362 | adapter->ptp_clock_info.getcrosststamp = 363 | e1000e_phc_getcrosststamp; 364 | #endif /*CONFIG_PTP_1588_CLOCK */ 365 | 366 | INIT_DELAYED_WORK(&adapter->systim_overflow_work, 367 | e1000e_systim_overflow_work); 368 | 369 | schedule_delayed_work(&adapter->systim_overflow_work, 370 | E1000_SYSTIM_OVERFLOW_PERIOD); 371 | 372 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info, 373 | pci_dev_to_dev(adapter->pdev)); 374 | if (IS_ERR(adapter->ptp_clock)) { 375 | adapter->ptp_clock = NULL; 376 | e_err("ptp_clock_register failed\n"); 377 | } else if (adapter->ptp_clock) { 378 | e_info("registered PHC clock\n"); 379 | } 380 | } 381 | 382 | /** 383 | * e1000e_ptp_remove - disable PTP device and stop the overflow check 384 | * @adapter: board private structure 385 | * 386 | * Stop the PTP support, and cancel the delayed work. 387 | **/ 388 | void e1000e_ptp_remove(struct e1000_adapter *adapter) 389 | { 390 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 391 | return; 392 | 393 | cancel_delayed_work_sync(&adapter->systim_overflow_work); 394 | 395 | if (adapter->ptp_clock) { 396 | ptp_clock_unregister(adapter->ptp_clock); 397 | adapter->ptp_clock = NULL; 398 | e_info("removed PHC\n"); 399 | } 400 | } 401 | -------------------------------------------------------------------------------- /regs.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2017 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_REGS_H_ 23 | #define _E1000E_REGS_H_ 24 | 25 | #define E1000_CTRL 0x00000 /* Device Control - RW */ 26 | #define E1000_STATUS 0x00008 /* Device Status - RO */ 27 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 28 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 29 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 30 | #define E1000_FLA 0x0001C /* Flash Access - RW */ 31 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ 32 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 33 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 34 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 35 | #define E1000_FEXT 0x0002C /* Future Extended - RW */ 36 | #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 37 | #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ 38 | #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 39 | #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 40 | #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ 41 | #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */ 42 | #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ 43 | #define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */ 44 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 45 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 46 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 47 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 48 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 49 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 50 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 51 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 52 | #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 53 | #define E1000_SVCR 0x000F0 54 | #define E1000_SVT 0x000F4 55 | #define E1000_LPIC 0x000FC /* Low Power IDLE control */ 56 | #define E1000_RCTL 0x00100 /* Rx Control - RW */ 57 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 58 | #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 59 | #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 60 | #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 61 | #define E1000_TCTL 0x00400 /* Tx Control - RW */ 62 | #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ 63 | #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ 64 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 65 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 66 | #define E1000_LEDMUX 0x08130 /* LED MUX Control */ 67 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 68 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 69 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 70 | #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ 71 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 72 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ 73 | #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ 74 | #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ 75 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 76 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 77 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 78 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 79 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 80 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 81 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 82 | #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ 83 | #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ 84 | #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ 85 | #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ 86 | #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ 87 | /* Split and Replication Rx Control - RW */ 88 | #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 89 | #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 90 | /* Convenience macros 91 | * 92 | * Note: "_n" is the queue number of the register to be written to. 93 | * 94 | * Example usage: 95 | * E1000_RDBAL_REG(current_rx_queue) 96 | */ 97 | #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 98 | (0x0C000 + ((_n) * 0x40))) 99 | #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 100 | (0x0C004 + ((_n) * 0x40))) 101 | #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 102 | (0x0C008 + ((_n) * 0x40))) 103 | #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 104 | (0x0C010 + ((_n) * 0x40))) 105 | #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 106 | (0x0C018 + ((_n) * 0x40))) 107 | #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 108 | (0x0C028 + ((_n) * 0x40))) 109 | #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 110 | (0x0E000 + ((_n) * 0x40))) 111 | #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 112 | (0x0E004 + ((_n) * 0x40))) 113 | #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 114 | (0x0E008 + ((_n) * 0x40))) 115 | #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 116 | (0x0E010 + ((_n) * 0x40))) 117 | #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 118 | (0x0E018 + ((_n) * 0x40))) 119 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 120 | (0x0E028 + ((_n) * 0x40))) 121 | #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100)) 122 | #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 123 | #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 124 | (0x054E0 + ((_i - 16) * 8))) 125 | #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 126 | (0x054E4 + ((_i - 16) * 8))) 127 | #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 128 | #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 129 | #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 130 | #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 131 | #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 132 | #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 133 | #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 134 | #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ 135 | #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ 136 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 137 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 138 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 139 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 140 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 141 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 142 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 143 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 144 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 145 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 146 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ 147 | #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ 148 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 149 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 150 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 151 | #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ 152 | #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ 153 | #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ 154 | #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ 155 | #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ 156 | #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ 157 | #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ 158 | #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ 159 | #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ 160 | #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ 161 | #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ 162 | #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ 163 | #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ 164 | #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ 165 | #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ 166 | #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ 167 | #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ 168 | #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ 169 | #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ 170 | #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ 171 | #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ 172 | #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ 173 | #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ 174 | #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ 175 | #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ 176 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 177 | #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ 178 | #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ 179 | #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ 180 | #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ 181 | #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ 182 | #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ 183 | #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ 184 | #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ 185 | #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ 186 | #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ 187 | #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ 188 | #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ 189 | #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ 190 | #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ 191 | #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ 192 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ 193 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ 194 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 195 | #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 196 | #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 197 | #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 198 | #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 199 | #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 200 | #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 201 | #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 202 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 203 | #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ 204 | 205 | #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 206 | #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 207 | #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ 208 | #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 209 | #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ 210 | #define E1000_RFCTL 0x05008 /* Receive Filter Control */ 211 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 212 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ 213 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 214 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 215 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 216 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 217 | #define E1000_MANC 0x05820 /* Management Control - RW */ 218 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 219 | #define E1000_HOST_IF 0x08800 /* Host Interface */ 220 | 221 | #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 222 | #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 223 | /* Management Decision Filters */ 224 | #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) 225 | #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ 226 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 227 | #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 228 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 229 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ 230 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ 231 | /* Driver-only SW semaphore (not used by BOOT agents) */ 232 | #define E1000_SWSM2 0x05B58 233 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 234 | #define E1000_HICR 0x08F00 /* Host Interface Control */ 235 | 236 | /* RSS registers */ 237 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 238 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ 239 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ 240 | #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 241 | #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 242 | #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 243 | #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 244 | #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 245 | #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 246 | #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 247 | #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 248 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 249 | #define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */ 250 | #define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */ 251 | #define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */ 252 | #define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */ 253 | #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 254 | #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 255 | 256 | #endif 257 | -------------------------------------------------------------------------------- /version.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | BuildVersion 6 | 2 7 | CFBundleShortVersionString 8 | 1.0 9 | CFBundleVersion 10 | 1 11 | ProjectName 12 | DevToolsWizardTemplates 13 | SourceVersion 14 | 15920000 15 | 16 | 17 | --------------------------------------------------------------------------------