├── .gitattributes ├── .gitignore ├── README.md ├── bonus ├── bonus.sv ├── dnn_bonus.sv └── tb_dnn_bonus.sv ├── data ├── nn.bin ├── test_00.bin ├── test_01.bin ├── test_02.bin ├── test_03.bin ├── test_04.bin ├── test_05.bin ├── test_06.bin ├── test_07.bin ├── test_08.bin ├── test_09.bin ├── test_10.bin ├── test_11.bin ├── test_12.bin ├── test_13.bin ├── test_14.bin ├── test_15.bin ├── test_16.bin ├── test_17.bin ├── test_18.bin ├── test_19.bin ├── test_20.bin ├── test_21.bin ├── test_22.bin ├── test_23.bin ├── test_24.bin ├── test_25.bin ├── test_26.bin ├── test_27.bin ├── test_28.bin ├── test_29.bin ├── test_30.bin ├── test_31.bin ├── test_32.bin ├── test_33.bin ├── test_34.bin ├── test_35.bin ├── test_36.bin ├── test_37.bin ├── test_38.bin ├── test_39.bin ├── test_40.bin ├── test_41.bin ├── test_42.bin ├── test_43.bin ├── test_44.bin ├── test_45.bin ├── test_46.bin ├── test_47.bin ├── test_48.bin ├── test_49.bin ├── test_50.bin ├── test_51.bin ├── test_52.bin ├── test_53.bin ├── test_54.bin ├── test_55.bin ├── test_56.bin ├── test_57.bin ├── test_58.bin ├── test_59.bin ├── test_60.bin ├── test_61.bin ├── test_62.bin ├── test_63.bin ├── test_64.bin ├── test_65.bin ├── test_66.bin ├── test_67.bin ├── test_68.bin ├── test_69.bin ├── test_70.bin ├── test_71.bin ├── test_72.bin ├── test_73.bin ├── test_74.bin ├── test_75.bin ├── test_76.bin ├── test_77.bin ├── test_78.bin ├── test_79.bin ├── test_80.bin ├── test_81.bin ├── test_82.bin ├── test_83.bin ├── test_84.bin ├── test_85.bin ├── test_86.bin ├── test_87.bin ├── test_88.bin ├── test_89.bin ├── test_90.bin ├── test_91.bin ├── test_92.bin ├── test_93.bin ├── test_94.bin ├── test_95.bin ├── test_96.bin ├── test_97.bin ├── test_98.bin └── test_99.bin ├── dnn_accel_system.bsf ├── dnn_accel_system.cmp ├── dnn_accel_system.csv ├── dnn_accel_system.html ├── dnn_accel_system.spd ├── dnn_accel_system.xml ├── dnn_accel_system_generation.rpt ├── figures └── test_images.png ├── scripts └── train.py ├── simulation ├── aldec │ └── rivierapro_setup.tcl ├── cadence │ ├── cds.lib │ ├── cds_libs │ │ ├── avalon_st_adapter.cds.lib │ │ ├── avalon_st_adapter_002.cds.lib │ │ ├── cmd_demux.cds.lib │ │ ├── cmd_demux_001.cds.lib │ │ ├── cmd_mux.cds.lib │ │ ├── cmd_mux_001.cds.lib │ │ ├── cpu.cds.lib │ │ ├── error_adapter_0.cds.lib │ │ ├── irq_mapper.cds.lib │ │ ├── jtag_uart_0.cds.lib │ │ ├── jtag_uart_0_avalon_jtag_slave_agent.cds.lib │ │ ├── jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo.cds.lib │ │ ├── jtag_uart_0_avalon_jtag_slave_translator.cds.lib │ │ ├── mm_interconnect_0.cds.lib │ │ ├── new_sdram_controller_0.cds.lib │ │ ├── new_sdram_controller_0_s1_burst_adapter.cds.lib │ │ ├── new_sdram_controller_0_s1_rsp_width_adapter.cds.lib │ │ ├── nios2_gen2_0.cds.lib │ │ ├── nios2_gen2_0_data_master_agent.cds.lib │ │ ├── nios2_gen2_0_data_master_translator.cds.lib │ │ ├── pio_0.cds.lib │ │ ├── pll_0.cds.lib │ │ ├── router.cds.lib │ │ ├── router_001.cds.lib │ │ ├── router_002.cds.lib │ │ ├── router_003.cds.lib │ │ ├── router_004.cds.lib │ │ ├── rsp_demux.cds.lib │ │ ├── rsp_mux.cds.lib │ │ ├── rsp_mux_001.cds.lib │ │ └── rst_controller.cds.lib │ ├── hdl.var │ └── ncsim_setup.sh ├── dnn_accel_system.sip ├── dnn_accel_system.v ├── mentor │ └── msim_setup.tcl ├── submodules │ ├── altera_avalon_sc_fifo.v │ ├── altera_avalon_st_pipeline_base.v │ ├── altera_avalon_st_pipeline_stage.sv │ ├── altera_default_burst_converter.sv │ ├── altera_incr_burst_converter.sv │ ├── altera_merlin_address_alignment.sv │ ├── altera_merlin_arbitrator.sv │ ├── altera_merlin_burst_adapter.sv │ ├── altera_merlin_burst_adapter_13_1.sv │ ├── altera_merlin_burst_adapter_new.sv │ ├── altera_merlin_burst_adapter_uncmpr.sv │ ├── altera_merlin_burst_uncompressor.sv │ ├── altera_merlin_master_agent.sv │ ├── altera_merlin_master_translator.sv │ ├── altera_merlin_slave_agent.sv │ ├── altera_merlin_slave_translator.sv │ ├── altera_merlin_width_adapter.sv │ ├── altera_reset_controller.sdc │ ├── altera_reset_controller.v │ ├── altera_reset_synchronizer.v │ ├── altera_wrap_burst_converter.sv │ ├── dnn_accel_system_irq_mapper.sv │ ├── dnn_accel_system_jtag_uart_0.v │ ├── dnn_accel_system_mm_interconnect_0.v │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter.v │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002.v │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002_error_adapter_0.sv │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_001.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_001.sv │ ├── dnn_accel_system_mm_interconnect_0_router.sv │ ├── dnn_accel_system_mm_interconnect_0_router_001.sv │ ├── dnn_accel_system_mm_interconnect_0_router_002.sv │ ├── dnn_accel_system_mm_interconnect_0_router_003.sv │ ├── dnn_accel_system_mm_interconnect_0_router_004.sv │ ├── dnn_accel_system_mm_interconnect_0_rsp_demux.sv │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux.sv │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_001.sv │ ├── dnn_accel_system_new_sdram_controller_0.v │ ├── dnn_accel_system_nios2_gen2_0.v │ ├── dnn_accel_system_nios2_gen2_0_cpu.sdc │ ├── dnn_accel_system_nios2_gen2_0_cpu.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_sysclk.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_tck.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_wrapper.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_nios2_waves.do │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.dat │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.hex │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.mif │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.dat │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.hex │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.dat │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.hex │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif │ ├── dnn_accel_system_nios2_gen2_0_cpu_test_bench.v │ ├── dnn_accel_system_pio_0.v │ └── dnn_accel_system_pll_0.vo └── synopsys │ ├── vcs │ └── vcs_setup.sh │ └── vcsmx │ ├── synopsys_sim.setup │ └── vcsmx_setup.sh ├── synthesis ├── dnn_accel_system.debuginfo ├── dnn_accel_system.qip ├── dnn_accel_system.regmap ├── dnn_accel_system.v └── submodules │ ├── altera_avalon_sc_fifo.v │ ├── altera_avalon_st_pipeline_base.v │ ├── altera_avalon_st_pipeline_stage.sv │ ├── altera_default_burst_converter.sv │ ├── altera_incr_burst_converter.sv │ ├── altera_merlin_address_alignment.sv │ ├── altera_merlin_arbitrator.sv │ ├── altera_merlin_burst_adapter.sv │ ├── altera_merlin_burst_adapter_13_1.sv │ ├── altera_merlin_burst_adapter_new.sv │ ├── altera_merlin_burst_adapter_uncmpr.sv │ ├── altera_merlin_burst_uncompressor.sv │ ├── altera_merlin_master_agent.sv │ ├── altera_merlin_master_translator.sv │ ├── altera_merlin_slave_agent.sv │ ├── altera_merlin_slave_translator.sv │ ├── altera_merlin_width_adapter.sv │ ├── altera_reset_controller.sdc │ ├── altera_reset_controller.v │ ├── altera_reset_synchronizer.v │ ├── altera_wrap_burst_converter.sv │ ├── dnn_accel_system_irq_mapper.sv │ ├── dnn_accel_system_jtag_uart_0.v │ ├── dnn_accel_system_mm_interconnect_0.v │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter.v │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002.v │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002_error_adapter_0.sv │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_001.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux.sv │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_001.sv │ ├── dnn_accel_system_mm_interconnect_0_router.sv │ ├── dnn_accel_system_mm_interconnect_0_router_001.sv │ ├── dnn_accel_system_mm_interconnect_0_router_002.sv │ ├── dnn_accel_system_mm_interconnect_0_router_003.sv │ ├── dnn_accel_system_mm_interconnect_0_router_004.sv │ ├── dnn_accel_system_mm_interconnect_0_rsp_demux.sv │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux.sv │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_001.sv │ ├── dnn_accel_system_new_sdram_controller_0.v │ ├── dnn_accel_system_nios2_gen2_0.v │ ├── dnn_accel_system_nios2_gen2_0_cpu.sdc │ ├── dnn_accel_system_nios2_gen2_0_cpu.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_sysclk.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_tck.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_wrapper.v │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.mif │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif │ ├── dnn_accel_system_nios2_gen2_0_cpu_test_bench.v │ ├── dnn_accel_system_pio_0.v │ ├── dnn_accel_system_pll_0.qip │ └── dnn_accel_system_pll_0.v ├── task1 ├── dnn_accel_system.qsys ├── dnn_accel_system.sopcinfo ├── dnn_accel_system │ ├── dnn_accel_system.bsf │ ├── dnn_accel_system.cmp │ ├── dnn_accel_system.csv │ ├── dnn_accel_system.html │ ├── dnn_accel_system.spd │ ├── dnn_accel_system.xml │ ├── dnn_accel_system_bb.v │ ├── dnn_accel_system_generation.rpt │ ├── dnn_accel_system_generation_previous.rpt │ ├── dnn_accel_system_inst.v │ ├── dnn_accel_system_inst.vhd │ ├── simulation │ │ ├── aldec │ │ │ └── rivierapro_setup.tcl │ │ ├── cadence │ │ │ ├── cds.lib │ │ │ ├── cds_libs │ │ │ │ ├── avalon_st_adapter.cds.lib │ │ │ │ ├── avalon_st_adapter_001.cds.lib │ │ │ │ ├── avalon_st_adapter_002.cds.lib │ │ │ │ ├── cmd_demux.cds.lib │ │ │ │ ├── cmd_demux_001.cds.lib │ │ │ │ ├── cmd_demux_002.cds.lib │ │ │ │ ├── cmd_demux_003.cds.lib │ │ │ │ ├── cmd_mux.cds.lib │ │ │ │ ├── cmd_mux_001.cds.lib │ │ │ │ ├── cmd_mux_003.cds.lib │ │ │ │ ├── cmd_mux_004.cds.lib │ │ │ │ ├── cpu.cds.lib │ │ │ │ ├── dnn_interface_0.cds.lib │ │ │ │ ├── error_adapter_0.cds.lib │ │ │ │ ├── irq_mapper.cds.lib │ │ │ │ ├── jtag_uart_0.cds.lib │ │ │ │ ├── jtag_uart_0_avalon_jtag_slave_agent.cds.lib │ │ │ │ ├── jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo.cds.lib │ │ │ │ ├── jtag_uart_0_avalon_jtag_slave_translator.cds.lib │ │ │ │ ├── mm_interconnect_0.cds.lib │ │ │ │ ├── new_sdram_controller_0.cds.lib │ │ │ │ ├── new_sdram_controller_0_s1_agent.cds.lib │ │ │ │ ├── new_sdram_controller_0_s1_agent_rsp_fifo.cds.lib │ │ │ │ ├── new_sdram_controller_0_s1_burst_adapter.cds.lib │ │ │ │ ├── new_sdram_controller_0_s1_rsp_width_adapter.cds.lib │ │ │ │ ├── new_sdram_controller_0_s1_translator.cds.lib │ │ │ │ ├── nios2_gen2_0.cds.lib │ │ │ │ ├── nios2_gen2_0_data_master_agent.cds.lib │ │ │ │ ├── nios2_gen2_0_data_master_translator.cds.lib │ │ │ │ ├── pio_0.cds.lib │ │ │ │ ├── pll_0.cds.lib │ │ │ │ ├── router.cds.lib │ │ │ │ ├── router_001.cds.lib │ │ │ │ ├── router_002.cds.lib │ │ │ │ ├── router_003.cds.lib │ │ │ │ ├── router_004.cds.lib │ │ │ │ ├── router_005.cds.lib │ │ │ │ ├── router_006.cds.lib │ │ │ │ ├── router_008.cds.lib │ │ │ │ ├── rsp_demux.cds.lib │ │ │ │ ├── rsp_demux_001.cds.lib │ │ │ │ ├── rsp_mux.cds.lib │ │ │ │ ├── rsp_mux_001.cds.lib │ │ │ │ ├── rsp_mux_002.cds.lib │ │ │ │ ├── rsp_mux_003.cds.lib │ │ │ │ ├── rst_controller.cds.lib │ │ │ │ ├── wordcopy_interface_0.cds.lib │ │ │ │ ├── wordcopy_interface_0_avalon_master_agent.cds.lib │ │ │ │ └── wordcopy_interface_0_avalon_master_translator.cds.lib │ │ │ ├── hdl.var │ │ │ └── ncsim_setup.sh │ │ ├── dnn_accel_system.sip │ │ ├── dnn_accel_system.v │ │ ├── mentor │ │ │ └── msim_setup.tcl │ │ ├── submodules │ │ │ ├── altera_avalon_sc_fifo.v │ │ │ ├── altera_avalon_st_pipeline_base.v │ │ │ ├── altera_avalon_st_pipeline_stage.sv │ │ │ ├── altera_default_burst_converter.sv │ │ │ ├── altera_incr_burst_converter.sv │ │ │ ├── altera_merlin_address_alignment.sv │ │ │ ├── altera_merlin_arbitrator.sv │ │ │ ├── altera_merlin_burst_adapter.sv │ │ │ ├── altera_merlin_burst_adapter_13_1.sv │ │ │ ├── altera_merlin_burst_adapter_new.sv │ │ │ ├── altera_merlin_burst_adapter_uncmpr.sv │ │ │ ├── altera_merlin_burst_uncompressor.sv │ │ │ ├── altera_merlin_master_agent.sv │ │ │ ├── altera_merlin_master_translator.sv │ │ │ ├── altera_merlin_slave_agent.sv │ │ │ ├── altera_merlin_slave_translator.sv │ │ │ ├── altera_merlin_width_adapter.sv │ │ │ ├── altera_reset_controller.sdc │ │ │ ├── altera_reset_controller.v │ │ │ ├── altera_reset_synchronizer.v │ │ │ ├── altera_wrap_burst_converter.sv │ │ │ ├── dnn.sv │ │ │ ├── dnn_accel_system_irq_mapper.sv │ │ │ ├── dnn_accel_system_jtag_uart_0.v │ │ │ ├── dnn_accel_system_mm_interconnect_0.v │ │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter.v │ │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_001.v │ │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002.v │ │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002_error_adapter_0.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_001.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_002.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_003.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_001.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_003.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_004.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_001.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_002.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_003.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_004.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_005.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_006.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_router_008.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_demux.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_demux_001.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_001.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_002.sv │ │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_003.sv │ │ │ ├── dnn_accel_system_new_sdram_controller_0.v │ │ │ ├── dnn_accel_system_nios2_gen2_0.v │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu.sdc │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu.v │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_sysclk.v │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_tck.v │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_wrapper.v │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_nios2_waves.do │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.dat │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.hex │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.mif │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.dat │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.hex │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.dat │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.hex │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif │ │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_test_bench.v │ │ │ ├── dnn_accel_system_pio_0.v │ │ │ ├── dnn_accel_system_pll_0.vo │ │ │ └── wordcopy.sv │ │ └── synopsys │ │ │ ├── vcs │ │ │ └── vcs_setup.sh │ │ │ └── vcsmx │ │ │ ├── synopsys_sim.setup │ │ │ └── vcsmx_setup.sh │ └── synthesis │ │ ├── dnn_accel_system.debuginfo │ │ ├── dnn_accel_system.qip │ │ ├── dnn_accel_system.regmap │ │ ├── dnn_accel_system.v │ │ └── submodules │ │ ├── altera_avalon_sc_fifo.v │ │ ├── altera_avalon_st_pipeline_base.v │ │ ├── altera_avalon_st_pipeline_stage.sv │ │ ├── altera_default_burst_converter.sv │ │ ├── altera_incr_burst_converter.sv │ │ ├── altera_merlin_address_alignment.sv │ │ ├── altera_merlin_arbitrator.sv │ │ ├── altera_merlin_burst_adapter.sv │ │ ├── altera_merlin_burst_adapter_13_1.sv │ │ ├── altera_merlin_burst_adapter_new.sv │ │ ├── altera_merlin_burst_adapter_uncmpr.sv │ │ ├── altera_merlin_burst_uncompressor.sv │ │ ├── altera_merlin_master_agent.sv │ │ ├── altera_merlin_master_translator.sv │ │ ├── altera_merlin_slave_agent.sv │ │ ├── altera_merlin_slave_translator.sv │ │ ├── altera_merlin_width_adapter.sv │ │ ├── altera_reset_controller.sdc │ │ ├── altera_reset_controller.v │ │ ├── altera_reset_synchronizer.v │ │ ├── altera_wrap_burst_converter.sv │ │ ├── dnn.sv │ │ ├── dnn_accel_system_irq_mapper.sv │ │ ├── dnn_accel_system_jtag_uart_0.v │ │ ├── dnn_accel_system_mm_interconnect_0.v │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter.v │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_001.v │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002.v │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_002_error_adapter_0.sv │ │ ├── dnn_accel_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_001.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_002.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_demux_003.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_001.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_003.sv │ │ ├── dnn_accel_system_mm_interconnect_0_cmd_mux_004.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_001.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_002.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_003.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_004.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_005.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_006.sv │ │ ├── dnn_accel_system_mm_interconnect_0_router_008.sv │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_demux.sv │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_demux_001.sv │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux.sv │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_001.sv │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_002.sv │ │ ├── dnn_accel_system_mm_interconnect_0_rsp_mux_003.sv │ │ ├── dnn_accel_system_new_sdram_controller_0.v │ │ ├── dnn_accel_system_nios2_gen2_0.v │ │ ├── dnn_accel_system_nios2_gen2_0_cpu.sdc │ │ ├── dnn_accel_system_nios2_gen2_0_cpu.v │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_sysclk.v │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_tck.v │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_debug_slave_wrapper.v │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_ociram_default_contents.mif │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif │ │ ├── dnn_accel_system_nios2_gen2_0_cpu_test_bench.v │ │ ├── dnn_accel_system_pio_0.v │ │ ├── dnn_accel_system_pll_0.qip │ │ ├── dnn_accel_system_pll_0.v │ │ └── wordcopy.sv ├── run_nn.c ├── run_nn.elf ├── run_nn.srec ├── task1.amp └── task1.sv ├── task2 ├── .qsys_edit │ ├── filters.xml │ └── preferences.xml ├── Untitled-1.sv ├── task2.amp ├── task2.qws ├── task2.sv ├── task2_description.txt ├── tb_wordcopy.sv ├── wordcopy.c ├── wordcopy.elf ├── wordcopy.srec └── wordcopy.sv ├── task3 ├── dnn.sv ├── run_nn.elf ├── run_nn.srec ├── task3.amp ├── task3.sv └── tb_dnn.sv └── unsaved ├── unsaved.bsf ├── unsaved.cmp ├── unsaved_bb.v ├── unsaved_inst.v └── unsaved_inst.vhd /.gitattributes: -------------------------------------------------------------------------------- 1 | *.bin binary 2 | *.png binary 3 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | transcript 2 | c5_pin_model_dump.txt 3 | *.mti 4 | *.mpf 5 | *.wlf 6 | *.qdb 7 | *.qpg 8 | *.qtl 9 | *.qsf 10 | *.qpf 11 | *.bak 12 | *.o 13 | work/ 14 | db/ 15 | incremental_db/ 16 | output_files/ 17 | -------------------------------------------------------------------------------- /bonus/bonus.sv: -------------------------------------------------------------------------------- 1 | module bonus(input logic CLOCK_50, input logic [3:0] KEY, // KEY[3] is async active-low reset 2 | input logic [9:0] SW, output logic [9:0] LEDR, 3 | output logic DRAM_CLK, output logic DRAM_CKE, 4 | output logic DRAM_CAS_N, output logic DRAM_RAS_N, output logic DRAM_WE_N, 5 | output logic [12:0] DRAM_ADDR, output logic [1:0] DRAM_BA, output logic DRAM_CS_N, 6 | inout logic [15:0] DRAM_DQ, output logic DRAM_UDQM, output logic DRAM_LDQM, 7 | output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, 8 | output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5); 9 | assign HEX1 = 7'b1111111; 10 | assign HEX2 = 7'b1111111; 11 | assign HEX3 = 7'b1111111; 12 | assign HEX4 = 7'b1111111; 13 | assign HEX5 = 7'b1111111; 14 | assign LEDR[8:0] = 9'b000000000; 15 | dnn_accel_system sys(.clk_clk(CLOCK_50), .reset_reset_n(KEY[3]), 16 | .pll_locked_export(LEDR[9]), 17 | .sdram_clk_clk(DRAM_CLK), 18 | .sdram_addr(DRAM_ADDR), 19 | .sdram_ba(DRAM_BA), 20 | .sdram_cas_n(DRAM_CAS_N), 21 | .sdram_cke(DRAM_CKE), 22 | .sdram_cs_n(DRAM_CS_N), 23 | .sdram_dq(DRAM_DQ), 24 | .sdram_dqm({DRAM_UDQM, DRAM_LDQM}), 25 | .sdram_ras_n(DRAM_RAS_N), 26 | .sdram_we_n(DRAM_WE_N), 27 | .hex_export(HEX0)); 28 | endmodule: bonus 29 | 30 | -------------------------------------------------------------------------------- /bonus/dnn_bonus.sv: -------------------------------------------------------------------------------- 1 | module dnn_bonus(input logic clk, input logic rst_n, 2 | // slave (CPU-facing) 3 | output logic slave_waitrequest, 4 | input logic [3:0] slave_address, 5 | input logic slave_read, output logic [31:0] slave_readdata, 6 | input logic slave_write, input logic [31:0] slave_writedata, 7 | // master (SDRAM-facing) 8 | input logic master_waitrequest, 9 | output logic [31:0] master_address, 10 | output logic master_read, input logic [31:0] master_readdata, input logic master_readdatavalid, 11 | output logic master_write, output logic [31:0] master_writedata); 12 | 13 | // your code here 14 | 15 | endmodule: dnn_bonus 16 | -------------------------------------------------------------------------------- /bonus/tb_dnn_bonus.sv: -------------------------------------------------------------------------------- 1 | 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dnn_accel_system is 2 | port ( 3 | clk_clk : in std_logic := 'X'; -- clk 4 | hex_export : out std_logic_vector(6 downto 0); -- export 5 | pll_locked_export : out std_logic; -- export 6 | reset_reset_n : in std_logic := 'X'; -- reset_n 7 | sdram_addr : out std_logic_vector(12 downto 0); -- addr 8 | sdram_ba : out std_logic_vector(1 downto 0); -- ba 9 | sdram_cas_n : out std_logic; -- cas_n 10 | sdram_cke : out std_logic; -- cke 11 | sdram_cs_n : out std_logic; -- cs_n 12 | sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq 13 | sdram_dqm : out std_logic_vector(1 downto 0); -- dqm 14 | sdram_ras_n : out std_logic; -- ras_n 15 | sdram_we_n : out std_logic; -- we_n 16 | sdram_clk_clk : out std_logic -- clk 17 | ); 18 | end component dnn_accel_system; 19 | 20 | -------------------------------------------------------------------------------- /figures/test_images.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrisneuf/Deep-Neural-Network-Hardware-Accelerator/8df834fa268973698b0c18b137d8fab0316a1a61/figures/test_images.png -------------------------------------------------------------------------------- /scripts/train.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import numpy as np, chainer, chainer.functions as F, chainer.links as L 4 | from chainer import training, serializers 5 | from chainer.training import extensions 6 | 7 | class CPEN311NN(chainer.Chain): 8 | def __init__(self): 9 | super(CPEN311NN, self).__init__() 10 | with self.init_scope(): 11 | self.l1 = L.Linear(None, 1000) 12 | self.l2 = L.Linear(None, 1000) 13 | self.l3 = L.Linear(None, 10) 14 | def forward(self, x): 15 | o1 = F.relu(self.l1(x)) 16 | o2 = F.relu(self.l2(o1)) 17 | o3 = self.l3(o2) 18 | return o3 19 | 20 | nn = L.Classifier(CPEN311NN()) 21 | 22 | optimizer = chainer.optimizers.Adam() 23 | optimizer.setup(nn) 24 | 25 | train, test = chainer.datasets.get_mnist() 26 | 27 | train_iter = chainer.iterators.SerialIterator(train, 100) 28 | test_iter = chainer.iterators.SerialIterator(test, 100, repeat=False, shuffle=False) 29 | 30 | updater = training.updaters.StandardUpdater(train_iter, optimizer) 31 | trainer = training.Trainer(updater, (20, 'epoch')) 32 | 33 | trainer.extend(extensions.Evaluator(test_iter, nn)) 34 | trainer.extend(extensions.LogReport()) 35 | trainer.extend(extensions.PrintReport(['epoch', 'main/loss', 'validation/main/loss', 'main/accuracy', 'validation/main/accuracy', 'elapsed_time'])) 36 | trainer.extend(extensions.ProgressBar()) 37 | 38 | trainer.run() 39 | serializers.save_npz('cpen311_trained_nn.npz', nn) 40 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/avalon_st_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE avalon_st_adapter ./../libraries/avalon_st_adapter/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/avalon_st_adapter_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE avalon_st_adapter_002 ./../libraries/avalon_st_adapter_002/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/cmd_demux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_demux ./../libraries/cmd_demux/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/cmd_demux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_demux_001 ./../libraries/cmd_demux_001/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/cmd_mux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_mux ./../libraries/cmd_mux/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/cmd_mux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_mux_001 ./../libraries/cmd_mux_001/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/cpu.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cpu ./../libraries/cpu/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/error_adapter_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE error_adapter_0 ./../libraries/error_adapter_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/irq_mapper.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE irq_mapper ./../libraries/irq_mapper/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/jtag_uart_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0 ./../libraries/jtag_uart_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/jtag_uart_0_avalon_jtag_slave_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0_avalon_jtag_slave_agent ./../libraries/jtag_uart_0_avalon_jtag_slave_agent/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo ./../libraries/jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/jtag_uart_0_avalon_jtag_slave_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0_avalon_jtag_slave_translator ./../libraries/jtag_uart_0_avalon_jtag_slave_translator/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/mm_interconnect_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE mm_interconnect_0 ./../libraries/mm_interconnect_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/new_sdram_controller_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0 ./../libraries/new_sdram_controller_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/new_sdram_controller_0_s1_burst_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_burst_adapter ./../libraries/new_sdram_controller_0_s1_burst_adapter/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/new_sdram_controller_0_s1_rsp_width_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_rsp_width_adapter ./../libraries/new_sdram_controller_0_s1_rsp_width_adapter/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/nios2_gen2_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE nios2_gen2_0 ./../libraries/nios2_gen2_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/nios2_gen2_0_data_master_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE nios2_gen2_0_data_master_agent ./../libraries/nios2_gen2_0_data_master_agent/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/nios2_gen2_0_data_master_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE nios2_gen2_0_data_master_translator ./../libraries/nios2_gen2_0_data_master_translator/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/pio_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE pio_0 ./../libraries/pio_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/pll_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE pll_0 ./../libraries/pll_0/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/router.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router ./../libraries/router/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/router_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_001 ./../libraries/router_001/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/router_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_002 ./../libraries/router_002/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/router_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_003 ./../libraries/router_003/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/router_004.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_004 ./../libraries/router_004/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/rsp_demux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_demux ./../libraries/rsp_demux/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/rsp_mux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_mux ./../libraries/rsp_mux/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/rsp_mux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_mux_001 ./../libraries/rsp_mux_001/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/cds_libs/rst_controller.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rst_controller ./../libraries/rst_controller/ 21 | -------------------------------------------------------------------------------- /simulation/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /simulation/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_irq_mapper.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/17.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2017/07/30 $ 17 | // $Author: swbranch $ 18 | 19 | // ------------------------------------------------------- 20 | // Altera IRQ Mapper 21 | // 22 | // Parameters 23 | // NUM_RCVRS : 1 24 | // SENDER_IRW_WIDTH : 32 25 | // IRQ_MAP : 0:0 26 | // 27 | // ------------------------------------------------------- 28 | 29 | `timescale 1 ns / 1 ns 30 | 31 | module dnn_accel_system_irq_mapper 32 | ( 33 | // ------------------- 34 | // Clock & Reset 35 | // ------------------- 36 | input clk, 37 | input reset, 38 | 39 | // ------------------- 40 | // IRQ Receivers 41 | // ------------------- 42 | input receiver0_irq, 43 | 44 | // ------------------- 45 | // Command Source (Output) 46 | // ------------------- 47 | output reg [31 : 0] sender_irq 48 | ); 49 | 50 | 51 | always @* begin 52 | sender_irq = 0; 53 | 54 | sender_irq[0] = receiver0_irq; 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.dat: -------------------------------------------------------------------------------- 1 | @00 2 | deadbeef 3 | deadbeef 4 | deadbeef 5 | deadbeef 6 | deadbeef 7 | deadbeef 8 | deadbeef 9 | deadbeef 10 | deadbeef 11 | deadbeef 12 | deadbeef 13 | deadbeef 14 | deadbeef 15 | deadbeef 16 | deadbeef 17 | deadbeef 18 | deadbeef 19 | deadbeef 20 | deadbeef 21 | deadbeef 22 | deadbeef 23 | deadbeef 24 | deadbeef 25 | deadbeef 26 | deadbeef 27 | deadbeef 28 | deadbeef 29 | deadbeef 30 | deadbeef 31 | deadbeef 32 | deadbeef 33 | deadbeef 34 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.hex: -------------------------------------------------------------------------------- 1 | :020000020000fc 2 | :04000000deadbeefc4 3 | :04000100deadbeefc3 4 | :04000200deadbeefc2 5 | :04000300deadbeefc1 6 | :04000400deadbeefc0 7 | :04000500deadbeefbf 8 | :04000600deadbeefbe 9 | :04000700deadbeefbd 10 | :04000800deadbeefbc 11 | :04000900deadbeefbb 12 | :04000a00deadbeefba 13 | :04000b00deadbeefb9 14 | :04000c00deadbeefb8 15 | :04000d00deadbeefb7 16 | :04000e00deadbeefb6 17 | :04000f00deadbeefb5 18 | :04001000deadbeefb4 19 | :04001100deadbeefb3 20 | :04001200deadbeefb2 21 | :04001300deadbeefb1 22 | :04001400deadbeefb0 23 | :04001500deadbeefaf 24 | :04001600deadbeefae 25 | :04001700deadbeefad 26 | :04001800deadbeefac 27 | :04001900deadbeefab 28 | :04001a00deadbeefaa 29 | :04001b00deadbeefa9 30 | :04001c00deadbeefa8 31 | :04001d00deadbeefa7 32 | :04001e00deadbeefa6 33 | :04001f00deadbeefa5 34 | :00000001FF 35 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.dat: -------------------------------------------------------------------------------- 1 | @00 2 | deadbeef 3 | deadbeef 4 | deadbeef 5 | deadbeef 6 | deadbeef 7 | deadbeef 8 | deadbeef 9 | deadbeef 10 | deadbeef 11 | deadbeef 12 | deadbeef 13 | deadbeef 14 | deadbeef 15 | deadbeef 16 | deadbeef 17 | deadbeef 18 | deadbeef 19 | deadbeef 20 | deadbeef 21 | deadbeef 22 | deadbeef 23 | deadbeef 24 | deadbeef 25 | deadbeef 26 | deadbeef 27 | deadbeef 28 | deadbeef 29 | deadbeef 30 | deadbeef 31 | deadbeef 32 | deadbeef 33 | deadbeef 34 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.hex: -------------------------------------------------------------------------------- 1 | :020000020000fc 2 | :04000000deadbeefc4 3 | :04000100deadbeefc3 4 | :04000200deadbeefc2 5 | :04000300deadbeefc1 6 | :04000400deadbeefc0 7 | :04000500deadbeefbf 8 | :04000600deadbeefbe 9 | :04000700deadbeefbd 10 | :04000800deadbeefbc 11 | :04000900deadbeefbb 12 | :04000a00deadbeefba 13 | :04000b00deadbeefb9 14 | :04000c00deadbeefb8 15 | :04000d00deadbeefb7 16 | :04000e00deadbeefb6 17 | :04000f00deadbeefb5 18 | :04001000deadbeefb4 19 | :04001100deadbeefb3 20 | :04001200deadbeefb2 21 | :04001300deadbeefb1 22 | :04001400deadbeefb0 23 | :04001500deadbeefaf 24 | :04001600deadbeefae 25 | :04001700deadbeefad 26 | :04001800deadbeefac 27 | :04001900deadbeefab 28 | :04001a00deadbeefaa 29 | :04001b00deadbeefa9 30 | :04001c00deadbeefa8 31 | :04001d00deadbeefa7 32 | :04001e00deadbeefa6 33 | :04001f00deadbeefa5 34 | :00000001FF 35 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /simulation/submodules/dnn_accel_system_pio_0.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | // synthesis translate_off 14 | `timescale 1ns / 1ps 15 | // synthesis translate_on 16 | 17 | // turn off superfluous verilog processor warnings 18 | // altera message_level Level1 19 | // altera message_off 10034 10035 10036 10037 10230 10240 10030 20 | 21 | module dnn_accel_system_pio_0 ( 22 | // inputs: 23 | address, 24 | chipselect, 25 | clk, 26 | reset_n, 27 | write_n, 28 | writedata, 29 | 30 | // outputs: 31 | out_port, 32 | readdata 33 | ) 34 | ; 35 | 36 | output [ 6: 0] out_port; 37 | output [ 31: 0] readdata; 38 | input [ 1: 0] address; 39 | input chipselect; 40 | input clk; 41 | input reset_n; 42 | input write_n; 43 | input [ 31: 0] writedata; 44 | 45 | 46 | wire clk_en; 47 | reg [ 6: 0] data_out; 48 | wire [ 6: 0] out_port; 49 | wire [ 6: 0] read_mux_out; 50 | wire [ 31: 0] readdata; 51 | assign clk_en = 1; 52 | //s1, which is an e_avalon_slave 53 | assign read_mux_out = {7 {(address == 0)}} & data_out; 54 | always @(posedge clk or negedge reset_n) 55 | begin 56 | if (reset_n == 0) 57 | data_out <= 127; 58 | else if (chipselect && ~write_n && (address == 0)) 59 | data_out <= writedata[6 : 0]; 60 | end 61 | 62 | 63 | assign readdata = {32'b0 | read_mux_out}; 64 | assign out_port = data_out; 65 | 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /synthesis/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /synthesis/submodules/dnn_accel_system_irq_mapper.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/17.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2017/07/30 $ 17 | // $Author: swbranch $ 18 | 19 | // ------------------------------------------------------- 20 | // Altera IRQ Mapper 21 | // 22 | // Parameters 23 | // NUM_RCVRS : 1 24 | // SENDER_IRW_WIDTH : 32 25 | // IRQ_MAP : 0:0 26 | // 27 | // ------------------------------------------------------- 28 | 29 | `timescale 1 ns / 1 ns 30 | 31 | module dnn_accel_system_irq_mapper 32 | ( 33 | // ------------------- 34 | // Clock & Reset 35 | // ------------------- 36 | input clk, 37 | input reset, 38 | 39 | // ------------------- 40 | // IRQ Receivers 41 | // ------------------- 42 | input receiver0_irq, 43 | 44 | // ------------------- 45 | // Command Source (Output) 46 | // ------------------- 47 | output reg [31 : 0] sender_irq 48 | ); 49 | 50 | 51 | always @* begin 52 | sender_irq = 0; 53 | 54 | sender_irq[0] = receiver0_irq; 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /synthesis/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /synthesis/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /synthesis/submodules/dnn_accel_system_pio_0.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | // synthesis translate_off 14 | `timescale 1ns / 1ps 15 | // synthesis translate_on 16 | 17 | // turn off superfluous verilog processor warnings 18 | // altera message_level Level1 19 | // altera message_off 10034 10035 10036 10037 10230 10240 10030 20 | 21 | module dnn_accel_system_pio_0 ( 22 | // inputs: 23 | address, 24 | chipselect, 25 | clk, 26 | reset_n, 27 | write_n, 28 | writedata, 29 | 30 | // outputs: 31 | out_port, 32 | readdata 33 | ) 34 | ; 35 | 36 | output [ 6: 0] out_port; 37 | output [ 31: 0] readdata; 38 | input [ 1: 0] address; 39 | input chipselect; 40 | input clk; 41 | input reset_n; 42 | input write_n; 43 | input [ 31: 0] writedata; 44 | 45 | 46 | wire clk_en; 47 | reg [ 6: 0] data_out; 48 | wire [ 6: 0] out_port; 49 | wire [ 6: 0] read_mux_out; 50 | wire [ 31: 0] readdata; 51 | assign clk_en = 1; 52 | //s1, which is an e_avalon_slave 53 | assign read_mux_out = {7 {(address == 0)}} & data_out; 54 | always @(posedge clk or negedge reset_n) 55 | begin 56 | if (reset_n == 0) 57 | data_out <= 127; 58 | else if (chipselect && ~write_n && (address == 0)) 59 | data_out <= writedata[6 : 0]; 60 | end 61 | 62 | 63 | assign readdata = {32'b0 | read_mux_out}; 64 | assign out_port = data_out; 65 | 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /synthesis/submodules/dnn_accel_system_pll_0.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*dnn_accel_system_pll_0*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*dnn_accel_system_pll_0*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*dnn_accel_system_pll_0*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/dnn_accel_system.cmp: -------------------------------------------------------------------------------- 1 | component dnn_accel_system is 2 | port ( 3 | clk_clk : in std_logic := 'X'; -- clk 4 | hex_export : out std_logic_vector(6 downto 0); -- export 5 | pll_locked_export : out std_logic; -- export 6 | reset_reset_n : in std_logic := 'X'; -- reset_n 7 | sdram_addr : out std_logic_vector(12 downto 0); -- addr 8 | sdram_ba : out std_logic_vector(1 downto 0); -- ba 9 | sdram_cas_n : out std_logic; -- cas_n 10 | sdram_cke : out std_logic; -- cke 11 | sdram_cs_n : out std_logic; -- cs_n 12 | sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq 13 | sdram_dqm : out std_logic_vector(1 downto 0); -- dqm 14 | sdram_ras_n : out std_logic; -- ras_n 15 | sdram_we_n : out std_logic; -- we_n 16 | sdram_clk_clk : out std_logic -- clk 17 | ); 18 | end component dnn_accel_system; 19 | 20 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/dnn_accel_system_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module dnn_accel_system ( 3 | clk_clk, 4 | hex_export, 5 | pll_locked_export, 6 | reset_reset_n, 7 | sdram_addr, 8 | sdram_ba, 9 | sdram_cas_n, 10 | sdram_cke, 11 | sdram_cs_n, 12 | sdram_dq, 13 | sdram_dqm, 14 | sdram_ras_n, 15 | sdram_we_n, 16 | sdram_clk_clk); 17 | 18 | input clk_clk; 19 | output [6:0] hex_export; 20 | output pll_locked_export; 21 | input reset_reset_n; 22 | output [12:0] sdram_addr; 23 | output [1:0] sdram_ba; 24 | output sdram_cas_n; 25 | output sdram_cke; 26 | output sdram_cs_n; 27 | inout [15:0] sdram_dq; 28 | output [1:0] sdram_dqm; 29 | output sdram_ras_n; 30 | output sdram_we_n; 31 | output sdram_clk_clk; 32 | endmodule 33 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/dnn_accel_system_inst.v: -------------------------------------------------------------------------------- 1 | dnn_accel_system u0 ( 2 | .clk_clk (), // clk.clk 3 | .hex_export (), // hex.export 4 | .pll_locked_export (), // pll_locked.export 5 | .reset_reset_n (), // reset.reset_n 6 | .sdram_addr (), // sdram.addr 7 | .sdram_ba (), // .ba 8 | .sdram_cas_n (), // .cas_n 9 | .sdram_cke (), // .cke 10 | .sdram_cs_n (), // .cs_n 11 | .sdram_dq (), // .dq 12 | .sdram_dqm (), // .dqm 13 | .sdram_ras_n (), // .ras_n 14 | .sdram_we_n (), // .we_n 15 | .sdram_clk_clk () // sdram_clk.clk 16 | ); 17 | 18 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/avalon_st_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE avalon_st_adapter ./../libraries/avalon_st_adapter/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/avalon_st_adapter_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE avalon_st_adapter_001 ./../libraries/avalon_st_adapter_001/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/avalon_st_adapter_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE avalon_st_adapter_002 ./../libraries/avalon_st_adapter_002/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_demux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_demux ./../libraries/cmd_demux/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_demux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_demux_001 ./../libraries/cmd_demux_001/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_demux_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_demux_002 ./../libraries/cmd_demux_002/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_demux_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_demux_003 ./../libraries/cmd_demux_003/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_mux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_mux ./../libraries/cmd_mux/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_mux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_mux_001 ./../libraries/cmd_mux_001/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_mux_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_mux_003 ./../libraries/cmd_mux_003/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cmd_mux_004.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cmd_mux_004 ./../libraries/cmd_mux_004/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/cpu.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE cpu ./../libraries/cpu/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/dnn_interface_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE dnn_interface_0 ./../libraries/dnn_interface_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/error_adapter_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE error_adapter_0 ./../libraries/error_adapter_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/irq_mapper.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE irq_mapper ./../libraries/irq_mapper/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/jtag_uart_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0 ./../libraries/jtag_uart_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/jtag_uart_0_avalon_jtag_slave_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0_avalon_jtag_slave_agent ./../libraries/jtag_uart_0_avalon_jtag_slave_agent/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo ./../libraries/jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/jtag_uart_0_avalon_jtag_slave_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE jtag_uart_0_avalon_jtag_slave_translator ./../libraries/jtag_uart_0_avalon_jtag_slave_translator/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/mm_interconnect_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE mm_interconnect_0 ./../libraries/mm_interconnect_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/new_sdram_controller_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0 ./../libraries/new_sdram_controller_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/new_sdram_controller_0_s1_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_agent ./../libraries/new_sdram_controller_0_s1_agent/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/new_sdram_controller_0_s1_agent_rsp_fifo.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_agent_rsp_fifo ./../libraries/new_sdram_controller_0_s1_agent_rsp_fifo/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/new_sdram_controller_0_s1_burst_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_burst_adapter ./../libraries/new_sdram_controller_0_s1_burst_adapter/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/new_sdram_controller_0_s1_rsp_width_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_rsp_width_adapter ./../libraries/new_sdram_controller_0_s1_rsp_width_adapter/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/new_sdram_controller_0_s1_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE new_sdram_controller_0_s1_translator ./../libraries/new_sdram_controller_0_s1_translator/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/nios2_gen2_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE nios2_gen2_0 ./../libraries/nios2_gen2_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/nios2_gen2_0_data_master_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE nios2_gen2_0_data_master_agent ./../libraries/nios2_gen2_0_data_master_agent/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/nios2_gen2_0_data_master_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE nios2_gen2_0_data_master_translator ./../libraries/nios2_gen2_0_data_master_translator/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/pio_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE pio_0 ./../libraries/pio_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/pll_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE pll_0 ./../libraries/pll_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router ./../libraries/router/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_001 ./../libraries/router_001/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_002 ./../libraries/router_002/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_003 ./../libraries/router_003/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_004.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_004 ./../libraries/router_004/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_005.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_005 ./../libraries/router_005/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_006.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_006 ./../libraries/router_006/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/router_008.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE router_008 ./../libraries/router_008/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rsp_demux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_demux ./../libraries/rsp_demux/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rsp_demux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_demux_001 ./../libraries/rsp_demux_001/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rsp_mux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_mux ./../libraries/rsp_mux/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rsp_mux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_mux_001 ./../libraries/rsp_mux_001/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rsp_mux_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_mux_002 ./../libraries/rsp_mux_002/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rsp_mux_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rsp_mux_003 ./../libraries/rsp_mux_003/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/rst_controller.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE rst_controller ./../libraries/rst_controller/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/wordcopy_interface_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE wordcopy_interface_0 ./../libraries/wordcopy_interface_0/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/wordcopy_interface_0_avalon_master_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE wordcopy_interface_0_avalon_master_agent ./../libraries/wordcopy_interface_0_avalon_master_agent/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/cds_libs/wordcopy_interface_0_avalon_master_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE wordcopy_interface_0_avalon_master_translator ./../libraries/wordcopy_interface_0_avalon_master_translator/ 21 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_irq_mapper.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/17.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2017/07/30 $ 17 | // $Author: swbranch $ 18 | 19 | // ------------------------------------------------------- 20 | // Altera IRQ Mapper 21 | // 22 | // Parameters 23 | // NUM_RCVRS : 1 24 | // SENDER_IRW_WIDTH : 32 25 | // IRQ_MAP : 0:5 26 | // 27 | // ------------------------------------------------------- 28 | 29 | `timescale 1 ns / 1 ns 30 | 31 | module dnn_accel_system_irq_mapper 32 | ( 33 | // ------------------- 34 | // Clock & Reset 35 | // ------------------- 36 | input clk, 37 | input reset, 38 | 39 | // ------------------- 40 | // IRQ Receivers 41 | // ------------------- 42 | input receiver0_irq, 43 | 44 | // ------------------- 45 | // Command Source (Output) 46 | // ------------------- 47 | output reg [31 : 0] sender_irq 48 | ); 49 | 50 | 51 | always @* begin 52 | sender_irq = 0; 53 | 54 | sender_irq[5] = receiver0_irq; 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.dat: -------------------------------------------------------------------------------- 1 | @00 2 | deadbeef 3 | deadbeef 4 | deadbeef 5 | deadbeef 6 | deadbeef 7 | deadbeef 8 | deadbeef 9 | deadbeef 10 | deadbeef 11 | deadbeef 12 | deadbeef 13 | deadbeef 14 | deadbeef 15 | deadbeef 16 | deadbeef 17 | deadbeef 18 | deadbeef 19 | deadbeef 20 | deadbeef 21 | deadbeef 22 | deadbeef 23 | deadbeef 24 | deadbeef 25 | deadbeef 26 | deadbeef 27 | deadbeef 28 | deadbeef 29 | deadbeef 30 | deadbeef 31 | deadbeef 32 | deadbeef 33 | deadbeef 34 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.hex: -------------------------------------------------------------------------------- 1 | :020000020000fc 2 | :04000000deadbeefc4 3 | :04000100deadbeefc3 4 | :04000200deadbeefc2 5 | :04000300deadbeefc1 6 | :04000400deadbeefc0 7 | :04000500deadbeefbf 8 | :04000600deadbeefbe 9 | :04000700deadbeefbd 10 | :04000800deadbeefbc 11 | :04000900deadbeefbb 12 | :04000a00deadbeefba 13 | :04000b00deadbeefb9 14 | :04000c00deadbeefb8 15 | :04000d00deadbeefb7 16 | :04000e00deadbeefb6 17 | :04000f00deadbeefb5 18 | :04001000deadbeefb4 19 | :04001100deadbeefb3 20 | :04001200deadbeefb2 21 | :04001300deadbeefb1 22 | :04001400deadbeefb0 23 | :04001500deadbeefaf 24 | :04001600deadbeefae 25 | :04001700deadbeefad 26 | :04001800deadbeefac 27 | :04001900deadbeefab 28 | :04001a00deadbeefaa 29 | :04001b00deadbeefa9 30 | :04001c00deadbeefa8 31 | :04001d00deadbeefa7 32 | :04001e00deadbeefa6 33 | :04001f00deadbeefa5 34 | :00000001FF 35 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.dat: -------------------------------------------------------------------------------- 1 | @00 2 | deadbeef 3 | deadbeef 4 | deadbeef 5 | deadbeef 6 | deadbeef 7 | deadbeef 8 | deadbeef 9 | deadbeef 10 | deadbeef 11 | deadbeef 12 | deadbeef 13 | deadbeef 14 | deadbeef 15 | deadbeef 16 | deadbeef 17 | deadbeef 18 | deadbeef 19 | deadbeef 20 | deadbeef 21 | deadbeef 22 | deadbeef 23 | deadbeef 24 | deadbeef 25 | deadbeef 26 | deadbeef 27 | deadbeef 28 | deadbeef 29 | deadbeef 30 | deadbeef 31 | deadbeef 32 | deadbeef 33 | deadbeef 34 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.hex: -------------------------------------------------------------------------------- 1 | :020000020000fc 2 | :04000000deadbeefc4 3 | :04000100deadbeefc3 4 | :04000200deadbeefc2 5 | :04000300deadbeefc1 6 | :04000400deadbeefc0 7 | :04000500deadbeefbf 8 | :04000600deadbeefbe 9 | :04000700deadbeefbd 10 | :04000800deadbeefbc 11 | :04000900deadbeefbb 12 | :04000a00deadbeefba 13 | :04000b00deadbeefb9 14 | :04000c00deadbeefb8 15 | :04000d00deadbeefb7 16 | :04000e00deadbeefb6 17 | :04000f00deadbeefb5 18 | :04001000deadbeefb4 19 | :04001100deadbeefb3 20 | :04001200deadbeefb2 21 | :04001300deadbeefb1 22 | :04001400deadbeefb0 23 | :04001500deadbeefaf 24 | :04001600deadbeefae 25 | :04001700deadbeefad 26 | :04001800deadbeefac 27 | :04001900deadbeefab 28 | :04001a00deadbeefaa 29 | :04001b00deadbeefa9 30 | :04001c00deadbeefa8 31 | :04001d00deadbeefa7 32 | :04001e00deadbeefa6 33 | :04001f00deadbeefa5 34 | :00000001FF 35 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/simulation/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/synthesis/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/synthesis/submodules/dnn_accel_system_irq_mapper.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/17.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2017/07/30 $ 17 | // $Author: swbranch $ 18 | 19 | // ------------------------------------------------------- 20 | // Altera IRQ Mapper 21 | // 22 | // Parameters 23 | // NUM_RCVRS : 1 24 | // SENDER_IRW_WIDTH : 32 25 | // IRQ_MAP : 0:5 26 | // 27 | // ------------------------------------------------------- 28 | 29 | `timescale 1 ns / 1 ns 30 | 31 | module dnn_accel_system_irq_mapper 32 | ( 33 | // ------------------- 34 | // Clock & Reset 35 | // ------------------- 36 | input clk, 37 | input reset, 38 | 39 | // ------------------- 40 | // IRQ Receivers 41 | // ------------------- 42 | input receiver0_irq, 43 | 44 | // ------------------- 45 | // Command Source (Output) 46 | // ------------------- 47 | output reg [31 : 0] sender_irq 48 | ); 49 | 50 | 51 | always @* begin 52 | sender_irq = 0; 53 | 54 | sender_irq[5] = receiver0_irq; 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/synthesis/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_a.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/synthesis/submodules/dnn_accel_system_nios2_gen2_0_cpu_rf_ram_b.mif: -------------------------------------------------------------------------------- 1 | WIDTH=32; 2 | DEPTH=32; 3 | 4 | ADDRESS_RADIX=HEX; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 9 | 00 : deadbeef; 10 | 01 : deadbeef; 11 | 02 : deadbeef; 12 | 03 : deadbeef; 13 | 04 : deadbeef; 14 | 05 : deadbeef; 15 | 06 : deadbeef; 16 | 07 : deadbeef; 17 | 08 : deadbeef; 18 | 09 : deadbeef; 19 | 0a : deadbeef; 20 | 0b : deadbeef; 21 | 0c : deadbeef; 22 | 0d : deadbeef; 23 | 0e : deadbeef; 24 | 0f : deadbeef; 25 | 10 : deadbeef; 26 | 11 : deadbeef; 27 | 12 : deadbeef; 28 | 13 : deadbeef; 29 | 14 : deadbeef; 30 | 15 : deadbeef; 31 | 16 : deadbeef; 32 | 17 : deadbeef; 33 | 18 : deadbeef; 34 | 19 : deadbeef; 35 | 1a : deadbeef; 36 | 1b : deadbeef; 37 | 1c : deadbeef; 38 | 1d : deadbeef; 39 | 1e : deadbeef; 40 | 1f : deadbeef; 41 | 42 | END; 43 | -------------------------------------------------------------------------------- /task1/dnn_accel_system/synthesis/submodules/dnn_accel_system_pll_0.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*dnn_accel_system_pll_0*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*dnn_accel_system_pll_0*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*dnn_accel_system_pll_0*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /task1/run_nn.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrisneuf/Deep-Neural-Network-Hardware-Accelerator/8df834fa268973698b0c18b137d8fab0316a1a61/task1/run_nn.elf -------------------------------------------------------------------------------- /task1/task1.amp: -------------------------------------------------------------------------------- 1 | 2 | Nios II 3 | 4 | ../../../../../../intelFPGA_lite/17.1/dnn_accel_system.sopcinfo 5 | ../../../../../../intelFPGA_lite/17.1/output_files/task1.sof 6 | 7 | DE-SoC [USB-1] 8 | nios2_gen2_0 9 | false 10 | jtag_uart_0 11 | 12 | 13 | C Program 14 | 15 | run_nn.c 16 | 17 | 18 | -g -O0 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile 19 | true 20 | false 21 | 22 | 23 | 24 | new_sdram_controller_0.s1 25 | 0x08000000 26 | 0x09FFFFFF 27 | 28 | 29 | 30 | new_sdram_controller_0.s1 31 | 0x0A000000 32 | 0x0BFFFFFF 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /task1/task1.sv: -------------------------------------------------------------------------------- 1 | module task1(input logic CLOCK_50, input logic [3:0] KEY, // KEY[3] is async active-low reset 2 | input logic [9:0] SW, output logic [9:0] LEDR, 3 | output logic DRAM_CLK, output logic DRAM_CKE, 4 | output logic DRAM_CAS_N, output logic DRAM_RAS_N, output logic DRAM_WE_N, 5 | output logic [12:0] DRAM_ADDR, output logic [1:0] DRAM_BA, output logic DRAM_CS_N, 6 | inout [15:0] DRAM_DQ, output logic DRAM_UDQM, output logic DRAM_LDQM, 7 | output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, 8 | output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5); 9 | assign HEX1 = 7'b1111111; 10 | assign HEX2 = 7'b1111111; 11 | assign HEX3 = 7'b1111111; 12 | assign HEX4 = 7'b1111111; 13 | assign HEX5 = 7'b1111111; 14 | assign LEDR[8:0] = 9'b000000000; 15 | dnn_accel_system sys(.clk_clk(CLOCK_50), .reset_reset_n(KEY[3]), 16 | .pll_locked_export(LEDR[9]), 17 | .sdram_clk_clk(DRAM_CLK), 18 | .sdram_addr(DRAM_ADDR), 19 | .sdram_ba(DRAM_BA), 20 | .sdram_cas_n(DRAM_CAS_N), 21 | .sdram_cke(DRAM_CKE), 22 | .sdram_cs_n(DRAM_CS_N), 23 | .sdram_dq(DRAM_DQ), 24 | .sdram_dqm({DRAM_UDQM, DRAM_LDQM}), 25 | .sdram_ras_n(DRAM_RAS_N), 26 | .sdram_we_n(DRAM_WE_N), 27 | .hex_export(HEX0)); 28 | endmodule: task1 29 | 30 | -------------------------------------------------------------------------------- /task2/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /task2/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 15 | 16 | -------------------------------------------------------------------------------- /task2/task2.amp: -------------------------------------------------------------------------------- 1 | 2 | Nios II 3 | 4 | ../../../../../../intelFPGA_lite/17.1/dnn_accel_system.sopcinfo 5 | output_files/task2.sof 6 | 7 | DE-SoC [USB-1] 8 | nios2_gen2_0 9 | false 10 | jtag_uart_0 11 | 12 | 13 | C Program 14 | 15 | wordcopy.c 16 | 17 | 18 | -g -O0 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile 19 | true 20 | false 21 | 22 | 23 | 24 | new_sdram_controller_0.s1 25 | 0x08000000 26 | 0x0BFFFFFF 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /task2/task2.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrisneuf/Deep-Neural-Network-Hardware-Accelerator/8df834fa268973698b0c18b137d8fab0316a1a61/task2/task2.qws -------------------------------------------------------------------------------- /task2/task2.sv: -------------------------------------------------------------------------------- 1 | module task2(input logic CLOCK_50, input logic [3:0] KEY, // KEY[3] is async active-low reset 2 | input logic [9:0] SW, output logic [9:0] LEDR, 3 | output logic DRAM_CLK, output logic DRAM_CKE, 4 | output logic DRAM_CAS_N, output logic DRAM_RAS_N, output logic DRAM_WE_N, 5 | output logic [12:0] DRAM_ADDR, output logic [1:0] DRAM_BA, output logic DRAM_CS_N, 6 | inout [15:0] DRAM_DQ, output logic DRAM_UDQM, output logic DRAM_LDQM, 7 | output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, 8 | output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5); 9 | assign HEX1 = 7'b1111111; 10 | assign HEX2 = 7'b1111111; 11 | assign HEX3 = 7'b1111111; 12 | assign HEX4 = 7'b1111111; 13 | assign HEX5 = 7'b1111111; 14 | assign LEDR[8:0] = 9'b000000000; 15 | dnn_accel_system sys(.clk_clk(CLOCK_50), .reset_reset_n(KEY[3]), 16 | .pll_locked_export(LEDR[9]), 17 | .sdram_clk_clk(DRAM_CLK), 18 | .sdram_addr(DRAM_ADDR), 19 | .sdram_ba(DRAM_BA), 20 | .sdram_cas_n(DRAM_CAS_N), 21 | .sdram_cke(DRAM_CKE), 22 | .sdram_cs_n(DRAM_CS_N), 23 | .sdram_dq(DRAM_DQ), 24 | .sdram_dqm({DRAM_UDQM, DRAM_LDQM}), 25 | .sdram_ras_n(DRAM_RAS_N), 26 | .sdram_we_n(DRAM_WE_N), 27 | .hex_export(HEX0)); 28 | endmodule: task2 29 | 30 | -------------------------------------------------------------------------------- /task2/task2_description.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrisneuf/Deep-Neural-Network-Hardware-Accelerator/8df834fa268973698b0c18b137d8fab0316a1a61/task2/task2_description.txt -------------------------------------------------------------------------------- /task2/wordcopy.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | #define wordcpy_acc (volatile unsigned *) 0x00001040 /* memory copy accelerator */ 4 | #define source (volatile unsigned *) 0x0a004000 5 | #define dest (volatile unsigned *) 0x0a004020 6 | 7 | /* use our memcpy accelerator; pointers must be word-aligned */ 8 | void wordcpy(int *dst, int *src, int n_words) { 9 | *(wordcpy_acc + 1) = (unsigned) dst; 10 | *(wordcpy_acc + 2) = (unsigned) src; 11 | *(wordcpy_acc + 3) = (unsigned) n_words; 12 | *wordcpy_acc = 0; /* start */ 13 | *wordcpy_acc; /* make sure the accelerator is finished */ 14 | } 15 | 16 | void main() { 17 | 18 | *(source) = (int) 10; 19 | *(source + 1) = (int) 11; 20 | *(source + 2) = (int) 12; 21 | *(source + 3) = (int) 13; 22 | *(source + 4) = (int) 0xDEADBEEF; 23 | 24 | wordcpy((int *)dest, (int *)source, 5); 25 | 26 | return; 27 | } 28 | -------------------------------------------------------------------------------- /task2/wordcopy.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrisneuf/Deep-Neural-Network-Hardware-Accelerator/8df834fa268973698b0c18b137d8fab0316a1a61/task2/wordcopy.elf -------------------------------------------------------------------------------- /task3/run_nn.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrisneuf/Deep-Neural-Network-Hardware-Accelerator/8df834fa268973698b0c18b137d8fab0316a1a61/task3/run_nn.elf -------------------------------------------------------------------------------- /task3/task3.amp: -------------------------------------------------------------------------------- 1 | 2 | Nios II 3 | 4 | ../../../../../../intelFPGA_lite/17.1/dnn_accel_system.sopcinfo 5 | ../task2/output_files/task2.sof 6 | 7 | DE-SoC [USB-1] 8 | nios2_gen2_0 9 | false 10 | jtag_uart_0 11 | 12 | 13 | C Program 14 | 15 | ../task1/run_nn.c 16 | 17 | 18 | -g -O0 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile 19 | true 20 | false 21 | 22 | 23 | 24 | new_sdram_controller_0.s1 25 | 0x08000000 26 | 0x09FFFFFF 27 | 28 | 29 | 30 | new_sdram_controller_0.s1 31 | 0x0A000000 32 | 0x0BFFFFFF 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /task3/task3.sv: -------------------------------------------------------------------------------- 1 | module task3(input logic CLOCK_50, input logic [3:0] KEY, // KEY[3] is async active-low reset 2 | input logic [9:0] SW, output logic [9:0] LEDR, 3 | output logic DRAM_CLK, output logic DRAM_CKE, 4 | output logic DRAM_CAS_N, output logic DRAM_RAS_N, output logic DRAM_WE_N, 5 | output logic [12:0] DRAM_ADDR, output logic [1:0] DRAM_BA, output logic DRAM_CS_N, 6 | inout [15:0] DRAM_DQ, output logic DRAM_UDQM, output logic DRAM_LDQM, 7 | output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, 8 | output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5); 9 | assign HEX1 = 7'b1111111; 10 | assign HEX2 = 7'b1111111; 11 | assign HEX3 = 7'b1111111; 12 | assign HEX4 = 7'b1111111; 13 | assign HEX5 = 7'b1111111; 14 | assign LEDR[8:0] = 9'b000000000; 15 | dnn_accel_system sys(.clk_clk(CLOCK_50), .reset_reset_n(KEY[3]), 16 | .pll_locked_export(LEDR[9]), 17 | .sdram_clk_clk(DRAM_CLK), 18 | .sdram_addr(DRAM_ADDR), 19 | .sdram_ba(DRAM_BA), 20 | .sdram_cas_n(DRAM_CAS_N), 21 | .sdram_cke(DRAM_CKE), 22 | .sdram_cs_n(DRAM_CS_N), 23 | .sdram_dq(DRAM_DQ), 24 | .sdram_dqm({DRAM_UDQM, DRAM_LDQM}), 25 | .sdram_ras_n(DRAM_RAS_N), 26 | .sdram_we_n(DRAM_WE_N), 27 | .hex_export(HEX0)); 28 | endmodule: task3 29 | 30 | -------------------------------------------------------------------------------- /unsaved/unsaved.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2017 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 64) 24 | (text "unsaved" (rect 17 -1 51 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 48 20 60)(font "Arial" )) 26 | (drawing 27 | (text " system " (rect 45 48 138 106)(font "Arial" )) 28 | (line (pt 16 32)(pt 80 32)(line_width 1)) 29 | (line (pt 80 32)(pt 80 48)(line_width 1)) 30 | (line (pt 16 48)(pt 80 48)(line_width 1)) 31 | (line (pt 16 32)(pt 16 48)(line_width 1)) 32 | (line (pt 0 0)(pt 80 0)(line_width 1)) 33 | (line (pt 80 0)(pt 80 64)(line_width 1)) 34 | (line (pt 0 64)(pt 80 64)(line_width 1)) 35 | (line (pt 0 0)(pt 0 64)(line_width 1)) 36 | ) 37 | ) 38 | -------------------------------------------------------------------------------- /unsaved/unsaved.cmp: -------------------------------------------------------------------------------- 1 | component unsaved is 2 | end component unsaved; 3 | 4 | -------------------------------------------------------------------------------- /unsaved/unsaved_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module unsaved ( 3 | ); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /unsaved/unsaved_inst.v: -------------------------------------------------------------------------------- 1 | unsaved u0 ( 2 | ); 3 | 4 | -------------------------------------------------------------------------------- /unsaved/unsaved_inst.vhd: -------------------------------------------------------------------------------- 1 | component unsaved is 2 | end component unsaved; 3 | 4 | u0 : component unsaved 5 | port map ( 6 | ); 7 | 8 | --------------------------------------------------------------------------------