├── .gitignore ├── .gitlab-ci.yml ├── .setup ├── LICENSE ├── README.md ├── assets ├── plasma.jpg ├── time-sleuth-hw.jpg └── time-sleuth.jpg ├── build ├── compile ├── lagtester.qpf ├── lagtester.qsf ├── lagtester.sdc ├── program ├── report-timing ├── report-timing.tcl └── source ├── char_rom ├── char_rom.v ├── font │ ├── 8x16-font-digits.v │ ├── 8x16-font.png │ ├── 8x16-font.v │ ├── README │ ├── deco-8x16.png │ ├── display-8x16.png │ ├── old.v │ ├── predef │ │ └── lagdisplay.v │ ├── rcopt2-8x16.png │ └── string-to-pixels.py ├── lagdisplay.v └── resolution.v ├── config └── video_modes.v ├── configuration.v ├── defines.v ├── generated ├── slots.v └── video-modes.v ├── lagtester.v ├── measure.v ├── misc ├── Binary_to_BCD.v ├── Flag_CrossDomain.v ├── bcdcounter.v ├── data_cross.v ├── data_fifo.qip ├── data_fifo.v ├── delayline.v └── edge_detect.v ├── pll ├── config │ ├── 148_5_Mhz.mif │ ├── 148_5_Mhz.v │ ├── 27_MHz.mif │ ├── 27_MHz.v │ ├── 74_25_MHz.mif │ ├── 74_25_MHz.v │ ├── VGA.mif │ ├── create_from_mif.pl │ ├── default.mif │ └── default.v ├── pll.ppf ├── pll.qip ├── pll.v ├── pll_bb.v ├── pll_main.v ├── pll_reconf.qip ├── pll_reconf.v └── pll_reconf_rom.v ├── sensor.v ├── tfp410 ├── I2C.v ├── i2c_master.vhd └── tfp410.v ├── typedef.v ├── video.v └── video ├── textgen.v ├── timingsgen.v ├── video_config.v └── videogen.v /.gitignore: -------------------------------------------------------------------------------- 1 | db/ 2 | incremental_db/ 3 | output_files/ 4 | greybox_tmp/ 5 | source/osc/osc.sopcinfo 6 | .environment 7 | notes 8 | .vscode/ 9 | *.BAK.v 10 | *.rbf 11 | *.vvp 12 | source/.qsys_edit/ 13 | source/greybox_tmp/cbx_args.txt 14 | *.sopcinfo 15 | .qsys_edit/preferences.xml 16 | .qsys_edit/filters.xml 17 | source/pll/greybox_tmp/ 18 | *.qws 19 | source/Untitled-* 20 | test/ -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | stages: 2 | - build-fpga 3 | #- deploy 4 | 5 | fpga-firmware: 6 | stage: build-fpga 7 | script: 8 | - script -qfc "$(printf "%q %q " "/usr/local/bin/quartus_wrapper" "quartus_sh --flow compile lagtester.qpf")" /dev/null 9 | #- script -qfc "$(printf "%q %q " "/usr/local/bin/quartus_wrapper" "quartus_cpf -c lagtester.cof")" /dev/null 10 | - cp output_files/lagtester.pof . 11 | artifacts: 12 | name: time-sleuth-firmware 13 | paths: 14 | - lagtester.pof 15 | # - output_files/lagtester*.sof 16 | # - output_files/lagtester*.rpd 17 | # - output_files/lagtester*.map 18 | tags: 19 | - quartus-lite 20 | only: 21 | - develop 22 | - master 23 | - experimental 24 | - tags 25 | 26 | # firmware-publish: 27 | # stage: deploy 28 | # script: create-index-html-ps2 29 | # artifacts: 30 | # expire_in: 1 sec 31 | # dependencies: 32 | # - esp-firmware 33 | # tags: 34 | # - index-gen 35 | # only: 36 | # - develop 37 | # - master 38 | -------------------------------------------------------------------------------- /.setup: -------------------------------------------------------------------------------- 1 | 2 | function docker_run { 3 | docker run --rm -it \ 4 | -e "JTAG_SERVER=$JTAG_SERVER" \ 5 | -e "JTAG_PASSWD=$JTAG_PASSWD" \ 6 | -v $(pwd):/build \ 7 | chriz2600/quartus-lite:latest \ 8 | /usr/local/bin/quartus_wrapper "$@" 9 | } 10 | 11 | # add JTAG_SERVER and JTAG_PASSWD into .environment as needed 12 | if [ -f ".environment" ] ; then 13 | source ".environment" 14 | fi 15 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 chriz2600 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Time Sleuth - Open Source Lag Tester 2 | 3 | ## Hardware 4 | 5 | Hardware by [**citrus3000psi**](https://twitter.com/citrus3000psi) 6 | 7 | Kicad project can be found here: [github.com/citrus3000psi/Time-Sleuth](https://github.com/citrus3000psi/Time-Sleuth). 8 | 9 | ## Firmware 10 | 11 | Latest Firmware: [time-sleuth-firmware.zip](https://gitlab.com/chriz2600/lagtester/-/jobs/artifacts/master/download?job=fpga-firmware) 12 | 13 | Automatic builds are done with [gitlab-ci](https://gitlab.com/chriz2600/time-sleuth/pipelines). 14 | 15 | To program the firmware, a USB Blaster programmer is needed, e.g. from [ebay](https://www.ebay.com/i/272455039767?chn=ps) 16 | 17 | Software to program the FPGA: 18 | 19 | - [Linux 64 Bit](http://download.altera.com/akdlm/software/acdsinst/18.1std/625/ib_installers/QuartusProgrammerSetup-18.1.0.625-linux.run) 20 | 21 | - [Windows 64 Bit](http://download.altera.com/akdlm/software/acdsinst/18.1std/625/ib_installers/QuartusProgrammerSetup-18.1.0.625-windows.exe) 22 | 23 | - [Windows 32 Bit](http://download.altera.com/akdlm/software/acdsinst/18.1std/625/ib_installers/QuartusProgrammerSetup-18.1.0.625-windows32.exe) 24 | 25 | ## Operation 26 | 27 | Time Sleuth generates a flicker pattern and then measures the time it takes from the start of the first pattern to the moment it shows up on screen using a photo transistor. 28 | 29 | 30 | 31 | The counter measuring the lag starts at the first line of the first field. So if you're using a display, which generates the image from top to bottom (line by line, as LCD/OLED/CRT monitors/TVs will do), the first field will give you the processing lag of the screen, while the second and third field will also include the lag inherent to the line by line drawing of the image. 32 | 33 | There are 4 values displayed on the screen: 34 | 35 | - `current` 36 | 37 | Shows the value of the last measurement. 38 | 39 | - `min/max` 40 | 41 | Minimum and maximum value within the last averaging period. These values are reset, when a new averaging period starts. 42 | 43 | - `average` 44 | 45 | Average value of the last **16** measurements. Most LED backlit LCD screens are using pulse width modulation for brightness adjustment and the PWM duty cycle of the backlight is often not 100% even if brightness is. So the current readings are often jumping, so `average` gives you the mean lag. 46 | 47 | 48 | 49 | - ***LED*** 50 | 51 | Flashes, when a measurement was performed. 52 | 53 | - ***Switch*** 54 | 55 | Switches between 1080p (`1`), 720p (`2`) and VGA (`3`) output. 56 | 57 | *VGA will be changed to 480i in a future firmware revision* 58 | 59 | - ***10pin JTAG connection*** 60 | 61 | JTAG interface for updateing the firmware using an USB Blaster. 62 | 63 | - ***Crosshair*** 64 | 65 | The crosshair indicates the position of the photo transistor on the bottom of the device and helps aligning over the measurement fields. 66 | 67 | ## Notes 68 | 69 | - While the time to display a frame in 60Hz is **16.6 ms** the display time for 1080p from the first visible line to the last visible line is only **16 ms** and **14.6 ms** from the middle of the first field to the middle of the last field. 70 | 71 | - Plasma displays are not displaying the image line by line, so you will see nearly the same amount of lag on all fields. 72 | 73 |
74 | *Time Sleuth on a Panasonic 42VT30 Plasma* 75 | -------------------------------------------------------------------------------- /assets/plasma.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/assets/plasma.jpg -------------------------------------------------------------------------------- /assets/time-sleuth-hw.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/assets/time-sleuth-hw.jpg -------------------------------------------------------------------------------- /assets/time-sleuth.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/assets/time-sleuth.jpg -------------------------------------------------------------------------------- /build: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd $(dirname $0) 4 | 5 | ./compile lagtester && \ 6 | md5sum output_files/lagtester.pof && \ 7 | ls -alF output_files/lagtester.pof && \ 8 | cat output_files/lagtester.fit.rpt | grep '; Total logic elements ;' 9 | -------------------------------------------------------------------------------- /compile: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd $(dirname $0) 4 | 5 | source .setup 6 | 7 | if [ -z "$1" ] ; then 8 | echo "usage: $0 <.qpf>" 9 | exit 1 10 | fi 11 | 12 | docker_run quartus_sh --flow compile "$@" 13 | -------------------------------------------------------------------------------- /lagtester.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 21 | # Date created = 02:13:21 January 18, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.1" 26 | DATE = "02:13:21 January 18, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "lagtester" 31 | -------------------------------------------------------------------------------- /lagtester.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 21 | # Date created = 02:13:21 January 18, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # lagtester_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | set_global_assignment -name FAMILY "MAX 10" 39 | set_global_assignment -name DEVICE 10M02SCE144C8G 40 | set_global_assignment -name TOP_LEVEL_ENTITY lagtester 41 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 42 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:13:21 JANUARY 18, 2019" 43 | set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" 44 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 45 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 46 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 47 | set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" 48 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 49 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 50 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 51 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 52 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 53 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON 54 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "50.0 %" 55 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 56 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 57 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 58 | 59 | ######################################################## 60 | # timing optimization 61 | ######################################################## 62 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 63 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 64 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 65 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 66 | 67 | #set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 16.0 68 | #set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 8.0 69 | #set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED 70 | #set_global_assignment -name FITTER_EFFORT "AUTO FIT" 71 | #set_global_assignment -name SEED 12 72 | #set_global_assignment -name AUTO_RAM_RECOGNITION Off 73 | #set_global_assignment -name AUTO_ROM_RECOGNITION Off 74 | 75 | ######################################################## 76 | # source files 77 | ######################################################## 78 | set_global_assignment -name SDC_FILE lagtester.sdc 79 | set_global_assignment -name VERILOG_FILE source/lagtester.v 80 | set_global_assignment -name QIP_FILE source/pll/pll.qip 81 | set_global_assignment -name QIP_FILE source/pll/pll_reconf.qip 82 | set_global_assignment -name QIP_FILE source/misc/data_fifo.qip 83 | set_global_assignment -name VERILOG_FILE source/pll/pll_main.v 84 | set_global_assignment -name VERILOG_FILE source/pll/pll_reconf_rom.v 85 | set_global_assignment -name VERILOG_FILE source/misc/edge_detect.v 86 | set_global_assignment -name VERILOG_FILE source/misc/data_cross.v 87 | set_global_assignment -name VERILOG_FILE source/misc/delayline.v 88 | set_global_assignment -name VERILOG_FILE source/misc/Flag_CrossDomain.v 89 | set_global_assignment -name VERILOG_FILE source/misc/bcdcounter.v 90 | set_global_assignment -name VERILOG_FILE source/misc/Binary_to_BCD.v 91 | set_global_assignment -name VERILOG_FILE source/sensor.v 92 | set_global_assignment -name VERILOG_FILE source/configuration.v 93 | set_global_assignment -name VERILOG_FILE source/measure.v 94 | set_global_assignment -name VERILOG_FILE source/video.v 95 | set_global_assignment -name VERILOG_FILE source/video/video_config.v 96 | set_global_assignment -name VERILOG_FILE source/video/timingsgen.v 97 | set_global_assignment -name VERILOG_FILE source/video/textgen.v 98 | set_global_assignment -name VERILOG_FILE source/video/videogen.v 99 | set_global_assignment -name VERILOG_FILE source/typedef.v 100 | set_global_assignment -name VERILOG_FILE source/tfp410/tfp410.v 101 | set_global_assignment -name VERILOG_FILE source/tfp410/I2C.v 102 | set_global_assignment -name VHDL_FILE source/tfp410/i2c_master.vhd 103 | set_global_assignment -name VERILOG_FILE source/char_rom/char_rom.v 104 | set_global_assignment -name VERILOG_FILE source/char_rom/resolution.v 105 | set_global_assignment -name VERILOG_FILE source/char_rom/lagdisplay.v 106 | 107 | ######################################################## 108 | # pin assignments 109 | ######################################################## 110 | set_location_assignment PIN_27 -to clock 111 | set_location_assignment PIN_33 -to DVI_CLOCK 112 | 113 | set_location_assignment PIN_6 -to RES_CONFIG[0] 114 | set_location_assignment PIN_5 -to RES_CONFIG[1] 115 | set_location_assignment PIN_4 -to RES_CONFIG[2] 116 | set_location_assignment PIN_8 -to RES_CONFIG[3] 117 | set_location_assignment PIN_9 -to RES_CONFIG[4] 118 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[0] 119 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[1] 120 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[2] 121 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[3] 122 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RES_CONFIG[4] 123 | 124 | set_location_assignment PIN_40 -to TFP410_reset 125 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TFP410_reset 126 | 127 | set_location_assignment PIN_115 -to LED 128 | 129 | set_location_assignment PIN_79 -to DVI_RED[7] 130 | set_location_assignment PIN_78 -to DVI_RED[6] 131 | set_location_assignment PIN_76 -to DVI_RED[5] 132 | set_location_assignment PIN_75 -to DVI_RED[4] 133 | set_location_assignment PIN_74 -to DVI_RED[3] 134 | set_location_assignment PIN_70 -to DVI_RED[2] 135 | set_location_assignment PIN_69 -to DVI_RED[1] 136 | set_location_assignment PIN_68 -to DVI_RED[0] 137 | 138 | set_location_assignment PIN_67 -to DVI_GREEN[7] 139 | set_location_assignment PIN_65 -to DVI_GREEN[6] 140 | set_location_assignment PIN_63 -to DVI_GREEN[5] 141 | set_location_assignment PIN_62 -to DVI_GREEN[4] 142 | set_location_assignment PIN_61 -to DVI_GREEN[3] 143 | set_location_assignment PIN_60 -to DVI_GREEN[2] 144 | set_location_assignment PIN_59 -to DVI_GREEN[1] 145 | set_location_assignment PIN_54 -to DVI_GREEN[0] 146 | 147 | set_location_assignment PIN_53 -to DVI_BLUE[7] 148 | set_location_assignment PIN_52 -to DVI_BLUE[6] 149 | set_location_assignment PIN_51 -to DVI_BLUE[5] 150 | set_location_assignment PIN_50 -to DVI_BLUE[4] 151 | set_location_assignment PIN_49 -to DVI_BLUE[3] 152 | set_location_assignment PIN_48 -to DVI_BLUE[2] 153 | set_location_assignment PIN_47 -to DVI_BLUE[1] 154 | set_location_assignment PIN_46 -to DVI_BLUE[0] 155 | 156 | set_location_assignment PIN_44 -to DVI_DE 157 | set_location_assignment PIN_42 -to DVI_HSYNC 158 | set_location_assignment PIN_41 -to DVI_VSYNC 159 | 160 | set_location_assignment PIN_39 -to SDA 161 | # Error (18496): The Output SCL in pin location 28 (pad_956) is too close to PLL clock input pin (clock) in pin location 27 (pad_0) File: /build/source/lagtester.v Line: 2 162 | #set_location_assignment PIN_28 -to SCL 163 | set_location_assignment PIN_24 -to SCL 164 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDA 165 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SCL 166 | 167 | set_location_assignment PIN_7 -to SENSOR 168 | set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to SENSOR 169 | 170 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clock 171 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_CLOCK 172 | set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RES_CONFIG[0] 173 | set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RES_CONFIG[1] 174 | set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RES_CONFIG[2] 175 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[7] 176 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[6] 177 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[5] 178 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[4] 179 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[3] 180 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[2] 181 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[1] 182 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_RED[0] 183 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[7] 184 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[6] 185 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[5] 186 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[4] 187 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[3] 188 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[2] 189 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[1] 190 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_GREEN[0] 191 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[7] 192 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[6] 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[5] 194 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[4] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[3] 196 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[2] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[1] 198 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_BLUE[0] 199 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_DE 200 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_HSYNC 201 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DVI_VSYNC 202 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDA 203 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SCL 204 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TFP410_reset 205 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED 206 | -------------------------------------------------------------------------------- /lagtester.sdc: -------------------------------------------------------------------------------- 1 | ################## 2 | # clocks # 3 | ################## 4 | create_clock -period 27Mhz -name clock [get_ports clock] 5 | create_generated_clock -multiply_by 11 -divide_by 4 -name data_clock -source {pll|pll|altpll_component|auto_generated|pll1|inclk[0]} {pll|pll|altpll_component|auto_generated|pll1|clk[0]} 6 | create_generated_clock -multiply_by 11 -divide_by 2 -name output_clock -source {pll|pll|altpll_component|auto_generated|pll1|inclk[0]} {pll|pll|altpll_component|auto_generated|pll1|clk[1]} 7 | create_generated_clock -name bcd_trigger -source [get_ports clock] -divide_by 27 -multiply_by 1 { measure|counter_trigger } 8 | 9 | derive_pll_clocks 10 | derive_clock_uncertainty 11 | 12 | ################## 13 | # false paths # 14 | ################## 15 | set_false_path -from [get_ports {RES_CONFIG*}] 16 | 17 | set_clock_groups -exclusive -group clock -group data_clock 18 | set_clock_groups -exclusive -group clock -group output_clock 19 | 20 | ################## 21 | # output delays # 22 | ################## 23 | set tSU 1.5 24 | set tH 1.6 25 | set adv_clock_delay 0.0 26 | set dvi_outputs [get_ports {DVI_RED* DVI_GREEN* DVI_BLUE* DVI_DE DVI_HSYNC DVI_VSYNC}] 27 | set_output_delay -clock output_clock -reference_pin [get_ports DVI_CLOCK] -max [expr $tSU - $adv_clock_delay] $dvi_outputs 28 | set_output_delay -clock output_clock -reference_pin [get_ports DVI_CLOCK] -min [expr 0 - $tH - $adv_clock_delay ] $dvi_outputs 29 | set_false_path -setup -rise_from [get_clocks data_clock] -fall_to [get_clocks output_clock] 30 | set_false_path -setup -fall_from [get_clocks data_clock] -rise_to [get_clocks output_clock] 31 | set_false_path -hold -rise_from [get_clocks data_clock] -rise_to [get_clocks output_clock] 32 | set_false_path -hold -fall_from [get_clocks data_clock] -fall_to [get_clocks output_clock] 33 | set_false_path -to [remove_from_collection [all_outputs] "$dvi_outputs"] 34 | -------------------------------------------------------------------------------- /program: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd $(dirname $0) 4 | 5 | source .setup 6 | 7 | if [ "$1" ] ; then 8 | PGM="$1" 9 | fi 10 | 11 | PROGRAMMER=$(docker_run jtagconfig --enum | tr -d '\r' | head -n 1 | sed 's/1) //') 12 | docker_run quartus_pgm -c "$PROGRAMMER" -m jtag -o "pv;${PGM}" 13 | -------------------------------------------------------------------------------- /report-timing: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd $(dirname $0) 4 | 5 | source .setup 6 | 7 | docker_run quartus_sta -t report-timing.tcl 8 | -------------------------------------------------------------------------------- /report-timing.tcl: -------------------------------------------------------------------------------- 1 | project_open lagtester 2 | 3 | create_timing_netlist -model slow 4 | read_sdc 5 | update_timing_netlist 6 | 7 | check_timing -include {latches loops} 8 | 9 | report_timing \ 10 | -setup \ 11 | -npaths 2000 \ 12 | -detail full_path \ 13 | -panel_name {Report Timing} \ 14 | -multi_corner \ 15 | -file "output_files/worst_case_setup_paths.rpt" 16 | 17 | report_min_pulse_width \ 18 | -nworst 2000 \ 19 | -detail full_path \ 20 | -panel_name {Report Timing} \ 21 | -multi_corner \ 22 | -file "output_files/worst_case_min_pulse_width.rpt" 23 | 24 | set domain_list [get_clock_fmax_info] 25 | foreach domain $domain_list { 26 | set name [lindex $domain 0] 27 | set fmax [lindex $domain 1] 28 | set restricted_fmax [lindex $domain 2] 29 | puts "Clock $name : Fmax = $fmax (Restricted Fmax = \ 30 | $restricted_fmax)" 31 | } 32 | 33 | project_close 34 | -------------------------------------------------------------------------------- /source/char_rom/char_rom.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | module char_rom ( 4 | input clock, 5 | input [7:0] address, 6 | output [7:0] q 7 | ); 8 | 9 | reg[7:0] q_reg; 10 | reg[7:0] q_reg_2; 11 | 12 | assign q = q_reg_2; 13 | 14 | always @(posedge clock) begin 15 | case (address) 16 | `include "font/8x16-font-digits.v" 17 | endcase 18 | q_reg_2 <= q_reg; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /source/char_rom/font/8x16-font-digits.v: -------------------------------------------------------------------------------- 1 | 0000: q_reg <= 8'b00000000; 2 | 0001: q_reg <= 8'b00000000; 3 | 0002: q_reg <= 8'b00111100; 4 | 0003: q_reg <= 8'b01000010; 5 | 0004: q_reg <= 8'b01000010; 6 | 0005: q_reg <= 8'b01000110; 7 | 0006: q_reg <= 8'b01001010; 8 | 0007: q_reg <= 8'b01010010; 9 | 0008: q_reg <= 8'b01100010; 10 | 0009: q_reg <= 8'b01000010; 11 | 0010: q_reg <= 8'b01000010; 12 | 0011: q_reg <= 8'b01000010; 13 | 0012: q_reg <= 8'b00111100; 14 | 0013: q_reg <= 8'b00000000; 15 | 0014: q_reg <= 8'b00000000; 16 | 0015: q_reg <= 8'b00000000; 17 | 0016: q_reg <= 8'b00000000; 18 | 0017: q_reg <= 8'b00000000; 19 | 0018: q_reg <= 8'b00011000; 20 | 0019: q_reg <= 8'b00101000; 21 | 0020: q_reg <= 8'b00001000; 22 | 0021: q_reg <= 8'b00001000; 23 | 0022: q_reg <= 8'b00001000; 24 | 0023: q_reg <= 8'b00001000; 25 | 0024: q_reg <= 8'b00001000; 26 | 0025: q_reg <= 8'b00001000; 27 | 0026: q_reg <= 8'b00001000; 28 | 0027: q_reg <= 8'b00001000; 29 | 0028: q_reg <= 8'b00111110; 30 | 0029: q_reg <= 8'b00000000; 31 | 0030: q_reg <= 8'b00000000; 32 | 0031: q_reg <= 8'b00000000; 33 | 0032: q_reg <= 8'b00000000; 34 | 0033: q_reg <= 8'b00000000; 35 | 0034: q_reg <= 8'b00111100; 36 | 0035: q_reg <= 8'b01000010; 37 | 0036: q_reg <= 8'b00000010; 38 | 0037: q_reg <= 8'b00000010; 39 | 0038: q_reg <= 8'b00000010; 40 | 0039: q_reg <= 8'b00000010; 41 | 0040: q_reg <= 8'b00111100; 42 | 0041: q_reg <= 8'b01000000; 43 | 0042: q_reg <= 8'b01000000; 44 | 0043: q_reg <= 8'b01000000; 45 | 0044: q_reg <= 8'b01111110; 46 | 0045: q_reg <= 8'b00000000; 47 | 0046: q_reg <= 8'b00000000; 48 | 0047: q_reg <= 8'b00000000; 49 | 0048: q_reg <= 8'b00000000; 50 | 0049: q_reg <= 8'b00000000; 51 | 0050: q_reg <= 8'b00111100; 52 | 0051: q_reg <= 8'b01000010; 53 | 0052: q_reg <= 8'b00000010; 54 | 0053: q_reg <= 8'b00000010; 55 | 0054: q_reg <= 8'b00001100; 56 | 0055: q_reg <= 8'b00000010; 57 | 0056: q_reg <= 8'b00000010; 58 | 0057: q_reg <= 8'b00000010; 59 | 0058: q_reg <= 8'b00000010; 60 | 0059: q_reg <= 8'b01000010; 61 | 0060: q_reg <= 8'b00111100; 62 | 0061: q_reg <= 8'b00000000; 63 | 0062: q_reg <= 8'b00000000; 64 | 0063: q_reg <= 8'b00000000; 65 | 0064: q_reg <= 8'b00000000; 66 | 0065: q_reg <= 8'b00000000; 67 | 0066: q_reg <= 8'b00001000; 68 | 0067: q_reg <= 8'b00001000; 69 | 0068: q_reg <= 8'b00011000; 70 | 0069: q_reg <= 8'b00011000; 71 | 0070: q_reg <= 8'b00101000; 72 | 0071: q_reg <= 8'b00101000; 73 | 0072: q_reg <= 8'b01001000; 74 | 0073: q_reg <= 8'b01001000; 75 | 0074: q_reg <= 8'b01111110; 76 | 0075: q_reg <= 8'b00001000; 77 | 0076: q_reg <= 8'b00001000; 78 | 0077: q_reg <= 8'b00000000; 79 | 0078: q_reg <= 8'b00000000; 80 | 0079: q_reg <= 8'b00000000; 81 | 0080: q_reg <= 8'b00000000; 82 | 0081: q_reg <= 8'b00000000; 83 | 0082: q_reg <= 8'b01111110; 84 | 0083: q_reg <= 8'b01000000; 85 | 0084: q_reg <= 8'b01000000; 86 | 0085: q_reg <= 8'b01000000; 87 | 0086: q_reg <= 8'b01111100; 88 | 0087: q_reg <= 8'b00000010; 89 | 0088: q_reg <= 8'b00000010; 90 | 0089: q_reg <= 8'b00000010; 91 | 0090: q_reg <= 8'b00000010; 92 | 0091: q_reg <= 8'b01000010; 93 | 0092: q_reg <= 8'b00111100; 94 | 0093: q_reg <= 8'b00000000; 95 | 0094: q_reg <= 8'b00000000; 96 | 0095: q_reg <= 8'b00000000; 97 | 0096: q_reg <= 8'b00000000; 98 | 0097: q_reg <= 8'b00000000; 99 | 0098: q_reg <= 8'b00111100; 100 | 0099: q_reg <= 8'b01000000; 101 | 0100: q_reg <= 8'b01000000; 102 | 0101: q_reg <= 8'b01000000; 103 | 0102: q_reg <= 8'b01111100; 104 | 0103: q_reg <= 8'b01000010; 105 | 0104: q_reg <= 8'b01000010; 106 | 0105: q_reg <= 8'b01000010; 107 | 0106: q_reg <= 8'b01000010; 108 | 0107: q_reg <= 8'b01000010; 109 | 0108: q_reg <= 8'b00111100; 110 | 0109: q_reg <= 8'b00000000; 111 | 0110: q_reg <= 8'b00000000; 112 | 0111: q_reg <= 8'b00000000; 113 | 0112: q_reg <= 8'b00000000; 114 | 0113: q_reg <= 8'b00000000; 115 | 0114: q_reg <= 8'b01111110; 116 | 0115: q_reg <= 8'b00000010; 117 | 0116: q_reg <= 8'b00000010; 118 | 0117: q_reg <= 8'b00000100; 119 | 0118: q_reg <= 8'b00000100; 120 | 0119: q_reg <= 8'b00001000; 121 | 0120: q_reg <= 8'b00001000; 122 | 0121: q_reg <= 8'b00010000; 123 | 0122: q_reg <= 8'b00010000; 124 | 0123: q_reg <= 8'b00010000; 125 | 0124: q_reg <= 8'b00010000; 126 | 0125: q_reg <= 8'b00000000; 127 | 0126: q_reg <= 8'b00000000; 128 | 0127: q_reg <= 8'b00000000; 129 | 0128: q_reg <= 8'b00000000; 130 | 0129: q_reg <= 8'b00000000; 131 | 0130: q_reg <= 8'b00111100; 132 | 0131: q_reg <= 8'b01000010; 133 | 0132: q_reg <= 8'b01000010; 134 | 0133: q_reg <= 8'b01000010; 135 | 0134: q_reg <= 8'b00111100; 136 | 0135: q_reg <= 8'b01000010; 137 | 0136: q_reg <= 8'b01000010; 138 | 0137: q_reg <= 8'b01000010; 139 | 0138: q_reg <= 8'b01000010; 140 | 0139: q_reg <= 8'b01000010; 141 | 0140: q_reg <= 8'b00111100; 142 | 0141: q_reg <= 8'b00000000; 143 | 0142: q_reg <= 8'b00000000; 144 | 0143: q_reg <= 8'b00000000; 145 | 0144: q_reg <= 8'b00000000; 146 | 0145: q_reg <= 8'b00000000; 147 | 0146: q_reg <= 8'b00111100; 148 | 0147: q_reg <= 8'b01000010; 149 | 0148: q_reg <= 8'b01000010; 150 | 0149: q_reg <= 8'b01000010; 151 | 0150: q_reg <= 8'b01000010; 152 | 0151: q_reg <= 8'b01000010; 153 | 0152: q_reg <= 8'b00111110; 154 | 0153: q_reg <= 8'b00000010; 155 | 0154: q_reg <= 8'b00000010; 156 | 0155: q_reg <= 8'b00000010; 157 | 0156: q_reg <= 8'b00111100; 158 | 0157: q_reg <= 8'b00000000; 159 | 0158: q_reg <= 8'b00000000; 160 | 0159: q_reg <= 8'b00000000; 161 | -------------------------------------------------------------------------------- /source/char_rom/font/8x16-font.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/source/char_rom/font/8x16-font.png -------------------------------------------------------------------------------- /source/char_rom/font/README: -------------------------------------------------------------------------------- 1 | Font reference: http://uzebox.org/wiki/Font_Bitmaps#8x16 2 | -------------------------------------------------------------------------------- /source/char_rom/font/deco-8x16.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/source/char_rom/font/deco-8x16.png -------------------------------------------------------------------------------- /source/char_rom/font/display-8x16.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/source/char_rom/font/display-8x16.png -------------------------------------------------------------------------------- /source/char_rom/font/predef/lagdisplay.v: -------------------------------------------------------------------------------- 1 | case (addr) 2 | 00: q_reg <= 512'b_00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; 3 | 01: q_reg <= 512'b_00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; 4 | 02: q_reg <= 512'b_01000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; 5 | 03: q_reg <= 512'b_01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; 6 | 04: q_reg <= 512'b_01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; 7 | 05: q_reg <= 512'b_01000000001110000011110000000000001100000111100000000000011010000011100000000000000111000100010000011100000111000011100001111000001110000000000000000000000000000000000000000000000000000000000000000000011010000011000001111000000001000110100000111000010001000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000001110000100010000111000000111000011100000111100001110000000000000000000000000000000000000000000000000000000000000000000; 8 | 06: q_reg <= 512'b_01000000000001000100010000000000000100000100010000000000010101000100000000010000001000000100010000100000001000000100010001000100000100000001000000000000000000000000000000000000000000000000000000000000010101000001000001000100000001000101010000000100001010000001000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000100010001000100001000000000010001000100010001000001000000000000000000000000000000000000000000000000000000000000; 9 | 07: q_reg <= 512'b_01000000000001000100010000000000000100000100010000000000010101000100000000000000001000000100010000100000001000000100010001000100000100000000000000000000001111100011111000111110000000000011111000111110010101000001000001000100000010000101010000000100001010000000000000000000001111100011111000111110000000000011111000111110000000000000100000000000001111100011111000111110000000000011111000111110000001000100010001000100001000000000010001000100010001000000000000000000001111100011111000111110000000000011111000111110; 10 | 08: q_reg <= 512'b_01000000001111000100010000000000000100000100010000000000010101000011100000000000001000000100010000100000001000000111100001000100000100000000000000000000000000000000000000000000000000000000000000000000010101000001000001000100000010000101010000111100000100000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000001111000100010001111000001000000011110001000100011110000000000000000000000000000000000000000000000000000000000000000000; 11 | 09: q_reg <= 512'b_01000000010001000100010000000000000100000100010000000000010101000000010000000000001000000100010000100000001000000100000001000100000100000000000000000000000000000000000000000000000000000000000000000000010101000001000001000100000100000101010001000100000100000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000010001000010100001000000001000000100010001000100010000000000000000000000000000000000000000000000000000000000000000000000; 12 | 10: q_reg <= 512'b_01000000010001000100010000000000000100000100010000000000010101000000010000000000001000000100010000100000001000000100000001000100000100000000000000000000000000000000000000000000000000000000000000000000010101000001000001000100000100000101010001000100001010000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000010001000010100001000000001000000100010001000100010000000000000000000000000000000000000000000000000000000000000000000000; 13 | 11: q_reg <= 512'b_01000000010001000100010000000000000100000100010000000000010101000000010000000000001000000100010000100000001000000100000001000100000100000000000000000000000000000000000000000000000000000000000000000000010101000001000001000100001000000101010001000100001010000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000010001000001000001000000001000000100010001000100010000000000000000000000000000000000000000000000000000000000000000000000; 14 | 12: q_reg <= 512'b_01111110001111000011110000000000001110000100010000000000010101000111100000010000000111000011100000100000001000000011110001000100000011000001000000000000000000000000000000000000000100000000000000000000010101000011100001000100001000000101010000111100010001000001000000000000000000000000000000000000000100000000000000000000000000000010000000000000000000000000000000000000000100000000000000000000001111000001000000111100001000000011110000111100001111000001000000000000000000000000000000000000000100000000000000000000; 15 | 13: q_reg <= 512'b_00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000; 16 | 14: q_reg <= 512'b_00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000; 17 | 15: q_reg <= 512'b_00000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000000000000000000; 18 | endcase 19 | -------------------------------------------------------------------------------- /source/char_rom/font/rcopt2-8x16.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chriz2600/time-sleuth/4139d9f2c9398c8865f0f42f78e598371d602b64/source/char_rom/font/rcopt2-8x16.png -------------------------------------------------------------------------------- /source/char_rom/font/string-to-pixels.py: -------------------------------------------------------------------------------- 1 | #!env python 2 | 3 | import sys 4 | import re 5 | 6 | Matrix = [''] * 16 7 | 8 | def extract(line): 9 | match = re.findall(r'.*8\'b(........).*', line) 10 | return match[0] 11 | 12 | for line in sys.stdin: 13 | for c in line: 14 | search = hex(ord(c))[1:] 15 | with open("8x16-font.v") as origin_file: 16 | c = 0 17 | for fline in origin_file: 18 | fline = fline.rstrip() 19 | if c > 0 and c <= 16: 20 | Matrix[c-1] += extract(fline) 21 | c = c + 1 22 | xline = re.findall(r'' + search, fline) 23 | if xline: 24 | c = 1 25 | 26 | addr = 0 27 | print("case (addr)") 28 | for x in Matrix: 29 | #print("%02i: q_reg <= %i'b_%s;" % (addr, len(x), x[::-1])) 30 | print("%02i: q_reg <= %i'b_%s;" % (addr, len(x), x)) 31 | addr = addr + 1 32 | print("endcase") 33 | -------------------------------------------------------------------------------- /source/char_rom/lagdisplay.v: -------------------------------------------------------------------------------- 1 | module lagdisplay( 2 | input clock, 3 | input [3:0] addr, 4 | output [WIDTH-1:0] q 5 | ); 6 | parameter WIDTH = 512; 7 | 8 | reg [WIDTH-1:0] q_reg; 9 | reg [WIDTH-1:0] q_reg_2; 10 | 11 | always @(posedge clock) begin 12 | `include "font/predef/lagdisplay.v"; 13 | q_reg_2 <= q_reg; 14 | end 15 | 16 | assign q = q_reg_2; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /source/char_rom/resolution.v: -------------------------------------------------------------------------------- 1 | 2 | `include "../defines.v" 3 | 4 | module resolution( 5 | input clock, 6 | input VideoMode videoMode, 7 | input [3:0] addr, 8 | output [`RESLINE_SIZE-1:0] q 9 | ); 10 | 11 | reg [`RESLINE_SIZE-1:0] q_reg; 12 | 13 | always @(posedge clock) begin 14 | case (addr) 15 | 00: q_reg <= 0; 16 | 01: q_reg <= 0; 17 | 02: q_reg <= { 96'b_111111100001000000000000000000000000000000111100000100000000000000000000000100000100000000000000, (videoMode.id[3] ? 32'b_00000000000010000011110000111100 : (videoMode.id[2] ? 32'b_00000000011111100011110000111100 : 32'b_00011000001111000011110000111100)), (videoMode.id[0] ? 8'b_00010000 : 8'b_00000000 ) }; 18 | 03: q_reg <= { 96'b_000100000000000000000000000000000000000001000010000100000000000000000000000100000100000000000000, (videoMode.id[3] ? 32'b_00000000000010000100001001000010 : (videoMode.id[2] ? 32'b_00000000000000100100001001000010 : 32'b_00101000010000100100001001000010)), (videoMode.id[0] ? 8'b_00000000 : 8'b_00000000 ) }; 19 | 04: q_reg <= { 96'b_000100000000000000000000000000000000000001000000000100000000000000000000000100000100000000000000, (videoMode.id[3] ? 32'b_00000000000110000100001001000010 : (videoMode.id[2] ? 32'b_00000000000000100000001001000010 : 32'b_00001000010000100100001001000010)), (videoMode.id[0] ? 8'b_00000000 : 8'b_00000000 ) }; 20 | 05: q_reg <= { 96'b_000100000011000001101000001110000000000001000000000100000011100001000100001110000111100000000000, (videoMode.id[3] ? 32'b_00000000000110000100001001000110 : (videoMode.id[2] ? 32'b_00000000000001000000001001000110 : 32'b_00001000010001100100001001000110)), (videoMode.id[0] ? 8'b_00110000 : 8'b_01111000 ) }; 21 | 06: q_reg <= { 96'b_000100000001000001010100010001000000000000111100000100000100010001000100000100000100010000000000, (videoMode.id[3] ? 32'b_00000000001010000011110001001010 : (videoMode.id[2] ? 32'b_00000000000001000000001001001010 : 32'b_00001000010010100011110001001010)), (videoMode.id[0] ? 8'b_00010000 : 8'b_01000100 ) }; 22 | 07: q_reg <= { 96'b_000100000001000001010100010001000000000000000010000100000100010001000100000100000100010000000000, (videoMode.id[3] ? 32'b_00000000001010000100001001010010 : (videoMode.id[2] ? 32'b_00000000000010000000001001010010 : 32'b_00001000010100100100001001010010)), (videoMode.id[0] ? 8'b_00010000 : 8'b_01000100 ) }; 23 | 08: q_reg <= { 96'b_000100000001000001010100011110000000000000000010000100000111100001000100000100000100010000000000, (videoMode.id[3] ? 32'b_00000000010010000100001001100010 : (videoMode.id[2] ? 32'b_00000000000010000011110001100010 : 32'b_00001000011000100100001001100010)), (videoMode.id[0] ? 8'b_00010000 : 8'b_01000100 ) }; 24 | 09: q_reg <= { 96'b_000100000001000001010100010000000000000000000010000100000100000001000100000100000100010000000000, (videoMode.id[3] ? 32'b_00000000010010000100001001000010 : (videoMode.id[2] ? 32'b_00000000000100000100000001000010 : 32'b_00001000010000100100001001000010)), (videoMode.id[0] ? 8'b_00010000 : 8'b_01000100 ) }; 25 | 10: q_reg <= { 96'b_000100000001000001010100010000000000000000000010000100000100000001000100000100000100010000000000, (videoMode.id[3] ? 32'b_00000000011111100100001001000010 : (videoMode.id[2] ? 32'b_00000000000100000100000001000010 : 32'b_00001000010000100100001001000010)), (videoMode.id[0] ? 8'b_00010000 : 8'b_01000100 ) }; 26 | 11: q_reg <= { 96'b_000100000001000001010100010000000000000001000010000100000100000001000100000100000100010000000000, (videoMode.id[3] ? 32'b_00000000000010000100001001000010 : (videoMode.id[2] ? 32'b_00000000000100000100000001000010 : 32'b_00001000010000100100001001000010)), (videoMode.id[0] ? 8'b_00010000 : 8'b_01000100 ) }; 27 | 12: q_reg <= { 96'b_000100000011100001010100001111000000000000111100000011000011110000111000000011000100010000000000, (videoMode.id[3] ? 32'b_00000000000010000011110000111100 : (videoMode.id[2] ? 32'b_00000000000100000111111000111100 : 32'b_00111110001111000011110000111100)), (videoMode.id[0] ? 8'b_00111000 : 8'b_01111000 ) }; 28 | 13: q_reg <= { 128'b_0, (videoMode.id[0] ? 8'b_00000000 : 8'b_01000000 ) }; 29 | 14: q_reg <= { 128'b_0, (videoMode.id[0] ? 8'b_00000000 : 8'b_01000000 ) }; 30 | 15: q_reg <= { 128'b_0, (videoMode.id[0] ? 8'b_00000000 : 8'b_01000000 ) }; 31 | endcase 32 | end 33 | 34 | assign q = q_reg; 35 | 36 | endmodule 37 | 38 | 39 | -------------------------------------------------------------------------------- /source/config/video_modes.v: -------------------------------------------------------------------------------- 1 | 2 | `include "../defines.v" 3 | 4 | const VideoMode VIDEO_MODE_480P = { 5 | `MODE_480p, // id 6 | 12'd_858, // h_total 7 | 12'd_720, // h_active 8 | 12'd_16, // h_front_porch 9 | 12'd_62, // h_sync 10 | 12'd_60, // h_back_porch 11 | 1'b_0, // h_sync_pol 12 | 13 | 12'd_480, // v_active 14 | 12'd_9, // v_front_porch 15 | 12'd_6, // v_sync 16 | 17 | 12'd_525, // v_total_1 18 | 12'd_30, // v_back_porch_1 19 | 12'd_0, // v_pxl_offset_1 20 | 21 | 12'd_525, // v_total_2 22 | 12'd_30, // v_back_porch_2 23 | 12'd_0, // v_pxl_offset_2 24 | 25 | 1'b_0, // v_sync_pol 26 | 27 | 12'd_40, // h_field_start 28 | 12'd_200, // h_field_end 29 | 12'd_0, // v_field1_start 30 | 12'd_40, // v_field1_end 31 | 12'd_220, // v_field2_start 32 | 12'd_260, // v_field2_end 33 | 12'd_440, // v_field3_start 34 | 12'd_480, // v_field3_end 35 | 36 | 4'd_0, // h_res_divider 37 | 4'd_0, // v_res_divider 38 | 12'd_720 - `RESLINE_SIZE, // h_res_start 39 | 40 | 4'd_1, // h_lag_divider 41 | 4'd_1, // v_lag_divider 42 | 12'd_110, // h_lag_start 43 | 12'd_50 // v_lag_start 44 | }; 45 | 46 | const VideoMode VIDEO_MODE_480I = { 47 | `MODE_480i, // id 48 | 12'd_1716, // h_total 49 | 12'd_1440, // h_active 50 | 12'd_38, // h_front_porch 51 | 12'd_124, // h_sync 52 | 12'd_114, // h_back_porch 53 | 1'b_0, // h_sync_pol 54 | 55 | 12'd_240, // v_active 56 | 12'd_4, // v_front_porch 57 | 12'd_3, // v_sync 58 | 59 | 12'd_262, // v_total_1 60 | 12'd_15, // v_back_porch_1 61 | 12'd_0, // v_pxl_offset_1 62 | 63 | 12'd_263, // v_total_2 64 | 12'd_16, // v_back_porch_2 65 | 12'd_858, // v_pxl_offset_2 66 | 67 | 1'b_0, // v_sync_pol 68 | 69 | 12'd_80, // h_field_start 70 | 12'd_400, // h_field_end 71 | 12'd_0, // v_field1_start 72 | 12'd_20, // v_field1_end 73 | 12'd_110, // v_field2_start 74 | 12'd_130, // v_field2_end 75 | 12'd_220, // v_field3_start 76 | 12'd_240, // v_field3_end 77 | 78 | 4'd_1, // h_res_divider 79 | 4'd_0, // v_res_divider 80 | 12'd_720 - `RESLINE_SIZE, // h_res_start 81 | 82 | 4'd_2, // h_lag_divider 83 | 4'd_0, // v_lag_divider 84 | 12'd_110, // h_lag_start 85 | 12'd_25 // v_lag_start 86 | }; 87 | 88 | const VideoMode VIDEO_MODE_720P = { 89 | `MODE_720p, // id 90 | 12'd_1650, // h_total 91 | 12'd_1280, // h_active 92 | 12'd_110, // h_front_porch 93 | 12'd_40, // h_sync 94 | 12'd_220, // h_back_porch 95 | 1'b_1, // h_sync_pol 96 | 97 | 12'd_720, // v_active 98 | 12'd_5, // v_front_porch 99 | 12'd_5, // v_sync 100 | 101 | 12'd_750, // v_total_1 102 | 12'd_20, // v_back_porch_1 103 | 12'd_0, // v_pxl_offset_1 104 | 105 | 12'd_750, // v_total_2 106 | 12'd_20, // v_back_porch_2 107 | 12'd_0, // v_pxl_offset_2 108 | 109 | 1'b_1, // v_sync_pol 110 | 111 | 12'd_80, // h_field_start 112 | 12'd_400, // h_field_end 113 | 12'd_0, // v_field1_start 114 | 12'd_60, // v_field1_end 115 | 12'd_330, // v_field2_start 116 | 12'd_390, // v_field2_end 117 | 12'd_660, // v_field3_start 118 | 12'd_720, // v_field3_end 119 | 120 | 4'd_1, // h_res_divider 121 | 4'd_1, // v_res_divider 122 | 12'd_640 - `RESLINE_SIZE, // h_res_start 123 | 124 | 4'd_2, // h_lag_divider 125 | 4'd_2, // v_lag_divider 126 | 12'd_110, // h_lag_start 127 | 12'd_60 // v_lag_start 128 | }; 129 | 130 | const VideoMode VIDEO_MODE_1080P = { 131 | `MODE_1080p, // id 132 | 12'd_1100, // h_total 133 | 12'd_960, // h_active 134 | 12'd_44, // h_front_porch 135 | 12'd_22, // h_sync 136 | 12'd_74, // h_back_porch 137 | 1'b_1, // h_sync_pol 138 | 139 | 12'd_1080, // v_active 140 | 12'd_4, // v_front_porch 141 | 12'd_5, // v_sync 142 | 143 | 12'd_1125, // v_total_1 144 | 12'd_36, // v_back_porch_1 145 | 12'd_0, // v_pxl_offset_1 146 | 147 | 12'd_1125, // v_total_2 148 | 12'd_36, // v_back_porch_2 149 | 12'd_0, // v_pxl_offset_2 150 | 151 | 1'b_1, // v_sync_pol 152 | 153 | 12'd_60, // h_field_start 154 | 12'd_300, // h_field_end 155 | 12'd_0, // v_field1_start 156 | 12'd_90, // v_field1_end 157 | 12'd_495, // v_field2_start 158 | 12'd_585, // v_field2_end 159 | 12'd_990, // v_field3_start 160 | 12'd_1080, // v_field3_end 161 | 162 | 4'd_0, // h_res_divider 163 | 4'd_1, // v_res_divider 164 | 12'd_960 - `RESLINE_SIZE, // h_res_start 165 | 166 | 4'd_1, // h_lag_divider 167 | 4'd_2, // v_lag_divider 168 | 12'd_180, // h_lag_start (px / 2) 169 | 12'd_120 // v_lag_start 170 | }; 171 | 172 | const VideoMode VIDEO_MODE_1080I = { 173 | `MODE_1080i, // id 174 | 12'd_2200, // h_total 175 | 12'd_1920, // h_active 176 | 12'd_88, // h_front_porch 177 | 12'd_44, // h_sync 178 | 12'd_148, // h_back_porch 179 | 1'b_1, // h_sync_pol 180 | 181 | 12'd_540, // v_active 182 | 12'd_2, // v_front_porch 183 | 12'd_5, // v_sync 184 | 185 | 12'd_562, // v_total_1 186 | 12'd_15, // v_back_porch_1 187 | 12'd_0, // v_pxl_offset_1 188 | 189 | 12'd_563, // v_total_2 190 | 12'd_16, // v_back_porch_2 191 | 12'd_1100, // v_pxl_offset_2 192 | 193 | 1'b_1, // v_sync_pol 194 | 195 | 12'd_120, // h_field_start 196 | 12'd_600, // h_field_end 197 | 12'd_0, // v_field1_start 198 | 12'd_45, // v_field1_end 199 | 12'd_247, // v_field2_start 200 | 12'd_292, // v_field2_end 201 | 12'd_495, // v_field3_start 202 | 12'd_540, // v_field3_end 203 | 204 | 4'd_1, // h_res_divider 205 | 4'd_0, // v_res_divider 206 | 12'd_960 - `RESLINE_SIZE, // h_res_start 207 | 208 | 4'd_2, // h_lag_divider 209 | 4'd_1, // v_lag_divider 210 | 12'd_180, // h_lag_start (px / 2) 211 | 12'd_60 // v_lag_start 212 | }; 213 | -------------------------------------------------------------------------------- /source/configuration.v: -------------------------------------------------------------------------------- 1 | `include "defines.v" 2 | 3 | module configuration( 4 | input clock, 5 | input [4:0] config_in, 6 | output reg [7:0] config_data, 7 | output config_changed 8 | ); 9 | reg [7:0] prev_config_data; 10 | 11 | always @(posedge clock) begin 12 | prev_config_data <= config_data; 13 | case (config_in) 14 | 5'b_11110: config_data <= `MODE_1080p; // switch 1 15 | 5'b_11101: config_data <= `MODE_1080i; // switch 2 16 | 5'b_11011: config_data <= `MODE_720p; // switch 3 17 | 5'b_10111: config_data <= `MODE_480p; // switch 4 18 | 5'b_01111: config_data <= `MODE_480i; // switch 5 19 | default: config_data <= `DEFAULT_FB_MODE; 20 | endcase 21 | end 22 | 23 | assign config_changed = (prev_config_data != config_data); 24 | 25 | endmodule -------------------------------------------------------------------------------- /source/defines.v: -------------------------------------------------------------------------------- 1 | `define MODE_1080p 8'b_0000_0010 2 | `define MODE_1080i 8'b_0000_0011 3 | `define MODE_720p 8'b_0000_0100 4 | `define MODE_480p 8'b_0000_1000 5 | `define MODE_480i 8'b_0000_1001 6 | `define MAX_BCDCOUNT 20'h_9_99_99 7 | // clock.frquency / CLOCK_DIVIDER = 1MHz 8 | `define CLOCK_DIVIDER 27 9 | `define FRAME_COUNTER 20 10 | `define FRAME_ON_COUNT 15 11 | `define LAGLINE_SIZE 512 12 | `define RESLINE_SIZE 12'd_136 13 | // averaging 14 | `define AVERAGE_BITS 4 15 | `define AVERAGE_SIZE (2 ** `AVERAGE_BITS) 16 | // ... 17 | `define DEFAULT_FB_MODE `MODE_1080p 18 | -------------------------------------------------------------------------------- /source/generated/slots.v: -------------------------------------------------------------------------------- 1 | `define SLOT1 `MODE_576p 2 | `define SLOT2 `MODE_576i 3 | `define SLOT3 `MODE_288p 4 | `define SLOT4 `MODE_1080p 5 | `define SLOT5 `MODE_1080i 6 | 7 | -------------------------------------------------------------------------------- /source/generated/video-modes.v: -------------------------------------------------------------------------------- 1 | `MODE_576p: videoMode_reg <= VIDEO_MODE_576P; 2 | `MODE_576i: videoMode_reg <= VIDEO_MODE_576I; 3 | `MODE_288p: videoMode_reg <= VIDEO_MODE_288P; 4 | `MODE_1080p: videoMode_reg <= VIDEO_MODE_1080P; 5 | `MODE_1080i: videoMode_reg <= VIDEO_MODE_1080I; 6 | -------------------------------------------------------------------------------- /source/lagtester.v: -------------------------------------------------------------------------------- 1 | module lagtester( 2 | input clock, 3 | 4 | input [4:0] RES_CONFIG, 5 | 6 | inout wire SDA, 7 | inout wire SCL, 8 | 9 | input SENSOR, 10 | output [7:0] DVI_RED, 11 | output [7:0] DVI_GREEN, 12 | output [7:0] DVI_BLUE, 13 | output DVI_DE, 14 | output DVI_HSYNC, 15 | output DVI_VSYNC, 16 | output DVI_CLOCK, 17 | 18 | output TFP410_reset, 19 | output LED 20 | ); 21 | wire internal_clock; 22 | 23 | wire sensor_out; 24 | wire sensor_trigger; 25 | 26 | wire config_changed; 27 | wire [7:0] config_data; 28 | 29 | wire starttrigger; 30 | wire reset_counter; 31 | wire [7:0] config_data_crossed; 32 | wire [79:0] bcdcount_crossed; 33 | wire [19:0] bcd_current; 34 | wire [19:0] bcd_minimum; 35 | wire [19:0] bcd_maximum; 36 | wire [19:0] bcd_average; 37 | 38 | wire pll_locked; 39 | wire tfp410_ready; 40 | wire hpd_detected; 41 | 42 | /////////////////////////////////////////// 43 | // clocks 44 | pll_main pll( 45 | .clock(clock), 46 | .reset(1'b0), 47 | .data(config_data), 48 | 49 | .clock_out(internal_clock), 50 | .clock_out_video(DVI_CLOCK), 51 | .locked(pll_locked) 52 | ); 53 | 54 | /////////////////////////////////////////// 55 | // sensor 56 | sensor sensor( 57 | .clock(clock), 58 | .sensor(SENSOR), 59 | .sensor_out(sensor_out), 60 | .sensor_trigger(sensor_trigger) 61 | ); 62 | 63 | /////////////////////////////////////////// 64 | // config 65 | configuration configuration( 66 | .clock(clock), 67 | .config_in(RES_CONFIG), 68 | .config_data(config_data), 69 | .config_changed(config_changed) 70 | ); 71 | 72 | /////////////////////////////////////////// 73 | // measurement 74 | Flag_CrossDomain reset_control( 75 | .clkA(internal_clock), 76 | .FlagIn_clkA(starttrigger), 77 | .clkB(clock), 78 | .FlagOut_clkB(reset_counter) 79 | ); 80 | 81 | measure measure( 82 | .clock(clock), 83 | .reset_counter(reset_counter), 84 | .sensor_trigger(sensor_trigger), 85 | .reset_bcdoutput(config_changed), 86 | .bcd_current(bcd_current), 87 | .bcd_minimum(bcd_minimum), 88 | .bcd_maximum(bcd_maximum), 89 | .bcd_average(bcd_average) 90 | ); 91 | 92 | /////////////////////////////////////////// 93 | // video generator 94 | data_cross #( 95 | .WIDTH(8) 96 | ) video_data_cross ( 97 | .clkIn(clock), 98 | .clkOut(internal_clock), 99 | .dataIn(config_data), 100 | .dataOut(config_data_crossed) 101 | ); 102 | 103 | data_cross #( 104 | .WIDTH(80) 105 | ) bcdcounter_cross ( 106 | .clkIn(clock), 107 | .clkOut(internal_clock), 108 | .dataIn({ bcd_average, bcd_maximum, bcd_minimum, bcd_current }), 109 | .dataOut(bcdcount_crossed) 110 | ); 111 | 112 | video video( 113 | .clock(internal_clock), 114 | .config_data(config_data_crossed), 115 | .bcdcount(bcdcount_crossed), 116 | .red(DVI_RED), 117 | .green(DVI_GREEN), 118 | .blue(DVI_BLUE), 119 | .de(DVI_DE), 120 | .hsync(DVI_HSYNC), 121 | .vsync(DVI_VSYNC), 122 | .starttrigger(starttrigger) 123 | ); 124 | /////////////////////////////////////////// 125 | 126 | /////////////////////////////////////////// 127 | // dvi transmitter 128 | TFP410 tfp410( 129 | .clk(clock), 130 | .reset(1'b1), 131 | .output_ready(pll_locked), 132 | .sda(SDA), 133 | .scl(SCL), 134 | .ready(tfp410_ready), 135 | .hpd_detected(hpd_detected) 136 | ); 137 | /////////////////////////////////////////// 138 | 139 | assign LED = ~sensor_out; 140 | assign TFP410_reset = 1'b1; 141 | 142 | endmodule -------------------------------------------------------------------------------- /source/measure.v: -------------------------------------------------------------------------------- 1 | `include "defines.v" 2 | 3 | module measure( 4 | input clock, 5 | input reset_counter, 6 | input sensor_trigger, // ~prev_sensor_input && sensor_input 7 | input reset_bcdoutput, // prev_config_data != config_data 8 | 9 | output [19:0] bcd_current, 10 | output [19:0] bcd_minimum, 11 | output [19:0] bcd_maximum, 12 | output [19:0] bcd_average 13 | ); 14 | wire [23:0] bcdcount; 15 | wire [23:0] avg_counter_bcd; 16 | wire avg_counter_ready; 17 | 18 | reg waiting; 19 | reg [8:0] counter; 20 | reg [24:0] raw_counter; 21 | reg counter_trigger = 0; 22 | reg reset_bcdcounter = 0; 23 | reg [19:0] bcdcount_out = `MAX_BCDCOUNT; 24 | reg [19:0] bcdcount_min = `MAX_BCDCOUNT; 25 | reg [19:0] bcdcount_max = 0; 26 | reg [19:0] avg_counter; 27 | reg [31:0] avg_counter_reg; 28 | reg [31:0] avg_counter_reg_avg; 29 | reg [19:0] avg_counter_bcd_reg = `MAX_BCDCOUNT; 30 | reg avg_counter_start; 31 | reg [`AVERAGE_BITS-1:0] avg_loop; 32 | 33 | bcdcounter bcdcounter( 34 | .trigger(counter_trigger), 35 | .reset(reset_bcdcounter), 36 | .bcdcount(bcdcount) 37 | ); 38 | 39 | Binary_to_BCD #( 40 | .INPUT_WIDTH(20), 41 | .DECIMAL_DIGITS(6) 42 | ) Binary_to_BCD ( 43 | .i_Clock(clock), 44 | .i_Start(avg_counter_start), 45 | .i_Binary(avg_counter_reg_avg[19:0]), 46 | .o_BCD(avg_counter_bcd), 47 | .o_DV(avg_counter_ready) 48 | ); 49 | 50 | /* 51 | create trigger for the bcd counter, 52 | 27MHz / 27, so trigger every 0.001 ms 53 | */ 54 | always @(posedge clock) begin 55 | if (reset_counter) begin 56 | raw_counter <= 0; 57 | counter <= 0; 58 | counter_trigger <= 0; 59 | reset_bcdcounter <= 1; 60 | end else begin 61 | raw_counter <= raw_counter + 1'b1; 62 | reset_bcdcounter <= 0; 63 | if (counter < `CLOCK_DIVIDER - 1) begin 64 | counter <= counter + 1'b1; 65 | counter_trigger <= 0; 66 | end else begin 67 | counter <= 0; 68 | counter_trigger <= 1; 69 | end 70 | end 71 | end 72 | 73 | /////////////////////////////////////////////////////// 74 | 75 | always @(posedge counter_trigger or posedge reset_bcdcounter) begin 76 | if (reset_bcdcounter) begin 77 | avg_counter <= 0; 78 | end else begin 79 | avg_counter <= avg_counter + 1'b1; 80 | end 81 | end 82 | 83 | /////////////////////////////////////////////////////// 84 | 85 | always @(posedge clock) begin 86 | if (reset_counter) begin 87 | waiting <= 1; 88 | end else if (reset_bcdoutput) begin 89 | bcdcount_out <= `MAX_BCDCOUNT; 90 | bcdcount_max <= 0; 91 | bcdcount_min <= `MAX_BCDCOUNT; 92 | avg_counter_reg_avg <= 0; 93 | avg_counter_reg <= 0; 94 | avg_loop <= 0; 95 | avg_counter_bcd_reg <= `MAX_BCDCOUNT; 96 | end else if (waiting && sensor_trigger) begin 97 | bcdcount_out <= bcdcount[23:4]; 98 | if (avg_loop == 0) begin 99 | // reset min and max at the start of the averaging period 100 | bcdcount_max <= bcdcount[23:4]; 101 | bcdcount_min <= bcdcount[23:4]; 102 | end else begin 103 | if (bcdcount[23:4] < bcdcount_min) begin 104 | bcdcount_min <= bcdcount[23:4]; 105 | end 106 | if (bcdcount[23:4] > bcdcount_max) begin 107 | bcdcount_max <= bcdcount[23:4]; 108 | end 109 | end 110 | if (avg_counter != 0) begin 111 | if (avg_loop == (`AVERAGE_SIZE - 1)) begin 112 | avg_counter_reg_avg <= (avg_counter_reg + avg_counter) >> `AVERAGE_BITS; 113 | avg_counter_reg <= 0; 114 | avg_loop <= 0; 115 | avg_counter_start <= 1'b1; 116 | end else begin 117 | avg_counter_reg <= avg_counter_reg + avg_counter; 118 | avg_loop <= avg_loop + 1'b1; 119 | avg_counter_start <= 1'b0; 120 | end 121 | end 122 | waiting <= 0; 123 | end 124 | if (avg_counter_ready) begin 125 | avg_counter_bcd_reg <= avg_counter_bcd[23:4]; 126 | end 127 | end 128 | 129 | assign bcd_current = bcdcount_out; 130 | assign bcd_minimum = bcdcount_min; 131 | assign bcd_maximum = bcdcount_max; 132 | assign bcd_average = avg_counter_bcd_reg; 133 | 134 | endmodule -------------------------------------------------------------------------------- /source/misc/Binary_to_BCD.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // File Downloaded from http://www.nandland.com 3 | /////////////////////////////////////////////////////////////////////////////// 4 | module Binary_to_BCD( 5 | input i_Clock, 6 | input [INPUT_WIDTH-1:0] i_Binary, 7 | input i_Start, 8 | // 9 | output [DECIMAL_DIGITS*4-1:0] o_BCD, 10 | output o_DV 11 | ); 12 | 13 | parameter INPUT_WIDTH = 16; 14 | parameter DECIMAL_DIGITS = 4; 15 | 16 | parameter s_IDLE = 3'b000; 17 | parameter s_SHIFT = 3'b001; 18 | parameter s_CHECK_SHIFT_INDEX = 3'b010; 19 | parameter s_ADD = 3'b011; 20 | parameter s_CHECK_DIGIT_INDEX = 3'b100; 21 | parameter s_BCD_DONE = 3'b101; 22 | 23 | reg [2:0] r_SM_Main = s_IDLE; 24 | 25 | // The vector that contains the output BCD 26 | reg [DECIMAL_DIGITS*4-1:0] r_BCD = 0; 27 | 28 | // The vector that contains the input binary value being shifted. 29 | reg [INPUT_WIDTH-1:0] r_Binary = 0; 30 | 31 | // Keeps track of which Decimal Digit we are indexing 32 | reg [DECIMAL_DIGITS-1:0] r_Digit_Index = 0; 33 | 34 | // Keeps track of which loop iteration we are on. 35 | // Number of loops performed = INPUT_WIDTH 36 | reg [7:0] r_Loop_Count = 0; 37 | 38 | wire [3:0] w_BCD_Digit; 39 | reg r_DV = 1'b0; 40 | 41 | always @(posedge i_Clock) 42 | begin 43 | 44 | case (r_SM_Main) 45 | 46 | // Stay in this state until i_Start comes along 47 | s_IDLE : 48 | begin 49 | r_DV <= 1'b0; 50 | 51 | if (i_Start == 1'b1) 52 | begin 53 | r_Binary <= i_Binary; 54 | r_SM_Main <= s_SHIFT; 55 | r_BCD <= 0; 56 | end 57 | else 58 | r_SM_Main <= s_IDLE; 59 | end 60 | 61 | 62 | // Always shift the BCD Vector until we have shifted all bits through 63 | // Shift the most significant bit of r_Binary into r_BCD lowest bit. 64 | s_SHIFT : 65 | begin 66 | r_BCD <= r_BCD << 1; 67 | r_BCD[0] <= r_Binary[INPUT_WIDTH-1]; 68 | r_Binary <= r_Binary << 1; 69 | r_SM_Main <= s_CHECK_SHIFT_INDEX; 70 | end 71 | 72 | 73 | // Check if we are done with shifting in r_Binary vector 74 | s_CHECK_SHIFT_INDEX : 75 | begin 76 | if (r_Loop_Count == INPUT_WIDTH-1) 77 | begin 78 | r_Loop_Count <= 0; 79 | r_SM_Main <= s_BCD_DONE; 80 | end 81 | else 82 | begin 83 | r_Loop_Count <= r_Loop_Count + 1'b1; 84 | r_SM_Main <= s_ADD; 85 | end 86 | end 87 | 88 | 89 | // Break down each BCD Digit individually. Check them one-by-one to 90 | // see if they are greater than 4. If they are, increment by 3. 91 | // Put the result back into r_BCD Vector. 92 | s_ADD : 93 | begin 94 | if (w_BCD_Digit > 4) 95 | begin 96 | r_BCD[(r_Digit_Index*4)+:4] <= w_BCD_Digit + 2'd3; 97 | end 98 | 99 | r_SM_Main <= s_CHECK_DIGIT_INDEX; 100 | end 101 | 102 | 103 | // Check if we are done incrementing all of the BCD Digits 104 | s_CHECK_DIGIT_INDEX : 105 | begin 106 | if (r_Digit_Index == DECIMAL_DIGITS-1) 107 | begin 108 | r_Digit_Index <= 0; 109 | r_SM_Main <= s_SHIFT; 110 | end 111 | else 112 | begin 113 | r_Digit_Index <= r_Digit_Index + 1'b1; 114 | r_SM_Main <= s_ADD; 115 | end 116 | end 117 | 118 | 119 | 120 | s_BCD_DONE : 121 | begin 122 | r_DV <= 1'b1; 123 | r_SM_Main <= s_IDLE; 124 | end 125 | 126 | 127 | default : 128 | r_SM_Main <= s_IDLE; 129 | 130 | endcase 131 | end // always @ (posedge i_Clock) 132 | 133 | 134 | assign w_BCD_Digit = r_BCD[r_Digit_Index*4 +: 4]; 135 | 136 | assign o_BCD = r_BCD; 137 | assign o_DV = r_DV; 138 | 139 | endmodule // Binary_to_BCD -------------------------------------------------------------------------------- /source/misc/Flag_CrossDomain.v: -------------------------------------------------------------------------------- 1 | // http://www.fpga4fun.com/CrossClockDomain2.html 2 | 3 | module Flag_CrossDomain( 4 | input clkA, 5 | input FlagIn_clkA, 6 | //output Busy_clkA, 7 | input clkB, 8 | output FlagOut_clkB 9 | ); 10 | reg data_out; 11 | reg[3:0] rCount; 12 | reg[2:0] data_out_reg; 13 | 14 | assign FlagOut_clkB = data_out_reg[2]; 15 | 16 | always @(posedge clkA) begin 17 | if (FlagIn_clkA) begin 18 | rCount <= 4'b1000; 19 | data_out <= 1'b1; 20 | end else if (rCount > 0) begin 21 | rCount <= rCount - 1'b1; 22 | end else begin 23 | data_out <= 1'b0; 24 | end 25 | end 26 | 27 | always @(posedge clkB) begin 28 | data_out_reg <= { data_out_reg[1], data_out_reg[0], data_out }; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /source/misc/bcdcounter.v: -------------------------------------------------------------------------------- 1 | 2 | module bcdcounter( 3 | input trigger, 4 | input reset, 5 | output [23:0] bcdcount 6 | ); 7 | 8 | reg [3:0] first; 9 | reg [3:0] second; 10 | reg [3:0] third; 11 | reg [3:0] fourth; 12 | reg [3:0] fifth; 13 | reg [3:0] sixth; 14 | 15 | always @(posedge trigger or posedge reset) begin 16 | if (reset) begin 17 | first <= 0; 18 | second <= 0; 19 | third <= 0; 20 | fourth <= 0; 21 | fifth <= 0; 22 | sixth <= 0; 23 | end else if (first == 4'd9) begin // xxxxx9 reached 24 | first <= 0; 25 | if (second == 4'd9) begin // xxxx99 reached 26 | second <= 0; 27 | if (third == 4'd9) begin // xxx999 reached 28 | third <= 0; 29 | if (fourth == 4'd9) begin // xx9999 reached 30 | fourth <= 0; 31 | if (fifth == 4'd9) begin // x99999 reached 32 | fifth <= 0; 33 | if (sixth == 4'd9) begin // 999999 reached 34 | sixth <= 0; 35 | end else begin 36 | sixth <= sixth + 1'b1; 37 | end 38 | end else begin 39 | fifth <= fifth + 1'b1; 40 | end 41 | end else begin 42 | fourth <= fourth + 1'b1; 43 | end 44 | end else begin 45 | third <= third + 1'b1; 46 | end 47 | end else begin 48 | second <= second + 1'b1; 49 | end 50 | end else begin 51 | first <= first + 1'b1; 52 | end 53 | end 54 | 55 | assign bcdcount = { sixth, fifth, fourth, third, second, first }; 56 | endmodule 57 | 58 | 59 | -------------------------------------------------------------------------------- /source/misc/data_cross.v: -------------------------------------------------------------------------------- 1 | 2 | module data_cross( 3 | input clkIn, 4 | input clkOut, 5 | input [WIDTH-1:0] dataIn, 6 | output reg [WIDTH-1:0] dataOut 7 | ); 8 | parameter WIDTH = 24; 9 | 10 | reg wrreq = 0; 11 | reg rdreq = 0; 12 | reg wrfull; 13 | reg rdempty; 14 | reg [WIDTH-1:0] dataIn_reg = 0; 15 | 16 | data_fifo #( 17 | .WIDTH(WIDTH) 18 | ) fifo ( 19 | .wrclk(clkIn), 20 | .data(dataIn_reg), 21 | .wrreq(wrreq), 22 | .wrfull(wrfull), 23 | 24 | .rdclk(clkOut), 25 | .rdreq(rdreq), 26 | .rdempty(rdempty), 27 | .q(dataOut) 28 | ); 29 | 30 | always @(posedge clkIn) begin 31 | dataIn_reg <= dataIn; 32 | if (dataIn_reg != dataIn) begin 33 | wrreq <= 1'b1; 34 | end else begin 35 | wrreq <= 1'b0; 36 | end 37 | end 38 | 39 | always @(posedge clkOut) begin 40 | if (~rdempty) begin 41 | rdreq <= 1'b1; 42 | end else begin 43 | rdreq <= 1'b0; 44 | end 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /source/misc/data_fifo.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "data_fifo.v"] 5 | -------------------------------------------------------------------------------- /source/misc/data_fifo.v: -------------------------------------------------------------------------------- 1 | // synopsys translate_off 2 | `timescale 1 ps / 1 ps 3 | // synopsys translate_on 4 | module data_fifo ( 5 | data, 6 | rdclk, 7 | rdreq, 8 | wrclk, 9 | wrreq, 10 | q, 11 | rdempty, 12 | wrfull); 13 | 14 | parameter WIDTH = 24; 15 | 16 | input [WIDTH-1:0] data; 17 | input rdclk; 18 | input rdreq; 19 | input wrclk; 20 | input wrreq; 21 | output [WIDTH-1:0] q; 22 | output rdempty; 23 | output wrfull; 24 | 25 | wire [WIDTH-1:0] sub_wire0; 26 | wire sub_wire1; 27 | wire sub_wire2; 28 | wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0]; 29 | wire rdempty = sub_wire1; 30 | wire wrfull = sub_wire2; 31 | 32 | dcfifo dcfifo_component ( 33 | .data (data), 34 | .rdclk (rdclk), 35 | .rdreq (rdreq), 36 | .wrclk (wrclk), 37 | .wrreq (wrreq), 38 | .q (sub_wire0), 39 | .rdempty (sub_wire1), 40 | .wrfull (sub_wire2), 41 | .aclr (), 42 | .eccstatus (), 43 | .rdfull (), 44 | .rdusedw (), 45 | .wrempty (), 46 | .wrusedw ()); 47 | defparam 48 | dcfifo_component.intended_device_family = "MAX 10", 49 | dcfifo_component.lpm_numwords = 4, 50 | dcfifo_component.lpm_showahead = "OFF", 51 | dcfifo_component.lpm_type = "dcfifo", 52 | dcfifo_component.lpm_width = WIDTH, 53 | dcfifo_component.lpm_widthu = 2, 54 | dcfifo_component.overflow_checking = "ON", 55 | dcfifo_component.rdsync_delaypipe = 5, 56 | dcfifo_component.underflow_checking = "ON", 57 | dcfifo_component.use_eab = "ON", 58 | dcfifo_component.wrsync_delaypipe = 5; 59 | 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /source/misc/delayline.v: -------------------------------------------------------------------------------- 1 | module delayline( 2 | input clock, 3 | input [WIDTH-1:0] in, 4 | output [WIDTH-1:0] out 5 | ); 6 | 7 | parameter WIDTH = 8; 8 | parameter CYCLES = 4; 9 | 10 | reg [WIDTH-1:0] buffer [CYCLES-1:0]; 11 | 12 | always @(posedge clock) begin 13 | out <= buffer[CYCLES-1]; 14 | buffer[CYCLES-1:1] <= buffer[CYCLES-2:0]; 15 | buffer[0] <= in; 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /source/misc/edge_detect.v: -------------------------------------------------------------------------------- 1 | module edge_detect( 2 | input async_sig, 3 | input clk, 4 | output reg rise, 5 | output reg fall 6 | ); 7 | 8 | reg [1:3] resync; 9 | 10 | always @(posedge clk) begin 11 | rise <= resync[2] && !resync[3]; 12 | fall <= resync[3] && !resync[2]; 13 | resync <= { async_sig, resync[1:2] }; 14 | end 15 | 16 | endmodule -------------------------------------------------------------------------------- /source/pll/config/148_5_Mhz.mif: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- MIF file representing initial state of PLL Scan Chain 16 | -- Device Family: MAX 10 17 | -- Device Part: - 18 | -- Device Speed Grade: - 19 | -- PLL Scan Chain: Fast PLL (144 bits) 20 | -- File Name: C:/Users/chriz/Development/lagtester/source/pll/config//1080p.mif 21 | -- Generated: Sun Feb 03 01:21:00 2019 22 | 23 | WIDTH=1; 24 | DEPTH=144; 25 | 26 | ADDRESS_RADIX=UNS; 27 | DATA_RADIX=UNS; 28 | 29 | CONTENT BEGIN 30 | 0 : 0; -- Reserved Bits = 0 (1 bit(s)) 31 | 1 : 0; -- Reserved Bits = 0 (1 bit(s)) 32 | 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 33 | 3 : 0; 34 | 4 : 1; -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24) 35 | 5 : 1; 36 | 6 : 0; 37 | 7 : 0; 38 | 8 : 0; 39 | 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 40 | 10 : 0; -- Reserved Bits = 0 (5 bit(s)) 41 | 11 : 0; 42 | 12 : 0; 43 | 13 : 0; 44 | 14 : 0; 45 | 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 46 | 16 : 0; 47 | 17 : 1; 48 | 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) 49 | 19 : 0; -- N counter: High Count = 0 (8 bit(s)) 50 | 20 : 0; 51 | 21 : 0; 52 | 22 : 0; 53 | 23 : 0; 54 | 24 : 0; 55 | 25 : 0; 56 | 26 : 0; 57 | 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) 58 | 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) 59 | 29 : 0; 60 | 30 : 0; 61 | 31 : 0; 62 | 32 : 0; 63 | 33 : 0; 64 | 34 : 0; 65 | 35 : 0; 66 | 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) 67 | 37 : 0; -- M counter: High Count = 11 (8 bit(s)) 68 | 38 : 0; 69 | 39 : 0; 70 | 40 : 0; 71 | 41 : 1; 72 | 42 : 0; 73 | 43 : 1; 74 | 44 : 1; 75 | 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) 76 | 46 : 0; -- M counter: Low Count = 11 (8 bit(s)) 77 | 47 : 0; 78 | 48 : 0; 79 | 49 : 0; 80 | 50 : 1; 81 | 51 : 0; 82 | 52 : 1; 83 | 53 : 1; 84 | 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) 85 | 55 : 0; -- clk0 counter: High Count = 4 (8 bit(s)) 86 | 56 : 0; 87 | 57 : 0; 88 | 58 : 0; 89 | 59 : 0; 90 | 60 : 1; 91 | 61 : 0; 92 | 62 : 0; 93 | 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) 94 | 64 : 0; -- clk0 counter: Low Count = 4 (8 bit(s)) 95 | 65 : 0; 96 | 66 : 0; 97 | 67 : 0; 98 | 68 : 0; 99 | 69 : 1; 100 | 70 : 0; 101 | 71 : 0; 102 | 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) 103 | 73 : 0; -- clk1 counter: High Count = 2 (8 bit(s)) 104 | 74 : 0; 105 | 75 : 0; 106 | 76 : 0; 107 | 77 : 0; 108 | 78 : 0; 109 | 79 : 1; 110 | 80 : 0; 111 | 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) 112 | 82 : 0; -- clk1 counter: Low Count = 2 (8 bit(s)) 113 | 83 : 0; 114 | 84 : 0; 115 | 85 : 0; 116 | 86 : 0; 117 | 87 : 0; 118 | 88 : 1; 119 | 89 : 0; 120 | 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 121 | 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 122 | 92 : 0; 123 | 93 : 0; 124 | 94 : 0; 125 | 95 : 0; 126 | 96 : 0; 127 | 97 : 0; 128 | 98 : 0; 129 | 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) 130 | 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) 131 | 101 : 0; 132 | 102 : 0; 133 | 103 : 0; 134 | 104 : 0; 135 | 105 : 0; 136 | 106 : 0; 137 | 107 : 0; 138 | 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) 139 | 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) 140 | 110 : 0; 141 | 111 : 0; 142 | 112 : 0; 143 | 113 : 0; 144 | 114 : 0; 145 | 115 : 0; 146 | 116 : 0; 147 | 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) 148 | 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) 149 | 119 : 0; 150 | 120 : 0; 151 | 121 : 0; 152 | 122 : 0; 153 | 123 : 0; 154 | 124 : 0; 155 | 125 : 0; 156 | 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) 157 | 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) 158 | 128 : 0; 159 | 129 : 0; 160 | 130 : 0; 161 | 131 : 0; 162 | 132 : 0; 163 | 133 : 0; 164 | 134 : 0; 165 | 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) 166 | 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) 167 | 137 : 0; 168 | 138 : 0; 169 | 139 : 0; 170 | 140 : 0; 171 | 141 : 0; 172 | 142 : 0; 173 | 143 : 0; 174 | END; 175 | -------------------------------------------------------------------------------- /source/pll/config/148_5_Mhz.v: -------------------------------------------------------------------------------- 1 | case (address) 2 | 0: q_reg <= 1'b0; // -- Reserved Bits = 0 (1 bit(s)) 3 | 1: q_reg <= 1'b0; // -- Reserved Bits = 0 (1 bit(s)) 4 | 2: q_reg <= 1'b0; // -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 5 | 3: q_reg <= 1'b0; // 6 | 4: q_reg <= 1'b1; // -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24) 7 | 5: q_reg <= 1'b1; // 8 | 6: q_reg <= 1'b0; // 9 | 7: q_reg <= 1'b0; // 10 | 8: q_reg <= 1'b0; // 11 | 9: q_reg <= 1'b0; // -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 12 | 10: q_reg <= 1'b0; // -- Reserved Bits = 0 (5 bit(s)) 13 | 11: q_reg <= 1'b0; // 14 | 12: q_reg <= 1'b0; // 15 | 13: q_reg <= 1'b0; // 16 | 14: q_reg <= 1'b0; // 17 | 15: q_reg <= 1'b0; // -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 18 | 16: q_reg <= 1'b0; // 19 | 17: q_reg <= 1'b1; // 20 | 18: q_reg <= 1'b1; // -- N counter: Bypass = 1 (1 bit(s)) 21 | 19: q_reg <= 1'b0; // -- N counter: High Count = 0 (8 bit(s)) 22 | 20: q_reg <= 1'b0; // 23 | 21: q_reg <= 1'b0; // 24 | 22: q_reg <= 1'b0; // 25 | 23: q_reg <= 1'b0; // 26 | 24: q_reg <= 1'b0; // 27 | 25: q_reg <= 1'b0; // 28 | 26: q_reg <= 1'b0; // 29 | 27: q_reg <= 1'b0; // -- N counter: Odd Division = 0 (1 bit(s)) 30 | 28: q_reg <= 1'b0; // -- N counter: Low Count = 0 (8 bit(s)) 31 | 29: q_reg <= 1'b0; // 32 | 30: q_reg <= 1'b0; // 33 | 31: q_reg <= 1'b0; // 34 | 32: q_reg <= 1'b0; // 35 | 33: q_reg <= 1'b0; // 36 | 34: q_reg <= 1'b0; // 37 | 35: q_reg <= 1'b0; // 38 | 36: q_reg <= 1'b0; // -- M counter: Bypass = 0 (1 bit(s)) 39 | 37: q_reg <= 1'b0; // -- M counter: High Count = 11 (8 bit(s)) 40 | 38: q_reg <= 1'b0; // 41 | 39: q_reg <= 1'b0; // 42 | 40: q_reg <= 1'b0; // 43 | 41: q_reg <= 1'b1; // 44 | 42: q_reg <= 1'b0; // 45 | 43: q_reg <= 1'b1; // 46 | 44: q_reg <= 1'b1; // 47 | 45: q_reg <= 1'b0; // -- M counter: Odd Division = 0 (1 bit(s)) 48 | 46: q_reg <= 1'b0; // -- M counter: Low Count = 11 (8 bit(s)) 49 | 47: q_reg <= 1'b0; // 50 | 48: q_reg <= 1'b0; // 51 | 49: q_reg <= 1'b0; // 52 | 50: q_reg <= 1'b1; // 53 | 51: q_reg <= 1'b0; // 54 | 52: q_reg <= 1'b1; // 55 | 53: q_reg <= 1'b1; // 56 | 54: q_reg <= 1'b0; // -- clk0 counter: Bypass = 0 (1 bit(s)) 57 | 55: q_reg <= 1'b0; // -- clk0 counter: High Count = 4 (8 bit(s)) 58 | 56: q_reg <= 1'b0; // 59 | 57: q_reg <= 1'b0; // 60 | 58: q_reg <= 1'b0; // 61 | 59: q_reg <= 1'b0; // 62 | 60: q_reg <= 1'b1; // 63 | 61: q_reg <= 1'b0; // 64 | 62: q_reg <= 1'b0; // 65 | 63: q_reg <= 1'b0; // -- clk0 counter: Odd Division = 0 (1 bit(s)) 66 | 64: q_reg <= 1'b0; // -- clk0 counter: Low Count = 4 (8 bit(s)) 67 | 65: q_reg <= 1'b0; // 68 | 66: q_reg <= 1'b0; // 69 | 67: q_reg <= 1'b0; // 70 | 68: q_reg <= 1'b0; // 71 | 69: q_reg <= 1'b1; // 72 | 70: q_reg <= 1'b0; // 73 | 71: q_reg <= 1'b0; // 74 | 72: q_reg <= 1'b0; // -- clk1 counter: Bypass = 0 (1 bit(s)) 75 | 73: q_reg <= 1'b0; // -- clk1 counter: High Count = 2 (8 bit(s)) 76 | 74: q_reg <= 1'b0; // 77 | 75: q_reg <= 1'b0; // 78 | 76: q_reg <= 1'b0; // 79 | 77: q_reg <= 1'b0; // 80 | 78: q_reg <= 1'b0; // 81 | 79: q_reg <= 1'b1; // 82 | 80: q_reg <= 1'b0; // 83 | 81: q_reg <= 1'b0; // -- clk1 counter: Odd Division = 0 (1 bit(s)) 84 | 82: q_reg <= 1'b0; // -- clk1 counter: Low Count = 2 (8 bit(s)) 85 | 83: q_reg <= 1'b0; // 86 | 84: q_reg <= 1'b0; // 87 | 85: q_reg <= 1'b0; // 88 | 86: q_reg <= 1'b0; // 89 | 87: q_reg <= 1'b0; // 90 | 88: q_reg <= 1'b1; // 91 | 89: q_reg <= 1'b0; // 92 | 90: q_reg <= 1'b1; // -- clk2 counter: Bypass = 1 (1 bit(s)) 93 | 91: q_reg <= 1'b0; // -- clk2 counter: High Count = 0 (8 bit(s)) 94 | 92: q_reg <= 1'b0; // 95 | 93: q_reg <= 1'b0; // 96 | 94: q_reg <= 1'b0; // 97 | 95: q_reg <= 1'b0; // 98 | 96: q_reg <= 1'b0; // 99 | 97: q_reg <= 1'b0; // 100 | 98: q_reg <= 1'b0; // 101 | 99: q_reg <= 1'b0; // -- clk2 counter: Odd Division = 0 (1 bit(s)) 102 | 100: q_reg <= 1'b0; // -- clk2 counter: Low Count = 0 (8 bit(s)) 103 | 101: q_reg <= 1'b0; // 104 | 102: q_reg <= 1'b0; // 105 | 103: q_reg <= 1'b0; // 106 | 104: q_reg <= 1'b0; // 107 | 105: q_reg <= 1'b0; // 108 | 106: q_reg <= 1'b0; // 109 | 107: q_reg <= 1'b0; // 110 | 108: q_reg <= 1'b1; // -- clk3 counter: Bypass = 1 (1 bit(s)) 111 | 109: q_reg <= 1'b0; // -- clk3 counter: High Count = 0 (8 bit(s)) 112 | 110: q_reg <= 1'b0; // 113 | 111: q_reg <= 1'b0; // 114 | 112: q_reg <= 1'b0; // 115 | 113: q_reg <= 1'b0; // 116 | 114: q_reg <= 1'b0; // 117 | 115: q_reg <= 1'b0; // 118 | 116: q_reg <= 1'b0; // 119 | 117: q_reg <= 1'b0; // -- clk3 counter: Odd Division = 0 (1 bit(s)) 120 | 118: q_reg <= 1'b0; // -- clk3 counter: Low Count = 0 (8 bit(s)) 121 | 119: q_reg <= 1'b0; // 122 | 120: q_reg <= 1'b0; // 123 | 121: q_reg <= 1'b0; // 124 | 122: q_reg <= 1'b0; // 125 | 123: q_reg <= 1'b0; // 126 | 124: q_reg <= 1'b0; // 127 | 125: q_reg <= 1'b0; // 128 | 126: q_reg <= 1'b1; // -- clk4 counter: Bypass = 1 (1 bit(s)) 129 | 127: q_reg <= 1'b0; // -- clk4 counter: High Count = 0 (8 bit(s)) 130 | 128: q_reg <= 1'b0; // 131 | 129: q_reg <= 1'b0; // 132 | 130: q_reg <= 1'b0; // 133 | 131: q_reg <= 1'b0; // 134 | 132: q_reg <= 1'b0; // 135 | 133: q_reg <= 1'b0; // 136 | 134: q_reg <= 1'b0; // 137 | 135: q_reg <= 1'b0; // -- clk4 counter: Odd Division = 0 (1 bit(s)) 138 | 136: q_reg <= 1'b0; // -- clk4 counter: Low Count = 0 (8 bit(s)) 139 | 137: q_reg <= 1'b0; // 140 | 138: q_reg <= 1'b0; // 141 | 139: q_reg <= 1'b0; // 142 | 140: q_reg <= 1'b0; // 143 | 141: q_reg <= 1'b0; // 144 | 142: q_reg <= 1'b0; // 145 | 143: q_reg <= 1'b0; // 146 | endcase 147 | -------------------------------------------------------------------------------- /source/pll/config/27_MHz.mif: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- MIF file representing initial state of PLL Scan Chain 16 | -- Device Family: MAX 10 17 | -- Device Part: - 18 | -- Device Speed Grade: - 19 | -- PLL Scan Chain: Fast PLL (144 bits) 20 | -- File Name: C:/Users/chriz/Development/lagtester/source/pll/config//480p.mif 21 | -- Generated: Sat Jan 19 15:20:50 2019 22 | 23 | WIDTH=1; 24 | DEPTH=144; 25 | 26 | ADDRESS_RADIX=UNS; 27 | DATA_RADIX=UNS; 28 | 29 | CONTENT BEGIN 30 | 0 : 0; -- Reserved Bits = 0 (1 bit(s)) 31 | 1 : 0; -- Reserved Bits = 0 (1 bit(s)) 32 | 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 33 | 3 : 0; 34 | 4 : 1; -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24) 35 | 5 : 1; 36 | 6 : 0; 37 | 7 : 0; 38 | 8 : 0; 39 | 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 40 | 10 : 0; -- Reserved Bits = 0 (5 bit(s)) 41 | 11 : 0; 42 | 12 : 0; 43 | 13 : 0; 44 | 14 : 0; 45 | 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 46 | 16 : 0; 47 | 17 : 1; 48 | 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) 49 | 19 : 0; -- N counter: High Count = 0 (8 bit(s)) 50 | 20 : 0; 51 | 21 : 0; 52 | 22 : 0; 53 | 23 : 0; 54 | 24 : 0; 55 | 25 : 0; 56 | 26 : 0; 57 | 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) 58 | 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) 59 | 29 : 0; 60 | 30 : 0; 61 | 31 : 0; 62 | 32 : 0; 63 | 33 : 0; 64 | 34 : 0; 65 | 35 : 0; 66 | 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) 67 | 37 : 0; -- M counter: High Count = 12 (8 bit(s)) 68 | 38 : 0; 69 | 39 : 0; 70 | 40 : 0; 71 | 41 : 1; 72 | 42 : 1; 73 | 43 : 0; 74 | 44 : 0; 75 | 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) 76 | 46 : 0; -- M counter: Low Count = 12 (8 bit(s)) 77 | 47 : 0; 78 | 48 : 0; 79 | 49 : 0; 80 | 50 : 1; 81 | 51 : 1; 82 | 52 : 0; 83 | 53 : 0; 84 | 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) 85 | 55 : 0; -- clk0 counter: High Count = 12 (8 bit(s)) 86 | 56 : 0; 87 | 57 : 0; 88 | 58 : 0; 89 | 59 : 1; 90 | 60 : 1; 91 | 61 : 0; 92 | 62 : 0; 93 | 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) 94 | 64 : 0; -- clk0 counter: Low Count = 12 (8 bit(s)) 95 | 65 : 0; 96 | 66 : 0; 97 | 67 : 0; 98 | 68 : 1; 99 | 69 : 1; 100 | 70 : 0; 101 | 71 : 0; 102 | 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) 103 | 73 : 0; -- clk1 counter: High Count = 12 (8 bit(s)) 104 | 74 : 0; 105 | 75 : 0; 106 | 76 : 0; 107 | 77 : 1; 108 | 78 : 1; 109 | 79 : 0; 110 | 80 : 0; 111 | 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) 112 | 82 : 0; -- clk1 counter: Low Count = 12 (8 bit(s)) 113 | 83 : 0; 114 | 84 : 0; 115 | 85 : 0; 116 | 86 : 1; 117 | 87 : 1; 118 | 88 : 0; 119 | 89 : 0; 120 | 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 121 | 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 122 | 92 : 0; 123 | 93 : 0; 124 | 94 : 0; 125 | 95 : 0; 126 | 96 : 0; 127 | 97 : 0; 128 | 98 : 0; 129 | 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) 130 | 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) 131 | 101 : 0; 132 | 102 : 0; 133 | 103 : 0; 134 | 104 : 0; 135 | 105 : 0; 136 | 106 : 0; 137 | 107 : 0; 138 | 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) 139 | 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) 140 | 110 : 0; 141 | 111 : 0; 142 | 112 : 0; 143 | 113 : 0; 144 | 114 : 0; 145 | 115 : 0; 146 | 116 : 0; 147 | 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) 148 | 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) 149 | 119 : 0; 150 | 120 : 0; 151 | 121 : 0; 152 | 122 : 0; 153 | 123 : 0; 154 | 124 : 0; 155 | 125 : 0; 156 | 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) 157 | 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) 158 | 128 : 0; 159 | 129 : 0; 160 | 130 : 0; 161 | 131 : 0; 162 | 132 : 0; 163 | 133 : 0; 164 | 134 : 0; 165 | 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) 166 | 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) 167 | 137 : 0; 168 | 138 : 0; 169 | 139 : 0; 170 | 140 : 0; 171 | 141 : 0; 172 | 142 : 0; 173 | 143 : 0; 174 | END; 175 | -------------------------------------------------------------------------------- /source/pll/config/27_MHz.v: -------------------------------------------------------------------------------- 1 | case (address) 2 | 0: q_reg <= 1'b0; // -- Reserved Bits = 0 (1 bit(s)) 3 | 1: q_reg <= 1'b0; // -- Reserved Bits = 0 (1 bit(s)) 4 | 2: q_reg <= 1'b0; // -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 5 | 3: q_reg <= 1'b0; // 6 | 4: q_reg <= 1'b1; // -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24) 7 | 5: q_reg <= 1'b1; // 8 | 6: q_reg <= 1'b0; // 9 | 7: q_reg <= 1'b0; // 10 | 8: q_reg <= 1'b0; // 11 | 9: q_reg <= 1'b0; // -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 12 | 10: q_reg <= 1'b0; // -- Reserved Bits = 0 (5 bit(s)) 13 | 11: q_reg <= 1'b0; // 14 | 12: q_reg <= 1'b0; // 15 | 13: q_reg <= 1'b0; // 16 | 14: q_reg <= 1'b0; // 17 | 15: q_reg <= 1'b0; // -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 18 | 16: q_reg <= 1'b0; // 19 | 17: q_reg <= 1'b1; // 20 | 18: q_reg <= 1'b1; // -- N counter: Bypass = 1 (1 bit(s)) 21 | 19: q_reg <= 1'b0; // -- N counter: High Count = 0 (8 bit(s)) 22 | 20: q_reg <= 1'b0; // 23 | 21: q_reg <= 1'b0; // 24 | 22: q_reg <= 1'b0; // 25 | 23: q_reg <= 1'b0; // 26 | 24: q_reg <= 1'b0; // 27 | 25: q_reg <= 1'b0; // 28 | 26: q_reg <= 1'b0; // 29 | 27: q_reg <= 1'b0; // -- N counter: Odd Division = 0 (1 bit(s)) 30 | 28: q_reg <= 1'b0; // -- N counter: Low Count = 0 (8 bit(s)) 31 | 29: q_reg <= 1'b0; // 32 | 30: q_reg <= 1'b0; // 33 | 31: q_reg <= 1'b0; // 34 | 32: q_reg <= 1'b0; // 35 | 33: q_reg <= 1'b0; // 36 | 34: q_reg <= 1'b0; // 37 | 35: q_reg <= 1'b0; // 38 | 36: q_reg <= 1'b0; // -- M counter: Bypass = 0 (1 bit(s)) 39 | 37: q_reg <= 1'b0; // -- M counter: High Count = 12 (8 bit(s)) 40 | 38: q_reg <= 1'b0; // 41 | 39: q_reg <= 1'b0; // 42 | 40: q_reg <= 1'b0; // 43 | 41: q_reg <= 1'b1; // 44 | 42: q_reg <= 1'b1; // 45 | 43: q_reg <= 1'b0; // 46 | 44: q_reg <= 1'b0; // 47 | 45: q_reg <= 1'b0; // -- M counter: Odd Division = 0 (1 bit(s)) 48 | 46: q_reg <= 1'b0; // -- M counter: Low Count = 12 (8 bit(s)) 49 | 47: q_reg <= 1'b0; // 50 | 48: q_reg <= 1'b0; // 51 | 49: q_reg <= 1'b0; // 52 | 50: q_reg <= 1'b1; // 53 | 51: q_reg <= 1'b1; // 54 | 52: q_reg <= 1'b0; // 55 | 53: q_reg <= 1'b0; // 56 | 54: q_reg <= 1'b0; // -- clk0 counter: Bypass = 0 (1 bit(s)) 57 | 55: q_reg <= 1'b0; // -- clk0 counter: High Count = 12 (8 bit(s)) 58 | 56: q_reg <= 1'b0; // 59 | 57: q_reg <= 1'b0; // 60 | 58: q_reg <= 1'b0; // 61 | 59: q_reg <= 1'b1; // 62 | 60: q_reg <= 1'b1; // 63 | 61: q_reg <= 1'b0; // 64 | 62: q_reg <= 1'b0; // 65 | 63: q_reg <= 1'b0; // -- clk0 counter: Odd Division = 0 (1 bit(s)) 66 | 64: q_reg <= 1'b0; // -- clk0 counter: Low Count = 12 (8 bit(s)) 67 | 65: q_reg <= 1'b0; // 68 | 66: q_reg <= 1'b0; // 69 | 67: q_reg <= 1'b0; // 70 | 68: q_reg <= 1'b1; // 71 | 69: q_reg <= 1'b1; // 72 | 70: q_reg <= 1'b0; // 73 | 71: q_reg <= 1'b0; // 74 | 72: q_reg <= 1'b0; // -- clk1 counter: Bypass = 0 (1 bit(s)) 75 | 73: q_reg <= 1'b0; // -- clk1 counter: High Count = 12 (8 bit(s)) 76 | 74: q_reg <= 1'b0; // 77 | 75: q_reg <= 1'b0; // 78 | 76: q_reg <= 1'b0; // 79 | 77: q_reg <= 1'b1; // 80 | 78: q_reg <= 1'b1; // 81 | 79: q_reg <= 1'b0; // 82 | 80: q_reg <= 1'b0; // 83 | 81: q_reg <= 1'b0; // -- clk1 counter: Odd Division = 0 (1 bit(s)) 84 | 82: q_reg <= 1'b0; // -- clk1 counter: Low Count = 12 (8 bit(s)) 85 | 83: q_reg <= 1'b0; // 86 | 84: q_reg <= 1'b0; // 87 | 85: q_reg <= 1'b0; // 88 | 86: q_reg <= 1'b1; // 89 | 87: q_reg <= 1'b1; // 90 | 88: q_reg <= 1'b0; // 91 | 89: q_reg <= 1'b0; // 92 | 90: q_reg <= 1'b1; // -- clk2 counter: Bypass = 1 (1 bit(s)) 93 | 91: q_reg <= 1'b0; // -- clk2 counter: High Count = 0 (8 bit(s)) 94 | 92: q_reg <= 1'b0; // 95 | 93: q_reg <= 1'b0; // 96 | 94: q_reg <= 1'b0; // 97 | 95: q_reg <= 1'b0; // 98 | 96: q_reg <= 1'b0; // 99 | 97: q_reg <= 1'b0; // 100 | 98: q_reg <= 1'b0; // 101 | 99: q_reg <= 1'b0; // -- clk2 counter: Odd Division = 0 (1 bit(s)) 102 | 100: q_reg <= 1'b0; // -- clk2 counter: Low Count = 0 (8 bit(s)) 103 | 101: q_reg <= 1'b0; // 104 | 102: q_reg <= 1'b0; // 105 | 103: q_reg <= 1'b0; // 106 | 104: q_reg <= 1'b0; // 107 | 105: q_reg <= 1'b0; // 108 | 106: q_reg <= 1'b0; // 109 | 107: q_reg <= 1'b0; // 110 | 108: q_reg <= 1'b1; // -- clk3 counter: Bypass = 1 (1 bit(s)) 111 | 109: q_reg <= 1'b0; // -- clk3 counter: High Count = 0 (8 bit(s)) 112 | 110: q_reg <= 1'b0; // 113 | 111: q_reg <= 1'b0; // 114 | 112: q_reg <= 1'b0; // 115 | 113: q_reg <= 1'b0; // 116 | 114: q_reg <= 1'b0; // 117 | 115: q_reg <= 1'b0; // 118 | 116: q_reg <= 1'b0; // 119 | 117: q_reg <= 1'b0; // -- clk3 counter: Odd Division = 0 (1 bit(s)) 120 | 118: q_reg <= 1'b0; // -- clk3 counter: Low Count = 0 (8 bit(s)) 121 | 119: q_reg <= 1'b0; // 122 | 120: q_reg <= 1'b0; // 123 | 121: q_reg <= 1'b0; // 124 | 122: q_reg <= 1'b0; // 125 | 123: q_reg <= 1'b0; // 126 | 124: q_reg <= 1'b0; // 127 | 125: q_reg <= 1'b0; // 128 | 126: q_reg <= 1'b1; // -- clk4 counter: Bypass = 1 (1 bit(s)) 129 | 127: q_reg <= 1'b0; // -- clk4 counter: High Count = 0 (8 bit(s)) 130 | 128: q_reg <= 1'b0; // 131 | 129: q_reg <= 1'b0; // 132 | 130: q_reg <= 1'b0; // 133 | 131: q_reg <= 1'b0; // 134 | 132: q_reg <= 1'b0; // 135 | 133: q_reg <= 1'b0; // 136 | 134: q_reg <= 1'b0; // 137 | 135: q_reg <= 1'b0; // -- clk4 counter: Odd Division = 0 (1 bit(s)) 138 | 136: q_reg <= 1'b0; // -- clk4 counter: Low Count = 0 (8 bit(s)) 139 | 137: q_reg <= 1'b0; // 140 | 138: q_reg <= 1'b0; // 141 | 139: q_reg <= 1'b0; // 142 | 140: q_reg <= 1'b0; // 143 | 141: q_reg <= 1'b0; // 144 | 142: q_reg <= 1'b0; // 145 | 143: q_reg <= 1'b0; // 146 | endcase 147 | -------------------------------------------------------------------------------- /source/pll/config/74_25_MHz.mif: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- MIF file representing initial state of PLL Scan Chain 16 | -- Device Family: MAX 10 17 | -- Device Part: - 18 | -- Device Speed Grade: - 19 | -- PLL Scan Chain: Fast PLL (144 bits) 20 | -- File Name: C:/Users/chriz/Development/lagtester/source/pll/config//720p.mif 21 | -- Generated: Sat Jan 19 15:22:20 2019 22 | 23 | WIDTH=1; 24 | DEPTH=144; 25 | 26 | ADDRESS_RADIX=UNS; 27 | DATA_RADIX=UNS; 28 | 29 | CONTENT BEGIN 30 | 0 : 0; -- Reserved Bits = 0 (1 bit(s)) 31 | 1 : 0; -- Reserved Bits = 0 (1 bit(s)) 32 | 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 33 | 3 : 0; 34 | 4 : 1; -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24) 35 | 5 : 1; 36 | 6 : 0; 37 | 7 : 0; 38 | 8 : 0; 39 | 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 40 | 10 : 0; -- Reserved Bits = 0 (5 bit(s)) 41 | 11 : 0; 42 | 12 : 0; 43 | 13 : 0; 44 | 14 : 0; 45 | 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 46 | 16 : 0; 47 | 17 : 1; 48 | 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) 49 | 19 : 0; -- N counter: High Count = 0 (8 bit(s)) 50 | 20 : 0; 51 | 21 : 0; 52 | 22 : 0; 53 | 23 : 0; 54 | 24 : 0; 55 | 25 : 0; 56 | 26 : 0; 57 | 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) 58 | 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) 59 | 29 : 0; 60 | 30 : 0; 61 | 31 : 0; 62 | 32 : 0; 63 | 33 : 0; 64 | 34 : 0; 65 | 35 : 0; 66 | 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) 67 | 37 : 0; -- M counter: High Count = 11 (8 bit(s)) 68 | 38 : 0; 69 | 39 : 0; 70 | 40 : 0; 71 | 41 : 1; 72 | 42 : 0; 73 | 43 : 1; 74 | 44 : 1; 75 | 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) 76 | 46 : 0; -- M counter: Low Count = 11 (8 bit(s)) 77 | 47 : 0; 78 | 48 : 0; 79 | 49 : 0; 80 | 50 : 1; 81 | 51 : 0; 82 | 52 : 1; 83 | 53 : 1; 84 | 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) 85 | 55 : 0; -- clk0 counter: High Count = 4 (8 bit(s)) 86 | 56 : 0; 87 | 57 : 0; 88 | 58 : 0; 89 | 59 : 0; 90 | 60 : 1; 91 | 61 : 0; 92 | 62 : 0; 93 | 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) 94 | 64 : 0; -- clk0 counter: Low Count = 4 (8 bit(s)) 95 | 65 : 0; 96 | 66 : 0; 97 | 67 : 0; 98 | 68 : 0; 99 | 69 : 1; 100 | 70 : 0; 101 | 71 : 0; 102 | 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) 103 | 73 : 0; -- clk1 counter: High Count = 4 (8 bit(s)) 104 | 74 : 0; 105 | 75 : 0; 106 | 76 : 0; 107 | 77 : 0; 108 | 78 : 1; 109 | 79 : 0; 110 | 80 : 0; 111 | 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) 112 | 82 : 0; -- clk1 counter: Low Count = 4 (8 bit(s)) 113 | 83 : 0; 114 | 84 : 0; 115 | 85 : 0; 116 | 86 : 0; 117 | 87 : 1; 118 | 88 : 0; 119 | 89 : 0; 120 | 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 121 | 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 122 | 92 : 0; 123 | 93 : 0; 124 | 94 : 0; 125 | 95 : 0; 126 | 96 : 0; 127 | 97 : 0; 128 | 98 : 0; 129 | 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) 130 | 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) 131 | 101 : 0; 132 | 102 : 0; 133 | 103 : 0; 134 | 104 : 0; 135 | 105 : 0; 136 | 106 : 0; 137 | 107 : 0; 138 | 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) 139 | 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) 140 | 110 : 0; 141 | 111 : 0; 142 | 112 : 0; 143 | 113 : 0; 144 | 114 : 0; 145 | 115 : 0; 146 | 116 : 0; 147 | 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) 148 | 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) 149 | 119 : 0; 150 | 120 : 0; 151 | 121 : 0; 152 | 122 : 0; 153 | 123 : 0; 154 | 124 : 0; 155 | 125 : 0; 156 | 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) 157 | 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) 158 | 128 : 0; 159 | 129 : 0; 160 | 130 : 0; 161 | 131 : 0; 162 | 132 : 0; 163 | 133 : 0; 164 | 134 : 0; 165 | 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) 166 | 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) 167 | 137 : 0; 168 | 138 : 0; 169 | 139 : 0; 170 | 140 : 0; 171 | 141 : 0; 172 | 142 : 0; 173 | 143 : 0; 174 | END; 175 | -------------------------------------------------------------------------------- /source/pll/config/74_25_MHz.v: -------------------------------------------------------------------------------- 1 | case (address) 2 | 0: q_reg <= 1'b0; // -- Reserved Bits = 0 (1 bit(s)) 3 | 1: q_reg <= 1'b0; // -- Reserved Bits = 0 (1 bit(s)) 4 | 2: q_reg <= 1'b0; // -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 5 | 3: q_reg <= 1'b0; // 6 | 4: q_reg <= 1'b1; // -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24) 7 | 5: q_reg <= 1'b1; // 8 | 6: q_reg <= 1'b0; // 9 | 7: q_reg <= 1'b0; // 10 | 8: q_reg <= 1'b0; // 11 | 9: q_reg <= 1'b0; // -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 12 | 10: q_reg <= 1'b0; // -- Reserved Bits = 0 (5 bit(s)) 13 | 11: q_reg <= 1'b0; // 14 | 12: q_reg <= 1'b0; // 15 | 13: q_reg <= 1'b0; // 16 | 14: q_reg <= 1'b0; // 17 | 15: q_reg <= 1'b0; // -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 18 | 16: q_reg <= 1'b0; // 19 | 17: q_reg <= 1'b1; // 20 | 18: q_reg <= 1'b1; // -- N counter: Bypass = 1 (1 bit(s)) 21 | 19: q_reg <= 1'b0; // -- N counter: High Count = 0 (8 bit(s)) 22 | 20: q_reg <= 1'b0; // 23 | 21: q_reg <= 1'b0; // 24 | 22: q_reg <= 1'b0; // 25 | 23: q_reg <= 1'b0; // 26 | 24: q_reg <= 1'b0; // 27 | 25: q_reg <= 1'b0; // 28 | 26: q_reg <= 1'b0; // 29 | 27: q_reg <= 1'b0; // -- N counter: Odd Division = 0 (1 bit(s)) 30 | 28: q_reg <= 1'b0; // -- N counter: Low Count = 0 (8 bit(s)) 31 | 29: q_reg <= 1'b0; // 32 | 30: q_reg <= 1'b0; // 33 | 31: q_reg <= 1'b0; // 34 | 32: q_reg <= 1'b0; // 35 | 33: q_reg <= 1'b0; // 36 | 34: q_reg <= 1'b0; // 37 | 35: q_reg <= 1'b0; // 38 | 36: q_reg <= 1'b0; // -- M counter: Bypass = 0 (1 bit(s)) 39 | 37: q_reg <= 1'b0; // -- M counter: High Count = 11 (8 bit(s)) 40 | 38: q_reg <= 1'b0; // 41 | 39: q_reg <= 1'b0; // 42 | 40: q_reg <= 1'b0; // 43 | 41: q_reg <= 1'b1; // 44 | 42: q_reg <= 1'b0; // 45 | 43: q_reg <= 1'b1; // 46 | 44: q_reg <= 1'b1; // 47 | 45: q_reg <= 1'b0; // -- M counter: Odd Division = 0 (1 bit(s)) 48 | 46: q_reg <= 1'b0; // -- M counter: Low Count = 11 (8 bit(s)) 49 | 47: q_reg <= 1'b0; // 50 | 48: q_reg <= 1'b0; // 51 | 49: q_reg <= 1'b0; // 52 | 50: q_reg <= 1'b1; // 53 | 51: q_reg <= 1'b0; // 54 | 52: q_reg <= 1'b1; // 55 | 53: q_reg <= 1'b1; // 56 | 54: q_reg <= 1'b0; // -- clk0 counter: Bypass = 0 (1 bit(s)) 57 | 55: q_reg <= 1'b0; // -- clk0 counter: High Count = 4 (8 bit(s)) 58 | 56: q_reg <= 1'b0; // 59 | 57: q_reg <= 1'b0; // 60 | 58: q_reg <= 1'b0; // 61 | 59: q_reg <= 1'b0; // 62 | 60: q_reg <= 1'b1; // 63 | 61: q_reg <= 1'b0; // 64 | 62: q_reg <= 1'b0; // 65 | 63: q_reg <= 1'b0; // -- clk0 counter: Odd Division = 0 (1 bit(s)) 66 | 64: q_reg <= 1'b0; // -- clk0 counter: Low Count = 4 (8 bit(s)) 67 | 65: q_reg <= 1'b0; // 68 | 66: q_reg <= 1'b0; // 69 | 67: q_reg <= 1'b0; // 70 | 68: q_reg <= 1'b0; // 71 | 69: q_reg <= 1'b1; // 72 | 70: q_reg <= 1'b0; // 73 | 71: q_reg <= 1'b0; // 74 | 72: q_reg <= 1'b0; // -- clk1 counter: Bypass = 0 (1 bit(s)) 75 | 73: q_reg <= 1'b0; // -- clk1 counter: High Count = 4 (8 bit(s)) 76 | 74: q_reg <= 1'b0; // 77 | 75: q_reg <= 1'b0; // 78 | 76: q_reg <= 1'b0; // 79 | 77: q_reg <= 1'b0; // 80 | 78: q_reg <= 1'b1; // 81 | 79: q_reg <= 1'b0; // 82 | 80: q_reg <= 1'b0; // 83 | 81: q_reg <= 1'b0; // -- clk1 counter: Odd Division = 0 (1 bit(s)) 84 | 82: q_reg <= 1'b0; // -- clk1 counter: Low Count = 4 (8 bit(s)) 85 | 83: q_reg <= 1'b0; // 86 | 84: q_reg <= 1'b0; // 87 | 85: q_reg <= 1'b0; // 88 | 86: q_reg <= 1'b0; // 89 | 87: q_reg <= 1'b1; // 90 | 88: q_reg <= 1'b0; // 91 | 89: q_reg <= 1'b0; // 92 | 90: q_reg <= 1'b1; // -- clk2 counter: Bypass = 1 (1 bit(s)) 93 | 91: q_reg <= 1'b0; // -- clk2 counter: High Count = 0 (8 bit(s)) 94 | 92: q_reg <= 1'b0; // 95 | 93: q_reg <= 1'b0; // 96 | 94: q_reg <= 1'b0; // 97 | 95: q_reg <= 1'b0; // 98 | 96: q_reg <= 1'b0; // 99 | 97: q_reg <= 1'b0; // 100 | 98: q_reg <= 1'b0; // 101 | 99: q_reg <= 1'b0; // -- clk2 counter: Odd Division = 0 (1 bit(s)) 102 | 100: q_reg <= 1'b0; // -- clk2 counter: Low Count = 0 (8 bit(s)) 103 | 101: q_reg <= 1'b0; // 104 | 102: q_reg <= 1'b0; // 105 | 103: q_reg <= 1'b0; // 106 | 104: q_reg <= 1'b0; // 107 | 105: q_reg <= 1'b0; // 108 | 106: q_reg <= 1'b0; // 109 | 107: q_reg <= 1'b0; // 110 | 108: q_reg <= 1'b1; // -- clk3 counter: Bypass = 1 (1 bit(s)) 111 | 109: q_reg <= 1'b0; // -- clk3 counter: High Count = 0 (8 bit(s)) 112 | 110: q_reg <= 1'b0; // 113 | 111: q_reg <= 1'b0; // 114 | 112: q_reg <= 1'b0; // 115 | 113: q_reg <= 1'b0; // 116 | 114: q_reg <= 1'b0; // 117 | 115: q_reg <= 1'b0; // 118 | 116: q_reg <= 1'b0; // 119 | 117: q_reg <= 1'b0; // -- clk3 counter: Odd Division = 0 (1 bit(s)) 120 | 118: q_reg <= 1'b0; // -- clk3 counter: Low Count = 0 (8 bit(s)) 121 | 119: q_reg <= 1'b0; // 122 | 120: q_reg <= 1'b0; // 123 | 121: q_reg <= 1'b0; // 124 | 122: q_reg <= 1'b0; // 125 | 123: q_reg <= 1'b0; // 126 | 124: q_reg <= 1'b0; // 127 | 125: q_reg <= 1'b0; // 128 | 126: q_reg <= 1'b1; // -- clk4 counter: Bypass = 1 (1 bit(s)) 129 | 127: q_reg <= 1'b0; // -- clk4 counter: High Count = 0 (8 bit(s)) 130 | 128: q_reg <= 1'b0; // 131 | 129: q_reg <= 1'b0; // 132 | 130: q_reg <= 1'b0; // 133 | 131: q_reg <= 1'b0; // 134 | 132: q_reg <= 1'b0; // 135 | 133: q_reg <= 1'b0; // 136 | 134: q_reg <= 1'b0; // 137 | 135: q_reg <= 1'b0; // -- clk4 counter: Odd Division = 0 (1 bit(s)) 138 | 136: q_reg <= 1'b0; // -- clk4 counter: Low Count = 0 (8 bit(s)) 139 | 137: q_reg <= 1'b0; // 140 | 138: q_reg <= 1'b0; // 141 | 139: q_reg <= 1'b0; // 142 | 140: q_reg <= 1'b0; // 143 | 141: q_reg <= 1'b0; // 144 | 142: q_reg <= 1'b0; // 145 | 143: q_reg <= 1'b0; // 146 | endcase 147 | -------------------------------------------------------------------------------- /source/pll/config/VGA.mif: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- MIF file representing initial state of PLL Scan Chain 16 | -- Device Family: MAX 10 17 | -- Device Part: - 18 | -- Device Speed Grade: - 19 | -- PLL Scan Chain: Fast PLL (144 bits) 20 | -- File Name: C:/Users/chriz/Development/lagtester/source/pll/config//VGA.mif 21 | -- Generated: Sat Jan 19 15:19:42 2019 22 | 23 | WIDTH=1; 24 | DEPTH=144; 25 | 26 | ADDRESS_RADIX=UNS; 27 | DATA_RADIX=UNS; 28 | 29 | CONTENT BEGIN 30 | 0 : 0; -- Reserved Bits = 0 (1 bit(s)) 31 | 1 : 0; -- Reserved Bits = 0 (1 bit(s)) 32 | 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 33 | 3 : 0; 34 | 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) 35 | 5 : 1; 36 | 6 : 0; 37 | 7 : 1; 38 | 8 : 1; 39 | 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 40 | 10 : 0; -- Reserved Bits = 0 (5 bit(s)) 41 | 11 : 0; 42 | 12 : 0; 43 | 13 : 0; 44 | 14 : 0; 45 | 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 46 | 16 : 0; 47 | 17 : 1; 48 | 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) 49 | 19 : 0; -- N counter: High Count = 0 (8 bit(s)) 50 | 20 : 0; 51 | 21 : 0; 52 | 22 : 0; 53 | 23 : 0; 54 | 24 : 0; 55 | 25 : 0; 56 | 26 : 0; 57 | 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) 58 | 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) 59 | 29 : 0; 60 | 30 : 0; 61 | 31 : 0; 62 | 32 : 0; 63 | 33 : 0; 64 | 34 : 0; 65 | 35 : 0; 66 | 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) 67 | 37 : 0; -- M counter: High Count = 7 (8 bit(s)) 68 | 38 : 0; 69 | 39 : 0; 70 | 40 : 0; 71 | 41 : 0; 72 | 42 : 1; 73 | 43 : 1; 74 | 44 : 1; 75 | 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) 76 | 46 : 0; -- M counter: Low Count = 7 (8 bit(s)) 77 | 47 : 0; 78 | 48 : 0; 79 | 49 : 0; 80 | 50 : 0; 81 | 51 : 1; 82 | 52 : 1; 83 | 53 : 1; 84 | 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) 85 | 55 : 0; -- clk0 counter: High Count = 8 (8 bit(s)) 86 | 56 : 0; 87 | 57 : 0; 88 | 58 : 0; 89 | 59 : 1; 90 | 60 : 0; 91 | 61 : 0; 92 | 62 : 0; 93 | 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s)) 94 | 64 : 0; -- clk0 counter: Low Count = 7 (8 bit(s)) 95 | 65 : 0; 96 | 66 : 0; 97 | 67 : 0; 98 | 68 : 0; 99 | 69 : 1; 100 | 70 : 1; 101 | 71 : 1; 102 | 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) 103 | 73 : 0; -- clk1 counter: High Count = 8 (8 bit(s)) 104 | 74 : 0; 105 | 75 : 0; 106 | 76 : 0; 107 | 77 : 1; 108 | 78 : 0; 109 | 79 : 0; 110 | 80 : 0; 111 | 81 : 1; -- clk1 counter: Odd Division = 1 (1 bit(s)) 112 | 82 : 0; -- clk1 counter: Low Count = 7 (8 bit(s)) 113 | 83 : 0; 114 | 84 : 0; 115 | 85 : 0; 116 | 86 : 0; 117 | 87 : 1; 118 | 88 : 1; 119 | 89 : 1; 120 | 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 121 | 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 122 | 92 : 0; 123 | 93 : 0; 124 | 94 : 0; 125 | 95 : 0; 126 | 96 : 0; 127 | 97 : 0; 128 | 98 : 0; 129 | 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) 130 | 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) 131 | 101 : 0; 132 | 102 : 0; 133 | 103 : 0; 134 | 104 : 0; 135 | 105 : 0; 136 | 106 : 0; 137 | 107 : 0; 138 | 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) 139 | 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) 140 | 110 : 0; 141 | 111 : 0; 142 | 112 : 0; 143 | 113 : 0; 144 | 114 : 0; 145 | 115 : 0; 146 | 116 : 0; 147 | 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) 148 | 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) 149 | 119 : 0; 150 | 120 : 0; 151 | 121 : 0; 152 | 122 : 0; 153 | 123 : 0; 154 | 124 : 0; 155 | 125 : 0; 156 | 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) 157 | 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) 158 | 128 : 0; 159 | 129 : 0; 160 | 130 : 0; 161 | 131 : 0; 162 | 132 : 0; 163 | 133 : 0; 164 | 134 : 0; 165 | 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) 166 | 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) 167 | 137 : 0; 168 | 138 : 0; 169 | 139 : 0; 170 | 140 : 0; 171 | 141 : 0; 172 | 142 : 0; 173 | 143 : 0; 174 | END; 175 | -------------------------------------------------------------------------------- /source/pll/config/create_from_mif.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | my $x=0; 4 | 5 | if (!defined($ARGV[0]) or $ARGV[0] =~ /^\s*$/ or !defined($ARGV[1]) or $ARGV[1] =~ /^\s*$/) { 6 | print "\n usage: create_from_mif \n\n"; 7 | exit 1; 8 | } 9 | 10 | open(MIF_OUT, "> " . $ARGV[1]); 11 | 12 | print MIF_OUT <){ 21 | chomp($_); 22 | 23 | if ($start && $_ =~ /^END;/) { 24 | $start = 0; 25 | } 26 | 27 | if ($start) { 28 | if ($_ =~ /([0-9]+)\s*:\s*([0-9])\s*;(.*)$/) { 29 | print MIF_OUT sprintf(" %d", $1) . ": q_reg <= 1'b" . $2 . "; // " . $3 . "\n"; 30 | } 31 | } 32 | 33 | if ($_ =~ /^CONTENT BEGIN/) { 34 | $start = 1; 35 | } 36 | } 37 | close(MIF_IN); 38 | 39 | print MIF_OUT < 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /source/pll/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 6 | -------------------------------------------------------------------------------- /source/pll/pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.0 Build 625 09/12/2018 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module pll ( 40 | areset, 41 | configupdate, 42 | inclk0, 43 | scanclk, 44 | scanclkena, 45 | scandata, 46 | c0, 47 | c1, 48 | locked, 49 | scandataout, 50 | scandone); 51 | 52 | input areset; 53 | input configupdate; 54 | input inclk0; 55 | input scanclk; 56 | input scanclkena; 57 | input scandata; 58 | output c0; 59 | output c1; 60 | output locked; 61 | output scandataout; 62 | output scandone; 63 | `ifndef ALTERA_RESERVED_QIS 64 | // synopsys translate_off 65 | `endif 66 | tri0 areset; 67 | tri0 configupdate; 68 | tri0 scanclkena; 69 | tri0 scandata; 70 | `ifndef ALTERA_RESERVED_QIS 71 | // synopsys translate_on 72 | `endif 73 | 74 | wire [0:0] sub_wire2 = 1'h0; 75 | wire [4:0] sub_wire3; 76 | wire sub_wire6; 77 | wire sub_wire7; 78 | wire sub_wire8; 79 | wire sub_wire0 = inclk0; 80 | wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; 81 | wire [1:1] sub_wire5 = sub_wire3[1:1]; 82 | wire [0:0] sub_wire4 = sub_wire3[0:0]; 83 | wire c0 = sub_wire4; 84 | wire c1 = sub_wire5; 85 | wire locked = sub_wire6; 86 | wire scandataout = sub_wire7; 87 | wire scandone = sub_wire8; 88 | 89 | altpll altpll_component ( 90 | .areset (areset), 91 | .configupdate (configupdate), 92 | .inclk (sub_wire1), 93 | .scanclk (scanclk), 94 | .scanclkena (scanclkena), 95 | .scandata (scandata), 96 | .clk (sub_wire3), 97 | .locked (sub_wire6), 98 | .scandataout (sub_wire7), 99 | .scandone (sub_wire8), 100 | .activeclock (), 101 | .clkbad (), 102 | .clkena ({6{1'b1}}), 103 | .clkloss (), 104 | .clkswitch (1'b0), 105 | .enable0 (), 106 | .enable1 (), 107 | .extclk (), 108 | .extclkena ({4{1'b1}}), 109 | .fbin (1'b1), 110 | .fbmimicbidir (), 111 | .fbout (), 112 | .fref (), 113 | .icdrclk (), 114 | .pfdena (1'b1), 115 | .phasecounterselect ({4{1'b1}}), 116 | .phasedone (), 117 | .phasestep (1'b1), 118 | .phaseupdown (1'b1), 119 | .pllena (1'b1), 120 | .scanaclr (1'b0), 121 | .scanread (1'b0), 122 | .scanwrite (1'b0), 123 | .sclkout0 (), 124 | .sclkout1 (), 125 | .vcooverrange (), 126 | .vcounderrange ()); 127 | defparam 128 | altpll_component.bandwidth_type = "AUTO", 129 | altpll_component.clk0_divide_by = 4, 130 | altpll_component.clk0_duty_cycle = 50, 131 | altpll_component.clk0_multiply_by = 11, 132 | altpll_component.clk0_phase_shift = "0", 133 | altpll_component.clk1_divide_by = 2, 134 | altpll_component.clk1_duty_cycle = 50, 135 | altpll_component.clk1_multiply_by = 11, 136 | altpll_component.clk1_phase_shift = "0", 137 | altpll_component.inclk0_input_frequency = 37037, 138 | altpll_component.intended_device_family = "MAX 10", 139 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 140 | altpll_component.lpm_type = "altpll", 141 | altpll_component.operation_mode = "NO_COMPENSATION", 142 | altpll_component.pll_type = "AUTO", 143 | altpll_component.port_activeclock = "PORT_UNUSED", 144 | altpll_component.port_areset = "PORT_USED", 145 | altpll_component.port_clkbad0 = "PORT_UNUSED", 146 | altpll_component.port_clkbad1 = "PORT_UNUSED", 147 | altpll_component.port_clkloss = "PORT_UNUSED", 148 | altpll_component.port_clkswitch = "PORT_UNUSED", 149 | altpll_component.port_configupdate = "PORT_USED", 150 | altpll_component.port_fbin = "PORT_UNUSED", 151 | altpll_component.port_inclk0 = "PORT_USED", 152 | altpll_component.port_inclk1 = "PORT_UNUSED", 153 | altpll_component.port_locked = "PORT_USED", 154 | altpll_component.port_pfdena = "PORT_UNUSED", 155 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 156 | altpll_component.port_phasedone = "PORT_UNUSED", 157 | altpll_component.port_phasestep = "PORT_UNUSED", 158 | altpll_component.port_phaseupdown = "PORT_UNUSED", 159 | altpll_component.port_pllena = "PORT_UNUSED", 160 | altpll_component.port_scanaclr = "PORT_UNUSED", 161 | altpll_component.port_scanclk = "PORT_USED", 162 | altpll_component.port_scanclkena = "PORT_USED", 163 | altpll_component.port_scandata = "PORT_USED", 164 | altpll_component.port_scandataout = "PORT_USED", 165 | altpll_component.port_scandone = "PORT_USED", 166 | altpll_component.port_scanread = "PORT_UNUSED", 167 | altpll_component.port_scanwrite = "PORT_UNUSED", 168 | altpll_component.port_clk0 = "PORT_USED", 169 | altpll_component.port_clk1 = "PORT_USED", 170 | altpll_component.port_clk2 = "PORT_UNUSED", 171 | altpll_component.port_clk3 = "PORT_UNUSED", 172 | altpll_component.port_clk4 = "PORT_UNUSED", 173 | altpll_component.port_clk5 = "PORT_UNUSED", 174 | altpll_component.port_clkena0 = "PORT_UNUSED", 175 | altpll_component.port_clkena1 = "PORT_UNUSED", 176 | altpll_component.port_clkena2 = "PORT_UNUSED", 177 | altpll_component.port_clkena3 = "PORT_UNUSED", 178 | altpll_component.port_clkena4 = "PORT_UNUSED", 179 | altpll_component.port_clkena5 = "PORT_UNUSED", 180 | altpll_component.port_extclk0 = "PORT_UNUSED", 181 | altpll_component.port_extclk1 = "PORT_UNUSED", 182 | altpll_component.port_extclk2 = "PORT_UNUSED", 183 | altpll_component.port_extclk3 = "PORT_UNUSED", 184 | altpll_component.self_reset_on_loss_lock = "OFF", 185 | altpll_component.width_clock = 5, 186 | altpll_component.scan_chain_mif_file = "../source/pll/config/default.mif"; 187 | 188 | 189 | endmodule 190 | 191 | // ============================================================ 192 | // CNX file retrieval info 193 | // ============================================================ 194 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 195 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 196 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 197 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 198 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 199 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 200 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 201 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 203 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" 205 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 208 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 209 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 210 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 211 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 212 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 213 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 214 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "74.250000" 215 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "148.500000" 216 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 217 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 218 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 219 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 220 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 221 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 222 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 223 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" 224 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 225 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 226 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 227 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 228 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 229 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" 230 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 231 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" 232 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 233 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 234 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 235 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 236 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" 237 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 238 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 239 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 240 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 241 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 242 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" 243 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "74.25000000" 244 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "148.50000000" 245 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 246 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 247 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 248 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 249 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 250 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 251 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 252 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 253 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 254 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 255 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" 256 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 257 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" 258 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 259 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 260 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 261 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 262 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 263 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 264 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 265 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 266 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "../source/pll/config/default.mif" 267 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" 268 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 269 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 270 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 271 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 272 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 273 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 274 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 275 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 276 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 277 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 278 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 279 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" 280 | // Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" 281 | // Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" 282 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 283 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 284 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 285 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 286 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 287 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 288 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 289 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 290 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 291 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 292 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 293 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4" 294 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 295 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11" 296 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 297 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" 298 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 299 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11" 300 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 301 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" 302 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" 303 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 304 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" 305 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 306 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 307 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" 308 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 309 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 310 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 311 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 312 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" 313 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 314 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 315 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 316 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" 317 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 318 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 319 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 320 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 321 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 322 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 323 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 324 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" 325 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" 326 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" 327 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" 328 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" 329 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 330 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 331 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 332 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 333 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 334 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 335 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 336 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 337 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 338 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 339 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 340 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 341 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 342 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 343 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 344 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 345 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 346 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 347 | // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" 348 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 349 | // Retrieval info: CONSTANT: scan_chain_mif_file STRING "../source/pll/config/default.mif" 350 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 351 | // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" 352 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 353 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 354 | // Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" 355 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 356 | // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" 357 | // Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" 358 | // Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" 359 | // Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" 360 | // Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" 361 | // Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" 362 | // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 363 | // Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 364 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 365 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 366 | // Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 367 | // Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 368 | // Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 369 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 370 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 371 | // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 372 | // Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 373 | // Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 374 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 375 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 376 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 377 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 378 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 379 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 380 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE 381 | // Retrieval info: GEN_FILE: TYPE_NORMAL default.mif TRUE 382 | // Retrieval info: LIB_FILE: altera_mf 383 | // Retrieval info: CBX_MODULE_PREFIX: ON 384 | -------------------------------------------------------------------------------- /source/pll/pll_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.0 Build 625 09/12/2018 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module pll ( 35 | areset, 36 | configupdate, 37 | inclk0, 38 | scanclk, 39 | scanclkena, 40 | scandata, 41 | c0, 42 | c1, 43 | locked, 44 | scandataout, 45 | scandone); 46 | 47 | input areset; 48 | input configupdate; 49 | input inclk0; 50 | input scanclk; 51 | input scanclkena; 52 | input scandata; 53 | output c0; 54 | output c1; 55 | output locked; 56 | output scandataout; 57 | output scandone; 58 | `ifndef ALTERA_RESERVED_QIS 59 | // synopsys translate_off 60 | `endif 61 | tri0 areset; 62 | tri0 configupdate; 63 | tri0 scanclkena; 64 | tri0 scandata; 65 | `ifndef ALTERA_RESERVED_QIS 66 | // synopsys translate_on 67 | `endif 68 | 69 | endmodule 70 | 71 | // ============================================================ 72 | // CNX file retrieval info 73 | // ============================================================ 74 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 75 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 76 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 77 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 78 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 79 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 80 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 81 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 82 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 83 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 84 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 85 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 86 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 87 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 88 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 89 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 90 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 91 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 92 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 93 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 94 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.200001" 95 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.200001" 96 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 97 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 98 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 99 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 100 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 101 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 102 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 103 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" 104 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 105 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 106 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 107 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 108 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 109 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" 110 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 111 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" 112 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 113 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 114 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 115 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 116 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" 117 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 118 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 119 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 120 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 121 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 122 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 123 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000" 124 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.20000000" 125 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 126 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 127 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 128 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 129 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 130 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 131 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 132 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 133 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 134 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 135 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" 136 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 137 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" 138 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 139 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 140 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 141 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 142 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 143 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 144 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 145 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 146 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 147 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" 148 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 149 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 150 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 151 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 152 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 153 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 154 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 155 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 156 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 157 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 158 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 159 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" 160 | // Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" 161 | // Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" 162 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 163 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 164 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 165 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 166 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 167 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 168 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 169 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 170 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 171 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 172 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 173 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15" 174 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 175 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14" 176 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 177 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15" 178 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 179 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "14" 180 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 181 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 182 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" 183 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" 184 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 185 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 186 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 187 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 188 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" 189 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 190 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 191 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 192 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 193 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" 194 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 195 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 196 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 197 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" 198 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 199 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 200 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 201 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 202 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 203 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 204 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 205 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" 206 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" 207 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" 208 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" 209 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" 210 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 211 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 212 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 213 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 214 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 215 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 216 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 217 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 218 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 219 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 220 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 221 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 222 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 223 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 224 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 225 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 226 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 227 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 228 | // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" 229 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 230 | // Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll.mif" 231 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 232 | // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" 233 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 234 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 235 | // Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" 236 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 237 | // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" 238 | // Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" 239 | // Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" 240 | // Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" 241 | // Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" 242 | // Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" 243 | // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 244 | // Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 245 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 246 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 247 | // Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 248 | // Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 249 | // Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 250 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 251 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 252 | // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 253 | // Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 254 | // Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 255 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 256 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 257 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 258 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 259 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 260 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 261 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 262 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.mif TRUE 263 | // Retrieval info: LIB_FILE: altera_mf 264 | // Retrieval info: CBX_MODULE_PREFIX: ON 265 | -------------------------------------------------------------------------------- /source/pll/pll_main.v: -------------------------------------------------------------------------------- 1 | module pll_main( 2 | input clock, 3 | input reset, 4 | input [7:0] data, 5 | 6 | output clock_out, 7 | output clock_out_video, 8 | output locked 9 | ); 10 | wire pll_areset; 11 | wire pll_scanclk; 12 | wire pll_scandata; 13 | wire pll_scanclkena; 14 | wire pll_configupdate; 15 | wire pll_locked; 16 | wire pll_scandataout; 17 | wire pll_scandone; 18 | 19 | wire pll_reconfig; 20 | wire pll_reconf_busy; 21 | wire pll_write_from_rom; 22 | wire pll_rom_data_in; 23 | wire [7:0] pll_rom_address_out; 24 | wire pll_write_rom_ena; 25 | wire pll_lockloss; 26 | 27 | edge_detect pll_lockloss_check( 28 | .async_sig(~pll_locked), 29 | .clk(clock), 30 | .rise(pll_lockloss) 31 | ); 32 | 33 | pll pll ( 34 | .inclk0(clock), 35 | .c0(clock_out), 36 | .c1(clock_out_video), 37 | .locked(pll_locked), 38 | 39 | .areset(pll_areset), 40 | .scanclk(pll_scanclk), 41 | .scandata(pll_scandata), 42 | .scanclkena(pll_scanclkena), 43 | .configupdate(pll_configupdate), 44 | .scandataout(pll_scandataout), 45 | .scandone(pll_scandone) 46 | ); 47 | 48 | pll_reconf pll_reconf( 49 | .clock(clock), 50 | .reconfig(pll_reconfig), 51 | .busy(pll_reconf_busy), 52 | .data_in(9'b0), 53 | .counter_type(4'b0), 54 | .counter_param(3'b0), 55 | 56 | .pll_areset_in(reset || pll_lockloss), 57 | 58 | .pll_scandataout(pll_scandataout), 59 | .pll_scandone(pll_scandone), 60 | .pll_areset(pll_areset), 61 | .pll_configupdate(pll_configupdate), 62 | .pll_scanclk(pll_scanclk), 63 | .pll_scanclkena(pll_scanclkena), 64 | .pll_scandata(pll_scandata), 65 | 66 | .write_from_rom(pll_write_from_rom), 67 | .rom_data_in(pll_rom_data_in), 68 | .rom_address_out(pll_rom_address_out), 69 | .write_rom_ena(pll_write_rom_ena) 70 | ); 71 | 72 | pll_reconf_rom reconf_rom( 73 | .clock(clock), 74 | .address(pll_rom_address_out), 75 | .read_ena(pll_write_rom_ena), 76 | .data(data), 77 | .q(pll_rom_data_in), 78 | .reconfig(pll_reconfig), 79 | .trigger_read(pll_write_from_rom), 80 | .pll_reconf_busy(pll_reconf_busy) 81 | ); 82 | 83 | assign locked = pll_locked; 84 | 85 | endmodule -------------------------------------------------------------------------------- /source/pll/pll_reconf.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconf.v"] 5 | -------------------------------------------------------------------------------- /source/pll/pll_reconf_rom.v: -------------------------------------------------------------------------------- 1 | `include "../defines.v" 2 | 3 | module pll_reconf_rom ( 4 | input clock, 5 | input [7:0] address, 6 | input read_ena, 7 | input [7:0] data, 8 | input pll_reconf_busy, 9 | 10 | output q, 11 | output reconfig, 12 | output reg trigger_read 13 | ); 14 | 15 | reg _read_ena = 0; 16 | reg q_reg; 17 | reg q_reg_2; 18 | reg doReconfig; 19 | reg doReconfig_2; 20 | reg doReconfig_3; 21 | 22 | reg [7:0] data_req = 8'h_FF; 23 | 24 | assign q = q_reg_2; 25 | assign reconfig = doReconfig_3; 26 | 27 | always @(posedge clock) begin 28 | _read_ena <= read_ena; 29 | 30 | if (_read_ena && ~read_ena) begin 31 | doReconfig <= 1; 32 | end else begin 33 | doReconfig <= 0; 34 | end 35 | 36 | if (~pll_reconf_busy && data != data_req) begin 37 | data_req <= data; 38 | trigger_read <= 1'b1; 39 | end else begin 40 | trigger_read <= 1'b0; 41 | end 42 | 43 | // RECONF 44 | case (data_req) 45 | // RECONF 46 | `MODE_1080p: begin 47 | `include "config/148_5_Mhz.v" 48 | end 49 | `MODE_1080i: begin 50 | `include "config/74_25_MHz.v" 51 | end 52 | `MODE_720p: begin 53 | `include "config/74_25_MHz.v" 54 | end 55 | `MODE_480p: begin 56 | `include "config/27_MHz.v" 57 | end 58 | `MODE_480i: begin 59 | `include "config/27_MHz.v" 60 | end 61 | endcase 62 | 63 | // delay output, to match ROM based timing 64 | q_reg_2 <= q_reg; 65 | doReconfig_2 <= doReconfig; 66 | doReconfig_3 <= doReconfig_2; 67 | end 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /source/sensor.v: -------------------------------------------------------------------------------- 1 | module sensor( 2 | input clock, 3 | input sensor, 4 | output reg sensor_out, 5 | output sensor_trigger 6 | ); 7 | 8 | reg prev_sensor_input = 0; 9 | 10 | always @(posedge clock) begin 11 | sensor_out <= ~sensor; 12 | prev_sensor_input <= sensor_out; 13 | end 14 | 15 | assign sensor_trigger = (~prev_sensor_input && sensor_out); 16 | 17 | endmodule -------------------------------------------------------------------------------- /source/tfp410/I2C.v: -------------------------------------------------------------------------------- 1 | module I2C( 2 | // clock and reset 3 | input clk, 4 | input reset, 5 | 6 | // inputs 7 | input [6:0] chip_addr, 8 | input [7:0] reg_addr, 9 | input [7:0] value, 10 | input enable, 11 | input is_read, 12 | 13 | // I2C pins 14 | inout sda, 15 | inout scl, 16 | 17 | // outputs 18 | output reg [7:0] data, 19 | output reg done, 20 | output i2c_ack_error, 21 | input [31:0] divider 22 | ); 23 | 24 | reg i2c_ena; 25 | reg [6:0] i2c_addr; 26 | reg i2c_rw; 27 | reg [7:0] i2c_data_wr; 28 | reg i2c_busy; 29 | reg [7:0] i2c_data_rd; 30 | 31 | i2c_master i2c_master( 32 | .clk (clk), 33 | .reset_n (1'b1), 34 | .ena (i2c_ena), 35 | .addr (i2c_addr), 36 | .rw (i2c_rw), 37 | .data_wr (i2c_data_wr), 38 | .busy (i2c_busy), 39 | .data_rd (i2c_data_rd), 40 | .ack_error (i2c_ack_error), 41 | .sda (sda), 42 | .scl (scl), 43 | .divider (divider) 44 | ); 45 | 46 | (* syn_encoding = "safe" *) 47 | reg [1:0] state; 48 | reg [5:0] busy_cnt; 49 | reg busy_prev; 50 | 51 | reg [6:0] chip_addr_reg; 52 | reg [7:0] reg_addr_reg; 53 | reg [7:0] value_reg; 54 | 55 | localparam s_idle = 0, 56 | s_send = 1; 57 | 58 | initial begin 59 | state <= s_idle; 60 | busy_cnt = 0; 61 | done <= 1'b1; 62 | end 63 | 64 | always @ (posedge clk) begin 65 | if (~reset) begin 66 | state <= s_idle; 67 | busy_cnt = 0; 68 | done <= 1'b1; 69 | end 70 | else begin 71 | case(state) 72 | s_idle: begin 73 | if (enable) begin 74 | chip_addr_reg <= chip_addr; 75 | reg_addr_reg <= reg_addr; 76 | value_reg <= value; 77 | done <= 1'b0; 78 | state <= s_send; 79 | end 80 | end 81 | 82 | s_send: begin 83 | busy_prev <= i2c_busy; 84 | if (~busy_prev && i2c_busy) begin 85 | busy_cnt = busy_cnt + 1'b1; 86 | end 87 | case (busy_cnt) 88 | 0: begin 89 | i2c_ena <= 1'b1; 90 | i2c_addr <= chip_addr_reg; 91 | i2c_rw <= 1'b0; 92 | i2c_data_wr <= reg_addr_reg; 93 | end 94 | 95 | 1: begin 96 | if (is_read) begin 97 | i2c_rw <= 1'b1; 98 | end else begin 99 | i2c_data_wr <= value_reg; 100 | end 101 | end 102 | 103 | 2: begin 104 | i2c_ena <= 1'b0; 105 | if (~i2c_busy) begin 106 | data <= i2c_data_rd; 107 | busy_cnt = 0; 108 | done <= 1'b1; 109 | state <= s_idle; 110 | end 111 | end 112 | endcase 113 | end 114 | endcase 115 | end 116 | end 117 | 118 | endmodule 119 | 120 | -------------------------------------------------------------------------------- /source/tfp410/i2c_master.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- FileName: i2c_master.vhd 4 | -- Dependencies: none 5 | -- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version 6 | -- 7 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 8 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 9 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 10 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 11 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 12 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 13 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 14 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 15 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 16 | -- 17 | -- Version History 18 | -- Version 1.0 11/01/2012 Scott Larson 19 | -- Initial Public Release 20 | -- Version 2.0 06/20/2014 Scott Larson 21 | -- Added ability to interface with different slaves in the same transaction 22 | -- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error 23 | -- Corrected timing of when ack_error signal clears 24 | -- Version 2.1 10/21/2014 Scott Larson 25 | -- Replaced gated clock with clock enable 26 | -- Adjusted timing of SCL during start and stop conditions 27 | -- Version 2.2 02/05/2015 Scott Larson 28 | -- Corrected small SDA glitch introduced in version 2.1 29 | -- 30 | -------------------------------------------------------------------------------- 31 | 32 | LIBRARY ieee; 33 | USE ieee.std_logic_1164.all; 34 | USE ieee.std_logic_unsigned.all; 35 | 36 | ENTITY i2c_master IS 37 | PORT( 38 | clk : IN STD_LOGIC; --system clock 39 | reset_n : IN STD_LOGIC; --active low reset 40 | ena : IN STD_LOGIC; --latch in command 41 | addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave 42 | rw : IN STD_LOGIC; --'0' is write, '1' is read 43 | data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave 44 | busy : OUT STD_LOGIC; --indicates transaction in progress 45 | data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave 46 | ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave 47 | sda : INOUT STD_LOGIC; --serial data output of i2c bus 48 | scl : INOUT STD_LOGIC; --serial clock output of i2c bus 49 | divider : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); 50 | END i2c_master; 51 | 52 | ARCHITECTURE logic OF i2c_master IS 53 | TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states 54 | SIGNAL state : machine; --state machine 55 | SIGNAL data_clk : STD_LOGIC; --data clock for sda 56 | SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock 57 | SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl 58 | SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output 59 | SIGNAL sda_int : STD_LOGIC := '1'; --internal sda 60 | SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output 61 | SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write 62 | SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave 63 | SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave 64 | SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction 65 | SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl 66 | BEGIN 67 | --generate the timing for the bus clock (scl_clk) and the data clock (data_clk) 68 | PROCESS(clk, reset_n) 69 | VARIABLE count : INTEGER RANGE 0 TO 255; --timing for clock generation 70 | BEGIN 71 | IF(reset_n = '0') THEN --reset asserted 72 | stretch <= '0'; 73 | count := 0; 74 | ELSIF(clk'EVENT AND clk = '1') THEN 75 | data_clk_prev <= data_clk; --store previous value of data clock 76 | IF(count = divider(31 downto 24)-1) THEN --end of timing cycle 77 | count := 0; --reset timer 78 | ELSIF(stretch = '0') THEN --clock stretching from slave not detected 79 | count := count + 1; --continue clock generation timing 80 | END IF; 81 | IF(count < divider(7 downto 0)) THEN 82 | scl_clk <= '0'; 83 | data_clk <= '0'; 84 | ELSIF(count < divider(15 downto 8)) THEN 85 | scl_clk <= '0'; 86 | data_clk <= '1'; 87 | ELSIF(count < divider(23 downto 16)) THEN 88 | scl_clk <= '1'; --release scl 89 | IF(scl = '0') THEN --detect if slave is stretching clock 90 | stretch <= '1'; 91 | ELSE 92 | stretch <= '0'; 93 | END IF; 94 | data_clk <= '1'; 95 | ELSE 96 | scl_clk <= '1'; 97 | data_clk <= '0'; 98 | END IF; 99 | -- IF(count < div1) THEN 100 | -- scl_clk <= '0'; 101 | -- data_clk <= '0'; 102 | -- ELSIF(count < div2) THEN 103 | -- scl_clk <= '0'; 104 | -- data_clk <= '1'; 105 | -- ELSIF(count < div3) THEN 106 | -- scl_clk <= '1'; --release scl 107 | -- IF(scl = '0') THEN --detect if slave is stretching clock 108 | -- stretch <= '1'; 109 | -- ELSE 110 | -- stretch <= '0'; 111 | -- END IF; 112 | -- data_clk <= '1'; 113 | -- ELSE 114 | -- scl_clk <= '1'; 115 | -- data_clk <= '0'; 116 | -- END IF; 117 | END IF; 118 | END PROCESS; 119 | 120 | --state machine and writing to sda during scl low (data_clk rising edge) 121 | PROCESS(clk, reset_n) 122 | BEGIN 123 | IF(reset_n = '0') THEN --reset asserted 124 | state <= ready; --return to initial state 125 | busy <= '1'; --indicate not available 126 | scl_ena <= '0'; --sets scl high impedance 127 | sda_int <= '1'; --sets sda high impedance 128 | ack_error <= '0'; --clear acknowledge error flag 129 | bit_cnt <= 7; --restarts data bit counter 130 | data_rd <= "00000000"; --clear data read port 131 | ELSIF(clk'EVENT AND clk = '1') THEN 132 | IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge 133 | CASE state IS 134 | WHEN ready => --idle state 135 | IF(ena = '1') THEN --transaction requested 136 | busy <= '1'; --flag busy 137 | addr_rw <= addr & rw; --collect requested slave address and command 138 | data_tx <= data_wr; --collect requested data to write 139 | state <= start; --go to start bit 140 | ELSE --remain idle 141 | busy <= '0'; --unflag busy 142 | state <= ready; --remain idle 143 | END IF; 144 | WHEN start => --start bit of transaction 145 | busy <= '1'; --resume busy if continuous mode 146 | sda_int <= addr_rw(bit_cnt); --set first address bit to bus 147 | state <= command; --go to command 148 | WHEN command => --address and command byte of transaction 149 | IF(bit_cnt = 0) THEN --command transmit finished 150 | sda_int <= '1'; --release sda for slave acknowledge 151 | bit_cnt <= 7; --reset bit counter for "byte" states 152 | state <= slv_ack1; --go to slave acknowledge (command) 153 | ELSE --next clock cycle of command state 154 | bit_cnt <= bit_cnt - 1; --keep track of transaction bits 155 | sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus 156 | state <= command; --continue with command 157 | END IF; 158 | WHEN slv_ack1 => --slave acknowledge bit (command) 159 | IF(addr_rw(0) = '0') THEN --write command 160 | sda_int <= data_tx(bit_cnt); --write first bit of data 161 | state <= wr; --go to write byte 162 | ELSE --read command 163 | sda_int <= '1'; --release sda from incoming data 164 | state <= rd; --go to read byte 165 | END IF; 166 | WHEN wr => --write byte of transaction 167 | busy <= '1'; --resume busy if continuous mode 168 | IF(bit_cnt = 0) THEN --write byte transmit finished 169 | sda_int <= '1'; --release sda for slave acknowledge 170 | bit_cnt <= 7; --reset bit counter for "byte" states 171 | state <= slv_ack2; --go to slave acknowledge (write) 172 | ELSE --next clock cycle of write state 173 | bit_cnt <= bit_cnt - 1; --keep track of transaction bits 174 | sda_int <= data_tx(bit_cnt-1); --write next bit to bus 175 | state <= wr; --continue writing 176 | END IF; 177 | WHEN rd => --read byte of transaction 178 | busy <= '1'; --resume busy if continuous mode 179 | IF(bit_cnt = 0) THEN --read byte receive finished 180 | IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address 181 | sda_int <= '0'; --acknowledge the byte has been received 182 | ELSE --stopping or continuing with a write 183 | sda_int <= '1'; --send a no-acknowledge (before stop or repeated start) 184 | END IF; 185 | bit_cnt <= 7; --reset bit counter for "byte" states 186 | data_rd <= data_rx; --output received data 187 | state <= mstr_ack; --go to master acknowledge 188 | ELSE --next clock cycle of read state 189 | bit_cnt <= bit_cnt - 1; --keep track of transaction bits 190 | state <= rd; --continue reading 191 | END IF; 192 | WHEN slv_ack2 => --slave acknowledge bit (write) 193 | IF(ena = '1') THEN --continue transaction 194 | busy <= '0'; --continue is accepted 195 | addr_rw <= addr & rw; --collect requested slave address and command 196 | data_tx <= data_wr; --collect requested data to write 197 | IF(addr_rw = addr & rw) THEN --continue transaction with another write 198 | sda_int <= data_wr(bit_cnt); --write first bit of data 199 | state <= wr; --go to write byte 200 | ELSE --continue transaction with a read or new slave 201 | state <= start; --go to repeated start 202 | END IF; 203 | ELSE --complete transaction 204 | state <= stop; --go to stop bit 205 | END IF; 206 | WHEN mstr_ack => --master acknowledge bit after a read 207 | IF(ena = '1') THEN --continue transaction 208 | busy <= '0'; --continue is accepted and data received is available on bus 209 | addr_rw <= addr & rw; --collect requested slave address and command 210 | data_tx <= data_wr; --collect requested data to write 211 | IF(addr_rw = addr & rw) THEN --continue transaction with another read 212 | sda_int <= '1'; --release sda from incoming data 213 | state <= rd; --go to read byte 214 | ELSE --continue transaction with a write or new slave 215 | state <= start; --repeated start 216 | END IF; 217 | ELSE --complete transaction 218 | state <= stop; --go to stop bit 219 | END IF; 220 | WHEN stop => --stop bit of transaction 221 | busy <= '0'; --unflag busy 222 | state <= ready; --go to idle state 223 | END CASE; 224 | ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge 225 | CASE state IS 226 | WHEN start => 227 | IF(scl_ena = '0') THEN --starting new transaction 228 | scl_ena <= '1'; --enable scl output 229 | ack_error <= '0'; --reset acknowledge error output 230 | END IF; 231 | WHEN slv_ack1 => --receiving slave acknowledge (command) 232 | IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge 233 | ack_error <= '1'; --set error output if no-acknowledge 234 | END IF; 235 | WHEN rd => --receiving slave data 236 | data_rx(bit_cnt) <= sda; --receive current slave data bit 237 | WHEN slv_ack2 => --receiving slave acknowledge (write) 238 | IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge 239 | ack_error <= '1'; --set error output if no-acknowledge 240 | END IF; 241 | WHEN stop => 242 | scl_ena <= '0'; --disable scl 243 | WHEN OTHERS => 244 | NULL; 245 | END CASE; 246 | END IF; 247 | END IF; 248 | END PROCESS; 249 | 250 | --set sda output 251 | WITH state SELECT 252 | sda_ena_n <= data_clk_prev WHEN start, --generate start condition 253 | NOT data_clk_prev WHEN stop, --generate stop condition 254 | sda_int WHEN OTHERS; --set to internal sda signal 255 | 256 | --set scl and sda outputs 257 | scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; 258 | sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; 259 | 260 | END logic; 261 | -------------------------------------------------------------------------------- /source/tfp410/tfp410.v: -------------------------------------------------------------------------------- 1 | //`include "config.inc" 2 | 3 | module TFP410( 4 | input clk, 5 | input reset, 6 | input output_ready, 7 | 8 | inout sda, 9 | inout scl, 10 | output reg ready, 11 | output reg hpd_detected 12 | ); 13 | 14 | reg [6:0] i2c_chip_addr; 15 | reg [7:0] i2c_reg_addr; 16 | reg [7:0] i2c_value; 17 | reg i2c_enable; 18 | reg i2c_is_read; 19 | 20 | wire [7:0] i2c_data; 21 | wire i2c_done; 22 | wire i2c_ack_error; 23 | 24 | I2C I2C( 25 | .clk (clk), 26 | .reset (1'b1), 27 | 28 | .chip_addr (i2c_chip_addr), 29 | .reg_addr (i2c_reg_addr), 30 | .value (i2c_value), 31 | .enable (i2c_enable), 32 | .is_read (i2c_is_read), 33 | 34 | .sda (sda), 35 | .scl (scl), 36 | 37 | .data (i2c_data), 38 | .done (i2c_done), 39 | .i2c_ack_error (i2c_ack_error), 40 | 41 | .divider (32'h_C8_96_64_32) 42 | ); 43 | 44 | (* syn_encoding = "safe" *) 45 | reg [1:0] state; 46 | reg [2:0] cmd_counter; 47 | reg [5:0] subcmd_counter; 48 | 49 | localparam CHIP_ADDR = 7'h38; 50 | localparam s_start = 0, 51 | s_wait = 1, 52 | s_wait_2 = 2, 53 | s_idle = 3; 54 | localparam cs_pwrdown = 3'd0, 55 | cs_init = 3'd1, 56 | cs_init2 = 3'd2, 57 | cs_pllcheck = 3'd3, 58 | cs_hpdcheck = 3'd4, 59 | cs_ready = 3'd5; 60 | localparam scs_start = 6'd0; 61 | 62 | initial begin 63 | ready <= 0; 64 | end 65 | 66 | reg [32:0] counter = 0; 67 | 68 | always @ (posedge clk) begin 69 | if (~reset) begin 70 | state <= s_start; 71 | cmd_counter <= cs_pwrdown; 72 | subcmd_counter <= scs_start; 73 | i2c_enable <= 1'b0; 74 | end else begin 75 | case (state) 76 | s_start: begin 77 | if (i2c_done) begin 78 | case (cmd_counter) 79 | cs_pwrdown: begin 80 | ready <= 1'b0; 81 | powerdown(cs_init); 82 | end 83 | cs_init: monitor_hpd(cs_init2, cs_pwrdown); 84 | cs_init2: init(cs_pllcheck); 85 | cs_pllcheck: pllcheck(cs_ready, cs_pllcheck); 86 | 87 | cs_hpdcheck: monitor_hpd(cs_ready, cs_pwrdown); 88 | 89 | default: begin 90 | cmd_counter <= cs_init; 91 | subcmd_counter <= scs_start; 92 | state <= s_idle; 93 | ready <= 1'b1; 94 | end 95 | endcase 96 | end 97 | end 98 | 99 | s_wait: begin 100 | state <= s_wait_2; 101 | end 102 | 103 | s_wait_2: begin 104 | i2c_enable <= 1'b0; 105 | 106 | if (i2c_done) begin 107 | if (~i2c_ack_error) begin 108 | subcmd_counter <= subcmd_counter + 1'b1; 109 | end 110 | state <= s_start; 111 | end 112 | end 113 | 114 | s_idle: begin 115 | if (~output_ready) begin 116 | state <= s_start; 117 | cmd_counter <= cs_pwrdown; 118 | subcmd_counter <= scs_start; 119 | end else if (counter == 32'd_16_000_000) begin 120 | state <= s_start; 121 | cmd_counter <= cs_hpdcheck; 122 | subcmd_counter <= scs_start; 123 | counter <= 1'b0; 124 | end else begin 125 | counter <= counter + 1'b1; 126 | end 127 | end 128 | 129 | endcase 130 | end 131 | end 132 | 133 | task write_i2c; 134 | input [6:0] t_chip_addr; 135 | input [15:0] t_data; 136 | 137 | begin 138 | i2c_chip_addr <= t_chip_addr; 139 | i2c_reg_addr <= t_data[15:8]; 140 | i2c_value <= t_data[7:0]; 141 | i2c_enable <= 1'b1; 142 | i2c_is_read <= 1'b0; 143 | state <= s_wait; 144 | end 145 | endtask 146 | 147 | task read_i2c; 148 | input [6:0] t_chip_addr; 149 | input [7:0] t_addr; 150 | 151 | begin 152 | i2c_chip_addr <= t_chip_addr; 153 | i2c_reg_addr <= t_addr; 154 | i2c_enable <= 1'b1; 155 | i2c_is_read <= 1'b1; 156 | state <= s_wait; 157 | end 158 | endtask 159 | 160 | // ---------------------------------------------------------------- 161 | task monitor_hpd; 162 | input [2:0] success_cmd; 163 | input [2:0] failure_cmd; 164 | 165 | begin 166 | case (subcmd_counter) 167 | 0: write_i2c(CHIP_ADDR, 16'h_09_01); // -> clears interrupt state, mark all interrupts as detected 168 | // check status 169 | 1: read_i2c(CHIP_ADDR, 8'h_09); 170 | 2: begin 171 | if (i2c_data[2] && i2c_data[1]) begin 172 | cmd_counter <= success_cmd; 173 | subcmd_counter <= scs_start; 174 | hpd_detected <= 1'b1; 175 | end else begin 176 | cmd_counter <= failure_cmd; 177 | subcmd_counter <= scs_start; 178 | hpd_detected <= 1'b0; 179 | end 180 | end 181 | endcase 182 | end 183 | endtask 184 | 185 | task init; 186 | input [2:0] next_cmd; 187 | 188 | begin 189 | case (subcmd_counter) 190 | 0: write_i2c(CHIP_ADDR, 16'h_08_BF); // CTL_1_MODE 191 | 1: write_i2c(CHIP_ADDR, 16'h_09_00); // CTL_2_MODE 192 | 2: write_i2c(CHIP_ADDR, 16'h_0A_80); // CTL_3_MODE 193 | 3: write_i2c(CHIP_ADDR, 16'h_33_00); // DE_CTL 194 | default: begin 195 | cmd_counter <= next_cmd; 196 | subcmd_counter <= scs_start; 197 | end 198 | endcase 199 | end 200 | endtask 201 | 202 | task powerdown; 203 | input [2:0] next_cmd; 204 | 205 | begin 206 | case (subcmd_counter) 207 | 0: write_i2c(CHIP_ADDR, 16'h_08_FE); // CTL_1_MODE 208 | default: begin 209 | cmd_counter <= next_cmd; 210 | subcmd_counter <= scs_start; 211 | end 212 | endcase 213 | end 214 | endtask 215 | 216 | task pllcheck; 217 | input [2:0] success_cmd; 218 | input [2:0] failure_cmd; 219 | 220 | begin 221 | case (subcmd_counter) 222 | 0: begin 223 | if (output_ready) begin 224 | // proceed to next command 225 | subcmd_counter <= subcmd_counter + 1'b1; 226 | end else begin 227 | cmd_counter <= failure_cmd; 228 | subcmd_counter <= scs_start; 229 | end 230 | end 231 | default: begin 232 | cmd_counter <= success_cmd; 233 | subcmd_counter <= scs_start; 234 | end 235 | endcase 236 | end 237 | endtask 238 | 239 | endmodule 240 | -------------------------------------------------------------------------------- /source/typedef.v: -------------------------------------------------------------------------------- 1 | typedef struct packed { 2 | reg [7:0] id; 3 | 4 | reg [11:0] h_total; 5 | reg [11:0] h_active; 6 | reg [11:0] h_front_porch; 7 | reg [11:0] h_sync; 8 | reg [11:0] h_back_porch; 9 | reg h_sync_pol; 10 | 11 | reg [11:0] v_active; 12 | reg [11:0] v_front_porch; 13 | reg [11:0] v_sync; 14 | 15 | reg [11:0] v_total_1; 16 | reg [11:0] v_back_porch_1; 17 | reg [11:0] v_pxl_offset_1; 18 | 19 | reg [11:0] v_total_2; 20 | reg [11:0] v_back_porch_2; 21 | reg [11:0] v_pxl_offset_2; 22 | 23 | reg v_sync_pol; 24 | 25 | reg [11:0] h_field_start; 26 | reg [11:0] h_field_end; 27 | 28 | reg [11:0] v_field1_start; 29 | reg [11:0] v_field1_end; 30 | 31 | reg [11:0] v_field2_start; 32 | reg [11:0] v_field2_end; 33 | 34 | reg [11:0] v_field3_start; 35 | reg [11:0] v_field3_end; 36 | 37 | reg [3:0] h_res_divider; 38 | reg [3:0] v_res_divider; 39 | reg [11:0] h_res_start; 40 | 41 | reg [3:0] h_lag_divider; 42 | reg [3:0] v_lag_divider; 43 | reg [11:0] h_lag_start; 44 | reg [11:0] v_lag_start; 45 | } VideoMode; 46 | 47 | -------------------------------------------------------------------------------- /source/video.v: -------------------------------------------------------------------------------- 1 | `include "defines.v" 2 | 3 | module video( 4 | input clock, 5 | input [7:0] config_data, 6 | input [79:0] bcdcount, 7 | output [7:0] red, 8 | output [7:0] green, 9 | output [7:0] blue, 10 | output de, 11 | output hsync, 12 | output vsync, 13 | output starttrigger 14 | ); 15 | wire [11:0] counterX; 16 | wire [11:0] counterY; 17 | wire [11:0] visible_counterX; 18 | wire [11:0] visible_counterY; 19 | wire [`RESLINE_SIZE-1:0] resolution_line; 20 | wire [`LAGLINE_SIZE-1:0] lagdisplay_line; 21 | wire state; 22 | 23 | VideoMode videoMode; 24 | 25 | video_config video_config( 26 | .clock(clock), 27 | .data_in(config_data), 28 | .videoMode(videoMode) 29 | ); 30 | 31 | timingsgen timingsgen( 32 | .clock(clock), 33 | .videoMode(videoMode), 34 | .counterX(counterX), 35 | .counterY(counterY), 36 | .visible_counterX(visible_counterX), 37 | .visible_counterY(visible_counterY), 38 | .hsync(hsync), 39 | .vsync(vsync), 40 | .de(de), 41 | .state(state) 42 | ); 43 | 44 | textgen textgen( 45 | .clock(clock), 46 | .videoMode(videoMode), 47 | .counterX(counterX), 48 | .visible_counterX(visible_counterX), 49 | .visible_counterY(visible_counterY), 50 | .bcdcount(bcdcount), 51 | .resolution_line(resolution_line), 52 | .lagdisplay_line_out(lagdisplay_line) 53 | ); 54 | 55 | videogen videogen( 56 | .clock(clock), 57 | .videoMode(videoMode), 58 | .counterX(counterX), 59 | .counterY(counterY), 60 | .visible_counterX(visible_counterX), 61 | .visible_counterY(visible_counterY), 62 | .resolution_line(resolution_line), 63 | .lagdisplay_line(lagdisplay_line), 64 | .state(state), 65 | .starttrigger(starttrigger), 66 | .data({ red, green, blue }) 67 | ); 68 | 69 | endmodule -------------------------------------------------------------------------------- /source/video/textgen.v: -------------------------------------------------------------------------------- 1 | `include "../defines.v" 2 | 3 | module textgen( 4 | input clock, 5 | input VideoMode videoMode, 6 | input [11:0] counterX, 7 | input [11:0] visible_counterX, 8 | input [11:0] visible_counterY, 9 | input [79:0] bcdcount, 10 | output [`RESLINE_SIZE-1:0] resolution_line, 11 | output reg [`LAGLINE_SIZE-1:0] lagdisplay_line_out 12 | ); 13 | wire [`LAGLINE_SIZE-1:0] lagdisplay_line; 14 | 15 | reg trigger_write_lag; 16 | reg [5:0] write_lag_counter; 17 | 18 | reg [3:0] resolution_addr; 19 | reg [3:0] lagdisplay_addr; 20 | 21 | reg [7:0] char_addr; 22 | reg [7:0] char_data; 23 | 24 | char_rom char_rom_inst( 25 | .clock(clock), 26 | .address(char_addr), 27 | .q(char_data) 28 | ); 29 | 30 | resolution resolution( 31 | .clock(clock), 32 | .videoMode(videoMode), 33 | .addr(resolution_addr), 34 | .q(resolution_line) 35 | ); 36 | 37 | lagdisplay lagdisplay( 38 | .clock(clock), 39 | .addr(lagdisplay_addr), 40 | .q(lagdisplay_line) 41 | ); 42 | 43 | /* bcdcount */ 44 | always @(posedge clock) begin 45 | case (counterX) 46 | 0: begin 47 | // addr for resolution_line 48 | resolution_addr <= (visible_counterY + 1'b1) >> videoMode.v_res_divider; 49 | lagdisplay_addr <= (visible_counterY + 1'b1 - videoMode.v_lag_start) >> videoMode.v_lag_divider; 50 | end 51 | 2: begin 52 | trigger_write_lag <= 1; 53 | end 54 | 3: begin 55 | trigger_write_lag <= 0; 56 | end 57 | endcase 58 | end 59 | 60 | task idwc; 61 | begin 62 | write_lag_counter <= write_lag_counter + 1'b1; 63 | end 64 | endtask 65 | 66 | always @(posedge clock) begin 67 | if (trigger_write_lag) begin 68 | write_lag_counter <= 0; 69 | end else begin 70 | case (write_lag_counter) 71 | 0: begin 72 | lagdisplay_line_out <= lagdisplay_line; 73 | idwc(); 74 | end 75 | // bcdcount 76 | 1: begin 77 | if (bcdcount[19:0] == `MAX_BCDCOUNT) begin 78 | write_lag_counter <= write_lag_counter + 6'd9; 79 | end else begin 80 | idwc(); 81 | end 82 | end 83 | 2: begin 84 | char_addr <= lagdisplay_addr + (bcdcount[3:0] << 4); 85 | idwc(); 86 | end 87 | 3: begin 88 | char_addr <= lagdisplay_addr + (bcdcount[7:4] << 4); 89 | idwc(); 90 | end 91 | 4: begin 92 | char_addr <= lagdisplay_addr + (bcdcount[11:8] << 4); 93 | idwc(); 94 | end 95 | 5: begin 96 | lagdisplay_line_out[319:312] <= char_data; 97 | char_addr <= lagdisplay_addr + (bcdcount[15:12] << 4); 98 | idwc(); 99 | end 100 | 6: begin 101 | lagdisplay_line_out[327:320] <= char_data; 102 | char_addr <= lagdisplay_addr + (bcdcount[19:16] << 4); 103 | idwc(); 104 | end 105 | 7: begin 106 | lagdisplay_line_out[343:336] <= char_data; 107 | idwc(); 108 | end 109 | 8: begin 110 | lagdisplay_line_out[351:344] <= char_data; 111 | idwc(); 112 | end 113 | 9: begin 114 | lagdisplay_line_out[360:352] <= char_data; 115 | idwc(); 116 | end 117 | // bcdcount_min 118 | 10: begin 119 | if (bcdcount[39:20] == `MAX_BCDCOUNT) begin 120 | write_lag_counter <= write_lag_counter + 6'd9; 121 | end else begin 122 | idwc(); 123 | end 124 | end 125 | 11: begin 126 | char_addr <= lagdisplay_addr + (bcdcount[23:20] << 4); 127 | idwc(); 128 | end 129 | 12: begin 130 | char_addr <= lagdisplay_addr + (bcdcount[27:24] << 4); 131 | idwc(); 132 | end 133 | 13: begin 134 | char_addr <= lagdisplay_addr + (bcdcount[31:28] << 4); 135 | idwc(); 136 | end 137 | 14: begin 138 | lagdisplay_line_out[199:192] <= char_data; 139 | char_addr <= lagdisplay_addr + (bcdcount[35:32] << 4); 140 | idwc(); 141 | end 142 | 15: begin 143 | lagdisplay_line_out[207:200] <= char_data; 144 | char_addr <= lagdisplay_addr + (bcdcount[39:36] << 4); 145 | idwc(); 146 | end 147 | 16: begin 148 | lagdisplay_line_out[223:216] <= char_data; 149 | idwc(); 150 | end 151 | 17: begin 152 | lagdisplay_line_out[231:224] <= char_data; 153 | idwc(); 154 | end 155 | 18: begin 156 | lagdisplay_line_out[239:232] <= char_data; 157 | idwc(); 158 | end 159 | 160 | // bcdcount_max 161 | 19: begin 162 | if (bcdcount[59:40] == 0) begin 163 | write_lag_counter <= write_lag_counter + 6'd9; 164 | end else begin 165 | idwc(); 166 | end 167 | end 168 | 20: begin 169 | char_addr <= lagdisplay_addr + (bcdcount[43:40] << 4); 170 | idwc(); 171 | end 172 | 21: begin 173 | char_addr <= lagdisplay_addr + (bcdcount[47:44] << 4); 174 | idwc(); 175 | end 176 | 22: begin 177 | char_addr <= lagdisplay_addr + (bcdcount[51:48] << 4); 178 | idwc(); 179 | end 180 | 23: begin 181 | lagdisplay_line_out[127:120] <= char_data; 182 | char_addr <= lagdisplay_addr + (bcdcount[55:52] << 4); 183 | idwc(); 184 | end 185 | 24: begin 186 | lagdisplay_line_out[136:128] <= char_data; 187 | char_addr <= lagdisplay_addr + (bcdcount[59:56] << 4); 188 | idwc(); 189 | end 190 | 25: begin 191 | lagdisplay_line_out[151:144] <= char_data; 192 | idwc(); 193 | end 194 | 26: begin 195 | lagdisplay_line_out[159:152] <= char_data; 196 | idwc(); 197 | end 198 | 27: begin 199 | lagdisplay_line_out[167:160] <= char_data; 200 | idwc(); 201 | end 202 | 203 | // avg_counter 204 | 28: begin 205 | if (bcdcount[79:60] == `MAX_BCDCOUNT) begin 206 | write_lag_counter <= write_lag_counter + 6'd9; 207 | end else begin 208 | idwc(); 209 | end 210 | end 211 | 29: begin 212 | char_addr <= lagdisplay_addr + (bcdcount[63:60] << 4); 213 | idwc(); 214 | end 215 | 30: begin 216 | char_addr <= lagdisplay_addr + (bcdcount[67:64] << 4); 217 | idwc(); 218 | end 219 | 31: begin 220 | char_addr <= lagdisplay_addr + (bcdcount[71:68] << 4); 221 | idwc(); 222 | end 223 | 32: begin 224 | lagdisplay_line_out[7:0] <= char_data; 225 | char_addr <= lagdisplay_addr + (bcdcount[75:72] << 4); 226 | idwc(); 227 | end 228 | 33: begin 229 | lagdisplay_line_out[15:8] <= char_data; 230 | char_addr <= lagdisplay_addr + (bcdcount[79:76] << 4); 231 | idwc(); 232 | end 233 | 34: begin 234 | lagdisplay_line_out[31:24] <= char_data; 235 | idwc(); 236 | end 237 | 35: begin 238 | lagdisplay_line_out[39:32] <= char_data; 239 | idwc(); 240 | end 241 | 36: begin 242 | lagdisplay_line_out[47:40] <= char_data; 243 | idwc(); 244 | end 245 | endcase 246 | end 247 | end 248 | endmodule -------------------------------------------------------------------------------- /source/video/timingsgen.v: -------------------------------------------------------------------------------- 1 | module timingsgen( 2 | input clock, 3 | input VideoMode videoMode, 4 | output reg [11:0] counterX, 5 | output reg [11:0] counterY, 6 | output reg [11:0] visible_counterX, 7 | output reg [11:0] visible_counterY, 8 | output reg hsync, 9 | output reg vsync, 10 | output reg de, 11 | output reg state 12 | ); 13 | /* 14 | H_SYNC H_BACK_PORCH H_ACTIVE H_FRONT_PORCH 15 | V_SYNC V_BACK_PORCH V_ACTIVE V_FRONT_PORCH 16 | */ 17 | 18 | /* generate counter */ 19 | always @(posedge clock) begin 20 | if (counterX < videoMode.h_total - 1) begin 21 | counterX <= counterX + 1'b1; 22 | end else begin 23 | counterX <= 0; 24 | if (counterY < (state ? videoMode.v_total_2 : videoMode.v_total_1) - 1) begin 25 | counterY <= counterY + 1'b1; 26 | end else begin 27 | counterY <= 0; 28 | state <= ~state; 29 | end 30 | end 31 | end 32 | 33 | /* generate visible area timings */ 34 | always @(posedge clock) begin 35 | visible_counterX <= counterX + 1'b1 /* add one */ - (videoMode.h_sync + videoMode.h_back_porch); 36 | visible_counterY <= counterY - (videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1)); 37 | end 38 | 39 | /* generate hsync */ 40 | always @(posedge clock) begin 41 | if (counterX < videoMode.h_sync) begin 42 | hsync <= videoMode.h_sync_pol; 43 | end else begin 44 | hsync <= ~videoMode.h_sync_pol; 45 | end 46 | end 47 | 48 | `define VerticalSyncPixelOffset (state ? videoMode.v_pxl_offset_2 : videoMode.v_pxl_offset_1) 49 | 50 | /* generate vsync */ 51 | always @(posedge clock) begin 52 | if (counterY <= videoMode.v_sync) begin 53 | if (counterY == 0 && counterX < `VerticalSyncPixelOffset 54 | || counterY == videoMode.v_sync && counterX >= `VerticalSyncPixelOffset) begin 55 | vsync <= ~videoMode.v_sync_pol; 56 | end else begin 57 | vsync <= videoMode.v_sync_pol; 58 | end 59 | end else begin 60 | vsync <= ~videoMode.v_sync_pol; 61 | end 62 | end 63 | 64 | /* generate DE */ 65 | always @(posedge clock) begin 66 | if (counterX >= videoMode.h_sync + videoMode.h_back_porch 67 | && counterY >= videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1) 68 | && counterX < videoMode.h_sync + videoMode.h_back_porch + videoMode.h_active 69 | && counterY < videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1) + videoMode.v_active) 70 | begin 71 | de <= 1'b1; 72 | end else begin 73 | de <= 0; 74 | end 75 | end 76 | endmodule -------------------------------------------------------------------------------- /source/video/video_config.v: -------------------------------------------------------------------------------- 1 | `include "../defines.v" 2 | 3 | module video_config( 4 | input clock, 5 | input [7:0] data_in, 6 | output VideoMode videoMode 7 | ); 8 | `include "../config/video_modes.v" 9 | 10 | reg [7:0] data_in_reg; 11 | 12 | VideoMode videoMode_reg; 13 | assign videoMode = videoMode_reg; 14 | 15 | always @(posedge clock) begin 16 | data_in_reg <= data_in; 17 | 18 | if (data_in_reg != data_in) begin 19 | case (data_in) 20 | `MODE_1080p: videoMode_reg <= VIDEO_MODE_1080P; 21 | `MODE_1080i: videoMode_reg <= VIDEO_MODE_1080I; 22 | `MODE_720p: videoMode_reg <= VIDEO_MODE_720P; 23 | `MODE_480p: videoMode_reg <= VIDEO_MODE_480P; 24 | `MODE_480i: videoMode_reg <= VIDEO_MODE_480I; 25 | endcase 26 | end 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /source/video/videogen.v: -------------------------------------------------------------------------------- 1 | `include "../defines.v" 2 | 3 | module videogen( 4 | input clock, 5 | input VideoMode videoMode, 6 | input [11:0] counterX, 7 | input [11:0] counterY, 8 | input [11:0] visible_counterX, 9 | input [11:0] visible_counterY, 10 | input [`RESLINE_SIZE-1:0] resolution_line, 11 | input [`LAGLINE_SIZE-1:0] lagdisplay_line, 12 | input state, 13 | output reg starttrigger, 14 | output reg [23:0] data 15 | ); 16 | reg [5:0] frameCounter = 0; 17 | reg displayFields = 0; 18 | reg [2:0] metaCounter = 0; 19 | 20 | /* frame counter */ 21 | always @(posedge clock) begin 22 | if (counterX == videoMode.h_sync + videoMode.h_back_porch 23 | && counterY == videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1)) begin 24 | if (frameCounter < `FRAME_COUNTER - 1 + metaCounter) begin 25 | frameCounter <= frameCounter + 1'b1; 26 | end else begin 27 | frameCounter <= 0; 28 | end 29 | 30 | if (frameCounter == 0) begin 31 | starttrigger <= 1; 32 | displayFields <= 1; 33 | end else if (frameCounter > `FRAME_ON_COUNT - 1) begin 34 | displayFields <= 0; 35 | end 36 | 37 | metaCounter <= metaCounter + 1'b1; 38 | end else begin 39 | starttrigger <= 0; 40 | end 41 | end 42 | 43 | always @(posedge clock) begin 44 | doOutputValue( 45 | .xpos(visible_counterX), 46 | .ypos(visible_counterY), 47 | .resolution_hpos((`RESLINE_SIZE - 1) - ((visible_counterX >> videoMode.h_res_divider) - videoMode.h_res_start)), 48 | .lagdisplay_hpos((`LAGLINE_SIZE - 1) - ((visible_counterX >> videoMode.h_lag_divider) - videoMode.h_lag_start)) 49 | ); 50 | end 51 | 52 | task doOutputValue; 53 | input [11:0] xpos; 54 | input [11:0] ypos; 55 | input [11:0] resolution_hpos; 56 | input [11:0] lagdisplay_hpos; 57 | begin 58 | if (displayFields && 59 | (xpos >= videoMode.h_field_start && xpos < videoMode.h_field_end && 60 | ((ypos >= videoMode.v_field1_start && ypos < videoMode.v_field1_end) 61 | || (ypos >= videoMode.v_field2_start && ypos < videoMode.v_field2_end) 62 | || (ypos >= videoMode.v_field3_start && ypos < videoMode.v_field3_end)))) 63 | begin 64 | data <= 24'h_FF_FF_FF; 65 | end else if ( 66 | ypos < (12'd16 << videoMode.v_res_divider) 67 | && (xpos >> videoMode.h_res_divider) >= videoMode.h_res_start 68 | ) begin // resolution info 69 | if (resolution_line[resolution_hpos]) begin 70 | data <= 24'h_FF_FF_FF; 71 | end else begin 72 | data <= 0; 73 | end 74 | end else if ( 75 | ypos >= videoMode.v_lag_start 76 | && ypos < videoMode.v_lag_start + (12'd16 << videoMode.v_lag_divider) 77 | && (xpos >> videoMode.h_lag_divider) >= videoMode.h_lag_start 78 | && (xpos >> videoMode.h_lag_divider) < videoMode.h_lag_start + 80 79 | ) begin 80 | if (lagdisplay_line[lagdisplay_hpos]) begin 81 | data <= 24'h_FF_FF_FF; 82 | end else begin 83 | data <= 0; 84 | end 85 | end else if ( 86 | ypos >= videoMode.v_lag_start + (12'd16 << videoMode.v_lag_divider) 87 | && ypos < videoMode.v_lag_start + (12'd32 << videoMode.v_lag_divider) 88 | && (xpos >> videoMode.h_lag_divider) >= videoMode.h_lag_start 89 | && (xpos >> videoMode.h_lag_divider) < videoMode.h_lag_start + 120 90 | ) begin 91 | if (lagdisplay_line[lagdisplay_hpos - 80]) begin 92 | data <= 24'h_FF_FF_FF; 93 | end else begin 94 | data <= 0; 95 | end 96 | end else if ( 97 | ypos >= videoMode.v_lag_start + (12'd32 << videoMode.v_lag_divider) 98 | && ypos < videoMode.v_lag_start + (12'd48 << videoMode.v_lag_divider) 99 | && (xpos >> videoMode.h_lag_divider) >= videoMode.h_lag_start 100 | && (xpos >> videoMode.h_lag_divider) < videoMode.h_lag_start + 192 101 | ) begin 102 | if (lagdisplay_line[lagdisplay_hpos - 200]) begin 103 | data <= 24'h_FF_FF_FF; 104 | end else begin 105 | data <= 0; 106 | end 107 | end else if ( 108 | ypos >= videoMode.v_lag_start + (12'd48 << videoMode.v_lag_divider) 109 | && ypos < videoMode.v_lag_start + (12'd64 << videoMode.v_lag_divider) 110 | && (xpos >> videoMode.h_lag_divider) >= videoMode.h_lag_start 111 | && (xpos >> videoMode.h_lag_divider) < videoMode.h_lag_start + 120 112 | ) begin 113 | if (lagdisplay_line[lagdisplay_hpos - 392]) begin 114 | data <= 24'h_FF_FF_FF; 115 | end else begin 116 | data <= 0; 117 | end 118 | end else begin 119 | data <= 0; 120 | end 121 | end 122 | endtask 123 | endmodule --------------------------------------------------------------------------------