├── README.md ├── cs42l42 ├── cs42l42.c ├── stdint.h ├── resource.h ├── hidcommon.h ├── cs42l42.rc ├── spb.h ├── trace.h ├── cs42l42.inf ├── cs42l42.vcxproj ├── cs42l42.h ├── spb.c └── registers.h ├── cs42l42.sln ├── LICENSE.txt ├── .gitignore └── cs42l42 Package └── cs42l42 Package.vcxproj /README.md: -------------------------------------------------------------------------------- 1 | # cs42l42 2 | CS42L42 Headphone Codec Driver 3 | 4 | Tested on Dell Chromebook 3100 -------------------------------------------------------------------------------- /cs42l42/cs42l42.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/chrultrabook/cs42l42/master/cs42l42/cs42l42.c -------------------------------------------------------------------------------- /cs42l42/stdint.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define BIT(nr) (1UL << (nr)) -------------------------------------------------------------------------------- /cs42l42/resource.h: -------------------------------------------------------------------------------- 1 | //{{NO_DEPENDENCIES}} 2 | // Microsoft Visual C++ generated include file. 3 | // Used by cs42l42.rc 4 | 5 | // Next default values for new objects 6 | // 7 | #ifdef APSTUDIO_INVOKED 8 | #ifndef APSTUDIO_READONLY_SYMBOLS 9 | #define _APS_NEXT_RESOURCE_VALUE 101 10 | #define _APS_NEXT_COMMAND_VALUE 40001 11 | #define _APS_NEXT_CONTROL_VALUE 1001 12 | #define _APS_NEXT_SYMED_VALUE 101 13 | #endif 14 | #endif 15 | -------------------------------------------------------------------------------- /cs42l42/hidcommon.h: -------------------------------------------------------------------------------- 1 | #if !defined(_CS42L42_COMMON_H_) 2 | #define _CS42L42_COMMON_H_ 3 | 4 | // 5 | //These are the device attributes returned by vmulti in response 6 | // to IOCTL_HID_GET_DEVICE_ATTRIBUTES. 7 | // 8 | 9 | #define CS42L42_PID 0x4242 10 | #define CS42L42_VID 0x1013 11 | #define CS42L42_VERSION 0x0001 12 | 13 | // 14 | // These are the report ids 15 | // 16 | 17 | #define REPORTID_MEDIA 0x01 18 | #define REPORTID_SPECKEYS 0x02 19 | 20 | #pragma pack(1) 21 | typedef struct _CS42L42_MEDIA_REPORT 22 | { 23 | 24 | BYTE ReportID; 25 | 26 | BYTE ControlCode; 27 | 28 | } Cs42l42MediaReport; 29 | #pragma pack() 30 | 31 | #define CONTROL_CODE_JACK_TYPE 0x1 32 | 33 | #pragma pack(1) 34 | typedef struct _CSAUDIO_SPECKEY_REPORT 35 | { 36 | 37 | BYTE ReportID; 38 | 39 | BYTE ControlCode; 40 | 41 | BYTE ControlValue; 42 | 43 | } CsAudioSpecialKeyReport; 44 | 45 | #pragma pack() 46 | 47 | #pragma pack(1) 48 | typedef struct _CSAUDIO_SPECKEYREQ_REPORT 49 | { 50 | 51 | BYTE ReportID; 52 | 53 | BYTE AnyCode; 54 | 55 | } CsAudioSpecialKeyRequestReport; 56 | #pragma pack() 57 | 58 | #endif 59 | -------------------------------------------------------------------------------- /cs42l42/cs42l42.rc: -------------------------------------------------------------------------------- 1 | /*++ 2 | 3 | Copyright (c) Microsoft Corporation All Rights Reserved 4 | 5 | Module Name: 6 | 7 | cs42l42.rc 8 | 9 | Abstract: 10 | 11 | --*/ 12 | 13 | #include 14 | 15 | #define VER_FILETYPE VFT_DRV 16 | #define VER_FILESUBTYPE VFT2_DRV_SOUND 17 | #define VER_FILEDESCRIPTION_STR "Cirrus Logic CS42L42 Codec" 18 | #define VER_INTERNALNAME_STR "cs42l42.sys" 19 | #define VER_ORIGINALFILENAME_STR "cs42l42.sys" 20 | 21 | #define VER_LEGALCOPYRIGHT_YEARS "2023" 22 | #define VER_LEGALCOPYRIGHT_STR "Copyright (C) " VER_LEGALCOPYRIGHT_YEARS " CoolStar." 23 | 24 | #define VER_FILEVERSION 1,0,0,0 25 | #define VER_PRODUCTVERSION_STR "1.0.0.0" 26 | #define VER_PRODUCTVERSION 1,0,0,0 27 | #define LVER_PRODUCTVERSION_STR L"1.0.0.0" 28 | 29 | #define VER_FILEFLAGSMASK (VS_FF_DEBUG | VS_FF_PRERELEASE) 30 | #ifdef DEBUG 31 | #define VER_FILEFLAGS (VS_FF_DEBUG) 32 | #else 33 | #define VER_FILEFLAGS (0) 34 | #endif 35 | 36 | #define VER_FILEOS VOS_NT_WINDOWS32 37 | 38 | #define VER_COMPANYNAME_STR "CoolStar" 39 | #define VER_PRODUCTNAME_STR "Cirrus Logic CS42L42 Codec" 40 | 41 | #include "common.ver" -------------------------------------------------------------------------------- /cs42l42/spb.h: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.h 8 | 9 | Abstract: 10 | 11 | This module contains the touch driver I2C helper definitions. 12 | 13 | Environment: 14 | 15 | Kernel Mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #pragma once 22 | 23 | #include 24 | #include 25 | 26 | #define DEFAULT_SPB_BUFFER_SIZE 64 27 | #define RESHUB_USE_HELPER_ROUTINES 28 | 29 | // 30 | // SPB (I2C) context 31 | // 32 | 33 | typedef struct _SPB_CONTEXT 34 | { 35 | WDFIOTARGET SpbIoTarget; 36 | LARGE_INTEGER I2cResHubId; 37 | WDFMEMORY WriteMemory; 38 | WDFMEMORY ReadMemory; 39 | WDFWAITLOCK SpbLock; 40 | } SPB_CONTEXT; 41 | 42 | NTSTATUS 43 | SpbXferDataSynchronously( 44 | _In_ SPB_CONTEXT* SpbContext, 45 | _In_ PVOID SendData, 46 | _In_ ULONG SendLength, 47 | _In_reads_bytes_(Length) PVOID Data, 48 | _In_ ULONG Length 49 | ); 50 | 51 | VOID 52 | SpbTargetDeinitialize( 53 | IN WDFDEVICE FxDevice, 54 | IN SPB_CONTEXT* SpbContext 55 | ); 56 | 57 | NTSTATUS 58 | SpbTargetInitialize( 59 | IN WDFDEVICE FxDevice, 60 | IN SPB_CONTEXT* SpbContext 61 | ); 62 | 63 | NTSTATUS 64 | SpbWriteDataSynchronously( 65 | IN SPB_CONTEXT* SpbContext, 66 | IN PVOID Data, 67 | IN ULONG Length 68 | ); -------------------------------------------------------------------------------- /cs42l42/trace.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #ifndef _TRACE_H_ 4 | #define _TRACE_H_ 5 | 6 | extern "C" 7 | { 8 | // 9 | // Tracing Definitions: 10 | // 11 | // Control GUID: 12 | // {73e3b785-f5fb-423e-94a9-56627fea9053} 13 | // 14 | 15 | #define WPP_CONTROL_GUIDS \ 16 | WPP_DEFINE_CONTROL_GUID( \ 17 | SpbTestToolTraceGuid, \ 18 | (73e3b785,f5fb,423e,94a9,56627fea9053), \ 19 | WPP_DEFINE_BIT(TRACE_FLAG_WDFLOADING) \ 20 | WPP_DEFINE_BIT(TRACE_FLAG_SPBAPI) \ 21 | WPP_DEFINE_BIT(TRACE_FLAG_OTHER) \ 22 | ) 23 | } 24 | 25 | #define WPP_LEVEL_FLAGS_LOGGER(level,flags) WPP_LEVEL_LOGGER(flags) 26 | #define WPP_LEVEL_FLAGS_ENABLED(level, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= level) 27 | 28 | #define Trace CyapaPrint 29 | #define FuncEntry 30 | #define FuncExit 31 | #define WPP_INIT_TRACING 32 | #define WPP_CLEANUP 33 | #define TRACE_FLAG_SPBAPI 0 34 | #define TRACE_FLAG_WDFLOADING 0 35 | 36 | // begin_wpp config 37 | // FUNC FuncEntry{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 38 | // FUNC FuncExit{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 39 | // USEPREFIX(FuncEntry, "%!STDPREFIX! [%!FUNC!] --> entry"); 40 | // USEPREFIX(FuncExit, "%!STDPREFIX! [%!FUNC!] <--"); 41 | // end_wpp 42 | 43 | #endif _TRACE_H_ 44 | -------------------------------------------------------------------------------- /cs42l42/cs42l42.inf: -------------------------------------------------------------------------------- 1 | ;/*++ 2 | ; 3 | ;Copyright (c) CoolStar. All rights reserved. 4 | ; 5 | ;Module Name: 6 | ; coolstar.inf 7 | ; 8 | ;Abstract: 9 | ; INF file for installing the Cirrus Logic CS42L42 Driver 10 | ; 11 | ; 12 | ;--*/ 13 | 14 | [Version] 15 | Signature = "$WINDOWS NT$" 16 | Class = Media 17 | ClassGuid = {4d36e96c-e325-11ce-bfc1-08002be10318} 18 | Provider = CoolStar 19 | DriverVer = 2/25/2022,1.0.0 20 | CatalogFile = cs42l42.cat 21 | PnpLockdown=1 22 | 23 | [DestinationDirs] 24 | DefaultDestDir = 12 25 | 26 | ; ================= Class section ===================== 27 | 28 | [SourceDisksNames] 29 | 1 = %DiskId1%,,,"" 30 | 31 | [SourceDisksFiles] 32 | cs42l42.sys = 1,, 33 | 34 | ;***************************************** 35 | ; cs42l42 Install Section 36 | ;***************************************** 37 | 38 | [Manufacturer] 39 | %StdMfg%=Standard,NTAMD64 40 | 41 | ; Decorated model section take precedence over undecorated 42 | ; ones on XP and later. 43 | [Standard.NTAMD64] 44 | %cs42l42.DeviceDesc%=Cs42l42_Device, ACPI\10134242 45 | 46 | [Cs42l42_Device.NT] 47 | CopyFiles=Drivers_Dir 48 | 49 | [Cs42l42_Device.NT.HW] 50 | AddReg=Cs42l42_AddReg 51 | 52 | [Drivers_Dir] 53 | cs42l42.sys 54 | 55 | [Cs42l42_AddReg] 56 | ; Set to 1 to connect the first interrupt resource found, 0 to leave disconnected 57 | HKR,Settings,"ConnectInterrupt",0x00010001,0 58 | HKR,,"UpperFilters",0x00010000,"mshidkmdf" 59 | 60 | ;-------------- Service installation 61 | [Cs42l42_Device.NT.Services] 62 | AddService = cs42l42,%SPSVCINST_ASSOCSERVICE%, Cs42l42_Service_Inst 63 | 64 | ; -------------- cs42l42 driver install sections 65 | [Cs42l42_Service_Inst] 66 | DisplayName = %cs42l42.SVCDESC% 67 | ServiceType = 1 ; SERVICE_KERNEL_DRIVER 68 | StartType = 3 ; SERVICE_DEMAND_START 69 | ErrorControl = 1 ; SERVICE_ERROR_NORMAL 70 | ServiceBinary = %12%\cs42l42.sys 71 | LoadOrderGroup = Base 72 | 73 | [Strings] 74 | SPSVCINST_ASSOCSERVICE= 0x00000002 75 | StdMfg = "CoolStar" 76 | DiskId1 = "CS42L42 Installation Disk #1" 77 | cs42l42.DeviceDesc = "Cirrus Logic CS42L42 Codec" 78 | cs42l42.SVCDESC = "CS42L42 Service" 79 | -------------------------------------------------------------------------------- /cs42l42.sln: -------------------------------------------------------------------------------- 1 | 2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.31829.152 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "cs42l42", "cs42l42\cs42l42.vcxproj", "{36580C07-EDC3-4C2B-B45F-6AB017E01A5D}" 7 | EndProject 8 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "cs42l42 Package", "cs42l42 Package\cs42l42 Package.vcxproj", "{3DAE7ED3-003A-4495-8352-3D7B5B5D846F}" 9 | ProjectSection(ProjectDependencies) = postProject 10 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} = {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} 11 | EndProjectSection 12 | EndProject 13 | Global 14 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 15 | Debug|Win32 = Debug|Win32 16 | Debug|x64 = Debug|x64 17 | Release|Win32 = Release|Win32 18 | Release|x64 = Release|x64 19 | EndGlobalSection 20 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 21 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.ActiveCfg = Debug|Win32 22 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.Build.0 = Debug|Win32 23 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.Deploy.0 = Debug|Win32 24 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.ActiveCfg = Release|x64 25 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.Build.0 = Release|x64 26 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.Deploy.0 = Release|x64 27 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.ActiveCfg = Release|Win32 28 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.Build.0 = Release|Win32 29 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.Deploy.0 = Release|Win32 30 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.ActiveCfg = Release|x64 31 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.Build.0 = Release|x64 32 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.Deploy.0 = Release|x64 33 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.ActiveCfg = Debug|Win32 34 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.Build.0 = Debug|Win32 35 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.Deploy.0 = Debug|Win32 36 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.ActiveCfg = Release|x64 37 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.Build.0 = Release|x64 38 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.Deploy.0 = Release|x64 39 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.ActiveCfg = Release|Win32 40 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.Build.0 = Release|Win32 41 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.Deploy.0 = Release|Win32 42 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.ActiveCfg = Release|x64 43 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.Build.0 = Release|x64 44 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.Deploy.0 = Release|x64 45 | EndGlobalSection 46 | GlobalSection(SolutionProperties) = preSolution 47 | HideSolutionNode = FALSE 48 | EndGlobalSection 49 | GlobalSection(ExtensibilityGlobals) = postSolution 50 | SolutionGuid = {9976A14A-3F14-4DE9-A9B7-4F14DEDB8D18} 51 | EndGlobalSection 52 | EndGlobal 53 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | Copyright 2022 CoolStar 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | 15 | 16 | ====================== Windows Driver Samples License ====================== 17 | 18 | The Microsoft Public License (MS-PL) 19 | Copyright (c) 2015 Microsoft 20 | 21 | This license governs use of the accompanying software. If you use the software, you 22 | accept this license. If you do not accept the license, do not use the software. 23 | 24 | 1. Definitions 25 | The terms "reproduce," "reproduction," "derivative works," and "distribution" have the 26 | same meaning here as under U.S. copyright law. 27 | A "contribution" is the original software, or any additions or changes to the software. 28 | A "contributor" is any person that distributes its contribution under this license. 29 | "Licensed patents" are a contributor's patent claims that read directly on its contribution. 30 | 31 | 2. Grant of Rights 32 | (A) Copyright Grant- Subject to the terms of this license, including the license conditions and limitations in section 3, each contributor grants you a non-exclusive, worldwide, royalty-free copyright license to reproduce its contribution, prepare derivative works of its contribution, and distribute its contribution or any derivative works that you create. 33 | (B) Patent Grant- Subject to the terms of this license, including the license conditions and limitations in section 3, each contributor grants you a non-exclusive, worldwide, royalty-free license under its licensed patents to make, have made, use, sell, offer for sale, import, and/or otherwise dispose of its contribution in the software or derivative works of the contribution in the software. 34 | 35 | 3. Conditions and Limitations 36 | (A) No Trademark License- This license does not grant you rights to use any contributors' name, logo, or trademarks. 37 | (B) If you bring a patent claim against any contributor over patents that you claim are infringed by the software, your patent license from such contributor to the software ends automatically. 38 | (C) If you distribute any portion of the software, you must retain all copyright, patent, trademark, and attribution notices that are present in the software. 39 | (D) If you distribute any portion of the software in source code form, you may do so only under this license by including a complete copy of this license with your distribution. If you distribute any portion of the software in compiled or object code form, you may only do so under a license that complies with this license. 40 | (E) The software is licensed "as-is." You bear the risk of using it. The contributors give no express warranties, guarantees or conditions. You may have additional consumer rights under your local laws which this license cannot change. To the extent permitted under your local laws, the contributors exclude the implied warranties of merchantability, fitness for a particular purpose and non-infringement. -------------------------------------------------------------------------------- /cs42l42/cs42l42.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} 23 | {1bc93793-694f-48fe-9372-81e2b05556fd} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | cs42l42 29 | $(LatestTargetPlatformVersion) 30 | 31 | 32 | 33 | 34 | 35 | true 36 | WindowsKernelModeDriver10.0 37 | Driver 38 | KMDF 39 | 40 | 41 | 42 | 43 | false 44 | WindowsKernelModeDriver10.0 45 | Driver 46 | KMDF 47 | 48 | 49 | 50 | 51 | true 52 | WindowsKernelModeDriver10.0 53 | Driver 54 | KMDF 55 | 56 | 57 | 58 | 59 | false 60 | WindowsKernelModeDriver10.0 61 | Driver 62 | KMDF 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | DbgengKernelDebugger 74 | 75 | 76 | DbgengKernelDebugger 77 | 78 | 79 | DbgengKernelDebugger 80 | 81 | 82 | DbgengKernelDebugger 83 | 84 | 85 | 86 | true 87 | trace.h 88 | true 89 | false 90 | 91 | 92 | 1.0.0 93 | 94 | 95 | 96 | 97 | true 98 | trace.h 99 | true 100 | false 101 | 102 | 103 | 1.0.0 104 | 105 | 106 | 107 | 108 | true 109 | trace.h 110 | true 111 | false 112 | 113 | 114 | 1.0.0 115 | 116 | 117 | 118 | 119 | true 120 | trace.h 121 | true 122 | false 123 | 124 | 125 | 1.0.0 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ## 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Backup files are not needed, 238 | # because we have git ;-) 239 | _UpgradeReport_Files/ 240 | Backup*/ 241 | UpgradeLog*.XML 242 | UpgradeLog*.htm 243 | ServiceFabricBackup/ 244 | *.rptproj.bak 245 | 246 | # SQL Server files 247 | *.mdf 248 | *.ldf 249 | *.ndf 250 | 251 | # Business Intelligence projects 252 | *.rdl.data 253 | *.bim.layout 254 | *.bim_*.settings 255 | *.rptproj.rsuser 256 | 257 | # Microsoft Fakes 258 | FakesAssemblies/ 259 | 260 | # GhostDoc plugin setting file 261 | *.GhostDoc.xml 262 | 263 | # Node.js Tools for Visual Studio 264 | .ntvs_analysis.dat 265 | node_modules/ 266 | 267 | # Visual Studio 6 build log 268 | *.plg 269 | 270 | # Visual Studio 6 workspace options file 271 | *.opt 272 | 273 | # Visual Studio 6 auto-generated workspace file (contains which files were open etc.) 274 | *.vbw 275 | 276 | # Visual Studio LightSwitch build output 277 | **/*.HTMLClient/GeneratedArtifacts 278 | **/*.DesktopClient/GeneratedArtifacts 279 | **/*.DesktopClient/ModelManifest.xml 280 | **/*.Server/GeneratedArtifacts 281 | **/*.Server/ModelManifest.xml 282 | _Pvt_Extensions 283 | 284 | # Paket dependency manager 285 | .paket/paket.exe 286 | paket-files/ 287 | 288 | # FAKE - F# Make 289 | .fake/ 290 | 291 | # JetBrains Rider 292 | .idea/ 293 | *.sln.iml 294 | 295 | # CodeRush personal settings 296 | .cr/personal 297 | 298 | # Python Tools for Visual Studio (PTVS) 299 | __pycache__/ 300 | *.pyc 301 | 302 | # Cake - Uncomment if you are using it 303 | # tools/** 304 | # !tools/packages.config 305 | 306 | # Tabs Studio 307 | *.tss 308 | 309 | # Telerik's JustMock configuration file 310 | *.jmconfig 311 | 312 | # BizTalk build output 313 | *.btp.cs 314 | *.btm.cs 315 | *.odx.cs 316 | *.xsd.cs 317 | 318 | # OpenCover UI analysis results 319 | OpenCover/ 320 | 321 | # Azure Stream Analytics local run output 322 | ASALocalRun/ 323 | 324 | # MSBuild Binary and Structured Log 325 | *.binlog 326 | 327 | # NVidia Nsight GPU debugger configuration file 328 | *.nvuser 329 | 330 | # MFractors (Xamarin productivity tool) working folder 331 | .mfractor/ 332 | 333 | # Local History for Visual Studio 334 | .localhistory/ 335 | -------------------------------------------------------------------------------- /cs42l42 Package/cs42l42 Package.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F} 23 | {4605da2c-74a5-4865-98e1-152ef136825f} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | cs42l42_Package 29 | $(LatestTargetPlatformVersion) 30 | 31 | 32 | 33 | 34 | 35 | true 36 | WindowsKernelModeDriver10.0 37 | Utility 38 | Package 39 | true 40 | 41 | 42 | 43 | 44 | false 45 | WindowsKernelModeDriver10.0 46 | Utility 47 | Package 48 | true 49 | 50 | 51 | 52 | 53 | true 54 | WindowsKernelModeDriver10.0 55 | Utility 56 | Package 57 | true 58 | 59 | 60 | 61 | 62 | false 63 | WindowsKernelModeDriver10.0 64 | Utility 65 | Package 66 | true 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | DbgengKernelDebugger 78 | False 79 | True 80 | 81 | 82 | 83 | False 84 | False 85 | True 86 | 87 | 133563 88 | 89 | 90 | DbgengKernelDebugger 91 | False 92 | True 93 | 94 | 95 | 96 | False 97 | False 98 | True 99 | 100 | 133563 101 | 102 | 103 | DbgengKernelDebugger 104 | False 105 | True 106 | 107 | 108 | 109 | False 110 | False 111 | True 112 | 113 | 133563 114 | 115 | 116 | DbgengKernelDebugger 117 | False 118 | True 119 | 120 | 121 | 122 | False 123 | False 124 | True 125 | 126 | 133563 127 | 128 | 129 | 130 | SHA256 131 | 132 | 133 | 134 | 135 | SHA256 136 | 137 | 138 | 139 | 140 | SHA256 141 | 142 | 143 | 144 | 145 | SHA256 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | {36580c07-edc3-4c2b-b45f-6ab017e01a5d} 154 | 155 | 156 | 157 | 158 | 159 | -------------------------------------------------------------------------------- /cs42l42/cs42l42.h: -------------------------------------------------------------------------------- 1 | #if !defined(_CS42L42_H_) 2 | #define _CS42L42_H_ 3 | 4 | #pragma warning(disable:4200) // suppress nameless struct/union warning 5 | #pragma warning(disable:4201) // suppress nameless struct/union warning 6 | #pragma warning(disable:4214) // suppress bit field types other than int warning 7 | #include 8 | #include 9 | 10 | #pragma warning(default:4200) 11 | #pragma warning(default:4201) 12 | #pragma warning(default:4214) 13 | #include 14 | 15 | #pragma warning(disable:4201) // suppress nameless struct/union warning 16 | #pragma warning(disable:4214) // suppress bit field types other than int warning 17 | #include 18 | 19 | #include "hidcommon.h" 20 | 21 | #include 22 | 23 | #include "spb.h" 24 | 25 | enum snd_jack_types { 26 | SND_JACK_HEADPHONE = 0x0001, 27 | SND_JACK_MICROPHONE = 0x0002, 28 | SND_JACK_HEADSET = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE, 29 | SND_JACK_LINEOUT = 0x0004, 30 | SND_JACK_MECHANICAL = 0x0008, /* If detected separately */ 31 | SND_JACK_VIDEOOUT = 0x0010, 32 | SND_JACK_AVOUT = SND_JACK_LINEOUT | SND_JACK_VIDEOOUT, 33 | SND_JACK_LINEIN = 0x0020, 34 | 35 | /* Kept separate from switches to facilitate implementation */ 36 | SND_JACK_BTN_0 = 0x4000, 37 | SND_JACK_BTN_1 = 0x2000, 38 | SND_JACK_BTN_2 = 0x1000, 39 | SND_JACK_BTN_3 = 0x0800, 40 | SND_JACK_BTN_4 = 0x0400, 41 | SND_JACK_BTN_5 = 0x0200, 42 | }; 43 | 44 | // 45 | // String definitions 46 | // 47 | 48 | #define DRIVERNAME "da7219.sys: " 49 | 50 | #define CS42L42_POOL_TAG (ULONG) '24SC' 51 | 52 | #define true 1 53 | #define false 0 54 | 55 | typedef UCHAR HID_REPORT_DESCRIPTOR, * PHID_REPORT_DESCRIPTOR; 56 | 57 | #ifdef DESCRIPTOR_DEF 58 | HID_REPORT_DESCRIPTOR DefaultReportDescriptor[] = { 59 | // 60 | // Consumer Control starts here 61 | // 62 | 0x05, 0x0C, /* Usage Page (Consumer Devices) */ 63 | 0x09, 0x01, /* Usage (Consumer Control) */ 64 | 0xA1, 0x01, /* Collection (Application) */ 65 | 0x85, REPORTID_MEDIA, /* Report ID=1 */ 66 | 0x05, 0x0C, /* Usage Page (Consumer Devices) */ 67 | 0x15, 0x00, /* Logical Minimum (0) */ 68 | 0x25, 0x01, /* Logical Maximum (1) */ 69 | 0x75, 0x01, /* Report Size (1) */ 70 | 0x95, 0x04, /* Report Count (4) */ 71 | 0x09, 0xCD, /* Usage (Play / Pause) */ 72 | 0x09, 0xCF, /* Usage (Voice Command) */ 73 | 0x09, 0xE9, /* Usage (Volume Up) */ 74 | 0x09, 0xEA, /* Usage (Volume Down) */ 75 | 0x81, 0x02, /* Input (Data, Variable, Absolute) */ 76 | 0x95, 0x04, /* Report Count (4) */ 77 | 0x81, 0x01, /* Input (Constant) */ 78 | 0xC0, /* End Collection */ 79 | 80 | 0x06, 0x00, 0xff, // USAGE_PAGE (Vendor Defined Page 1) 81 | 0x09, 0x04, // USAGE (Vendor Usage 4) 82 | 0xa1, 0x01, // COLLECTION (Application) 83 | 0x85, REPORTID_SPECKEYS, // REPORT_ID (Special Keys) 84 | 0x15, 0x00, // LOGICAL_MINIMUM (0) 85 | 0x26, 0xff, 0x00, // LOGICAL_MAXIMUM (256) 86 | 0x75, 0x08, // REPORT_SIZE (8) - bits 87 | 0x95, 0x01, // REPORT_COUNT (1) - Bytes 88 | 0x09, 0x02, // USAGE (Vendor Usage 1) 89 | 0x81, 0x02, // INPUT (Data,Var,Abs) 90 | 0x09, 0x03, // USAGE (Vendor Usage 2) 91 | 0x81, 0x02, // INPUT (Data,Var,Abs) 92 | 0xc0, // END_COLLECTION 93 | }; 94 | 95 | 96 | // 97 | // This is the default HID descriptor returned by the mini driver 98 | // in response to IOCTL_HID_GET_DEVICE_DESCRIPTOR. The size 99 | // of report descriptor is currently the size of DefaultReportDescriptor. 100 | // 101 | 102 | CONST HID_DESCRIPTOR DefaultHidDescriptor = { 103 | 0x09, // length of HID descriptor 104 | 0x21, // descriptor type == HID 0x21 105 | 0x0100, // hid spec release 106 | 0x00, // country code == Not Specified 107 | 0x01, // number of HID class descriptors 108 | { 0x22, // descriptor type 109 | sizeof(DefaultReportDescriptor) } // total length of report descriptor 110 | }; 111 | #endif 112 | 113 | struct reg { 114 | uint16_t reg; 115 | uint8_t val; 116 | }; 117 | 118 | typedef struct _CS42L42_CONTEXT 119 | { 120 | 121 | WDFDEVICE FxDevice; 122 | 123 | WDFQUEUE ReportQueue; 124 | 125 | SPB_CONTEXT I2CContext; 126 | 127 | WDFWAITLOCK RegisterLock; 128 | 129 | BOOLEAN DevicePoweredOn; 130 | 131 | WDFINTERRUPT Interrupt; 132 | 133 | INT JackType; 134 | 135 | //device data 136 | UINT8 ts_inv; 137 | UINT8 ts_dbnc_rise; 138 | UINT8 ts_dbnc_fall; 139 | UINT8 btn_det_init_dbnce; 140 | UINT8 btn_det_event_dbnce; 141 | 142 | UINT32 bias_thresholds[4]; 143 | 144 | UINT8 hs_bias_ramp_rate; 145 | UINT8 hs_bias_ramp_time; 146 | UINT8 hs_bias_sense_en; 147 | 148 | //device variables 149 | UINT8 plug_state; 150 | UINT8 hs_type; 151 | 152 | int pll_config; 153 | 154 | int button_state; 155 | } CS42L42_CONTEXT, *PCS42L42_CONTEXT; 156 | 157 | WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(CS42L42_CONTEXT, GetDeviceContext) 158 | 159 | // 160 | // Function definitions 161 | // 162 | 163 | DRIVER_INITIALIZE DriverEntry; 164 | 165 | EVT_WDF_DRIVER_UNLOAD Cs42l42DriverUnload; 166 | 167 | EVT_WDF_DRIVER_DEVICE_ADD Cs42l42EvtDeviceAdd; 168 | 169 | EVT_WDFDEVICE_WDM_IRP_PREPROCESS Cs42l42EvtWdmPreprocessMnQueryId; 170 | 171 | EVT_WDF_IO_QUEUE_IO_INTERNAL_DEVICE_CONTROL Cs42l42EvtInternalDeviceControl; 172 | 173 | NTSTATUS 174 | Cs42l42GetHidDescriptor( 175 | IN WDFDEVICE Device, 176 | IN WDFREQUEST Request 177 | ); 178 | 179 | NTSTATUS 180 | Cs42l42GetReportDescriptor( 181 | IN WDFDEVICE Device, 182 | IN WDFREQUEST Request 183 | ); 184 | 185 | NTSTATUS 186 | Cs42l42GetDeviceAttributes( 187 | IN WDFREQUEST Request 188 | ); 189 | 190 | NTSTATUS 191 | Cs42l42GetString( 192 | IN WDFREQUEST Request 193 | ); 194 | 195 | NTSTATUS 196 | Cs42l42WriteReport( 197 | IN PCS42L42_CONTEXT DevContext, 198 | IN WDFREQUEST Request 199 | ); 200 | 201 | NTSTATUS 202 | Cs42l42ProcessVendorReport( 203 | IN PCS42L42_CONTEXT DevContext, 204 | IN PVOID ReportBuffer, 205 | IN ULONG ReportBufferLen, 206 | OUT size_t* BytesWritten 207 | ); 208 | 209 | NTSTATUS 210 | Cs42l42ReadReport( 211 | IN PCS42L42_CONTEXT DevContext, 212 | IN WDFREQUEST Request, 213 | OUT BOOLEAN* CompleteRequest 214 | ); 215 | 216 | NTSTATUS 217 | Cs42l42SetFeature( 218 | IN PCS42L42_CONTEXT DevContext, 219 | IN WDFREQUEST Request, 220 | OUT BOOLEAN* CompleteRequest 221 | ); 222 | 223 | NTSTATUS 224 | Cs42l42GetFeature( 225 | IN PCS42L42_CONTEXT DevContext, 226 | IN WDFREQUEST Request, 227 | OUT BOOLEAN* CompleteRequest 228 | ); 229 | 230 | PCHAR 231 | DbgHidInternalIoctlString( 232 | IN ULONG IoControlCode 233 | ); 234 | 235 | // 236 | // Helper macros 237 | // 238 | 239 | #define DEBUG_LEVEL_ERROR 1 240 | #define DEBUG_LEVEL_INFO 2 241 | #define DEBUG_LEVEL_VERBOSE 3 242 | 243 | #define DBG_INIT 1 244 | #define DBG_PNP 2 245 | #define DBG_IOCTL 4 246 | 247 | #if 0 248 | #define Cs42l42Print(dbglevel, dbgcatagory, fmt, ...) { \ 249 | if (Cs42l42DebugLevel >= dbglevel && \ 250 | (Cs42l42DebugCatagories && dbgcatagory)) \ 251 | { \ 252 | DbgPrint(DRIVERNAME); \ 253 | DbgPrint(fmt, __VA_ARGS__); \ 254 | } \ 255 | } 256 | #else 257 | #define Cs42l42Print(dbglevel, fmt, ...) { \ 258 | } 259 | #endif 260 | 261 | #endif -------------------------------------------------------------------------------- /cs42l42/spb.c: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.c 8 | 9 | Abstract: 10 | 11 | Contains all I2C-specific functionality 12 | 13 | Environment: 14 | 15 | Kernel mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #include "cs42l42.h" 22 | #include "spb.h" 23 | #include 24 | 25 | static ULONG Cs42l42DebugLevel = 100; 26 | static ULONG Cs42l42DebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 27 | 28 | NTSTATUS 29 | SpbDoWriteDataSynchronously( 30 | IN SPB_CONTEXT* SpbContext, 31 | IN PVOID Data, 32 | IN ULONG Length 33 | ) 34 | /*++ 35 | 36 | Routine Description: 37 | 38 | This helper routine abstracts creating and sending an I/O 39 | request (I2C Write) to the Spb I/O target. 40 | 41 | Arguments: 42 | 43 | SpbContext - Pointer to the current device context 44 | Address - The I2C register address to write to 45 | Data - A buffer to receive the data at at the above address 46 | Length - The amount of data to be read from the above address 47 | 48 | Return Value: 49 | 50 | NTSTATUS Status indicating success or failure 51 | 52 | --*/ 53 | { 54 | PUCHAR buffer; 55 | ULONG length; 56 | WDFMEMORY memory; 57 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 58 | NTSTATUS status; 59 | 60 | length = Length; 61 | memory = NULL; 62 | 63 | if (length > DEFAULT_SPB_BUFFER_SIZE) 64 | { 65 | status = WdfMemoryCreate( 66 | WDF_NO_OBJECT_ATTRIBUTES, 67 | NonPagedPool, 68 | CS42L42_POOL_TAG, 69 | length, 70 | &memory, 71 | (PVOID*)&buffer); 72 | 73 | if (!NT_SUCCESS(status)) 74 | { 75 | Cs42l42Print( 76 | DEBUG_LEVEL_ERROR, 77 | DBG_IOCTL, 78 | "Error allocating memory for Spb write - %!STATUS!", 79 | status); 80 | goto exit; 81 | } 82 | 83 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 84 | &memoryDescriptor, 85 | memory, 86 | NULL); 87 | } 88 | else 89 | { 90 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->WriteMemory, NULL); 91 | 92 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 93 | &memoryDescriptor, 94 | (PVOID)buffer, 95 | length); 96 | } 97 | 98 | RtlCopyMemory(buffer, Data, length); 99 | 100 | status = WdfIoTargetSendWriteSynchronously( 101 | SpbContext->SpbIoTarget, 102 | NULL, 103 | &memoryDescriptor, 104 | NULL, 105 | NULL, 106 | NULL); 107 | 108 | if (!NT_SUCCESS(status)) 109 | { 110 | Cs42l42Print( 111 | DEBUG_LEVEL_ERROR, 112 | DBG_IOCTL, 113 | "Error writing to Spb - %!STATUS!", 114 | status); 115 | goto exit; 116 | } 117 | 118 | exit: 119 | 120 | if (NULL != memory) 121 | { 122 | WdfObjectDelete(memory); 123 | } 124 | 125 | return status; 126 | } 127 | 128 | NTSTATUS 129 | SpbWriteDataSynchronously( 130 | IN SPB_CONTEXT* SpbContext, 131 | IN PVOID Data, 132 | IN ULONG Length 133 | ) 134 | /*++ 135 | 136 | Routine Description: 137 | 138 | This routine abstracts creating and sending an I/O 139 | request (I2C Write) to the Spb I/O target and utilizes 140 | a helper routine to do work inside of locked code. 141 | 142 | Arguments: 143 | 144 | SpbContext - Pointer to the current device context 145 | Address - The I2C register address to write to 146 | Data - A buffer to receive the data at at the above address 147 | Length - The amount of data to be read from the above address 148 | 149 | Return Value: 150 | 151 | NTSTATUS Status indicating success or failure 152 | 153 | --*/ 154 | { 155 | NTSTATUS status; 156 | 157 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 158 | 159 | status = SpbDoWriteDataSynchronously( 160 | SpbContext, 161 | Data, 162 | Length); 163 | 164 | WdfWaitLockRelease(SpbContext->SpbLock); 165 | 166 | return status; 167 | } 168 | 169 | NTSTATUS 170 | SpbXferDataSynchronously( 171 | _In_ SPB_CONTEXT* SpbContext, 172 | _In_ PVOID SendData, 173 | _In_ ULONG SendLength, 174 | _In_reads_bytes_(Length) PVOID Data, 175 | _In_ ULONG Length 176 | ) 177 | /*++ 178 | Routine Description: 179 | This helper routine abstracts creating and sending an I/O 180 | request (I2C Read) to the Spb I/O target. 181 | Arguments: 182 | SpbContext - Pointer to the current device context 183 | Address - The I2C register address to read from 184 | Data - A buffer to receive the data at at the above address 185 | Length - The amount of data to be read from the above address 186 | Return Value: 187 | NTSTATUS Status indicating success or failure 188 | --*/ 189 | { 190 | PUCHAR buffer; 191 | WDFMEMORY memory; 192 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 193 | NTSTATUS status; 194 | ULONG_PTR bytesRead; 195 | 196 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 197 | 198 | memory = NULL; 199 | status = STATUS_INVALID_PARAMETER; 200 | bytesRead = 0; 201 | 202 | // 203 | // Xfer transactions start by writing an address pointer 204 | // 205 | status = SpbDoWriteDataSynchronously( 206 | SpbContext, 207 | SendData, 208 | SendLength); 209 | 210 | if (!NT_SUCCESS(status)) 211 | { 212 | Cs42l42Print( 213 | DEBUG_LEVEL_ERROR, 214 | DBG_IOCTL, 215 | "Error setting address pointer for Spb read - %!STATUS!", 216 | status); 217 | goto exit; 218 | } 219 | 220 | if (Length > DEFAULT_SPB_BUFFER_SIZE) 221 | { 222 | status = WdfMemoryCreate( 223 | WDF_NO_OBJECT_ATTRIBUTES, 224 | NonPagedPool, 225 | CS42L42_POOL_TAG, 226 | Length, 227 | &memory, 228 | (PVOID*)&buffer); 229 | 230 | if (!NT_SUCCESS(status)) 231 | { 232 | Cs42l42Print( 233 | DEBUG_LEVEL_ERROR, 234 | DBG_IOCTL, 235 | "Error allocating memory for Spb read - %!STATUS!", 236 | status); 237 | goto exit; 238 | } 239 | 240 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 241 | &memoryDescriptor, 242 | memory, 243 | NULL); 244 | } 245 | else 246 | { 247 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->ReadMemory, NULL); 248 | 249 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 250 | &memoryDescriptor, 251 | (PVOID)buffer, 252 | Length); 253 | } 254 | 255 | 256 | status = WdfIoTargetSendReadSynchronously( 257 | SpbContext->SpbIoTarget, 258 | NULL, 259 | &memoryDescriptor, 260 | NULL, 261 | NULL, 262 | &bytesRead); 263 | 264 | if (!NT_SUCCESS(status) || 265 | bytesRead != Length) 266 | { 267 | Cs42l42Print( 268 | DEBUG_LEVEL_ERROR, 269 | DBG_IOCTL, 270 | "Error reading from Spb - %!STATUS!", 271 | status); 272 | goto exit; 273 | } 274 | 275 | // 276 | // Copy back to the caller's buffer 277 | // 278 | RtlCopyMemory(Data, buffer, Length); 279 | 280 | exit: 281 | if (NULL != memory) 282 | { 283 | WdfObjectDelete(memory); 284 | } 285 | 286 | WdfWaitLockRelease(SpbContext->SpbLock); 287 | 288 | return status; 289 | } 290 | 291 | VOID 292 | SpbTargetDeinitialize( 293 | IN WDFDEVICE FxDevice, 294 | IN SPB_CONTEXT* SpbContext 295 | ) 296 | /*++ 297 | 298 | Routine Description: 299 | 300 | This helper routine is used to free any members added to the SPB_CONTEXT, 301 | note the SPB I/O target is parented to the device and will be 302 | closed and free'd when the device is removed. 303 | 304 | Arguments: 305 | 306 | FxDevice - Handle to the framework device object 307 | SpbContext - Pointer to the current device context 308 | 309 | Return Value: 310 | 311 | NTSTATUS Status indicating success or failure 312 | 313 | --*/ 314 | { 315 | UNREFERENCED_PARAMETER(FxDevice); 316 | UNREFERENCED_PARAMETER(SpbContext); 317 | 318 | // 319 | // Free any SPB_CONTEXT allocations here 320 | // 321 | if (SpbContext->SpbLock != NULL) 322 | { 323 | WdfObjectDelete(SpbContext->SpbLock); 324 | } 325 | 326 | if (SpbContext->ReadMemory != NULL) 327 | { 328 | WdfObjectDelete(SpbContext->ReadMemory); 329 | } 330 | 331 | if (SpbContext->WriteMemory != NULL) 332 | { 333 | WdfObjectDelete(SpbContext->WriteMemory); 334 | } 335 | } 336 | 337 | NTSTATUS 338 | SpbTargetInitialize( 339 | IN WDFDEVICE FxDevice, 340 | IN SPB_CONTEXT* SpbContext 341 | ) 342 | /*++ 343 | 344 | Routine Description: 345 | 346 | This helper routine opens the Spb I/O target and 347 | initializes a request object used for the lifetime 348 | of communication between this driver and Spb. 349 | 350 | Arguments: 351 | 352 | FxDevice - Handle to the framework device object 353 | SpbContext - Pointer to the current device context 354 | 355 | Return Value: 356 | 357 | NTSTATUS Status indicating success or failure 358 | 359 | --*/ 360 | { 361 | WDF_OBJECT_ATTRIBUTES objectAttributes; 362 | WDF_IO_TARGET_OPEN_PARAMS openParams; 363 | UNICODE_STRING spbDeviceName; 364 | WCHAR spbDeviceNameBuffer[RESOURCE_HUB_PATH_SIZE]; 365 | NTSTATUS status; 366 | 367 | WDF_OBJECT_ATTRIBUTES_INIT(&objectAttributes); 368 | objectAttributes.ParentObject = FxDevice; 369 | 370 | status = WdfIoTargetCreate( 371 | FxDevice, 372 | &objectAttributes, 373 | &SpbContext->SpbIoTarget); 374 | 375 | if (!NT_SUCCESS(status)) 376 | { 377 | Cs42l42Print( 378 | DEBUG_LEVEL_ERROR, 379 | DBG_IOCTL, 380 | "Error creating IoTarget object - %!STATUS!", 381 | status); 382 | 383 | WdfObjectDelete(SpbContext->SpbIoTarget); 384 | goto exit; 385 | } 386 | 387 | RtlInitEmptyUnicodeString( 388 | &spbDeviceName, 389 | spbDeviceNameBuffer, 390 | sizeof(spbDeviceNameBuffer)); 391 | 392 | status = RESOURCE_HUB_CREATE_PATH_FROM_ID( 393 | &spbDeviceName, 394 | SpbContext->I2cResHubId.LowPart, 395 | SpbContext->I2cResHubId.HighPart); 396 | 397 | if (!NT_SUCCESS(status)) 398 | { 399 | Cs42l42Print( 400 | DEBUG_LEVEL_ERROR, 401 | DBG_IOCTL, 402 | "Error creating Spb resource hub path string - %!STATUS!", 403 | status); 404 | goto exit; 405 | } 406 | 407 | WDF_IO_TARGET_OPEN_PARAMS_INIT_OPEN_BY_NAME( 408 | &openParams, 409 | &spbDeviceName, 410 | (GENERIC_READ | GENERIC_WRITE)); 411 | 412 | openParams.ShareAccess = 0; 413 | openParams.CreateDisposition = FILE_OPEN; 414 | openParams.FileAttributes = FILE_ATTRIBUTE_NORMAL; 415 | 416 | status = WdfIoTargetOpen(SpbContext->SpbIoTarget, &openParams); 417 | 418 | if (!NT_SUCCESS(status)) 419 | { 420 | Cs42l42Print( 421 | DEBUG_LEVEL_ERROR, 422 | DBG_IOCTL, 423 | "Error opening Spb target for communication - %!STATUS!", 424 | status); 425 | goto exit; 426 | } 427 | 428 | // 429 | // Allocate some fixed-size buffers from NonPagedPool for typical 430 | // Spb transaction sizes to avoid pool fragmentation in most cases 431 | // 432 | status = WdfMemoryCreate( 433 | WDF_NO_OBJECT_ATTRIBUTES, 434 | NonPagedPool, 435 | CS42L42_POOL_TAG, 436 | DEFAULT_SPB_BUFFER_SIZE, 437 | &SpbContext->WriteMemory, 438 | NULL); 439 | 440 | if (!NT_SUCCESS(status)) 441 | { 442 | Cs42l42Print( 443 | DEBUG_LEVEL_ERROR, 444 | DBG_IOCTL, 445 | "Error allocating default memory for Spb write - %!STATUS!", 446 | status); 447 | goto exit; 448 | } 449 | 450 | status = WdfMemoryCreate( 451 | WDF_NO_OBJECT_ATTRIBUTES, 452 | NonPagedPool, 453 | CS42L42_POOL_TAG, 454 | DEFAULT_SPB_BUFFER_SIZE, 455 | &SpbContext->ReadMemory, 456 | NULL); 457 | 458 | if (!NT_SUCCESS(status)) 459 | { 460 | Cs42l42Print( 461 | DEBUG_LEVEL_ERROR, 462 | DBG_IOCTL, 463 | "Error allocating default memory for Spb read - %!STATUS!", 464 | status); 465 | goto exit; 466 | } 467 | 468 | // 469 | // Allocate a waitlock to guard access to the default buffers 470 | // 471 | status = WdfWaitLockCreate( 472 | WDF_NO_OBJECT_ATTRIBUTES, 473 | &SpbContext->SpbLock); 474 | 475 | if (!NT_SUCCESS(status)) 476 | { 477 | Cs42l42Print( 478 | DEBUG_LEVEL_ERROR, 479 | DBG_IOCTL, 480 | "Error creating Spb Waitlock - %!STATUS!", 481 | status); 482 | goto exit; 483 | } 484 | 485 | exit: 486 | 487 | if (!NT_SUCCESS(status)) 488 | { 489 | SpbTargetDeinitialize(FxDevice, SpbContext); 490 | } 491 | 492 | return status; 493 | } -------------------------------------------------------------------------------- /cs42l42/registers.h: -------------------------------------------------------------------------------- 1 | #include "stdint.h" 2 | 3 | #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */ 4 | #define CS42L42_WIN_START 0x00 5 | #define CS42L42_WIN_LEN 0x100 6 | #define CS42L42_RANGE_MIN 0x00 7 | #define CS42L42_RANGE_MAX 0x7F 8 | 9 | #define CS42L42_PAGE_10 0x1000 10 | #define CS42L42_PAGE_11 0x1100 11 | #define CS42L42_PAGE_12 0x1200 12 | #define CS42L42_PAGE_13 0x1300 13 | #define CS42L42_PAGE_15 0x1500 14 | #define CS42L42_PAGE_19 0x1900 15 | #define CS42L42_PAGE_1B 0x1B00 16 | #define CS42L42_PAGE_1C 0x1C00 17 | #define CS42L42_PAGE_1D 0x1D00 18 | #define CS42L42_PAGE_1F 0x1F00 19 | #define CS42L42_PAGE_20 0x2000 20 | #define CS42L42_PAGE_21 0x2100 21 | #define CS42L42_PAGE_23 0x2300 22 | #define CS42L42_PAGE_24 0x2400 23 | #define CS42L42_PAGE_25 0x2500 24 | #define CS42L42_PAGE_26 0x2600 25 | #define CS42L42_PAGE_28 0x2800 26 | #define CS42L42_PAGE_29 0x2900 27 | #define CS42L42_PAGE_2A 0x2A00 28 | #define CS42L42_PAGE_30 0x3000 29 | 30 | #define CS42L42_CHIP_ID 0x42A42 31 | #define CS42L83_CHIP_ID 0x42A83 32 | 33 | /* Page 0x10 Global Registers */ 34 | #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01) 35 | #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02) 36 | #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03) 37 | #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04) 38 | #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05) 39 | #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06) 40 | 41 | #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07) 42 | #define CS42L42_SRC_BYPASS_DAC_SHIFT 1 43 | #define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT) 44 | 45 | #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08) 46 | 47 | #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09) 48 | #define CS42L42_INTERNAL_FS_SHIFT 1 49 | #define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT) 50 | 51 | #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A) 52 | #define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B) 53 | #define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4) 54 | #define CS42L42_SLOW_START_EN_SHIFT 4 55 | #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E) 56 | #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F) 57 | #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10) 58 | 59 | /* Page 0x11 Power and Headset Detect Registers */ 60 | #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01) 61 | #define CS42L42_ASP_DAO_PDN_SHIFT 7 62 | #define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT) 63 | #define CS42L42_ASP_DAI_PDN_SHIFT 6 64 | #define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT) 65 | #define CS42L42_MIXER_PDN_SHIFT 5 66 | #define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT) 67 | #define CS42L42_EQ_PDN_SHIFT 4 68 | #define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT) 69 | #define CS42L42_HP_PDN_SHIFT 3 70 | #define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT) 71 | #define CS42L42_ADC_PDN_SHIFT 2 72 | #define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT) 73 | #define CS42L42_PDN_ALL_SHIFT 0 74 | #define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT) 75 | 76 | #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02) 77 | #define CS42L42_ADC_SRC_PDNB_SHIFT 0 78 | #define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT) 79 | #define CS42L42_DAC_SRC_PDNB_SHIFT 1 80 | #define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT) 81 | #define CS42L42_ASP_DAI1_PDN_SHIFT 2 82 | #define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT) 83 | #define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3 84 | #define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT) 85 | #define CS42L42_DISCHARGE_FILT_SHIFT 4 86 | #define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT) 87 | 88 | #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03) 89 | #define CS42L42_RING_SENSE_PDNB_SHIFT 1 90 | #define CS42L42_RING_SENSE_PDNB_MASK (1 << CS42L42_RING_SENSE_PDNB_SHIFT) 91 | #define CS42L42_VPMON_PDNB_SHIFT 2 92 | #define CS42L42_VPMON_PDNB_MASK (1 << CS42L42_VPMON_PDNB_SHIFT) 93 | #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5 94 | #define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << CS42L42_SW_CLK_STP_STAT_SEL_SHIFT) 95 | 96 | #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04) 97 | #define CS42L42_RS_TRIM_R_SHIFT 0 98 | #define CS42L42_RS_TRIM_R_MASK (1 << CS42L42_RS_TRIM_R_SHIFT) 99 | #define CS42L42_RS_TRIM_T_SHIFT 1 100 | #define CS42L42_RS_TRIM_T_MASK (1 << CS42L42_RS_TRIM_T_SHIFT) 101 | #define CS42L42_HPREF_RS_SHIFT 2 102 | #define CS42L42_HPREF_RS_MASK (1 << CS42L42_HPREF_RS_SHIFT) 103 | #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3 104 | #define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << CS42L42_HSBIAS_FILT_REF_RS_SHIFT) 105 | #define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6 106 | #define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << CS42L42_RING_SENSE_PU_HIZ_SHIFT) 107 | 108 | #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05) 109 | #define CS42L42_TS_RS_GATE_SHIFT 7 110 | #define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT) 111 | 112 | #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07) 113 | #define CS42L42_SCLK_PRESENT_SHIFT 0 114 | #define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT) 115 | 116 | #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09) 117 | #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0 118 | #define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT) 119 | #define CS42L42_OSC_PDNB_STAT_SHIFT 2 120 | #define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT) 121 | 122 | #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12) 123 | #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0 124 | #define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << CS42L42_RS_RISE_DBNCE_TIME_SHIFT) 125 | #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3 126 | #define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << CS42L42_RS_FALL_DBNCE_TIME_SHIFT) 127 | #define CS42L42_RS_PU_EN_SHIFT 6 128 | #define CS42L42_RS_PU_EN_MASK (1 << CS42L42_RS_PU_EN_SHIFT) 129 | #define CS42L42_RS_INV_SHIFT 7 130 | #define CS42L42_RS_INV_MASK (1 << CS42L42_RS_INV_SHIFT) 131 | 132 | #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13) 133 | #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0 134 | #define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << CS42L42_TS_RISE_DBNCE_TIME_SHIFT) 135 | #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3 136 | #define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << CS42L42_TS_FALL_DBNCE_TIME_SHIFT) 137 | #define CS42L42_TS_INV_SHIFT 7 138 | #define CS42L42_TS_INV_MASK (1 << CS42L42_TS_INV_SHIFT) 139 | 140 | #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14) 141 | #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0 142 | #define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT) 143 | #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1 144 | #define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT) 145 | #define CS42L42_D_TS_PLUG_DBNC_SHIFT 2 146 | #define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT) 147 | #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3 148 | #define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT) 149 | 150 | #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15) 151 | #define CS42L42_RS_PLUG_DBNC_SHIFT 0 152 | #define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT) 153 | #define CS42L42_RS_UNPLUG_DBNC_SHIFT 1 154 | #define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT) 155 | #define CS42L42_TS_PLUG_DBNC_SHIFT 2 156 | #define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT) 157 | #define CS42L42_TS_UNPLUG_DBNC_SHIFT 3 158 | #define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT) 159 | 160 | #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F) 161 | #define CS42L42_HSDET_COMP1_LVL_SHIFT 0 162 | #define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT) 163 | #define CS42L42_HSDET_COMP2_LVL_SHIFT 4 164 | #define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT) 165 | 166 | #define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 1.25V Comparator */ 167 | #define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 1.75V Comparator */ 168 | #define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 1V Comparator */ 169 | #define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 2V Comparator */ 170 | 171 | #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20) 172 | #define CS42L42_HSDET_AUTO_TIME_SHIFT 0 173 | #define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT) 174 | #define CS42L42_HSBIAS_REF_SHIFT 3 175 | #define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT) 176 | #define CS42L42_HSDET_SET_SHIFT 4 177 | #define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT) 178 | #define CS42L42_HSDET_CTRL_SHIFT 6 179 | #define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT) 180 | 181 | #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21) 182 | #define CS42L42_SW_GNDHS_HS4_SHIFT 0 183 | #define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT) 184 | #define CS42L42_SW_GNDHS_HS3_SHIFT 1 185 | #define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT) 186 | #define CS42L42_SW_HSB_HS4_SHIFT 2 187 | #define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT) 188 | #define CS42L42_SW_HSB_HS3_SHIFT 3 189 | #define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT) 190 | #define CS42L42_SW_HSB_FILT_HS4_SHIFT 4 191 | #define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) 192 | #define CS42L42_SW_HSB_FILT_HS3_SHIFT 5 193 | #define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) 194 | #define CS42L42_SW_REF_HS4_SHIFT 6 195 | #define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT) 196 | #define CS42L42_SW_REF_HS3_SHIFT 7 197 | #define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT) 198 | 199 | #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24) 200 | #define CS42L42_HSDET_TYPE_SHIFT 0 201 | #define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT) 202 | #define CS42L42_HSDET_COMP1_OUT_SHIFT 6 203 | #define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT) 204 | #define CS42L42_HSDET_COMP2_OUT_SHIFT 7 205 | #define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT) 206 | #define CS42L42_PLUG_CTIA 0 207 | #define CS42L42_PLUG_OMTP 1 208 | #define CS42L42_PLUG_HEADPHONE 2 209 | #define CS42L42_PLUG_INVALID 3 210 | 211 | #define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 212 | (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 213 | (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ 214 | (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 215 | (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 216 | (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 217 | (0 << CS42L42_SW_REF_HS4_SHIFT) | \ 218 | (1 << CS42L42_SW_REF_HS3_SHIFT)) 219 | #define CS42L42_HSDET_SW_COMP2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 220 | (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 221 | (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ 222 | (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ 223 | (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 224 | (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 225 | (1 << CS42L42_SW_REF_HS4_SHIFT) | \ 226 | (0 << CS42L42_SW_REF_HS3_SHIFT)) 227 | #define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 228 | (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 229 | (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ 230 | (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 231 | (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 232 | (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 233 | (0 << CS42L42_SW_REF_HS4_SHIFT) | \ 234 | (1 << CS42L42_SW_REF_HS3_SHIFT)) 235 | #define CS42L42_HSDET_SW_TYPE2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 236 | (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 237 | (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ 238 | (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ 239 | (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 240 | (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 241 | (1 << CS42L42_SW_REF_HS4_SHIFT) | \ 242 | (0 << CS42L42_SW_REF_HS3_SHIFT)) 243 | #define CS42L42_HSDET_SW_TYPE3 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 244 | (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 245 | (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ 246 | (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 247 | (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 248 | (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 249 | (1 << CS42L42_SW_REF_HS4_SHIFT) | \ 250 | (1 << CS42L42_SW_REF_HS3_SHIFT)) 251 | #define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 252 | (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 253 | (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ 254 | (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 255 | (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 256 | (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 257 | (0 << CS42L42_SW_REF_HS4_SHIFT) | \ 258 | (1 << CS42L42_SW_REF_HS3_SHIFT)) 259 | 260 | #define CS42L42_HSDET_COMP_TYPE1 1 261 | #define CS42L42_HSDET_COMP_TYPE2 2 262 | #define CS42L42_HSDET_COMP_TYPE3 0 263 | #define CS42L42_HSDET_COMP_TYPE4 3 264 | 265 | #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29) 266 | #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0 267 | #define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT) 268 | 269 | /* Page 0x12 Clocking Registers */ 270 | #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01) 271 | #define CS42L42_MCLKDIV_SHIFT 1 272 | #define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT) 273 | #define CS42L42_MCLK_SRC_SEL_SHIFT 0 274 | #define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT) 275 | 276 | #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02) 277 | #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03) 278 | 279 | #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04) 280 | #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0 281 | #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \ 282 | CS42L42_FSYNC_PULSE_WIDTH_SHIFT) 283 | 284 | #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05) 285 | 286 | #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06) 287 | #define CS42L42_FSYNC_PERIOD_SHIFT 0 288 | #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT) 289 | 290 | #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07) 291 | #define CS42L42_ASP_SCLK_EN_SHIFT 5 292 | #define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT) 293 | #define CS42L42_ASP_MASTER_MODE 0x01 294 | #define CS42L42_ASP_SLAVE_MODE 0x00 295 | #define CS42L42_ASP_MODE_SHIFT 4 296 | #define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT) 297 | #define CS42L42_ASP_SCPOL_SHIFT 2 298 | #define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT) 299 | #define CS42L42_ASP_SCPOL_NOR 3 300 | #define CS42L42_ASP_LCPOL_SHIFT 0 301 | #define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT) 302 | #define CS42L42_ASP_LCPOL_INV 3 303 | 304 | #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08) 305 | #define CS42L42_ASP_STP_SHIFT 4 306 | #define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT) 307 | #define CS42L42_ASP_5050_SHIFT 3 308 | #define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT) 309 | #define CS42L42_ASP_FSD_SHIFT 0 310 | #define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT) 311 | #define CS42L42_ASP_FSD_0_5 1 312 | #define CS42L42_ASP_FSD_1_0 2 313 | #define CS42L42_ASP_FSD_1_5 3 314 | #define CS42L42_ASP_FSD_2_0 4 315 | 316 | #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09) 317 | #define CS42L42_FS_EN_SHIFT 0 318 | #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT) 319 | #define CS42L42_FS_EN_IASRC_96K 0x1 320 | #define CS42L42_FS_EN_OASRC_96K 0x2 321 | 322 | #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A) 323 | #define CS42L42_CLK_IASRC_SEL_SHIFT 0 324 | #define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT) 325 | #define CS42L42_CLK_IASRC_SEL_6 0 326 | #define CS42L42_CLK_IASRC_SEL_12 1 327 | 328 | #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B) 329 | #define CS42L42_CLK_OASRC_SEL_SHIFT 0 330 | #define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT) 331 | #define CS42L42_CLK_OASRC_SEL_12 1 332 | 333 | #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C) 334 | #define CS42L42_SCLK_PREDIV_SHIFT 0 335 | #define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT) 336 | 337 | /* Page 0x13 Interrupt Registers */ 338 | /* Interrupts */ 339 | #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01) 340 | #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02) 341 | #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03) 342 | #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04) 343 | #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05) 344 | #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08) 345 | #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09) 346 | #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A) 347 | #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B) 348 | #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D) 349 | #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E) 350 | #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F) 351 | /* Masks */ 352 | #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16) 353 | #define CS42L42_ADC_OVFL_SHIFT 0 354 | #define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT) 355 | #define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK 356 | 357 | #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17) 358 | #define CS42L42_MIX_CHB_OVFL_SHIFT 0 359 | #define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT) 360 | #define CS42L42_MIX_CHA_OVFL_SHIFT 1 361 | #define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT) 362 | #define CS42L42_EQ_OVFL_SHIFT 2 363 | #define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT) 364 | #define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3 365 | #define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT) 366 | #define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \ 367 | CS42L42_MIX_CHA_OVFL_MASK | \ 368 | CS42L42_EQ_OVFL_MASK | \ 369 | CS42L42_EQ_BIQUAD_OVFL_MASK) 370 | 371 | #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18) 372 | #define CS42L42_SRC_ILK_SHIFT 0 373 | #define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT) 374 | #define CS42L42_SRC_OLK_SHIFT 1 375 | #define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT) 376 | #define CS42L42_SRC_IUNLK_SHIFT 2 377 | #define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT) 378 | #define CS42L42_SRC_OUNLK_SHIFT 3 379 | #define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT) 380 | #define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \ 381 | CS42L42_SRC_OLK_MASK | \ 382 | CS42L42_SRC_IUNLK_MASK | \ 383 | CS42L42_SRC_OUNLK_MASK) 384 | 385 | #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19) 386 | #define CS42L42_ASPRX_NOLRCK_SHIFT 0 387 | #define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT) 388 | #define CS42L42_ASPRX_EARLY_SHIFT 1 389 | #define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT) 390 | #define CS42L42_ASPRX_LATE_SHIFT 2 391 | #define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT) 392 | #define CS42L42_ASPRX_ERROR_SHIFT 3 393 | #define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT) 394 | #define CS42L42_ASPRX_OVLD_SHIFT 4 395 | #define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT) 396 | #define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \ 397 | CS42L42_ASPRX_EARLY_MASK | \ 398 | CS42L42_ASPRX_LATE_MASK | \ 399 | CS42L42_ASPRX_ERROR_MASK | \ 400 | CS42L42_ASPRX_OVLD_MASK) 401 | 402 | #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A) 403 | #define CS42L42_ASPTX_NOLRCK_SHIFT 0 404 | #define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT) 405 | #define CS42L42_ASPTX_EARLY_SHIFT 1 406 | #define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT) 407 | #define CS42L42_ASPTX_LATE_SHIFT 2 408 | #define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT) 409 | #define CS42L42_ASPTX_SMERROR_SHIFT 3 410 | #define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT) 411 | #define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \ 412 | CS42L42_ASPTX_EARLY_MASK | \ 413 | CS42L42_ASPTX_LATE_MASK | \ 414 | CS42L42_ASPTX_SMERROR_MASK) 415 | 416 | #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B) 417 | #define CS42L42_PDN_DONE_SHIFT 0 418 | #define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT) 419 | #define CS42L42_HSDET_AUTO_DONE_SHIFT 1 420 | #define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT) 421 | #define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \ 422 | CS42L42_HSDET_AUTO_DONE_MASK) 423 | 424 | #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C) 425 | #define CS42L42_SRCPL_ADC_LK_SHIFT 0 426 | #define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT) 427 | #define CS42L42_SRCPL_DAC_LK_SHIFT 2 428 | #define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT) 429 | #define CS42L42_SRCPL_ADC_UNLK_SHIFT 5 430 | #define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) 431 | #define CS42L42_SRCPL_DAC_UNLK_SHIFT 6 432 | #define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT) 433 | #define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \ 434 | CS42L42_SRCPL_DAC_LK_MASK | \ 435 | CS42L42_SRCPL_ADC_UNLK_MASK | \ 436 | CS42L42_SRCPL_DAC_UNLK_MASK) 437 | 438 | #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E) 439 | #define CS42L42_VPMON_SHIFT 0 440 | #define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT) 441 | #define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK 442 | 443 | #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F) 444 | #define CS42L42_PLL_LOCK_SHIFT 0 445 | #define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT) 446 | #define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK 447 | 448 | #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20) 449 | #define CS42L42_RS_PLUG_SHIFT 0 450 | #define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT) 451 | #define CS42L42_RS_UNPLUG_SHIFT 1 452 | #define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT) 453 | #define CS42L42_TS_PLUG_SHIFT 2 454 | #define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT) 455 | #define CS42L42_TS_UNPLUG_SHIFT 3 456 | #define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT) 457 | #define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \ 458 | CS42L42_RS_UNPLUG_MASK | \ 459 | CS42L42_TS_PLUG_MASK | \ 460 | CS42L42_TS_UNPLUG_MASK) 461 | #define CS42L42_TS_PLUG 3 462 | #define CS42L42_TS_UNPLUG 0 463 | #define CS42L42_TS_TRANS 1 464 | 465 | /* 466 | * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1. 467 | * Otherwise it will prevent FILT+ from charging properly. 468 | */ 469 | #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01) 470 | #define CS42L42_PLL_START_SHIFT 0 471 | #define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT) 472 | 473 | #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02) 474 | #define CS42L42_PLL_DIV_FRAC_SHIFT 0 475 | #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT) 476 | 477 | #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03) 478 | #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04) 479 | 480 | #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05) 481 | #define CS42L42_PLL_DIV_INT_SHIFT 0 482 | #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT) 483 | 484 | #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08) 485 | #define CS42L42_PLL_DIVOUT_SHIFT 0 486 | #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT) 487 | 488 | #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A) 489 | #define CS42L42_PLL_CAL_RATIO_SHIFT 0 490 | #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT) 491 | 492 | #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B) 493 | #define CS42L42_PLL_MODE_SHIFT 0 494 | #define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT) 495 | 496 | /* Page 0x19 HP Load Detect Registers */ 497 | #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25) 498 | #define CS42L42_RLA_STAT_SHIFT 0 499 | #define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT) 500 | #define CS42L42_RLA_STAT_15_OHM 0 501 | 502 | #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26) 503 | #define CS42L42_HPLOAD_DET_DONE_SHIFT 0 504 | #define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT) 505 | 506 | #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27) 507 | #define CS42L42_HP_LD_EN_SHIFT 0 508 | #define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT) 509 | 510 | /* Page 0x1B Headset Interface Registers */ 511 | #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70) 512 | #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0 513 | #define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT) 514 | #define CS42L42_TIP_SENSE_EN_SHIFT 5 515 | #define CS42L42_TIP_SENSE_EN_MASK (1 << CS42L42_TIP_SENSE_EN_SHIFT) 516 | #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6 517 | #define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) 518 | #define CS42L42_HSBIAS_SENSE_EN_SHIFT 7 519 | #define CS42L42_HSBIAS_SENSE_EN_MASK (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) 520 | 521 | #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71) 522 | #define CS42L42_WAKEB_CLEAR_SHIFT 0 523 | #define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT) 524 | #define CS42L42_WAKEB_MODE_SHIFT 5 525 | #define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT) 526 | #define CS42L42_M_HP_WAKE_SHIFT 6 527 | #define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT) 528 | #define CS42L42_M_MIC_WAKE_SHIFT 7 529 | #define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT) 530 | 531 | #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72) 532 | #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7 533 | #define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << CS42L42_ADC_DISABLE_S0_MUTE_SHIFT) 534 | 535 | #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73) 536 | #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0 537 | #define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT) 538 | #define CS42L42_TIP_SENSE_INV_SHIFT 5 539 | #define CS42L42_TIP_SENSE_INV_MASK (1 << CS42L42_TIP_SENSE_INV_SHIFT) 540 | #define CS42L42_TIP_SENSE_CTRL_SHIFT 6 541 | #define CS42L42_TIP_SENSE_CTRL_MASK (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) 542 | 543 | /* 544 | * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1. 545 | * Otherwise it will prevent FILT+ from charging properly. 546 | */ 547 | #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74) 548 | #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 549 | #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT) 550 | #define CS42L42_HSBIAS_CTL_SHIFT 1 551 | #define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT) 552 | #define CS42L42_DETECT_MODE_SHIFT 3 553 | #define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT) 554 | 555 | #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75) 556 | #define CS42L42_HS_DET_LEVEL_SHIFT 0 557 | #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT) 558 | #define CS42L42_EVENT_STAT_SEL_SHIFT 6 559 | #define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT) 560 | #define CS42L42_LATCH_TO_VP_SHIFT 7 561 | #define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT) 562 | 563 | #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76) 564 | #define CS42L42_DEBOUNCE_TIME_SHIFT 5 565 | #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT) 566 | 567 | #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77) 568 | #define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6 569 | #define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT) 570 | #define CS42L42_TIP_SENSE_SHIFT 7 571 | #define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT) 572 | 573 | #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78) 574 | #define CS42L42_SHORT_TRUE_SHIFT 0 575 | #define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT) 576 | #define CS42L42_HS_TRUE_SHIFT 1 577 | #define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT) 578 | 579 | #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79) 580 | #define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5 581 | #define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) 582 | #define CS42L42_TIP_SENSE_PLUG_SHIFT 6 583 | #define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) 584 | #define CS42L42_HSBIAS_SENSE_SHIFT 7 585 | #define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT) 586 | #define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \ 587 | CS42L42_TIP_SENSE_PLUG_MASK | \ 588 | CS42L42_HSBIAS_SENSE_MASK) 589 | 590 | #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A) 591 | #define CS42L42_M_SHORT_DET_SHIFT 0 592 | #define CS42L42_M_SHORT_DET_MASK (1 << CS42L42_M_SHORT_DET_SHIFT) 593 | #define CS42L42_M_SHORT_RLS_SHIFT 1 594 | #define CS42L42_M_SHORT_RLS_MASK (1 << CS42L42_M_SHORT_RLS_SHIFT) 595 | #define CS42L42_M_HSBIAS_HIZ_SHIFT 2 596 | #define CS42L42_M_HSBIAS_HIZ_MASK (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) 597 | #define CS42L42_M_DETECT_FT_SHIFT 6 598 | #define CS42L42_M_DETECT_FT_MASK (1 << CS42L42_M_DETECT_FT_SHIFT) 599 | #define CS42L42_M_DETECT_TF_SHIFT 7 600 | #define CS42L42_M_DETECT_TF_MASK (1 << CS42L42_M_DETECT_TF_SHIFT) 601 | #define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \ 602 | CS42L42_M_SHORT_RLS_MASK | \ 603 | CS42L42_M_HSBIAS_HIZ_MASK | \ 604 | CS42L42_M_DETECT_FT_MASK | \ 605 | CS42L42_M_DETECT_TF_MASK) 606 | 607 | /* Page 0x1C Headset Bias Registers */ 608 | #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03) 609 | #define CS42L42_HSBIAS_RAMP_SHIFT 0 610 | #define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT) 611 | #define CS42L42_HSBIAS_PD_SHIFT 4 612 | #define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT) 613 | #define CS42L42_HSBIAS_CAPLESS_SHIFT 7 614 | #define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT) 615 | 616 | /* Page 0x1D ADC Registers */ 617 | #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01) 618 | #define CS42L42_ADC_NOTCH_DIS_SHIFT 5 619 | #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4 620 | #define CS42L42_ADC_INV_SHIFT 2 621 | #define CS42L42_ADC_DIG_BOOST_SHIFT 0 622 | 623 | #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03) 624 | #define CS42L42_ADC_VOL_SHIFT 0 625 | 626 | #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04) 627 | #define CS42L42_ADC_WNF_CF_SHIFT 4 628 | #define CS42L42_ADC_WNF_EN_SHIFT 3 629 | #define CS42L42_ADC_HPF_CF_SHIFT 1 630 | #define CS42L42_ADC_HPF_EN_SHIFT 0 631 | 632 | /* Page 0x1F DAC Registers */ 633 | #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01) 634 | #define CS42L42_DACB_INV_SHIFT 1 635 | #define CS42L42_DACA_INV_SHIFT 0 636 | 637 | #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06) 638 | #define CS42L42_HPOUT_PULLDOWN_SHIFT 4 639 | #define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT) 640 | #define CS42L42_HPOUT_LOAD_SHIFT 3 641 | #define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT) 642 | #define CS42L42_HPOUT_CLAMP_SHIFT 2 643 | #define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT) 644 | #define CS42L42_DAC_HPF_EN_SHIFT 1 645 | #define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT) 646 | #define CS42L42_DAC_MON_EN_SHIFT 0 647 | #define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT) 648 | 649 | /* Page 0x20 HP CTL Registers */ 650 | #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01) 651 | #define CS42L42_HP_ANA_BMUTE_SHIFT 3 652 | #define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT) 653 | #define CS42L42_HP_ANA_AMUTE_SHIFT 2 654 | #define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT) 655 | #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1 656 | #define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT) 657 | 658 | /* Page 0x21 Class H Registers */ 659 | #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01) 660 | 661 | /* Page 0x23 Mixer Volume Registers */ 662 | #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01) 663 | #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02) 664 | 665 | #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03) 666 | #define CS42L42_MIXER_CH_VOL_SHIFT 0 667 | #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT) 668 | 669 | /* Page 0x24 EQ Registers */ 670 | #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01) 671 | #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02) 672 | #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03) 673 | #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04) 674 | #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06) 675 | #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07) 676 | #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08) 677 | #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09) 678 | #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A) 679 | #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B) 680 | #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C) 681 | #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E) 682 | 683 | /* Page 0x25 Audio Port Registers */ 684 | #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01) 685 | #define CS42L42_SP_RX_CHB_SEL_SHIFT 2 686 | #define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT) 687 | 688 | #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02) 689 | #define CS42L42_SP_RX_RSYNC_SHIFT 6 690 | #define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT) 691 | #define CS42L42_SP_RX_NSB_POS_SHIFT 3 692 | #define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT) 693 | #define CS42L42_SP_RX_NFS_NSBB_SHIFT 2 694 | #define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT) 695 | #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0 696 | #define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT) 697 | 698 | #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03) 699 | #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04) 700 | #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05) 701 | #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06) 702 | #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07) 703 | 704 | /* Page 0x26 SRC Registers */ 705 | #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01) 706 | #define CS42L42_SRC_SDIN_FS_SHIFT 0 707 | #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT) 708 | 709 | #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09) 710 | 711 | /* Page 0x28 S/PDIF Registers */ 712 | #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01) 713 | #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02) 714 | #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03) 715 | #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04) 716 | 717 | /* Page 0x29 Serial Port TX Registers */ 718 | #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01) 719 | #define CS42L42_ASP_TX_EN_SHIFT 0 720 | #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02) 721 | #define CS42L42_ASP_TX0_CH2_SHIFT 1 722 | #define CS42L42_ASP_TX0_CH1_SHIFT 0 723 | 724 | #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03) 725 | #define CS42L42_ASP_TX_CH1_AP_SHIFT 7 726 | #define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT) 727 | #define CS42L42_ASP_TX_CH2_AP_SHIFT 6 728 | #define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT) 729 | #define CS42L42_ASP_TX_CH2_RES_SHIFT 2 730 | #define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT) 731 | #define CS42L42_ASP_TX_CH1_RES_SHIFT 0 732 | #define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT) 733 | #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04) 734 | #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05) 735 | #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06) 736 | #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A) 737 | #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B) 738 | 739 | /* Page 0x2A Serial Port RX Registers */ 740 | #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01) 741 | #define CS42L42_ASP_RX0_CH_EN_SHIFT 2 742 | #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT) 743 | #define CS42L42_ASP_RX0_CH1_SHIFT 2 744 | #define CS42L42_ASP_RX0_CH2_SHIFT 3 745 | #define CS42L42_ASP_RX0_CH3_SHIFT 4 746 | #define CS42L42_ASP_RX0_CH4_SHIFT 5 747 | 748 | #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02) 749 | #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03) 750 | #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04) 751 | #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05) 752 | #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06) 753 | #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07) 754 | #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08) 755 | #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09) 756 | #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A) 757 | #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B) 758 | #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C) 759 | #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D) 760 | #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E) 761 | #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F) 762 | #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10) 763 | #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11) 764 | #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12) 765 | #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13) 766 | 767 | #define CS42L42_ASP_RX_CH_AP_SHIFT 6 768 | #define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT) 769 | #define CS42L42_ASP_RX_CH_AP_LOW 0 770 | #define CS42L42_ASP_RX_CH_AP_HI 1 771 | #define CS42L42_ASP_RX_CH_RES_SHIFT 0 772 | #define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT) 773 | #define CS42L42_ASP_RX_CH_RES_32 3 774 | #define CS42L42_ASP_RX_CH_RES_16 1 775 | #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0 776 | #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT) 777 | 778 | /* Page 0x30 ID Registers */ 779 | #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14) 780 | #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14) 781 | 782 | /* Defines for fracturing values spread across multiple registers */ 783 | #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff) 784 | #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8) 785 | #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16) 786 | 787 | #define CS42L42_NUM_SUPPLIES 5 788 | #define CS42L42_BOOT_TIME_US 3000 789 | #define CS42L42_PLL_DIVOUT_TIME_US 800 790 | #define CS42L42_CLOCK_SWITCH_DELAY_US 150 791 | #define CS42L42_PLL_LOCK_POLL_US 250 792 | #define CS42L42_PLL_LOCK_TIMEOUT_US 1250 793 | #define CS42L42_HP_ADC_EN_TIME_US 20000 794 | #define CS42L42_PDN_DONE_POLL_US 1000 795 | #define CS42L42_PDN_DONE_TIMEOUT_US 200000 796 | #define CS42L42_PDN_DONE_TIME_MS 100 797 | #define CS42L42_FILT_DISCHARGE_TIME_MS 46 --------------------------------------------------------------------------------