├── .gitattributes ├── README.md ├── LICENSE.txt ├── rt5677i2c ├── spb.h ├── trace.h ├── rt5677i2c.inf ├── driver.h ├── rt5677i2c.vcxproj ├── spb.c ├── rt5677i2c.c └── rt5677i2c.h ├── rt5677i2c.sln ├── .gitignore └── rt5677i2c Package └── rt5677i2c Package.vcxproj /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # rt5677 2 | Realtek ALC 5677 I2C Codec driver 3 | 4 | Supports: 5 | * Jack Detection (Only detects whether headphones are plugged in. Assumes Headphones have microphone). 6 | * Headphone output 7 | * Sleep/Wake 8 | 9 | Note: 10 | * Intel SST proprietary drivers do NOT have documented interfaces, so this driver will not work with them. 11 | * Using this driver on chromebooks with this audio chip will require using CoolStar SST Audio 12 | 13 | Tested on Google Chromebook Pixel 2 LS (2015) -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | Copyright 2016 CoolStar 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. -------------------------------------------------------------------------------- /rt5677i2c/spb.h: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.h 8 | 9 | Abstract: 10 | 11 | This module contains the touch driver I2C helper definitions. 12 | 13 | Environment: 14 | 15 | Kernel Mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #pragma once 22 | 23 | #include 24 | #include 25 | 26 | #define DEFAULT_SPB_BUFFER_SIZE 64 27 | #define RESHUB_USE_HELPER_ROUTINES 28 | 29 | // 30 | // SPB (I2C) context 31 | // 32 | 33 | typedef struct _SPB_CONTEXT 34 | { 35 | WDFIOTARGET SpbIoTarget; 36 | LARGE_INTEGER I2cResHubId; 37 | WDFMEMORY WriteMemory; 38 | WDFMEMORY ReadMemory; 39 | WDFWAITLOCK SpbLock; 40 | } SPB_CONTEXT; 41 | 42 | NTSTATUS 43 | SpbXferDataSynchronously( 44 | _In_ SPB_CONTEXT* SpbContext, 45 | _In_ PVOID SendData, 46 | _In_ ULONG SendLength, 47 | _In_reads_bytes_(Length) PVOID Data, 48 | _In_ ULONG Length 49 | ); 50 | 51 | VOID 52 | SpbTargetDeinitialize( 53 | IN WDFDEVICE FxDevice, 54 | IN SPB_CONTEXT* SpbContext 55 | ); 56 | 57 | NTSTATUS 58 | SpbTargetInitialize( 59 | IN WDFDEVICE FxDevice, 60 | IN SPB_CONTEXT* SpbContext 61 | ); 62 | 63 | NTSTATUS 64 | SpbWriteDataSynchronously( 65 | IN SPB_CONTEXT* SpbContext, 66 | IN PVOID Data, 67 | IN ULONG Length 68 | ); -------------------------------------------------------------------------------- /rt5677i2c/trace.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #ifndef _TRACE_H_ 4 | #define _TRACE_H_ 5 | 6 | extern "C" 7 | { 8 | // 9 | // Tracing Definitions: 10 | // 11 | // Control GUID: 12 | // {73e3b785-f5fb-423e-94a9-56627fea9053} 13 | // 14 | 15 | #define WPP_CONTROL_GUIDS \ 16 | WPP_DEFINE_CONTROL_GUID( \ 17 | SpbTestToolTraceGuid, \ 18 | (73e3b785,f5fb,423e,94a9,56627fea9053), \ 19 | WPP_DEFINE_BIT(TRACE_FLAG_WDFLOADING) \ 20 | WPP_DEFINE_BIT(TRACE_FLAG_SPBAPI) \ 21 | WPP_DEFINE_BIT(TRACE_FLAG_OTHER) \ 22 | ) 23 | } 24 | 25 | #define WPP_LEVEL_FLAGS_LOGGER(level,flags) WPP_LEVEL_LOGGER(flags) 26 | #define WPP_LEVEL_FLAGS_ENABLED(level, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= level) 27 | 28 | #define Trace CyapaPrint 29 | #define FuncEntry 30 | #define FuncExit 31 | #define WPP_INIT_TRACING 32 | #define WPP_CLEANUP 33 | #define TRACE_FLAG_SPBAPI 0 34 | #define TRACE_FLAG_WDFLOADING 0 35 | 36 | // begin_wpp config 37 | // FUNC FuncEntry{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 38 | // FUNC FuncExit{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 39 | // USEPREFIX(FuncEntry, "%!STDPREFIX! [%!FUNC!] --> entry"); 40 | // USEPREFIX(FuncExit, "%!STDPREFIX! [%!FUNC!] <--"); 41 | // end_wpp 42 | 43 | #endif _TRACE_H_ 44 | -------------------------------------------------------------------------------- /rt5677i2c/rt5677i2c.inf: -------------------------------------------------------------------------------- 1 | ;/*++ 2 | ; 3 | ;Copyright (c) CoolStar. All rights reserved. 4 | ; 5 | ;Module Name: 6 | ; rt5677i2c.inf 7 | ; 8 | ;Abstract: 9 | ; INF file for installing the Realtek ALC 5677 Driver 10 | ; 11 | ; 12 | ;--*/ 13 | 14 | [Version] 15 | Signature = "$WINDOWS NT$" 16 | Class = Media 17 | ClassGuid = {4d36e96c-e325-11ce-bfc1-08002be10318} 18 | Provider = CoolStar 19 | DriverVer = 12/16/2021,1.0.0 20 | CatalogFile = rt5677i2c.cat 21 | PnpLockdown = 1 22 | 23 | [DestinationDirs] 24 | DefaultDestDir = 12 25 | 26 | ; ================= Class section ===================== 27 | 28 | [SourceDisksNames] 29 | 1 = %DiskId1%,,,"" 30 | 31 | [SourceDisksFiles] 32 | rt5677i2c.sys = 1,, 33 | 34 | ;***************************************** 35 | ; Rt5677I2c Install Section 36 | ;***************************************** 37 | 38 | [Manufacturer] 39 | %StdMfg%=Standard,NT$ARCH$ 40 | 41 | ; Decorated model section take precedence over undecorated 42 | ; ones on XP and later. 43 | [Standard.NT$ARCH$] 44 | %Rt5677I2c.DeviceDesc%=Rt5677I2c_Device, ACPI\RT5677CE 45 | 46 | [Rt5677I2c_Device.NT] 47 | CopyFiles=Drivers_Dir 48 | 49 | [Rt5677I2c_Device.NT.HW] 50 | AddReg=Rt5677I2c_AddReg 51 | 52 | [Drivers_Dir] 53 | rt5677i2c.sys 54 | 55 | [Rt5677I2c_AddReg] 56 | ; Set to 1 to connect the first interrupt resource found, 0 to leave disconnected 57 | HKR,Settings,"ConnectInterrupt",0x00010001,0 58 | 59 | ;-------------- Service installation 60 | [Rt5677I2c_Device.NT.Services] 61 | AddService = Rt5677I2c,%SPSVCINST_ASSOCSERVICE%, Rt5677I2c_Service_Inst 62 | 63 | ; -------------- Rt5677I2c driver install sections 64 | [Rt5677I2c_Service_Inst] 65 | DisplayName = %Rt5677I2c.SVCDESC% 66 | ServiceType = 1 ; SERVICE_KERNEL_DRIVER 67 | StartType = 3 ; SERVICE_DEMAND_START 68 | ErrorControl = 1 ; SERVICE_ERROR_NORMAL 69 | ServiceBinary = %12%\rt5677i2c.sys 70 | LoadOrderGroup = Base 71 | 72 | [Strings] 73 | SPSVCINST_ASSOCSERVICE= 0x00000002 74 | StdMfg = "CoolStar" 75 | DiskId1 = "Realtek 5677 Installation Disk #1" 76 | Rt5677I2c.DeviceDesc = "Realtek 5677 I2S Audio" 77 | Rt5677I2c.SVCDESC = "Rt5677I2c Service" 78 | -------------------------------------------------------------------------------- /rt5677i2c/driver.h: -------------------------------------------------------------------------------- 1 | #if !defined(_RTI2S_H_) 2 | #define _RTI2S_H_ 3 | 4 | #pragma warning(disable:4200) // suppress nameless struct/union warning 5 | #pragma warning(disable:4201) // suppress nameless struct/union warning 6 | #pragma warning(disable:4214) // suppress bit field types other than int warning 7 | #include 8 | #include 9 | 10 | #pragma warning(default:4200) 11 | #pragma warning(default:4201) 12 | #pragma warning(default:4214) 13 | #include 14 | 15 | #pragma warning(disable:4201) // suppress nameless struct/union warning 16 | #pragma warning(disable:4214) // suppress bit field types other than int warning 17 | #include 18 | 19 | #include "rt5677i2c.h" 20 | #include "spb.h" 21 | 22 | // 23 | // String definitions 24 | // 25 | 26 | #define DRIVERNAME "rt5677i2c.sys: " 27 | 28 | #define RTI2S_POOL_TAG (ULONG) 'SIRT' 29 | #define RTI2S_HARDWARE_IDS L"CoolStar\\10EC5677\0\0" 30 | #define RTI2S_HARDWARE_IDS_LENGTH sizeof(RTI2S_HARDWARE_IDS) 31 | 32 | #define NTDEVICE_NAME_STRING L"\\Device\\10EC5677" 33 | #define SYMBOLIC_NAME_STRING L"\\DosDevices\\10EC5677" 34 | 35 | #define true 1 36 | #define false 0 37 | 38 | typedef struct _RTI2S_CONTEXT 39 | { 40 | 41 | // 42 | // Handle back to the WDFDEVICE 43 | // 44 | 45 | WDFDEVICE FxDevice; 46 | 47 | WDFQUEUE ReportQueue; 48 | 49 | SPB_CONTEXT I2CContext; 50 | 51 | WDFTIMER Timer; 52 | 53 | BOOLEAN ConnectInterrupt; 54 | 55 | BOOLEAN HeadphonesConnected; 56 | 57 | BOOLEAN HeadsetMicConnected; 58 | 59 | } RTI2S_CONTEXT, *PRTI2S_CONTEXT; 60 | 61 | WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(RTI2S_CONTEXT, GetDeviceContext) 62 | 63 | // 64 | // Function definitions 65 | // 66 | 67 | DRIVER_INITIALIZE DriverEntry; 68 | 69 | EVT_WDF_DRIVER_UNLOAD RtI2SDriverUnload; 70 | 71 | EVT_WDF_DRIVER_DEVICE_ADD RtI2SEvtDeviceAdd; 72 | 73 | EVT_WDFDEVICE_WDM_IRP_PREPROCESS RtI2SEvtWdmPreprocessMnQueryId; 74 | 75 | EVT_WDF_IO_QUEUE_IO_INTERNAL_DEVICE_CONTROL RtI2SEvtInternalDeviceControl; 76 | 77 | // 78 | // Helper macros 79 | // 80 | 81 | #define DEBUG_LEVEL_ERROR 1 82 | #define DEBUG_LEVEL_INFO 2 83 | #define DEBUG_LEVEL_VERBOSE 3 84 | 85 | #define DBG_INIT 1 86 | #define DBG_PNP 2 87 | #define DBG_IOCTL 4 88 | 89 | #if 0 90 | #define RtI2SPrint(dbglevel, dbgcatagory, fmt, ...) { \ 91 | if (RtI2SDebugLevel >= dbglevel && \ 92 | (RtI2SDebugCatagories && dbgcatagory)) \ 93 | { \ 94 | DbgPrint(DRIVERNAME); \ 95 | DbgPrint(fmt, __VA_ARGS__); \ 96 | } \ 97 | } 98 | #else 99 | #define RtI2SPrint(dbglevel, fmt, ...) { \ 100 | } 101 | #endif 102 | #endif -------------------------------------------------------------------------------- /rt5677i2c.sln: -------------------------------------------------------------------------------- 1 | 2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.31829.152 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "rt5677i2c", "rt5677i2c\rt5677i2c.vcxproj", "{B3E71397-9BE4-492B-AAED-4D056E59CB1F}" 7 | EndProject 8 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "rt5677i2c Package", "rt5677i2c Package\rt5677i2c Package.vcxproj", "{EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}" 9 | ProjectSection(ProjectDependencies) = postProject 10 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F} = {B3E71397-9BE4-492B-AAED-4D056E59CB1F} 11 | EndProjectSection 12 | EndProject 13 | Global 14 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 15 | Debug|Win32 = Debug|Win32 16 | Debug|x64 = Debug|x64 17 | Release|Win32 = Release|Win32 18 | Release|x64 = Release|x64 19 | EndGlobalSection 20 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 21 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Debug|Win32.ActiveCfg = Debug|Win32 22 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Debug|Win32.Build.0 = Debug|Win32 23 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Debug|Win32.Deploy.0 = Debug|Win32 24 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Debug|x64.ActiveCfg = Debug|x64 25 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Debug|x64.Build.0 = Debug|x64 26 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Debug|x64.Deploy.0 = Debug|x64 27 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Release|Win32.ActiveCfg = Release|Win32 28 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Release|Win32.Build.0 = Release|Win32 29 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Release|Win32.Deploy.0 = Release|Win32 30 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Release|x64.ActiveCfg = Release|x64 31 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Release|x64.Build.0 = Release|x64 32 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F}.Release|x64.Deploy.0 = Release|x64 33 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Debug|Win32.ActiveCfg = Debug|Win32 34 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Debug|Win32.Build.0 = Debug|Win32 35 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Debug|Win32.Deploy.0 = Debug|Win32 36 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Debug|x64.ActiveCfg = Debug|x64 37 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Debug|x64.Build.0 = Debug|x64 38 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Debug|x64.Deploy.0 = Debug|x64 39 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Release|Win32.ActiveCfg = Release|Win32 40 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Release|Win32.Build.0 = Release|Win32 41 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Release|Win32.Deploy.0 = Release|Win32 42 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Release|x64.ActiveCfg = Release|x64 43 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Release|x64.Build.0 = Release|x64 44 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B}.Release|x64.Deploy.0 = Release|x64 45 | EndGlobalSection 46 | GlobalSection(SolutionProperties) = preSolution 47 | HideSolutionNode = FALSE 48 | EndGlobalSection 49 | GlobalSection(ExtensibilityGlobals) = postSolution 50 | SolutionGuid = {86D249D6-FF1E-41F4-AA9B-3813428D6C1A} 51 | EndGlobalSection 52 | EndGlobal 53 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ## Ignore Visual Studio temporary files, build results, and 2 | ## files generated by popular Visual Studio add-ons. 3 | ## 4 | ## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore 5 | 6 | # User-specific files 7 | *.rsuser 8 | *.suo 9 | *.user 10 | *.userosscache 11 | *.sln.docstates 12 | 13 | # User-specific files (MonoDevelop/Xamarin Studio) 14 | *.userprefs 15 | 16 | # Build results 17 | [Dd]ebug/ 18 | [Dd]ebugPublic/ 19 | [Rr]elease/ 20 | [Rr]eleases/ 21 | x64/ 22 | x86/ 23 | bld/ 24 | [Bb]in/ 25 | [Oo]bj/ 26 | [Ll]og/ 27 | 28 | # Visual Studio 2015/2017 cache/options directory 29 | .vs/ 30 | # Uncomment if you have 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Backup files are not needed, 238 | # because we have git ;-) 239 | _UpgradeReport_Files/ 240 | Backup*/ 241 | UpgradeLog*.XML 242 | UpgradeLog*.htm 243 | ServiceFabricBackup/ 244 | *.rptproj.bak 245 | 246 | # SQL Server files 247 | *.mdf 248 | *.ldf 249 | *.ndf 250 | 251 | # Business Intelligence projects 252 | *.rdl.data 253 | *.bim.layout 254 | *.bim_*.settings 255 | *.rptproj.rsuser 256 | 257 | # Microsoft Fakes 258 | FakesAssemblies/ 259 | 260 | # GhostDoc plugin setting file 261 | *.GhostDoc.xml 262 | 263 | # Node.js Tools for Visual Studio 264 | .ntvs_analysis.dat 265 | node_modules/ 266 | 267 | # Visual Studio 6 build log 268 | *.plg 269 | 270 | # Visual Studio 6 workspace options file 271 | *.opt 272 | 273 | # Visual Studio 6 auto-generated workspace file (contains which files were open etc.) 274 | *.vbw 275 | 276 | # Visual Studio LightSwitch build output 277 | **/*.HTMLClient/GeneratedArtifacts 278 | **/*.DesktopClient/GeneratedArtifacts 279 | **/*.DesktopClient/ModelManifest.xml 280 | **/*.Server/GeneratedArtifacts 281 | **/*.Server/ModelManifest.xml 282 | _Pvt_Extensions 283 | 284 | # Paket dependency manager 285 | .paket/paket.exe 286 | paket-files/ 287 | 288 | # FAKE - F# Make 289 | .fake/ 290 | 291 | # JetBrains Rider 292 | .idea/ 293 | *.sln.iml 294 | 295 | # CodeRush personal settings 296 | .cr/personal 297 | 298 | # Python Tools for Visual Studio (PTVS) 299 | __pycache__/ 300 | *.pyc 301 | 302 | # Cake - Uncomment if you are using it 303 | # tools/** 304 | # !tools/packages.config 305 | 306 | # Tabs Studio 307 | *.tss 308 | 309 | # Telerik's JustMock configuration file 310 | *.jmconfig 311 | 312 | # BizTalk build output 313 | *.btp.cs 314 | *.btm.cs 315 | *.odx.cs 316 | *.xsd.cs 317 | 318 | # OpenCover UI analysis results 319 | OpenCover/ 320 | 321 | # Azure Stream Analytics local run output 322 | ASALocalRun/ 323 | 324 | # MSBuild Binary and Structured Log 325 | *.binlog 326 | 327 | # NVidia Nsight GPU debugger configuration file 328 | *.nvuser 329 | 330 | # MFractors (Xamarin productivity tool) working folder 331 | .mfractor/ 332 | 333 | # Local History for Visual Studio 334 | .localhistory/ 335 | -------------------------------------------------------------------------------- /rt5677i2c/rt5677i2c.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {B3E71397-9BE4-492B-AAED-4D056E59CB1F} 23 | {1bc93793-694f-48fe-9372-81e2b05556fd} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | rt5677i2c 29 | 10.0.22000.0 30 | rt5677i2c 31 | 32 | 33 | 34 | 35 | 36 | true 37 | WindowsKernelModeDriver10.0 38 | Driver 39 | KMDF 40 | 41 | 42 | 43 | 44 | false 45 | WindowsKernelModeDriver10.0 46 | Driver 47 | KMDF 48 | 49 | 50 | 51 | 52 | true 53 | WindowsKernelModeDriver10.0 54 | Driver 55 | KMDF 56 | 57 | 58 | 59 | 60 | false 61 | WindowsKernelModeDriver10.0 62 | Driver 63 | KMDF 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | DbgengKernelDebugger 75 | 76 | 77 | DbgengKernelDebugger 78 | 79 | 80 | DbgengKernelDebugger 81 | 82 | 83 | DbgengKernelDebugger 84 | 85 | 86 | 87 | true 88 | trace.h 89 | true 90 | false 91 | 92 | 93 | 1.0.1 94 | 95 | 96 | SHA256 97 | 98 | 99 | 100 | 101 | true 102 | trace.h 103 | true 104 | false 105 | 106 | 107 | 1.0.1 108 | 109 | 110 | SHA256 111 | 112 | 113 | 114 | 115 | true 116 | trace.h 117 | true 118 | false 119 | 120 | 121 | 1.0.1 122 | 123 | 124 | SHA256 125 | 126 | 127 | 128 | 129 | true 130 | trace.h 131 | true 132 | false 133 | 134 | 135 | 1.0.1 136 | 137 | 138 | SHA256 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | -------------------------------------------------------------------------------- /rt5677i2c Package/rt5677i2c Package.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {EA676041-89D8-4ACF-A48B-F11CA9F5DD8B} 23 | {4605da2c-74a5-4865-98e1-152ef136825f} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | rt5677i2c_Package 29 | 10.0.22000.0 30 | rt5677i2c Package 31 | 32 | 33 | 34 | 35 | 36 | true 37 | WindowsKernelModeDriver10.0 38 | Utility 39 | Package 40 | true 41 | 42 | 43 | 44 | 45 | false 46 | WindowsKernelModeDriver10.0 47 | Utility 48 | Package 49 | true 50 | 51 | 52 | 53 | 54 | true 55 | WindowsKernelModeDriver10.0 56 | Utility 57 | Package 58 | true 59 | 60 | 61 | 62 | 63 | false 64 | WindowsKernelModeDriver10.0 65 | Utility 66 | Package 67 | true 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | DbgengKernelDebugger 79 | False 80 | True 81 | 82 | 83 | 84 | False 85 | False 86 | True 87 | 88 | 133563 89 | 90 | 91 | DbgengKernelDebugger 92 | False 93 | True 94 | 95 | 96 | 97 | False 98 | False 99 | True 100 | 101 | 133563 102 | 103 | 104 | DbgengKernelDebugger 105 | False 106 | True 107 | 108 | 109 | 110 | False 111 | False 112 | True 113 | 114 | 133563 115 | 116 | 117 | DbgengKernelDebugger 118 | False 119 | True 120 | 121 | 122 | 123 | False 124 | False 125 | True 126 | 127 | 133563 128 | 129 | 130 | 131 | SHA256 132 | 133 | 134 | 135 | 136 | SHA256 137 | 138 | 139 | 140 | 141 | SHA256 142 | 143 | 144 | 145 | 146 | SHA256 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | {b3e71397-9be4-492b-aaed-4d056e59cb1f} 155 | 156 | 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /rt5677i2c/spb.c: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.c 8 | 9 | Abstract: 10 | 11 | Contains all I2C-specific functionality 12 | 13 | Environment: 14 | 15 | Kernel mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #include "driver.h" 22 | #include "spb.h" 23 | #include 24 | 25 | static ULONG RtI2SDebugLevel = 100; 26 | static ULONG RtI2SDebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 27 | 28 | NTSTATUS 29 | SpbDoWriteDataSynchronously( 30 | IN SPB_CONTEXT* SpbContext, 31 | IN PVOID Data, 32 | IN ULONG Length 33 | ) 34 | /*++ 35 | 36 | Routine Description: 37 | 38 | This helper routine abstracts creating and sending an I/O 39 | request (I2C Write) to the Spb I/O target. 40 | 41 | Arguments: 42 | 43 | SpbContext - Pointer to the current device context 44 | Address - The I2C register address to write to 45 | Data - A buffer to receive the data at at the above address 46 | Length - The amount of data to be read from the above address 47 | 48 | Return Value: 49 | 50 | NTSTATUS Status indicating success or failure 51 | 52 | --*/ 53 | { 54 | PUCHAR buffer; 55 | ULONG length; 56 | WDFMEMORY memory; 57 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 58 | NTSTATUS status; 59 | 60 | length = Length; 61 | memory = NULL; 62 | 63 | if (length > DEFAULT_SPB_BUFFER_SIZE) 64 | { 65 | status = WdfMemoryCreate( 66 | WDF_NO_OBJECT_ATTRIBUTES, 67 | NonPagedPool, 68 | RTI2S_POOL_TAG, 69 | length, 70 | &memory, 71 | (PVOID*)&buffer); 72 | 73 | if (!NT_SUCCESS(status)) 74 | { 75 | RtI2SPrint( 76 | DEBUG_LEVEL_ERROR, 77 | DBG_IOCTL, 78 | "Error allocating memory for Spb write - %!STATUS!", 79 | status); 80 | goto exit; 81 | } 82 | 83 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 84 | &memoryDescriptor, 85 | memory, 86 | NULL); 87 | } 88 | else 89 | { 90 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->WriteMemory, NULL); 91 | 92 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 93 | &memoryDescriptor, 94 | (PVOID)buffer, 95 | length); 96 | } 97 | 98 | RtlCopyMemory(buffer, Data, length); 99 | 100 | status = WdfIoTargetSendWriteSynchronously( 101 | SpbContext->SpbIoTarget, 102 | NULL, 103 | &memoryDescriptor, 104 | NULL, 105 | NULL, 106 | NULL); 107 | 108 | if (!NT_SUCCESS(status)) 109 | { 110 | RtI2SPrint( 111 | DEBUG_LEVEL_ERROR, 112 | DBG_IOCTL, 113 | "Error writing to Spb - %!STATUS!", 114 | status); 115 | goto exit; 116 | } 117 | 118 | exit: 119 | 120 | if (NULL != memory) 121 | { 122 | WdfObjectDelete(memory); 123 | } 124 | 125 | return status; 126 | } 127 | 128 | NTSTATUS 129 | SpbWriteDataSynchronously( 130 | IN SPB_CONTEXT* SpbContext, 131 | IN PVOID Data, 132 | IN ULONG Length 133 | ) 134 | /*++ 135 | 136 | Routine Description: 137 | 138 | This routine abstracts creating and sending an I/O 139 | request (I2C Write) to the Spb I/O target and utilizes 140 | a helper routine to do work inside of locked code. 141 | 142 | Arguments: 143 | 144 | SpbContext - Pointer to the current device context 145 | Address - The I2C register address to write to 146 | Data - A buffer to receive the data at at the above address 147 | Length - The amount of data to be read from the above address 148 | 149 | Return Value: 150 | 151 | NTSTATUS Status indicating success or failure 152 | 153 | --*/ 154 | { 155 | NTSTATUS status; 156 | 157 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 158 | 159 | status = SpbDoWriteDataSynchronously( 160 | SpbContext, 161 | Data, 162 | Length); 163 | 164 | WdfWaitLockRelease(SpbContext->SpbLock); 165 | 166 | return status; 167 | } 168 | 169 | NTSTATUS 170 | SpbXferDataSynchronously( 171 | _In_ SPB_CONTEXT* SpbContext, 172 | _In_ PVOID SendData, 173 | _In_ ULONG SendLength, 174 | _In_reads_bytes_(Length) PVOID Data, 175 | _In_ ULONG Length 176 | ) 177 | /*++ 178 | Routine Description: 179 | This helper routine abstracts creating and sending an I/O 180 | request (I2C Read) to the Spb I/O target. 181 | Arguments: 182 | SpbContext - Pointer to the current device context 183 | Address - The I2C register address to read from 184 | Data - A buffer to receive the data at at the above address 185 | Length - The amount of data to be read from the above address 186 | Return Value: 187 | NTSTATUS Status indicating success or failure 188 | --*/ 189 | { 190 | PUCHAR buffer; 191 | WDFMEMORY memory; 192 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 193 | NTSTATUS status; 194 | ULONG_PTR bytesRead; 195 | 196 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 197 | 198 | memory = NULL; 199 | status = STATUS_INVALID_PARAMETER; 200 | bytesRead = 0; 201 | 202 | // 203 | // Xfer transactions start by writing an address pointer 204 | // 205 | status = SpbDoWriteDataSynchronously( 206 | SpbContext, 207 | SendData, 208 | SendLength); 209 | 210 | if (!NT_SUCCESS(status)) 211 | { 212 | RtI2SPrint( 213 | DEBUG_LEVEL_ERROR, 214 | DBG_IOCTL, 215 | "Error setting address pointer for Spb read - %!STATUS!", 216 | status); 217 | goto exit; 218 | } 219 | 220 | if (Length > DEFAULT_SPB_BUFFER_SIZE) 221 | { 222 | status = WdfMemoryCreate( 223 | WDF_NO_OBJECT_ATTRIBUTES, 224 | NonPagedPool, 225 | RTI2S_POOL_TAG, 226 | Length, 227 | &memory, 228 | (PVOID*)&buffer); 229 | 230 | if (!NT_SUCCESS(status)) 231 | { 232 | RtI2SPrint( 233 | DEBUG_LEVEL_ERROR, 234 | DBG_IOCTL, 235 | "Error allocating memory for Spb read - %!STATUS!", 236 | status); 237 | goto exit; 238 | } 239 | 240 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 241 | &memoryDescriptor, 242 | memory, 243 | NULL); 244 | } 245 | else 246 | { 247 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->ReadMemory, NULL); 248 | 249 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 250 | &memoryDescriptor, 251 | (PVOID)buffer, 252 | Length); 253 | } 254 | 255 | 256 | status = WdfIoTargetSendReadSynchronously( 257 | SpbContext->SpbIoTarget, 258 | NULL, 259 | &memoryDescriptor, 260 | NULL, 261 | NULL, 262 | &bytesRead); 263 | 264 | if (!NT_SUCCESS(status) || 265 | bytesRead != Length) 266 | { 267 | RtI2SPrint( 268 | DEBUG_LEVEL_ERROR, 269 | DBG_IOCTL, 270 | "Error reading from Spb - %!STATUS!", 271 | status); 272 | goto exit; 273 | } 274 | 275 | // 276 | // Copy back to the caller's buffer 277 | // 278 | RtlCopyMemory(Data, buffer, Length); 279 | 280 | exit: 281 | if (NULL != memory) 282 | { 283 | WdfObjectDelete(memory); 284 | } 285 | 286 | WdfWaitLockRelease(SpbContext->SpbLock); 287 | 288 | return status; 289 | } 290 | 291 | VOID 292 | SpbTargetDeinitialize( 293 | IN WDFDEVICE FxDevice, 294 | IN SPB_CONTEXT* SpbContext 295 | ) 296 | /*++ 297 | 298 | Routine Description: 299 | 300 | This helper routine is used to free any members added to the SPB_CONTEXT, 301 | note the SPB I/O target is parented to the device and will be 302 | closed and free'd when the device is removed. 303 | 304 | Arguments: 305 | 306 | FxDevice - Handle to the framework device object 307 | SpbContext - Pointer to the current device context 308 | 309 | Return Value: 310 | 311 | NTSTATUS Status indicating success or failure 312 | 313 | --*/ 314 | { 315 | UNREFERENCED_PARAMETER(FxDevice); 316 | UNREFERENCED_PARAMETER(SpbContext); 317 | 318 | // 319 | // Free any SPB_CONTEXT allocations here 320 | // 321 | if (SpbContext->SpbLock != NULL) 322 | { 323 | WdfObjectDelete(SpbContext->SpbLock); 324 | } 325 | 326 | if (SpbContext->ReadMemory != NULL) 327 | { 328 | WdfObjectDelete(SpbContext->ReadMemory); 329 | } 330 | 331 | if (SpbContext->WriteMemory != NULL) 332 | { 333 | WdfObjectDelete(SpbContext->WriteMemory); 334 | } 335 | } 336 | 337 | NTSTATUS 338 | SpbTargetInitialize( 339 | IN WDFDEVICE FxDevice, 340 | IN SPB_CONTEXT* SpbContext 341 | ) 342 | /*++ 343 | 344 | Routine Description: 345 | 346 | This helper routine opens the Spb I/O target and 347 | initializes a request object used for the lifetime 348 | of communication between this driver and Spb. 349 | 350 | Arguments: 351 | 352 | FxDevice - Handle to the framework device object 353 | SpbContext - Pointer to the current device context 354 | 355 | Return Value: 356 | 357 | NTSTATUS Status indicating success or failure 358 | 359 | --*/ 360 | { 361 | WDF_OBJECT_ATTRIBUTES objectAttributes; 362 | WDF_IO_TARGET_OPEN_PARAMS openParams; 363 | UNICODE_STRING spbDeviceName; 364 | WCHAR spbDeviceNameBuffer[RESOURCE_HUB_PATH_SIZE]; 365 | NTSTATUS status; 366 | 367 | WDF_OBJECT_ATTRIBUTES_INIT(&objectAttributes); 368 | objectAttributes.ParentObject = FxDevice; 369 | 370 | status = WdfIoTargetCreate( 371 | FxDevice, 372 | &objectAttributes, 373 | &SpbContext->SpbIoTarget); 374 | 375 | if (!NT_SUCCESS(status)) 376 | { 377 | RtI2SPrint( 378 | DEBUG_LEVEL_ERROR, 379 | DBG_IOCTL, 380 | "Error creating IoTarget object - %!STATUS!", 381 | status); 382 | 383 | WdfObjectDelete(SpbContext->SpbIoTarget); 384 | goto exit; 385 | } 386 | 387 | RtlInitEmptyUnicodeString( 388 | &spbDeviceName, 389 | spbDeviceNameBuffer, 390 | sizeof(spbDeviceNameBuffer)); 391 | 392 | status = RESOURCE_HUB_CREATE_PATH_FROM_ID( 393 | &spbDeviceName, 394 | SpbContext->I2cResHubId.LowPart, 395 | SpbContext->I2cResHubId.HighPart); 396 | 397 | if (!NT_SUCCESS(status)) 398 | { 399 | RtI2SPrint( 400 | DEBUG_LEVEL_ERROR, 401 | DBG_IOCTL, 402 | "Error creating Spb resource hub path string - %!STATUS!", 403 | status); 404 | goto exit; 405 | } 406 | 407 | WDF_IO_TARGET_OPEN_PARAMS_INIT_OPEN_BY_NAME( 408 | &openParams, 409 | &spbDeviceName, 410 | (GENERIC_READ | GENERIC_WRITE)); 411 | 412 | openParams.ShareAccess = 0; 413 | openParams.CreateDisposition = FILE_OPEN; 414 | openParams.FileAttributes = FILE_ATTRIBUTE_NORMAL; 415 | 416 | status = WdfIoTargetOpen(SpbContext->SpbIoTarget, &openParams); 417 | 418 | if (!NT_SUCCESS(status)) 419 | { 420 | RtI2SPrint( 421 | DEBUG_LEVEL_ERROR, 422 | DBG_IOCTL, 423 | "Error opening Spb target for communication - %!STATUS!", 424 | status); 425 | goto exit; 426 | } 427 | 428 | // 429 | // Allocate some fixed-size buffers from NonPagedPool for typical 430 | // Spb transaction sizes to avoid pool fragmentation in most cases 431 | // 432 | status = WdfMemoryCreate( 433 | WDF_NO_OBJECT_ATTRIBUTES, 434 | NonPagedPool, 435 | RTI2S_POOL_TAG, 436 | DEFAULT_SPB_BUFFER_SIZE, 437 | &SpbContext->WriteMemory, 438 | NULL); 439 | 440 | if (!NT_SUCCESS(status)) 441 | { 442 | RtI2SPrint( 443 | DEBUG_LEVEL_ERROR, 444 | DBG_IOCTL, 445 | "Error allocating default memory for Spb write - %!STATUS!", 446 | status); 447 | goto exit; 448 | } 449 | 450 | status = WdfMemoryCreate( 451 | WDF_NO_OBJECT_ATTRIBUTES, 452 | NonPagedPool, 453 | RTI2S_POOL_TAG, 454 | DEFAULT_SPB_BUFFER_SIZE, 455 | &SpbContext->ReadMemory, 456 | NULL); 457 | 458 | if (!NT_SUCCESS(status)) 459 | { 460 | RtI2SPrint( 461 | DEBUG_LEVEL_ERROR, 462 | DBG_IOCTL, 463 | "Error allocating default memory for Spb read - %!STATUS!", 464 | status); 465 | goto exit; 466 | } 467 | 468 | // 469 | // Allocate a waitlock to guard access to the default buffers 470 | // 471 | status = WdfWaitLockCreate( 472 | WDF_NO_OBJECT_ATTRIBUTES, 473 | &SpbContext->SpbLock); 474 | 475 | if (!NT_SUCCESS(status)) 476 | { 477 | RtI2SPrint( 478 | DEBUG_LEVEL_ERROR, 479 | DBG_IOCTL, 480 | "Error creating Spb Waitlock - %!STATUS!", 481 | status); 482 | goto exit; 483 | } 484 | 485 | exit: 486 | 487 | if (!NT_SUCCESS(status)) 488 | { 489 | SpbTargetDeinitialize(FxDevice, SpbContext); 490 | } 491 | 492 | return status; 493 | } -------------------------------------------------------------------------------- /rt5677i2c/rt5677i2c.c: -------------------------------------------------------------------------------- 1 | #define DESCRIPTOR_DEF 2 | #include "driver.h" 3 | #include "stdint.h" 4 | 5 | #define bool int 6 | #define MS_IN_US 1000 7 | 8 | static ULONG RtI2SDebugLevel = 100; 9 | static ULONG RtI2SDebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 10 | 11 | NTSTATUS 12 | DriverEntry( 13 | __in PDRIVER_OBJECT DriverObject, 14 | __in PUNICODE_STRING RegistryPath 15 | ) 16 | { 17 | NTSTATUS status = STATUS_SUCCESS; 18 | WDF_DRIVER_CONFIG config; 19 | WDF_OBJECT_ATTRIBUTES attributes; 20 | 21 | RtI2SPrint(DEBUG_LEVEL_INFO, DBG_INIT, 22 | "Driver Entry\n"); 23 | 24 | WDF_DRIVER_CONFIG_INIT(&config, RtI2SEvtDeviceAdd); 25 | 26 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 27 | 28 | // 29 | // Create a framework driver object to represent our driver. 30 | // 31 | 32 | status = WdfDriverCreate(DriverObject, 33 | RegistryPath, 34 | &attributes, 35 | &config, 36 | WDF_NO_HANDLE 37 | ); 38 | 39 | if (!NT_SUCCESS(status)) 40 | { 41 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_INIT, 42 | "WdfDriverCreate failed with status 0x%x\n", status); 43 | } 44 | 45 | return status; 46 | } 47 | 48 | /* RT5677 has 256 8-bit register addresses, and 16-bit register data */ 49 | struct rt5677_init_reg { 50 | uint8_t reg; 51 | uint16_t val; 52 | }; 53 | 54 | #define RT5677_PR_RANGE_BASE (0xff + 1) 55 | #define RT5677_PR_SPACING 0x100 56 | 57 | #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 58 | 59 | static struct rt5677_init_reg init_list[] = { 60 | {RT5677_LOUT1, RT5677_LOUT1_L_DF | RT5677_LOUT2_L_DF | RT5677_LOUT3_L_DF | RT5677_LOUT3_L_MUTE}, 61 | {RT5677_IN1, RT5677_IN_DF1 | RT5677_IN_DF2}, 62 | {RT5677_MICBIAS, RT5677_MICBIAS1_CTRL_VDD_3_3V}, 63 | 64 | {RT5677_SIDETONE_CTRL, 0x000b}, 65 | {RT5677_STO1_ADC_DIG_VOL, 0x7F7F}, 66 | {RT5677_STO2_ADC_MIXER, 0xD4C0}, 67 | {RT5677_STO1_ADC_MIXER, 0x5480}, //0x5480 for internal mic, 0x9440 for external mic 68 | {RT5677_STO1_DAC_MIXER, 0x8A8A}, 69 | {RT5677_MONO_ADC_MIXER, 0x54D1}, 70 | {RT5677_PWR_DIG1, RT5677_PWR_I2S1 | RT5677_PWR_DAC1 | RT5677_PWR_DAC2}, //add RT5677_PWR_DAC1 | RT5677_PWR_DAC2 for headphones, add RT5677_PWR_ADCFED1 | RT5677_PWR_ADC_L for external mic 71 | {RT5677_PWR_DIG2, RT5677_PWR_ADC_S1F | RT5677_PWR_ADC_MF_L | RT5677_PWR_DAC_S1F | RT5677_PWR_PDM1}, //add RT5677_PWR_PDM1 for speaker 72 | {RT5677_PWR_ANLG1, 0xFDD5}, 73 | {RT5677_PWR_ANLG2, 0x2CC0}, //0x2CC0 for internal mic, 0xACE0 for external mic 74 | {RT5677_PWR_DSP2, 0x0C00}, 75 | {RT5677_I2S2_SDP, 0x0000}, 76 | {RT5677_CLK_TREE_CTRL1, 0x1111}, 77 | {RT5677_PLL1_CTRL1, 0x0000}, 78 | {RT5677_PLL1_CTRL2, 0x0000}, 79 | {RT5677_GPIO_CTRL2, 0x0030}, 80 | {RT5677_DIG_MISC, 0x0029}, 81 | {RT5677_GEN_CTRL1, 0x00FF}, 82 | {RT5677_PDM_OUT_CTRL, 0x0088}, //0x8888 for headphones only, 0x0088 for both 83 | {RT5677_DAC1_DIG_VOL, 0x9f9f}, //0x9f9f for headphones, 0xafaf for speakers 84 | {RT5677_DAC2_DIG_VOL, 0xffff}, 85 | {RT5677_STO1_ADC_DIG_VOL, 0x3f3f}, 86 | {RT5677_DMIC_CTRL1, 0x9545}, 87 | {RT5677_ANA_ADC_GAIN_CTRL, 0xa000}, 88 | {RT5677_STO1_2_ADC_BST, 0xa000}, 89 | {RT5677_ADC_BST_CTRL2, 0xa000}, 90 | 91 | {RT5677_TDM1_CTRL1, 0x0300}, //0x0380 for ext mic, 0x0300 for int mic 92 | 93 | {RT5677_ASRC_1, 0x0001}, 94 | {RT5677_ASRC_2, 0x4820}, //0x4020 to for ext mic, 0x4820 for int mic 95 | {RT5677_ASRC_3, 0x1000}, 96 | {RT5677_ASRC_5, 0x1000}, 97 | {RT5677_ASRC_6, 0x7000}, 98 | 99 | {RT5677_VAD_CTRL4, 0x010c}, 100 | 101 | {RT5677_DSP_INB_CTRL1, 0x4000}, 102 | 103 | {RT5677_JD_CTRL1, 0x2c00}, 104 | {RT5677_IRQ_CTRL1, 0x0504}, 105 | 106 | {RT5677_GPIO_CTRL1, 0x8000}, 107 | 108 | {RT5677_ASRC_12, 0x0018}, 109 | 110 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x3d}, 111 | {RT5677_PRIV_DATA, 0x364D}, 112 | 113 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x17}, 114 | {RT5677_PRIV_DATA, 0x4fc0}, 115 | 116 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x13}, 117 | {RT5677_PRIV_DATA, 0x0312}, 118 | 119 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x1e}, 120 | {RT5677_PRIV_DATA, 0x0000}, 121 | 122 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x12}, 123 | {RT5677_PRIV_DATA, 0x0eaa}, 124 | 125 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x14}, 126 | {RT5677_PRIV_DATA, 0x018a}, 127 | 128 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x15}, 129 | {RT5677_PRIV_DATA, 0x0490}, 130 | 131 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x38}, 132 | {RT5677_PRIV_DATA, 0x0f71}, 133 | 134 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + 0x39}, 135 | {RT5677_PRIV_DATA, 0x0f71}, 136 | 137 | //Private register, no doc [rt5677_set_vad_source] 138 | {RT5677_PRIV_INDEX, RT5677_PR_BASE + RT5677_BIAS_CUR4}, 139 | {RT5677_PRIV_DATA, 0x0f8a}, 140 | }; 141 | 142 | NTSTATUS rt5677_reg_read( 143 | _In_ PRTI2S_CONTEXT pDevice, 144 | uint8_t reg, 145 | uint16_t* data 146 | ) { 147 | uint16_t raw_data = 0; 148 | NTSTATUS status = SpbXferDataSynchronously(&pDevice->I2CContext, ®, sizeof(uint8_t), &raw_data, sizeof(uint16_t)); 149 | *data = raw_data; 150 | return status; 151 | } 152 | 153 | NTSTATUS rt5677_reg_write( 154 | _In_ PRTI2S_CONTEXT pDevice, 155 | uint8_t reg, 156 | uint16_t data 157 | ) { 158 | uint8_t buf[3]; 159 | buf[0] = reg; 160 | buf[1] = (data >> 8); 161 | buf[2] = data & 0xFF; 162 | return SpbWriteDataSynchronously(&pDevice->I2CContext, buf, sizeof(buf)); 163 | } 164 | 165 | NTSTATUS rt5677_reg_update( 166 | _In_ PRTI2S_CONTEXT pDevice, 167 | uint8_t reg, 168 | uint16_t mask, 169 | uint16_t val 170 | ) { 171 | uint16_t tmp = 0, orig = 0; 172 | 173 | NTSTATUS status = rt5677_reg_read(pDevice, reg, &orig); 174 | if (!NT_SUCCESS(status)) { 175 | return status; 176 | } 177 | 178 | tmp = orig & ~mask; 179 | tmp |= val & mask; 180 | 181 | if (tmp != orig) { 182 | uint8_t buf[3]; 183 | buf[0] = reg; 184 | buf[1] = (tmp >> 8); 185 | buf[2] = tmp & 0xFF; 186 | status = SpbWriteDataSynchronously(&pDevice->I2CContext, buf, sizeof(buf)); 187 | } 188 | return status; 189 | } 190 | 191 | NTSTATUS rt5677_reset(PRTI2S_CONTEXT pDevice) { 192 | NTSTATUS status = rt5677_reg_write(pDevice, RT5677_RESET, RT5677_SW_RESET); 193 | if (!NT_SUCCESS(status)) { 194 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 195 | "Error resetting codec!\n"); 196 | return status; 197 | } 198 | return status; 199 | } 200 | 201 | /*static void debug_dump_5677_regs(PRTI2S_CONTEXT pDevice) 202 | { 203 | uint16_t i, reg_word; 204 | // Show all 16-bit codec regs 205 | for (i = 0; i < RT5677_REG_CNT; i += 8) { 206 | uint32_t regs[8]; 207 | for (int j = 0; j < 8; j++) { 208 | rt5677_reg_read(pDevice, (uint8_t)(i + j), ®_word); 209 | regs[j] = reg_word; 210 | } 211 | DbgPrint("%02x: %04x %04x %04x %04x %04x %04x %04x %04x \n", i, regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7]); 212 | } 213 | }*/ 214 | 215 | VOID 216 | RtI2SBootWorkItem( 217 | IN WDFWORKITEM WorkItem 218 | ) 219 | { 220 | WDFDEVICE Device = (WDFDEVICE)WdfWorkItemGetParentObject(WorkItem); 221 | PRTI2S_CONTEXT pDevice = GetDeviceContext(Device); 222 | 223 | pDevice->ConnectInterrupt = true; 224 | 225 | uint16_t id, reg; 226 | 227 | if (!NT_SUCCESS(rt5677_reg_read(pDevice, RT5677_VENDOR_ID1, &id))) { 228 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 229 | "Error reading vendor ID!\n"); 230 | goto end; 231 | } 232 | RtI2SPrint(DEBUG_LEVEL_INFO, DBG_PNP, 233 | "Hardware ID: 0x%x\n", id); 234 | 235 | if (!NT_SUCCESS(rt5677_reg_read(pDevice, RT5677_VENDOR_ID2, ®))) { 236 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 237 | "Error reading vendor rev!\n"); 238 | goto end; 239 | } 240 | RtI2SPrint(DEBUG_LEVEL_INFO, DBG_PNP, 241 | "Hardware revision: 0x%x\n", reg); 242 | 243 | /* Initialize codec regs with static base/values */ 244 | for (int i = 0; i < ARRAYSIZE(init_list); i++) { 245 | rt5677_reg_write(pDevice, init_list[i].reg, init_list[i].val); 246 | } 247 | 248 | //16 bits per sample 249 | if (!NT_SUCCESS(rt5677_reg_update(pDevice, RT5677_I2S1_SDP, RT5677_I2S_DL_MASK, 0))) { 250 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 251 | "Error updating I2S1 interface Ctrl reg!\n"); 252 | goto end; 253 | } 254 | 255 | NTSTATUS status; 256 | /* Set format here: Assumes I2S, NB_NF, CBS_CFS */ 257 | 258 | /* CBS_CFS (Codec Bit Slave/Codec Frame Slave) */ 259 | status = rt5677_reg_update(pDevice, RT5677_I2S1_SDP, RT5677_I2S_MS_MASK, 260 | RT5677_I2S_MS_S); 261 | if (!NT_SUCCESS(status)) { 262 | goto end; 263 | } 264 | 265 | /* NB_NF (Normal Bit/Normal Frame) */ 266 | status = rt5677_reg_update(pDevice, RT5677_I2S1_SDP, RT5677_I2S_BP_MASK, 267 | RT5677_I2S_BP_NOR); 268 | if (!NT_SUCCESS(status)) { 269 | goto end; 270 | } 271 | 272 | /* I2S mode */ 273 | status = rt5677_reg_update(pDevice, RT5677_I2S1_SDP, RT5677_I2S_DF_MASK, 274 | RT5677_I2S_DF_I2S); 275 | if (!NT_SUCCESS(status)) { 276 | goto end; 277 | } 278 | 279 | /* NB_NF (Normal Bit/Normal Frame) */ 280 | status = rt5677_reg_update(pDevice, RT5677_I2S2_SDP, RT5677_I2S_BP_MASK, 281 | RT5677_I2S_BP_NOR); 282 | if (!NT_SUCCESS(status)) { 283 | goto end; 284 | } 285 | 286 | /* I2S mode */ 287 | status = rt5677_reg_update(pDevice, RT5677_I2S2_SDP, RT5677_I2S_DF_MASK, 288 | RT5677_I2S_DF_I2S); 289 | if (!NT_SUCCESS(status)) { 290 | goto end; 291 | } 292 | 293 | /* Master Select */ 294 | status = rt5677_reg_update(pDevice, RT5677_I2S2_SDP, RT5677_I2S_MS_MASK, 295 | RT5677_I2S_MS_S); 296 | if (!NT_SUCCESS(status)) { 297 | goto end; 298 | } 299 | 300 | //Set GPIO pull states 301 | int gpios[] = {RT5677_GPIO5, RT5677_GPIO6 }; 302 | for (int i = 0; i < sizeof(gpios) / sizeof(int); i++) { 303 | int offset = gpios[i]; 304 | int value = 2; //Pull up 305 | 306 | status = rt5677_reg_write(pDevice, RT5677_PRIV_INDEX, RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3); 307 | if (!NT_SUCCESS(status)) { 308 | continue; 309 | } 310 | 311 | int shift = 2 * (9 - offset); 312 | status = rt5677_reg_update(pDevice, RT5677_PRIV_DATA, 0x3 << shift, (value & 0x3) << shift); 313 | if (!NT_SUCCESS(status)) { 314 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 315 | "Failed to set pullup state for %d\n", offset); 316 | } 317 | } 318 | 319 | status = rt5677_reg_update(pDevice, RT5677_GPIO_CTRL2, 320 | 0x1 << (RT5677_GPIO5 * 3 + 2), 0x0); 321 | if (!NT_SUCCESS(status)) { 322 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 323 | "Failed to set gpio in for %d\n", RT5677_GPIO5); 324 | } 325 | 326 | status = rt5677_reg_update(pDevice, RT5677_GPIO_CTRL3, 327 | RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); 328 | if (!NT_SUCCESS(status)) { 329 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 330 | "Failed to set gpio in for %d\n", RT5677_GPIO6); 331 | } 332 | 333 | /*debug_dump_5677_regs(pDevice); 334 | 335 | DbgPrint("Dumped Registers!\n");*/ 336 | end: 337 | WdfObjectDelete(WorkItem); 338 | } 339 | 340 | void RtI2SBootTimer(_In_ WDFTIMER hTimer) { 341 | WDFDEVICE Device = (WDFDEVICE)WdfTimerGetParentObject(hTimer); 342 | PRTI2S_CONTEXT pDevice = GetDeviceContext(Device); 343 | 344 | WDF_OBJECT_ATTRIBUTES attributes; 345 | WDF_WORKITEM_CONFIG workitemConfig; 346 | WDFWORKITEM hWorkItem; 347 | 348 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 349 | WDF_OBJECT_ATTRIBUTES_SET_CONTEXT_TYPE(&attributes, RTI2S_CONTEXT); 350 | attributes.ParentObject = Device; 351 | WDF_WORKITEM_CONFIG_INIT(&workitemConfig, RtI2SBootWorkItem); 352 | 353 | WdfWorkItemCreate(&workitemConfig, 354 | &attributes, 355 | &hWorkItem); 356 | 357 | WdfWorkItemEnqueue(hWorkItem); 358 | WdfTimerStop(hTimer, FALSE); 359 | } 360 | 361 | NTSTATUS BOOTCODEC( 362 | _In_ PRTI2S_CONTEXT pDevice 363 | ) 364 | { 365 | NTSTATUS status = 0; 366 | 367 | pDevice->ConnectInterrupt = false; 368 | 369 | pDevice->HeadphonesConnected = false; 370 | 371 | uint16_t reg; 372 | RtI2SPrint(DEBUG_LEVEL_INFO, DBG_PNP, 373 | "Initializing ALC5677!\n"); 374 | 375 | /* Read status reg */ 376 | rt5677_reg_read(pDevice, RT5677_RESET, ®); 377 | RtI2SPrint(DEBUG_LEVEL_INFO, DBG_PNP, 378 | "%s: reg 00h, Software Reset & Status = 0x%X\n", __func__, 379 | reg); 380 | 381 | status = rt5677_reset(pDevice); 382 | if (!NT_SUCCESS(status)) { 383 | return status; 384 | } 385 | 386 | WDF_TIMER_CONFIG timerConfig; 387 | WDFTIMER hTimer; 388 | WDF_OBJECT_ATTRIBUTES attributes; 389 | 390 | WDF_TIMER_CONFIG_INIT(&timerConfig, RtI2SBootTimer); 391 | 392 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 393 | attributes.ParentObject = pDevice->FxDevice; 394 | status = WdfTimerCreate(&timerConfig, &attributes, &hTimer); 395 | 396 | WdfTimerStart(hTimer, WDF_REL_TIMEOUT_IN_MS(20)); 397 | 398 | return status; 399 | } 400 | 401 | NTSTATUS 402 | OnPrepareHardware( 403 | _In_ WDFDEVICE FxDevice, 404 | _In_ WDFCMRESLIST FxResourcesRaw, 405 | _In_ WDFCMRESLIST FxResourcesTranslated 406 | ) 407 | /*++ 408 | 409 | Routine Description: 410 | 411 | This routine caches the SPB resource connection ID. 412 | 413 | Arguments: 414 | 415 | FxDevice - a handle to the framework device object 416 | FxResourcesRaw - list of translated hardware resources that 417 | the PnP manager has assigned to the device 418 | FxResourcesTranslated - list of raw hardware resources that 419 | the PnP manager has assigned to the device 420 | 421 | Return Value: 422 | 423 | Status 424 | 425 | --*/ 426 | { 427 | PRTI2S_CONTEXT pDevice = GetDeviceContext(FxDevice); 428 | BOOLEAN fSpbResourceFound = FALSE; 429 | BOOLEAN fJackDetectResourceFound = FALSE; 430 | NTSTATUS status = STATUS_INSUFFICIENT_RESOURCES; 431 | 432 | UNREFERENCED_PARAMETER(FxResourcesRaw); 433 | 434 | // 435 | // Parse the peripheral's resources. 436 | // 437 | 438 | ULONG resourceCount = WdfCmResourceListGetCount(FxResourcesTranslated); 439 | 440 | for (ULONG i = 0; i < resourceCount; i++) 441 | { 442 | PCM_PARTIAL_RESOURCE_DESCRIPTOR pDescriptor; 443 | UCHAR Class; 444 | UCHAR Type; 445 | 446 | pDescriptor = WdfCmResourceListGetDescriptor( 447 | FxResourcesTranslated, i); 448 | 449 | switch (pDescriptor->Type) 450 | { 451 | case CmResourceTypeConnection: 452 | // 453 | // Look for I2C or SPI resource and save connection ID. 454 | // 455 | Class = pDescriptor->u.Connection.Class; 456 | Type = pDescriptor->u.Connection.Type; 457 | if (Class == CM_RESOURCE_CONNECTION_CLASS_SERIAL && 458 | Type == CM_RESOURCE_CONNECTION_TYPE_SERIAL_I2C) 459 | { 460 | if (fSpbResourceFound == FALSE) 461 | { 462 | status = STATUS_SUCCESS; 463 | pDevice->I2CContext.I2cResHubId.LowPart = pDescriptor->u.Connection.IdLowPart; 464 | pDevice->I2CContext.I2cResHubId.HighPart = pDescriptor->u.Connection.IdHighPart; 465 | fSpbResourceFound = TRUE; 466 | } 467 | else 468 | { 469 | } 470 | } 471 | break; 472 | default: 473 | // 474 | // Ignoring all other resource types. 475 | // 476 | break; 477 | } 478 | } 479 | 480 | // 481 | // An SPB resource is required. 482 | // 483 | 484 | if (fSpbResourceFound == FALSE) 485 | { 486 | status = STATUS_NOT_FOUND; 487 | return status; 488 | } 489 | 490 | status = SpbTargetInitialize(FxDevice, &pDevice->I2CContext); 491 | if (!NT_SUCCESS(status)) 492 | { 493 | return status; 494 | } 495 | 496 | return status; 497 | } 498 | 499 | NTSTATUS 500 | OnReleaseHardware( 501 | _In_ WDFDEVICE FxDevice, 502 | _In_ WDFCMRESLIST FxResourcesTranslated 503 | ) 504 | /*++ 505 | 506 | Routine Description: 507 | 508 | Arguments: 509 | 510 | FxDevice - a handle to the framework device object 511 | FxResourcesTranslated - list of raw hardware resources that 512 | the PnP manager has assigned to the device 513 | 514 | Return Value: 515 | 516 | Status 517 | 518 | --*/ 519 | { 520 | PRTI2S_CONTEXT pDevice = GetDeviceContext(FxDevice); 521 | NTSTATUS status = STATUS_SUCCESS; 522 | 523 | UNREFERENCED_PARAMETER(FxResourcesTranslated); 524 | 525 | SpbTargetDeinitialize(FxDevice, &pDevice->I2CContext); 526 | 527 | return status; 528 | } 529 | 530 | NTSTATUS 531 | OnD0Entry( 532 | _In_ WDFDEVICE FxDevice, 533 | _In_ WDF_POWER_DEVICE_STATE FxPreviousState 534 | ) 535 | /*++ 536 | 537 | Routine Description: 538 | 539 | This routine allocates objects needed by the driver. 540 | 541 | Arguments: 542 | 543 | FxDevice - a handle to the framework device object 544 | FxPreviousState - previous power state 545 | 546 | Return Value: 547 | 548 | Status 549 | 550 | --*/ 551 | { 552 | UNREFERENCED_PARAMETER(FxPreviousState); 553 | 554 | PRTI2S_CONTEXT pDevice = GetDeviceContext(FxDevice); 555 | NTSTATUS status = STATUS_SUCCESS; 556 | 557 | WdfTimerStart(pDevice->Timer, WDF_REL_TIMEOUT_IN_MS(10)); 558 | 559 | BOOTCODEC(pDevice); 560 | 561 | return status; 562 | } 563 | 564 | NTSTATUS 565 | OnD0Exit( 566 | _In_ WDFDEVICE FxDevice, 567 | _In_ WDF_POWER_DEVICE_STATE FxPreviousState 568 | ) 569 | /*++ 570 | 571 | Routine Description: 572 | 573 | This routine destroys objects needed by the driver. 574 | 575 | Arguments: 576 | 577 | FxDevice - a handle to the framework device object 578 | FxPreviousState - previous power state 579 | 580 | Return Value: 581 | 582 | Status 583 | 584 | --*/ 585 | { 586 | UNREFERENCED_PARAMETER(FxPreviousState); 587 | 588 | PRTI2S_CONTEXT pDevice = GetDeviceContext(FxDevice); 589 | 590 | WdfTimerStop(pDevice->Timer, TRUE); 591 | 592 | pDevice->ConnectInterrupt = false; 593 | 594 | return STATUS_SUCCESS; 595 | } 596 | 597 | VOID 598 | CodecJackSwitchWorkItem( 599 | IN WDFWORKITEM WorkItem 600 | ) 601 | { 602 | WDFDEVICE Device = (WDFDEVICE)WdfWorkItemGetParentObject(WorkItem); 603 | PRTI2S_CONTEXT pDevice = GetDeviceContext(Device); 604 | 605 | uint16_t value; 606 | NTSTATUS status = rt5677_reg_read(pDevice, RT5677_GPIO_ST, &value); 607 | if (NT_SUCCESS(status)) { 608 | value = value >> 8; 609 | 610 | BOOLEAN isJDet = (value & (1 << 4)) != 0; 611 | if (isJDet != pDevice->HeadphonesConnected) { 612 | pDevice->HeadphonesConnected = isJDet; 613 | pDevice->HeadsetMicConnected = pDevice->HeadphonesConnected; 614 | 615 | uint16_t dig1 = RT5677_PWR_I2S1; 616 | if (pDevice->HeadphonesConnected) { 617 | dig1 |= RT5677_PWR_DAC1 | RT5677_PWR_DAC2; 618 | } 619 | if (pDevice->HeadsetMicConnected) { 620 | dig1 |= RT5677_PWR_ADCFED1 | RT5677_PWR_ADC_L; 621 | } 622 | 623 | if (pDevice->HeadphonesConnected) { 624 | rt5677_reg_write(pDevice, RT5677_PWR_DIG2, RT5677_PWR_ADC_S1F | RT5677_PWR_ADC_MF_L | RT5677_PWR_DAC_S1F); 625 | } 626 | else { 627 | rt5677_reg_write(pDevice, RT5677_PWR_DIG2, RT5677_PWR_ADC_S1F | RT5677_PWR_ADC_MF_L | RT5677_PWR_DAC_S1F | RT5677_PWR_PDM1); 628 | } 629 | 630 | if (pDevice->HeadsetMicConnected) { 631 | static struct rt5677_init_reg update_list[] = { 632 | { RT5677_STO1_ADC_MIXER, 0x9440 }, //0x5480 for internal mic, 0x9440 for external mic 633 | { RT5677_PWR_ANLG2, 0xACE0 }, //0x2CC0 for internal mic, 0xACE0 for external mic 634 | { RT5677_TDM1_CTRL1, 0x0380 }, //0x0380 for ext mic, 0x0300 for int mic 635 | { RT5677_ASRC_2, 0x4020 } //0x4020 to for ext mic, 0x4820 for int mic 636 | }; 637 | for (int i = 0; i < ARRAYSIZE(update_list); i++) { 638 | rt5677_reg_write(pDevice, update_list[i].reg, update_list[i].val); 639 | } 640 | 641 | } 642 | else { 643 | static struct rt5677_init_reg update_list[] = { 644 | { RT5677_STO1_ADC_MIXER, 0x5480 }, //0x5480 for internal mic, 0x9440 for external mic 645 | { RT5677_PWR_ANLG2, 0x2CC0 }, //0x2CC0 for internal mic, 0xACE0 for external mic 646 | { RT5677_TDM1_CTRL1, 0x0300 }, //0x0380 for ext mic, 0x0300 for int mic 647 | { RT5677_ASRC_2, 0x4820 } //0x4020 to for ext mic, 0x4820 for int mic 648 | }; 649 | for (int i = 0; i < ARRAYSIZE(update_list); i++) { 650 | rt5677_reg_write(pDevice, update_list[i].reg, update_list[i].val); 651 | } 652 | } 653 | 654 | rt5677_reg_write(pDevice, RT5677_PWR_DIG1, dig1); 655 | } 656 | } 657 | 658 | WdfObjectDelete(WorkItem); 659 | } 660 | 661 | void RtI2SJDetTimer(_In_ WDFTIMER hTimer) { 662 | WDFDEVICE Device = (WDFDEVICE)WdfTimerGetParentObject(hTimer); 663 | PRTI2S_CONTEXT pDevice = GetDeviceContext(Device); 664 | 665 | if (!pDevice->ConnectInterrupt) 666 | return; 667 | 668 | WDF_OBJECT_ATTRIBUTES attributes; 669 | WDF_WORKITEM_CONFIG workitemConfig; 670 | WDFWORKITEM hWorkItem; 671 | 672 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 673 | WDF_OBJECT_ATTRIBUTES_SET_CONTEXT_TYPE(&attributes, RTI2S_CONTEXT); 674 | attributes.ParentObject = Device; 675 | WDF_WORKITEM_CONFIG_INIT(&workitemConfig, CodecJackSwitchWorkItem); 676 | 677 | WdfWorkItemCreate(&workitemConfig, 678 | &attributes, 679 | &hWorkItem); 680 | 681 | WdfWorkItemEnqueue(hWorkItem); 682 | } 683 | 684 | NTSTATUS 685 | RtI2SEvtDeviceAdd( 686 | IN WDFDRIVER Driver, 687 | IN PWDFDEVICE_INIT DeviceInit 688 | ) 689 | { 690 | NTSTATUS status = STATUS_SUCCESS; 691 | WDF_IO_QUEUE_CONFIG queueConfig; 692 | WDF_OBJECT_ATTRIBUTES attributes; 693 | WDFDEVICE device; 694 | WDF_INTERRUPT_CONFIG interruptConfig; 695 | WDFQUEUE queue; 696 | UCHAR minorFunction; 697 | PRTI2S_CONTEXT devContext; 698 | 699 | UNREFERENCED_PARAMETER(Driver); 700 | 701 | PAGED_CODE(); 702 | 703 | RtI2SPrint(DEBUG_LEVEL_INFO, DBG_PNP, 704 | "RtI2SEvtDeviceAdd called\n"); 705 | 706 | { 707 | WDF_PNPPOWER_EVENT_CALLBACKS pnpCallbacks; 708 | WDF_PNPPOWER_EVENT_CALLBACKS_INIT(&pnpCallbacks); 709 | 710 | pnpCallbacks.EvtDevicePrepareHardware = OnPrepareHardware; 711 | pnpCallbacks.EvtDeviceReleaseHardware = OnReleaseHardware; 712 | pnpCallbacks.EvtDeviceD0Entry = OnD0Entry; 713 | pnpCallbacks.EvtDeviceD0Exit = OnD0Exit; 714 | 715 | WdfDeviceInitSetPnpPowerEventCallbacks(DeviceInit, &pnpCallbacks); 716 | } 717 | 718 | // 719 | // Because we are a virtual device the root enumerator would just put null values 720 | // in response to IRP_MN_QUERY_ID. Lets override that. 721 | // 722 | 723 | minorFunction = IRP_MN_QUERY_ID; 724 | 725 | status = WdfDeviceInitAssignWdmIrpPreprocessCallback( 726 | DeviceInit, 727 | RtI2SEvtWdmPreprocessMnQueryId, 728 | IRP_MJ_PNP, 729 | &minorFunction, 730 | 1 731 | ); 732 | if (!NT_SUCCESS(status)) 733 | { 734 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 735 | "WdfDeviceInitAssignWdmIrpPreprocessCallback failed Status 0x%x\n", status); 736 | 737 | return status; 738 | } 739 | 740 | // 741 | // Setup the device context 742 | // 743 | 744 | WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, RTI2S_CONTEXT); 745 | 746 | // 747 | // Create a framework device object.This call will in turn create 748 | // a WDM device object, attach to the lower stack, and set the 749 | // appropriate flags and attributes. 750 | // 751 | 752 | status = WdfDeviceCreate(&DeviceInit, &attributes, &device); 753 | 754 | if (!NT_SUCCESS(status)) 755 | { 756 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 757 | "WdfDeviceCreate failed with status code 0x%x\n", status); 758 | 759 | return status; 760 | } 761 | 762 | WDF_IO_QUEUE_CONFIG_INIT_DEFAULT_QUEUE(&queueConfig, WdfIoQueueDispatchParallel); 763 | 764 | queueConfig.EvtIoInternalDeviceControl = RtI2SEvtInternalDeviceControl; 765 | 766 | status = WdfIoQueueCreate(device, 767 | &queueConfig, 768 | WDF_NO_OBJECT_ATTRIBUTES, 769 | &queue 770 | ); 771 | 772 | if (!NT_SUCCESS(status)) 773 | { 774 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 775 | "WdfIoQueueCreate failed 0x%x\n", status); 776 | 777 | return status; 778 | } 779 | 780 | // 781 | // Create manual I/O queue to take care of hid report read requests 782 | // 783 | 784 | devContext = GetDeviceContext(device); 785 | 786 | WDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchManual); 787 | 788 | queueConfig.PowerManaged = WdfFalse; 789 | 790 | status = WdfIoQueueCreate(device, 791 | &queueConfig, 792 | WDF_NO_OBJECT_ATTRIBUTES, 793 | &devContext->ReportQueue 794 | ); 795 | 796 | if (!NT_SUCCESS(status)) 797 | { 798 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 799 | "WdfIoQueueCreate failed 0x%x\n", status); 800 | 801 | return status; 802 | } 803 | 804 | WDF_TIMER_CONFIG timerConfig; 805 | WDFTIMER hTimer; 806 | 807 | WDF_TIMER_CONFIG_INIT_PERIODIC(&timerConfig, RtI2SJDetTimer, 10); 808 | 809 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 810 | attributes.ParentObject = device; 811 | status = WdfTimerCreate(&timerConfig, &attributes, &hTimer); 812 | devContext->Timer = hTimer; 813 | if (!NT_SUCCESS(status)) 814 | { 815 | RtI2SPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "(%!FUNC!) WdfTimerCreate failed status:%!STATUS!\n", status); 816 | return status; 817 | } 818 | 819 | devContext->FxDevice = device; 820 | 821 | return status; 822 | } 823 | 824 | NTSTATUS 825 | RtI2SEvtWdmPreprocessMnQueryId( 826 | WDFDEVICE Device, 827 | PIRP Irp 828 | ) 829 | { 830 | NTSTATUS status; 831 | PIO_STACK_LOCATION IrpStack, previousSp; 832 | PDEVICE_OBJECT DeviceObject; 833 | PWCHAR buffer; 834 | 835 | PAGED_CODE(); 836 | 837 | // 838 | // Get a pointer to the current location in the Irp 839 | // 840 | 841 | IrpStack = IoGetCurrentIrpStackLocation(Irp); 842 | 843 | // 844 | // Get the device object 845 | // 846 | DeviceObject = WdfDeviceWdmGetDeviceObject(Device); 847 | 848 | 849 | RtI2SPrint(DEBUG_LEVEL_VERBOSE, DBG_PNP, 850 | "RtI2SEvtWdmPreprocessMnQueryId Entry\n"); 851 | 852 | // 853 | // This check is required to filter out QUERY_IDs forwarded 854 | // by the HIDCLASS for the parent FDO. These IDs are sent 855 | // by PNP manager for the parent FDO if you root-enumerate this driver. 856 | // 857 | previousSp = ((PIO_STACK_LOCATION)((UCHAR *)(IrpStack)+ 858 | sizeof(IO_STACK_LOCATION))); 859 | 860 | if (previousSp->DeviceObject == DeviceObject) 861 | { 862 | // 863 | // Filtering out this basically prevents the Found New Hardware 864 | // popup for the root-enumerated RtI2S on reboot. 865 | // 866 | status = Irp->IoStatus.Status; 867 | } 868 | else 869 | { 870 | switch (IrpStack->Parameters.QueryId.IdType) 871 | { 872 | case BusQueryDeviceID: 873 | case BusQueryHardwareIDs: 874 | // 875 | // HIDClass is asking for child deviceid & hardwareids. 876 | // Let us just make up some id for our child device. 877 | // 878 | buffer = (PWCHAR)ExAllocatePoolWithTag( 879 | NonPagedPool, 880 | RTI2S_HARDWARE_IDS_LENGTH, 881 | RTI2S_POOL_TAG 882 | ); 883 | 884 | if (buffer) 885 | { 886 | // 887 | // Do the copy, store the buffer in the Irp 888 | // 889 | RtlCopyMemory(buffer, 890 | RTI2S_HARDWARE_IDS, 891 | RTI2S_HARDWARE_IDS_LENGTH 892 | ); 893 | 894 | Irp->IoStatus.Information = (ULONG_PTR)buffer; 895 | status = STATUS_SUCCESS; 896 | } 897 | else 898 | { 899 | // 900 | // No memory 901 | // 902 | status = STATUS_INSUFFICIENT_RESOURCES; 903 | } 904 | 905 | Irp->IoStatus.Status = status; 906 | // 907 | // We don't need to forward this to our bus. This query 908 | // is for our child so we should complete it right here. 909 | // fallthru. 910 | // 911 | IoCompleteRequest(Irp, IO_NO_INCREMENT); 912 | 913 | break; 914 | 915 | default: 916 | status = Irp->IoStatus.Status; 917 | IoCompleteRequest(Irp, IO_NO_INCREMENT); 918 | break; 919 | } 920 | } 921 | 922 | RtI2SPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 923 | "RtI2SEvtWdmPreprocessMnQueryId Exit = 0x%x\n", status); 924 | 925 | return status; 926 | } 927 | 928 | VOID 929 | RtI2SEvtInternalDeviceControl( 930 | IN WDFQUEUE Queue, 931 | IN WDFREQUEST Request, 932 | IN size_t OutputBufferLength, 933 | IN size_t InputBufferLength, 934 | IN ULONG IoControlCode 935 | ) 936 | { 937 | NTSTATUS status = STATUS_SUCCESS; 938 | WDFDEVICE device; 939 | PRTI2S_CONTEXT devContext; 940 | 941 | UNREFERENCED_PARAMETER(OutputBufferLength); 942 | UNREFERENCED_PARAMETER(InputBufferLength); 943 | 944 | device = WdfIoQueueGetDevice(Queue); 945 | devContext = GetDeviceContext(device); 946 | 947 | switch (IoControlCode) 948 | { 949 | default: 950 | status = STATUS_NOT_SUPPORTED; 951 | break; 952 | } 953 | 954 | WdfRequestComplete(Request, status); 955 | 956 | return; 957 | } 958 | -------------------------------------------------------------------------------- /rt5677i2c/rt5677i2c.h: -------------------------------------------------------------------------------- 1 | #ifndef __DRIVERS_SOUND_RT5677_H__ 2 | #define __DRIVERS_SOUND_RT5677_H__ 3 | 4 | /* 5 | * RT5677 Registers Definition 6 | */ 7 | /* Info */ 8 | #define RT5677_RESET 0x00 9 | #define RT5677_VENDOR_ID 0xfd 10 | #define RT5677_VENDOR_ID1 0xfe 11 | #define RT5677_VENDOR_ID2 0xff 12 | 13 | #define RT5677_REG_CNT (RT5677_VENDOR_ID2 + 1) 14 | #define RT5677_PR_REG_CNT 255 15 | 16 | /* I/O - Output */ 17 | #define RT5677_LOUT1 0x01 18 | /* I/O - Input */ 19 | #define RT5677_IN1 0x03 20 | #define RT5677_MICBIAS 0x04 21 | /* I/O - SLIMBus */ 22 | #define RT5677_SLIMBUS_PARAM 0x07 23 | #define RT5677_SLIMBUS_RX 0x08 24 | #define RT5677_SLIMBUS_CTRL 0x09 25 | /* I/O */ 26 | #define RT5677_SIDETONE_CTRL 0x13 27 | /* I/O - ADC/DAC */ 28 | #define RT5677_ANA_DAC1_2_3_SRC 0x15 29 | #define RT5677_IF_DSP_DAC3_4_MIXER 0x16 30 | #define RT5677_DAC4_DIG_VOL 0x17 31 | #define RT5677_DAC3_DIG_VOL 0x18 32 | #define RT5677_DAC1_DIG_VOL 0x19 33 | #define RT5677_DAC2_DIG_VOL 0x1a 34 | #define RT5677_IF_DSP_DAC2_MIXER 0x1b 35 | #define RT5677_STO1_ADC_DIG_VOL 0x1c 36 | #define RT5677_MONO_ADC_DIG_VOL 0x1d 37 | #define RT5677_STO1_2_ADC_BST 0x1e 38 | #define RT5677_STO2_ADC_DIG_VOL 0x1f 39 | /* Mixer - D-D */ 40 | #define RT5677_ADC_BST_CTRL2 0x20 41 | #define RT5677_STO3_4_ADC_BST 0x21 42 | #define RT5677_STO3_ADC_DIG_VOL 0x22 43 | #define RT5677_STO4_ADC_DIG_VOL 0x23 44 | #define RT5677_STO4_ADC_MIXER 0x24 45 | #define RT5677_STO3_ADC_MIXER 0x25 46 | #define RT5677_STO2_ADC_MIXER 0x26 47 | #define RT5677_STO1_ADC_MIXER 0x27 48 | #define RT5677_MONO_ADC_MIXER 0x28 49 | #define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29 50 | #define RT5677_STO1_DAC_MIXER 0x2a 51 | #define RT5677_MONO_DAC_MIXER 0x2b 52 | #define RT5677_DD1_MIXER 0x2c 53 | #define RT5677_DD2_MIXER 0x2d 54 | #define RT5677_IF3_DATA 0x2f 55 | #define RT5677_IF4_DATA 0x30 56 | /* Mixer - PDM */ 57 | #define RT5677_PDM_OUT_CTRL 0x31 58 | #define RT5677_PDM_DATA_CTRL1 0x32 59 | #define RT5677_PDM_DATA_CTRL2 0x33 60 | #define RT5677_PDM1_DATA_CTRL2 0x34 61 | #define RT5677_PDM1_DATA_CTRL3 0x35 62 | #define RT5677_PDM1_DATA_CTRL4 0x36 63 | #define RT5677_PDM2_DATA_CTRL2 0x37 64 | #define RT5677_PDM2_DATA_CTRL3 0x38 65 | #define RT5677_PDM2_DATA_CTRL4 0x39 66 | /* TDM */ 67 | #define RT5677_TDM1_CTRL1 0x3b 68 | #define RT5677_TDM1_CTRL2 0x3c 69 | #define RT5677_TDM1_CTRL3 0x3d 70 | #define RT5677_TDM1_CTRL4 0x3e 71 | #define RT5677_TDM1_CTRL5 0x3f 72 | #define RT5677_TDM2_CTRL1 0x40 73 | #define RT5677_TDM2_CTRL2 0x41 74 | #define RT5677_TDM2_CTRL3 0x42 75 | #define RT5677_TDM2_CTRL4 0x43 76 | #define RT5677_TDM2_CTRL5 0x44 77 | /* I2C_MASTER_CTRL */ 78 | #define RT5677_I2C_MASTER_CTRL1 0x47 79 | #define RT5677_I2C_MASTER_CTRL2 0x48 80 | #define RT5677_I2C_MASTER_CTRL3 0x49 81 | #define RT5677_I2C_MASTER_CTRL4 0x4a 82 | #define RT5677_I2C_MASTER_CTRL5 0x4b 83 | #define RT5677_I2C_MASTER_CTRL6 0x4c 84 | #define RT5677_I2C_MASTER_CTRL7 0x4d 85 | #define RT5677_I2C_MASTER_CTRL8 0x4e 86 | /* DMIC */ 87 | #define RT5677_DMIC_CTRL1 0x50 88 | #define RT5677_DMIC_CTRL2 0x51 89 | /* Haptic Generator */ 90 | #define RT5677_HAP_GENE_CTRL1 0x56 91 | #define RT5677_HAP_GENE_CTRL2 0x57 92 | #define RT5677_HAP_GENE_CTRL3 0x58 93 | #define RT5677_HAP_GENE_CTRL4 0x59 94 | #define RT5677_HAP_GENE_CTRL5 0x5a 95 | #define RT5677_HAP_GENE_CTRL6 0x5b 96 | #define RT5677_HAP_GENE_CTRL7 0x5c 97 | #define RT5677_HAP_GENE_CTRL8 0x5d 98 | #define RT5677_HAP_GENE_CTRL9 0x5e 99 | #define RT5677_HAP_GENE_CTRL10 0x5f 100 | /* Power */ 101 | #define RT5677_PWR_DIG1 0x61 102 | #define RT5677_PWR_DIG2 0x62 103 | #define RT5677_PWR_ANLG1 0x63 104 | #define RT5677_PWR_ANLG2 0x64 105 | #define RT5677_PWR_DSP1 0x65 106 | #define RT5677_PWR_DSP_ST 0x66 107 | #define RT5677_PWR_DSP2 0x67 108 | #define RT5677_ADC_DAC_HPF_CTRL1 0x68 109 | /* Private Register Control */ 110 | #define RT5677_PRIV_INDEX 0x6a 111 | #define RT5677_PRIV_DATA 0x6c 112 | /* Format - ADC/DAC */ 113 | #define RT5677_I2S4_SDP 0x6f 114 | #define RT5677_I2S1_SDP 0x70 115 | #define RT5677_I2S2_SDP 0x71 116 | #define RT5677_I2S3_SDP 0x72 117 | #define RT5677_CLK_TREE_CTRL1 0x73 118 | #define RT5677_CLK_TREE_CTRL2 0x74 119 | #define RT5677_CLK_TREE_CTRL3 0x75 120 | /* Function - Analog */ 121 | #define RT5677_PLL1_CTRL1 0x7a 122 | #define RT5677_PLL1_CTRL2 0x7b 123 | #define RT5677_PLL2_CTRL1 0x7c 124 | #define RT5677_PLL2_CTRL2 0x7d 125 | #define RT5677_GLB_CLK1 0x80 126 | #define RT5677_GLB_CLK2 0x81 127 | #define RT5677_ASRC_1 0x83 128 | #define RT5677_ASRC_2 0x84 129 | #define RT5677_ASRC_3 0x85 130 | #define RT5677_ASRC_4 0x86 131 | #define RT5677_ASRC_5 0x87 132 | #define RT5677_ASRC_6 0x88 133 | #define RT5677_ASRC_7 0x89 134 | #define RT5677_ASRC_8 0x8a 135 | #define RT5677_ASRC_9 0x8b 136 | #define RT5677_ASRC_10 0x8c 137 | #define RT5677_ASRC_11 0x8d 138 | #define RT5677_ASRC_12 0x8e 139 | #define RT5677_ASRC_13 0x8f 140 | #define RT5677_ASRC_14 0x90 141 | #define RT5677_ASRC_15 0x91 142 | #define RT5677_ASRC_16 0x92 143 | #define RT5677_ASRC_17 0x93 144 | #define RT5677_ASRC_18 0x94 145 | #define RT5677_ASRC_19 0x95 146 | #define RT5677_ASRC_20 0x97 147 | #define RT5677_ASRC_21 0x98 148 | #define RT5677_ASRC_22 0x99 149 | #define RT5677_ASRC_23 0x9a 150 | #define RT5677_VAD_CTRL1 0x9c 151 | #define RT5677_VAD_CTRL2 0x9d 152 | #define RT5677_VAD_CTRL3 0x9e 153 | #define RT5677_VAD_CTRL4 0x9f 154 | #define RT5677_VAD_CTRL5 0xa0 155 | /* Function - Digital */ 156 | #define RT5677_DSP_INB_CTRL1 0xa3 157 | #define RT5677_DSP_INB_CTRL2 0xa4 158 | #define RT5677_DSP_IN_OUTB_CTRL 0xa5 159 | #define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6 160 | #define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7 161 | #define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8 162 | #define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9 163 | #define RT5677_ADC_EQ_CTRL1 0xae 164 | #define RT5677_ADC_EQ_CTRL2 0xaf 165 | #define RT5677_EQ_CTRL1 0xb0 166 | #define RT5677_EQ_CTRL2 0xb1 167 | #define RT5677_EQ_CTRL3 0xb2 168 | #define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3 169 | #define RT5677_JD_CTRL1 0xb5 170 | #define RT5677_JD_CTRL2 0xb6 171 | #define RT5677_JD_CTRL3 0xb8 172 | #define RT5677_IRQ_CTRL1 0xbd 173 | #define RT5677_IRQ_CTRL2 0xbe 174 | #define RT5677_GPIO_ST 0xbf 175 | #define RT5677_GPIO_CTRL1 0xc0 176 | #define RT5677_GPIO_CTRL2 0xc1 177 | #define RT5677_GPIO_CTRL3 0xc2 178 | #define RT5677_STO1_ADC_HI_FILTER1 0xc5 179 | #define RT5677_STO1_ADC_HI_FILTER2 0xc6 180 | #define RT5677_MONO_ADC_HI_FILTER1 0xc7 181 | #define RT5677_MONO_ADC_HI_FILTER2 0xc8 182 | #define RT5677_STO2_ADC_HI_FILTER1 0xc9 183 | #define RT5677_STO2_ADC_HI_FILTER2 0xca 184 | #define RT5677_STO3_ADC_HI_FILTER1 0xcb 185 | #define RT5677_STO3_ADC_HI_FILTER2 0xcc 186 | #define RT5677_STO4_ADC_HI_FILTER1 0xcd 187 | #define RT5677_STO4_ADC_HI_FILTER2 0xce 188 | #define RT5677_MB_DRC_CTRL1 0xd0 189 | #define RT5677_DRC1_CTRL1 0xd2 190 | #define RT5677_DRC1_CTRL2 0xd3 191 | #define RT5677_DRC1_CTRL3 0xd4 192 | #define RT5677_DRC1_CTRL4 0xd5 193 | #define RT5677_DRC1_CTRL5 0xd6 194 | #define RT5677_DRC1_CTRL6 0xd7 195 | #define RT5677_DRC2_CTRL1 0xd8 196 | #define RT5677_DRC2_CTRL2 0xd9 197 | #define RT5677_DRC2_CTRL3 0xda 198 | #define RT5677_DRC2_CTRL4 0xdb 199 | #define RT5677_DRC2_CTRL5 0xdc 200 | #define RT5677_DRC2_CTRL6 0xdd 201 | #define RT5677_DRC1_HL_CTRL1 0xde 202 | #define RT5677_DRC1_HL_CTRL2 0xdf 203 | #define RT5677_DRC2_HL_CTRL1 0xe0 204 | #define RT5677_DRC2_HL_CTRL2 0xe1 205 | #define RT5677_DSP_INB1_SRC_CTRL1 0xe3 206 | #define RT5677_DSP_INB1_SRC_CTRL2 0xe4 207 | #define RT5677_DSP_INB1_SRC_CTRL3 0xe5 208 | #define RT5677_DSP_INB1_SRC_CTRL4 0xe6 209 | #define RT5677_DSP_INB2_SRC_CTRL1 0xe7 210 | #define RT5677_DSP_INB2_SRC_CTRL2 0xe8 211 | #define RT5677_DSP_INB2_SRC_CTRL3 0xe9 212 | #define RT5677_DSP_INB2_SRC_CTRL4 0xea 213 | #define RT5677_DSP_INB3_SRC_CTRL1 0xeb 214 | #define RT5677_DSP_INB3_SRC_CTRL2 0xec 215 | #define RT5677_DSP_INB3_SRC_CTRL3 0xed 216 | #define RT5677_DSP_INB3_SRC_CTRL4 0xee 217 | #define RT5677_DSP_OUTB1_SRC_CTRL1 0xef 218 | #define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0 219 | #define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1 220 | #define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2 221 | #define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3 222 | #define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4 223 | #define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5 224 | #define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6 225 | 226 | /* Virtual DSP Mixer Control */ 227 | #define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7 228 | #define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8 229 | #define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9 230 | 231 | /* General Control */ 232 | #define RT5677_DIG_MISC 0xfa 233 | #define RT5677_GEN_CTRL1 0xfb 234 | #define RT5677_GEN_CTRL2 0xfc 235 | 236 | /* DSP Mode I2C Control*/ 237 | #define RT5677_DSP_I2C_OP_CODE 0x00 238 | #define RT5677_DSP_I2C_ADDR_LSB 0x01 239 | #define RT5677_DSP_I2C_ADDR_MSB 0x02 240 | #define RT5677_DSP_I2C_DATA_LSB 0x03 241 | #define RT5677_DSP_I2C_DATA_MSB 0x04 242 | 243 | /* Index of Codec Private Register definition */ 244 | #define RT5677_PR_DRC1_CTRL_1 0x01 245 | #define RT5677_PR_DRC1_CTRL_2 0x02 246 | #define RT5677_PR_DRC1_CTRL_3 0x03 247 | #define RT5677_PR_DRC1_CTRL_4 0x04 248 | #define RT5677_PR_DRC1_CTRL_5 0x05 249 | #define RT5677_PR_DRC1_CTRL_6 0x06 250 | #define RT5677_PR_DRC1_CTRL_7 0x07 251 | #define RT5677_PR_DRC2_CTRL_1 0x08 252 | #define RT5677_PR_DRC2_CTRL_2 0x09 253 | #define RT5677_PR_DRC2_CTRL_3 0x0a 254 | #define RT5677_PR_DRC2_CTRL_4 0x0b 255 | #define RT5677_PR_DRC2_CTRL_5 0x0c 256 | #define RT5677_PR_DRC2_CTRL_6 0x0d 257 | #define RT5677_PR_DRC2_CTRL_7 0x0e 258 | #define RT5677_BIAS_CUR1 0x10 259 | #define RT5677_BIAS_CUR2 0x12 260 | #define RT5677_BIAS_CUR3 0x13 261 | #define RT5677_BIAS_CUR4 0x14 262 | #define RT5677_BIAS_CUR5 0x15 263 | #define RT5677_VREF_LOUT_CTRL 0x17 264 | #define RT5677_DIG_VOL_CTRL1 0x1a 265 | #define RT5677_DIG_VOL_CTRL2 0x1b 266 | #define RT5677_ANA_ADC_GAIN_CTRL 0x1e 267 | #define RT5677_VAD_SRAM_TEST1 0x20 268 | #define RT5677_VAD_SRAM_TEST2 0x21 269 | #define RT5677_VAD_SRAM_TEST3 0x22 270 | #define RT5677_VAD_SRAM_TEST4 0x23 271 | #define RT5677_PAD_DRV_CTRL 0x26 272 | #define RT5677_DIG_IN_PIN_ST_CTRL1 0x29 273 | #define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a 274 | #define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b 275 | #define RT5677_PLL1_INT 0x38 276 | #define RT5677_PLL2_INT 0x39 277 | #define RT5677_TEST_CTRL1 0x3a 278 | #define RT5677_TEST_CTRL2 0x3b 279 | #define RT5677_TEST_CTRL3 0x3c 280 | #define RT5677_CHOP_DAC_ADC 0x3d 281 | #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e 282 | #define RT5677_CROSS_OVER_FILTER1 0x90 283 | #define RT5677_CROSS_OVER_FILTER2 0x91 284 | #define RT5677_CROSS_OVER_FILTER3 0x92 285 | #define RT5677_CROSS_OVER_FILTER4 0x93 286 | #define RT5677_CROSS_OVER_FILTER5 0x94 287 | #define RT5677_CROSS_OVER_FILTER6 0x95 288 | #define RT5677_CROSS_OVER_FILTER7 0x96 289 | #define RT5677_CROSS_OVER_FILTER8 0x97 290 | #define RT5677_CROSS_OVER_FILTER9 0x98 291 | #define RT5677_CROSS_OVER_FILTER10 0x99 292 | 293 | /* global definition */ 294 | #define RT5677_L_MUTE (0x1 << 15) 295 | #define RT5677_L_MUTE_SFT 15 296 | #define RT5677_VOL_L_MUTE (0x1 << 14) 297 | #define RT5677_VOL_L_SFT 14 298 | #define RT5677_R_MUTE (0x1 << 7) 299 | #define RT5677_R_MUTE_SFT 7 300 | #define RT5677_VOL_R_MUTE (0x1 << 6) 301 | #define RT5677_VOL_R_SFT 6 302 | #define RT5677_L_VOL_MASK (0x7f << 9) 303 | #define RT5677_L_VOL_SFT 9 304 | #define RT5677_R_VOL_MASK (0x7f << 1) 305 | #define RT5677_R_VOL_SFT 1 306 | 307 | /* LOUT1 Control (0x01) */ 308 | #define RT5677_LOUT1_L_MUTE (0x1 << 15) 309 | #define RT5677_LOUT1_L_MUTE_SFT (15) 310 | #define RT5677_LOUT1_L_DF (0x1 << 14) 311 | #define RT5677_LOUT1_L_DF_SFT (14) 312 | #define RT5677_LOUT2_L_MUTE (0x1 << 13) 313 | #define RT5677_LOUT2_L_MUTE_SFT (13) 314 | #define RT5677_LOUT2_L_DF (0x1 << 12) 315 | #define RT5677_LOUT2_L_DF_SFT (12) 316 | #define RT5677_LOUT3_L_MUTE (0x1 << 11) 317 | #define RT5677_LOUT3_L_MUTE_SFT (11) 318 | #define RT5677_LOUT3_L_DF (0x1 << 10) 319 | #define RT5677_LOUT3_L_DF_SFT (10) 320 | #define RT5677_LOUT1_ENH_DRV (0x1 << 9) 321 | #define RT5677_LOUT1_ENH_DRV_SFT (9) 322 | #define RT5677_LOUT2_ENH_DRV (0x1 << 8) 323 | #define RT5677_LOUT2_ENH_DRV_SFT (8) 324 | #define RT5677_LOUT3_ENH_DRV (0x1 << 7) 325 | #define RT5677_LOUT3_ENH_DRV_SFT (7) 326 | 327 | /* IN1 Control (0x03) */ 328 | #define RT5677_BST_MASK1 (0xf << 12) 329 | #define RT5677_BST_SFT1 12 330 | #define RT5677_BST_MASK2 (0xf << 8) 331 | #define RT5677_BST_SFT2 8 332 | #define RT5677_IN_DF1 (0x1 << 7) 333 | #define RT5677_IN_DF1_SFT 7 334 | #define RT5677_IN_DF2 (0x1 << 6) 335 | #define RT5677_IN_DF2_SFT 6 336 | 337 | /* Micbias Control (0x04) */ 338 | #define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15) 339 | #define RT5677_MICBIAS1_OUTVOLT_SFT (15) 340 | #define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15) 341 | #define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15) 342 | #define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14) 343 | #define RT5677_MICBIAS1_CTRL_VDD_SFT (14) 344 | #define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14) 345 | #define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14) 346 | #define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11) 347 | #define RT5677_MICBIAS1_OVCD_SHIFT (11) 348 | #define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11) 349 | #define RT5677_MICBIAS1_OVCD_EN (0x1 << 11) 350 | #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9) 351 | #define RT5677_MICBIAS1_OVTH_SFT 9 352 | #define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9) 353 | #define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9) 354 | #define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9) 355 | 356 | /* SLIMbus Parameter (0x07) */ 357 | 358 | /* SLIMbus Rx (0x08) */ 359 | #define RT5677_SLB_ADC4_MASK (0x3 << 6) 360 | #define RT5677_SLB_ADC4_SFT 6 361 | #define RT5677_SLB_ADC3_MASK (0x3 << 4) 362 | #define RT5677_SLB_ADC3_SFT 4 363 | #define RT5677_SLB_ADC2_MASK (0x3 << 2) 364 | #define RT5677_SLB_ADC2_SFT 2 365 | #define RT5677_SLB_ADC1_MASK (0x3 << 0) 366 | #define RT5677_SLB_ADC1_SFT 0 367 | 368 | /* SLIMBus control (0x09) */ 369 | 370 | /* Sidetone Control (0x13) */ 371 | #define RT5677_ST_HPF_SEL_MASK (0x7 << 13) 372 | #define RT5677_ST_HPF_SEL_SFT 13 373 | #define RT5677_ST_HPF_PATH (0x1 << 12) 374 | #define RT5677_ST_HPF_PATH_SFT 12 375 | #define RT5677_ST_SEL_MASK (0x7 << 9) 376 | #define RT5677_ST_SEL_SFT 9 377 | #define RT5677_ST_EN (0x1 << 6) 378 | #define RT5677_ST_EN_SFT 6 379 | #define RT5677_ST_GAIN (0x1 << 5) 380 | #define RT5677_ST_GAIN_SFT 5 381 | #define RT5677_ST_VOL_MASK (0x1f << 0) 382 | #define RT5677_ST_VOL_SFT 0 383 | 384 | /* Analog DAC1/2/3 Source Control (0x15) */ 385 | #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4) 386 | #define RT5677_ANA_DAC3_SRC_SEL_SFT 4 387 | #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0) 388 | #define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0 389 | 390 | /* IF/DSP to DAC3/4 Mixer Control (0x16) */ 391 | #define RT5677_M_DAC4_L_VOL (0x1 << 15) 392 | #define RT5677_M_DAC4_L_VOL_SFT 15 393 | #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12) 394 | #define RT5677_SEL_DAC4_L_SRC_SFT 12 395 | #define RT5677_M_DAC4_R_VOL (0x1 << 11) 396 | #define RT5677_M_DAC4_R_VOL_SFT 11 397 | #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8) 398 | #define RT5677_SEL_DAC4_R_SRC_SFT 8 399 | #define RT5677_M_DAC3_L_VOL (0x1 << 7) 400 | #define RT5677_M_DAC3_L_VOL_SFT 7 401 | #define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4) 402 | #define RT5677_SEL_DAC3_L_SRC_SFT 4 403 | #define RT5677_M_DAC3_R_VOL (0x1 << 3) 404 | #define RT5677_M_DAC3_R_VOL_SFT 3 405 | #define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0) 406 | #define RT5677_SEL_DAC3_R_SRC_SFT 0 407 | 408 | /* DAC4 Digital Volume (0x17) */ 409 | #define RT5677_DAC4_L_VOL_MASK (0xff << 8) 410 | #define RT5677_DAC4_L_VOL_SFT 8 411 | #define RT5677_DAC4_R_VOL_MASK (0xff) 412 | #define RT5677_DAC4_R_VOL_SFT 0 413 | 414 | /* DAC3 Digital Volume (0x18) */ 415 | #define RT5677_DAC3_L_VOL_MASK (0xff << 8) 416 | #define RT5677_DAC3_L_VOL_SFT 8 417 | #define RT5677_DAC3_R_VOL_MASK (0xff) 418 | #define RT5677_DAC3_R_VOL_SFT 0 419 | 420 | /* DAC3 Digital Volume (0x19) */ 421 | #define RT5677_DAC1_L_VOL_MASK (0xff << 8) 422 | #define RT5677_DAC1_L_VOL_SFT 8 423 | #define RT5677_DAC1_R_VOL_MASK (0xff) 424 | #define RT5677_DAC1_R_VOL_SFT 0 425 | 426 | /* DAC2 Digital Volume (0x1a) */ 427 | #define RT5677_DAC2_L_VOL_MASK (0xff << 8) 428 | #define RT5677_DAC2_L_VOL_SFT 8 429 | #define RT5677_DAC2_R_VOL_MASK (0xff) 430 | #define RT5677_DAC2_R_VOL_SFT 0 431 | 432 | /* IF/DSP to DAC2 Mixer Control (0x1b) */ 433 | #define RT5677_M_DAC2_L_VOL (0x1 << 7) 434 | #define RT5677_M_DAC2_L_VOL_SFT 7 435 | #define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4) 436 | #define RT5677_SEL_DAC2_L_SRC_SFT 4 437 | #define RT5677_M_DAC2_R_VOL (0x1 << 3) 438 | #define RT5677_M_DAC2_R_VOL_SFT 3 439 | #define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0) 440 | #define RT5677_SEL_DAC2_R_SRC_SFT 0 441 | 442 | /* Stereo1 ADC Digital Volume Control (0x1c) */ 443 | #define RT5677_STO1_ADC_L_VOL_MASK (0x3f << 9) 444 | #define RT5677_STO1_ADC_L_VOL_SFT 9 445 | #define RT5677_STO1_ADC_R_VOL_MASK (0x3f << 1) 446 | #define RT5677_STO1_ADC_R_VOL_SFT 1 447 | 448 | /* Mono ADC Digital Volume Control (0x1d) */ 449 | #define RT5677_MONO_ADC_L_VOL_MASK (0x3f << 9) 450 | #define RT5677_MONO_ADC_L_VOL_SFT 9 451 | #define RT5677_MONO_ADC_R_VOL_MASK (0x3f << 1) 452 | #define RT5677_MONO_ADC_R_VOL_SFT 1 453 | 454 | /* Stereo 1/2 ADC Boost Gain Control (0x1e) */ 455 | #define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14) 456 | #define RT5677_STO1_ADC_L_BST_SFT 14 457 | #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12) 458 | #define RT5677_STO1_ADC_R_BST_SFT 12 459 | #define RT5677_STO1_ADC_COMP_MASK (0x3 << 10) 460 | #define RT5677_STO1_ADC_COMP_SFT 10 461 | #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8) 462 | #define RT5677_STO2_ADC_L_BST_SFT 8 463 | #define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6) 464 | #define RT5677_STO2_ADC_R_BST_SFT 6 465 | #define RT5677_STO2_ADC_COMP_MASK (0x3 << 4) 466 | #define RT5677_STO2_ADC_COMP_SFT 4 467 | 468 | /* Stereo2 ADC Digital Volume Control (0x1f) */ 469 | #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8) 470 | #define RT5677_STO2_ADC_L_VOL_SFT 8 471 | #define RT5677_STO2_ADC_R_VOL_MASK (0x7f) 472 | #define RT5677_STO2_ADC_R_VOL_SFT 0 473 | 474 | /* ADC Boost Gain Control 2 (0x20) */ 475 | #define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14) 476 | #define RT5677_MONO_ADC_L_BST_SFT 14 477 | #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12) 478 | #define RT5677_MONO_ADC_R_BST_SFT 12 479 | #define RT5677_MONO_ADC_COMP_MASK (0x3 << 10) 480 | #define RT5677_MONO_ADC_COMP_SFT 10 481 | 482 | /* Stereo 3/4 ADC Boost Gain Control (0x21) */ 483 | #define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14) 484 | #define RT5677_STO3_ADC_L_BST_SFT 14 485 | #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12) 486 | #define RT5677_STO3_ADC_R_BST_SFT 12 487 | #define RT5677_STO3_ADC_COMP_MASK (0x3 << 10) 488 | #define RT5677_STO3_ADC_COMP_SFT 10 489 | #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8) 490 | #define RT5677_STO4_ADC_L_BST_SFT 8 491 | #define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6) 492 | #define RT5677_STO4_ADC_R_BST_SFT 6 493 | #define RT5677_STO4_ADC_COMP_MASK (0x3 << 4) 494 | #define RT5677_STO4_ADC_COMP_SFT 4 495 | 496 | /* Stereo3 ADC Digital Volume Control (0x22) */ 497 | #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8) 498 | #define RT5677_STO3_ADC_L_VOL_SFT 8 499 | #define RT5677_STO3_ADC_R_VOL_MASK (0x7f) 500 | #define RT5677_STO3_ADC_R_VOL_SFT 0 501 | 502 | /* Stereo4 ADC Digital Volume Control (0x23) */ 503 | #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8) 504 | #define RT5677_STO4_ADC_L_VOL_SFT 8 505 | #define RT5677_STO4_ADC_R_VOL_MASK (0x7f) 506 | #define RT5677_STO4_ADC_R_VOL_SFT 0 507 | 508 | /* Stereo4 ADC Mixer control (0x24) */ 509 | #define RT5677_M_STO4_ADC_L2 (0x1 << 15) 510 | #define RT5677_M_STO4_ADC_L2_SFT 15 511 | #define RT5677_M_STO4_ADC_L1 (0x1 << 14) 512 | #define RT5677_M_STO4_ADC_L1_SFT 14 513 | #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12) 514 | #define RT5677_SEL_STO4_ADC1_SFT 12 515 | #define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10) 516 | #define RT5677_SEL_STO4_ADC2_SFT 10 517 | #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8) 518 | #define RT5677_SEL_STO4_DMIC_SFT 8 519 | #define RT5677_M_STO4_ADC_R1 (0x1 << 7) 520 | #define RT5677_M_STO4_ADC_R1_SFT 7 521 | #define RT5677_M_STO4_ADC_R2 (0x1 << 6) 522 | #define RT5677_M_STO4_ADC_R2_SFT 6 523 | 524 | /* Stereo3 ADC Mixer control (0x25) */ 525 | #define RT5677_M_STO3_ADC_L2 (0x1 << 15) 526 | #define RT5677_M_STO3_ADC_L2_SFT 15 527 | #define RT5677_M_STO3_ADC_L1 (0x1 << 14) 528 | #define RT5677_M_STO3_ADC_L1_SFT 14 529 | #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12) 530 | #define RT5677_SEL_STO3_ADC1_SFT 12 531 | #define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10) 532 | #define RT5677_SEL_STO3_ADC2_SFT 10 533 | #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8) 534 | #define RT5677_SEL_STO3_DMIC_SFT 8 535 | #define RT5677_M_STO3_ADC_R1 (0x1 << 7) 536 | #define RT5677_M_STO3_ADC_R1_SFT 7 537 | #define RT5677_M_STO3_ADC_R2 (0x1 << 6) 538 | #define RT5677_M_STO3_ADC_R2_SFT 6 539 | 540 | /* Stereo2 ADC Mixer Control (0x26) */ 541 | #define RT5677_M_STO2_ADC_L2 (0x1 << 15) 542 | #define RT5677_M_STO2_ADC_L2_SFT 15 543 | #define RT5677_M_STO2_ADC_L1 (0x1 << 14) 544 | #define RT5677_M_STO2_ADC_L1_SFT 14 545 | #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12) 546 | #define RT5677_SEL_STO2_ADC1_SFT 12 547 | #define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10) 548 | #define RT5677_SEL_STO2_ADC2_SFT 10 549 | #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8) 550 | #define RT5677_SEL_STO2_DMIC_SFT 8 551 | #define RT5677_M_STO2_ADC_R1 (0x1 << 7) 552 | #define RT5677_M_STO2_ADC_R1_SFT 7 553 | #define RT5677_M_STO2_ADC_R2 (0x1 << 6) 554 | #define RT5677_M_STO2_ADC_R2_SFT 6 555 | #define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0) 556 | #define RT5677_SEL_STO2_LR_MIX_SFT 0 557 | #define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0) 558 | #define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0) 559 | 560 | /* Stereo1 ADC Mixer control (0x27) */ 561 | #define RT5677_M_STO1_ADC_L2 (0x1 << 15) 562 | #define RT5677_M_STO1_ADC_L2_SFT 15 563 | #define RT5677_M_STO1_ADC_L1 (0x1 << 14) 564 | #define RT5677_M_STO1_ADC_L1_SFT 14 565 | #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12) 566 | #define RT5677_SEL_STO1_ADC1_SFT 12 567 | #define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10) 568 | #define RT5677_SEL_STO1_ADC2_SFT 10 569 | #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8) 570 | #define RT5677_SEL_STO1_DMIC_SFT 8 571 | #define RT5677_M_STO1_ADC_R1 (0x1 << 7) 572 | #define RT5677_M_STO1_ADC_R1_SFT 7 573 | #define RT5677_M_STO1_ADC_R2 (0x1 << 6) 574 | #define RT5677_M_STO1_ADC_R2_SFT 6 575 | 576 | /* Mono ADC Mixer control (0x28) */ 577 | #define RT5677_M_MONO_ADC_L2 (0x1 << 15) 578 | #define RT5677_M_MONO_ADC_L2_SFT 15 579 | #define RT5677_M_MONO_ADC_L1 (0x1 << 14) 580 | #define RT5677_M_MONO_ADC_L1_SFT 14 581 | #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12) 582 | #define RT5677_SEL_MONO_ADC_L1_SFT 12 583 | #define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10) 584 | #define RT5677_SEL_MONO_ADC_L2_SFT 10 585 | #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8) 586 | #define RT5677_SEL_MONO_DMIC_L_SFT 8 587 | #define RT5677_M_MONO_ADC_R1 (0x1 << 7) 588 | #define RT5677_M_MONO_ADC_R1_SFT 7 589 | #define RT5677_M_MONO_ADC_R2 (0x1 << 6) 590 | #define RT5677_M_MONO_ADC_R2_SFT 6 591 | #define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4) 592 | #define RT5677_SEL_MONO_ADC_R1_SFT 4 593 | #define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2) 594 | #define RT5677_SEL_MONO_ADC_R2_SFT 2 595 | #define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0) 596 | #define RT5677_SEL_MONO_DMIC_R_SFT 0 597 | 598 | /* ADC/IF/DSP to DAC1 Mixer control (0x29) */ 599 | #define RT5677_M_ADDA_MIXER1_L (0x1 << 15) 600 | #define RT5677_M_ADDA_MIXER1_L_SFT 15 601 | #define RT5677_M_DAC1_L (0x1 << 14) 602 | #define RT5677_M_DAC1_L_SFT 14 603 | #define RT5677_DAC1_L_SEL_MASK (0x7 << 8) 604 | #define RT5677_DAC1_L_SEL_SFT 8 605 | #define RT5677_M_ADDA_MIXER1_R (0x1 << 7) 606 | #define RT5677_M_ADDA_MIXER1_R_SFT 7 607 | #define RT5677_M_DAC1_R (0x1 << 6) 608 | #define RT5677_M_DAC1_R_SFT 6 609 | #define RT5677_ADDA1_SEL_MASK (0x3 << 0) 610 | #define RT5677_ADDA1_SEL_SFT 0 611 | 612 | /* Stereo1 DAC Mixer L/R Control (0x2a) */ 613 | #define RT5677_M_ST_DAC1_L (0x1 << 15) 614 | #define RT5677_M_ST_DAC1_L_SFT 15 615 | #define RT5677_M_DAC1_L_STO_L (0x1 << 13) 616 | #define RT5677_M_DAC1_L_STO_L_SFT 13 617 | #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12) 618 | #define RT5677_DAC1_L_STO_L_VOL_SFT 12 619 | #define RT5677_M_DAC2_L_STO_L (0x1 << 11) 620 | #define RT5677_M_DAC2_L_STO_L_SFT 11 621 | #define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10) 622 | #define RT5677_DAC2_L_STO_L_VOL_SFT 10 623 | #define RT5677_M_DAC1_R_STO_L (0x1 << 9) 624 | #define RT5677_M_DAC1_R_STO_L_SFT 9 625 | #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8) 626 | #define RT5677_DAC1_R_STO_L_VOL_SFT 8 627 | #define RT5677_M_ST_DAC1_R (0x1 << 7) 628 | #define RT5677_M_ST_DAC1_R_SFT 7 629 | #define RT5677_M_DAC1_R_STO_R (0x1 << 5) 630 | #define RT5677_M_DAC1_R_STO_R_SFT 5 631 | #define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4) 632 | #define RT5677_DAC1_R_STO_R_VOL_SFT 4 633 | #define RT5677_M_DAC2_R_STO_R (0x1 << 3) 634 | #define RT5677_M_DAC2_R_STO_R_SFT 3 635 | #define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2) 636 | #define RT5677_DAC2_R_STO_R_VOL_SFT 2 637 | #define RT5677_M_DAC1_L_STO_R (0x1 << 1) 638 | #define RT5677_M_DAC1_L_STO_R_SFT 1 639 | #define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0) 640 | #define RT5677_DAC1_L_STO_R_VOL_SFT 0 641 | 642 | /* Mono DAC Mixer L/R Control (0x2b) */ 643 | #define RT5677_M_ST_DAC2_L (0x1 << 15) 644 | #define RT5677_M_ST_DAC2_L_SFT 15 645 | #define RT5677_M_DAC2_L_MONO_L (0x1 << 13) 646 | #define RT5677_M_DAC2_L_MONO_L_SFT 13 647 | #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12) 648 | #define RT5677_DAC2_L_MONO_L_VOL_SFT 12 649 | #define RT5677_M_DAC2_R_MONO_L (0x1 << 11) 650 | #define RT5677_M_DAC2_R_MONO_L_SFT 11 651 | #define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10) 652 | #define RT5677_DAC2_R_MONO_L_VOL_SFT 10 653 | #define RT5677_M_DAC1_L_MONO_L (0x1 << 9) 654 | #define RT5677_M_DAC1_L_MONO_L_SFT 9 655 | #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8) 656 | #define RT5677_DAC1_L_MONO_L_VOL_SFT 8 657 | #define RT5677_M_ST_DAC2_R (0x1 << 7) 658 | #define RT5677_M_ST_DAC2_R_SFT 7 659 | #define RT5677_M_DAC2_R_MONO_R (0x1 << 5) 660 | #define RT5677_M_DAC2_R_MONO_R_SFT 5 661 | #define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4) 662 | #define RT5677_DAC2_R_MONO_R_VOL_SFT 4 663 | #define RT5677_M_DAC1_R_MONO_R (0x1 << 3) 664 | #define RT5677_M_DAC1_R_MONO_R_SFT 3 665 | #define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2) 666 | #define RT5677_DAC1_R_MONO_R_VOL_SFT 2 667 | #define RT5677_M_DAC2_L_MONO_R (0x1 << 1) 668 | #define RT5677_M_DAC2_L_MONO_R_SFT 1 669 | #define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0) 670 | #define RT5677_DAC2_L_MONO_R_VOL_SFT 0 671 | 672 | /* DD Mixer 1 Control (0x2c) */ 673 | #define RT5677_M_STO_L_DD1_L (0x1 << 15) 674 | #define RT5677_M_STO_L_DD1_L_SFT 15 675 | #define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14) 676 | #define RT5677_STO_L_DD1_L_VOL_SFT 14 677 | #define RT5677_M_MONO_L_DD1_L (0x1 << 13) 678 | #define RT5677_M_MONO_L_DD1_L_SFT 13 679 | #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12) 680 | #define RT5677_MONO_L_DD1_L_VOL_SFT 12 681 | #define RT5677_M_DAC3_L_DD1_L (0x1 << 11) 682 | #define RT5677_M_DAC3_L_DD1_L_SFT 11 683 | #define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10) 684 | #define RT5677_DAC3_L_DD1_L_VOL_SFT 10 685 | #define RT5677_M_DAC3_R_DD1_L (0x1 << 9) 686 | #define RT5677_M_DAC3_R_DD1_L_SFT 9 687 | #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8) 688 | #define RT5677_DAC3_R_DD1_L_VOL_SFT 8 689 | #define RT5677_M_STO_R_DD1_R (0x1 << 7) 690 | #define RT5677_M_STO_R_DD1_R_SFT 7 691 | #define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6) 692 | #define RT5677_STO_R_DD1_R_VOL_SFT 6 693 | #define RT5677_M_MONO_R_DD1_R (0x1 << 5) 694 | #define RT5677_M_MONO_R_DD1_R_SFT 5 695 | #define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4) 696 | #define RT5677_MONO_R_DD1_R_VOL_SFT 4 697 | #define RT5677_M_DAC3_R_DD1_R (0x1 << 3) 698 | #define RT5677_M_DAC3_R_DD1_R_SFT 3 699 | #define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2) 700 | #define RT5677_DAC3_R_DD1_R_VOL_SFT 2 701 | #define RT5677_M_DAC3_L_DD1_R (0x1 << 1) 702 | #define RT5677_M_DAC3_L_DD1_R_SFT 1 703 | #define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0) 704 | #define RT5677_DAC3_L_DD1_R_VOL_SFT 0 705 | 706 | /* DD Mixer 2 Control (0x2d) */ 707 | #define RT5677_M_STO_L_DD2_L (0x1 << 15) 708 | #define RT5677_M_STO_L_DD2_L_SFT 15 709 | #define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14) 710 | #define RT5677_STO_L_DD2_L_VOL_SFT 14 711 | #define RT5677_M_MONO_L_DD2_L (0x1 << 13) 712 | #define RT5677_M_MONO_L_DD2_L_SFT 13 713 | #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12) 714 | #define RT5677_MONO_L_DD2_L_VOL_SFT 12 715 | #define RT5677_M_DAC4_L_DD2_L (0x1 << 11) 716 | #define RT5677_M_DAC4_L_DD2_L_SFT 11 717 | #define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10) 718 | #define RT5677_DAC4_L_DD2_L_VOL_SFT 10 719 | #define RT5677_M_DAC4_R_DD2_L (0x1 << 9) 720 | #define RT5677_M_DAC4_R_DD2_L_SFT 9 721 | #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8) 722 | #define RT5677_DAC4_R_DD2_L_VOL_SFT 8 723 | #define RT5677_M_STO_R_DD2_R (0x1 << 7) 724 | #define RT5677_M_STO_R_DD2_R_SFT 7 725 | #define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6) 726 | #define RT5677_STO_R_DD2_R_VOL_SFT 6 727 | #define RT5677_M_MONO_R_DD2_R (0x1 << 5) 728 | #define RT5677_M_MONO_R_DD2_R_SFT 5 729 | #define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4) 730 | #define RT5677_MONO_R_DD2_R_VOL_SFT 4 731 | #define RT5677_M_DAC4_R_DD2_R (0x1 << 3) 732 | #define RT5677_M_DAC4_R_DD2_R_SFT 3 733 | #define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2) 734 | #define RT5677_DAC4_R_DD2_R_VOL_SFT 2 735 | #define RT5677_M_DAC4_L_DD2_R (0x1 << 1) 736 | #define RT5677_M_DAC4_L_DD2_R_SFT 1 737 | #define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0) 738 | #define RT5677_DAC4_L_DD2_R_VOL_SFT 0 739 | 740 | /* IF3 data control (0x2f) */ 741 | #define RT5677_IF3_DAC_SEL_MASK (0x3 << 6) 742 | #define RT5677_IF3_DAC_SEL_SFT 6 743 | #define RT5677_IF3_ADC_SEL_MASK (0x3 << 4) 744 | #define RT5677_IF3_ADC_SEL_SFT 4 745 | #define RT5677_IF3_ADC_IN_MASK (0xf << 0) 746 | #define RT5677_IF3_ADC_IN_SFT 0 747 | 748 | /* IF4 data control (0x30) */ 749 | #define RT5677_IF4_ADC_IN_MASK (0xf << 4) 750 | #define RT5677_IF4_ADC_IN_SFT 4 751 | #define RT5677_IF4_DAC_SEL_MASK (0x3 << 2) 752 | #define RT5677_IF4_DAC_SEL_SFT 2 753 | #define RT5677_IF4_ADC_SEL_MASK (0x3 << 0) 754 | #define RT5677_IF4_ADC_SEL_SFT 0 755 | 756 | /* PDM Output Control (0x31) */ 757 | #define RT5677_M_PDM1_L (0x1 << 15) 758 | #define RT5677_M_PDM1_L_SFT 15 759 | #define RT5677_SEL_PDM1_L_MASK (0x3 << 12) 760 | #define RT5677_SEL_PDM1_L_SFT 12 761 | #define RT5677_M_PDM1_R (0x1 << 11) 762 | #define RT5677_M_PDM1_R_SFT 11 763 | #define RT5677_SEL_PDM1_R_MASK (0x3 << 8) 764 | #define RT5677_SEL_PDM1_R_SFT 8 765 | #define RT5677_M_PDM2_L (0x1 << 7) 766 | #define RT5677_M_PDM2_L_SFT 7 767 | #define RT5677_SEL_PDM2_L_MASK (0x3 << 4) 768 | #define RT5677_SEL_PDM2_L_SFT 4 769 | #define RT5677_M_PDM2_R (0x1 << 3) 770 | #define RT5677_M_PDM2_R_SFT 3 771 | #define RT5677_SEL_PDM2_R_MASK (0x3 << 0) 772 | #define RT5677_SEL_PDM2_R_SFT 0 773 | 774 | /* PDM I2C / Data Control 1 (0x32) */ 775 | #define RT5677_PDM2_PW_DOWN (0x1 << 7) 776 | #define RT5677_PDM1_PW_DOWN (0x1 << 6) 777 | #define RT5677_PDM2_BUSY (0x1 << 5) 778 | #define RT5677_PDM1_BUSY (0x1 << 4) 779 | #define RT5677_PDM_PATTERN (0x1 << 3) 780 | #define RT5677_PDM_GAIN (0x1 << 2) 781 | #define RT5677_PDM_DIV_MASK (0x3 << 0) 782 | 783 | /* PDM I2C / Data Control 2 (0x33) */ 784 | #define RT5677_PDM1_I2C_ID (0xf << 12) 785 | #define RT5677_PDM1_EXE (0x1 << 11) 786 | #define RT5677_PDM1_I2C_CMD (0x1 << 10) 787 | #define RT5677_PDM1_I2C_EXE (0x1 << 9) 788 | #define RT5677_PDM1_I2C_BUSY (0x1 << 8) 789 | #define RT5677_PDM2_I2C_ID (0xf << 4) 790 | #define RT5677_PDM2_EXE (0x1 << 3) 791 | #define RT5677_PDM2_I2C_CMD (0x1 << 2) 792 | #define RT5677_PDM2_I2C_EXE (0x1 << 1) 793 | #define RT5677_PDM2_I2C_BUSY (0x1 << 0) 794 | 795 | /* TDM1 control 1 (0x3b) */ 796 | #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12) 797 | #define RT5677_IF1_ADC_MODE_SFT 12 798 | #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12) 799 | #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12) 800 | #define RT5677_IF1_ADC1_SWAP_MASK (0x3 << 6) 801 | #define RT5677_IF1_ADC1_SWAP_SFT 6 802 | #define RT5677_IF1_ADC2_SWAP_MASK (0x3 << 4) 803 | #define RT5677_IF1_ADC2_SWAP_SFT 4 804 | #define RT5677_IF1_ADC3_SWAP_MASK (0x3 << 2) 805 | #define RT5677_IF1_ADC3_SWAP_SFT 2 806 | #define RT5677_IF1_ADC4_SWAP_MASK (0x3 << 0) 807 | #define RT5677_IF1_ADC4_SWAP_SFT 0 808 | 809 | /* TDM1 control 2 (0x3c) */ 810 | #define RT5677_IF1_ADC4_MASK (0x3 << 10) 811 | #define RT5677_IF1_ADC4_SFT 10 812 | #define RT5677_IF1_ADC3_MASK (0x3 << 8) 813 | #define RT5677_IF1_ADC3_SFT 8 814 | #define RT5677_IF1_ADC2_MASK (0x3 << 6) 815 | #define RT5677_IF1_ADC2_SFT 6 816 | #define RT5677_IF1_ADC1_MASK (0x3 << 4) 817 | #define RT5677_IF1_ADC1_SFT 4 818 | #define RT5677_IF1_ADC_CTRL_MASK (0x7 << 0) 819 | #define RT5677_IF1_ADC_CTRL_SFT 0 820 | 821 | /* TDM1 control 4 (0x3e) */ 822 | #define RT5677_IF1_DAC0_MASK (0x7 << 12) 823 | #define RT5677_IF1_DAC0_SFT 12 824 | #define RT5677_IF1_DAC1_MASK (0x7 << 8) 825 | #define RT5677_IF1_DAC1_SFT 8 826 | #define RT5677_IF1_DAC2_MASK (0x7 << 4) 827 | #define RT5677_IF1_DAC2_SFT 4 828 | #define RT5677_IF1_DAC3_MASK (0x7 << 0) 829 | #define RT5677_IF1_DAC3_SFT 0 830 | 831 | /* TDM1 control 5 (0x3f) */ 832 | #define RT5677_IF1_DAC4_MASK (0x7 << 12) 833 | #define RT5677_IF1_DAC4_SFT 12 834 | #define RT5677_IF1_DAC5_MASK (0x7 << 8) 835 | #define RT5677_IF1_DAC5_SFT 8 836 | #define RT5677_IF1_DAC6_MASK (0x7 << 4) 837 | #define RT5677_IF1_DAC6_SFT 4 838 | #define RT5677_IF1_DAC7_MASK (0x7 << 0) 839 | #define RT5677_IF1_DAC7_SFT 0 840 | 841 | /* TDM2 control 1 (0x40) */ 842 | #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12) 843 | #define RT5677_IF2_ADC_MODE_SFT 12 844 | #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12) 845 | #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12) 846 | #define RT5677_IF2_ADC1_SWAP_MASK (0x3 << 6) 847 | #define RT5677_IF2_ADC1_SWAP_SFT 6 848 | #define RT5677_IF2_ADC2_SWAP_MASK (0x3 << 4) 849 | #define RT5677_IF2_ADC2_SWAP_SFT 4 850 | #define RT5677_IF2_ADC3_SWAP_MASK (0x3 << 2) 851 | #define RT5677_IF2_ADC3_SWAP_SFT 2 852 | #define RT5677_IF2_ADC4_SWAP_MASK (0x3 << 0) 853 | #define RT5677_IF2_ADC4_SWAP_SFT 0 854 | 855 | /* TDM2 control 2 (0x41) */ 856 | #define RT5677_IF2_ADC4_MASK (0x3 << 10) 857 | #define RT5677_IF2_ADC4_SFT 10 858 | #define RT5677_IF2_ADC3_MASK (0x3 << 8) 859 | #define RT5677_IF2_ADC3_SFT 8 860 | #define RT5677_IF2_ADC2_MASK (0x3 << 6) 861 | #define RT5677_IF2_ADC2_SFT 6 862 | #define RT5677_IF2_ADC1_MASK (0x3 << 4) 863 | #define RT5677_IF2_ADC1_SFT 4 864 | #define RT5677_IF2_ADC_CTRL_MASK (0x7 << 0) 865 | #define RT5677_IF2_ADC_CTRL_SFT 0 866 | 867 | /* TDM2 control 4 (0x43) */ 868 | #define RT5677_IF2_DAC0_MASK (0x7 << 12) 869 | #define RT5677_IF2_DAC0_SFT 12 870 | #define RT5677_IF2_DAC1_MASK (0x7 << 8) 871 | #define RT5677_IF2_DAC1_SFT 8 872 | #define RT5677_IF2_DAC2_MASK (0x7 << 4) 873 | #define RT5677_IF2_DAC2_SFT 4 874 | #define RT5677_IF2_DAC3_MASK (0x7 << 0) 875 | #define RT5677_IF2_DAC3_SFT 0 876 | 877 | /* TDM2 control 5 (0x44) */ 878 | #define RT5677_IF2_DAC4_MASK (0x7 << 12) 879 | #define RT5677_IF2_DAC4_SFT 12 880 | #define RT5677_IF2_DAC5_MASK (0x7 << 8) 881 | #define RT5677_IF2_DAC5_SFT 8 882 | #define RT5677_IF2_DAC6_MASK (0x7 << 4) 883 | #define RT5677_IF2_DAC6_SFT 4 884 | #define RT5677_IF2_DAC7_MASK (0x7 << 0) 885 | #define RT5677_IF2_DAC7_SFT 0 886 | 887 | /* Digital Microphone Control 1 (0x50) */ 888 | #define RT5677_DMIC_1_EN_MASK (0x1 << 15) 889 | #define RT5677_DMIC_1_EN_SFT 15 890 | #define RT5677_DMIC_1_DIS (0x0 << 15) 891 | #define RT5677_DMIC_1_EN (0x1 << 15) 892 | #define RT5677_DMIC_2_EN_MASK (0x1 << 14) 893 | #define RT5677_DMIC_2_EN_SFT 14 894 | #define RT5677_DMIC_2_DIS (0x0 << 14) 895 | #define RT5677_DMIC_2_EN (0x1 << 14) 896 | #define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13) 897 | #define RT5677_DMIC_L_STO1_LH_SFT 13 898 | #define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13) 899 | #define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13) 900 | #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12) 901 | #define RT5677_DMIC_R_STO1_LH_SFT 12 902 | #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12) 903 | #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12) 904 | #define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11) 905 | #define RT5677_DMIC_L_STO3_LH_SFT 11 906 | #define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11) 907 | #define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11) 908 | #define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10) 909 | #define RT5677_DMIC_R_STO3_LH_SFT 10 910 | #define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10) 911 | #define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10) 912 | #define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9) 913 | #define RT5677_DMIC_L_STO2_LH_SFT 9 914 | #define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9) 915 | #define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9) 916 | #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8) 917 | #define RT5677_DMIC_R_STO2_LH_SFT 8 918 | #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8) 919 | #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8) 920 | #define RT5677_DMIC_CLK_MASK (0x7 << 5) 921 | #define RT5677_DMIC_CLK_SFT 5 922 | #define RT5677_DMIC_3_EN_MASK (0x1 << 4) 923 | #define RT5677_DMIC_3_EN_SFT 4 924 | #define RT5677_DMIC_3_DIS (0x0 << 4) 925 | #define RT5677_DMIC_3_EN (0x1 << 4) 926 | #define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2) 927 | #define RT5677_DMIC_R_MONO_LH_SFT 2 928 | #define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2) 929 | #define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2) 930 | #define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1) 931 | #define RT5677_DMIC_L_STO4_LH_SFT 1 932 | #define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1) 933 | #define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1) 934 | #define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0) 935 | #define RT5677_DMIC_R_STO4_LH_SFT 0 936 | #define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0) 937 | #define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0) 938 | 939 | /* Digital Microphone Control 2 (0x51) */ 940 | #define RT5677_DMIC_4_EN_MASK (0x1 << 15) 941 | #define RT5677_DMIC_4_EN_SFT 15 942 | #define RT5677_DMIC_4_DIS (0x0 << 15) 943 | #define RT5677_DMIC_4_EN (0x1 << 15) 944 | #define RT5677_DMIC_4L_LH_MASK (0x1 << 7) 945 | #define RT5677_DMIC_4L_LH_SFT 7 946 | #define RT5677_DMIC_4L_LH_FALLING (0x0 << 7) 947 | #define RT5677_DMIC_4L_LH_RISING (0x1 << 7) 948 | #define RT5677_DMIC_4R_LH_MASK (0x1 << 6) 949 | #define RT5677_DMIC_4R_LH_SFT 6 950 | #define RT5677_DMIC_4R_LH_FALLING (0x0 << 6) 951 | #define RT5677_DMIC_4R_LH_RISING (0x1 << 6) 952 | #define RT5677_DMIC_3L_LH_MASK (0x1 << 5) 953 | #define RT5677_DMIC_3L_LH_SFT 5 954 | #define RT5677_DMIC_3L_LH_FALLING (0x0 << 5) 955 | #define RT5677_DMIC_3L_LH_RISING (0x1 << 5) 956 | #define RT5677_DMIC_3R_LH_MASK (0x1 << 4) 957 | #define RT5677_DMIC_3R_LH_SFT 4 958 | #define RT5677_DMIC_3R_LH_FALLING (0x0 << 4) 959 | #define RT5677_DMIC_3R_LH_RISING (0x1 << 4) 960 | #define RT5677_DMIC_2L_LH_MASK (0x1 << 3) 961 | #define RT5677_DMIC_2L_LH_SFT 3 962 | #define RT5677_DMIC_2L_LH_FALLING (0x0 << 3) 963 | #define RT5677_DMIC_2L_LH_RISING (0x1 << 3) 964 | #define RT5677_DMIC_2R_LH_MASK (0x1 << 2) 965 | #define RT5677_DMIC_2R_LH_SFT 2 966 | #define RT5677_DMIC_2R_LH_FALLING (0x0 << 2) 967 | #define RT5677_DMIC_2R_LH_RISING (0x1 << 2) 968 | #define RT5677_DMIC_1L_LH_MASK (0x1 << 1) 969 | #define RT5677_DMIC_1L_LH_SFT 1 970 | #define RT5677_DMIC_1L_LH_FALLING (0x0 << 1) 971 | #define RT5677_DMIC_1L_LH_RISING (0x1 << 1) 972 | #define RT5677_DMIC_1R_LH_MASK (0x1 << 0) 973 | #define RT5677_DMIC_1R_LH_SFT 0 974 | #define RT5677_DMIC_1R_LH_FALLING (0x0 << 0) 975 | #define RT5677_DMIC_1R_LH_RISING (0x1 << 0) 976 | 977 | /* Power Management for Digital 1 (0x61) */ 978 | #define RT5677_PWR_I2S1 (0x1 << 15) 979 | #define RT5677_PWR_I2S1_BIT 15 980 | #define RT5677_PWR_I2S2 (0x1 << 14) 981 | #define RT5677_PWR_I2S2_BIT 14 982 | #define RT5677_PWR_I2S3 (0x1 << 13) 983 | #define RT5677_PWR_I2S3_BIT 13 984 | #define RT5677_PWR_DAC1 (0x1 << 12) 985 | #define RT5677_PWR_DAC1_BIT 12 986 | #define RT5677_PWR_DAC2 (0x1 << 11) 987 | #define RT5677_PWR_DAC2_BIT 11 988 | #define RT5677_PWR_I2S4 (0x1 << 10) 989 | #define RT5677_PWR_I2S4_BIT 10 990 | #define RT5677_PWR_SLB (0x1 << 9) 991 | #define RT5677_PWR_SLB_BIT 9 992 | #define RT5677_PWR_DAC3 (0x1 << 7) 993 | #define RT5677_PWR_DAC3_BIT 7 994 | #define RT5677_PWR_ADCFED2 (0x1 << 4) 995 | #define RT5677_PWR_ADCFED2_BIT 4 996 | #define RT5677_PWR_ADCFED1 (0x1 << 3) 997 | #define RT5677_PWR_ADCFED1_BIT 3 998 | #define RT5677_PWR_ADC_L (0x1 << 2) 999 | #define RT5677_PWR_ADC_L_BIT 2 1000 | #define RT5677_PWR_ADC_R (0x1 << 1) 1001 | #define RT5677_PWR_ADC_R_BIT 1 1002 | #define RT5677_PWR_I2C_MASTER (0x1 << 0) 1003 | #define RT5677_PWR_I2C_MASTER_BIT 0 1004 | 1005 | /* Power Management for Digital 2 (0x62) */ 1006 | #define RT5677_PWR_ADC_S1F (0x1 << 15) 1007 | #define RT5677_PWR_ADC_S1F_BIT 15 1008 | #define RT5677_PWR_ADC_MF_L (0x1 << 14) 1009 | #define RT5677_PWR_ADC_MF_L_BIT 14 1010 | #define RT5677_PWR_ADC_MF_R (0x1 << 13) 1011 | #define RT5677_PWR_ADC_MF_R_BIT 13 1012 | #define RT5677_PWR_DAC_S1F (0x1 << 12) 1013 | #define RT5677_PWR_DAC_S1F_BIT 12 1014 | #define RT5677_PWR_DAC_M2F_L (0x1 << 11) 1015 | #define RT5677_PWR_DAC_M2F_L_BIT 11 1016 | #define RT5677_PWR_DAC_M2F_R (0x1 << 10) 1017 | #define RT5677_PWR_DAC_M2F_R_BIT 10 1018 | #define RT5677_PWR_DAC_M3F_L (0x1 << 9) 1019 | #define RT5677_PWR_DAC_M3F_L_BIT 9 1020 | #define RT5677_PWR_DAC_M3F_R (0x1 << 8) 1021 | #define RT5677_PWR_DAC_M3F_R_BIT 8 1022 | #define RT5677_PWR_DAC_M4F_L (0x1 << 7) 1023 | #define RT5677_PWR_DAC_M4F_L_BIT 7 1024 | #define RT5677_PWR_DAC_M4F_R (0x1 << 6) 1025 | #define RT5677_PWR_DAC_M4F_R_BIT 6 1026 | #define RT5677_PWR_ADC_S2F (0x1 << 5) 1027 | #define RT5677_PWR_ADC_S2F_BIT 5 1028 | #define RT5677_PWR_ADC_S3F (0x1 << 4) 1029 | #define RT5677_PWR_ADC_S3F_BIT 4 1030 | #define RT5677_PWR_ADC_S4F (0x1 << 3) 1031 | #define RT5677_PWR_ADC_S4F_BIT 3 1032 | #define RT5677_PWR_PDM1 (0x1 << 2) 1033 | #define RT5677_PWR_PDM1_BIT 2 1034 | #define RT5677_PWR_PDM2 (0x1 << 1) 1035 | #define RT5677_PWR_PDM2_BIT 1 1036 | 1037 | /* Power Management for Analog 1 (0x63) */ 1038 | #define RT5677_PWR_VREF1 (0x1 << 15) 1039 | #define RT5677_PWR_VREF1_BIT 15 1040 | #define RT5677_PWR_FV1 (0x1 << 14) 1041 | #define RT5677_PWR_FV1_BIT 14 1042 | #define RT5677_PWR_MB (0x1 << 13) 1043 | #define RT5677_PWR_MB_BIT 13 1044 | #define RT5677_PWR_LO1 (0x1 << 12) 1045 | #define RT5677_PWR_LO1_BIT 12 1046 | #define RT5677_PWR_BG (0x1 << 11) 1047 | #define RT5677_PWR_BG_BIT 11 1048 | #define RT5677_PWR_LO2 (0x1 << 10) 1049 | #define RT5677_PWR_LO2_BIT 10 1050 | #define RT5677_PWR_LO3 (0x1 << 9) 1051 | #define RT5677_PWR_LO3_BIT 9 1052 | #define RT5677_PWR_VREF2 (0x1 << 8) 1053 | #define RT5677_PWR_VREF2_BIT 8 1054 | #define RT5677_PWR_FV2 (0x1 << 7) 1055 | #define RT5677_PWR_FV2_BIT 7 1056 | #define RT5677_LDO2_SEL_MASK (0x7 << 4) 1057 | #define RT5677_LDO2_SEL_SFT 4 1058 | #define RT5677_LDO1_SEL_MASK (0x7 << 0) 1059 | #define RT5677_LDO1_SEL_SFT 0 1060 | 1061 | /* Power Management for Analog 2 (0x64) */ 1062 | #define RT5677_PWR_BST1 (0x1 << 15) 1063 | #define RT5677_PWR_BST1_BIT 15 1064 | #define RT5677_PWR_BST2 (0x1 << 14) 1065 | #define RT5677_PWR_BST2_BIT 14 1066 | #define RT5677_PWR_CLK_MB1 (0x1 << 13) 1067 | #define RT5677_PWR_CLK_MB1_BIT 13 1068 | #define RT5677_PWR_SLIM (0x1 << 12) 1069 | #define RT5677_PWR_SLIM_BIT 12 1070 | #define RT5677_PWR_MB1 (0x1 << 11) 1071 | #define RT5677_PWR_MB1_BIT 11 1072 | #define RT5677_PWR_PP_MB1 (0x1 << 10) 1073 | #define RT5677_PWR_PP_MB1_BIT 10 1074 | #define RT5677_PWR_PLL1 (0x1 << 9) 1075 | #define RT5677_PWR_PLL1_BIT 9 1076 | #define RT5677_PWR_PLL2 (0x1 << 8) 1077 | #define RT5677_PWR_PLL2_BIT 8 1078 | #define RT5677_PWR_CORE (0x1 << 7) 1079 | #define RT5677_PWR_CORE_BIT 7 1080 | #define RT5677_PWR_CLK_MB (0x1 << 6) 1081 | #define RT5677_PWR_CLK_MB_BIT 6 1082 | #define RT5677_PWR_BST1_P (0x1 << 5) 1083 | #define RT5677_PWR_BST1_P_BIT 5 1084 | #define RT5677_PWR_BST2_P (0x1 << 4) 1085 | #define RT5677_PWR_BST2_P_BIT 4 1086 | #define RT5677_PWR_IPTV (0x1 << 3) 1087 | #define RT5677_PWR_IPTV_BIT 3 1088 | #define RT5677_PWR_25M_CLK (0x1 << 1) 1089 | #define RT5677_PWR_25M_CLK_BIT 1 1090 | #define RT5677_PWR_LDO1 (0x1 << 0) 1091 | #define RT5677_PWR_LDO1_BIT 0 1092 | 1093 | /* Power Management for DSP (0x65) */ 1094 | #define RT5677_PWR_SR7 (0x1 << 10) 1095 | #define RT5677_PWR_SR7_BIT 10 1096 | #define RT5677_PWR_SR6 (0x1 << 9) 1097 | #define RT5677_PWR_SR6_BIT 9 1098 | #define RT5677_PWR_SR5 (0x1 << 8) 1099 | #define RT5677_PWR_SR5_BIT 8 1100 | #define RT5677_PWR_SR4 (0x1 << 7) 1101 | #define RT5677_PWR_SR4_BIT 7 1102 | #define RT5677_PWR_SR3 (0x1 << 6) 1103 | #define RT5677_PWR_SR3_BIT 6 1104 | #define RT5677_PWR_SR2 (0x1 << 5) 1105 | #define RT5677_PWR_SR2_BIT 5 1106 | #define RT5677_PWR_SR1 (0x1 << 4) 1107 | #define RT5677_PWR_SR1_BIT 4 1108 | #define RT5677_PWR_SR0 (0x1 << 3) 1109 | #define RT5677_PWR_SR0_BIT 3 1110 | #define RT5677_PWR_MLT (0x1 << 2) 1111 | #define RT5677_PWR_MLT_BIT 2 1112 | #define RT5677_PWR_DSP (0x1 << 1) 1113 | #define RT5677_PWR_DSP_BIT 1 1114 | #define RT5677_PWR_DSP_CPU (0x1 << 0) 1115 | #define RT5677_PWR_DSP_CPU_BIT 0 1116 | 1117 | /* Power Status for DSP (0x66) */ 1118 | #define RT5677_PWR_SR7_RDY (0x1 << 9) 1119 | #define RT5677_PWR_SR7_RDY_BIT 9 1120 | #define RT5677_PWR_SR6_RDY (0x1 << 8) 1121 | #define RT5677_PWR_SR6_RDY_BIT 8 1122 | #define RT5677_PWR_SR5_RDY (0x1 << 7) 1123 | #define RT5677_PWR_SR5_RDY_BIT 7 1124 | #define RT5677_PWR_SR4_RDY (0x1 << 6) 1125 | #define RT5677_PWR_SR4_RDY_BIT 6 1126 | #define RT5677_PWR_SR3_RDY (0x1 << 5) 1127 | #define RT5677_PWR_SR3_RDY_BIT 5 1128 | #define RT5677_PWR_SR2_RDY (0x1 << 4) 1129 | #define RT5677_PWR_SR2_RDY_BIT 4 1130 | #define RT5677_PWR_SR1_RDY (0x1 << 3) 1131 | #define RT5677_PWR_SR1_RDY_BIT 3 1132 | #define RT5677_PWR_SR0_RDY (0x1 << 2) 1133 | #define RT5677_PWR_SR0_RDY_BIT 2 1134 | #define RT5677_PWR_MLT_RDY (0x1 << 1) 1135 | #define RT5677_PWR_MLT_RDY_BIT 1 1136 | #define RT5677_PWR_DSP_RDY (0x1 << 0) 1137 | #define RT5677_PWR_DSP_RDY_BIT 0 1138 | 1139 | /* Power Management for DSP (0x67) */ 1140 | #define RT5677_PWR_SLIM_ISO (0x1 << 11) 1141 | #define RT5677_PWR_SLIM_ISO_BIT 11 1142 | #define RT5677_PWR_CORE_ISO (0x1 << 10) 1143 | #define RT5677_PWR_CORE_ISO_BIT 10 1144 | #define RT5677_PWR_DSP_ISO (0x1 << 9) 1145 | #define RT5677_PWR_DSP_ISO_BIT 9 1146 | #define RT5677_PWR_SR7_ISO (0x1 << 8) 1147 | #define RT5677_PWR_SR7_ISO_BIT 8 1148 | #define RT5677_PWR_SR6_ISO (0x1 << 7) 1149 | #define RT5677_PWR_SR6_ISO_BIT 7 1150 | #define RT5677_PWR_SR5_ISO (0x1 << 6) 1151 | #define RT5677_PWR_SR5_ISO_BIT 6 1152 | #define RT5677_PWR_SR4_ISO (0x1 << 5) 1153 | #define RT5677_PWR_SR4_ISO_BIT 5 1154 | #define RT5677_PWR_SR3_ISO (0x1 << 4) 1155 | #define RT5677_PWR_SR3_ISO_BIT 4 1156 | #define RT5677_PWR_SR2_ISO (0x1 << 3) 1157 | #define RT5677_PWR_SR2_ISO_BIT 3 1158 | #define RT5677_PWR_SR1_ISO (0x1 << 2) 1159 | #define RT5677_PWR_SR1_ISO_BIT 2 1160 | #define RT5677_PWR_SR0_ISO (0x1 << 1) 1161 | #define RT5677_PWR_SR0_ISO_BIT 1 1162 | #define RT5677_PWR_MLT_ISO (0x1 << 0) 1163 | #define RT5677_PWR_MLT_ISO_BIT 0 1164 | 1165 | /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */ 1166 | #define RT5677_I2S_MS_MASK (0x1 << 15) 1167 | #define RT5677_I2S_MS_SFT 15 1168 | #define RT5677_I2S_MS_M (0x0 << 15) 1169 | #define RT5677_I2S_MS_S (0x1 << 15) 1170 | #define RT5677_I2S_O_CP_MASK (0x3 << 10) 1171 | #define RT5677_I2S_O_CP_SFT 10 1172 | #define RT5677_I2S_O_CP_OFF (0x0 << 10) 1173 | #define RT5677_I2S_O_CP_U_LAW (0x1 << 10) 1174 | #define RT5677_I2S_O_CP_A_LAW (0x2 << 10) 1175 | #define RT5677_I2S_I_CP_MASK (0x3 << 8) 1176 | #define RT5677_I2S_I_CP_SFT 8 1177 | #define RT5677_I2S_I_CP_OFF (0x0 << 8) 1178 | #define RT5677_I2S_I_CP_U_LAW (0x1 << 8) 1179 | #define RT5677_I2S_I_CP_A_LAW (0x2 << 8) 1180 | #define RT5677_I2S_BP_MASK (0x1 << 7) 1181 | #define RT5677_I2S_BP_SFT 7 1182 | #define RT5677_I2S_BP_NOR (0x0 << 7) 1183 | #define RT5677_I2S_BP_INV (0x1 << 7) 1184 | #define RT5677_I2S_DL_MASK (0x3 << 2) 1185 | #define RT5677_I2S_DL_SFT 2 1186 | #define RT5677_I2S_DL_16 (0x0 << 2) 1187 | #define RT5677_I2S_DL_20 (0x1 << 2) 1188 | #define RT5677_I2S_DL_24 (0x2 << 2) 1189 | #define RT5677_I2S_DL_8 (0x3 << 2) 1190 | #define RT5677_I2S_DF_MASK (0x3 << 0) 1191 | #define RT5677_I2S_DF_SFT 0 1192 | #define RT5677_I2S_DF_I2S (0x0 << 0) 1193 | #define RT5677_I2S_DF_LEFT (0x1 << 0) 1194 | #define RT5677_I2S_DF_PCM_A (0x2 << 0) 1195 | #define RT5677_I2S_DF_PCM_B (0x3 << 0) 1196 | 1197 | /* Clock Tree Control 1 (0x73) */ 1198 | #define RT5677_I2S_PD1_MASK (0x7 << 12) 1199 | #define RT5677_I2S_PD1_SFT 12 1200 | #define RT5677_I2S_PD1_1 (0x0 << 12) 1201 | #define RT5677_I2S_PD1_2 (0x1 << 12) 1202 | #define RT5677_I2S_PD1_3 (0x2 << 12) 1203 | #define RT5677_I2S_PD1_4 (0x3 << 12) 1204 | #define RT5677_I2S_PD1_6 (0x4 << 12) 1205 | #define RT5677_I2S_PD1_8 (0x5 << 12) 1206 | #define RT5677_I2S_PD1_12 (0x6 << 12) 1207 | #define RT5677_I2S_PD1_16 (0x7 << 12) 1208 | #define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11) 1209 | #define RT5677_I2S_BCLK_MS2_SFT 11 1210 | #define RT5677_I2S_BCLK_MS2_32 (0x0 << 11) 1211 | #define RT5677_I2S_BCLK_MS2_64 (0x1 << 11) 1212 | #define RT5677_I2S_PD2_MASK (0x7 << 8) 1213 | #define RT5677_I2S_PD2_SFT 8 1214 | #define RT5677_I2S_PD2_1 (0x0 << 8) 1215 | #define RT5677_I2S_PD2_2 (0x1 << 8) 1216 | #define RT5677_I2S_PD2_3 (0x2 << 8) 1217 | #define RT5677_I2S_PD2_4 (0x3 << 8) 1218 | #define RT5677_I2S_PD2_6 (0x4 << 8) 1219 | #define RT5677_I2S_PD2_8 (0x5 << 8) 1220 | #define RT5677_I2S_PD2_12 (0x6 << 8) 1221 | #define RT5677_I2S_PD2_16 (0x7 << 8) 1222 | #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7) 1223 | #define RT5677_I2S_BCLK_MS3_SFT 7 1224 | #define RT5677_I2S_BCLK_MS3_32 (0x0 << 7) 1225 | #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7) 1226 | #define RT5677_I2S_PD3_MASK (0x7 << 4) 1227 | #define RT5677_I2S_PD3_SFT 4 1228 | #define RT5677_I2S_PD3_1 (0x0 << 4) 1229 | #define RT5677_I2S_PD3_2 (0x1 << 4) 1230 | #define RT5677_I2S_PD3_3 (0x2 << 4) 1231 | #define RT5677_I2S_PD3_4 (0x3 << 4) 1232 | #define RT5677_I2S_PD3_6 (0x4 << 4) 1233 | #define RT5677_I2S_PD3_8 (0x5 << 4) 1234 | #define RT5677_I2S_PD3_12 (0x6 << 4) 1235 | #define RT5677_I2S_PD3_16 (0x7 << 4) 1236 | #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3) 1237 | #define RT5677_I2S_BCLK_MS4_SFT 3 1238 | #define RT5677_I2S_BCLK_MS4_32 (0x0 << 3) 1239 | #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3) 1240 | #define RT5677_I2S_PD4_MASK (0x7 << 0) 1241 | #define RT5677_I2S_PD4_SFT 0 1242 | #define RT5677_I2S_PD4_1 (0x0 << 0) 1243 | #define RT5677_I2S_PD4_2 (0x1 << 0) 1244 | #define RT5677_I2S_PD4_3 (0x2 << 0) 1245 | #define RT5677_I2S_PD4_4 (0x3 << 0) 1246 | #define RT5677_I2S_PD4_6 (0x4 << 0) 1247 | #define RT5677_I2S_PD4_8 (0x5 << 0) 1248 | #define RT5677_I2S_PD4_12 (0x6 << 0) 1249 | #define RT5677_I2S_PD4_16 (0x7 << 0) 1250 | 1251 | /* Clock Tree Control 2 (0x74) */ 1252 | #define RT5677_I2S_PD5_MASK (0x7 << 12) 1253 | #define RT5677_I2S_PD5_SFT 12 1254 | #define RT5677_I2S_PD5_1 (0x0 << 12) 1255 | #define RT5677_I2S_PD5_2 (0x1 << 12) 1256 | #define RT5677_I2S_PD5_3 (0x2 << 12) 1257 | #define RT5677_I2S_PD5_4 (0x3 << 12) 1258 | #define RT5677_I2S_PD5_6 (0x4 << 12) 1259 | #define RT5677_I2S_PD5_8 (0x5 << 12) 1260 | #define RT5677_I2S_PD5_12 (0x6 << 12) 1261 | #define RT5677_I2S_PD5_16 (0x7 << 12) 1262 | #define RT5677_I2S_PD6_MASK (0x7 << 8) 1263 | #define RT5677_I2S_PD6_SFT 8 1264 | #define RT5677_I2S_PD6_1 (0x0 << 8) 1265 | #define RT5677_I2S_PD6_2 (0x1 << 8) 1266 | #define RT5677_I2S_PD6_3 (0x2 << 8) 1267 | #define RT5677_I2S_PD6_4 (0x3 << 8) 1268 | #define RT5677_I2S_PD6_6 (0x4 << 8) 1269 | #define RT5677_I2S_PD6_8 (0x5 << 8) 1270 | #define RT5677_I2S_PD6_12 (0x6 << 8) 1271 | #define RT5677_I2S_PD6_16 (0x7 << 8) 1272 | #define RT5677_I2S_PD7_MASK (0x7 << 4) 1273 | #define RT5677_I2S_PD7_SFT 4 1274 | #define RT5677_I2S_PD7_1 (0x0 << 4) 1275 | #define RT5677_I2S_PD7_2 (0x1 << 4) 1276 | #define RT5677_I2S_PD7_3 (0x2 << 4) 1277 | #define RT5677_I2S_PD7_4 (0x3 << 4) 1278 | #define RT5677_I2S_PD7_6 (0x4 << 4) 1279 | #define RT5677_I2S_PD7_8 (0x5 << 4) 1280 | #define RT5677_I2S_PD7_12 (0x6 << 4) 1281 | #define RT5677_I2S_PD7_16 (0x7 << 4) 1282 | #define RT5677_I2S_PD8_MASK (0x7 << 0) 1283 | #define RT5677_I2S_PD8_SFT 0 1284 | #define RT5677_I2S_PD8_1 (0x0 << 0) 1285 | #define RT5677_I2S_PD8_2 (0x1 << 0) 1286 | #define RT5677_I2S_PD8_3 (0x2 << 0) 1287 | #define RT5677_I2S_PD8_4 (0x3 << 0) 1288 | #define RT5677_I2S_PD8_6 (0x4 << 0) 1289 | #define RT5677_I2S_PD8_8 (0x5 << 0) 1290 | #define RT5677_I2S_PD8_12 (0x6 << 0) 1291 | #define RT5677_I2S_PD8_16 (0x7 << 0) 1292 | 1293 | /* Clock Tree Control 3 (0x75) */ 1294 | #define RT5677_DSP_ASRC_O_MASK (0x3 << 6) 1295 | #define RT5677_DSP_ASRC_O_SFT 6 1296 | #define RT5677_DSP_ASRC_O_1_0 (0x0 << 6) 1297 | #define RT5677_DSP_ASRC_O_1_5 (0x1 << 6) 1298 | #define RT5677_DSP_ASRC_O_2_0 (0x2 << 6) 1299 | #define RT5677_DSP_ASRC_O_3_0 (0x3 << 6) 1300 | #define RT5677_DSP_ASRC_I_MASK (0x3 << 4) 1301 | #define RT5677_DSP_ASRC_I_SFT 4 1302 | #define RT5677_DSP_ASRC_I_1_0 (0x0 << 4) 1303 | #define RT5677_DSP_ASRC_I_1_5 (0x1 << 4) 1304 | #define RT5677_DSP_ASRC_I_2_0 (0x2 << 4) 1305 | #define RT5677_DSP_ASRC_I_3_0 (0x3 << 4) 1306 | #define RT5677_DSP_BUS_PD_MASK (0x7 << 0) 1307 | #define RT5677_DSP_BUS_PD_SFT 0 1308 | #define RT5677_DSP_BUS_PD_1 (0x0 << 0) 1309 | #define RT5677_DSP_BUS_PD_2 (0x1 << 0) 1310 | #define RT5677_DSP_BUS_PD_3 (0x2 << 0) 1311 | #define RT5677_DSP_BUS_PD_4 (0x3 << 0) 1312 | #define RT5677_DSP_BUS_PD_6 (0x4 << 0) 1313 | #define RT5677_DSP_BUS_PD_8 (0x5 << 0) 1314 | #define RT5677_DSP_BUS_PD_12 (0x6 << 0) 1315 | #define RT5677_DSP_BUS_PD_16 (0x7 << 0) 1316 | 1317 | #define RT5677_PLL_INP_MAX 40000000 1318 | #define RT5677_PLL_INP_MIN 2048000 1319 | /* PLL M/N/K Code Control 1 (0x7a 0x7c) */ 1320 | #define RT5677_PLL_N_MAX 0x1ff 1321 | #define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7) 1322 | #define RT5677_PLL_N_SFT 7 1323 | #define RT5677_PLL_K_BP (0x1 << 5) 1324 | #define RT5677_PLL_K_BP_SFT 5 1325 | #define RT5677_PLL_K_MAX 0x1f 1326 | #define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX) 1327 | #define RT5677_PLL_K_SFT 0 1328 | 1329 | /* PLL M/N/K Code Control 2 (0x7b 0x7d) */ 1330 | #define RT5677_PLL_M_MAX 0xf 1331 | #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12) 1332 | #define RT5677_PLL_M_SFT 12 1333 | #define RT5677_PLL_M_BP (0x1 << 11) 1334 | #define RT5677_PLL_M_BP_SFT 11 1335 | #define RT5677_PLL_UPDATE_PLL1 (0x1 << 1) 1336 | #define RT5677_PLL_UPDATE_PLL1_SFT 1 1337 | 1338 | /* Global Clock Control 1 (0x80) */ 1339 | #define RT5677_SCLK_SRC_MASK (0x3 << 14) 1340 | #define RT5677_SCLK_SRC_SFT 14 1341 | #define RT5677_SCLK_SRC_MCLK (0x0 << 14) 1342 | #define RT5677_SCLK_SRC_PLL1 (0x1 << 14) 1343 | #define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */ 1344 | #define RT5677_SCLK_SRC_SLIM (0x3 << 14) 1345 | #define RT5677_PLL1_SRC_MASK (0x7 << 11) 1346 | #define RT5677_PLL1_SRC_SFT 11 1347 | #define RT5677_PLL1_SRC_MCLK (0x0 << 11) 1348 | #define RT5677_PLL1_SRC_BCLK1 (0x1 << 11) 1349 | #define RT5677_PLL1_SRC_BCLK2 (0x2 << 11) 1350 | #define RT5677_PLL1_SRC_BCLK3 (0x3 << 11) 1351 | #define RT5677_PLL1_SRC_BCLK4 (0x4 << 11) 1352 | #define RT5677_PLL1_SRC_RCCLK (0x5 << 11) 1353 | #define RT5677_PLL1_SRC_SLIM (0x6 << 11) 1354 | #define RT5677_MCLK_SRC_MASK (0x1 << 10) 1355 | #define RT5677_MCLK_SRC_SFT 10 1356 | #define RT5677_MCLK1_SRC (0x0 << 10) 1357 | #define RT5677_MCLK2_SRC (0x1 << 10) 1358 | #define RT5677_PLL1_PD_MASK (0x1 << 8) 1359 | #define RT5677_PLL1_PD_SFT 8 1360 | #define RT5677_PLL1_PD_1 (0x0 << 8) 1361 | #define RT5677_PLL1_PD_2 (0x1 << 8) 1362 | #define RT5677_DAC_OSR_MASK (0x3 << 6) 1363 | #define RT5677_DAC_OSR_SFT 6 1364 | #define RT5677_DAC_OSR_128 (0x0 << 6) 1365 | #define RT5677_DAC_OSR_64 (0x1 << 6) 1366 | #define RT5677_DAC_OSR_32 (0x2 << 6) 1367 | #define RT5677_ADC_OSR_MASK (0x3 << 4) 1368 | #define RT5677_ADC_OSR_SFT 4 1369 | #define RT5677_ADC_OSR_128 (0x0 << 4) 1370 | #define RT5677_ADC_OSR_64 (0x1 << 4) 1371 | #define RT5677_ADC_OSR_32 (0x2 << 4) 1372 | 1373 | /* Global Clock Control 2 (0x81) */ 1374 | #define RT5677_PLL2_PR_SRC_MASK (0x1 << 15) 1375 | #define RT5677_PLL2_PR_SRC_SFT 15 1376 | #define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15) 1377 | #define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15) 1378 | #define RT5677_PLL2_SRC_MASK (0x7 << 12) 1379 | #define RT5677_PLL2_SRC_SFT 12 1380 | #define RT5677_PLL2_SRC_MCLK (0x0 << 12) 1381 | #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12) 1382 | #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12) 1383 | #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12) 1384 | #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12) 1385 | #define RT5677_PLL2_SRC_RCCLK (0x5 << 12) 1386 | #define RT5677_PLL2_SRC_SLIM (0x6 << 12) 1387 | #define RT5677_DSP_ASRC_O_SRC (0x3 << 10) 1388 | #define RT5677_DSP_ASRC_O_SRC_SFT 10 1389 | #define RT5677_DSP_ASRC_O_MCLK (0x0 << 10) 1390 | #define RT5677_DSP_ASRC_O_PLL1 (0x1 << 10) 1391 | #define RT5677_DSP_ASRC_O_SLIM (0x2 << 10) 1392 | #define RT5677_DSP_ASRC_O_RCCLK (0x3 << 10) 1393 | #define RT5677_DSP_ASRC_I_SRC (0x3 << 8) 1394 | #define RT5677_DSP_ASRC_I_SRC_SFT 8 1395 | #define RT5677_DSP_ASRC_I_MCLK (0x0 << 8) 1396 | #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8) 1397 | #define RT5677_DSP_ASRC_I_SLIM (0x2 << 8) 1398 | #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8) 1399 | #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7) 1400 | #define RT5677_DSP_CLK_SRC_SFT 7 1401 | #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7) 1402 | #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7) 1403 | 1404 | /* ASRC Control 3 (0x85) */ 1405 | #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12) 1406 | #define RT5677_DA_STO_CLK_SEL_SFT 12 1407 | #define RT5677_DA_MONO2L_CLK_SEL_MASK (0xf << 4) 1408 | #define RT5677_DA_MONO2L_CLK_SEL_SFT 4 1409 | #define RT5677_DA_MONO2R_CLK_SEL_MASK (0xf << 0) 1410 | #define RT5677_DA_MONO2R_CLK_SEL_SFT 0 1411 | 1412 | /* ASRC Control 4 (0x86) */ 1413 | #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12) 1414 | #define RT5677_DA_MONO3L_CLK_SEL_SFT 12 1415 | #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8) 1416 | #define RT5677_DA_MONO3R_CLK_SEL_SFT 8 1417 | #define RT5677_DA_MONO4L_CLK_SEL_MASK (0xf << 4) 1418 | #define RT5677_DA_MONO4L_CLK_SEL_SFT 4 1419 | #define RT5677_DA_MONO4R_CLK_SEL_MASK (0xf << 0) 1420 | #define RT5677_DA_MONO4R_CLK_SEL_SFT 0 1421 | 1422 | /* ASRC Control 5 (0x87) */ 1423 | #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12) 1424 | #define RT5677_AD_STO1_CLK_SEL_SFT 12 1425 | #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8) 1426 | #define RT5677_AD_STO2_CLK_SEL_SFT 8 1427 | #define RT5677_AD_STO3_CLK_SEL_MASK (0xf << 4) 1428 | #define RT5677_AD_STO3_CLK_SEL_SFT 4 1429 | #define RT5677_AD_STO4_CLK_SEL_MASK (0xf << 0) 1430 | #define RT5677_AD_STO4_CLK_SEL_SFT 0 1431 | 1432 | /* ASRC Control 6 (0x88) */ 1433 | #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12) 1434 | #define RT5677_AD_MONOL_CLK_SEL_SFT 12 1435 | #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8) 1436 | #define RT5677_AD_MONOR_CLK_SEL_SFT 8 1437 | 1438 | /* ASRC Control 7 (0x89) */ 1439 | #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12) 1440 | #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12 1441 | #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8) 1442 | #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8 1443 | 1444 | /* ASRC Control 8 (0x8a) */ 1445 | #define RT5677_I2S1_CLK_SEL_MASK (0xf << 12) 1446 | #define RT5677_I2S1_CLK_SEL_SFT 12 1447 | #define RT5677_I2S2_CLK_SEL_MASK (0xf << 8) 1448 | #define RT5677_I2S2_CLK_SEL_SFT 8 1449 | #define RT5677_I2S3_CLK_SEL_MASK (0xf << 4) 1450 | #define RT5677_I2S3_CLK_SEL_SFT 4 1451 | #define RT5677_I2S4_CLK_SEL_MASK (0xf) 1452 | #define RT5677_I2S4_CLK_SEL_SFT 0 1453 | 1454 | /* VAD Function Control 1 (0x9c) */ 1455 | #define RT5677_VAD_MIN_DUR_MASK (0x3 << 13) 1456 | #define RT5677_VAD_MIN_DUR_SFT 13 1457 | #define RT5677_VAD_ADPCM_BYPASS (1 << 10) 1458 | #define RT5677_VAD_ADPCM_BYPASS_BIT 10 1459 | #define RT5677_VAD_FG2ENC (1 << 9) 1460 | #define RT5677_VAD_FG2ENC_BIT 9 1461 | #define RT5677_VAD_BUF_OW (1 << 8) 1462 | #define RT5677_VAD_BUF_OW_BIT 8 1463 | #define RT5677_VAD_CLR_FLAG (1 << 7) 1464 | #define RT5677_VAD_CLR_FLAG_BIT 7 1465 | #define RT5677_VAD_BUF_POP (1 << 6) 1466 | #define RT5677_VAD_BUF_POP_BIT 6 1467 | #define RT5677_VAD_BUF_PUSH (1 << 5) 1468 | #define RT5677_VAD_BUF_PUSH_BIT 5 1469 | #define RT5677_VAD_DET_ENABLE (1 << 4) 1470 | #define RT5677_VAD_DET_ENABLE_BIT 4 1471 | #define RT5677_VAD_FUNC_ENABLE (1 << 3) 1472 | #define RT5677_VAD_FUNC_ENABLE_BIT 3 1473 | #define RT5677_VAD_FUNC_RESET (1 << 2) 1474 | #define RT5677_VAD_FUNC_RESET_BIT 2 1475 | 1476 | /* VAD Function Control 4 (0x9f) */ 1477 | #define RT5677_VAD_OUT_SRC_RATE_MASK (0x1 << 11) 1478 | #define RT5677_VAD_OUT_SRC_RATE_SFT 11 1479 | #define RT5677_VAD_OUT_SRC_MASK (0x1 << 10) 1480 | #define RT5677_VAD_OUT_SRC_SFT 10 1481 | #define RT5677_VAD_SRC_MASK (0x3 << 8) 1482 | #define RT5677_VAD_SRC_SFT 8 1483 | #define RT5677_VAD_LV_DIFF_MASK (0xff << 0) 1484 | #define RT5677_VAD_LV_DIFF_SFT 0 1485 | 1486 | /* DSP InBound Control (0xa3) */ 1487 | #define RT5677_IB01_SRC_MASK (0x7 << 12) 1488 | #define RT5677_IB01_SRC_SFT 12 1489 | #define RT5677_IB23_SRC_MASK (0x7 << 8) 1490 | #define RT5677_IB23_SRC_SFT 8 1491 | #define RT5677_IB45_SRC_MASK (0x7 << 4) 1492 | #define RT5677_IB45_SRC_SFT 4 1493 | #define RT5677_IB6_SRC_MASK (0x7 << 0) 1494 | #define RT5677_IB6_SRC_SFT 0 1495 | 1496 | /* DSP InBound Control (0xa4) */ 1497 | #define RT5677_IB7_SRC_MASK (0x7 << 12) 1498 | #define RT5677_IB7_SRC_SFT 12 1499 | #define RT5677_IB8_SRC_MASK (0x7 << 8) 1500 | #define RT5677_IB8_SRC_SFT 8 1501 | #define RT5677_IB9_SRC_MASK (0x7 << 4) 1502 | #define RT5677_IB9_SRC_SFT 4 1503 | 1504 | /* DSP In/OutBound Control (0xa5) */ 1505 | #define RT5677_SEL_SRC_OB23 (0x1 << 4) 1506 | #define RT5677_SEL_SRC_OB23_SFT 4 1507 | #define RT5677_SEL_SRC_OB01 (0x1 << 3) 1508 | #define RT5677_SEL_SRC_OB01_SFT 3 1509 | #define RT5677_SEL_SRC_IB45 (0x1 << 2) 1510 | #define RT5677_SEL_SRC_IB45_SFT 2 1511 | #define RT5677_SEL_SRC_IB23 (0x1 << 1) 1512 | #define RT5677_SEL_SRC_IB23_SFT 1 1513 | #define RT5677_SEL_SRC_IB01 (0x1 << 0) 1514 | #define RT5677_SEL_SRC_IB01_SFT 0 1515 | 1516 | /* Jack Detect Control 1 (0xb5) */ 1517 | #define RT5677_SEL_GPIO_JD1_MASK (0x3 << 14) 1518 | #define RT5677_SEL_GPIO_JD1_SFT 14 1519 | #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12) 1520 | #define RT5677_SEL_GPIO_JD2_SFT 12 1521 | #define RT5677_SEL_GPIO_JD3_MASK (0x3 << 10) 1522 | #define RT5677_SEL_GPIO_JD3_SFT 10 1523 | 1524 | /* IRQ Control 1 (0xbd) */ 1525 | #define RT5677_STA_GPIO_JD1 (0x1 << 15) 1526 | #define RT5677_STA_GPIO_JD1_SFT 15 1527 | #define RT5677_EN_IRQ_GPIO_JD1 (0x1 << 14) 1528 | #define RT5677_EN_IRQ_GPIO_JD1_SFT 14 1529 | #define RT5677_EN_GPIO_JD1_STICKY (0x1 << 13) 1530 | #define RT5677_EN_GPIO_JD1_STICKY_SFT 13 1531 | #define RT5677_INV_GPIO_JD1 (0x1 << 12) 1532 | #define RT5677_INV_GPIO_JD1_SFT 12 1533 | #define RT5677_STA_GPIO_JD2 (0x1 << 11) 1534 | #define RT5677_STA_GPIO_JD2_SFT 11 1535 | #define RT5677_EN_IRQ_GPIO_JD2 (0x1 << 10) 1536 | #define RT5677_EN_IRQ_GPIO_JD2_SFT 10 1537 | #define RT5677_EN_GPIO_JD2_STICKY (0x1 << 9) 1538 | #define RT5677_EN_GPIO_JD2_STICKY_SFT 9 1539 | #define RT5677_INV_GPIO_JD2 (0x1 << 8) 1540 | #define RT5677_INV_GPIO_JD2_SFT 8 1541 | #define RT5677_STA_MICBIAS1_OVCD (0x1 << 7) 1542 | #define RT5677_STA_MICBIAS1_OVCD_SFT 7 1543 | #define RT5677_EN_IRQ_MICBIAS1_OVCD (0x1 << 6) 1544 | #define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT 6 1545 | #define RT5677_EN_MICBIAS1_OVCD_STICKY (0x1 << 5) 1546 | #define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT 5 1547 | #define RT5677_INV_MICBIAS1_OVCD (0x1 << 4) 1548 | #define RT5677_INV_MICBIAS1_OVCD_SFT 4 1549 | #define RT5677_STA_GPIO_JD3 (0x1 << 3) 1550 | #define RT5677_STA_GPIO_JD3_SFT 3 1551 | #define RT5677_EN_IRQ_GPIO_JD3 (0x1 << 2) 1552 | #define RT5677_EN_IRQ_GPIO_JD3_SFT 2 1553 | #define RT5677_EN_GPIO_JD3_STICKY (0x1 << 1) 1554 | #define RT5677_EN_GPIO_JD3_STICKY_SFT 1 1555 | #define RT5677_INV_GPIO_JD3 (0x1 << 0) 1556 | #define RT5677_INV_GPIO_JD3_SFT 0 1557 | 1558 | /* GPIO status (0xbf) */ 1559 | #define RT5677_GPIO6_STATUS_MASK (0x1 << 5) 1560 | #define RT5677_GPIO6_STATUS_SFT 5 1561 | #define RT5677_GPIO5_STATUS_MASK (0x1 << 4) 1562 | #define RT5677_GPIO5_STATUS_SFT 4 1563 | #define RT5677_GPIO4_STATUS_MASK (0x1 << 3) 1564 | #define RT5677_GPIO4_STATUS_SFT 3 1565 | #define RT5677_GPIO3_STATUS_MASK (0x1 << 2) 1566 | #define RT5677_GPIO3_STATUS_SFT 2 1567 | #define RT5677_GPIO2_STATUS_MASK (0x1 << 1) 1568 | #define RT5677_GPIO2_STATUS_SFT 1 1569 | #define RT5677_GPIO1_STATUS_MASK (0x1 << 0) 1570 | #define RT5677_GPIO1_STATUS_SFT 0 1571 | 1572 | /* GPIO Control 1 (0xc0) */ 1573 | #define RT5677_GPIO1_PIN_MASK (0x1 << 15) 1574 | #define RT5677_GPIO1_PIN_SFT 15 1575 | #define RT5677_GPIO1_PIN_GPIO1 (0x0 << 15) 1576 | #define RT5677_GPIO1_PIN_IRQ (0x1 << 15) 1577 | #define RT5677_IPTV_MODE_MASK (0x1 << 14) 1578 | #define RT5677_IPTV_MODE_SFT 14 1579 | #define RT5677_IPTV_MODE_GPIO (0x0 << 14) 1580 | #define RT5677_IPTV_MODE_IPTV (0x1 << 14) 1581 | #define RT5677_FUNC_MODE_MASK (0x1 << 13) 1582 | #define RT5677_FUNC_MODE_SFT 13 1583 | #define RT5677_FUNC_MODE_DMIC_GPIO (0x0 << 13) 1584 | #define RT5677_FUNC_MODE_JTAG (0x1 << 13) 1585 | 1586 | /* GPIO Control 2 (0xc1) */ 1587 | #define RT5677_GPIO5_DIR_MASK (0x1 << 14) 1588 | #define RT5677_GPIO5_DIR_SFT 14 1589 | #define RT5677_GPIO5_DIR_IN (0x0 << 14) 1590 | #define RT5677_GPIO5_DIR_OUT (0x1 << 14) 1591 | #define RT5677_GPIO5_OUT_MASK (0x1 << 13) 1592 | #define RT5677_GPIO5_OUT_SFT 13 1593 | #define RT5677_GPIO5_OUT_LO (0x0 << 13) 1594 | #define RT5677_GPIO5_OUT_HI (0x1 << 13) 1595 | #define RT5677_GPIO5_P_MASK (0x1 << 12) 1596 | #define RT5677_GPIO5_P_SFT 12 1597 | #define RT5677_GPIO5_P_NOR (0x0 << 12) 1598 | #define RT5677_GPIO5_P_INV (0x1 << 12) 1599 | #define RT5677_GPIO4_DIR_MASK (0x1 << 11) 1600 | #define RT5677_GPIO4_DIR_SFT 11 1601 | #define RT5677_GPIO4_DIR_IN (0x0 << 11) 1602 | #define RT5677_GPIO4_DIR_OUT (0x1 << 11) 1603 | #define RT5677_GPIO4_OUT_MASK (0x1 << 10) 1604 | #define RT5677_GPIO4_OUT_SFT 10 1605 | #define RT5677_GPIO4_OUT_LO (0x0 << 10) 1606 | #define RT5677_GPIO4_OUT_HI (0x1 << 10) 1607 | #define RT5677_GPIO4_P_MASK (0x1 << 9) 1608 | #define RT5677_GPIO4_P_SFT 9 1609 | #define RT5677_GPIO4_P_NOR (0x0 << 9) 1610 | #define RT5677_GPIO4_P_INV (0x1 << 9) 1611 | #define RT5677_GPIO3_DIR_MASK (0x1 << 8) 1612 | #define RT5677_GPIO3_DIR_SFT 8 1613 | #define RT5677_GPIO3_DIR_IN (0x0 << 8) 1614 | #define RT5677_GPIO3_DIR_OUT (0x1 << 8) 1615 | #define RT5677_GPIO3_OUT_MASK (0x1 << 7) 1616 | #define RT5677_GPIO3_OUT_SFT 7 1617 | #define RT5677_GPIO3_OUT_LO (0x0 << 7) 1618 | #define RT5677_GPIO3_OUT_HI (0x1 << 7) 1619 | #define RT5677_GPIO3_P_MASK (0x1 << 6) 1620 | #define RT5677_GPIO3_P_SFT 6 1621 | #define RT5677_GPIO3_P_NOR (0x0 << 6) 1622 | #define RT5677_GPIO3_P_INV (0x1 << 6) 1623 | #define RT5677_GPIO2_DIR_MASK (0x1 << 5) 1624 | #define RT5677_GPIO2_DIR_SFT 5 1625 | #define RT5677_GPIO2_DIR_IN (0x0 << 5) 1626 | #define RT5677_GPIO2_DIR_OUT (0x1 << 5) 1627 | #define RT5677_GPIO2_OUT_MASK (0x1 << 4) 1628 | #define RT5677_GPIO2_OUT_SFT 4 1629 | #define RT5677_GPIO2_OUT_LO (0x0 << 4) 1630 | #define RT5677_GPIO2_OUT_HI (0x1 << 4) 1631 | #define RT5677_GPIO2_P_MASK (0x1 << 3) 1632 | #define RT5677_GPIO2_P_SFT 3 1633 | #define RT5677_GPIO2_P_NOR (0x0 << 3) 1634 | #define RT5677_GPIO2_P_INV (0x1 << 3) 1635 | #define RT5677_GPIO1_DIR_MASK (0x1 << 2) 1636 | #define RT5677_GPIO1_DIR_SFT 2 1637 | #define RT5677_GPIO1_DIR_IN (0x0 << 2) 1638 | #define RT5677_GPIO1_DIR_OUT (0x1 << 2) 1639 | #define RT5677_GPIO1_OUT_MASK (0x1 << 1) 1640 | #define RT5677_GPIO1_OUT_SFT 1 1641 | #define RT5677_GPIO1_OUT_LO (0x0 << 1) 1642 | #define RT5677_GPIO1_OUT_HI (0x1 << 1) 1643 | #define RT5677_GPIO1_P_MASK (0x1 << 0) 1644 | #define RT5677_GPIO1_P_SFT 0 1645 | #define RT5677_GPIO1_P_NOR (0x0 << 0) 1646 | #define RT5677_GPIO1_P_INV (0x1 << 0) 1647 | 1648 | /* GPIO Control 3 (0xc2) */ 1649 | #define RT5677_GPIO6_DIR_MASK (0x1 << 2) 1650 | #define RT5677_GPIO6_DIR_SFT 2 1651 | #define RT5677_GPIO6_DIR_IN (0x0 << 2) 1652 | #define RT5677_GPIO6_DIR_OUT (0x1 << 2) 1653 | #define RT5677_GPIO6_OUT_MASK (0x1 << 1) 1654 | #define RT5677_GPIO6_OUT_SFT 1 1655 | #define RT5677_GPIO6_OUT_LO (0x0 << 1) 1656 | #define RT5677_GPIO6_OUT_HI (0x1 << 1) 1657 | #define RT5677_GPIO6_P_MASK (0x1 << 0) 1658 | #define RT5677_GPIO6_P_SFT 0 1659 | #define RT5677_GPIO6_P_NOR (0x0 << 0) 1660 | #define RT5677_GPIO6_P_INV (0x1 << 0) 1661 | 1662 | /* General Control (0xfa) */ 1663 | #define RT5677_IRQ_DEBOUNCE_SEL_MASK (0x3 << 3) 1664 | #define RT5677_IRQ_DEBOUNCE_SEL_MCLK (0x0 << 3) 1665 | #define RT5677_IRQ_DEBOUNCE_SEL_RC (0x1 << 3) 1666 | #define RT5677_IRQ_DEBOUNCE_SEL_SLIM (0x2 << 3) 1667 | 1668 | /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */ 1669 | #define RT5677_DSP_IB_01_H (0x1 << 15) 1670 | #define RT5677_DSP_IB_01_H_SFT 15 1671 | #define RT5677_DSP_IB_23_H (0x1 << 14) 1672 | #define RT5677_DSP_IB_23_H_SFT 14 1673 | #define RT5677_DSP_IB_45_H (0x1 << 13) 1674 | #define RT5677_DSP_IB_45_H_SFT 13 1675 | #define RT5677_DSP_IB_6_H (0x1 << 12) 1676 | #define RT5677_DSP_IB_6_H_SFT 12 1677 | #define RT5677_DSP_IB_7_H (0x1 << 11) 1678 | #define RT5677_DSP_IB_7_H_SFT 11 1679 | #define RT5677_DSP_IB_8_H (0x1 << 10) 1680 | #define RT5677_DSP_IB_8_H_SFT 10 1681 | #define RT5677_DSP_IB_9_H (0x1 << 9) 1682 | #define RT5677_DSP_IB_9_H_SFT 9 1683 | #define RT5677_DSP_IB_01_L (0x1 << 7) 1684 | #define RT5677_DSP_IB_01_L_SFT 7 1685 | #define RT5677_DSP_IB_23_L (0x1 << 6) 1686 | #define RT5677_DSP_IB_23_L_SFT 6 1687 | #define RT5677_DSP_IB_45_L (0x1 << 5) 1688 | #define RT5677_DSP_IB_45_L_SFT 5 1689 | #define RT5677_DSP_IB_6_L (0x1 << 4) 1690 | #define RT5677_DSP_IB_6_L_SFT 4 1691 | #define RT5677_DSP_IB_7_L (0x1 << 3) 1692 | #define RT5677_DSP_IB_7_L_SFT 3 1693 | #define RT5677_DSP_IB_8_L (0x1 << 2) 1694 | #define RT5677_DSP_IB_8_L_SFT 2 1695 | #define RT5677_DSP_IB_9_L (0x1 << 1) 1696 | #define RT5677_DSP_IB_9_L_SFT 1 1697 | #define RT5677_SW_RESET 0x10EC 1698 | /* System Clock Source */ 1699 | enum { 1700 | RT5677_SCLK_S_MCLK, 1701 | RT5677_SCLK_S_PLL1, 1702 | RT5677_SCLK_S_RCCLK, 1703 | }; 1704 | /* PLL1 Source */ 1705 | enum { 1706 | RT5677_PLL1_S_MCLK, 1707 | RT5677_PLL1_S_BCLK1, 1708 | RT5677_PLL1_S_BCLK2, 1709 | RT5677_PLL1_S_BCLK3, 1710 | RT5677_PLL1_S_BCLK4, 1711 | }; 1712 | enum { 1713 | RT5677_AIF1, 1714 | RT5677_AIF2, 1715 | RT5677_AIF3, 1716 | RT5677_AIF4, 1717 | RT5677_AIF5, 1718 | RT5677_AIFS, 1719 | }; 1720 | 1721 | enum { 1722 | RT5677_GPIO1, 1723 | RT5677_GPIO2, 1724 | RT5677_GPIO3, 1725 | RT5677_GPIO4, 1726 | RT5677_GPIO5, 1727 | RT5677_GPIO6, 1728 | RT5677_GPIO_NUM, 1729 | }; 1730 | 1731 | enum { 1732 | RT5677_IRQ_JD1, 1733 | RT5677_IRQ_JD2, 1734 | RT5677_IRQ_JD3, 1735 | RT5677_IRQ_NUM, 1736 | }; 1737 | 1738 | #endif /* __DRIVERS_SOUND_RT5677_H__ */ --------------------------------------------------------------------------------