├── rt5682 ├── stdint.h ├── resource.h ├── rl6231.h ├── hidcommon.h ├── rt5682.rc ├── trace.h ├── spb.h ├── rt5682.inf ├── rl6231.c ├── rt5682.vcxproj ├── rt5682.h ├── spb.c ├── registers.h └── rt5682.c ├── README.md ├── rt5682.sln ├── LICENSE.txt ├── .gitignore └── rt5682 Package └── rt5682 Package.vcxproj /rt5682/stdint.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define BIT(nr) (1UL << (nr)) -------------------------------------------------------------------------------- /rt5682/resource.h: -------------------------------------------------------------------------------- 1 | //{{NO_DEPENDENCIES}} 2 | // Microsoft Visual C++ generated include file. 3 | // Used by rt5682.rc 4 | 5 | // Next default values for new objects 6 | // 7 | #ifdef APSTUDIO_INVOKED 8 | #ifndef APSTUDIO_READONLY_SYMBOLS 9 | #define _APS_NEXT_RESOURCE_VALUE 101 10 | #define _APS_NEXT_COMMAND_VALUE 40001 11 | #define _APS_NEXT_CONTROL_VALUE 1001 12 | #define _APS_NEXT_SYMED_VALUE 101 13 | #endif 14 | #endif 15 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # rt5682 2 | Realtek ALC 5682 I2C Codec driver 3 | 4 | Supports: 5 | * Jack Detection 6 | * Headphone output 7 | * Sleep/Wake 8 | * Microphone input 9 | 10 | Note: 11 | * Intel SST and AMD ACP proprietary drivers do NOT have documented interfaces, so this driver will not work with them. 12 | * Using this driver on chromebooks with this audio chip will require using CoolStar ACP Audio, CoolStar SST Audio or CoolStar SOF Audio 13 | * Certain chromebooks will also need the Chrome EC + Chrome EC I2C drivers to be able to use this driver 14 | 15 | Tested on HP Chromebook 14b (Ryzen 3 3250C) and Asus Chromebook Flip C234 (Intel Celeron N4020) 16 | -------------------------------------------------------------------------------- /rt5682/rl6231.h: -------------------------------------------------------------------------------- 1 | #ifndef __RL6231_H__ 2 | #define __RL6231_H__ 3 | 4 | #include 5 | 6 | #define RL6231_PLL_INP_MAX 50000000 7 | #define RL6231_PLL_INP_MIN 256000 8 | #define RL6231_PLL_N_MAX 0x1ff 9 | #define RL6231_PLL_K_MAX 0x1f 10 | #define RL6231_PLL_M_MAX 0xf 11 | 12 | struct rl6231_pll_code { 13 | BOOLEAN m_bp; /* Indicates bypass m code or not. */ 14 | BOOLEAN k_bp; /* Indicates bypass k code or not. */ 15 | INT m_code; 16 | INT n_code; 17 | INT k_code; 18 | }; 19 | 20 | NTSTATUS rl6231_calc_dmic_clk(int rate, int* clk); 21 | NTSTATUS rl6231_pll_calc(const unsigned int freq_in, 22 | const unsigned int freq_out, struct rl6231_pll_code* pll_code); 23 | NTSTATUS rl6231_get_clk_info(int sclk, int rate); 24 | NTSTATUS rl6231_get_pre_div(unsigned int regval, int sft); 25 | 26 | #endif /* __RL6231_H__ */ -------------------------------------------------------------------------------- /rt5682/hidcommon.h: -------------------------------------------------------------------------------- 1 | #if !defined(_RT5682_COMMON_H_) 2 | #define _RT5682_COMMON_H_ 3 | 4 | // 5 | //These are the device attributes returned by vmulti in response 6 | // to IOCTL_HID_GET_DEVICE_ATTRIBUTES. 7 | // 8 | 9 | #define RT5682_PID 0x5682 10 | #define RT5682_VID 0x10EC 11 | #define RT5682_VERSION 0x0001 12 | 13 | // 14 | // These are the report ids 15 | // 16 | 17 | #define REPORTID_MEDIA 0x01 18 | #define REPORTID_SPECKEYS 0x02 19 | 20 | #pragma pack(1) 21 | typedef struct _RT5682_MEDIA_REPORT 22 | { 23 | 24 | BYTE ReportID; 25 | 26 | BYTE ControlCode; 27 | 28 | } Rt5682MediaReport; 29 | #pragma pack() 30 | 31 | #define CONTROL_CODE_JACK_TYPE 0x1 32 | 33 | #pragma pack(1) 34 | typedef struct _CSAUDIO_SPECKEY_REPORT 35 | { 36 | 37 | BYTE ReportID; 38 | 39 | BYTE ControlCode; 40 | 41 | BYTE ControlValue; 42 | 43 | } CsAudioSpecialKeyReport; 44 | 45 | #pragma pack() 46 | 47 | #pragma pack(1) 48 | typedef struct _CSAUDIO_SPECKEYREQ_REPORT 49 | { 50 | 51 | BYTE ReportID; 52 | 53 | BYTE AnyCode; 54 | 55 | } CsAudioSpecialKeyRequestReport; 56 | #pragma pack() 57 | 58 | #endif 59 | -------------------------------------------------------------------------------- /rt5682/rt5682.rc: -------------------------------------------------------------------------------- 1 | /*++ 2 | 3 | Copyright (c) Microsoft Corporation All Rights Reserved 4 | 5 | Module Name: 6 | 7 | rt5682.rc 8 | 9 | Abstract: 10 | 11 | --*/ 12 | 13 | #include 14 | 15 | #define VER_FILETYPE VFT_DRV 16 | #define VER_FILESUBTYPE VFT2_DRV_SOUND 17 | #define VER_FILEDESCRIPTION_STR "Realtek ALC5682 I2S Audio" 18 | #define VER_INTERNALNAME_STR "rt5682.sys" 19 | #define VER_ORIGINALFILENAME_STR "rt5682.sys" 20 | 21 | #define VER_LEGALCOPYRIGHT_YEARS "2023" 22 | #define VER_LEGALCOPYRIGHT_STR "Copyright (C) " VER_LEGALCOPYRIGHT_YEARS " CoolStar." 23 | 24 | #define VER_FILEVERSION 1,0,2,0 25 | #define VER_PRODUCTVERSION_STR "1.0.2.0" 26 | #define VER_PRODUCTVERSION 1,0,2,0 27 | #define LVER_PRODUCTVERSION_STR L"1.0.2.0" 28 | 29 | #define VER_FILEFLAGSMASK (VS_FF_DEBUG | VS_FF_PRERELEASE) 30 | #ifdef DEBUG 31 | #define VER_FILEFLAGS (VS_FF_DEBUG) 32 | #else 33 | #define VER_FILEFLAGS (0) 34 | #endif 35 | 36 | #define VER_FILEOS VOS_NT_WINDOWS32 37 | 38 | #define VER_COMPANYNAME_STR "CoolStar" 39 | #define VER_PRODUCTNAME_STR "Realtek ALC5682 I2S Audio" 40 | 41 | #include "common.ver" -------------------------------------------------------------------------------- /rt5682/trace.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #ifndef _TRACE_H_ 4 | #define _TRACE_H_ 5 | 6 | extern "C" 7 | { 8 | // 9 | // Tracing Definitions: 10 | // 11 | // Control GUID: 12 | // {73e3b785-f5fb-423e-94a9-56627fea9053} 13 | // 14 | 15 | #define WPP_CONTROL_GUIDS \ 16 | WPP_DEFINE_CONTROL_GUID( \ 17 | SpbTestToolTraceGuid, \ 18 | (73e3b785,f5fb,423e,94a9,56627fea9053), \ 19 | WPP_DEFINE_BIT(TRACE_FLAG_WDFLOADING) \ 20 | WPP_DEFINE_BIT(TRACE_FLAG_SPBAPI) \ 21 | WPP_DEFINE_BIT(TRACE_FLAG_OTHER) \ 22 | ) 23 | } 24 | 25 | #define WPP_LEVEL_FLAGS_LOGGER(level,flags) WPP_LEVEL_LOGGER(flags) 26 | #define WPP_LEVEL_FLAGS_ENABLED(level, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= level) 27 | 28 | #define Trace CyapaPrint 29 | #define FuncEntry 30 | #define FuncExit 31 | #define WPP_INIT_TRACING 32 | #define WPP_CLEANUP 33 | #define TRACE_FLAG_SPBAPI 0 34 | #define TRACE_FLAG_WDFLOADING 0 35 | 36 | // begin_wpp config 37 | // FUNC FuncEntry{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 38 | // FUNC FuncExit{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 39 | // USEPREFIX(FuncEntry, "%!STDPREFIX! [%!FUNC!] --> entry"); 40 | // USEPREFIX(FuncExit, "%!STDPREFIX! [%!FUNC!] <--"); 41 | // end_wpp 42 | 43 | #endif _TRACE_H_ 44 | -------------------------------------------------------------------------------- /rt5682/spb.h: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.h 8 | 9 | Abstract: 10 | 11 | This module contains the touch driver I2C helper definitions. 12 | 13 | Environment: 14 | 15 | Kernel Mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #pragma once 22 | 23 | #include 24 | #include 25 | 26 | #define DEFAULT_SPB_BUFFER_SIZE 64 27 | #define RESHUB_USE_HELPER_ROUTINES 28 | 29 | // 30 | // SPB (I2C) context 31 | // 32 | 33 | typedef struct _SPB_CONTEXT 34 | { 35 | WDFIOTARGET SpbIoTarget; 36 | LARGE_INTEGER I2cResHubId; 37 | WDFMEMORY WriteMemory; 38 | WDFMEMORY ReadMemory; 39 | WDFWAITLOCK SpbLock; 40 | } SPB_CONTEXT; 41 | 42 | NTSTATUS 43 | SpbXferDataSynchronously( 44 | _In_ SPB_CONTEXT* SpbContext, 45 | _In_ PVOID SendData, 46 | _In_ ULONG SendLength, 47 | _In_reads_bytes_(Length) PVOID Data, 48 | _In_ ULONG Length 49 | ); 50 | 51 | VOID 52 | SpbTargetDeinitialize( 53 | IN WDFDEVICE FxDevice, 54 | IN SPB_CONTEXT* SpbContext 55 | ); 56 | 57 | NTSTATUS 58 | SpbTargetInitialize( 59 | IN WDFDEVICE FxDevice, 60 | IN SPB_CONTEXT* SpbContext 61 | ); 62 | 63 | NTSTATUS 64 | SpbWriteDataSynchronously( 65 | IN SPB_CONTEXT* SpbContext, 66 | IN PVOID Data, 67 | IN ULONG Length 68 | ); 69 | 70 | typedef struct _SPB_BURST_INFO { 71 | PVOID Data; 72 | ULONG Length; 73 | } SPB_BURST_INFO; 74 | 75 | NTSTATUS 76 | SpbBurstWriteDataSynchronously( 77 | IN SPB_CONTEXT* SpbContext, 78 | IN SPB_BURST_INFO* Data, 79 | IN ULONG Count 80 | ); -------------------------------------------------------------------------------- /rt5682/rt5682.inf: -------------------------------------------------------------------------------- 1 | ;/*++ 2 | ; 3 | ;Copyright (c) CoolStar. All rights reserved. 4 | ; 5 | ;Module Name: 6 | ; coolstar.inf 7 | ; 8 | ;Abstract: 9 | ; INF file for installing the RT5682 Jack Detect Driver 10 | ; 11 | ; 12 | ;--*/ 13 | 14 | [Version] 15 | Signature = "$WINDOWS NT$" 16 | Class = Media 17 | ClassGuid = {4d36e96c-e325-11ce-bfc1-08002be10318} 18 | Provider = CoolStar 19 | DriverVer = 12/16/2021,1.0.0 20 | CatalogFile = rt5682.cat 21 | PnpLockdown=1 22 | 23 | [DestinationDirs] 24 | DefaultDestDir = 12 25 | 26 | ; ================= Class section ===================== 27 | 28 | [SourceDisksNames] 29 | 1 = %DiskId1%,,,"" 30 | 31 | [SourceDisksFiles] 32 | rt5682.sys = 1,, 33 | 34 | ;***************************************** 35 | ; rt5682 Install Section 36 | ;***************************************** 37 | 38 | [Manufacturer] 39 | %StdMfg%=Standard,NTAMD64 40 | 41 | ; Decorated model section take precedence over undecorated 42 | ; ones on XP and later. 43 | [Standard.NTAMD64] 44 | %rt5682.DeviceDesc%=Rt5682_Device, ACPI\10EC5682 45 | 46 | [Rt5682_Device.NT] 47 | CopyFiles=Drivers_Dir 48 | 49 | [Rt5682_Device.NT.HW] 50 | AddReg=Rt5682_AddReg, Rt5682_AddReg.Configuration.AddReg 51 | Include=pci.inf 52 | Needs=PciD3ColdSupported.HW 53 | 54 | [Drivers_Dir] 55 | rt5682.sys 56 | 57 | [Rt5682_AddReg] 58 | ; Set to 1 to connect the first interrupt resource found, 0 to leave disconnected 59 | HKR,Settings,"ConnectInterrupt",0x00010001,0 60 | HKR,,"UpperFilters",0x00010000,"mshidkmdf" 61 | 62 | [Rt5682_AddReg.Configuration.AddReg] 63 | HKR,,"EnhancedPowerManagementEnabled",0x00010001,1 64 | 65 | ;-------------- Service installation 66 | [Rt5682_Device.NT.Services] 67 | AddService = rt5682,%SPSVCINST_ASSOCSERVICE%, Rt5682_Service_Inst 68 | 69 | ; -------------- rt5682 driver install sections 70 | [Rt5682_Service_Inst] 71 | DisplayName = %rt5682.SVCDESC% 72 | ServiceType = 1 ; SERVICE_KERNEL_DRIVER 73 | StartType = 3 ; SERVICE_DEMAND_START 74 | ErrorControl = 1 ; SERVICE_ERROR_NORMAL 75 | ServiceBinary = %12%\rt5682.sys 76 | LoadOrderGroup = Base 77 | 78 | [Strings] 79 | SPSVCINST_ASSOCSERVICE= 0x00000002 80 | StdMfg = "CoolStar" 81 | DiskId1 = "ALC5682 Installation Disk #1" 82 | rt5682.DeviceDesc = "Realtek ALC5682 I2S Audio" 83 | rt5682.SVCDESC = "ALC5682 Service" 84 | -------------------------------------------------------------------------------- /rt5682.sln: -------------------------------------------------------------------------------- 1 | 2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.31829.152 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "rt5682", "rt5682\rt5682.vcxproj", "{36580C07-EDC3-4C2B-B45F-6AB017E01A5D}" 7 | EndProject 8 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "rt5682 Package", "rt5682 Package\rt5682 Package.vcxproj", "{3DAE7ED3-003A-4495-8352-3D7B5B5D846F}" 9 | ProjectSection(ProjectDependencies) = postProject 10 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} = {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} 11 | EndProjectSection 12 | EndProject 13 | Global 14 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 15 | Debug|Win32 = Debug|Win32 16 | Debug|x64 = Debug|x64 17 | Release|Win32 = Release|Win32 18 | Release|x64 = Release|x64 19 | EndGlobalSection 20 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 21 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.ActiveCfg = Debug|Win32 22 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.Build.0 = Debug|Win32 23 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.Deploy.0 = Debug|Win32 24 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.ActiveCfg = Debug|x64 25 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.Build.0 = Debug|x64 26 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.Deploy.0 = Debug|x64 27 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.ActiveCfg = Release|Win32 28 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.Build.0 = Release|Win32 29 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.Deploy.0 = Release|Win32 30 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.ActiveCfg = Release|x64 31 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.Build.0 = Release|x64 32 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.Deploy.0 = Release|x64 33 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.ActiveCfg = Debug|Win32 34 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.Build.0 = Debug|Win32 35 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.Deploy.0 = Debug|Win32 36 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.ActiveCfg = Debug|x64 37 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.Build.0 = Debug|x64 38 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.Deploy.0 = Debug|x64 39 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.ActiveCfg = Release|Win32 40 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.Build.0 = Release|Win32 41 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.Deploy.0 = Release|Win32 42 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.ActiveCfg = Release|x64 43 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.Build.0 = Release|x64 44 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.Deploy.0 = Release|x64 45 | EndGlobalSection 46 | GlobalSection(SolutionProperties) = preSolution 47 | HideSolutionNode = FALSE 48 | EndGlobalSection 49 | GlobalSection(ExtensibilityGlobals) = postSolution 50 | SolutionGuid = {1EBAC2E3-504A-4D97-960C-BBD6F6AFBEC6} 51 | EndGlobalSection 52 | EndGlobal 53 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | Copyright 2021 CoolStar 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | 15 | 16 | ====================== Windows Driver Samples License ====================== 17 | 18 | The Microsoft Public License (MS-PL) 19 | Copyright (c) 2015 Microsoft 20 | 21 | This license governs use of the accompanying software. If you use the software, you 22 | accept this license. If you do not accept the license, do not use the software. 23 | 24 | 1. Definitions 25 | The terms "reproduce," "reproduction," "derivative works," and "distribution" have the 26 | same meaning here as under U.S. copyright law. 27 | A "contribution" is the original software, or any additions or changes to the software. 28 | A "contributor" is any person that distributes its contribution under this license. 29 | "Licensed patents" are a contributor's patent claims that read directly on its contribution. 30 | 31 | 2. Grant of Rights 32 | (A) Copyright Grant- Subject to the terms of this license, including the license conditions and limitations in section 3, each contributor grants you a non-exclusive, worldwide, royalty-free copyright license to reproduce its contribution, prepare derivative works of its contribution, and distribute its contribution or any derivative works that you create. 33 | (B) Patent Grant- Subject to the terms of this license, including the license conditions and limitations in section 3, each contributor grants you a non-exclusive, worldwide, royalty-free license under its licensed patents to make, have made, use, sell, offer for sale, import, and/or otherwise dispose of its contribution in the software or derivative works of the contribution in the software. 34 | 35 | 3. Conditions and Limitations 36 | (A) No Trademark License- This license does not grant you rights to use any contributors' name, logo, or trademarks. 37 | (B) If you bring a patent claim against any contributor over patents that you claim are infringed by the software, your patent license from such contributor to the software ends automatically. 38 | (C) If you distribute any portion of the software, you must retain all copyright, patent, trademark, and attribution notices that are present in the software. 39 | (D) If you distribute any portion of the software in source code form, you may do so only under this license by including a complete copy of this license with your distribution. If you distribute any portion of the software in compiled or object code form, you may only do so under a license that complies with this license. 40 | (E) The software is licensed "as-is." You bear the risk of using it. The contributors give no express warranties, guarantees or conditions. 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To the extent permitted under your local laws, the contributors exclude the implied warranties of merchantability, fitness for a particular purpose and non-infringement. -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ## Ignore Visual Studio temporary files, build results, and 2 | ## files generated by popular Visual Studio add-ons. 3 | ## 4 | ## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore 5 | 6 | # User-specific files 7 | *.rsuser 8 | *.suo 9 | *.user 10 | *.userosscache 11 | *.sln.docstates 12 | 13 | # User-specific files (MonoDevelop/Xamarin Studio) 14 | *.userprefs 15 | 16 | # Build results 17 | [Dd]ebug/ 18 | [Dd]ebugPublic/ 19 | [Rr]elease/ 20 | [Rr]eleases/ 21 | x64/ 22 | x86/ 23 | bld/ 24 | [Bb]in/ 25 | [Oo]bj/ 26 | [Ll]og/ 27 | 28 | # Visual Studio 2015/2017 cache/options directory 29 | .vs/ 30 | # Uncomment if you have tasks that create the project's static files in wwwroot 31 | #wwwroot/ 32 | 33 | # Visual Studio 2017 auto generated files 34 | Generated\ Files/ 35 | 36 | # MSTest test Results 37 | [Tt]est[Rr]esult*/ 38 | [Bb]uild[Ll]og.* 39 | 40 | # NUNIT 41 | *.VisualState.xml 42 | TestResult.xml 43 | 44 | # Build Results of an ATL Project 45 | [Dd]ebugPS/ 46 | [Rr]eleasePS/ 47 | dlldata.c 48 | 49 | # Benchmark Results 50 | BenchmarkDotNet.Artifacts/ 51 | 52 | # .NET Core 53 | project.lock.json 54 | project.fragment.lock.json 55 | artifacts/ 56 | 57 | # StyleCop 58 | StyleCopReport.xml 59 | 60 | # Files built by Visual Studio 61 | *_i.c 62 | *_p.c 63 | *_h.h 64 | *.ilk 65 | *.meta 66 | *.obj 67 | *.iobj 68 | *.pch 69 | *.pdb 70 | *.ipdb 71 | *.pgc 72 | *.pgd 73 | *.rsp 74 | *.sbr 75 | *.tlb 76 | *.tli 77 | *.tlh 78 | *.tmp 79 | *.tmp_proj 80 | *_wpftmp.csproj 81 | *.log 82 | *.vspscc 83 | *.vssscc 84 | .builds 85 | *.pidb 86 | *.svclog 87 | *.scc 88 | 89 | # Chutzpah Test files 90 | _Chutzpah* 91 | 92 | # Visual C++ cache files 93 | ipch/ 94 | *.aps 95 | *.ncb 96 | *.opendb 97 | *.opensdf 98 | *.sdf 99 | *.cachefile 100 | *.VC.db 101 | *.VC.VC.opendb 102 | 103 | # Visual Studio profiler 104 | *.psess 105 | *.vsp 106 | *.vspx 107 | *.sap 108 | 109 | # Visual Studio Trace Files 110 | *.e2e 111 | 112 | # TFS 2012 Local Workspace 113 | $tf/ 114 | 115 | # Guidance Automation Toolkit 116 | *.gpState 117 | 118 | # ReSharper is a .NET coding add-in 119 | _ReSharper*/ 120 | *.[Rr]e[Ss]harper 121 | *.DotSettings.user 122 | 123 | # JustCode is a .NET coding add-in 124 | .JustCode 125 | 126 | # TeamCity is a build add-in 127 | _TeamCity* 128 | 129 | # DotCover is a Code Coverage Tool 130 | *.dotCover 131 | 132 | # AxoCover is a Code Coverage Tool 133 | .axoCover/* 134 | !.axoCover/settings.json 135 | 136 | # Visual Studio code coverage results 137 | *.coverage 138 | *.coveragexml 139 | 140 | # NCrunch 141 | _NCrunch_* 142 | .*crunch*.local.xml 143 | nCrunchTemp_* 144 | 145 | # MightyMoose 146 | *.mm.* 147 | AutoTest.Net/ 148 | 149 | # Web workbench (sass) 150 | .sass-cache/ 151 | 152 | # Installshield output folder 153 | [Ee]xpress/ 154 | 155 | # DocProject is a documentation generator add-in 156 | DocProject/buildhelp/ 157 | DocProject/Help/*.HxT 158 | DocProject/Help/*.HxC 159 | DocProject/Help/*.hhc 160 | DocProject/Help/*.hhk 161 | DocProject/Help/*.hhp 162 | DocProject/Help/Html2 163 | DocProject/Help/html 164 | 165 | # Click-Once directory 166 | publish/ 167 | 168 | # Publish Web Output 169 | *.[Pp]ublish.xml 170 | *.azurePubxml 171 | # Note: Comment the next line if you want to checkin your web deploy settings, 172 | # but database connection strings (with potential passwords) will be unencrypted 173 | *.pubxml 174 | *.publishproj 175 | 176 | # Microsoft Azure Web App publish settings. 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Backup files are not needed, 238 | # because we have git ;-) 239 | _UpgradeReport_Files/ 240 | Backup*/ 241 | UpgradeLog*.XML 242 | UpgradeLog*.htm 243 | ServiceFabricBackup/ 244 | *.rptproj.bak 245 | 246 | # SQL Server files 247 | *.mdf 248 | *.ldf 249 | *.ndf 250 | 251 | # Business Intelligence projects 252 | *.rdl.data 253 | *.bim.layout 254 | *.bim_*.settings 255 | *.rptproj.rsuser 256 | 257 | # Microsoft Fakes 258 | FakesAssemblies/ 259 | 260 | # GhostDoc plugin setting file 261 | *.GhostDoc.xml 262 | 263 | # Node.js Tools for Visual Studio 264 | .ntvs_analysis.dat 265 | node_modules/ 266 | 267 | # Visual Studio 6 build log 268 | *.plg 269 | 270 | # Visual Studio 6 workspace options file 271 | *.opt 272 | 273 | # Visual Studio 6 auto-generated workspace file (contains which files were open etc.) 274 | *.vbw 275 | 276 | # Visual Studio LightSwitch build output 277 | **/*.HTMLClient/GeneratedArtifacts 278 | **/*.DesktopClient/GeneratedArtifacts 279 | **/*.DesktopClient/ModelManifest.xml 280 | **/*.Server/GeneratedArtifacts 281 | **/*.Server/ModelManifest.xml 282 | _Pvt_Extensions 283 | 284 | # Paket dependency manager 285 | .paket/paket.exe 286 | paket-files/ 287 | 288 | # FAKE - F# Make 289 | .fake/ 290 | 291 | # JetBrains Rider 292 | .idea/ 293 | *.sln.iml 294 | 295 | # CodeRush personal settings 296 | .cr/personal 297 | 298 | # Python Tools for Visual Studio (PTVS) 299 | __pycache__/ 300 | *.pyc 301 | 302 | # Cake - Uncomment if you are using it 303 | # tools/** 304 | # !tools/packages.config 305 | 306 | # Tabs Studio 307 | *.tss 308 | 309 | # Telerik's JustMock configuration file 310 | *.jmconfig 311 | 312 | # BizTalk build output 313 | *.btp.cs 314 | *.btm.cs 315 | *.odx.cs 316 | *.xsd.cs 317 | 318 | # OpenCover UI analysis results 319 | OpenCover/ 320 | 321 | # Azure Stream Analytics local run output 322 | ASALocalRun/ 323 | 324 | # MSBuild Binary and Structured Log 325 | *.binlog 326 | 327 | # NVidia Nsight GPU debugger configuration file 328 | *.nvuser 329 | 330 | # MFractors (Xamarin productivity tool) working folder 331 | .mfractor/ 332 | 333 | # Local History for Visual Studio 334 | .localhistory/ 335 | -------------------------------------------------------------------------------- /rt5682 Package/rt5682 Package.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F} 23 | {4605da2c-74a5-4865-98e1-152ef136825f} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | rt5682_Package 29 | $(LatestTargetPlatformVersion) 30 | 31 | 32 | 33 | Windows10 34 | true 35 | WindowsKernelModeDriver10.0 36 | Utility 37 | Package 38 | true 39 | 40 | 41 | Windows10 42 | false 43 | WindowsKernelModeDriver10.0 44 | Utility 45 | Package 46 | true 47 | 48 | 49 | Windows10 50 | true 51 | WindowsKernelModeDriver10.0 52 | Utility 53 | Package 54 | true 55 | 56 | 57 | Windows10 58 | false 59 | WindowsKernelModeDriver10.0 60 | Utility 61 | Package 62 | true 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | DbgengKernelDebugger 74 | False 75 | True 76 | 77 | 78 | 79 | False 80 | False 81 | True 82 | 83 | 133563 84 | 85 | 86 | DbgengKernelDebugger 87 | False 88 | True 89 | 90 | 91 | 92 | False 93 | False 94 | True 95 | 96 | 133563 97 | 98 | 99 | DbgengKernelDebugger 100 | False 101 | True 102 | 103 | 104 | 105 | False 106 | False 107 | True 108 | 109 | 133563 110 | 111 | 112 | DbgengKernelDebugger 113 | False 114 | True 115 | 116 | 117 | 118 | False 119 | False 120 | True 121 | 122 | 133563 123 | 124 | 125 | 126 | SHA256 127 | 128 | 129 | 130 | 131 | SHA256 132 | 133 | 134 | 135 | 136 | SHA256 137 | 138 | 139 | 140 | 141 | SHA256 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | {36580c07-edc3-4c2b-b45f-6ab017e01a5d} 150 | 151 | 152 | 153 | 154 | 155 | -------------------------------------------------------------------------------- /rt5682/rl6231.c: -------------------------------------------------------------------------------- 1 | #include "rl6231.h" 2 | 3 | /** 4 | * __ffs - find first bit in word. 5 | * @word: The word to search 6 | * 7 | * Undefined if no bit exists, so code should check against 0 first. 8 | */ 9 | static unsigned long __ffs(unsigned long word) 10 | { 11 | int num = 0; 12 | 13 | #if BITS_PER_LONG == 64 14 | if ((word & 0xffffffff) == 0) { 15 | num += 32; 16 | word >>= 32; 17 | } 18 | #endif 19 | if ((word & 0xffff) == 0) { 20 | num += 16; 21 | word >>= 16; 22 | } 23 | if ((word & 0xff) == 0) { 24 | num += 8; 25 | word >>= 8; 26 | } 27 | if ((word & 0xf) == 0) { 28 | num += 4; 29 | word >>= 4; 30 | } 31 | if ((word & 0x3) == 0) { 32 | num += 2; 33 | word >>= 2; 34 | } 35 | if ((word & 0x1) == 0) 36 | num += 1; 37 | return num; 38 | } 39 | 40 | /** 41 | * gcd - calculate and return the greatest common divisor of 2 unsigned longs 42 | * @a: first value 43 | * @b: second value 44 | */ 45 | unsigned long gcd(unsigned long a, unsigned long b) 46 | { 47 | unsigned long r = a | b; 48 | 49 | if (!a || !b) 50 | return r; 51 | 52 | b >>= __ffs(b); 53 | if (b == 1) 54 | return r & -r; 55 | 56 | for (;;) { 57 | a >>= __ffs(a); 58 | if (a == 1) 59 | return r & -r; 60 | if (a == b) 61 | return a << __ffs(r); 62 | 63 | if (a < b) { 64 | unsigned long temp = a; 65 | a = b; 66 | b = temp; 67 | } 68 | a -= b; 69 | } 70 | } 71 | 72 | /** 73 | * rl6231_get_pre_div - Return the value of pre divider. 74 | * 75 | * @map: map for setting. 76 | * @reg: register. 77 | * @sft: shift. 78 | * 79 | * Return the value of pre divider from given register value. 80 | * Return negative error code for unexpected register value. 81 | */ 82 | NTSTATUS rl6231_get_pre_div(unsigned int regval, int sft) 83 | { 84 | int pd, val; 85 | 86 | val = (regval >> sft) & 0x7; 87 | 88 | switch (val) { 89 | case 0: 90 | case 1: 91 | case 2: 92 | case 3: 93 | pd = val + 1; 94 | break; 95 | case 4: 96 | pd = 6; 97 | break; 98 | case 5: 99 | pd = 8; 100 | break; 101 | case 6: 102 | pd = 12; 103 | break; 104 | case 7: 105 | pd = 16; 106 | break; 107 | default: 108 | pd = -1; 109 | break; 110 | } 111 | 112 | return pd; 113 | } 114 | 115 | /** 116 | * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic. 117 | * 118 | * @rate: base clock rate. 119 | * 120 | * Choose divider parameter that gives the highest possible DMIC frequency in 121 | * 1MHz - 3MHz range. 122 | */ 123 | NTSTATUS rl6231_calc_dmic_clk(int rate, int* clk) 124 | { 125 | static const int div[] = { 2, 3, 4, 6, 8, 12 }; 126 | int i; 127 | 128 | if (rate < 1000000 * div[0]) { 129 | DbgPrint("Base clock rate %d is too low\n", rate); 130 | return STATUS_INVALID_PARAMETER; 131 | } 132 | 133 | for (i = 0; i < sizeof(div) / sizeof(const int); i++) { 134 | if ((div[i] % 3) == 0) 135 | continue; 136 | /* find divider that gives DMIC frequency below 1.536MHz */ 137 | if (1536000 * div[i] >= rate) { 138 | *clk = i; 139 | return STATUS_SUCCESS; 140 | } 141 | } 142 | 143 | DbgPrint("Base clock rate %d is too high\n", rate); 144 | return STATUS_INVALID_PARAMETER; 145 | } 146 | 147 | struct pll_calc_map { 148 | UINT32 pll_in; 149 | UINT32 pll_out; 150 | INT k; 151 | INT n; 152 | INT m; 153 | BOOLEAN m_bp; 154 | BOOLEAN k_bp; 155 | }; 156 | 157 | static const struct pll_calc_map pll_preset_table[] = { 158 | {19200000, 4096000, 23, 14, 1, FALSE, FALSE}, 159 | {19200000, 24576000, 3, 30, 3, FALSE, FALSE}, 160 | {48000000, 3840000, 23, 2, 0, FALSE, FALSE}, 161 | {3840000, 24576000, 3, 30, 0, TRUE, FALSE}, 162 | {3840000, 22579200, 3, 5, 0, TRUE, FALSE}, 163 | }; 164 | 165 | static unsigned int find_best_div(unsigned int in, 166 | unsigned int max, unsigned int div) 167 | { 168 | unsigned int d; 169 | 170 | if (in <= max) 171 | return 1; 172 | 173 | d = in / max; 174 | if (in % max) 175 | d++; 176 | 177 | while (div % d != 0) 178 | d++; 179 | 180 | 181 | return d; 182 | } 183 | 184 | /** 185 | * rl6231_pll_calc - Calcualte PLL M/N/K code. 186 | * @freq_in: external clock provided to codec. 187 | * @freq_out: target clock which codec works on. 188 | * @pll_code: Pointer to structure with M, N, K, m_bypass and k_bypass flag. 189 | * 190 | * Calcualte M/N/K code to configure PLL for codec. 191 | * 192 | * Returns 0 for success or negative error code. 193 | */ 194 | NTSTATUS rl6231_pll_calc(const unsigned int freq_in, 195 | const unsigned int freq_out, struct rl6231_pll_code* pll_code) 196 | { 197 | int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX; 198 | int i, k, n_t; 199 | int k_t, min_k, max_k, n = 0, m = 0, m_t = 0; 200 | unsigned int red, pll_out, in_t, out_t, div, div_t; 201 | unsigned int red_t = abs(freq_out - freq_in); 202 | unsigned int f_in, f_out, f_max; 203 | BOOLEAN m_bypass = FALSE, k_bypass = FALSE; 204 | 205 | if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in) 206 | return STATUS_INVALID_PARAMETER; 207 | 208 | for (i = 0; i < sizeof(pll_preset_table) / sizeof(const struct pll_calc_map); i++) { 209 | if (freq_in == pll_preset_table[i].pll_in && 210 | freq_out == pll_preset_table[i].pll_out) { 211 | k = pll_preset_table[i].k; 212 | m = pll_preset_table[i].m; 213 | n = pll_preset_table[i].n; 214 | m_bypass = pll_preset_table[i].m_bp; 215 | k_bypass = pll_preset_table[i].k_bp; 216 | goto code_find; 217 | } 218 | } 219 | 220 | min_k = 80000000 / freq_out - 2; 221 | max_k = 150000000 / freq_out - 2; 222 | if (max_k > RL6231_PLL_K_MAX) 223 | max_k = RL6231_PLL_K_MAX; 224 | if (min_k > RL6231_PLL_K_MAX) 225 | min_k = max_k = RL6231_PLL_K_MAX; 226 | div_t = gcd(freq_in, freq_out); 227 | f_max = 0xffffffff / RL6231_PLL_N_MAX; 228 | div = find_best_div(freq_in, f_max, div_t); 229 | f_in = freq_in / div; 230 | f_out = freq_out / div; 231 | k = min_k; 232 | if (min_k < -1) 233 | min_k = -1; 234 | for (k_t = min_k; k_t <= max_k; k_t++) { 235 | for (n_t = 0; n_t <= max_n; n_t++) { 236 | in_t = f_in * (n_t + 2); 237 | pll_out = f_out * (k_t + 2); 238 | if (in_t == pll_out) { 239 | m_bypass = TRUE; 240 | n = n_t; 241 | k = k_t; 242 | goto code_find; 243 | } 244 | out_t = in_t / (k_t + 2); 245 | red = abs(f_out - out_t); 246 | if (red < red_t) { 247 | m_bypass = TRUE; 248 | n = n_t; 249 | m = 0; 250 | k = k_t; 251 | if (red == 0) 252 | goto code_find; 253 | red_t = red; 254 | } 255 | for (m_t = 0; m_t <= max_m; m_t++) { 256 | out_t = in_t / ((m_t + 2) * (k_t + 2)); 257 | red = abs(f_out - out_t); 258 | if (red < red_t) { 259 | m_bypass = FALSE; 260 | n = n_t; 261 | m = m_t; 262 | k = k_t; 263 | if (red == 0) 264 | goto code_find; 265 | red_t = red; 266 | } 267 | } 268 | } 269 | } 270 | 271 | code_find: 272 | if (k == -1) { 273 | k_bypass = TRUE; 274 | k = 0; 275 | } 276 | 277 | pll_code->m_bp = m_bypass; 278 | pll_code->k_bp = k_bypass; 279 | pll_code->m_code = m; 280 | pll_code->n_code = n; 281 | pll_code->k_code = k; 282 | return STATUS_SUCCESS; 283 | } 284 | 285 | NTSTATUS rl6231_get_clk_info(int sclk, int rate) 286 | { 287 | int i; 288 | static const int pd[] = { 1, 2, 3, 4, 6, 8, 12, 16 }; 289 | 290 | if (sclk <= 0 || rate <= 0) 291 | return STATUS_INVALID_PARAMETER; 292 | 293 | rate = rate << 8; 294 | for (i = 0; i < sizeof(pd) / sizeof(const int); i++) 295 | if (sclk == rate * pd[i]) 296 | return i; 297 | 298 | return STATUS_INVALID_PARAMETER; 299 | } -------------------------------------------------------------------------------- /rt5682/rt5682.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} 23 | {1bc93793-694f-48fe-9372-81e2b05556fd} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | rt5682 29 | $(LatestTargetPlatformVersion) 30 | 31 | 32 | 33 | Windows10 34 | true 35 | WindowsKernelModeDriver10.0 36 | Driver 37 | KMDF 38 | 39 | 40 | Windows10 41 | false 42 | WindowsKernelModeDriver10.0 43 | Driver 44 | KMDF 45 | 46 | 47 | Windows10 48 | true 49 | WindowsKernelModeDriver10.0 50 | Driver 51 | KMDF 52 | 53 | 54 | Windows10 55 | false 56 | WindowsKernelModeDriver10.0 57 | Driver 58 | KMDF 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | DbgengKernelDebugger 70 | 71 | 72 | DbgengKernelDebugger 73 | 74 | 75 | DbgengKernelDebugger 76 | 77 | 78 | DbgengKernelDebugger 79 | 80 | 81 | 82 | true 83 | trace.h 84 | true 85 | false 86 | 87 | 88 | 1.0.2 89 | 90 | 91 | SHA256 92 | 93 | 94 | 95 | 96 | true 97 | trace.h 98 | true 99 | false 100 | 101 | 102 | 1.0.2 103 | 104 | 105 | SHA256 106 | 107 | 108 | 109 | 110 | true 111 | trace.h 112 | true 113 | false 114 | 115 | 116 | 1.0.2 117 | 118 | 119 | SHA256 120 | 121 | 122 | 123 | 124 | true 125 | trace.h 126 | true 127 | false 128 | 129 | 130 | 1.0.2 131 | 132 | 133 | SHA256 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | -------------------------------------------------------------------------------- /rt5682/rt5682.h: -------------------------------------------------------------------------------- 1 | #if !defined(_RT5682_H_) 2 | #define _RT5682_H_ 3 | 4 | #pragma warning(disable:4200) // suppress nameless struct/union warning 5 | #pragma warning(disable:4201) // suppress nameless struct/union warning 6 | #pragma warning(disable:4214) // suppress bit field types other than int warning 7 | #include 8 | #include 9 | 10 | #pragma warning(default:4200) 11 | #pragma warning(default:4201) 12 | #pragma warning(default:4214) 13 | #include 14 | 15 | #pragma warning(disable:4201) // suppress nameless struct/union warning 16 | #pragma warning(disable:4214) // suppress bit field types other than int warning 17 | #include 18 | 19 | #include "hidcommon.h" 20 | #include "spb.h" 21 | #include 22 | 23 | #define true 1 24 | #define false 0 25 | 26 | typedef enum { 27 | CSAudioEndpointTypeDSP, 28 | CSAudioEndpointTypeSpeaker, 29 | CSAudioEndpointTypeHeadphone, 30 | CSAudioEndpointTypeMicArray, 31 | CSAudioEndpointTypeMicJack 32 | } CSAudioEndpointType; 33 | 34 | typedef enum { 35 | CSAudioEndpointRegister, 36 | CSAudioEndpointStart, 37 | CSAudioEndpointStop, 38 | CSAudioEndpointOverrideFormat, 39 | CSAudioEndpointI2SParameters 40 | } CSAudioEndpointRequest; 41 | 42 | typedef struct CSAUDIOFORMATOVERRIDE { 43 | UINT16 channels; 44 | UINT16 frequency; 45 | UINT16 bitsPerSample; 46 | UINT16 validBitsPerSample; 47 | BOOLEAN force32BitOutputContainer; 48 | } CsAudioFormatOverride; 49 | 50 | typedef struct CSAUDIOI2SPARAMS { 51 | UINT32 version; 52 | 53 | UINT32 mclk; 54 | UINT32 bclk_rate; 55 | UINT32 frequency; 56 | UINT32 tdm_slots; 57 | UINT32 tdm_slot_width; 58 | UINT32 rx_slots; 59 | UINT32 tx_slots; 60 | UINT32 valid_bits; //end of version 1 61 | } CsAudioI2SParameters; 62 | 63 | typedef struct CSAUDIOARG { 64 | UINT32 argSz; 65 | CSAudioEndpointType endpointType; 66 | CSAudioEndpointRequest endpointRequest; 67 | union { 68 | CsAudioFormatOverride formatOverride; 69 | CsAudioI2SParameters i2sParameters; 70 | }; 71 | } CsAudioArg, * PCsAudioArg; 72 | 73 | typedef enum platform { 74 | PlatformNone, 75 | PlatformRyzen, 76 | PlatformGeminiLake, 77 | PlatformCometLake, 78 | PlatformTigerLake 79 | } Platform; 80 | 81 | enum snd_jack_types { 82 | SND_JACK_HEADPHONE = 0x0001, 83 | SND_JACK_MICROPHONE = 0x0002, 84 | SND_JACK_HEADSET = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE, 85 | }; 86 | 87 | struct reg { 88 | UINT16 reg; 89 | UINT16 val; 90 | }; 91 | 92 | // 93 | // String definitions 94 | // 95 | 96 | #define DRIVERNAME "rt5682.sys: " 97 | 98 | #define RT5682_POOL_TAG (ULONG) '856R' 99 | 100 | typedef UCHAR HID_REPORT_DESCRIPTOR, *PHID_REPORT_DESCRIPTOR; 101 | 102 | #ifdef DESCRIPTOR_DEF 103 | HID_REPORT_DESCRIPTOR DefaultReportDescriptor[] = { 104 | // 105 | // Consumer Control starts here 106 | // 107 | 0x05, 0x0C, /* Usage Page (Consumer Devices) */ 108 | 0x09, 0x01, /* Usage (Consumer Control) */ 109 | 0xA1, 0x01, /* Collection (Application) */ 110 | 0x85, REPORTID_MEDIA, /* Report ID=1 */ 111 | 0x05, 0x0C, /* Usage Page (Consumer Devices) */ 112 | 0x15, 0x00, /* Logical Minimum (0) */ 113 | 0x25, 0x01, /* Logical Maximum (1) */ 114 | 0x75, 0x01, /* Report Size (1) */ 115 | 0x95, 0x04, /* Report Count (4) */ 116 | 0x09, 0xCD, /* Usage (Play / Pause) */ 117 | 0x09, 0xCF, /* Usage (Voice Command) */ 118 | 0x09, 0xE9, /* Usage (Volume Up) */ 119 | 0x09, 0xEA, /* Usage (Volume Down) */ 120 | 0x81, 0x02, /* Input (Data, Variable, Absolute) */ 121 | 0x95, 0x04, /* Report Count (4) */ 122 | 0x81, 0x01, /* Input (Constant) */ 123 | 0xC0, /* End Collection */ 124 | 125 | 0x06, 0x00, 0xff, // USAGE_PAGE (Vendor Defined Page 1) 126 | 0x09, 0x04, // USAGE (Vendor Usage 4) 127 | 0xa1, 0x01, // COLLECTION (Application) 128 | 0x85, REPORTID_SPECKEYS, // REPORT_ID (Special Keys) 129 | 0x15, 0x00, // LOGICAL_MINIMUM (0) 130 | 0x26, 0xff, 0x00, // LOGICAL_MAXIMUM (256) 131 | 0x75, 0x08, // REPORT_SIZE (8) - bits 132 | 0x95, 0x01, // REPORT_COUNT (1) - Bytes 133 | 0x09, 0x02, // USAGE (Vendor Usage 1) 134 | 0x81, 0x02, // INPUT (Data,Var,Abs) 135 | 0x09, 0x03, // USAGE (Vendor Usage 2) 136 | 0x81, 0x02, // INPUT (Data,Var,Abs) 137 | 0x09, 0x02, // USAGE (Vendor Usage 1) 138 | 0x91, 0x02, // OUTPUT (Data,Var,Abs) 139 | 0xc0, // END_COLLECTION 140 | }; 141 | 142 | 143 | // 144 | // This is the default HID descriptor returned by the mini driver 145 | // in response to IOCTL_HID_GET_DEVICE_DESCRIPTOR. The size 146 | // of report descriptor is currently the size of DefaultReportDescriptor. 147 | // 148 | 149 | CONST HID_DESCRIPTOR DefaultHidDescriptor = { 150 | 0x09, // length of HID descriptor 151 | 0x21, // descriptor type == HID 0x21 152 | 0x0100, // hid spec release 153 | 0x00, // country code == Not Specified 154 | 0x01, // number of HID class descriptors 155 | { 0x22, // descriptor type 156 | sizeof(DefaultReportDescriptor) } // total length of report descriptor 157 | }; 158 | #endif 159 | 160 | typedef struct _RTEK_CONTEXT 161 | { 162 | 163 | WDFDEVICE FxDevice; 164 | 165 | WDFQUEUE ReportQueue; 166 | 167 | WDFQUEUE IdleQueue; 168 | 169 | SPB_CONTEXT I2CContext; 170 | 171 | WDFINTERRUPT Interrupt; 172 | 173 | BOOLEAN ConnectInterrupt; 174 | 175 | INT JackType; 176 | 177 | PCALLBACK_OBJECT CSAudioAPICallback; 178 | PVOID CSAudioAPICallbackObj; 179 | 180 | BOOLEAN CSAudioManaged; 181 | 182 | BOOLEAN ReclockRequested; 183 | UINT32 mclk; 184 | UINT32 freq; 185 | UINT32 slotWidth; 186 | } RTEK_CONTEXT, *PRTEK_CONTEXT; 187 | 188 | WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(RTEK_CONTEXT, GetDeviceContext) 189 | 190 | // 191 | // Power Idle Workitem context 192 | // 193 | typedef struct _IDLE_WORKITEM_CONTEXT 194 | { 195 | // Handle to a WDF device object 196 | WDFDEVICE FxDevice; 197 | 198 | // Handle to a WDF request object 199 | WDFREQUEST FxRequest; 200 | 201 | } IDLE_WORKITEM_CONTEXT, * PIDLE_WORKITEM_CONTEXT; 202 | WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(IDLE_WORKITEM_CONTEXT, GetIdleWorkItemContext) 203 | 204 | // 205 | // Function definitions 206 | // 207 | 208 | DRIVER_INITIALIZE DriverEntry; 209 | 210 | EVT_WDF_DRIVER_UNLOAD Rt5682DriverUnload; 211 | 212 | EVT_WDF_DRIVER_DEVICE_ADD Rt5682EvtDeviceAdd; 213 | 214 | EVT_WDFDEVICE_WDM_IRP_PREPROCESS Rt5682EvtWdmPreprocessMnQueryId; 215 | 216 | EVT_WDF_IO_QUEUE_IO_INTERNAL_DEVICE_CONTROL Rt5682EvtInternalDeviceControl; 217 | 218 | NTSTATUS 219 | Rt5682GetHidDescriptor( 220 | IN WDFDEVICE Device, 221 | IN WDFREQUEST Request 222 | ); 223 | 224 | NTSTATUS 225 | Rt5682GetReportDescriptor( 226 | IN WDFDEVICE Device, 227 | IN WDFREQUEST Request 228 | ); 229 | 230 | NTSTATUS 231 | Rt5682GetDeviceAttributes( 232 | IN WDFREQUEST Request 233 | ); 234 | 235 | NTSTATUS 236 | Rt5682GetString( 237 | IN WDFREQUEST Request 238 | ); 239 | 240 | NTSTATUS 241 | Rt5682WriteReport( 242 | IN PRTEK_CONTEXT DevContext, 243 | IN WDFREQUEST Request 244 | ); 245 | 246 | NTSTATUS 247 | Rt5682ProcessVendorReport( 248 | IN PRTEK_CONTEXT DevContext, 249 | IN PVOID ReportBuffer, 250 | IN ULONG ReportBufferLen, 251 | OUT size_t* BytesWritten 252 | ); 253 | 254 | NTSTATUS 255 | Rt5682ReadReport( 256 | IN PRTEK_CONTEXT DevContext, 257 | IN WDFREQUEST Request, 258 | OUT BOOLEAN* CompleteRequest 259 | ); 260 | 261 | NTSTATUS 262 | Rt5682SetFeature( 263 | IN PRTEK_CONTEXT DevContext, 264 | IN WDFREQUEST Request, 265 | OUT BOOLEAN* CompleteRequest 266 | ); 267 | 268 | NTSTATUS 269 | Rt5682GetFeature( 270 | IN PRTEK_CONTEXT DevContext, 271 | IN WDFREQUEST Request, 272 | OUT BOOLEAN* CompleteRequest 273 | ); 274 | 275 | PCHAR 276 | DbgHidInternalIoctlString( 277 | IN ULONG IoControlCode 278 | ); 279 | 280 | VOID 281 | RtekCompleteIdleIrp( 282 | IN PRTEK_CONTEXT FxDeviceContext 283 | ); 284 | 285 | // 286 | // Helper macros 287 | // 288 | 289 | #define DEBUG_LEVEL_ERROR 1 290 | #define DEBUG_LEVEL_INFO 2 291 | #define DEBUG_LEVEL_VERBOSE 3 292 | 293 | #define DBG_INIT 1 294 | #define DBG_PNP 2 295 | #define DBG_IOCTL 4 296 | 297 | #if 0 298 | #define RtekPrint(dbglevel, dbgcatagory, fmt, ...) { \ 299 | if (Rt5682DebugLevel >= dbglevel && \ 300 | (Rt5682DebugCatagories && dbgcatagory)) \ 301 | { \ 302 | DbgPrint(DRIVERNAME); \ 303 | DbgPrint(fmt, __VA_ARGS__); \ 304 | } \ 305 | } 306 | #else 307 | #define RtekPrint(dbglevel, fmt, ...) { \ 308 | } 309 | #endif 310 | 311 | #endif -------------------------------------------------------------------------------- /rt5682/spb.c: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.c 8 | 9 | Abstract: 10 | 11 | Contains all I2C-specific functionality 12 | 13 | Environment: 14 | 15 | Kernel mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #include "rt5682.h" 22 | #include "spb.h" 23 | #include 24 | #include 25 | 26 | static ULONG Rt5682DebugLevel = 100; 27 | static ULONG Rt5682DebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 28 | 29 | NTSTATUS 30 | SpbDoWriteDataSynchronously( 31 | IN SPB_CONTEXT* SpbContext, 32 | IN PVOID Data, 33 | IN ULONG Length 34 | ) 35 | /*++ 36 | 37 | Routine Description: 38 | 39 | This helper routine abstracts creating and sending an I/O 40 | request (I2C Write) to the Spb I/O target. 41 | 42 | Arguments: 43 | 44 | SpbContext - Pointer to the current device context 45 | Address - The I2C register address to write to 46 | Data - A buffer to receive the data at at the above address 47 | Length - The amount of data to be read from the above address 48 | 49 | Return Value: 50 | 51 | NTSTATUS Status indicating success or failure 52 | 53 | --*/ 54 | { 55 | PUCHAR buffer; 56 | ULONG length; 57 | WDFMEMORY memory; 58 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 59 | NTSTATUS status; 60 | 61 | length = Length; 62 | memory = NULL; 63 | 64 | if (length > DEFAULT_SPB_BUFFER_SIZE) 65 | { 66 | status = WdfMemoryCreate( 67 | WDF_NO_OBJECT_ATTRIBUTES, 68 | NonPagedPool, 69 | RT5682_POOL_TAG, 70 | length, 71 | &memory, 72 | (PVOID*)&buffer); 73 | 74 | if (!NT_SUCCESS(status)) 75 | { 76 | RtekPrint( 77 | DEBUG_LEVEL_ERROR, 78 | DBG_IOCTL, 79 | "Error allocating memory for Spb write - %!STATUS!", 80 | status); 81 | goto exit; 82 | } 83 | 84 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 85 | &memoryDescriptor, 86 | memory, 87 | NULL); 88 | } 89 | else 90 | { 91 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->WriteMemory, NULL); 92 | 93 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 94 | &memoryDescriptor, 95 | (PVOID)buffer, 96 | length); 97 | } 98 | 99 | RtlCopyMemory(buffer, Data, length); 100 | 101 | status = WdfIoTargetSendWriteSynchronously( 102 | SpbContext->SpbIoTarget, 103 | NULL, 104 | &memoryDescriptor, 105 | NULL, 106 | NULL, 107 | NULL); 108 | 109 | if (!NT_SUCCESS(status)) 110 | { 111 | RtekPrint( 112 | DEBUG_LEVEL_ERROR, 113 | DBG_IOCTL, 114 | "Error writing to Spb - %!STATUS!", 115 | status); 116 | goto exit; 117 | } 118 | 119 | exit: 120 | 121 | if (NULL != memory) 122 | { 123 | WdfObjectDelete(memory); 124 | } 125 | 126 | return status; 127 | } 128 | 129 | NTSTATUS 130 | SpbWriteDataSynchronously( 131 | IN SPB_CONTEXT* SpbContext, 132 | IN PVOID Data, 133 | IN ULONG Length 134 | ) 135 | /*++ 136 | 137 | Routine Description: 138 | 139 | This routine abstracts creating and sending an I/O 140 | request (I2C Write) to the Spb I/O target and utilizes 141 | a helper routine to do work inside of locked code. 142 | 143 | Arguments: 144 | 145 | SpbContext - Pointer to the current device context 146 | Address - The I2C register address to write to 147 | Data - A buffer to receive the data at at the above address 148 | Length - The amount of data to be read from the above address 149 | 150 | Return Value: 151 | 152 | NTSTATUS Status indicating success or failure 153 | 154 | --*/ 155 | { 156 | NTSTATUS status; 157 | 158 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 159 | 160 | status = SpbDoWriteDataSynchronously( 161 | SpbContext, 162 | Data, 163 | Length); 164 | 165 | WdfWaitLockRelease(SpbContext->SpbLock); 166 | 167 | return status; 168 | } 169 | 170 | NTSTATUS 171 | SpbBurstWriteDataSynchronously( 172 | IN SPB_CONTEXT* SpbContext, 173 | IN SPB_BURST_INFO* BurstInfo, 174 | IN ULONG Count 175 | ) 176 | { 177 | NTSTATUS status; 178 | 179 | typedef struct _SPB_TRANSFER { 180 | SPB_TRANSFER_LIST List; 181 | SPB_TRANSFER_LIST_ENTRY ExtraTransfers[]; 182 | } SPB_TRANSFER; 183 | 184 | size_t seq_size = sizeof(SPB_TRANSFER) + (sizeof(SPB_TRANSFER_LIST_ENTRY) * (Count - 1)); 185 | SPB_TRANSFER* seq = ExAllocatePoolWithTag(NonPagedPool, seq_size, RT5682_POOL_TAG); 186 | if (!seq) 187 | return STATUS_NO_MEMORY; 188 | 189 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 190 | 191 | SPB_TRANSFER_LIST_INIT(&(seq->List), Count); 192 | 193 | for (int i = 0; i < Count; i++) { 194 | SPB_BURST_INFO Info = BurstInfo[i]; 195 | 196 | seq->List.Transfers[i] = SPB_TRANSFER_LIST_ENTRY_INIT_SIMPLE( 197 | SpbTransferDirectionToDevice, 198 | 0, 199 | Info.Data, 200 | Info.Length); 201 | } 202 | 203 | WDF_MEMORY_DESCRIPTOR MemoryDescriptor; 204 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 205 | &MemoryDescriptor, 206 | seq, 207 | seq_size); 208 | ULONG_PTR BytesTransferred = 0; 209 | status = WdfIoTargetSendIoctlSynchronously( 210 | SpbContext->SpbIoTarget, 211 | NULL, 212 | IOCTL_SPB_EXECUTE_SEQUENCE, 213 | &MemoryDescriptor, 214 | NULL, 215 | NULL, 216 | &BytesTransferred 217 | ); 218 | 219 | WdfWaitLockRelease(SpbContext->SpbLock); 220 | 221 | exit: 222 | if (seq) 223 | ExFreePoolWithTag(seq, RT5682_POOL_TAG); 224 | return status; 225 | } 226 | 227 | NTSTATUS 228 | SpbXferDataSynchronously( 229 | _In_ SPB_CONTEXT* SpbContext, 230 | _In_ PVOID SendData, 231 | _In_ ULONG SendLength, 232 | _In_reads_bytes_(Length) PVOID Data, 233 | _In_ ULONG Length 234 | ) 235 | /*++ 236 | Routine Description: 237 | This helper routine abstracts creating and sending an I/O 238 | request (I2C Read) to the Spb I/O target. 239 | Arguments: 240 | SpbContext - Pointer to the current device context 241 | Address - The I2C register address to read from 242 | Data - A buffer to receive the data at at the above address 243 | Length - The amount of data to be read from the above address 244 | Return Value: 245 | NTSTATUS Status indicating success or failure 246 | --*/ 247 | { 248 | PUCHAR buffer; 249 | WDFMEMORY memory; 250 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 251 | NTSTATUS status; 252 | ULONG_PTR bytesRead; 253 | 254 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 255 | 256 | memory = NULL; 257 | status = STATUS_INVALID_PARAMETER; 258 | bytesRead = 0; 259 | 260 | // 261 | // Xfer transactions start by writing an address pointer 262 | // 263 | status = SpbDoWriteDataSynchronously( 264 | SpbContext, 265 | SendData, 266 | SendLength); 267 | 268 | if (!NT_SUCCESS(status)) 269 | { 270 | RtekPrint( 271 | DEBUG_LEVEL_ERROR, 272 | DBG_IOCTL, 273 | "Error setting address pointer for Spb read - %!STATUS!", 274 | status); 275 | goto exit; 276 | } 277 | 278 | if (Length > DEFAULT_SPB_BUFFER_SIZE) 279 | { 280 | status = WdfMemoryCreate( 281 | WDF_NO_OBJECT_ATTRIBUTES, 282 | NonPagedPool, 283 | RT5682_POOL_TAG, 284 | Length, 285 | &memory, 286 | (PVOID*)&buffer); 287 | 288 | if (!NT_SUCCESS(status)) 289 | { 290 | RtekPrint( 291 | DEBUG_LEVEL_ERROR, 292 | DBG_IOCTL, 293 | "Error allocating memory for Spb read - %!STATUS!", 294 | status); 295 | goto exit; 296 | } 297 | 298 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 299 | &memoryDescriptor, 300 | memory, 301 | NULL); 302 | } 303 | else 304 | { 305 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->ReadMemory, NULL); 306 | 307 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 308 | &memoryDescriptor, 309 | (PVOID)buffer, 310 | Length); 311 | } 312 | 313 | 314 | status = WdfIoTargetSendReadSynchronously( 315 | SpbContext->SpbIoTarget, 316 | NULL, 317 | &memoryDescriptor, 318 | NULL, 319 | NULL, 320 | &bytesRead); 321 | 322 | if (!NT_SUCCESS(status) || 323 | bytesRead != Length) 324 | { 325 | RtekPrint( 326 | DEBUG_LEVEL_ERROR, 327 | DBG_IOCTL, 328 | "Error reading from Spb - %!STATUS!", 329 | status); 330 | goto exit; 331 | } 332 | 333 | // 334 | // Copy back to the caller's buffer 335 | // 336 | RtlCopyMemory(Data, buffer, Length); 337 | 338 | exit: 339 | if (NULL != memory) 340 | { 341 | WdfObjectDelete(memory); 342 | } 343 | 344 | WdfWaitLockRelease(SpbContext->SpbLock); 345 | 346 | return status; 347 | } 348 | 349 | VOID 350 | SpbTargetDeinitialize( 351 | IN WDFDEVICE FxDevice, 352 | IN SPB_CONTEXT* SpbContext 353 | ) 354 | /*++ 355 | 356 | Routine Description: 357 | 358 | This helper routine is used to free any members added to the SPB_CONTEXT, 359 | note the SPB I/O target is parented to the device and will be 360 | closed and free'd when the device is removed. 361 | 362 | Arguments: 363 | 364 | FxDevice - Handle to the framework device object 365 | SpbContext - Pointer to the current device context 366 | 367 | Return Value: 368 | 369 | NTSTATUS Status indicating success or failure 370 | 371 | --*/ 372 | { 373 | UNREFERENCED_PARAMETER(FxDevice); 374 | UNREFERENCED_PARAMETER(SpbContext); 375 | 376 | // 377 | // Free any SPB_CONTEXT allocations here 378 | // 379 | if (SpbContext->SpbLock != NULL) 380 | { 381 | WdfObjectDelete(SpbContext->SpbLock); 382 | } 383 | 384 | if (SpbContext->ReadMemory != NULL) 385 | { 386 | WdfObjectDelete(SpbContext->ReadMemory); 387 | } 388 | 389 | if (SpbContext->WriteMemory != NULL) 390 | { 391 | WdfObjectDelete(SpbContext->WriteMemory); 392 | } 393 | } 394 | 395 | NTSTATUS 396 | SpbTargetInitialize( 397 | IN WDFDEVICE FxDevice, 398 | IN SPB_CONTEXT* SpbContext 399 | ) 400 | /*++ 401 | 402 | Routine Description: 403 | 404 | This helper routine opens the Spb I/O target and 405 | initializes a request object used for the lifetime 406 | of communication between this driver and Spb. 407 | 408 | Arguments: 409 | 410 | FxDevice - Handle to the framework device object 411 | SpbContext - Pointer to the current device context 412 | 413 | Return Value: 414 | 415 | NTSTATUS Status indicating success or failure 416 | 417 | --*/ 418 | { 419 | WDF_OBJECT_ATTRIBUTES objectAttributes; 420 | WDF_IO_TARGET_OPEN_PARAMS openParams; 421 | UNICODE_STRING spbDeviceName; 422 | WCHAR spbDeviceNameBuffer[RESOURCE_HUB_PATH_SIZE]; 423 | NTSTATUS status; 424 | 425 | WDF_OBJECT_ATTRIBUTES_INIT(&objectAttributes); 426 | objectAttributes.ParentObject = FxDevice; 427 | 428 | status = WdfIoTargetCreate( 429 | FxDevice, 430 | &objectAttributes, 431 | &SpbContext->SpbIoTarget); 432 | 433 | if (!NT_SUCCESS(status)) 434 | { 435 | RtekPrint( 436 | DEBUG_LEVEL_ERROR, 437 | DBG_IOCTL, 438 | "Error creating IoTarget object - %!STATUS!", 439 | status); 440 | 441 | WdfObjectDelete(SpbContext->SpbIoTarget); 442 | goto exit; 443 | } 444 | 445 | RtlInitEmptyUnicodeString( 446 | &spbDeviceName, 447 | spbDeviceNameBuffer, 448 | sizeof(spbDeviceNameBuffer)); 449 | 450 | status = RESOURCE_HUB_CREATE_PATH_FROM_ID( 451 | &spbDeviceName, 452 | SpbContext->I2cResHubId.LowPart, 453 | SpbContext->I2cResHubId.HighPart); 454 | 455 | if (!NT_SUCCESS(status)) 456 | { 457 | RtekPrint( 458 | DEBUG_LEVEL_ERROR, 459 | DBG_IOCTL, 460 | "Error creating Spb resource hub path string - %!STATUS!", 461 | status); 462 | goto exit; 463 | } 464 | 465 | WDF_IO_TARGET_OPEN_PARAMS_INIT_OPEN_BY_NAME( 466 | &openParams, 467 | &spbDeviceName, 468 | (GENERIC_READ | GENERIC_WRITE)); 469 | 470 | openParams.ShareAccess = 0; 471 | openParams.CreateDisposition = FILE_OPEN; 472 | openParams.FileAttributes = FILE_ATTRIBUTE_NORMAL; 473 | 474 | status = WdfIoTargetOpen(SpbContext->SpbIoTarget, &openParams); 475 | 476 | if (!NT_SUCCESS(status)) 477 | { 478 | RtekPrint( 479 | DEBUG_LEVEL_ERROR, 480 | DBG_IOCTL, 481 | "Error opening Spb target for communication - %!STATUS!", 482 | status); 483 | goto exit; 484 | } 485 | 486 | // 487 | // Allocate some fixed-size buffers from NonPagedPool for typical 488 | // Spb transaction sizes to avoid pool fragmentation in most cases 489 | // 490 | status = WdfMemoryCreate( 491 | WDF_NO_OBJECT_ATTRIBUTES, 492 | NonPagedPool, 493 | RT5682_POOL_TAG, 494 | DEFAULT_SPB_BUFFER_SIZE, 495 | &SpbContext->WriteMemory, 496 | NULL); 497 | 498 | if (!NT_SUCCESS(status)) 499 | { 500 | RtekPrint( 501 | DEBUG_LEVEL_ERROR, 502 | DBG_IOCTL, 503 | "Error allocating default memory for Spb write - %!STATUS!", 504 | status); 505 | goto exit; 506 | } 507 | 508 | status = WdfMemoryCreate( 509 | WDF_NO_OBJECT_ATTRIBUTES, 510 | NonPagedPool, 511 | RT5682_POOL_TAG, 512 | DEFAULT_SPB_BUFFER_SIZE, 513 | &SpbContext->ReadMemory, 514 | NULL); 515 | 516 | if (!NT_SUCCESS(status)) 517 | { 518 | RtekPrint( 519 | DEBUG_LEVEL_ERROR, 520 | DBG_IOCTL, 521 | "Error allocating default memory for Spb read - %!STATUS!", 522 | status); 523 | goto exit; 524 | } 525 | 526 | // 527 | // Allocate a waitlock to guard access to the default buffers 528 | // 529 | status = WdfWaitLockCreate( 530 | WDF_NO_OBJECT_ATTRIBUTES, 531 | &SpbContext->SpbLock); 532 | 533 | if (!NT_SUCCESS(status)) 534 | { 535 | RtekPrint( 536 | DEBUG_LEVEL_ERROR, 537 | DBG_IOCTL, 538 | "Error creating Spb Waitlock - %!STATUS!", 539 | status); 540 | goto exit; 541 | } 542 | 543 | exit: 544 | 545 | if (!NT_SUCCESS(status)) 546 | { 547 | SpbTargetDeinitialize(FxDevice, SpbContext); 548 | } 549 | 550 | return status; 551 | } -------------------------------------------------------------------------------- /rt5682/registers.h: -------------------------------------------------------------------------------- 1 | #ifndef __RT5682_H__ 2 | #define __RT5682_H__ 3 | 4 | /* 5 | * RT5682 Registers Definition 6 | */ 7 | 8 | #define DEVICE_ID 0x6530 9 | 10 | /* Info */ 11 | #define RT5682_RESET 0x0000 12 | #define RT5682_VERSION_ID 0x00fd 13 | #define RT5682_VENDOR_ID 0x00fe 14 | #define RT5682_DEVICE_ID 0x00ff 15 | /* I/O - Output */ 16 | #define RT5682_HP_CTRL_1 0x0002 17 | #define RT5682_HP_CTRL_2 0x0003 18 | #define RT5682_HPL_GAIN 0x0005 19 | #define RT5682_HPR_GAIN 0x0006 20 | 21 | #define RT5682_I2C_CTRL 0x0008 22 | 23 | /* I/O - Input */ 24 | #define RT5682_CBJ_BST_CTRL 0x000b 25 | #define RT5682_CBJ_CTRL_1 0x0010 26 | #define RT5682_CBJ_CTRL_2 0x0011 27 | #define RT5682_CBJ_CTRL_3 0x0012 28 | #define RT5682_CBJ_CTRL_4 0x0013 29 | #define RT5682_CBJ_CTRL_5 0x0014 30 | #define RT5682_CBJ_CTRL_6 0x0015 31 | #define RT5682_CBJ_CTRL_7 0x0016 32 | /* I/O - ADC/DAC/DMIC */ 33 | #define RT5682_DAC1_DIG_VOL 0x0019 34 | #define RT5682_STO1_ADC_DIG_VOL 0x001c 35 | #define RT5682_STO1_ADC_BOOST 0x001f 36 | #define RT5682_HP_IMP_GAIN_1 0x0022 37 | #define RT5682_HP_IMP_GAIN_2 0x0023 38 | /* Mixer - D-D */ 39 | #define RT5682_SIDETONE_CTRL 0x0024 40 | #define RT5682_STO1_ADC_MIXER 0x0026 41 | #define RT5682_AD_DA_MIXER 0x0029 42 | #define RT5682_STO1_DAC_MIXER 0x002a 43 | #define RT5682_A_DAC1_MUX 0x002b 44 | #define RT5682_DIG_INF2_DATA 0x0030 45 | /* Mixer - ADC */ 46 | #define RT5682_REC_MIXER 0x003c 47 | #define RT5682_CAL_REC 0x0044 48 | #define RT5682_ALC_BACK_GAIN 0x0049 49 | /* Power */ 50 | #define RT5682_PWR_DIG_1 0x0061 51 | #define RT5682_PWR_DIG_2 0x0062 52 | #define RT5682_PWR_ANLG_1 0x0063 53 | #define RT5682_PWR_ANLG_2 0x0064 54 | #define RT5682_PWR_ANLG_3 0x0065 55 | #define RT5682_PWR_MIXER 0x0066 56 | #define RT5682_PWR_VOL 0x0067 57 | /* Clock Detect */ 58 | #define RT5682_CLK_DET 0x006b 59 | /* Filter Auto Reset */ 60 | #define RT5682_RESET_LPF_CTRL 0x006c 61 | #define RT5682_RESET_HPF_CTRL 0x006d 62 | /* DMIC */ 63 | #define RT5682_DMIC_CTRL_1 0x006e 64 | /* Format - ADC/DAC */ 65 | #define RT5682_I2S1_SDP 0x0070 66 | #define RT5682_I2S2_SDP 0x0071 67 | #define RT5682_ADDA_CLK_1 0x0073 68 | #define RT5682_ADDA_CLK_2 0x0074 69 | #define RT5682_I2S1_F_DIV_CTRL_1 0x0075 70 | #define RT5682_I2S1_F_DIV_CTRL_2 0x0076 71 | /* Format - TDM Control */ 72 | #define RT5682_TDM_CTRL 0x0079 73 | #define RT5682_TDM_ADDA_CTRL_1 0x007a 74 | #define RT5682_TDM_ADDA_CTRL_2 0x007b 75 | #define RT5682_DATA_SEL_CTRL_1 0x007c 76 | #define RT5682_TDM_TCON_CTRL 0x007e 77 | /* Function - Analog */ 78 | #define RT5682_GLB_CLK 0x0080 79 | #define RT5682_PLL_CTRL_1 0x0081 80 | #define RT5682_PLL_CTRL_2 0x0082 81 | #define RT5682_PLL_TRACK_1 0x0083 82 | #define RT5682_PLL_TRACK_2 0x0084 83 | #define RT5682_PLL_TRACK_3 0x0085 84 | #define RT5682_PLL_TRACK_4 0x0086 85 | #define RT5682_PLL_TRACK_5 0x0087 86 | #define RT5682_PLL_TRACK_6 0x0088 87 | #define RT5682_PLL_TRACK_11 0x008c 88 | #define RT5682_SDW_REF_CLK 0x008d 89 | #define RT5682_DEPOP_1 0x008e 90 | #define RT5682_DEPOP_2 0x008f 91 | #define RT5682_HP_CHARGE_PUMP_1 0x0091 92 | #define RT5682_HP_CHARGE_PUMP_2 0x0092 93 | #define RT5682_MICBIAS_1 0x0093 94 | #define RT5682_MICBIAS_2 0x0094 95 | #define RT5682_PLL_TRACK_12 0x0098 96 | #define RT5682_PLL_TRACK_14 0x009a 97 | #define RT5682_PLL2_CTRL_1 0x009b 98 | #define RT5682_PLL2_CTRL_2 0x009c 99 | #define RT5682_PLL2_CTRL_3 0x009d 100 | #define RT5682_PLL2_CTRL_4 0x009e 101 | #define RT5682_RC_CLK_CTRL 0x009f 102 | #define RT5682_I2S_M_CLK_CTRL_1 0x00a0 103 | #define RT5682_I2S2_F_DIV_CTRL_1 0x00a3 104 | #define RT5682_I2S2_F_DIV_CTRL_2 0x00a4 105 | /* Function - Digital */ 106 | #define RT5682_EQ_CTRL_1 0x00ae 107 | #define RT5682_EQ_CTRL_2 0x00af 108 | #define RT5682_IRQ_CTRL_1 0x00b6 109 | #define RT5682_IRQ_CTRL_2 0x00b7 110 | #define RT5682_IRQ_CTRL_3 0x00b8 111 | #define RT5682_IRQ_CTRL_4 0x00b9 112 | #define RT5682_INT_ST_1 0x00be 113 | #define RT5682_GPIO_CTRL_1 0x00c0 114 | #define RT5682_GPIO_CTRL_2 0x00c1 115 | #define RT5682_GPIO_CTRL_3 0x00c2 116 | #define RT5682_HP_AMP_DET_CTRL_1 0x00d0 117 | #define RT5682_HP_AMP_DET_CTRL_2 0x00d1 118 | #define RT5682_MID_HP_AMP_DET 0x00d2 119 | #define RT5682_LOW_HP_AMP_DET 0x00d3 120 | #define RT5682_DELAY_BUF_CTRL 0x00d4 121 | #define RT5682_SV_ZCD_1 0x00d9 122 | #define RT5682_SV_ZCD_2 0x00da 123 | #define RT5682_IL_CMD_1 0x00db 124 | #define RT5682_IL_CMD_2 0x00dc 125 | #define RT5682_IL_CMD_3 0x00dd 126 | #define RT5682_IL_CMD_4 0x00de 127 | #define RT5682_IL_CMD_5 0x00df 128 | #define RT5682_IL_CMD_6 0x00e0 129 | #define RT5682_4BTN_IL_CMD_1 0x00e2 130 | #define RT5682_4BTN_IL_CMD_2 0x00e3 131 | #define RT5682_4BTN_IL_CMD_3 0x00e4 132 | #define RT5682_4BTN_IL_CMD_4 0x00e5 133 | #define RT5682_4BTN_IL_CMD_5 0x00e6 134 | #define RT5682_4BTN_IL_CMD_6 0x00e7 135 | #define RT5682_4BTN_IL_CMD_7 0x00e8 136 | 137 | #define RT5682_ADC_STO1_HP_CTRL_1 0x00ea 138 | #define RT5682_ADC_STO1_HP_CTRL_2 0x00eb 139 | #define RT5682_AJD1_CTRL 0x00f0 140 | #define RT5682_JD1_THD 0x00f1 141 | #define RT5682_JD2_THD 0x00f2 142 | #define RT5682_JD_CTRL_1 0x00f6 143 | /* General Control */ 144 | #define RT5682_DUMMY_1 0x00fa 145 | #define RT5682_DUMMY_2 0x00fb 146 | #define RT5682_DUMMY_3 0x00fc 147 | 148 | #define RT5682_DAC_ADC_DIG_VOL1 0x0100 149 | #define RT5682_BIAS_CUR_CTRL_2 0x010b 150 | #define RT5682_BIAS_CUR_CTRL_3 0x010c 151 | #define RT5682_BIAS_CUR_CTRL_4 0x010d 152 | #define RT5682_BIAS_CUR_CTRL_5 0x010e 153 | #define RT5682_BIAS_CUR_CTRL_6 0x010f 154 | #define RT5682_BIAS_CUR_CTRL_7 0x0110 155 | #define RT5682_BIAS_CUR_CTRL_8 0x0111 156 | #define RT5682_BIAS_CUR_CTRL_9 0x0112 157 | #define RT5682_BIAS_CUR_CTRL_10 0x0113 158 | #define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117 159 | #define RT5682_CHARGE_PUMP_1 0x0125 160 | #define RT5682_DIG_IN_CTRL_1 0x0132 161 | #define RT5682_PAD_DRIVING_CTRL 0x0136 162 | #define RT5682_SOFT_RAMP_DEPOP 0x0138 163 | #define RT5682_CHOP_DAC 0x013a 164 | #define RT5682_CHOP_ADC 0x013b 165 | #define RT5682_CALIB_ADC_CTRL 0x013c 166 | #define RT5682_VOL_TEST 0x013f 167 | #define RT5682_SPKVDD_DET_STA 0x0142 168 | #define RT5682_TEST_MODE_CTRL_1 0x0145 169 | #define RT5682_TEST_MODE_CTRL_2 0x0146 170 | #define RT5682_TEST_MODE_CTRL_3 0x0147 171 | #define RT5682_TEST_MODE_CTRL_4 0x0148 172 | #define RT5682_TEST_MODE_CTRL_5 0x0149 173 | #define RT5682_PLL1_INTERNAL 0x0150 174 | #define RT5682_PLL2_INTERNAL 0x0156 175 | #define RT5682_STO_NG2_CTRL_1 0x0160 176 | #define RT5682_STO_NG2_CTRL_2 0x0161 177 | #define RT5682_STO_NG2_CTRL_3 0x0162 178 | #define RT5682_STO_NG2_CTRL_4 0x0163 179 | #define RT5682_STO_NG2_CTRL_5 0x0164 180 | #define RT5682_STO_NG2_CTRL_6 0x0165 181 | #define RT5682_STO_NG2_CTRL_7 0x0166 182 | #define RT5682_STO_NG2_CTRL_8 0x0167 183 | #define RT5682_STO_NG2_CTRL_9 0x0168 184 | #define RT5682_STO_NG2_CTRL_10 0x0169 185 | #define RT5682_STO1_DAC_SIL_DET 0x0190 186 | #define RT5682_SIL_PSV_CTRL1 0x0194 187 | #define RT5682_SIL_PSV_CTRL2 0x0195 188 | #define RT5682_SIL_PSV_CTRL3 0x0197 189 | #define RT5682_SIL_PSV_CTRL4 0x0198 190 | #define RT5682_SIL_PSV_CTRL5 0x0199 191 | #define RT5682_HP_IMP_SENS_CTRL_01 0x01af 192 | #define RT5682_HP_IMP_SENS_CTRL_02 0x01b0 193 | #define RT5682_HP_IMP_SENS_CTRL_03 0x01b1 194 | #define RT5682_HP_IMP_SENS_CTRL_04 0x01b2 195 | #define RT5682_HP_IMP_SENS_CTRL_05 0x01b3 196 | #define RT5682_HP_IMP_SENS_CTRL_06 0x01b4 197 | #define RT5682_HP_IMP_SENS_CTRL_07 0x01b5 198 | #define RT5682_HP_IMP_SENS_CTRL_08 0x01b6 199 | #define RT5682_HP_IMP_SENS_CTRL_09 0x01b7 200 | #define RT5682_HP_IMP_SENS_CTRL_10 0x01b8 201 | #define RT5682_HP_IMP_SENS_CTRL_11 0x01b9 202 | #define RT5682_HP_IMP_SENS_CTRL_12 0x01ba 203 | #define RT5682_HP_IMP_SENS_CTRL_13 0x01bb 204 | #define RT5682_HP_IMP_SENS_CTRL_14 0x01bc 205 | #define RT5682_HP_IMP_SENS_CTRL_15 0x01bd 206 | #define RT5682_HP_IMP_SENS_CTRL_16 0x01be 207 | #define RT5682_HP_IMP_SENS_CTRL_17 0x01bf 208 | #define RT5682_HP_IMP_SENS_CTRL_18 0x01c0 209 | #define RT5682_HP_IMP_SENS_CTRL_19 0x01c1 210 | #define RT5682_HP_IMP_SENS_CTRL_20 0x01c2 211 | #define RT5682_HP_IMP_SENS_CTRL_21 0x01c3 212 | #define RT5682_HP_IMP_SENS_CTRL_22 0x01c4 213 | #define RT5682_HP_IMP_SENS_CTRL_23 0x01c5 214 | #define RT5682_HP_IMP_SENS_CTRL_24 0x01c6 215 | #define RT5682_HP_IMP_SENS_CTRL_25 0x01c7 216 | #define RT5682_HP_IMP_SENS_CTRL_26 0x01c8 217 | #define RT5682_HP_IMP_SENS_CTRL_27 0x01c9 218 | #define RT5682_HP_IMP_SENS_CTRL_28 0x01ca 219 | #define RT5682_HP_IMP_SENS_CTRL_29 0x01cb 220 | #define RT5682_HP_IMP_SENS_CTRL_30 0x01cc 221 | #define RT5682_HP_IMP_SENS_CTRL_31 0x01cd 222 | #define RT5682_HP_IMP_SENS_CTRL_32 0x01ce 223 | #define RT5682_HP_IMP_SENS_CTRL_33 0x01cf 224 | #define RT5682_HP_IMP_SENS_CTRL_34 0x01d0 225 | #define RT5682_HP_IMP_SENS_CTRL_35 0x01d1 226 | #define RT5682_HP_IMP_SENS_CTRL_36 0x01d2 227 | #define RT5682_HP_IMP_SENS_CTRL_37 0x01d3 228 | #define RT5682_HP_IMP_SENS_CTRL_38 0x01d4 229 | #define RT5682_HP_IMP_SENS_CTRL_39 0x01d5 230 | #define RT5682_HP_IMP_SENS_CTRL_40 0x01d6 231 | #define RT5682_HP_IMP_SENS_CTRL_41 0x01d7 232 | #define RT5682_HP_IMP_SENS_CTRL_42 0x01d8 233 | #define RT5682_HP_IMP_SENS_CTRL_43 0x01d9 234 | #define RT5682_HP_LOGIC_CTRL_1 0x01da 235 | #define RT5682_HP_LOGIC_CTRL_2 0x01db 236 | #define RT5682_HP_LOGIC_CTRL_3 0x01dc 237 | #define RT5682_HP_CALIB_CTRL_1 0x01de 238 | #define RT5682_HP_CALIB_CTRL_2 0x01df 239 | #define RT5682_HP_CALIB_CTRL_3 0x01e0 240 | #define RT5682_HP_CALIB_CTRL_4 0x01e1 241 | #define RT5682_HP_CALIB_CTRL_5 0x01e2 242 | #define RT5682_HP_CALIB_CTRL_6 0x01e3 243 | #define RT5682_HP_CALIB_CTRL_7 0x01e4 244 | #define RT5682_HP_CALIB_CTRL_9 0x01e6 245 | #define RT5682_HP_CALIB_CTRL_10 0x01e7 246 | #define RT5682_HP_CALIB_CTRL_11 0x01e8 247 | #define RT5682_HP_CALIB_STA_1 0x01ea 248 | #define RT5682_HP_CALIB_STA_2 0x01eb 249 | #define RT5682_HP_CALIB_STA_3 0x01ec 250 | #define RT5682_HP_CALIB_STA_4 0x01ed 251 | #define RT5682_HP_CALIB_STA_5 0x01ee 252 | #define RT5682_HP_CALIB_STA_6 0x01ef 253 | #define RT5682_HP_CALIB_STA_7 0x01f0 254 | #define RT5682_HP_CALIB_STA_8 0x01f1 255 | #define RT5682_HP_CALIB_STA_9 0x01f2 256 | #define RT5682_HP_CALIB_STA_10 0x01f3 257 | #define RT5682_HP_CALIB_STA_11 0x01f4 258 | #define RT5682_SAR_IL_CMD_1 0x0210 259 | #define RT5682_SAR_IL_CMD_2 0x0211 260 | #define RT5682_SAR_IL_CMD_3 0x0212 261 | #define RT5682_SAR_IL_CMD_4 0x0213 262 | #define RT5682_SAR_IL_CMD_5 0x0214 263 | #define RT5682_SAR_IL_CMD_6 0x0215 264 | #define RT5682_SAR_IL_CMD_7 0x0216 265 | #define RT5682_SAR_IL_CMD_8 0x0217 266 | #define RT5682_SAR_IL_CMD_9 0x0218 267 | #define RT5682_SAR_IL_CMD_10 0x0219 268 | #define RT5682_SAR_IL_CMD_11 0x021a 269 | #define RT5682_SAR_IL_CMD_12 0x021b 270 | #define RT5682_SAR_IL_CMD_13 0x021c 271 | #define RT5682_EFUSE_CTRL_1 0x0250 272 | #define RT5682_EFUSE_CTRL_2 0x0251 273 | #define RT5682_EFUSE_CTRL_3 0x0252 274 | #define RT5682_EFUSE_CTRL_4 0x0253 275 | #define RT5682_EFUSE_CTRL_5 0x0254 276 | #define RT5682_EFUSE_CTRL_6 0x0255 277 | #define RT5682_EFUSE_CTRL_7 0x0256 278 | #define RT5682_EFUSE_CTRL_8 0x0257 279 | #define RT5682_EFUSE_CTRL_9 0x0258 280 | #define RT5682_EFUSE_CTRL_10 0x0259 281 | #define RT5682_EFUSE_CTRL_11 0x025a 282 | #define RT5682_JD_TOP_VC_VTRL 0x0270 283 | #define RT5682_DRC1_CTRL_0 0x02ff 284 | #define RT5682_DRC1_CTRL_1 0x0300 285 | #define RT5682_DRC1_CTRL_2 0x0301 286 | #define RT5682_DRC1_CTRL_3 0x0302 287 | #define RT5682_DRC1_CTRL_4 0x0303 288 | #define RT5682_DRC1_CTRL_5 0x0304 289 | #define RT5682_DRC1_CTRL_6 0x0305 290 | #define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306 291 | #define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307 292 | #define RT5682_DRC1_PRIV_1 0x0310 293 | #define RT5682_DRC1_PRIV_2 0x0311 294 | #define RT5682_DRC1_PRIV_3 0x0312 295 | #define RT5682_DRC1_PRIV_4 0x0313 296 | #define RT5682_DRC1_PRIV_5 0x0314 297 | #define RT5682_DRC1_PRIV_6 0x0315 298 | #define RT5682_DRC1_PRIV_7 0x0316 299 | #define RT5682_DRC1_PRIV_8 0x0317 300 | #define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0 301 | #define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1 302 | #define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2 303 | #define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3 304 | #define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4 305 | #define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5 306 | #define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6 307 | #define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7 308 | #define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8 309 | #define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9 310 | #define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca 311 | #define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb 312 | #define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc 313 | #define RT5682_ADC_L_EQ_LPF1_A1 0x03d0 314 | #define RT5682_R_EQ_LPF1_A1 0x03d1 315 | #define RT5682_L_EQ_LPF1_H0 0x03d2 316 | #define RT5682_R_EQ_LPF1_H0 0x03d3 317 | #define RT5682_L_EQ_BPF1_A1 0x03d4 318 | #define RT5682_R_EQ_BPF1_A1 0x03d5 319 | #define RT5682_L_EQ_BPF1_A2 0x03d6 320 | #define RT5682_R_EQ_BPF1_A2 0x03d7 321 | #define RT5682_L_EQ_BPF1_H0 0x03d8 322 | #define RT5682_R_EQ_BPF1_H0 0x03d9 323 | #define RT5682_L_EQ_BPF2_A1 0x03da 324 | #define RT5682_R_EQ_BPF2_A1 0x03db 325 | #define RT5682_L_EQ_BPF2_A2 0x03dc 326 | #define RT5682_R_EQ_BPF2_A2 0x03dd 327 | #define RT5682_L_EQ_BPF2_H0 0x03de 328 | #define RT5682_R_EQ_BPF2_H0 0x03df 329 | #define RT5682_L_EQ_BPF3_A1 0x03e0 330 | #define RT5682_R_EQ_BPF3_A1 0x03e1 331 | #define RT5682_L_EQ_BPF3_A2 0x03e2 332 | #define RT5682_R_EQ_BPF3_A2 0x03e3 333 | #define RT5682_L_EQ_BPF3_H0 0x03e4 334 | #define RT5682_R_EQ_BPF3_H0 0x03e5 335 | #define RT5682_L_EQ_BPF4_A1 0x03e6 336 | #define RT5682_R_EQ_BPF4_A1 0x03e7 337 | #define RT5682_L_EQ_BPF4_A2 0x03e8 338 | #define RT5682_R_EQ_BPF4_A2 0x03e9 339 | #define RT5682_L_EQ_BPF4_H0 0x03ea 340 | #define RT5682_R_EQ_BPF4_H0 0x03eb 341 | #define RT5682_L_EQ_HPF1_A1 0x03ec 342 | #define RT5682_R_EQ_HPF1_A1 0x03ed 343 | #define RT5682_L_EQ_HPF1_H0 0x03ee 344 | #define RT5682_R_EQ_HPF1_H0 0x03ef 345 | #define RT5682_L_EQ_PRE_VOL 0x03f0 346 | #define RT5682_R_EQ_PRE_VOL 0x03f1 347 | #define RT5682_L_EQ_POST_VOL 0x03f2 348 | #define RT5682_R_EQ_POST_VOL 0x03f3 349 | #define RT5682_I2C_MODE 0xffff 350 | 351 | 352 | /* global definition */ 353 | #define RT5682_L_MUTE (0x1 << 15) 354 | #define RT5682_L_MUTE_SFT 15 355 | #define RT5682_VOL_L_MUTE (0x1 << 14) 356 | #define RT5682_VOL_L_SFT 14 357 | #define RT5682_R_MUTE (0x1 << 7) 358 | #define RT5682_R_MUTE_SFT 7 359 | #define RT5682_VOL_R_MUTE (0x1 << 6) 360 | #define RT5682_VOL_R_SFT 6 361 | #define RT5682_L_VOL_MASK (0x3f << 8) 362 | #define RT5682_L_VOL_SFT 8 363 | #define RT5682_R_VOL_MASK (0x3f) 364 | #define RT5682_R_VOL_SFT 0 365 | 366 | /* Headphone Amp Control 2 (0x0003) */ 367 | #define RT5682_HP_C2_DAC_AMP_MUTE_SFT 15 368 | #define RT5682_HP_C2_DAC_AMP_MUTE (0x1 << 15) 369 | #define RT5682_HP_C2_DAC_L_EN_SFT 14 370 | #define RT5682_HP_C2_DAC_L_EN (0x1 << 14) 371 | #define RT5682_HP_C2_DAC_R_EN_SFT 13 372 | #define RT5682_HP_C2_DAC_R_EN (0x1 << 13) 373 | 374 | /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 375 | #define RT5682_G_HP (0xf << 8) 376 | #define RT5682_G_HP_SFT 8 377 | #define RT5682_G_STO_DA_DMIX (0xf) 378 | #define RT5682_G_STO_DA_SFT 0 379 | 380 | /* CBJ Control (0x000b) */ 381 | #define RT5682_BST_CBJ_MASK (0xf << 8) 382 | #define RT5682_BST_CBJ_SFT 8 383 | 384 | /* Embeeded Jack and Type Detection Control 1 (0x0010) */ 385 | #define RT5682_EMB_JD_EN (0x1 << 15) 386 | #define RT5682_EMB_JD_EN_SFT 15 387 | #define RT5682_EMB_JD_RST (0x1 << 14) 388 | #define RT5682_JD_MODE (0x1 << 13) 389 | #define RT5682_JD_MODE_SFT 13 390 | #define RT5682_DET_TYPE (0x1 << 12) 391 | #define RT5682_DET_TYPE_SFT 12 392 | #define RT5682_POLA_EXT_JD_MASK (0x1 << 11) 393 | #define RT5682_POLA_EXT_JD_LOW (0x1 << 11) 394 | #define RT5682_POLA_EXT_JD_HIGH (0x0 << 11) 395 | #define RT5682_EXT_JD_DIG (0x1 << 9) 396 | #define RT5682_POL_FAST_OFF_MASK (0x1 << 8) 397 | #define RT5682_POL_FAST_OFF_HIGH (0x1 << 8) 398 | #define RT5682_POL_FAST_OFF_LOW (0x0 << 8) 399 | #define RT5682_FAST_OFF_MASK (0x1 << 7) 400 | #define RT5682_FAST_OFF_EN (0x1 << 7) 401 | #define RT5682_FAST_OFF_DIS (0x0 << 7) 402 | #define RT5682_VREF_POW_MASK (0x1 << 6) 403 | #define RT5682_VREF_POW_FSM (0x0 << 6) 404 | #define RT5682_VREF_POW_REG (0x1 << 6) 405 | #define RT5682_MB1_PATH_MASK (0x1 << 5) 406 | #define RT5682_CTRL_MB1_REG (0x1 << 5) 407 | #define RT5682_CTRL_MB1_FSM (0x0 << 5) 408 | #define RT5682_MB2_PATH_MASK (0x1 << 4) 409 | #define RT5682_CTRL_MB2_REG (0x1 << 4) 410 | #define RT5682_CTRL_MB2_FSM (0x0 << 4) 411 | #define RT5682_TRIG_JD_MASK (0x1 << 3) 412 | #define RT5682_TRIG_JD_HIGH (0x1 << 3) 413 | #define RT5682_TRIG_JD_LOW (0x0 << 3) 414 | #define RT5682_MIC_CAP_MASK (0x1 << 1) 415 | #define RT5682_MIC_CAP_HS (0x1 << 1) 416 | #define RT5682_MIC_CAP_HP (0x0 << 1) 417 | #define RT5682_MIC_CAP_SRC_MASK (0x1) 418 | #define RT5682_MIC_CAP_SRC_REG (0x1) 419 | #define RT5682_MIC_CAP_SRC_ANA (0x0) 420 | 421 | /* Embeeded Jack and Type Detection Control 2 (0x0011) */ 422 | #define RT5682_EXT_JD_SRC (0x7 << 4) 423 | #define RT5682_EXT_JD_SRC_SFT 4 424 | #define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) 425 | #define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) 426 | #define RT5682_EXT_JD_SRC_JDH (0x2 << 4) 427 | #define RT5682_EXT_JD_SRC_JDL (0x3 << 4) 428 | #define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4) 429 | #define RT5682_JACK_TYPE_MASK (0x3) 430 | 431 | /* Combo Jack and Type Detection Control 3 (0x0012) */ 432 | #define RT5682_CBJ_IN_BUF_EN (0x1 << 7) 433 | 434 | /* Combo Jack and Type Detection Control 4 (0x0013) */ 435 | #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12) 436 | #define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12) 437 | #define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12) 438 | #define RT5682_CBJ_JD_TEST_MASK (0x1 << 6) 439 | #define RT5682_CBJ_JD_TEST_NORM (0x0 << 6) 440 | #define RT5682_CBJ_JD_TEST_MODE (0x1 << 6) 441 | 442 | /* DAC1 Digital Volume (0x0019) */ 443 | #define RT5682_DAC_L1_VOL_MASK (0xff << 8) 444 | #define RT5682_DAC_L1_VOL_SFT 8 445 | #define RT5682_DAC_R1_VOL_MASK (0xff) 446 | #define RT5682_DAC_R1_VOL_SFT 0 447 | 448 | /* ADC Digital Volume Control (0x001c) */ 449 | #define RT5682_ADC_L_VOL_MASK (0x7f << 8) 450 | #define RT5682_ADC_L_VOL_SFT 8 451 | #define RT5682_ADC_R_VOL_MASK (0x7f) 452 | #define RT5682_ADC_R_VOL_SFT 0 453 | 454 | /* Stereo1 ADC Boost Gain Control (0x001f) */ 455 | #define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14) 456 | #define RT5682_STO1_ADC_L_BST_SFT 14 457 | #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12) 458 | #define RT5682_STO1_ADC_R_BST_SFT 12 459 | 460 | /* Sidetone Control (0x0024) */ 461 | #define RT5682_ST_SRC_SEL (0x1 << 8) 462 | #define RT5682_ST_SRC_SFT 8 463 | #define RT5682_ST_EN_MASK (0x1 << 6) 464 | #define RT5682_ST_DIS (0x0 << 6) 465 | #define RT5682_ST_EN (0x1 << 6) 466 | #define RT5682_ST_EN_SFT 6 467 | 468 | /* Stereo1 ADC Mixer Control (0x0026) */ 469 | #define RT5682_M_STO1_ADC_L1 (0x1 << 15) 470 | #define RT5682_M_STO1_ADC_L1_SFT 15 471 | #define RT5682_M_STO1_ADC_L2 (0x1 << 14) 472 | #define RT5682_M_STO1_ADC_L2_SFT 14 473 | #define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13) 474 | #define RT5682_STO1_ADC1L_SRC_SFT 13 475 | #define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13) 476 | #define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13) 477 | #define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12) 478 | #define RT5682_STO1_ADC2L_SRC_SFT 12 479 | #define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10) 480 | #define RT5682_STO1_ADCL_SRC_SFT 10 481 | #define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9) 482 | #define RT5682_STO1_DD_L_SRC_SFT 9 483 | #define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8) 484 | #define RT5682_STO1_DMIC_SRC_SFT 8 485 | #define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8) 486 | #define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8) 487 | #define RT5682_M_STO1_ADC_R1 (0x1 << 7) 488 | #define RT5682_M_STO1_ADC_R1_SFT 7 489 | #define RT5682_M_STO1_ADC_R2 (0x1 << 6) 490 | #define RT5682_M_STO1_ADC_R2_SFT 6 491 | #define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5) 492 | #define RT5682_STO1_ADC1R_SRC_SFT 5 493 | #define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4) 494 | #define RT5682_STO1_ADC2R_SRC_SFT 4 495 | #define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2) 496 | #define RT5682_STO1_ADCR_SRC_SFT 2 497 | 498 | /* ADC Mixer to DAC Mixer Control (0x0029) */ 499 | #define RT5682_M_ADCMIX_L (0x1 << 15) 500 | #define RT5682_M_ADCMIX_L_SFT 15 501 | #define RT5682_M_DAC1_L (0x1 << 14) 502 | #define RT5682_M_DAC1_L_SFT 14 503 | #define RT5682_DAC1_R_SEL_MASK (0x1 << 10) 504 | #define RT5682_DAC1_R_SEL_SFT 10 505 | #define RT5682_DAC1_L_SEL_MASK (0x1 << 8) 506 | #define RT5682_DAC1_L_SEL_SFT 8 507 | #define RT5682_M_ADCMIX_R (0x1 << 7) 508 | #define RT5682_M_ADCMIX_R_SFT 7 509 | #define RT5682_M_DAC1_R (0x1 << 6) 510 | #define RT5682_M_DAC1_R_SFT 6 511 | 512 | /* Stereo1 DAC Mixer Control (0x002a) */ 513 | #define RT5682_M_DAC_L1_STO_L (0x1 << 15) 514 | #define RT5682_M_DAC_L1_STO_L_SFT 15 515 | #define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14) 516 | #define RT5682_G_DAC_L1_STO_L_SFT 14 517 | #define RT5682_M_DAC_R1_STO_L (0x1 << 13) 518 | #define RT5682_M_DAC_R1_STO_L_SFT 13 519 | #define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12) 520 | #define RT5682_G_DAC_R1_STO_L_SFT 12 521 | #define RT5682_M_DAC_L1_STO_R (0x1 << 7) 522 | #define RT5682_M_DAC_L1_STO_R_SFT 7 523 | #define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6) 524 | #define RT5682_G_DAC_L1_STO_R_SFT 6 525 | #define RT5682_M_DAC_R1_STO_R (0x1 << 5) 526 | #define RT5682_M_DAC_R1_STO_R_SFT 5 527 | #define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4) 528 | #define RT5682_G_DAC_R1_STO_R_SFT 4 529 | 530 | /* Analog DAC1 Input Source Control (0x002b) */ 531 | #define RT5682_M_ST_STO_L (0x1 << 9) 532 | #define RT5682_M_ST_STO_L_SFT 9 533 | #define RT5682_M_ST_STO_R (0x1 << 8) 534 | #define RT5682_M_ST_STO_R_SFT 8 535 | #define RT5682_DAC_L1_SRC_MASK (0x3 << 4) 536 | #define RT5682_A_DACL1_SFT 4 537 | #define RT5682_DAC_R1_SRC_MASK (0x3) 538 | #define RT5682_A_DACR1_SFT 0 539 | 540 | /* Digital Interface Data Control (0x0030) */ 541 | #define RT5682_IF2_ADC_SEL_MASK (0x3 << 0) 542 | #define RT5682_IF2_ADC_SEL_SFT 0 543 | 544 | /* REC Left Mixer Control 2 (0x003c) */ 545 | #define RT5682_G_CBJ_RM1_L (0x7 << 10) 546 | #define RT5682_G_CBJ_RM1_L_SFT 10 547 | #define RT5682_M_CBJ_RM1_L (0x1 << 7) 548 | #define RT5682_M_CBJ_RM1_L_SFT 7 549 | 550 | /* Power Management for Digital 1 (0x0061) */ 551 | #define RT5682_PWR_I2S1 (0x1 << 15) 552 | #define RT5682_PWR_I2S1_BIT 15 553 | #define RT5682_PWR_I2S2 (0x1 << 14) 554 | #define RT5682_PWR_I2S2_BIT 14 555 | #define RT5682_PWR_DAC_L1 (0x1 << 11) 556 | #define RT5682_PWR_DAC_L1_BIT 11 557 | #define RT5682_PWR_DAC_R1 (0x1 << 10) 558 | #define RT5682_PWR_DAC_R1_BIT 10 559 | #define RT5682_PWR_LDO (0x1 << 8) 560 | #define RT5682_PWR_LDO_BIT 8 561 | #define RT5682_PWR_ADC_L1 (0x1 << 4) 562 | #define RT5682_PWR_ADC_L1_BIT 4 563 | #define RT5682_PWR_ADC_R1 (0x1 << 3) 564 | #define RT5682_PWR_ADC_R1_BIT 3 565 | #define RT5682_DIG_GATE_CTRL (0x1 << 0) 566 | #define RT5682_DIG_GATE_CTRL_SFT 0 567 | 568 | 569 | /* Power Management for Digital 2 (0x0062) */ 570 | #define RT5682_PWR_ADC_S1F (0x1 << 15) 571 | #define RT5682_PWR_ADC_S1F_BIT 15 572 | #define RT5682_PWR_DAC_S1F (0x1 << 10) 573 | #define RT5682_PWR_DAC_S1F_BIT 10 574 | 575 | /* Power Management for Analog 1 (0x0063) */ 576 | #define RT5682_PWR_VREF1 (0x1 << 15) 577 | #define RT5682_PWR_VREF1_BIT 15 578 | #define RT5682_PWR_FV1 (0x1 << 14) 579 | #define RT5682_PWR_FV1_BIT 14 580 | #define RT5682_PWR_VREF2 (0x1 << 13) 581 | #define RT5682_PWR_VREF2_BIT 13 582 | #define RT5682_PWR_FV2 (0x1 << 12) 583 | #define RT5682_PWR_FV2_BIT 12 584 | #define RT5682_LDO1_DBG_MASK (0x3 << 10) 585 | #define RT5682_PWR_MB (0x1 << 9) 586 | #define RT5682_PWR_MB_BIT 9 587 | #define RT5682_PWR_BG (0x1 << 7) 588 | #define RT5682_PWR_BG_BIT 7 589 | #define RT5682_LDO1_BYPASS_MASK (0x1 << 6) 590 | #define RT5682_LDO1_BYPASS (0x1 << 6) 591 | #define RT5682_LDO1_NOT_BYPASS (0x0 << 6) 592 | #define RT5682_PWR_MA_BIT 6 593 | #define RT5682_LDO1_DVO_MASK (0x3 << 4) 594 | #define RT5682_LDO1_DVO_09 (0x0 << 4) 595 | #define RT5682_LDO1_DVO_10 (0x1 << 4) 596 | #define RT5682_LDO1_DVO_12 (0x2 << 4) 597 | #define RT5682_LDO1_DVO_14 (0x3 << 4) 598 | #define RT5682_HP_DRIVER_MASK (0x3 << 2) 599 | #define RT5682_HP_DRIVER_1X (0x0 << 2) 600 | #define RT5682_HP_DRIVER_3X (0x1 << 2) 601 | #define RT5682_HP_DRIVER_5X (0x3 << 2) 602 | #define RT5682_PWR_HA_L (0x1 << 1) 603 | #define RT5682_PWR_HA_L_BIT 1 604 | #define RT5682_PWR_HA_R (0x1 << 0) 605 | #define RT5682_PWR_HA_R_BIT 0 606 | 607 | /* Power Management for Analog 2 (0x0064) */ 608 | #define RT5682_PWR_MB1 (0x1 << 11) 609 | #define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11) 610 | #define RT5682_PWR_MB1_BIT 11 611 | #define RT5682_PWR_MB2 (0x1 << 10) 612 | #define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10) 613 | #define RT5682_PWR_MB2_BIT 10 614 | #define RT5682_PWR_JDH (0x1 << 3) 615 | #define RT5682_PWR_JDH_BIT 3 616 | #define RT5682_PWR_JDL (0x1 << 2) 617 | #define RT5682_PWR_JDL_BIT 2 618 | #define RT5682_PWR_RM1_L (0x1 << 1) 619 | #define RT5682_PWR_RM1_L_BIT 1 620 | 621 | /* Power Management for Analog 3 (0x0065) */ 622 | #define RT5682_PWR_CBJ (0x1 << 9) 623 | #define RT5682_PWR_CBJ_BIT 9 624 | #define RT5682_PWR_PLL (0x1 << 6) 625 | #define RT5682_PWR_PLL_BIT 6 626 | #define RT5682_PWR_PLL2B (0x1 << 5) 627 | #define RT5682_PWR_PLL2B_BIT 5 628 | #define RT5682_PWR_PLL2F (0x1 << 4) 629 | #define RT5682_PWR_PLL2F_BIT 4 630 | #define RT5682_PWR_LDO2 (0x1 << 2) 631 | #define RT5682_PWR_LDO2_BIT 2 632 | #define RT5682_PWR_DET_SPKVDD (0x1 << 1) 633 | #define RT5682_PWR_DET_SPKVDD_BIT 1 634 | 635 | /* Power Management for Mixer (0x0066) */ 636 | #define RT5682_PWR_STO1_DAC_L (0x1 << 5) 637 | #define RT5682_PWR_STO1_DAC_L_BIT 5 638 | #define RT5682_PWR_STO1_DAC_R (0x1 << 4) 639 | #define RT5682_PWR_STO1_DAC_R_BIT 4 640 | 641 | /* MCLK and System Clock Detection Control (0x006b) */ 642 | #define RT5682_SYS_CLK_DET (0x1 << 15) 643 | #define RT5682_SYS_CLK_DET_SFT 15 644 | #define RT5682_PLL1_CLK_DET (0x1 << 14) 645 | #define RT5682_PLL1_CLK_DET_SFT 14 646 | #define RT5682_PLL2_CLK_DET (0x1 << 13) 647 | #define RT5682_PLL2_CLK_DET_SFT 13 648 | #define RT5682_POW_CLK_DET2_SFT 8 649 | #define RT5682_POW_CLK_DET_SFT 0 650 | 651 | /* Digital Microphone Control 1 (0x006e) */ 652 | #define RT5682_DMIC_1_EN_MASK (0x1 << 15) 653 | #define RT5682_DMIC_1_EN_SFT 15 654 | #define RT5682_DMIC_1_DIS (0x0 << 15) 655 | #define RT5682_DMIC_1_EN (0x1 << 15) 656 | #define RT5682_FIFO_CLK_DIV_MASK (0x7 << 12) 657 | #define RT5682_FIFO_CLK_DIV_2 (0x1 << 12) 658 | #define RT5682_DMIC_1_DP_MASK (0x3 << 4) 659 | #define RT5682_DMIC_1_DP_SFT 4 660 | #define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4) 661 | #define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4) 662 | #define RT5682_DMIC_CLK_MASK (0xf << 0) 663 | #define RT5682_DMIC_CLK_SFT 0 664 | 665 | /* I2S1 Audio Serial Data Port Control (0x0070) */ 666 | #define RT5682_SEL_ADCDAT_MASK (0x1 << 15) 667 | #define RT5682_SEL_ADCDAT_OUT (0x0 << 15) 668 | #define RT5682_SEL_ADCDAT_IN (0x1 << 15) 669 | #define RT5682_SEL_ADCDAT_SFT 15 670 | #define RT5682_I2S1_TX_CHL_MASK (0x7 << 12) 671 | #define RT5682_I2S1_TX_CHL_SFT 12 672 | #define RT5682_I2S1_TX_CHL_16 (0x0 << 12) 673 | #define RT5682_I2S1_TX_CHL_20 (0x1 << 12) 674 | #define RT5682_I2S1_TX_CHL_24 (0x2 << 12) 675 | #define RT5682_I2S1_TX_CHL_32 (0x3 << 12) 676 | #define RT5682_I2S1_TX_CHL_8 (0x4 << 12) 677 | #define RT5682_I2S1_RX_CHL_MASK (0x7 << 8) 678 | #define RT5682_I2S1_RX_CHL_SFT 8 679 | #define RT5682_I2S1_RX_CHL_16 (0x0 << 8) 680 | #define RT5682_I2S1_RX_CHL_20 (0x1 << 8) 681 | #define RT5682_I2S1_RX_CHL_24 (0x2 << 8) 682 | #define RT5682_I2S1_RX_CHL_32 (0x3 << 8) 683 | #define RT5682_I2S1_RX_CHL_8 (0x4 << 8) 684 | #define RT5682_I2S1_MONO_MASK (0x1 << 7) 685 | #define RT5682_I2S1_MONO_EN (0x1 << 7) 686 | #define RT5682_I2S1_MONO_DIS (0x0 << 7) 687 | #define RT5682_I2S2_MONO_MASK (0x1 << 6) 688 | #define RT5682_I2S2_MONO_EN (0x1 << 6) 689 | #define RT5682_I2S2_MONO_DIS (0x0 << 6) 690 | #define RT5682_I2S1_DL_MASK (0x7 << 4) 691 | #define RT5682_I2S1_DL_SFT 4 692 | #define RT5682_I2S1_DL_16 (0x0 << 4) 693 | #define RT5682_I2S1_DL_20 (0x1 << 4) 694 | #define RT5682_I2S1_DL_24 (0x2 << 4) 695 | #define RT5682_I2S1_DL_32 (0x3 << 4) 696 | #define RT5682_I2S1_DL_8 (0x4 << 4) 697 | 698 | /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ 699 | #define RT5682_I2S2_MS_MASK (0x1 << 15) 700 | #define RT5682_I2S2_MS_SFT 15 701 | #define RT5682_I2S2_MS_M (0x0 << 15) 702 | #define RT5682_I2S2_MS_S (0x1 << 15) 703 | #define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14) 704 | #define RT5682_I2S2_PIN_CFG_SFT 14 705 | #define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11) 706 | #define RT5682_I2S2_CLK_SEL_SFT 11 707 | #define RT5682_I2S2_OUT_MASK (0x1 << 9) 708 | #define RT5682_I2S2_OUT_SFT 9 709 | #define RT5682_I2S2_OUT_UM (0x0 << 9) 710 | #define RT5682_I2S2_OUT_M (0x1 << 9) 711 | #define RT5682_I2S_BP_MASK (0x1 << 8) 712 | #define RT5682_I2S_BP_SFT 8 713 | #define RT5682_I2S_BP_NOR (0x0 << 8) 714 | #define RT5682_I2S_BP_INV (0x1 << 8) 715 | #define RT5682_I2S2_MONO_EN (0x1 << 6) 716 | #define RT5682_I2S2_MONO_DIS (0x0 << 6) 717 | #define RT5682_I2S2_DL_MASK (0x3 << 4) 718 | #define RT5682_I2S2_DL_SFT 4 719 | #define RT5682_I2S2_DL_16 (0x0 << 4) 720 | #define RT5682_I2S2_DL_20 (0x1 << 4) 721 | #define RT5682_I2S2_DL_24 (0x2 << 4) 722 | #define RT5682_I2S2_DL_8 (0x3 << 4) 723 | #define RT5682_I2S_DF_MASK (0x7) 724 | #define RT5682_I2S_DF_SFT 0 725 | #define RT5682_I2S_DF_I2S (0x0) 726 | #define RT5682_I2S_DF_LEFT (0x1) 727 | #define RT5682_I2S_DF_PCM_A (0x2) 728 | #define RT5682_I2S_DF_PCM_B (0x3) 729 | #define RT5682_I2S_DF_PCM_A_N (0x6) 730 | #define RT5682_I2S_DF_PCM_B_N (0x7) 731 | 732 | /* ADC/DAC Clock Control 1 (0x0073) */ 733 | #define RT5682_ADC_OSR_MASK (0xf << 12) 734 | #define RT5682_ADC_OSR_SFT 12 735 | #define RT5682_ADC_OSR_D_1 (0x0 << 12) 736 | #define RT5682_ADC_OSR_D_2 (0x1 << 12) 737 | #define RT5682_ADC_OSR_D_4 (0x2 << 12) 738 | #define RT5682_ADC_OSR_D_6 (0x3 << 12) 739 | #define RT5682_ADC_OSR_D_8 (0x4 << 12) 740 | #define RT5682_ADC_OSR_D_12 (0x5 << 12) 741 | #define RT5682_ADC_OSR_D_16 (0x6 << 12) 742 | #define RT5682_ADC_OSR_D_24 (0x7 << 12) 743 | #define RT5682_ADC_OSR_D_32 (0x8 << 12) 744 | #define RT5682_ADC_OSR_D_48 (0x9 << 12) 745 | #define RT5682_I2S_M_DIV_MASK (0xf << 8) 746 | #define RT5682_I2S_M_DIV_SFT 8 747 | #define RT5682_I2S_M_D_1 (0x0 << 8) 748 | #define RT5682_I2S_M_D_2 (0x1 << 8) 749 | #define RT5682_I2S_M_D_3 (0x2 << 8) 750 | #define RT5682_I2S_M_D_4 (0x3 << 8) 751 | #define RT5682_I2S_M_D_6 (0x4 << 8) 752 | #define RT5682_I2S_M_D_8 (0x5 << 8) 753 | #define RT5682_I2S_M_D_12 (0x6 << 8) 754 | #define RT5682_I2S_M_D_16 (0x7 << 8) 755 | #define RT5682_I2S_M_D_24 (0x8 << 8) 756 | #define RT5682_I2S_M_D_32 (0x9 << 8) 757 | #define RT5682_I2S_M_D_48 (0x10 << 8) 758 | #define RT5682_I2S_CLK_SRC_MASK (0x7 << 4) 759 | #define RT5682_I2S_CLK_SRC_SFT 4 760 | #define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4) 761 | #define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4) 762 | #define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4) 763 | #define RT5682_I2S_CLK_SRC_SDW (0x3 << 4) 764 | #define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */ 765 | #define RT5682_DAC_OSR_MASK (0xf << 0) 766 | #define RT5682_DAC_OSR_SFT 0 767 | #define RT5682_DAC_OSR_D_1 (0x0 << 0) 768 | #define RT5682_DAC_OSR_D_2 (0x1 << 0) 769 | #define RT5682_DAC_OSR_D_4 (0x2 << 0) 770 | #define RT5682_DAC_OSR_D_6 (0x3 << 0) 771 | #define RT5682_DAC_OSR_D_8 (0x4 << 0) 772 | #define RT5682_DAC_OSR_D_12 (0x5 << 0) 773 | #define RT5682_DAC_OSR_D_16 (0x6 << 0) 774 | #define RT5682_DAC_OSR_D_24 (0x7 << 0) 775 | #define RT5682_DAC_OSR_D_32 (0x8 << 0) 776 | #define RT5682_DAC_OSR_D_48 (0x9 << 0) 777 | 778 | /* ADC/DAC Clock Control 2 (0x0074) */ 779 | #define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11) 780 | #define RT5682_I2S2_BCLK_MS2_SFT 11 781 | #define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11) 782 | #define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11) 783 | 784 | 785 | /* TDM control 1 (0x0079) */ 786 | #define RT5682_TDM_TX_CH_MASK (0x3 << 12) 787 | #define RT5682_TDM_TX_CH_2 (0x0 << 12) 788 | #define RT5682_TDM_TX_CH_4 (0x1 << 12) 789 | #define RT5682_TDM_TX_CH_6 (0x2 << 12) 790 | #define RT5682_TDM_TX_CH_8 (0x3 << 12) 791 | #define RT5682_TDM_RX_CH_MASK (0x3 << 8) 792 | #define RT5682_TDM_RX_CH_2 (0x0 << 8) 793 | #define RT5682_TDM_RX_CH_4 (0x1 << 8) 794 | #define RT5682_TDM_RX_CH_6 (0x2 << 8) 795 | #define RT5682_TDM_RX_CH_8 (0x3 << 8) 796 | #define RT5682_TDM_ADC_LCA_MASK (0xf << 4) 797 | #define RT5682_TDM_ADC_LCA_SFT 4 798 | #define RT5682_TDM_ADC_DL_SFT 0 799 | 800 | /* TDM control 2 (0x007a) */ 801 | #define RT5682_IF1_ADC1_SEL_SFT 14 802 | #define RT5682_IF1_ADC2_SEL_SFT 12 803 | #define RT5682_IF1_ADC3_SEL_SFT 10 804 | #define RT5682_IF1_ADC4_SEL_SFT 8 805 | #define RT5682_TDM_ADC_SEL_SFT 4 806 | 807 | /* TDM control 3 (0x007b) */ 808 | #define RT5682_TDM_EN (0x1 << 7) 809 | 810 | /* TDM/I2S control (0x007e) */ 811 | #define RT5682_TDM_S_BP_MASK (0x1 << 15) 812 | #define RT5682_TDM_S_BP_SFT 15 813 | #define RT5682_TDM_S_BP_NOR (0x0 << 15) 814 | #define RT5682_TDM_S_BP_INV (0x1 << 15) 815 | #define RT5682_TDM_S_LP_MASK (0x1 << 14) 816 | #define RT5682_TDM_S_LP_SFT 14 817 | #define RT5682_TDM_S_LP_NOR (0x0 << 14) 818 | #define RT5682_TDM_S_LP_INV (0x1 << 14) 819 | #define RT5682_TDM_DF_MASK (0x7 << 11) 820 | #define RT5682_TDM_DF_SFT 11 821 | #define RT5682_TDM_DF_I2S (0x0 << 11) 822 | #define RT5682_TDM_DF_LEFT (0x1 << 11) 823 | #define RT5682_TDM_DF_PCM_A (0x2 << 11) 824 | #define RT5682_TDM_DF_PCM_B (0x3 << 11) 825 | #define RT5682_TDM_DF_PCM_A_N (0x6 << 11) 826 | #define RT5682_TDM_DF_PCM_B_N (0x7 << 11) 827 | #define RT5682_TDM_BCLK_MS1_MASK (0x3 << 9) 828 | #define RT5682_TDM_BCLK_MS1_SFT 9 829 | #define RT5682_TDM_BCLK_MS1_32 (0x0 << 9) 830 | #define RT5682_TDM_BCLK_MS1_64 (0x1 << 9) 831 | #define RT5682_TDM_BCLK_MS1_128 (0x2 << 9) 832 | #define RT5682_TDM_BCLK_MS1_256 (0x3 << 9) 833 | #define RT5682_TDM_CL_MASK (0x3 << 4) 834 | #define RT5682_TDM_CL_16 (0x0 << 4) 835 | #define RT5682_TDM_CL_20 (0x1 << 4) 836 | #define RT5682_TDM_CL_24 (0x2 << 4) 837 | #define RT5682_TDM_CL_32 (0x3 << 4) 838 | #define RT5682_TDM_M_BP_MASK (0x1 << 2) 839 | #define RT5682_TDM_M_BP_SFT 2 840 | #define RT5682_TDM_M_BP_NOR (0x0 << 2) 841 | #define RT5682_TDM_M_BP_INV (0x1 << 2) 842 | #define RT5682_TDM_M_LP_MASK (0x1 << 1) 843 | #define RT5682_TDM_M_LP_SFT 1 844 | #define RT5682_TDM_M_LP_NOR (0x0 << 1) 845 | #define RT5682_TDM_M_LP_INV (0x1 << 1) 846 | #define RT5682_TDM_MS_MASK (0x1 << 0) 847 | #define RT5682_TDM_MS_SFT 0 848 | #define RT5682_TDM_MS_S (0x0 << 0) 849 | #define RT5682_TDM_MS_M (0x1 << 0) 850 | 851 | /* Global Clock Control (0x0080) */ 852 | #define RT5682_SCLK_SRC_MASK (0x7 << 13) 853 | #define RT5682_SCLK_SRC_SFT 13 854 | #define RT5682_SCLK_SRC_MCLK (0x0 << 13) 855 | #define RT5682_SCLK_SRC_PLL1 (0x1 << 13) 856 | #define RT5682_SCLK_SRC_PLL2 (0x2 << 13) 857 | #define RT5682_SCLK_SRC_SDW (0x3 << 13) 858 | #define RT5682_SCLK_SRC_RCCLK (0x4 << 13) 859 | #define RT5682_PLL2_SRC_MASK (0x3 << 10) 860 | #define RT5682_PLL2_SRC_SFT 10 861 | #define RT5682_PLL2_SRC_MCLK (0x0 << 10) 862 | #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) 863 | #define RT5682_PLL2_SRC_SDW (0x2 << 10) 864 | #define RT5682_PLL2_SRC_RC (0x3 << 10) 865 | #define RT5682_PLL1_SRC_MASK (0x3 << 8) 866 | #define RT5682_PLL1_SRC_SFT 8 867 | #define RT5682_PLL1_SRC_MCLK (0x0 << 8) 868 | #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) 869 | #define RT5682_PLL1_SRC_SDW (0x2 << 8) 870 | #define RT5682_PLL1_SRC_RC (0x3 << 8) 871 | 872 | 873 | 874 | #define RT5682_PLL_INP_MAX 40000000 875 | #define RT5682_PLL_INP_MIN 256000 876 | /* PLL M/N/K Code Control 1 (0x0081) */ 877 | #define RT5682_PLL_N_MAX 0x001ff 878 | #define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7) 879 | #define RT5682_PLL_N_SFT 7 880 | #define RT5682_PLL_K_MAX 0x001f 881 | #define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX) 882 | #define RT5682_PLL_K_SFT 0 883 | 884 | /* PLL M/N/K Code Control 2 (0x0082) */ 885 | #define RT5682_PLL_M_MAX 0x00f 886 | #define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12) 887 | #define RT5682_PLL_M_SFT 12 888 | #define RT5682_PLL_M_BP (0x1 << 11) 889 | #define RT5682_PLL_M_BP_SFT 11 890 | #define RT5682_PLL_K_BP (0x1 << 10) 891 | #define RT5682_PLL_K_BP_SFT 10 892 | #define RT5682_PLL_RST (0x1 << 1) 893 | 894 | /* PLL tracking mode 1 (0x0083) */ 895 | #define RT5682_DA_ASRC_MASK (0x1 << 13) 896 | #define RT5682_DA_ASRC_SFT 13 897 | #define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12) 898 | #define RT5682_DAC_STO1_ASRC_SFT 12 899 | #define RT5682_AD_ASRC_MASK (0x1 << 8) 900 | #define RT5682_AD_ASRC_SFT 8 901 | #define RT5682_AD_ASRC_SEL_MASK (0x1 << 4) 902 | #define RT5682_AD_ASRC_SEL_SFT 4 903 | #define RT5682_DMIC_ASRC_MASK (0x1 << 3) 904 | #define RT5682_DMIC_ASRC_SFT 3 905 | #define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2) 906 | #define RT5682_ADC_STO1_ASRC_SFT 2 907 | #define RT5682_DA_ASRC_SEL_MASK (0x1 << 0) 908 | #define RT5682_DA_ASRC_SEL_SFT 0 909 | 910 | /* PLL tracking mode 2 3 (0x0084)(0x0085)*/ 911 | #define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12) 912 | #define RT5682_FILTER_CLK_SEL_SFT 12 913 | #define RT5682_FILTER_CLK_DIV_MASK (0xf << 8) 914 | #define RT5682_FILTER_CLK_DIV_SFT 8 915 | 916 | /* ASRC Control 4 (0x0086) */ 917 | #define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14) 918 | #define RT5682_ASRCIN_FTK_N1_SFT 14 919 | #define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12) 920 | #define RT5682_ASRCIN_FTK_N2_SFT 12 921 | #define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8) 922 | #define RT5682_ASRCIN_FTK_M1_SFT 8 923 | #define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4) 924 | #define RT5682_ASRCIN_FTK_M2_SFT 4 925 | 926 | /* SoundWire reference clk (0x008d) */ 927 | #define RT5682_PLL2_OUT_MASK (0x1 << 8) 928 | #define RT5682_PLL2_OUT_98M (0x0 << 8) 929 | #define RT5682_PLL2_OUT_49M (0x1 << 8) 930 | #define RT5682_SDW_REF_2_MASK (0xf << 4) 931 | #define RT5682_SDW_REF_2_SFT 4 932 | #define RT5682_SDW_REF_2_48K (0x0 << 4) 933 | #define RT5682_SDW_REF_2_96K (0x1 << 4) 934 | #define RT5682_SDW_REF_2_192K (0x2 << 4) 935 | #define RT5682_SDW_REF_2_32K (0x3 << 4) 936 | #define RT5682_SDW_REF_2_24K (0x4 << 4) 937 | #define RT5682_SDW_REF_2_16K (0x5 << 4) 938 | #define RT5682_SDW_REF_2_12K (0x6 << 4) 939 | #define RT5682_SDW_REF_2_8K (0x7 << 4) 940 | #define RT5682_SDW_REF_2_44K (0x8 << 4) 941 | #define RT5682_SDW_REF_2_88K (0x9 << 4) 942 | #define RT5682_SDW_REF_2_176K (0xa << 4) 943 | #define RT5682_SDW_REF_2_353K (0xb << 4) 944 | #define RT5682_SDW_REF_2_22K (0xc << 4) 945 | #define RT5682_SDW_REF_2_384K (0xd << 4) 946 | #define RT5682_SDW_REF_2_11K (0xe << 4) 947 | #define RT5682_SDW_REF_1_MASK (0xf << 0) 948 | #define RT5682_SDW_REF_1_SFT 0 949 | #define RT5682_SDW_REF_1_48K (0x0 << 0) 950 | #define RT5682_SDW_REF_1_96K (0x1 << 0) 951 | #define RT5682_SDW_REF_1_192K (0x2 << 0) 952 | #define RT5682_SDW_REF_1_32K (0x3 << 0) 953 | #define RT5682_SDW_REF_1_24K (0x4 << 0) 954 | #define RT5682_SDW_REF_1_16K (0x5 << 0) 955 | #define RT5682_SDW_REF_1_12K (0x6 << 0) 956 | #define RT5682_SDW_REF_1_8K (0x7 << 0) 957 | #define RT5682_SDW_REF_1_44K (0x8 << 0) 958 | #define RT5682_SDW_REF_1_88K (0x9 << 0) 959 | #define RT5682_SDW_REF_1_176K (0xa << 0) 960 | #define RT5682_SDW_REF_1_353K (0xb << 0) 961 | #define RT5682_SDW_REF_1_22K (0xc << 0) 962 | #define RT5682_SDW_REF_1_384K (0xd << 0) 963 | #define RT5682_SDW_REF_1_11K (0xe << 0) 964 | 965 | /* Depop Mode Control 1 (0x008e) */ 966 | #define RT5682_PUMP_EN (0x1 << 3) 967 | #define RT5682_PUMP_EN_SFT 3 968 | #define RT5682_CAPLESS_EN (0x1 << 0) 969 | #define RT5682_CAPLESS_EN_SFT 0 970 | 971 | /* Depop Mode Control 2 (0x8f) */ 972 | #define RT5682_RAMP_MASK (0x1 << 12) 973 | #define RT5682_RAMP_SFT 12 974 | #define RT5682_RAMP_DIS (0x0 << 12) 975 | #define RT5682_RAMP_EN (0x1 << 12) 976 | #define RT5682_BPS_MASK (0x1 << 11) 977 | #define RT5682_BPS_SFT 11 978 | #define RT5682_BPS_DIS (0x0 << 11) 979 | #define RT5682_BPS_EN (0x1 << 11) 980 | #define RT5682_FAST_UPDN_MASK (0x1 << 10) 981 | #define RT5682_FAST_UPDN_SFT 10 982 | #define RT5682_FAST_UPDN_DIS (0x0 << 10) 983 | #define RT5682_FAST_UPDN_EN (0x1 << 10) 984 | #define RT5682_VLO_MASK (0x1 << 7) 985 | #define RT5682_VLO_SFT 7 986 | #define RT5682_VLO_3V (0x0 << 7) 987 | #define RT5682_VLO_33V (0x1 << 7) 988 | 989 | /* HPOUT charge pump 1 (0x0091) */ 990 | #define RT5682_OSW_L_MASK (0x1 << 11) 991 | #define RT5682_OSW_L_SFT 11 992 | #define RT5682_OSW_L_DIS (0x0 << 11) 993 | #define RT5682_OSW_L_EN (0x1 << 11) 994 | #define RT5682_OSW_R_MASK (0x1 << 10) 995 | #define RT5682_OSW_R_SFT 10 996 | #define RT5682_OSW_R_DIS (0x0 << 10) 997 | #define RT5682_OSW_R_EN (0x1 << 10) 998 | #define RT5682_PM_HP_MASK (0x3 << 8) 999 | #define RT5682_PM_HP_SFT 8 1000 | #define RT5682_PM_HP_LV (0x0 << 8) 1001 | #define RT5682_PM_HP_MV (0x1 << 8) 1002 | #define RT5682_PM_HP_HV (0x2 << 8) 1003 | #define RT5682_IB_HP_MASK (0x3 << 6) 1004 | #define RT5682_IB_HP_SFT 6 1005 | #define RT5682_IB_HP_125IL (0x0 << 6) 1006 | #define RT5682_IB_HP_25IL (0x1 << 6) 1007 | #define RT5682_IB_HP_5IL (0x2 << 6) 1008 | #define RT5682_IB_HP_1IL (0x3 << 6) 1009 | 1010 | /* Micbias Control1 (0x93) */ 1011 | #define RT5682_MIC1_OV_MASK (0x3 << 14) 1012 | #define RT5682_MIC1_OV_SFT 14 1013 | #define RT5682_MIC1_OV_2V7 (0x0 << 14) 1014 | #define RT5682_MIC1_OV_2V4 (0x1 << 14) 1015 | #define RT5682_MIC1_OV_2V25 (0x3 << 14) 1016 | #define RT5682_MIC1_OV_1V8 (0x4 << 14) 1017 | #define RT5682_MIC1_CLK_MASK (0x1 << 13) 1018 | #define RT5682_MIC1_CLK_SFT 13 1019 | #define RT5682_MIC1_CLK_DIS (0x0 << 13) 1020 | #define RT5682_MIC1_CLK_EN (0x1 << 13) 1021 | #define RT5682_MIC1_OVCD_MASK (0x1 << 12) 1022 | #define RT5682_MIC1_OVCD_SFT 12 1023 | #define RT5682_MIC1_OVCD_DIS (0x0 << 12) 1024 | #define RT5682_MIC1_OVCD_EN (0x1 << 12) 1025 | #define RT5682_MIC1_OVTH_MASK (0x3 << 10) 1026 | #define RT5682_MIC1_OVTH_SFT 10 1027 | #define RT5682_MIC1_OVTH_768UA (0x0 << 10) 1028 | #define RT5682_MIC1_OVTH_960UA (0x1 << 10) 1029 | #define RT5682_MIC1_OVTH_1152UA (0x2 << 10) 1030 | #define RT5682_MIC1_OVTH_1960UA (0x3 << 10) 1031 | #define RT5682_MIC2_OV_MASK (0x3 << 8) 1032 | #define RT5682_MIC2_OV_SFT 8 1033 | #define RT5682_MIC2_OV_2V7 (0x0 << 8) 1034 | #define RT5682_MIC2_OV_2V4 (0x1 << 8) 1035 | #define RT5682_MIC2_OV_2V25 (0x3 << 8) 1036 | #define RT5682_MIC2_OV_1V8 (0x4 << 8) 1037 | #define RT5682_MIC2_CLK_MASK (0x1 << 7) 1038 | #define RT5682_MIC2_CLK_SFT 7 1039 | #define RT5682_MIC2_CLK_DIS (0x0 << 7) 1040 | #define RT5682_MIC2_CLK_EN (0x1 << 7) 1041 | #define RT5682_MIC2_OVTH_MASK (0x3 << 4) 1042 | #define RT5682_MIC2_OVTH_SFT 4 1043 | #define RT5682_MIC2_OVTH_768UA (0x0 << 4) 1044 | #define RT5682_MIC2_OVTH_960UA (0x1 << 4) 1045 | #define RT5682_MIC2_OVTH_1152UA (0x2 << 4) 1046 | #define RT5682_MIC2_OVTH_1960UA (0x3 << 4) 1047 | #define RT5682_PWR_MB_MASK (0x1 << 3) 1048 | #define RT5682_PWR_MB_SFT 3 1049 | #define RT5682_PWR_MB_PD (0x0 << 3) 1050 | #define RT5682_PWR_MB_PU (0x1 << 3) 1051 | 1052 | /* Micbias Control2 (0x0094) */ 1053 | #define RT5682_PWR_CLK25M_MASK (0x1 << 9) 1054 | #define RT5682_PWR_CLK25M_SFT 9 1055 | #define RT5682_PWR_CLK25M_PD (0x0 << 9) 1056 | #define RT5682_PWR_CLK25M_PU (0x1 << 9) 1057 | #define RT5682_PWR_CLK1M_MASK (0x1 << 8) 1058 | #define RT5682_PWR_CLK1M_SFT 8 1059 | #define RT5682_PWR_CLK1M_PD (0x0 << 8) 1060 | #define RT5682_PWR_CLK1M_PU (0x1 << 8) 1061 | 1062 | /* PLL2 M/N/K Code Control 1 (0x009b) */ 1063 | #define RT5682_PLL2F_K_MASK (0x1f << 8) 1064 | #define RT5682_PLL2F_K_SFT 8 1065 | #define RT5682_PLL2B_K_MASK (0xf << 4) 1066 | #define RT5682_PLL2B_K_SFT 4 1067 | #define RT5682_PLL2B_M_MASK (0xf << 0) 1068 | 1069 | /* PLL2 M/N/K Code Control 2 (0x009c) */ 1070 | #define RT5682_PLL2F_M_MASK (0x3f << 8) 1071 | #define RT5682_PLL2F_M_SFT 8 1072 | #define RT5682_PLL2B_N_MASK (0x3f << 0) 1073 | 1074 | /* PLL2 M/N/K Code Control 2 (0x009d) */ 1075 | #define RT5682_PLL2F_N_MASK (0x7f << 8) 1076 | #define RT5682_PLL2F_N_SFT 8 1077 | 1078 | /* PLL2 M/N/K Code Control 2 (0x009e) */ 1079 | #define RT5682_PLL2B_SEL_PS_MASK (0x1 << 13) 1080 | #define RT5682_PLL2B_SEL_PS_SFT 13 1081 | #define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12) 1082 | #define RT5682_PLL2B_PS_BYP_SFT 12 1083 | #define RT5682_PLL2B_M_BP_MASK (0x1 << 11) 1084 | #define RT5682_PLL2B_M_BP_SFT 11 1085 | #define RT5682_PLL2F_M_BP_MASK (0x1 << 7) 1086 | #define RT5682_PLL2F_M_BP_SFT 7 1087 | 1088 | /* RC Clock Control (0x009f) */ 1089 | #define RT5682_POW_IRQ (0x1 << 15) 1090 | #define RT5682_POW_JDH (0x1 << 14) 1091 | #define RT5682_POW_JDL (0x1 << 13) 1092 | #define RT5682_POW_ANA (0x1 << 12) 1093 | 1094 | /* I2S Master Mode Clock Control 1 (0x00a0) */ 1095 | #define RT5682_CLK_SRC_MCLK (0x0) 1096 | #define RT5682_CLK_SRC_PLL1 (0x1) 1097 | #define RT5682_CLK_SRC_PLL2 (0x2) 1098 | #define RT5682_CLK_SRC_SDW (0x3) 1099 | #define RT5682_CLK_SRC_RCCLK (0x4) 1100 | #define RT5682_I2S_PD_1 (0x0) 1101 | #define RT5682_I2S_PD_2 (0x1) 1102 | #define RT5682_I2S_PD_3 (0x2) 1103 | #define RT5682_I2S_PD_4 (0x3) 1104 | #define RT5682_I2S_PD_6 (0x4) 1105 | #define RT5682_I2S_PD_8 (0x5) 1106 | #define RT5682_I2S_PD_12 (0x6) 1107 | #define RT5682_I2S_PD_16 (0x7) 1108 | #define RT5682_I2S_PD_24 (0x8) 1109 | #define RT5682_I2S_PD_32 (0x9) 1110 | #define RT5682_I2S_PD_48 (0xa) 1111 | #define RT5682_I2S2_SRC_MASK (0x3 << 4) 1112 | #define RT5682_I2S2_SRC_SFT 4 1113 | #define RT5682_I2S2_M_PD_MASK (0xf << 0) 1114 | #define RT5682_I2S2_M_PD_SFT 0 1115 | 1116 | /* IRQ Control 1 (0x00b6) */ 1117 | #define RT5682_JD1_PULSE_EN_MASK (0x1 << 10) 1118 | #define RT5682_JD1_PULSE_EN_SFT 10 1119 | #define RT5682_JD1_PULSE_DIS (0x0 << 10) 1120 | #define RT5682_JD1_PULSE_EN (0x1 << 10) 1121 | 1122 | /* IRQ Control 2 (0x00b7) */ 1123 | #define RT5682_JD1_EN_MASK (0x1 << 15) 1124 | #define RT5682_JD1_EN_SFT 15 1125 | #define RT5682_JD1_DIS (0x0 << 15) 1126 | #define RT5682_JD1_EN (0x1 << 15) 1127 | #define RT5682_JD1_POL_MASK (0x1 << 13) 1128 | #define RT5682_JD1_POL_NOR (0x0 << 13) 1129 | #define RT5682_JD1_POL_INV (0x1 << 13) 1130 | #define RT5682_JD1_IRQ_MASK (0x1 << 10) 1131 | #define RT5682_JD1_IRQ_LEV (0x0 << 10) 1132 | #define RT5682_JD1_IRQ_PUL (0x1 << 10) 1133 | 1134 | /* IRQ Control 3 (0x00b8) */ 1135 | #define RT5682_IL_IRQ_MASK (0x1 << 7) 1136 | #define RT5682_IL_IRQ_DIS (0x0 << 7) 1137 | #define RT5682_IL_IRQ_EN (0x1 << 7) 1138 | #define RT5682_IL_IRQ_TYPE_MASK (0x1 << 4) 1139 | #define RT5682_IL_IRQ_LEV (0x0 << 4) 1140 | #define RT5682_IL_IRQ_PUL (0x1 << 4) 1141 | 1142 | /* GPIO Control 1 (0x00c0) */ 1143 | #define RT5682_GP1_PIN_MASK (0x3 << 14) 1144 | #define RT5682_GP1_PIN_SFT 14 1145 | #define RT5682_GP1_PIN_GPIO1 (0x0 << 14) 1146 | #define RT5682_GP1_PIN_IRQ (0x1 << 14) 1147 | #define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14) 1148 | #define RT5682_GP2_PIN_MASK (0x3 << 12) 1149 | #define RT5682_GP2_PIN_SFT 12 1150 | #define RT5682_GP2_PIN_GPIO2 (0x0 << 12) 1151 | #define RT5682_GP2_PIN_LRCK2 (0x1 << 12) 1152 | #define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12) 1153 | #define RT5682_GP3_PIN_MASK (0x3 << 10) 1154 | #define RT5682_GP3_PIN_SFT 10 1155 | #define RT5682_GP3_PIN_GPIO3 (0x0 << 10) 1156 | #define RT5682_GP3_PIN_BCLK2 (0x1 << 10) 1157 | #define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10) 1158 | #define RT5682_GP4_PIN_MASK (0x3 << 8) 1159 | #define RT5682_GP4_PIN_SFT 8 1160 | #define RT5682_GP4_PIN_GPIO4 (0x0 << 8) 1161 | #define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8) 1162 | #define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8) 1163 | #define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8) 1164 | #define RT5682_GP5_PIN_MASK (0x3 << 6) 1165 | #define RT5682_GP5_PIN_SFT 6 1166 | #define RT5682_GP5_PIN_GPIO5 (0x0 << 6) 1167 | #define RT5682_GP5_PIN_DACDAT1 (0x1 << 6) 1168 | #define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6) 1169 | #define RT5682_GP6_PIN_MASK (0x1 << 5) 1170 | #define RT5682_GP6_PIN_SFT 5 1171 | #define RT5682_GP6_PIN_GPIO6 (0x0 << 5) 1172 | #define RT5682_GP6_PIN_LRCK1 (0x1 << 5) 1173 | 1174 | /* GPIO Control 2 (0x00c1)*/ 1175 | #define RT5682_GP1_PF_MASK (0x1 << 15) 1176 | #define RT5682_GP1_PF_IN (0x0 << 15) 1177 | #define RT5682_GP1_PF_OUT (0x1 << 15) 1178 | #define RT5682_GP1_OUT_MASK (0x1 << 14) 1179 | #define RT5682_GP1_OUT_L (0x0 << 14) 1180 | #define RT5682_GP1_OUT_H (0x1 << 14) 1181 | #define RT5682_GP2_PF_MASK (0x1 << 13) 1182 | #define RT5682_GP2_PF_IN (0x0 << 13) 1183 | #define RT5682_GP2_PF_OUT (0x1 << 13) 1184 | #define RT5682_GP2_OUT_MASK (0x1 << 12) 1185 | #define RT5682_GP2_OUT_L (0x0 << 12) 1186 | #define RT5682_GP2_OUT_H (0x1 << 12) 1187 | #define RT5682_GP3_PF_MASK (0x1 << 11) 1188 | #define RT5682_GP3_PF_IN (0x0 << 11) 1189 | #define RT5682_GP3_PF_OUT (0x1 << 11) 1190 | #define RT5682_GP3_OUT_MASK (0x1 << 10) 1191 | #define RT5682_GP3_OUT_L (0x0 << 10) 1192 | #define RT5682_GP3_OUT_H (0x1 << 10) 1193 | #define RT5682_GP4_PF_MASK (0x1 << 9) 1194 | #define RT5682_GP4_PF_IN (0x0 << 9) 1195 | #define RT5682_GP4_PF_OUT (0x1 << 9) 1196 | #define RT5682_GP4_OUT_MASK (0x1 << 8) 1197 | #define RT5682_GP4_OUT_L (0x0 << 8) 1198 | #define RT5682_GP4_OUT_H (0x1 << 8) 1199 | #define RT5682_GP5_PF_MASK (0x1 << 7) 1200 | #define RT5682_GP5_PF_IN (0x0 << 7) 1201 | #define RT5682_GP5_PF_OUT (0x1 << 7) 1202 | #define RT5682_GP5_OUT_MASK (0x1 << 6) 1203 | #define RT5682_GP5_OUT_L (0x0 << 6) 1204 | #define RT5682_GP5_OUT_H (0x1 << 6) 1205 | #define RT5682_GP6_PF_MASK (0x1 << 5) 1206 | #define RT5682_GP6_PF_IN (0x0 << 5) 1207 | #define RT5682_GP6_PF_OUT (0x1 << 5) 1208 | #define RT5682_GP6_OUT_MASK (0x1 << 4) 1209 | #define RT5682_GP6_OUT_L (0x0 << 4) 1210 | #define RT5682_GP6_OUT_H (0x1 << 4) 1211 | 1212 | 1213 | /* GPIO Status (0x00c2) */ 1214 | #define RT5682_GP6_STA (0x1 << 6) 1215 | #define RT5682_GP5_STA (0x1 << 5) 1216 | #define RT5682_GP4_STA (0x1 << 4) 1217 | #define RT5682_GP3_STA (0x1 << 3) 1218 | #define RT5682_GP2_STA (0x1 << 2) 1219 | #define RT5682_GP1_STA (0x1 << 1) 1220 | 1221 | /* Soft volume and zero cross control 1 (0x00d9) */ 1222 | #define RT5682_SV_MASK (0x1 << 15) 1223 | #define RT5682_SV_SFT 15 1224 | #define RT5682_SV_DIS (0x0 << 15) 1225 | #define RT5682_SV_EN (0x1 << 15) 1226 | #define RT5682_ZCD_MASK (0x1 << 10) 1227 | #define RT5682_ZCD_SFT 10 1228 | #define RT5682_ZCD_PD (0x0 << 10) 1229 | #define RT5682_ZCD_PU (0x1 << 10) 1230 | #define RT5682_SV_DLY_MASK (0xf) 1231 | #define RT5682_SV_DLY_SFT 0 1232 | 1233 | /* Soft volume and zero cross control 2 (0x00da) */ 1234 | #define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7) 1235 | #define RT5682_ZCD_BST1_CBJ_SFT 7 1236 | #define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7) 1237 | #define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7) 1238 | #define RT5682_ZCD_RECMIX_MASK (0x1) 1239 | #define RT5682_ZCD_RECMIX_SFT 0 1240 | #define RT5682_ZCD_RECMIX_DIS (0x0) 1241 | #define RT5682_ZCD_RECMIX_EN (0x1) 1242 | 1243 | /* 4 Button Inline Command Control 2 (0x00e3) */ 1244 | #define RT5682_4BTN_IL_MASK (0x1 << 15) 1245 | #define RT5682_4BTN_IL_EN (0x1 << 15) 1246 | #define RT5682_4BTN_IL_DIS (0x0 << 15) 1247 | #define RT5682_4BTN_IL_RST_MASK (0x1 << 14) 1248 | #define RT5682_4BTN_IL_NOR (0x1 << 14) 1249 | #define RT5682_4BTN_IL_RST (0x0 << 14) 1250 | 1251 | /* Analog JD Control (0x00f0) */ 1252 | #define RT5682_JDH_RS_MASK (0x1 << 4) 1253 | #define RT5682_JDH_NO_PLUG (0x1 << 4) 1254 | #define RT5682_JDH_PLUG (0x0 << 4) 1255 | 1256 | /* Bias current control 8 (0x0111) */ 1257 | #define RT5682_HPA_CP_BIAS_CTRL_MASK (0x3 << 2) 1258 | #define RT5682_HPA_CP_BIAS_2UA (0x0 << 2) 1259 | #define RT5682_HPA_CP_BIAS_3UA (0x1 << 2) 1260 | #define RT5682_HPA_CP_BIAS_4UA (0x2 << 2) 1261 | #define RT5682_HPA_CP_BIAS_6UA (0x3 << 2) 1262 | 1263 | /* Charge Pump Internal Register1 (0x0125) */ 1264 | #define RT5682_CP_SW_SIZE_MASK (0x7 << 8) 1265 | #define RT5682_CP_SW_SIZE_L (0x4 << 8) 1266 | #define RT5682_CP_SW_SIZE_M (0x2 << 8) 1267 | #define RT5682_CP_SW_SIZE_S (0x1 << 8) 1268 | #define RT5682_CP_CLK_HP_MASK (0x3 << 4) 1269 | #define RT5682_CP_CLK_HP_100KHZ (0x0 << 4) 1270 | #define RT5682_CP_CLK_HP_200KHZ (0x1 << 4) 1271 | #define RT5682_CP_CLK_HP_300KHZ (0x2 << 4) 1272 | #define RT5682_CP_CLK_HP_600KHZ (0x3 << 4) 1273 | 1274 | /* Pad Driving Control (0x0136) */ 1275 | #define RT5682_PAD_DRV_GP1_MASK (0x3 << 14) 1276 | #define RT5682_PAD_DRV_GP1_SFT 14 1277 | #define RT5682_PAD_DRV_GP2_MASK (0x3 << 12) 1278 | #define RT5682_PAD_DRV_GP2_SFT 12 1279 | #define RT5682_PAD_DRV_GP3_MASK (0x3 << 10) 1280 | #define RT5682_PAD_DRV_GP3_SFT 10 1281 | #define RT5682_PAD_DRV_GP4_MASK (0x3 << 8) 1282 | #define RT5682_PAD_DRV_GP4_SFT 8 1283 | #define RT5682_PAD_DRV_GP5_MASK (0x3 << 6) 1284 | #define RT5682_PAD_DRV_GP5_SFT 6 1285 | #define RT5682_PAD_DRV_GP6_MASK (0x3 << 4) 1286 | #define RT5682_PAD_DRV_GP6_SFT 4 1287 | 1288 | /* Chopper and Clock control for DAC (0x013a)*/ 1289 | #define RT5682_CKXEN_DAC1_MASK (0x1 << 13) 1290 | #define RT5682_CKXEN_DAC1_SFT 13 1291 | #define RT5682_CKGEN_DAC1_MASK (0x1 << 12) 1292 | #define RT5682_CKGEN_DAC1_SFT 12 1293 | 1294 | /* Chopper and Clock control for ADC (0x013b)*/ 1295 | #define RT5682_CKXEN_ADC1_MASK (0x1 << 13) 1296 | #define RT5682_CKXEN_ADC1_SFT 13 1297 | #define RT5682_CKGEN_ADC1_MASK (0x1 << 12) 1298 | #define RT5682_CKGEN_ADC1_SFT 12 1299 | 1300 | /* Volume test (0x013f)*/ 1301 | #define RT5682_SEL_CLK_VOL_MASK (0x1 << 15) 1302 | #define RT5682_SEL_CLK_VOL_EN (0x1 << 15) 1303 | #define RT5682_SEL_CLK_VOL_DIS (0x0 << 15) 1304 | 1305 | /* Test Mode Control 1 (0x0145) */ 1306 | #define RT5682_AD2DA_LB_MASK (0x1 << 10) 1307 | #define RT5682_AD2DA_LB_SFT 10 1308 | 1309 | /* Stereo Noise Gate Control 1 (0x0160) */ 1310 | #define RT5682_NG2_EN_MASK (0x1 << 15) 1311 | #define RT5682_NG2_EN (0x1 << 15) 1312 | #define RT5682_NG2_DIS (0x0 << 15) 1313 | 1314 | /* Stereo1 DAC Silence Detection Control (0x0190) */ 1315 | #define RT5682_DEB_STO_DAC_MASK (0x7 << 4) 1316 | #define RT5682_DEB_80_MS (0x0 << 4) 1317 | 1318 | /* HP Behavior Logic Control 2 (0x01db) */ 1319 | #define RT5682_HP_LC2_SIG_SOUR2_MASK (0x1 << 4) 1320 | #define RT5682_HP_LC2_SIG_SOUR2_REG (0x1 << 4) 1321 | #define RT5682_HP_LC2_SIG_SOUR2_DC_CAL (0x0 << 4) 1322 | #define RT5682_HP_LC2_SIG_SOUR1_MASK (0x7) 1323 | #define RT5682_HP_LC2_SIG_SOUR1_1BIT (0x7) 1324 | #define RT5682_HP_LC2_SIG_SOUR1_LEGA (0x2) 1325 | 1326 | /* SAR ADC Inline Command Control 1 (0x0210) */ 1327 | #define RT5682_SAR_BUTT_DET_MASK (0x1 << 15) 1328 | #define RT5682_SAR_BUTT_DET_EN (0x1 << 15) 1329 | #define RT5682_SAR_BUTT_DET_DIS (0x0 << 15) 1330 | #define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14) 1331 | #define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14) 1332 | #define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14) 1333 | #define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13) 1334 | #define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13) 1335 | #define RT5682_SAR_BUTDET_RST (0x0 << 13) 1336 | #define RT5682_SAR_POW_MASK (0x1 << 12) 1337 | #define RT5682_SAR_POW_EN (0x1 << 12) 1338 | #define RT5682_SAR_POW_DIS (0x0 << 12) 1339 | #define RT5682_SAR_RST_MASK (0x1 << 11) 1340 | #define RT5682_SAR_RST_NORMAL (0x1 << 11) 1341 | #define RT5682_SAR_RST (0x0 << 11) 1342 | #define RT5682_SAR_BYPASS_MASK (0x1 << 10) 1343 | #define RT5682_SAR_BYPASS_EN (0x1 << 10) 1344 | #define RT5682_SAR_BYPASS_DIS (0x0 << 10) 1345 | #define RT5682_SAR_SEL_MB1_MASK (0x1 << 9) 1346 | #define RT5682_SAR_SEL_MB1_SEL (0x1 << 9) 1347 | #define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9) 1348 | #define RT5682_SAR_SEL_MB2_MASK (0x1 << 8) 1349 | #define RT5682_SAR_SEL_MB2_SEL (0x1 << 8) 1350 | #define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8) 1351 | #define RT5682_SAR_SEL_MODE_MASK (0x1 << 7) 1352 | #define RT5682_SAR_SEL_MODE_CMP (0x1 << 7) 1353 | #define RT5682_SAR_SEL_MODE_ADC (0x0 << 7) 1354 | #define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5) 1355 | #define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) 1356 | #define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5) 1357 | #define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4) 1358 | #define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4) 1359 | #define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4) 1360 | 1361 | /* SAR ADC Inline Command Control 13 (0x021c) */ 1362 | #define RT5682_SAR_SOUR_MASK (0x3f) 1363 | #define RT5682_SAR_SOUR_BTN (0x3f) 1364 | #define RT5682_SAR_SOUR_TYPE (0x0) 1365 | 1366 | /* soundwire timeout */ 1367 | #define RT5682_PROBE_TIMEOUT 5000 1368 | 1369 | 1370 | #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1371 | #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1372 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1373 | 1374 | /* System Clock Source */ 1375 | enum { 1376 | RT5682_SCLK_S_MCLK, 1377 | RT5682_SCLK_S_PLL1, 1378 | RT5682_SCLK_S_PLL2, 1379 | RT5682_SCLK_S_RCCLK, 1380 | }; 1381 | 1382 | /* PLL Source */ 1383 | enum { 1384 | RT5682_PLL1_S_MCLK, 1385 | RT5682_PLL1_S_BCLK1, 1386 | RT5682_PLL1_S_RCCLK, 1387 | RT5682_PLL2_S_MCLK, 1388 | }; 1389 | 1390 | enum { 1391 | RT5682_PLL1, 1392 | RT5682_PLL2, 1393 | RT5682_PLLS, 1394 | }; 1395 | 1396 | enum { 1397 | RT5682_AIF1, 1398 | RT5682_AIF2, 1399 | RT5682_SDW, 1400 | RT5682_AIFS 1401 | }; 1402 | 1403 | /* filter mask */ 1404 | enum { 1405 | RT5682_DA_STEREO1_FILTER = 0x1, 1406 | RT5682_AD_STEREO1_FILTER = (0x1 << 1), 1407 | }; 1408 | 1409 | enum { 1410 | RT5682_CLK_SEL_SYS, 1411 | RT5682_CLK_SEL_I2S1_ASRC, 1412 | RT5682_CLK_SEL_I2S2_ASRC, 1413 | }; 1414 | 1415 | #define RT5682_REG_NUM 318 1416 | 1417 | #endif -------------------------------------------------------------------------------- /rt5682/rt5682.c: -------------------------------------------------------------------------------- 1 | #define DESCRIPTOR_DEF 2 | #include "rt5682.h" 3 | #include "registers.h" 4 | 5 | #define bool int 6 | #define MHz 1000000 7 | 8 | static ULONG Rt5682DebugLevel = 100; 9 | static ULONG Rt5682DebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 10 | 11 | NTSTATUS rt5682_set_component_pll(PRTEK_CONTEXT pDevice, 12 | int pll_id, int source, unsigned int freq_in, 13 | unsigned int freq_out); 14 | NTSTATUS rt5682_set_tdm_slot(PRTEK_CONTEXT pDevice, unsigned int tx_mask, 15 | unsigned int rx_mask, int slots, int slot_width); 16 | NTSTATUS rt5682_set_component_sysclk(PRTEK_CONTEXT pDevice, 17 | int clk_id); 18 | void rt5682_update_reclock(IN PRTEK_CONTEXT pDevice); 19 | 20 | NTSTATUS 21 | DriverEntry( 22 | __in PDRIVER_OBJECT DriverObject, 23 | __in PUNICODE_STRING RegistryPath 24 | ) 25 | { 26 | NTSTATUS status = STATUS_SUCCESS; 27 | WDF_DRIVER_CONFIG config; 28 | WDF_OBJECT_ATTRIBUTES attributes; 29 | 30 | RtekPrint(DEBUG_LEVEL_INFO, DBG_INIT, 31 | "Driver Entry\n"); 32 | 33 | WDF_DRIVER_CONFIG_INIT(&config, Rt5682EvtDeviceAdd); 34 | 35 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 36 | 37 | // 38 | // Create a framework driver object to represent our driver. 39 | // 40 | 41 | status = WdfDriverCreate(DriverObject, 42 | RegistryPath, 43 | &attributes, 44 | &config, 45 | WDF_NO_HANDLE 46 | ); 47 | 48 | if (!NT_SUCCESS(status)) 49 | { 50 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_INIT, 51 | "WdfDriverCreate failed with status 0x%x\n", status); 52 | } 53 | 54 | return status; 55 | } 56 | 57 | 58 | static NTSTATUS rt5682_reg_write(PRTEK_CONTEXT pDevice, uint16_t reg, uint16_t data) 59 | { 60 | uint16_t rawdata[2]; 61 | rawdata[0] = RtlUshortByteSwap(reg); 62 | rawdata[1] = RtlUshortByteSwap(data); 63 | return SpbWriteDataSynchronously(&pDevice->I2CContext, rawdata, sizeof(rawdata)); 64 | } 65 | 66 | static NTSTATUS rt5682_reg_read(PRTEK_CONTEXT pDevice, uint16_t reg, uint16_t* data) 67 | { 68 | uint16_t reg_swap = RtlUshortByteSwap(reg); 69 | uint16_t data_swap = 0; 70 | NTSTATUS ret = SpbXferDataSynchronously(&pDevice->I2CContext, ®_swap, sizeof(uint16_t), &data_swap, sizeof(uint16_t)); 71 | *data = RtlUshortByteSwap(data_swap); 72 | return ret; 73 | } 74 | 75 | static NTSTATUS rt5682_reg_update( 76 | _In_ PRTEK_CONTEXT pDevice, 77 | uint16_t reg, 78 | uint16_t mask, 79 | uint16_t val 80 | ) { 81 | uint16_t tmp = 0, orig = 0; 82 | 83 | NTSTATUS status = rt5682_reg_read(pDevice, reg, &orig); 84 | if (!NT_SUCCESS(status)) { 85 | return status; 86 | } 87 | 88 | tmp = orig & ~mask; 89 | tmp |= val & mask; 90 | 91 | if (tmp != orig) { 92 | status = rt5682_reg_write(pDevice, reg, tmp); 93 | } 94 | return status; 95 | } 96 | 97 | /* 98 | static NTSTATUS rt5682_reg_burstWrite(PRTEK_CONTEXT pDevice, struct reg* regs, int regCount) { 99 | if (regCount > 4) { 100 | DbgPrint("Count > 4; Splitting!\n"); 101 | NTSTATUS status = rt5682_reg_burstWrite(pDevice, regs, 4); 102 | if (!NT_SUCCESS(status)) { 103 | return status; 104 | } 105 | DbgPrint("Done first batch. Doing 2nd\n"); 106 | status = rt5682_reg_burstWrite(pDevice, ®s[4], regCount - 4); 107 | return status; 108 | } 109 | 110 | NTSTATUS status = STATUS_NO_MEMORY; 111 | 112 | SPB_BURST_INFO* burstInfo = ExAllocatePoolWithTag(NonPagedPool, sizeof(SPB_BURST_INFO) * regCount, RT5682_POOL_TAG); 113 | if (!burstInfo) { 114 | status = STATUS_NO_MEMORY; 115 | goto exit; 116 | } 117 | RtlZeroMemory(burstInfo, sizeof(SPB_BURST_INFO) * regCount); 118 | 119 | for (int i = 0; i < regCount; i++) { 120 | struct reg* regToSet = ®s[i]; 121 | 122 | UINT16* rawdata = ExAllocatePoolWithTag(NonPagedPool, sizeof(UINT16) * 2, RT5682_POOL_TAG); 123 | if (!rawdata) { 124 | status = STATUS_NO_MEMORY; 125 | goto exit; 126 | } 127 | 128 | rawdata[0] = RtlUshortByteSwap(regToSet->reg); 129 | rawdata[1] = RtlUshortByteSwap(regToSet->val); 130 | 131 | SPB_BURST_INFO* info = &burstInfo[i]; 132 | info->Data = rawdata; 133 | info->Length = sizeof(UINT16) * 2; 134 | } 135 | status = SpbBurstWriteDataSynchronously(&pDevice->I2CContext, burstInfo, regCount); 136 | 137 | exit: 138 | if (burstInfo) { 139 | for (int i = 0; i < regCount; i++) { 140 | if (burstInfo[i].Data) 141 | ExFreePoolWithTag(burstInfo[i].Data, RT5682_POOL_TAG); 142 | } 143 | ExFreePoolWithTag(burstInfo, RT5682_POOL_TAG); 144 | } 145 | return status; 146 | } 147 | */ 148 | 149 | static NTSTATUS rt5682_reg_burstWrite(PRTEK_CONTEXT pDevice, struct reg* regs, int regCount) { 150 | NTSTATUS status = STATUS_NO_MEMORY; 151 | for (int i = 0; i < regCount; i++) { 152 | struct reg* regToSet = ®s[i]; 153 | status = rt5682_reg_write(pDevice, regToSet->reg, regToSet->val); 154 | if (!NT_SUCCESS(status)) { 155 | return status; 156 | } 157 | } 158 | return status; 159 | } 160 | 161 | static Platform GetPlatform() { 162 | int cpuinfo[4]; 163 | __cpuidex(cpuinfo, 0, 0); 164 | 165 | int temp = cpuinfo[2]; 166 | cpuinfo[2] = cpuinfo[3]; 167 | cpuinfo[3] = temp; 168 | 169 | char vendorName[13]; 170 | RtlZeroMemory(vendorName, 13); 171 | memcpy(vendorName, &cpuinfo[1], 12); 172 | 173 | __cpuidex(cpuinfo, 1, 0); 174 | 175 | UINT16 family = (cpuinfo[0] >> 8) & 0xF; 176 | UINT8 model = (cpuinfo[0] >> 4) & 0xF; 177 | UINT8 stepping = cpuinfo[0] & 0xF; 178 | if (family == 0xF || family == 0x6) { 179 | model += (((cpuinfo[0] >> 16) & 0xF) << 4); 180 | } 181 | if (family == 0xF) { 182 | family += (cpuinfo[0] >> 20) & 0xFF; 183 | } 184 | 185 | if (strcmp(vendorName, "AuthenticAMD") == 0) { 186 | return PlatformRyzen; //family 23 for Picasso / Dali 187 | } else if (strcmp(vendorName, "GenuineIntel") == 0) { 188 | if (model == 122 || model == 92) //92 = Apollo Lake but keep for compatibility 189 | return PlatformGeminiLake; 190 | else if (model == 156) //Jasper Lake, but use same settings as CML 191 | return PlatformCometLake; 192 | else if (model == 142) 193 | return PlatformCometLake; 194 | else 195 | return PlatformTigerLake; //should be 140 196 | } 197 | return PlatformNone; 198 | } 199 | 200 | NTSTATUS BOOTCODEC( 201 | _In_ PRTEK_CONTEXT devContext 202 | ) 203 | { 204 | NTSTATUS status = rt5682_reg_write(devContext, RT5682_RESET, 0); 205 | if (!NT_SUCCESS(status)) { 206 | return status; 207 | } 208 | 209 | status = rt5682_reg_write(devContext, RT5682_I2C_MODE, 1); 210 | if (!NT_SUCCESS(status)) { 211 | return status; 212 | } 213 | 214 | LARGE_INTEGER WaitInterval; 215 | WaitInterval.QuadPart = -10 * 1000 * 15; 216 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 217 | 218 | UINT16 val; 219 | status = rt5682_reg_read(devContext, RT5682_DEVICE_ID, &val); 220 | if (!NT_SUCCESS(status)) { 221 | return status; 222 | } 223 | 224 | if (val != DEVICE_ID) { 225 | DbgPrint("Device with ID 0x%x is not ALC5682\n", val); 226 | return STATUS_NO_SUCH_DEVICE; 227 | } 228 | 229 | { //Calibrate 230 | struct reg initAnlg[] = { 231 | {RT5682_I2C_CTRL, 0x000f}, 232 | {RT5682_PWR_ANLG_1, 0xa2af} 233 | }; 234 | status = rt5682_reg_burstWrite(devContext, initAnlg, sizeof(initAnlg) / sizeof(struct reg)); 235 | if (!NT_SUCCESS(status)) { 236 | return status; 237 | } 238 | 239 | WaitInterval.QuadPart = -10 * 1000 * 15; 240 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 241 | 242 | struct reg preCalib[] = { 243 | {RT5682_PWR_ANLG_1, 0xf2af}, 244 | {RT5682_MICBIAS_2, 0x0300 }, 245 | {RT5682_GLB_CLK, 0x8000}, 246 | {RT5682_PWR_DIG_1, 0x0100}, 247 | {RT5682_HP_IMP_SENS_CTRL_19, 0x3800}, 248 | {RT5682_CHOP_DAC, 0x3000}, 249 | {RT5682_CALIB_ADC_CTRL, 0x7005}, 250 | {RT5682_STO1_ADC_MIXER, 0x686c}, 251 | {RT5682_CAL_REC, 0x0d0d}, 252 | {RT5682_HP_CALIB_CTRL_2, 0x0321}, 253 | {RT5682_HP_LOGIC_CTRL_2, 0x0004}, 254 | {RT5682_HP_CALIB_CTRL_1, 0x7c00}, 255 | {RT5682_HP_CALIB_CTRL_3, 0x06a1}, 256 | {RT5682_A_DAC1_MUX, 0x0311}, 257 | {RT5682_HP_CALIB_CTRL_1, 0x7c00}, 258 | {RT5682_HP_CALIB_CTRL_1, 0xfc00} 259 | }; 260 | status = rt5682_reg_burstWrite(devContext, preCalib, sizeof(preCalib) / sizeof(struct reg)); 261 | if (!NT_SUCCESS(status)) { 262 | return status; 263 | } 264 | 265 | int count; 266 | for (count = 0; count < 60; count++) { 267 | UINT16 value; 268 | rt5682_reg_read(devContext, RT5682_HP_CALIB_STA_1, &value); 269 | if (!(value & 0x8000)) 270 | break; 271 | 272 | WaitInterval.QuadPart = -10 * 1000 * 10; 273 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 274 | } 275 | 276 | if (count >= 60) { 277 | DbgPrint("HP Calibration Failure\n"); 278 | } 279 | } 280 | 281 | struct reg restoreSettingsAndPatch[] = { 282 | {RT5682_PWR_ANLG_1, 0x002f}, 283 | {RT5682_MICBIAS_2, 0x0080 }, 284 | {RT5682_GLB_CLK, 0x0000}, 285 | {RT5682_PWR_DIG_1, 0x0000}, 286 | {RT5682_CHOP_DAC, 0x2000}, 287 | {RT5682_CALIB_ADC_CTRL, 0x2005}, 288 | {RT5682_STO1_ADC_MIXER, 0xc064}, 289 | {RT5682_CAL_REC, 0x0c0c}, 290 | 291 | //Patch 292 | {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 293 | {RT5682_DAC_ADC_DIG_VOL1, 0xa0a0}, //0xa020 for internal mic 294 | {RT5682_I2C_CTRL, 0x000f}, 295 | {RT5682_PLL2_INTERNAL, 0x8266}, 296 | {RT5682_SAR_IL_CMD_1, 0x22b7}, 297 | {RT5682_SAR_IL_CMD_3, 0x0365}, 298 | {RT5682_SAR_IL_CMD_6, 0x0110}, 299 | {RT5682_CHARGE_PUMP_1, 0x0210}, 300 | {RT5682_HP_LOGIC_CTRL_2, 0x0007}, 301 | {RT5682_SAR_IL_CMD_2, 0xac01}, //0xac00 for internal mic 302 | {RT5682_CBJ_CTRL_7, 0x0104} 303 | }; 304 | status = rt5682_reg_burstWrite(devContext, restoreSettingsAndPatch, sizeof(restoreSettingsAndPatch) / sizeof(struct reg)); 305 | if (!NT_SUCCESS(status)) { 306 | return status; 307 | } 308 | 309 | struct reg finishInit1[] = { 310 | //{RT5682_DEPOP_1, 0x0000}, 311 | //{RT5682_DMIC_CTRL_1, 0xa00}, 312 | //{RT5682_GPIO_CTRL_1, 0x2160}, 313 | {RT5682_TEST_MODE_CTRL_1, 0x0000}, 314 | {RT5682_BIAS_CUR_CTRL_8, 0x4a6}, 315 | //{RT5682_CHARGE_PUMP_1, 0x220}, 316 | {RT5682_HP_CHARGE_PUMP_1, 0xe26}, 317 | {RT5682_DMIC_CTRL_1, 0x1a00} 318 | }; 319 | 320 | struct reg setClocksRyzen[] = { 321 | //set DAI format 322 | //{RT5682_TDM_TCON_CTRL, 0x1a00}, 323 | 324 | //Set component PLL Ryzen 325 | {RT5682_PLL2_CTRL_1, 0x1730}, 326 | {RT5682_PLL2_CTRL_2, 0x1e}, 327 | {RT5682_PLL2_CTRL_3, 0x200}, 328 | {RT5682_PLL2_CTRL_4, 0x180f}, 329 | 330 | //set component sysclk Ryzen 331 | {RT5682_GLB_CLK, 0x4000}, 332 | 333 | //set bclk1 ratio Ryzen 334 | {RT5682_TDM_TCON_CTRL, 0x201}, 335 | 336 | //set wclk prepare 337 | {RT5682_PWR_ANLG_3, 0x34}, //0x30 for internal mic [Ryzen], 338 | 339 | //set clk 340 | {RT5682_ADDA_CLK_1, 0x1121} //[Ryzen] 341 | }; 342 | 343 | struct reg setClocksGeminiLake[] = { 344 | //Set component PLL GLK 345 | {RT5682_PLL_CTRL_1, 0x0f03}, 346 | {RT5682_PLL_CTRL_2, 0x3003}, 347 | 348 | //set component sysclk GLK 349 | {RT5682_GLB_CLK, 0x2000}, 350 | 351 | //set bclk1 ratio GLK 352 | {RT5682_TDM_TCON_CTRL, 0x0020}, 353 | 354 | //set wclk prepare 355 | {RT5682_PWR_ANLG_3, 0x44}, //0x40 for internal mic [Gemini Lake] 356 | 357 | {RT5682_ADDA_CLK_1, 0x1001}, //[Gemini Lake] 358 | }; 359 | 360 | struct reg setClocksCometLake[] = { 361 | //Set component PLL CML 362 | {RT5682_PLL_CTRL_1, 0x1481}, 363 | {RT5682_PLL_CTRL_2, 0xc003}, 364 | 365 | //set component sysclk GLK 366 | {RT5682_GLB_CLK, 0x2000}, 367 | 368 | //set bclk1 ratio CML 369 | {RT5682_TDM_TCON_CTRL, 0x0020}, 370 | 371 | //set wclk prepare 372 | {RT5682_PWR_ANLG_3, 0x40}, 373 | 374 | {RT5682_ADDA_CLK_1, 0x1001}, //[Gemini Lake] 375 | }; 376 | 377 | struct reg setClocksTigerLake[] = { 378 | //set bclk1 ratio TGL 379 | //{RT5682_TDM_TCON_CTRL, 0x0030}, //Reclocker should set this 380 | 381 | {RT5682_ADDA_CLK_1, 0x1001}, //[Gemini Lake] 382 | }; 383 | 384 | struct reg finishInit2[] = { 385 | //set wclk prepare 386 | //{RT5682_PWR_ANLG_1, 0x722f}, 387 | //{RT5682_PWR_DIG_1, 0x8000}, 388 | 389 | //set clk 390 | {RT5682_PLL_TRACK_2, 0x0100}, 391 | 392 | //set bias level 393 | //{RT5682_PWR_DIG_1, 0x8001}, 394 | 395 | //Update more defaults 396 | //{RT5682_HP_CTRL_2, 0x0000}, 397 | {RT5682_DAC1_DIG_VOL, 0x9f9f}, 398 | {RT5682_STO1_ADC_DIG_VOL, 0x2f2f}, //0xaf2f for internal mic 399 | {RT5682_REC_MIXER, 0x0000}, 400 | //{RT5682_PWR_ANLG_1, 0xc000}, 401 | {RT5682_I2S2_SDP, 0xc000}, 402 | {RT5682_TDM_ADDA_CTRL_1, 0x8000}, 403 | {RT5682_PLL_TRACK_3, 0x0100}, 404 | {RT5682_GPIO_CTRL_1, 0x1160}, 405 | 406 | //Headphone defaults 407 | {RT5682_HP_CTRL_2, 0x6000}, 408 | {RT5682_STO1_ADC_MIXER, 0x6064}, 409 | {RT5682_PWR_DIG_1, 0x8d11}, 410 | {RT5682_PWR_DIG_2, 0x8400}, 411 | {RT5682_PWR_ANLG_1, 0xf2af}, 412 | {RT5682_CLK_DET, 0x8001}, 413 | {RT5682_DEPOP_1, 0x69}, 414 | {RT5682_CHARGE_PUMP_1, 0x420}, 415 | {RT5682_CHOP_DAC, 0x3000}, 416 | {RT5682_CHOP_ADC, 0x3000} //not present for internal mic 417 | }; 418 | 419 | struct reg setDefaultsRyzen[] = { 420 | //For Ryzen 421 | {RT5682_CBJ_BST_CTRL, 0x0200}, 422 | {RT5682_I2S1_SDP, 0x0000}, 423 | {RT5682_HP_LOGIC_CTRL_2, 0x17} 424 | }; 425 | 426 | struct reg setDefaultsGeminiLake[] = { 427 | //For Gemini Lake 428 | {RT5682_HP_CTRL_1, 0x0000}, 429 | {RT5682_CBJ_BST_CTRL, 0x0300}, 430 | {RT5682_DAC1_DIG_VOL, 0xa3a3}, 431 | {RT5682_STO1_DAC_MIXER, 0x2080}, //was 0xa0a0 432 | {RT5682_PWR_ANLG_2, 0xe}, //was 0a0a 433 | {RT5682_I2S1_SDP, 0x2200}, 434 | {RT5682_TDM_ADDA_CTRL_2, 0x0080}, 435 | {RT5682_HP_LOGIC_CTRL_2, 0x12} 436 | }; 437 | 438 | struct reg setDefaultsCometLake[] = { 439 | //For Comet Lake 440 | {RT5682_HP_CTRL_1, 0x8080}, 441 | {RT5682_CBJ_BST_CTRL, 0x0300}, 442 | {RT5682_DAC1_DIG_VOL, 0xafaf}, 443 | {RT5682_STO1_DAC_MIXER, 0x2080}, 444 | {RT5682_I2S1_SDP, 0x2220}, 445 | {RT5682_TDM_ADDA_CTRL_2, 0x0080}, 446 | {RT5682_HP_LOGIC_CTRL_2, 0x17}, 447 | 448 | //PLL tracks are different here 449 | {RT5682_PLL_TRACK_1, 0x3104}, 450 | {RT5682_PLL_TRACK_2, 0x1100}, 451 | {RT5682_PLL_TRACK_3, 0x1100} 452 | }; 453 | 454 | struct reg setDefaultsTigerLake[] = { 455 | //For Tiger Lake 456 | {RT5682_HP_CTRL_1, 0x8080}, 457 | {RT5682_CBJ_BST_CTRL, 0x0300}, 458 | {RT5682_DAC1_DIG_VOL, 0xafaf}, 459 | {RT5682_STO1_DAC_MIXER, 0x2080}, //was 0xa0a0 460 | {RT5682_I2S1_SDP, 0x0000}, 461 | //{RT5682_I2S1_SDP, 0x3330}, //Reclocker should set this 462 | {RT5682_TDM_ADDA_CTRL_2, 0x0080}, 463 | {RT5682_HP_LOGIC_CTRL_2, 0x17} 464 | }; 465 | 466 | Platform currentPlatform = GetPlatform(); 467 | 468 | status = rt5682_reg_burstWrite(devContext, finishInit1, sizeof(finishInit1) / sizeof(struct reg)); 469 | if (!NT_SUCCESS(status)) { 470 | return status; 471 | } 472 | 473 | switch (currentPlatform) { 474 | case PlatformRyzen: 475 | status = rt5682_reg_burstWrite(devContext, setClocksRyzen, sizeof(setClocksRyzen) / sizeof(struct reg)); 476 | break; 477 | case PlatformGeminiLake: 478 | status = rt5682_reg_burstWrite(devContext, setClocksGeminiLake, sizeof(setClocksGeminiLake) / sizeof(struct reg)); 479 | break; 480 | case PlatformCometLake: 481 | status = rt5682_reg_burstWrite(devContext, setClocksCometLake, sizeof(setClocksCometLake) / sizeof(struct reg)); 482 | break; 483 | case PlatformTigerLake: 484 | status = rt5682_reg_burstWrite(devContext, setClocksTigerLake, sizeof(setClocksTigerLake) / sizeof(struct reg)); 485 | break; 486 | } 487 | 488 | if (!NT_SUCCESS(status)) { 489 | return status; 490 | } 491 | 492 | status = rt5682_reg_burstWrite(devContext, finishInit2, sizeof(finishInit2) / sizeof(struct reg)); 493 | if (!NT_SUCCESS(status)) { 494 | return status; 495 | } 496 | 497 | switch (currentPlatform) { 498 | case PlatformRyzen: 499 | status = rt5682_reg_burstWrite(devContext, setDefaultsRyzen, sizeof(setDefaultsRyzen) / sizeof(struct reg)); 500 | break; 501 | case PlatformGeminiLake: 502 | status = rt5682_reg_burstWrite(devContext, setDefaultsGeminiLake, sizeof(setDefaultsGeminiLake) / sizeof(struct reg)); 503 | break; 504 | case PlatformCometLake: 505 | status = rt5682_reg_burstWrite(devContext, setDefaultsCometLake, sizeof(setDefaultsCometLake) / sizeof(struct reg)); 506 | break; 507 | case PlatformTigerLake: 508 | status = rt5682_reg_burstWrite(devContext, setDefaultsTigerLake, sizeof(setDefaultsTigerLake) / sizeof(struct reg)); 509 | break; 510 | } 511 | if (!NT_SUCCESS(status)) { 512 | return status; 513 | } 514 | 515 | rt5682_update_reclock(devContext); 516 | 517 | struct reg prepJackDetect[] = { 518 | {RT5682_CBJ_CTRL_5, 0xa60a}, 519 | {RT5682_CBJ_CTRL_2, 0x40}, 520 | {RT5682_CBJ_CTRL_1, 0xd142}, 521 | {RT5682_CBJ_CTRL_3, 0x1484}, 522 | {RT5682_SAR_IL_CMD_1, 0x32b7}, 523 | {RT5682_GPIO_CTRL_1, 0x6960}, 524 | {RT5682_RC_CLK_CTRL, 0xd000}, 525 | {RT5682_PWR_ANLG_2, 0xa}, 526 | {RT5682_IRQ_CTRL_2, 0x8000}, 527 | {RT5682_4BTN_IL_CMD_4, 0x1010}, 528 | {RT5682_4BTN_IL_CMD_5, 0x1010}, 529 | {RT5682_4BTN_IL_CMD_6, 0x1010}, 530 | {RT5682_4BTN_IL_CMD_7, 0x1010} 531 | }; 532 | status = rt5682_reg_burstWrite(devContext, prepJackDetect, sizeof(prepJackDetect) / sizeof(struct reg)); 533 | if (!NT_SUCCESS(status)) { 534 | return status; 535 | } 536 | return STATUS_SUCCESS; 537 | } 538 | 539 | int CsAudioArg2 = 1; 540 | 541 | VOID 542 | CSAudioRegisterEndpoint( 543 | PRTEK_CONTEXT pDevice 544 | ) { 545 | CsAudioArg arg; 546 | RtlZeroMemory(&arg, sizeof(CsAudioArg)); 547 | arg.argSz = sizeof(CsAudioArg); 548 | arg.endpointType = CSAudioEndpointTypeHeadphone; 549 | arg.endpointRequest = CSAudioEndpointRegister; 550 | ExNotifyCallback(pDevice->CSAudioAPICallback, &arg, &CsAudioArg2); 551 | 552 | arg.endpointType = CSAudioEndpointTypeMicJack; 553 | ExNotifyCallback(pDevice->CSAudioAPICallback, &arg, &CsAudioArg2); //register both in case user decides to record first 554 | } 555 | 556 | void rt5682_update_reclock(IN PRTEK_CONTEXT pDevice) { 557 | UINT32 mclk = pDevice->mclk; 558 | UINT32 freq = pDevice->freq; 559 | UINT32 slotWidth = pDevice->slotWidth; 560 | 561 | if (!pDevice->ReclockRequested) 562 | return; 563 | 564 | UINT32 outclk = freq * 512; 565 | if (mclk != outclk) 566 | rt5682_set_component_pll(pDevice, RT5682_PLL1, RT5682_PLL1_S_MCLK, mclk, outclk); 567 | rt5682_set_tdm_slot(pDevice, 1, 1, 2, slotWidth); 568 | rt5682_set_component_sysclk(pDevice, mclk == outclk ? RT5682_SCLK_S_MCLK : RT5682_SCLK_S_PLL1); 569 | rt5682_reg_update(pDevice, RT5682_PWR_ANLG_3, RT5682_PWR_PLL, mclk != outclk ? RT5682_PWR_PLL : 0); 570 | } 571 | 572 | VOID 573 | CsAudioCallbackFunction( 574 | IN PRTEK_CONTEXT pDevice, 575 | CsAudioArg* arg, 576 | PVOID Argument2 577 | ) { 578 | if (!pDevice) { 579 | return; 580 | } 581 | 582 | if (Argument2 == &CsAudioArg2) { 583 | return; 584 | } 585 | 586 | pDevice->CSAudioManaged = TRUE; 587 | 588 | CsAudioArg localArg; 589 | RtlZeroMemory(&localArg, sizeof(CsAudioArg)); 590 | RtlCopyMemory(&localArg, arg, min(arg->argSz, sizeof(CsAudioArg))); 591 | 592 | if (localArg.endpointType == CSAudioEndpointTypeDSP && localArg.endpointRequest == CSAudioEndpointRegister) { 593 | CSAudioRegisterEndpoint(pDevice); 594 | } 595 | else if (localArg.endpointType != CSAudioEndpointTypeHeadphone && 596 | localArg.endpointType != CSAudioEndpointTypeMicJack) { //check both in case user decides to record first 597 | return; 598 | } 599 | 600 | if (localArg.endpointRequest == CSAudioEndpointI2SParameters && 601 | localArg.i2sParameters.version >= 1) { //Supports version 1 or higher 602 | 603 | Platform currentPlatform = GetPlatform(); 604 | if (currentPlatform == PlatformTigerLake) { //Reclock requested 605 | UINT32 mclk = localArg.i2sParameters.mclk; 606 | UINT32 freq = localArg.i2sParameters.frequency; 607 | UINT32 slotWidth = localArg.i2sParameters.valid_bits; 608 | 609 | pDevice->mclk = mclk; 610 | pDevice->freq = freq; 611 | pDevice->slotWidth = slotWidth; 612 | pDevice->ReclockRequested = TRUE; 613 | 614 | rt5682_update_reclock(pDevice); 615 | } 616 | } 617 | } 618 | 619 | #include "rl6231.h" 620 | NTSTATUS rt5682_set_component_pll(PRTEK_CONTEXT pDevice, 621 | int pll_id, int source, unsigned int freq_in, 622 | unsigned int freq_out) 623 | { 624 | struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 625 | unsigned int pll2_fout1, pll2_ps_val; 626 | int ret; 627 | 628 | if (!freq_in || !freq_out) { 629 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 630 | "PLL disabled\n"); 631 | rt5682_reg_update(pDevice, RT5682_GLB_CLK, 632 | RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 633 | return STATUS_SUCCESS; 634 | } 635 | 636 | if (pll_id == RT5682_PLL2) { 637 | switch (source) { 638 | case RT5682_PLL2_S_MCLK: 639 | rt5682_reg_update(pDevice, 640 | RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 641 | RT5682_PLL2_SRC_MCLK); 642 | break; 643 | default: 644 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 645 | "Unknown PLL2 Source %d\n", 646 | source); 647 | return STATUS_INVALID_PARAMETER; 648 | } 649 | 650 | /** 651 | * PLL2 concatenates 2 PLL units. 652 | * We suggest the Fout of the front PLL is 3.84MHz. 653 | */ 654 | pll2_fout1 = 3840000; 655 | ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 656 | if (ret < 0) { 657 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 658 | "Unsupported input clock %d\n", 659 | freq_in); 660 | return ret; 661 | } 662 | RtekPrint(DEBUG_LEVEL_INFO, DBG_PNP, 663 | "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 664 | freq_in, pll2_fout1, 665 | pll2f_code.m_bp, 666 | (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 667 | pll2f_code.n_code, pll2f_code.k_code); 668 | 669 | ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 670 | if (ret < 0) { 671 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 672 | "Unsupported input clock %d\n", 673 | pll2_fout1); 674 | return ret; 675 | } 676 | RtekPrint(DEBUG_LEVEL_INFO, DBG_PNP, 677 | "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 678 | pll2_fout1, freq_out, 679 | pll2b_code.m_bp, 680 | (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 681 | pll2b_code.n_code, pll2b_code.k_code); 682 | 683 | rt5682_reg_write(pDevice, RT5682_PLL2_CTRL_1, 684 | pll2f_code.k_code << RT5682_PLL2F_K_SFT | 685 | pll2b_code.k_code << RT5682_PLL2B_K_SFT | 686 | pll2b_code.m_code); 687 | rt5682_reg_write(pDevice, RT5682_PLL2_CTRL_2, 688 | pll2f_code.m_code << RT5682_PLL2F_M_SFT | 689 | pll2b_code.n_code); 690 | rt5682_reg_write(pDevice, RT5682_PLL2_CTRL_3, 691 | pll2f_code.n_code << RT5682_PLL2F_N_SFT); 692 | 693 | if (freq_out == 22579200) 694 | pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 695 | else 696 | pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 697 | rt5682_reg_update(pDevice, RT5682_PLL2_CTRL_4, 698 | RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 699 | RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 700 | pll2_ps_val | 701 | (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 702 | (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 703 | 0xf); 704 | } 705 | else { 706 | switch (source) { 707 | case RT5682_PLL1_S_MCLK: 708 | rt5682_reg_update(pDevice, 709 | RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 710 | RT5682_PLL1_SRC_MCLK); 711 | break; 712 | case RT5682_PLL1_S_BCLK1: 713 | rt5682_reg_update(pDevice, 714 | RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 715 | RT5682_PLL1_SRC_BCLK1); 716 | break; 717 | default: 718 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 719 | "Unknown PLL1 Source %d\n", 720 | source); 721 | return STATUS_INVALID_PARAMETER; 722 | } 723 | 724 | ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 725 | if (ret < 0) { 726 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 727 | "Unsupported input clock %d\n", 728 | freq_in); 729 | return ret; 730 | } 731 | 732 | RtekPrint(DEBUG_LEVEL_INFO, DBG_PNP, 733 | "bypass=%d m=%d n=%d k=%d\n", 734 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 735 | pll_code.n_code, pll_code.k_code); 736 | 737 | rt5682_reg_write(pDevice, RT5682_PLL_CTRL_1, 738 | (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code); 739 | rt5682_reg_write(pDevice, RT5682_PLL_CTRL_2, 740 | ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) | 741 | ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST)); 742 | } 743 | 744 | return STATUS_SUCCESS; 745 | } 746 | 747 | NTSTATUS rt5682_set_tdm_slot(PRTEK_CONTEXT pDevice, unsigned int tx_mask, 748 | unsigned int rx_mask, int slots, int slot_width) 749 | { 750 | unsigned int cl, val = 0; 751 | 752 | if (tx_mask || rx_mask) 753 | rt5682_reg_update(pDevice, RT5682_TDM_ADDA_CTRL_2, 754 | RT5682_TDM_EN, RT5682_TDM_EN); 755 | else 756 | rt5682_reg_update(pDevice, RT5682_TDM_ADDA_CTRL_2, 757 | RT5682_TDM_EN, 0); 758 | 759 | switch (slots) { 760 | case 4: 761 | val |= RT5682_TDM_TX_CH_4; 762 | val |= RT5682_TDM_RX_CH_4; 763 | break; 764 | case 6: 765 | val |= RT5682_TDM_TX_CH_6; 766 | val |= RT5682_TDM_RX_CH_6; 767 | break; 768 | case 8: 769 | val |= RT5682_TDM_TX_CH_8; 770 | val |= RT5682_TDM_RX_CH_8; 771 | break; 772 | case 2: 773 | break; 774 | default: 775 | return STATUS_INVALID_PARAMETER; 776 | } 777 | 778 | rt5682_reg_update(pDevice, RT5682_TDM_ADDA_CTRL_2, RT5682_TDM_CTRL, 779 | RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 780 | 781 | switch (slot_width) { 782 | case 8: 783 | if (tx_mask || rx_mask) 784 | return STATUS_INVALID_PARAMETER; 785 | cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 786 | break; 787 | case 16: 788 | val = RT5682_TDM_CL_16; 789 | cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 790 | break; 791 | case 20: 792 | val = RT5682_TDM_CL_20; 793 | cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20 | RT5682_I2S1_DL_20; 794 | break; 795 | case 24: 796 | val = RT5682_TDM_CL_24; 797 | cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24 | RT5682_I2S1_DL_24; 798 | break; 799 | case 32: 800 | val = RT5682_TDM_CL_32; 801 | cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32 | RT5682_I2S1_DL_32; 802 | break; 803 | default: 804 | return STATUS_INVALID_PARAMETER; 805 | } 806 | 807 | rt5682_reg_update(pDevice, RT5682_TDM_TCON_CTRL, 808 | RT5682_TDM_CL_MASK, val); 809 | rt5682_reg_update(pDevice, RT5682_I2S1_SDP, 810 | RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK | RT5682_I2S1_DL_MASK, cl); 811 | 812 | return STATUS_SUCCESS; 813 | } 814 | 815 | NTSTATUS rt5682_set_component_sysclk(PRTEK_CONTEXT pDevice, 816 | int clk_id) 817 | { 818 | unsigned int reg_val = 0, src = 0; 819 | 820 | switch (clk_id) { 821 | case RT5682_SCLK_S_MCLK: 822 | reg_val |= RT5682_SCLK_SRC_MCLK; 823 | src = RT5682_CLK_SRC_MCLK; 824 | break; 825 | case RT5682_SCLK_S_PLL1: 826 | reg_val |= RT5682_SCLK_SRC_PLL1; 827 | src = RT5682_CLK_SRC_PLL1; 828 | break; 829 | case RT5682_SCLK_S_PLL2: 830 | reg_val |= RT5682_SCLK_SRC_PLL2; 831 | src = RT5682_CLK_SRC_PLL2; 832 | break; 833 | case RT5682_SCLK_S_RCCLK: 834 | reg_val |= RT5682_SCLK_SRC_RCCLK; 835 | src = RT5682_CLK_SRC_RCCLK; 836 | break; 837 | default: 838 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 839 | "Invalid clock id (%d)\n", clk_id); 840 | return STATUS_INVALID_PARAMETER; 841 | } 842 | rt5682_reg_update(pDevice, RT5682_GLB_CLK, 843 | RT5682_SCLK_SRC_MASK, reg_val); 844 | 845 | return STATUS_SUCCESS; 846 | } 847 | 848 | 849 | NTSTATUS 850 | OnPrepareHardware( 851 | _In_ WDFDEVICE FxDevice, 852 | _In_ WDFCMRESLIST FxResourcesRaw, 853 | _In_ WDFCMRESLIST FxResourcesTranslated 854 | ) 855 | /*++ 856 | 857 | Routine Description: 858 | 859 | This routine caches the SPB resource connection ID. 860 | 861 | Arguments: 862 | 863 | FxDevice - a handle to the framework device object 864 | FxResourcesRaw - list of translated hardware resources that 865 | the PnP manager has assigned to the device 866 | FxResourcesTranslated - list of raw hardware resources that 867 | the PnP manager has assigned to the device 868 | 869 | Return Value: 870 | 871 | Status 872 | 873 | --*/ 874 | { 875 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 876 | BOOLEAN fSpbResourceFound = FALSE; 877 | NTSTATUS status = STATUS_INSUFFICIENT_RESOURCES; 878 | 879 | UNREFERENCED_PARAMETER(FxResourcesRaw); 880 | 881 | // 882 | // Parse the peripheral's resources. 883 | // 884 | 885 | ULONG resourceCount = WdfCmResourceListGetCount(FxResourcesTranslated); 886 | 887 | for (ULONG i = 0; i < resourceCount; i++) 888 | { 889 | PCM_PARTIAL_RESOURCE_DESCRIPTOR pDescriptor; 890 | UCHAR Class; 891 | UCHAR Type; 892 | 893 | pDescriptor = WdfCmResourceListGetDescriptor( 894 | FxResourcesTranslated, i); 895 | 896 | switch (pDescriptor->Type) 897 | { 898 | case CmResourceTypeConnection: 899 | // 900 | // Look for I2C or SPI resource and save connection ID. 901 | // 902 | Class = pDescriptor->u.Connection.Class; 903 | Type = pDescriptor->u.Connection.Type; 904 | if (Class == CM_RESOURCE_CONNECTION_CLASS_SERIAL && 905 | Type == CM_RESOURCE_CONNECTION_TYPE_SERIAL_I2C) 906 | { 907 | if (fSpbResourceFound == FALSE) 908 | { 909 | status = STATUS_SUCCESS; 910 | pDevice->I2CContext.I2cResHubId.LowPart = pDescriptor->u.Connection.IdLowPart; 911 | pDevice->I2CContext.I2cResHubId.HighPart = pDescriptor->u.Connection.IdHighPart; 912 | fSpbResourceFound = TRUE; 913 | } 914 | else 915 | { 916 | } 917 | } 918 | break; 919 | default: 920 | // 921 | // Ignoring all other resource types. 922 | // 923 | break; 924 | } 925 | } 926 | 927 | // 928 | // An SPB resource is required. 929 | // 930 | 931 | if (fSpbResourceFound == FALSE) 932 | { 933 | status = STATUS_NOT_FOUND; 934 | } 935 | 936 | status = SpbTargetInitialize(FxDevice, &pDevice->I2CContext); 937 | 938 | if (!NT_SUCCESS(status)) 939 | { 940 | return status; 941 | } 942 | 943 | return status; 944 | } 945 | 946 | NTSTATUS 947 | OnReleaseHardware( 948 | _In_ WDFDEVICE FxDevice, 949 | _In_ WDFCMRESLIST FxResourcesTranslated 950 | ) 951 | /*++ 952 | 953 | Routine Description: 954 | 955 | Arguments: 956 | 957 | FxDevice - a handle to the framework device object 958 | FxResourcesTranslated - list of raw hardware resources that 959 | the PnP manager has assigned to the device 960 | 961 | Return Value: 962 | 963 | Status 964 | 965 | --*/ 966 | { 967 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 968 | NTSTATUS status = STATUS_SUCCESS; 969 | 970 | UNREFERENCED_PARAMETER(FxResourcesTranslated); 971 | 972 | SpbTargetDeinitialize(FxDevice, &pDevice->I2CContext); 973 | 974 | if (pDevice->CSAudioAPICallbackObj) { 975 | ExUnregisterCallback(pDevice->CSAudioAPICallbackObj); 976 | pDevice->CSAudioAPICallbackObj = NULL; 977 | } 978 | 979 | if (pDevice->CSAudioAPICallback) { 980 | ObfDereferenceObject(pDevice->CSAudioAPICallback); 981 | pDevice->CSAudioAPICallback = NULL; 982 | } 983 | 984 | return status; 985 | } 986 | 987 | NTSTATUS 988 | OnSelfManagedIoInit( 989 | _In_ 990 | WDFDEVICE FxDevice 991 | ) { 992 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 993 | NTSTATUS status = STATUS_SUCCESS; 994 | 995 | // CS Audio Callback 996 | 997 | UNICODE_STRING CSAudioCallbackAPI; 998 | RtlInitUnicodeString(&CSAudioCallbackAPI, L"\\CallBack\\CsAudioCallbackAPI"); 999 | 1000 | 1001 | OBJECT_ATTRIBUTES attributes; 1002 | InitializeObjectAttributes(&attributes, 1003 | &CSAudioCallbackAPI, 1004 | OBJ_KERNEL_HANDLE | OBJ_OPENIF | OBJ_CASE_INSENSITIVE | OBJ_PERMANENT, 1005 | NULL, 1006 | NULL 1007 | ); 1008 | status = ExCreateCallback(&pDevice->CSAudioAPICallback, &attributes, TRUE, TRUE); 1009 | if (!NT_SUCCESS(status)) { 1010 | 1011 | return status; 1012 | } 1013 | 1014 | pDevice->CSAudioAPICallbackObj = ExRegisterCallback(pDevice->CSAudioAPICallback, 1015 | CsAudioCallbackFunction, 1016 | pDevice 1017 | ); 1018 | if (!pDevice->CSAudioAPICallbackObj) { 1019 | 1020 | return STATUS_NO_CALLBACK_ACTIVE; 1021 | } 1022 | 1023 | CSAudioRegisterEndpoint(pDevice); 1024 | 1025 | return status; 1026 | } 1027 | 1028 | NTSTATUS 1029 | OnD0Entry( 1030 | _In_ WDFDEVICE FxDevice, 1031 | _In_ WDF_POWER_DEVICE_STATE FxPreviousState 1032 | ) 1033 | /*++ 1034 | 1035 | Routine Description: 1036 | 1037 | This routine allocates objects needed by the driver. 1038 | 1039 | Arguments: 1040 | 1041 | FxDevice - a handle to the framework device object 1042 | FxPreviousState - previous power state 1043 | 1044 | Return Value: 1045 | 1046 | Status 1047 | 1048 | --*/ 1049 | { 1050 | UNREFERENCED_PARAMETER(FxPreviousState); 1051 | 1052 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 1053 | NTSTATUS status = STATUS_SUCCESS; 1054 | 1055 | pDevice->JackType = 0; 1056 | 1057 | status = BOOTCODEC(pDevice); 1058 | if (!NT_SUCCESS(status)) { 1059 | return status; 1060 | } 1061 | 1062 | pDevice->ConnectInterrupt = true; 1063 | 1064 | RtekCompleteIdleIrp(pDevice); 1065 | 1066 | return status; 1067 | } 1068 | 1069 | NTSTATUS 1070 | OnD0Exit( 1071 | _In_ WDFDEVICE FxDevice, 1072 | _In_ WDF_POWER_DEVICE_STATE FxPreviousState 1073 | ) 1074 | /*++ 1075 | 1076 | Routine Description: 1077 | 1078 | This routine destroys objects needed by the driver. 1079 | 1080 | Arguments: 1081 | 1082 | FxDevice - a handle to the framework device object 1083 | FxPreviousState - previous power state 1084 | 1085 | Return Value: 1086 | 1087 | Status 1088 | 1089 | --*/ 1090 | { 1091 | UNREFERENCED_PARAMETER(FxPreviousState); 1092 | 1093 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 1094 | 1095 | pDevice->ConnectInterrupt = false; 1096 | 1097 | return STATUS_SUCCESS; 1098 | } 1099 | 1100 | static void rt5682_enable_push_button_irq(PRTEK_CONTEXT pDevice, 1101 | bool enable) 1102 | { 1103 | 1104 | if (enable) { 1105 | rt5682_reg_update(pDevice, RT5682_SAR_IL_CMD_1, 1106 | RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 1107 | rt5682_reg_update(pDevice, RT5682_SAR_IL_CMD_13, 1108 | RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 1109 | rt5682_reg_write(pDevice, RT5682_IL_CMD_1, 0x0040); 1110 | rt5682_reg_update(pDevice, RT5682_4BTN_IL_CMD_2, 1111 | RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 1112 | RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 1113 | 1114 | rt5682_reg_update(pDevice, 1115 | RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 1116 | RT5682_IL_IRQ_EN); 1117 | } 1118 | else { 1119 | rt5682_reg_update(pDevice, RT5682_IRQ_CTRL_3, 1120 | RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 1121 | rt5682_reg_update(pDevice, RT5682_SAR_IL_CMD_1, 1122 | RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 1123 | rt5682_reg_update(pDevice, RT5682_4BTN_IL_CMD_2, 1124 | RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 1125 | rt5682_reg_update(pDevice, RT5682_4BTN_IL_CMD_2, 1126 | RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 1127 | rt5682_reg_update(pDevice, RT5682_SAR_IL_CMD_13, 1128 | RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 1129 | } 1130 | } 1131 | 1132 | int rt5682_headset_detect(PRTEK_CONTEXT pDevice, int jack_insert) { 1133 | UINT16 val, count; 1134 | if (jack_insert) { 1135 | rt5682_reg_update(pDevice, 1136 | RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1137 | 1138 | LARGE_INTEGER WaitInterval; 1139 | WaitInterval.QuadPart = -10 * 1000 * 15; 1140 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1141 | 1142 | rt5682_reg_update(pDevice, 1143 | RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 1144 | rt5682_reg_update(pDevice, RT5682_PWR_ANLG_3, 1145 | RT5682_PWR_CBJ, RT5682_PWR_CBJ); 1146 | rt5682_reg_update(pDevice, 1147 | RT5682_HP_CHARGE_PUMP_1, 1148 | RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 1149 | 1150 | rt5682_enable_push_button_irq(pDevice, false); 1151 | 1152 | rt5682_reg_update(pDevice, RT5682_CBJ_CTRL_1, 1153 | RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 1154 | 1155 | WaitInterval.QuadPart = -10 * 1000 * 55; 1156 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1157 | 1158 | rt5682_reg_update(pDevice, RT5682_CBJ_CTRL_1, 1159 | RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 1160 | 1161 | count = 0; 1162 | rt5682_reg_read(pDevice, RT5682_CBJ_CTRL_2, &val); 1163 | val &= RT5682_JACK_TYPE_MASK; 1164 | while (val == 0 && count < 50) { 1165 | WaitInterval.QuadPart = -10 * 1000 * 15; 1166 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1167 | 1168 | rt5682_reg_read(pDevice, RT5682_CBJ_CTRL_2, &val); 1169 | val &= RT5682_JACK_TYPE_MASK; 1170 | count++; 1171 | } 1172 | 1173 | switch (val) { 1174 | case 0x1: 1175 | case 0x2: 1176 | pDevice->JackType = SND_JACK_HEADSET; 1177 | rt5682_reg_update(pDevice, RT5682_CBJ_CTRL_1, 1178 | RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN); 1179 | rt5682_enable_push_button_irq(pDevice, true); 1180 | break; 1181 | default: 1182 | pDevice->JackType = SND_JACK_HEADPHONE; 1183 | } 1184 | 1185 | rt5682_reg_update(pDevice, 1186 | RT5682_HP_CHARGE_PUMP_1, 1187 | RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 1188 | RT5682_OSW_L_EN | RT5682_OSW_R_EN); 1189 | rt5682_reg_update(pDevice, RT5682_MICBIAS_2, 1190 | RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 1191 | RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 1192 | } 1193 | else { 1194 | rt5682_enable_push_button_irq(pDevice, false); 1195 | rt5682_reg_update(pDevice, RT5682_CBJ_CTRL_1, 1196 | RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 1197 | 1198 | rt5682_reg_update(pDevice, RT5682_PWR_ANLG_3, 1199 | RT5682_PWR_CBJ, 0); 1200 | rt5682_reg_update(pDevice, RT5682_MICBIAS_2, 1201 | RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 1202 | RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 1203 | rt5682_reg_update(pDevice, RT5682_CBJ_CTRL_1, 1204 | RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS); 1205 | 1206 | pDevice->JackType = 0; 1207 | } 1208 | 1209 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1210 | "Jack Type: %d\n", pDevice->JackType); 1211 | return pDevice->JackType; 1212 | } 1213 | 1214 | static int rt5682_button_detect(PRTEK_CONTEXT pDevice) 1215 | { 1216 | UINT16 btn_type, val; 1217 | 1218 | rt5682_reg_read(pDevice, RT5682_4BTN_IL_CMD_1, &val); 1219 | btn_type = val & 0xfff0; 1220 | rt5682_reg_write(pDevice, RT5682_4BTN_IL_CMD_1, val); 1221 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1222 | "btn_type=%x\n", btn_type); 1223 | rt5682_reg_update(pDevice, 1224 | RT5682_SAR_IL_CMD_2, 0x10, 0x10); 1225 | 1226 | return btn_type; 1227 | } 1228 | 1229 | void rt5682_jackdetect(PRTEK_CONTEXT pDevice) { 1230 | NTSTATUS status = STATUS_SUCCESS; 1231 | 1232 | UINT16 val; 1233 | status = rt5682_reg_read(pDevice, RT5682_AJD1_CTRL, &val); 1234 | if (!NT_SUCCESS(status)) { 1235 | DbgPrint("Failed to read jack detect\n"); 1236 | return; 1237 | } 1238 | 1239 | val = val & RT5682_JDH_RS_MASK; 1240 | if (!val) { 1241 | /* jack in */ 1242 | if (pDevice->JackType == 0) { 1243 | /* jack was out, report jack type */ 1244 | pDevice->JackType = rt5682_headset_detect(pDevice, 1); 1245 | } 1246 | else if ((pDevice->JackType & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 1247 | /* jack is already in, report button event */ 1248 | int btn_type = rt5682_button_detect(pDevice); 1249 | /** 1250 | * rt5682 can report three kinds of button behavior, 1251 | * one click, double click and hold. However, 1252 | * currently we will report button pressed/released 1253 | * event. So all the three button behaviors are 1254 | * treated as button pressed. 1255 | */ 1256 | int rawButton = 0; 1257 | 1258 | switch (btn_type) { 1259 | case 0x8000: 1260 | case 0x4000: 1261 | case 0x2000: 1262 | rawButton = 1; 1263 | break; 1264 | case 0x1000: 1265 | case 0x0800: 1266 | case 0x0400: 1267 | rawButton = 2; 1268 | break; 1269 | case 0x0200: 1270 | case 0x0100: 1271 | case 0x0080: 1272 | rawButton = 3; 1273 | break; 1274 | case 0x0040: 1275 | case 0x0020: 1276 | case 0x0010: 1277 | rawButton = 4; 1278 | break; 1279 | case 0x0000: /* unpressed */ 1280 | break; 1281 | default: 1282 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1283 | "Unexpected button code 0x%04x\n", 1284 | btn_type); 1285 | break; 1286 | } 1287 | 1288 | Rt5682MediaReport report; 1289 | report.ReportID = REPORTID_MEDIA; 1290 | report.ControlCode = rawButton; 1291 | 1292 | size_t bytesWritten; 1293 | Rt5682ProcessVendorReport(pDevice, &report, sizeof(report), &bytesWritten); 1294 | } 1295 | } 1296 | else { 1297 | /* jack out */ 1298 | pDevice->JackType = rt5682_headset_detect(pDevice, 0); 1299 | } 1300 | 1301 | CsAudioSpecialKeyReport report; 1302 | report.ReportID = REPORTID_SPECKEYS; 1303 | report.ControlCode = CONTROL_CODE_JACK_TYPE; 1304 | report.ControlValue = pDevice->JackType; 1305 | 1306 | size_t bytesWritten; 1307 | Rt5682ProcessVendorReport(pDevice, &report, sizeof(report), &bytesWritten); 1308 | } 1309 | 1310 | VOID 1311 | RtekJdetWorkItem( 1312 | IN WDFWORKITEM WorkItem 1313 | ) 1314 | { 1315 | WDFDEVICE Device = (WDFDEVICE)WdfWorkItemGetParentObject(WorkItem); 1316 | PRTEK_CONTEXT pDevice = GetDeviceContext(Device); 1317 | 1318 | rt5682_jackdetect(pDevice); 1319 | } 1320 | 1321 | BOOLEAN OnInterruptIsr( 1322 | WDFINTERRUPT Interrupt, 1323 | ULONG MessageID) { 1324 | UNREFERENCED_PARAMETER(MessageID); 1325 | 1326 | WDFDEVICE Device = WdfInterruptGetDevice(Interrupt); 1327 | PRTEK_CONTEXT pDevice = GetDeviceContext(Device); 1328 | 1329 | if (!pDevice->ConnectInterrupt) 1330 | return true; 1331 | 1332 | NTSTATUS status = STATUS_SUCCESS; 1333 | 1334 | WDF_OBJECT_ATTRIBUTES attributes; 1335 | WDF_WORKITEM_CONFIG workitemConfig; 1336 | WDFWORKITEM hWorkItem; 1337 | 1338 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 1339 | WDF_OBJECT_ATTRIBUTES_SET_CONTEXT_TYPE(&attributes, RTEK_CONTEXT); 1340 | attributes.ParentObject = Device; 1341 | WDF_WORKITEM_CONFIG_INIT(&workitemConfig, RtekJdetWorkItem); 1342 | 1343 | WdfWorkItemCreate(&workitemConfig, 1344 | &attributes, 1345 | &hWorkItem); 1346 | 1347 | WdfWorkItemEnqueue(hWorkItem); 1348 | 1349 | return true; 1350 | } 1351 | 1352 | NTSTATUS 1353 | Rt5682EvtDeviceAdd( 1354 | IN WDFDRIVER Driver, 1355 | IN PWDFDEVICE_INIT DeviceInit 1356 | ) 1357 | { 1358 | NTSTATUS status = STATUS_SUCCESS; 1359 | WDF_IO_QUEUE_CONFIG queueConfig; 1360 | WDF_OBJECT_ATTRIBUTES attributes; 1361 | WDFDEVICE device; 1362 | WDF_INTERRUPT_CONFIG interruptConfig; 1363 | WDFQUEUE queue; 1364 | UCHAR minorFunction; 1365 | PRTEK_CONTEXT devContext; 1366 | 1367 | UNREFERENCED_PARAMETER(Driver); 1368 | 1369 | PAGED_CODE(); 1370 | 1371 | RtekPrint(DEBUG_LEVEL_INFO, DBG_PNP, 1372 | "Rt5682EvtDeviceAdd called\n"); 1373 | 1374 | // 1375 | // Tell framework this is a filter driver. Filter drivers by default are 1376 | // not power policy owners. This works well for this driver because 1377 | // HIDclass driver is the power policy owner for HID minidrivers. 1378 | // 1379 | 1380 | WdfFdoInitSetFilter(DeviceInit); 1381 | 1382 | { 1383 | WDF_PNPPOWER_EVENT_CALLBACKS pnpCallbacks; 1384 | WDF_PNPPOWER_EVENT_CALLBACKS_INIT(&pnpCallbacks); 1385 | 1386 | pnpCallbacks.EvtDevicePrepareHardware = OnPrepareHardware; 1387 | pnpCallbacks.EvtDeviceReleaseHardware = OnReleaseHardware; 1388 | pnpCallbacks.EvtDeviceSelfManagedIoInit = OnSelfManagedIoInit; 1389 | pnpCallbacks.EvtDeviceD0Entry = OnD0Entry; 1390 | pnpCallbacks.EvtDeviceD0Exit = OnD0Exit; 1391 | 1392 | WdfDeviceInitSetPnpPowerEventCallbacks(DeviceInit, &pnpCallbacks); 1393 | } 1394 | 1395 | // 1396 | // Setup the device context 1397 | // 1398 | 1399 | WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, RTEK_CONTEXT); 1400 | 1401 | // 1402 | // Create a framework device object.This call will in turn create 1403 | // a WDM device object, attach to the lower stack, and set the 1404 | // appropriate flags and attributes. 1405 | // 1406 | 1407 | status = WdfDeviceCreate(&DeviceInit, &attributes, &device); 1408 | 1409 | if (!NT_SUCCESS(status)) 1410 | { 1411 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1412 | "WdfDeviceCreate failed with status code 0x%x\n", status); 1413 | 1414 | return status; 1415 | } 1416 | 1417 | { 1418 | WDF_DEVICE_STATE deviceState; 1419 | WDF_DEVICE_STATE_INIT(&deviceState); 1420 | 1421 | deviceState.NotDisableable = WdfFalse; 1422 | WdfDeviceSetDeviceState(device, &deviceState); 1423 | } 1424 | 1425 | WDF_IO_QUEUE_CONFIG_INIT_DEFAULT_QUEUE(&queueConfig, WdfIoQueueDispatchParallel); 1426 | 1427 | queueConfig.EvtIoInternalDeviceControl = Rt5682EvtInternalDeviceControl; 1428 | 1429 | status = WdfIoQueueCreate(device, 1430 | &queueConfig, 1431 | WDF_NO_OBJECT_ATTRIBUTES, 1432 | &queue 1433 | ); 1434 | 1435 | if (!NT_SUCCESS(status)) 1436 | { 1437 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1438 | "WdfIoQueueCreate failed 0x%x\n", status); 1439 | 1440 | return status; 1441 | } 1442 | 1443 | // 1444 | // Create manual I/O queue to take care of hid report read requests 1445 | // 1446 | 1447 | devContext = GetDeviceContext(device); 1448 | 1449 | devContext->FxDevice = device; 1450 | 1451 | devContext->ReclockRequested = FALSE; 1452 | 1453 | WDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchManual); 1454 | 1455 | queueConfig.PowerManaged = WdfFalse; 1456 | 1457 | status = WdfIoQueueCreate(device, 1458 | &queueConfig, 1459 | WDF_NO_OBJECT_ATTRIBUTES, 1460 | &devContext->ReportQueue 1461 | ); 1462 | 1463 | if (!NT_SUCCESS(status)) 1464 | { 1465 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1466 | "WdfIoQueueCreate failed 0x%x\n", status); 1467 | 1468 | return status; 1469 | } 1470 | 1471 | // 1472 | // Create manual I/O queue to take care of idle power requests 1473 | // 1474 | 1475 | WDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchManual); 1476 | 1477 | queueConfig.PowerManaged = WdfFalse; 1478 | 1479 | status = WdfIoQueueCreate(device, 1480 | &queueConfig, 1481 | WDF_NO_OBJECT_ATTRIBUTES, 1482 | &devContext->IdleQueue 1483 | ); 1484 | 1485 | if (!NT_SUCCESS(status)) 1486 | { 1487 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1488 | "WdfIoQueueCreate failed 0x%x\n", status); 1489 | 1490 | return status; 1491 | } 1492 | 1493 | // 1494 | // Create an interrupt object for hardware notifications 1495 | // 1496 | WDF_INTERRUPT_CONFIG_INIT( 1497 | &interruptConfig, 1498 | OnInterruptIsr, 1499 | NULL); 1500 | interruptConfig.PassiveHandling = TRUE; 1501 | 1502 | status = WdfInterruptCreate( 1503 | device, 1504 | &interruptConfig, 1505 | WDF_NO_OBJECT_ATTRIBUTES, 1506 | &devContext->Interrupt); 1507 | 1508 | if (!NT_SUCCESS(status)) 1509 | { 1510 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1511 | "Error creating WDF interrupt object - %!STATUS!", 1512 | status); 1513 | 1514 | return status; 1515 | } 1516 | 1517 | return status; 1518 | } 1519 | 1520 | void 1521 | RtekIdleIrpWorkItem 1522 | ( 1523 | IN WDFWORKITEM IdleWorkItem 1524 | ) 1525 | { 1526 | NTSTATUS status; 1527 | PIDLE_WORKITEM_CONTEXT idleWorkItemContext; 1528 | PRTEK_CONTEXT deviceContext; 1529 | PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO idleCallbackInfo; 1530 | 1531 | idleWorkItemContext = GetIdleWorkItemContext(IdleWorkItem); 1532 | NT_ASSERT(idleWorkItemContext != NULL); 1533 | 1534 | deviceContext = GetDeviceContext(idleWorkItemContext->FxDevice); 1535 | NT_ASSERT(deviceContext != NULL); 1536 | 1537 | // 1538 | // Get the idle callback info from the workitem context 1539 | // 1540 | PIRP irp = WdfRequestWdmGetIrp(idleWorkItemContext->FxRequest); 1541 | PIO_STACK_LOCATION stackLocation = IoGetCurrentIrpStackLocation(irp); 1542 | 1543 | idleCallbackInfo = (PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO) 1544 | (stackLocation->Parameters.DeviceIoControl.Type3InputBuffer); 1545 | 1546 | // 1547 | // idleCallbackInfo is validated already, so invoke idle callback 1548 | // 1549 | idleCallbackInfo->IdleCallback(idleCallbackInfo->IdleContext); 1550 | 1551 | // 1552 | // Park this request in our IdleQueue and mark it as pending 1553 | // This way if the IRP was cancelled, WDF will cancel it for us 1554 | // 1555 | status = WdfRequestForwardToIoQueue( 1556 | idleWorkItemContext->FxRequest, 1557 | deviceContext->IdleQueue); 1558 | 1559 | if (!NT_SUCCESS(status)) 1560 | { 1561 | // 1562 | // IdleQueue is a manual-dispatch, non-power-managed queue. This should 1563 | // *never* fail. 1564 | // 1565 | 1566 | NT_ASSERTMSG("WdfRequestForwardToIoQueue to IdleQueue failed!", FALSE); 1567 | 1568 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1569 | "Error forwarding idle notification Request:0x%p to IdleQueue:0x%p - %!STATUS!", 1570 | idleWorkItemContext->FxRequest, 1571 | deviceContext->IdleQueue, 1572 | status); 1573 | 1574 | // 1575 | // Complete the request if we couldnt forward to the Idle Queue 1576 | // 1577 | WdfRequestComplete(idleWorkItemContext->FxRequest, status); 1578 | } 1579 | else 1580 | { 1581 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1582 | "Forwarded idle notification Request:0x%p to IdleQueue:0x%p - %!STATUS!", 1583 | idleWorkItemContext->FxRequest, 1584 | deviceContext->IdleQueue, 1585 | status); 1586 | } 1587 | 1588 | // 1589 | // Delete the workitem since we're done with it 1590 | // 1591 | WdfObjectDelete(IdleWorkItem); 1592 | 1593 | return; 1594 | } 1595 | 1596 | NTSTATUS 1597 | Rt5682ProcessIdleRequest( 1598 | IN PRTEK_CONTEXT pDevice, 1599 | IN WDFREQUEST Request, 1600 | OUT BOOLEAN* Complete 1601 | ) 1602 | { 1603 | PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO idleCallbackInfo; 1604 | PIRP irp; 1605 | PIO_STACK_LOCATION irpSp; 1606 | NTSTATUS status; 1607 | 1608 | NT_ASSERT(Complete != NULL); 1609 | *Complete = TRUE; 1610 | 1611 | // 1612 | // Retrieve request parameters and validate 1613 | // 1614 | irp = WdfRequestWdmGetIrp(Request); 1615 | irpSp = IoGetCurrentIrpStackLocation(irp); 1616 | 1617 | if (irpSp->Parameters.DeviceIoControl.InputBufferLength < 1618 | sizeof(HID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO)) 1619 | { 1620 | status = STATUS_INVALID_BUFFER_SIZE; 1621 | 1622 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1623 | "Error: Input buffer is too small to process idle request - %!STATUS!", 1624 | status); 1625 | 1626 | goto exit; 1627 | } 1628 | 1629 | // 1630 | // Grab the callback 1631 | // 1632 | idleCallbackInfo = (PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO) 1633 | irpSp->Parameters.DeviceIoControl.Type3InputBuffer; 1634 | 1635 | NT_ASSERT(idleCallbackInfo != NULL); 1636 | 1637 | if (idleCallbackInfo == NULL || idleCallbackInfo->IdleCallback == NULL) 1638 | { 1639 | status = STATUS_NO_CALLBACK_ACTIVE; 1640 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1641 | "Error: Idle Notification request %p has no idle callback info - %!STATUS!", 1642 | Request, 1643 | status); 1644 | goto exit; 1645 | } 1646 | 1647 | { 1648 | // 1649 | // Create a workitem for the idle callback 1650 | // 1651 | WDF_OBJECT_ATTRIBUTES workItemAttributes; 1652 | WDF_WORKITEM_CONFIG workitemConfig; 1653 | WDFWORKITEM idleWorkItem; 1654 | PIDLE_WORKITEM_CONTEXT idleWorkItemContext; 1655 | 1656 | WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&workItemAttributes, IDLE_WORKITEM_CONTEXT); 1657 | workItemAttributes.ParentObject = pDevice->FxDevice; 1658 | 1659 | WDF_WORKITEM_CONFIG_INIT(&workitemConfig, RtekIdleIrpWorkItem); 1660 | 1661 | status = WdfWorkItemCreate( 1662 | &workitemConfig, 1663 | &workItemAttributes, 1664 | &idleWorkItem 1665 | ); 1666 | 1667 | if (!NT_SUCCESS(status)) { 1668 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1669 | "Error creating creating idle work item - %!STATUS!", 1670 | status); 1671 | goto exit; 1672 | } 1673 | 1674 | // 1675 | // Set the workitem context 1676 | // 1677 | idleWorkItemContext = GetIdleWorkItemContext(idleWorkItem); 1678 | idleWorkItemContext->FxDevice = pDevice->FxDevice; 1679 | idleWorkItemContext->FxRequest = Request; 1680 | 1681 | // 1682 | // Enqueue a workitem for the idle callback 1683 | // 1684 | WdfWorkItemEnqueue(idleWorkItem); 1685 | 1686 | // 1687 | // Mark the request as pending so that 1688 | // we can complete it when we come out of idle 1689 | // 1690 | *Complete = FALSE; 1691 | } 1692 | 1693 | exit: 1694 | 1695 | return status; 1696 | } 1697 | 1698 | VOID 1699 | RtekCompleteIdleIrp( 1700 | IN PRTEK_CONTEXT FxDeviceContext 1701 | ) 1702 | /*++ 1703 | 1704 | Routine Description: 1705 | 1706 | This is invoked when we enter D0. 1707 | We simply complete the Idle Irp if it hasn't been cancelled already. 1708 | 1709 | Arguments: 1710 | 1711 | FxDeviceContext - Pointer to Device Context for the device 1712 | 1713 | Return Value: 1714 | 1715 | 1716 | 1717 | --*/ 1718 | { 1719 | NTSTATUS status; 1720 | WDFREQUEST request = NULL; 1721 | 1722 | // 1723 | // Lets try to retrieve the Idle IRP from the Idle queue 1724 | // 1725 | status = WdfIoQueueRetrieveNextRequest( 1726 | FxDeviceContext->IdleQueue, 1727 | &request); 1728 | 1729 | // 1730 | // We did not find the Idle IRP, maybe it was cancelled 1731 | // 1732 | if (!NT_SUCCESS(status) || (request == NULL)) 1733 | { 1734 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1735 | "Error finding idle notification request in IdleQueue:0x%p - %!STATUS!", 1736 | FxDeviceContext->IdleQueue, 1737 | status); 1738 | } 1739 | else 1740 | { 1741 | // 1742 | // Complete the Idle IRP 1743 | // 1744 | WdfRequestComplete(request, status); 1745 | 1746 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1747 | "Completed idle notification Request:0x%p from IdleQueue:0x%p - %!STATUS!", 1748 | request, 1749 | FxDeviceContext->IdleQueue, 1750 | status); 1751 | } 1752 | 1753 | return; 1754 | } 1755 | 1756 | VOID 1757 | Rt5682EvtInternalDeviceControl( 1758 | IN WDFQUEUE Queue, 1759 | IN WDFREQUEST Request, 1760 | IN size_t OutputBufferLength, 1761 | IN size_t InputBufferLength, 1762 | IN ULONG IoControlCode 1763 | ) 1764 | { 1765 | NTSTATUS status = STATUS_SUCCESS; 1766 | WDFDEVICE device; 1767 | PRTEK_CONTEXT devContext; 1768 | BOOLEAN completeRequest = TRUE; 1769 | 1770 | UNREFERENCED_PARAMETER(OutputBufferLength); 1771 | UNREFERENCED_PARAMETER(InputBufferLength); 1772 | 1773 | device = WdfIoQueueGetDevice(Queue); 1774 | devContext = GetDeviceContext(device); 1775 | 1776 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1777 | "%s, Queue:0x%p, Request:0x%p\n", 1778 | DbgHidInternalIoctlString(IoControlCode), 1779 | Queue, 1780 | Request 1781 | ); 1782 | 1783 | // 1784 | // Please note that HIDCLASS provides the buffer in the Irp->UserBuffer 1785 | // field irrespective of the ioctl buffer type. However, framework is very 1786 | // strict about type checking. You cannot get Irp->UserBuffer by using 1787 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 1788 | // internal ioctl. So depending on the ioctl code, we will either 1789 | // use retreive function or escape to WDM to get the UserBuffer. 1790 | // 1791 | 1792 | switch (IoControlCode) 1793 | { 1794 | 1795 | case IOCTL_HID_GET_DEVICE_DESCRIPTOR: 1796 | // 1797 | // Retrieves the device's HID descriptor. 1798 | // 1799 | status = Rt5682GetHidDescriptor(device, Request); 1800 | break; 1801 | 1802 | case IOCTL_HID_GET_DEVICE_ATTRIBUTES: 1803 | // 1804 | //Retrieves a device's attributes in a HID_DEVICE_ATTRIBUTES structure. 1805 | // 1806 | status = Rt5682GetDeviceAttributes(Request); 1807 | break; 1808 | 1809 | case IOCTL_HID_GET_REPORT_DESCRIPTOR: 1810 | // 1811 | //Obtains the report descriptor for the HID device. 1812 | // 1813 | status = Rt5682GetReportDescriptor(device, Request); 1814 | break; 1815 | 1816 | case IOCTL_HID_GET_STRING: 1817 | // 1818 | // Requests that the HID minidriver retrieve a human-readable string 1819 | // for either the manufacturer ID, the product ID, or the serial number 1820 | // from the string descriptor of the device. The minidriver must send 1821 | // a Get String Descriptor request to the device, in order to retrieve 1822 | // the string descriptor, then it must extract the string at the 1823 | // appropriate index from the string descriptor and return it in the 1824 | // output buffer indicated by the IRP. Before sending the Get String 1825 | // Descriptor request, the minidriver must retrieve the appropriate 1826 | // index for the manufacturer ID, the product ID or the serial number 1827 | // from the device extension of a top level collection associated with 1828 | // the device. 1829 | // 1830 | status = Rt5682GetString(Request); 1831 | break; 1832 | 1833 | case IOCTL_HID_WRITE_REPORT: 1834 | case IOCTL_HID_SET_OUTPUT_REPORT: 1835 | // 1836 | //Transmits a class driver-supplied report to the device. 1837 | // 1838 | status = Rt5682WriteReport(devContext, Request); 1839 | break; 1840 | 1841 | case IOCTL_HID_READ_REPORT: 1842 | case IOCTL_HID_GET_INPUT_REPORT: 1843 | // 1844 | // Returns a report from the device into a class driver-supplied buffer. 1845 | // 1846 | status = Rt5682ReadReport(devContext, Request, &completeRequest); 1847 | break; 1848 | 1849 | case IOCTL_HID_SET_FEATURE: 1850 | // 1851 | // This sends a HID class feature report to a top-level collection of 1852 | // a HID class device. 1853 | // 1854 | status = Rt5682SetFeature(devContext, Request, &completeRequest); 1855 | break; 1856 | 1857 | case IOCTL_HID_GET_FEATURE: 1858 | // 1859 | // returns a feature report associated with a top-level collection 1860 | status = Rt5682GetFeature(devContext, Request, &completeRequest); 1861 | break; 1862 | 1863 | case IOCTL_HID_SEND_IDLE_NOTIFICATION_REQUEST: 1864 | //Handle HID Idle request 1865 | status = Rt5682ProcessIdleRequest(devContext, Request, &completeRequest); 1866 | break; 1867 | 1868 | case IOCTL_HID_ACTIVATE_DEVICE: 1869 | // 1870 | // Makes the device ready for I/O operations. 1871 | // 1872 | case IOCTL_HID_DEACTIVATE_DEVICE: 1873 | // 1874 | // Causes the device to cease operations and terminate all outstanding 1875 | // I/O requests. 1876 | // 1877 | default: 1878 | status = STATUS_NOT_SUPPORTED; 1879 | break; 1880 | } 1881 | 1882 | if (completeRequest) 1883 | { 1884 | WdfRequestComplete(Request, status); 1885 | 1886 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1887 | "%s completed, Queue:0x%p, Request:0x%p\n", 1888 | DbgHidInternalIoctlString(IoControlCode), 1889 | Queue, 1890 | Request 1891 | ); 1892 | } 1893 | else 1894 | { 1895 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1896 | "%s deferred, Queue:0x%p, Request:0x%p\n", 1897 | DbgHidInternalIoctlString(IoControlCode), 1898 | Queue, 1899 | Request 1900 | ); 1901 | } 1902 | 1903 | return; 1904 | } 1905 | 1906 | NTSTATUS 1907 | Rt5682GetHidDescriptor( 1908 | IN WDFDEVICE Device, 1909 | IN WDFREQUEST Request 1910 | ) 1911 | { 1912 | NTSTATUS status = STATUS_SUCCESS; 1913 | size_t bytesToCopy = 0; 1914 | WDFMEMORY memory; 1915 | 1916 | UNREFERENCED_PARAMETER(Device); 1917 | 1918 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1919 | "Rt5682GetHidDescriptor Entry\n"); 1920 | 1921 | // 1922 | // This IOCTL is METHOD_NEITHER so WdfRequestRetrieveOutputMemory 1923 | // will correctly retrieve buffer from Irp->UserBuffer. 1924 | // Remember that HIDCLASS provides the buffer in the Irp->UserBuffer 1925 | // field irrespective of the ioctl buffer type. However, framework is very 1926 | // strict about type checking. You cannot get Irp->UserBuffer by using 1927 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 1928 | // internal ioctl. 1929 | // 1930 | status = WdfRequestRetrieveOutputMemory(Request, &memory); 1931 | 1932 | if (!NT_SUCCESS(status)) 1933 | { 1934 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1935 | "WdfRequestRetrieveOutputMemory failed 0x%x\n", status); 1936 | 1937 | return status; 1938 | } 1939 | 1940 | // 1941 | // Use hardcoded "HID Descriptor" 1942 | // 1943 | bytesToCopy = DefaultHidDescriptor.bLength; 1944 | 1945 | if (bytesToCopy == 0) 1946 | { 1947 | status = STATUS_INVALID_DEVICE_STATE; 1948 | 1949 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1950 | "DefaultHidDescriptor is zero, 0x%x\n", status); 1951 | 1952 | return status; 1953 | } 1954 | 1955 | status = WdfMemoryCopyFromBuffer(memory, 1956 | 0, // Offset 1957 | (PVOID)&DefaultHidDescriptor, 1958 | bytesToCopy); 1959 | 1960 | if (!NT_SUCCESS(status)) 1961 | { 1962 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1963 | "WdfMemoryCopyFromBuffer failed 0x%x\n", status); 1964 | 1965 | return status; 1966 | } 1967 | 1968 | // 1969 | // Report how many bytes were copied 1970 | // 1971 | WdfRequestSetInformation(Request, bytesToCopy); 1972 | 1973 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1974 | "Rt5682GetHidDescriptor Exit = 0x%x\n", status); 1975 | 1976 | return status; 1977 | } 1978 | 1979 | NTSTATUS 1980 | Rt5682GetReportDescriptor( 1981 | IN WDFDEVICE Device, 1982 | IN WDFREQUEST Request 1983 | ) 1984 | { 1985 | NTSTATUS status = STATUS_SUCCESS; 1986 | ULONG_PTR bytesToCopy; 1987 | WDFMEMORY memory; 1988 | 1989 | PRTEK_CONTEXT devContext = GetDeviceContext(Device); 1990 | 1991 | UNREFERENCED_PARAMETER(Device); 1992 | 1993 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1994 | "Rt5682GetReportDescriptor Entry\n"); 1995 | 1996 | // 1997 | // This IOCTL is METHOD_NEITHER so WdfRequestRetrieveOutputMemory 1998 | // will correctly retrieve buffer from Irp->UserBuffer. 1999 | // Remember that HIDCLASS provides the buffer in the Irp->UserBuffer 2000 | // field irrespective of the ioctl buffer type. However, framework is very 2001 | // strict about type checking. You cannot get Irp->UserBuffer by using 2002 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 2003 | // internal ioctl. 2004 | // 2005 | status = WdfRequestRetrieveOutputMemory(Request, &memory); 2006 | if (!NT_SUCCESS(status)) 2007 | { 2008 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2009 | "WdfRequestRetrieveOutputMemory failed 0x%x\n", status); 2010 | 2011 | return status; 2012 | } 2013 | 2014 | // 2015 | // Use hardcoded Report descriptor 2016 | // 2017 | bytesToCopy = DefaultHidDescriptor.DescriptorList[0].wReportLength; 2018 | 2019 | if (bytesToCopy == 0) 2020 | { 2021 | status = STATUS_INVALID_DEVICE_STATE; 2022 | 2023 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2024 | "DefaultHidDescriptor's reportLength is zero, 0x%x\n", status); 2025 | 2026 | return status; 2027 | } 2028 | 2029 | status = WdfMemoryCopyFromBuffer(memory, 2030 | 0, 2031 | (PVOID)DefaultReportDescriptor, 2032 | bytesToCopy); 2033 | if (!NT_SUCCESS(status)) 2034 | { 2035 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2036 | "WdfMemoryCopyFromBuffer failed 0x%x\n", status); 2037 | 2038 | return status; 2039 | } 2040 | 2041 | // 2042 | // Report how many bytes were copied 2043 | // 2044 | WdfRequestSetInformation(Request, bytesToCopy); 2045 | 2046 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2047 | "Rt5682GetReportDescriptor Exit = 0x%x\n", status); 2048 | 2049 | return status; 2050 | } 2051 | 2052 | 2053 | NTSTATUS 2054 | Rt5682GetDeviceAttributes( 2055 | IN WDFREQUEST Request 2056 | ) 2057 | { 2058 | NTSTATUS status = STATUS_SUCCESS; 2059 | PHID_DEVICE_ATTRIBUTES deviceAttributes = NULL; 2060 | 2061 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2062 | "Rt5682GetDeviceAttributes Entry\n"); 2063 | 2064 | // 2065 | // This IOCTL is METHOD_NEITHER so WdfRequestRetrieveOutputMemory 2066 | // will correctly retrieve buffer from Irp->UserBuffer. 2067 | // Remember that HIDCLASS provides the buffer in the Irp->UserBuffer 2068 | // field irrespective of the ioctl buffer type. However, framework is very 2069 | // strict about type checking. You cannot get Irp->UserBuffer by using 2070 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 2071 | // internal ioctl. 2072 | // 2073 | status = WdfRequestRetrieveOutputBuffer(Request, 2074 | sizeof(HID_DEVICE_ATTRIBUTES), 2075 | (PVOID *)&deviceAttributes, 2076 | NULL); 2077 | if (!NT_SUCCESS(status)) 2078 | { 2079 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2080 | "WdfRequestRetrieveOutputBuffer failed 0x%x\n", status); 2081 | 2082 | return status; 2083 | } 2084 | 2085 | // 2086 | // Set USB device descriptor 2087 | // 2088 | 2089 | deviceAttributes->Size = sizeof(HID_DEVICE_ATTRIBUTES); 2090 | deviceAttributes->VendorID = RT5682_VID; 2091 | deviceAttributes->ProductID = RT5682_PID; 2092 | deviceAttributes->VersionNumber = RT5682_VERSION; 2093 | 2094 | // 2095 | // Report how many bytes were copied 2096 | // 2097 | WdfRequestSetInformation(Request, sizeof(HID_DEVICE_ATTRIBUTES)); 2098 | 2099 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2100 | "Rt5682GetDeviceAttributes Exit = 0x%x\n", status); 2101 | 2102 | return status; 2103 | } 2104 | 2105 | NTSTATUS 2106 | Rt5682GetString( 2107 | IN WDFREQUEST Request 2108 | ) 2109 | { 2110 | 2111 | NTSTATUS status = STATUS_SUCCESS; 2112 | PWSTR pwstrID; 2113 | size_t lenID; 2114 | WDF_REQUEST_PARAMETERS params; 2115 | void *pStringBuffer = NULL; 2116 | 2117 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2118 | "Rt5682GetString Entry\n"); 2119 | 2120 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2121 | WdfRequestGetParameters(Request, ¶ms); 2122 | 2123 | switch ((ULONG_PTR)params.Parameters.DeviceIoControl.Type3InputBuffer & 0xFFFF) 2124 | { 2125 | case HID_STRING_ID_IMANUFACTURER: 2126 | pwstrID = L"Rt5682.\0"; 2127 | break; 2128 | 2129 | case HID_STRING_ID_IPRODUCT: 2130 | pwstrID = L"MaxTouch Touch Screen\0"; 2131 | break; 2132 | 2133 | case HID_STRING_ID_ISERIALNUMBER: 2134 | pwstrID = L"123123123\0"; 2135 | break; 2136 | 2137 | default: 2138 | pwstrID = NULL; 2139 | break; 2140 | } 2141 | 2142 | lenID = pwstrID ? wcslen(pwstrID) * sizeof(WCHAR) + sizeof(UNICODE_NULL) : 0; 2143 | 2144 | if (pwstrID == NULL) 2145 | { 2146 | 2147 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2148 | "Rt5682GetString Invalid request type\n"); 2149 | 2150 | status = STATUS_INVALID_PARAMETER; 2151 | 2152 | return status; 2153 | } 2154 | 2155 | status = WdfRequestRetrieveOutputBuffer(Request, 2156 | lenID, 2157 | &pStringBuffer, 2158 | &lenID); 2159 | 2160 | if (!NT_SUCCESS(status)) 2161 | { 2162 | 2163 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2164 | "Rt5682GetString WdfRequestRetrieveOutputBuffer failed Status 0x%x\n", status); 2165 | 2166 | return status; 2167 | } 2168 | 2169 | RtlCopyMemory(pStringBuffer, pwstrID, lenID); 2170 | 2171 | WdfRequestSetInformation(Request, lenID); 2172 | 2173 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2174 | "Rt5682GetString Exit = 0x%x\n", status); 2175 | 2176 | return status; 2177 | } 2178 | 2179 | NTSTATUS 2180 | Rt5682WriteReport( 2181 | IN PRTEK_CONTEXT DevContext, 2182 | IN WDFREQUEST Request 2183 | ) 2184 | { 2185 | NTSTATUS status = STATUS_SUCCESS; 2186 | WDF_REQUEST_PARAMETERS params; 2187 | PHID_XFER_PACKET transferPacket = NULL; 2188 | size_t bytesWritten = 0; 2189 | 2190 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2191 | "Rt5682WriteReport Entry\n"); 2192 | 2193 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2194 | WdfRequestGetParameters(Request, ¶ms); 2195 | 2196 | if (params.Parameters.DeviceIoControl.InputBufferLength < sizeof(HID_XFER_PACKET)) 2197 | { 2198 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2199 | "Rt5682WriteReport Xfer packet too small\n"); 2200 | 2201 | status = STATUS_BUFFER_TOO_SMALL; 2202 | } 2203 | else 2204 | { 2205 | 2206 | transferPacket = (PHID_XFER_PACKET)WdfRequestWdmGetIrp(Request)->UserBuffer; 2207 | 2208 | if (transferPacket == NULL) 2209 | { 2210 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2211 | "Rt5682WriteReport No xfer packet\n"); 2212 | 2213 | status = STATUS_INVALID_DEVICE_REQUEST; 2214 | } 2215 | else 2216 | { 2217 | // 2218 | // switch on the report id 2219 | // 2220 | 2221 | switch (transferPacket->reportId) 2222 | { 2223 | case REPORTID_SPECKEYS: 2224 | status = STATUS_SUCCESS; 2225 | 2226 | CsAudioSpecialKeyReport report; 2227 | report.ReportID = REPORTID_SPECKEYS; 2228 | report.ControlCode = CONTROL_CODE_JACK_TYPE; 2229 | report.ControlValue = DevContext->JackType; 2230 | 2231 | size_t bytesWritten; 2232 | Rt5682ProcessVendorReport(DevContext, &report, sizeof(report), &bytesWritten); 2233 | break; 2234 | default: 2235 | 2236 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2237 | "Rt5682WriteReport Unhandled report type %d\n", transferPacket->reportId); 2238 | 2239 | status = STATUS_INVALID_PARAMETER; 2240 | 2241 | break; 2242 | } 2243 | } 2244 | } 2245 | 2246 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2247 | "Rt5682WriteReport Exit = 0x%x\n", status); 2248 | 2249 | return status; 2250 | 2251 | } 2252 | 2253 | NTSTATUS 2254 | Rt5682ProcessVendorReport( 2255 | IN PRTEK_CONTEXT DevContext, 2256 | IN PVOID ReportBuffer, 2257 | IN ULONG ReportBufferLen, 2258 | OUT size_t* BytesWritten 2259 | ) 2260 | { 2261 | NTSTATUS status = STATUS_SUCCESS; 2262 | WDFREQUEST reqRead; 2263 | PVOID pReadReport = NULL; 2264 | size_t bytesReturned = 0; 2265 | 2266 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2267 | "Rt5682ProcessVendorReport Entry\n"); 2268 | 2269 | status = WdfIoQueueRetrieveNextRequest(DevContext->ReportQueue, 2270 | &reqRead); 2271 | 2272 | if (NT_SUCCESS(status)) 2273 | { 2274 | status = WdfRequestRetrieveOutputBuffer(reqRead, 2275 | ReportBufferLen, 2276 | &pReadReport, 2277 | &bytesReturned); 2278 | 2279 | if (NT_SUCCESS(status)) 2280 | { 2281 | // 2282 | // Copy ReportBuffer into read request 2283 | // 2284 | 2285 | if (bytesReturned > ReportBufferLen) 2286 | { 2287 | bytesReturned = ReportBufferLen; 2288 | } 2289 | 2290 | RtlCopyMemory(pReadReport, 2291 | ReportBuffer, 2292 | bytesReturned); 2293 | 2294 | // 2295 | // Complete read with the number of bytes returned as info 2296 | // 2297 | 2298 | WdfRequestCompleteWithInformation(reqRead, 2299 | status, 2300 | bytesReturned); 2301 | 2302 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 2303 | "Rt5682ProcessVendorReport %d bytes returned\n", bytesReturned); 2304 | 2305 | // 2306 | // Return the number of bytes written for the write request completion 2307 | // 2308 | 2309 | *BytesWritten = bytesReturned; 2310 | 2311 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 2312 | "%s completed, Queue:0x%p, Request:0x%p\n", 2313 | DbgHidInternalIoctlString(IOCTL_HID_READ_REPORT), 2314 | DevContext->ReportQueue, 2315 | reqRead); 2316 | } 2317 | else 2318 | { 2319 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2320 | "WdfRequestRetrieveOutputBuffer failed Status 0x%x\n", status); 2321 | } 2322 | } 2323 | else 2324 | { 2325 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2326 | "WdfIoQueueRetrieveNextRequest failed Status 0x%x\n", status); 2327 | } 2328 | 2329 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2330 | "Rt5682ProcessVendorReport Exit = 0x%x\n", status); 2331 | 2332 | return status; 2333 | } 2334 | 2335 | NTSTATUS 2336 | Rt5682ReadReport( 2337 | IN PRTEK_CONTEXT DevContext, 2338 | IN WDFREQUEST Request, 2339 | OUT BOOLEAN* CompleteRequest 2340 | ) 2341 | { 2342 | NTSTATUS status = STATUS_SUCCESS; 2343 | 2344 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2345 | "Rt5682ReadReport Entry\n"); 2346 | 2347 | // 2348 | // Forward this read request to our manual queue 2349 | // (in other words, we are going to defer this request 2350 | // until we have a corresponding write request to 2351 | // match it with) 2352 | // 2353 | 2354 | status = WdfRequestForwardToIoQueue(Request, DevContext->ReportQueue); 2355 | 2356 | if (!NT_SUCCESS(status)) 2357 | { 2358 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2359 | "WdfRequestForwardToIoQueue failed Status 0x%x\n", status); 2360 | } 2361 | else 2362 | { 2363 | *CompleteRequest = FALSE; 2364 | } 2365 | 2366 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2367 | "Rt5682ReadReport Exit = 0x%x\n", status); 2368 | 2369 | return status; 2370 | } 2371 | 2372 | NTSTATUS 2373 | Rt5682SetFeature( 2374 | IN PRTEK_CONTEXT DevContext, 2375 | IN WDFREQUEST Request, 2376 | OUT BOOLEAN* CompleteRequest 2377 | ) 2378 | { 2379 | NTSTATUS status = STATUS_SUCCESS; 2380 | WDF_REQUEST_PARAMETERS params; 2381 | PHID_XFER_PACKET transferPacket = NULL; 2382 | 2383 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2384 | "Rt5682SetFeature Entry\n"); 2385 | 2386 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2387 | WdfRequestGetParameters(Request, ¶ms); 2388 | 2389 | if (params.Parameters.DeviceIoControl.InputBufferLength < sizeof(HID_XFER_PACKET)) 2390 | { 2391 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2392 | "Rt5682SetFeature Xfer packet too small\n"); 2393 | 2394 | status = STATUS_BUFFER_TOO_SMALL; 2395 | } 2396 | else 2397 | { 2398 | 2399 | transferPacket = (PHID_XFER_PACKET)WdfRequestWdmGetIrp(Request)->UserBuffer; 2400 | 2401 | if (transferPacket == NULL) 2402 | { 2403 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2404 | "Rt5682WriteReport No xfer packet\n"); 2405 | 2406 | status = STATUS_INVALID_DEVICE_REQUEST; 2407 | } 2408 | else 2409 | { 2410 | // 2411 | // switch on the report id 2412 | // 2413 | 2414 | switch (transferPacket->reportId) 2415 | { 2416 | default: 2417 | 2418 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2419 | "Rt5682SetFeature Unhandled report type %d\n", transferPacket->reportId); 2420 | 2421 | status = STATUS_INVALID_PARAMETER; 2422 | 2423 | break; 2424 | } 2425 | } 2426 | } 2427 | 2428 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2429 | "Rt5682SetFeature Exit = 0x%x\n", status); 2430 | 2431 | return status; 2432 | } 2433 | 2434 | NTSTATUS 2435 | Rt5682GetFeature( 2436 | IN PRTEK_CONTEXT DevContext, 2437 | IN WDFREQUEST Request, 2438 | OUT BOOLEAN* CompleteRequest 2439 | ) 2440 | { 2441 | NTSTATUS status = STATUS_SUCCESS; 2442 | WDF_REQUEST_PARAMETERS params; 2443 | PHID_XFER_PACKET transferPacket = NULL; 2444 | 2445 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2446 | "Rt5682GetFeature Entry\n"); 2447 | 2448 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2449 | WdfRequestGetParameters(Request, ¶ms); 2450 | 2451 | if (params.Parameters.DeviceIoControl.OutputBufferLength < sizeof(HID_XFER_PACKET)) 2452 | { 2453 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2454 | "Rt5682GetFeature Xfer packet too small\n"); 2455 | 2456 | status = STATUS_BUFFER_TOO_SMALL; 2457 | } 2458 | else 2459 | { 2460 | 2461 | transferPacket = (PHID_XFER_PACKET)WdfRequestWdmGetIrp(Request)->UserBuffer; 2462 | 2463 | if (transferPacket == NULL) 2464 | { 2465 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2466 | "Rt5682GetFeature No xfer packet\n"); 2467 | 2468 | status = STATUS_INVALID_DEVICE_REQUEST; 2469 | } 2470 | else 2471 | { 2472 | // 2473 | // switch on the report id 2474 | // 2475 | 2476 | switch (transferPacket->reportId) 2477 | { 2478 | default: 2479 | 2480 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2481 | "Rt5682GetFeature Unhandled report type %d\n", transferPacket->reportId); 2482 | 2483 | status = STATUS_INVALID_PARAMETER; 2484 | 2485 | break; 2486 | } 2487 | } 2488 | } 2489 | 2490 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2491 | "Rt5682GetFeature Exit = 0x%x\n", status); 2492 | 2493 | return status; 2494 | } 2495 | 2496 | PCHAR 2497 | DbgHidInternalIoctlString( 2498 | IN ULONG IoControlCode 2499 | ) 2500 | { 2501 | switch (IoControlCode) 2502 | { 2503 | case IOCTL_HID_GET_DEVICE_DESCRIPTOR: 2504 | return "IOCTL_HID_GET_DEVICE_DESCRIPTOR"; 2505 | case IOCTL_HID_GET_REPORT_DESCRIPTOR: 2506 | return "IOCTL_HID_GET_REPORT_DESCRIPTOR"; 2507 | case IOCTL_HID_READ_REPORT: 2508 | return "IOCTL_HID_READ_REPORT"; 2509 | case IOCTL_HID_GET_DEVICE_ATTRIBUTES: 2510 | return "IOCTL_HID_GET_DEVICE_ATTRIBUTES"; 2511 | case IOCTL_HID_WRITE_REPORT: 2512 | return "IOCTL_HID_WRITE_REPORT"; 2513 | case IOCTL_HID_SET_FEATURE: 2514 | return "IOCTL_HID_SET_FEATURE"; 2515 | case IOCTL_HID_GET_FEATURE: 2516 | return "IOCTL_HID_GET_FEATURE"; 2517 | case IOCTL_HID_GET_STRING: 2518 | return "IOCTL_HID_GET_STRING"; 2519 | case IOCTL_HID_ACTIVATE_DEVICE: 2520 | return "IOCTL_HID_ACTIVATE_DEVICE"; 2521 | case IOCTL_HID_DEACTIVATE_DEVICE: 2522 | return "IOCTL_HID_DEACTIVATE_DEVICE"; 2523 | case IOCTL_HID_SEND_IDLE_NOTIFICATION_REQUEST: 2524 | return "IOCTL_HID_SEND_IDLE_NOTIFICATION_REQUEST"; 2525 | case IOCTL_HID_SET_OUTPUT_REPORT: 2526 | return "IOCTL_HID_SET_OUTPUT_REPORT"; 2527 | case IOCTL_HID_GET_INPUT_REPORT: 2528 | return "IOCTL_HID_GET_INPUT_REPORT"; 2529 | default: 2530 | return "Unknown IOCTL"; 2531 | } 2532 | } --------------------------------------------------------------------------------