├── rt5682s ├── stdint.h ├── resource.h ├── hidcommon.h ├── rt5682s.rc ├── trace.h ├── spb.h ├── rt5682s.inf ├── rt5682s.vcxproj ├── rt5682s.h ├── spb.c ├── registers.h └── rt5682s.c ├── README.md ├── rt5682s.sln ├── LICENSE.txt ├── .gitignore └── rt5682s Package └── rt5682s Package.vcxproj /rt5682s/stdint.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define BIT(nr) (1UL << (nr)) -------------------------------------------------------------------------------- /rt5682s/resource.h: -------------------------------------------------------------------------------- 1 | //{{NO_DEPENDENCIES}} 2 | // Microsoft Visual C++ generated include file. 3 | // Used by rt5682s.rc 4 | 5 | // Next default values for new objects 6 | // 7 | #ifdef APSTUDIO_INVOKED 8 | #ifndef APSTUDIO_READONLY_SYMBOLS 9 | #define _APS_NEXT_RESOURCE_VALUE 101 10 | #define _APS_NEXT_COMMAND_VALUE 40001 11 | #define _APS_NEXT_CONTROL_VALUE 1001 12 | #define _APS_NEXT_SYMED_VALUE 101 13 | #endif 14 | #endif 15 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # rt5682s 2 | Realtek ALC 5682s I2C Codec driver 3 | 4 | Supports: 5 | * Jack Detection 6 | * Headphone output 7 | * Sleep/Wake 8 | * Microphone input 9 | 10 | Note: 11 | * Intel SST and AMD ACP proprietary drivers do NOT have documented interfaces, so this driver will not work with them. 12 | * Using this driver on chromebooks with this audio chip will require using CoolStar ACP Audio, CoolStar SST Audio or CoolStar SOF Audio 13 | * Certain chromebooks will also need the Chrome EC + Chrome EC I2C drivers to be able to use this driver 14 | 15 | Tested on Framework Laptop Chromebook Edition 16 | -------------------------------------------------------------------------------- /rt5682s/hidcommon.h: -------------------------------------------------------------------------------- 1 | #if !defined(_RT5682_COMMON_H_) 2 | #define _RT5682_COMMON_H_ 3 | 4 | // 5 | //These are the device attributes returned by vmulti in response 6 | // to IOCTL_HID_GET_DEVICE_ATTRIBUTES. 7 | // 8 | 9 | #define RT5682_PID 0x5682 10 | #define RT5682_VID 0x10EC 11 | #define RT5682_VERSION 0x0001 12 | 13 | // 14 | // These are the report ids 15 | // 16 | 17 | #define REPORTID_MEDIA 0x01 18 | #define REPORTID_SPECKEYS 0x02 19 | 20 | #pragma pack(1) 21 | typedef struct _RT5682_MEDIA_REPORT 22 | { 23 | 24 | BYTE ReportID; 25 | 26 | BYTE ControlCode; 27 | 28 | } Rt5682MediaReport; 29 | #pragma pack() 30 | 31 | #define CONTROL_CODE_JACK_TYPE 0x1 32 | 33 | #pragma pack(1) 34 | typedef struct _CSAUDIO_SPECKEY_REPORT 35 | { 36 | 37 | BYTE ReportID; 38 | 39 | BYTE ControlCode; 40 | 41 | BYTE ControlValue; 42 | 43 | } CsAudioSpecialKeyReport; 44 | 45 | #pragma pack() 46 | 47 | #pragma pack(1) 48 | typedef struct _CSAUDIO_SPECKEYREQ_REPORT 49 | { 50 | 51 | BYTE ReportID; 52 | 53 | BYTE AnyCode; 54 | 55 | } CsAudioSpecialKeyRequestReport; 56 | #pragma pack() 57 | 58 | #endif 59 | -------------------------------------------------------------------------------- /rt5682s/rt5682s.rc: -------------------------------------------------------------------------------- 1 | /*++ 2 | 3 | Copyright (c) Microsoft Corporation All Rights Reserved 4 | 5 | Module Name: 6 | 7 | rt5682s.rc 8 | 9 | Abstract: 10 | 11 | --*/ 12 | 13 | #include 14 | 15 | #define VER_FILETYPE VFT_DRV 16 | #define VER_FILESUBTYPE VFT2_DRV_SOUND 17 | #define VER_FILEDESCRIPTION_STR "Realtek ALC5682s I2S Audio" 18 | #define VER_INTERNALNAME_STR "rt5682s.sys" 19 | #define VER_ORIGINALFILENAME_STR "rt5682s.sys" 20 | 21 | #define VER_LEGALCOPYRIGHT_YEARS "2023" 22 | #define VER_LEGALCOPYRIGHT_STR "Copyright (C) " VER_LEGALCOPYRIGHT_YEARS " CoolStar." 23 | 24 | #define VER_FILEVERSION 1,0,1,0 25 | #define VER_PRODUCTVERSION_STR "1.0.1.0" 26 | #define VER_PRODUCTVERSION 1,0,1,0 27 | #define LVER_PRODUCTVERSION_STR L"1.0.1.0" 28 | 29 | #define VER_FILEFLAGSMASK (VS_FF_DEBUG | VS_FF_PRERELEASE) 30 | #ifdef DEBUG 31 | #define VER_FILEFLAGS (VS_FF_DEBUG) 32 | #else 33 | #define VER_FILEFLAGS (0) 34 | #endif 35 | 36 | #define VER_FILEOS VOS_NT_WINDOWS32 37 | 38 | #define VER_COMPANYNAME_STR "CoolStar" 39 | #define VER_PRODUCTNAME_STR "Realtek ALC5682s I2S Audio" 40 | 41 | #include "common.ver" -------------------------------------------------------------------------------- /rt5682s/trace.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #ifndef _TRACE_H_ 4 | #define _TRACE_H_ 5 | 6 | extern "C" 7 | { 8 | // 9 | // Tracing Definitions: 10 | // 11 | // Control GUID: 12 | // {73e3b785-f5fb-423e-94a9-56627fea9053} 13 | // 14 | 15 | #define WPP_CONTROL_GUIDS \ 16 | WPP_DEFINE_CONTROL_GUID( \ 17 | SpbTestToolTraceGuid, \ 18 | (73e3b785,f5fb,423e,94a9,56627fea9053), \ 19 | WPP_DEFINE_BIT(TRACE_FLAG_WDFLOADING) \ 20 | WPP_DEFINE_BIT(TRACE_FLAG_SPBAPI) \ 21 | WPP_DEFINE_BIT(TRACE_FLAG_OTHER) \ 22 | ) 23 | } 24 | 25 | #define WPP_LEVEL_FLAGS_LOGGER(level,flags) WPP_LEVEL_LOGGER(flags) 26 | #define WPP_LEVEL_FLAGS_ENABLED(level, flags) (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= level) 27 | 28 | #define Trace CyapaPrint 29 | #define FuncEntry 30 | #define FuncExit 31 | #define WPP_INIT_TRACING 32 | #define WPP_CLEANUP 33 | #define TRACE_FLAG_SPBAPI 0 34 | #define TRACE_FLAG_WDFLOADING 0 35 | 36 | // begin_wpp config 37 | // FUNC FuncEntry{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 38 | // FUNC FuncExit{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS); 39 | // USEPREFIX(FuncEntry, "%!STDPREFIX! [%!FUNC!] --> entry"); 40 | // USEPREFIX(FuncExit, "%!STDPREFIX! [%!FUNC!] <--"); 41 | // end_wpp 42 | 43 | #endif _TRACE_H_ 44 | -------------------------------------------------------------------------------- /rt5682s/spb.h: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.h 8 | 9 | Abstract: 10 | 11 | This module contains the touch driver I2C helper definitions. 12 | 13 | Environment: 14 | 15 | Kernel Mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #pragma once 22 | 23 | #include 24 | #include 25 | 26 | #define DEFAULT_SPB_BUFFER_SIZE 64 27 | #define RESHUB_USE_HELPER_ROUTINES 28 | 29 | // 30 | // SPB (I2C) context 31 | // 32 | 33 | typedef struct _SPB_CONTEXT 34 | { 35 | WDFIOTARGET SpbIoTarget; 36 | LARGE_INTEGER I2cResHubId; 37 | WDFMEMORY WriteMemory; 38 | WDFMEMORY ReadMemory; 39 | WDFWAITLOCK SpbLock; 40 | } SPB_CONTEXT; 41 | 42 | NTSTATUS 43 | SpbXferDataSynchronously( 44 | _In_ SPB_CONTEXT* SpbContext, 45 | _In_ PVOID SendData, 46 | _In_ ULONG SendLength, 47 | _In_reads_bytes_(Length) PVOID Data, 48 | _In_ ULONG Length 49 | ); 50 | 51 | VOID 52 | SpbTargetDeinitialize( 53 | IN WDFDEVICE FxDevice, 54 | IN SPB_CONTEXT* SpbContext 55 | ); 56 | 57 | NTSTATUS 58 | SpbTargetInitialize( 59 | IN WDFDEVICE FxDevice, 60 | IN SPB_CONTEXT* SpbContext 61 | ); 62 | 63 | NTSTATUS 64 | SpbWriteDataSynchronously( 65 | IN SPB_CONTEXT* SpbContext, 66 | IN PVOID Data, 67 | IN ULONG Length 68 | ); 69 | 70 | typedef struct _SPB_BURST_INFO { 71 | PVOID Data; 72 | ULONG Length; 73 | } SPB_BURST_INFO; 74 | 75 | NTSTATUS 76 | SpbBurstWriteDataSynchronously( 77 | IN SPB_CONTEXT* SpbContext, 78 | IN SPB_BURST_INFO* Data, 79 | IN ULONG Count 80 | ); -------------------------------------------------------------------------------- /rt5682s/rt5682s.inf: -------------------------------------------------------------------------------- 1 | ;/*++ 2 | ; 3 | ;Copyright (c) CoolStar. All rights reserved. 4 | ; 5 | ;Module Name: 6 | ; coolstar.inf 7 | ; 8 | ;Abstract: 9 | ; INF file for installing the RT5682s Jack Detect Driver 10 | ; 11 | ; 12 | ;--*/ 13 | 14 | [Version] 15 | Signature = "$WINDOWS NT$" 16 | Class = Media 17 | ClassGuid = {4d36e96c-e325-11ce-bfc1-08002be10318} 18 | Provider = CoolStar 19 | DriverVer = 12/16/2021,1.0.0 20 | CatalogFile = rt5682s.cat 21 | PnpLockdown=1 22 | 23 | [DestinationDirs] 24 | DefaultDestDir = 12 25 | 26 | ; ================= Class section ===================== 27 | 28 | [SourceDisksNames] 29 | 1 = %DiskId1%,,,"" 30 | 31 | [SourceDisksFiles] 32 | rt5682s.sys = 1,, 33 | 34 | ;***************************************** 35 | ; rt5682s Install Section 36 | ;***************************************** 37 | 38 | [Manufacturer] 39 | %StdMfg%=Standard,NTAMD64 40 | 41 | ; Decorated model section take precedence over undecorated 42 | ; ones on XP and later. 43 | [Standard.NTAMD64] 44 | %rt5682s.DeviceDesc%=Rt5682s_Device, ACPI\RTL5682 45 | 46 | [Rt5682s_Device.NT] 47 | CopyFiles=Drivers_Dir 48 | 49 | [Rt5682s_Device.NT.HW] 50 | AddReg=Rt5682s_AddReg, Rt5682s_AddReg.Configuration.AddReg 51 | Include=pci.inf 52 | Needs=PciD3ColdSupported.HW 53 | 54 | [Drivers_Dir] 55 | rt5682s.sys 56 | 57 | [Rt5682s_AddReg] 58 | ; Set to 1 to connect the first interrupt resource found, 0 to leave disconnected 59 | HKR,Settings,"ConnectInterrupt",0x00010001,0 60 | HKR,,"UpperFilters",0x00010000,"mshidkmdf" 61 | 62 | [Rt5682s_AddReg.Configuration.AddReg] 63 | HKR,,"EnhancedPowerManagementEnabled",0x00010001,1 64 | 65 | ;-------------- Service installation 66 | [Rt5682s_Device.NT.Services] 67 | AddService = rt5682s,%SPSVCINST_ASSOCSERVICE%, Rt5682s_Service_Inst 68 | 69 | ; -------------- rt5682s driver install sections 70 | [Rt5682s_Service_Inst] 71 | DisplayName = %rt5682s.SVCDESC% 72 | ServiceType = 1 ; SERVICE_KERNEL_DRIVER 73 | StartType = 3 ; SERVICE_DEMAND_START 74 | ErrorControl = 1 ; SERVICE_ERROR_NORMAL 75 | ServiceBinary = %12%\rt5682s.sys 76 | LoadOrderGroup = Base 77 | 78 | [Strings] 79 | SPSVCINST_ASSOCSERVICE= 0x00000002 80 | StdMfg = "CoolStar" 81 | DiskId1 = "ALC5682s Installation Disk #1" 82 | rt5682s.DeviceDesc = "Realtek ALC5682s I2S Audio" 83 | rt5682s.SVCDESC = "ALC5682s Service" 84 | -------------------------------------------------------------------------------- /rt5682s.sln: -------------------------------------------------------------------------------- 1 | 2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.31829.152 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "rt5682s", "rt5682s\rt5682s.vcxproj", "{36580C07-EDC3-4C2B-B45F-6AB017E01A5D}" 7 | EndProject 8 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "rt5682s Package", "rt5682s Package\rt5682s Package.vcxproj", "{3DAE7ED3-003A-4495-8352-3D7B5B5D846F}" 9 | ProjectSection(ProjectDependencies) = postProject 10 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} = {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} 11 | EndProjectSection 12 | EndProject 13 | Global 14 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 15 | Debug|Win32 = Debug|Win32 16 | Debug|x64 = Debug|x64 17 | Release|Win32 = Release|Win32 18 | Release|x64 = Release|x64 19 | EndGlobalSection 20 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 21 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.ActiveCfg = Debug|Win32 22 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.Build.0 = Debug|Win32 23 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|Win32.Deploy.0 = Debug|Win32 24 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.ActiveCfg = Debug|x64 25 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.Build.0 = Debug|x64 26 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Debug|x64.Deploy.0 = Debug|x64 27 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.ActiveCfg = Release|Win32 28 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.Build.0 = Release|Win32 29 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|Win32.Deploy.0 = Release|Win32 30 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.ActiveCfg = Release|x64 31 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.Build.0 = Release|x64 32 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D}.Release|x64.Deploy.0 = Release|x64 33 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.ActiveCfg = Debug|Win32 34 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.Build.0 = Debug|Win32 35 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|Win32.Deploy.0 = Debug|Win32 36 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.ActiveCfg = Debug|x64 37 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.Build.0 = Debug|x64 38 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Debug|x64.Deploy.0 = Debug|x64 39 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.ActiveCfg = Release|Win32 40 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.Build.0 = Release|Win32 41 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|Win32.Deploy.0 = Release|Win32 42 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.ActiveCfg = Release|x64 43 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.Build.0 = Release|x64 44 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F}.Release|x64.Deploy.0 = Release|x64 45 | EndGlobalSection 46 | GlobalSection(SolutionProperties) = preSolution 47 | HideSolutionNode = FALSE 48 | EndGlobalSection 49 | GlobalSection(ExtensibilityGlobals) = postSolution 50 | SolutionGuid = {1EBAC2E3-504A-4D97-960C-BBD6F6AFBEC6} 51 | EndGlobalSection 52 | EndGlobal 53 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | Copyright 2021 CoolStar 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | 15 | 16 | ====================== Windows Driver Samples License ====================== 17 | 18 | The Microsoft Public License (MS-PL) 19 | Copyright (c) 2015 Microsoft 20 | 21 | This license governs use of the accompanying software. If you use the software, you 22 | accept this license. If you do not accept the license, do not use the software. 23 | 24 | 1. Definitions 25 | The terms "reproduce," "reproduction," "derivative works," and "distribution" have the 26 | same meaning here as under U.S. copyright law. 27 | A "contribution" is the original software, or any additions or changes to the software. 28 | A "contributor" is any person that distributes its contribution under this license. 29 | "Licensed patents" are a contributor's patent claims that read directly on its contribution. 30 | 31 | 2. Grant of Rights 32 | (A) Copyright Grant- Subject to the terms of this license, including the license conditions and limitations in section 3, each contributor grants you a non-exclusive, worldwide, royalty-free copyright license to reproduce its contribution, prepare derivative works of its contribution, and distribute its contribution or any derivative works that you create. 33 | (B) Patent Grant- Subject to the terms of this license, including the license conditions and limitations in section 3, each contributor grants you a non-exclusive, worldwide, royalty-free license under its licensed patents to make, have made, use, sell, offer for sale, import, and/or otherwise dispose of its contribution in the software or derivative works of the contribution in the software. 34 | 35 | 3. Conditions and Limitations 36 | (A) No Trademark License- This license does not grant you rights to use any contributors' name, logo, or trademarks. 37 | (B) If you bring a patent claim against any contributor over patents that you claim are infringed by the software, your patent license from such contributor to the software ends automatically. 38 | (C) If you distribute any portion of the software, you must retain all copyright, patent, trademark, and attribution notices that are present in the software. 39 | (D) If you distribute any portion of the software in source code form, you may do so only under this license by including a complete copy of this license with your distribution. If you distribute any portion of the software in compiled or object code form, you may only do so under a license that complies with this license. 40 | (E) The software is licensed "as-is." You bear the risk of using it. The contributors give no express warranties, guarantees or conditions. You may have additional consumer rights under your local laws which this license cannot change. To the extent permitted under your local laws, the contributors exclude the implied warranties of merchantability, fitness for a particular purpose and non-infringement. -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ## Ignore Visual Studio temporary files, build results, and 2 | ## files generated by popular Visual Studio add-ons. 3 | ## 4 | ## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore 5 | 6 | # User-specific files 7 | *.rsuser 8 | *.suo 9 | *.user 10 | *.userosscache 11 | *.sln.docstates 12 | 13 | # User-specific files (MonoDevelop/Xamarin Studio) 14 | *.userprefs 15 | 16 | # Build results 17 | [Dd]ebug/ 18 | [Dd]ebugPublic/ 19 | [Rr]elease/ 20 | [Rr]eleases/ 21 | x64/ 22 | x86/ 23 | bld/ 24 | [Bb]in/ 25 | [Oo]bj/ 26 | [Ll]og/ 27 | 28 | # Visual Studio 2015/2017 cache/options directory 29 | .vs/ 30 | # Uncomment if you have tasks that create the project's static files in wwwroot 31 | #wwwroot/ 32 | 33 | # Visual Studio 2017 auto generated files 34 | Generated\ Files/ 35 | 36 | # MSTest test Results 37 | [Tt]est[Rr]esult*/ 38 | [Bb]uild[Ll]og.* 39 | 40 | # NUNIT 41 | *.VisualState.xml 42 | TestResult.xml 43 | 44 | # Build Results of an ATL Project 45 | [Dd]ebugPS/ 46 | [Rr]eleasePS/ 47 | dlldata.c 48 | 49 | # Benchmark Results 50 | BenchmarkDotNet.Artifacts/ 51 | 52 | # .NET Core 53 | project.lock.json 54 | project.fragment.lock.json 55 | artifacts/ 56 | 57 | # StyleCop 58 | StyleCopReport.xml 59 | 60 | # Files built by Visual Studio 61 | *_i.c 62 | *_p.c 63 | *_h.h 64 | *.ilk 65 | *.meta 66 | *.obj 67 | *.iobj 68 | *.pch 69 | *.pdb 70 | *.ipdb 71 | *.pgc 72 | *.pgd 73 | *.rsp 74 | *.sbr 75 | *.tlb 76 | *.tli 77 | *.tlh 78 | *.tmp 79 | *.tmp_proj 80 | *_wpftmp.csproj 81 | *.log 82 | *.vspscc 83 | *.vssscc 84 | .builds 85 | *.pidb 86 | *.svclog 87 | *.scc 88 | 89 | # Chutzpah Test files 90 | _Chutzpah* 91 | 92 | # Visual C++ cache files 93 | ipch/ 94 | *.aps 95 | *.ncb 96 | *.opendb 97 | *.opensdf 98 | *.sdf 99 | *.cachefile 100 | *.VC.db 101 | *.VC.VC.opendb 102 | 103 | # Visual Studio profiler 104 | *.psess 105 | *.vsp 106 | *.vspx 107 | *.sap 108 | 109 | # Visual Studio Trace Files 110 | *.e2e 111 | 112 | # TFS 2012 Local Workspace 113 | $tf/ 114 | 115 | # Guidance Automation Toolkit 116 | *.gpState 117 | 118 | # ReSharper is a .NET coding add-in 119 | _ReSharper*/ 120 | *.[Rr]e[Ss]harper 121 | *.DotSettings.user 122 | 123 | # JustCode is a .NET coding add-in 124 | .JustCode 125 | 126 | # TeamCity is a build add-in 127 | _TeamCity* 128 | 129 | # DotCover is a Code Coverage Tool 130 | *.dotCover 131 | 132 | # AxoCover is a Code Coverage Tool 133 | .axoCover/* 134 | !.axoCover/settings.json 135 | 136 | # Visual Studio code coverage results 137 | *.coverage 138 | *.coveragexml 139 | 140 | # NCrunch 141 | _NCrunch_* 142 | .*crunch*.local.xml 143 | nCrunchTemp_* 144 | 145 | # MightyMoose 146 | *.mm.* 147 | AutoTest.Net/ 148 | 149 | # Web workbench (sass) 150 | .sass-cache/ 151 | 152 | # Installshield output folder 153 | [Ee]xpress/ 154 | 155 | # DocProject is a documentation generator add-in 156 | DocProject/buildhelp/ 157 | DocProject/Help/*.HxT 158 | DocProject/Help/*.HxC 159 | DocProject/Help/*.hhc 160 | DocProject/Help/*.hhk 161 | DocProject/Help/*.hhp 162 | DocProject/Help/Html2 163 | DocProject/Help/html 164 | 165 | # Click-Once directory 166 | publish/ 167 | 168 | # Publish Web Output 169 | *.[Pp]ublish.xml 170 | *.azurePubxml 171 | # Note: Comment the next line if you want to checkin your web deploy settings, 172 | # but database connection strings (with potential passwords) will be unencrypted 173 | *.pubxml 174 | *.publishproj 175 | 176 | # Microsoft Azure Web App publish settings. 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Backup files are not needed, 238 | # because we have git ;-) 239 | _UpgradeReport_Files/ 240 | Backup*/ 241 | UpgradeLog*.XML 242 | UpgradeLog*.htm 243 | ServiceFabricBackup/ 244 | *.rptproj.bak 245 | 246 | # SQL Server files 247 | *.mdf 248 | *.ldf 249 | *.ndf 250 | 251 | # Business Intelligence projects 252 | *.rdl.data 253 | *.bim.layout 254 | *.bim_*.settings 255 | *.rptproj.rsuser 256 | 257 | # Microsoft Fakes 258 | FakesAssemblies/ 259 | 260 | # GhostDoc plugin setting file 261 | *.GhostDoc.xml 262 | 263 | # Node.js Tools for Visual Studio 264 | .ntvs_analysis.dat 265 | node_modules/ 266 | 267 | # Visual Studio 6 build log 268 | *.plg 269 | 270 | # Visual Studio 6 workspace options file 271 | *.opt 272 | 273 | # Visual Studio 6 auto-generated workspace file (contains which files were open etc.) 274 | *.vbw 275 | 276 | # Visual Studio LightSwitch build output 277 | **/*.HTMLClient/GeneratedArtifacts 278 | **/*.DesktopClient/GeneratedArtifacts 279 | **/*.DesktopClient/ModelManifest.xml 280 | **/*.Server/GeneratedArtifacts 281 | **/*.Server/ModelManifest.xml 282 | _Pvt_Extensions 283 | 284 | # Paket dependency manager 285 | .paket/paket.exe 286 | paket-files/ 287 | 288 | # FAKE - F# Make 289 | .fake/ 290 | 291 | # JetBrains Rider 292 | .idea/ 293 | *.sln.iml 294 | 295 | # CodeRush personal settings 296 | .cr/personal 297 | 298 | # Python Tools for Visual Studio (PTVS) 299 | __pycache__/ 300 | *.pyc 301 | 302 | # Cake - Uncomment if you are using it 303 | # tools/** 304 | # !tools/packages.config 305 | 306 | # Tabs Studio 307 | *.tss 308 | 309 | # Telerik's JustMock configuration file 310 | *.jmconfig 311 | 312 | # BizTalk build output 313 | *.btp.cs 314 | *.btm.cs 315 | *.odx.cs 316 | *.xsd.cs 317 | 318 | # OpenCover UI analysis results 319 | OpenCover/ 320 | 321 | # Azure Stream Analytics local run output 322 | ASALocalRun/ 323 | 324 | # MSBuild Binary and Structured Log 325 | *.binlog 326 | 327 | # NVidia Nsight GPU debugger configuration file 328 | *.nvuser 329 | 330 | # MFractors (Xamarin productivity tool) working folder 331 | .mfractor/ 332 | 333 | # Local History for Visual Studio 334 | .localhistory/ 335 | -------------------------------------------------------------------------------- /rt5682s Package/rt5682s Package.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {3DAE7ED3-003A-4495-8352-3D7B5B5D846F} 23 | {4605da2c-74a5-4865-98e1-152ef136825f} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | rt5682s_Package 29 | $(LatestTargetPlatformVersion) 30 | 31 | 32 | 33 | Windows10 34 | true 35 | WindowsKernelModeDriver10.0 36 | Utility 37 | Package 38 | true 39 | 40 | 41 | Windows10 42 | false 43 | WindowsKernelModeDriver10.0 44 | Utility 45 | Package 46 | true 47 | 48 | 49 | Windows10 50 | true 51 | WindowsKernelModeDriver10.0 52 | Utility 53 | Package 54 | true 55 | 56 | 57 | Windows10 58 | false 59 | WindowsKernelModeDriver10.0 60 | Utility 61 | Package 62 | true 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | DbgengKernelDebugger 74 | False 75 | True 76 | 77 | 78 | 79 | False 80 | False 81 | True 82 | 83 | 133563 84 | 85 | 86 | DbgengKernelDebugger 87 | False 88 | True 89 | 90 | 91 | 92 | False 93 | False 94 | True 95 | 96 | 133563 97 | 98 | 99 | DbgengKernelDebugger 100 | False 101 | True 102 | 103 | 104 | 105 | False 106 | False 107 | True 108 | 109 | 133563 110 | 111 | 112 | DbgengKernelDebugger 113 | False 114 | True 115 | 116 | 117 | 118 | False 119 | False 120 | True 121 | 122 | 133563 123 | 124 | 125 | 126 | SHA256 127 | 128 | 129 | 130 | 131 | SHA256 132 | 133 | 134 | 135 | 136 | SHA256 137 | 138 | 139 | 140 | 141 | SHA256 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | {36580c07-edc3-4c2b-b45f-6ab017e01a5d} 150 | 151 | 152 | 153 | 154 | 155 | -------------------------------------------------------------------------------- /rt5682s/rt5682s.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {36580C07-EDC3-4C2B-B45F-6AB017E01A5D} 23 | {1bc93793-694f-48fe-9372-81e2b05556fd} 24 | v4.5 25 | 11.0 26 | Win8.1 Debug 27 | Win32 28 | rt5682s 29 | $(LatestTargetPlatformVersion) 30 | 31 | 32 | 33 | Windows10 34 | true 35 | WindowsKernelModeDriver10.0 36 | Driver 37 | KMDF 38 | 39 | 40 | Windows10 41 | false 42 | WindowsKernelModeDriver10.0 43 | Driver 44 | KMDF 45 | 46 | 47 | Windows10 48 | true 49 | WindowsKernelModeDriver10.0 50 | Driver 51 | KMDF 52 | 53 | 54 | Windows10 55 | false 56 | WindowsKernelModeDriver10.0 57 | Driver 58 | KMDF 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | DbgengKernelDebugger 70 | 71 | 72 | DbgengKernelDebugger 73 | 74 | 75 | DbgengKernelDebugger 76 | 77 | 78 | DbgengKernelDebugger 79 | 80 | 81 | 82 | true 83 | trace.h 84 | true 85 | false 86 | 87 | 88 | 1.0.1 89 | 90 | 91 | SHA256 92 | 93 | 94 | 95 | 96 | true 97 | trace.h 98 | true 99 | false 100 | 101 | 102 | 1.0.1 103 | 104 | 105 | SHA256 106 | 107 | 108 | 109 | 110 | true 111 | trace.h 112 | true 113 | false 114 | 115 | 116 | 1.0.1 117 | 118 | 119 | SHA256 120 | 121 | 122 | 123 | 124 | true 125 | trace.h 126 | true 127 | false 128 | 129 | 130 | 1.0.1 131 | 132 | 133 | SHA256 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | -------------------------------------------------------------------------------- /rt5682s/rt5682s.h: -------------------------------------------------------------------------------- 1 | #if !defined(_RT5682_H_) 2 | #define _RT5682_H_ 3 | 4 | #pragma warning(disable:4200) // suppress nameless struct/union warning 5 | #pragma warning(disable:4201) // suppress nameless struct/union warning 6 | #pragma warning(disable:4214) // suppress bit field types other than int warning 7 | #include 8 | #include 9 | 10 | #pragma warning(default:4200) 11 | #pragma warning(default:4201) 12 | #pragma warning(default:4214) 13 | #include 14 | 15 | #pragma warning(disable:4201) // suppress nameless struct/union warning 16 | #pragma warning(disable:4214) // suppress bit field types other than int warning 17 | #include 18 | 19 | #include "hidcommon.h" 20 | #include "spb.h" 21 | #include 22 | 23 | #define true 1 24 | #define false 0 25 | 26 | typedef enum { 27 | CSAudioEndpointTypeDSP, 28 | CSAudioEndpointTypeSpeaker, 29 | CSAudioEndpointTypeHeadphone, 30 | CSAudioEndpointTypeMicArray, 31 | CSAudioEndpointTypeMicJack 32 | } CSAudioEndpointType; 33 | 34 | typedef enum { 35 | CSAudioEndpointRegister, 36 | CSAudioEndpointStart, 37 | CSAudioEndpointStop, 38 | CSAudioEndpointOverrideFormat, 39 | CSAudioEndpointI2SParameters 40 | } CSAudioEndpointRequest; 41 | 42 | typedef struct CSAUDIOFORMATOVERRIDE { 43 | UINT16 channels; 44 | UINT16 frequency; 45 | UINT16 bitsPerSample; 46 | UINT16 validBitsPerSample; 47 | BOOLEAN force32BitOutputContainer; 48 | } CsAudioFormatOverride; 49 | 50 | typedef struct CSAUDIOI2SPARAMS { 51 | UINT32 version; 52 | 53 | UINT32 mclk; 54 | UINT32 bclk_rate; 55 | UINT32 frequency; 56 | UINT32 tdm_slots; 57 | UINT32 tdm_slot_width; 58 | UINT32 rx_slots; 59 | UINT32 tx_slots; 60 | UINT32 valid_bits; //end of version 1 61 | } CsAudioI2SParameters; 62 | 63 | typedef struct CSAUDIOARG { 64 | UINT32 argSz; 65 | CSAudioEndpointType endpointType; 66 | CSAudioEndpointRequest endpointRequest; 67 | union { 68 | CsAudioFormatOverride formatOverride; 69 | CsAudioI2SParameters i2sParameters; 70 | }; 71 | } CsAudioArg, * PCsAudioArg; 72 | 73 | typedef enum platform { 74 | PlatformNone, 75 | PlatformRyzenDali, 76 | PlatformRyzenCezanne, 77 | PlatformRyzenMendocino, 78 | PlatformGeminiLake, 79 | PlatformTigerLake 80 | } Platform; 81 | 82 | enum snd_jack_types { 83 | SND_JACK_HEADPHONE = 0x0001, 84 | SND_JACK_MICROPHONE = 0x0002, 85 | SND_JACK_HEADSET = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE, 86 | }; 87 | 88 | struct reg { 89 | UINT16 reg; 90 | UINT16 val; 91 | }; 92 | 93 | // 94 | // String definitions 95 | // 96 | 97 | #define DRIVERNAME "rt5682.sys: " 98 | 99 | #define RT5682_POOL_TAG (ULONG) '856R' 100 | 101 | typedef UCHAR HID_REPORT_DESCRIPTOR, *PHID_REPORT_DESCRIPTOR; 102 | 103 | #ifdef DESCRIPTOR_DEF 104 | HID_REPORT_DESCRIPTOR DefaultReportDescriptor[] = { 105 | // 106 | // Consumer Control starts here 107 | // 108 | 0x05, 0x0C, /* Usage Page (Consumer Devices) */ 109 | 0x09, 0x01, /* Usage (Consumer Control) */ 110 | 0xA1, 0x01, /* Collection (Application) */ 111 | 0x85, REPORTID_MEDIA, /* Report ID=1 */ 112 | 0x05, 0x0C, /* Usage Page (Consumer Devices) */ 113 | 0x15, 0x00, /* Logical Minimum (0) */ 114 | 0x25, 0x01, /* Logical Maximum (1) */ 115 | 0x75, 0x01, /* Report Size (1) */ 116 | 0x95, 0x04, /* Report Count (4) */ 117 | 0x09, 0xCD, /* Usage (Play / Pause) */ 118 | 0x09, 0xCF, /* Usage (Voice Command) */ 119 | 0x09, 0xE9, /* Usage (Volume Up) */ 120 | 0x09, 0xEA, /* Usage (Volume Down) */ 121 | 0x81, 0x02, /* Input (Data, Variable, Absolute) */ 122 | 0x95, 0x04, /* Report Count (4) */ 123 | 0x81, 0x01, /* Input (Constant) */ 124 | 0xC0, /* End Collection */ 125 | 126 | 0x06, 0x00, 0xff, // USAGE_PAGE (Vendor Defined Page 1) 127 | 0x09, 0x04, // USAGE (Vendor Usage 4) 128 | 0xa1, 0x01, // COLLECTION (Application) 129 | 0x85, REPORTID_SPECKEYS, // REPORT_ID (Special Keys) 130 | 0x15, 0x00, // LOGICAL_MINIMUM (0) 131 | 0x26, 0xff, 0x00, // LOGICAL_MAXIMUM (256) 132 | 0x75, 0x08, // REPORT_SIZE (8) - bits 133 | 0x95, 0x01, // REPORT_COUNT (1) - Bytes 134 | 0x09, 0x02, // USAGE (Vendor Usage 1) 135 | 0x81, 0x02, // INPUT (Data,Var,Abs) 136 | 0x09, 0x03, // USAGE (Vendor Usage 2) 137 | 0x81, 0x02, // INPUT (Data,Var,Abs) 138 | 0x09, 0x02, // USAGE (Vendor Usage 1) 139 | 0x91, 0x02, // OUTPUT (Data,Var,Abs) 140 | 0xc0, // END_COLLECTION 141 | }; 142 | 143 | 144 | // 145 | // This is the default HID descriptor returned by the mini driver 146 | // in response to IOCTL_HID_GET_DEVICE_DESCRIPTOR. The size 147 | // of report descriptor is currently the size of DefaultReportDescriptor. 148 | // 149 | 150 | CONST HID_DESCRIPTOR DefaultHidDescriptor = { 151 | 0x09, // length of HID descriptor 152 | 0x21, // descriptor type == HID 0x21 153 | 0x0100, // hid spec release 154 | 0x00, // country code == Not Specified 155 | 0x01, // number of HID class descriptors 156 | { 0x22, // descriptor type 157 | sizeof(DefaultReportDescriptor) } // total length of report descriptor 158 | }; 159 | #endif 160 | 161 | typedef struct _RTEK_CONTEXT 162 | { 163 | 164 | WDFDEVICE FxDevice; 165 | 166 | WDFQUEUE ReportQueue; 167 | 168 | WDFQUEUE IdleQueue; 169 | 170 | SPB_CONTEXT I2CContext; 171 | 172 | WDFINTERRUPT Interrupt; 173 | 174 | BOOLEAN ConnectInterrupt; 175 | 176 | INT JackType; 177 | 178 | PCALLBACK_OBJECT CSAudioAPICallback; 179 | PVOID CSAudioAPICallbackObj; 180 | 181 | BOOLEAN CSAudioManaged; 182 | 183 | BOOLEAN HeadphonePlaying; 184 | 185 | BOOLEAN ReclockRequested; 186 | UINT32 mclk; 187 | UINT32 freq; 188 | UINT32 slotWidth; 189 | 190 | } RTEK_CONTEXT, *PRTEK_CONTEXT; 191 | 192 | WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(RTEK_CONTEXT, GetDeviceContext) 193 | 194 | // 195 | // Power Idle Workitem context 196 | // 197 | typedef struct _IDLE_WORKITEM_CONTEXT 198 | { 199 | // Handle to a WDF device object 200 | WDFDEVICE FxDevice; 201 | 202 | // Handle to a WDF request object 203 | WDFREQUEST FxRequest; 204 | 205 | } IDLE_WORKITEM_CONTEXT, * PIDLE_WORKITEM_CONTEXT; 206 | WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(IDLE_WORKITEM_CONTEXT, GetIdleWorkItemContext) 207 | 208 | // 209 | // Function definitions 210 | // 211 | 212 | DRIVER_INITIALIZE DriverEntry; 213 | 214 | EVT_WDF_DRIVER_UNLOAD Rt5682DriverUnload; 215 | 216 | EVT_WDF_DRIVER_DEVICE_ADD Rt5682EvtDeviceAdd; 217 | 218 | EVT_WDFDEVICE_WDM_IRP_PREPROCESS Rt5682EvtWdmPreprocessMnQueryId; 219 | 220 | EVT_WDF_IO_QUEUE_IO_INTERNAL_DEVICE_CONTROL Rt5682EvtInternalDeviceControl; 221 | 222 | NTSTATUS 223 | Rt5682GetHidDescriptor( 224 | IN WDFDEVICE Device, 225 | IN WDFREQUEST Request 226 | ); 227 | 228 | NTSTATUS 229 | Rt5682GetReportDescriptor( 230 | IN WDFDEVICE Device, 231 | IN WDFREQUEST Request 232 | ); 233 | 234 | NTSTATUS 235 | Rt5682GetDeviceAttributes( 236 | IN WDFREQUEST Request 237 | ); 238 | 239 | NTSTATUS 240 | Rt5682GetString( 241 | IN WDFREQUEST Request 242 | ); 243 | 244 | NTSTATUS 245 | Rt5682WriteReport( 246 | IN PRTEK_CONTEXT DevContext, 247 | IN WDFREQUEST Request 248 | ); 249 | 250 | NTSTATUS 251 | Rt5682ProcessVendorReport( 252 | IN PRTEK_CONTEXT DevContext, 253 | IN PVOID ReportBuffer, 254 | IN ULONG ReportBufferLen, 255 | OUT size_t* BytesWritten 256 | ); 257 | 258 | NTSTATUS 259 | Rt5682ReadReport( 260 | IN PRTEK_CONTEXT DevContext, 261 | IN WDFREQUEST Request, 262 | OUT BOOLEAN* CompleteRequest 263 | ); 264 | 265 | NTSTATUS 266 | Rt5682SetFeature( 267 | IN PRTEK_CONTEXT DevContext, 268 | IN WDFREQUEST Request, 269 | OUT BOOLEAN* CompleteRequest 270 | ); 271 | 272 | NTSTATUS 273 | Rt5682GetFeature( 274 | IN PRTEK_CONTEXT DevContext, 275 | IN WDFREQUEST Request, 276 | OUT BOOLEAN* CompleteRequest 277 | ); 278 | 279 | PCHAR 280 | DbgHidInternalIoctlString( 281 | IN ULONG IoControlCode 282 | ); 283 | 284 | VOID 285 | RtekCompleteIdleIrp( 286 | IN PRTEK_CONTEXT FxDeviceContext 287 | ); 288 | 289 | // 290 | // Helper macros 291 | // 292 | 293 | #define DEBUG_LEVEL_ERROR 1 294 | #define DEBUG_LEVEL_INFO 2 295 | #define DEBUG_LEVEL_VERBOSE 3 296 | 297 | #define DBG_INIT 1 298 | #define DBG_PNP 2 299 | #define DBG_IOCTL 4 300 | 301 | #if 0 302 | #define RtekPrint(dbglevel, dbgcatagory, fmt, ...) { \ 303 | if (Rt5682DebugLevel >= dbglevel && \ 304 | (Rt5682DebugCatagories && dbgcatagory)) \ 305 | { \ 306 | DbgPrint(DRIVERNAME); \ 307 | DbgPrint(fmt, __VA_ARGS__); \ 308 | } \ 309 | } 310 | #else 311 | #define RtekPrint(dbglevel, fmt, ...) { \ 312 | } 313 | #endif 314 | 315 | #endif -------------------------------------------------------------------------------- /rt5682s/spb.c: -------------------------------------------------------------------------------- 1 | /*++ 2 | Copyright (c) Microsoft Corporation. All Rights Reserved. 3 | Sample code. Dealpoint ID #843729. 4 | 5 | Module Name: 6 | 7 | spb.c 8 | 9 | Abstract: 10 | 11 | Contains all I2C-specific functionality 12 | 13 | Environment: 14 | 15 | Kernel mode 16 | 17 | Revision History: 18 | 19 | --*/ 20 | 21 | #include "rt5682s.h" 22 | #include "spb.h" 23 | #include 24 | #include 25 | 26 | static ULONG Rt5682DebugLevel = 100; 27 | static ULONG Rt5682DebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 28 | 29 | NTSTATUS 30 | SpbDoWriteDataSynchronously( 31 | IN SPB_CONTEXT* SpbContext, 32 | IN PVOID Data, 33 | IN ULONG Length 34 | ) 35 | /*++ 36 | 37 | Routine Description: 38 | 39 | This helper routine abstracts creating and sending an I/O 40 | request (I2C Write) to the Spb I/O target. 41 | 42 | Arguments: 43 | 44 | SpbContext - Pointer to the current device context 45 | Address - The I2C register address to write to 46 | Data - A buffer to receive the data at at the above address 47 | Length - The amount of data to be read from the above address 48 | 49 | Return Value: 50 | 51 | NTSTATUS Status indicating success or failure 52 | 53 | --*/ 54 | { 55 | PUCHAR buffer; 56 | ULONG length; 57 | WDFMEMORY memory; 58 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 59 | NTSTATUS status; 60 | 61 | length = Length; 62 | memory = NULL; 63 | 64 | if (length > DEFAULT_SPB_BUFFER_SIZE) 65 | { 66 | status = WdfMemoryCreate( 67 | WDF_NO_OBJECT_ATTRIBUTES, 68 | NonPagedPool, 69 | RT5682_POOL_TAG, 70 | length, 71 | &memory, 72 | (PVOID*)&buffer); 73 | 74 | if (!NT_SUCCESS(status)) 75 | { 76 | RtekPrint( 77 | DEBUG_LEVEL_ERROR, 78 | DBG_IOCTL, 79 | "Error allocating memory for Spb write - %!STATUS!", 80 | status); 81 | goto exit; 82 | } 83 | 84 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 85 | &memoryDescriptor, 86 | memory, 87 | NULL); 88 | } 89 | else 90 | { 91 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->WriteMemory, NULL); 92 | 93 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 94 | &memoryDescriptor, 95 | (PVOID)buffer, 96 | length); 97 | } 98 | 99 | RtlCopyMemory(buffer, Data, length); 100 | 101 | status = WdfIoTargetSendWriteSynchronously( 102 | SpbContext->SpbIoTarget, 103 | NULL, 104 | &memoryDescriptor, 105 | NULL, 106 | NULL, 107 | NULL); 108 | 109 | if (!NT_SUCCESS(status)) 110 | { 111 | RtekPrint( 112 | DEBUG_LEVEL_ERROR, 113 | DBG_IOCTL, 114 | "Error writing to Spb - %!STATUS!", 115 | status); 116 | goto exit; 117 | } 118 | 119 | exit: 120 | 121 | if (NULL != memory) 122 | { 123 | WdfObjectDelete(memory); 124 | } 125 | 126 | return status; 127 | } 128 | 129 | NTSTATUS 130 | SpbWriteDataSynchronously( 131 | IN SPB_CONTEXT* SpbContext, 132 | IN PVOID Data, 133 | IN ULONG Length 134 | ) 135 | /*++ 136 | 137 | Routine Description: 138 | 139 | This routine abstracts creating and sending an I/O 140 | request (I2C Write) to the Spb I/O target and utilizes 141 | a helper routine to do work inside of locked code. 142 | 143 | Arguments: 144 | 145 | SpbContext - Pointer to the current device context 146 | Address - The I2C register address to write to 147 | Data - A buffer to receive the data at at the above address 148 | Length - The amount of data to be read from the above address 149 | 150 | Return Value: 151 | 152 | NTSTATUS Status indicating success or failure 153 | 154 | --*/ 155 | { 156 | NTSTATUS status; 157 | 158 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 159 | 160 | status = SpbDoWriteDataSynchronously( 161 | SpbContext, 162 | Data, 163 | Length); 164 | 165 | WdfWaitLockRelease(SpbContext->SpbLock); 166 | 167 | return status; 168 | } 169 | 170 | NTSTATUS 171 | SpbBurstWriteDataSynchronously( 172 | IN SPB_CONTEXT* SpbContext, 173 | IN SPB_BURST_INFO* BurstInfo, 174 | IN ULONG Count 175 | ) 176 | { 177 | NTSTATUS status; 178 | 179 | typedef struct _SPB_TRANSFER { 180 | SPB_TRANSFER_LIST List; 181 | SPB_TRANSFER_LIST_ENTRY ExtraTransfers[]; 182 | } SPB_TRANSFER; 183 | 184 | size_t seq_size = sizeof(SPB_TRANSFER) + (sizeof(SPB_TRANSFER_LIST_ENTRY) * (Count - 1)); 185 | SPB_TRANSFER* seq = ExAllocatePoolWithTag(NonPagedPool, seq_size, RT5682_POOL_TAG); 186 | if (!seq) 187 | return STATUS_NO_MEMORY; 188 | 189 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 190 | 191 | SPB_TRANSFER_LIST_INIT(&(seq->List), Count); 192 | 193 | for (int i = 0; i < Count; i++) { 194 | SPB_BURST_INFO Info = BurstInfo[i]; 195 | 196 | seq->List.Transfers[i] = SPB_TRANSFER_LIST_ENTRY_INIT_SIMPLE( 197 | SpbTransferDirectionToDevice, 198 | 0, 199 | Info.Data, 200 | Info.Length); 201 | } 202 | 203 | WDF_MEMORY_DESCRIPTOR MemoryDescriptor; 204 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 205 | &MemoryDescriptor, 206 | seq, 207 | seq_size); 208 | ULONG_PTR BytesTransferred = 0; 209 | status = WdfIoTargetSendIoctlSynchronously( 210 | SpbContext->SpbIoTarget, 211 | NULL, 212 | IOCTL_SPB_EXECUTE_SEQUENCE, 213 | &MemoryDescriptor, 214 | NULL, 215 | NULL, 216 | &BytesTransferred 217 | ); 218 | 219 | WdfWaitLockRelease(SpbContext->SpbLock); 220 | 221 | exit: 222 | if (seq) 223 | ExFreePoolWithTag(seq, RT5682_POOL_TAG); 224 | return status; 225 | } 226 | 227 | NTSTATUS 228 | SpbXferDataSynchronously( 229 | _In_ SPB_CONTEXT* SpbContext, 230 | _In_ PVOID SendData, 231 | _In_ ULONG SendLength, 232 | _In_reads_bytes_(Length) PVOID Data, 233 | _In_ ULONG Length 234 | ) 235 | /*++ 236 | Routine Description: 237 | This helper routine abstracts creating and sending an I/O 238 | request (I2C Read) to the Spb I/O target. 239 | Arguments: 240 | SpbContext - Pointer to the current device context 241 | Address - The I2C register address to read from 242 | Data - A buffer to receive the data at at the above address 243 | Length - The amount of data to be read from the above address 244 | Return Value: 245 | NTSTATUS Status indicating success or failure 246 | --*/ 247 | { 248 | PUCHAR buffer; 249 | WDFMEMORY memory; 250 | WDF_MEMORY_DESCRIPTOR memoryDescriptor; 251 | NTSTATUS status; 252 | ULONG_PTR bytesRead; 253 | 254 | WdfWaitLockAcquire(SpbContext->SpbLock, NULL); 255 | 256 | memory = NULL; 257 | status = STATUS_INVALID_PARAMETER; 258 | bytesRead = 0; 259 | 260 | // 261 | // Xfer transactions start by writing an address pointer 262 | // 263 | status = SpbDoWriteDataSynchronously( 264 | SpbContext, 265 | SendData, 266 | SendLength); 267 | 268 | if (!NT_SUCCESS(status)) 269 | { 270 | RtekPrint( 271 | DEBUG_LEVEL_ERROR, 272 | DBG_IOCTL, 273 | "Error setting address pointer for Spb read - %!STATUS!", 274 | status); 275 | goto exit; 276 | } 277 | 278 | if (Length > DEFAULT_SPB_BUFFER_SIZE) 279 | { 280 | status = WdfMemoryCreate( 281 | WDF_NO_OBJECT_ATTRIBUTES, 282 | NonPagedPool, 283 | RT5682_POOL_TAG, 284 | Length, 285 | &memory, 286 | (PVOID*)&buffer); 287 | 288 | if (!NT_SUCCESS(status)) 289 | { 290 | RtekPrint( 291 | DEBUG_LEVEL_ERROR, 292 | DBG_IOCTL, 293 | "Error allocating memory for Spb read - %!STATUS!", 294 | status); 295 | goto exit; 296 | } 297 | 298 | WDF_MEMORY_DESCRIPTOR_INIT_HANDLE( 299 | &memoryDescriptor, 300 | memory, 301 | NULL); 302 | } 303 | else 304 | { 305 | buffer = (PUCHAR)WdfMemoryGetBuffer(SpbContext->ReadMemory, NULL); 306 | 307 | WDF_MEMORY_DESCRIPTOR_INIT_BUFFER( 308 | &memoryDescriptor, 309 | (PVOID)buffer, 310 | Length); 311 | } 312 | 313 | 314 | status = WdfIoTargetSendReadSynchronously( 315 | SpbContext->SpbIoTarget, 316 | NULL, 317 | &memoryDescriptor, 318 | NULL, 319 | NULL, 320 | &bytesRead); 321 | 322 | if (!NT_SUCCESS(status) || 323 | bytesRead != Length) 324 | { 325 | RtekPrint( 326 | DEBUG_LEVEL_ERROR, 327 | DBG_IOCTL, 328 | "Error reading from Spb - %!STATUS!", 329 | status); 330 | goto exit; 331 | } 332 | 333 | // 334 | // Copy back to the caller's buffer 335 | // 336 | RtlCopyMemory(Data, buffer, Length); 337 | 338 | exit: 339 | if (NULL != memory) 340 | { 341 | WdfObjectDelete(memory); 342 | } 343 | 344 | WdfWaitLockRelease(SpbContext->SpbLock); 345 | 346 | return status; 347 | } 348 | 349 | VOID 350 | SpbTargetDeinitialize( 351 | IN WDFDEVICE FxDevice, 352 | IN SPB_CONTEXT* SpbContext 353 | ) 354 | /*++ 355 | 356 | Routine Description: 357 | 358 | This helper routine is used to free any members added to the SPB_CONTEXT, 359 | note the SPB I/O target is parented to the device and will be 360 | closed and free'd when the device is removed. 361 | 362 | Arguments: 363 | 364 | FxDevice - Handle to the framework device object 365 | SpbContext - Pointer to the current device context 366 | 367 | Return Value: 368 | 369 | NTSTATUS Status indicating success or failure 370 | 371 | --*/ 372 | { 373 | UNREFERENCED_PARAMETER(FxDevice); 374 | UNREFERENCED_PARAMETER(SpbContext); 375 | 376 | // 377 | // Free any SPB_CONTEXT allocations here 378 | // 379 | if (SpbContext->SpbLock != NULL) 380 | { 381 | WdfObjectDelete(SpbContext->SpbLock); 382 | } 383 | 384 | if (SpbContext->ReadMemory != NULL) 385 | { 386 | WdfObjectDelete(SpbContext->ReadMemory); 387 | } 388 | 389 | if (SpbContext->WriteMemory != NULL) 390 | { 391 | WdfObjectDelete(SpbContext->WriteMemory); 392 | } 393 | } 394 | 395 | NTSTATUS 396 | SpbTargetInitialize( 397 | IN WDFDEVICE FxDevice, 398 | IN SPB_CONTEXT* SpbContext 399 | ) 400 | /*++ 401 | 402 | Routine Description: 403 | 404 | This helper routine opens the Spb I/O target and 405 | initializes a request object used for the lifetime 406 | of communication between this driver and Spb. 407 | 408 | Arguments: 409 | 410 | FxDevice - Handle to the framework device object 411 | SpbContext - Pointer to the current device context 412 | 413 | Return Value: 414 | 415 | NTSTATUS Status indicating success or failure 416 | 417 | --*/ 418 | { 419 | WDF_OBJECT_ATTRIBUTES objectAttributes; 420 | WDF_IO_TARGET_OPEN_PARAMS openParams; 421 | UNICODE_STRING spbDeviceName; 422 | WCHAR spbDeviceNameBuffer[RESOURCE_HUB_PATH_SIZE]; 423 | NTSTATUS status; 424 | 425 | WDF_OBJECT_ATTRIBUTES_INIT(&objectAttributes); 426 | objectAttributes.ParentObject = FxDevice; 427 | 428 | status = WdfIoTargetCreate( 429 | FxDevice, 430 | &objectAttributes, 431 | &SpbContext->SpbIoTarget); 432 | 433 | if (!NT_SUCCESS(status)) 434 | { 435 | RtekPrint( 436 | DEBUG_LEVEL_ERROR, 437 | DBG_IOCTL, 438 | "Error creating IoTarget object - %!STATUS!", 439 | status); 440 | 441 | WdfObjectDelete(SpbContext->SpbIoTarget); 442 | goto exit; 443 | } 444 | 445 | RtlInitEmptyUnicodeString( 446 | &spbDeviceName, 447 | spbDeviceNameBuffer, 448 | sizeof(spbDeviceNameBuffer)); 449 | 450 | status = RESOURCE_HUB_CREATE_PATH_FROM_ID( 451 | &spbDeviceName, 452 | SpbContext->I2cResHubId.LowPart, 453 | SpbContext->I2cResHubId.HighPart); 454 | 455 | if (!NT_SUCCESS(status)) 456 | { 457 | RtekPrint( 458 | DEBUG_LEVEL_ERROR, 459 | DBG_IOCTL, 460 | "Error creating Spb resource hub path string - %!STATUS!", 461 | status); 462 | goto exit; 463 | } 464 | 465 | WDF_IO_TARGET_OPEN_PARAMS_INIT_OPEN_BY_NAME( 466 | &openParams, 467 | &spbDeviceName, 468 | (GENERIC_READ | GENERIC_WRITE)); 469 | 470 | openParams.ShareAccess = 0; 471 | openParams.CreateDisposition = FILE_OPEN; 472 | openParams.FileAttributes = FILE_ATTRIBUTE_NORMAL; 473 | 474 | status = WdfIoTargetOpen(SpbContext->SpbIoTarget, &openParams); 475 | 476 | if (!NT_SUCCESS(status)) 477 | { 478 | RtekPrint( 479 | DEBUG_LEVEL_ERROR, 480 | DBG_IOCTL, 481 | "Error opening Spb target for communication - %!STATUS!", 482 | status); 483 | goto exit; 484 | } 485 | 486 | // 487 | // Allocate some fixed-size buffers from NonPagedPool for typical 488 | // Spb transaction sizes to avoid pool fragmentation in most cases 489 | // 490 | status = WdfMemoryCreate( 491 | WDF_NO_OBJECT_ATTRIBUTES, 492 | NonPagedPool, 493 | RT5682_POOL_TAG, 494 | DEFAULT_SPB_BUFFER_SIZE, 495 | &SpbContext->WriteMemory, 496 | NULL); 497 | 498 | if (!NT_SUCCESS(status)) 499 | { 500 | RtekPrint( 501 | DEBUG_LEVEL_ERROR, 502 | DBG_IOCTL, 503 | "Error allocating default memory for Spb write - %!STATUS!", 504 | status); 505 | goto exit; 506 | } 507 | 508 | status = WdfMemoryCreate( 509 | WDF_NO_OBJECT_ATTRIBUTES, 510 | NonPagedPool, 511 | RT5682_POOL_TAG, 512 | DEFAULT_SPB_BUFFER_SIZE, 513 | &SpbContext->ReadMemory, 514 | NULL); 515 | 516 | if (!NT_SUCCESS(status)) 517 | { 518 | RtekPrint( 519 | DEBUG_LEVEL_ERROR, 520 | DBG_IOCTL, 521 | "Error allocating default memory for Spb read - %!STATUS!", 522 | status); 523 | goto exit; 524 | } 525 | 526 | // 527 | // Allocate a waitlock to guard access to the default buffers 528 | // 529 | status = WdfWaitLockCreate( 530 | WDF_NO_OBJECT_ATTRIBUTES, 531 | &SpbContext->SpbLock); 532 | 533 | if (!NT_SUCCESS(status)) 534 | { 535 | RtekPrint( 536 | DEBUG_LEVEL_ERROR, 537 | DBG_IOCTL, 538 | "Error creating Spb Waitlock - %!STATUS!", 539 | status); 540 | goto exit; 541 | } 542 | 543 | exit: 544 | 545 | if (!NT_SUCCESS(status)) 546 | { 547 | SpbTargetDeinitialize(FxDevice, SpbContext); 548 | } 549 | 550 | return status; 551 | } -------------------------------------------------------------------------------- /rt5682s/registers.h: -------------------------------------------------------------------------------- 1 | #ifndef __RT5682S_H__ 2 | #define __RT5682S_H__ 3 | 4 | /* 5 | * RT5682S Registers Definition 6 | */ 7 | 8 | #define DEVICE_ID 0x6749 9 | 10 | /* Info */ 11 | #define RT5682S_RESET 0x0000 12 | #define RT5682S_VERSION_ID 0x00fd 13 | #define RT5682S_VENDOR_ID 0x00fe 14 | #define RT5682S_DEVICE_ID 0x00ff 15 | /* I/O - Output */ 16 | #define RT5682S_HP_CTRL_1 0x0002 17 | #define RT5682S_HP_CTRL_2 0x0003 18 | #define RT5682S_HPL_GAIN 0x0005 19 | #define RT5682S_HPR_GAIN 0x0006 20 | 21 | #define RT5682S_I2C_CTRL 0x0008 22 | 23 | /* I/O - Input */ 24 | #define RT5682S_CBJ_BST_CTRL 0x000b 25 | #define RT5682S_CBJ_DET_CTRL 0x000f 26 | #define RT5682S_CBJ_CTRL_1 0x0010 27 | #define RT5682S_CBJ_CTRL_2 0x0011 28 | #define RT5682S_CBJ_CTRL_3 0x0012 29 | #define RT5682S_CBJ_CTRL_4 0x0013 30 | #define RT5682S_CBJ_CTRL_5 0x0014 31 | #define RT5682S_CBJ_CTRL_6 0x0015 32 | #define RT5682S_CBJ_CTRL_7 0x0016 33 | #define RT5682S_CBJ_CTRL_8 0x0017 34 | /* I/O - ADC/DAC/DMIC */ 35 | #define RT5682S_DAC1_DIG_VOL 0x0019 36 | #define RT5682S_STO1_ADC_DIG_VOL 0x001c 37 | #define RT5682S_STO1_ADC_BOOST 0x001f 38 | #define RT5682S_HP_IMP_GAIN_1 0x0022 39 | #define RT5682S_HP_IMP_GAIN_2 0x0023 40 | /* Mixer - D-D */ 41 | #define RT5682S_SIDETONE_CTRL 0x0024 42 | #define RT5682S_STO1_ADC_MIXER 0x0026 43 | #define RT5682S_AD_DA_MIXER 0x0029 44 | #define RT5682S_STO1_DAC_MIXER 0x002a 45 | #define RT5682S_A_DAC1_MUX 0x002b 46 | #define RT5682S_DIG_INF2_DATA 0x0030 47 | /* Mixer - ADC */ 48 | #define RT5682S_REC_MIXER 0x003c 49 | #define RT5682S_CAL_REC 0x0044 50 | /* HP Analog Offset Control */ 51 | #define RT5682S_HP_ANA_OST_CTRL_1 0x004b 52 | #define RT5682S_HP_ANA_OST_CTRL_2 0x004c 53 | #define RT5682S_HP_ANA_OST_CTRL_3 0x004d 54 | /* Power */ 55 | #define RT5682S_PWR_DIG_1 0x0061 56 | #define RT5682S_PWR_DIG_2 0x0062 57 | #define RT5682S_PWR_ANLG_1 0x0063 58 | #define RT5682S_PWR_ANLG_2 0x0064 59 | #define RT5682S_PWR_ANLG_3 0x0065 60 | #define RT5682S_PWR_MIXER 0x0066 61 | 62 | #define RT5682S_MB_CTRL 0x0067 63 | #define RT5682S_CLK_GATE_TCON_1 0x0068 64 | #define RT5682S_CLK_GATE_TCON_2 0x0069 65 | #define RT5682S_CLK_GATE_TCON_3 0x006a 66 | /* Clock Detect */ 67 | #define RT5682S_CLK_DET 0x006b 68 | /* Filter Auto Reset */ 69 | #define RT5682S_RESET_LPF_CTRL 0x006c 70 | #define RT5682S_RESET_HPF_CTRL 0x006d 71 | /* DMIC */ 72 | #define RT5682S_DMIC_CTRL_1 0x006e 73 | #define RT5682S_LPF_AD_DMIC 0x006f 74 | /* Format - ADC/DAC */ 75 | #define RT5682S_I2S1_SDP 0x0070 76 | #define RT5682S_I2S2_SDP 0x0071 77 | #define RT5682S_ADDA_CLK_1 0x0073 78 | #define RT5682S_ADDA_CLK_2 0x0074 79 | #define RT5682S_I2S1_F_DIV_CTRL_1 0x0075 80 | #define RT5682S_I2S1_F_DIV_CTRL_2 0x0076 81 | /* Format - TDM Control */ 82 | #define RT5682S_TDM_CTRL 0x0079 83 | #define RT5682S_TDM_ADDA_CTRL_1 0x007a 84 | #define RT5682S_TDM_ADDA_CTRL_2 0x007b 85 | #define RT5682S_DATA_SEL_CTRL_1 0x007c 86 | #define RT5682S_TDM_TCON_CTRL_1 0x007e 87 | #define RT5682S_TDM_TCON_CTRL_2 0x007f 88 | /* Function - Analog */ 89 | #define RT5682S_GLB_CLK 0x0080 90 | #define RT5682S_PLL_TRACK_1 0x0083 91 | #define RT5682S_PLL_TRACK_2 0x0084 92 | #define RT5682S_PLL_TRACK_3 0x0085 93 | #define RT5682S_PLL_TRACK_4 0x0086 94 | #define RT5682S_PLL_TRACK_5 0x0087 95 | #define RT5682S_PLL_TRACK_6 0x0088 96 | #define RT5682S_PLL_TRACK_11 0x008c 97 | #define RT5682S_DEPOP_1 0x008e 98 | #define RT5682S_HP_CHARGE_PUMP_1 0x008f 99 | #define RT5682S_HP_CHARGE_PUMP_2 0x0091 100 | #define RT5682S_HP_CHARGE_PUMP_3 0x0092 101 | #define RT5682S_MICBIAS_1 0x0093 102 | #define RT5682S_MICBIAS_2 0x0094 103 | #define RT5682S_MICBIAS_3 0x0095 104 | 105 | #define RT5682S_PLL_TRACK_12 0x0096 106 | #define RT5682S_PLL_TRACK_14 0x0097 107 | #define RT5682S_PLL_CTRL_1 0x0098 108 | #define RT5682S_PLL_CTRL_2 0x0099 109 | #define RT5682S_PLL_CTRL_3 0x009a 110 | #define RT5682S_PLL_CTRL_4 0x009b 111 | #define RT5682S_PLL_CTRL_5 0x009c 112 | #define RT5682S_PLL_CTRL_6 0x009d 113 | #define RT5682S_PLL_CTRL_7 0x009e 114 | 115 | #define RT5682S_RC_CLK_CTRL 0x009f 116 | #define RT5682S_I2S2_M_CLK_CTRL_1 0x00a0 117 | #define RT5682S_I2S2_F_DIV_CTRL_1 0x00a3 118 | #define RT5682S_I2S2_F_DIV_CTRL_2 0x00a4 119 | 120 | #define RT5682S_IRQ_CTRL_1 0x00b6 121 | #define RT5682S_IRQ_CTRL_2 0x00b7 122 | #define RT5682S_IRQ_CTRL_3 0x00b8 123 | #define RT5682S_IRQ_CTRL_4 0x00b9 124 | #define RT5682S_INT_ST_1 0x00be 125 | #define RT5682S_GPIO_CTRL_1 0x00c0 126 | #define RT5682S_GPIO_CTRL_2 0x00c1 127 | #define RT5682S_GPIO_ST 0x00c2 128 | #define RT5682S_HP_AMP_DET_CTRL_1 0x00d0 129 | #define RT5682S_MID_HP_AMP_DET 0x00d2 130 | #define RT5682S_LOW_HP_AMP_DET 0x00d3 131 | #define RT5682S_DELAY_BUF_CTRL 0x00d4 132 | #define RT5682S_SV_ZCD_1 0x00d9 133 | #define RT5682S_SV_ZCD_2 0x00da 134 | #define RT5682S_IL_CMD_1 0x00db 135 | #define RT5682S_IL_CMD_2 0x00dc 136 | #define RT5682S_IL_CMD_3 0x00dd 137 | #define RT5682S_IL_CMD_4 0x00de 138 | #define RT5682S_IL_CMD_5 0x00df 139 | #define RT5682S_IL_CMD_6 0x00e0 140 | #define RT5682S_4BTN_IL_CMD_1 0x00e2 141 | #define RT5682S_4BTN_IL_CMD_2 0x00e3 142 | #define RT5682S_4BTN_IL_CMD_3 0x00e4 143 | #define RT5682S_4BTN_IL_CMD_4 0x00e5 144 | #define RT5682S_4BTN_IL_CMD_5 0x00e6 145 | #define RT5682S_4BTN_IL_CMD_6 0x00e7 146 | #define RT5682S_4BTN_IL_CMD_7 0x00e8 147 | 148 | #define RT5682S_ADC_STO1_HP_CTRL_1 0x00ea 149 | #define RT5682S_ADC_STO1_HP_CTRL_2 0x00eb 150 | #define RT5682S_AJD1_CTRL 0x00f0 151 | #define RT5682S_JD_CTRL_1 0x00f6 152 | /* General Control */ 153 | #define RT5682S_DUMMY_1 0x00fa 154 | #define RT5682S_DUMMY_2 0x00fb 155 | #define RT5682S_DUMMY_3 0x00fc 156 | 157 | #define RT5682S_DAC_ADC_DIG_VOL1 0x0100 158 | #define RT5682S_BIAS_CUR_CTRL_2 0x010b 159 | #define RT5682S_BIAS_CUR_CTRL_3 0x010c 160 | #define RT5682S_BIAS_CUR_CTRL_4 0x010d 161 | #define RT5682S_BIAS_CUR_CTRL_5 0x010e 162 | #define RT5682S_BIAS_CUR_CTRL_6 0x010f 163 | #define RT5682S_BIAS_CUR_CTRL_7 0x0110 164 | #define RT5682S_BIAS_CUR_CTRL_8 0x0111 165 | #define RT5682S_BIAS_CUR_CTRL_9 0x0112 166 | #define RT5682S_BIAS_CUR_CTRL_10 0x0113 167 | #define RT5682S_VREF_REC_OP_FB_CAP_CTRL_1 0x0117 168 | #define RT5682S_VREF_REC_OP_FB_CAP_CTRL_2 0x0118 169 | #define RT5682S_CHARGE_PUMP_1 0x0125 170 | #define RT5682S_DIG_IN_CTRL_1 0x0132 171 | #define RT5682S_PAD_DRIVING_CTRL 0x0136 172 | #define RT5682S_CHOP_DAC_1 0x0139 173 | #define RT5682S_CHOP_DAC_2 0x013a 174 | #define RT5682S_CHOP_ADC 0x013b 175 | #define RT5682S_CALIB_ADC_CTRL 0x013c 176 | #define RT5682S_VOL_TEST 0x013f 177 | #define RT5682S_SPKVDD_DET_ST 0x0142 178 | #define RT5682S_TEST_MODE_CTRL_1 0x0145 179 | #define RT5682S_TEST_MODE_CTRL_2 0x0146 180 | #define RT5682S_TEST_MODE_CTRL_3 0x0147 181 | #define RT5682S_TEST_MODE_CTRL_4 0x0148 182 | #define RT5682S_PLL_INTERNAL_1 0x0156 183 | #define RT5682S_PLL_INTERNAL_2 0x0157 184 | #define RT5682S_PLL_INTERNAL_3 0x0158 185 | #define RT5682S_PLL_INTERNAL_4 0x0159 186 | #define RT5682S_STO_NG2_CTRL_1 0x0160 187 | #define RT5682S_STO_NG2_CTRL_2 0x0161 188 | #define RT5682S_STO_NG2_CTRL_3 0x0162 189 | #define RT5682S_STO_NG2_CTRL_4 0x0163 190 | #define RT5682S_STO_NG2_CTRL_5 0x0164 191 | #define RT5682S_STO_NG2_CTRL_6 0x0165 192 | #define RT5682S_STO_NG2_CTRL_7 0x0166 193 | #define RT5682S_STO_NG2_CTRL_8 0x0167 194 | #define RT5682S_STO_NG2_CTRL_9 0x0168 195 | #define RT5682S_STO_NG2_CTRL_10 0x0169 196 | #define RT5682S_STO1_DAC_SIL_DET 0x0190 197 | #define RT5682S_SIL_PSV_CTRL1 0x0194 198 | #define RT5682S_SIL_PSV_CTRL2 0x0195 199 | #define RT5682S_SIL_PSV_CTRL3 0x0197 200 | #define RT5682S_SIL_PSV_CTRL4 0x0198 201 | #define RT5682S_SIL_PSV_CTRL5 0x0199 202 | #define RT5682S_HP_IMP_SENS_CTRL_1 0x01ac 203 | #define RT5682S_HP_IMP_SENS_CTRL_2 0x01ad 204 | #define RT5682S_HP_IMP_SENS_CTRL_3 0x01ae 205 | #define RT5682S_HP_IMP_SENS_CTRL_4 0x01af 206 | #define RT5682S_HP_IMP_SENS_CTRL_5 0x01b0 207 | #define RT5682S_HP_IMP_SENS_CTRL_6 0x01b1 208 | #define RT5682S_HP_IMP_SENS_CTRL_7 0x01b2 209 | #define RT5682S_HP_IMP_SENS_CTRL_8 0x01b3 210 | #define RT5682S_HP_IMP_SENS_CTRL_9 0x01b4 211 | #define RT5682S_HP_IMP_SENS_CTRL_10 0x01b5 212 | #define RT5682S_HP_IMP_SENS_CTRL_11 0x01b6 213 | #define RT5682S_HP_IMP_SENS_CTRL_12 0x01b7 214 | #define RT5682S_HP_IMP_SENS_CTRL_13 0x01b8 215 | #define RT5682S_HP_IMP_SENS_CTRL_14 0x01b9 216 | #define RT5682S_HP_IMP_SENS_CTRL_15 0x01ba 217 | #define RT5682S_HP_IMP_SENS_CTRL_16 0x01bb 218 | #define RT5682S_HP_IMP_SENS_CTRL_17 0x01bc 219 | #define RT5682S_HP_IMP_SENS_CTRL_18 0x01bd 220 | #define RT5682S_HP_IMP_SENS_CTRL_19 0x01be 221 | #define RT5682S_HP_IMP_SENS_CTRL_20 0x01bf 222 | #define RT5682S_HP_IMP_SENS_CTRL_21 0x01c0 223 | #define RT5682S_HP_IMP_SENS_CTRL_22 0x01c1 224 | #define RT5682S_HP_IMP_SENS_CTRL_23 0x01c2 225 | #define RT5682S_HP_IMP_SENS_CTRL_24 0x01c3 226 | #define RT5682S_HP_IMP_SENS_CTRL_25 0x01c4 227 | #define RT5682S_HP_IMP_SENS_CTRL_26 0x01c5 228 | #define RT5682S_HP_IMP_SENS_CTRL_27 0x01c6 229 | #define RT5682S_HP_IMP_SENS_CTRL_28 0x01c7 230 | #define RT5682S_HP_IMP_SENS_CTRL_29 0x01c8 231 | #define RT5682S_HP_IMP_SENS_CTRL_30 0x01c9 232 | #define RT5682S_HP_IMP_SENS_CTRL_31 0x01ca 233 | #define RT5682S_HP_IMP_SENS_CTRL_32 0x01cb 234 | #define RT5682S_HP_IMP_SENS_CTRL_33 0x01cc 235 | #define RT5682S_HP_IMP_SENS_CTRL_34 0x01cd 236 | #define RT5682S_HP_IMP_SENS_CTRL_35 0x01ce 237 | #define RT5682S_HP_IMP_SENS_CTRL_36 0x01cf 238 | #define RT5682S_HP_IMP_SENS_CTRL_37 0x01d0 239 | #define RT5682S_HP_IMP_SENS_CTRL_38 0x01d1 240 | #define RT5682S_HP_IMP_SENS_CTRL_39 0x01d2 241 | #define RT5682S_HP_IMP_SENS_CTRL_40 0x01d3 242 | #define RT5682S_HP_IMP_SENS_CTRL_41 0x01d4 243 | #define RT5682S_HP_IMP_SENS_CTRL_42 0x01d5 244 | #define RT5682S_HP_IMP_SENS_CTRL_43 0x01d6 245 | #define RT5682S_HP_IMP_SENS_CTRL_44 0x01d7 246 | #define RT5682S_HP_IMP_SENS_CTRL_45 0x01d8 247 | #define RT5682S_HP_IMP_SENS_CTRL_46 0x01d9 248 | #define RT5682S_HP_LOGIC_CTRL_1 0x01da 249 | #define RT5682S_HP_LOGIC_CTRL_2 0x01db 250 | #define RT5682S_HP_LOGIC_CTRL_3 0x01dc 251 | #define RT5682S_HP_CALIB_CTRL_1 0x01de 252 | #define RT5682S_HP_CALIB_CTRL_2 0x01df 253 | #define RT5682S_HP_CALIB_CTRL_3 0x01e0 254 | #define RT5682S_HP_CALIB_CTRL_4 0x01e1 255 | #define RT5682S_HP_CALIB_CTRL_5 0x01e2 256 | #define RT5682S_HP_CALIB_CTRL_6 0x01e3 257 | #define RT5682S_HP_CALIB_CTRL_7 0x01e4 258 | #define RT5682S_HP_CALIB_CTRL_8 0x01e5 259 | #define RT5682S_HP_CALIB_CTRL_9 0x01e6 260 | #define RT5682S_HP_CALIB_CTRL_10 0x01e7 261 | #define RT5682S_HP_CALIB_CTRL_11 0x01e8 262 | #define RT5682S_HP_CALIB_ST_1 0x01ea 263 | #define RT5682S_HP_CALIB_ST_2 0x01eb 264 | #define RT5682S_HP_CALIB_ST_3 0x01ec 265 | #define RT5682S_HP_CALIB_ST_4 0x01ed 266 | #define RT5682S_HP_CALIB_ST_5 0x01ee 267 | #define RT5682S_HP_CALIB_ST_6 0x01ef 268 | #define RT5682S_HP_CALIB_ST_7 0x01f0 269 | #define RT5682S_HP_CALIB_ST_8 0x01f1 270 | #define RT5682S_HP_CALIB_ST_9 0x01f2 271 | #define RT5682S_HP_CALIB_ST_10 0x01f3 272 | #define RT5682S_HP_CALIB_ST_11 0x01f4 273 | #define RT5682S_SAR_IL_CMD_1 0x0210 274 | #define RT5682S_SAR_IL_CMD_2 0x0211 275 | #define RT5682S_SAR_IL_CMD_3 0x0212 276 | #define RT5682S_SAR_IL_CMD_4 0x0213 277 | #define RT5682S_SAR_IL_CMD_5 0x0214 278 | #define RT5682S_SAR_IL_CMD_6 0x0215 279 | #define RT5682S_SAR_IL_CMD_7 0x0216 280 | #define RT5682S_SAR_IL_CMD_8 0x0217 281 | #define RT5682S_SAR_IL_CMD_9 0x0218 282 | #define RT5682S_SAR_IL_CMD_10 0x0219 283 | #define RT5682S_SAR_IL_CMD_11 0x021a 284 | #define RT5682S_SAR_IL_CMD_12 0x021b 285 | #define RT5682S_SAR_IL_CMD_13 0x021c 286 | #define RT5682S_SAR_IL_CMD_14 0x021d 287 | #define RT5682S_DUMMY_4 0x02fa 288 | #define RT5682S_DUMMY_5 0x02fb 289 | #define RT5682S_DUMMY_6 0x02fc 290 | #define RT5682S_VERSION_ID_HIDE 0x03fe 291 | #define RT5682S_VERSION_ID_CUS 0x03ff 292 | #define RT5682S_SCAN_CTL 0x0500 293 | #define RT5682S_HP_AMP_DET 0x0600 294 | #define RT5682S_BIAS_CUR_CTRL_11 0x0610 295 | #define RT5682S_BIAS_CUR_CTRL_12 0x0611 296 | #define RT5682S_BIAS_CUR_CTRL_13 0x0620 297 | #define RT5682S_BIAS_CUR_CTRL_14 0x0621 298 | #define RT5682S_BIAS_CUR_CTRL_15 0x0630 299 | #define RT5682S_BIAS_CUR_CTRL_16 0x0631 300 | #define RT5682S_BIAS_CUR_CTRL_17 0x0640 301 | #define RT5682S_BIAS_CUR_CTRL_18 0x0641 302 | #define RT5682S_I2C_TRANS_CTRL 0x07fa 303 | #define RT5682S_DUMMY_7 0x08fa 304 | #define RT5682S_DUMMY_8 0x08fb 305 | #define RT5682S_DMIC_FLOAT_DET 0x0d00 306 | #define RT5682S_HA_CMP_OP_1 0x1100 307 | #define RT5682S_HA_CMP_OP_2 0x1101 308 | #define RT5682S_HA_CMP_OP_3 0x1102 309 | #define RT5682S_HA_CMP_OP_4 0x1103 310 | #define RT5682S_HA_CMP_OP_5 0x1104 311 | #define RT5682S_HA_CMP_OP_6 0x1105 312 | #define RT5682S_HA_CMP_OP_7 0x1106 313 | #define RT5682S_HA_CMP_OP_8 0x1107 314 | #define RT5682S_HA_CMP_OP_9 0x1108 315 | #define RT5682S_HA_CMP_OP_10 0x1109 316 | #define RT5682S_HA_CMP_OP_11 0x110a 317 | #define RT5682S_HA_CMP_OP_12 0x110b 318 | #define RT5682S_HA_CMP_OP_13 0x110c 319 | #define RT5682S_HA_CMP_OP_14 0x1111 320 | #define RT5682S_HA_CMP_OP_15 0x1112 321 | #define RT5682S_HA_CMP_OP_16 0x1113 322 | #define RT5682S_HA_CMP_OP_17 0x1114 323 | #define RT5682S_HA_CMP_OP_18 0x1115 324 | #define RT5682S_HA_CMP_OP_19 0x1116 325 | #define RT5682S_HA_CMP_OP_20 0x1117 326 | #define RT5682S_HA_CMP_OP_21 0x1118 327 | #define RT5682S_HA_CMP_OP_22 0x1119 328 | #define RT5682S_HA_CMP_OP_23 0x111a 329 | #define RT5682S_HA_CMP_OP_24 0x111b 330 | #define RT5682S_HA_CMP_OP_25 0x111c 331 | #define RT5682S_NEW_CBJ_DET_CTL_1 0x1401 332 | #define RT5682S_NEW_CBJ_DET_CTL_2 0x1402 333 | #define RT5682S_NEW_CBJ_DET_CTL_3 0x1403 334 | #define RT5682S_NEW_CBJ_DET_CTL_4 0x1404 335 | #define RT5682S_NEW_CBJ_DET_CTL_5 0x1406 336 | #define RT5682S_NEW_CBJ_DET_CTL_6 0x1407 337 | #define RT5682S_NEW_CBJ_DET_CTL_7 0x1408 338 | #define RT5682S_NEW_CBJ_DET_CTL_8 0x1409 339 | #define RT5682S_NEW_CBJ_DET_CTL_9 0x140a 340 | #define RT5682S_NEW_CBJ_DET_CTL_10 0x140b 341 | #define RT5682S_NEW_CBJ_DET_CTL_11 0x140c 342 | #define RT5682S_NEW_CBJ_DET_CTL_12 0x140d 343 | #define RT5682S_NEW_CBJ_DET_CTL_13 0x140e 344 | #define RT5682S_NEW_CBJ_DET_CTL_14 0x140f 345 | #define RT5682S_NEW_CBJ_DET_CTL_15 0x1410 346 | #define RT5682S_NEW_CBJ_DET_CTL_16 0x1411 347 | #define RT5682S_DA_FILTER_1 0x1801 348 | #define RT5682S_DA_FILTER_2 0x1802 349 | #define RT5682S_DA_FILTER_3 0x1803 350 | #define RT5682S_DA_FILTER_4 0x1804 351 | #define RT5682S_DA_FILTER_5 0x1805 352 | #define RT5682S_CLK_SW_TEST_1 0x2c00 353 | #define RT5682S_CLK_SW_TEST_2 0x3400 354 | #define RT5682S_CLK_SW_TEST_3 0x3404 355 | #define RT5682S_CLK_SW_TEST_4 0x3405 356 | #define RT5682S_CLK_SW_TEST_5 0x3406 357 | #define RT5682S_CLK_SW_TEST_6 0x3407 358 | #define RT5682S_CLK_SW_TEST_7 0x3408 359 | #define RT5682S_CLK_SW_TEST_8 0x3409 360 | #define RT5682S_CLK_SW_TEST_9 0x340a 361 | #define RT5682S_CLK_SW_TEST_10 0x340b 362 | #define RT5682S_CLK_SW_TEST_11 0x340c 363 | #define RT5682S_CLK_SW_TEST_12 0x340d 364 | #define RT5682S_CLK_SW_TEST_13 0x340e 365 | #define RT5682S_CLK_SW_TEST_14 0x340f 366 | #define RT5682S_EFUSE_MANU_WRITE_1 0x3410 367 | #define RT5682S_EFUSE_MANU_WRITE_2 0x3411 368 | #define RT5682S_EFUSE_MANU_WRITE_3 0x3412 369 | #define RT5682S_EFUSE_MANU_WRITE_4 0x3413 370 | #define RT5682S_EFUSE_MANU_WRITE_5 0x3414 371 | #define RT5682S_EFUSE_MANU_WRITE_6 0x3415 372 | #define RT5682S_EFUSE_READ_1 0x3424 373 | #define RT5682S_EFUSE_READ_2 0x3425 374 | #define RT5682S_EFUSE_READ_3 0x3426 375 | #define RT5682S_EFUSE_READ_4 0x3427 376 | #define RT5682S_EFUSE_READ_5 0x3428 377 | #define RT5682S_EFUSE_READ_6 0x3429 378 | #define RT5682S_EFUSE_READ_7 0x342a 379 | #define RT5682S_EFUSE_READ_8 0x342b 380 | #define RT5682S_EFUSE_READ_9 0x342c 381 | #define RT5682S_EFUSE_READ_10 0x342d 382 | #define RT5682S_EFUSE_READ_11 0x342e 383 | #define RT5682S_EFUSE_READ_12 0x342f 384 | #define RT5682S_EFUSE_READ_13 0x3430 385 | #define RT5682S_EFUSE_READ_14 0x3431 386 | #define RT5682S_EFUSE_READ_15 0x3432 387 | #define RT5682S_EFUSE_READ_16 0x3433 388 | #define RT5682S_EFUSE_READ_17 0x3434 389 | #define RT5682S_EFUSE_READ_18 0x3435 390 | #define RT5682S_EFUSE_TIMING_CTL_1 0x3440 391 | #define RT5682S_EFUSE_TIMING_CTL_2 0x3441 392 | #define RT5682S_PILOT_DIG_CTL_1 0x3500 393 | #define RT5682S_PILOT_DIG_CTL_2 0x3501 394 | #define RT5682S_HP_AMP_DET_CTL_1 0x3b00 395 | #define RT5682S_HP_AMP_DET_CTL_2 0x3b01 396 | #define RT5682S_HP_AMP_DET_CTL_3 0x3b02 397 | #define RT5682S_HP_AMP_DET_CTL_4 0x3b03 398 | 399 | #define RT5682S_MAX_REG (RT5682S_HP_AMP_DET_CTL_4) 400 | 401 | /* global definition */ 402 | #define RT5682S_L_MUTE (0x1 << 15) 403 | #define RT5682S_L_MUTE_SFT 15 404 | #define RT5682S_R_MUTE (0x1 << 7) 405 | #define RT5682S_R_MUTE_SFT 7 406 | #define RT5682S_L_VOL_SFT 8 407 | #define RT5682S_R_VOL_SFT 0 408 | #define RT5682S_CLK_SRC_MCLK (0x0) 409 | #define RT5682S_CLK_SRC_PLL1 (0x1) 410 | #define RT5682S_CLK_SRC_PLL2 (0x2) 411 | #define RT5682S_CLK_SRC_RCCLK (0x4) /* 25M */ 412 | 413 | 414 | /* Headphone Amp Control 2 (0x0003) */ 415 | #define RT5682S_HPO_L_PATH_MASK (0x1 << 14) 416 | #define RT5682S_HPO_L_PATH_EN (0x1 << 14) 417 | #define RT5682S_HPO_L_PATH_DIS (0x0 << 14) 418 | #define RT5682S_HPO_R_PATH_MASK (0x1 << 13) 419 | #define RT5682S_HPO_R_PATH_EN (0x1 << 13) 420 | #define RT5682S_HPO_R_PATH_DIS (0x0 << 13) 421 | #define RT5682S_HPO_SEL_IP_EN_SW (0x1) 422 | #define RT5682S_HPO_IP_EN_GATING (0x1) 423 | #define RT5682S_HPO_IP_NO_GATING (0x0) 424 | 425 | /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 426 | #define RT5682S_G_HP (0xf << 8) 427 | #define RT5682S_G_HP_SFT 8 428 | #define RT5682S_G_STO_DA_DMIX (0xf) 429 | #define RT5682S_G_STO_DA_SFT 0 430 | 431 | /* Embeeded Jack and Type Detection Control 2 (0x0010) */ 432 | #define RT5682S_EMB_JD_MASK (0x1 << 15) 433 | #define RT5682S_EMB_JD_EN (0x1 << 15) 434 | #define RT5682S_EMB_JD_EN_SFT 15 435 | #define RT5682S_EMB_JD_RST (0x1 << 14) 436 | #define RT5682S_JD_MODE (0x1 << 13) 437 | #define RT5682S_JD_MODE_SFT 13 438 | #define RT5682S_DET_TYPE (0x1 << 12) 439 | #define RT5682S_DET_TYPE_SFT 12 440 | #define RT5682S_POLA_EXT_JD_MASK (0x1 << 11) 441 | #define RT5682S_POLA_EXT_JD_LOW (0x1 << 11) 442 | #define RT5682S_POLA_EXT_JD_HIGH (0x0 << 11) 443 | #define RT5682S_SEL_FAST_OFF_MASK (0x3 << 9) 444 | #define RT5682S_SEL_FAST_OFF_SFT 9 445 | #define RT5682S_POL_FAST_OFF_MASK (0x1 << 8) 446 | #define RT5682S_POL_FAST_OFF_HIGH (0x1 << 8) 447 | #define RT5682S_POL_FAST_OFF_LOW (0x0 << 8) 448 | #define RT5682S_FAST_OFF_MASK (0x1 << 7) 449 | #define RT5682S_FAST_OFF_EN (0x1 << 7) 450 | #define RT5682S_FAST_OFF_DIS (0x0 << 7) 451 | #define RT5682S_VREF_POW_MASK (0x1 << 6) 452 | #define RT5682S_VREF_POW_FSM (0x0 << 6) 453 | #define RT5682S_VREF_POW_REG (0x1 << 6) 454 | #define RT5682S_MB1_PATH_BIT 5 455 | #define RT5682S_MB1_PATH_MASK (0x1 << 5) 456 | #define RT5682S_CTRL_MB1_REG (0x1 << 5) 457 | #define RT5682S_CTRL_MB1_FSM (0x0 << 5) 458 | #define RT5682S_MB2_PATH_BIT 4 459 | #define RT5682S_MB2_PATH_MASK (0x1 << 4) 460 | #define RT5682S_CTRL_MB2_REG (0x1 << 4) 461 | #define RT5682S_CTRL_MB2_FSM (0x0 << 4) 462 | #define RT5682S_TRIG_JD_MASK (0x1 << 3) 463 | #define RT5682S_TRIG_JD_HIGH (0x1 << 3) 464 | #define RT5682S_TRIG_JD_LOW (0x0 << 3) 465 | #define RT5682S_MIC_CAP_MASK (0x1 << 1) 466 | #define RT5682S_MIC_CAP_HS (0x1 << 1) 467 | #define RT5682S_MIC_CAP_HP (0x0 << 1) 468 | #define RT5682S_MIC_CAP_SRC_MASK (0x1) 469 | #define RT5682S_MIC_CAP_SRC_REG (0x1) 470 | #define RT5682S_MIC_CAP_SRC_ANA (0x0) 471 | 472 | /* Embeeded Jack and Type Detection Control 3 (0x0011) */ 473 | #define RT5682S_SEL_CBJ_TYPE_SLOW (0x1 << 15) 474 | #define RT5682S_SEL_CBJ_TYPE_NORM (0x0 << 15) 475 | #define RT5682S_SEL_CBJ_TYPE_MASK (0x1 << 15) 476 | #define RT5682S_POW_BG_MB1_MASK (0x1 << 13) 477 | #define RT5682S_POW_BG_MB1_REG (0x1 << 13) 478 | #define RT5682S_POW_BG_MB1_FSM (0x0 << 13) 479 | #define RT5682S_POW_BG_MB2_MASK (0x1 << 12) 480 | #define RT5682S_POW_BG_MB2_REG (0x1 << 12) 481 | #define RT5682S_POW_BG_MB2_FSM (0x0 << 12) 482 | #define RT5682S_EXT_JD_SRC (0x7 << 4) 483 | #define RT5682S_EXT_JD_SRC_SFT 4 484 | #define RT5682S_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) 485 | #define RT5682S_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) 486 | #define RT5682S_EXT_JD_SRC_JDH (0x2 << 4) 487 | #define RT5682S_EXT_JD_SRC_JDL (0x3 << 4) 488 | #define RT5682S_EXT_JD_SRC_MANUAL (0x4 << 4) 489 | #define RT5682S_JACK_TYPE_MASK (0x3) 490 | 491 | /* Combo Jack and Type Detection Control 4 (0x0012) */ 492 | #define RT5682S_CBJ_IN_BUF_MASK (0x1 << 7) 493 | #define RT5682S_CBJ_IN_BUF_EN (0x1 << 7) 494 | #define RT5682S_CBJ_IN_BUF_DIS (0x0 << 7) 495 | #define RT5682S_CBJ_IN_BUF_BIT 7 496 | 497 | /* Combo Jack and Type Detection Control 5 (0x0013) */ 498 | #define RT5682S_SEL_SHT_MID_TON_MASK (0x3 << 12) 499 | #define RT5682S_SEL_SHT_MID_TON_2 (0x0 << 12) 500 | #define RT5682S_SEL_SHT_MID_TON_3 (0x1 << 12) 501 | #define RT5682S_CBJ_JD_TEST_MASK (0x1 << 6) 502 | #define RT5682S_CBJ_JD_TEST_NORM (0x0 << 6) 503 | #define RT5682S_CBJ_JD_TEST_MODE (0x1 << 6) 504 | 505 | /* Combo Jack and Type Detection Control 6 (0x0014) */ 506 | #define RT5682S_JD_FAST_OFF_SRC_MASK (0x7 << 8) 507 | #define RT5682S_JD_FAST_OFF_SRC_JDH (0x6 << 8) 508 | #define RT5682S_JD_FAST_OFF_SRC_GPIO6 (0x5 << 8) 509 | #define RT5682S_JD_FAST_OFF_SRC_GPIO5 (0x4 << 8) 510 | #define RT5682S_JD_FAST_OFF_SRC_GPIO4 (0x3 << 8) 511 | #define RT5682S_JD_FAST_OFF_SRC_GPIO3 (0x2 << 8) 512 | #define RT5682S_JD_FAST_OFF_SRC_GPIO2 (0x1 << 8) 513 | #define RT5682S_JD_FAST_OFF_SRC_GPIO1 (0x0 << 8) 514 | 515 | /* DAC1 Digital Volume (0x0019) */ 516 | #define RT5682S_DAC_L1_VOL_MASK (0xff << 8) 517 | #define RT5682S_DAC_L1_VOL_SFT 8 518 | #define RT5682S_DAC_R1_VOL_MASK (0xff) 519 | #define RT5682S_DAC_R1_VOL_SFT 0 520 | 521 | /* ADC Digital Volume Control (0x001c) */ 522 | #define RT5682S_ADC_L_VOL_MASK (0x7f << 8) 523 | #define RT5682S_ADC_L_VOL_SFT 8 524 | #define RT5682S_ADC_R_VOL_MASK (0x7f) 525 | #define RT5682S_ADC_R_VOL_SFT 0 526 | 527 | /* Stereo1 ADC Boost Gain Control (0x001f) */ 528 | #define RT5682S_STO1_ADC_L_BST_MASK (0x3 << 14) 529 | #define RT5682S_STO1_ADC_L_BST_SFT 14 530 | #define RT5682S_STO1_ADC_R_BST_MASK (0x3 << 12) 531 | #define RT5682S_STO1_ADC_R_BST_SFT 12 532 | 533 | /* Sidetone Control (0x0024) */ 534 | #define RT5682S_ST_SRC_SEL (0x1 << 8) 535 | #define RT5682S_ST_SRC_SFT 8 536 | #define RT5682S_ST_EN_MASK (0x1 << 6) 537 | #define RT5682S_ST_DIS (0x0 << 6) 538 | #define RT5682S_ST_EN (0x1 << 6) 539 | #define RT5682S_ST_EN_SFT 6 540 | 541 | /* Stereo1 ADC Mixer Control (0x0026) */ 542 | #define RT5682S_M_STO1_ADC_L1 (0x1 << 15) 543 | #define RT5682S_M_STO1_ADC_L1_SFT 15 544 | #define RT5682S_M_STO1_ADC_L2 (0x1 << 14) 545 | #define RT5682S_M_STO1_ADC_L2_SFT 14 546 | #define RT5682S_STO1_ADC1L_SRC_MASK (0x1 << 13) 547 | #define RT5682S_STO1_ADC1L_SRC_SFT 13 548 | #define RT5682S_STO1_ADC1_SRC_ADC (0x1 << 13) 549 | #define RT5682S_STO1_ADC1_SRC_DACMIX (0x0 << 13) 550 | #define RT5682S_STO1_ADC2L_SRC_MASK (0x1 << 12) 551 | #define RT5682S_STO1_ADC2L_SRC_SFT 12 552 | #define RT5682S_STO1_ADCL_SRC_MASK (0x3 << 10) 553 | #define RT5682S_STO1_ADCL_SRC_SFT 10 554 | #define RT5682S_M_STO1_ADC_R1 (0x1 << 7) 555 | #define RT5682S_M_STO1_ADC_R1_SFT 7 556 | #define RT5682S_M_STO1_ADC_R2 (0x1 << 6) 557 | #define RT5682S_M_STO1_ADC_R2_SFT 6 558 | #define RT5682S_STO1_ADC1R_SRC_MASK (0x1 << 5) 559 | #define RT5682S_STO1_ADC1R_SRC_SFT 5 560 | #define RT5682S_STO1_ADC2R_SRC_MASK (0x1 << 4) 561 | #define RT5682S_STO1_ADC2R_SRC_SFT 4 562 | #define RT5682S_STO1_ADCR_SRC_MASK (0x3 << 2) 563 | #define RT5682S_STO1_ADCR_SRC_SFT 2 564 | 565 | /* ADC Mixer to DAC Mixer Control (0x0029) */ 566 | #define RT5682S_M_ADCMIX_L (0x1 << 15) 567 | #define RT5682S_M_ADCMIX_L_SFT 15 568 | #define RT5682S_M_DAC1_L (0x1 << 14) 569 | #define RT5682S_M_DAC1_L_SFT 14 570 | #define RT5682S_M_ADCMIX_R (0x1 << 7) 571 | #define RT5682S_M_ADCMIX_R_SFT 7 572 | #define RT5682S_M_DAC1_R (0x1 << 6) 573 | #define RT5682S_M_DAC1_R_SFT 6 574 | 575 | /* Stereo1 DAC Mixer Control (0x002a) */ 576 | #define RT5682S_M_DAC_L1_STO_L (0x1 << 15) 577 | #define RT5682S_M_DAC_L1_STO_L_SFT 15 578 | #define RT5682S_G_DAC_L1_STO_L_MASK (0x1 << 14) 579 | #define RT5682S_G_DAC_L1_STO_L_SFT 14 580 | #define RT5682S_M_DAC_R1_STO_L (0x1 << 13) 581 | #define RT5682S_M_DAC_R1_STO_L_SFT 13 582 | #define RT5682S_G_DAC_R1_STO_L_MASK (0x1 << 12) 583 | #define RT5682S_G_DAC_R1_STO_L_SFT 12 584 | #define RT5682S_M_DAC_L1_STO_R (0x1 << 7) 585 | #define RT5682S_M_DAC_L1_STO_R_SFT 7 586 | #define RT5682S_G_DAC_L1_STO_R_MASK (0x1 << 6) 587 | #define RT5682S_G_DAC_L1_STO_R_SFT 6 588 | #define RT5682S_M_DAC_R1_STO_R (0x1 << 5) 589 | #define RT5682S_M_DAC_R1_STO_R_SFT 5 590 | #define RT5682S_G_DAC_R1_STO_R_MASK (0x1 << 4) 591 | #define RT5682S_G_DAC_R1_STO_R_SFT 4 592 | 593 | /* Analog DAC1 Input Source Control (0x002b) */ 594 | #define RT5682S_M_ST_STO_L (0x1 << 9) 595 | #define RT5682S_M_ST_STO_L_SFT 9 596 | #define RT5682S_M_ST_STO_R (0x1 << 8) 597 | #define RT5682S_M_ST_STO_R_SFT 8 598 | #define RT5682S_DAC_L1_SRC_MASK (0x1 << 4) 599 | #define RT5682S_A_DACL1_SFT 4 600 | #define RT5682S_DAC_R1_SRC_MASK (0x1) 601 | #define RT5682S_A_DACR1_SFT 0 602 | 603 | /* Digital Interface Data Control (0x0030) */ 604 | #define RT5682S_IF2_DAC_SEL_MASK (0x3 << 2) 605 | #define RT5682S_IF2_DAC_SEL_SFT 2 606 | #define RT5682S_IF2_ADC_SEL_MASK (0x3 << 0) 607 | #define RT5682S_IF2_ADC_SEL_SFT 0 608 | 609 | /* REC Left/Right Mixer Control 2 (0x003c) */ 610 | #define RT5682S_BST_CBJ_MASK (0x3f << 8) 611 | #define RT5682S_BST_CBJ_SFT 8 612 | #define RT5682S_M_CBJ_RM1_L (0x1 << 7) 613 | #define RT5682S_M_CBJ_RM1_L_SFT 7 614 | #define RT5682S_M_CBJ_RM1_R (0x1 << 6) 615 | #define RT5682S_M_CBJ_RM1_R_SFT 6 616 | 617 | /* REC Left/Right Mixer Calibration Control(0x0044) */ 618 | #define RT5682S_PWR_RM1_R_BIT 8 619 | #define RT5682S_PWR_RM1_L_BIT 0 620 | 621 | /* Power Management for Digital 1 (0x0061) */ 622 | #define RT5682S_PWR_I2S1 (0x1 << 15) 623 | #define RT5682S_PWR_I2S1_BIT 15 624 | #define RT5682S_PWR_I2S2 (0x1 << 14) 625 | #define RT5682S_PWR_I2S2_BIT 14 626 | #define RT5682S_PRE_CHR_DAC_L1 (0x1 << 13) 627 | #define RT5682S_PRE_CHR_DAC_L1_BIT 13 628 | #define RT5682S_PRE_CHR_DAC_R1 (0x1 << 12) 629 | #define RT5682S_PRE_CHR_DAC_R1_BIT 12 630 | #define RT5682S_PWR_DAC_L1 (0x1 << 11) 631 | #define RT5682S_PWR_DAC_L1_BIT 11 632 | #define RT5682S_PWR_DAC_R1 (0x1 << 10) 633 | #define RT5682S_PWR_DAC_R1_BIT 10 634 | #define RT5682S_PWR_LDO (0x1 << 8) 635 | #define RT5682S_PWR_LDO_BIT 8 636 | #define RT5682S_PWR_D2S_L (0x1 << 7) 637 | #define RT5682S_PWR_D2S_L_BIT 7 638 | #define RT5682S_PWR_D2S_R (0x1 << 6) 639 | #define RT5682S_PWR_D2S_R_BIT 6 640 | #define RT5682S_PWR_ADC_L1 (0x1 << 4) 641 | #define RT5682S_PWR_ADC_L1_BIT 4 642 | #define RT5682S_PWR_ADC_R1 (0x1 << 3) 643 | #define RT5682S_PWR_ADC_R1_BIT 3 644 | #define RT5682S_EFUSE_SW_EN (0x1 << 2) 645 | #define RT5682S_EFUSE_SW_DIS (0x0 << 2) 646 | #define RT5682S_PWR_EFUSE (0x1 << 1) 647 | #define RT5682S_PWR_EFUSE_BIT 1 648 | #define RT5682S_DIG_GATE_CTRL (0x1 << 0) 649 | #define RT5682S_DIG_GATE_CTRL_SFT 0 650 | 651 | /* Power Management for Digital 2 (0x0062) */ 652 | #define RT5682S_PWR_ADC_S1F (0x1 << 15) 653 | #define RT5682S_PWR_ADC_S1F_BIT 15 654 | #define RT5682S_PWR_DAC_S1F (0x1 << 10) 655 | #define RT5682S_PWR_DAC_S1F_BIT 10 656 | #define RT5682S_DLDO_I_LIMIT_MASK (0x1 << 7) 657 | #define RT5682S_DLDO_I_LIMIT_EN (0x1 << 7) 658 | #define RT5682S_DLDO_I_LIMIT_DIS (0x0 << 7) 659 | #define RT5682S_DLDO_I_BIAS_SEL_4 (0x1 << 6) 660 | #define RT5682S_DLDO_I_BIAS_SEL_0 (0x0 << 6) 661 | #define RT5682S_DLDO_REG_TEST_1 (0x1 << 5) 662 | #define RT5682S_DLDO_REG_TEST_0 (0x0 << 5) 663 | #define RT5682S_DLDO_SRC_REG (0x1 << 4) 664 | #define RT5682S_DLDO_SRC_EFUSE (0x0 << 4) 665 | 666 | /* Power Management for Analog 1 (0x0063) */ 667 | #define RT5682S_PWR_VREF1 (0x1 << 15) 668 | #define RT5682S_PWR_VREF1_BIT 15 669 | #define RT5682S_PWR_FV1 (0x1 << 14) 670 | #define RT5682S_PWR_FV1_BIT 14 671 | #define RT5682S_PWR_VREF2 (0x1 << 13) 672 | #define RT5682S_PWR_VREF2_BIT 13 673 | #define RT5682S_PWR_FV2 (0x1 << 12) 674 | #define RT5682S_PWR_FV2_BIT 12 675 | #define RT5682S_LDO1_DBG_MASK (0x3 << 10) 676 | #define RT5682S_PWR_MB (0x1 << 9) 677 | #define RT5682S_PWR_MB_BIT 9 678 | #define RT5682S_PWR_BG (0x1 << 7) 679 | #define RT5682S_PWR_BG_BIT 7 680 | #define RT5682S_LDO1_BYPASS_MASK (0x1 << 6) 681 | #define RT5682S_LDO1_BYPASS (0x1 << 6) 682 | #define RT5682S_LDO1_NOT_BYPASS (0x0 << 6) 683 | 684 | /* Power Management for Analog 2 (0x0064) */ 685 | #define RT5682S_PWR_MCLK0_WD (0x1 << 15) 686 | #define RT5682S_PWR_MCLK0_WD_BIT 15 687 | #define RT5682S_PWR_MCLK1_WD (0x1 << 14) 688 | #define RT5682S_PWR_MCLK1_WD_BIT 14 689 | #define RT5682S_RST_MCLK0 (0x1 << 13) 690 | #define RT5682S_RST_MCLK0_BIT 13 691 | #define RT5682S_RST_MCLK1 (0x1 << 12) 692 | #define RT5682S_RST_MCLK1_BIT 12 693 | #define RT5682S_PWR_MB1 (0x1 << 11) 694 | #define RT5682S_PWR_MB1_PWR_DOWN (0x0 << 11) 695 | #define RT5682S_PWR_MB1_BIT 11 696 | #define RT5682S_PWR_MB2 (0x1 << 10) 697 | #define RT5682S_PWR_MB2_PWR_DOWN (0x0 << 10) 698 | #define RT5682S_PWR_MB2_BIT 10 699 | #define RT5682S_PWR_JD_MASK (0x1 << 0) 700 | #define RT5682S_PWR_JD_ENABLE (0x1 << 0) 701 | #define RT5682S_PWR_JD_DISABLE (0x0 << 0) 702 | 703 | /* Power Management for Analog 3 (0x0065) */ 704 | #define RT5682S_PWR_LDO_PLLA (0x1 << 15) 705 | #define RT5682S_PWR_LDO_PLLA_BIT 15 706 | #define RT5682S_PWR_LDO_PLLB (0x1 << 14) 707 | #define RT5682S_PWR_LDO_PLLB_BIT 14 708 | #define RT5682S_PWR_BIAS_PLLA (0x1 << 13) 709 | #define RT5682S_PWR_BIAS_PLLA_BIT 13 710 | #define RT5682S_PWR_BIAS_PLLB (0x1 << 12) 711 | #define RT5682S_PWR_BIAS_PLLB_BIT 12 712 | #define RT5682S_PWR_CBJ (0x1 << 9) 713 | #define RT5682S_PWR_CBJ_BIT 9 714 | #define RT5682S_RSTB_PLLB (0x1 << 7) 715 | #define RT5682S_RSTB_PLLB_BIT 7 716 | #define RT5682S_RSTB_PLLA (0x1 << 6) 717 | #define RT5682S_RSTB_PLLA_BIT 6 718 | #define RT5682S_PWR_PLLB (0x1 << 5) 719 | #define RT5682S_PWR_PLLB_BIT 5 720 | #define RT5682S_PWR_PLLA (0x1 << 4) 721 | #define RT5682S_PWR_PLLA_BIT 4 722 | #define RT5682S_PWR_LDO_MB2 (0x1 << 2) 723 | #define RT5682S_PWR_LDO_MB2_BIT 2 724 | #define RT5682S_PWR_LDO_MB1 (0x1 << 1) 725 | #define RT5682S_PWR_LDO_MB1_BIT 1 726 | #define RT5682S_PWR_BGLDO (0x1 << 0) 727 | #define RT5682S_PWR_BGLDO_BIT 0 728 | 729 | /* Power Management for Mixer (0x0066) */ 730 | #define RT5682S_PWR_CLK_COMP_8FS (0x1 << 15) 731 | #define RT5682S_PWR_CLK_COMP_8FS_BIT 15 732 | #define RT5682S_DBG_BGLDO_MASK (0x3 << 12) 733 | #define RT5682S_DBG_BGLDO_SFT 12 734 | #define RT5682S_DBG_BGLDO_MB1_MASK (0x3 << 10) 735 | #define RT5682S_DBG_BGLDO_MB1_SFT 10 736 | #define RT5682S_DBG_BGLDO_MB2_MASK (0x3 << 8) 737 | #define RT5682S_DBG_BGLDO_MB2_SFT 8 738 | #define RT5682S_DLDO_BGLDO_MASK (0x3 << 6) 739 | #define RT5682S_DLDO_BGLDO_MB2_SFT 6 740 | #define RT5682S_PWR_STO1_DAC_L (0x1 << 5) 741 | #define RT5682S_PWR_STO1_DAC_L_BIT 5 742 | #define RT5682S_PWR_STO1_DAC_R (0x1 << 4) 743 | #define RT5682S_PWR_STO1_DAC_R_BIT 4 744 | #define RT5682S_DVO_BGLDO_MB1_MASK (0x3 << 2) 745 | #define RT5682S_DVO_BGLDO_MB1_SFT 2 746 | #define RT5682S_DVO_BGLDO_MB2_MASK (0x3 << 0) 747 | 748 | /* MCLK and System Clock Detection Control (0x006b) */ 749 | #define RT5682S_SYS_CLK_DET (0x1 << 15) 750 | #define RT5682S_SYS_CLK_DET_SFT 15 751 | #define RT5682S_PLL1_CLK_DET (0x1 << 14) 752 | #define RT5682S_PLL1_CLK_DET_SFT 14 753 | 754 | /* Digital Microphone Control 1 (0x006e) */ 755 | #define RT5682S_DMIC_1_EN_MASK (0x1 << 15) 756 | #define RT5682S_DMIC_1_EN_SFT 15 757 | #define RT5682S_DMIC_1_DIS (0x0 << 15) 758 | #define RT5682S_DMIC_1_EN (0x1 << 15) 759 | #define RT5682S_FIFO_CLK_DIV_MASK (0x7 << 12) 760 | #define RT5682S_FIFO_CLK_DIV_2 (0x1 << 12) 761 | #define RT5682S_DMIC_1_DP_MASK (0x3 << 4) 762 | #define RT5682S_DMIC_1_DP_SFT 4 763 | #define RT5682S_DMIC_1_DP_GPIO2 (0x0 << 4) 764 | #define RT5682S_DMIC_1_DP_GPIO5 (0x1 << 4) 765 | #define RT5682S_DMIC_CLK_MASK (0xf << 0) 766 | #define RT5682S_DMIC_CLK_SFT 0 767 | 768 | /* I2S1 Audio Serial Data Port Control (0x0070) */ 769 | #define RT5682S_SEL_ADCDAT_MASK (0x1 << 15) 770 | #define RT5682S_SEL_ADCDAT_OUT (0x0 << 15) 771 | #define RT5682S_SEL_ADCDAT_IN (0x1 << 15) 772 | #define RT5682S_SEL_ADCDAT_SFT 15 773 | #define RT5682S_I2S1_TX_CHL_MASK (0x7 << 12) 774 | #define RT5682S_I2S1_TX_CHL_SFT 12 775 | #define RT5682S_I2S1_TX_CHL_16 (0x0 << 12) 776 | #define RT5682S_I2S1_TX_CHL_20 (0x1 << 12) 777 | #define RT5682S_I2S1_TX_CHL_24 (0x2 << 12) 778 | #define RT5682S_I2S1_TX_CHL_32 (0x3 << 12) 779 | #define RT5682S_I2S1_TX_CHL_8 (0x4 << 12) 780 | #define RT5682S_I2S1_RX_CHL_MASK (0x7 << 8) 781 | #define RT5682S_I2S1_RX_CHL_SFT 8 782 | #define RT5682S_I2S1_RX_CHL_16 (0x0 << 8) 783 | #define RT5682S_I2S1_RX_CHL_20 (0x1 << 8) 784 | #define RT5682S_I2S1_RX_CHL_24 (0x2 << 8) 785 | #define RT5682S_I2S1_RX_CHL_32 (0x3 << 8) 786 | #define RT5682S_I2S1_RX_CHL_8 (0x4 << 8) 787 | #define RT5682S_I2S1_MONO_MASK (0x1 << 7) 788 | #define RT5682S_I2S1_MONO_EN (0x1 << 7) 789 | #define RT5682S_I2S1_MONO_DIS (0x0 << 7) 790 | #define RT5682S_I2S1_DL_MASK (0x7 << 4) 791 | #define RT5682S_I2S1_DL_SFT 4 792 | #define RT5682S_I2S1_DL_16 (0x0 << 4) 793 | #define RT5682S_I2S1_DL_20 (0x1 << 4) 794 | #define RT5682S_I2S1_DL_24 (0x2 << 4) 795 | #define RT5682S_I2S1_DL_32 (0x3 << 4) 796 | #define RT5682S_I2S1_DL_8 (0x4 << 4) 797 | 798 | /* I2S1/2 Audio Serial Data Port Control (0x0071) */ 799 | #define RT5682S_I2S2_MS_MASK (0x1 << 15) 800 | #define RT5682S_I2S2_MS_SFT 15 801 | #define RT5682S_I2S2_MS_M (0x0 << 15) 802 | #define RT5682S_I2S2_MS_S (0x1 << 15) 803 | #define RT5682S_I2S2_PIN_CFG_MASK (0x1 << 14) 804 | #define RT5682S_I2S2_PIN_CFG_SFT 14 805 | #define RT5682S_I2S2_OUT_MASK (0x1 << 9) 806 | #define RT5682S_I2S2_OUT_SFT 9 807 | #define RT5682S_I2S2_OUT_UM (0x0 << 9) 808 | #define RT5682S_I2S2_OUT_M (0x1 << 9) 809 | #define RT5682S_I2S_BP_MASK (0x1 << 8) 810 | #define RT5682S_I2S_BP_SFT 8 811 | #define RT5682S_I2S_BP_NOR (0x0 << 8) 812 | #define RT5682S_I2S_BP_INV (0x1 << 8) 813 | #define RT5682S_I2S2_MONO_MASK (0x1 << 7) 814 | #define RT5682S_I2S2_MONO_EN (0x1 << 7) 815 | #define RT5682S_I2S2_MONO_DIS (0x0 << 7) 816 | #define RT5682S_I2S2_DL_MASK (0x7 << 4) 817 | #define RT5682S_I2S2_DL_SFT 4 818 | #define RT5682S_I2S2_DL_8 (0x0 << 4) 819 | #define RT5682S_I2S2_DL_16 (0x1 << 4) 820 | #define RT5682S_I2S2_DL_20 (0x2 << 4) 821 | #define RT5682S_I2S2_DL_24 (0x3 << 4) 822 | #define RT5682S_I2S2_DL_32 (0x4 << 4) 823 | #define RT5682S_I2S_DF_MASK (0x7) 824 | #define RT5682S_I2S_DF_SFT 0 825 | #define RT5682S_I2S_DF_I2S (0x0) 826 | #define RT5682S_I2S_DF_LEFT (0x1) 827 | #define RT5682S_I2S_DF_PCM_A (0x2) 828 | #define RT5682S_I2S_DF_PCM_B (0x3) 829 | #define RT5682S_I2S_DF_PCM_A_N (0x6) 830 | #define RT5682S_I2S_DF_PCM_B_N (0x7) 831 | 832 | /* ADC/DAC Clock Control 1 (0x0073) */ 833 | #define RT5682S_ADC_OSR_MASK (0xf << 12) 834 | #define RT5682S_ADC_OSR_SFT 12 835 | #define RT5682S_ADC_OSR_D_1 (0x0 << 12) 836 | #define RT5682S_ADC_OSR_D_2 (0x1 << 12) 837 | #define RT5682S_ADC_OSR_D_4 (0x2 << 12) 838 | #define RT5682S_ADC_OSR_D_6 (0x3 << 12) 839 | #define RT5682S_ADC_OSR_D_8 (0x4 << 12) 840 | #define RT5682S_ADC_OSR_D_12 (0x5 << 12) 841 | #define RT5682S_ADC_OSR_D_16 (0x6 << 12) 842 | #define RT5682S_ADC_OSR_D_24 (0x7 << 12) 843 | #define RT5682S_ADC_OSR_D_32 (0x8 << 12) 844 | #define RT5682S_ADC_OSR_D_48 (0x9 << 12) 845 | #define RT5682S_I2S_M_D_MASK (0xf << 8) 846 | #define RT5682S_I2S_M_D_SFT 8 847 | #define RT5682S_I2S_M_D_1 (0x0 << 8) 848 | #define RT5682S_I2S_M_D_2 (0x1 << 8) 849 | #define RT5682S_I2S_M_D_3 (0x2 << 8) 850 | #define RT5682S_I2S_M_D_4 (0x3 << 8) 851 | #define RT5682S_I2S_M_D_6 (0x4 << 8) 852 | #define RT5682S_I2S_M_D_8 (0x5 << 8) 853 | #define RT5682S_I2S_M_D_12 (0x6 << 8) 854 | #define RT5682S_I2S_M_D_16 (0x7 << 8) 855 | #define RT5682S_I2S_M_D_24 (0x8 << 8) 856 | #define RT5682S_I2S_M_D_32 (0x9 << 8) 857 | #define RT5682S_I2S_M_D_48 (0x10 << 8) 858 | #define RT5682S_I2S_M_CLK_SRC_MASK (0x7 << 4) 859 | #define RT5682S_I2S_M_CLK_SRC_SFT 4 860 | #define RT5682S_DAC_OSR_MASK (0xf << 0) 861 | #define RT5682S_DAC_OSR_SFT 0 862 | #define RT5682S_DAC_OSR_D_1 (0x0 << 0) 863 | #define RT5682S_DAC_OSR_D_2 (0x1 << 0) 864 | #define RT5682S_DAC_OSR_D_4 (0x2 << 0) 865 | #define RT5682S_DAC_OSR_D_6 (0x3 << 0) 866 | #define RT5682S_DAC_OSR_D_8 (0x4 << 0) 867 | #define RT5682S_DAC_OSR_D_12 (0x5 << 0) 868 | #define RT5682S_DAC_OSR_D_16 (0x6 << 0) 869 | #define RT5682S_DAC_OSR_D_24 (0x7 << 0) 870 | #define RT5682S_DAC_OSR_D_32 (0x8 << 0) 871 | #define RT5682S_DAC_OSR_D_48 (0x9 << 0) 872 | 873 | /* ADC/DAC Clock Control 2 (0x0074) */ 874 | #define RT5682S_I2S2_BCLK_MS2_MASK (0x1 << 11) 875 | #define RT5682S_I2S2_BCLK_MS2_SFT 11 876 | #define RT5682S_I2S2_BCLK_MS2_32 (0x0 << 11) 877 | #define RT5682S_I2S2_BCLK_MS2_64 (0x1 << 11) 878 | 879 | 880 | /* TDM control 1 (0x0079) */ 881 | #define RT5682S_TDM_TX_CH_MASK (0x3 << 12) 882 | #define RT5682S_TDM_TX_CH_2 (0x0 << 12) 883 | #define RT5682S_TDM_TX_CH_4 (0x1 << 12) 884 | #define RT5682S_TDM_TX_CH_6 (0x2 << 12) 885 | #define RT5682S_TDM_TX_CH_8 (0x3 << 12) 886 | #define RT5682S_TDM_RX_CH_MASK (0x3 << 8) 887 | #define RT5682S_TDM_RX_CH_2 (0x0 << 8) 888 | #define RT5682S_TDM_RX_CH_4 (0x1 << 8) 889 | #define RT5682S_TDM_RX_CH_6 (0x2 << 8) 890 | #define RT5682S_TDM_RX_CH_8 (0x3 << 8) 891 | #define RT5682S_TDM_ADC_LCA_MASK (0x7 << 4) 892 | #define RT5682S_TDM_ADC_LCA_SFT 4 893 | #define RT5682S_TDM_ADC_DL_MASK (0x3 << 0) 894 | #define RT5682S_TDM_ADC_DL_SFT 0 895 | 896 | /* TDM control 2 (0x007a) */ 897 | #define RT5682S_IF1_ADC1_SEL_SFT 14 898 | #define RT5682S_IF1_ADC2_SEL_SFT 12 899 | #define RT5682S_IF1_ADC3_SEL_SFT 10 900 | #define RT5682S_IF1_ADC4_SEL_SFT 8 901 | #define RT5682S_TDM_ADC_SEL_SFT 3 902 | 903 | /* TDM control 3 (0x007b) */ 904 | #define RT5682S_TDM_EN (0x1 << 7) 905 | 906 | /* TDM/I2S control (0x007e) */ 907 | #define RT5682S_TDM_S_BP_MASK (0x1 << 15) 908 | #define RT5682S_TDM_S_BP_SFT 15 909 | #define RT5682S_TDM_S_BP_NOR (0x0 << 15) 910 | #define RT5682S_TDM_S_BP_INV (0x1 << 15) 911 | #define RT5682S_TDM_S_LP_MASK (0x1 << 14) 912 | #define RT5682S_TDM_S_LP_SFT 14 913 | #define RT5682S_TDM_S_LP_NOR (0x0 << 14) 914 | #define RT5682S_TDM_S_LP_INV (0x1 << 14) 915 | #define RT5682S_TDM_DF_MASK (0x7 << 11) 916 | #define RT5682S_TDM_DF_SFT 11 917 | #define RT5682S_TDM_DF_I2S (0x0 << 11) 918 | #define RT5682S_TDM_DF_LEFT (0x1 << 11) 919 | #define RT5682S_TDM_DF_PCM_A (0x2 << 11) 920 | #define RT5682S_TDM_DF_PCM_B (0x3 << 11) 921 | #define RT5682S_TDM_DF_PCM_A_N (0x6 << 11) 922 | #define RT5682S_TDM_DF_PCM_B_N (0x7 << 11) 923 | #define RT5682S_TDM_BCLK_MS1_MASK (0x3 << 8) 924 | #define RT5682S_TDM_BCLK_MS1_SFT 8 925 | #define RT5682S_TDM_BCLK_MS1_32 (0x0 << 8) 926 | #define RT5682S_TDM_BCLK_MS1_64 (0x1 << 8) 927 | #define RT5682S_TDM_BCLK_MS1_128 (0x2 << 8) 928 | #define RT5682S_TDM_BCLK_MS1_256 (0x3 << 8) 929 | #define RT5682S_TDM_BCLK_MS1_16 (0x4 << 8) 930 | #define RT5682S_TDM_CL_MASK (0x3 << 4) 931 | #define RT5682S_TDM_CL_16 (0x0 << 4) 932 | #define RT5682S_TDM_CL_20 (0x1 << 4) 933 | #define RT5682S_TDM_CL_24 (0x2 << 4) 934 | #define RT5682S_TDM_CL_32 (0x3 << 4) 935 | #define RT5682S_TDM_M_BP_MASK (0x1 << 2) 936 | #define RT5682S_TDM_M_BP_SFT 2 937 | #define RT5682S_TDM_M_BP_NOR (0x0 << 2) 938 | #define RT5682S_TDM_M_BP_INV (0x1 << 2) 939 | #define RT5682S_TDM_M_LP_MASK (0x1 << 1) 940 | #define RT5682S_TDM_M_LP_SFT 1 941 | #define RT5682S_TDM_M_LP_NOR (0x0 << 1) 942 | #define RT5682S_TDM_M_LP_INV (0x1 << 1) 943 | #define RT5682S_TDM_MS_MASK (0x1 << 0) 944 | #define RT5682S_TDM_MS_SFT 0 945 | #define RT5682S_TDM_MS_S (0x0 << 0) 946 | #define RT5682S_TDM_MS_M (0x1 << 0) 947 | 948 | /* Global Clock Control (0x0080) */ 949 | #define RT5682S_SCLK_SRC_MASK (0x7 << 13) 950 | #define RT5682S_SCLK_SRC_SFT 13 951 | #define RT5682S_PLL_SRC_MASK (0x3 << 8) 952 | #define RT5682S_PLL_SRC_SFT 8 953 | #define RT5682S_PLL_SRC_MCLK (0x0 << 8) 954 | #define RT5682S_PLL_SRC_BCLK1 (0x1 << 8) 955 | #define RT5682S_PLL_SRC_RC (0x3 << 8) 956 | 957 | /* PLL tracking mode 1 (0x0083) */ 958 | #define RT5682S_DA_ASRC_MASK (0x1 << 13) 959 | #define RT5682S_DA_ASRC_SFT 13 960 | #define RT5682S_DAC_STO1_ASRC_MASK (0x1 << 12) 961 | #define RT5682S_DAC_STO1_ASRC_SFT 12 962 | #define RT5682S_AD_ASRC_MASK (0x1 << 8) 963 | #define RT5682S_AD_ASRC_SFT 8 964 | #define RT5682S_AD_ASRC_SEL_MASK (0x1 << 4) 965 | #define RT5682S_AD_ASRC_SEL_SFT 4 966 | #define RT5682S_DMIC_ASRC_MASK (0x1 << 3) 967 | #define RT5682S_DMIC_ASRC_SFT 3 968 | #define RT5682S_ADC_STO1_ASRC_MASK (0x1 << 2) 969 | #define RT5682S_ADC_STO1_ASRC_SFT 2 970 | #define RT5682S_DA_ASRC_SEL_MASK (0x1 << 0) 971 | #define RT5682S_DA_ASRC_SEL_SFT 0 972 | 973 | /* PLL tracking mode 2 3 (0x0084)(0x0085)*/ 974 | #define RT5682S_FILTER_CLK_SEL_MASK (0x7 << 12) 975 | #define RT5682S_FILTER_CLK_SEL_SFT 12 976 | #define RT5682S_FILTER_CLK_DIV_MASK (0xf << 8) 977 | #define RT5682S_FILTER_CLK_DIV_SFT 8 978 | 979 | /* ASRC Control 4 (0x0086) */ 980 | #define RT5682S_ASRCIN_FTK_N1_MASK (0x3 << 14) 981 | #define RT5682S_ASRCIN_FTK_N1_SFT 14 982 | #define RT5682S_ASRCIN_FTK_N2_MASK (0x3 << 12) 983 | #define RT5682S_ASRCIN_FTK_N2_SFT 12 984 | #define RT5682S_ASRCIN_FTK_M1_MASK (0x7 << 8) 985 | #define RT5682S_ASRCIN_FTK_M1_SFT 8 986 | #define RT5682S_ASRCIN_FTK_M2_MASK (0x7 << 4) 987 | #define RT5682S_ASRCIN_FTK_M2_SFT 4 988 | 989 | /* ASRC Control 11 (0x008c) */ 990 | #define RT5682S_ASRCIN_AUTO_CLKOUT_MASK (0x1 << 5) 991 | #define RT5682S_ASRCIN_AUTO_CLKOUT_EN (0x1 << 5) 992 | #define RT5682S_ASRCIN_AUTO_CLKOUT_DIS (0x0 << 5) 993 | #define RT5682S_ASRCIN_AUTO_RST_MASK (0x1 << 4) 994 | #define RT5682S_ASRCIN_AUTO_RST_EN (0x1 << 4) 995 | #define RT5682S_ASRCIN_AUTO_RST_DIS (0x0 << 4) 996 | #define RT5682S_SEL_LRCK_DET_MASK (0x3) 997 | #define RT5682S_SEL_LRCK_DET_DIV8 (0x3) 998 | #define RT5682S_SEL_LRCK_DET_DIV4 (0x2) 999 | #define RT5682S_SEL_LRCK_DET_DIV2 (0x1) 1000 | #define RT5682S_SEL_LRCK_DET_DIV1 (0x0) 1001 | 1002 | /* Depop Mode Control 1 (0x008e) */ 1003 | #define RT5682S_OUT_HP_L_EN (0x1 << 6) 1004 | #define RT5682S_OUT_HP_R_EN (0x1 << 5) 1005 | #define RT5682S_LDO_PUMP_EN (0x1 << 4) 1006 | #define RT5682S_LDO_PUMP_EN_SFT 4 1007 | #define RT5682S_PUMP_EN (0x1 << 3) 1008 | #define RT5682S_PUMP_EN_SFT 3 1009 | #define RT5682S_CAPLESS_L_EN (0x1 << 1) 1010 | #define RT5682S_CAPLESS_L_EN_SFT 1 1011 | #define RT5682S_CAPLESS_R_EN (0x1 << 0) 1012 | #define RT5682S_CAPLESS_R_EN_SFT 0 1013 | 1014 | /* Depop Mode Control 2 (0x8f) */ 1015 | #define RT5682S_RAMP_MASK (0x1 << 12) 1016 | #define RT5682S_RAMP_SFT 12 1017 | #define RT5682S_RAMP_DIS (0x0 << 12) 1018 | #define RT5682S_RAMP_EN (0x1 << 12) 1019 | #define RT5682S_BPS_MASK (0x1 << 11) 1020 | #define RT5682S_BPS_SFT 11 1021 | #define RT5682S_BPS_DIS (0x0 << 11) 1022 | #define RT5682S_BPS_EN (0x1 << 11) 1023 | #define RT5682S_FAST_UPDN_MASK (0x1 << 10) 1024 | #define RT5682S_FAST_UPDN_SFT 10 1025 | #define RT5682S_FAST_UPDN_DIS (0x0 << 10) 1026 | #define RT5682S_FAST_UPDN_EN (0x1 << 10) 1027 | #define RT5682S_VLO_MASK (0x1 << 7) 1028 | #define RT5682S_VLO_SFT 7 1029 | #define RT5682S_VLO_3V (0x0 << 7) 1030 | #define RT5682S_VLO_33V (0x1 << 7) 1031 | 1032 | /* HPOUT charge pump 1 (0x0091) */ 1033 | #define RT5682S_OSW_L_MASK (0x1 << 11) 1034 | #define RT5682S_OSW_L_SFT 11 1035 | #define RT5682S_OSW_L_DIS (0x0 << 11) 1036 | #define RT5682S_OSW_L_EN (0x1 << 11) 1037 | #define RT5682S_OSW_R_MASK (0x1 << 10) 1038 | #define RT5682S_OSW_R_SFT 10 1039 | #define RT5682S_OSW_R_DIS (0x0 << 10) 1040 | #define RT5682S_OSW_R_EN (0x1 << 10) 1041 | #define RT5682S_PM_HP_MASK (0x3 << 8) 1042 | #define RT5682S_PM_HP_SFT 8 1043 | #define RT5682S_PM_HP_LV (0x0 << 8) 1044 | #define RT5682S_PM_HP_MV (0x1 << 8) 1045 | #define RT5682S_PM_HP_HV (0x2 << 8) 1046 | 1047 | /* Micbias Control1 (0x93) */ 1048 | #define RT5682S_MIC1_OV_MASK (0x3 << 14) 1049 | #define RT5682S_MIC1_OV_SFT 14 1050 | #define RT5682S_MIC1_OV_2V7 (0x0 << 14) 1051 | #define RT5682S_MIC1_OV_2V4 (0x1 << 14) 1052 | #define RT5682S_MIC1_OV_2V25 (0x3 << 14) 1053 | #define RT5682S_MIC1_OV_1V8 (0x4 << 14) 1054 | #define RT5682S_MIC2_OV_MASK (0x3 << 8) 1055 | #define RT5682S_MIC2_OV_SFT 8 1056 | #define RT5682S_MIC2_OV_2V7 (0x0 << 8) 1057 | #define RT5682S_MIC2_OV_2V4 (0x1 << 8) 1058 | #define RT5682S_MIC2_OV_2V25 (0x3 << 8) 1059 | #define RT5682S_MIC2_OV_1V8 (0x4 << 8) 1060 | 1061 | /* Micbias Control2 (0x0094) */ 1062 | #define RT5682S_PWR_CLK25M_MASK (0x1 << 9) 1063 | #define RT5682S_PWR_CLK25M_SFT 9 1064 | #define RT5682S_PWR_CLK25M_PD (0x0 << 9) 1065 | #define RT5682S_PWR_CLK25M_PU (0x1 << 9) 1066 | #define RT5682S_PWR_CLK1M_MASK (0x1 << 8) 1067 | #define RT5682S_PWR_CLK1M_SFT 8 1068 | #define RT5682S_PWR_CLK1M_PD (0x0 << 8) 1069 | #define RT5682S_PWR_CLK1M_PU (0x1 << 8) 1070 | 1071 | /* PLL M/N/K Code Control 1 (0x0098) */ 1072 | #define RT5682S_PLLA_N_MASK (0x1ff << 0) 1073 | 1074 | /* PLL M/N/K Code Control 2 (0x0099) */ 1075 | #define RT5682S_PLLA_M_MASK (0x1f << 8) 1076 | #define RT5682S_PLLA_M_SFT 8 1077 | #define RT5682S_PLLA_K_MASK (0x1f << 0) 1078 | 1079 | /* PLL M/N/K Code Control 3 (0x009a) */ 1080 | #define RT5682S_PLLB_N_MASK (0x3ff << 0) 1081 | 1082 | /* PLL M/N/K Code Control 4 (0x009b) */ 1083 | #define RT5682S_PLLB_M_MASK (0x1f << 8) 1084 | #define RT5682S_PLLB_M_SFT 8 1085 | #define RT5682S_PLLB_K_MASK (0x1f << 0) 1086 | 1087 | /* PLL M/N/K Code Control 6 (0x009d) */ 1088 | #define RT5682S_PLLB_SEL_PS_MASK (0x1 << 13) 1089 | #define RT5682S_PLLB_SEL_PS_SFT 13 1090 | #define RT5682S_PLLB_BYP_PS_MASK (0x1 << 12) 1091 | #define RT5682S_PLLB_BYP_PS_SFT 12 1092 | #define RT5682S_PLLB_M_BP_MASK (0x1 << 11) 1093 | #define RT5682S_PLLB_M_BP_SFT 11 1094 | #define RT5682S_PLLB_K_BP_MASK (0x1 << 10) 1095 | #define RT5682S_PLLB_K_BP_SFT 10 1096 | #define RT5682S_PLLA_M_BP_MASK (0x1 << 7) 1097 | #define RT5682S_PLLA_M_BP_SFT 7 1098 | #define RT5682S_PLLA_K_BP_MASK (0x1 << 6) 1099 | #define RT5682S_PLLA_K_BP_SFT 6 1100 | 1101 | /* PLL M/N/K Code Control 7 (0x009e) */ 1102 | #define RT5682S_PLLB_SRC_MASK (0x1) 1103 | #define RT5682S_PLLB_SRC_DFIN (0x1) 1104 | #define RT5682S_PLLB_SRC_PLLA (0x0) 1105 | 1106 | /* RC Clock Control (0x009f) */ 1107 | #define RT5682S_POW_IRQ (0x1 << 15) 1108 | #define RT5682S_POW_JDH (0x1 << 14) 1109 | 1110 | /* I2S2 Master Mode Clock Control 1 (0x00a0) */ 1111 | #define RT5682S_I2S2_M_CLK_SRC_MASK (0x7 << 4) 1112 | #define RT5682S_I2S2_M_CLK_SRC_SFT 4 1113 | #define RT5682S_I2S2_M_D_MASK (0xf << 0) 1114 | #define RT5682S_I2S2_M_D_1 (0x0) 1115 | #define RT5682S_I2S2_M_D_2 (0x1) 1116 | #define RT5682S_I2S2_M_D_3 (0x2) 1117 | #define RT5682S_I2S2_M_D_4 (0x3) 1118 | #define RT5682S_I2S2_M_D_6 (0x4) 1119 | #define RT5682S_I2S2_M_D_8 (0x5) 1120 | #define RT5682S_I2S2_M_D_12 (0x6) 1121 | #define RT5682S_I2S2_M_D_16 (0x7) 1122 | #define RT5682S_I2S2_M_D_24 (0x8) 1123 | #define RT5682S_I2S2_M_D_32 (0x9) 1124 | #define RT5682S_I2S2_M_D_48 (0xa) 1125 | #define RT5682S_I2S2_M_D_SFT 0 1126 | 1127 | /* IRQ Control 1 (0x00b6) */ 1128 | #define RT5682S_JD1_PULSE_EN_MASK (0x1 << 10) 1129 | #define RT5682S_JD1_PULSE_EN_SFT 10 1130 | #define RT5682S_JD1_PULSE_DIS (0x0 << 10) 1131 | #define RT5682S_JD1_PULSE_EN (0x1 << 10) 1132 | 1133 | /* IRQ Control 2 (0x00b7) */ 1134 | #define RT5682S_JD1_EN_MASK (0x1 << 15) 1135 | #define RT5682S_JD1_EN_SFT 15 1136 | #define RT5682S_JD1_DIS (0x0 << 15) 1137 | #define RT5682S_JD1_EN (0x1 << 15) 1138 | #define RT5682S_JD1_POL_MASK (0x1 << 13) 1139 | #define RT5682S_JD1_POL_NOR (0x0 << 13) 1140 | #define RT5682S_JD1_POL_INV (0x1 << 13) 1141 | #define RT5682S_JD1_IRQ_MASK (0x1 << 10) 1142 | #define RT5682S_JD1_IRQ_LEV (0x0 << 10) 1143 | #define RT5682S_JD1_IRQ_PUL (0x1 << 10) 1144 | 1145 | /* IRQ Control 3 (0x00b8) */ 1146 | #define RT5682S_IL_IRQ_MASK (0x1 << 7) 1147 | #define RT5682S_IL_IRQ_DIS (0x0 << 7) 1148 | #define RT5682S_IL_IRQ_EN (0x1 << 7) 1149 | #define RT5682S_IL_IRQ_TYPE_MASK (0x1 << 4) 1150 | #define RT5682S_IL_IRQ_LEV (0x0 << 4) 1151 | #define RT5682S_IL_IRQ_PUL (0x1 << 4) 1152 | 1153 | /* GPIO Control 1 (0x00c0) */ 1154 | #define RT5682S_GP1_PIN_MASK (0x3 << 14) 1155 | #define RT5682S_GP1_PIN_SFT 14 1156 | #define RT5682S_GP1_PIN_GPIO1 (0x0 << 14) 1157 | #define RT5682S_GP1_PIN_IRQ (0x1 << 14) 1158 | #define RT5682S_GP1_PIN_DMIC_CLK (0x2 << 14) 1159 | #define RT5682S_GP2_PIN_MASK (0x3 << 12) 1160 | #define RT5682S_GP2_PIN_SFT 12 1161 | #define RT5682S_GP2_PIN_GPIO2 (0x0 << 12) 1162 | #define RT5682S_GP2_PIN_LRCK2 (0x1 << 12) 1163 | #define RT5682S_GP2_PIN_DMIC_SDA (0x2 << 12) 1164 | #define RT5682S_GP3_PIN_MASK (0x3 << 10) 1165 | #define RT5682S_GP3_PIN_SFT 10 1166 | #define RT5682S_GP3_PIN_GPIO3 (0x0 << 10) 1167 | #define RT5682S_GP3_PIN_BCLK2 (0x1 << 10) 1168 | #define RT5682S_GP3_PIN_DMIC_CLK (0x2 << 10) 1169 | #define RT5682S_GP4_PIN_MASK (0x3 << 8) 1170 | #define RT5682S_GP4_PIN_SFT 8 1171 | #define RT5682S_GP4_PIN_GPIO4 (0x0 << 8) 1172 | #define RT5682S_GP4_PIN_ADCDAT1 (0x1 << 8) 1173 | #define RT5682S_GP4_PIN_DMIC_CLK (0x2 << 8) 1174 | #define RT5682S_GP4_PIN_ADCDAT2 (0x3 << 8) 1175 | #define RT5682S_GP5_PIN_MASK (0x3 << 6) 1176 | #define RT5682S_GP5_PIN_SFT 6 1177 | #define RT5682S_GP5_PIN_GPIO5 (0x0 << 6) 1178 | #define RT5682S_GP5_PIN_DACDAT1 (0x1 << 6) 1179 | #define RT5682S_GP5_PIN_DMIC_SDA (0x2 << 6) 1180 | #define RT5682S_GP6_PIN_MASK (0x1 << 5) 1181 | #define RT5682S_GP6_PIN_SFT 5 1182 | #define RT5682S_GP6_PIN_GPIO6 (0x0 << 5) 1183 | #define RT5682S_GP6_PIN_LRCK1 (0x1 << 5) 1184 | 1185 | /* GPIO Control 2 (0x00c1)*/ 1186 | #define RT5682S_GP1_PF_MASK (0x1 << 15) 1187 | #define RT5682S_GP1_PF_IN (0x0 << 15) 1188 | #define RT5682S_GP1_PF_OUT (0x1 << 15) 1189 | #define RT5682S_GP1_OUT_MASK (0x1 << 14) 1190 | #define RT5682S_GP1_OUT_L (0x0 << 14) 1191 | #define RT5682S_GP1_OUT_H (0x1 << 14) 1192 | #define RT5682S_GP2_PF_MASK (0x1 << 13) 1193 | #define RT5682S_GP2_PF_IN (0x0 << 13) 1194 | #define RT5682S_GP2_PF_OUT (0x1 << 13) 1195 | #define RT5682S_GP2_OUT_MASK (0x1 << 12) 1196 | #define RT5682S_GP2_OUT_L (0x0 << 12) 1197 | #define RT5682S_GP2_OUT_H (0x1 << 12) 1198 | #define RT5682S_GP3_PF_MASK (0x1 << 11) 1199 | #define RT5682S_GP3_PF_IN (0x0 << 11) 1200 | #define RT5682S_GP3_PF_OUT (0x1 << 11) 1201 | #define RT5682S_GP3_OUT_MASK (0x1 << 10) 1202 | #define RT5682S_GP3_OUT_L (0x0 << 10) 1203 | #define RT5682S_GP3_OUT_H (0x1 << 10) 1204 | #define RT5682S_GP4_PF_MASK (0x1 << 9) 1205 | #define RT5682S_GP4_PF_IN (0x0 << 9) 1206 | #define RT5682S_GP4_PF_OUT (0x1 << 9) 1207 | #define RT5682S_GP4_OUT_MASK (0x1 << 8) 1208 | #define RT5682S_GP4_OUT_L (0x0 << 8) 1209 | #define RT5682S_GP4_OUT_H (0x1 << 8) 1210 | #define RT5682S_GP5_PF_MASK (0x1 << 7) 1211 | #define RT5682S_GP5_PF_IN (0x0 << 7) 1212 | #define RT5682S_GP5_PF_OUT (0x1 << 7) 1213 | #define RT5682S_GP5_OUT_MASK (0x1 << 6) 1214 | #define RT5682S_GP5_OUT_L (0x0 << 6) 1215 | #define RT5682S_GP5_OUT_H (0x1 << 6) 1216 | #define RT5682S_GP6_PF_MASK (0x1 << 5) 1217 | #define RT5682S_GP6_PF_IN (0x0 << 5) 1218 | #define RT5682S_GP6_PF_OUT (0x1 << 5) 1219 | #define RT5682S_GP6_OUT_MASK (0x1 << 4) 1220 | #define RT5682S_GP6_OUT_L (0x0 << 4) 1221 | #define RT5682S_GP6_OUT_H (0x1 << 4) 1222 | 1223 | /* GPIO Status (0x00c2) */ 1224 | #define RT5682S_GP6_ST (0x1 << 6) 1225 | #define RT5682S_GP5_ST (0x1 << 5) 1226 | #define RT5682S_GP4_ST (0x1 << 4) 1227 | #define RT5682S_GP3_ST (0x1 << 3) 1228 | #define RT5682S_GP2_ST (0x1 << 2) 1229 | #define RT5682S_GP1_ST (0x1 << 1) 1230 | 1231 | /* Soft volume and zero cross control 1 (0x00d9) */ 1232 | #define RT5682S_ZCD_MASK (0x1 << 10) 1233 | #define RT5682S_ZCD_SFT 10 1234 | #define RT5682S_ZCD_PD (0x0 << 10) 1235 | #define RT5682S_ZCD_PU (0x1 << 10) 1236 | 1237 | /* 4 Button Inline Command Control 2 (0x00e3) */ 1238 | #define RT5682S_4BTN_IL_MASK (0x1 << 15) 1239 | #define RT5682S_4BTN_IL_EN (0x1 << 15) 1240 | #define RT5682S_4BTN_IL_DIS (0x0 << 15) 1241 | #define RT5682S_4BTN_IL_RST_MASK (0x1 << 14) 1242 | #define RT5682S_4BTN_IL_NOR (0x1 << 14) 1243 | #define RT5682S_4BTN_IL_RST (0x0 << 14) 1244 | 1245 | /* 4 Button Inline Command Control 3~6 (0x00e5~0x00e8) */ 1246 | #define RT5682S_4BTN_IL_HOLD_WIN_MASK (0x7f << 8) 1247 | #define RT5682S_4BTN_IL_HOLD_WIN_SFT 8 1248 | #define RT5682S_4BTN_IL_CLICK_WIN_MASK (0x7f) 1249 | #define RT5682S_4BTN_IL_CLICK_WIN_SFT 0 1250 | 1251 | /* Analog JD Control (0x00f0) */ 1252 | #define RT5682S_JDH_RS_MASK (0x1 << 4) 1253 | #define RT5682S_JDH_NO_PLUG (0x1 << 4) 1254 | #define RT5682S_JDH_PLUG (0x0 << 4) 1255 | 1256 | /* Charge Pump Internal Register1 (0x0125) */ 1257 | #define RT5682S_CP_CLK_HP_MASK (0x3 << 4) 1258 | #define RT5682S_CP_CLK_HP_100KHZ (0x0 << 4) 1259 | #define RT5682S_CP_CLK_HP_200KHZ (0x1 << 4) 1260 | #define RT5682S_CP_CLK_HP_300KHZ (0x2 << 4) 1261 | #define RT5682S_CP_CLK_HP_600KHZ (0x3 << 4) 1262 | 1263 | /* Pad Driving Control (0x0136) */ 1264 | #define RT5682S_PAD_DRV_GP1_MASK (0x1 << 14) 1265 | #define RT5682S_PAD_DRV_GP1_HIGH (0x1 << 14) 1266 | #define RT5682S_PAD_DRV_GP1_LOW (0x0 << 14) 1267 | #define RT5682S_PAD_DRV_GP2_MASK (0x1 << 12) 1268 | #define RT5682S_PAD_DRV_GP2_HIGH (0x1 << 12) 1269 | #define RT5682S_PAD_DRV_GP2_LOW (0x0 << 12) 1270 | #define RT5682S_PAD_DRV_GP3_MASK (0x1 << 10) 1271 | #define RT5682S_PAD_DRV_GP3_HIGH (0x1 << 10) 1272 | #define RT5682S_PAD_DRV_GP3_LOW (0x0 << 10) 1273 | #define RT5682S_PAD_DRV_GP4_MASK (0x1 << 8) 1274 | #define RT5682S_PAD_DRV_GP4_HIGH (0x1 << 8) 1275 | #define RT5682S_PAD_DRV_GP4_LOW (0x0 << 8) 1276 | #define RT5682S_PAD_DRV_GP5_MASK (0x1 << 6) 1277 | #define RT5682S_PAD_DRV_GP5_HIGH (0x1 << 6) 1278 | #define RT5682S_PAD_DRV_GP5_LOW (0x0 << 6) 1279 | #define RT5682S_PAD_DRV_GP6_MASK (0x1 << 4) 1280 | #define RT5682S_PAD_DRV_GP6_HIGH (0x1 << 4) 1281 | #define RT5682S_PAD_DRV_GP6_LOW (0x0 << 4) 1282 | 1283 | /* Chopper and Clock control for DAC (0x013a)*/ 1284 | #define RT5682S_CKXEN_DAC1_MASK (0x1 << 13) 1285 | #define RT5682S_CKXEN_DAC1_SFT 13 1286 | #define RT5682S_CKGEN_DAC1_MASK (0x1 << 12) 1287 | #define RT5682S_CKGEN_DAC1_SFT 12 1288 | 1289 | /* Chopper and Clock control for ADC (0x013b)*/ 1290 | #define RT5682S_CKXEN_ADC1_MASK (0x1 << 13) 1291 | #define RT5682S_CKXEN_ADC1_SFT 13 1292 | #define RT5682S_CKGEN_ADC1_MASK (0x1 << 12) 1293 | #define RT5682S_CKGEN_ADC1_SFT 12 1294 | 1295 | /* Volume test (0x013f)*/ 1296 | #define RT5682S_SEL_CLK_VOL_MASK (0x1 << 15) 1297 | #define RT5682S_SEL_CLK_VOL_EN (0x1 << 15) 1298 | #define RT5682S_SEL_CLK_VOL_DIS (0x0 << 15) 1299 | 1300 | /* Test Mode Control 1 (0x0145) */ 1301 | #define RT5682S_AD2DA_LB_MASK (0x1 << 10) 1302 | #define RT5682S_AD2DA_LB_SFT 10 1303 | 1304 | /* Stereo Noise Gate Control 1 (0x0160) */ 1305 | #define RT5682S_NG2_EN_MASK (0x1 << 15) 1306 | #define RT5682S_NG2_EN (0x1 << 15) 1307 | #define RT5682S_NG2_DIS (0x0 << 15) 1308 | 1309 | /* Stereo1 DAC Silence Detection Control (0x0190) */ 1310 | #define RT5682S_DEB_STO_DAC_MASK (0x7 << 4) 1311 | #define RT5682S_DEB_80_MS (0x0 << 4) 1312 | 1313 | /* HP Behavior Logic Control 2 (0x01db) */ 1314 | #define RT5682S_HP_SIG_SRC_MASK (0x3) 1315 | #define RT5682S_HP_SIG_SRC_1BIT_CTL (0x3) 1316 | #define RT5682S_HP_SIG_SRC_REG (0x2) 1317 | #define RT5682S_HP_SIG_SRC_IMPE_REG (0x1) 1318 | #define RT5682S_HP_SIG_SRC_DC_CALI (0x0) 1319 | 1320 | /* SAR ADC Inline Command Control 1 (0x0210) */ 1321 | #define RT5682S_SAR_BUTDET_MASK (0x1 << 15) 1322 | #define RT5682S_SAR_BUTDET_EN (0x1 << 15) 1323 | #define RT5682S_SAR_BUTDET_DIS (0x0 << 15) 1324 | #define RT5682S_SAR_BUTDET_POW_MASK (0x1 << 14) 1325 | #define RT5682S_SAR_BUTDET_POW_SAV (0x1 << 14) 1326 | #define RT5682S_SAR_BUTDET_POW_NORM (0x0 << 14) 1327 | #define RT5682S_SAR_BUTDET_RST_MASK (0x1 << 13) 1328 | #define RT5682S_SAR_BUTDET_RST_NORM (0x1 << 13) 1329 | #define RT5682S_SAR_BUTDET_RST (0x0 << 13) 1330 | #define RT5682S_SAR_POW_MASK (0x1 << 12) 1331 | #define RT5682S_SAR_POW_EN (0x1 << 12) 1332 | #define RT5682S_SAR_POW_DIS (0x0 << 12) 1333 | #define RT5682S_SAR_RST_MASK (0x1 << 11) 1334 | #define RT5682S_SAR_RST_NORMAL (0x1 << 11) 1335 | #define RT5682S_SAR_RST (0x0 << 11) 1336 | #define RT5682S_SAR_BYPASS_MASK (0x1 << 10) 1337 | #define RT5682S_SAR_BYPASS_EN (0x1 << 10) 1338 | #define RT5682S_SAR_BYPASS_DIS (0x0 << 10) 1339 | #define RT5682S_SAR_SEL_MB1_2_MASK (0x3 << 8) 1340 | #define RT5682S_SAR_SEL_MB1_2_SFT 8 1341 | #define RT5682S_SAR_SEL_MODE_MASK (0x1 << 7) 1342 | #define RT5682S_SAR_SEL_MODE_CMP (0x1 << 7) 1343 | #define RT5682S_SAR_SEL_MODE_ADC (0x0 << 7) 1344 | #define RT5682S_SAR_SEL_MB1_2_CTL_MASK (0x1 << 5) 1345 | #define RT5682S_SAR_SEL_MB1_2_AUTO (0x1 << 5) 1346 | #define RT5682S_SAR_SEL_MB1_2_MANU (0x0 << 5) 1347 | #define RT5682S_SAR_SEL_SIGNAL_MASK (0x1 << 4) 1348 | #define RT5682S_SAR_SEL_SIGNAL_AUTO (0x1 << 4) 1349 | #define RT5682S_SAR_SEL_SIGNAL_MANU (0x0 << 4) 1350 | 1351 | /* SAR ADC Inline Command Control 2 (0x0211) */ 1352 | #define RT5682S_SAR_ADC_PSV_MASK (0x1 << 4) 1353 | #define RT5682S_SAR_ADC_PSV_ENTRY (0x1 << 4) 1354 | 1355 | 1356 | /* SAR ADC Inline Command Control 13 (0x021c) */ 1357 | #define RT5682S_SAR_SOUR_MASK (0x3f) 1358 | #define RT5682S_SAR_SOUR_BTN (0x3f) 1359 | #define RT5682S_SAR_SOUR_TYPE (0x0) 1360 | 1361 | /* Headphone Amp Detection Control 1 (0x3b00) */ 1362 | #define RT5682S_CP_SW_SIZE_MASK (0x7 << 4) 1363 | #define RT5682S_CP_SW_SIZE_L (0x4 << 4) 1364 | #define RT5682S_CP_SW_SIZE_M (0x2 << 4) 1365 | #define RT5682S_CP_SW_SIZE_S (0x1 << 4) 1366 | 1367 | #define RT5682S_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1368 | #define RT5682S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1369 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1370 | 1371 | /* System Clock Source */ 1372 | enum { 1373 | RT5682S_SCLK_S_MCLK, 1374 | RT5682S_SCLK_S_PLL1, 1375 | RT5682S_SCLK_S_PLL2, 1376 | RT5682S_SCLK_S_RCCLK, 1377 | }; 1378 | 1379 | /* PLL Source */ 1380 | enum { 1381 | RT5682S_PLL_S_MCLK, 1382 | RT5682S_PLL_S_BCLK1, 1383 | RT5682S_PLL_S_BCLK2, 1384 | RT5682S_PLL_S_RCCLK, 1385 | }; 1386 | 1387 | enum { 1388 | RT5682S_PLL1, 1389 | RT5682S_PLL2, 1390 | RT5682S_PLLS, 1391 | }; 1392 | 1393 | enum { 1394 | RT5682S_AIF1, 1395 | RT5682S_AIF2, 1396 | RT5682S_AIFS 1397 | }; 1398 | 1399 | /* filter mask */ 1400 | enum { 1401 | RT5682S_DA_STEREO1_FILTER = 0x1, 1402 | RT5682S_AD_STEREO1_FILTER = (0x1 << 1), 1403 | }; 1404 | 1405 | enum { 1406 | RT5682S_CLK_SEL_SYS, 1407 | RT5682S_CLK_SEL_I2S1_ASRC, 1408 | RT5682S_CLK_SEL_I2S2_ASRC, 1409 | }; 1410 | 1411 | enum { 1412 | USE_PLLA, 1413 | USE_PLLB, 1414 | USE_PLLAB, 1415 | }; 1416 | 1417 | struct pll_calc_map { 1418 | unsigned int freq_in; 1419 | unsigned int freq_out; 1420 | int m; 1421 | int n; 1422 | int k; 1423 | BOOLEAN m_bp; 1424 | BOOLEAN k_bp; 1425 | BOOLEAN byp_ps; 1426 | BOOLEAN sel_ps; 1427 | }; 1428 | 1429 | #endif -------------------------------------------------------------------------------- /rt5682s/rt5682s.c: -------------------------------------------------------------------------------- 1 | #define DESCRIPTOR_DEF 2 | #include "rt5682s.h" 3 | #include "registers.h" 4 | 5 | #define bool int 6 | #define MHz 1000000 7 | 8 | static ULONG Rt5682DebugLevel = 100; 9 | static ULONG Rt5682DebugCatagories = DBG_INIT || DBG_PNP || DBG_IOCTL; 10 | 11 | NTSTATUS rt5682s_set_component_pll(PRTEK_CONTEXT pDevice, 12 | int pll_id, int source, unsigned int freq_in, 13 | unsigned int freq_out); 14 | NTSTATUS rt5682s_set_tdm_slot(PRTEK_CONTEXT pDevice, unsigned int tx_mask, 15 | unsigned int rx_mask, int slots, int slot_width); 16 | NTSTATUS rt5682s_set_component_sysclk(PRTEK_CONTEXT pDevice, 17 | int clk_id); 18 | void rt5682s_update_reclock(IN PRTEK_CONTEXT pDevice); 19 | 20 | unsigned int __sw_hweight32(unsigned int w) 21 | { 22 | w -= (w >> 1) & 0x55555555; 23 | w = (w & 0x33333333) + ((w >> 2) & 0x33333333); 24 | w = (w + (w >> 4)) & 0x0f0f0f0f; 25 | return (w * 0x01010101) >> 24; 26 | } 27 | 28 | #define hweight_long __sw_hweight32 29 | 30 | NTSTATUS 31 | DriverEntry( 32 | __in PDRIVER_OBJECT DriverObject, 33 | __in PUNICODE_STRING RegistryPath 34 | ) 35 | { 36 | NTSTATUS status = STATUS_SUCCESS; 37 | WDF_DRIVER_CONFIG config; 38 | WDF_OBJECT_ATTRIBUTES attributes; 39 | 40 | RtekPrint(DEBUG_LEVEL_INFO, DBG_INIT, 41 | "Driver Entry\n"); 42 | 43 | WDF_DRIVER_CONFIG_INIT(&config, Rt5682EvtDeviceAdd); 44 | 45 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 46 | 47 | // 48 | // Create a framework driver object to represent our driver. 49 | // 50 | 51 | status = WdfDriverCreate(DriverObject, 52 | RegistryPath, 53 | &attributes, 54 | &config, 55 | WDF_NO_HANDLE 56 | ); 57 | 58 | if (!NT_SUCCESS(status)) 59 | { 60 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_INIT, 61 | "WdfDriverCreate failed with status 0x%x\n", status); 62 | } 63 | 64 | return status; 65 | } 66 | 67 | 68 | static NTSTATUS rt5682s_reg_write(PRTEK_CONTEXT pDevice, uint16_t reg, uint16_t data) 69 | { 70 | uint16_t rawdata[2]; 71 | rawdata[0] = RtlUshortByteSwap(reg); 72 | rawdata[1] = RtlUshortByteSwap(data); 73 | return SpbWriteDataSynchronously(&pDevice->I2CContext, rawdata, sizeof(rawdata)); 74 | } 75 | 76 | static NTSTATUS rt5682s_reg_read(PRTEK_CONTEXT pDevice, uint16_t reg, uint16_t* data) 77 | { 78 | uint16_t reg_swap = RtlUshortByteSwap(reg); 79 | uint16_t data_swap = 0; 80 | NTSTATUS ret = SpbXferDataSynchronously(&pDevice->I2CContext, ®_swap, sizeof(uint16_t), &data_swap, sizeof(uint16_t)); 81 | *data = RtlUshortByteSwap(data_swap); 82 | return ret; 83 | } 84 | 85 | static NTSTATUS rt5682s_reg_update( 86 | _In_ PRTEK_CONTEXT pDevice, 87 | uint16_t reg, 88 | uint16_t mask, 89 | uint16_t val 90 | ) { 91 | uint16_t tmp = 0, orig = 0; 92 | 93 | NTSTATUS status = rt5682s_reg_read(pDevice, reg, &orig); 94 | if (!NT_SUCCESS(status)) { 95 | return status; 96 | } 97 | 98 | tmp = orig & ~mask; 99 | tmp |= val & mask; 100 | 101 | if (tmp != orig) { 102 | status = rt5682s_reg_write(pDevice, reg, tmp); 103 | } 104 | return status; 105 | } 106 | 107 | static NTSTATUS rt5682s_reg_burstWrite(PRTEK_CONTEXT pDevice, struct reg* regs, int regCount) { 108 | NTSTATUS status = STATUS_NO_MEMORY; 109 | for (int i = 0; i < regCount; i++) { 110 | struct reg* regToSet = ®s[i]; 111 | status = rt5682s_reg_write(pDevice, regToSet->reg, regToSet->val); 112 | if (!NT_SUCCESS(status)) { 113 | return status; 114 | } 115 | } 116 | return status; 117 | } 118 | 119 | static Platform GetPlatform() { 120 | int cpuinfo[4]; 121 | __cpuidex(cpuinfo, 0, 0); 122 | 123 | int temp = cpuinfo[2]; 124 | cpuinfo[2] = cpuinfo[3]; 125 | cpuinfo[3] = temp; 126 | 127 | char vendorName[13]; 128 | RtlZeroMemory(vendorName, 13); 129 | memcpy(vendorName, &cpuinfo[1], 12); 130 | 131 | __cpuidex(cpuinfo, 1, 0); 132 | 133 | UINT16 family = (cpuinfo[0] >> 8) & 0xF; 134 | UINT8 model = (cpuinfo[0] >> 4) & 0xF; 135 | UINT8 stepping = cpuinfo[0] & 0xF; 136 | if (family == 0xF || family == 0x6) { 137 | model += (((cpuinfo[0] >> 16) & 0xF) << 4); 138 | } 139 | if (family == 0xF) { 140 | family += (cpuinfo[0] >> 20) & 0xFF; 141 | } 142 | 143 | if (strcmp(vendorName, "AuthenticAMD") == 0) { 144 | if (family == 25 && model == 80) 145 | return PlatformRyzenCezanne; 146 | else if (family == 23 && (model == 32 || model == 24)) 147 | return PlatformRyzenDali; //Picasso is model 24 but add that too 148 | else 149 | return PlatformRyzenMendocino; //family 23 for Mendocino (model 160) 150 | } else if (strcmp(vendorName, "GenuineIntel") == 0) { 151 | if (model == 122 || model == 92) //92 = Apollo Lake but keep for compatibility 152 | return PlatformGeminiLake; 153 | else 154 | return PlatformTigerLake; 155 | } 156 | return PlatformNone; 157 | } 158 | 159 | static void rt5682s_calibrate(_In_ PRTEK_CONTEXT pDevice) 160 | { 161 | int count; 162 | UINT16 value; 163 | 164 | rt5682s_reg_write(pDevice, RT5682S_PWR_ANLG_1, 0xaa80); 165 | 166 | LARGE_INTEGER WaitInterval; 167 | WaitInterval.QuadPart = -10 * 1000 * 15; 168 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 169 | 170 | rt5682s_reg_write(pDevice, RT5682S_PWR_ANLG_1, 0xfa80); 171 | rt5682s_reg_write(pDevice, RT5682S_PWR_DIG_1, 0x01c0); 172 | rt5682s_reg_write(pDevice, RT5682S_MICBIAS_2, 0x0380); 173 | rt5682s_reg_write(pDevice, RT5682S_GLB_CLK, 0x8000); 174 | rt5682s_reg_write(pDevice, RT5682S_ADDA_CLK_1, 0x1001); 175 | rt5682s_reg_write(pDevice, RT5682S_CHOP_DAC_2, 0x3030); 176 | rt5682s_reg_write(pDevice, RT5682S_CHOP_ADC, 0xb000); 177 | rt5682s_reg_write(pDevice, RT5682S_STO1_ADC_MIXER, 0x686c); 178 | rt5682s_reg_write(pDevice, RT5682S_CAL_REC, 0x5151); 179 | rt5682s_reg_write(pDevice, RT5682S_HP_CALIB_CTRL_2, 0x0321); 180 | rt5682s_reg_write(pDevice, RT5682S_HP_LOGIC_CTRL_2, 0x0004); 181 | rt5682s_reg_write(pDevice, RT5682S_HP_CALIB_CTRL_1, 0x7c00); 182 | rt5682s_reg_write(pDevice, RT5682S_HP_CALIB_CTRL_1, 0xfc00); 183 | 184 | for (count = 0; count < 60; count++) { 185 | rt5682s_reg_read(pDevice, RT5682S_HP_CALIB_ST_1, &value); 186 | if (!(value & 0x8000)) 187 | break; 188 | 189 | WaitInterval.QuadPart = -10 * 1000 * 10; 190 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 191 | } 192 | 193 | if (count >= 60) 194 | DbgPrint("HP Calibration Failure\n"); 195 | 196 | /* restore settings */ 197 | rt5682s_reg_write(pDevice, RT5682S_MICBIAS_2, 0x0180); 198 | rt5682s_reg_write(pDevice, RT5682S_CAL_REC, 0x5859); 199 | rt5682s_reg_write(pDevice, RT5682S_STO1_ADC_MIXER, 0xc0c4); 200 | rt5682s_reg_write(pDevice, RT5682S_HP_CALIB_CTRL_2, 0x0320); 201 | rt5682s_reg_write(pDevice, RT5682S_PWR_DIG_1, 0x00c0); 202 | rt5682s_reg_write(pDevice, RT5682S_PWR_ANLG_1, 0x0800); 203 | rt5682s_reg_write(pDevice, RT5682S_GLB_CLK, 0x0000); 204 | } 205 | 206 | NTSTATUS BOOTCODEC( 207 | _In_ PRTEK_CONTEXT devContext 208 | ) 209 | { 210 | NTSTATUS status = rt5682s_reg_write(devContext, RT5682S_RESET, 0); 211 | if (!NT_SUCCESS(status)) { 212 | return status; 213 | } 214 | 215 | LARGE_INTEGER WaitInterval; 216 | WaitInterval.QuadPart = -10 * 1000 * 50; 217 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 218 | 219 | UINT16 val; 220 | status = rt5682s_reg_read(devContext, RT5682S_DEVICE_ID, &val); 221 | if (!NT_SUCCESS(status)) { 222 | return status; 223 | } 224 | 225 | if (val != DEVICE_ID) { 226 | DbgPrint("Device with ID 0x%x is not ALC5682S\n", val); 227 | return STATUS_NO_SUCH_DEVICE; 228 | } 229 | 230 | { 231 | //Apply patch list 232 | struct reg patch_list[] = { 233 | {RT5682S_I2C_CTRL, 0x0007}, 234 | {RT5682S_DIG_IN_CTRL_1, 0x0000}, 235 | {RT5682S_CHOP_DAC_2, 0x2020}, 236 | {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101}, 237 | {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0}, 238 | {RT5682S_HP_CALIB_CTRL_9, 0x0002}, 239 | {RT5682S_DEPOP_1, 0x0000}, 240 | {RT5682S_HP_CHARGE_PUMP_2, 0x3c15}, 241 | {RT5682S_DAC1_DIG_VOL, 0xfefe}, 242 | {RT5682S_SAR_IL_CMD_2, 0xac00}, 243 | {RT5682S_SAR_IL_CMD_3, 0x024c}, 244 | {RT5682S_CBJ_CTRL_6, 0x0804}, 245 | }; 246 | status = rt5682s_reg_burstWrite(devContext, patch_list, sizeof(patch_list) / sizeof(struct reg)); 247 | if (!NT_SUCCESS(status)) { 248 | return status; 249 | } 250 | } 251 | 252 | rt5682s_reg_update(devContext, RT5682S_PWR_DIG_2, 253 | RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS); 254 | 255 | WaitInterval.QuadPart = -10 * 1000 * 20; 256 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 257 | 258 | rt5682s_calibrate(devContext); 259 | 260 | rt5682s_reg_update(devContext, RT5682S_MICBIAS_2, 261 | RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK, 262 | RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU); 263 | rt5682s_reg_update(devContext, RT5682S_PWR_ANLG_1, 264 | RT5682S_PWR_BG, RT5682S_PWR_BG); 265 | rt5682s_reg_update(devContext, RT5682S_HP_LOGIC_CTRL_2, 266 | RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL); 267 | rt5682s_reg_update(devContext, RT5682S_HP_CHARGE_PUMP_2, 268 | RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV); 269 | rt5682s_reg_update(devContext, RT5682S_HP_AMP_DET_CTL_1, 270 | RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S); 271 | 272 | //Set Clocks (AlderLake) 273 | 274 | struct reg setClocksAlderLake[] = { 275 | //{RT5682S_PLL_CTRL_3, 0x0006}, //reclocking should set these 276 | //{RT5682S_PLL_CTRL_4, 0x0203}, 277 | //{RT5682S_PLL_CTRL_7, 0x0001}, 278 | {RT5682S_RC_CLK_CTRL, 0xc009}, 279 | {RT5682S_I2S2_M_CLK_CTRL_1, 0x0020}, 280 | 281 | {RT5682S_GLB_CLK, 0x0000}, //Reclocking should set 0x4000 282 | 283 | //set bclk1 ratio ADL 284 | //{RT5682S_TDM_TCON_CTRL_1, 0x0020}, //Reclocking should set this 285 | 286 | {RT5682S_ADDA_CLK_1, 0x1021}, 287 | }; 288 | 289 | status = rt5682s_reg_burstWrite(devContext, setClocksAlderLake, sizeof(setClocksAlderLake) / sizeof(struct reg)); 290 | if (!NT_SUCCESS(status)) { 291 | return status; 292 | } 293 | 294 | struct reg finishInit2[] = { 295 | 296 | //set clk 297 | {RT5682S_PLL_TRACK_2, 0x0100}, 298 | 299 | //Update more defaults 300 | {RT5682S_STO1_ADC_DIG_VOL, 0x2faf}, 301 | {RT5682S_REC_MIXER, 0x1940}, 302 | {RT5682S_I2S2_SDP, 0x4000}, 303 | {RT5682S_PLL_TRACK_3, 0x0100}, 304 | {RT5682S_GPIO_CTRL_1, 0x6960}, 305 | {RT5682S_DMIC_CTRL_1, 0x0800}, 306 | 307 | //Headphone defaults 308 | {RT5682S_HP_CTRL_2, 0x6001}, 309 | {RT5682S_STO1_ADC_MIXER, 0x6064}, 310 | {RT5682S_PWR_DIG_1, 0x8dd1}, 311 | {RT5682S_PWR_DIG_2, 0x840a}, 312 | {RT5682S_PWR_ANLG_2, 0x8001}, 313 | {RT5682S_PWR_ANLG_3, 0x52a1}, 314 | {RT5682S_CLK_DET, 0x8000}, 315 | {RT5682S_DEPOP_1, 0x7b}, 316 | 317 | {RT5682S_BIAS_CUR_CTRL_12, 0xa82a} 318 | }; 319 | 320 | status = rt5682s_reg_burstWrite(devContext, finishInit2, sizeof(finishInit2) / sizeof(struct reg)); 321 | if (!NT_SUCCESS(status)) { 322 | return status; 323 | } 324 | 325 | struct reg setDefaultsAlderLake[] = { 326 | //For Alder Lake 327 | {RT5682S_HP_CTRL_1, 0x8080}, 328 | {RT5682S_DAC1_DIG_VOL, 0xecec}, 329 | {RT5682S_STO1_DAC_MIXER, 0x2080}, 330 | {RT5682S_I2S1_SDP, 0x0000}, //Reclocking should set 0x2220 331 | {RT5682S_TDM_ADDA_CTRL_1, 0x8000}, 332 | {RT5682S_TDM_ADDA_CTRL_2, 0x0080} 333 | }; 334 | 335 | status = rt5682s_reg_burstWrite(devContext, setDefaultsAlderLake, sizeof(setDefaultsAlderLake) / sizeof(struct reg)); 336 | if (!NT_SUCCESS(status)) { 337 | return status; 338 | } 339 | 340 | rt5682s_update_reclock(devContext); 341 | 342 | Platform platform = GetPlatform(); 343 | 344 | if (platform == PlatformRyzenMendocino) { 345 | struct reg setDefaultsMendocino[] = { 346 | //For Mendocino 347 | {RT5682S_DAC1_DIG_VOL, 0xeaea}, 348 | {RT5682S_STO1_ADC_DIG_VOL, 0x6565}, 349 | {RT5682S_STO1_DAC_MIXER, 0xa0a0}, 350 | {RT5682S_A_DAC1_MUX, 0x0311}, 351 | {RT5682S_REC_MIXER, 0x0d40} 352 | }; 353 | 354 | status = rt5682s_reg_burstWrite(devContext, setDefaultsMendocino, sizeof(setDefaultsMendocino) / sizeof(struct reg)); 355 | if (!NT_SUCCESS(status)) { 356 | return status; 357 | } 358 | 359 | rt5682s_reg_update(devContext, RT5682S_I2S1_SDP, RT5682S_I2S_DF_MASK, 360 | RT5682S_I2S_DF_PCM_A); 361 | rt5682s_reg_update(devContext, RT5682S_TDM_TCON_CTRL_1, RT5682S_TDM_BCLK_MS1_MASK | RT5682S_TDM_DF_MASK, 362 | RT5682S_TDM_BCLK_MS1_128 | RT5682S_TDM_DF_PCM_A); 363 | 364 | rt5682s_set_component_pll(devContext, RT5682S_PLL2, RT5682S_PLL_S_MCLK, 48000000, 48000 * 512); 365 | rt5682s_set_tdm_slot(devContext, 3, 3, 8, 16); 366 | rt5682s_set_component_sysclk(devContext, RT5682S_SCLK_S_PLL2); 367 | } 368 | else if (platform == PlatformRyzenCezanne || platform == PlatformRyzenDali) { 369 | struct reg setDefaultsCezanne[] = { 370 | //For Cezanne 371 | {RT5682S_DAC1_DIG_VOL, 0xfcfc}, 372 | {RT5682S_STO1_ADC_DIG_VOL, 0x6565}, 373 | {RT5682S_STO1_DAC_MIXER, 0xa0a0}, 374 | {RT5682S_A_DAC1_MUX, 0x0311}, 375 | {RT5682S_REC_MIXER, 0x0d40}, 376 | 377 | //Set Clocks for Cezanne 378 | {RT5682S_I2S1_SDP, 0x3300}, 379 | {RT5682S_ADDA_CLK_1, 0x1121}, 380 | {RT5682S_TDM_ADDA_CTRL_2, 0x0000}, 381 | {RT5682S_TDM_TCON_CTRL_1, 0x0101} 382 | }; 383 | 384 | status = rt5682s_reg_burstWrite(devContext, setDefaultsCezanne, sizeof(setDefaultsCezanne) / sizeof(struct reg)); 385 | if (!NT_SUCCESS(status)) { 386 | return status; 387 | } 388 | 389 | rt5682s_reg_update(devContext, RT5682S_TDM_TCON_CTRL_1, RT5682S_TDM_BCLK_MS1_MASK | RT5682S_TDM_DF_MASK, 390 | RT5682S_TDM_BCLK_MS1_64 | RT5682S_TDM_DF_I2S); 391 | 392 | rt5682s_set_component_pll(devContext, RT5682S_PLL2, RT5682S_PLL_S_MCLK, 48000000, 48000 * 512); 393 | rt5682s_set_component_sysclk(devContext, RT5682S_SCLK_S_PLL2); 394 | } 395 | 396 | //Set Jack Detect 397 | 398 | { 399 | int btndet_delay = 16; 400 | 401 | rt5682s_reg_update(devContext, RT5682S_CBJ_CTRL_5, 402 | RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH); 403 | rt5682s_reg_update(devContext, RT5682S_CBJ_CTRL_2, 404 | RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL); 405 | rt5682s_reg_update(devContext, RT5682S_CBJ_CTRL_1, 406 | RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE | 407 | RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK, 408 | RT5682S_EMB_JD_EN | RT5682S_DET_TYPE | 409 | RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS); 410 | rt5682s_reg_update(devContext, RT5682S_SAR_IL_CMD_1, 411 | RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN); 412 | rt5682s_reg_update(devContext, RT5682S_GPIO_CTRL_1, 413 | RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ); 414 | rt5682s_reg_update(devContext, RT5682S_PWR_ANLG_3, 415 | RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO); 416 | rt5682s_reg_update(devContext, RT5682S_PWR_ANLG_2, 417 | RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE); 418 | rt5682s_reg_update(devContext, RT5682S_RC_CLK_CTRL, 419 | RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH); 420 | rt5682s_reg_update(devContext, RT5682S_IRQ_CTRL_2, 421 | RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK, 422 | RT5682S_JD1_EN | RT5682S_JD1_POL_NOR); 423 | rt5682s_reg_update(devContext, RT5682S_4BTN_IL_CMD_4, 424 | RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 425 | (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 426 | rt5682s_reg_update(devContext, RT5682S_4BTN_IL_CMD_5, 427 | RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 428 | (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 429 | rt5682s_reg_update(devContext, RT5682S_4BTN_IL_CMD_6, 430 | RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 431 | (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 432 | rt5682s_reg_update(devContext, RT5682S_4BTN_IL_CMD_7, 433 | RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 434 | (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 435 | } 436 | 437 | return STATUS_SUCCESS; 438 | } 439 | 440 | int CsAudioArg2 = 1; 441 | 442 | VOID 443 | CSAudioRegisterEndpoint( 444 | PRTEK_CONTEXT pDevice 445 | ) { 446 | CsAudioArg arg; 447 | RtlZeroMemory(&arg, sizeof(CsAudioArg)); 448 | arg.argSz = sizeof(CsAudioArg); 449 | arg.endpointType = CSAudioEndpointTypeHeadphone; 450 | arg.endpointRequest = CSAudioEndpointRegister; 451 | ExNotifyCallback(pDevice->CSAudioAPICallback, &arg, &CsAudioArg2); 452 | 453 | arg.endpointType = CSAudioEndpointTypeMicJack; 454 | ExNotifyCallback(pDevice->CSAudioAPICallback, &arg, &CsAudioArg2); //register both in case user decides to record first 455 | } 456 | 457 | void rt5682s_update_reclock(IN PRTEK_CONTEXT pDevice) { 458 | UINT32 mclk = pDevice->mclk; 459 | UINT32 freq = pDevice->freq; 460 | UINT32 slotWidth = pDevice->slotWidth; 461 | 462 | if (!pDevice->ReclockRequested) 463 | return; 464 | 465 | UINT32 outclk = freq * 512; 466 | if (mclk != outclk) 467 | rt5682s_set_component_pll(pDevice, RT5682S_PLL2, RT5682S_PLL_S_MCLK, mclk, outclk); 468 | rt5682s_set_tdm_slot(pDevice, 1, 1, 2, slotWidth); 469 | rt5682s_set_component_sysclk(pDevice, mclk == outclk ? RT5682S_SCLK_S_MCLK : RT5682S_SCLK_S_PLL2); 470 | rt5682s_reg_update(pDevice, RT5682S_PWR_ANLG_3, 471 | RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_RSTB_PLLB | RT5682S_PWR_PLLB, 472 | mclk != outclk ? (RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_RSTB_PLLB | RT5682S_PWR_PLLB) : 0); 473 | } 474 | 475 | void StartStopSpeaker( 476 | IN PRTEK_CONTEXT pDevice, 477 | IN BOOLEAN start) { 478 | CsAudioArg localArg; 479 | RtlZeroMemory(&localArg, sizeof(CsAudioArg)); 480 | localArg.argSz = sizeof(localArg); 481 | localArg.endpointType = CSAudioEndpointTypeSpeaker; 482 | localArg.endpointRequest = start ? CSAudioEndpointStart : CSAudioEndpointStop; 483 | ExNotifyCallback(pDevice->CSAudioAPICallback, &localArg, &CsAudioArg2); 484 | } 485 | 486 | VOID 487 | CsAudioCallbackFunction( 488 | IN PRTEK_CONTEXT pDevice, 489 | CsAudioArg* arg, 490 | PVOID Argument2 491 | ) { 492 | if (!pDevice) { 493 | return; 494 | } 495 | 496 | if (Argument2 == &CsAudioArg2) { 497 | return; 498 | } 499 | 500 | pDevice->CSAudioManaged = TRUE; 501 | 502 | CsAudioArg localArg; 503 | RtlZeroMemory(&localArg, sizeof(CsAudioArg)); 504 | RtlCopyMemory(&localArg, arg, min(arg->argSz, sizeof(CsAudioArg))); 505 | 506 | if (localArg.endpointType == CSAudioEndpointTypeDSP && localArg.endpointRequest == CSAudioEndpointRegister) { 507 | CSAudioRegisterEndpoint(pDevice); 508 | } 509 | else if (localArg.endpointType != CSAudioEndpointTypeHeadphone && 510 | localArg.endpointType != CSAudioEndpointTypeMicJack) { //check both in case user decides to record first 511 | return; 512 | } 513 | 514 | if ((localArg.endpointRequest == CSAudioEndpointStart || localArg.endpointRequest == CSAudioEndpointStop) && 515 | localArg.endpointType == CSAudioEndpointTypeHeadphone) { 516 | pDevice->HeadphonePlaying = (localArg.endpointRequest == CSAudioEndpointStart); 517 | if (pDevice->JackType == 0 && GetPlatform() == PlatformRyzenCezanne) { 518 | StartStopSpeaker(pDevice, localArg.endpointRequest == CSAudioEndpointStart); 519 | } 520 | } 521 | 522 | if (localArg.endpointRequest == CSAudioEndpointI2SParameters && 523 | localArg.i2sParameters.version >= 1) { //Supports version 1 or higher 524 | 525 | Platform currentPlatform = GetPlatform(); 526 | if (currentPlatform == PlatformTigerLake) { //Reclock requested 527 | UINT32 mclk = localArg.i2sParameters.mclk; 528 | UINT32 freq = localArg.i2sParameters.frequency; 529 | UINT32 slotWidth = localArg.i2sParameters.valid_bits; 530 | 531 | pDevice->mclk = mclk; 532 | pDevice->freq = freq; 533 | pDevice->slotWidth = slotWidth; 534 | pDevice->ReclockRequested = TRUE; 535 | 536 | rt5682s_update_reclock(pDevice); 537 | } 538 | } 539 | } 540 | 541 | static const struct pll_calc_map plla_table[] = { 542 | {2048000, 24576000, 0, 46, 2, true, false, false, false}, 543 | {256000, 24576000, 0, 382, 2, true, false, false, false}, 544 | {512000, 24576000, 0, 190, 2, true, false, false, false}, 545 | {4096000, 24576000, 0, 22, 2, true, false, false, false}, 546 | {1024000, 24576000, 0, 94, 2, true, false, false, false}, 547 | {11289600, 22579200, 1, 22, 2, false, false, false, false}, 548 | {1411200, 22579200, 0, 62, 2, true, false, false, false}, 549 | {2822400, 22579200, 0, 30, 2, true, false, false, false}, 550 | {12288000, 24576000, 1, 22, 2, false, false, false, false}, 551 | {1536000, 24576000, 0, 62, 2, true, false, false, false}, 552 | {3072000, 24576000, 0, 30, 2, true, false, false, false}, 553 | {24576000, 49152000, 4, 22, 0, false, false, false, false}, 554 | {3072000, 49152000, 0, 30, 0, true, false, false, false}, 555 | {6144000, 49152000, 0, 30, 0, false, false, false, false}, 556 | {49152000, 98304000, 10, 22, 0, false, true, false, false}, 557 | {6144000, 98304000, 0, 30, 0, false, true, false, false}, 558 | {12288000, 98304000, 1, 22, 0, false, true, false, false}, 559 | {48000000, 3840000, 10, 22, 23, false, false, false, false}, 560 | {24000000, 3840000, 4, 22, 23, false, false, false, false}, 561 | {19200000, 3840000, 3, 23, 23, false, false, false, false}, 562 | {38400000, 3840000, 8, 23, 23, false, false, false, false}, 563 | }; 564 | 565 | static const struct pll_calc_map pllb_table[] = { 566 | {48000000, 24576000, 8, 6, 3, false, false, false, false}, 567 | {48000000, 22579200, 23, 12, 3, false, false, false, true}, 568 | {24000000, 24576000, 3, 6, 3, false, false, false, false}, 569 | {24000000, 22579200, 23, 26, 3, false, false, false, true}, 570 | {19200000, 24576000, 2, 6, 3, false, false, false, false}, 571 | {19200000, 22579200, 3, 5, 3, false, false, false, true}, 572 | {38400000, 24576000, 6, 6, 3, false, false, false, false}, 573 | {38400000, 22579200, 8, 5, 3, false, false, false, true}, 574 | {3840000, 49152000, 0, 6, 0, true, false, false, false}, 575 | }; 576 | 577 | static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out, 578 | struct pll_calc_map* a, struct pll_calc_map* b) 579 | { 580 | int i, j; 581 | 582 | /* Look at PLLA table */ 583 | for (i = 0; i < sizeof(plla_table) / sizeof(plla_table[0]); i++) { 584 | if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) { 585 | memcpy(a, plla_table + i, sizeof(*a)); 586 | return USE_PLLA; 587 | } 588 | } 589 | 590 | /* Look at PLLB table */ 591 | for (i = 0; i < sizeof(pllb_table) / sizeof(pllb_table[0]); i++) { 592 | if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) { 593 | memcpy(b, pllb_table + i, sizeof(*b)); 594 | return USE_PLLB; 595 | } 596 | } 597 | 598 | /* Find a combination of PLLA & PLLB */ 599 | for (i = (sizeof(plla_table) / sizeof(plla_table[0])) - 1; i >= 0; i--) { 600 | if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) { 601 | for (j = (sizeof(pllb_table) / sizeof(pllb_table[0])) - 1; j >= 0; j--) { 602 | if (pllb_table[j].freq_in == 3840000 && 603 | pllb_table[j].freq_out == f_out) { 604 | memcpy(a, plla_table + i, sizeof(*a)); 605 | memcpy(b, pllb_table + j, sizeof(*b)); 606 | return USE_PLLAB; 607 | } 608 | } 609 | } 610 | } 611 | 612 | return -1; 613 | } 614 | 615 | 616 | NTSTATUS rt5682s_set_component_pll(PRTEK_CONTEXT pDevice, 617 | int pll_id, int source, unsigned int freq_in, 618 | unsigned int freq_out) 619 | { 620 | struct pll_calc_map a_map, b_map; 621 | 622 | if (!freq_in || !freq_out) { 623 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "PLL disabled\n"); 624 | rt5682s_reg_update(pDevice, RT5682S_GLB_CLK, 625 | RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT); 626 | return STATUS_SUCCESS; 627 | } 628 | 629 | switch (source) { 630 | case RT5682S_PLL_S_MCLK: 631 | rt5682s_reg_update(pDevice, RT5682S_GLB_CLK, 632 | RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK); 633 | break; 634 | case RT5682S_PLL_S_BCLK1: 635 | rt5682s_reg_update(pDevice, RT5682S_GLB_CLK, 636 | RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1); 637 | break; 638 | default: 639 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "Unknown PLL Source %d\n", source); 640 | return STATUS_INVALID_PARAMETER; 641 | } 642 | 643 | int pll_comb = find_pll_inter_combination(freq_in, freq_out, 644 | &a_map, &b_map); 645 | 646 | if ((pll_id == RT5682S_PLL1 && pll_comb == USE_PLLA) || 647 | (pll_id == RT5682S_PLL2 && (pll_comb == USE_PLLB || 648 | pll_comb == USE_PLLAB))) { 649 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "Supported freq conversion for PLL%d:(%d->%d): %d\n", 650 | pll_id + 1, freq_in, freq_out, rt5682s->pll_comb); 651 | } 652 | else { 653 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "Unsupported freq conversion for PLL%d:(%d->%d): %d\n", 654 | pll_id + 1, freq_in, freq_out, rt5682s->pll_comb); 655 | return STATUS_INVALID_PARAMETER; 656 | } 657 | 658 | if (pll_comb == USE_PLLA || pll_comb == USE_PLLAB) { 659 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n", 660 | a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp, 661 | (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k)); 662 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_1, 663 | RT5682S_PLLA_N_MASK, a_map.n); 664 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_2, 665 | RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK, 666 | a_map.m << RT5682S_PLLA_M_SFT | a_map.k); 667 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_6, 668 | RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK, 669 | a_map.m_bp << RT5682S_PLLA_M_BP_SFT | 670 | a_map.k_bp << RT5682S_PLLA_K_BP_SFT); 671 | } 672 | 673 | if (pll_comb == USE_PLLB || pll_comb == USE_PLLAB) { 674 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n", 675 | b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp, 676 | (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k), 677 | b_map.byp_ps, b_map.sel_ps); 678 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_3, 679 | RT5682S_PLLB_N_MASK, b_map.n); 680 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_4, 681 | RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK, 682 | b_map.m << RT5682S_PLLB_M_SFT | b_map.k); 683 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_6, 684 | RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK | 685 | RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK, 686 | b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT | 687 | b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT | 688 | b_map.m_bp << RT5682S_PLLB_M_BP_SFT | 689 | b_map.k_bp << RT5682S_PLLB_K_BP_SFT); 690 | } 691 | 692 | if (pll_comb == USE_PLLB) 693 | rt5682s_reg_update(pDevice, RT5682S_PLL_CTRL_7, 694 | RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN); 695 | 696 | return STATUS_SUCCESS; 697 | } 698 | 699 | NTSTATUS rt5682s_set_tdm_slot(PRTEK_CONTEXT pDevice, unsigned int tx_mask, 700 | unsigned int rx_mask, int slots, int slot_width) 701 | { 702 | unsigned int cl, val = 0, tx_slotnum; 703 | 704 | if (tx_mask || rx_mask) 705 | rt5682s_reg_update(pDevice, RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN); 706 | else 707 | rt5682s_reg_update(pDevice, RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0); 708 | 709 | /* Tx slot configuration */ 710 | tx_slotnum = hweight_long(tx_mask); 711 | if (tx_slotnum) { 712 | if (tx_slotnum > slots) { 713 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "Invalid or oversized Tx slots.\n"); 714 | return STATUS_INVALID_PARAMETER; 715 | } 716 | val |= (tx_slotnum - 1) << RT5682S_TDM_ADC_DL_SFT; 717 | } 718 | 719 | switch (slots) { 720 | case 4: 721 | val |= RT5682S_TDM_TX_CH_4; 722 | val |= RT5682S_TDM_RX_CH_4; 723 | break; 724 | case 6: 725 | val |= RT5682S_TDM_TX_CH_6; 726 | val |= RT5682S_TDM_RX_CH_6; 727 | break; 728 | case 8: 729 | val |= RT5682S_TDM_TX_CH_8; 730 | val |= RT5682S_TDM_RX_CH_8; 731 | break; 732 | case 2: 733 | break; 734 | default: 735 | return STATUS_INVALID_PARAMETER; 736 | } 737 | 738 | rt5682s_reg_update(pDevice, RT5682S_TDM_CTRL, 739 | RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK | 740 | RT5682S_TDM_ADC_DL_MASK, val); 741 | 742 | switch (slot_width) { 743 | case 8: 744 | if (tx_mask || rx_mask) 745 | return STATUS_INVALID_PARAMETER; 746 | cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8; 747 | break; 748 | case 16: 749 | val = RT5682S_TDM_CL_16; 750 | cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16; 751 | break; 752 | case 20: 753 | val = RT5682S_TDM_CL_20; 754 | cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20; 755 | break; 756 | case 24: 757 | val = RT5682S_TDM_CL_24; 758 | cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24; 759 | break; 760 | case 32: 761 | val = RT5682S_TDM_CL_32; 762 | cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32; 763 | break; 764 | default: 765 | return STATUS_INVALID_PARAMETER; 766 | } 767 | 768 | rt5682s_reg_update(pDevice, RT5682S_TDM_TCON_CTRL_1, 769 | RT5682S_TDM_CL_MASK, val); 770 | rt5682s_reg_update(pDevice, RT5682S_I2S1_SDP, 771 | RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl); 772 | 773 | return STATUS_SUCCESS; 774 | } 775 | 776 | NTSTATUS rt5682s_set_component_sysclk(PRTEK_CONTEXT pDevice, 777 | int clk_id) 778 | { 779 | unsigned int src = 0; 780 | 781 | switch (clk_id) { 782 | case RT5682S_SCLK_S_MCLK: 783 | src = RT5682S_CLK_SRC_MCLK; 784 | break; 785 | case RT5682S_SCLK_S_PLL1: 786 | src = RT5682S_CLK_SRC_PLL1; 787 | break; 788 | case RT5682S_SCLK_S_PLL2: 789 | src = RT5682S_CLK_SRC_PLL2; 790 | break; 791 | case RT5682S_SCLK_S_RCCLK: 792 | src = RT5682S_CLK_SRC_RCCLK; 793 | break; 794 | default: 795 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "Invalid clock id (%d)\n", clk_id); 796 | return STATUS_INVALID_PARAMETER; 797 | } 798 | 799 | rt5682s_reg_update(pDevice, RT5682S_GLB_CLK, 800 | RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT); 801 | rt5682s_reg_update(pDevice, RT5682S_ADDA_CLK_1, 802 | RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT); 803 | rt5682s_reg_update(pDevice, RT5682S_I2S2_M_CLK_CTRL_1, 804 | RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT); 805 | 806 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, "Sysclk is %dHz and clock id is %d\n", 807 | freq, clk_id); 808 | 809 | return STATUS_SUCCESS; 810 | } 811 | 812 | NTSTATUS 813 | OnPrepareHardware( 814 | _In_ WDFDEVICE FxDevice, 815 | _In_ WDFCMRESLIST FxResourcesRaw, 816 | _In_ WDFCMRESLIST FxResourcesTranslated 817 | ) 818 | /*++ 819 | 820 | Routine Description: 821 | 822 | This routine caches the SPB resource connection ID. 823 | 824 | Arguments: 825 | 826 | FxDevice - a handle to the framework device object 827 | FxResourcesRaw - list of translated hardware resources that 828 | the PnP manager has assigned to the device 829 | FxResourcesTranslated - list of raw hardware resources that 830 | the PnP manager has assigned to the device 831 | 832 | Return Value: 833 | 834 | Status 835 | 836 | --*/ 837 | { 838 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 839 | BOOLEAN fSpbResourceFound = FALSE; 840 | NTSTATUS status = STATUS_INSUFFICIENT_RESOURCES; 841 | 842 | UNREFERENCED_PARAMETER(FxResourcesRaw); 843 | 844 | // 845 | // Parse the peripheral's resources. 846 | // 847 | 848 | ULONG resourceCount = WdfCmResourceListGetCount(FxResourcesTranslated); 849 | 850 | for (ULONG i = 0; i < resourceCount; i++) 851 | { 852 | PCM_PARTIAL_RESOURCE_DESCRIPTOR pDescriptor; 853 | UCHAR Class; 854 | UCHAR Type; 855 | 856 | pDescriptor = WdfCmResourceListGetDescriptor( 857 | FxResourcesTranslated, i); 858 | 859 | switch (pDescriptor->Type) 860 | { 861 | case CmResourceTypeConnection: 862 | // 863 | // Look for I2C or SPI resource and save connection ID. 864 | // 865 | Class = pDescriptor->u.Connection.Class; 866 | Type = pDescriptor->u.Connection.Type; 867 | if (Class == CM_RESOURCE_CONNECTION_CLASS_SERIAL && 868 | Type == CM_RESOURCE_CONNECTION_TYPE_SERIAL_I2C) 869 | { 870 | if (fSpbResourceFound == FALSE) 871 | { 872 | status = STATUS_SUCCESS; 873 | pDevice->I2CContext.I2cResHubId.LowPart = pDescriptor->u.Connection.IdLowPart; 874 | pDevice->I2CContext.I2cResHubId.HighPart = pDescriptor->u.Connection.IdHighPart; 875 | fSpbResourceFound = TRUE; 876 | } 877 | else 878 | { 879 | } 880 | } 881 | break; 882 | default: 883 | // 884 | // Ignoring all other resource types. 885 | // 886 | break; 887 | } 888 | } 889 | 890 | // 891 | // An SPB resource is required. 892 | // 893 | 894 | if (fSpbResourceFound == FALSE) 895 | { 896 | status = STATUS_NOT_FOUND; 897 | } 898 | 899 | status = SpbTargetInitialize(FxDevice, &pDevice->I2CContext); 900 | 901 | if (!NT_SUCCESS(status)) 902 | { 903 | return status; 904 | } 905 | 906 | return status; 907 | } 908 | 909 | NTSTATUS 910 | OnReleaseHardware( 911 | _In_ WDFDEVICE FxDevice, 912 | _In_ WDFCMRESLIST FxResourcesTranslated 913 | ) 914 | /*++ 915 | 916 | Routine Description: 917 | 918 | Arguments: 919 | 920 | FxDevice - a handle to the framework device object 921 | FxResourcesTranslated - list of raw hardware resources that 922 | the PnP manager has assigned to the device 923 | 924 | Return Value: 925 | 926 | Status 927 | 928 | --*/ 929 | { 930 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 931 | NTSTATUS status = STATUS_SUCCESS; 932 | 933 | UNREFERENCED_PARAMETER(FxResourcesTranslated); 934 | 935 | SpbTargetDeinitialize(FxDevice, &pDevice->I2CContext); 936 | 937 | if (pDevice->CSAudioAPICallbackObj) { 938 | ExUnregisterCallback(pDevice->CSAudioAPICallbackObj); 939 | pDevice->CSAudioAPICallbackObj = NULL; 940 | } 941 | 942 | if (pDevice->CSAudioAPICallback) { 943 | ObfDereferenceObject(pDevice->CSAudioAPICallback); 944 | pDevice->CSAudioAPICallback = NULL; 945 | } 946 | 947 | return status; 948 | } 949 | 950 | NTSTATUS 951 | OnSelfManagedIoInit( 952 | _In_ 953 | WDFDEVICE FxDevice 954 | ) { 955 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 956 | NTSTATUS status = STATUS_SUCCESS; 957 | 958 | // CS Audio Callback 959 | 960 | UNICODE_STRING CSAudioCallbackAPI; 961 | RtlInitUnicodeString(&CSAudioCallbackAPI, L"\\CallBack\\CsAudioCallbackAPI"); 962 | 963 | 964 | OBJECT_ATTRIBUTES attributes; 965 | InitializeObjectAttributes(&attributes, 966 | &CSAudioCallbackAPI, 967 | OBJ_KERNEL_HANDLE | OBJ_OPENIF | OBJ_CASE_INSENSITIVE | OBJ_PERMANENT, 968 | NULL, 969 | NULL 970 | ); 971 | status = ExCreateCallback(&pDevice->CSAudioAPICallback, &attributes, TRUE, TRUE); 972 | if (!NT_SUCCESS(status)) { 973 | 974 | return status; 975 | } 976 | 977 | pDevice->CSAudioAPICallbackObj = ExRegisterCallback(pDevice->CSAudioAPICallback, 978 | CsAudioCallbackFunction, 979 | pDevice 980 | ); 981 | if (!pDevice->CSAudioAPICallbackObj) { 982 | 983 | return STATUS_NO_CALLBACK_ACTIVE; 984 | } 985 | 986 | CSAudioRegisterEndpoint(pDevice); 987 | 988 | return status; 989 | } 990 | 991 | NTSTATUS 992 | OnD0Entry( 993 | _In_ WDFDEVICE FxDevice, 994 | _In_ WDF_POWER_DEVICE_STATE FxPreviousState 995 | ) 996 | /*++ 997 | 998 | Routine Description: 999 | 1000 | This routine allocates objects needed by the driver. 1001 | 1002 | Arguments: 1003 | 1004 | FxDevice - a handle to the framework device object 1005 | FxPreviousState - previous power state 1006 | 1007 | Return Value: 1008 | 1009 | Status 1010 | 1011 | --*/ 1012 | { 1013 | UNREFERENCED_PARAMETER(FxPreviousState); 1014 | 1015 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 1016 | NTSTATUS status = STATUS_SUCCESS; 1017 | 1018 | pDevice->JackType = 0; 1019 | 1020 | status = BOOTCODEC(pDevice); 1021 | if (!NT_SUCCESS(status)) { 1022 | return status; 1023 | } 1024 | 1025 | pDevice->ConnectInterrupt = true; 1026 | 1027 | RtekCompleteIdleIrp(pDevice); 1028 | 1029 | return status; 1030 | } 1031 | 1032 | NTSTATUS 1033 | OnD0Exit( 1034 | _In_ WDFDEVICE FxDevice, 1035 | _In_ WDF_POWER_DEVICE_STATE FxPreviousState 1036 | ) 1037 | /*++ 1038 | 1039 | Routine Description: 1040 | 1041 | This routine destroys objects needed by the driver. 1042 | 1043 | Arguments: 1044 | 1045 | FxDevice - a handle to the framework device object 1046 | FxPreviousState - previous power state 1047 | 1048 | Return Value: 1049 | 1050 | Status 1051 | 1052 | --*/ 1053 | { 1054 | UNREFERENCED_PARAMETER(FxPreviousState); 1055 | 1056 | PRTEK_CONTEXT pDevice = GetDeviceContext(FxDevice); 1057 | 1058 | pDevice->ConnectInterrupt = false; 1059 | 1060 | return STATUS_SUCCESS; 1061 | } 1062 | 1063 | enum { 1064 | SAR_PWR_OFF, 1065 | SAR_PWR_NORMAL, 1066 | SAR_PWR_SAVING, 1067 | }; 1068 | 1069 | static void rt5682s_sar_power_mode(PRTEK_CONTEXT pDevice, int mode) 1070 | { 1071 | LARGE_INTEGER WaitInterval; 1072 | 1073 | switch (mode) { 1074 | case SAR_PWR_SAVING: 1075 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_3, 1076 | RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS); 1077 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1078 | RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 1079 | RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG); 1080 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1081 | RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 1082 | RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 1083 | RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 1084 | 1085 | WaitInterval.QuadPart = -10 * 1000 * 5; 1086 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1087 | 1088 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1089 | RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN); 1090 | 1091 | WaitInterval.QuadPart = -10 * 1000 * 5; 1092 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1093 | 1094 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_2, 1095 | RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY); 1096 | break; 1097 | case SAR_PWR_NORMAL: 1098 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_3, 1099 | RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN); 1100 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1101 | RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 1102 | RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM); 1103 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1104 | RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO); 1105 | 1106 | WaitInterval.QuadPart = -10 * 1000 * 5; 1107 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1108 | 1109 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1110 | RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK, 1111 | RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM); 1112 | break; 1113 | case SAR_PWR_OFF: 1114 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1115 | RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 1116 | RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM); 1117 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1118 | RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 1119 | RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 1120 | RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 1121 | break; 1122 | default: 1123 | DbgPrint("Invalid SAR Power mode: %d\n", mode); 1124 | break; 1125 | } 1126 | } 1127 | 1128 | static void rt5682s_enable_push_button_irq(PRTEK_CONTEXT pDevice, 1129 | bool enable) 1130 | { 1131 | 1132 | if (enable) { 1133 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_13, 1134 | RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN); 1135 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1136 | RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 1137 | RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN | 1138 | RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO); 1139 | rt5682s_reg_write(pDevice, RT5682S_IL_CMD_1, 0x0040); 1140 | rt5682s_reg_update(pDevice, RT5682S_4BTN_IL_CMD_2, 1141 | RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK, 1142 | RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR); 1143 | rt5682s_reg_update(pDevice, RT5682S_IRQ_CTRL_3, 1144 | RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN); 1145 | } 1146 | else { 1147 | rt5682s_reg_update(pDevice, RT5682S_IRQ_CTRL_3, 1148 | RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS); 1149 | rt5682s_reg_update(pDevice, RT5682S_4BTN_IL_CMD_2, 1150 | RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS); 1151 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_13, 1152 | RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE); 1153 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1154 | RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 1155 | RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 1156 | RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 1157 | } 1158 | } 1159 | 1160 | int rt5682s_headset_detect(PRTEK_CONTEXT pDevice, int jack_insert) { 1161 | UINT16 val, count; 1162 | if (jack_insert) { 1163 | rt5682s_enable_push_button_irq(pDevice, false); 1164 | 1165 | rt5682s_reg_update(pDevice, RT5682S_PWR_ANLG_1, 1166 | RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 1167 | RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB); 1168 | rt5682s_reg_update(pDevice, RT5682S_PWR_ANLG_1, 1169 | RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0); 1170 | 1171 | LARGE_INTEGER WaitInterval; 1172 | WaitInterval.QuadPart = -10 * 1000 * 15; 1173 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1174 | 1175 | rt5682s_reg_update(pDevice, RT5682S_PWR_ANLG_1, 1176 | RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 1177 | RT5682S_PWR_FV1 | RT5682S_PWR_FV2); 1178 | rt5682s_reg_update(pDevice, RT5682S_PWR_ANLG_3, 1179 | RT5682S_PWR_CBJ, RT5682S_PWR_CBJ); 1180 | rt5682s_reg_write(pDevice, RT5682S_SAR_IL_CMD_3, 0x0365); 1181 | rt5682s_reg_update(pDevice, RT5682S_HP_CHARGE_PUMP_2, 1182 | RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK, 1183 | RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS); 1184 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_13, 1185 | RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE); 1186 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_3, 1187 | RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN); 1188 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1189 | RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW); 1190 | 1191 | WaitInterval.QuadPart = -10 * 1000 * 45; 1192 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1193 | 1194 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1195 | RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH); 1196 | 1197 | count = 0; 1198 | rt5682s_reg_read(pDevice, RT5682S_CBJ_CTRL_2, &val); 1199 | val &= RT5682S_JACK_TYPE_MASK; 1200 | while (val == 0 && count < 50) { 1201 | WaitInterval.QuadPart = -10 * 1000 * 15; 1202 | KeDelayExecutionThread(KernelMode, false, &WaitInterval); 1203 | 1204 | rt5682s_reg_read(pDevice, RT5682S_CBJ_CTRL_2, &val); 1205 | val &= RT5682S_JACK_TYPE_MASK; 1206 | count++; 1207 | } 1208 | 1209 | switch (val) { 1210 | case 0x1: 1211 | case 0x2: 1212 | pDevice->JackType = SND_JACK_HEADSET; 1213 | rt5682s_reg_write(pDevice, RT5682S_SAR_IL_CMD_3, 0x024c); 1214 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1215 | RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN); 1216 | rt5682s_reg_update(pDevice, RT5682S_SAR_IL_CMD_1, 1217 | RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT); 1218 | 1219 | rt5682s_enable_push_button_irq(pDevice, true); 1220 | rt5682s_sar_power_mode(pDevice, SAR_PWR_NORMAL); 1221 | break; 1222 | default: 1223 | pDevice->JackType = SND_JACK_HEADPHONE; 1224 | } 1225 | 1226 | rt5682s_reg_update(pDevice, RT5682S_HP_CHARGE_PUMP_2, 1227 | RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK, 1228 | RT5682S_OSW_L_EN | RT5682S_OSW_R_EN); 1229 | } 1230 | else { 1231 | rt5682s_sar_power_mode(pDevice, SAR_PWR_OFF); 1232 | rt5682s_enable_push_button_irq(pDevice, false); 1233 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1234 | RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW); 1235 | 1236 | rt5682s_reg_update(pDevice, RT5682S_PWR_ANLG_3, 1237 | RT5682S_PWR_CBJ, 0); 1238 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_1, 1239 | RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS); 1240 | rt5682s_reg_update(pDevice, RT5682S_CBJ_CTRL_3, 1241 | RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS); 1242 | 1243 | pDevice->JackType = 0; 1244 | } 1245 | 1246 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1247 | "Jack Type: %d\n", pDevice->JackType); 1248 | return pDevice->JackType; 1249 | } 1250 | 1251 | static int rt5682s_button_detect(PRTEK_CONTEXT pDevice) 1252 | { 1253 | UINT16 btn_type, val; 1254 | 1255 | rt5682s_reg_read(pDevice, RT5682S_4BTN_IL_CMD_1, &val); 1256 | btn_type = val & 0xfff0; 1257 | rt5682s_reg_write(pDevice, RT5682S_4BTN_IL_CMD_1, val); 1258 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1259 | "btn_type=%x\n", btn_type); 1260 | rt5682s_reg_update(pDevice, 1261 | RT5682S_SAR_IL_CMD_2, RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY); 1262 | 1263 | return btn_type; 1264 | } 1265 | 1266 | void rt5682s_jackdetect(PRTEK_CONTEXT pDevice) { 1267 | NTSTATUS status = STATUS_SUCCESS; 1268 | 1269 | UINT16 val; 1270 | status = rt5682s_reg_read(pDevice, RT5682S_AJD1_CTRL, &val); 1271 | if (!NT_SUCCESS(status)) { 1272 | DbgPrint("Failed to read jack detect\n"); 1273 | return; 1274 | } 1275 | 1276 | val = val & RT5682S_JDH_RS_MASK; 1277 | if (!val) { 1278 | /* jack in */ 1279 | if (pDevice->JackType == 0) { 1280 | /* jack was out, report jack type */ 1281 | pDevice->JackType = rt5682s_headset_detect(pDevice, 1); 1282 | } 1283 | else if ((pDevice->JackType & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 1284 | /* jack is already in, report button event */ 1285 | int btn_type = rt5682s_button_detect(pDevice); 1286 | /** 1287 | * rt5682 can report three kinds of button behavior, 1288 | * one click, double click and hold. However, 1289 | * currently we will report button pressed/released 1290 | * event. So all the three button behaviors are 1291 | * treated as button pressed. 1292 | */ 1293 | int rawButton = 0; 1294 | 1295 | switch (btn_type) { 1296 | case 0x8000: 1297 | case 0x4000: 1298 | case 0x2000: 1299 | rawButton = 1; 1300 | break; 1301 | case 0x1000: 1302 | case 0x0800: 1303 | case 0x0400: 1304 | rawButton = 2; 1305 | break; 1306 | case 0x0200: 1307 | case 0x0100: 1308 | case 0x0080: 1309 | rawButton = 3; 1310 | break; 1311 | case 0x0040: 1312 | case 0x0020: 1313 | case 0x0010: 1314 | rawButton = 4; 1315 | break; 1316 | case 0x0000: /* unpressed */ 1317 | break; 1318 | default: 1319 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1320 | "Unexpected button code 0x%04x\n", 1321 | btn_type); 1322 | break; 1323 | } 1324 | 1325 | Rt5682MediaReport report; 1326 | report.ReportID = REPORTID_MEDIA; 1327 | report.ControlCode = rawButton; 1328 | 1329 | size_t bytesWritten; 1330 | Rt5682ProcessVendorReport(pDevice, &report, sizeof(report), &bytesWritten); 1331 | } 1332 | } 1333 | else { 1334 | /* jack out */ 1335 | pDevice->JackType = rt5682s_headset_detect(pDevice, 0); 1336 | } 1337 | 1338 | CsAudioSpecialKeyReport report; 1339 | report.ReportID = REPORTID_SPECKEYS; 1340 | report.ControlCode = CONTROL_CODE_JACK_TYPE; 1341 | report.ControlValue = pDevice->JackType; 1342 | 1343 | size_t bytesWritten; 1344 | Rt5682ProcessVendorReport(pDevice, &report, sizeof(report), &bytesWritten); 1345 | } 1346 | 1347 | VOID 1348 | RtekJdetWorkItem( 1349 | IN WDFWORKITEM WorkItem 1350 | ) 1351 | { 1352 | WDFDEVICE Device = (WDFDEVICE)WdfWorkItemGetParentObject(WorkItem); 1353 | PRTEK_CONTEXT pDevice = GetDeviceContext(Device); 1354 | 1355 | rt5682s_jackdetect(pDevice); 1356 | 1357 | if (GetPlatform() == PlatformRyzenCezanne) { //Speakers are managed by jack driver on Cezanne 1358 | if (pDevice->JackType) { 1359 | StartStopSpeaker(pDevice, FALSE); 1360 | } 1361 | else { 1362 | StartStopSpeaker(pDevice, pDevice->HeadphonePlaying); 1363 | } 1364 | } 1365 | } 1366 | 1367 | BOOLEAN OnInterruptIsr( 1368 | WDFINTERRUPT Interrupt, 1369 | ULONG MessageID) { 1370 | UNREFERENCED_PARAMETER(MessageID); 1371 | 1372 | WDFDEVICE Device = WdfInterruptGetDevice(Interrupt); 1373 | PRTEK_CONTEXT pDevice = GetDeviceContext(Device); 1374 | 1375 | if (!pDevice->ConnectInterrupt) 1376 | return true; 1377 | 1378 | NTSTATUS status = STATUS_SUCCESS; 1379 | 1380 | WDF_OBJECT_ATTRIBUTES attributes; 1381 | WDF_WORKITEM_CONFIG workitemConfig; 1382 | WDFWORKITEM hWorkItem; 1383 | 1384 | WDF_OBJECT_ATTRIBUTES_INIT(&attributes); 1385 | WDF_OBJECT_ATTRIBUTES_SET_CONTEXT_TYPE(&attributes, RTEK_CONTEXT); 1386 | attributes.ParentObject = Device; 1387 | WDF_WORKITEM_CONFIG_INIT(&workitemConfig, RtekJdetWorkItem); 1388 | 1389 | WdfWorkItemCreate(&workitemConfig, 1390 | &attributes, 1391 | &hWorkItem); 1392 | 1393 | WdfWorkItemEnqueue(hWorkItem); 1394 | 1395 | return true; 1396 | } 1397 | 1398 | NTSTATUS 1399 | Rt5682EvtDeviceAdd( 1400 | IN WDFDRIVER Driver, 1401 | IN PWDFDEVICE_INIT DeviceInit 1402 | ) 1403 | { 1404 | NTSTATUS status = STATUS_SUCCESS; 1405 | WDF_IO_QUEUE_CONFIG queueConfig; 1406 | WDF_OBJECT_ATTRIBUTES attributes; 1407 | WDFDEVICE device; 1408 | WDF_INTERRUPT_CONFIG interruptConfig; 1409 | WDFQUEUE queue; 1410 | UCHAR minorFunction; 1411 | PRTEK_CONTEXT devContext; 1412 | 1413 | UNREFERENCED_PARAMETER(Driver); 1414 | 1415 | PAGED_CODE(); 1416 | 1417 | RtekPrint(DEBUG_LEVEL_INFO, DBG_PNP, 1418 | "Rt5682EvtDeviceAdd called\n"); 1419 | 1420 | // 1421 | // Tell framework this is a filter driver. Filter drivers by default are 1422 | // not power policy owners. This works well for this driver because 1423 | // HIDclass driver is the power policy owner for HID minidrivers. 1424 | // 1425 | 1426 | WdfFdoInitSetFilter(DeviceInit); 1427 | 1428 | { 1429 | WDF_PNPPOWER_EVENT_CALLBACKS pnpCallbacks; 1430 | WDF_PNPPOWER_EVENT_CALLBACKS_INIT(&pnpCallbacks); 1431 | 1432 | pnpCallbacks.EvtDevicePrepareHardware = OnPrepareHardware; 1433 | pnpCallbacks.EvtDeviceReleaseHardware = OnReleaseHardware; 1434 | pnpCallbacks.EvtDeviceSelfManagedIoInit = OnSelfManagedIoInit; 1435 | pnpCallbacks.EvtDeviceD0Entry = OnD0Entry; 1436 | pnpCallbacks.EvtDeviceD0Exit = OnD0Exit; 1437 | 1438 | WdfDeviceInitSetPnpPowerEventCallbacks(DeviceInit, &pnpCallbacks); 1439 | } 1440 | 1441 | // 1442 | // Setup the device context 1443 | // 1444 | 1445 | WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, RTEK_CONTEXT); 1446 | 1447 | // 1448 | // Create a framework device object.This call will in turn create 1449 | // a WDM device object, attach to the lower stack, and set the 1450 | // appropriate flags and attributes. 1451 | // 1452 | 1453 | status = WdfDeviceCreate(&DeviceInit, &attributes, &device); 1454 | 1455 | if (!NT_SUCCESS(status)) 1456 | { 1457 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1458 | "WdfDeviceCreate failed with status code 0x%x\n", status); 1459 | 1460 | return status; 1461 | } 1462 | 1463 | { 1464 | WDF_DEVICE_STATE deviceState; 1465 | WDF_DEVICE_STATE_INIT(&deviceState); 1466 | 1467 | deviceState.NotDisableable = WdfFalse; 1468 | WdfDeviceSetDeviceState(device, &deviceState); 1469 | } 1470 | 1471 | WDF_IO_QUEUE_CONFIG_INIT_DEFAULT_QUEUE(&queueConfig, WdfIoQueueDispatchParallel); 1472 | 1473 | queueConfig.EvtIoInternalDeviceControl = Rt5682EvtInternalDeviceControl; 1474 | 1475 | status = WdfIoQueueCreate(device, 1476 | &queueConfig, 1477 | WDF_NO_OBJECT_ATTRIBUTES, 1478 | &queue 1479 | ); 1480 | 1481 | if (!NT_SUCCESS(status)) 1482 | { 1483 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1484 | "WdfIoQueueCreate failed 0x%x\n", status); 1485 | 1486 | return status; 1487 | } 1488 | 1489 | // 1490 | // Create manual I/O queue to take care of hid report read requests 1491 | // 1492 | 1493 | devContext = GetDeviceContext(device); 1494 | 1495 | devContext->FxDevice = device; 1496 | 1497 | devContext->ReclockRequested = FALSE; 1498 | 1499 | WDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchManual); 1500 | 1501 | queueConfig.PowerManaged = WdfFalse; 1502 | 1503 | status = WdfIoQueueCreate(device, 1504 | &queueConfig, 1505 | WDF_NO_OBJECT_ATTRIBUTES, 1506 | &devContext->ReportQueue 1507 | ); 1508 | 1509 | if (!NT_SUCCESS(status)) 1510 | { 1511 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1512 | "WdfIoQueueCreate failed 0x%x\n", status); 1513 | 1514 | return status; 1515 | } 1516 | 1517 | // 1518 | // Create manual I/O queue to take care of idle power requests 1519 | // 1520 | 1521 | WDF_IO_QUEUE_CONFIG_INIT(&queueConfig, WdfIoQueueDispatchManual); 1522 | 1523 | queueConfig.PowerManaged = WdfFalse; 1524 | 1525 | status = WdfIoQueueCreate(device, 1526 | &queueConfig, 1527 | WDF_NO_OBJECT_ATTRIBUTES, 1528 | &devContext->IdleQueue 1529 | ); 1530 | 1531 | if (!NT_SUCCESS(status)) 1532 | { 1533 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1534 | "WdfIoQueueCreate failed 0x%x\n", status); 1535 | 1536 | return status; 1537 | } 1538 | 1539 | // 1540 | // Create an interrupt object for hardware notifications 1541 | // 1542 | WDF_INTERRUPT_CONFIG_INIT( 1543 | &interruptConfig, 1544 | OnInterruptIsr, 1545 | NULL); 1546 | interruptConfig.PassiveHandling = TRUE; 1547 | 1548 | status = WdfInterruptCreate( 1549 | device, 1550 | &interruptConfig, 1551 | WDF_NO_OBJECT_ATTRIBUTES, 1552 | &devContext->Interrupt); 1553 | 1554 | if (!NT_SUCCESS(status)) 1555 | { 1556 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_PNP, 1557 | "Error creating WDF interrupt object - %!STATUS!", 1558 | status); 1559 | 1560 | return status; 1561 | } 1562 | 1563 | return status; 1564 | } 1565 | 1566 | void 1567 | RtekIdleIrpWorkItem 1568 | ( 1569 | IN WDFWORKITEM IdleWorkItem 1570 | ) 1571 | { 1572 | NTSTATUS status; 1573 | PIDLE_WORKITEM_CONTEXT idleWorkItemContext; 1574 | PRTEK_CONTEXT deviceContext; 1575 | PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO idleCallbackInfo; 1576 | 1577 | idleWorkItemContext = GetIdleWorkItemContext(IdleWorkItem); 1578 | NT_ASSERT(idleWorkItemContext != NULL); 1579 | 1580 | deviceContext = GetDeviceContext(idleWorkItemContext->FxDevice); 1581 | NT_ASSERT(deviceContext != NULL); 1582 | 1583 | // 1584 | // Get the idle callback info from the workitem context 1585 | // 1586 | PIRP irp = WdfRequestWdmGetIrp(idleWorkItemContext->FxRequest); 1587 | PIO_STACK_LOCATION stackLocation = IoGetCurrentIrpStackLocation(irp); 1588 | 1589 | idleCallbackInfo = (PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO) 1590 | (stackLocation->Parameters.DeviceIoControl.Type3InputBuffer); 1591 | 1592 | // 1593 | // idleCallbackInfo is validated already, so invoke idle callback 1594 | // 1595 | idleCallbackInfo->IdleCallback(idleCallbackInfo->IdleContext); 1596 | 1597 | // 1598 | // Park this request in our IdleQueue and mark it as pending 1599 | // This way if the IRP was cancelled, WDF will cancel it for us 1600 | // 1601 | status = WdfRequestForwardToIoQueue( 1602 | idleWorkItemContext->FxRequest, 1603 | deviceContext->IdleQueue); 1604 | 1605 | if (!NT_SUCCESS(status)) 1606 | { 1607 | // 1608 | // IdleQueue is a manual-dispatch, non-power-managed queue. This should 1609 | // *never* fail. 1610 | // 1611 | 1612 | NT_ASSERTMSG("WdfRequestForwardToIoQueue to IdleQueue failed!", FALSE); 1613 | 1614 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1615 | "Error forwarding idle notification Request:0x%p to IdleQueue:0x%p - %!STATUS!", 1616 | idleWorkItemContext->FxRequest, 1617 | deviceContext->IdleQueue, 1618 | status); 1619 | 1620 | // 1621 | // Complete the request if we couldnt forward to the Idle Queue 1622 | // 1623 | WdfRequestComplete(idleWorkItemContext->FxRequest, status); 1624 | } 1625 | else 1626 | { 1627 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1628 | "Forwarded idle notification Request:0x%p to IdleQueue:0x%p - %!STATUS!", 1629 | idleWorkItemContext->FxRequest, 1630 | deviceContext->IdleQueue, 1631 | status); 1632 | } 1633 | 1634 | // 1635 | // Delete the workitem since we're done with it 1636 | // 1637 | WdfObjectDelete(IdleWorkItem); 1638 | 1639 | return; 1640 | } 1641 | 1642 | NTSTATUS 1643 | Rt5682ProcessIdleRequest( 1644 | IN PRTEK_CONTEXT pDevice, 1645 | IN WDFREQUEST Request, 1646 | OUT BOOLEAN* Complete 1647 | ) 1648 | { 1649 | PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO idleCallbackInfo; 1650 | PIRP irp; 1651 | PIO_STACK_LOCATION irpSp; 1652 | NTSTATUS status; 1653 | 1654 | NT_ASSERT(Complete != NULL); 1655 | *Complete = TRUE; 1656 | 1657 | // 1658 | // Retrieve request parameters and validate 1659 | // 1660 | irp = WdfRequestWdmGetIrp(Request); 1661 | irpSp = IoGetCurrentIrpStackLocation(irp); 1662 | 1663 | if (irpSp->Parameters.DeviceIoControl.InputBufferLength < 1664 | sizeof(HID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO)) 1665 | { 1666 | status = STATUS_INVALID_BUFFER_SIZE; 1667 | 1668 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1669 | "Error: Input buffer is too small to process idle request - %!STATUS!", 1670 | status); 1671 | 1672 | goto exit; 1673 | } 1674 | 1675 | // 1676 | // Grab the callback 1677 | // 1678 | idleCallbackInfo = (PHID_SUBMIT_IDLE_NOTIFICATION_CALLBACK_INFO) 1679 | irpSp->Parameters.DeviceIoControl.Type3InputBuffer; 1680 | 1681 | NT_ASSERT(idleCallbackInfo != NULL); 1682 | 1683 | if (idleCallbackInfo == NULL || idleCallbackInfo->IdleCallback == NULL) 1684 | { 1685 | status = STATUS_NO_CALLBACK_ACTIVE; 1686 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1687 | "Error: Idle Notification request %p has no idle callback info - %!STATUS!", 1688 | Request, 1689 | status); 1690 | goto exit; 1691 | } 1692 | 1693 | { 1694 | // 1695 | // Create a workitem for the idle callback 1696 | // 1697 | WDF_OBJECT_ATTRIBUTES workItemAttributes; 1698 | WDF_WORKITEM_CONFIG workitemConfig; 1699 | WDFWORKITEM idleWorkItem; 1700 | PIDLE_WORKITEM_CONTEXT idleWorkItemContext; 1701 | 1702 | WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&workItemAttributes, IDLE_WORKITEM_CONTEXT); 1703 | workItemAttributes.ParentObject = pDevice->FxDevice; 1704 | 1705 | WDF_WORKITEM_CONFIG_INIT(&workitemConfig, RtekIdleIrpWorkItem); 1706 | 1707 | status = WdfWorkItemCreate( 1708 | &workitemConfig, 1709 | &workItemAttributes, 1710 | &idleWorkItem 1711 | ); 1712 | 1713 | if (!NT_SUCCESS(status)) { 1714 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1715 | "Error creating creating idle work item - %!STATUS!", 1716 | status); 1717 | goto exit; 1718 | } 1719 | 1720 | // 1721 | // Set the workitem context 1722 | // 1723 | idleWorkItemContext = GetIdleWorkItemContext(idleWorkItem); 1724 | idleWorkItemContext->FxDevice = pDevice->FxDevice; 1725 | idleWorkItemContext->FxRequest = Request; 1726 | 1727 | // 1728 | // Enqueue a workitem for the idle callback 1729 | // 1730 | WdfWorkItemEnqueue(idleWorkItem); 1731 | 1732 | // 1733 | // Mark the request as pending so that 1734 | // we can complete it when we come out of idle 1735 | // 1736 | *Complete = FALSE; 1737 | } 1738 | 1739 | exit: 1740 | 1741 | return status; 1742 | } 1743 | 1744 | VOID 1745 | RtekCompleteIdleIrp( 1746 | IN PRTEK_CONTEXT FxDeviceContext 1747 | ) 1748 | /*++ 1749 | 1750 | Routine Description: 1751 | 1752 | This is invoked when we enter D0. 1753 | We simply complete the Idle Irp if it hasn't been cancelled already. 1754 | 1755 | Arguments: 1756 | 1757 | FxDeviceContext - Pointer to Device Context for the device 1758 | 1759 | Return Value: 1760 | 1761 | 1762 | 1763 | --*/ 1764 | { 1765 | NTSTATUS status; 1766 | WDFREQUEST request = NULL; 1767 | 1768 | // 1769 | // Lets try to retrieve the Idle IRP from the Idle queue 1770 | // 1771 | status = WdfIoQueueRetrieveNextRequest( 1772 | FxDeviceContext->IdleQueue, 1773 | &request); 1774 | 1775 | // 1776 | // We did not find the Idle IRP, maybe it was cancelled 1777 | // 1778 | if (!NT_SUCCESS(status) || (request == NULL)) 1779 | { 1780 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1781 | "Error finding idle notification request in IdleQueue:0x%p - %!STATUS!", 1782 | FxDeviceContext->IdleQueue, 1783 | status); 1784 | } 1785 | else 1786 | { 1787 | // 1788 | // Complete the Idle IRP 1789 | // 1790 | WdfRequestComplete(request, status); 1791 | 1792 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1793 | "Completed idle notification Request:0x%p from IdleQueue:0x%p - %!STATUS!", 1794 | request, 1795 | FxDeviceContext->IdleQueue, 1796 | status); 1797 | } 1798 | 1799 | return; 1800 | } 1801 | 1802 | VOID 1803 | Rt5682EvtInternalDeviceControl( 1804 | IN WDFQUEUE Queue, 1805 | IN WDFREQUEST Request, 1806 | IN size_t OutputBufferLength, 1807 | IN size_t InputBufferLength, 1808 | IN ULONG IoControlCode 1809 | ) 1810 | { 1811 | NTSTATUS status = STATUS_SUCCESS; 1812 | WDFDEVICE device; 1813 | PRTEK_CONTEXT devContext; 1814 | BOOLEAN completeRequest = TRUE; 1815 | 1816 | UNREFERENCED_PARAMETER(OutputBufferLength); 1817 | UNREFERENCED_PARAMETER(InputBufferLength); 1818 | 1819 | device = WdfIoQueueGetDevice(Queue); 1820 | devContext = GetDeviceContext(device); 1821 | 1822 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1823 | "%s, Queue:0x%p, Request:0x%p\n", 1824 | DbgHidInternalIoctlString(IoControlCode), 1825 | Queue, 1826 | Request 1827 | ); 1828 | 1829 | // 1830 | // Please note that HIDCLASS provides the buffer in the Irp->UserBuffer 1831 | // field irrespective of the ioctl buffer type. However, framework is very 1832 | // strict about type checking. You cannot get Irp->UserBuffer by using 1833 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 1834 | // internal ioctl. So depending on the ioctl code, we will either 1835 | // use retreive function or escape to WDM to get the UserBuffer. 1836 | // 1837 | 1838 | switch (IoControlCode) 1839 | { 1840 | 1841 | case IOCTL_HID_GET_DEVICE_DESCRIPTOR: 1842 | // 1843 | // Retrieves the device's HID descriptor. 1844 | // 1845 | status = Rt5682GetHidDescriptor(device, Request); 1846 | break; 1847 | 1848 | case IOCTL_HID_GET_DEVICE_ATTRIBUTES: 1849 | // 1850 | //Retrieves a device's attributes in a HID_DEVICE_ATTRIBUTES structure. 1851 | // 1852 | status = Rt5682GetDeviceAttributes(Request); 1853 | break; 1854 | 1855 | case IOCTL_HID_GET_REPORT_DESCRIPTOR: 1856 | // 1857 | //Obtains the report descriptor for the HID device. 1858 | // 1859 | status = Rt5682GetReportDescriptor(device, Request); 1860 | break; 1861 | 1862 | case IOCTL_HID_GET_STRING: 1863 | // 1864 | // Requests that the HID minidriver retrieve a human-readable string 1865 | // for either the manufacturer ID, the product ID, or the serial number 1866 | // from the string descriptor of the device. The minidriver must send 1867 | // a Get String Descriptor request to the device, in order to retrieve 1868 | // the string descriptor, then it must extract the string at the 1869 | // appropriate index from the string descriptor and return it in the 1870 | // output buffer indicated by the IRP. Before sending the Get String 1871 | // Descriptor request, the minidriver must retrieve the appropriate 1872 | // index for the manufacturer ID, the product ID or the serial number 1873 | // from the device extension of a top level collection associated with 1874 | // the device. 1875 | // 1876 | status = Rt5682GetString(Request); 1877 | break; 1878 | 1879 | case IOCTL_HID_WRITE_REPORT: 1880 | case IOCTL_HID_SET_OUTPUT_REPORT: 1881 | // 1882 | //Transmits a class driver-supplied report to the device. 1883 | // 1884 | status = Rt5682WriteReport(devContext, Request); 1885 | break; 1886 | 1887 | case IOCTL_HID_READ_REPORT: 1888 | case IOCTL_HID_GET_INPUT_REPORT: 1889 | // 1890 | // Returns a report from the device into a class driver-supplied buffer. 1891 | // 1892 | status = Rt5682ReadReport(devContext, Request, &completeRequest); 1893 | break; 1894 | 1895 | case IOCTL_HID_SET_FEATURE: 1896 | // 1897 | // This sends a HID class feature report to a top-level collection of 1898 | // a HID class device. 1899 | // 1900 | status = Rt5682SetFeature(devContext, Request, &completeRequest); 1901 | break; 1902 | 1903 | case IOCTL_HID_GET_FEATURE: 1904 | // 1905 | // returns a feature report associated with a top-level collection 1906 | status = Rt5682GetFeature(devContext, Request, &completeRequest); 1907 | break; 1908 | 1909 | case IOCTL_HID_SEND_IDLE_NOTIFICATION_REQUEST: 1910 | //Handle HID Idle request 1911 | status = Rt5682ProcessIdleRequest(devContext, Request, &completeRequest); 1912 | break; 1913 | 1914 | case IOCTL_HID_ACTIVATE_DEVICE: 1915 | // 1916 | // Makes the device ready for I/O operations. 1917 | // 1918 | case IOCTL_HID_DEACTIVATE_DEVICE: 1919 | // 1920 | // Causes the device to cease operations and terminate all outstanding 1921 | // I/O requests. 1922 | // 1923 | default: 1924 | status = STATUS_NOT_SUPPORTED; 1925 | break; 1926 | } 1927 | 1928 | if (completeRequest) 1929 | { 1930 | WdfRequestComplete(Request, status); 1931 | 1932 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1933 | "%s completed, Queue:0x%p, Request:0x%p\n", 1934 | DbgHidInternalIoctlString(IoControlCode), 1935 | Queue, 1936 | Request 1937 | ); 1938 | } 1939 | else 1940 | { 1941 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 1942 | "%s deferred, Queue:0x%p, Request:0x%p\n", 1943 | DbgHidInternalIoctlString(IoControlCode), 1944 | Queue, 1945 | Request 1946 | ); 1947 | } 1948 | 1949 | return; 1950 | } 1951 | 1952 | NTSTATUS 1953 | Rt5682GetHidDescriptor( 1954 | IN WDFDEVICE Device, 1955 | IN WDFREQUEST Request 1956 | ) 1957 | { 1958 | NTSTATUS status = STATUS_SUCCESS; 1959 | size_t bytesToCopy = 0; 1960 | WDFMEMORY memory; 1961 | 1962 | UNREFERENCED_PARAMETER(Device); 1963 | 1964 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 1965 | "Rt5682GetHidDescriptor Entry\n"); 1966 | 1967 | // 1968 | // This IOCTL is METHOD_NEITHER so WdfRequestRetrieveOutputMemory 1969 | // will correctly retrieve buffer from Irp->UserBuffer. 1970 | // Remember that HIDCLASS provides the buffer in the Irp->UserBuffer 1971 | // field irrespective of the ioctl buffer type. However, framework is very 1972 | // strict about type checking. You cannot get Irp->UserBuffer by using 1973 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 1974 | // internal ioctl. 1975 | // 1976 | status = WdfRequestRetrieveOutputMemory(Request, &memory); 1977 | 1978 | if (!NT_SUCCESS(status)) 1979 | { 1980 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1981 | "WdfRequestRetrieveOutputMemory failed 0x%x\n", status); 1982 | 1983 | return status; 1984 | } 1985 | 1986 | // 1987 | // Use hardcoded "HID Descriptor" 1988 | // 1989 | bytesToCopy = DefaultHidDescriptor.bLength; 1990 | 1991 | if (bytesToCopy == 0) 1992 | { 1993 | status = STATUS_INVALID_DEVICE_STATE; 1994 | 1995 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 1996 | "DefaultHidDescriptor is zero, 0x%x\n", status); 1997 | 1998 | return status; 1999 | } 2000 | 2001 | status = WdfMemoryCopyFromBuffer(memory, 2002 | 0, // Offset 2003 | (PVOID)&DefaultHidDescriptor, 2004 | bytesToCopy); 2005 | 2006 | if (!NT_SUCCESS(status)) 2007 | { 2008 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2009 | "WdfMemoryCopyFromBuffer failed 0x%x\n", status); 2010 | 2011 | return status; 2012 | } 2013 | 2014 | // 2015 | // Report how many bytes were copied 2016 | // 2017 | WdfRequestSetInformation(Request, bytesToCopy); 2018 | 2019 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2020 | "Rt5682GetHidDescriptor Exit = 0x%x\n", status); 2021 | 2022 | return status; 2023 | } 2024 | 2025 | NTSTATUS 2026 | Rt5682GetReportDescriptor( 2027 | IN WDFDEVICE Device, 2028 | IN WDFREQUEST Request 2029 | ) 2030 | { 2031 | NTSTATUS status = STATUS_SUCCESS; 2032 | ULONG_PTR bytesToCopy; 2033 | WDFMEMORY memory; 2034 | 2035 | PRTEK_CONTEXT devContext = GetDeviceContext(Device); 2036 | 2037 | UNREFERENCED_PARAMETER(Device); 2038 | 2039 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2040 | "Rt5682GetReportDescriptor Entry\n"); 2041 | 2042 | // 2043 | // This IOCTL is METHOD_NEITHER so WdfRequestRetrieveOutputMemory 2044 | // will correctly retrieve buffer from Irp->UserBuffer. 2045 | // Remember that HIDCLASS provides the buffer in the Irp->UserBuffer 2046 | // field irrespective of the ioctl buffer type. However, framework is very 2047 | // strict about type checking. You cannot get Irp->UserBuffer by using 2048 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 2049 | // internal ioctl. 2050 | // 2051 | status = WdfRequestRetrieveOutputMemory(Request, &memory); 2052 | if (!NT_SUCCESS(status)) 2053 | { 2054 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2055 | "WdfRequestRetrieveOutputMemory failed 0x%x\n", status); 2056 | 2057 | return status; 2058 | } 2059 | 2060 | // 2061 | // Use hardcoded Report descriptor 2062 | // 2063 | bytesToCopy = DefaultHidDescriptor.DescriptorList[0].wReportLength; 2064 | 2065 | if (bytesToCopy == 0) 2066 | { 2067 | status = STATUS_INVALID_DEVICE_STATE; 2068 | 2069 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2070 | "DefaultHidDescriptor's reportLength is zero, 0x%x\n", status); 2071 | 2072 | return status; 2073 | } 2074 | 2075 | status = WdfMemoryCopyFromBuffer(memory, 2076 | 0, 2077 | (PVOID)DefaultReportDescriptor, 2078 | bytesToCopy); 2079 | if (!NT_SUCCESS(status)) 2080 | { 2081 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2082 | "WdfMemoryCopyFromBuffer failed 0x%x\n", status); 2083 | 2084 | return status; 2085 | } 2086 | 2087 | // 2088 | // Report how many bytes were copied 2089 | // 2090 | WdfRequestSetInformation(Request, bytesToCopy); 2091 | 2092 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2093 | "Rt5682GetReportDescriptor Exit = 0x%x\n", status); 2094 | 2095 | return status; 2096 | } 2097 | 2098 | 2099 | NTSTATUS 2100 | Rt5682GetDeviceAttributes( 2101 | IN WDFREQUEST Request 2102 | ) 2103 | { 2104 | NTSTATUS status = STATUS_SUCCESS; 2105 | PHID_DEVICE_ATTRIBUTES deviceAttributes = NULL; 2106 | 2107 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2108 | "Rt5682GetDeviceAttributes Entry\n"); 2109 | 2110 | // 2111 | // This IOCTL is METHOD_NEITHER so WdfRequestRetrieveOutputMemory 2112 | // will correctly retrieve buffer from Irp->UserBuffer. 2113 | // Remember that HIDCLASS provides the buffer in the Irp->UserBuffer 2114 | // field irrespective of the ioctl buffer type. However, framework is very 2115 | // strict about type checking. You cannot get Irp->UserBuffer by using 2116 | // WdfRequestRetrieveOutputMemory if the ioctl is not a METHOD_NEITHER 2117 | // internal ioctl. 2118 | // 2119 | status = WdfRequestRetrieveOutputBuffer(Request, 2120 | sizeof(HID_DEVICE_ATTRIBUTES), 2121 | (PVOID *)&deviceAttributes, 2122 | NULL); 2123 | if (!NT_SUCCESS(status)) 2124 | { 2125 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2126 | "WdfRequestRetrieveOutputBuffer failed 0x%x\n", status); 2127 | 2128 | return status; 2129 | } 2130 | 2131 | // 2132 | // Set USB device descriptor 2133 | // 2134 | 2135 | deviceAttributes->Size = sizeof(HID_DEVICE_ATTRIBUTES); 2136 | deviceAttributes->VendorID = RT5682_VID; 2137 | deviceAttributes->ProductID = RT5682_PID; 2138 | deviceAttributes->VersionNumber = RT5682_VERSION; 2139 | 2140 | // 2141 | // Report how many bytes were copied 2142 | // 2143 | WdfRequestSetInformation(Request, sizeof(HID_DEVICE_ATTRIBUTES)); 2144 | 2145 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2146 | "Rt5682GetDeviceAttributes Exit = 0x%x\n", status); 2147 | 2148 | return status; 2149 | } 2150 | 2151 | NTSTATUS 2152 | Rt5682GetString( 2153 | IN WDFREQUEST Request 2154 | ) 2155 | { 2156 | 2157 | NTSTATUS status = STATUS_SUCCESS; 2158 | PWSTR pwstrID; 2159 | size_t lenID; 2160 | WDF_REQUEST_PARAMETERS params; 2161 | void *pStringBuffer = NULL; 2162 | 2163 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2164 | "Rt5682GetString Entry\n"); 2165 | 2166 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2167 | WdfRequestGetParameters(Request, ¶ms); 2168 | 2169 | switch ((ULONG_PTR)params.Parameters.DeviceIoControl.Type3InputBuffer & 0xFFFF) 2170 | { 2171 | case HID_STRING_ID_IMANUFACTURER: 2172 | pwstrID = L"Rt5682.\0"; 2173 | break; 2174 | 2175 | case HID_STRING_ID_IPRODUCT: 2176 | pwstrID = L"MaxTouch Touch Screen\0"; 2177 | break; 2178 | 2179 | case HID_STRING_ID_ISERIALNUMBER: 2180 | pwstrID = L"123123123\0"; 2181 | break; 2182 | 2183 | default: 2184 | pwstrID = NULL; 2185 | break; 2186 | } 2187 | 2188 | lenID = pwstrID ? wcslen(pwstrID) * sizeof(WCHAR) + sizeof(UNICODE_NULL) : 0; 2189 | 2190 | if (pwstrID == NULL) 2191 | { 2192 | 2193 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2194 | "Rt5682GetString Invalid request type\n"); 2195 | 2196 | status = STATUS_INVALID_PARAMETER; 2197 | 2198 | return status; 2199 | } 2200 | 2201 | status = WdfRequestRetrieveOutputBuffer(Request, 2202 | lenID, 2203 | &pStringBuffer, 2204 | &lenID); 2205 | 2206 | if (!NT_SUCCESS(status)) 2207 | { 2208 | 2209 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2210 | "Rt5682GetString WdfRequestRetrieveOutputBuffer failed Status 0x%x\n", status); 2211 | 2212 | return status; 2213 | } 2214 | 2215 | RtlCopyMemory(pStringBuffer, pwstrID, lenID); 2216 | 2217 | WdfRequestSetInformation(Request, lenID); 2218 | 2219 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2220 | "Rt5682GetString Exit = 0x%x\n", status); 2221 | 2222 | return status; 2223 | } 2224 | 2225 | NTSTATUS 2226 | Rt5682WriteReport( 2227 | IN PRTEK_CONTEXT DevContext, 2228 | IN WDFREQUEST Request 2229 | ) 2230 | { 2231 | NTSTATUS status = STATUS_SUCCESS; 2232 | WDF_REQUEST_PARAMETERS params; 2233 | PHID_XFER_PACKET transferPacket = NULL; 2234 | size_t bytesWritten = 0; 2235 | 2236 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2237 | "Rt5682WriteReport Entry\n"); 2238 | 2239 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2240 | WdfRequestGetParameters(Request, ¶ms); 2241 | 2242 | if (params.Parameters.DeviceIoControl.InputBufferLength < sizeof(HID_XFER_PACKET)) 2243 | { 2244 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2245 | "Rt5682WriteReport Xfer packet too small\n"); 2246 | 2247 | status = STATUS_BUFFER_TOO_SMALL; 2248 | } 2249 | else 2250 | { 2251 | 2252 | transferPacket = (PHID_XFER_PACKET)WdfRequestWdmGetIrp(Request)->UserBuffer; 2253 | 2254 | if (transferPacket == NULL) 2255 | { 2256 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2257 | "Rt5682WriteReport No xfer packet\n"); 2258 | 2259 | status = STATUS_INVALID_DEVICE_REQUEST; 2260 | } 2261 | else 2262 | { 2263 | // 2264 | // switch on the report id 2265 | // 2266 | 2267 | switch (transferPacket->reportId) 2268 | { 2269 | case REPORTID_SPECKEYS: 2270 | status = STATUS_SUCCESS; 2271 | 2272 | CsAudioSpecialKeyReport report; 2273 | report.ReportID = REPORTID_SPECKEYS; 2274 | report.ControlCode = CONTROL_CODE_JACK_TYPE; 2275 | report.ControlValue = DevContext->JackType; 2276 | 2277 | size_t bytesWritten; 2278 | Rt5682ProcessVendorReport(DevContext, &report, sizeof(report), &bytesWritten); 2279 | break; 2280 | default: 2281 | 2282 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2283 | "Rt5682WriteReport Unhandled report type %d\n", transferPacket->reportId); 2284 | 2285 | status = STATUS_INVALID_PARAMETER; 2286 | 2287 | break; 2288 | } 2289 | } 2290 | } 2291 | 2292 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2293 | "Rt5682WriteReport Exit = 0x%x\n", status); 2294 | 2295 | return status; 2296 | 2297 | } 2298 | 2299 | NTSTATUS 2300 | Rt5682ProcessVendorReport( 2301 | IN PRTEK_CONTEXT DevContext, 2302 | IN PVOID ReportBuffer, 2303 | IN ULONG ReportBufferLen, 2304 | OUT size_t* BytesWritten 2305 | ) 2306 | { 2307 | NTSTATUS status = STATUS_SUCCESS; 2308 | WDFREQUEST reqRead; 2309 | PVOID pReadReport = NULL; 2310 | size_t bytesReturned = 0; 2311 | 2312 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2313 | "Rt5682ProcessVendorReport Entry\n"); 2314 | 2315 | status = WdfIoQueueRetrieveNextRequest(DevContext->ReportQueue, 2316 | &reqRead); 2317 | 2318 | if (NT_SUCCESS(status)) 2319 | { 2320 | status = WdfRequestRetrieveOutputBuffer(reqRead, 2321 | ReportBufferLen, 2322 | &pReadReport, 2323 | &bytesReturned); 2324 | 2325 | if (NT_SUCCESS(status)) 2326 | { 2327 | // 2328 | // Copy ReportBuffer into read request 2329 | // 2330 | 2331 | if (bytesReturned > ReportBufferLen) 2332 | { 2333 | bytesReturned = ReportBufferLen; 2334 | } 2335 | 2336 | RtlCopyMemory(pReadReport, 2337 | ReportBuffer, 2338 | bytesReturned); 2339 | 2340 | // 2341 | // Complete read with the number of bytes returned as info 2342 | // 2343 | 2344 | WdfRequestCompleteWithInformation(reqRead, 2345 | status, 2346 | bytesReturned); 2347 | 2348 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 2349 | "Rt5682ProcessVendorReport %d bytes returned\n", bytesReturned); 2350 | 2351 | // 2352 | // Return the number of bytes written for the write request completion 2353 | // 2354 | 2355 | *BytesWritten = bytesReturned; 2356 | 2357 | RtekPrint(DEBUG_LEVEL_INFO, DBG_IOCTL, 2358 | "%s completed, Queue:0x%p, Request:0x%p\n", 2359 | DbgHidInternalIoctlString(IOCTL_HID_READ_REPORT), 2360 | DevContext->ReportQueue, 2361 | reqRead); 2362 | } 2363 | else 2364 | { 2365 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2366 | "WdfRequestRetrieveOutputBuffer failed Status 0x%x\n", status); 2367 | } 2368 | } 2369 | else 2370 | { 2371 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2372 | "WdfIoQueueRetrieveNextRequest failed Status 0x%x\n", status); 2373 | } 2374 | 2375 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2376 | "Rt5682ProcessVendorReport Exit = 0x%x\n", status); 2377 | 2378 | return status; 2379 | } 2380 | 2381 | NTSTATUS 2382 | Rt5682ReadReport( 2383 | IN PRTEK_CONTEXT DevContext, 2384 | IN WDFREQUEST Request, 2385 | OUT BOOLEAN* CompleteRequest 2386 | ) 2387 | { 2388 | NTSTATUS status = STATUS_SUCCESS; 2389 | 2390 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2391 | "Rt5682ReadReport Entry\n"); 2392 | 2393 | // 2394 | // Forward this read request to our manual queue 2395 | // (in other words, we are going to defer this request 2396 | // until we have a corresponding write request to 2397 | // match it with) 2398 | // 2399 | 2400 | status = WdfRequestForwardToIoQueue(Request, DevContext->ReportQueue); 2401 | 2402 | if (!NT_SUCCESS(status)) 2403 | { 2404 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2405 | "WdfRequestForwardToIoQueue failed Status 0x%x\n", status); 2406 | } 2407 | else 2408 | { 2409 | *CompleteRequest = FALSE; 2410 | } 2411 | 2412 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2413 | "Rt5682ReadReport Exit = 0x%x\n", status); 2414 | 2415 | return status; 2416 | } 2417 | 2418 | NTSTATUS 2419 | Rt5682SetFeature( 2420 | IN PRTEK_CONTEXT DevContext, 2421 | IN WDFREQUEST Request, 2422 | OUT BOOLEAN* CompleteRequest 2423 | ) 2424 | { 2425 | NTSTATUS status = STATUS_SUCCESS; 2426 | WDF_REQUEST_PARAMETERS params; 2427 | PHID_XFER_PACKET transferPacket = NULL; 2428 | 2429 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2430 | "Rt5682SetFeature Entry\n"); 2431 | 2432 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2433 | WdfRequestGetParameters(Request, ¶ms); 2434 | 2435 | if (params.Parameters.DeviceIoControl.InputBufferLength < sizeof(HID_XFER_PACKET)) 2436 | { 2437 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2438 | "Rt5682SetFeature Xfer packet too small\n"); 2439 | 2440 | status = STATUS_BUFFER_TOO_SMALL; 2441 | } 2442 | else 2443 | { 2444 | 2445 | transferPacket = (PHID_XFER_PACKET)WdfRequestWdmGetIrp(Request)->UserBuffer; 2446 | 2447 | if (transferPacket == NULL) 2448 | { 2449 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2450 | "Rt5682WriteReport No xfer packet\n"); 2451 | 2452 | status = STATUS_INVALID_DEVICE_REQUEST; 2453 | } 2454 | else 2455 | { 2456 | // 2457 | // switch on the report id 2458 | // 2459 | 2460 | switch (transferPacket->reportId) 2461 | { 2462 | default: 2463 | 2464 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2465 | "Rt5682SetFeature Unhandled report type %d\n", transferPacket->reportId); 2466 | 2467 | status = STATUS_INVALID_PARAMETER; 2468 | 2469 | break; 2470 | } 2471 | } 2472 | } 2473 | 2474 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2475 | "Rt5682SetFeature Exit = 0x%x\n", status); 2476 | 2477 | return status; 2478 | } 2479 | 2480 | NTSTATUS 2481 | Rt5682GetFeature( 2482 | IN PRTEK_CONTEXT DevContext, 2483 | IN WDFREQUEST Request, 2484 | OUT BOOLEAN* CompleteRequest 2485 | ) 2486 | { 2487 | NTSTATUS status = STATUS_SUCCESS; 2488 | WDF_REQUEST_PARAMETERS params; 2489 | PHID_XFER_PACKET transferPacket = NULL; 2490 | 2491 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2492 | "Rt5682GetFeature Entry\n"); 2493 | 2494 | WDF_REQUEST_PARAMETERS_INIT(¶ms); 2495 | WdfRequestGetParameters(Request, ¶ms); 2496 | 2497 | if (params.Parameters.DeviceIoControl.OutputBufferLength < sizeof(HID_XFER_PACKET)) 2498 | { 2499 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2500 | "Rt5682GetFeature Xfer packet too small\n"); 2501 | 2502 | status = STATUS_BUFFER_TOO_SMALL; 2503 | } 2504 | else 2505 | { 2506 | 2507 | transferPacket = (PHID_XFER_PACKET)WdfRequestWdmGetIrp(Request)->UserBuffer; 2508 | 2509 | if (transferPacket == NULL) 2510 | { 2511 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2512 | "Rt5682GetFeature No xfer packet\n"); 2513 | 2514 | status = STATUS_INVALID_DEVICE_REQUEST; 2515 | } 2516 | else 2517 | { 2518 | // 2519 | // switch on the report id 2520 | // 2521 | 2522 | switch (transferPacket->reportId) 2523 | { 2524 | default: 2525 | 2526 | RtekPrint(DEBUG_LEVEL_ERROR, DBG_IOCTL, 2527 | "Rt5682GetFeature Unhandled report type %d\n", transferPacket->reportId); 2528 | 2529 | status = STATUS_INVALID_PARAMETER; 2530 | 2531 | break; 2532 | } 2533 | } 2534 | } 2535 | 2536 | RtekPrint(DEBUG_LEVEL_VERBOSE, DBG_IOCTL, 2537 | "Rt5682GetFeature Exit = 0x%x\n", status); 2538 | 2539 | return status; 2540 | } 2541 | 2542 | PCHAR 2543 | DbgHidInternalIoctlString( 2544 | IN ULONG IoControlCode 2545 | ) 2546 | { 2547 | switch (IoControlCode) 2548 | { 2549 | case IOCTL_HID_GET_DEVICE_DESCRIPTOR: 2550 | return "IOCTL_HID_GET_DEVICE_DESCRIPTOR"; 2551 | case IOCTL_HID_GET_REPORT_DESCRIPTOR: 2552 | return "IOCTL_HID_GET_REPORT_DESCRIPTOR"; 2553 | case IOCTL_HID_READ_REPORT: 2554 | return "IOCTL_HID_READ_REPORT"; 2555 | case IOCTL_HID_GET_DEVICE_ATTRIBUTES: 2556 | return "IOCTL_HID_GET_DEVICE_ATTRIBUTES"; 2557 | case IOCTL_HID_WRITE_REPORT: 2558 | return "IOCTL_HID_WRITE_REPORT"; 2559 | case IOCTL_HID_SET_FEATURE: 2560 | return "IOCTL_HID_SET_FEATURE"; 2561 | case IOCTL_HID_GET_FEATURE: 2562 | return "IOCTL_HID_GET_FEATURE"; 2563 | case IOCTL_HID_GET_STRING: 2564 | return "IOCTL_HID_GET_STRING"; 2565 | case IOCTL_HID_ACTIVATE_DEVICE: 2566 | return "IOCTL_HID_ACTIVATE_DEVICE"; 2567 | case IOCTL_HID_DEACTIVATE_DEVICE: 2568 | return "IOCTL_HID_DEACTIVATE_DEVICE"; 2569 | case IOCTL_HID_SEND_IDLE_NOTIFICATION_REQUEST: 2570 | return "IOCTL_HID_SEND_IDLE_NOTIFICATION_REQUEST"; 2571 | case IOCTL_HID_SET_OUTPUT_REPORT: 2572 | return "IOCTL_HID_SET_OUTPUT_REPORT"; 2573 | case IOCTL_HID_GET_INPUT_REPORT: 2574 | return "IOCTL_HID_GET_INPUT_REPORT"; 2575 | default: 2576 | return "Unknown IOCTL"; 2577 | } 2578 | } --------------------------------------------------------------------------------