├── .github └── workflows │ └── blank.yml ├── .gitignore ├── LICENSE ├── README.md ├── docs ├── arch │ ├── arch_demo.md │ ├── arch_design.md │ ├── arm_training_day1.md │ ├── arm_training_day2.md │ ├── atomic.md │ ├── cache.md │ ├── chiplet.md │ ├── computer_arch.md │ ├── hotchip33.md │ ├── hotchip33 │ │ ├── arm_neoverse_roadmap.PNG │ │ ├── graphcore_mk2.PNG │ │ ├── graphcore_mk2_bert.PNG │ │ ├── graphcore_mk2_calc.PNG │ │ ├── graphcore_mk2_tile.PNG │ │ └── hotchip33.md │ ├── numa.md │ ├── register_rename.md │ ├── rob.md │ ├── superscalar.md │ ├── think1.md │ ├── tlb.md │ ├── vector.md │ └── xs-arch-simple.html ├── books │ ├── bash.pdf │ ├── gcc.pdf │ └── shell.pdf ├── c │ ├── cast.md │ ├── complement.md │ ├── cplus.md │ ├── cpp-param-pack.md │ ├── default_cast.md │ ├── explicit.md │ ├── gcc_tools.md │ ├── int_uint.md │ ├── lvalue_and_rvalue.md │ ├── makefile.md │ ├── omp.md │ ├── reverse.md │ ├── stl_containers.md │ └── undefined_reference_to.md ├── chisel │ ├── chisel.md │ ├── rocketchip.md │ ├── sbt.md │ └── scala.md ├── debug │ └── objcopy.md ├── deeplearning │ ├── bert.md │ ├── deeplearning.md │ ├── onehot.md │ └── topk.md ├── design-patterns │ └── design-patterns.md ├── google4f96b64050b868eb.html ├── ic │ ├── axi4.md │ ├── cordic.md │ ├── esl.md │ ├── ic_develop.md │ ├── ic_flow.png │ ├── pcie.md │ ├── qemu.md │ ├── simulator.md │ ├── simulator2.md │ ├── tlm.md │ └── usb.md ├── imgs │ ├── SOC_FE310_G0000.png │ ├── amd_opteron_dcache.PNG │ ├── arm_ci700_3x3_topo.png │ ├── arm_dsu110_cluster.png │ ├── arm_mem_layout.png │ ├── boom_rename.PNG │ ├── branch_predicter_GHR_checkpoint.PNG │ ├── branch_predictor_all.PNG │ ├── branch_predictor_choice.PNG │ ├── branch_predictor_global_history.PNG │ ├── branch_predictor_local_history.PNG │ ├── btb_set.PNG │ ├── cache_2way.PNG │ ├── cache_multi_cycle.PNG │ ├── cache_virtual_phy.png │ ├── class_diagram.png │ ├── commit_flow1.png │ ├── commit_flow2.png │ ├── commit_struct.png │ ├── common_boot_flow_multi_stage.PNG │ ├── ddr │ │ ├── candence_ddr_axi_controller_core_interface.png │ │ ├── candence_ddr_controller_core.png │ │ ├── candence_ddr_mc_block_diagram.png │ │ ├── candence_ddr_select_logic.png │ │ ├── ddr_lpddr4x_lpddr5_diff.png │ │ ├── ddr_one_bank_structure.png │ │ ├── ddr_types.png │ │ ├── dram_bank_state_diagram.png │ │ ├── dram_cell_1t1c_3t1c.png │ │ ├── dram_modern_organization.png │ │ ├── dram_raw_access_cmd_timing.png │ │ ├── dram_read_access.png │ │ ├── dram_read_precharge.png │ │ ├── dram_read_restore.png │ │ ├── dram_read_sense.png │ │ ├── dram_tRCD_tRAS_tRP.png │ │ ├── dram_tWR.png │ │ └── lpddr5_bank_mode.png │ ├── developboard.png │ ├── elf_header.png │ ├── gem5_minor.jpg │ ├── gem5_o3cpu │ │ ├── execute_pip.png │ │ ├── fetch_macroOp.png │ │ ├── iew_arbiter.png │ │ ├── iew_demo.png │ │ ├── struct_commit.png │ │ ├── struct_decode.png │ │ ├── struct_fetch.png │ │ ├── struct_iew.png │ │ └── struct_rename.png │ ├── gtkwave-demo.png │ ├── ko_load_flow.png │ ├── multi-bank-cache.PNG │ ├── one-hot.png │ ├── pcie │ │ ├── pcie_addr_space_type_transaction_type.png │ │ ├── pcie_example_topology.png │ │ ├── pcie_general_tlp_format.png │ │ ├── pcie_high_level_layerinig_diagram.png │ │ ├── pcie_packet_flow_layers.png │ │ ├── pcie_request_header_format.png │ │ ├── pcie_switch_logical_block_diagram.png │ │ ├── pcie_tc_vc_config_example.png │ │ ├── pcie_tlp_address_routing.png │ │ ├── pcie_tlp_header_common_fmt.png │ │ ├── pcie_tlp_header_completion_fmt.png │ │ ├── pcie_tlp_header_fmt.png │ │ ├── pcie_tlp_header_fmt_type.png │ │ ├── pcie_tlp_header_len.png │ │ ├── pcie_tlp_header_message_req.png │ │ ├── pcie_tlp_id_routing_3dw.png │ │ ├── pcie_tlp_id_routing_4dw.png │ │ ├── pcie_tlp_ordering_rules.png │ │ └── pcie_transaction_descriptor.png │ ├── protobuf_protoc.png │ ├── protobuf_protoc.png:Zone.Identifier │ ├── protobuf_python_inout.png │ ├── protobuf_python_inout.png:Zone.Identifier │ ├── ras_push_pop.PNG │ ├── rename_4way_rat.PNG │ ├── riscv_common_boot_flow_multi_stage.PNG │ ├── riscv_opensbi_system.PNG │ ├── rob_inout.png │ ├── rob_pos.png │ ├── rob_struct.png │ ├── rvv_vector_engine.png │ ├── simple_system.svg │ ├── spike_diagram.png │ ├── spike_mainflow.png │ ├── spinlock_files.png │ ├── sv39 │ │ ├── Sv39_pa.png │ │ ├── Sv39_pte.png │ │ ├── Sv39_satp.png │ │ └── Sv39_va.png │ ├── syscall.png │ ├── tmp75_data.png │ └── tmp75_register.png ├── index.md ├── linux │ ├── arm-linux-kmodule-load.md │ ├── kernel-status.md │ ├── lzma_transplant.md │ ├── sync-and-exclusion.md │ └── syscall.md ├── mcu │ ├── ads7843.md │ ├── emwin_debug.md │ ├── fatfs_f_readdir.md │ └── lpc1114_hex2bin.md ├── misc │ ├── howtolearn.md │ ├── latex.md │ ├── pcie.md │ ├── photograph.md │ ├── pytest.md │ ├── randomx.md │ ├── roadmap.md │ ├── shell.md │ ├── skiing.md │ ├── vlog.md │ ├── words.md │ ├── work-201904-202102.md │ └── xmr.md ├── python │ ├── env_requirement.md │ ├── numpy_softfloat.md │ └── python.md ├── riscv │ ├── RISC-V.md │ ├── la.md │ ├── opensbi.md │ ├── pma.md │ ├── riscv-rvv.md │ ├── riscv-torture.md │ ├── virtual_mem_manage.md │ └── wfi.md ├── robots.txt ├── simulator │ ├── dramsim_ddr.md │ ├── gem5-se.md │ ├── gem5.md │ ├── gem5_introduction.md │ ├── gem5_isa.md │ ├── gem5_o3cpu.md │ ├── gem5_part1.htm │ ├── gem5_part2.htm │ ├── gem5_part3.htm │ ├── gem5_random.md │ ├── gem5浅析.pdf │ ├── simplescalar.PNG │ ├── simplescalar_cpus.PNG │ ├── simplescalar_outorder.PNG │ ├── simplesim.md │ ├── spike.md │ └── trace_format.md ├── sitemap.txt ├── smt-pnp │ └── smt-pnp-introduction.md ├── tools │ ├── arm-atp.md │ ├── cache-size.md │ ├── chrome-tracing.md │ ├── cii-and-crontable.md │ ├── engine.md │ ├── git-hooks.md │ ├── git.md │ ├── llvm-riscv-compile.md │ ├── llvm-symbolizer.md │ ├── markdown.md │ ├── ntfs-mount.md │ ├── perf.md │ ├── protobuf.md │ ├── screen.md │ ├── stream.md │ ├── vscode-remotessh.md │ └── wsl.md ├── tvm │ ├── codebase-struct.md │ ├── node.md │ ├── runtime.md │ └── tvm-start.md └── verilog │ ├── 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