├── doc ├── .gitignore ├── figure │ └── uart_waveform.json5 └── Makefile ├── eda ├── blink │ ├── .gitignore │ ├── Makefile │ ├── src │ │ ├── tangnano1k │ │ │ ├── pins.cst │ │ │ └── top.sv │ │ ├── tangnano9k │ │ │ ├── pins.cst │ │ │ └── top.sv │ │ └── runber │ │ │ ├── top.sv │ │ │ └── pins.cst │ └── project.tcl ├── stp_emu │ ├── .gitignore │ ├── src │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ └── project.tcl ├── ws2812 │ ├── .gitignore │ ├── src │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ └── project.tcl ├── cpu_stopwatch │ ├── .gitignore │ ├── src │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── link.ld │ │ │ └── bootrom.hex │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ └── project.tcl ├── i2c_slave │ ├── .gitignore │ ├── src │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ └── project.tcl ├── lifegame_fram │ ├── .gitignore │ ├── Makefile │ ├── src │ │ └── tangnano9k │ │ │ ├── timing.sdc │ │ │ └── top.sv │ └── project.tcl ├── matrix_led │ ├── .gitignore │ ├── Makefile │ ├── project.tcl │ └── src │ │ └── tangnano9k │ │ └── pins.cst ├── segment_led │ ├── .gitignore │ ├── src │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ └── project.tcl ├── stop_watch │ ├── .gitignore │ ├── src │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ └── project.tcl ├── switch_input │ ├── .gitignore │ ├── src │ │ └── runber │ │ │ └── timing.sdc │ ├── Makefile │ ├── switch_input.gprj │ └── project.tcl ├── multi_segment_led │ ├── .gitignore │ ├── src │ │ └── tangnano20k │ │ │ ├── .gitignore │ │ │ ├── timing.sdc │ │ │ ├── pins.cst.template │ │ │ ├── reset_seq.sv │ │ │ ├── pins.cst │ │ │ └── top.sv │ ├── project.tcl │ └── Makefile ├── dvi_out_tpg │ ├── .gitignore │ ├── src │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ └── link.ld │ │ ├── tangnano9k │ │ │ ├── .gitignore │ │ │ ├── ip │ │ │ │ ├── .gitignore │ │ │ │ ├── gowin_clkdiv │ │ │ │ │ └── gowin_clkdiv.ipc │ │ │ │ ├── dvi_tx │ │ │ │ │ └── dvi_tx.ipc │ │ │ │ ├── gowin_rpll │ │ │ │ │ └── gowin_rpll.ipc │ │ │ │ └── gowin_rpll_ser │ │ │ │ │ └── gowin_rpll_ser.ipc │ │ │ ├── Makefile │ │ │ ├── iobuf_sim.sv │ │ │ ├── reset_seq.sv │ │ │ ├── timing.sdc │ │ │ └── tb.sv │ │ ├── tangprimer20k │ │ │ ├── .gitignore │ │ │ ├── ip │ │ │ │ ├── .gitignore │ │ │ │ ├── gowin_rpll_dvi │ │ │ │ │ └── gowin_rpll_dvi.ipc │ │ │ │ └── gowin_rpll_ser │ │ │ │ │ └── gowin_rpll_ser.ipc │ │ │ ├── reset_seq.sv │ │ │ └── timing.sdc │ │ ├── tangprimer25k │ │ │ ├── .gitignore │ │ │ ├── timing.sdc │ │ │ ├── reset_seq.sv │ │ │ ├── pins.cst.template │ │ │ └── pins.cst │ │ ├── interface_logo.bin │ │ └── conv_logo.py │ ├── README.md │ └── Makefile ├── i2s_master │ ├── .gitignore │ ├── src │ │ ├── tangnano9k │ │ │ ├── ip │ │ │ │ ├── .gitignore │ │ │ │ └── gowin_rpll │ │ │ │ │ └── gowin_rpll.ipc │ │ │ ├── reset_seq.sv │ │ │ └── timing.sdc │ │ └── tangprimer20k │ │ │ ├── .gitignore │ │ │ ├── timing.sdc │ │ │ ├── ip │ │ │ └── rpll_main │ │ │ │ └── rpll_main.ipc │ │ │ ├── reset_seq.sv │ │ │ └── top.sv │ ├── project.tcl │ └── Makefile ├── cpu_riscv_chisel_book_blink │ ├── .gitignore │ ├── src │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── bootrom.hex │ │ │ └── link.ld │ │ ├── runber │ │ │ └── timing.sdc │ │ ├── tangnano9k │ │ │ ├── timing.sdc │ │ │ └── pins.cst │ │ └── comprocboard_9k │ │ │ ├── timing.sdc │ │ │ └── pins.cst │ ├── Makefile │ └── project.tcl ├── ethernet_icmp │ ├── .gitignore │ ├── README.md │ └── src │ │ ├── tangnano9k │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── iobuf_sim.sv │ │ ├── reset_seq.sv │ │ ├── timing.sdc │ │ └── tb.sv │ │ ├── tangprimer20k │ │ ├── .gitignore │ │ ├── reset_seq.sv │ │ ├── timing.sdc │ │ └── pins.cst │ │ ├── tangnano9k_pmod │ │ ├── ip │ │ │ ├── .gitignore │ │ │ └── gowin_rpll │ │ │ │ └── gowin_rpll.ipc │ │ ├── reset_seq.sv │ │ └── timing.sdc │ │ ├── tangnano9k_matrix_led │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── iobuf_sim.sv │ │ ├── reset_seq.sv │ │ ├── timing.sdc │ │ └── tb.sv │ │ └── tangprimer20k_hub75 │ │ ├── .gitignore │ │ ├── reset_seq.sv │ │ └── timing.sdc ├── turn_table │ ├── .gitignore │ ├── src │ │ └── tangnano9k_pmod │ │ │ ├── timing.sdc │ │ │ ├── reset_seq.sv │ │ │ └── pins.cst.template │ ├── project.tcl │ └── Makefile ├── ethernet_audio │ ├── .gitignore │ ├── README.md │ └── src │ │ └── tangprimer20k │ │ ├── .gitignore │ │ ├── ip │ │ └── rpll_main │ │ │ └── rpll_main.ipc │ │ ├── reset_seq.sv │ │ └── timing.sdc ├── ethernet_video │ ├── .gitignore │ ├── README.md │ ├── src │ │ └── tangprimer20k │ │ │ ├── .gitignore │ │ │ ├── ip │ │ │ └── rpll_main │ │ │ │ └── rpll_main.ipc │ │ │ ├── reset_seq.sv │ │ │ └── timing.sdc │ └── probedec.sh ├── cpu_riscv_chisel_book_matrix │ ├── .gitignore │ ├── src │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ └── link.ld │ │ └── comprocboard_9k │ │ │ ├── timing.sdc │ │ │ └── test │ │ │ ├── iobuf_sim.sv │ │ │ ├── Makefile │ │ │ └── tb.sv │ ├── Makefile │ └── project.tcl ├── cpu_matrix_led │ ├── src │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── bootrom.hex │ │ │ └── link.ld │ │ ├── tangprimer20k │ │ │ ├── .gitignore │ │ │ ├── timing.sdc │ │ │ ├── reset_seq.sv │ │ │ ├── pins.cst.template │ │ │ └── pins.cst │ │ ├── tangnano9k │ │ │ ├── timing.sdc │ │ │ └── pins.cst │ │ ├── comprocboard_9k │ │ │ ├── timing.sdc │ │ │ └── pins.cst │ │ └── tangnano9k_pmod │ │ │ ├── timing.sdc │ │ │ ├── pins.cst.template │ │ │ └── pins.cst │ ├── project.tcl │ └── Makefile ├── .gitignore ├── targets │ ├── runber │ │ └── target.mk │ ├── tangnano1k │ │ └── target.mk │ ├── tangnano20k │ │ ├── target.mk │ │ └── pmod_ports.csv │ ├── tangnano9k │ │ └── target.mk │ ├── comprocboard_9k │ │ └── target.mk │ ├── tangnano9k_pmod │ │ ├── target.mk │ │ └── pmod_ports.csv │ ├── tangprimer20k │ │ ├── target.mk │ │ └── pmod_ports.csv │ ├── tangnano9k_matrix_led │ │ └── target.mk │ └── tangprimer20k_hub75 │ │ ├── target.mk │ │ └── pmod_ports.csv └── uart │ ├── src │ ├── runber.cst │ └── tangnano.cst │ └── uart.gprj ├── xls ├── mixer │ ├── .gitignore │ └── Makefile ├── filter │ ├── .gitignore │ ├── moving_average.cc │ ├── Makefile │ └── moving_average.dslx └── .gitignore ├── rtl ├── .gitignore ├── dds │ ├── .gitignore │ ├── test │ │ ├── .gitignore │ │ └── Makefile │ └── Veryl.toml ├── ethernet │ ├── crc │ │ └── test │ │ │ ├── test.tcl │ │ │ └── Makefile │ ├── mii_mac │ │ ├── .gitignore │ │ ├── test_append_crc │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── test_crc_mac │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── test_loopback │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── Makefile │ │ └── crc_mac.sv │ ├── rmii_mac │ │ ├── .gitignore │ │ └── Makefile │ ├── util │ │ ├── test_simple_fifo │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── axis_dispose.v │ │ └── simple_fifo.v │ ├── mii_axis │ │ ├── axis_to_mii │ │ │ ├── .gitignore │ │ │ └── Makefile │ │ ├── mii_to_axis │ │ │ ├── .gitignore │ │ │ └── Makefile │ │ ├── test_axis_to_axis │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── test_axis_to_mii │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── test_axis_to_rmii │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── test_mii_to_axis │ │ │ ├── test.tcl │ │ │ └── Makefile │ │ ├── prepend_preamble │ │ │ ├── .gitignore │ │ │ └── Makefile │ │ └── test_axis_to_axis_rmii │ │ │ ├── test.tcl │ │ │ └── Makefile │ ├── .gitignore │ ├── README.md │ └── LICENSE ├── uart │ ├── Makefile │ ├── uart_system.sv │ └── uart_tx.sv ├── dvi_out │ └── test │ │ └── Makefile ├── i2c_slave │ ├── test │ │ └── Makefile │ └── iobuf_sim.sv ├── chisel │ ├── uart │ │ └── uartsystem.anno.json │ └── lifegame_fram │ │ └── lifegame_fram.anno.json ├── blink │ └── blink_all.sv ├── util │ ├── simple_fifo.sv │ └── timer_counter.sv └── segment_led │ └── segment_led.sv ├── util ├── mappmod │ ├── .gitignore │ └── Cargo.toml ├── udpsend │ ├── .gitignore │ ├── assets │ │ ├── fpga.bmp │ │ ├── fuga.bmp │ │ ├── hoge.bmp │ │ ├── fpga_udp.bmp │ │ ├── fuga_64x64.bmp │ │ ├── white_64x64.bmp │ │ ├── pattern_64x64.bmp │ │ └── rustacean-orig-noshadow_64x64.bmp │ └── Cargo.toml ├── udpaudiocontrol │ ├── .gitignore │ ├── Cargo.toml │ └── src │ │ └── main.rs ├── udpaudiosend │ ├── .gitignore │ └── Cargo.toml ├── udpvideosend │ ├── .gitignore │ ├── README.md │ └── Cargo.toml └── probedec │ ├── .gitignore │ └── Cargo.toml ├── .gitignore ├── chisel ├── src │ ├── test │ │ └── scala │ │ │ ├── ethernet │ │ │ └── data │ │ │ │ ├── arp.input.bin │ │ │ │ ├── udp.input.bin │ │ │ │ ├── icmp.input.bin │ │ │ │ ├── udp.output.bin │ │ │ │ ├── arp.expected.bin │ │ │ │ ├── icmp.expected.bin │ │ │ │ ├── udp_ping.input.bin │ │ │ │ ├── icmp_dump.input.bin │ │ │ │ ├── icmp_dump.expected.bin │ │ │ │ └── udp_ping.expected.bin │ │ │ ├── video-tests │ │ │ └── dvi_out.scala │ │ │ └── util-tests │ │ │ └── regslice.scala │ └── main │ │ └── scala │ │ ├── spi │ │ └── spi_io.scala.scala │ │ ├── sound │ │ └── timing.json5 │ │ ├── axi │ │ ├── axi4_channel_combine.scala │ │ ├── axi4_randomizer.scala │ │ └── axi4_gate.scala │ │ ├── system │ │ ├── sdramtestsystem.scala │ │ └── sample_uart.scala │ │ ├── util │ │ ├── flushable.scala │ │ ├── irrevocable_randomizer.scala │ │ ├── irrevocable_checker.scala │ │ ├── graycode.scala │ │ ├── multibytesymbol.scala │ │ ├── irrevocable_gate.scala │ │ └── regslice.scala │ │ ├── gowin │ │ └── oser10.scala │ │ └── display │ │ └── matrix_led.scala └── sbt │ └── build.sbt ├── mod ├── sipeed │ └── pmod_dvi │ │ └── pmod_pins.csv ├── pmod_7segx6_single │ └── pmod_pins.csv ├── pmod_ethernet_w_adapter │ └── pmod_pins.csv ├── pmod_ethernet │ └── pmod_pins.csv ├── pmod_stepper2 │ └── pmod_pins.csv ├── pmod_hub75 │ └── pmod_pins.csv └── pmod_matrix_led │ └── pmod_pins.csv ├── LICENSE.header ├── set_license_identifier.sh ├── README.md ├── .gitmodules └── LICENSE /doc/.gitignore: -------------------------------------------------------------------------------- 1 | node_modules -------------------------------------------------------------------------------- /eda/blink/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/stp_emu/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/ws2812/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /xls/mixer/.gitignore: -------------------------------------------------------------------------------- 1 | !mixer.v -------------------------------------------------------------------------------- /eda/cpu_stopwatch/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/i2c_slave/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/lifegame_fram/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/matrix_led/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/segment_led/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/stop_watch/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/switch_input/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /rtl/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.vcd -------------------------------------------------------------------------------- /eda/multi_segment_led/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /xls/filter/.gitignore: -------------------------------------------------------------------------------- 1 | !moving_average.v -------------------------------------------------------------------------------- /eda/dvi_out_tpg/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | arty-a7 -------------------------------------------------------------------------------- /eda/i2s_master/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | arty-a7 -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/.gitignore: -------------------------------------------------------------------------------- 1 | build -------------------------------------------------------------------------------- /eda/ethernet_icmp/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | arty-a7 -------------------------------------------------------------------------------- /eda/turn_table/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | chisel_output -------------------------------------------------------------------------------- /util/mappmod/.gitignore: -------------------------------------------------------------------------------- 1 | Cargo.lock 2 | target -------------------------------------------------------------------------------- /util/udpsend/.gitignore: -------------------------------------------------------------------------------- 1 | Cargo.lock 2 | target -------------------------------------------------------------------------------- /xls/.gitignore: -------------------------------------------------------------------------------- 1 | *.ir 2 | *.v 3 | *.vcd 4 | *.tmp -------------------------------------------------------------------------------- /eda/ethernet_audio/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | chisel_output -------------------------------------------------------------------------------- /eda/ethernet_video/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | chisel_output -------------------------------------------------------------------------------- /util/udpaudiocontrol/.gitignore: -------------------------------------------------------------------------------- 1 | Cargo.lock 2 | target -------------------------------------------------------------------------------- /util/udpaudiosend/.gitignore: -------------------------------------------------------------------------------- 1 | Cargo.lock 2 | target -------------------------------------------------------------------------------- /util/udpvideosend/.gitignore: -------------------------------------------------------------------------------- 1 | Cargo.lock 2 | target -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | arty-a7 -------------------------------------------------------------------------------- /rtl/dds/.gitignore: -------------------------------------------------------------------------------- 1 | *.f 2 | dependencies 3 | src/*.sv 4 | Veryl.lock -------------------------------------------------------------------------------- /rtl/ethernet/crc/test/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /util/probedec/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.csv 3 | Cargo.lock 4 | target -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/sw/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.dump 3 | *.bin 4 | *.elf -------------------------------------------------------------------------------- /eda/cpu_stopwatch/src/sw/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.dump 3 | *.bin 4 | *.elf -------------------------------------------------------------------------------- /eda/ethernet_audio/README.md: -------------------------------------------------------------------------------- 1 | # Ethernet UDP Audioデザイン 2 | 3 | ## 概要 4 | -------------------------------------------------------------------------------- /eda/ethernet_video/README.md: -------------------------------------------------------------------------------- 1 | # Ethernet UDP Audioデザイン 2 | 3 | ## 概要 4 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | xgui 4 | component.xml -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/sw/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.dump 3 | *.bin 4 | *.elf 5 | *.hex -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /eda/ethernet_icmp/README.md: -------------------------------------------------------------------------------- 1 | # Ethernet ICMP + UDP応答デザイン 2 | 3 | ## 概要 4 | -------------------------------------------------------------------------------- /rtl/ethernet/rmii_mac/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | xgui 4 | component.xml -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangprimer20k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/sw/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.dump 3 | *.bin 4 | *.elf -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/ip/.gitignore: -------------------------------------------------------------------------------- 1 | *.v 2 | *.vo 3 | *.mod 4 | temp 5 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer20k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer20k/ip/.gitignore: -------------------------------------------------------------------------------- 1 | *.v 2 | *.vo 3 | *.mod 4 | temp 5 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /eda/i2s_master/src/tangnano9k/ip/.gitignore: -------------------------------------------------------------------------------- 1 | *.v 2 | *.vo 3 | *.mod 4 | temp 5 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/test_append_crc/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/test_crc_mac/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/test_loopback/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /rtl/ethernet/util/test_simple_fifo/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/sw/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.dump 3 | *.bin 4 | *.elf -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_pmod/ip/.gitignore: -------------------------------------------------------------------------------- 1 | *.v 2 | *.vo 3 | *.mod 4 | temp 5 | -------------------------------------------------------------------------------- /eda/multi_segment_led/src/tangnano20k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/axis_to_mii/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | xgui 4 | component.xml -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/mii_to_axis/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | xgui 4 | component.xml -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_axis/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_mii/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_rmii/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_mii_to_axis/test.tcl: -------------------------------------------------------------------------------- 1 | add_wave -recursive * 2 | run all 3 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer25k/.gitignore: -------------------------------------------------------------------------------- 1 | ip/rpll_main/* 2 | !ip/rpll_main/rpll_main.ipc -------------------------------------------------------------------------------- /eda/ethernet_audio/src/tangprimer20k/.gitignore: -------------------------------------------------------------------------------- 1 | ip/rpll_main/* 2 | !ip/rpll_main/rpll_main.ipc -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_matrix_led/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v -------------------------------------------------------------------------------- /eda/ethernet_video/src/tangprimer20k/.gitignore: -------------------------------------------------------------------------------- 1 | ip/rpll_main/* 2 | !ip/rpll_main/rpll_main.ipc -------------------------------------------------------------------------------- /eda/i2s_master/src/tangprimer20k/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v 4 | pins.cst -------------------------------------------------------------------------------- /rtl/ethernet/.gitignore: -------------------------------------------------------------------------------- 1 | *.jou 2 | *.log 3 | *.str 4 | *.wdb 5 | .Xil 6 | *.pb 7 | *.dir 8 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/prepend_preamble/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | xgui 4 | component.xml -------------------------------------------------------------------------------- /xls/filter/moving_average.cc: -------------------------------------------------------------------------------- 1 | #pragma hls_top 2 | int add3(int input) { return input + 3; } -------------------------------------------------------------------------------- /eda/.gitignore: -------------------------------------------------------------------------------- 1 | */build/* 2 | !*/build/*/impl/project_process_config.json 3 | */*.gprj.user 4 | temp 5 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k_hub75/.gitignore: -------------------------------------------------------------------------------- 1 | output.vcd 2 | testbench 3 | riscv.v 4 | pins.cst -------------------------------------------------------------------------------- /eda/stp_emu/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/ws2812/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /rtl/dds/test/.gitignore: -------------------------------------------------------------------------------- 1 | test.wdb 2 | *.log 3 | *.jou 4 | *.str 5 | *.pb 6 | *.jou 7 | .Xil 8 | xsim.dir 9 | run-* -------------------------------------------------------------------------------- /util/udpsend/assets/fpga.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/fpga.bmp -------------------------------------------------------------------------------- /util/udpsend/assets/fuga.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/fuga.bmp -------------------------------------------------------------------------------- /util/udpsend/assets/hoge.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/hoge.bmp -------------------------------------------------------------------------------- /eda/i2c_slave/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/segment_led/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/stop_watch/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/switch_input/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangnano9k/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 37.037 -waveform {0 18.519} [get_ports {clk}] -------------------------------------------------------------------------------- /eda/cpu_stopwatch/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /util/udpsend/assets/fpga_udp.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/fpga_udp.bmp -------------------------------------------------------------------------------- /util/udpsend/assets/fuga_64x64.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/fuga_64x64.bmp -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/comprocboard_9k/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 37.037 -waveform {0 18.519} [get_ports {clk}] -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangnano9k_pmod/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 37.037 -waveform {0 18.519} [get_ports {clk}] -------------------------------------------------------------------------------- /util/udpsend/assets/white_64x64.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/white_64x64.bmp -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/runber/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock -period 83.333 -waveform {0 41.667} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/interface_logo.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/eda/dvi_out_tpg/src/interface_logo.bin -------------------------------------------------------------------------------- /util/udpsend/assets/pattern_64x64.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/pattern_64x64.bmp -------------------------------------------------------------------------------- /eda/targets/runber/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW1N-4B 2 | DEVICE_PART := GW1N-LV4LQ144C6/I5 3 | OPENFPGA_LOADER_TARGET := --board runber -------------------------------------------------------------------------------- /rtl/dds/Veryl.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "dds" 3 | version = "0.1.0" 4 | 5 | [build] 6 | clock_type = "posedge" 7 | reset_type = "sync_low" -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .bloop 2 | .idea 3 | .metals 4 | target 5 | project 6 | test_run_dir 7 | 8 | .Xil 9 | .bsp 10 | .jvmopts 11 | .vscode 12 | -------------------------------------------------------------------------------- /eda/targets/tangnano1k/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW1NZ-1 2 | DEVICE_PART := GW1NZ-LV1QN48C6/I5 3 | OPENFPGA_LOADER_TARGET := --board tangnano1k -------------------------------------------------------------------------------- /eda/targets/tangnano20k/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW2AR-18C 2 | DEVICE_PART := GW2AR-LV18QN88C8/I7 3 | OPENFPGA_LOADER_TARGET := --board tangnano20k -------------------------------------------------------------------------------- /eda/targets/tangnano9k/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW1NR-9C 2 | DEVICE_PART := GW1NR-LV9QN88PC6/I5 3 | OPENFPGA_LOADER_TARGET := --board tangnano9k -------------------------------------------------------------------------------- /eda/ws2812/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := ws2812 2 | SRCS := $(wildcard src/*.cst) $(wildcard src/*.sdc) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/arp.input.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/arp.input.bin -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/udp.input.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/udp.input.bin -------------------------------------------------------------------------------- /eda/targets/comprocboard_9k/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW1NR-9C 2 | DEVICE_PART := GW1NR-LV9QN88PC6/I5 3 | OPENFPGA_LOADER_TARGET := --board tangnano9k -------------------------------------------------------------------------------- /eda/targets/tangnano9k_pmod/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW1NR-9C 2 | DEVICE_PART := GW1NR-LV9QN88PC6/I5 3 | OPENFPGA_LOADER_TARGET := --board tangnano9k -------------------------------------------------------------------------------- /eda/targets/tangprimer20k/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW2A-18C 2 | DEVICE_PART := GW2A-LV18PG256C8/I7 3 | OPENFPGA_LOADER_TARGET := --board tangprimer20k -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/icmp.input.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/icmp.input.bin -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/udp.output.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/udp.output.bin -------------------------------------------------------------------------------- /eda/targets/tangnano9k_matrix_led/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW1NR-9C 2 | DEVICE_PART := GW1NR-LV9QN88PC6/I5 3 | OPENFPGA_LOADER_TARGET := --board tangnano9k -------------------------------------------------------------------------------- /eda/targets/tangprimer20k_hub75/target.mk: -------------------------------------------------------------------------------- 1 | DEVICE_FAMILY := GW2A-18C 2 | DEVICE_PART := GW2A-LV18PG256C8/I7 3 | OPENFPGA_LOADER_TARGET := --board tangprimer20k -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/arp.expected.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/arp.expected.bin -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/icmp.expected.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/icmp.expected.bin -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/udp_ping.input.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/udp_ping.input.bin -------------------------------------------------------------------------------- /mod/sipeed/pmod_dvi/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | tmds_data_p[2],pmod0_1 3 | tmds_data_p[1],pmod0_2 4 | tmds_data_p[0],pmod0_3 5 | tmds_clk_p,pmod0_4 6 | -------------------------------------------------------------------------------- /util/udpsend/assets/rustacean-orig-noshadow_64x64.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/util/udpsend/assets/rustacean-orig-noshadow_64x64.bmp -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/icmp_dump.input.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/icmp_dump.input.bin -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/icmp_dump.expected.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/icmp_dump.expected.bin -------------------------------------------------------------------------------- /chisel/src/test/scala/ethernet/data/udp_ping.expected.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ciniml/fpga_samples/HEAD/chisel/src/test/scala/ethernet/data/udp_ping.expected.bin -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_axis_rmii/test.tcl: -------------------------------------------------------------------------------- 1 | open_vcd 2 | log_vcd [get_object /tb/dut_rmii_to_axis/*] 3 | 4 | add_wave -recursive * 5 | run all 6 | 7 | close_vcd -------------------------------------------------------------------------------- /eda/targets/tangnano20k/pmod_ports.csv: -------------------------------------------------------------------------------- 1 | pmod_pin,fpga_pin 2 | pmod0_1,71 3 | pmod0_2,85 4 | pmod0_3,75 5 | pmod0_4,74 6 | pmod0_7,72 7 | pmod0_8,80 8 | pmod0_9,76 9 | pmod0_10,73 -------------------------------------------------------------------------------- /eda/segment_led/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := segment_led 2 | SRCS := $(wildcard ../../rtl/blink/*.cst) $(wildcard src/*.cst) $(wildcard src/*.sv) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /eda/switch_input/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := switch_input 2 | SRCS := $(wildcard ../../rtl/blink/*.cst) $(wildcard src/*.cst) $(wildcard src/*.sdc) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /eda/matrix_led/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := matrix_led 2 | SRCS := $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /mod/pmod_7segx6_single/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | com_ser,pmod0_1 3 | com_rclk,pmod0_2 4 | com_srclk,pmod0_7 5 | com_oe,pmod0_8 6 | seg_ser,pmod0_3 7 | seg_rclk,pmod0_4 8 | seg_srclk,pmod0_9 9 | seg_oe,pmod0_10 -------------------------------------------------------------------------------- /eda/blink/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := blink 2 | SRCS := $(wildcard ../../rtl/blink/*.cst) $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl 3 | 4 | include ../build_gowin.mk 5 | -------------------------------------------------------------------------------- /mod/pmod_ethernet_w_adapter/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | rmii_txclk,pmod0_1 3 | rmii_rxd[0],pmod0_2 4 | rmii_rxd[1],pmod0_8 5 | rmii_crs_dv,pmod0_7 6 | rmii_txd[0],pmod0_9 7 | rmii_txd[1],pmod0_4 8 | rmii_txen,pmod0_3 9 | -------------------------------------------------------------------------------- /eda/i2c_slave/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := i2c_slave 2 | SRCS := $(wildcard ../../rtl/i2c_slave/*.sv) $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /mod/pmod_ethernet/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | rmii_txclk,pmod0_9 3 | rmii_rxd[0],pmod0_8 4 | rmii_rxd[1],pmod0_2 5 | rmii_crs_dv,pmod0_3 6 | rmii_txd[0],pmod0_1 7 | rmii_txen,pmod0_7 8 | rmii_mdio,pmod0_10 9 | rmii_mdc,pmod0_4 -------------------------------------------------------------------------------- /doc/figure/uart_waveform.json5: -------------------------------------------------------------------------------- 1 | { 2 | "config": { 3 | "skin": "default" 4 | }, 5 | "signal": [ 6 | 7 | { "name": "uart_rx", "wave": "1.2.2.2.2.2.2.2.2.2.2.1.", data: ["START",0,1,2,3,4,5,6,7,"STOP"]} 8 | ] 9 | } -------------------------------------------------------------------------------- /eda/stp_emu/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := stp_emu 2 | SRCS := $(wildcard src/*.cst) $(wildcard src/*.sdc) $(wildcard src/*.sv) $(wildcard ../../rtl/segment_led/*.sv) $(wildcard ../../rtl/stp_emu/*.sv) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /eda/stop_watch/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := stop_watch 2 | SRCS := $(wildcard src/*.cst) $(wildcard src/*.sdc) $(wildcard src/*.sv) $(wildcard ../../rtl/segment_led/*.sv) $(wildcard ../../rtl/switch_input/*.sv) project.tcl 3 | 4 | include ../build_gowin.mk -------------------------------------------------------------------------------- /eda/lifegame_fram/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := lifegame_fram 2 | SRCS := $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) ../../rtl//chisel/lifegame_fram/lifegame_fram.v project.tcl 3 | include ../build_gowin.mk 4 | -------------------------------------------------------------------------------- /LICENSE.header: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2022. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) -------------------------------------------------------------------------------- /util/udpsend/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "udpsend" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | bmp = "0.5.0" 10 | -------------------------------------------------------------------------------- /mod/pmod_stepper2/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | stepper_m1p[0],pmod0_1 3 | stepper_m1p[1],pmod0_7 4 | stepper_m1p[2],pmod0_2 5 | stepper_m1p[3],pmod0_8 6 | stepper_m2p[0],pmod0_3 7 | stepper_m2p[1],pmod0_9 8 | stepper_m2p[2],pmod0_4 9 | stepper_m2p[3],pmod0_10 -------------------------------------------------------------------------------- /eda/uart/src/runber.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 4; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | IO_LOC "resetn" 58; 4 | IO_PORT "resetn" IO_TYPE=LVCMOS33; 5 | 6 | IO_LOC "rx" 135; 7 | IO_PORT "rx" IO_TYPE=LVCMOS33; 8 | IO_LOC "tx" 134; 9 | IO_PORT "tx" IO_TYPE=LVCMOS33; 10 | -------------------------------------------------------------------------------- /eda/uart/src/tangnano.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 35; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | IO_LOC "resetn" 15; 4 | IO_PORT "resetn" IO_TYPE=LVCMOS33; 5 | 6 | IO_LOC "rx" 5; 7 | IO_PORT "rx" IO_TYPE=LVCMOS33; 8 | IO_LOC "tx" 13; 9 | IO_PORT "tx" IO_TYPE=LVCMOS33; 10 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | WAVEDROM_SVGS := $(patsubst %.json5,%.svg,$(wildcard figure/*.json5)) 4 | 5 | all: $(WAVEDROM_SVGS) 6 | 7 | figure/%.svg: figure/%.json5 8 | $(shell npm bin)/wavedrom-cli -i $< -s $@ 9 | 10 | 11 | clean: 12 | -@$(RM) *.svg -------------------------------------------------------------------------------- /eda/blink/src/tangnano1k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 47; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "led_r" 9; 5 | IO_PORT "led_r" IO_TYPE=LVCMOS33; 6 | IO_LOC "led_b" 10; 7 | IO_PORT "led_b" IO_TYPE=LVCMOS33; 8 | IO_LOC "led_g" 11; 9 | IO_PORT "led_g" IO_TYPE=LVCMOS33; 10 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/ip/gowin_clkdiv/gowin_clkdiv.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_clkdiv 4 | module=Gowin_CLKDIV 5 | target_device=gw1nr9c-004 6 | type=clock_clkdiv 7 | version=1.0 8 | 9 | [Config] 10 | Calibration=false 11 | Division_Factor=5 12 | Language=0 13 | -------------------------------------------------------------------------------- /set_license_identifier.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPT_DIR=$(cd $(dirname $0); pwd) 4 | for f in `find ./src -name "*.scala"`; do 5 | if ! head -n 1 $f | grep "SPDX-License-Identifier" > /dev/null; then 6 | echo -e "$(cat ${SCRIPT_DIR}/LICENSE.header)\n\n$(cat $f)" > $f 7 | fi 8 | done -------------------------------------------------------------------------------- /util/udpvideosend/README.md: -------------------------------------------------------------------------------- 1 | 2 | ```shell 3 | cat video_fifo | cargo run& 4 | cat audio_fifo | ../udpaudiosend/target/debug/udpaudiosend & 5 | ffmpeg -y -stream_loop -1 -i ${VIDEO_FILE} -f rawvideo -pix_fmt rgb24 -vf "eq=gamma=0.5,scale=64:64" -r 30 -an video_fifo -f s16le -ar 48000 -acodec pcm_s16le audio_fifo 6 | ``` -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA Samples 2 | 3 | GOWIN LittleBeeなどの小規模FPGA向けのサンプルやライブラリ 4 | 5 | ## 内容 6 | 7 | ### rtl 8 | 9 | SystemVerilogで記述したモジュール 10 | 11 | ### src/main/scala 12 | 13 | Chisel3で記述したモジュール 14 | 15 | ### src/test/scala 16 | 17 | Chisel3で記述したモジュールのテスト 18 | 19 | ## ライセンス 20 | 21 | Boost Software License 1.0 -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/axis_to_mii/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean ip 2 | 3 | MODULES := ../axis_to_mii.sv 4 | 5 | all: ip 6 | 7 | clean: 8 | -@$(RM) component.xml 9 | -@$(RM) -rf xgui 10 | 11 | ip: component.xml 12 | 13 | component.xml xgui: $(MODULES) package_ip.tcl 14 | vivado -mode batch -source package_ip.tcl 15 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/mii_to_axis/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean ip 2 | 3 | MODULES := ../mii_to_axis.sv 4 | 5 | all: ip 6 | 7 | clean: 8 | -@$(RM) component.xml 9 | -@$(RM) -rf xgui 10 | 11 | ip: component.xml 12 | 13 | component.xml xgui: $(MODULES) package_ip.tcl 14 | vivado -mode batch -source package_ip.tcl 15 | -------------------------------------------------------------------------------- /util/udpaudiocontrol/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "udpaudiocontrol" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | anyhow = "1.0.69" 10 | clap = { version = "4.1.8", features = ["derive"] } -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/prepend_preamble/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean ip 2 | 3 | MODULES := ../mii_to_axis.sv 4 | 5 | all: ip 6 | 7 | clean: 8 | -@$(RM) component.xml 9 | -@$(RM) -rf xgui 10 | 11 | ip: component.xml 12 | 13 | component.xml xgui: $(MODULES) package_ip.tcl 14 | vivado -mode batch -source package_ip.tcl 15 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangprimer20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clk -period 37.037 -waveform {0 18.518} [get_ports {clk}] -------------------------------------------------------------------------------- /eda/cpu_stopwatch/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := cpu_stopwatch 2 | SRCS := $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) ../../external/picorv32/picorv32.v project.tcl src/sw/bootrom.hex 3 | 4 | include ../build_gowin.mk 5 | 6 | src/sw/bootrom.hex: src/sw/bootrom.c src/sw/link.ld src/sw/Makefile 7 | cd src/sw; make -------------------------------------------------------------------------------- /eda/i2s_master/src/tangprimer20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2023 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/lifegame_fram/src/tangnano9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] -------------------------------------------------------------------------------- /rtl/uart/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | TEST ?= test-uart 4 | SRCS := uart_rx.sv uart_tx.sv test_uart.sv 5 | OPTS := -g2012 6 | 7 | all: $(TEST) 8 | 9 | test-%.elf: $(SRCS) 10 | iverilog $(OPTS) -s test_$(patsubst test-%.elf,%,$@) -o $@ $(SRCS) 11 | 12 | test-%: test-%.elf 13 | ./$< 14 | 15 | clean: 16 | -@$(RM) *.elf 17 | -@$(RM) *.vcd -------------------------------------------------------------------------------- /eda/multi_segment_led/src/tangnano20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/turn_table/src/tangnano9k_pmod/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/tangnano9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] -------------------------------------------------------------------------------- /util/udpaudiosend/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "udpaudiosend" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | anyhow = "1.0.69" 10 | clap = { version = "4.1.8", features = ["derive"] } 11 | env_logger = "0.10.0" 12 | log = "0.4.20" 13 | -------------------------------------------------------------------------------- /util/udpvideosend/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "udpaudiosend" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | anyhow = "1.0.69" 10 | clap = { version = "4.1.8", features = ["derive"] } 11 | env_logger = "0.10.0" 12 | log = "0.4.20" 13 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/comprocboard_9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/comprocboard_9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/ip/dvi_tx/dvi_tx.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=dvi_tx 4 | module=DVI_TX_Top 5 | target_device=gw1nr9c-004 6 | type=dvi_tx 7 | version=1.0 8 | 9 | [Config] 10 | DISABLE_IO_INSERTION=true 11 | ELVDS=true 12 | LANG=0 13 | RX_CLOCK_IN_FREQUENCY=74.25 14 | Synthesis_tool=GowinSynthesis 15 | TLVDS=false 16 | USING_EXTERNAL_CLOCK=false 17 | -------------------------------------------------------------------------------- /rtl/dvi_out/test/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) *.vcd testbench 7 | 8 | test: testbench 9 | ./testbench 10 | 11 | testbench: tb.sv ../dvi_out.sv ../dviout_chisel.v 12 | @echo Compiling testbench 13 | iverilog -g2005-sv $^ -o $@ 14 | 15 | output.vcd: testbench 16 | ./testbench 17 | 18 | view: output.vcd 19 | gtkwave output.vcd& 20 | -------------------------------------------------------------------------------- /rtl/i2c_slave/test/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) *.vcd testbench 7 | 8 | test: testbench 9 | ./testbench 10 | 11 | testbench: tb.sv ../i2c_slave.sv ../iobuf_sim.sv 12 | @echo Compiling testbench 13 | iverilog -g2005-sv $^ -o $@ 14 | 15 | output.vcd: testbench 16 | ./testbench 17 | 18 | view: output.vcd 19 | gtkwave output.vcd& 20 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "external/picorv32"] 2 | path = external/picorv32 3 | url = https://github.com/cliffordwolf/picorv32 4 | [submodule "external/riscv-chisel-book"] 5 | path = external/riscv-chisel-book 6 | url = https://github.com/chadyuu/riscv-chisel-book 7 | [submodule "external/ebaz4205_ethernet"] 8 | path = external/ebaz4205_ethernet 9 | url = https://github.com/ciniml/ebaz4205_ethernet 10 | -------------------------------------------------------------------------------- /mod/pmod_hub75/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | hub75io_clk,pmod1_9 3 | hub75io_r[0],pmod0_1 4 | hub75io_r[1],pmod0_3 5 | hub75io_g[0],pmod0_7 6 | hub75io_g[1],pmod0_8 7 | hub75io_b[0],pmod0_2 8 | hub75io_b[1],pmod0_4 9 | hub75io_row_a,pmod1_7 10 | hub75io_row_b,pmod0_10 11 | hub75io_row_c,pmod1_8 12 | hub75io_row_d,pmod1_1 13 | hub75io_row_e,pmod0_9 14 | hub75io_lat,pmod1_2 15 | hub75io_oe,pmod1_10 -------------------------------------------------------------------------------- /mod/pmod_matrix_led/pmod_pins.csv: -------------------------------------------------------------------------------- 1 | signal_name,pmod_pin 2 | anode[0],pmod0_7 3 | anode[1],pmod0_1 4 | anode[2],pmod0_8 5 | anode[3],pmod0_2 6 | anode[4],pmod0_9 7 | anode[5],pmod0_3 8 | anode[6],pmod0_10 9 | anode[7],pmod0_4 10 | cathode[0],pmod1_7 11 | cathode[1],pmod1_1 12 | cathode[2],pmod1_8 13 | cathode[3],pmod1_2 14 | cathode[4],pmod1_9 15 | cathode[5],pmod1_3 16 | cathode[6],pmod1_10 17 | cathode[7],pmod1_4 -------------------------------------------------------------------------------- /util/mappmod/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "mappmod" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | anyhow = "1.0.69" 10 | bmp = "0.5.0" 11 | clap = { version = "4.1.8", features = ["derive"] } 12 | csv = "1.2.0" 13 | once_cell = "1.17.1" 14 | regex = { version = "1.7.1", features = ["use_std"] } 15 | -------------------------------------------------------------------------------- /eda/targets/tangnano9k_pmod/pmod_ports.csv: -------------------------------------------------------------------------------- 1 | pmod_pin,fpga_pin 2 | pmod0_1,28 3 | pmod0_2,26 4 | pmod0_3,39 5 | pmod0_4,37 6 | pmod0_7,27 7 | pmod0_8,25 8 | pmod0_9,36 9 | pmod0_10,38 10 | pmod1_1,42 11 | pmod1_2,35 12 | pmod1_3,34 13 | pmod1_4,30 14 | pmod1_7,41 15 | pmod1_8,40 16 | pmod1_9,33 17 | pmod1_10,29 18 | pmod2_1,32 19 | pmod2_2,57 20 | pmod2_3,55 21 | pmod2_4,53 22 | pmod2_7,31 23 | pmod2_8,56 24 | pmod2_9,54 25 | pmod2_10,51 -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer25k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2024 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 20 -waveform {0 10} [get_ports {clock}] 9 | set_false_path -from [get_pins {reset_seq_dvi/reset_seq_0_s0/Q}] -to [get_pins {oser_dvi_*/RESET}] -------------------------------------------------------------------------------- /rtl/ethernet/util/axis_dispose.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module axis_dispose #( 4 | parameter TDATA_BYTES = 1 5 | ) ( 6 | input wire aclk, 7 | input wire aresetn, 8 | 9 | input wire [TDATA_BYTES*8-1:0] saxis_tdata, 10 | input wire saxis_tvalid, 11 | output wire saxis_tready 12 | ); 13 | 14 | assign saxis_tready = 1; 15 | 16 | endmodule 17 | 18 | `default_nettype wire 19 | -------------------------------------------------------------------------------- /eda/ethernet_video/probedec.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cargo run -- --port /dev/ttyACM0 \ 4 | --signal advanceRenderingBufferIndex:1 \ 5 | --signal backPressureValid:1 \ 6 | --signal sendContextValid:1 \ 7 | --signal sendContextReady:1 \ 8 | --signal sendDataValid:1 \ 9 | --signal sendDataReady:1 \ 10 | --signal renderingBufferIndex:2 \ 11 | --signal receivingBuferIndex:2 \ 12 | --csv output.csv \ 13 | --count 1 \ 14 | && code output.0.csv -------------------------------------------------------------------------------- /eda/blink/src/tangnano9k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 52; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "led[0]" 10; 5 | IO_LOC "led[1]" 11; 6 | IO_LOC "led[2]" 13; 7 | IO_LOC "led[3]" 14; 8 | IO_LOC "led[4]" 15; 9 | IO_LOC "led[5]" 16; 10 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 11 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 12 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 13 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 14 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 15 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 16 | -------------------------------------------------------------------------------- /eda/multi_segment_led/src/tangnano20k/pins.cst.template: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 4; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_PORT "com_ser" IO_TYPE=LVCMOS33; 5 | IO_PORT "com_rclk" IO_TYPE=LVCMOS33; 6 | IO_PORT "com_srclk" IO_TYPE=LVCMOS33; 7 | IO_PORT "com_oe" IO_TYPE=LVCMOS33; 8 | IO_PORT "seg_ser" IO_TYPE=LVCMOS33; 9 | IO_PORT "seg_rclk" IO_TYPE=LVCMOS33; 10 | IO_PORT "seg_srclk" IO_TYPE=LVCMOS33; 11 | IO_PORT "seg_oe" IO_TYPE=LVCMOS33; 12 | 13 | // PMOD pin locations 14 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_mii/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 7 | -@$(RM) -rf xsim.dir .Xil 8 | 9 | xelab.pb: tb.sv ../axis_to_mii.sv 10 | xvlog -work work --sv tb.sv ../axis_to_mii.sv 11 | xelab -L work tb -debug all 12 | 13 | compile: xelab.pb 14 | 15 | test: xelab.pb 16 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb 17 | 18 | view: test.wdb 19 | vivado ./test.wdb& 20 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_mii_to_axis/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 7 | -@$(RM) -rf xsim.dir .Xil 8 | 9 | xelab.pb: tb.sv ../mii_to_axis.sv 10 | xvlog -work work --sv tb.sv ../mii_to_axis.sv 11 | xelab -L work tb -debug all 12 | 13 | compile: xelab.pb 14 | 15 | test: xelab.pb 16 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb 17 | 18 | view: test.wdb 19 | vivado ./test.wdb& 20 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_rmii/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 7 | -@$(RM) -rf xsim.dir .Xil 8 | 9 | xelab.pb: tb.sv ../axis_to_rmii.sv 10 | xvlog -work work --sv tb.sv ../axis_to_rmii.sv 11 | xelab -L work tb -debug all 12 | 13 | compile: xelab.pb 14 | 15 | test: xelab.pb 16 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb 17 | 18 | view: test.wdb 19 | vivado ./test.wdb& 20 | -------------------------------------------------------------------------------- /rtl/chisel/uart/uartsystem.anno.json: -------------------------------------------------------------------------------- 1 | [ 2 | { 3 | "class":"logger.LogLevelAnnotation", 4 | "globalLogLevel":{ 5 | 6 | } 7 | }, 8 | { 9 | "class":"firrtl.stage.phases.DriverCompatibility$TopNameAnnotation", 10 | "topName":"uartsystem" 11 | }, 12 | { 13 | "class":"firrtl.EmitCircuitAnnotation", 14 | "emitter":"firrtl.VerilogEmitter" 15 | }, 16 | { 17 | "class":"firrtl.transforms.BlackBoxTargetDirAnno", 18 | "targetDir":"rtl/uart" 19 | } 20 | ] -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/tangnano9k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 52; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "led[0]" 10; 5 | IO_LOC "led[1]" 11; 6 | IO_LOC "led[2]" 13; 7 | IO_LOC "led[3]" 14; 8 | IO_LOC "led[4]" 15; 9 | IO_LOC "led[5]" 16; 10 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 11 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 12 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 13 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 14 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 15 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 16 | -------------------------------------------------------------------------------- /eda/i2s_master/src/tangnano9k/ip/gowin_rpll/gowin_rpll.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_rpll 4 | module=gowin_rpll 5 | target_device=gw1nr9c-004 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=50 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=20 18 | CLKOUT_TOLERANCE=0 19 | DYNAMIC=true 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/i2s_master/src/tangprimer20k/ip/rpll_main/rpll_main.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=rpll_main 4 | module=rpll_main 5 | target_device=gw2a18c-011 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=27 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=36 18 | CLKOUT_TOLERANCE=3 19 | DYNAMIC=false 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/ethernet_audio/src/tangprimer20k/ip/rpll_main/rpll_main.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=rpll_main 4 | module=rpll_main 5 | target_device=gw2a18c-011 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=27 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=36 18 | CLKOUT_TOLERANCE=3 19 | DYNAMIC=false 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/ethernet_video/src/tangprimer20k/ip/rpll_main/rpll_main.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=rpll_main 4 | module=rpll_main 5 | target_device=gw2a18c-011 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=27 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=36 18 | CLKOUT_TOLERANCE=3 19 | DYNAMIC=false 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /rtl/ethernet/crc/test/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean compile test view 2 | 3 | MODULES := ../crc_mac.v ../../util/axis_if.sv 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 9 | -@$(RM) -rf xsim.dir .Xil 10 | 11 | xelab.pb: tb.sv $(MODULES) 12 | xvlog -work work --sv tb.sv $(MODULES) 13 | xelab -L work tb -debug all 14 | 15 | compile: xelab.pb 16 | 17 | test: xelab.pb 18 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb 19 | 20 | view: test.wdb 21 | vivado ./test.wdb& 22 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/ip/gowin_rpll/gowin_rpll.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_rpll 4 | module=gowin_rpll_dvi 5 | target_device=gw1nr9c-004 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=27 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=74.25 18 | CLKOUT_TOLERANCE=0 19 | DYNAMIC=true 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_pmod/ip/gowin_rpll/gowin_rpll.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_rpll 4 | module=gowin_rpll 5 | target_device=gw1nr9c-004 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=50 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=20 18 | CLKOUT_TOLERANCE=0 19 | DYNAMIC=true 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | SIM_SRCS := tb.sv ./iobuf_sim.sv ./top.sv ./riscv.v 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) *.vcd testbench 9 | 10 | test: testbench 11 | ./testbench 12 | 13 | testbench: $(SIM_SRCS) ../sw/bootrom.hex 14 | @echo Compiling testbench 15 | iverilog -g2012 $(SIM_SRCS) -o $@ 16 | 17 | output.vcd: testbench 18 | ./testbench > /dev/null 2>&1 19 | 20 | ../sw/bootrom.hex: 21 | cd ../sw && make 22 | 23 | view: output.vcd 24 | gtkwave output.vcd& 25 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | SIM_SRCS := tb.sv ./iobuf_sim.sv ./top.sv ./riscv.v 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) *.vcd testbench 9 | 10 | test: testbench 11 | ./testbench 12 | 13 | testbench: $(SIM_SRCS) ../sw/bootrom.hex 14 | @echo Compiling testbench 15 | iverilog -g2012 $(SIM_SRCS) -o $@ 16 | 17 | output.vcd: testbench 18 | ./testbench > /dev/null 2>&1 19 | 20 | ../sw/bootrom.hex: 21 | cd ../sw && make 22 | 23 | view: output.vcd 24 | gtkwave output.vcd& 25 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/test_crc_mac/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean compile test view 2 | 3 | MODULES := ../crc_mac.sv ../../util/axis_if.sv 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 9 | -@$(RM) -rf xsim.dir .Xil 10 | 11 | xelab.pb: tb.sv $(MODULES) 12 | xvlog -work work --sv tb.sv $(MODULES) 13 | xelab -L work tb -debug all 14 | 15 | compile: xelab.pb 16 | 17 | test: xelab.pb 18 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb 19 | 20 | view: test.wdb 21 | vivado ./test.wdb& 22 | -------------------------------------------------------------------------------- /rtl/i2c_slave/iobuf_sim.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file iobuf_sim.v 3 | * @brief IOBUF module for iverilog simulation. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module IOBUF ( 12 | output wire O, 13 | input wire I, 14 | inout wire IO, 15 | input wire OEN 16 | ); 17 | 18 | assign O = IO; 19 | assign IO = !OEN ? I : 1'bz; 20 | 21 | endmodule -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/ip/gowin_rpll_ser/gowin_rpll_ser.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_rpll_ser 4 | module=gowin_rpll_ser 5 | target_device=gw1nr9c-004 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=74.25 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=371.25 18 | CLKOUT_TOLERANCE=0 19 | DYNAMIC=true 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer20k/ip/gowin_rpll_dvi/gowin_rpll_dvi.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_rpll_dvi 4 | module=gowin_rpll_dvi 5 | target_device=gw2a18c-011 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=27 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=148.5 18 | CLKOUT_TOLERANCE=0 19 | DYNAMIC=false 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer20k/ip/gowin_rpll_ser/gowin_rpll_ser.ipc: -------------------------------------------------------------------------------- 1 | [General] 2 | ipc_version=4 3 | file=gowin_rpll_ser 4 | module=gowin_rpll_ser 5 | target_device=gw2a18c-011 6 | type=clock_rpll 7 | version=1.0 8 | 9 | [Config] 10 | CKLOUTD3=false 11 | CLKFB_SOURCE=0 12 | CLKIN_FREQ=27 13 | CLKOUTD=false 14 | CLKOUTP=false 15 | CLKOUT_BYPASS=false 16 | CLKOUT_DIVIDE_DYN=true 17 | CLKOUT_FREQ=371.25 18 | CLKOUT_TOLERANCE=0 19 | DYNAMIC=false 20 | LANG=0 21 | LOCK_EN=true 22 | MODE_GENERAL=true 23 | PLL_PWD=false 24 | RESET_PLL=false 25 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_matrix_led/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | SIM_SRCS := tb.sv ./iobuf_sim.sv ./top.sv ./riscv.v 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) *.vcd testbench 9 | 10 | test: testbench 11 | ./testbench 12 | 13 | testbench: $(SIM_SRCS) ../sw/bootrom.hex 14 | @echo Compiling testbench 15 | iverilog -g2012 $(SIM_SRCS) -o $@ 16 | 17 | output.vcd: testbench 18 | ./testbench > /dev/null 2>&1 19 | 20 | ../sw/bootrom.hex: 21 | cd ../sw && make 22 | 23 | view: output.vcd 24 | gtkwave output.vcd& 25 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/iobuf_sim.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file iobuf_sim.v 3 | * @brief IOBUF module for iverilog simulation. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module IOBUF ( 12 | output wire O, 13 | input wire I, 14 | inout wire IO, 15 | input wire OEN 16 | ); 17 | 18 | assign O = IO; 19 | assign IO = !OEN ? I : 1'bz; 20 | 21 | endmodule -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k/iobuf_sim.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file iobuf_sim.v 3 | * @brief IOBUF module for iverilog simulation. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module IOBUF ( 12 | output wire O, 13 | input wire I, 14 | inout wire IO, 15 | input wire OEN 16 | ); 17 | 18 | assign O = IO; 19 | assign IO = !OEN ? I : 1'bz; 20 | 21 | endmodule -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean ip 2 | 3 | MODULES := append_crc.sv \ 4 | remove_crc.sv \ 5 | crc_mac.sv \ 6 | mii_mac_rx.sv \ 7 | mii_mac_tx.sv \ 8 | mii_mac.sv \ 9 | ../mii_axis/prepend_preamble.sv \ 10 | ../mii_axis/axis_to_mii.sv \ 11 | ../mii_axis/mii_to_axis.sv \ 12 | ../util/simple_fifo.v 13 | 14 | all: ip 15 | 16 | clean: 17 | -@$(RM) component.xml 18 | -@$(RM) -rf xgui 19 | 20 | ip: component.xml 21 | 22 | component.xml xgui: $(MODULES) package_ip.tcl 23 | vivado -mode batch -source package_ip.tcl 24 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_matrix_led/iobuf_sim.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file iobuf_sim.v 3 | * @brief IOBUF module for iverilog simulation. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module IOBUF ( 12 | output wire O, 13 | input wire I, 14 | inout wire IO, 15 | input wire OEN 16 | ); 17 | 18 | assign O = IO; 19 | assign IO = !OEN ? I : 1'bz; 20 | 21 | endmodule -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/comprocboard_9k/test/iobuf_sim.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file iobuf_sim.v 3 | * @brief IOBUF module for iverilog simulation. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module IOBUF ( 12 | output wire O, 13 | input wire I, 14 | inout wire IO, 15 | input wire OEN 16 | ); 17 | 18 | assign O = IO; 19 | assign IO = !OEN ? I : 1'bz; 20 | 21 | endmodule -------------------------------------------------------------------------------- /eda/targets/tangprimer20k/pmod_ports.csv: -------------------------------------------------------------------------------- 1 | pmod_pin,fpga_pin 2 | pmod0_1,P6 3 | pmod0_2,R8 4 | pmod0_3,P8 5 | pmod0_4,T9 6 | pmod0_7,T6 7 | pmod0_8,T7 8 | pmod0_9,T8 9 | pmod0_10,P9 10 | pmod1_1,P11 11 | pmod1_2,R11 12 | pmod1_3,M15 13 | pmod1_4,J16 14 | pmod1_7,T11 15 | pmod1_8,T12 16 | pmod1_9,M14 17 | pmod1_10,J14 18 | pmod2_1,E15 19 | pmod2_2,A15 20 | pmod2_3,A14 21 | pmod2_4,C12 22 | pmod2_7,D14 23 | pmod2_8,B14 24 | pmod2_9,B13 25 | pmod2_10,B12 26 | pmod3_1,B11 27 | pmod3_2,D11 28 | pmod3_3,N7 29 | pmod3_4,N8 30 | pmod3_7,A11 31 | pmod3_8,N6 32 | pmod3_9,N9 33 | pmod3_10,L9 -------------------------------------------------------------------------------- /eda/targets/tangprimer20k_hub75/pmod_ports.csv: -------------------------------------------------------------------------------- 1 | pmod_pin,fpga_pin 2 | pmod0_1,P6 3 | pmod0_2,R8 4 | pmod0_3,P8 5 | pmod0_4,T9 6 | pmod0_7,T6 7 | pmod0_8,T7 8 | pmod0_9,T8 9 | pmod0_10,P9 10 | pmod1_1,P11 11 | pmod1_2,R11 12 | pmod1_3,M15 13 | pmod1_4,J16 14 | pmod1_7,T11 15 | pmod1_8,T12 16 | pmod1_9,M14 17 | pmod1_10,J14 18 | pmod2_1,E15 19 | pmod2_2,A15 20 | pmod2_3,A14 21 | pmod2_4,C12 22 | pmod2_7,D14 23 | pmod2_8,B14 24 | pmod2_9,B13 25 | pmod2_10,B12 26 | pmod3_1,B11 27 | pmod3_2,D11 28 | pmod3_3,N7 29 | pmod3_4,N8 30 | pmod3_7,A11 31 | pmod3_8,N6 32 | pmod3_9,N9 33 | pmod3_10,L9 -------------------------------------------------------------------------------- /eda/blink/src/runber/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file top.sv 3 | * @brief Top module for WS2812 example 4 | */ 5 | // Copyright 2021 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | module top ( 11 | input wire clock, 12 | 13 | output logic [7:0] led_out 14 | ); 15 | 16 | localparam int CLOCK_HZ = 12_000_000; 17 | 18 | blink #( 19 | .CLOCK_HZ(CLOCK_HZ), 20 | .NUMBER_OF_LEDS(8) 21 | ) blink_inst ( 22 | .* 23 | ); 24 | 25 | endmodule -------------------------------------------------------------------------------- /rtl/ethernet/util/test_simple_fifo/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean compile test view 2 | 3 | MODULES := ../simple_fifo.v ../axis_if.sv 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 9 | -@$(RM) -rf xsim.dir .Xil 10 | 11 | xelab.pb: tb.sv $(MODULES) 12 | xvlog -work work --sv tb.sv $(MODULES) 13 | xelab -L work tb -debug all 14 | 15 | compile: xelab.pb 16 | 17 | test: xelab.pb 18 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb | tee test.log 19 | if grep Error test.log; then echo "Error."; exit 1; fi 20 | 21 | view: test.wdb 22 | vivado ./test.wdb& 23 | -------------------------------------------------------------------------------- /rtl/ethernet/rmii_mac/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean ip 2 | 3 | MODULES := ../mii_mac/append_crc.sv \ 4 | ../mii_mac/remove_crc.sv \ 5 | ../mii_mac/crc_mac.sv \ 6 | ../mii_mac/mii_mac_rx.sv \ 7 | ../mii_mac/mii_mac_tx.sv \ 8 | ./rmii_mac.sv \ 9 | ../mii_axis/prepend_preamble.sv \ 10 | ../mii_axis/axis_to_rmii.sv \ 11 | ../mii_axis/rmii_to_axis.sv \ 12 | ../util/simple_fifo.v 13 | 14 | all: ip 15 | 16 | clean: 17 | -@$(RM) component.xml 18 | -@$(RM) -rf xgui 19 | 20 | ip: component.xml 21 | 22 | component.xml xgui: $(MODULES) package_ip.tcl 23 | vivado -mode batch -source package_ip.tcl 24 | -------------------------------------------------------------------------------- /eda/i2s_master/src/tangnano9k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /util/probedec/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "probedec" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | anyhow = "1.0.71" 10 | bitvec = "1.0.1" 11 | bytes = "1.4.0" 12 | clap = { version = "4.3.11", features = ["derive"] } 13 | csv = "1.2.2" 14 | env_logger = "0.10.0" 15 | futures = "0.3.28" 16 | log = { version = "0.4.19", features = ["std"] } 17 | tokio = { version = "1.29.1", features = ["rt", "macros", "full"] } 18 | tokio-serial = "5.4.4" 19 | tokio-util = { version = "0.7.8", features = ["codec"] } 20 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer25k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/i2s_master/src/tangprimer20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/turn_table/src/tangnano9k_pmod/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_axis/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 7 | -@$(RM) -rf xsim.dir .Xil 8 | 9 | xelab.pb: tb.sv ../axis_to_mii.sv ../mii_to_axis.sv ../prepend_preamble.sv 10 | xvlog -work work --sv tb.sv ../axis_to_mii.sv ../mii_to_axis.sv ../prepend_preamble.sv 11 | xelab -L work tb -debug all 12 | 13 | compile: xelab.pb 14 | 15 | test: xelab.pb 16 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb | tee test.log 17 | if grep Error test.log; then echo "Error."; exit 1; fi 18 | view: test.wdb 19 | vivado ./test.wdb& 20 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangprimer20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/ethernet_audio/src/tangprimer20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_pmod/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/ethernet_video/src/tangprimer20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/multi_segment_led/src/tangnano20k/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/test_append_crc/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean compile test view 2 | 3 | MODULES := ../crc_mac.sv ../append_crc.sv ../remove_crc.sv ../../util/axis_if.sv 4 | 5 | all: test 6 | 7 | clean: 8 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 9 | -@$(RM) -rf xsim.dir .Xil 10 | 11 | xelab.pb: tb.sv $(MODULES) 12 | xvlog -work work --sv tb.sv $(MODULES) 13 | xelab -L work tb -debug all 14 | 15 | compile: xelab.pb 16 | 17 | test: xelab.pb 18 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb | tee test.log 19 | if grep Error test.log; then echo "Error."; exit 1; fi 20 | 21 | view: test.wdb 22 | vivado ./test.wdb& 23 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_matrix_led/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k_hub75/reset_seq.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module reset_seq #( 3 | parameter int RESET_DELAY_CYCLES = 16 4 | )( 5 | input wire reset_in, 6 | input wire clock, 7 | 8 | output logic reset_out 9 | ); 10 | 11 | // Reset sequencer 12 | logic [RESET_DELAY_CYCLES:0] reset_seq; 13 | initial begin 14 | reset_seq = '1; 15 | end 16 | always_ff @(posedge clock) begin 17 | if(reset_in) begin 18 | reset_seq = '1; 19 | end 20 | else begin 21 | reset_seq <= reset_seq >> 1; 22 | end 23 | end 24 | 25 | assign reset_out = reset_seq[0]; 26 | 27 | endmodule 28 | 29 | 30 | `default_nettype wire -------------------------------------------------------------------------------- /rtl/ethernet/mii_axis/test_axis_to_axis_rmii/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | all: test 4 | 5 | clean: 6 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 7 | -@$(RM) -rf xsim.dir .Xil 8 | 9 | xelab.pb: tb.sv ../axis_to_rmii.sv ../rmii_to_axis.sv ../prepend_preamble.sv 10 | xvlog -work work --sv tb.sv ../axis_to_rmii.sv ../rmii_to_axis.sv ../prepend_preamble.sv 11 | xelab -L work tb -debug all 12 | 13 | compile: xelab.pb 14 | 15 | test: xelab.pb 16 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb | tee test.log 17 | if grep Error test.log; then echo "Error."; exit 1; fi 18 | view: test.wdb 19 | vivado ./test.wdb& 20 | -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 11 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 11 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] -------------------------------------------------------------------------------- /eda/matrix_led/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | set_option -use_sspi_as_gpio 1 15 | 16 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 17 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 18 | 19 | run all -------------------------------------------------------------------------------- /rtl/uart/uart_system.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module uart_system ( 4 | input wire clock, 5 | input wire resetn, 6 | 7 | output wire tx, 8 | input wire rx 9 | ); 10 | 11 | localparam int CLOCK_HZ = 24000000; 12 | localparam int BAUD_RATE = 115200; 13 | 14 | logic reset; 15 | assign reset = !resetn; 16 | logic data_valid; 17 | logic data_ready; 18 | logic [7:0] data_bits; 19 | logic overrun; 20 | 21 | uart_rx #(.BAUD_DIVIDER(CLOCK_HZ/BAUD_RATE)) uart_rx_inst(.*); 22 | uart_tx #(.BAUD_DIVIDER(CLOCK_HZ/BAUD_RATE)) uart_tx_inst( 23 | .data_bits(data_bits + 8'd1), 24 | .*); 25 | 26 | endmodule 27 | 28 | `default_nettype wire -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 10 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] 11 | set_false_path -from [get_pins {reset_seq_dvi/reset_seq_0_s0/Q}] -to [get_pins {oser_dvi_*/RESET}] -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 10 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] 11 | set_false_path -from [get_pins {reset_seq_dvi/reset_seq_0_s0/Q}] -to [get_pins {oser_dvi_*/RESET}] -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_matrix_led/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 11 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k_hub75/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 11 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer25k/pins.cst.template: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" E2; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_PORT "tmds_data_p[2]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 5 | IO_PORT "tmds_data_p[1]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 6 | IO_PORT "tmds_data_p[0]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 7 | IO_PORT "tmds_clk_p" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 8 | IO_PORT "tmds_data_n[2]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 9 | IO_PORT "tmds_data_n[1]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 10 | IO_PORT "tmds_data_n[0]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 11 | IO_PORT "tmds_clk_n" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 12 | -------------------------------------------------------------------------------- /rtl/ethernet/README.md: -------------------------------------------------------------------------------- 1 | # 100M Ethernet MAC 2 | 3 | ## 概要 4 | 5 | 100M Ethernet PHYを使って、PL上でEthernet通信を行うためのコアです。 6 | 7 | このデザインは株式会社フィックスターズ Tech Blog の記事(https://proc-cpuinfo.fixstars.com/2020/05/alveo-u50-10g-ethernet/) で説明されている10G MAC IPを参考に作られています。 8 | オリジナルのリポジトリは https://github.com/fixstars/xg_mac です。 9 | 10 | ## 動作環境 11 | 12 | 以下のボードで動作確認を行っています。 13 | 14 | * EBAZ4205 15 | * Tang Nano 9K + LAN8720 16 | * Tang Primer 20K (RTL8211) 17 | 18 | ## ライセンス 19 | 20 | ほとんどオリジナルの10G Ethrenet MACのコードは残っていませんが、一部プロジェクト復元周りのスクリプトやFIFOのRTLを使っています。 21 | 10G Ethernet MAC IP自体は3条項BSDライセンスで公開されていますので、本プロジェクトのデザインも3条項BSDライセンスとします。 22 | 23 | 詳しくは本ディレクトリに含まれている `LICENSE` ファイルを確認してください。 -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/sw/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | CC = riscv64-unknown-elf-gcc 4 | OBJDUMP = riscv64-unknown-elf-objdump 5 | OBJCOPY = riscv64-unknown-elf-objcopy 6 | CFLAGS = -mabi=ilp32 -march=rv32i -Os -g 7 | LDFLAGS = -Wl,-Tlink.ld -nostartfiles 8 | 9 | OBJS := bootrom.o 10 | 11 | all: bootrom.bin bootrom.hex bootrom.dump 12 | 13 | bootrom.elf: $(OBJS) link.ld 14 | $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJS) 15 | 16 | %.o: %.c 17 | $(CC) -c -o $@ $(CFLAGS) $< 18 | 19 | %.bin: %.elf 20 | $(OBJCOPY) -O binary $< $@ 21 | 22 | %.hex: %.bin 23 | od -An -tx4 -w4 -v $< > $@ 24 | %.dump: %.elf 25 | $(OBJDUMP) -dSC $< > $@ 26 | 27 | clean: 28 | -@$(RM) *.o *.elf *.bin *.hex -------------------------------------------------------------------------------- /eda/cpu_stopwatch/src/sw/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | CC = riscv64-unknown-elf-gcc 4 | OBJDUMP = riscv64-unknown-elf-objdump 5 | OBJCOPY = riscv64-unknown-elf-objcopy 6 | CFLAGS = -mabi=ilp32 -march=rv32i -Os -g 7 | LDFLAGS = -Wl,-Tlink.ld -nostartfiles 8 | 9 | OBJS := bootrom.o 10 | 11 | all: bootrom.bin bootrom.hex bootrom.dump 12 | 13 | bootrom.elf: $(OBJS) link.ld 14 | $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJS) 15 | 16 | %.o: %.c 17 | $(CC) -c -o $@ $(CFLAGS) $< 18 | 19 | %.bin: %.elf 20 | $(OBJCOPY) -O binary $< $@ 21 | 22 | %.hex: %.bin 23 | od -An -tx4 -w4 -v $< > $@ 24 | %.dump: %.elf 25 | $(OBJDUMP) -dSC $< > $@ 26 | 27 | clean: 28 | -@$(RM) *.o *.elf *.bin *.hex -------------------------------------------------------------------------------- /eda/blink/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/blink/blink_all.sv] 17 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 18 | 19 | run all -------------------------------------------------------------------------------- /eda/blink/src/tangnano9k/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file top.sv 3 | * @brief Top module for LED blink example 4 | */ 5 | // Copyright 2021-2022 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | module top ( 11 | input wire clock, 12 | 13 | output logic [5:0] led 14 | ); 15 | 16 | localparam int CLOCK_HZ = 27_000_000; 17 | 18 | logic [5:0] led_out; 19 | 20 | blink #( 21 | .CLOCK_HZ(CLOCK_HZ), 22 | .NUMBER_OF_LEDS(6) 23 | ) blink_inst ( 24 | .* 25 | ); 26 | 27 | always_comb begin 28 | led <= led_out; 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/sw/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | CC = riscv64-unknown-elf-gcc 4 | OBJDUMP = riscv64-unknown-elf-objdump 5 | OBJCOPY = riscv64-unknown-elf-objcopy 6 | CFLAGS = -mabi=ilp32 -march=rv32i -Os -g 7 | LDFLAGS = -Wl,-Tlink.ld -nostartfiles 8 | 9 | OBJS := bootrom.o 10 | 11 | all: bootrom.bin bootrom.hex bootrom.dump 12 | 13 | bootrom.elf: $(OBJS) link.ld 14 | $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJS) 15 | 16 | %.o: %.c 17 | $(CC) -c -o $@ $(CFLAGS) $< 18 | 19 | %.bin: %.elf 20 | $(OBJCOPY) -O binary $< $@ 21 | 22 | %.hex: %.bin 23 | od -An -tx4 -w4 -v $< > $@ 24 | %.dump: %.elf 25 | $(OBJDUMP) -dSC $< > $@ 26 | 27 | clean: 28 | -@$(RM) *.o *.elf *.bin *.hex -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/sw/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | CC = riscv64-unknown-elf-gcc 4 | OBJDUMP = riscv64-unknown-elf-objdump 5 | OBJCOPY = riscv64-unknown-elf-objcopy 6 | CFLAGS = -mabi=ilp32 -march=rv32i -Os -g 7 | LDFLAGS = -Wl,-Tlink.ld -nostartfiles 8 | 9 | OBJS := bootrom.o 10 | 11 | all: bootrom.bin bootrom.hex bootrom.dump 12 | 13 | bootrom.elf: $(OBJS) link.ld 14 | $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJS) 15 | 16 | %.o: %.c 17 | $(CC) -c -o $@ $(CFLAGS) $< 18 | 19 | %.bin: %.elf 20 | $(OBJCOPY) -O binary $< $@ 21 | 22 | %.hex: %.bin 23 | od -An -tx4 -w4 -v $< > $@ 24 | %.dump: %.elf 25 | $(OBJDUMP) -dSC $< > $@ 26 | 27 | clean: 28 | -@$(RM) *.o *.elf *.bin *.hex -------------------------------------------------------------------------------- /chisel/src/main/scala/spi/spi_io.scala.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2022. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | // See README.md for license details. 8 | 9 | package spi 10 | 11 | import chisel3._ 12 | import chisel3.util._ 13 | import _root_.util._ 14 | 15 | class SPIIO extends Bundle { 16 | val miso = Input(Bool()) 17 | val mosi = Output(Bool()) 18 | val cs = Output(Bool()) 19 | val sck = Output(Bool()) 20 | } 21 | object SPIIO { 22 | def apply() : SPIIO = { 23 | new SPIIO() 24 | } 25 | } -------------------------------------------------------------------------------- /chisel/sbt/build.sbt: -------------------------------------------------------------------------------- 1 | ThisBuild / scalaVersion := "2.13.8" 2 | ThisBuild / version := "0.1.0" 3 | ThisBuild / organization := "org.fugafuga" 4 | 5 | lazy val fpga_samples = (project in file("..")) 6 | .settings( 7 | name := "fpga_samples", 8 | libraryDependencies ++= Seq( 9 | "edu.berkeley.cs" %% "chisel3" % "3.5.4", 10 | "edu.berkeley.cs" %% "chiseltest" % "0.5.4" % "test" 11 | ), 12 | scalacOptions ++= Seq( 13 | "-Xsource:2.13", 14 | "-language:reflectiveCalls", 15 | "-deprecation", 16 | "-feature", 17 | "-Xcheckinit" 18 | ), 19 | addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.4" cross CrossVersion.full), 20 | ) 21 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/sw/bootrom.hex: -------------------------------------------------------------------------------- 1 | 0080006f 2 | 0040006f 3 | 18000117 4 | 1f810113 5 | 004000ef 6 | 400007b7 7 | 0047a603 8 | 00000313 9 | 00100793 10 | 00165613 11 | 080008b7 12 | 300015b7 13 | 30000e37 14 | 0a888713 15 | 00074503 16 | 04051a63 17 | 00179713 18 | 00fe2023 19 | 0077d793 20 | 0017f793 21 | 00f767b3 22 | c8002873 23 | c0002ef3 24 | c8002773 25 | fee81ae3 26 | c8002773 27 | c00026f3 28 | c8002573 29 | fea71ae3 30 | 41d68533 31 | 00a6b6b3 32 | 41070733 33 | 40d70733 34 | fae318e3 35 | fcc56ee3 36 | fa9ff06f 37 | 00170713 38 | 0005a683 39 | 0016f693 40 | fe069ce3 41 | 00a5a023 42 | f95ff06f 43 | 6c6c6548 44 | 52202c6f 45 | 2d435349 46 | 000a0d56 47 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/comprocboard_9k/test/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean test view 2 | 3 | SIM_SRCS := tb.sv ./iobuf_sim.sv ../top.sv ../../../../../rtl/cpu_riscv_chisel_book_matrix/tangnano9k/riscv.v 4 | BOOTROM := ../../sw/bootrom.hex 5 | 6 | all: test 7 | 8 | clean: 9 | -@$(RM) *.vcd testbench 10 | 11 | test: testbench 12 | ./testbench 13 | 14 | testbench: $(SIM_SRCS) $(BOOTROM) 15 | @echo Compiling testbench 16 | iverilog -g2012 $(SIM_SRCS) -o $@ -D BOOTROM_PATH=\"$(abspath $(BOOTROM))\" 17 | 18 | $(BOOTROM): ../../sw/bootrom.c 19 | cd ../../..; make TARGET=comprocboard_9k src/sw/bootrom.hex 20 | 21 | output.vcd: testbench 22 | ./testbench > /dev/null 2>&1 23 | 24 | view: output.vcd 25 | gtkwave output.vcd& 26 | -------------------------------------------------------------------------------- /eda/multi_segment_led/src/tangnano20k/pins.cst: -------------------------------------------------------------------------------- 1 | // This file is automatically generated by build script. DO NOT EDIT THIS FILE. 2 | IO_LOC "clock" 4; 3 | IO_PORT "clock" IO_TYPE=LVCMOS33; 4 | 5 | IO_PORT "com_ser" IO_TYPE=LVCMOS33; 6 | IO_PORT "com_rclk" IO_TYPE=LVCMOS33; 7 | IO_PORT "com_srclk" IO_TYPE=LVCMOS33; 8 | IO_PORT "com_oe" IO_TYPE=LVCMOS33; 9 | IO_PORT "seg_ser" IO_TYPE=LVCMOS33; 10 | IO_PORT "seg_rclk" IO_TYPE=LVCMOS33; 11 | IO_PORT "seg_srclk" IO_TYPE=LVCMOS33; 12 | IO_PORT "seg_oe" IO_TYPE=LVCMOS33; 13 | 14 | // PMOD pin locations 15 | IO_LOC "com_ser" 18 16 | IO_LOC "com_rclk" 20 17 | IO_LOC "seg_ser" 31 18 | IO_LOC "seg_rclk" 49 19 | IO_LOC "com_srclk" 19 20 | IO_LOC "com_oe" 17 21 | IO_LOC "seg_srclk" 30 22 | IO_LOC "seg_oe" 29 23 | -------------------------------------------------------------------------------- /eda/blink/src/tangnano1k/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file top.sv 3 | * @brief Top module for WS2812 example 4 | */ 5 | // Copyright 2021 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | module top ( 11 | input wire clock, 12 | 13 | output logic led_r, 14 | output logic led_g, 15 | output logic led_b 16 | ); 17 | 18 | localparam int CLOCK_HZ = 27_000_000; 19 | 20 | logic [2:0] led_out; 21 | 22 | blink #( 23 | .CLOCK_HZ(CLOCK_HZ), 24 | .NUMBER_OF_LEDS(3) 25 | ) blink_inst ( 26 | .* 27 | ); 28 | 29 | always_comb begin 30 | led_r <= led_out[0]; 31 | led_g <= led_out[1]; 32 | led_b <= led_out[2]; 33 | end 34 | 35 | endmodule -------------------------------------------------------------------------------- /chisel/src/main/scala/sound/timing.json5: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | {"name": "dataIn.valid", "wave": "1........0............."}, 3 | {"name": "dataIn.ready", "wave": "0......10.............."}, 4 | {"name": "dataIn.bits", "wave": "3x.3.....x.............", "data": ["A", "B"]}, 5 | {}, 6 | {"name": "ws", "wave": "10...1...0...1...0...1."}, 7 | {"name": "bck", "wave": "p......................"}, 8 | {"name": "din", "wave": "03...4...3...4...3...4."}, 9 | {}, 10 | {"name": "counter", "wave": "33333444433334444333344", "data": ["0", "3", "2", "1", "0", "3", "2", "1", "0", "3", "2", "1", "0", "3", "2", "1", "0", "3", "2", "1", "0", "3"]}, 11 | {"name": "data", "wave": "33...4...3...4...3...4.", "data": ["0", "0", "0", "A", "A", "B", "B"]}, 12 | ]} -------------------------------------------------------------------------------- /eda/lifegame_fram/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | set_option -use_sspi_as_gpio 1 15 | 16 | add_file -type verilog [file normalize ${RTL_DIR}/chisel/lifegame_fram/lifegame_fram.v] 17 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 18 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 19 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 20 | 21 | run all -------------------------------------------------------------------------------- /eda/uart/uart.gprj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 5 6 | gw1n1-004 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangprimer25k/pins.cst: -------------------------------------------------------------------------------- 1 | // This file is automatically generated by build script. DO NOT EDIT THIS FILE. 2 | IO_LOC "clock" E2; 3 | IO_PORT "clock" IO_TYPE=LVCMOS33; 4 | 5 | IO_PORT "tmds_data_p[2]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 6 | IO_PORT "tmds_data_p[1]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 7 | IO_PORT "tmds_data_p[0]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 8 | IO_PORT "tmds_clk_p" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 9 | IO_PORT "tmds_data_n[2]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 10 | IO_PORT "tmds_data_n[1]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 11 | IO_PORT "tmds_data_n[0]" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 12 | IO_PORT "tmds_clk_n" PULL_MODE=NONE IO_TYPE=LVCMOS33D DRIVE=8; 13 | IO_LOC "tmds_data_p[2]" F5 14 | IO_LOC "tmds_data_p[1]" G7 15 | IO_LOC "tmds_data_p[0]" H8 16 | IO_LOC "tmds_clk_p" H5 17 | -------------------------------------------------------------------------------- /eda/switch_input/switch_input.gprj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 5 6 | gw1n4b-011 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | set_option -use_sspi_as_gpio 1 15 | set_option -use_done_as_gpio 1 16 | set_option -use_ready_as_gpio 1 17 | 18 | add_file -type verilog [file normalize ${RTL_DIR}/../external/picorv32/picorv32.v] 19 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 20 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 21 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 22 | 23 | run all -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/test_loopback/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean compile test view 2 | 3 | MODULES := ../crc_mac.sv \ 4 | ../append_crc.sv \ 5 | ../remove_crc.sv \ 6 | ../mii_mac_rx.sv \ 7 | ../mii_mac_tx.sv \ 8 | ../../mii_axis/axis_to_mii.sv \ 9 | ../../mii_axis/prepend_preamble.sv \ 10 | ../../mii_axis/mii_to_axis.sv \ 11 | ../../util/simple_fifo.v \ 12 | ../../util/axis_if.sv 13 | 14 | all: test 15 | 16 | clean: 17 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 18 | -@$(RM) -rf xsim.dir .Xil 19 | 20 | xelab.pb: tb.sv $(MODULES) 21 | xvlog -work work --sv tb.sv $(MODULES) 22 | xelab -L work tb -debug all 23 | 24 | compile: xelab.pb 25 | 26 | test: xelab.pb 27 | xsim tb --onfinish quit --tclbatch ./test.tcl --wdb test.wdb | tee test.log 28 | if grep Error test.log; then echo "Error."; exit 1; fi 29 | 30 | view: test.wdb 31 | vivado ./test.wdb& 32 | -------------------------------------------------------------------------------- /eda/cpu_stopwatch/src/sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | MEMORY 5 | { 6 | imem(rx) : ORIGIN = 0x08000000, LENGTH = 2048 7 | dmem(rwx) : ORIGIN = 0x20000000, LENGTH = 2048 8 | } 9 | 10 | SECTIONS 11 | { 12 | .isr_vector : { 13 | . = ALIGN(4); 14 | KEEP(*(.isr_vector)) 15 | . = ALIGN(4); 16 | } >imem 17 | .text : { 18 | . = ALIGN(4); 19 | *(.text) 20 | . = ALIGN(4); 21 | } >imem 22 | .rodata : { 23 | . = ALIGN(4); 24 | *(.rodata) 25 | . = ALIGN(4); 26 | } >imem 27 | .data : { 28 | . = ALIGN(4); 29 | *(.data) 30 | . = ALIGN(4); 31 | } >dmem AT>imem 32 | .bss : { 33 | *(.bss) 34 | . = ALIGN(4); 35 | } >dmem 36 | PROVIDE(stack_bottom = .); 37 | PROVIDE(_end = .); 38 | PROVIDE(end = .); 39 | PROVIDE(ramend = ORIGIN(dmem) + LENGTH(dmem)); 40 | } 41 | -------------------------------------------------------------------------------- /eda/multi_segment_led/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | set_option -use_sspi_as_gpio 1 15 | set_option -use_done_as_gpio 1 16 | set_option -use_ready_as_gpio 1 17 | 18 | add_file -type verilog [file normalize ${RTL_DIR}/chisel/segment_led/multi_segment_led.v] 19 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 20 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 21 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 22 | 23 | run all -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | MEMORY 5 | { 6 | imem(rx) : ORIGIN = 0x08000000, LENGTH = 1024 7 | dmem(rwx) : ORIGIN = 0x20000000, LENGTH = 512 8 | } 9 | 10 | SECTIONS 11 | { 12 | .isr_vector : { 13 | . = ALIGN(4); 14 | KEEP(*(.isr_vector)) 15 | . = ALIGN(4); 16 | } >imem 17 | .text : { 18 | . = ALIGN(4); 19 | *(.text) 20 | . = ALIGN(4); 21 | } >imem 22 | .rodata : { 23 | . = ALIGN(4); 24 | *(.rodata) 25 | . = ALIGN(4); 26 | } >imem 27 | .data : { 28 | . = ALIGN(4); 29 | *(.data) 30 | . = ALIGN(4); 31 | } >dmem AT>imem 32 | .bss : { 33 | *(.bss) 34 | . = ALIGN(4); 35 | } >dmem 36 | PROVIDE(stack_bottom = .); 37 | PROVIDE(_end = .); 38 | PROVIDE(end = .); 39 | PROVIDE(ramend = ORIGIN(dmem) + LENGTH(dmem)); 40 | } 41 | -------------------------------------------------------------------------------- /eda/switch_input/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/bounce_detector.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 18 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 19 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 20 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 21 | 22 | run all -------------------------------------------------------------------------------- /eda/segment_led/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 18 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 19 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 20 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 21 | 22 | run all -------------------------------------------------------------------------------- /eda/cpu_stopwatch/src/sw/bootrom.hex: -------------------------------------------------------------------------------- 1 | 0080006f 2 | 0040006f 3 | 18000117 4 | 7f810113 5 | 004000ef 6 | 300007b7 7 | 0307ae03 8 | 00100713 9 | 02100e93 10 | 00171693 11 | 00e7a223 12 | 00775713 13 | 00177713 14 | 00e6e733 15 | c8002ff3 16 | c0002573 17 | c80026f3 18 | fedf9ae3 19 | 01055693 20 | 01455613 21 | 01855593 22 | 00f6f693 23 | 00f67613 24 | 00f5f593 25 | 01c55313 26 | 0206e693 27 | 02066613 28 | 0205e593 29 | 02036313 30 | c80028f3 31 | c0002873 32 | c8002f73 33 | ffe89ae3 34 | 40a80f33 35 | 01e83833 36 | 41f888b3 37 | 00878293 38 | 01089463 39 | 05cf6063 40 | 0002a683 41 | 0016f693 42 | f80680e3 43 | 0347a683 44 | 0026f693 45 | fe068ce3 46 | 0387a683 47 | 0ff6f613 48 | f7d604e3 49 | 0347a603 50 | 00167613 51 | fe060ce3 52 | 0ff6f693 53 | 02d7ac23 54 | fd5ff06f 55 | 0087a803 56 | 00787813 57 | 0107a823 58 | 02d7a623 59 | 02c7a423 60 | 02b7a223 61 | 0267a023 62 | f81ff06f 63 | -------------------------------------------------------------------------------- /xls/filter/Makefile: -------------------------------------------------------------------------------- 1 | TOP_ENTITY := moving_average 2 | TOP := moving_average 3 | 4 | TEST_MODULE := test_$(TOP) 5 | TEST_TOP := $(TEST_MODULE) 6 | TEST_OPTS := -g2012 7 | 8 | .PHONY: run 9 | run: 10 | interpreter_main $(TOP).dslx 11 | 12 | .PHONY: gen 13 | gen: $(TOP).ir $(TOP).opt.ir $(TOP).v 14 | 15 | %.ir: %.dslx 16 | ir_converter_main --top $(TOP_ENTITY) $< > $@ 17 | 18 | %.opt.ir: %.ir 19 | opt_main $< > $@ 20 | 21 | %.v: %.opt.ir 22 | codegen_main --use_system_verilog=false --module_name=$(TOP_ENTITY) --reset reset --generator=pipeline --delay_model=unit --clock_period_ps=10000 $< > $@ 23 | 24 | .PHONY: test 25 | test: $(TEST_MODULE).vcd 26 | 27 | .PHONY: show 28 | show: $(TEST_MODULE).vcd 29 | gtkwave $< & 30 | 31 | 32 | $(TEST_MODULE).vcd: $(TOP).v $(TEST_MODULE).sv 33 | iverilog $(TEST_OPTS) -s $(TEST_TOP) $^ -o $@ $(SRCS) 34 | ./$(patsubst .vcd,.elf,$@) 35 | 36 | .PHONY: clean 37 | clean: 38 | -@$(RM) *.v *.ir *.elf -------------------------------------------------------------------------------- /chisel/src/main/scala/axi/axi4_channel_combine.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | package axi 9 | 10 | import chisel3._ 11 | import chisel3.util._ 12 | import _root_.util._ 13 | 14 | object AXIChannelCombine { 15 | def apply(reader: AXI4IO, writer: AXI4IO ): AXI4IO = { 16 | val combinedParams = AXI4Params(reader.params.addressBits, reader.params.dataBits, AXI4ReadWrite, reader.params.maxBurstLength) 17 | val combined = Wire(AXI4IO(combinedParams)) 18 | 19 | combined.ar.get <> reader.ar.get 20 | combined.r.get <> reader.r.get 21 | combined.aw.get <> writer.aw.get 22 | combined.w.get <> writer.w.get 23 | combined.b.get <> writer.b.get 24 | 25 | combined 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /chisel/src/main/scala/system/sdramtestsystem.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package system 8 | 9 | import chisel3._ 10 | import chisel3.util._ 11 | import sdram._ 12 | import axi._ 13 | import java.io.FileInputStream 14 | import scala.collection.mutable 15 | 16 | class SDRAMTestSystem() extends Module { 17 | val params = SDRAMBridgeParams(20, 4, 8) 18 | val axi4Params = AXI4Params(params.addressBits, params.dataBits, AXI4ReadWrite, Some(params.maxBurstLength)) 19 | val io = IO(new Bundle { 20 | val axi = Flipped(new AXI4IO(axi4Params)) 21 | }) 22 | 23 | val dut = Module(new SDRCBridge(params)) 24 | val mem = Module(new SimSDRC(params, 1024*1024)) 25 | 26 | dut.io.sdrc <> mem.io.sdrc 27 | io.axi <> dut.io.axi 28 | } 29 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/sw/bootrom.hex: -------------------------------------------------------------------------------- 1 | 05c0006f 2 | 0580006f 3 | 200007b7 4 | 20000737 5 | 00078793 6 | 00070713 7 | 02e7e263 8 | 200007b7 9 | 80000737 10 | 200006b7 11 | 00078793 12 | 10470713 13 | 00068693 14 | 00d7ea63 15 | 00008067 16 | 0007a023 17 | 00478793 18 | fd5ff06f 19 | 00072603 20 | 00478793 21 | 00470713 22 | fec7ae23 23 | fddff06f 24 | a0000117 25 | 7a410113 26 | ffc10113 27 | fa1ff0ef 28 | 004000ef 29 | 300007b7 30 | 80000537 31 | 0047a303 32 | 00000613 33 | 00100793 34 | 300005b7 35 | 0f450513 36 | 00361713 37 | 00e50733 38 | 00072683 39 | 00472703 40 | 00f5a423 41 | 00d5a623 42 | 00e5a823 43 | 00164613 44 | c80028f3 45 | c0002e73 46 | c8002773 47 | fee89ae3 48 | c80026f3 49 | c0002773 50 | c8002873 51 | ff069ae3 52 | 41c70833 53 | 01073733 54 | 411686b3 55 | 00e69463 56 | fe6860e3 57 | 00179713 58 | 0077d793 59 | 0017f793 60 | 00f767b3 61 | f9dff06f 62 | 70808070 63 | 070b0906 64 | 070b0906 65 | 70808070 66 | -------------------------------------------------------------------------------- /eda/stp_emu/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/stp_emu/stp_emu.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 18 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 19 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 20 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 21 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 22 | 23 | run all -------------------------------------------------------------------------------- /chisel/src/main/scala/util/flushable.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | import chisel3._ 10 | import chisel3.internal.firrtl.Width 11 | 12 | class Flushable[T <: Data](gen: T) extends Bundle { 13 | val data = gen.cloneType.asInstanceOf[T] 14 | val last = Bool() 15 | } 16 | 17 | object Flushable { 18 | def apply[T <: Data](gen: T): Flushable[T] = { 19 | new Flushable(gen) 20 | } 21 | def apply(width: Width): Flushable[UInt] = { 22 | new Flushable(UInt(width)) 23 | } 24 | def apply(multibyte: MultiByteSymbol): Flushable[UInt] = { 25 | val flushable = Wire(new Flushable(UInt(multibyte.numberOfBits.W))) 26 | flushable.data := multibyte.data 27 | flushable.last := multibyte.last 28 | flushable 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /chisel/src/main/scala/util/irrevocable_randomizer.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | import chisel3._ 10 | import chisel3.util._ 11 | 12 | class IrrevocableRandomizer[T <: Data](gen: T) extends Module { 13 | val io = IO(new Bundle{ 14 | val in = Flipped(Irrevocable(gen)) 15 | val out = Irrevocable(gen) 16 | }) 17 | 18 | val block = random.LFSR(16).xorR() 19 | io.out.valid := io.in.valid && !block 20 | io.in.ready := io.out.ready && !block 21 | io.out.bits := io.in.bits 22 | } 23 | 24 | object IrrevocableRandomizer { 25 | def apply[T <: Data](in: IrrevocableIO[T]): IrrevocableIO[T] = { 26 | val checker = Module(new IrrevocableRandomizer(chiselTypeOf(in.bits))) 27 | checker.io.in <> in 28 | checker.io.out 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/sw/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | CC = riscv64-unknown-elf-gcc 4 | OBJDUMP = riscv64-unknown-elf-objdump 5 | OBJCOPY = riscv64-unknown-elf-objcopy 6 | CFLAGS = -mabi=ilp32 -march=rv32i -Os -g 7 | LDFLAGS = -Wl,-Tlink.ld -nostartfiles 8 | 9 | OBJS := bootrom.o 10 | 11 | BOOTROM_TARGETS := bootrom.hex bootrom_0.hex bootrom_1.hex bootrom_2.hex bootrom_3.hex 12 | 13 | all: bootrom.bin $(BOOTROM_TARGETS) bootrom.dump 14 | 15 | bootrom.elf: $(OBJS) link.ld 16 | $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJS) 17 | 18 | %.o: %.c 19 | $(CC) -c -o $@ $(CFLAGS) $< 20 | 21 | %.bin: %.elf 22 | $(OBJCOPY) -O binary $< $@ 23 | 24 | %.hex: %.bin 25 | od -An -tx4 -w4 -v $< > $@ 26 | %.dump: %.elf 27 | $(OBJDUMP) -dSC $< > $@ 28 | 29 | %_0.hex: %.hex 30 | awk '{print substr($$1,7,2)}' $< > $@ 31 | %_1.hex: %.hex 32 | awk '{print substr($$1,5,2)}' $< > $@ 33 | %_2.hex: %.hex 34 | awk '{print substr($$1,3,2)}' $< > $@ 35 | %_3.hex: %.hex 36 | awk '{print substr($$1,1,2)}' $< > $@ 37 | 38 | 39 | clean: 40 | -@$(RM) *.o *.elf *.bin *.hex -------------------------------------------------------------------------------- /eda/multi_segment_led/src/tangnano20k/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file top.sv 3 | * @brief Top module for PicoRV32 matrix LED example 4 | */ 5 | // Copyright 2023 Eisuke Mochizuki 6 | // Kenta IDA 7 | // Distributed under the Boost Software License, Version 1.0. 8 | // (See accompanying file LICENSE_1_0.txt or copy at 9 | // http://www.boost.org/LICENSE_1_0.txt) 10 | `default_nettype none 11 | 12 | module top ( 13 | input wire clock, 14 | output logic com_ser, 15 | output logic com_rclk, 16 | output logic com_srclk, 17 | output logic com_oe, 18 | output logic seg_ser, 19 | output logic seg_rclk, 20 | output logic seg_srclk, 21 | output logic seg_oe 22 | ); 23 | 24 | // リセット回路 (16サイクル) 25 | logic reset; 26 | logic [15:0] reset_reg = '1; 27 | assign reset = reset_reg[0]; 28 | always_ff @(posedge clock) begin 29 | reset_reg <= {1'b0, reset_reg[15:1]}; 30 | end 31 | 32 | MultiSegmentLed multi_segment_led_inst ( 33 | .resetn(!reset), 34 | .* 35 | ); 36 | endmodule 37 | `default_nettype wire -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | MEMORY 5 | { 6 | mem(rx) : ORIGIN = 0x00000000, LENGTH = 8192 7 | } 8 | 9 | SECTIONS 10 | { 11 | .isr_vector : { 12 | . = ALIGN(4); 13 | KEEP(*(.isr_vector)) 14 | . = ALIGN(4); 15 | } >mem 16 | .text : { 17 | . = ALIGN(4); 18 | *(.text) 19 | . = ALIGN(4); 20 | } >mem 21 | .rodata : { 22 | . = ALIGN(4); 23 | *(.rodata) 24 | . = ALIGN(4); 25 | } >mem 26 | .data : { 27 | PROVIDE(_data_start = .); 28 | PROVIDE(_data_rom_start = LOADADDR(.data)); 29 | . = ALIGN(4); 30 | *(.sdata .sdata.* .data .data.*) 31 | . = ALIGN(4); 32 | PROVIDE(_data_end = .); 33 | } >mem 34 | .bss : { 35 | PROVIDE(_bss_start = .); 36 | *(.sbss .sbss.* .bss .bss.*) 37 | . = ALIGN(4); 38 | PROVIDE(_bss_end = .); 39 | } >mem 40 | PROVIDE(stack_bottom = .); 41 | PROVIDE(_end = .); 42 | PROVIDE(end = .); 43 | PROVIDE(stack_top = ORIGIN(mem) + LENGTH(mem) - 4); 44 | } 45 | -------------------------------------------------------------------------------- /eda/ws2812/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 18 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 19 | add_file -type verilog [file normalize ${RTL_DIR}/ws2812/ws2812b.sv] 20 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 21 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 22 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 23 | 24 | run all -------------------------------------------------------------------------------- /rtl/blink/blink_all.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file blink_all.sv 3 | * @brief simple LED blink example. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module blink #( 12 | parameter longint CLOCK_HZ = 24_000_000, 13 | parameter NUMBER_OF_LEDS = 8 14 | ) ( 15 | input logic clock, 16 | output logic [NUMBER_OF_LEDS-1:0] led_out 17 | ); 18 | 19 | localparam longint COUNT_HALF = CLOCK_HZ/2; 20 | localparam int COUNTER_BITS = $clog2(COUNT_HALF); 21 | 22 | logic [COUNTER_BITS-1:0] counter = 0; 23 | logic led_out_internal = 0; 24 | 25 | always_comb begin 26 | led_out = {NUMBER_OF_LEDS {led_out_internal}}; 27 | end 28 | 29 | always_ff @(posedge clock) begin 30 | if( counter < COUNT_HALF - 1 ) begin 31 | counter <= counter + 1; 32 | end 33 | else begin 34 | counter <= 0; 35 | led_out_internal ^= 1; 36 | end 37 | end 38 | 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /eda/ethernet_audio/src/tangprimer20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | 11 | set_false_path -from [get_pins {ethernet_audio_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_audio_system_inst/txAsyncFifo/wIndexGrayReg*/D}] 12 | set_false_path -from [get_pins {ethernet_audio_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_audio_system_inst/rxAsyncFifo/wIndexGrayReg*/D}] 13 | set_false_path -from [get_pins {ethernet_audio_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_audio_system_inst/txAsyncFifo/rIndexGrayReg*/D}] 14 | set_false_path -from [get_pins {ethernet_audio_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_audio_system_inst/rxAsyncFifo/rIndexGrayReg*/D}] -------------------------------------------------------------------------------- /eda/ethernet_video/src/tangprimer20k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2022 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | 11 | set_false_path -from [get_pins {ethernet_video_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_video_system_inst/txAsyncFifo/wIndexGrayReg*/D}] 12 | set_false_path -from [get_pins {ethernet_video_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_video_system_inst/rxAsyncFifo/wIndexGrayReg*/D}] 13 | set_false_path -from [get_pins {ethernet_video_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_video_system_inst/txAsyncFifo/rIndexGrayReg*/D}] 14 | set_false_path -from [get_pins {ethernet_video_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_video_system_inst/rxAsyncFifo/rIndexGrayReg*/D}] -------------------------------------------------------------------------------- /eda/i2c_slave/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 18 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 19 | add_file -type verilog [file normalize ${RTL_DIR}/i2c_slave/i2c_slave.sv] 20 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 21 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 22 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 23 | 24 | run all -------------------------------------------------------------------------------- /eda/stop_watch/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 18 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/bounce_detector.sv] 19 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 20 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 21 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 22 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 23 | 24 | run all -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := cpu_riscv_chisel_book 2 | 3 | CHISEL_TEMPLATE_DIR ?= ../../external/riscv-chisel-book/chisel-template 4 | RTL_DIR ?= $(abspath ../../rtl) 5 | ROOT_DIR ?= $(abspath ../..) 6 | 7 | ifeq ($(TARGET),comprocboard_9k) 8 | RISCV_ELABORATE := system.ElaborateCpuRiscvChiselBookMatrix_TangNano9K 9 | RISCV_ELABORATE_OUTPUT_DIR := $(RTL_DIR)/cpu_riscv_chisel_book_matrix/tangnano9k 10 | endif 11 | 12 | RISCV_CORE_SRC := $(RISCV_ELABORATE_OUTPUT_DIR)/riscv.v 13 | PROJECT_ADDITIONAL_ARGS := $(abspath $(RISCV_CORE_SRC)) 14 | PROJECT_ADDITIONAL_CLEAN := $(RISCV_CORE_SRC) 15 | 16 | SRCS := $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) $(RISCV_CORE_SRC) project.tcl src/sw/bootrom.hex 17 | 18 | include ../build_gowin.mk 19 | 20 | $(CHISEL_TEMPLATE_DIR): 21 | git submodule update --init --recursive 22 | 23 | $(RISCV_CORE_SRC): $(CHISEL_TEMPLATE_DIR) 24 | cd $(ROOT_DIR) && sbt "project fpga_samples; runMain $(RISCV_ELABORATE)" 25 | 26 | src/sw/bootrom.hex: src/sw/bootrom.c src/sw/link.ld src/sw/Makefile 27 | cd src/sw; make -------------------------------------------------------------------------------- /eda/turn_table/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | set_option -top_module top 15 | # set_option -place_option 1 16 | # set_option -route_option 2 17 | 18 | if {${TARGET} == "tangnano9k_pmod"} { 19 | set_option -use_sspi_as_gpio 1 20 | } 21 | 22 | if {${TARGET} == "tangprimer20k"} { 23 | set_option -use_sspi_as_gpio 1 24 | set_option -use_done_as_gpio 1 25 | set_option -use_ready_as_gpio 1 26 | } 27 | 28 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 29 | add_file -type verilog [file normalize ${SRC_DIR}/reset_seq.sv] 30 | 31 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 32 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 33 | 34 | run all -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | MEMORY 5 | { 6 | imem(rx) : ORIGIN = 0x80000000, LENGTH = 2048 7 | dmem(rwx) : ORIGIN = 0x20000000, LENGTH = 2048 8 | } 9 | 10 | SECTIONS 11 | { 12 | .isr_vector : { 13 | . = ALIGN(4); 14 | KEEP(*(.isr_vector)) 15 | . = ALIGN(4); 16 | } >imem 17 | .text : { 18 | . = ALIGN(4); 19 | *(.text) 20 | . = ALIGN(4); 21 | } >imem 22 | .rodata : { 23 | . = ALIGN(4); 24 | *(.rodata) 25 | . = ALIGN(4); 26 | } >imem 27 | .data : { 28 | PROVIDE(_data_start = .); 29 | PROVIDE(_data_rom_start = LOADADDR(.data)); 30 | . = ALIGN(4); 31 | *(.sdata .sdata.* .data .data.*) 32 | . = ALIGN(4); 33 | PROVIDE(_data_end = .); 34 | } >dmem AT>imem 35 | .bss : { 36 | PROVIDE(_bss_start = .); 37 | *(.sbss .sbss.* .bss .bss.*) 38 | . = ALIGN(4); 39 | PROVIDE(_bss_end = .); 40 | } >dmem 41 | PROVIDE(stack_bottom = .); 42 | PROVIDE(_end = .); 43 | PROVIDE(end = .); 44 | PROVIDE(ramend = ORIGIN(dmem) + LENGTH(dmem)); 45 | } 46 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | MEMORY 5 | { 6 | imem(rx) : ORIGIN = 0x08000000, LENGTH = 2048 7 | dmem(rwx) : ORIGIN = 0x20000000, LENGTH = 512 8 | } 9 | 10 | SECTIONS 11 | { 12 | .isr_vector : { 13 | . = ALIGN(4); 14 | KEEP(*(.isr_vector)) 15 | . = ALIGN(4); 16 | } >imem 17 | .text : { 18 | . = ALIGN(4); 19 | *(.text) 20 | . = ALIGN(4); 21 | } >imem 22 | .rodata : { 23 | . = ALIGN(4); 24 | *(.rodata) 25 | . = ALIGN(4); 26 | } >imem 27 | .data : { 28 | PROVIDE(_data_start = .); 29 | PROVIDE(_data_rom_start = LOADADDR(.data)); 30 | . = ALIGN(4); 31 | *(.sdata .sdata.* .data .data.*) 32 | . = ALIGN(4); 33 | PROVIDE(_data_end = .); 34 | } >dmem AT>imem 35 | .bss : { 36 | PROVIDE(_bss_start = .); 37 | *(.sbss .sbss.* .bss .bss.*) 38 | . = ALIGN(4); 39 | PROVIDE(_bss_end = .); 40 | } >dmem 41 | PROVIDE(stack_bottom = .); 42 | PROVIDE(_end = .); 43 | PROVIDE(end = .); 44 | PROVIDE(ramend = ORIGIN(dmem) + LENGTH(dmem)); 45 | } 46 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangnano9k_pmod/pins.cst.template: -------------------------------------------------------------------------------- 1 | IO_LOC "clk" 52; 2 | IO_PORT "clk" IO_TYPE=LVCMOS33; 3 | 4 | IO_PORT "anode[0]" IO_TYPE=LVCMOS33; 5 | IO_PORT "anode[1]" IO_TYPE=LVCMOS33; 6 | IO_PORT "anode[2]" IO_TYPE=LVCMOS33; 7 | IO_PORT "anode[3]" IO_TYPE=LVCMOS33; 8 | IO_PORT "anode[4]" IO_TYPE=LVCMOS33; 9 | IO_PORT "anode[5]" IO_TYPE=LVCMOS33; 10 | IO_PORT "anode[6]" IO_TYPE=LVCMOS33; 11 | IO_PORT "anode[7]" IO_TYPE=LVCMOS33; 12 | IO_PORT "cathode[0]" IO_TYPE=LVCMOS33; 13 | IO_PORT "cathode[1]" IO_TYPE=LVCMOS33; 14 | IO_PORT "cathode[2]" IO_TYPE=LVCMOS33; 15 | IO_PORT "cathode[3]" IO_TYPE=LVCMOS33; 16 | IO_PORT "cathode[4]" IO_TYPE=LVCMOS33; 17 | IO_PORT "cathode[5]" IO_TYPE=LVCMOS33; 18 | IO_PORT "cathode[6]" IO_TYPE=LVCMOS33; 19 | IO_PORT "cathode[7]" IO_TYPE=LVCMOS33; 20 | 21 | IO_LOC "led[0]" 10; 22 | IO_LOC "led[1]" 11; 23 | IO_LOC "led[2]" 13; 24 | IO_LOC "led[3]" 14; 25 | IO_LOC "led[4]" 15; 26 | IO_LOC "led[5]" 16; 27 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 28 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 29 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 30 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 31 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 32 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 33 | -------------------------------------------------------------------------------- /rtl/chisel/lifegame_fram/lifegame_fram.anno.json: -------------------------------------------------------------------------------- 1 | [ 2 | { 3 | "class":"logger.LogLevelAnnotation", 4 | "globalLogLevel":{ 5 | 6 | } 7 | }, 8 | { 9 | "class":"firrtl.stage.phases.DriverCompatibility$TopNameAnnotation", 10 | "topName":"lifegame_fram" 11 | }, 12 | { 13 | "class":"firrtl.EmitCircuitAnnotation", 14 | "emitter":"firrtl.VerilogEmitter" 15 | }, 16 | { 17 | "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", 18 | "typeName":"system.LifeGameFram$State$1", 19 | "definition":{ 20 | "ReadBoard":5, 21 | "IssueRead":4, 22 | "Error":2, 23 | "ReadId":1, 24 | "IssueWrite":10, 25 | "WriteBoard":11, 26 | "WriteEnable":9, 27 | "UpdateBoard":7, 28 | "Idle":3, 29 | "InitializeBoard":6, 30 | "CheckStall":8, 31 | "Reset":0 32 | } 33 | }, 34 | { 35 | "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", 36 | "target":"LifeGameFram.LifeGameFram.state", 37 | "enumTypeName":"system.LifeGameFram$State$1" 38 | }, 39 | { 40 | "class":"firrtl.transforms.BlackBoxTargetDirAnno", 41 | "targetDir":"rtl/chisel/lifegame_fram" 42 | } 43 | ] -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangprimer20k/pins.cst.template: -------------------------------------------------------------------------------- 1 | IO_LOC "clk" H11; 2 | IO_PORT "clk" IO_TYPE=LVCMOS33; 3 | 4 | IO_PORT "anode[0]" IO_TYPE=LVCMOS33; 5 | IO_PORT "anode[1]" IO_TYPE=LVCMOS33; 6 | IO_PORT "anode[2]" IO_TYPE=LVCMOS33; 7 | IO_PORT "anode[3]" IO_TYPE=LVCMOS33; 8 | IO_PORT "anode[4]" IO_TYPE=LVCMOS33; 9 | IO_PORT "anode[5]" IO_TYPE=LVCMOS33; 10 | IO_PORT "anode[6]" IO_TYPE=LVCMOS33; 11 | IO_PORT "anode[7]" IO_TYPE=LVCMOS33; 12 | IO_PORT "cathode[0]" IO_TYPE=LVCMOS33; 13 | IO_PORT "cathode[1]" IO_TYPE=LVCMOS33; 14 | IO_PORT "cathode[2]" IO_TYPE=LVCMOS33; 15 | IO_PORT "cathode[3]" IO_TYPE=LVCMOS33; 16 | IO_PORT "cathode[4]" IO_TYPE=LVCMOS33; 17 | IO_PORT "cathode[5]" IO_TYPE=LVCMOS33; 18 | IO_PORT "cathode[6]" IO_TYPE=LVCMOS33; 19 | IO_PORT "cathode[7]" IO_TYPE=LVCMOS33; 20 | 21 | IO_LOC "led[0]" C13; 22 | IO_LOC "led[1]" A13; 23 | IO_LOC "led[2]" N16; 24 | IO_LOC "led[3]" N14; 25 | IO_LOC "led[4]" L14; 26 | IO_LOC "led[5]" L16; 27 | 28 | IO_PORT "led[0]" IO_TYPE=LVCMOS33; 29 | IO_PORT "led[1]" IO_TYPE=LVCMOS33; 30 | IO_PORT "led[2]" IO_TYPE=LVCMOS33; 31 | IO_PORT "led[3]" IO_TYPE=LVCMOS33; 32 | IO_PORT "led[4]" IO_TYPE=LVCMOS33; 33 | IO_PORT "led[5]" IO_TYPE=LVCMOS33; 34 | 35 | // PMOD pin locations 36 | -------------------------------------------------------------------------------- /eda/turn_table/src/tangnano9k_pmod/pins.cst.template: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 52; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "button_s0" 86; 5 | IO_LOC "button_s1" 85; 6 | IO_LOC "button_s2" 84; 7 | IO_LOC "button_s3" 83; 8 | IO_LOC "button_s4" 82; 9 | IO_PORT "button_s0" IO_TYPE=LVCMOS18; 10 | IO_PORT "button_s1" IO_TYPE=LVCMOS18; 11 | IO_PORT "button_s2" IO_TYPE=LVCMOS18; 12 | IO_PORT "button_s3" IO_TYPE=LVCMOS18; 13 | IO_PORT "button_s4" IO_TYPE=LVCMOS18; 14 | 15 | IO_LOC "led[0]" 10; 16 | IO_LOC "led[1]" 11; 17 | IO_LOC "led[2]" 13; 18 | IO_LOC "led[3]" 14; 19 | IO_LOC "led[4]" 15; 20 | IO_LOC "led[5]" 16; 21 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 22 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 23 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 24 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 25 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 26 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 27 | 28 | IO_PORT "stepper_m1p[0]" IO_TYPE=LVCMOS33; 29 | IO_PORT "stepper_m1p[1]" IO_TYPE=LVCMOS33; 30 | IO_PORT "stepper_m1p[2]" IO_TYPE=LVCMOS33; 31 | IO_PORT "stepper_m1p[3]" IO_TYPE=LVCMOS33; 32 | IO_PORT "stepper_m2p[0]" IO_TYPE=LVCMOS33; 33 | IO_PORT "stepper_m2p[1]" IO_TYPE=LVCMOS33; 34 | IO_PORT "stepper_m2p[2]" IO_TYPE=LVCMOS33; 35 | IO_PORT "stepper_m2p[3]" IO_TYPE=LVCMOS33; 36 | -------------------------------------------------------------------------------- /chisel/src/main/scala/system/sample_uart.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package system 8 | 9 | import chisel3._ 10 | import chisel3.util._ 11 | import chisel3.experimental.chiselName 12 | import uart._ 13 | import chisel3.stage.ChiselStage 14 | 15 | @chiselName 16 | class UartSystem() extends RawModule { 17 | val clock = IO(Input(Clock())) 18 | val resetn = IO(Input(Bool())) 19 | val tx = IO(Output(Bool())) 20 | val rx = IO(Input(Bool())) 21 | 22 | withClockAndReset(clock, !resetn) { 23 | val clockFreq = 24000000 // 24MHz 24 | val baudRate = 115200 25 | val uartRx = Module(new UartRx(8, clockFreq / baudRate, 3)) 26 | val uartTx = Module(new UartTx(8, clockFreq / baudRate)) 27 | 28 | uartRx.io.out <> uartTx.io.in 29 | 30 | tx <> uartTx.io.tx 31 | rx <> uartRx.io.rx 32 | } 33 | } 34 | 35 | 36 | object Elaborate extends App { 37 | (new ChiselStage).emitVerilog(new UartSystem, Array( 38 | "-o", "uart_system.v", 39 | "--target-dir", "rtl/chisel/uart", 40 | )) 41 | } 42 | -------------------------------------------------------------------------------- /eda/dvi_out_tpg/README.md: -------------------------------------------------------------------------------- 1 | # HDMI出力有効化版デザイン 2 | 3 | ## 概要 4 | 5 | Tang Nano 9Kに搭載されているHDMIコネクタからGOWIN DVI TX IPを使ってHDMI出力を行えるように変更したデザイン。 6 | 7 | HDMIコネクタで使用している信号はComProc CPU Boardのボード上で使用している信号と一部共用されているので、ボードの機能が一部使用不可となっている。影響をうけるボードの機能は次の通り。 8 | 9 | * 8x8マトリクスLED 10 | * 7+1セグメントLED 11 | * キャラクタ液晶 12 | 13 | 特にキャラクタ液晶はHDMIコネクタにケーブルを挿した状態だと物理的に干渉するので、ボードから取り外す必要がある。 14 | 15 | ## 合成の準備 16 | 17 | ### Tang Nano 9K向け 18 | 19 | いくつかのGOWIN EDA付属のIPを使用している。現状GOWINのIPはスクリプトからIPのHDLファイルを再生成することができないので、IP定義ファイルからの再生成をGUIを操作して手動で行う必要がある。 20 | 21 | `src/comprocboard_9k_ip` 以下にある3つのIPを復元する。 22 | 23 | * dvi_tx 24 | * gowin_clkdiv 25 | * gowin_rpll 26 | 27 | IPの復元はGOWIN EDAのGUI上の `Tools -> IP Core Generator` メニューから IP Core Generatorを開き、画面上部のボタンを押して各IPのディレクトリ下にある *.ipc ファイルを選択する。 28 | その後、値を変更せずにOKを押すと、対象のIPのHDLファイルが生成される。 29 | 30 | ![IPCファイルの読み込み](./regenerate_ip.drawio.svg) 31 | 32 | ### Tang Primer 25K向け 33 | 34 | Tang Primer 25K向けのデザインを試すには、Tang Primer 25K本体以外にSipeedのPmod DVIモジュールが必要となる。Pmod DVIモジュールは DE0 互換コネクタを手前に持ってきた状態 (Pmodコネクタを奥側にした状態) で一番右側のコネクタ (F5, G5のピンが含まれるコネクタ) に接続する。 35 | 36 | Tang Nano 9K向けと同様に、`src/ip` 以下にある、 `gowin_pll` と `gowin_pll_27` を復元する。 37 | 38 | その後、以下のコマンドでビットストリームを生成する。 39 | 40 | ``` 41 | $ make TARGET=tangprimer25k 42 | ``` 43 | -------------------------------------------------------------------------------- /eda/multi_segment_led/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := multi_segment_led 2 | SRCS := src/$(TARGET)/pins.cst $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl 3 | PMOD_PORT_OFFSET ?= 0 4 | PMOD_TARGETS := tangnano9k_pmod tangprimer20k tangnano20k 5 | 6 | # Check if the target contains PMOD ports 7 | ifneq (,$(filter $(TARGET),$(PMOD_TARGETS))) 8 | USE_PMOD := 1 9 | PROJECT_ADDITIONAL_CLEAN += src/$(TARGET)/pins.cst 10 | endif 11 | 12 | include ../build_gowin.mk 13 | 14 | src/sw/bootrom.hex: src/sw/bootrom.c src/sw/link.ld src/sw/Makefile 15 | cd src/sw; make 16 | 17 | 18 | ifeq ($(USE_PMOD),1) 19 | # Generate CST file from template. 20 | src/$(TARGET)/pins.cst: src/$(TARGET)/pins.cst.template $(TARGET_DEF_DIR)/pmod_ports.csv $(MOD_DIR)/pmod_7segx6_single/pmod_pins.csv $(MAPPMOD) 21 | echo Generating pin definition from Pmod pin map. 22 | echo // This file is automatically generated by build script. DO NOT EDIT THIS FILE. > $@ 23 | cat src/$(TARGET)/pins.cst.template >> $@ 24 | $(MAPPMOD) --pmod-port-def $(TARGET_DEF_DIR)/pmod_ports.csv --pmod $(MOD_DIR)/pmod_7segx6_single/pmod_pins.csv --port-offset $(PMOD_PORT_OFFSET) --direction right-to-left >> $@ 25 | else 26 | src/$(TARGET)/pins.cst: 27 | echo Use pre-generated pin definition. 28 | endif -------------------------------------------------------------------------------- /eda/turn_table/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := ethernet_video 2 | 3 | TARGET ?= tangprimer20k 4 | ROOT_DIR ?= $(abspath ../..) 5 | RTL_DIR ?= $(ROOT_DIR)/rtl 6 | 7 | SRCS := src/$(TARGET)/pins.cst $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl 8 | 9 | PMOD_PORT_OFFSET ?= 0 10 | PMOD_TARGETS := tangnano9k_pmod tangprimer20k 11 | 12 | # Check if the target contains PMOD ports 13 | USE_PMOD := 0 14 | ifneq (,$(filter $(TARGET),$(PMOD_TARGETS))) 15 | USE_PMOD := 1 16 | PROJECT_ADDITIONAL_CLEAN += src/$(TARGET)/pins.cst 17 | endif 18 | include ../build_gowin.mk 19 | 20 | PMOD_MODULES += $(MOD_DIR)/pmod_stepper2/pmod_pins.csv 21 | 22 | ifeq ($(USE_PMOD),1) 23 | # Generate CST file from template. 24 | src/$(TARGET)/pins.cst: src/$(TARGET)/pins.cst.template $(TARGET_DEF_DIR)/pmod_ports.csv $(PMOD_MODULES) $(MAPPMOD) 25 | echo Generating pin definition from Pmod pin map. 26 | echo // This file is automatically generated by build script. DO NOT EDIT THIS FILE. > $@ 27 | cat src/$(TARGET)/pins.cst.template >> $@ 28 | $(MAPPMOD) --pmod-port-def $(TARGET_DEF_DIR)/pmod_ports.csv $(addprefix --pmod ,$(PMOD_MODULES)) --port-offset $(PMOD_PORT_OFFSET) --direction right-to-left >> $@ 29 | else 30 | src/$(TARGET)/pins.cst: 31 | echo Use pre-generated pin definition. 32 | endif -------------------------------------------------------------------------------- /util/udpaudiocontrol/src/main.rs: -------------------------------------------------------------------------------- 1 | use std::net::UdpSocket; 2 | 3 | use clap::Parser; 4 | 5 | #[derive(Parser, Debug)] 6 | struct Cli { 7 | #[arg(long = "l0", default_value = "32768")] 8 | volume_left_0: u16, 9 | #[arg(long = "r0", default_value = "32768")] 10 | volume_right_0: u16, 11 | #[arg(long = "l1", default_value = "32768")] 12 | volume_left_1: u16, 13 | #[arg(long = "r1", default_value = "32768")] 14 | volume_right_1: u16, 15 | 16 | #[arg(long, default_value = "192.168.10.1:10001")] 17 | bind_to: String, 18 | 19 | #[arg(long, default_value = "192.168.10.2:10001")] 20 | destination: String, 21 | } 22 | 23 | fn main() -> anyhow::Result<()> { 24 | let args: Cli = Cli::parse(); 25 | let socket = UdpSocket::bind(&args.bind_to)?; 26 | 27 | let mut packet = [0u8; 9]; 28 | packet[1..3].copy_from_slice(&args.volume_left_0.to_le_bytes()); 29 | packet[3..5].copy_from_slice(&args.volume_right_0.to_le_bytes()); 30 | packet[5..7].copy_from_slice(&args.volume_left_1.to_le_bytes()); 31 | packet[7..9].copy_from_slice(&args.volume_right_1.to_le_bytes()); 32 | if let Err(error) = socket.send_to(&packet, &args.destination) { 33 | println!("pattern send error: {}", error); 34 | } 35 | Ok(()) 36 | } 37 | -------------------------------------------------------------------------------- /eda/i2s_master/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | # Additional args 8 | set I2S_MASTER_SRC [lindex $argv 6] 9 | 10 | set_option -output_base_name ${PROJECT_NAME} 11 | set_device -name $DEVICE_FAMILY $DEVICE_PART 12 | 13 | set_option -verilog_std sysv2017 14 | set_option -vhdl_std vhd2008 15 | set_option -print_all_synthesis_warning 1 16 | set_option -top_module top 17 | # set_option -place_option 1 18 | # set_option -route_option 2 19 | 20 | if {${TARGET} == "tangnano9k"} { 21 | set_option -use_sspi_as_gpio 1 22 | } 23 | if {${TARGET} == "tangprimer20k"} { 24 | set_option -use_sspi_as_gpio 1 25 | set_option -use_done_as_gpio 1 26 | set_option -use_ready_as_gpio 1 27 | } 28 | 29 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 30 | add_file -type verilog [file normalize ${SRC_DIR}/reset_seq.sv] 31 | add_file -type verilog [file normalize ${SRC_DIR}/ip/rpll_main/rpll_main.v] 32 | add_file -type verilog [file normalize ${I2S_MASTER_SRC}] 33 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 34 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 35 | 36 | run all -------------------------------------------------------------------------------- /eda/cpu_stopwatch/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | 8 | set_option -output_base_name ${PROJECT_NAME} 9 | set_device -name $DEVICE_FAMILY $DEVICE_PART 10 | 11 | set_option -verilog_std sysv2017 12 | set_option -vhdl_std vhd2008 13 | set_option -print_all_synthesis_warning 1 14 | 15 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 16 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 17 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 18 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 19 | add_file -type verilog [file normalize ${RTL_DIR}/util/simple_fifo.sv] 20 | add_file -type verilog [file normalize ${RTL_DIR}/uart/uart_tx.sv] 21 | add_file -type verilog [file normalize ${RTL_DIR}/uart/uart_rx.sv] 22 | add_file -type verilog [file normalize ${RTL_DIR}/../external/picorv32/picorv32.v] 23 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 24 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 25 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 26 | 27 | run all -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangprimer20k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" H11; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "button_s2" T3; 5 | IO_PORT "button_s2" IO_TYPE=LVCMOS15; 6 | 7 | IO_LOC "rmii_txclk" A9; 8 | IO_LOC "rmii_rxd[0]" F15; 9 | IO_LOC "rmii_rxd[1]" C9; 10 | IO_LOC "rmii_crs_dv" M6; 11 | IO_LOC "rmii_txd[0]" D16; 12 | IO_LOC "rmii_txd[1]" E14; 13 | IO_LOC "rmii_txen" E16; 14 | IO_LOC "rmii_mdio" F16; 15 | IO_LOC "rmii_mdc" F14; 16 | IO_LOC "rmii_rstn" F10; 17 | 18 | IO_PORT "rmii_txclk" IO_TYPE=LVCMOS33; 19 | IO_PORT "rmii_rxd[0]" IO_TYPE=LVCMOS33; 20 | IO_PORT "rmii_rxd[1]" IO_TYPE=LVCMOS33; 21 | IO_PORT "rmii_crs_dv" IO_TYPE=LVCMOS33; 22 | IO_PORT "rmii_txd[0]" IO_TYPE=LVCMOS33; 23 | IO_PORT "rmii_txd[1]" IO_TYPE=LVCMOS33; 24 | IO_PORT "rmii_txen" IO_TYPE=LVCMOS33; 25 | IO_PORT "rmii_mdio" IO_TYPE=LVCMOS33; 26 | IO_PORT "rmii_mdc" IO_TYPE=LVCMOS33; 27 | IO_PORT "rmii_rstn" IO_TYPE=LVCMOS33; 28 | 29 | IO_LOC "led[0]" C13; 30 | IO_LOC "led[1]" A13; 31 | IO_LOC "led[2]" N16; 32 | IO_LOC "led[3]" N14; 33 | IO_LOC "led[4]" L14; 34 | IO_LOC "led[5]" L16; 35 | 36 | IO_PORT "led[0]" IO_TYPE=LVCMOS33; 37 | IO_PORT "led[1]" IO_TYPE=LVCMOS33; 38 | IO_PORT "led[2]" IO_TYPE=LVCMOS33; 39 | IO_PORT "led[3]" IO_TYPE=LVCMOS33; 40 | IO_PORT "led[4]" IO_TYPE=LVCMOS33; 41 | IO_PORT "led[5]" IO_TYPE=LVCMOS33; 42 | -------------------------------------------------------------------------------- /eda/i2s_master/src/tangprimer20k/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file top.sv 3 | * @brief Top module for ethernet ICMP echo reply system. 4 | */ 5 | // Copyright 2023 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | `default_nettype none 11 | module top( 12 | input wire clock, 13 | 14 | output logic out_bclk_dbg, 15 | output logic out_data_dbg, 16 | output logic out_ws_dbg, 17 | 18 | output logic out_bclk, 19 | output logic out_data, 20 | output logic out_ws, 21 | output logic out_pa_en 22 | ); 23 | 24 | logic main_clock; 25 | logic main_clock_lock; 26 | 27 | rpll_main your_instance_name( 28 | .clkout(main_clock), //output clkout 29 | .lock(main_clock_lock), //output lock 30 | .clkin(clock) //input clkin 31 | ); 32 | 33 | logic reset; 34 | reset_seq reset_seq_ext( 35 | .clock(main_clock), 36 | .reset_in(!main_clock_lock), 37 | .reset_out(reset) 38 | ); 39 | 40 | assign out_pa_en = !reset; 41 | 42 | always_comb begin 43 | out_bclk_dbg = out_bclk; 44 | out_data_dbg = out_data; 45 | out_ws_dbg = out_ws; 46 | end 47 | 48 | I2sMasterSystem system ( 49 | .clock(main_clock), 50 | .* 51 | ); 52 | 53 | endmodule 54 | `default_nettype wire -------------------------------------------------------------------------------- /eda/cpu_matrix_led/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := cpu_stopwatch 2 | SRCS := src/$(TARGET)/pins.cst $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) ../../external/picorv32/picorv32.v project.tcl src/sw/bootrom.hex 3 | PMOD_PORT_OFFSET ?= 0 4 | PMOD_TARGETS := tangnano9k_pmod tangprimer20k 5 | 6 | # Check if the target contains PMOD ports 7 | ifneq (,$(filter $(TARGET),$(PMOD_TARGETS))) 8 | USE_PMOD := 1 9 | PROJECT_ADDITIONAL_CLEAN += src/$(TARGET)/pins.cst 10 | else ifeq ($(TARGET),tangprimer20k) 11 | USE_PMOD := 0 12 | endif 13 | 14 | include ../build_gowin.mk 15 | 16 | src/sw/bootrom.hex: src/sw/bootrom.c src/sw/link.ld src/sw/Makefile 17 | cd src/sw; make 18 | 19 | 20 | ifeq ($(USE_PMOD),1) 21 | # Generate CST file from template. 22 | src/$(TARGET)/pins.cst: src/$(TARGET)/pins.cst.template $(TARGET_DEF_DIR)/pmod_ports.csv $(MOD_DIR)/pmod_matrix_led/pmod_pins.csv $(MAPPMOD) 23 | echo Generating pin definition from Pmod pin map. 24 | echo // This file is automatically generated by build script. DO NOT EDIT THIS FILE. > $@ 25 | cat src/$(TARGET)/pins.cst.template >> $@ 26 | $(MAPPMOD) --pmod-port-def $(TARGET_DEF_DIR)/pmod_ports.csv --pmod $(MOD_DIR)/pmod_matrix_led/pmod_pins.csv --port-offset $(PMOD_PORT_OFFSET) --direction right-to-left >> $@ 27 | else 28 | src/$(TARGET)/pins.cst: 29 | echo Use pre-generated pin definition. 30 | endif -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := cpu_riscv_chisel_book 2 | 3 | CHISEL_TEMPLATE_DIR ?= ../../external/riscv-chisel-book/chisel-template 4 | 5 | ifeq ($(TARGET),runber) 6 | RISCV_ELABORATE := fpga.ElaborateRunber 7 | RISCV_ELABORATE_OUTPUT_DIR := $(CHISEL_TEMPLATE_DIR)/rtl/riscv_runber 8 | endif 9 | ifeq ($(TARGET),tangnano9k) 10 | RISCV_ELABORATE := fpga.ElaborateTangNano9K 11 | RISCV_ELABORATE_OUTPUT_DIR := $(CHISEL_TEMPLATE_DIR)/rtl/riscv_tangnano9k 12 | endif 13 | ifeq ($(TARGET),comprocboard_9k) 14 | RISCV_ELABORATE := fpga.ElaborateTangNano9K 15 | RISCV_ELABORATE_OUTPUT_DIR := $(CHISEL_TEMPLATE_DIR)/rtl/riscv_tangnano9k 16 | endif 17 | 18 | RISCV_CORE_SRC := $(RISCV_ELABORATE_OUTPUT_DIR)/riscv.v 19 | PROJECT_ADDITIONAL_ARGS := $(abspath $(RISCV_CORE_SRC)) 20 | PROJECT_ADDITIONAL_CLEAN := $(RISCV_CORE_SRC) 21 | 22 | SRCS := $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) $(RISCV_CORE_SRC) project.tcl src/sw/bootrom.hex 23 | 24 | include ../build_gowin.mk 25 | 26 | $(CHISEL_TEMPLATE_DIR): 27 | git submodule update --init --recursive 28 | 29 | $(RISCV_CORE_SRC): $(CHISEL_TEMPLATE_DIR) 30 | cd $(CHISEL_TEMPLATE_DIR) && sbt "project riscv_chisel_book; runMain $(RISCV_ELABORATE)" 31 | 32 | src/sw/bootrom.hex: src/sw/bootrom.c src/sw/link.ld src/sw/Makefile 33 | cd src/sw; make -------------------------------------------------------------------------------- /eda/i2s_master/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := ethernet_icmp 2 | 3 | TARGET ?= tangprimer20k 4 | ROOT_DIR ?= $(abspath ../..) 5 | RTL_DIR ?= $(ROOT_DIR)/rtl 6 | I2S_MASTER_SRC := $(RTL_DIR)/chisel/i2s_master_system/i2s_master_system.v 7 | 8 | PROJECT_ADDITIONAL_ARGS := $(abspath $(I2S_MASTER_SRC)) 9 | 10 | SRCS := src/$(TARGET)/pins.cst $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl $(I2S_MASTER_SRC) 11 | 12 | PMOD_PORT_OFFSET ?= 0 13 | PMOD_TARGETS := tangnano9k 14 | 15 | # Check if the target contains PMOD ports 16 | USE_PMOD := 0 17 | ifneq (,$(filter $(TARGET),$(PMOD_TARGETS))) 18 | USE_PMOD := 1 19 | PROJECT_ADDITIONAL_CLEAN += src/$(TARGET)/pins.cst 20 | endif 21 | include ../build_gowin.mk 22 | 23 | ifeq ($(USE_PMOD),1) 24 | # Generate CST file from template. 25 | src/$(TARGET)/pins.cst: src/$(TARGET)/pins.cst.template $(TARGET_DEF_DIR)/pmod_ports.csv $(PMOD_MODULES) $(MAPPMOD) 26 | echo Generating pin definition from Pmod pin map. 27 | echo // This file is automatically generated by build script. DO NOT EDIT THIS FILE. > $@ 28 | cat src/$(TARGET)/pins.cst.template >> $@ 29 | $(MAPPMOD) --pmod-port-def $(TARGET_DEF_DIR)/pmod_ports.csv $(addprefix --pmod ,$(PMOD_MODULES)) --port-offset $(PMOD_PORT_OFFSET) --direction right-to-left >> $@ 30 | else 31 | src/$(TARGET)/pins.cst: 32 | echo Use pre-generated pin definition. 33 | endif -------------------------------------------------------------------------------- /chisel/src/main/scala/util/irrevocable_checker.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | import chisel3._ 10 | import chisel3.util._ 11 | 12 | class IrrevocableChecker[T <: Data](gen: T) extends Module { 13 | val io = IO(new Bundle{ 14 | val in = Flipped(Irrevocable(gen)) 15 | val out = Irrevocable(gen) 16 | val error = Output(Bool()) 17 | }) 18 | 19 | io.out <> io.in 20 | 21 | val error = RegInit(false.B) 22 | io.error := error 23 | 24 | val prevValid = RegNext(io.in.valid) 25 | val prevReady = RegNext(io.in.ready) 26 | 27 | when(prevValid && !prevReady && !io.in.valid ) { 28 | printf(p"Irrevocable violation detected!") 29 | error := true.B 30 | } 31 | } 32 | 33 | object IrrevocableChecker { 34 | def apply[T <: Data](in: IrrevocableIO[T], error: Option[Bool] = None): IrrevocableIO[T] = { 35 | val checker = Module(new IrrevocableChecker(chiselTypeOf(in.bits))) 36 | checker.io.in <> in 37 | if( error.isDefined ) { 38 | error.get := checker.io.error 39 | } 40 | checker.io.out 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /chisel/src/main/scala/gowin/oser10.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2022. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package gowin 8 | 9 | import chisel3._ 10 | import chisel3.experimental._ 11 | 12 | /** 13 | * GOWIN IOBUF OSER10 - 10bit output serializer 14 | */ 15 | class OSER10 extends BlackBox(Map("GSREN" -> "false", // Disable global reset 16 | "LSREN" -> "true" // Enable local reset 17 | )) { 18 | val io = IO(new Bundle { 19 | val Q = Output(Bool()) // Serial out 20 | val D0 = Input(Bool()) // Parallel in 0 21 | val D1 = Input(Bool()) // Parallel in 1 22 | val D2 = Input(Bool()) // Parallel in 2 23 | val D3 = Input(Bool()) // Parallel in 3 24 | val D4 = Input(Bool()) // Parallel in 4 25 | val D5 = Input(Bool()) // Parallel in 5 26 | val D6 = Input(Bool()) // Parallel in 6 27 | val D7 = Input(Bool()) // Parallel in 7 28 | val D8 = Input(Bool()) // Parallel in 8 29 | val D9 = Input(Bool()) // Parallel in 9 30 | val FCLK = Input(Clock()) // Fast (serializer) clock 31 | val PCLK = Input(Clock()) // Parallel clock 32 | val RESET = Input(Bool()) // Reset 33 | }) 34 | } -------------------------------------------------------------------------------- /chisel/src/test/scala/video-tests/dvi_out.scala: -------------------------------------------------------------------------------- 1 | package video 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chiseltest._ 6 | import scala.util.control.Breaks 7 | import org.scalatest.flatspec.AnyFlatSpec 8 | import org.scalatest.matchers.should.Matchers 9 | 10 | class DviOutTest extends AnyFlatSpec with ChiselScalatestTester with Matchers { 11 | it must "runs DviOut" in { 12 | test(new DviOut) 13 | .withAnnotations(Seq(VerilatorBackendAnnotation, WriteFstAnnotation)) 14 | { c => 15 | val totalCycles = 10000 16 | c.reset.poke(true.B) 17 | c.clock.step(4) 18 | c.reset.poke(false.B) 19 | c.clock.setTimeout(totalCycles + 10) 20 | c.clock.step(10) 21 | c.io.video.hSync.poke(true.B) 22 | c.clock.step(3) 23 | c.io.video.hSync.poke(false.B) 24 | c.io.video.vSync.poke(true.B) 25 | c.clock.step(3) 26 | c.io.video.vSync.poke(false.B) 27 | c.clock.step(1) 28 | c.io.video.dataEnable.poke(true.B) 29 | for(i <- 0 to 999) { 30 | c.io.video.pixelData.poke(i.U) 31 | c.clock.step(1) 32 | } 33 | c.io.video.dataEnable.poke(false.B) 34 | c.clock.step(totalCycles - 20 - 1000) 35 | } 36 | } 37 | 38 | } 39 | -------------------------------------------------------------------------------- /chisel/src/main/scala/util/graycode.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | import chisel3._ 10 | import chisel3.util.Cat 11 | 12 | class Bin2Gray(val width: Int) extends Module { 13 | val io = IO(new Bundle { 14 | val in = Input(UInt(width.W)) 15 | val out = Output(UInt(width.W)) 16 | }) 17 | 18 | io.out := io.in ^ (io.in >> 1) 19 | } 20 | class Gray2Bin(val width: Int) extends Module { 21 | val io = IO(new Bundle { 22 | val in = Input(UInt(width.W)) 23 | val out = Output(UInt(width.W)) 24 | }) 25 | 26 | val out = Wire(Vec(width, Bool())) 27 | out(width - 1) := io.in(width - 1) 28 | 29 | (width - 2 to 0 by -1).foreach(i => { 30 | out(i) := out(i+1) ^ io.in(i) 31 | }) 32 | io.out := out.asUInt 33 | } 34 | class GrayCodeCounter(val width: Int) extends Module { 35 | val io = IO(new Bundle{ 36 | val counter = Output(UInt(width.W)) 37 | }) 38 | 39 | val bin2gray = Module(new Bin2Gray(width)) 40 | val counter = RegInit(0.U(width.W)) 41 | 42 | counter := counter + 1.U 43 | bin2gray.io.in := counter 44 | io.counter := bin2gray.io.out 45 | } 46 | -------------------------------------------------------------------------------- /rtl/ethernet/util/simple_fifo.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module simple_fifo #( 4 | parameter DATA_BITS = 8, 5 | parameter DEPTH_BITS = 3 6 | ) ( 7 | input wire clock, 8 | input wire aresetn, 9 | 10 | input wire [DATA_BITS-1:0] saxis_tdata, 11 | input wire saxis_tvalid, 12 | output wire saxis_tready, 13 | 14 | output wire [DATA_BITS-1:0] maxis_tdata, 15 | output wire maxis_tvalid, 16 | input wire maxis_tready 17 | ); 18 | 19 | reg [DEPTH_BITS:0] index_r; 20 | reg [DEPTH_BITS:0] index_w; 21 | 22 | reg [DATA_BITS-1:0] memory[2**DEPTH_BITS-1:0]; 23 | 24 | assign saxis_tready = index_r[DEPTH_BITS] == index_w[DEPTH_BITS] || index_r[DEPTH_BITS-1:0] != index_w[DEPTH_BITS-1:0]; 25 | assign maxis_tvalid = index_r != index_w; 26 | assign maxis_tdata = memory[index_r[DEPTH_BITS-1:0]]; 27 | 28 | always @(posedge clock) begin 29 | if( !aresetn ) begin 30 | index_r <= 0; 31 | index_w <= 0; 32 | end 33 | else begin 34 | index_w <= saxis_tvalid && saxis_tready ? index_w + 1 : index_w; 35 | index_r <= maxis_tvalid && maxis_tready ? index_r + 1 : index_r; 36 | if( saxis_tvalid && saxis_tready ) begin 37 | memory[index_w[DEPTH_BITS-1:0]] <= saxis_tdata; 38 | end 39 | end 40 | end 41 | 42 | endmodule 43 | 44 | `default_nettype wire 45 | -------------------------------------------------------------------------------- /eda/lifegame_fram/src/tangnano9k/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file top.sv 3 | * @brief Top module for lifegame with FRAM 4 | */ 5 | // Copyright 2021-2022 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | module top ( 11 | input wire clock, 12 | 13 | output logic [5:0] led, 14 | output logic [7:0] d, 15 | output logic [7:0] row, 16 | output logic seven_seg, 17 | 18 | output logic spi_cs_n, 19 | output logic spi_wp_n, 20 | output logic spi_hold_n, 21 | output logic spi_sck, 22 | output logic spi_si, 23 | input wire spi_so, 24 | 25 | input wire initialize 26 | ); 27 | 28 | assign led = 0; 29 | assign seven_seg = 0; 30 | logic [15:0] reset_seq; 31 | initial begin 32 | reset_seq = '1; 33 | end 34 | always_ff @(posedge clock) begin 35 | reset_seq <= reset_seq >> 1; 36 | end 37 | logic reset; 38 | assign reset = reset_seq[0]; 39 | 40 | logic [2:0] initialize_reg = 0; 41 | always_ff @(posedge clock) begin 42 | if( reset ) begin 43 | initialize_reg <= 0; 44 | end 45 | else begin 46 | initialize_reg <= {initialize_reg[1:0], !initialize}; 47 | end 48 | end 49 | 50 | LifeGameFram lifegame_i( 51 | .data(d), 52 | .row(row), 53 | .reset(reset), 54 | .initialize(initialize_reg[2]), 55 | .* 56 | ); 57 | 58 | endmodule -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Boost Software License - Version 1.0 - August 17th, 2003 2 | 3 | Permission is hereby granted, free of charge, to any person or organization 4 | obtaining a copy of the software and accompanying documentation covered by 5 | this license (the "Software") to use, reproduce, display, distribute, 6 | execute, and transmit the Software, and to prepare derivative works of the 7 | Software, and to permit third-parties to whom the Software is furnished to 8 | do so, all subject to the following: 9 | 10 | The copyright notices in the Software and this entire statement, including 11 | the above license grant, this restriction and the following disclaimer, 12 | must be included in all copies of the Software, in whole or in part, and 13 | all derivative works of the Software, unless such copies or derivative 14 | works are solely in the form of machine-executable object code generated by 15 | a source language processor. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT 20 | SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 21 | FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, 22 | ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 | DEALINGS IN THE SOFTWARE. 24 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/src/comprocboard_9k/test/tb.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file tb.sv 3 | * @brief Testbench for i2c_slave module 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | `timescale 10ns/1ps 12 | 13 | module tb (); 14 | localparam I2C_REG_ADDRESS_WIDTH = 8; 15 | localparam I2C_CLOCK_PERIOD = 1000; 16 | 17 | logic clock; 18 | logic reset; 19 | logic [7:0] row; 20 | logic [7:0] d; 21 | logic seven_seg; 22 | logic [5:0] led; 23 | logic lcd_rs; 24 | logic lcd_rw; 25 | logic lcd_e; 26 | logic [3:0] lcd_db; 27 | logic uart_tx; 28 | logic uart_rx; 29 | logic [5:0] debug_out; 30 | 31 | initial begin 32 | forever begin 33 | clock = 1; 34 | #2; 35 | clock = 0; 36 | #2; 37 | end 38 | end 39 | 40 | assign uart_rx = 1; 41 | top dut ( 42 | .* 43 | ); 44 | 45 | 46 | initial begin 47 | $dumpfile("output.vcd"); 48 | $dumpvars; 49 | 50 | reset <= 1; 51 | 52 | repeat(2) @(posedge clock); 53 | reset <= 0; 54 | @(posedge clock); 55 | 56 | repeat(10000) @(posedge clock); 57 | 58 | $finish; 59 | end 60 | endmodule -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/tangnano9k/tb.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file tb.sv 3 | * @brief Testbench for i2c_slave module 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | `timescale 10ns/1ps 12 | 13 | module tb (); 14 | localparam I2C_REG_ADDRESS_WIDTH = 8; 15 | localparam I2C_CLOCK_PERIOD = 1000; 16 | 17 | logic clock; 18 | logic reset; 19 | logic [7:0] row; 20 | logic [7:0] d; 21 | logic seven_seg; 22 | logic [5:0] led; 23 | logic lcd_rs; 24 | logic lcd_rw; 25 | logic lcd_e; 26 | logic [3:0] lcd_db; 27 | logic uart_tx; 28 | logic uart_rx; 29 | logic [5:0] debug_out; 30 | logic button_s2 = 1; 31 | 32 | initial begin 33 | forever begin 34 | clock = 1; 35 | #2; 36 | clock = 0; 37 | #2; 38 | end 39 | end 40 | 41 | assign uart_rx = 1; 42 | top dut ( 43 | .* 44 | ); 45 | 46 | 47 | initial begin 48 | $dumpfile("output.vcd"); 49 | $dumpvars; 50 | 51 | reset <= 1; 52 | 53 | repeat(2) @(posedge clock); 54 | reset <= 0; 55 | @(posedge clock); 56 | 57 | repeat(10000) @(posedge clock); 58 | 59 | $finish; 60 | end 61 | endmodule -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k/tb.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file tb.sv 3 | * @brief Testbench for i2c_slave module 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | `timescale 10ns/1ps 12 | 13 | module tb (); 14 | localparam I2C_REG_ADDRESS_WIDTH = 8; 15 | localparam I2C_CLOCK_PERIOD = 1000; 16 | 17 | logic clock; 18 | logic reset; 19 | logic [7:0] row; 20 | logic [7:0] d; 21 | logic seven_seg; 22 | logic [5:0] led; 23 | logic lcd_rs; 24 | logic lcd_rw; 25 | logic lcd_e; 26 | logic [3:0] lcd_db; 27 | logic uart_tx; 28 | logic uart_rx; 29 | logic [5:0] debug_out; 30 | logic button_s2 = 1; 31 | 32 | initial begin 33 | forever begin 34 | clock = 1; 35 | #2; 36 | clock = 0; 37 | #2; 38 | end 39 | end 40 | 41 | assign uart_rx = 1; 42 | top dut ( 43 | .* 44 | ); 45 | 46 | 47 | initial begin 48 | $dumpfile("output.vcd"); 49 | $dumpvars; 50 | 51 | reset <= 1; 52 | 53 | repeat(2) @(posedge clock); 54 | reset <= 0; 55 | @(posedge clock); 56 | 57 | repeat(10000) @(posedge clock); 58 | 59 | $finish; 60 | end 61 | endmodule -------------------------------------------------------------------------------- /eda/dvi_out_tpg/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := dvi_out_tpg 2 | 3 | TARGET ?= tangnano9k 4 | ROOT_DIR ?= $(abspath ../..) 5 | RTL_DIR ?= $(ROOT_DIR)/rtl 6 | 7 | PROJECT_ADDITIONAL_ARGS := $(abspath src/cq_logo.hex) 8 | 9 | SRCS := src/$(TARGET)/pins.cst $(wildcard src/$(TARGET)/*.cst) $(wildcard src/$(TARGET)/*.sdc) $(wildcard src/$(TARGET)/*.sv) project.tcl $(RTL_DIR)/dvi_out/dvi_out.sv $(RTL_DIR)/video/test_pattern_generator.sv 10 | 11 | PMOD_PORT_OFFSET ?= 0 12 | PMOD_TARGETS := tangprimer25k 13 | 14 | # Check if the target contains PMOD ports 15 | USE_PMOD := 0 16 | ifneq (,$(filter $(TARGET),$(PMOD_TARGETS))) 17 | USE_PMOD := 1 18 | PROJECT_ADDITIONAL_CLEAN += src/$(TARGET)/pins.cst 19 | endif 20 | 21 | include ../build_gowin.mk 22 | 23 | PMOD_MODULES += $(MOD_DIR)/sipeed/pmod_dvi/pmod_pins.csv 24 | 25 | ifeq ($(USE_PMOD),1) 26 | # Generate CST file from template. 27 | src/$(TARGET)/pins.cst: src/$(TARGET)/pins.cst.template $(TARGET_DEF_DIR)/pmod_ports.csv $(PMOD_MODULES) $(MAPPMOD) 28 | echo Generating pin definition from Pmod pin map. 29 | echo // This file is automatically generated by build script. DO NOT EDIT THIS FILE. > $@ 30 | cat src/$(TARGET)/pins.cst.template >> $@ 31 | $(MAPPMOD) --pmod-port-def $(TARGET_DEF_DIR)/pmod_ports.csv $(addprefix --pmod ,$(PMOD_MODULES)) --port-offset $(PMOD_PORT_OFFSET) --direction right-to-left >> $@ 32 | else 33 | src/$(TARGET)/pins.cst: 34 | echo Use pre-generated pin definition. 35 | endif -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_matrix_led/tb.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @file tb.sv 3 | * @brief Testbench for i2c_slave module 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | `timescale 10ns/1ps 12 | 13 | module tb (); 14 | localparam I2C_REG_ADDRESS_WIDTH = 8; 15 | localparam I2C_CLOCK_PERIOD = 1000; 16 | 17 | logic clock; 18 | logic reset; 19 | logic [7:0] row; 20 | logic [7:0] d; 21 | logic seven_seg; 22 | logic [5:0] led; 23 | logic lcd_rs; 24 | logic lcd_rw; 25 | logic lcd_e; 26 | logic [3:0] lcd_db; 27 | logic uart_tx; 28 | logic uart_rx; 29 | logic [5:0] debug_out; 30 | logic button_s2 = 1; 31 | 32 | initial begin 33 | forever begin 34 | clock = 1; 35 | #2; 36 | clock = 0; 37 | #2; 38 | end 39 | end 40 | 41 | assign uart_rx = 1; 42 | top dut ( 43 | .* 44 | ); 45 | 46 | 47 | initial begin 48 | $dumpfile("output.vcd"); 49 | $dumpvars; 50 | 51 | reset <= 1; 52 | 53 | repeat(2) @(posedge clock); 54 | reset <= 0; 55 | @(posedge clock); 56 | 57 | repeat(10000) @(posedge clock); 58 | 59 | $finish; 60 | end 61 | endmodule -------------------------------------------------------------------------------- /chisel/src/main/scala/util/multibytesymbol.scala: -------------------------------------------------------------------------------- 1 | package util 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | class MultiByteSymbol(val numberOfBytes: Int) extends Bundle { 7 | val numberOfBits = (numberOfBytes*8) 8 | val data = UInt(numberOfBits.W) 9 | val keep = UInt(numberOfBytes.W) 10 | val last = Bool() 11 | } 12 | object MultiByteSymbol { 13 | def apply(numberOfBytes: Int): MultiByteSymbol = { 14 | new MultiByteSymbol(numberOfBytes) 15 | } 16 | def apply(flushable: Flushable[UInt]): MultiByteSymbol = { 17 | val bitWidth = flushable.data.getWidth 18 | val byteWidth = bitWidth / 8 19 | assert((bitWidth % 8) == 0) 20 | val hw = Wire(new MultiByteSymbol(byteWidth)) 21 | hw.data := flushable.data 22 | hw.keep := Fill(byteWidth, 1.U(1.W)) 23 | hw.last := flushable.last 24 | hw 25 | } 26 | } 27 | class MultiByteSymbolWithMetadata[T <: Data](val numberOfBytes: Int, metadataGen: T) extends Bundle { 28 | val numberOfBits = (numberOfBytes*8) 29 | val data = UInt(numberOfBits.W) 30 | val keep = UInt(numberOfBytes.W) 31 | val metadata = metadataGen.cloneType.asInstanceOf[T] 32 | val last = Bool() 33 | } 34 | object MultiByteSymbolWithMetadata { 35 | def apply[T <: Data](numberOfBytes: Int, genMetadata: T): MultiByteSymbolWithMetadata[T] = { 36 | new MultiByteSymbolWithMetadata(numberOfBytes, genMetadata) 37 | } 38 | } -------------------------------------------------------------------------------- /rtl/util/simple_fifo.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module simple_fifo #( 4 | parameter int DATA_BITS = 8, 5 | parameter int DEPTH_BITS = 3 6 | ) ( 7 | input wire clock, 8 | input wire reset, 9 | 10 | input wire [DATA_BITS-1:0] saxis_tdata, 11 | input wire saxis_tvalid, 12 | output logic saxis_tready, 13 | 14 | output logic [DATA_BITS-1:0] maxis_tdata, 15 | output logic maxis_tvalid, 16 | input wire maxis_tready 17 | ); 18 | 19 | logic [DEPTH_BITS:0] index_r; 20 | logic [DEPTH_BITS:0] index_w; 21 | 22 | logic [DATA_BITS-1:0] memory[2**DEPTH_BITS-1:0]; 23 | 24 | always_comb begin 25 | saxis_tready = index_r[DEPTH_BITS] == index_w[DEPTH_BITS] || index_r[DEPTH_BITS-1:0] != index_w[DEPTH_BITS-1:0]; 26 | maxis_tvalid = index_r != index_w; 27 | maxis_tdata = memory[index_r[DEPTH_BITS-1:0]]; 28 | end 29 | 30 | 31 | always_ff @(posedge clock) begin 32 | if( reset ) begin 33 | index_r <= 0; 34 | index_w <= 0; 35 | end 36 | else begin 37 | index_w <= saxis_tvalid && saxis_tready ? index_w + 1 : index_w; 38 | index_r <= maxis_tvalid && maxis_tready ? index_r + 1 : index_r; 39 | if( saxis_tvalid && saxis_tready ) begin 40 | memory[index_w[DEPTH_BITS-1:0]] <= saxis_tdata; 41 | end 42 | end 43 | end 44 | 45 | endmodule 46 | 47 | `default_nettype wire 48 | -------------------------------------------------------------------------------- /chisel/src/main/scala/axi/axi4_randomizer.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package axi 8 | 9 | import chisel3._ 10 | import chisel3.util._ 11 | import _root_.util._ 12 | 13 | class AXIRandomizer(axiParams: AXI4Params) extends Module { 14 | val io = IO(new Bundle{ 15 | val in = Flipped(AXI4IO(axiParams)) 16 | val out = AXI4IO(axiParams) 17 | }) 18 | 19 | axiParams.mode match { 20 | case AXI4ReadOnly => {} 21 | case _ => { 22 | io.out.aw.get <> IrrevocableRandomizer(io.in.aw.get) 23 | io.out.w.get <> IrrevocableRandomizer(io.in.w.get) 24 | io.in.b.get <> IrrevocableRandomizer(io.out.b.get) 25 | } 26 | } 27 | val readChannelError = WireDefault(false.B) 28 | axiParams.mode match { 29 | case AXI4WriteOnly => {} 30 | case _ => { 31 | io.out.ar.get <> IrrevocableRandomizer(io.in.ar.get) 32 | io.in.r.get <> IrrevocableRandomizer(io.out.r.get) 33 | } 34 | } 35 | } 36 | object AXIRandomizer { 37 | def apply(in: AXI4IO): AXI4IO = { 38 | val randomizer = Module(new AXIProtocolChecker(in.params)) 39 | randomizer.io.in <> in 40 | randomizer.io.out 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | # Additional args 8 | set RISCV_CORE_SRC [lindex $argv 6] 9 | 10 | set_option -output_base_name ${PROJECT_NAME} 11 | set_device -name $DEVICE_FAMILY $DEVICE_PART 12 | 13 | set_option -verilog_std sysv2017 14 | set_option -vhdl_std vhd2008 15 | set_option -print_all_synthesis_warning 1 16 | if {${TARGET} == "comprocboard_9k"} { 17 | set_option -use_sspi_as_gpio 1 18 | } 19 | 20 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 21 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 22 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 23 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 24 | add_file -type verilog [file normalize ${RTL_DIR}/util/simple_fifo.sv] 25 | add_file -type verilog [file normalize ${RTL_DIR}/uart/uart_tx.sv] 26 | add_file -type verilog [file normalize ${RTL_DIR}/uart/uart_rx.sv] 27 | add_file -type verilog [file normalize ${RISCV_CORE_SRC}] 28 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 29 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 30 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 31 | 32 | run all -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_matrix/project.tcl: -------------------------------------------------------------------------------- 1 | set SRC_DIR [lindex $argv 0] 2 | set RTL_DIR [lindex $argv 1] 3 | set TARGET [lindex $argv 2] 4 | set DEVICE_FAMILY [lindex $argv 3] 5 | set DEVICE_PART [lindex $argv 4] 6 | set PROJECT_NAME [lindex $argv 5] 7 | # Additional args 8 | set RISCV_CORE_SRC [lindex $argv 6] 9 | 10 | set_option -output_base_name ${PROJECT_NAME} 11 | set_device -name $DEVICE_FAMILY $DEVICE_PART 12 | 13 | set_option -verilog_std sysv2017 14 | set_option -vhdl_std vhd2008 15 | set_option -print_all_synthesis_warning 1 16 | if {${TARGET} == "comprocboard_9k"} { 17 | set_option -use_sspi_as_gpio 1 18 | } 19 | 20 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/segment_led.sv] 21 | add_file -type verilog [file normalize ${RTL_DIR}/segment_led/seven_segment_with_dp.sv] 22 | add_file -type verilog [file normalize ${RTL_DIR}/switch_input/debounce.sv] 23 | add_file -type verilog [file normalize ${RTL_DIR}/util/timer_counter.sv] 24 | add_file -type verilog [file normalize ${RTL_DIR}/util/simple_fifo.sv] 25 | add_file -type verilog [file normalize ${RTL_DIR}/uart/uart_tx.sv] 26 | add_file -type verilog [file normalize ${RTL_DIR}/uart/uart_rx.sv] 27 | add_file -type verilog [file normalize ${RISCV_CORE_SRC}] 28 | add_file -type verilog [file normalize ${SRC_DIR}/top.sv] 29 | add_file -type cst [file normalize ${SRC_DIR}/pins.cst] 30 | add_file -type sdc [file normalize ${SRC_DIR}/timing.sdc] 31 | 32 | run all -------------------------------------------------------------------------------- /rtl/util/timer_counter.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file timer_counter.sv 3 | * @brief Timer Counter with compare match. 4 | */ 5 | // Copyright 2021 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | 11 | module timer_counter #( 12 | parameter int MAX_COUNTER_VALUE = 255, 13 | localparam int COUNTER_BITS = $clog2(MAX_COUNTER_VALUE+1) 14 | ) ( 15 | input logic clock, 16 | input logic reset, 17 | 18 | input logic enable, 19 | input logic [COUNTER_BITS-1:0] top_value, 20 | input logic [COUNTER_BITS-1:0] compare_value, 21 | 22 | output logic [COUNTER_BITS-1:0] counter_value, 23 | 24 | output logic overflow, 25 | output logic compare_match 26 | ); 27 | 28 | logic [COUNTER_BITS-1:0] counter = 0; 29 | assign compare_match = counter == compare_value; 30 | assign counter_value = counter; 31 | 32 | always_ff @(posedge clock) begin 33 | if( reset ) begin 34 | counter <= 0; 35 | overflow <= 0; 36 | end 37 | else begin 38 | if( enable ) begin 39 | overflow <= 0; 40 | 41 | if( counter < top_value ) begin 42 | counter <= counter + 1; 43 | end 44 | else begin 45 | overflow <= 1; 46 | counter <= 0; 47 | end 48 | end 49 | end 50 | end 51 | 52 | endmodule -------------------------------------------------------------------------------- /chisel/src/main/scala/axi/axi4_gate.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | package axi 9 | 10 | import chisel3._ 11 | import chisel3.util._ 12 | import chisel3.experimental.ChiselEnum 13 | import _root_.util.WithIrrevocableGate 14 | 15 | class AXI4Gate(axi4Params: AXI4Params) extends Module { 16 | val io = IO(new Bundle { 17 | val in = Flipped(AXI4IO(axi4Params)) 18 | val out = AXI4IO(axi4Params) 19 | val enable = Input(Bool()) 20 | }) 21 | 22 | axi4Params.mode match { 23 | case AXI4WriteOnly => {} 24 | case _ => { 25 | io.out.ar.get <> WithIrrevocableGate(io.in.ar.get, io.enable) 26 | io.out.r.get <> io.in.r.get 27 | } 28 | } 29 | 30 | axi4Params.mode match { 31 | case AXI4ReadOnly => {} 32 | case _ => { 33 | io.out.aw.get <> WithIrrevocableGate(io.in.aw.get, io.enable) 34 | io.out.w.get <> io.in.w.get 35 | io.out.b.get <> io.in.b.get 36 | } 37 | } 38 | } 39 | 40 | object WithAXI4Gate { 41 | def apply(in: AXI4IO, enable: Bool): AXI4IO = { 42 | val gate = Module(new AXI4Gate(in.params)) 43 | gate.io.in <> in 44 | gate.io.enable := enable 45 | gate.io.out 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /chisel/src/main/scala/util/irrevocable_gate.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | 10 | import chisel3._ 11 | import chisel3.util._ 12 | 13 | class IrrevocableGate[T <: Data](gen: T) extends Module { 14 | val io = IO(new Bundle{ 15 | val in = Flipped(Irrevocable(gen)) 16 | val out = Irrevocable(gen) 17 | val enable = Input(Bool()) 18 | }) 19 | 20 | val outBits = Reg(gen) 21 | val outValid = RegInit(false.B) 22 | val outReady = io.out.ready 23 | io.out.valid := outValid 24 | io.out.bits := outBits 25 | val inBits = io.in.bits 26 | val inValid = io.in.valid 27 | val inReady = WireDefault(false.B) 28 | io.in.ready := inReady 29 | 30 | when(outValid && outReady) { 31 | outValid := false.B 32 | } 33 | when((!outValid || outReady) && io.enable) { 34 | outValid := inValid 35 | outBits := inBits 36 | inReady := true.B 37 | } 38 | } 39 | 40 | object WithIrrevocableGate { 41 | def apply[T <: Data](in: IrrevocableIO[T], enable: Bool): IrrevocableIO[T] = { 42 | val gate = Module(new IrrevocableGate(chiselTypeOf(in.bits))) 43 | gate.io.in <> in 44 | gate.io.enable := enable 45 | gate.io.out 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /rtl/ethernet/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright 2020 Fixstars, 2021-2023 Kenta Ida 2 | 3 | Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 4 | 5 | 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 6 | 7 | 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 8 | 9 | 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. 10 | 11 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------------------- /eda/matrix_led/src/tangnano9k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 52; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "row[0]" 34; 5 | IO_LOC "row[1]" 35; 6 | IO_LOC "row[2]" 41; 7 | IO_LOC "row[3]" 42; 8 | IO_LOC "row[4]" 51; 9 | IO_LOC "row[5]" 53; 10 | IO_LOC "row[6]" 54; 11 | IO_LOC "row[7]" 55; 12 | IO_LOC "d[0]" 56; 13 | IO_LOC "d[1]" 57; 14 | IO_LOC "d[2]" 68; 15 | IO_LOC "d[3]" 69; 16 | IO_LOC "d[4]" 32; 17 | IO_LOC "d[5]" 31; 18 | IO_LOC "d[6]" 49; 19 | IO_LOC "d[7]" 48; 20 | IO_LOC "seven_seg" 40; 21 | IO_PORT "row[0]" IO_TYPE=LVCMOS33; 22 | IO_PORT "row[1]" IO_TYPE=LVCMOS33; 23 | IO_PORT "row[2]" IO_TYPE=LVCMOS33; 24 | IO_PORT "row[3]" IO_TYPE=LVCMOS33; 25 | IO_PORT "row[4]" IO_TYPE=LVCMOS33; 26 | IO_PORT "row[5]" IO_TYPE=LVCMOS33; 27 | IO_PORT "row[6]" IO_TYPE=LVCMOS33; 28 | IO_PORT "row[7]" IO_TYPE=LVCMOS33; 29 | IO_PORT "d[0]" IO_TYPE=LVCMOS33; 30 | IO_PORT "d[1]" IO_TYPE=LVCMOS33; 31 | IO_PORT "d[2]" IO_TYPE=LVCMOS33; 32 | IO_PORT "d[3]" IO_TYPE=LVCMOS33; 33 | IO_PORT "d[4]" IO_TYPE=LVCMOS33; 34 | IO_PORT "d[5]" IO_TYPE=LVCMOS33; 35 | IO_PORT "d[6]" IO_TYPE=LVCMOS33; 36 | IO_PORT "d[7]" IO_TYPE=LVCMOS33; 37 | IO_PORT "seven_seg" IO_TYPE=LVCMOS33; 38 | 39 | IO_LOC "led[0]" 10; 40 | IO_LOC "led[1]" 11; 41 | IO_LOC "led[2]" 13; 42 | IO_LOC "led[3]" 14; 43 | IO_LOC "led[4]" 15; 44 | IO_LOC "led[5]" 16; 45 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 46 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 47 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 48 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 49 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 50 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 51 | -------------------------------------------------------------------------------- /eda/i2s_master/src/tangnano9k/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2023 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | create_generated_clock -name clock_main -source [get_ports {rmii_txclk}] -master_clock rmii_txclk -divide_by 5 -multiply_by 2 [get_nets {clock_main}] 11 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 12 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] 13 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_main/reset_seq*/SET}] 14 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_main/reset_seq*/D}] 15 | set_false_path -from [get_pins {ethernet_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/txAsyncFifo/wIndexGrayReg*/D}] 16 | set_false_path -from [get_pins {ethernet_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/rxAsyncFifo/wIndexGrayReg*/D}] 17 | set_false_path -from [get_pins {ethernet_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/txAsyncFifo/rIndexGrayReg*/D}] 18 | set_false_path -from [get_pins {ethernet_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/rxAsyncFifo/rIndexGrayReg*/D}] -------------------------------------------------------------------------------- /eda/ethernet_icmp/src/tangnano9k_pmod/timing.sdc: -------------------------------------------------------------------------------- 1 | // timing.sdc 2 | // Copyright 2023 Kenta IDA 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // http://www.boost.org/LICENSE_1_0.txt) 6 | 7 | 8 | create_clock -name clock -period 37.037 -waveform {0 18.518} [get_ports {clock}] 9 | create_clock -name rmii_txclk -period 20.000 -waveform {0 10.000} [get_ports {rmii_txclk}] 10 | create_generated_clock -name clock_main -source [get_ports {rmii_txclk}] -master_clock rmii_txclk -divide_by 5 -multiply_by 2 [get_nets {clock_main}] 11 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/SET}] 12 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_ext/reset_seq*/D}] 13 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_main/reset_seq*/SET}] 14 | set_false_path -from [get_pins {reset_button_0_s1/Q}] -to [get_pins {reset_seq_main/reset_seq*/D}] 15 | set_false_path -from [get_pins {ethernet_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/txAsyncFifo/wIndexGrayReg*/D}] 16 | set_false_path -from [get_pins {ethernet_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/rxAsyncFifo/wIndexGrayReg*/D}] 17 | set_false_path -from [get_pins {ethernet_system_inst/txAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/txAsyncFifo/rIndexGrayReg*/D}] 18 | set_false_path -from [get_pins {ethernet_system_inst/rxAsyncFifo/index*/Q}] -to [get_pins {ethernet_system_inst/rxAsyncFifo/rIndexGrayReg*/D}] -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangnano9k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clk" 52; 2 | IO_PORT "clk" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "anode[0]" 34; 5 | IO_LOC "anode[1]" 35; 6 | IO_LOC "anode[2]" 41; 7 | IO_LOC "anode[3]" 42; 8 | IO_LOC "anode[4]" 51; 9 | IO_LOC "anode[5]" 53; 10 | IO_LOC "anode[6]" 54; 11 | IO_LOC "anode[7]" 55; 12 | IO_LOC "cathode[0]" 56; 13 | IO_LOC "cathode[1]" 57; 14 | IO_LOC "cathode[2]" 68; 15 | IO_LOC "cathode[3]" 69; 16 | IO_LOC "cathode[4]" 32; 17 | IO_LOC "cathode[5]" 31; 18 | IO_LOC "cathode[6]" 49; 19 | IO_LOC "cathode[7]" 48; 20 | IO_PORT "anode[0]" IO_TYPE=LVCMOS33; 21 | IO_PORT "anode[1]" IO_TYPE=LVCMOS33; 22 | IO_PORT "anode[2]" IO_TYPE=LVCMOS33; 23 | IO_PORT "anode[3]" IO_TYPE=LVCMOS33; 24 | IO_PORT "anode[4]" IO_TYPE=LVCMOS33; 25 | IO_PORT "anode[5]" IO_TYPE=LVCMOS33; 26 | IO_PORT "anode[6]" IO_TYPE=LVCMOS33; 27 | IO_PORT "anode[7]" IO_TYPE=LVCMOS33; 28 | IO_PORT "cathode[0]" IO_TYPE=LVCMOS33; 29 | IO_PORT "cathode[1]" IO_TYPE=LVCMOS33; 30 | IO_PORT "cathode[2]" IO_TYPE=LVCMOS33; 31 | IO_PORT "cathode[3]" IO_TYPE=LVCMOS33; 32 | IO_PORT "cathode[4]" IO_TYPE=LVCMOS33; 33 | IO_PORT "cathode[5]" IO_TYPE=LVCMOS33; 34 | IO_PORT "cathode[6]" IO_TYPE=LVCMOS33; 35 | IO_PORT "cathode[7]" IO_TYPE=LVCMOS33; 36 | 37 | IO_LOC "led[0]" 10; 38 | IO_LOC "led[1]" 11; 39 | IO_LOC "led[2]" 13; 40 | IO_LOC "led[3]" 14; 41 | IO_LOC "led[4]" 15; 42 | IO_LOC "led[5]" 16; 43 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 44 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 45 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 46 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 47 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 48 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 49 | -------------------------------------------------------------------------------- /xls/mixer/Makefile: -------------------------------------------------------------------------------- 1 | TOP_ENTITY := mixer 2 | TOP := mixer 3 | # Currently opt_main requires the top module name generated in the IR. 4 | OPT_TOP ?= __mixer__mixer__mixer_body_0__2_2_next 5 | 6 | TEST_MODULE := test_$(TOP) 7 | TEST_TOP := $(TEST_MODULE) 8 | TEST_OPTS := -g2012 9 | 10 | CODEGEN_OPTS := --generator=pipeline --reset reset --delay_model=unit --clock_period_ps=10000 11 | 12 | XLS_HOME ?= $(HOME)/.local/share/xls/xls 13 | XLSCC := $(XLS_HOME)/contrib/xlscc/xlscc 14 | INTERPRETER_MAIN := $(XLS_HOME)/dslx/interpreter_main 15 | IR_CONVERTER_MAIN := $(XLS_HOME)/dslx/ir_convert/ir_converter_main 16 | CODEGEN_MAIN := $(XLS_HOME)/tools/codegen_main 17 | OPT_MAIN := $(XLS_HOME)/tools/opt_main 18 | 19 | .PHONY: run 20 | run: 21 | $(INTERPRETER_MAIN) $(TOP).dslx 22 | 23 | .PHONY: gen 24 | gen: $(TOP).ir $(TOP).opt.ir $(TOP).v 25 | 26 | %.ir: %.cc 27 | $(XLSCC) --top $(TOP_ENTITY) $< > $@.tmp 28 | @mv $@.tmp $@ 29 | 30 | %.ir: %.dslx 31 | $(IR_CONVERTER_MAIN) --top $(TOP_ENTITY) $< > $@.tmp 32 | @mv $@.tmp $@ 33 | 34 | %.opt.ir: %.ir 35 | $(OPT_MAIN) --top $(OPT_TOP) $< > $@.tmp 36 | @mv $@.tmp $@ 37 | 38 | %.v: %.opt.ir 39 | $(CODEGEN_MAIN) --use_system_verilog=false --module_name=$(TOP_ENTITY) $(CODEGEN_OPTS) $< > $@.tmp 40 | @mv $@.tmp $@ 41 | 42 | .PHONY: test 43 | test: $(TEST_MODULE).vcd 44 | 45 | .PHONY: show 46 | show: $(TEST_MODULE).vcd 47 | gtkwave $< & 48 | 49 | 50 | $(TEST_MODULE).vcd: $(TOP).v $(TEST_MODULE).sv 51 | iverilog $(TEST_OPTS) -s $(TEST_TOP) $^ -o $@ $(SRCS) 52 | ./$(patsubst .vcd,.elf,$@) 53 | 54 | .PHONY: clean 55 | clean: 56 | -@$(RM) *.v *.ir *.elf *.tmp -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/comprocboard_9k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clk" 52; 2 | IO_PORT "clk" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "anode[0]" 34; 5 | IO_LOC "anode[1]" 35; 6 | IO_LOC "anode[2]" 41; 7 | IO_LOC "anode[3]" 42; 8 | IO_LOC "anode[4]" 51; 9 | IO_LOC "anode[5]" 53; 10 | IO_LOC "anode[6]" 54; 11 | IO_LOC "anode[7]" 55; 12 | IO_LOC "cathode[0]" 56; 13 | IO_LOC "cathode[1]" 57; 14 | IO_LOC "cathode[2]" 68; 15 | IO_LOC "cathode[3]" 69; 16 | IO_LOC "cathode[4]" 32; 17 | IO_LOC "cathode[5]" 31; 18 | IO_LOC "cathode[6]" 49; 19 | IO_LOC "cathode[7]" 48; 20 | IO_LOC "seven_seg" 40; 21 | IO_PORT "anode[0]" IO_TYPE=LVCMOS33; 22 | IO_PORT "anode[1]" IO_TYPE=LVCMOS33; 23 | IO_PORT "anode[2]" IO_TYPE=LVCMOS33; 24 | IO_PORT "anode[3]" IO_TYPE=LVCMOS33; 25 | IO_PORT "anode[4]" IO_TYPE=LVCMOS33; 26 | IO_PORT "anode[5]" IO_TYPE=LVCMOS33; 27 | IO_PORT "anode[6]" IO_TYPE=LVCMOS33; 28 | IO_PORT "anode[7]" IO_TYPE=LVCMOS33; 29 | IO_PORT "cathode[0]" IO_TYPE=LVCMOS33; 30 | IO_PORT "cathode[1]" IO_TYPE=LVCMOS33; 31 | IO_PORT "cathode[2]" IO_TYPE=LVCMOS33; 32 | IO_PORT "cathode[3]" IO_TYPE=LVCMOS33; 33 | IO_PORT "cathode[4]" IO_TYPE=LVCMOS33; 34 | IO_PORT "cathode[5]" IO_TYPE=LVCMOS33; 35 | IO_PORT "cathode[6]" IO_TYPE=LVCMOS33; 36 | IO_PORT "cathode[7]" IO_TYPE=LVCMOS33; 37 | IO_PORT "seven_seg" IO_TYPE=LVCMOS33; 38 | 39 | IO_LOC "led[0]" 10; 40 | IO_LOC "led[1]" 11; 41 | IO_LOC "led[2]" 13; 42 | IO_LOC "led[3]" 14; 43 | IO_LOC "led[4]" 15; 44 | IO_LOC "led[5]" 16; 45 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 46 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 47 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 48 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 49 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 50 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 51 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangnano9k_pmod/pins.cst: -------------------------------------------------------------------------------- 1 | // This file is automatically generated by build script. DO NOT EDIT THIS FILE. 2 | IO_LOC "clk" 52; 3 | IO_PORT "clk" IO_TYPE=LVCMOS33; 4 | 5 | IO_PORT "anode[0]" IO_TYPE=LVCMOS33; 6 | IO_PORT "anode[1]" IO_TYPE=LVCMOS33; 7 | IO_PORT "anode[2]" IO_TYPE=LVCMOS33; 8 | IO_PORT "anode[3]" IO_TYPE=LVCMOS33; 9 | IO_PORT "anode[4]" IO_TYPE=LVCMOS33; 10 | IO_PORT "anode[5]" IO_TYPE=LVCMOS33; 11 | IO_PORT "anode[6]" IO_TYPE=LVCMOS33; 12 | IO_PORT "anode[7]" IO_TYPE=LVCMOS33; 13 | IO_PORT "cathode[0]" IO_TYPE=LVCMOS33; 14 | IO_PORT "cathode[1]" IO_TYPE=LVCMOS33; 15 | IO_PORT "cathode[2]" IO_TYPE=LVCMOS33; 16 | IO_PORT "cathode[3]" IO_TYPE=LVCMOS33; 17 | IO_PORT "cathode[4]" IO_TYPE=LVCMOS33; 18 | IO_PORT "cathode[5]" IO_TYPE=LVCMOS33; 19 | IO_PORT "cathode[6]" IO_TYPE=LVCMOS33; 20 | IO_PORT "cathode[7]" IO_TYPE=LVCMOS33; 21 | 22 | IO_LOC "led[0]" 10; 23 | IO_LOC "led[1]" 11; 24 | IO_LOC "led[2]" 13; 25 | IO_LOC "led[3]" 14; 26 | IO_LOC "led[4]" 15; 27 | IO_LOC "led[5]" 16; 28 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 29 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 30 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 31 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 32 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 33 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 34 | IO_LOC "cathode[1]" 28 35 | IO_LOC "cathode[3]" 26 36 | IO_LOC "cathode[5]" 39 37 | IO_LOC "cathode[7]" 37 38 | IO_LOC "cathode[0]" 27 39 | IO_LOC "cathode[2]" 25 40 | IO_LOC "cathode[4]" 36 41 | IO_LOC "cathode[6]" 38 42 | IO_LOC "anode[1]" 42 43 | IO_LOC "anode[3]" 35 44 | IO_LOC "anode[5]" 34 45 | IO_LOC "anode[7]" 30 46 | IO_LOC "anode[0]" 41 47 | IO_LOC "anode[2]" 40 48 | IO_LOC "anode[4]" 33 49 | IO_LOC "anode[6]" 29 50 | -------------------------------------------------------------------------------- /rtl/dds/test/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean compile test view 2 | 3 | MODULES_tb_dds_core := ../src/dds_core.sv 4 | TESTCASES_tb_dds_core := default sine 5 | 6 | TESTBENCHES := tb_dds_core 7 | VERILATOR := verilator 8 | #VERILATOR := docker run -it -e CCACHE_DIR=/tmp/ccache -v `realpath ${PWD}/../..`:`realpath ${PWD}/../..` -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest 9 | 10 | 11 | all: $(addsuffix -all,$(addprefix test-, $(TESTBENCHES))) 12 | @echo "Done." 13 | 14 | clean: 15 | -@$(RM) -f *.pb *.jou *.log *.wdb *.str 16 | -@$(RM) -rf xsim.dir .Xil 17 | -@$(RM) -r run-* 18 | 19 | $(MODULES_tb_dds_core): $(wildcard ../src/*.veryl) 20 | cd ..; veryl build 21 | 22 | define testbench-rule 23 | test-$1-all: $(addprefix test-$1-, $(TESTCASES_$1)) 24 | @echo "Done." 25 | endef 26 | 27 | define testcase-rule 28 | run-$1-$2/obj_dir/test_bin: $1.sv $(MODULES_$1) 29 | $(info Compiling $1 $2) 30 | mkdir -p run-$1-$2 31 | cd run-$1-$2; $(VERILATOR) --binary --top-module tb_$2 --assert --trace-fst --trace-params --trace-structs --trace-underscore $(abspath $1.sv) $(foreach module,$(MODULES_$1),$(abspath $(module))) -o test_bin 32 | 33 | compile-$1-$2: run-$1-$2/obj_dir/test_bin 34 | 35 | test-$1-$2: run-$1-$2/obj_dir/test_bin 36 | cd run-$1-$2; ./obj_dir/test_bin | tee test.log 37 | @if grep Error run-$1-$2/test.log; then echo "Error."; exit 1; fi 38 | 39 | view-$1-$2: run-$1-$2/trace.fst 40 | gtkwave run-$1-$2/trace.fst& 41 | endef 42 | 43 | $(foreach testbench,$(TESTBENCHES),$(eval $(call testbench-rule,$(testbench)))) 44 | $(foreach testbench,$(TESTBENCHES),$(foreach testcase,$(TESTCASES_$(testbench)),$(eval $(call testcase-rule,$(testbench),$(testcase))))) -------------------------------------------------------------------------------- /eda/dvi_out_tpg/src/conv_logo.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from typing import Tuple 4 | from PIL import Image 5 | from PIL import GifImagePlugin 6 | 7 | img = Image.open('./interface_logo.png') 8 | #img = img.convert('RGB') 9 | print(f"{img.size} {img.format} {img.mode} {img.getpixel((0,0))}") 10 | 11 | stride = (img.size[0] + 7) & ~7 12 | 13 | def is_black(pixel: Tuple[int, int, int]) -> bool: 14 | return pixel[0] + pixel[1] + pixel[2] < 128*3 15 | def is_transparent(pixel: Tuple[int, int, int, int]) -> bool: 16 | return pixel[3] < 128 17 | 18 | def bit_reverse(b:int) -> int: 19 | r = 0 20 | for i in range(8): 21 | r <<= 1 22 | r |= b & 1 23 | b >>= 1 24 | return r 25 | 26 | image_bytes = stride * img.size[1] 27 | buffer = bytearray(image_bytes) 28 | ptr = memoryview(buffer) 29 | 30 | for y in range(img.size[1]): 31 | pixels = 0 32 | for x in range(img.size[0]): 33 | if x > 0 and (x & 7) == 0: 34 | ptr[0] = pixels 35 | ptr = ptr[1:] 36 | pixels = 0 37 | pixels >>= 1 38 | #pixels |= 128 if ((x & 1) | (y & 1)) else 0 39 | #pixels |= 0 if not is_black(img.getpixel((x, y))) else 128 40 | pixels |= 0 if is_transparent(img.getpixel((x, y))) else 128 41 | 42 | if (img.size[0] & 7) != 0: 43 | ptr[0] = pixels >> (8 - (img.size[0] & 7)) 44 | ptr = ptr[1:] 45 | 46 | with open('interface_logo.hex', "w") as f: 47 | for b in buffer: 48 | print(f"{b:02X}", file=f) 49 | with open('interface_logo.bin', "wb") as f: 50 | for i in range(len(buffer)): 51 | buffer[i] = bit_reverse(buffer[i]) 52 | f.write(buffer) 53 | 54 | -------------------------------------------------------------------------------- /eda/cpu_riscv_chisel_book_blink/src/comprocboard_9k/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 52; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | 4 | IO_LOC "row[0]" 34; 5 | IO_LOC "row[1]" 35; 6 | IO_LOC "row[2]" 41; 7 | IO_LOC "row[3]" 42; 8 | IO_LOC "row[4]" 51; 9 | IO_LOC "row[5]" 53; 10 | IO_LOC "row[6]" 54; 11 | IO_LOC "row[7]" 55; 12 | IO_LOC "d[0]" 56; 13 | IO_LOC "d[1]" 57; 14 | IO_LOC "d[2]" 68; 15 | IO_LOC "d[3]" 69; 16 | IO_LOC "d[4]" 32; 17 | IO_LOC "d[5]" 31; 18 | IO_LOC "d[6]" 49; 19 | IO_LOC "d[7]" 48; 20 | IO_LOC "seven_seg" 40; 21 | IO_PORT "row[0]" IO_TYPE=LVCMOS33; 22 | IO_PORT "row[1]" IO_TYPE=LVCMOS33; 23 | IO_PORT "row[2]" IO_TYPE=LVCMOS33; 24 | IO_PORT "row[3]" IO_TYPE=LVCMOS33; 25 | IO_PORT "row[4]" IO_TYPE=LVCMOS33; 26 | IO_PORT "row[5]" IO_TYPE=LVCMOS33; 27 | IO_PORT "row[6]" IO_TYPE=LVCMOS33; 28 | IO_PORT "row[7]" IO_TYPE=LVCMOS33; 29 | IO_PORT "d[0]" IO_TYPE=LVCMOS33; 30 | IO_PORT "d[1]" IO_TYPE=LVCMOS33; 31 | IO_PORT "d[2]" IO_TYPE=LVCMOS33; 32 | IO_PORT "d[3]" IO_TYPE=LVCMOS33; 33 | IO_PORT "d[4]" IO_TYPE=LVCMOS33; 34 | IO_PORT "d[5]" IO_TYPE=LVCMOS33; 35 | IO_PORT "d[6]" IO_TYPE=LVCMOS33; 36 | IO_PORT "d[7]" IO_TYPE=LVCMOS33; 37 | IO_PORT "seven_seg" IO_TYPE=LVCMOS33; 38 | 39 | IO_LOC "led[0]" 10; 40 | IO_LOC "led[1]" 11; 41 | IO_LOC "led[2]" 13; 42 | IO_LOC "led[3]" 14; 43 | IO_LOC "led[4]" 15; 44 | IO_LOC "led[5]" 16; 45 | IO_PORT "led[0]" IO_TYPE=LVCMOS18; 46 | IO_PORT "led[1]" IO_TYPE=LVCMOS18; 47 | IO_PORT "led[2]" IO_TYPE=LVCMOS18; 48 | IO_PORT "led[3]" IO_TYPE=LVCMOS18; 49 | IO_PORT "led[4]" IO_TYPE=LVCMOS18; 50 | IO_PORT "led[5]" IO_TYPE=LVCMOS18; 51 | 52 | IO_LOC "uart_rx" 30 53 | IO_LOC "uart_tx" 33 54 | IO_PORT "uart_rx" IO_TYPE=LVCMOS33; 55 | IO_PORT "uart_tx" IO_TYPE=LVCMOS33; 56 | -------------------------------------------------------------------------------- /chisel/src/test/scala/util-tests/regslice.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | import org.scalatest._ 10 | import chiseltest._ 11 | import chisel3.util._ 12 | import chisel3._ 13 | import scala.util.control.Breaks 14 | import scala.util.Random 15 | 16 | 17 | class RegSliceTester extends FlatSpec with ChiselScalatestTester with Matchers { 18 | val dutName = "IrrevocableRegSlice" 19 | behavior of dutName 20 | 21 | def checkResult(c: IrrevocableRegSlice[UInt]) { 22 | c.io.in.initSource().setSourceClock(c.clock) 23 | c.io.out.initSink().setSinkClock(c.clock) 24 | val random = new Random 25 | fork { 26 | (0 to 255).foreach(i => { 27 | val idleCycles = if (random.nextInt(10) < 1) {random.nextInt(1) + 1} else {0} 28 | (0 to idleCycles - 1).foreach(i => { 29 | c.clock.step(1) 30 | }) 31 | c.io.out.expectDequeue(i.U) 32 | }) 33 | } .fork { 34 | (0 to 255).foreach(i => { 35 | val idleCycles = if (random.nextInt(10) < 1) {random.nextInt(1) + 1} else {0} 36 | (0 to idleCycles - 1).foreach(i => { 37 | c.clock.step(1) 38 | }) 39 | c.io.in.enqueue(i.U) 40 | }) 41 | } .join 42 | } 43 | 44 | it should "8bit" in { 45 | test(new IrrevocableRegSlice(UInt(8.W))) { c => checkResult(c) } 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /rtl/segment_led/segment_led.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @file segment_led.sv 3 | * @brief simple LED blink example. 4 | */ 5 | // Copyright 2019 Kenta IDA 6 | // Distributed under the Boost Software License, Version 1.0. 7 | // (See accompanying file LICENSE_1_0.txt or copy at 8 | // http://www.boost.org/LICENSE_1_0.txt) 9 | 10 | `default_nettype none 11 | module segment_led #( 12 | parameter int NUMBER_OF_SEGMENTS = 8, 13 | parameter int NUMBER_OF_DIGITS = 4, 14 | parameter bit CATHODE_COMMON = 1'b1 15 | ) ( 16 | input wire clock, 17 | input wire reset, 18 | 19 | input wire next_segment, 20 | 21 | input wire [NUMBER_OF_SEGMENTS-1:0] digits [0:NUMBER_OF_DIGITS-1], 22 | 23 | output logic [NUMBER_OF_SEGMENTS-1:0] segment_out, 24 | output logic [NUMBER_OF_DIGITS-1:0] digit_selector_out 25 | ); 26 | 27 | logic [NUMBER_OF_DIGITS-1:0] digit_selector = 1; 28 | assign digit_selector_out = CATHODE_COMMON ? ~digit_selector : digit_selector; 29 | logic [NUMBER_OF_DIGITS-1:0] digit_selector_next; 30 | assign digit_selector_next = { digit_selector[NUMBER_OF_DIGITS-2:0], digit_selector[NUMBER_OF_DIGITS-1] }; 31 | 32 | always_ff @(posedge clock) begin 33 | if( reset ) begin 34 | segment_out <= 0; 35 | digit_selector <= 1; 36 | end 37 | else begin 38 | if( next_segment ) begin 39 | for(int digit = 0; digit < NUMBER_OF_DIGITS; digit++ ) begin 40 | if( digit_selector_next[digit] ) begin 41 | segment_out <= digits[digit]; 42 | end 43 | end 44 | digit_selector <= digit_selector_next; 45 | end 46 | end 47 | end 48 | 49 | endmodule 50 | `default_nettype wire 51 | -------------------------------------------------------------------------------- /eda/cpu_matrix_led/src/tangprimer20k/pins.cst: -------------------------------------------------------------------------------- 1 | // This file is automatically generated by build script. DO NOT EDIT THIS FILE. 2 | IO_LOC "clk" H11; 3 | IO_PORT "clk" IO_TYPE=LVCMOS33; 4 | 5 | IO_PORT "anode[0]" IO_TYPE=LVCMOS33; 6 | IO_PORT "anode[1]" IO_TYPE=LVCMOS33; 7 | IO_PORT "anode[2]" IO_TYPE=LVCMOS33; 8 | IO_PORT "anode[3]" IO_TYPE=LVCMOS33; 9 | IO_PORT "anode[4]" IO_TYPE=LVCMOS33; 10 | IO_PORT "anode[5]" IO_TYPE=LVCMOS33; 11 | IO_PORT "anode[6]" IO_TYPE=LVCMOS33; 12 | IO_PORT "anode[7]" IO_TYPE=LVCMOS33; 13 | IO_PORT "cathode[0]" IO_TYPE=LVCMOS33; 14 | IO_PORT "cathode[1]" IO_TYPE=LVCMOS33; 15 | IO_PORT "cathode[2]" IO_TYPE=LVCMOS33; 16 | IO_PORT "cathode[3]" IO_TYPE=LVCMOS33; 17 | IO_PORT "cathode[4]" IO_TYPE=LVCMOS33; 18 | IO_PORT "cathode[5]" IO_TYPE=LVCMOS33; 19 | IO_PORT "cathode[6]" IO_TYPE=LVCMOS33; 20 | IO_PORT "cathode[7]" IO_TYPE=LVCMOS33; 21 | 22 | IO_LOC "led[0]" C13; 23 | IO_LOC "led[1]" A13; 24 | IO_LOC "led[2]" N16; 25 | IO_LOC "led[3]" N14; 26 | IO_LOC "led[4]" L14; 27 | IO_LOC "led[5]" L16; 28 | 29 | IO_PORT "led[0]" IO_TYPE=LVCMOS33; 30 | IO_PORT "led[1]" IO_TYPE=LVCMOS33; 31 | IO_PORT "led[2]" IO_TYPE=LVCMOS33; 32 | IO_PORT "led[3]" IO_TYPE=LVCMOS33; 33 | IO_PORT "led[4]" IO_TYPE=LVCMOS33; 34 | IO_PORT "led[5]" IO_TYPE=LVCMOS33; 35 | 36 | // PMOD pin locations 37 | IO_LOC "cathode[1]" E15 38 | IO_LOC "cathode[3]" A15 39 | IO_LOC "cathode[5]" A14 40 | IO_LOC "cathode[7]" C12 41 | IO_LOC "cathode[0]" D14 42 | IO_LOC "cathode[2]" B14 43 | IO_LOC "cathode[4]" B13 44 | IO_LOC "cathode[6]" B12 45 | IO_LOC "anode[1]" B11 46 | IO_LOC "anode[3]" D11 47 | IO_LOC "anode[5]" N7 48 | IO_LOC "anode[7]" N8 49 | IO_LOC "anode[0]" A11 50 | IO_LOC "anode[2]" N6 51 | IO_LOC "anode[4]" N9 52 | IO_LOC "anode[6]" L9 53 | -------------------------------------------------------------------------------- /chisel/src/main/scala/display/matrix_led.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2022. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package display 8 | 9 | import chisel3._ 10 | import chisel3.util._ 11 | 12 | case class MatrixLedConfig(rows: Int = 8, columns: Int = 8, val clockFreq: Int, refreshInterval: Int, refreshGuardInterval: Int) 13 | 14 | class MatrixLed(val config: MatrixLedConfig) extends Module { 15 | val io = IO(new Bundle { 16 | val row = Output(UInt(config.rows.W)) 17 | val column = Output(UInt(config.columns.W)) 18 | val matrix = Input(Vec(config.rows, UInt(config.columns.W))) 19 | }) 20 | 21 | val refreshCounter = RegInit(0.U(log2Ceil(config.refreshInterval).W)) 22 | val rowReg = RegInit(1.U(config.rows.W)) 23 | val rowEnable = WireDefault(true.B) 24 | 25 | io.row := Mux(rowEnable, rowReg, 0.U(config.columns.W)) 26 | io.column := MuxCase(0.U, (0 to config.rows - 1).map(i => ((rowReg === (1.U << i), io.matrix(i))))) 27 | 28 | refreshCounter := refreshCounter + 1.U 29 | when( refreshCounter < (config.refreshInterval - config.refreshGuardInterval*2 - 1).U ) { 30 | } .elsewhen( refreshCounter === (config.refreshInterval - config.refreshGuardInterval - 1).U ) { 31 | rowEnable := false.B 32 | rowReg := (rowReg << 1) | rowReg(config.rows - 1) 33 | } .elsewhen( refreshCounter < (config.refreshInterval - 1).U ) { 34 | rowEnable := false.B 35 | } .elsewhen( refreshCounter === (config.refreshInterval - 1).U ) { 36 | refreshCounter := 0.U 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /rtl/uart/uart_tx.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module uart_tx #( 3 | parameter int NUMBER_OF_BITS = 8, 4 | parameter int BAUD_DIVIDER = 4 5 | ) ( 6 | input wire clock, 7 | input wire reset, 8 | 9 | input wire data_valid, 10 | output logic data_ready, 11 | input wire [NUMBER_OF_BITS-1:0] data_bits, 12 | 13 | output logic tx 14 | ); 15 | 16 | localparam int RATE_COUNTER_BITS = $clog2(BAUD_DIVIDER); 17 | localparam int BIT_COUNTER_BITS = $clog2(NUMBER_OF_BITS+2); 18 | 19 | logic [RATE_COUNTER_BITS-1:0] rate_counter = 0; 20 | logic [BIT_COUNTER_BITS-1:0] bit_counter = 0; 21 | logic [NUMBER_OF_BITS+1:0] bits; 22 | 23 | assign tx = bit_counter == 0 || bits[0]; 24 | assign data_ready = bit_counter == 0; 25 | 26 | always_ff @(posedge clock) begin 27 | if( reset ) begin 28 | rate_counter <= 0; 29 | bit_counter <= 0; 30 | end 31 | else begin 32 | if( data_valid && data_ready ) begin 33 | bits <= {1'b1, data_bits, 1'b0 }; // STOP(1), DATA, START(0) 34 | bit_counter <= BIT_COUNTER_BITS'(NUMBER_OF_BITS + 2); 35 | rate_counter <= RATE_COUNTER_BITS'(BAUD_DIVIDER - 1); 36 | end 37 | if( bit_counter > 0 ) begin 38 | if( rate_counter == 0 ) begin 39 | bits <= {1'b0, bits[NUMBER_OF_BITS+1:1]}; 40 | bit_counter <= bit_counter - 1; 41 | rate_counter <= RATE_COUNTER_BITS'(BAUD_DIVIDER - 1); 42 | end 43 | else begin 44 | rate_counter <= RATE_COUNTER_BITS'(rate_counter - RATE_COUNTER_BITS'(1)); 45 | end 46 | end 47 | end 48 | end 49 | 50 | endmodule 51 | `default_nettype wire -------------------------------------------------------------------------------- /xls/filter/moving_average.dslx: -------------------------------------------------------------------------------- 1 | struct State { 2 | buffer: s16[8], 3 | accumulator: s19, 4 | index: u3, 5 | filled: u1, 6 | } 7 | 8 | proc moving_average { 9 | input_consumer: chan in; 10 | output_producer: chan out; 11 | 12 | init { State { buffer: s16[8]:[s16:0, ...], accumulator: s19:0, index: u3:0, filled: u1:0 } } 13 | 14 | config(input_consumer: chan in, output_producer: chan out) { 15 | (input_consumer, output_producer) 16 | } 17 | 18 | next(tok: token, state: State) { 19 | let (tok, input) = recv(tok, input_consumer); 20 | let old = if state.filled { state.buffer[state.index] } else { s16:0 }; 21 | let accumulator = (state.accumulator - old as s19) + input as s19; 22 | let index = state.index + u3:1; 23 | let filled = state.filled || state.index == u3:7; 24 | let buffer = update(state.buffer, state.index, input); 25 | let tok = send(tok, output_producer, (accumulator >> 3) as s16); 26 | State { buffer, accumulator, index, filled } 27 | } 28 | } 29 | 30 | #[test_proc] 31 | proc smoke_test { 32 | input_s: chan out; 33 | output_r: chan in; 34 | terminator: chan out; 35 | 36 | init { () } 37 | 38 | config(terminator: chan out) { 39 | let (input_s, input_r) = chan; 40 | let (output_s, output_r) = chan; 41 | spawn moving_average(input_r, output_s); 42 | (input_s, output_r, terminator) 43 | } 44 | 45 | next(tok: token, state: ()) { 46 | let tok = send(tok, input_s, s16:0); 47 | let (tok, result) = recv(tok, output_r); 48 | assert_eq(result, s16:0); 49 | 50 | let tok = send(tok, terminator, true); 51 | } 52 | } -------------------------------------------------------------------------------- /chisel/src/main/scala/util/regslice.scala: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: BSL-1.0 2 | // Copyright Kenta Ida 2021. 3 | // Distributed under the Boost Software License, Version 1.0. 4 | // (See accompanying file LICENSE_1_0.txt or copy at 5 | // https://www.boost.org/LICENSE_1_0.txt) 6 | 7 | package util 8 | 9 | 10 | import chisel3._ 11 | import chisel3.util._ 12 | 13 | class IrrevocableRegSlice[T <: Data](gen: T) extends Module { 14 | val io = IO(new Bundle{ 15 | val in = Flipped(Irrevocable(gen)) 16 | val out = Irrevocable(gen) 17 | }) 18 | 19 | val read = RegInit(0.U(2.W)) 20 | val write = RegInit(0.U(2.W)) 21 | val data = Reg(Vec(2, gen)) 22 | 23 | val empty = Wire(Bool()) 24 | val full = Wire(Bool()) 25 | 26 | empty := read === write 27 | full := read(1) =/= write(1) && read(0) === write(0) 28 | 29 | when(io.in.valid && io.in.ready) { 30 | data(write(0)) := io.in.bits 31 | write := write + 1.U 32 | } 33 | when(io.out.valid && io.out.ready) { 34 | read := read + 1.U 35 | } 36 | 37 | io.in.ready := !full 38 | io.out.valid := !empty 39 | io.out.bits := data(read(0)) 40 | } 41 | 42 | object UnsafeIrrevocable { 43 | def apply[T <: Data](in: DecoupledIO[T]): IrrevocableIO[T] = { 44 | val irrevocable = Wire(new IrrevocableIO(chiselTypeOf(in.bits))) 45 | irrevocable.valid := in.valid 46 | irrevocable.bits := in.bits 47 | in.ready := irrevocable.ready 48 | irrevocable 49 | } 50 | } 51 | 52 | object WithIrrevocableRegSlice { 53 | def apply[T <: Data](in: IrrevocableIO[T]): IrrevocableIO[T] = { 54 | val regSlice = Module(new IrrevocableRegSlice(chiselTypeOf(in.bits))) 55 | regSlice.io.in <> in 56 | regSlice.io.out 57 | } 58 | } 59 | -------------------------------------------------------------------------------- /rtl/ethernet/mii_mac/crc_mac.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module crc_mac ( 4 | input wire clock, 5 | input wire aresetn, 6 | 7 | input wire [7:0] saxis_tdata, 8 | input wire saxis_tvalid, 9 | output wire saxis_tready, 10 | input wire saxis_tlast, 11 | input wire saxis_tuser, 12 | 13 | output wire [7:0] maxis_tdata, 14 | output wire maxis_tvalid, 15 | input wire maxis_tready, 16 | output wire maxis_tlast, 17 | output wire maxis_tuser, 18 | 19 | output wire [31:0] crc_out 20 | ); 21 | 22 | // Pass-through AXI Stream 23 | assign maxis_tdata = saxis_tdata; 24 | assign maxis_tvalid = saxis_tvalid; 25 | assign saxis_tready = maxis_tready; 26 | assign maxis_tlast = saxis_tlast; 27 | assign maxis_tuser = saxis_tuser; 28 | 29 | localparam [31:0] POLYNOMIAL = 32'b1110_1101_1011_1000_1000_0011_0010_0000; 30 | 31 | reg [31:0] remainder; 32 | wire [31:0] rem_stage[8:0]; 33 | 34 | assign rem_stage[0] = {remainder[31:8], remainder[7:0] ^ saxis_tdata}; 35 | generate 36 | for(genvar i = 0; i < 8; i = i + 1) begin 37 | assign rem_stage[i+1] = {1'b0, rem_stage[i][31:1] ^ (rem_stage[i][0] ? POLYNOMIAL : 32'b0)}; 38 | end 39 | endgenerate 40 | 41 | wire [31:0] remainder_next; 42 | assign remainder_next = rem_stage[8]; 43 | 44 | reg [31:0] crc_out_reg; 45 | assign crc_out = saxis_tvalid && saxis_tready && saxis_tlast ? ~remainder_next : crc_out_reg; 46 | 47 | always @(posedge clock) begin 48 | if( !aresetn ) begin 49 | remainder <= {32 {1'b1}}; 50 | crc_out_reg <= 0; 51 | end 52 | else begin 53 | remainder <= saxis_tvalid && saxis_tready ? (saxis_tlast ? {32 {1'b1}} : remainder_next) : remainder; 54 | crc_out_reg <= crc_out; 55 | end 56 | end 57 | 58 | endmodule 59 | 60 | `default_nettype wire 61 | -------------------------------------------------------------------------------- /eda/blink/src/runber/pins.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clock" 4; 2 | IO_PORT "clock" IO_TYPE=LVCMOS33; 3 | // IO_LOC "resetn" 58; 4 | // IO_PORT "resetn" IO_TYPE=LVCMOS33; 5 | 6 | // IO_LOC "seg_a" 138; 7 | // IO_LOC "seg_b" 142; 8 | // IO_LOC "seg_c" 9; 9 | // IO_LOC "seg_d" 11; 10 | // IO_LOC "seg_e" 12; 11 | // IO_LOC "seg_f" 139; 12 | // IO_LOC "seg_g" 8; 13 | // IO_LOC "seg_dp" 10; 14 | // IO_LOC "seg_dig1" 137; 15 | // IO_LOC "seg_dig2" 140 16 | // IO_LOC "seg_dig3" 141; 17 | // IO_LOC "seg_dig4" 7; 18 | // 19 | // IO_PORT "seg_a" IO_TYPE=LVCMOS33; 20 | // IO_PORT "seg_b" IO_TYPE=LVCMOS33; 21 | // IO_PORT "seg_c" IO_TYPE=LVCMOS33; 22 | // IO_PORT "seg_d" IO_TYPE=LVCMOS33; 23 | // IO_PORT "seg_e" IO_TYPE=LVCMOS33; 24 | // IO_PORT "seg_f" IO_TYPE=LVCMOS33; 25 | // IO_PORT "seg_g" IO_TYPE=LVCMOS33; 26 | // IO_PORT "seg_dp" IO_TYPE=LVCMOS33; 27 | // IO_PORT "seg_dig1" IO_TYPE=LVCMOS33; 28 | // IO_PORT "seg_dig2" IO_TYPE=LVCMOS33; 29 | // IO_PORT "seg_dig3" IO_TYPE=LVCMOS33; 30 | // IO_PORT "seg_dig4" IO_TYPE=LVCMOS33; 31 | // 32 | // // KEYS 33 | // IO_LOC "key_5" 62 34 | // IO_LOC "key_6" 63 35 | // IO_LOC "key_7" 64 36 | // IO_LOC "key_8" 65 37 | // IO_PORT "key_5" IO_TYPE=LVCMOS33; 38 | // IO_PORT "key_6" IO_TYPE=LVCMOS33; 39 | // IO_PORT "key_7" IO_TYPE=LVCMOS33; 40 | // IO_PORT "key_8" IO_TYPE=LVCMOS33; 41 | 42 | IO_LOC "led_out[0]" 23; 43 | IO_LOC "led_out[1]" 24; 44 | IO_LOC "led_out[2]" 25; 45 | IO_LOC "led_out[3]" 26; 46 | IO_LOC "led_out[4]" 27; 47 | IO_LOC "led_out[5]" 28; 48 | IO_LOC "led_out[6]" 29; 49 | IO_LOC "led_out[7]" 30; 50 | IO_PORT "led_out[0]" IO_TYPE=LVCMOS33; 51 | IO_PORT "led_out[1]" IO_TYPE=LVCMOS33; 52 | IO_PORT "led_out[2]" IO_TYPE=LVCMOS33; 53 | IO_PORT "led_out[3]" IO_TYPE=LVCMOS33; 54 | IO_PORT "led_out[4]" IO_TYPE=LVCMOS33; 55 | IO_PORT "led_out[5]" IO_TYPE=LVCMOS33; 56 | IO_PORT "led_out[6]" IO_TYPE=LVCMOS33; 57 | IO_PORT "led_out[7]" IO_TYPE=LVCMOS33; 58 | --------------------------------------------------------------------------------