├── Firmware_Binary ├── pcie.svf └── uart.svf ├── Images ├── Intel_FPGA_Board_reverse_engineering (1).JPG ├── Intel_FPGA_Board_reverse_engineering (2).JPG └── Intel_FPGA_Board_reverse_engineering (3).JPG ├── Projects ├── c4gx_qsys_pcie_gen1x1 │ ├── altgx_reconfig.v │ ├── altgx_reconfig_bb.v │ ├── c4gx_qsys_pcie_gen1x1.qpf │ ├── reconfig_pll.v │ ├── reconfig_pll_bb.v │ └── top_qsys_pcie.v └── pin_uart │ ├── clk_div.v │ ├── int_osc.qsys │ ├── pin_uart.qpf │ ├── pin_uart.v │ ├── pin_uart_top.v │ ├── pin_uart_top_tb.v │ ├── testtesttest.v │ └── testtesttest_bb.v ├── README.md ├── Reference_Docs ├── EP4CE15E22I7N.PDF ├── an456.pdf ├── c4gx_f896_host_b.pdf ├── cyclone-iv-product-table.pdf ├── ep4cgx22.pdf ├── pcie_testing.pdf ├── rm_civgx_fpga_dev_board.pdf ├── rm_civgx_trans_starter_board.pdf ├── ug-qpp-platform-designer-18-1-683609-704994.pdf ├── ug_altclock.pdf ├── ug_civgx_fpga_dev_kit.pdf └── ug_pci_express.pdf ├── Reference_Project ├── PCIe_Transfer_Fifo.zip ├── c4gx15-starter-qsys-pcie-gen1x1.zip └── s4gx230-qsys-pcie-gen2x4.zip ├── Schematic ├── JTAG.SchDoc └── JTAG.pdf └── bsdl └── EP4CGX22BF14.bsd /Firmware_Binary/pcie.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/circuitvalley/Intel_FPGA_Board_98Y2610/HEAD/Firmware_Binary/pcie.svf -------------------------------------------------------------------------------- /Firmware_Binary/uart.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/circuitvalley/Intel_FPGA_Board_98Y2610/HEAD/Firmware_Binary/uart.svf -------------------------------------------------------------------------------- /Images/Intel_FPGA_Board_reverse_engineering (1).JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/circuitvalley/Intel_FPGA_Board_98Y2610/HEAD/Images/Intel_FPGA_Board_reverse_engineering (1).JPG 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