├── README.md ├── dvint43 ├── DVINT.LST ├── FILE_ID.DIZ ├── INTERRUP.1ST └── RBROWN.TXT ├── faq.lst ├── inter61a ├── FILE_ID.DIZ ├── INTERRUP.A ├── INTERRUP.B ├── INTERRUP.C ├── INTERRUP.D ├── NEEDHELP.TXT ├── OVERVIEW.LST ├── RBROWN.TXT ├── README.1 ├── README.NOW ├── SAMPLE.FLT ├── SAMPLE1.FLT ├── SAMPLE2.FLT ├── TABLES.LST └── _ADVERT.TXT ├── inter61b ├── FILE_ID.DIZ ├── GLOSSARY.LST ├── INTERRUP.E ├── INTERRUP.F ├── INTERRUP.G ├── INTERRUP.H ├── INTERRUP.I └── README.2 ├── inter61c ├── CATEGORY.KEY ├── FARCALL.LST ├── FILE_ID.DIZ ├── INTERRUP.1ST ├── INTERRUP.J ├── INTERRUP.K ├── INTERRUP.L ├── INTERRUP.M ├── INTERRUP.N ├── INTERRUP.PRI ├── INTPRINT.COM ├── MEMORY.LST ├── MSR.LST ├── README.3 └── SMM.LST ├── inter61d ├── 86BUGS.DOC ├── 86BUGS.LST ├── BIBLIO.LST ├── CMOS.LST ├── COMBINE.COM ├── COMBINE.DOC ├── FILE_ID.DIZ ├── I2C.LST ├── INTERRUP.O ├── INTERRUP.P ├── INTERRUP.Q ├── INTERRUP.R ├── INTPRINT.DOC ├── OPCODES.LST ├── PGP-SIGS.ZIP ├── PORTS.A ├── PORTS.B ├── PORTS.C └── README.4 ├── inter61e ├── 86BUGS04.ZIP ├── COMBINE.ASM ├── FILE_ID.DIZ ├── II.ZIP ├── ILINA100.ZIP ├── INT.C ├── INT.COM ├── INTHLP10.ZIP ├── INTLIST.E ├── INTPRINT.C ├── INTSUM16.ZIP ├── IVIEW102.ZIP ├── README.5 └── VIEWINTL.ZIP ├── inter61f ├── FILE_ID.DIZ ├── HINTSRCH.ZIP ├── IL2ME102.ZIP ├── INT2GUID.ZIP ├── INT2HLP.ZIP ├── INT2IPF.ZIP ├── INT2QH.ZIP ├── INT2RTF.ZIP ├── INT2TPH.ZIP ├── INT2WHLP.ZIP ├── INTERRUP.ICO ├── RB2NG116.ZIP ├── README.6 └── WH_ED122.ZIP └── rbpci119 ├── 10040005.PCI ├── 10040006.PCI ├── 10110009.PCI ├── 10110014.PCI ├── 10421000.PCI ├── 11060585.PCI ├── 11060598.PCI ├── 53338811.PCI ├── 80860482.PCI ├── 80860483.PCI ├── 80860484.PCI ├── 80860486.PCI ├── 808604A3.PCI ├── 80861229.PCI ├── 8086122D.PCI ├── 80861230.PCI ├── 80861235.PCI ├── 80861237.PCI ├── 80861250.PCI ├── 80867000.PCI ├── 80867010.PCI ├── 80867020.PCI ├── 80867030.PCI ├── 80867100.PCI ├── 80867110.PCI ├── 80867111.PCI ├── 80867112.PCI ├── 80867113.PCI ├── 80867190.PCI ├── 80867192.PCI ├── BLANK.PCI ├── FILE_ID.DIZ ├── PCICFG.CPP ├── PCICFG.DAT ├── PCICFG.EXE ├── PCICFG.TXT ├── PGP-SIGS.ZIP └── RBROWN.TXT /README.md: -------------------------------------------------------------------------------- 1 | # Ralf Brown Interrupt List 2 | 3 | Origin: 4 | 5 | TODO: remove output files, expand all zips, understand what it all means. 6 | -------------------------------------------------------------------------------- /dvint43/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | DESQview/QEMM Interrupt List, Release 43 2 | A Comprehensive listing of interrupt 3 | calls related to TopView, DESQview, 4 | QEMM, and other Quarterdeck products, 5 | both documented and undocumented. 6 | Contains 110 entries and more than 7 | 200 tables. 8 | -------------------------------------------------------------------------------- /dvint43/INTERRUP.1ST: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/dvint43/INTERRUP.1ST -------------------------------------------------------------------------------- /dvint43/RBROWN.TXT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/dvint43/RBROWN.TXT -------------------------------------------------------------------------------- /faq.lst: -------------------------------------------------------------------------------- 1 | Frequently-Asked Questions Release 61 Last Edit 16jul00 2 | Copyright 2000 Ralf Brown 3 | 4 | Have a frequently-asked question about interrupts or ports and its answer? 5 | Mail them to me for inclusion in this file (with credit to you). 6 | ralf@pobox.com 7 | 8 | --------------------------------------------- 9 | Index: 10 | 1. Is there an interrupt to get the BIOS serial number as shown on the 11 | power-up screen? 12 | 13 | 14 | --------------------------------------------- 15 | Q1: Is there an interrupt to get the BIOS serial number as shown on the 16 | power-up screen? 17 | A: (Ralf Brown) 18 | There is no general way to get the serial number. In most cases, you 19 | need to know the proper offset in the BIOS image for that particular 20 | make, model, and revision of the BIOS (and that offset may not even 21 | be present in the real-mode image loaded into shadow RAM!). 22 | 23 | Further, with a flashable BIOS, it is quite likely that every single 24 | machine that has been updated with a downloadable upgrade from the 25 | Web will have identical serial numbers, assuming they weren't already 26 | identical as shipped from the factory with the original BIOS version. 27 | Because of this, the BIOS serial number is essentially useless for 28 | any identification purposes. 29 | 30 | --------------------------------------------- 31 | End of File 32 | -------------------------------------------------------------------------------- /inter61a/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | x86/MS-DOS Interrupt List, Release 61 2 | A Comprehensive listing of interrupt 3 | calls, both documented and undocumented, 4 | plus ports/memory/CMOS/etc. Over 9600 5 | entries (plus 5400 tables) in INTER61A 6 | to INTER61D, utility programs and 7 | viewers in INTER61E, and hypertext 8 | conversion progs & WinHelp utilities in 9 | INTER60F. Over 8 million bytes of 10 | text! Released 2000/07/16. 11 | -------------------------------------------------------------------------------- /inter61a/INTERRUP.B: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61a/INTERRUP.B -------------------------------------------------------------------------------- /inter61a/NEEDHELP.TXT: -------------------------------------------------------------------------------- 1 | VOLUNTEERS NEEDED 2 | ----------------- 3 | 4 | 15jul00: 5 | 6 | I haven't been managing any transcriptions for a while due to lack of 7 | time, but I hope to restart the process this fall. Once I'm ready to 8 | go, I'll contact everyone who has volunteered in the past. 9 | 10 | 11 | 30aug98: 12 | 13 | If you've always wanted to show your appreciation of the interrupt 14 | list, but never had anything to contribute before, here's your chance! 15 | I continue to have a need for volunteers to transcribe and condense the 16 | information in various on-line documents into a suitable form for 17 | inclusion in the list. A good job of transcription can save me 90% of 18 | the effort it would otherwise take me, which means that I can get far 19 | more information into the list -- and that helps everyone. 20 | 21 | If you're interested in transcribing one or more documents, send me 22 | mail and I'll provide you with the URL and a brief style guide. Let me 23 | know whether you're willing to work on a large document or only a 24 | small(ish) one. As an added incentive, those who contribute at least 25 | 120K of additions (roughly equivalent to the info from four motherboard 26 | chipsets; figure around 50 hours of effort) get a free autographed 27 | copy of one of my books. 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /inter61a/OVERVIEW.LST: -------------------------------------------------------------------------------- 1 | [Provided by Bent Lynggaard . Last Edit 6/5/94] 2 | This list is a brief description of each of the 256 interrupts. Each 3 | description begins with "INT nn " where "nn" is a two digit hexadecimal 4 | number 00 - FF. For automatic processing, do not rely on the order being 5 | consecutive. 6 | --------!---TITLES--------------------------- 7 | INT 00 - CPU-generated - DIVIDE ERROR 8 | INT 01 - CPU-generated - SINGLE STEP; (80386+) - DEBUGGING EXCEPTIONS 9 | INT 02 - external hardware - NON-MASKABLE INTERRUPT 10 | INT 03 - CPU-generated - BREAKPOINT 11 | INT 04 - CPU-generated - INTO DETECTED OVERFLOW 12 | INT 05 - PRINT SCREEN; CPU-generated (80186+) - BOUND RANGE EXCEEDED 13 | INT 06 - CPU-generated (80286+) - INVALID OPCODE 14 | INT 07 - CPU-generated (80286+) - PROCESSOR EXTENSION NOT AVAILABLE 15 | INT 08 - IRQ0 - SYSTEM TIMER; CPU-generated (80286+) 16 | INT 09 - IRQ1 - KEYBOARD DATA READY; CPU-generated (80286,80386) 17 | INT 0A - IRQ2 - LPT2/EGA,VGA/IRQ9; CPU-generated (80286+) 18 | INT 0B - IRQ3 - SERIAL COMMUNICATIONS (COM2); CPU-generated (80286+) 19 | INT 0C - IRQ4 - SERIAL COMMUNICATIONS (COM1); CPU-generated (80286+) 20 | INT 0D - IRQ5 - FIXED DISK/LPT2/reserved; CPU-generated (80286+) 21 | INT 0E - IRQ6 - DISKETTE CONTROLLER; CPU-generated (80386+) 22 | INT 0F - IRQ7 - PARALLEL PRINTER 23 | INT 10 - VIDEO; CPU-generated (80286+) 24 | INT 11 - BIOS - GET EQUIPMENT LIST; CPU-generated (80486+) 25 | INT 12 - BIOS - GET MEMORY SIZE 26 | INT 13 - DISK 27 | INT 14 - SERIAL 28 | INT 15 - CASSETTE 29 | INT 16 - KEYBOARD 30 | INT 17 - PRINTER 31 | INT 18 - DISKLESS BOOT HOOK (START CASSETTE BASIC) 32 | INT 19 - SYSTEM - BOOTSTRAP LOADER 33 | INT 1A - TIME 34 | INT 1B - KEYBOARD - CONTROL-BREAK HANDLER 35 | INT 1C - TIME - SYSTEM TIMER TICK 36 | INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES 37 | INT 1E - SYSTEM DATA - DISKETTE PARAMETERS 38 | INT 1F - SYSTEM DATA - 8x8 GRAPHICS FONT 39 | INT 20 - DOS 1+ - TERMINATE PROGRAM 40 | INT 21 - DOS 1+ - Function Calls 41 | INT 22 - DOS 1+ - PROGRAM TERMINATION ADDRESS 42 | INT 23 - DOS 1+ - CONTROL-C/CONTROL-BREAK HANDLER 43 | INT 24 - DOS 1+ - CRITICAL ERROR HANDLER 44 | INT 25 - DOS 1+ - ABSOLUTE DISK READ 45 | INT 26 - DOS 1+ - ABSOLUTE DISK WRITE 46 | INT 27 - DOS 1+ - TERMINATE AND STAY RESIDENT 47 | INT 28 - DOS 2+ - DOS IDLE INTERRUPT 48 | INT 29 - DOS 2+ - FAST CONSOLE OUTPUT 49 | INT 2A - NETBIOS 50 | INT 2B - DOS 2+ - RESERVED 51 | INT 2C - DOS 2+ - RESERVED 52 | INT 2D - DOS 2+ - RESERVED 53 | INT 2E - DOS 2+ - PASS COMMAND TO COMMAND INTERPRETER FOR EXECUTION 54 | INT 2F - Multiplex 55 | INT 30 - (NOT A VECTOR!) - DOS 1+ - FAR JMP instruction 56 | INT 31 - overwritten by CP/M jump instruction in INT 30 57 | INT 32 - (no special use) 58 | INT 33 - MS MOUSE 59 | INT 34 - FLOATING POINT EMULATION - OPCODE D8h 60 | INT 35 - FLOATING POINT EMULATION - OPCODE D9h 61 | INT 36 - FLOATING POINT EMULATION - OPCODE DAh 62 | INT 37 - FLOATING POINT EMULATION - OPCODE DBh 63 | INT 38 - FLOATING POINT EMULATION - OPCODE DCh 64 | INT 39 - FLOATING POINT EMULATION - OPCODE DDh 65 | INT 3A - FLOATING POINT EMULATION - OPCODE DEh 66 | INT 3B - FLOATING POINT EMULATION - OPCODE DFh 67 | INT 3C - FLOATING POINT EMULATION - SEGMENT OVERRIDE 68 | INT 3D - FLOATING POINT EMULATION - STANDALONE FWAIT 69 | INT 3E - FLOATING POINT EMULATION - Borland "SHORTCUT" CALL 70 | INT 3F - Overlay manager interrupt (Microsoft/Borland) 71 | INT 40 - DISKETTE - RELOCATED ROM BIOS DISKETTE HANDLER 72 | INT 41 - SYSTEM DATA - HARD DISK 0 PARAMETER TABLE; CPU - MS Windows 73 | INT 42 - VIDEO - RELOCATED DEFAULT INT 10 VIDEO SERVICES (EGA,VGA) 74 | INT 43 - VIDEO DATA - CHARACTER TABLE (EGA,MCGA,VGA) 75 | INT 44 - VIDEO DATA - CHARACTER FONT (PCjr); Novell NetWare 76 | INT 45 - Z100/Acorn 77 | INT 46 - SYSTEM DATA - HARD DISK 1 DRIVE PARAMETER TABLE 78 | INT 47 - Z100/Acorn/Western Digital/SQL Base 79 | INT 48 - KEYBOARD (PCjr) - Z100/Watstar/Acorn/Western Digital/Compaq 80 | INT 49 - SYSTEM DATA (PCjr) - Z100/TI/Watstar/Acorn/MAGic 81 | INT 4A - SYSTEM - USER ALARM HANDLER 82 | INT 4B - IBM SCSI interface; Virtual DMA Specification (VDS) 83 | INT 4C - Z100/Acorn/TI 84 | INT 4D - Z100 85 | INT 4E - TI/Z100 86 | INT 4F - Common Access Method SCSI 87 | INT 50 - IRQ0 relocated by software 88 | INT 51 - IRQ1 relocated by software 89 | INT 52 - IRQ2 relocated by software 90 | INT 53 - IRQ3 relocated by software 91 | INT 54 - IRQ4 relocated by software 92 | INT 55 - IRQ5 relocated by software 93 | INT 56 - IRQ6 relocated by software 94 | INT 57 - IRQ7 relocated by software 95 | INT 58 - IRQ8/0 relocated by software 96 | INT 59 - IRQ9/1 relocated by software; GSS Computer Graphics Interface 97 | INT 5A - IRQ10/2 relocated by software 98 | INT 5B - IRQ11/3 relocated by software; Network 99 | INT 5C - IRQ12/4 relocated by software; Network Interface 100 | INT 5D - IRQ13/5 relocated by software 101 | INT 5E - IRQ14/6 relocated by software 102 | INT 5F - IRQ15/7 relocated by software; HP 95LX GRAPHICS PRIMITIVES 103 | INT 60 - reserved for user interrupt; multiple purposes 104 | INT 61 - reserved for user interrupt; multiple purposes 105 | INT 62 - reserved for user interrupt; multiple purposes 106 | INT 63 - reserved for user interrupt; multiple purposes 107 | INT 64 - reserved for user interrupt; multiple purposes 108 | INT 65 - reserved for user interrupt; multiple purposes 109 | INT 66 - reserved for user interrupt; multiple purposes 110 | INT 67 - reserved for user interrupt; LIM EMS; multiple purposes 111 | INT 68 - multiple purposes 112 | INT 69 - multiple purposes 113 | INT 6A - multiple purposes 114 | INT 6B - multiple purposes 115 | INT 6C - CONVERTIBLE; DOS 3.2; DECnet DOS network scheduler 116 | INT 6D - VGA - internal 117 | INT 6E - DECnet DOS - DECnet NETWORK PROCESS API 118 | INT 6F - Novell NetWare; 10NET; MS Windows 3.0 119 | INT 70 - IRQ8 - CMOS REAL-TIME CLOCK 120 | INT 71 - IRQ9 - REDIRECTED TO INT 0A BY BIOS 121 | INT 72 - IRQ10 - RESERVED 122 | INT 73 - IRQ11 - RESERVED 123 | INT 74 - IRQ12 - POINTING DEVICE (PS) 124 | INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION (AT and up) 125 | INT 76 - IRQ14 - HARD DISK CONTROLLER (AT and later) 126 | INT 77 - IRQ15 - RESERVED (AT,PS); POWER CONSERVATION (Compaq) 127 | INT 78 - DOS extenders; multiple purposes 128 | INT 79 - multiple purposes 129 | INT 7A - Novell NetWare; IBM 3270; multiple purposes 130 | INT 7B - multiple purposes 131 | INT 7C - multiple purposes 132 | INT 7D - multiple purposes 133 | INT 7E - RESERVED FOR DIP, Ltd. ROM LIBRARY; multiple purposes 134 | INT 7F - multiple purposes 135 | INT 80 - reserved for BASIC; multiple purposes 136 | INT 81 - reserved for BASIC 137 | INT 82 - reserved for BASIC 138 | INT 83 - reserved for BASIC 139 | INT 84 - reserved for BASIC 140 | INT 85 - reserved for BASIC 141 | INT 86 - IBM ROM BASIC - used while in interpreter; multiple purposes 142 | INT 87 - IBM ROM BASIC - used while in interpreter 143 | INT 88 - IBM ROM BASIC - used while in interpreter; multiple purposes 144 | INT 89 - IBM ROM BASIC - used while in interpreter 145 | INT 8A - IBM ROM BASIC - used while in interpreter 146 | INT 8B - IBM ROM BASIC - used while in interpreter 147 | INT 8C - IBM ROM BASIC - used while in interpreter 148 | INT 8D - IBM ROM BASIC - used while in interpreter 149 | INT 8E - IBM ROM BASIC - used while in interpreter 150 | INT 8F - IBM ROM BASIC - used while in interpreter 151 | INT 90 - IBM ROM BASIC - used while in interpreter 152 | INT 91 - IBM ROM BASIC - used while in interpreter 153 | INT 92 - IBM ROM BASIC - used while in interpreter; multiple purposes 154 | INT 93 - IBM ROM BASIC - used while in interpreter 155 | INT 94 - IBM ROM BASIC - used while in interpreter; multiple purposes 156 | INT 95 - IBM ROM BASIC - used while in interpreter 157 | INT 96 - IBM ROM BASIC - used while in interpreter 158 | INT 97 - IBM ROM BASIC - used while in interpreter 159 | INT 98 - IBM ROM BASIC - used while in interpreter 160 | INT 99 - IBM ROM BASIC - used while in interpreter 161 | INT 9A - IBM ROM BASIC - used while in interpreter 162 | INT 9B - IBM ROM BASIC - used while in interpreter 163 | INT 9C - IBM ROM BASIC - used while in interpreter 164 | INT 9D - IBM ROM BASIC - used while in interpreter 165 | INT 9E - IBM ROM BASIC - used while in interpreter 166 | INT 9F - IBM ROM BASIC - used while in interpreter 167 | INT A0 - IBM ROM BASIC - used while in interpreter 168 | INT A1 - IBM ROM BASIC - used while in interpreter 169 | INT A2 - IBM ROM BASIC - used while in interpreter 170 | INT A3 - IBM ROM BASIC - used while in interpreter 171 | INT A4 - IBM ROM BASIC - used while in interpreter 172 | INT A5 - IBM ROM BASIC - used while in interpreter 173 | INT A6 - IBM ROM BASIC - used while in interpreter 174 | INT A7 - IBM ROM BASIC - used while in interpreter 175 | INT A8 - IBM ROM BASIC - used while in interpreter 176 | INT A9 - IBM ROM BASIC - used while in interpreter 177 | INT AA - IBM ROM BASIC - used while in interpreter 178 | INT AB - IBM ROM BASIC - used while in interpreter 179 | INT AC - IBM ROM BASIC - used while in interpreter 180 | INT AD - IBM ROM BASIC - used while in interpreter 181 | INT AE - IBM ROM BASIC - used while in interpreter 182 | INT AF - IBM ROM BASIC - used while in interpreter 183 | INT B0 - IBM ROM BASIC - used while in interpreter 184 | INT B1 - IBM ROM BASIC - used while in interpreter 185 | INT B2 - IBM ROM BASIC - used while in interpreter 186 | INT B3 - IBM ROM BASIC - used while in interpreter 187 | INT B4 - IBM ROM BASIC - used while in interpreter 188 | INT B5 - IBM ROM BASIC - used while in interpreter 189 | INT B6 - IBM ROM BASIC - used while in interpreter 190 | INT B7 - IBM ROM BASIC - used while in interpreter 191 | INT B8 - IBM ROM BASIC - used while in interpreter 192 | INT B9 - IBM ROM BASIC - used while in interpreter 193 | INT BA - IBM ROM BASIC - used while in interpreter 194 | INT BB - IBM ROM BASIC - used while in interpreter 195 | INT BC - IBM ROM BASIC - used while in interpreter 196 | INT BD - IBM ROM BASIC - used while in interpreter 197 | INT BE - IBM ROM BASIC - used while in interpreter 198 | INT BF - IBM ROM BASIC - used while in interpreter 199 | INT C0 - IBM ROM BASIC - used while in interpreter 200 | INT C1 - IBM ROM BASIC - used while in interpreter 201 | INT C2 - IBM ROM BASIC - used while in interpreter 202 | INT C3 - IBM ROM BASIC - used while in interpreter 203 | INT C4 - IBM ROM BASIC - used while in interpreter 204 | INT C5 - IBM ROM BASIC - used while in interpreter 205 | INT C6 - IBM ROM BASIC - used while in interpreter 206 | INT C7 - IBM ROM BASIC - used while in interpreter 207 | INT C8 - IBM ROM BASIC - used while in interpreter 208 | INT C9 - IBM ROM BASIC - used while in interpreter 209 | INT CA - IBM ROM BASIC - used while in interpreter 210 | INT CB - IBM ROM BASIC - used while in interpreter 211 | INT CC - IBM ROM BASIC - used while in interpreter 212 | INT CD - IBM ROM BASIC - used while in interpreter 213 | INT CE - IBM ROM BASIC - used while in interpreter 214 | INT CF - IBM ROM BASIC - used while in interpreter 215 | INT D0 - IBM ROM BASIC - used while in interpreter 216 | INT D1 - IBM ROM BASIC - used while in interpreter 217 | INT D2 - IBM ROM BASIC - used while in interpreter 218 | INT D3 - IBM ROM BASIC - used while in interpreter 219 | INT D4 - IBM ROM BASIC - used while in interpreter 220 | INT D5 - IBM ROM BASIC - used while in interpreter 221 | INT D6 - IBM ROM BASIC - used while in interpreter 222 | INT D7 - IBM ROM BASIC - used while in interpreter 223 | INT D8 - IBM ROM BASIC - used while in interpreter 224 | INT D9 - IBM ROM BASIC - used while in interpreter 225 | INT DA - IBM ROM BASIC - used while in interpreter 226 | INT DB - IBM ROM BASIC - used while in interpreter 227 | INT DC - IBM ROM BASIC - used while in interpreter 228 | INT DD - IBM ROM BASIC - used while in interpreter 229 | INT DE - IBM ROM BASIC - used while in interpreter 230 | INT DF - IBM ROM BASIC - used while in interpreter 231 | INT E0 - IBM ROM BASIC - used while in interpreter; multiple purposes 232 | INT E1 - IBM ROM BASIC - used while in interpreter 233 | INT E2 - IBM ROM BASIC - used while in interpreter 234 | INT E3 - IBM ROM BASIC - used while in interpreter 235 | INT E4 - IBM ROM BASIC - used while in interpreter 236 | INT E5 - IBM ROM BASIC - used while in interpreter 237 | INT E6 - IBM ROM BASIC - used while in interpreter 238 | INT E7 - IBM ROM BASIC - used while in interpreter 239 | INT E8 - IBM ROM BASIC - used while in interpreter 240 | INT E9 - IBM ROM BASIC - used while in interpreter 241 | INT EA - IBM ROM BASIC - used while in interpreter 242 | INT EB - IBM ROM BASIC - used while in interpreter 243 | INT EC - IBM ROM BASIC - used while in interpreter 244 | INT ED - IBM ROM BASIC - used while in interpreter 245 | INT EE - IBM ROM BASIC - used while in interpreter 246 | INT EF - BASIC - ORIGINAL INT 09 VECTOR 247 | INT F0 - BASICA.COM, GWBASIC, compiled BASIC - ORIGINAL INT 08 VECTOR 248 | INT F1 - reserved for user interrupt 249 | INT F2 - reserved for user interrupt 250 | INT F3 - reserved for user interrupt 251 | INT F4 - reserved for user interrupt 252 | INT F5 - reserved for user interrupt 253 | INT F6 - reserved for user interrupt 254 | INT F7 - reserved for user interrupt 255 | INT F8 - reserved for user interrupt 256 | INT F9 - reserved for user interrupt 257 | INT FA - reserved for user interrupt 258 | INT FB - reserved for user interrupt 259 | INT FC - reserved for user interrupt 260 | INT FD - reserved for user interrupt 261 | INT FE - AT/XT286/PS50+ - destroyed by return from protected mode 262 | INT FF - AT/XT286/PS50+ - destroyed by return from protected mode 263 | -------------------------------------------------------------------------------- /inter61a/RBROWN.TXT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61a/RBROWN.TXT -------------------------------------------------------------------------------- /inter61a/README.1: -------------------------------------------------------------------------------- 1 | This is the first of six archives containing the x86/MSDOS Interrupt List, 2 | release 61. It should contain the following files: 3 | 4 | README.NOW 5 | README.1 6 | INTERRUP.A 7 | INTERRUP.B 8 | INTERRUP.C 9 | INTERRUP.D 10 | FAQ.LST 11 | OVERVIEW.LST 12 | TABLES.LST 13 | SAMPLE.FLT 14 | SAMPLE1.FLT 15 | SAMPLE2.FLT 16 | NEEDHELP.TXT 17 | RBROWN.TXT 18 | _ADVERT.TXT 19 | -------------------------------------------------------------------------------- /inter61a/README.NOW: -------------------------------------------------------------------------------- 1 | As usual, I still have a queue of unprocessed submissions.... If 2 | you've sent in any contributions which don't appear in this release but 3 | which I've acknowledged, they are still on my queue and will appear in 4 | the future. 5 | 6 | Still on the queue: more OpenDOS info, the rest of the TI Professional 7 | info, lots of chipset info (see NEEDHELP.TXT), .... 8 | 9 | 10 | UPCOMING CHANGES 11 | ================ 12 | 13 | The individual sections of the list will be larger in future releases 14 | so that there are fewer parts. I'm planning on 720K per section unless 15 | there are strong objections. 16 | 17 | 18 | WHAT'S NEW 19 | ========== 20 | 21 | INTER61 22 | ------- 23 | New files: 24 | FAQ.LST start of an FAQ -- submissions welcome! 25 | 26 | updated files: 27 | OPCODES.LST 28 | 29 | new info: 30 | over 400k of additions, including: AHA-154x commands, ATASPI, 31 | more MSRs (including AMD Athlon), lots of DR-DOS/OpenDOS/PTS-DOS/S-DOS 32 | info (with more still to be added), AMIGATSR, MULTIJOY, USB4DOS, 33 | VXDLDR, etc. 34 | 35 | Other changes: 36 | INTERxxF and INTERxxG have been merged. 37 | 38 | Note: I have deliberately omitted the usual renumbering of tables because 39 | I still have lots of pending updates referencing tables using the 40 | numbering from INTER60 (and there are no doubt some dangling 41 | cross-references due to incomplete updating). As a result, many 42 | table numbers will be out of order. 43 | 44 | 45 | INTER60 46 | ------- 47 | updated files: 48 | OPCODES.LST 49 | 50 | updated programs: 51 | INT2WHLP can now handle the new five-character table numbers 52 | 53 | new info: 54 | Econet, VESA VBE/AF, Matrox VESA-OEM functions, more Soft-ICE backdoor 55 | commands, XBIOS, EZ-Drive, Adaptec AIC-7xxx and AHA-152x ports, 56 | GEM/ViewMAX, WinTel API, TrLit API, VHRBIOS.SYS, Philips SAA7110(A), 57 | Intel 82595FX 58 | 59 | 60 | INTER59 61 | ------- 62 | format changes: 63 | all table numbers are now five characters in length, and just in time, 64 | too: PORTS.LST now has 1014 tables.... 65 | 66 | updated files: 67 | OPCODES.LST 68 | 69 | new info: 70 | chipsets: Intel 440BX/EX/LX, Intel 82371MX, OPTi "Vendetta", OPTi 71 | 82C493/82C382, Via VT82C496G "486SXWB", Via VT82C570M "Apollo Master" 72 | PicoPower Vesuvius 73 | other hardware: C&T 82C9001A, C&T 64200/64310, Ensoniq ES1370/1371, 74 | Cirrus CL-PD6710/6722, Cirrus CL-PD6729 75 | Award-BIOS password algorithm, more PCI vendor IDs 76 | 77 | -------------------------------------------------------------------------------- /inter61a/SAMPLE.FLT: -------------------------------------------------------------------------------- 1 | # Sample filtering file. Lines starting with a hash mark in the first 2 | # column are comments. Actual filtering lines start with either a dash 3 | # or a plus sign in the first column (additional modes may be added in 4 | # the future). Lines starting with a dash specify that interrupt list 5 | # entries containing that string in the first line will be omitted from 6 | # the formatted output; lines starting with a plus sign specify that 7 | # interrupt list entries containing that string are to be included in 8 | # the formatted output unless one of the minus lines matches. 9 | 10 | # Extract MS-DOS calls, but exclude DR-DOS-specific, DOS-extender, and 11 | # non-DOS networking calls. Note: a few extraneous calls are still included. 12 | # 13 | + DOS 14 | -DR DOS 15 | -DR-DOS 16 | -DR Multiuser DOS 17 | -Concurrent DOS 18 | -DOS/16M 19 | -DOS4GX 20 | -DOS/4G 21 | -extender 22 | -LAN Manager 23 | -DECnet DOS 24 | # 25 | # end of SAMPLE.FLT 26 | -------------------------------------------------------------------------------- /inter61a/SAMPLE1.FLT: -------------------------------------------------------------------------------- 1 | # SAMPLE1.FLT 2 | # Sample filtering file number 1, using only title includes/excludes. 3 | # Extract MS-DOS calls, but exclude DR-DOS-specific, DOS-extender, and 4 | # non-DOS networking calls. 5 | # Note: a few extraneous calls are still included. 6 | # 7 | + DOS 8 | -DR DOS 9 | -DR-DOS 10 | -DR Multiuser DOS 11 | -Concurrent DOS 12 | -DOS/16M 13 | -DOS4GX 14 | -DOS/4G 15 | -extender 16 | -LAN Manager 17 | -DECnet DOS 18 | # 19 | # end of SAMPLE1.FLT 20 | -------------------------------------------------------------------------------- /inter61a/SAMPLE2.FLT: -------------------------------------------------------------------------------- 1 | # SAMPLE2.FLT 2 | # Sample filtering file number 2, using category includes/excludes. Extract 3 | # MS-DOS and DR-DOS calls, but exclude OS/2 and other operating systems. 4 | # 5 | # unconditionally include the DOS category 6 | >D 7 | # include 'other OSes' category, but remove OS/2, VMiX, PC-MOS, etc. 8 | iO 9 | -OS/2 10 | -VMiX 11 | -PC-MOS 12 | -STARLITE 13 | -WinDOS 14 | -Acorn BBC 15 | -Linux DOSEMU 16 | # 17 | # end of SAMPLE2.FLT 18 | -------------------------------------------------------------------------------- /inter61a/TABLES.LST: -------------------------------------------------------------------------------- 1 | SELECTED TABLES Release 61 Last change 16jul00 2 | Copyright (c) 1989-1999,2000 Ralf Brown 3 | --------!------------------------------------ 4 | 5 | Buses 6 | EISA (see INT 15/AX=D800h) 7 | I2C / IIC bus (see I2C 00h) 8 | PCI bus -- see below 9 | System Management Bus (see INT 15/AX=53B0h/BH=01h) 10 | Universal Serial Bus OpenHCI (see #00902 at INT 1A/AX=B10Ah) 11 | 12 | Country-Specific Information: 13 | country codes (see #01400 at INT 21/AH=38h) 14 | country-specific information (see #01398,#01399) 15 | country-dependent capitalization (see INT 21/AX=6520h) 16 | code pages (see #00470,#01757) 17 | extended country-specific info (see #01750 at INT 21/AX=6500h) 18 | uppercase table (see #01751) 19 | filename uppercase table (see #01753) 20 | filename terminator table (see #01754) 21 | collating table (see #01755) 22 | DBCS lead byte table (see #01756) 23 | yes/no response (see INT 21/AX=6523h) 24 | 25 | DESQview 26 | .PIF / .DVP file format (see #00427 at INT 15/AX=102Ch) 27 | TopView panel file format (see #00436 at INT 15/AH=12h) 28 | TopView/DESQview streams (see #00446,#00447,#00448 at INT 15/AH=12h) 29 | 30 | Device Drivers 31 | command code (see #02595 at INT 2F/AX=0802h) 32 | device driver header (see #01646 at INT 21/AH=52h) 33 | device attributes (see #01647,#01648 at INT 21/AH=52h) 34 | error codes (see #02598 at INT 2F/AX=0802h) 35 | request header (see #02596 at INT 2F/AX=0802h) 36 | 37 | Disks 38 | BIOS Parameter Block (BPB) (see #01663) 39 | diskette drive type (see #00242 at INT 13/AH=08h) 40 | diskette parameter table (see #01264 at INT 1E) 41 | DOS drive parameter block (see #01357 at INT 21/AH=1Fh) 42 | DOS media ID byte (see #01356 at INT 21/AH=1Bh) 43 | hard disk master boot sector (see #00650 at INT 19) 44 | hard disk partition record (see #00651 at INT 19) 45 | IDE controller commands (see #P0515 at PORT 01F0h) 46 | Partition Types (see #00652 at INT 19) 47 | serial number (see #01565 at INT 21/AX=440Dh,#01766 at INT 21/AH=69h) 48 | 49 | DOS (general) 50 | DOS commandline (see #02585 at INT 2E) 51 | DOS Environment block (see #01378 at INT 21/AH=26h,#01395) 52 | DOS memory allocation strategy (see #01679 at INT 21/AH=58h) 53 | DOS OEM number (see #01394 at INT 21/AH=30h) 54 | 55 | DOS error codes (see INT 21/AH=59h) 56 | critical error (see #02545 at INT 24) 57 | extended error codes (see #01680) 58 | error class (see #01682) 59 | error locus (see #01684) 60 | media ID structure (see #01681) 61 | recommended action (see #01683) 62 | 63 | DOS EXEC function (see INT 21/AH=4Bh): 64 | EXEC parameter block (see #01590,#01591,#01592) 65 | .EXE file formats (see #01594,#01596,#01609,#01616) 66 | Program Segment Prefix (PSP) (see #01378 at INT 21/AH=26h) 67 | 68 | DOS extenders 69 | DPMI error codes (see #03143 at INT 21/AX=0000h) 70 | DPMI mode switch (see #02718 at INT 2F/AX=1687h) 71 | DPMI vendor-specific API (see #02719 at INT 2F/AX=168Ah) 72 | DPMS registration structure (see #02793 at INT 2F/AX=43E0h) 73 | VCPI (see INT 67/AX=DE00h) 74 | mode switch (see #03665 at INT 67/AX=DE0Ch) 75 | 76 | DOS-internal data (see INT 21/AH=52h) 77 | Current Directory Structure (see #01643,#01644,#01645) 78 | Disk buffer (see #01649,#01650,#01652,#01653,#01655) 79 | DOS Parameter List (DPL) (see #01686 at INT 21/AX=5D00h) 80 | IFS entry point (see #01658) 81 | List of Lists (SYSVARS) (see #01627) 82 | Memory Control Block (see #01628,#01630,#01633) 83 | Novell DOS (see #01584,#01585 at INT 21/AX=4458h) 84 | SHARE hooks (see #01636) 85 | Swappable Data Area (SDA) (see #01687,#01690 at INT 21/AX=5D0Bh) 86 | System File Table (SFT) (see #01639,#01640,#01641,#01642) 87 | 88 | Error Codes (Other) 89 | AMI/Award/C&T/etc. BIOS diagnostics (POST) codes (see #P0410,#P0412) 90 | Advanced Power Management [APM] (see #00473 at INT 15/AX=5300h) 91 | EMS (see #03648 at INT 67/AH=40h) 92 | PRINT.EXE (see #02594 at INT 2F/AX=0101h) 93 | XMS (see #02775 at INT 2F/AX=4310h) 94 | 95 | Files and Directories 96 | Directory Entry: MS-DOS, DR DOS, Novell DOS (see #01352) 97 | file attributes (see #01401 at INT 21/AH=3Ch) 98 | File Control Block (FCB) (see #01345 at INT 21/AH=0Fh) 99 | File Date and Time (see #01665,#01666 at INT 21/AX=5700h) 100 | file-sharing behavior (see #01403 at INT 21/AH=3Dh) 101 | FindFirst data block (see #01626 at INT 21/AH=4Eh) 102 | Long File Names (see INT 21/AH=71h,#01355 at INT 21/AH=11h) 103 | 104 | Keyboard 105 | keyboard controller commands (see #P0386,#P0401) 106 | scan codes (see #00006 at INT 09"IRQ1") 107 | shift states (see #00587,#00588 at INT 16/AH=12h) 108 | 109 | Memory 110 | memory size (see INT 12,INT 15/AH=88h,INT 15/AX=E820h) 111 | SDRAM/DIMM configuration data (see #I0047 at I2C A0h) 112 | 113 | NetWare 114 | DOS Requester entry point (see #02859 at INT 2F/AX=7A20h) 115 | error codes (see #01807 at INT 21/AH=BCh,#01811,#01834 at INT 21/AH=E1h) 116 | LSL status (see #02989 at INT 2F/AX=C000h"LSL") 117 | NetWare Core Protocol functions (see #02095 at INT 21/AH=F2h) 118 | VLM error codes (see #02860 at INT 2F/AX=7A20h) 119 | VLM header (see #02862 at INT 2F/AX=7A20h) 120 | VLM identifier (see #02861 at INT 2F/AX=7A20h) 121 | 122 | PCI Bus 123 | PCI BIOS error codes (see #00729 at INT 1A/AX=B101h) 124 | PCI configuration data (see #00878 at INT 1A/AX=B10Ah) 125 | PCI vendor ID (see #00732 at INT 1A/AX=B102h) 126 | PCI IRQ Routing Table (see #01259 at INT 1A/AX=B406h) 127 | 128 | Plug-and-Play 129 | Plug-and-Play Installation Structure (see #F0024) 130 | Plug-and-Play error codes (see #F0081) 131 | Plug-and-Play device type codes (see #F0085) 132 | Extended System Configuration Data (ESCD)(see #01244 at INT 1A/AX=B401h) 133 | generic device IDs (see #F0086) 134 | 135 | Power Management 136 | Advanced Power Management [APM] (see INT 15/AX=5300h) 137 | Advanced Configuration and Power Interface [ACPI] 138 | (see #M0094 at MEM xxxxh:xxx0h"ACPI") 139 | 140 | Real-Time Clock (see also CMOS.LST) 141 | status registers (see #00406,#00407,#00408 at INT 15/AH=01h"Amstrad") 142 | 143 | Serial Port 144 | serial port parameters (see #00300 at INT 14/AH=00h) 145 | serial line status (see #00304 at INT 14/AH=03h) 146 | modem status (see #00305 at INT 14/AH=03h) 147 | 148 | Sound 149 | Adlib/SoundBlaster registers (see #P0645 at PORT 0388h"AdLib") 150 | Gravis UltraSound 151 | registers (see #P0593 at PORT 0340h"Gravis") 152 | board version (see PORT 0746h"Gravis") 153 | MegaEm (see INT 21/AX=FD12h,#03975 at INT 81/AX=0200h) 154 | SoundBlaster SBSIM (see #03972 at INT 80"SBSIM") 155 | Windows Sound System (see #P0895 at PORT 0530h"Windows Sound") 156 | 157 | Video 158 | character attributes (see #00014 at INT 10/AH=08h) 159 | Display Combination Code (DCC) (see #00039 at INT 10/AX=1A00h) 160 | TopView/RSIS shadow buffer [virtual screen] (see INT 10/AH=FEh) 161 | VESA DDC monitor information (see #00127 at INT 10/AX=4F15h/BL=01h) 162 | VESA SuperVGA information (see #00077 at INT 10/AX=4F00h) 163 | video modes 164 | mode numbers (see #00010 at INT 10/AH=00h) 165 | UltraVision modes (see #00220 at INT 10/AX=CD04h) 166 | VESA modes (see #00083 at INT 10/AX=4F02h) 167 | video parameters (see #01263 at INT 1D) 168 | 169 | Windows 170 | Global EMM Import record (see #01515 at INT 21/AX=4402h) 171 | Startup Information Structure (see #02631 at INT 2F/AX=1605h) 172 | VMMCALL (see INT 20"Windows") 173 | VxD identifiers (see #02642 at INT 2F/AX=1684h) 174 | 175 | Other Tables 176 | AMIS signatures (see #02569,#02570 at INT 2D/AH=00h) 177 | BIOS equipment list (see #00226 at INT 11) 178 | BIOS32 Service Directory (see #F0021) 179 | Interrupt Sharing Protocol (ISP) header (see #02568 at INT 2D) 180 | Multiprocessor Specification - Floating Pointer Structure (see #M0113) 181 | Option ROM header (see #F0082) 182 | ROM configuration table (see #00509 at INT 15/AH=C0h) 183 | --------!---CONTACT_INFO--------------------- 184 | E-mail: ralf@pobox.com (currently forwards to ralf@telerama.lm.com) 185 | -------------------------------------------------------------------------------- /inter61a/_ADVERT.TXT: -------------------------------------------------------------------------------- 1 | Warning: Blatant advertisements follow 2 | 3 | Tired of wearing out printer ribbons getting a hardcopy of the interrupt 4 | list? Want the list split up by subject and thoroughly indexed? Try 5 | 6 | PC Interrupts: 7 | A Programmer's Reference to BIOS, DOS, and Third-Party Calls 8 | (second edition) 9 | Ralf Brown and Jim Kyle 10 | 1210 pages 11 | Addison-Wesley 12 | ISBN 0-201-62485-0 13 | $39.95 14 | 15 | Corresponds to the non-networking portions of INTER36 with a few of the 16 | additions from INTER37. 17 | 18 | The companion book Network Interrupts corresponds to the networking 19 | portions of INTER37 with a few of the additions from INTER38. 20 | 21 | Network Interrupts: A Programmer's Reference to Network APIs 22 | Ralf Brown and Jim Kyle 23 | 730 pages 24 | Addison-Wesley 1994 25 | ISBN 0-201-6644-6 26 | $29.95 27 | 28 | Now (December 1994) available: 29 | 30 | Uninterrupted Interrupts: A Programmer's CD-ROM Reference to 31 | Network APIs, and to the BIOS, DOS, and Third-Party Calls 32 | Ralf Brown and Jim Kyle 33 | Addison-Wesley 34 | ISBN 0-201-40966-6 35 | $49.95 36 | 37 | CD-ROM containing the full text of both PC Interrupts (2nd ed) and 38 | Network Interrupts, updated to include information added through INTER42. 39 | 40 | ------- 41 | 42 | PC Interrupts is now available in Chinese. I don't know the exact title 43 | (and couldn't reproduce it here), but it is a three-volume set which 44 | appears to be a straight translation of the Interrupt List, circa 45 | INTER26. 46 | 47 | ISBN 957-652-272-2 (INT 00h-1Fh) 516 pages, NT$ 300 48 | ISBN 957-652-271-4 (INT 20h-30h) 704 pages, NT$ 400 49 | ISBN 957-652-261-7 (INT 31h-FFh) 488 pages, NT$ 280 50 | 51 | Also available in Russian.... ISBN 5-03-002989-3 (vol. 1) 52 | ISBN 5-03-002990-7 (vol. 2) 53 | The Russian version is a translation of the first edition. 54 | 55 | ------- 56 | 57 | Undocumented DOS: 58 | A Programmer's Guide to Reserved MS-DOS Functions and Data Structures 59 | (second edition) 60 | Andrew Schulman, Ralf Brown, David Maxey, Raymond J. Michels, and 61 | Jim Kyle 62 | 63 | 880 pages, 7-3/8" x 9-1/8" 64 | Addison-Wesley 65 | ISBN 0-201-63287-X 66 | $44.95 (book and 1.44M disk) 67 | 68 | Includes a repackaged version of INTER36, script-based interrupt 69 | monitoring utility, source for a sample network redirector, discussions 70 | of TSRs/multitasking/networks/installable file systems/debugging, 71 | lots of examples, etc. 72 | 73 | Jolt Productivity Award winner, 1991 (first edition) 74 | 75 | ------- 76 | 77 | Undocumented DOS (first edition) is now also available in Chinese. 78 | ISBN 7-302-01071-4. 79 | 80 | ------- 81 | 82 | WindowBook, Inc., the folks who prepared the hypertext version for 83 | _Undocumented_DOS_, first edition, is tracking my releases of the 84 | interrupt list, and offering the WindowBook version for $39.95 ($19.95 85 | for updates). You can reach them at 800-524-0380 or 617-661-9515. Note 86 | that I have no financial interest whatsoever in WindowBook's offering, 87 | I'm just letting people know of value-added versions of the list. 88 | 89 | Window Book, Inc. 90 | 61 Howard Street 91 | Cambridge, MA 02139 92 | 93 | ------- 94 | 95 | The following books may also be of interest: 96 | 97 | DOS Internals 98 | Geoff Chappell 99 | 740 pages + 1.44M disk, $39.95 100 | Addison-Wesley 101 | ISBN 0-201-60835-9 102 | 103 | The Undocumented PC: A Programmer's Guide to I/O, CPUs, and 104 | Fixed Memory Areas 105 | Frank van Gilluwe 106 | 916 pages + 1.44M disk, $44.95 107 | Addison-Wesley 108 | ISBN 0-201-62277-7 109 | 110 | Again, I have no financial interest in the above (though I have met both 111 | authors). 112 | 113 | -------------------------------------------------------------------------------- /inter61b/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | x86/MS-DOS Interrupt List, Release 61 2 | A Comprehensive listing of interrupt 3 | calls, both documented and undocumented, 4 | plus ports/memory/CMOS/etc. Over 9600 5 | entries (plus 5400 tables) in INTER61A 6 | to INTER61D, utility programs and 7 | viewers in INTER61E, and hypertext 8 | conversion progs & WinHelp utilities in 9 | INTER60F. Over 8 million bytes of 10 | text! Released 2000/07/16. 11 | -------------------------------------------------------------------------------- /inter61b/INTERRUP.E: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61b/INTERRUP.E -------------------------------------------------------------------------------- /inter61b/README.2: -------------------------------------------------------------------------------- 1 | This is the second of six archives containing the x86/MSDOS Interrupt List, 2 | release 61. It should contain the following files: 3 | 4 | README.2 5 | INTERRUP.E 6 | INTERRUP.F 7 | INTERRUP.G 8 | INTERRUP.H 9 | INTERRUP.I 10 | GLOSSARY.LST 11 | -------------------------------------------------------------------------------- /inter61c/CATEGORY.KEY: -------------------------------------------------------------------------------- 1 | [File provided by Bent Lynggaard ] 2 | This list suggests keywords for search on different categories. More than 3 | one keyword are suggested for some categories, separated by a semicolon. 4 | 5 | --------!---CATEGORYKEYS---------------------- 6 | A - applications, a - access software;screen readers, 7 | B - BIOS;Basic In/Out System (BIOS);In/Out system (BIOS);Out/In system (BIOS), 8 | b - vendor-specific BIOS;BIOS (vendor-specific);extensions (BIOS), 9 | C - CPU-generated, c - caches;spoolers, 10 | D - DOS kernel;kernel (DOS);operating system (DOS), 11 | d - disk I/O enhancements;enhancements (disk I/O), 12 | E - DOS extenders;extenders (DOS), 13 | e - electronic mail;e-mail;mail (electronic), 14 | F - FAX;telefax, f - file manipulation, 15 | G - debuggers;debugging tools, g - games 16 | H - hardware, h - vendor-specific hardware;hardware (vendor-specific), 17 | I - IBM workstation;IBM terminal emulators, 18 | i - system info;system monitoring 19 | J - Japanese, j - joke programs, 20 | K - keyboard enhancers;enhancers (keyboard), 21 | k - file compression;compression (files), 22 | l - shells;command interpreters, 23 | M - mouse;pointing device, m - memory management, 24 | N - network, n - non-traditional input devices;special input devices, 25 | O - other operating systems;non-standard operating systems;operating systems (non-standard), 26 | P - printer enhancements;enhancements (printer), p - power management, 27 | Q - DESQview programs;TopView programs;Quarterdeck programs, 28 | R - remote control;remote file access, r - runtime support, 29 | S - serial I/O;COM port I/O, s - sound;speech, 30 | T - DOS-based task switchers;task switchers;multitaskers, 31 | t - TSR libraries 32 | U - resident utilities;utilities (resident);TSR utilities, 33 | u - emulators, 34 | V - video, v - virus;antivirus, W - MS Windows;Windows, 35 | X - expansion bus BIOSes;BIOSes (expansion bus), 36 | y - security, * - reserved 37 | -------------------------------------------------------------------------------- /inter61c/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | x86/MS-DOS Interrupt List, Release 61 2 | A Comprehensive listing of interrupt 3 | calls, both documented and undocumented, 4 | plus ports/memory/CMOS/etc. Over 9600 5 | entries (plus 5400 tables) in INTER61A 6 | to INTER61D, utility programs and 7 | viewers in INTER61E, and hypertext 8 | conversion progs & WinHelp utilities in 9 | INTER60F. Over 8 million bytes of 10 | text! Released 2000/07/16. 11 | -------------------------------------------------------------------------------- /inter61c/INTERRUP.1ST: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61c/INTERRUP.1ST -------------------------------------------------------------------------------- /inter61c/INTERRUP.K: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61c/INTERRUP.K -------------------------------------------------------------------------------- /inter61c/INTERRUP.M: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61c/INTERRUP.M -------------------------------------------------------------------------------- /inter61c/INTERRUP.PRI: -------------------------------------------------------------------------------- 1 | iAPX 86 Interrupt Primer 2 | ------------------------ 3 | 4 | by Ralf Brown 5 | 12/87 6 | Updated 6/88, 4/90, 9/92, 1/97 7 | 8 | 9 | What is an interrupt? 10 | --------------------- 11 | An interrupt is a hardware signal that tells the CPU to temporarily 12 | stop what it is doing and go do something else. Without interrupts, 13 | the CPU would have to constantly check for external events; with 14 | interrupts, the CPU can work on something else and still respond to 15 | an event as soon as it occurs. 16 | 17 | CPUs typically have an instruction to disable interrupts for use 18 | when a section of code has to run without being disturbed by 19 | external events. Because of this, most CPUs also have a special 20 | interrupt called a Non-Maskable Interrupt (NMI), which is responded 21 | to even when all other interrupts are disabled. The NMI is used to 22 | signal calamities such as memory failure or imminent power loss. 23 | 24 | Why so many different interrupts? 25 | --------------------------------- 26 | The 8086 family of processors has the ability to recognize 256 27 | different interrupts. They also have the ability to let a program 28 | invoke any of these interrupts with a special instruction, known as 29 | a software interrupt (as opposed to a hardware interrupt which is 30 | signalled from outside the processor). Software interrupts are 31 | treated just like hardware interrupts, except that they are never 32 | disabled and do not result in an acknowledgement to other chips in 33 | the computer. The software interrupt instruction on the 8086 family 34 | is called INT, and is given the number of the interrupt. Thus an 35 | INT 21h instruction invokes interrupt number 33 decimal. 36 | 37 | Other processors also have software interrupts, though they often 38 | use different names, such as the Motorola 68000 family TRAP 39 | instruction, the Intel 8080 RST (ReSTart) instruction, or many 40 | mainframes' SVC (SuperVisor Call). 41 | 42 | Since a program can invoke an interrupt by number rather than by its 43 | address (as it has to in calling subroutines), interrupts are a 44 | convenient way of providing services without having to recompile a 45 | program whenever the address of the code providing the service 46 | changes. This also allows a user program to enhance the services 47 | provided by directing the interrupt to itself. These enhanced 48 | services can then be made available to other programs. 49 | 50 | How does an interrupt work in real-address mode? 51 | ------------------------------------------------ 52 | The 8086 reserves the lowest 1024 bytes of memory for a table (IVT, 53 | Interrupt Vector Table) containing the addresses for each of the 256 54 | possible interrupts. When an interrupt occurs (hardware or 55 | software), the processor multiplies its number by 4 and looks at the 56 | resulting memory location to find the address of the piece of code 57 | which handles the interrupt. It then places the current address in 58 | the program and the processor flags on the stack, and jumps to the 59 | beginning of the interrupt handler. 60 | 61 | When the interrupt handler finishes, it invokes a special 62 | instruction to return from the interrupt. This instruction takes 63 | the previously saved flags and program address off of the stack and 64 | places them back in the appropriate registers in the CPU. 65 | 66 | The interrupt handler has to be careful to preserve any registers 67 | that it uses which are not used to communicate results to the 68 | program that invoked the interrupt. If the interrupt can be 69 | triggered by a hardware interrupt (only certain ones can on IBM 70 | PC's, XT's, and AT's), then the interrupt handler has to preserve 71 | ALL registers, since the interrupt could have happened anywhere. 72 | 73 | How does an interrupt work in protected mode? 74 | --------------------------------------------- 75 | The 80286 and later processors can also operate in protected mode, 76 | in which case the interrupt handling is somewhat different. First, 77 | the interrupt table consists of eight-byte descriptors instead of 78 | four-byte addresses, and need not be located at physical address 79 | zero, nor contain the full 256 entries (the address and size of the 80 | Interrupt Descriptor Table (IDT) may be manipulated with the LIDT 81 | and SIDT instructions). 82 | 83 | Second, in protected mode, the descriptor for an interrupt number 84 | specifies HOW control is transferred to the interrupt handler. 85 | Three types of transfer are possible: Interrupt Gate, Trap Gate, 86 | and Task Gate. The first two types transfer control to a handler 87 | running in the same process as the active program, while a Task Gate 88 | performs a complete context switch in order to invoke a handler in 89 | a different process from the active program. Interrupt and Trap 90 | gates are identical except that an Interrupt Gate will clear IF 91 | and thus disable interrupts, while a Trap Gate leaves IF unchanged. 92 | 93 | How does an interrupt work in virtual-86 (V86) mode? 94 | ---------------------------------------------------- 95 | The 80386 and later processors provide a virtual-8086 mode which is 96 | a protected mode that appears to software to be the same as Real 97 | mode. Because it is a protected mode, however, interrupts and 98 | various other actions that potentially affect system integrity do 99 | not execute directly, but instead invoke a supervisor program running 100 | in standard protected mode. Thus, whenever a program running in 101 | V86 mode invokes an interrupt call, the CPU switches to protected 102 | mode and transfers control to the interrupt handler specified by 103 | the protected-mode IDT, rather than the real-mode IVT. The 104 | supervisor program may handle the interrupt call in any way it 105 | likes, but typically switches the CPU back into V86 mode and jumps 106 | to the address specified in the real-mode IVT (a process which is 107 | known as "reflecting" the interrupt). 108 | 109 | 110 | GLOSSARY 111 | -------- 112 | API (Application Program[ming] Interface) 113 | An API is the set of function calls and services that a program 114 | makes available to other processes (applications). Each function or 115 | service has a set format which specifies the values to be supplied 116 | by the caller and the values which are returned. Because of this 117 | interface specification, the underlying organization of the function 118 | or service can be changed without affecting the applications which 119 | use it. For example, the DOS INT 21h file access functions remained 120 | unchanged between DOS 2.x and DOS 3.x, even though the internal data 121 | structures and code organization changed significantly. 122 | 123 | IDT (Interrupt Descriptor Table) 124 | 125 | IVT (Interrupt Vector Table) 126 | 127 | NMI (Non-Maskable Interrupt) 128 | Most external (hardware) interrupts can be disabled by the CLI 129 | (CLear Interrupt enable flag) instruction when the CPU is executing 130 | critical code that should not be interrupted, such as switching from 131 | one stack to another. However, there are some situations so dire 132 | that the CPU must act on them immediately no matter what else it is 133 | doing, even if it has disabled interrupts. The Non-Maskable 134 | Interrupt serves precisely this purpose, as it cannot be disabled 135 | (masked) by the CPU. 136 | -------------------------------------------------------------------------------- /inter61c/INTPRINT.COM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61c/INTPRINT.COM -------------------------------------------------------------------------------- /inter61c/README.3: -------------------------------------------------------------------------------- 1 | This is the third of six archives containing the x86/MSDOS Interrupt List, 2 | release 61. It should contain: 3 | 4 | README.3 5 | INTERRUP.1ST 6 | INTERRUP.J 7 | INTERRUP.K 8 | INTERRUP.L 9 | INTERRUP.M 10 | INTERRUP.N 11 | INTERRUP.PRI 12 | FARCALL.LST 13 | MEMORY.LST 14 | MSR.LST 15 | SMM.LST 16 | INTPRINT.COM 17 | CATEGORY.KEY 18 | -------------------------------------------------------------------------------- /inter61c/SMM.LST: -------------------------------------------------------------------------------- 1 | SYSTEM-MANAGEMENT MODE Release 61 Last change 16jul00 2 | Copyright (c) 1997,1998,1999,2000 Ralf Brown 3 | 4 | --------------------------------------------- 5 | SMM Am486 6 | 7 | Format of Am486 SMM State-Save Map: 8 | Offset Size Description (Table S0001) 9 | FE00h reserved 10 | FEE4h DWORD DR3 11 | FEE8h DWORD DR2 12 | FEECh DWORD DR1 13 | FEF0h DWORD DR0 14 | FEF4h DWORD CR2 15 | FEF8h DWORD SMM state dump base address 16 | fEFCh DWORD SMM revision ID (see #S0004) 17 | FF00h WORD I/O restart 18 | (set to 00FFh to re-execute trapped I/O) 19 | FF02h WORD halt auto restart 20 | (bit 0 set on entry if SMI during HLT) 21 | (set to 00FFh to restart from HLT) 22 | FF04h DWORD I/O trap word (see #S0002) 23 | FF08h DWORD reserved 24 | FF0Ch DWORD reserved 25 | FF10h DWORD previous EIP 26 | FF14h 5 DWORDs ??? 27 | FF28h DWORD reserved 28 | FF2Ch DWORD reserved 29 | FF30h DWORD ES limit 30 | FF34h DWORD ES base 31 | FF38h DWORD ES attributes 32 | FF3Ch DWORD CS limit 33 | FF40h DWORD CS base 34 | FF44h DWORD CS attributes 35 | FF48h DWORD SS limit 36 | FF4Ch DWORD SS base 37 | FF50h DWORD SS attributes 38 | FF54h DWORD DS limit 39 | FF58h DWORD DS base 40 | FF5Ch DWORD DS attributes 41 | FF60h DWORD FS limit 42 | FF64h DWORD FS base 43 | FF68h DWORD FS attributes 44 | FF6Ch DWORD GS limit 45 | FF70h DWORD GS base 46 | FF74h DWORD GS attributes 47 | FF78h DWORD LDT limit 48 | FF7Ch DWORD LDT base 49 | FF80h DWORD LDT attribute 50 | FF84h DWORD GDT limit 51 | FF88h DWORD GDT base 52 | FF8Ch DWORD GDT attribute 53 | FF90h DWORD IDT limit 54 | FF94h DWORD IDT base 55 | FF98h DWORD IDT attribute 56 | FF9Ch DWORD TSS limit 57 | FFA0h DWORD TSS base 58 | FFA4h DWORD TSS attribute 59 | FFA8h WORD ES 60 | FFAAh WORD unused??? 61 | FFACh WORD CS 62 | FFAEh WORD unused??? 63 | FFB0h WORD SS 64 | FFB2h WORD unused??? 65 | FFB4h WORD DS 66 | FFB6h WORD unused??? 67 | FFB8h WORD FS 68 | FFBAh WORD unused??? 69 | FFBCh WORD GS 70 | FFBEh WORD unused??? 71 | FFC0h DWORD LDTR 72 | FFC4h DWORD TR 73 | FFC8h DWORD DR7 74 | FFCCh DWORD DR6 75 | FFD0h DWORD EAX 76 | FFD4h DWORD ECX 77 | FFD8h DWORD EDX 78 | FFDCh DWORD EBX 79 | FFE0h DWORD ESP 80 | FFE4h DWORD EBP 81 | FFE8h DWORD ESI 82 | FFECh DWORD EDI 83 | FFF0h DWORD EIP 84 | FFF4h DWORD EFLAGS 85 | FFF8h DWORD CR3 86 | FFFCh DWORD CR0 87 | SeeAlso: #S0003 88 | 89 | Bitfields for AMD Am486 I/O trap word: 90 | Bit(s) Description (Table S0002) 91 | 31-16 I/O address 92 | 15-2 reserved 93 | 1 valid I/O instruction 94 | 0 direction 95 | SeeAlso: #S0001 96 | --------------------------------------------- 97 | SMM AMD-K5 98 | 99 | Format of AMD K5 SMM State-Save Area: 100 | Offset Size Description (Table S0003) 101 | FE00h reserved 102 | FEF8h DWORD SMM base address 103 | (may be set to any multiple of 32K; initially 00030000h) 104 | FEFCh DWORD SMM revision identifier (see #S0004) 105 | FF00h WORD I/O trap restart slot (see #S0007) 106 | FF02h WORD HLT restart slot (see #S0005) 107 | FF04h DWORD I/O restart EDI 108 | FF08h DWORD I/O restart ECX 109 | FF0Ch DWORD I/O restart ESI 110 | FF10h DWORD CR4 111 | FF14h DWORD CR2 112 | FF18h 3 DWORDs reserved 113 | FF24h DWORD ES limit 114 | FF28h DWORD ES base 115 | FF2Ch DWORD ES attributes 116 | FF30h DWORD CS limit 117 | FF34h DWORD CS base 118 | FF38h DWORD CS attributes 119 | FF3Ch DWORD SS limit 120 | FF40h DWORD SS base 121 | FF44h DWORD SS attributes 122 | FF48h DWORD DS limit 123 | FF4Ch DWORD DS base 124 | FF50h DWORD DS attributes 125 | FF54h DWORD FS limit 126 | FF58h DWORD FS base 127 | FF5Ch DWORD FS attributes 128 | FF60h DWORD GS limit 129 | FF64h DWORD GS base 130 | FF68h DWORD GS attributes 131 | FF6Ch DWORD LDT limit 132 | FF70h DWORD LDT base 133 | FF74h DWORD LDT attributes 134 | FF78h DWORD TSS limit 135 | FF7Ch DWORD TSS base 136 | FF80h DWORD TSS attributes 137 | FF84h DWORD GDT limit 138 | FF88h DWORD GDT base 139 | FF8Ch DWORD IDT limit 140 | FF90h DWORD IDT base 141 | FF94h 2 DWORDs reserved 142 | FF9Ch DWORD I/O trap EIP 143 | FFA0h DWORD reserved 144 | FFA4h DWORD I/O trap DWORD (see #S0006) 145 | FFA8h WORD ES 146 | FFAAh WORD unused??? 147 | FFACh WORD CS 148 | FFAEh WORD unused??? 149 | FFB0h WORD SS 150 | FFB2h WORD unused??? 151 | FFB4h WORD DS 152 | FFB6h WORD unused??? 153 | FFB8h WORD FS 154 | FFBAh WORD unused??? 155 | FFBCh WORD GS 156 | FFBEh WORD unused??? 157 | FFC0h DWORD LDTR 158 | FFC4h DWORD TR 159 | FFC8h DWORD DR7 160 | FFCCh DWORD DR6 161 | FFD0h DWORD EAX 162 | FFD4h DWORD ECX 163 | FFD8h DWORD EDX 164 | FFDCh DWORD EBX 165 | FFE0h DWORD ESP 166 | FFE4h DWORD EBP 167 | FFE8h DWORD ESI 168 | FFECh DWORD EDI 169 | FFF0h DWORD EIP 170 | FFF4h DWORD EFLAGS 171 | FFF8h DWORD CR3 172 | FFFCh DWORD CR0 173 | SeeAlso: #S0001 174 | 175 | Bitfields for AMD K5 SMM Revision Identifier: 176 | Bit(s) Description (Table S0004) 177 | 31-18 reserved (0) 178 | 17 SMM base address relocation available (always 1 [enabled] on K5) 179 | 16 I/O trap restart supported (always 1 on K5) 180 | 15-0 SMM revision level (currently 0000h) 181 | SeeAlso: #S0003 182 | 183 | Bitfields for AMD K5 Halt Restart Slot: 184 | Bit(s) Description (Table S0005) 185 | 15-1 undefined 186 | 0 (on SMM entry) entered SMM from Halt state 187 | (at RSM) return to Halt state instead of state in SMM state-save area 188 | SeeAlso: #S0003 189 | 190 | Bitfields for AMD K5 I/O Trap DWORD: 191 | Bit(s) Description (Table S0006) 192 | 31-16 I/O port address 193 | 15 I/O was string operation (INS,OUTS,etc.) 194 | 14-2 reserved 195 | 1 valid I/O instruction 196 | 0 direction (0 = output, 1 = input) 197 | SeeAlso: #S0003,#S0007 198 | 199 | Bitfields for AMD K5 I/O Trap Restart Slot: 200 | Bit(s) Description (Table S0007) 201 | 31-16 reserved 202 | 15-0 I/O instruction restart on RSM 203 | 0000h resume at next instruction following trapped I/O instruction 204 | (default on SMM entry) 205 | 00FFh re-execute the trapped I/O instruction 206 | Note: before changing the restart value, check that the I/O instruction is 207 | actually valid (see #S0006) 208 | SeeAlso: #S0003,#S0006 209 | --------------------------------------------- 210 | SMM Pentium 211 | 212 | Format of Pentium State Dump record: 213 | Offset Size Description (Table S0008) 214 | FE00h 248 BYTEs officially reserved, actually unused 215 | FEF8h DWORD state dump base address (must be multiple of 32K) 216 | FEFCh DWORD SMM revision identifier 217 | bits 15-0: SMM revision level 218 | bit 16: I/O trap extension is present (offset FF00h) 219 | bit 17: SMM base relocation supported (offset FEF8h) 220 | bits 31-18: reserved 221 | FF00h WORD I/O Trap restart 222 | (set to 00FFh to re-execute trapped I/O) 223 | FF02h WORD Halt auto-restart 224 | (bit 0 set on entry if SMI during HLT; if handler clears it, 225 | the CPU returns to the instruction after the interrupted HLT 226 | rather than to the HLT instruction) 227 | FF04h DWORD (undoc) I/O restart EDI / CR0 228 | FF08h DWORD (undoc) I/O restart ECX 229 | FF0Ch DWORD (undoc) I/O restart ESI 230 | FF10h DWORD (undoc) I/O restart EIP 231 | FF14h 16 BYTEs unused 232 | FF24h WORD (undoc) alternate DR6 233 | FF26h WORD (undoc) RSM control 234 | if bit 0 set on return, the low word of DR6 is loaded from FF26h 235 | instead of FFCCh 236 | FF28h DWORD (undoc) CR4 237 | FF2Ch DWORD unused 238 | FF30h 12 BYTEs (undoc) ES descriptor cache 239 | DWORD limit 240 | DWORD base address 241 | DWORD type 242 | FF3Ch 12 BYTEs (undoc) CS descriptor cache 243 | FF48h 12 BYTEs (undoc) SS descriptor cache 244 | FF54h 12 BYTEs (undoc) DS descriptor cache 245 | FF60h 12 BYTEs (undoc) FS descriptor cache 246 | FF6Ch 12 BYTEs (undoc) GS descriptor cache 247 | FF78h 12 BYTEs (undoc) LDT descriptor cache 248 | FF84h 12 BYTEs (undoc) GDT descriptor cache 249 | FF90h 12 BYTEs (undoc) IDT descriptor cache 250 | FF9Ch 12 BYTEs (undoc) TSS descriptor cache 251 | FFA8h WORD ES 252 | FFAAh WORD reserved 253 | FFACh WORD CS 254 | FFAEh WORD reserved 255 | FFB0h WORD SS 256 | FFB2h WORD reserved 257 | FFB4h WORD DS 258 | FFB6h WORD reserved 259 | FFB8h WORD FS 260 | FFBAh WORD reserved 261 | FFBCh WORD GS 262 | FFBEh WORD reserved 263 | FFC0h DWORD LDTR 264 | FFC4h DWORD TR 265 | FFC8h DWORD DR7 266 | FFCCh DWORD DR6 267 | FFD0h DWORD EAX 268 | FFD4h DWORD ECX 269 | FFD8h DWORD EDX 270 | FFDCh DWORD EBX 271 | FFE0h DWORD ESP 272 | FFE4h DWORD EBP 273 | FFE8h DWORD ESI 274 | FFECh DWORD EDI 275 | FFF0h DWORD EIP 276 | FFF4h DWORD EFLAGS 277 | FFF8h DWORD CR3 278 | FFFCh DWORD CR0 279 | SeeAlso: #S0003 280 | --------!---Admin---------------------------- 281 | Highest Table Number = S0008 282 | --------!---FILELIST------------------------- 283 | Please redistribute all of the files comprising the interrupt list (listed at 284 | the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a 285 | quartet of archives named INTER61A through INTER61D (preferably the original 286 | authenticated PKZIP archives), and the utility and hypertext conversion 287 | programs in two additional archives called INTER61E.ZIP and INTER61F.ZIP. 288 | 289 | Copyright (c) 1989-1999,2000 Ralf Brown 290 | --------!---CONTACT_INFO--------------------- 291 | E-mail: ralf@pobox.com (currently forwards to ralf@telerama.lm.com) 292 | -------------------------------------------------------------------------------- /inter61d/86BUGS.DOC: -------------------------------------------------------------------------------- 1 | Hamarsoft (R) 86BUGS list, supplemental programs. 2 | The 86BUGSxy archive should contain the following files: 3 | 4 | - 86BUGS.HLP Microsoft QuickHelp hypertext version of the list. 5 | - 86LISTnn.LST The text version of the 86BUGS list. 6 | - FILE_ID.DIZ An upload description for Bulletin Boards. 7 | - iAPX122.ZIP Testing software archive from Chris Lueders, Germany. 8 | - INFO.EXE CPU info program with various information regarding your 9 | processor. 10 | - STAT.EXE Pentium Processor Pipeline & features performance monitor. 11 | 12 | Both STAT and INFO are provided by Christian Ludloff. These programs are 13 | based on his article in the german C't Magazine of November 1994 (issue 11). 14 | 15 | iAPX122 is a testing program provided by Chris Lueders. It tests for some 16 | of the bugs mentioned in the 86BUGS list. 17 | 18 | All programs are provided with this list as a service from Hamarsoft to the 19 | readers of the 86BUGS list. Hamarsoft does not accept any liability for 20 | these programs whatsoever. 21 | 22 | The 86BUGS list is also distributed with Ralf Brown's Interrupt List. 23 | 24 | [86BUGS.HLP has been omitted for space reasons, and the other files except 25 | for 86LISTnn.LST are located in INTERrrD.ZIP. 86LISTnn.LST has been 26 | renamed to 86BUGS.LST for compatibility with hypertext conversion 27 | programs expecting that name.] 28 | -------------------------------------------------------------------------------- /inter61d/86BUGS.LST: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61d/86BUGS.LST -------------------------------------------------------------------------------- /inter61d/COMBINE.COM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61d/COMBINE.COM -------------------------------------------------------------------------------- /inter61d/COMBINE.DOC: -------------------------------------------------------------------------------- 1 | COMBINE.COM v2.10 2 | by Ralf Brown 3 | 22 March 1998 4 | 5 | COMBINE.COM will concatenate all of the partial files in the interrupt 6 | list distribution archives into a single master file for interrupts and 7 | a single master file for I/O ports, which is required by some viewers 8 | and hypertext conversion programs. 9 | 10 | To use COMBINE, just change to the directory into which you extracted 11 | the distribution archives, and type 12 | 13 | COMBINE {dir} (for interrupts) 14 | and then 15 | COMBINE -p {dir} (for ports) 16 | 17 | where {dir} is the name of the directory in which you want the combined 18 | list to be stored (typically, you will type "COMBINE ." to store the 19 | result in the same directory as the individual sections). If there is 20 | not enough free disk space to hold both the individual sections and the 21 | combined list, you will be told and given the option of running COMBINE 22 | again with an option to tell it that it should delete each section as 23 | it is added to the combined file: 24 | 25 | COMBINE -d {dir} 26 | 27 | COMBINE will skip any missing sections of the interrupt list; if at 28 | least one section other than INTERRUP.A (PORTS.A with -p) is present, 29 | it will stop as soon as the last section has been processed (otherwise, 30 | it will continue trying all names through INTERRUP.Z/PORTS.Z). On 31 | completion, it sets the combined file's timestamp to be the same as 32 | that of the last of the individual sections. 33 | 34 | System Requirements: 35 | DOS 2.0+ or a DOS compatibility box 36 | 64K available RAM 37 | a copy of the interrupt list :-) 38 | sufficient free disk space (~360K with the -d option) 39 | -------------------------------------------------------------------------------- /inter61d/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | x86/MS-DOS Interrupt List, Release 61 2 | A Comprehensive listing of interrupt 3 | calls, both documented and undocumented, 4 | plus ports/memory/CMOS/etc. Over 9600 5 | entries (plus 5400 tables) in INTER61A 6 | to INTER61D, utility programs and 7 | viewers in INTER61E, and hypertext 8 | conversion progs & WinHelp utilities in 9 | INTER60F. Over 8 million bytes of 10 | text! Released 2000/07/16. 11 | -------------------------------------------------------------------------------- /inter61d/INTPRINT.DOC: -------------------------------------------------------------------------------- 1 | INTPRINT v3.11 2 | by Ralf Brown 3 | 4 | The INTPRINT program is hereby donated to the public domain, with the sincere 5 | hope that proper credit will be retained in all copies and derivatives. 6 | 7 | ------------------------------------------------------------------------------ 8 | 9 | INTPRINT.COM is a simple formatter for the interrupt list, both 10 | INTERRUP.LST and the other *.LST files. Use this program to print only 11 | a portion of the list, prevent widow lines at the beginning of a 12 | function call, number the pages, boldface key portions, center the 13 | printout, or create a summary of the function calls. After formatting 14 | is complete, the total number of pages is displayed on the screen. 15 | 16 | Usage: 17 | intprint [options] intlist [[>|>>]outfile] 18 | 19 | where the options are: 20 | -b boldface the title lines, Return:, and Notes: by overprinting 21 | -B boldface by sending printer control sequences 22 | 23 | -d (duplex) print even/odd pages with different margins; suitable 24 | for binding the printout. 25 | 26 | -e assume printer is in elite mode (96 characters per line), and 27 | indent the output eight spaces to center the printout. This 28 | is primarily for the default printer, as other printers may 29 | force the equivalent or override this option. 30 | 31 | -ffile create a file containing only the data structures described 32 | in the interrupt list. 33 | NOTE: you must put the filename immediately after the 'f'; no 34 | blanks are allowed. 35 | 36 | -Ffile filter the listing based on include and exclude strings 37 | in 'file'. Only entries whose headers match none of the 38 | exclude strings and at least one of the include strings 39 | will be processed. All others will be skipped. 40 | NOTE: you must put the filename immediately after the 'F'; no 41 | blanks are allowed. 42 | 43 | -H print a heading on each page indicating which interrupts 44 | are listed on the page 45 | 46 | -iN indent the output N spaces. The output device is assumed to be 47 | at least 80+N characters wide. 48 | NOTE: you must put the number immediately after the 'i'; no 49 | blanks are allowed. 50 | 51 | -I assume the printer is capable of producing IBM character 52 | graphics. Printers other than "default" may force this option. 53 | 54 | -k keep original divider lines instead of replacing them 55 | with all dashes. 56 | 57 | -lN print N lines per pages, overriding the printer-specific 58 | default. Use 0 to omit page breaks (in this case, the 59 | reported number of pages and -r page restriction may be 60 | incorrect unless you also use -L); this can be useful if 61 | you only want to filter the list before processing it 62 | further. 63 | 64 | -LN assume N lines on a page. If this is more than the number of 65 | lines to print on each page, INTPRINT will use line feeds to 66 | advance to the next page instead of form feeds. 67 | 68 | -m specify that the interrupt list is in multiple parts beginning 69 | with the named file. INTPRINT will increment the last 70 | character of the name to get the next filename, and continue 71 | until it is unable to open the file thus selected. 72 | 73 | -nN assume N pages have already been printed, and start numbering 74 | at N+1. This option allows you to create a properly-numbered 75 | printout even if there is not enough disk space to concatenate 76 | the parts of the interrupt list or hold a complete output file. 77 | See the examples below. 78 | NOTE: you must put the number immediately after the 'n'; no 79 | blanks are allowed. 80 | 81 | -p print the page number at the bottom center of each page 82 | 83 | -Pname use control codes for the specified printer (-P? lists the 84 | supported printers). The printer name may be given in either 85 | case and abbreviated to a unique prefix; use either dashes or 86 | underscores in place of blanks in the printer name. 87 | 88 | -rN:M print only pages N through M. The entire input is processed 89 | for use in -s and -f summaries (see below) even though only 90 | a portion is formatted for printing. If filtering is enabled, 91 | (see -F), page numbers are based on entries selected by the 92 | filter file. 93 | NOTE: you must put the page numbers immediately after the 'r'; 94 | no blanks are allowed. When using -l0 together with -r, 95 | you must specify the appropriate page length with -L so 96 | that page numbers can be computed correctly. 97 | 98 | -sfile create a one-line-per-function summary and write it to "file" 99 | if -n is also given, the summary will be appended to "file", 100 | allowing a properly numbered summary file to be created even if 101 | there is not enough disk space to concatenate the parts of the 102 | list. See the examples below. If -p is also given, page 103 | numbers will be included in the summary. If -V is also given, 104 | byte offsets for use by INTERVUE will be included. 105 | NOTE: you must put the filename immediately after the 's'; no 106 | blanks are allowed. 107 | 108 | -tN select typeface N for the chosen printer (currently supported 109 | only for the HP). 110 | 111 | -Tfile create a one-line-per-table summary and write it to "file" 112 | if -n is also given, the summary will be appended to the named 113 | file. If -p is also given, page numbers will be included in 114 | the summary. If -V is also given, byte offsets for use by 115 | INTERVUE will be included. 116 | NOTE: you must put the filename immediately after the 'T'; no 117 | blanks are allowed. 118 | 119 | -V indicate that the summary file is intended for use by INTERVUE. 120 | INTPRINT will output byte offsets that allow INTERVUE to jump 121 | directly to an entry. Also forces -I. 122 | 123 | -wN (widow lines) search N lines from the end of the page for a 124 | good place to break. The default is eight lines; the valid 125 | range is from 3 to one-half of the page length. 126 | NOTE: you must put the number immediately after the 'w'; no 127 | blanks are allowed. 128 | 129 | -x include Index: lines in formatted listing. These lines are 130 | are excluded by default because they are intended primarily 131 | for use by hypertext converters. 132 | 133 | Options may not be merged; "-ep" is illegal and the "p" will be ignored. 134 | Use "-e -p" instead. 135 | 136 | The formatted result of the input file is sent to the specified output file, 137 | or to standard output if no output file is given. Standard output may be 138 | redirected using the usual Unix or MSDOS redirection characters > or >>. If 139 | you only want a summary file or data formats file, send or redirect the 140 | output to the null device ("NUL" under MSDOS, "/dev/null" under Unix). 141 | 142 | 143 | FILTER FILE: 144 | ------------ 145 | 146 | The filter file specified with -F is a simple text file containing 147 | include lines, exclude lines, and comment lines. Both 'include' and 148 | 'exclude' lines may be based on either a category code or a substring 149 | of the entry's title line. Comment lines start with a hash mark (#) in 150 | the first column and are ignored. The other valid command characters 151 | in the first column are: 152 | 153 | > unconditionally include any entry with the specified category letter 154 | < unconditionally exclude any entry with the specified category letter 155 | + include entries containing the specified string, unless unconditionally 156 | excluded 157 | - exclude entries containing the specified string, unless unconditionally 158 | included 159 | i include entries with the given category letter unless specifically 160 | excluded by a '-' line 161 | o override '-' line and include entry anyway if it has the given 162 | category letter 163 | 164 | Note that any category letters or selection strings must immediately 165 | follow the command character. All spaces on '+' include and '-' exclude 166 | lines are significant. Thus, 167 | + DOS 168 | will only match entries containing the four-letter sequence " DOS", 169 | while 170 | +DOS 171 | will match any entries containing the sequence "DOS", whether or not it 172 | is preceded by a blank. 173 | 174 | If a filter file is specified, only entries whose title lines contain at 175 | least one of the '+' include lines (ignoring uppercase/lowercase 176 | distinctions), none of the '-' exclude lines, or whose category codes 177 | have been selected by other include/exclude lines, are processed. Thus, 178 | a filter file must contain at least one include line, or INTPRINT will 179 | skip all interrupt entries and print only the non-interrupt text in the 180 | file. 181 | 182 | ----cut here---- 183 | # SAMPLE1.FLT 184 | # Sample filtering file number 1, using only title includes/excludes. 185 | # Extract MS-DOS calls, but exclude DR-DOS-specific, DOS-extender, and 186 | # non-DOS networking calls. 187 | # Note: a few extraneous calls are still included. 188 | # 189 | + DOS 190 | -DR DOS 191 | -DR-DOS 192 | -DR Multiuser DOS 193 | -Concurrent DOS 194 | -DOS/16M 195 | -DOS4GX 196 | -DOS/4G 197 | -extender 198 | -LAN Manager 199 | -DECnet DOS 200 | # 201 | # end of SAMPLE1.FLT 202 | ----cut here---- 203 | 204 | ----cut here---- 205 | # SAMPLE2.FLT 206 | # Sample filtering file number 2, using category includes/excludes. Extract 207 | # MS-DOS and DR-DOS calls, but exclude OS/2 and other operating systems. 208 | # 209 | # unconditionally include the DOS category 210 | >D 211 | # include 'other OSes' category, but remove OS/2, VMiX, PC-MOS, etc. 212 | iO 213 | -OS/2 214 | -VMiX 215 | -PC-MOS 216 | -STARLITE 217 | -WinDOS 218 | -Acorn BBC 219 | -Linux DOSEMU 220 | # 221 | # end of SAMPLE2.FLT 222 | ----cut here---- 223 | 224 | ------------------------------------------------------------------------------ 225 | 226 | EXAMPLES: 227 | --------- 228 | 229 | Print the interrupt list with page numbers, and create a summary file, 230 | without concatenating INTERRUP.A, INTERRUP.B, and INTERRUP.C: 231 | 232 | A> intprint -sb:interrup.sum -p interrup.a >prn 233 | 146 pages [screen output from INTPRINT] 234 | A> intprint -sb:interrup.sum -p -n146 interrup.b prn 235 | 285 pages [screen output from INTPRINT] 236 | A> intprint -sb:interrup.sum -p -n285 interrup.c >prn 237 | 403 pages [screen output from INTPRINT] 238 | 239 | or, more easily: 240 | A> intprint -sb:interrup.sum -m -p interrup.a prn 241 | 1587 pages [screen output from INTPRINT] 242 | 243 | Create only a summary file: 244 | 245 | C> intprint -sinterrupt.sum interrup.lst nul 246 | 247 | Create a listing of the tables in the interrupt list: 248 | 249 | C> intprint -Tinterrup.tbl interrup.lst nul 250 | 251 | Print only those entries containing the string "DOS", except 252 | those containing the string "DR-DOS" 253 | 254 | C> type dos 255 | +DOS 256 | -DR-DOS 257 | 258 | C> intprint -Fdos interrup.lst nul 259 | 260 | 261 | Print the interrupt list on an Epson FX80, using 54 lines per page and 262 | omitting both page numbers and summary: 263 | 264 | C> intprint -Pepson -l54 interrup.lst >prn 265 | 266 | Print the interrupt list using 120 lines on every 132-line page (using 267 | superscript mode, for example), and make divider lines using IBM 268 | character graphics: 269 | 270 | C> intprint -I -l120 -L132 interrup.lst >prn 271 | 272 | Print only pages 123 through 127, assuming that 106 pages are contained 273 | in the first section of the list: 274 | 275 | C> intprint -n106 -r123:127 interrup.b prn 276 | 277 | Print using HP PCL4/5 escape sequences, numbering pages, from file 278 | "interrup.lst" to file "interrup.pcl", at the default 69 lines per 279 | page, using form-feeds: 280 | 281 | C> intprint -Php -p interrup.lst >interrup.pcl 282 | 1587 pages [screen output from INTPRINT] 283 | 284 | ------------------------------------------------------------------------------ 285 | 286 | PORTABILITY: 287 | ------------ 288 | 289 | INTPRINT.C contains the source code for INTPRINT, for those people who 290 | are using the interrupt list on a machine which does not run MSDOS. 291 | This code has been tested with Turbo C v2.0, Borland C++ v3.1, and Mach 292 | (BSD 4.3 Unix) "cc" and "gcc". 293 | 294 | -------------------------------------------------------------------------------- /inter61d/PGP-SIGS.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61d/PGP-SIGS.ZIP -------------------------------------------------------------------------------- /inter61d/PORTS.A: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61d/PORTS.A -------------------------------------------------------------------------------- /inter61d/PORTS.B: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61d/PORTS.B -------------------------------------------------------------------------------- /inter61d/README.4: -------------------------------------------------------------------------------- 1 | This is the fourth of six archives containing the x86/MSDOS Interrupt List, 2 | release 61. It should contain: 3 | 4 | README.4 5 | INTERRUP.O 6 | INTERRUP.P 7 | INTERRUP.Q 8 | INTERRUP.R 9 | 86BUGS.LST 10 | BIBLIO.LST 11 | CMOS.LST 12 | I2C.LST 13 | OPCODES.LST 14 | PORTS.A 15 | PORTS.B 16 | PORTS.C 17 | 86BUGS.DOC 18 | COMBINE.COM 19 | COMBINE.DOC 20 | INTPRINT.DOC 21 | PGP-SIGS.ZIP 22 | -------------------------------------------------------------------------------- /inter61e/86BUGS04.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/86BUGS04.ZIP -------------------------------------------------------------------------------- /inter61e/COMBINE.ASM: -------------------------------------------------------------------------------- 1 | ; COMBINE.ASM Interrupt List combiner 2 | ; by Ralf Brown 3 | ; last edit: 22mar98 4 | 5 | NAME COMBINE 6 | TITLE Combine Interrupt List sections 7 | 8 | ; declare all the segments in the order in which they are to appear in the 9 | ; executable 10 | CODE SEGMENT 'CODE' 11 | CODE ENDS 12 | STACKSEG SEGMENT PUBLIC WORD 'STACK' 13 | STACKSEG ENDS 14 | BUFFERSEG SEGMENT PUBLIC WORD 'DATA' 15 | BUFFERSEG ENDS 16 | ; 17 | DGROUP GROUP CODE,STACKSEG,BUFFERSEG 18 | 19 | ;;------------------------------------------------------------------------ 20 | 21 | FFBLK struc 22 | ff_reserved db 15h dup (?) 23 | ff_attrib db ? 24 | ff_ftime dw ? 25 | ff_fdate dw ? 26 | ff_fsize dd ? 27 | ff_fname db 13 dup (?) 28 | FFBLK ends 29 | 30 | ;;------------------------------------------------------------------------ 31 | 32 | CODE SEGMENT 'CODE' 33 | ORG 100h ; this is a .COM file 34 | ASSUME CS:DGROUP,DS:DGROUP,ES:DGROUP,SS:DGROUP 35 | 36 | combine: 37 | jmp near ptr main 38 | 39 | banner db 13,"COMBINE v2.10",9,"Ralf Brown 1996,1998",13,10,"$",26 40 | usage_msg db "Usage:",9,"COMBINE [options] dest-dir",13,10 41 | db 9,"where {dest-dir} is the directory in which to place",13,10 42 | db 9," the combined list ('.' for the current directory)",13,10 43 | db 10 44 | db 9,"options:",13,10 45 | db 9,9,"-d",9,"delete sections after copying",13,10 46 | db 9,9,"-p",9,"combine PORTS.LST instead of INTERRUP.LST",13,10 47 | db 10 48 | db "All sections of the interrupt/ports list must be in the current directory." 49 | db "$" 50 | 51 | bad_dos_msg db "Need DOS 2.0+$" 52 | bad_drive_msg db "Invalid destination drive$" 53 | no_mem_msg db "Insufficient memory$" 54 | no_files_msg db "No section files found!$" 55 | readerr_msg db "Read Error$" 56 | writeerr_msg db "Write Error$" 57 | diskfull_msg db "Disk full? while writing$" 58 | no_disk_msg db "Out of space on destination drive",13,10,"$" 59 | retry_msg db "Try again with -d to delete while copying$" 60 | 61 | cant_create_msg db "Check directory name -- unable to create " 62 | combined_file db "INTERRUP.LST",0,"$" 63 | combined_file2 db "PORTS.LST",0 64 | combined_file2_len equ $-combined_file2 65 | section_file1 db "INTERRUP.A",0,"$" 66 | section_letter equ section_file1+9 67 | section_file2 db " PORTS" 68 | section_file2_len equ $-section_file2 69 | section_file2_ofs equ 3 70 | missing_msg db "unavailable (skipped)" 71 | crlf db 13,10,"$" 72 | section_heading1 db "Interrupt List, part " 73 | section_hdr_len1 equ $-section_heading1 74 | section_heading2 db "Ports List, part " 75 | section_hdr_len2 equ $-section_heading2 76 | complete_msg db "Done.$" 77 | 78 | ; 79 | ; flags affecting operation 80 | ; 81 | del_after_copy db 0 82 | section_file dw offset section_file1 83 | section_heading dw offset section_heading1 84 | section_hdr_len dw section_hdr_len1 85 | 86 | ; 87 | ; data needed while processing 88 | ; 89 | filehandle equ di ; output file's handle 90 | numsections db 26 91 | dest_drive db 0 92 | nondefault_dest db 0 93 | ftime dw 0 94 | fdate dw 0 95 | filesize_lo dw 0 96 | filesize_hi equ bp 97 | 98 | ; (since we don't use disk_buffer until after FindFirst is no longer needed, 99 | ; save memory by overlaying the two) 100 | FindFirst equ DGROUP:disk_buffer 101 | 102 | ;;------------------------------------------------------------------------ 103 | 104 | write_string: 105 | mov ah,9 106 | int 21h 107 | ret 108 | 109 | ;;------------------------------------------------------------------------ 110 | 111 | skip_whitespace: 112 | lodsb 113 | cmp al,' ' 114 | je skip_whitespace 115 | cmp al,9 116 | je skip_whitespace 117 | dec si ; unget the last character 118 | ; set ZF to indicate whether we got to end of cmdline 119 | cmp al,0Dh 120 | ret 121 | 122 | ;;------------------------------------------------------------------------ 123 | 124 | get_destination_file: 125 | mov bx,si ; remember start of destination name 126 | get_dest_file_loop: 127 | lodsb 128 | cmp al,' ' 129 | je got_dest_end 130 | cmp al,9 131 | je got_dest_end 132 | cmp al,0Dh 133 | jne get_dest_file_loop 134 | got_dest_end: 135 | dec si ; unget last character 136 | mov di,si 137 | mov al,[si-1] ; check end of path -- is it terminated 138 | cmp al,'\' ; by a slash or backslash? 139 | je dest_has_slash 140 | cmp al,'/' 141 | je dest_has_slash 142 | cmp al,':' 143 | je dest_has_slash 144 | mov al,'\' 145 | stosb 146 | dest_has_slash: 147 | mov si,offset combined_file 148 | dest_copy_loop: 149 | lodsb 150 | stosb 151 | cmp al,0 152 | jne dest_copy_loop 153 | ; OK, now open the destination file 154 | ; (BX is still pointing at start of pathname) 155 | cmp byte ptr [bx+1],':' 156 | jne got_dest_drive 157 | mov al,[bx] 158 | and al,0DFh ; force to uppercase 159 | sub al,'A' 160 | jb got_dest_drive 161 | cmp al,dest_drive 162 | je got_dest_drive 163 | mov dest_drive,al 164 | mov nondefault_dest,al 165 | got_dest_drive: 166 | mov ah,3Ch ; create the output file 167 | xor cx,cx ; no special file attributes 168 | mov dx,bx 169 | int 21h 170 | mov dx,offset cant_create_msg 171 | jc exit_with_err_2 172 | mov filehandle,ax 173 | ret 174 | 175 | ;;------------------------------------------------------------------------ 176 | 177 | check_total_size: 178 | mov byte ptr section_letter,'A'-1 179 | mov ah,1Ah ; set DTA 180 | mov dx,offset FindFirst 181 | int 21h 182 | xor si,si ; keep track of # of sections found 183 | check_size_loop: 184 | inc byte ptr section_letter 185 | cmp byte ptr section_letter,'Z' 186 | ja short get_free_space 187 | mov ah,4Eh ; find first 188 | mov cx,001Fh ; ...regardless of attribute 189 | mov dx,section_file 190 | int 21h 191 | jc check_size_loop 192 | inc si ; another section found 193 | mov ax,FindFirst.ff_ftime 194 | mov ftime,ax 195 | mov ax,FindFirst.ff_fdate 196 | mov fdate,ax 197 | mov ax,word ptr FindFirst.ff_fsize 198 | mov dx,word ptr FindFirst.ff_fsize+2 199 | cmp del_after_copy,0 200 | je count_full_size 201 | cmp nondefault_dest,0 202 | jnz count_full_size 203 | cmp dx,filesize_hi 204 | jb check_size_loop 205 | ja check_size_bigger 206 | cmp ax,filesize_lo 207 | jbe check_size_loop 208 | check_size_bigger: 209 | mov filesize_lo,ax 210 | mov filesize_hi,dx 211 | jmp check_size_loop 212 | 213 | count_full_size: 214 | add filesize_lo,ax 215 | adc filesize_hi,dx 216 | jmp check_size_loop 217 | 218 | get_free_space: 219 | test si,si ; check number of sections found 220 | mov dx,offset no_files_msg 221 | jz short exit_with_err_2 222 | mov dl,dest_drive 223 | inc dx 224 | mov ah,36h ; get free disk space 225 | int 21h 226 | cmp ax,0FFFFh 227 | jne got_free_space 228 | mov dx,offset bad_drive_msg 229 | exit_with_err_2: 230 | jmp near ptr exit_with_errmsg 231 | got_free_space: 232 | mul cx ; DX:AX <- AX*CX 233 | mov cx,dx ; store high half of intermediate 234 | mul bx ; DX:AX <- low(AX*CX)*BX 235 | xchg ax,bx ; store low half of second interm. 236 | xchg cx,dx ; store high half of second interm. 237 | mul dx ; DX:AX <- high(AX*CX)*BX 238 | xchg ax,bx ; DX:BX:0000h + CX:AX = result 239 | add bx,cx 240 | adc dx,0 ; DX:BX:AX = AX*BX*CX = free space 241 | jnz plenty_free_space ; >4G free? 242 | sub ax,filesize_lo 243 | sbb bx,filesize_hi 244 | jnb plenty_free_space 245 | not_enough_space: 246 | mov dx,offset no_disk_msg 247 | call write_string 248 | cmp nondefault_dest,0 249 | jnz size_check_failed 250 | cmp del_after_copy,0 251 | jne size_check_failed 252 | mov dx,offset retry_msg 253 | call write_string 254 | size_check_failed: 255 | mov al,2 256 | jmp exit 257 | plenty_free_space: 258 | ret 259 | 260 | ;;------------------------------------------------------------------------ 261 | 262 | check_section_header: 263 | push si 264 | push di 265 | mov si,offset DGROUP:disk_buffer 266 | mov di,section_heading 267 | mov cx,section_hdr_len 268 | or cx,cx 269 | rep cmpsb 270 | jnz not_section_heading 271 | scan_curr_section: 272 | lodsb 273 | cmp al,' ' ; scan for the " of " 274 | jne scan_curr_section 275 | add si,3 ; skip "of " 276 | xor cl,cl 277 | num_sections_loop: 278 | lodsb 279 | sub al,'0' 280 | jb num_sections_done 281 | cmp al,9 282 | ja num_sections_done 283 | mov ch,al 284 | mov al,10 285 | mul cl 286 | mov cl,al 287 | add cl,ch 288 | jmp num_sections_loop 289 | num_sections_done: 290 | mov numsections,cl 291 | got_num_sections: 292 | not_section_heading: 293 | pop di 294 | pop si 295 | ret 296 | 297 | ;;------------------------------------------------------------------------ 298 | 299 | ; in: SI = file handle for current section 300 | copy_section: 301 | mov ax,4201h 302 | xor cx,cx 303 | xor dx,dx 304 | mov bx,filehandle 305 | int 21h 306 | mov filesize_lo,ax 307 | mov filesize_hi,dx 308 | copy_section_loop: 309 | mov ah,3Fh 310 | mov bx,si 311 | mov cx,disk_buffer_end - disk_buffer 312 | mov dx,offset DGROUP:disk_buffer 313 | int 21h 314 | jc copy_read_error 315 | mov cx,ax ; write same number of bytes read 316 | mov ah,40h 317 | ;; mov dx,offset DGROUP:disk_buffer 318 | mov bx,filehandle 319 | int 21h 320 | mov dx,offset writeerr_msg 321 | jc copy_error 322 | mov dx,offset diskfull_msg 323 | cmp ax,cx 324 | jb copy_error 325 | ; check for section header at start of buffer, and extract number 326 | ; of sections from it 327 | push cx 328 | call check_section_header 329 | pop ax 330 | cmp ax,disk_buffer_end - disk_buffer ; continue until only partial 331 | je copy_section_loop ; buffer read (EOF hit) 332 | ret 333 | 334 | copy_read_error: 335 | mov dx,offset readerr_msg 336 | copy_error: 337 | ; truncate output to size before section was started 338 | push dx ; store error message 339 | mov ax,4200h 340 | mov cx,filesize_hi 341 | mov dx,filesize_lo 342 | mov bx,filehandle 343 | int 21h 344 | mov ah,40h 345 | xor cx,cx ; write zero bytes to truncate 346 | int 21h 347 | pop dx ; get back error message 348 | ;; fall through to exit_with_errmsg ;; 349 | 350 | ;;------------------------------------------------------------------------ 351 | 352 | exit_with_errmsg: 353 | call write_string 354 | ; exit with errorlevel 1 355 | mov al,01h 356 | jmp near ptr exit 357 | 358 | main: 359 | ASSUME CS:DGROUP, DS:DGROUP, ES:DGROUP, SS:DGROUP 360 | mov dx,offset banner 361 | call write_string 362 | ; relocate the stack 363 | mov sp,offset DGROUP:stackbot 364 | ; ensure that we have enough memory 365 | mov ax,cs 366 | add ax,1000h ; require 64K memory 367 | cmp ax,ds:[0002h] ; is end of mem at least 64K above CS? 368 | mov dx,offset no_mem_msg 369 | ja exit_with_errmsg 370 | mov si,81h ; point at start of cmdline 371 | mov bl,[si-1] ; get length of cmdline 372 | mov bh,0 373 | mov byte ptr [bx+si],0Dh ; ensure cmdline properly terminated 374 | cld 375 | call skip_whitespace 376 | mov dx,offset usage_msg 377 | jz exit_with_errmsg 378 | get_cmdline_switches: 379 | call skip_whitespace 380 | jz not_a_switch 381 | cmp al,'-' ; is it a switch? 382 | jne not_a_switch 383 | lodsb ; get the switch character 384 | lodsb ; get the switch itself 385 | and al,0DFh ; force to uppercase 386 | cmp al,'P' 387 | je want_ports 388 | cmp al,'D' 389 | ;; mov dx,offset usage_msg 390 | jne exit_with_errmsg 391 | mov del_after_copy,1 392 | jmp get_cmdline_switches 393 | want_ports: 394 | jmp config_for_ports 395 | not_a_switch: 396 | mov ah,19h ; get default drive 397 | int 21h 398 | mov dest_drive,al 399 | mov ah,30h 400 | int 21h 401 | cmp al,2 402 | mov dx,offset bad_dos_msg 403 | jb exit_with_errmsg 404 | call get_destination_file 405 | xor filesize_hi,filesize_hi 406 | call check_total_size 407 | ; 408 | ; OK, all the preliminaries are done now, so go concatenate the 409 | ; sections of the interrupt list 410 | ; 411 | mov al,'A'-1 412 | concat_loop: 413 | inc ax 414 | mov section_letter,al 415 | sub al,'A'-1 416 | cmp al,numsections 417 | ja concat_done 418 | mov dx,section_file 419 | call write_string 420 | mov ax,3D00h 421 | int 21h 422 | mov dx,offset missing_msg 423 | jc concat_loop_end 424 | mov si,ax 425 | call copy_section 426 | mov bx,si ; BX <- section file's handle 427 | mov ah,3Eh ; DOS function: close file handle 428 | int 21h 429 | cmp del_after_copy,0 430 | je concat_no_del 431 | mov ah,41h ; DOS function: delete file 432 | mov dx,section_file 433 | int 21h 434 | concat_no_del: 435 | mov dx,offset crlf 436 | concat_loop_end: 437 | call write_string 438 | mov al,section_letter 439 | jmp concat_loop 440 | 441 | concat_done: 442 | mov dx,offset complete_msg 443 | call write_string 444 | mov al,00h ; successful completion 445 | exit: 446 | push ax 447 | mov dx,offset crlf 448 | call write_string 449 | mov ax,5701h ; (set file time & date) 450 | mov bx,filehandle 451 | mov cx,ftime ; set timestamp of combined file to 452 | mov dx,fdate ; be that of the last of the sections 453 | int 21h 454 | mov ah,3Eh ; DOS function: close file handle 455 | int 21h 456 | pop ax 457 | mov ah,4Ch 458 | int 21h 459 | 460 | config_for_ports: 461 | mov section_heading,offset section_heading2 462 | mov section_hdr_len,section_hdr_len2 463 | push di 464 | push si 465 | push cx 466 | ;; copy combined_file2 over combined_file 467 | mov cx,combined_file2_len 468 | mov si,offset combined_file2 469 | mov di,offset combined_file 470 | rep movsb 471 | ;; copy section_file2 over section_file1 472 | mov cx,section_file2_len 473 | mov si,offset section_file2 474 | mov di,offset section_file1 475 | rep movsb 476 | pop cx 477 | pop si 478 | pop di 479 | add section_file,section_file2_ofs 480 | jmp get_cmdline_switches 481 | 482 | CODE ENDS 483 | 484 | STACKSEG SEGMENT PUBLIC WORD 'STACK' 485 | stacktop dw 160 dup (?) 486 | stackbot label byte 487 | STACKSEG ENDS 488 | 489 | BUFFERSEG SEGMENT PUBLIC WORD 'DATA' 490 | disk_buffer db 62*1024 dup (?) 491 | disk_buffer_end label byte 492 | BUFFERSEG ENDS 493 | 494 | END combine 495 | -------------------------------------------------------------------------------- /inter61e/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | x86/MS-DOS Interrupt List, Release 61 2 | A Comprehensive listing of interrupt 3 | calls, both documented and undocumented, 4 | plus ports/memory/CMOS/etc. Over 9600 5 | entries (plus 5400 tables) in INTER61A 6 | to INTER61D, utility programs and 7 | viewers in INTER61E, and hypertext 8 | conversion progs & WinHelp utilities in 9 | INTER60F. Over 8 million bytes of 10 | text! Released 2000/07/16. 11 | -------------------------------------------------------------------------------- /inter61e/II.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/II.ZIP -------------------------------------------------------------------------------- /inter61e/ILINA100.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/ILINA100.ZIP -------------------------------------------------------------------------------- /inter61e/INT.COM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/INT.COM -------------------------------------------------------------------------------- /inter61e/INTHLP10.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/INTHLP10.ZIP -------------------------------------------------------------------------------- /inter61e/INTSUM16.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/INTSUM16.ZIP -------------------------------------------------------------------------------- /inter61e/IVIEW102.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/IVIEW102.ZIP -------------------------------------------------------------------------------- /inter61e/README.5: -------------------------------------------------------------------------------- 1 | This is the fifth of six archives containing the x/86MS-DOS Interrupt List, 2 | Release 61. 3 | 4 | This archive contains utility programs and viewers for the interrupt 5 | list. Most of these programs have been contributed by others; if you 6 | have problems with a contributed program, please contact the author of 7 | the program with which you experienced difficulties. 8 | 9 | The DOS viewers Interrupt Helper, Interrupt Summary, and IVIEW are 10 | offered in this archive, as is the Windows viewer ILINA. Interrupt 11 | Summary is designed to be keystroke-compatible with INTERVUE (which is 12 | no longer included), while offering additional functionality. IVIEW is 13 | designed to conserve disk space by not requiring any additional index 14 | files and by itself being as compact as possible (under 2K!). 15 | 16 | In addition, the source code for COMBINE, INTPRINT, INT.COM, and the 17 | Epsilon extension code I use while editing the list are included in 18 | this archive. 19 | 20 | Ralf Brown 21 | 22 | 23 | Files in this archive: 24 | README.5 this file 25 | 86BUGS04.ZIP 26 | COMBINE.ASM source code for COMBINE.COM 27 | II.ZIP interrupt list viewer by Martin Rystrand 28 | ILINA100.ZIP Interrupt LIst NAvigator for MS Windows 29 | INT.C source for INT.COM 30 | INT.COM invoke an interrupt from the command line 31 | INTHLP10.ZIP Interrupt Helper 32 | INTLIST.E code for Epsilon editor extensions for intlist 33 | INTPRINT.C INTPRINT source code 34 | INTSUM16.ZIP Interrupt Summary (including source) 35 | IVIEW102.ZIP 36 | VIEWINTL.ZIP list viewer by Sly Golovanov 37 | 38 | Note: PCICFG is now distributed separately in RBPCIxxx.ZIP (v1.17 as of 39 | this writing), available at 40 | http://www.pobox.com/~ralf/files.html#RBpci 41 | -------------------------------------------------------------------------------- /inter61e/VIEWINTL.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61e/VIEWINTL.ZIP -------------------------------------------------------------------------------- /inter61f/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | x86/MS-DOS Interrupt List, Release 61 2 | A Comprehensive listing of interrupt 3 | calls, both documented and undocumented, 4 | plus ports/memory/CMOS/etc. Over 9600 5 | entries (plus 5400 tables) in INTER61A 6 | to INTER61D, utility programs and 7 | viewers in INTER61E, and hypertext 8 | conversion progs & WinHelp utilities in 9 | INTER60F. Over 8 million bytes of 10 | text! Released 2000/07/16. 11 | -------------------------------------------------------------------------------- /inter61f/HINTSRCH.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/HINTSRCH.ZIP -------------------------------------------------------------------------------- /inter61f/IL2ME102.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/IL2ME102.ZIP -------------------------------------------------------------------------------- /inter61f/INT2GUID.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2GUID.ZIP -------------------------------------------------------------------------------- /inter61f/INT2HLP.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2HLP.ZIP -------------------------------------------------------------------------------- /inter61f/INT2IPF.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2IPF.ZIP -------------------------------------------------------------------------------- /inter61f/INT2QH.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2QH.ZIP -------------------------------------------------------------------------------- /inter61f/INT2RTF.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2RTF.ZIP -------------------------------------------------------------------------------- /inter61f/INT2TPH.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2TPH.ZIP -------------------------------------------------------------------------------- /inter61f/INT2WHLP.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INT2WHLP.ZIP -------------------------------------------------------------------------------- /inter61f/INTERRUP.ICO: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/INTERRUP.ICO -------------------------------------------------------------------------------- /inter61f/RB2NG116.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/RB2NG116.ZIP -------------------------------------------------------------------------------- /inter61f/README.6: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/README.6 -------------------------------------------------------------------------------- /inter61f/WH_ED122.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/inter61f/WH_ED122.ZIP -------------------------------------------------------------------------------- /rbpci119/10040005.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 10040005.PCI = Vendor 1004h, Device 0005h 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | VLSI VL82C591 Host/PCI Bridge registers in detail: 12 | Bus Number: %[40]2d 13 | Subordinate Bus: %[41]2d 14 | Device-Specific: %[54]2x %[55]2x %[58]2x %[59]2x %[5C]2x %[5D]2x %[5E]2x %[5F]2x %[60]2x %[FF]2x 15 | !end 16 | 17 | %! end of file 18 | -------------------------------------------------------------------------------- /rbpci119/10040006.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 10040005.PCI = Vendor 1004h, Device 0005h 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | VLSI VL82C593 PCI/ISA Bridge registers in detail: 12 | Device-Specific: %[50]2x %[51]2x %[52]2x %[53]2x %[54]2x %[55]2x %[56]2x %[57]2x 13 | %[58]2x %[59]2x %[5A]2x -- %[5C]2x %[5D]2d %[5E]2x %[5F]2x 14 | %[60]2x %[61]2x %[62]2x %[63]2x %[64]2x %[65]2x %[66]2x %[67]2x 15 | %[68]2x %[69]2x %[6A]2x %[6B]2x %[6C]2x %[6D]2x %[6E]2x %[6F]2x 16 | %[70]2x %[71]2x %[72]2x %[73]2x %[74]2x 17 | %[FF]2x 18 | !end 19 | 20 | %! end of file 21 | -------------------------------------------------------------------------------- /rbpci119/10110009.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 10110009.PCI = Vendor 1011h, Device 0009h = DEC DC24140(A) 4 | %! Last Edit 04feb98 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | DEC DC24140%[08:7-4]|;;A| Tulip Fast Ethernet registers in detail: 12 | Chip Stepping: %[08:7-4]d Revision within Stepping: %[08:3-0]d 13 | Configuration Driver Information: 14 | Sleep Mode: %[40:31]ed 15 | Snooze Mode: %[40:30]ed 16 | Driver Use: %[40:15-8]2x 17 | !end 18 | 19 | %! end of file 20 | -------------------------------------------------------------------------------- /rbpci119/10110014.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 10110014.PCI = Vendor 1011h, Device 0014h = DEC DC24014 4 | %! Last Edit 04feb98 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | DEC DC24014 Tulip Plus registers in detail: 12 | Chip Stepping: %[08:7-4]d Revision within Stepping: %[08:3-0]d 13 | Configuration Driver Information: 14 | Sleep Mode: %[40:31]ed 15 | Snooze Mode: %[40:30]ed 16 | Driver Use: %[40:15-8]2x 17 | ?: %[40]2x 18 | !end 19 | 20 | %! end of file 21 | -------------------------------------------------------------------------------- /rbpci119/10421000.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 10421000.PCI = Vendor 1042h, Device 1000h -- PC Techn. RZ-1000 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | Everything preceding a line beginning with the six characters "!begin" is 8 | a comment and will be ignored (with the proviso that the total file size 9 | not exceed 64K). Everything from the !begin line to a line starting with 10 | the four characters "!end" forms part of the device description, in a 11 | format similar to that used for printf(). 12 | 13 | [See file BLANK.PCI for description of formatting specification and how 14 | to create your own device descriptions.] 15 | 16 | !begin 17 | PC Technology RZ-1000 registers in detail: 18 | Read-Ahead Mode: %[40:13]ed 19 | ?: %[40:31-0]8x 20 | ?: %[44:31-0]8x 21 | ?: %[48]2x %[49]2x %[4A]2x %[4B]2x %[4C]2x %[4D]2x %[4E]2x %[4F]2x 22 | !end 23 | 24 | %! end of file 25 | -------------------------------------------------------------------------------- /rbpci119/11060585.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE 2 | %! 3 | %! Filename 11060585.PCI -- VIA VT82C585VPX Host Bus-PCI Bridge 4 | %! Last Edit 20sep98 by Denis Vlasenko 5 | %! 6 | %! Source: 580VPX.PDF file from VIA WWW site. 7 | %! Very detailed. All registers dumped in binary and all bits shown. 8 | %! 9 | %! '%!??' - doubtful and/or untested places. 10 | 11 | !begin 12 | VIA VPX Host Bus-PCI Bridge registers in detail: [by Denis Vlasenko] 13 | 14 | (50) Cache Control 1 %[50]8b 15 | 7-6 Cache Enable: %[50:7-6]|00 disabled;01 init;10 enabled;11 reserved| 16 | 5 Linear Burst Enabled: %[50:5]Y 17 | 4-3 Tag Configuration: %[50:4-3]|00 8 tag bits, no dirty bit;01 7 tag bits + dirty bit;10 10 tag bits, no dirty bit;11 9 tag bits + dirty bit| 18 | 2 SDRAM Interface Select: %[50:2]|0 CWE[0-7]#;1 GWE#, BWE#, SCASx#, SRASx#, SWEx#| 19 | (Selects the function of pins 90-93 and 73-76) 20 | 1-0 SRAM Type: %[50:1-0]|00 no SRAM;01 reserved;10 burst SRAM;11 pipelined burst SRAM| 21 | 22 | (51) Cache Control 2 %[51]8b 23 | 7-6 Reserved: %[51:7-6]2b 24 | 5 Backoff CPU: %[51:5]|0 defer ready return until L2 is filled;1 backoff CPU until L2 is filled| 25 | 4 Reserved: %[51:4]1b 26 | 3 SRAM Banks: %[51:3]|1 bank;2 banks| 27 | 2 Reserved: %[51:2]1b 28 | 1-0 Cache Size: %[51:1-0]|00 256K;01 512K;10 1M;11 2M| 29 | 30 | (52) Non-Cacheable Control %[52]8b 31 | Cacheable & Write-Protected: 32 | 7 C0000-C7FFF: %[52:7]Y 33 | 6 D0000-DFFFF: %[52:6]Y 34 | 5 E0000-EFFFF: %[52:5]Y 35 | 4 F0000-FFFFF: %[52:4]Y 36 | 3 Reserved: %[52:3]1b 37 | 2 L2 fill: %[52:2]|0 normal;1 forced (ignores CPU CACHE#)| 38 | 1 Reserved: %[52:1]1b 39 | 0 L2 mode: %[52:0]|0 write-back;1 write-through| 40 | 41 | (53) System Performance Control %[53]8b 42 | 7 Read Around Write: %[53:7]ed 43 | 6 Cache Read Pipeline Cycle: %[53:6]ed 44 | 5 Cache Write Pipeline Cycle: %[53:5]ed 45 | 4 DRAM Pipeline Cycle: %[53:4]ed 46 | 3 PCI Master Peer Concurrency: %[53:3]ed 47 | 2-0 Reserved: %[53:2-0]3b 48 | 49 | (54-55) Non-Cacheable Region #1 %[54]8b %[55]8b %!?? VIA's pdf says: 54:15-8 Base Address MSBs - A<28:21> 50 | 15-3 Address: %[54|55:7-3<16]8x hex %! 55:7-3 Base Address LSBs - A<20:16> 51 | 2-0 Size: %[55:2-0](RegionSize) %! 55:2-0 Range (Region Size) 52 | 53 | (56-57) Non-Cacheable Region #2 %[56]8b %[57]8b %!?? Similar to above 54 | 15-3 Address: %[56|57:7-3<16]8x hex 55 | 2-0 Size: %[57:2-0](RegionSize) 56 | 57 | (58) DRAM Configuration 1 %[58]8b 58 | 7-5 Bank 0/1 MA Map Type (EDO/FPG): %[58:7-5](EDOmapType) 59 | Bank 0/1 MA Map Type (SDRAM): %[58:7]|0xx 16Mbit SDRAM;1xx 64Mbit SDRAM| 60 | 4 Reserved: %[58:4]1b 61 | 3-1 Bank 2/3 MA Map Type (EDO/FPG): %[58:3-1](EDOmapType) 62 | Bank 2/3 MA Map Type (SDRAM): %[58:3]|0xx 16Mbit SDRAM;1xx 64Mbit SDRAM| 63 | 0 Reserved: %[58:1]1b 64 | 65 | (59) DRAM Configuration 2 %[59]8b 66 | 7-5 Bank 4/5 MA Map Type (EDO/FPG): %[59:7-5](EDOmapType) 67 | Bank 4/5 MA Map Type (SDRAM): %[59:7]|0xx 16Mbit SDRAM;1xx 64Mbit SDRAM| 68 | 4-3 Reserved: %[59:4-3]2b 69 | 2-0 Last Bank DRAM Populated: %[59:2-0]|000 bank 0;001 bank 1;010 bank 2;011 bank 3;100 bank 4;101 bank 5;11x reserved| 70 | 71 | (5A) Bank 0 Ending (HA[29:22]): %[5A]8b %[5A<2]4dMb 72 | (5B) Bank 1 Ending (HA[29:22]): %[5B]8b %[5B<2]4dMb 73 | (5C) Bank 2 Ending (HA[29:22]): %[5C]8b %[5C<2]4dMb 74 | (5D) Bank 3 Ending (HA[29:22]): %[5D]8b %[5D<2]4dMb 75 | (5E) Bank 4 Ending (HA[29:22]): %[5E]8b %[5E<2]4dMb 76 | (5F) Bank 5 Ending (HA[29:22]): %[5F]8b %[5F<2]4dMb 77 | 78 | (60) DRAM Type %[60]8b 79 | 7-6 Reserved: %[60:7-6]2b 80 | 5-4 DRAM Type for Bank 4/5: %[60:5-4](DRAMtype) 81 | 3-2 DRAM Type for Bank 2/3: %[60:3-2](DRAMtype) 82 | 1-0 DRAM Type for Bank 0/1: %[60:1-0](DRAMtype) 83 | 84 | (61) Shadow RAM Control 1 %[61]8b 85 | 7-6 CC000h-CFFFFh: %[61:7-6](Shadow) 86 | 5-4 C8000h-CBFFFh: %[61:5-4](Shadow) 87 | 3-2 C4000h-C7FFFh: %[61:3-2](Shadow) 88 | 1-0 C0000h-C3FFFh: %[61:1-0](Shadow) 89 | 90 | (62) Shadow RAM Control 2 %[62]8b 91 | 7-6 DC000h-DFFFFh: %[62:7-6](Shadow) 92 | 5-4 D8000h-DBFFFh: %[62:5-4](Shadow) 93 | 3-2 D4000h-D7FFFh: %[62:3-2](Shadow) 94 | 1-0 D0000h-D3FFFh: %[62:1-0](Shadow) 95 | 96 | (63) Shadow RAM Control 3 %[63]8b 97 | 7-6 E0000h-EFFFFh %[63:7-6](Shadow) 98 | 5-4 F0000h-FFFFFh %[63:5-4](Shadow) 99 | 3-2 Memory Hole %[63:3-2]|00 none;01 512K-640K;10 15M-16M (1M);11 14M-16M (2M)| 100 | 1 SMI Redirect to A0000h-BFFFFh: %[63:1]ed 101 | 0 I/O in A0000h-BFFFFh: %[63:0]|0 accesses VGA;1 accesses DRAM (not VGA!)| 102 | 103 | (64) DRAM Reference Timing (FPG Only) %[64]8b 104 | 7-6 RAS Precharge Time: %[64:7-6]|00 2T;01 3T;10 4T;11 6T| 105 | 5-4 RAS Pulse Width: %[64:5-4]|00 3T;01 4T;10 5T;11 6T| 106 | 3-2 CAS Read Pulse Width: %[64:3-2]|00 1T;01 2T (FPG), 1T (EDO);10 3T (FPG), 2T (EDO);11 4T (FPG), 3T (EDO)| 107 | 1 CAS Write Pulse Width: %[64:1]|0 1T;1 2T| 108 | 0 Column Address to CAS Delay: %[64:0]|0 1T;1 2T| 109 | (see also 67:7) 110 | 111 | (65) DRAM Timing Control 1 (EDO/SDRAM) %[65]8b 112 | 7-6 Page Mode Control: %[65:7-6]|00 page closes after access;01 reserved;10 page stays open after access;11 page closes if CPU is idle| 113 | 5 Fast DRAM Decoding Enable: %[65:5]|0 end of second T2;1 end of first T2| 114 | 4 EDO Leadoff Cycle Reduction: %[65:4]|0 normal leadoff cycle;1 reduce leadoff cycle by 1T| 115 | 3 DRAM Data Latch Delay: %[65:3]|0 latch DRAM data 1 cycle before CPU;1 latch DRAM data 1/2 cycle before CPU| 116 | 2 Pin 88 Function Select: %[65:2]|0 DB32;1 TA9| 117 | 1 Reserved: %[65:1]1b 118 | 0 Relaxed DRAM Read Cycle Latency:%[65:0]|0 DRAM decoding time is end of T2;1 DRAM decoding time is the end of the second T2 if the write-buffer is not empty| 119 | 120 | (66) DRAM Timing Control 2 (EDO/SDRAM) %[66]8b 121 | 7 EDO Test Mode Enable: %[66:7]|0 normal mode;1 test mode| 122 | 6 Reserved: %[66:6]1b 123 | 5,6C:3 SDRAM CAS Latency: %[66:5|6C:3]|00 latency is 2;<>00 latency is 3| 124 | 4 Reserved: %[66:4]1b 125 | 3 Turbo EDO Mode Enable: %[66:3]|0 -2-2-2 two-cycle burst;1 -1-1-1 one-cycle burst| 126 | 2 DRAM-to-CPU FIFO Control: %[66:2]|0 -1-1-1 to pop data from FIFO to CPU;1 -2-2-2 to pop data from FIFO to CPU| 127 | 1 SDRAM RAS-Precharge Reduction: %[66:1]|0 use 64:7-6 for RAS-precharge time;1 reduce 64:7-6 RAS precharge time by 1T| 128 | 0 SDRAM RAS-to-CAS Delay Reduct.: %[66:0]|0 use 64:0 for col addr to CAS delay;1 column address to CAS delay is 1T| 129 | 130 | (67) 32-Bit DRAM Width %[67]8b 131 | 7 RAS to Column Address Delay: %[67:7]|0 1T;1 2T| 132 | 6 NA# Delay: %[67:6]|0 no NA# delay, 3-1-1-1-2-1-1-1;1 delay NA# 1T, 3-1-1-1-3-1-1-1| 133 | (This bit only applies when 2 banks of PBSRAM are installed.) 134 | 5 Bank 5 Width: %[67:5]|0 64 bit;1 32 bit| 135 | 4 Bank 4 Width: %[67:4]|0 64 bit;1 32 bit| 136 | 3 Bank 3 Width: %[67:3]|0 64 bit;1 32 bit| 137 | 2 Bank 2 Width: %[67:2]|0 64 bit;1 32 bit| 138 | 1 Bank 1 Width: %[67:1]|0 64 bit;1 32 bit| 139 | 0 Bank 0 Width: %[67:0]|0 64 bit;1 32 bit| 140 | 141 | (68) Reserved (Do Not Program) %[68]8b 142 | 7-4 Reserved (do not program): %[68:7-4]4b 143 | 3 Pin 126 Function Select: %[68:3]|0 remains high all the time;1 pin 126 is MA12 for 64Mb DRAM support| 144 | (0 - backward compatibility with VP) 145 | 2-0 Reserved (do not program): %[68:2-0]3b 146 | 147 | (69) Reserved (Do Not Program) %[69]8b 148 | 149 | (6A) Refresh Counter: %[6A]dx16 CPUCLKs 150 | (When set to 0, DRAM refresh is disabled) 151 | 152 | (6B) Refresh Control %[6B]8b 153 | 7 CBR (CAS-before-RAS) Refresh: %[6B:7]ed 154 | 6 Burst Refresh (Burst 4 Times): %[6B:6]ed 155 | 5-3 Reserved: %[6B:5-3]3b 156 | 2 Extended Timing: %[6B:2]|0 normal timing;1 force 2T from MA to RAS# and CAS# falling for all cases| 157 | 1-0 Reserved: %[6B:1-0]2b 158 | 159 | (6C) SDRAM Control %[6C]8b 160 | 7 SDRAM Interleave (64Mbit only): %[6C:7]|0 2-bank interleave;1 4-bank interleave| 161 | (16Mbit can have 2-bank interleave only) 162 | 6 SDRAM Burst Write: %[6C:6]ed 163 | 5 SDRAM Bank Interleave Enable: %[6C:5]ed 164 | 4 Reserved: %[6C:4]1b 165 | 3,66:5 SDRAM CAS Latency: %[6C:3|66:5]|00 latency is 2;<>00 latency is 3| 166 | 2-0 SDRAM Operation Mode Select: %[6C:2-0]|000 normal;001 NOP command enabled;010 all-banks-precharge command enabled;011 CPU-to-DRAM cycles conv to commands;100 CBR cycle enabled;101 reserved;11x reserved| 167 | 168 | (6D) DRAM Control Drive Strength %[6D]8b 169 | 7 Bank Decoding Test: %[6D:7]1b 170 | 6 MA[0:1] Drive: %[6D:6]|0 12mA;1 24mA| 171 | 5 Duplicate Copy of MA[0:1]: %[6D:5]|0 RAS5# RAS4# bit 0;1 MA1 MA0 bit 6| 172 | 4 Force SMM Mode: %[6D:4]1b 173 | 3 SDRAM Command Drive: %[6D:3]|0 12mA;1 24mA| 174 | 2 MA[2:13] / WE# Drive: %[6D:2]|0 12mA;1 24mA| 175 | 1 CAS# Drive: %[6D:1]|0 8mA;1 12mA| 176 | 0 RAS# Drive: %[6D:0]|0 12mA;1 24mA| 177 | 178 | (70) PCI Buffer Control %[70]8b 179 | 7 CPU to PCI Post-Write: %[70:7]ed 180 | 6 PCI Master to DRAM Post-Write: %[70:6]ed 181 | 5 PCI Master to DRAM Prefetch: %[70:5]ed 182 | 4-2 Reserved: %[70:4-2]3b 183 | 1 PCI Retry for CPU QW Access: %[70:1]ed 184 | 0 PCI Master Flushes PCI Buffer: %[70:0]|0 yes;1 no| 185 | 186 | (71) CPU to PCI Flow Control 1 %[71]8b 187 | 7,3 CPU writes burst on PCI: %[71:7|71:3]|00 PCI bursts disabled;01 only burst writes;1x all writes burst if possible| 188 | 6 Byte Merge: %[71:6]ed 189 | 5 Reserved: %[71:5]1b 190 | 4 PCI I/O Cycle Post Write: %[71:4]ed 191 | 2 PCI Fast Back-to-Back Write: %[71:2]ed 192 | 1 Quick Frame Generation: %[71:1]ed 193 | 0 1 Wait State PCI Cycles: %[71:0]ed 194 | 195 | (72) CPU to PCI Flow Control 2 %[72]8b 196 | 7 Retry Status over 16/64 Times: %[72:7]|0 no retry occurred;1 retry occurred (write 1 to clear)| 197 | 6 Retry Timeout Action: %[72:6]|0 retry forever;1 flush buffer/return FFFFFFFF for read| 198 | 5-4 Retry Count and Retry Backoff: %[72:5-4]|00 retry 2 times, back off CPU;01 retry 16 times;10 retry 4 times, back off CPU;11 retry 64 times| 199 | 3 Clear Failed Data and Continue Retry: %[72:3]|0 disabled;1 keep posting| 200 | 2 CPU Backoff on PCI Read Retry Failure: %[72:2]|0 disabled;1 backoff CPU| 201 | 1 Reduce 1T for FRAME# Generation: %[72:1]ed 202 | 0 Reduce 1T for CPU Read PCI Slave: %[72:0]|0 disabled;1 enabled (bypass TRDY# to LRDY#)| 203 | 204 | (73) PCI Master Control 1 %[73]8b 205 | 7 Local Memory Decoding: %[73:7]|0 fast (address phase);1 slow (first data phase)| 206 | 6 PCI Master 1-Wait-State Write: %[73:6]|0 zero wait state TRDY# response;1 one wait state TRDY# response| 207 | 5 PCI Master 1-Wait-State Read: %[73:5]|0 zero wait state TRDY# response;1 one wait state TRDY# response| 208 | 4 Reserved: %[73:4]1b 209 | Assert STOP#... 210 | 3 ..after PCI Master Wrt Timeout: %[73:3]ed 211 | 2 ..after PCI Master Read Timeout:%[73:2]ed 212 | 1 LOCK# Function: %[73:1]ed 213 | 0 PCI Master Broken Timer Enable: %[73:0]ed 214 | (Enabled - force into arbitration when there is no 215 | FRAME# 16 PCICLK's after the GRANT) 216 | 217 | (74) PCI Master Control 2 %[74]8b 218 | 7 PCI Enhance Command Support: %[74:7]ed 219 | 6 PCI Master Single Write Merge: %[74:6]ed 220 | 5-0 Reserved: %[74:5-0]6b 221 | 222 | (75) PCI Arbitration 1 %[75]8b 223 | 7 Arbitration Mechanism: %[75:7]|0 PCI has priority;1 fair arbitration between PCI and CPU| 224 | 6 Arbitration Mode: %[75:6]|0 REQ-based (arbitrate at end of REQ#);1 frame-based (arbitrate at end of each FRAME#)| 225 | 5-4 Reserved: %[75:5-4]2b 226 | 3-0 PCI Master Bus Time-Out: %[75:3-0]dx32 PCICLKs 227 | (force into arbitration after a period of time) 228 | (0 - disable) 229 | 230 | (76) PCI Arbitration 2 %[76]8b 231 | 7 Master Priority Rotation Enable:%[76:7]|0 disabled (arbitration per 75:7);1 enabled (arbitration per 76:5-4)| 232 | 6 Reserved: %[76:6]1b 233 | 5-4 Master Priority Rotation Ctrl: %[76:5-4]|00 disabled (arbitration per 75:7);01 grant to CPU after every PCI master grant;10 grant to CPU after every 2 PCI master grants;11 grant to CPU after every 3 PCI master grants| 234 | 3-0 Reserved: %[76:3-0]4b 235 | !end 236 | 237 | !enum EDOmapType 238 | 000 8-bit column address 239 | 001 9-bit column address 240 | 010 10-bit column address 241 | 011 11-bit column address 242 | 100 12-bit column address 243 | 101 reserved 244 | 11x reserved 245 | !end 246 | 247 | !enum RegionSize 248 | 000 region disabled 249 | 001 64K 250 | 010 128K 251 | 011 256K 252 | 100 512K 253 | 101 1M 254 | 110 2M 255 | 111 4M 256 | !end 257 | 258 | !enum DRAMtype 259 | 00 Fast Page Mode DRAM 260 | 01 EDO DRAM 261 | 10 reserved 262 | 11 Synchronous DRAM 263 | !end 264 | 265 | !enum Shadow 266 | 00 read/write disabled 267 | 01 write enabled 268 | 10 read enabled 269 | 11 read/write enabled 270 | !end 271 | 272 | -------------------------------------------------------------------------------- /rbpci119/11060598.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 11060598.PCI = Vendor 1106h, Device 0598h 4 | %! VIA Technologies VT82C598MVP Host Bridge 5 | %! 6 | %! Written by Maurizio Vairani, email: mvairani@cloverinformatica.com 7 | %! Created 08jan99 by Maurizio Vairani 8 | %! Last edit 10jan99 by Ralf Brown 9 | %! 10 | !begin 11 | 12 | Via VT82C598MVP Host Bridge registers in detail: [by Maurizio Vairani] 13 | 14 | Cache Control 15 | Offset 50-51 - Cache Control 16 | Cache enable/initialize: %[50:7-6]|cache disable;cache initialize - L2 fill;cache enable;reserved| 17 | Linear Burst: %[50:5]e Tag Configuration: %[50:4-3]|8+0;7+1;reserved| 18 | Backoff CPU: %[51:5]|defer ready return until L2 filled;backoff CPU until L2 filled| 19 | Cache Size: %[51:1-0]|256K;512K;1M;2M| SRAM Banks: %[51:3+1]d 20 | Offset 52 - Non-Cacheable Control 21 | C0000-C7FFF Cacheable & Write-Protected: %[52:7]Y 22 | D0000-DFFFF Cacheable & Write-Protected: %[52:6]Y 23 | E0000-EFFFF Cacheable & Write-Protected: %[52:5]Y 24 | F0000-FFFFF Cacheable & Write-Protected: %[52:4]Y 25 | L2 Fill on Single Read: %[52:2]|normal;force (fastest)| 26 | L2 Write-Thru/Write-Back: %[52:0]|write-thru;write-back| 27 | Offset 53 - System Performance Control 28 | Read Around Write: %[53:7]e 29 | Cache Pipeline Cycle: Read = %[53:6]e Write = %[53:5]e 30 | DRAM Read Pipeline Cycle: %[53:4]e 31 | Offset 55-54 - Non-Cacheable region #1 32 | Base Address: %[54:15-3<16]xh (%[54:15-3*128]dKb) Size: %[54:2-0](Range) 33 | Offset 57-56 - Non-Cacheable region #2 34 | Base Address: %[56:15-3<16]xh (%[56:15-3*128]dKb) Size: %[56:2-0](Range) 35 | 36 | DRAM Control 37 | Offset 59-58 - DRAM MA (Memory Address) Map Type 38 | Bank 5/4 MA Map Type: %[60:5-4|58:15-13](EDO_FPG_SDRAM) 39 | Bank 5/4 Virtual Channel Enable: %[58:12]Y 40 | Bank 3/2 MA Map Type: %[60:3-2|58:3-1](EDO_FPG_SDRAM) 41 | Bank 3/2 Virtual Channel Enable: %[58:0]Y 42 | Bank 1/0 MA Map Type: %[60:1-0|58:7-5](EDO_FPG_SDRAM) 43 | Bank 1/0 Virtual Channel Enable: %[58:4]Y 44 | Offset 5F-5A - DRAM Row Ending Addresses 45 | Offset 5A - Bank 0 Ending: %[5A<23]8xh (%[5A*8]3dMb) 46 | Offset 5B - Bank 1 Ending: %[5B<23]8xh (%[5B*8]3dMb) 47 | Offset 5C - Bank 2 Ending: %[5C<23]8xh (%[5C*8]3dMb) 48 | Offset 5D - Bank 3 Ending: %[5D<23]8xh (%[5D*8]3dMb) 49 | Offset 5E - Bank 4 Ending: %[5E<23]8xh (%[5E*8]3dMb) 50 | Offset 5F - Bank 5 Ending: %[5F<23]8xh (%[5F*8]3dMb) 51 | Offset 60 - DRAM Type 52 | DRAM Type for Bank 5/4: %[60:5-4](DRAM) 53 | DRAM Type for Bank 3/2: %[60:3-2](DRAM) 54 | DRAM Type for Bank 1/0: %[60:1-0](DRAM) 55 | Offset 61,62,63 - Shadow RAM Control 56 | C0000h-C3FFFh: %[61:1-0](Shadow) D0000h-D3FFFh: %[62:1-0](Shadow) 57 | C4000h-C7FFFh: %[61:3-2](Shadow) D4000h-D7FFFh: %[62:3-2](Shadow) 58 | C8000h-CBFFFh: %[61:5-4](Shadow) D8000h-DBFFFh: %[62:5-4](Shadow) 59 | CC000h-CFFFFh: %[61:7-6](Shadow) DC000h-DFFFFh: %[62:7-6](Shadow) 60 | E0000h-EFFFFh: %[63:7-6](Shadow) F0000h-FFFFFh: %[63:5-4](Shadow) 61 | Memory Hole: %[63:3-2]|none;512K-640K;15M-16M (1M);14M-16M (2M)| 62 | SMI Mapping Control: %[63:1-0]|disable SMI address redirection;allow access DRAM Axxxx-Bxxxx for both 63 | normal and SMI cycles;reserved;allow SMI Axxxx-Bxxxx DRAM access| 64 | Offset 64 - DRAM Timing for Banks 0,1 65 | if DRAM is EDO/FPG: 66 | RAS Precharge Time: %[64:7+3]dT Pulse Width: %[64:6+4]dT 67 | CAS Pulse Width: Read = %[64:5-4]dT Write = %[64:3+1]dT 68 | MA-to-CAS Delay: %[64:2+1]dT RAS to MA Delay: %[64:1+1]dT 69 | if DRAM is SDRAM: 70 | Precharge Command to Activate Command Period, Trp: %[64:7+2]dT 71 | Activate Command to Precharge Command Period, Tras: %[64:6+5]dT 72 | CAS Latency: %[64:5-4]|SDRAM 1T or SDRAM-II n/a;SDRAM 2T or SDRAM-II n/a;SDRAM 3T or SDRAM-II 2T,2.5T;SDRAM n/a or SDRAM-II 3T| 73 | DDR Write Enable (SDRAM-II Only): %[64:3]e 74 | ACTIVE Command to CMD Command Period: %[64:2+2]dT 75 | Bank Interleave: %[64:1-0]|no interleave;2-way;4-way;reserved| 76 | Offset 65 - DRAM Timing for Banks 2,3 77 | if DRAM is EDO/FPG: 78 | RAS Precharge Time: %[65:7+3]dT Pulse Width: %[65:6+4]dT 79 | CAS Pulse Width: Read = %[65:5-4]dT Write = %[65:3+1]dT 80 | MA-to-CAS Delay: %[65:2+1]dT RAS to MA Delay: %[65:1+1]dT 81 | if DRAM is SDRAM: 82 | Precharge Command to Activate Command Period, Trp: %[65:7+2]dT 83 | Activate Command to Precharge Command Period, Tras: %[65:6+5]dT 84 | CAS Latency: %[65:5-4]|SDRAM 1T or SDRAM-II n/a;SDRAM 2T or SDRAM-II n/a;SDRAM 3T or SDRAM-II 2T,2.5T;SDRAM n/a or SDRAM-II 3T| 85 | DDR Write Enable (SDRAM-II Only): %[65:3]e 86 | ACTIVE Command to CMD Command Period: %[65:2+2]dT 87 | Bank Interleave: %[65:1-0]|no interleave;2-way;4-way;reserved| 88 | Offset 65 - DRAM Timing for Banks 4,5 89 | if DRAM is EDO/FPG: 90 | RAS Precharge Time: %[66:7+3]dT Pulse Width: %[66:6+4]dT 91 | CAS Pulse Width: Read = %[66:5-4]dT Write = %[66:3+1]dT 92 | MA-to-CAS Delay: %[66:2+1]dT RAS to MA Delay: %[66:1+1]dT 93 | if DRAM is SDRAM: 94 | Precharge Command to Activate Command Period, Trp: %[66:7+2]dT 95 | Activate Command to Precharge Command Period, Tras: %[66:6+5]dT 96 | CAS Latency: %[66:5-4]|SDRAM 1T or SDRAM-II n/a;SDRAM 2T or SDRAM-II n/a;SDRAM 3T or SDRAM-II 2T,2.5T;SDRAM n/a or SDRAM-II 3T| 97 | DDR Write Enable (SDRAM-II Only): %[66:3]e 98 | ACTIVE Command to CMD Command Period: %[66:2+2]dT 99 | Bank Interleave: %[66:1-0]|no interleave;2-way;4-way;reserved| 100 | Offset 68 - DRAM Control 101 | SDRAM Open Page Control: %[68:7]|always precharge SDRAM banks when accessing 102 | EDO/FPG DRAMs;SDRAM banks remain active when accessing 103 | EDO/FPG banks| 104 | Bank Page Control: %[68:6]|allow only pages of the same bank active;allow pages of different banks to be active| 105 | EDO Pipeline Burst Rate: X-2-2-2-%[68:5]|2-2-2-2;3-2-2-2| 106 | EDO Test Mode: %[68:3]e 107 | Burst Refresh: %[68:2]e 108 | System Frequency Divider: CPU/PCI Frequency Ratio %[68:1-0]|2x (66MHz);3x (100MHz);2x (66MHz);2.5x (75/83 MHz)| 109 | Offset 69 - DRAM Clock select 110 | DRAM Operating Frequency: Same as %[69:7]|CPU Frequency (66/75/83/100 MHz);AGP Frequency (66 MHz)| 111 | Offset 6A - DRAM Refresh Counter: %[6A]e, %[6A*16+16]d CPUCLKs (valid if enable) 112 | Offset 6B - DRAM Arbitration Control 113 | Arbitration Parking Policy: %[6B:7-6]|park at last bus owner;park at CPU side; park at AGP side;reserved| 114 | Multi-Page Open: %[6B:0]e 115 | Offset 6C - SDRAM Control 116 | DRAM Start Cycle: %[6C:6]|concurrent with cache hit detection (for 66MHz);after cache hit detection (for 100MHz)| 117 | MD-to-HD Pop: %[6C:5]|normal;add 1T latency for 100MHz| 118 | DDR Write-to-Read Turnaround: %[6C:4+1]dT turnaround 119 | Single RW Burst Stop Command: %[6C:3]e 120 | SDRAM Operation Mode Select: %[6C:2-0](SDRAM_Mode) 121 | Offset 6D - DRAM Drive Setting 122 | Delay DRAM read Latch: %[6D:6-5]|disable;0.5 ns;1.0 ns;2.0 ns| 123 | MD Drive: %[6D:4]|8;6| mA 124 | SDRAM Command Drive: %[6D:3]|16;24| mA CAS# Drive: %[6D:1]|8;12| mA 125 | MA[2:13]/WE# Drive: %[6D:2]|16;24| mA RAS# Drive: %[6D:0]|16;24| mA 126 | Offset 6E - ECC Control 127 | ECC / ECMode select: %[6E:7]|ECC checking and reporting;ECC checking, reporting and correcting| 128 | Enable (Assert) SERR# on ECC / EC Multi-Bit Error: %[6E:5]Y 129 | Enable (Assert) SERR# on ECC / EC Single-Bit Error: %[6E:4]Y 130 | ECC / EC Enable Bank 5/4 (DIMM 2): %[6E:2]e 131 | ECC / EC Enable Bank 3/2 (DIMM 1): %[6E:1]e 132 | ECC / EC Enable Bank 1/0 (DIMM 0): %[6E:0]e 133 | Offset 6F - ECC Status 134 | Multi-Bit Error Detected: %[6F:7]Y DRAM Bank: %[6F:6-4]d 135 | Single-Bit Error Detected: %[6F:3]Y DRAM Bank: %[6F:2-0]d 136 | 137 | PCI Bus #1 Control 138 | Offset 70 - PCI Buffer Control 139 | CPU to PCI Post-Write: %[70:7]e 140 | PCI Master to DRAM Post-Write: %[70:6]e 141 | CPU-to-PCI Prefetch: %[70:5]e 142 | PCI Master to DRAM Prefetch Disable: %[70:4]e 143 | PCI Master Read Caching: %[70:2]e 144 | Delay Transaction: %[70:1]e 145 | Offset 71,72 - CPU to PCI Flow Control 146 | Dynamic Burst: %[71:7]e PCI I/O Cycle Post Write: %[71:4]e 147 | Byte Merge: %[71:6]e PCI Burst: %[71:3]e 148 | PCI Fast Back-to-Back Write: %[71:2]e 149 | Quick Frame Generation: %[71:1]e 150 | 1 Wait State PCI Cycles: %[71:0]e 151 | Retry Status: retry occured %[72:7]|less;more| than retry limit (see Retry Limit) 152 | Retry Timeout Action: %[72:6]|retry forever (record status only);flush buffer for write or return all 1s for read| 153 | Retry Limit: retry %[72:5-4]|2;16;4;64| times 154 | Clear Failed Data and Continue Retry: %[72:3]|flush the entire post-write buffer;when data is posting and master (or 155 | target) abort fails, pop the failed data if any, and keep posting| 156 | CPU Backoff on PCI Read Retry Failure: %[72:2]e 157 | Reduce 1T for FRAME# Generation: %[72:1]e 158 | Offset 73,74 - PCI Master Control 159 | PCI Master 1-Wait-State Write: %[73:6]|zero;one| wait state TRDY# response 160 | PCI Master 1-Wait-State Read: %[73:5]|zero;one| wait state TRDY# response 161 | Prefetch Disable: %[73:4]e 162 | Assert STOP# after PCI Master Write Timeout: %[73:3]e 163 | Assert STOP# after PCI Master Read Timeout: %[73:2]e 164 | LOCK# Function: %[73:1]e 165 | PCI Master Broken Timer Enable: %[73:0]e 166 | PCI Master Read Prefetch by Enhance Command: %[74:7]|always prefetch;prefetch only if enhance 167 | command| 168 | PCI Master Write Merge: %[74:6]e 169 | Offset 75,76 - PCI Arbitration 170 | Arbitration Mechanism: %[75:7]|PCI has priority;fair arbitration between PCI and CPU| 171 | Arbitration Mode: %[75:6]|REQ-based (at the end of REQ#);frame-based (at #FRAME assertion)| 172 | Latency Timer: %[75:5-4]d 173 | PCI Master Bus Time-Out (0 means disable): %[75:3-0*32]d 174 | PCI #2 Master Access PCI #1 Retry Disconnect: %[76:7]e 175 | CPU Latency Timer Bit-0: %[76:6]|CPU has at least 1 PCLK time slot when CPU has 176 | PCI bus;CPU has no time slot| 177 | Master Priority Rotation Control: Grant CPU after every %[76:5-4]d PCI master 178 | grant(s) 179 | Offset 78 - PMU Control 180 | I/O Port 22 Access: CPU access to I/O address 22h is %[78:7]|passed on to PCI bus;processed internally| 181 | Suspend Refresh Type: %[78:6]|CBR;self| refresh 182 | Normal Refresh: %[78:5]|suspend refresh using SUSCLK;normal resresh| 183 | Dynamic Clock Control: %[78:4]|normal (clock is always running);clock to various internal functional blocks is 184 | disabled when those blocks are not being used| 185 | GCKRUN# De-assertion: GCKRUN# %[78:3]|always low;could be high due to PCKRUN#| 186 | PCKRUN# / GCKRUN# Pin Control: %[78:1]e 187 | Memory Clock Enable (CKE) Function: %[78:0]e 188 | 189 | Graphics Address Relocation Table (GART) / Graphics Aperture (GA) Control 190 | Offset 83-80 - GART/TLB Control 191 | Flush Page TLB: %[80:7]e 192 | PCI#1 Master Address Translation for GA Access: %[80:3]e 193 | PCI#2 Master Address Translation for GA Access: %[80:2]e 194 | CPU Address Translation for GA Access: %[80:1]e 195 | AGP Address Translation for GA Access: %[80:0]e 196 | Offset 84 - Graphics Aperture Size: %[84:7-5](GA_SIZE) (%[88:1]ed) 197 | Offset 8B-88 - GA Translation Table Base 198 | Graphics Aperture Translation Table Base: %[88:31-12]8x 199 | PCI Master Directly Accesses DRAM if in GART Range: %[88:2]e 200 | Translation Table is %[88:0]|;non-|cacheable 201 | !end 202 | 203 | !enum Range 204 | disabled 205 | 64K 206 | 128K 207 | 256K 208 | 512K 209 | 1M 210 | 2M 211 | 4M 212 | !end 213 | 214 | !enum DRAM 215 | Fast Page Mode DRAM (FPG) 216 | EDO DRAM (EDO) 217 | SDRAM Double Data Rate (DDR SDRAM-II) 218 | SDRAM Single Data Rate (SDR SDRAM) 219 | !end 220 | 221 | !enum EDO_FPG_SDRAM 222 | 8-bit Column Address 223 | 9-bit Column Address 224 | 10-bit Column Address 225 | 11-bit Column Address 226 | 12-bit Column Address 227 | reserved 228 | reserved 229 | reserved 230 | 16Mbit SDRAM 231 | 16Mbit SDRAM 232 | 16Mbit SDRAM 233 | 16Mbit SDRAM 234 | 64Mbit SDRAM 235 | reserved 236 | !end 237 | 238 | !enum SDRAM_Mode 239 | normal 240 | NOP command enable 241 | All-Banks-Precharge command enable 242 | MSR enable 243 | CRB cycle enable 244 | reserved 245 | !end 246 | 247 | !enum GA_SIZE 248 | 256M 249 | invalid 250 | invalid 251 | invalid 252 | 128M 253 | invalid 254 | 64M 255 | 32M or less 256 | !end 257 | 258 | !enum Shadow 259 | read/write disable 260 | write enable \ 261 | read enable \ 262 | read/write enable 263 | !end 264 | 265 | %! end of file 266 | 267 | -------------------------------------------------------------------------------- /rbpci119/53338811.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 53338811.PCI = Vendor 5333h, Device 8811h -- S3 Trio64V+ 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | S3 Trio64V+ registers in detail: 12 | The Trio64 doesn't seem to use any device-specific registers 13 | !end 14 | 15 | %! end of file 16 | -------------------------------------------------------------------------------- /rbpci119/80860482.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80860482.PCI = Vendor 8086h, Device 0482h 4 | %! Last Edit 10jan99 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | Intel 82375%[08+-3](Variant) registers in detail: 12 | PCI Control: %[40]2x 13 | PCI Arbiter Control: %[41]2x 14 | PCI Priority Control: %[43|42]4x 15 | PCI Decode Control: %[58]2x 16 | MEMCS# Control: %[44]2x Hole: %[45]d-%[46]dM MemTop: %[47]dM 17 | ISA I/O Recover Time: %[4C]2x 18 | EISA Address Decode: %[48]2x %[5A]2x 19 | EISA-to-PCI Memory: attr %[5C]2x addr=%[60:31-0]8x %[64:31-0]8x %[68:31-0]8x %[6C:31-0]8x 20 | EISA-to-PCI I/O: addr=%[70:31-0]8x %[74:31-0]8x %[78:31-0]8x %[7C:31-0]8x 21 | EISA Latency Timer: %[84]2x 22 | BIOS Timer Address: %[80:15-0]4x 23 | PCEB Test Control: %[88:31-0]8x 24 | !end 25 | 26 | !enum Variant 27 | EB 28 | SB 29 | 30 | !end 31 | 32 | %! end of file 33 | -------------------------------------------------------------------------------- /rbpci119/80860483.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80860483.PCI = Vendor 8086h, Device 0483h -- Intel 82424 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | !begin 8 | 82424 registers in detail: 9 | Programmable Attribute Map 10 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 11 | F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 12 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 13 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 14 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 15 | 16 | %! insert device description here 17 | 18 | !end 19 | 20 | %! end of file 21 | -------------------------------------------------------------------------------- /rbpci119/80860484.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80860484.PCI = Vendor 8086h, Device 0484h -- Intel 82378 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | !begin 8 | 82378/82379 registers in detail: 9 | PCI Control: %[40:6]/alias8x/ %[40:5]/IntAck/ SubDec=%[40:3-4]2b %[40:2]/PostWrt/ %[40:1]/ISAMstrBuf/ %[40:0]/DMALineBuf/ 10 | PCI Arbiter: Master Retry %[41:4-3]2b BusPark %[41:2]y BusLock %[41:1]y GAT: %[41:0]y 11 | PCI Arbiter Priority: %[42]2x 12 | PCI Arbiter Pr. Ext.: %[43]2x (REQ%[43:0]{23} has higher priority) 13 | MEMCS# Control: Master Enable %[41:4]y F000-FFFF: %[44:2]{-R}%[44:3]{-W} 8000-9FFF: %[44:0]{-R}%[44:1]{-W} 14 | MEMCS# Hole: %[45]2dM-%[46]2dM 15 | MEMCS# Top of Memory: %[47]2dM 16 | MEMCS# Attr #1: C000: %[54:0]{-R}%[54:1]{-W} C400: %[54:2]{-R}%[54:3]{-W} C800: %[54:4]{-R}%[54:5]{-W} CC00: %[54:6]{-R}%[54:7]{-W} 17 | MEMCS# Attr #2: D000: %[55:0]{-R}%[55:1]{-W} D400: %[55:2]{-R}%[55:3]{-W} D800: %[55:4]{-R}%[55:5]{-W} DC00: %[55:6]{-R}%[55:7]{-W} 18 | MEMCS# Attr #3: E000: %[56:0]{-R}%[56:1]{-W} E400: %[56:2]{-R}%[56:3]{-W} E800: %[56:4]{-R}%[56:5]{-W} EC00: %[56:6]{-R}%[56:7]{-W} 19 | ISA Address Control: ISAmemtop=%[48:7-4+1]dM DMAcycle seg=%[48:0]/01234567/%[48:1]/89/%[48:2]/AB/--%[48:3]/E/- 20 | ISA Addr ROM Blocks: Dx00=%[49:0]/0123/%[49:1]/4567/%[49:2]/89AB/%[49:3]/CDEF/ Ex00=%[49:4]/0123/%[49:5]/4567/%[49:6]/89AB/%[49:7]/CDEF/ 21 | ISA Addr Hole: %[4A]2dM-%[4B]2dM 22 | ISA Ctrlr Recovery: 8-bit: %[4C:6]y - %[4C:3-5]1d SYSCLK 16-bit: %[4C:2]y - %[4C:0-1]1d SYSCLK 23 | ISA Clock Divisor: divisor=%[4D:2-0]{43?} %[4D:6]/upperBIOS/ %[4D:5]/coproc-error/ %[4D:4]/mouse/ %[4D:3]/RSTDRV/ 24 | X-Bus Chip Select A: %[4E:7]/extBIOS/ %[4E:6]/lowBIOS/ %[4E:5]/2nd-floppy/ %[4E:4]/IDE/ floppy=%[4E:3-2]2b %[4E:1]/kbd/ %[4E:0]/RTC/ 25 | X-Bus Chip Select B: %[4F:7]/cfg-RAM/ %[4F:6]/port92/ par=LPT%[4F:5-4]{123-} serialA=COM%[4F:3-2]{12?-} serialB=COM%[4F:1-0]{12?-} 26 | Scatter/Gather Ports: %[57]2x10-%[57]2x3F 27 | IRQ0# Route Control: %[60:0-3]2x (%[60:7]Ed) 28 | IRQ1# Route Control: %[61:0-3]2x (%[61:7]Ed) 29 | IRQ2# Route Control: %[62:0-3]2x (%[62:7]Ed) 30 | IRQ3# Route Control: %[63:0-3]2x (%[63:7]Ed) 31 | PIC/APIC Cfg Control: %[70:1]/use APIC/ %[70:0]/INT disabled/ 32 | APIC Base Address: FEC0%[71:5-0<10]4x %[71:6]/ignore A12/ 33 | BIOS timer base: %[80:1-15<1]4x (%[80:0]ed) 34 | SMI Control: %[A0:6]/StopGnt/ %[A0:3]/frzFast-Off/ %[A0:2]/STPCLKscale/ %[A0:1]/STPCLKenable/ %[A0:0]/SMIgate/ 35 | SMI Enable: %[A2:8]/USB/ %[A2:7]/APMCwrite/ %[A2:6]/EXTSMI/ %[A2:5]/FastOff/ %[A2:4]/IRQ12/ %[A2:3]/IRQ8/ %[A2:2]/IRQ4/ %[A2:1]/IRQ3/ %[A2:0]/IRQ1/ 36 | System Event Enable: %[A4:0-31]8x 37 | \t\tFast-Off: %[A4:31]/SMI/ %[A4:30]/interrupt/ %[A4:28]/APIC/ %[A4:29]/NMI/ 38 | \t\treset Fast-Off on: %[A4:27]/COM/ %[A4:26]/LPT/ %[A4:25]/Drive/ %[A4:24]/DMA/ 39 | \t\treset Fast-Off on IRQ%[A4:0]/0/ %[A4:1]/1/ %[A4:3]/3/ %[A4:4]/4/ %[A4:5]/5/ %[A4:6]/6/ %[A4:7]/7/ %[A4:8]/8/ %[A4:9]/9/ %[A4:10]/10/ %[A4:10]/11/ %[A4:10]/12/ %[A4:10]/13/ %[A4:10]/14/ %[A4:15]/15/ 40 | SMI Request:\t due to %[AA:8]/legacy USB/ %[AA:7]/APM/ %[AA:6]/EXTSMI#/ %[AA:5]/Fast-Off/ IRQ: %[AA:4]/12/ %[AA:3]/8/ %[AA:2]/4/ %[AA:1]/3/ %[AA:0]/0/ 41 | Fast-Off Timer: %[A8]3d minutes 42 | STPCLK# Low Timer: %[AC<5]3d us 43 | STPCLK# High Timer: %[AE<5]3d us 44 | !end 45 | 46 | %! end of file 47 | -------------------------------------------------------------------------------- /rbpci119/80860486.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80860486.PCI = Vendor 8086h, Device 0486h -- Intel 80425EX 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | 11 | !begin 12 | 82425EX registers in detail: 13 | PCI Control: %[40]2x 14 | Host Device Control: %[44]2x 15 | IDE Control: %[48:15-0]4x 16 | ISA I/O Recovery: %[4C]2x 17 | Programmable Attribute Map 18 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 19 | F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 20 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 21 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 22 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 23 | 24 | %! insert device description here 25 | 26 | !end 27 | 28 | %! end of file 29 | -------------------------------------------------------------------------------- /rbpci119/808604A3.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 808604A3.PCI = Vendor 8086h, Device 04A3h -- Intel 82434 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | 82434%[08:4]|LX (Mercury);NX (Neptune)| registers in detail: 12 | Host CPU: type: %[50:7-5]3b bus speed: %[50:1-0](Bus) L1 cache %[50:2]ed 13 | L2 cache: %[52:7-6](L2) %[52:5]|async;burst| SRAM (%[52:0]ed) %[52:4]|;cache all reads| 14 | cache %[52:3]|write;byte| select %[52:2]|LX-compatible;enhanced| connectivity 15 | LX only: write-%[52:1]|through;back| 16 | Deturbo control: %[51]2x 17 | CPU Buf Control: read-around-write %[53:3]ed 18 | CPU-PCI posted writes %[53:1]ed, CPU-mem posted writes %[53:0]ed 19 | PCI Control: LBXs %[54:2]|not ;|connected to TRDY# 20 | PCI-memory posted writes %[54:0]ed, PCI burst %[54:1]ed 21 | DRAM Control: parity errors %[57:5]|not ;|masked SMRAM %[57:3]|not ;|enabled 22 | DRAM bursts: %[57:7-6](Dburst) 23 | 0-Active RAS# Mode: %[57:4]y Burst-of-Four Refresh: %[57:2]y 24 | Refresh Type: %[57:1]|RAS#-only;CAS#-before-RAS#| (%[57:0]ed) 25 | DRAM Timing: RAS# Wait State: %[58:1]y CAS# Wait State: %[58:0]y 26 | DRAM Boundaries: %[68:3-0|60]3dM %[68:7-4|61]3dM %[69:3-0|62]3dM %[69:7-4|63]3dM %[6A:3-0|64]3dM %[6A:7-4|65]3dM %[6B:3-0|66]3dM %[6B:7-4|67]3dM 27 | Memory Size: %[6B:7-4|67]3dM 28 | Programmable Attribute Map 29 | \tC000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 30 | \tF000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 31 | \tC400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 32 | \tC800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 33 | \tCC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}% 34 | \t8000-9FFF: %[59:2]{-C}%[59:1]{-W}%[59:0]{-R} 35 | Error Control: %[70]2x = SERR# on: %[70:7]/trg abort/ %[70:6]/PCI-write parity/ %[70:5]/PCI-read parity/ 36 | SERR# on %[70:4]/PCI-address parity/ %[70:3]/DRAM|L2 parity/ 37 | PERR# on %[70:3]/data parity/ %[70:0]|do not ;|assert PEN# on reads 38 | L2 cache parity %[70:2]ed 39 | Error Status: %[71]2x = %[71:6]/PCI-write parity/ %[71:5]/PCI-read parity/ %[71:4]/PCI-address parity/ 40 | %[71:3]/DRAM parity/ %[71:2]/L2 cache parity/ %[71:0]/SHUTDOWN/ 41 | SMRAM control: SMM Space at segment %[72:2-0+8]1x000 is %[72:6]/open/ %[72:5]/closed/ %[72:4]/locked/ 42 | ISA memory hole: at %[78:7-4]dM, size %[78:14-12+1]dM (%[78:15]ed) 43 | Frame Buffer: %[7C:3-0+1]dM at %[7C:31-20]dM (%[7C:31-20<20]8x) byte merging %[7C:13]ed 44 | lock requests %[7C:9]Ed transparent buffer writes %[7C:7]ed 45 | %[7C:13]|not ;|applied to VGA-range 46 | !end 47 | 48 | !enum Bus 49 | reserved 50 | 50 MHz 51 | 60 MHz 52 | 66 MHz 53 | !end 54 | 55 | !enum L2 56 | none 57 | reserved 58 | 256K 59 | 512K 60 | !end 61 | 62 | !enum Dburst 63 | X-4-4-4 64 | X-4-4-4 read/X-3-3-3 write 65 | reserved 66 | X-3-3-3 67 | !end 68 | 69 | 70 | %! end of file 71 | -------------------------------------------------------------------------------- /rbpci119/80861229.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80861229.PCI = Vendor 8086h, Device 1229h : Intel 82557 Fast Ethernet 4 | %! Last Edit 22jan98 by Ralf Brown 5 | %! 6 | 7 | !begin 8 | The 82557 does not use any device-specific PCI configuration registers. 9 | !end 10 | 11 | 12 | %! end of file 13 | -------------------------------------------------------------------------------- /rbpci119/8086122D.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 8086122D.PCI = Vendor 8086h, Device 122Dh = Intel 82437FX 4 | %! Last Edit 10jan99 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | 82437FX registers in detail: 12 | PCI Control: PeerConcurr=%[50:3]y PCIburst=%[50:2]n PCIstream=%[50:1]n BusConcurr=%[50:0]n CPUinact=%[50:7-5+1]d 13 | cache control: %[52]2x 14 | DRAM control: %[57]2x 15 | DRAM timing: %[58]2x 16 | DRAM Row Type: %[68]2x 17 | DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM %[63]3dM 18 | Memory Top: %[64]3dM 19 | Programmable Attribute Map 20 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R} D000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R} E000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R} 21 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R} D400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R} E400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 22 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R} D800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R} E800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 23 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R} DC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R} EC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 24 | F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 25 | SMRAM control: %[72]2x 26 | !end 27 | 28 | %! end of file 29 | -------------------------------------------------------------------------------- /rbpci119/80861230.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80861230.PCI = Vendor 8086h, Device 1230h Intel 82371FB IDE Ctrlr 4 | %! Last Edit 1/10/99 by Craig Hart 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | Intel 82371FB IDE Controller registers in detail: [by Craig Hart & RB] 12 | Bus Master Interface Base Address: %[20:31-0]8x 13 | IDE timing modes 14 | primary channel: 15 | %[40:15]|dis;en|abled 16 | IORDY sampled %[40:13-12]{5432} clocks after DIOx# 17 | recovery time after IORDY is %[40:9-8]{4321} clock(s) 18 | drive 0 enable: %[40:7]/DMA/ %[40:6]/prefetch,post/ %[40:5]/IORDY sampling/ %[40:4]/fast-timing/ 19 | drive 1 enable: %[40:3]/DMA/ %[40:2]/prefetch,post/ %[40:1]/IORDY sampling/ %[40:0]/fast-timing/ 20 | secondary channel: 21 | %[42:15]|dis;en|abled 22 | IORDY sampled %[42:13-12]{5432} clocks after DIOx# 23 | recovery time after IORDY is %[42:9-8]{4321} clock(s) 24 | drive 0 enable: %[42:7]/DMA/ %[42:6]/prefetch,post/ %[42:5]/IORDY sampling/ %[42:4]/fast-timing/ 25 | drive 1 enable: %[42:3]/DMA/ %[42:2]/prefetch,post/ %[42:1]/IORDY sampling/ %[42:0]/fast-timing/ 26 | !end 27 | 28 | %! end of file 29 | -------------------------------------------------------------------------------- /rbpci119/80861235.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80861235.PCI = Vendor 8086h, Device 1235h -- Intel 82437MX 4 | %! Last Edit 1/17/97 by Ralf Brown 5 | %! 6 | 7 | Everything preceding a line beginning with the six characters "!begin" is 8 | a comment and will be ignored (with the proviso that the total file size 9 | not exceed 64K). Everything from the !begin line to a line starting with 10 | the four characters "!end" forms part of the device description, in a 11 | format similar to that used for printf(). 12 | 13 | [See file BLANK.PCI for description of formatting specification and how 14 | to create your own device descriptions.] 15 | 16 | 17 | !begin 18 | 82437MX System Controller registers in detail: 19 | PCI Control: PeerConcurr=%[50:3]y PCIburst=%[50:2]n PCIstream=%[50:1]n BusConcurr=%[50:0]n CPUinact=%[50:7-5+1]d 20 | Cache Control: cache size %[52:7-6]|0K;256K;512K;reserved| 21 | L2 RAM type %[52:5-4]|p.burst;async;reserved;two banks p.burst| 22 | Force L2 miss %[52:1]y\tL1 cache %[52:0]Ed\tNA# %[52:3]Ed 23 | DRAM control: DRAMs are %[57:4]|NOT;| self-refreshing 24 | refresh = %[57:2-0]|15.6;32.2;62.4;125;250;reserved| microseconds 25 | DRAM hole = %[57:7-6]|none;512K-640K;15M-16M;reserved| 26 | EDO Detect mode is %[57:3]ed 27 | Memory Top: %[63]3dM 28 | DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM %[63]3dM 29 | DRAM Row Type: %[68:0]|FPM;EDO| %[68:1]|FPM;EDO| %[68:2]|FPM;EDO| %[68:3]|FPM;EDO| 30 | DRAM timing: read burst = %[58:6-5]|x444/x444;x333/x444;x222/x333;x322/x333| 31 | write burst = %[58:4-3]|x444;x333;x222;reserved| 32 | RAS-to-CAS = %[58:2]|3;2| clocks 33 | DRAM leadoff = %[58:1-0]|8/6/3;7/5/3;8/6/4;7/5/4| (read/write/precharge) 34 | MA[11:2] buffer strength is %[58:7]|8;12|mA 35 | Programmable Attribute Map 36 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 37 | F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 38 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 39 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 40 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 41 | SMRAM control: SMM Space at segment %[72:2-0+8]1x000 is %[72:6]/open/ %[72:5]/closed/ %[72:4]/locked/ 42 | !end 43 | 44 | ; everything between the above !end line and a following !enum line (not 45 | ; yet implemented) is also a comment 46 | 47 | !enum ToBeImplemented 48 | 49 | 50 | 51 | %! end of file 52 | -------------------------------------------------------------------------------- /rbpci119/80861237.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80861237.PCI = Vendor 8086h, Device 1237h -- Intel 82441FX 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | 11 | !begin 12 | 82441FX System Controller registers in detail: 13 | PMC Control: %[50]2x 14 | Cache Control: cache size %[52:7-6]|0K;256K;512K;reserved| 15 | L2 RAM type %[52:5-4](L2RAM) 16 | Force L2 miss %[52:1]y\tL1 cache %[52:0]Ed\tNA# %[52:3]Ed 17 | DRAM control: DRAMs are %[57:4]|NOT;| self-refreshing 18 | refresh = %[57:2-0](Refresh) 19 | DRAM hole = %[57:7-6]|none;512K-640K;15M-16M;reserved| 20 | EDO Detect mode is %[57:3]ed 21 | Memory Top: %[67<3]4dM 22 | DRAM Boundaries: %[60<3]4dM %[61<3]4dM %[62<3]4dM %[63<3]4dM %[64<3]4dM %[65<3]4dM %[66<3]4dM %[67<3]4dM 23 | DRAM Row Type: %[55]2x 24 | DRAM timing: burst: read = %[58:6-5](RBurst) write = %[58:4-3](WBurst) 25 | RAS-to-CAS = %[58:2]|3;2| clocks 26 | DRAM leadoff = %[58:1-0]|8/6/3;7/5/3;8/6/4;7/5/4| (read/write/precharge) 27 | MA[11:2] buffer strength is %[58:7]|8;12|mA 28 | Multi-Trn Timer: %[70]d PCLKs 29 | CPU-Latency: %[71]d 30 | SMRAM control: SMM Space at segment %[72:2-0+8]1x000 is %[72:6]/open/ %[72:5]/closed/ %[72:4]/locked/ 31 | Error Command: %[90]2x 32 | Error Status: %[91]2x 33 | Turbo Reset: %[93]2x 34 | Programmable Attribute Map 35 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 36 | F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 37 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 38 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 39 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 40 | 41 | !% insert device description here 42 | 43 | !end 44 | 45 | !enum L2RAM 46 | pipelined burst 47 | async 48 | reserved 49 | two banks p.burst 50 | !end 51 | 52 | !enum Refresh 53 | 15.6 microseconds 54 | 32.2 microseconds 55 | 62.4 microseconds 56 | 125 microseconds 57 | 250 microseconds 58 | reserved 59 | 60 | !enum RBurst 61 | x444/x444 62 | x333/x444 63 | x222/x333 64 | x322/x333 65 | !end 66 | 67 | !enum WBurst 68 | x444 69 | x333 70 | x222 71 | reserved 72 | !end 73 | 74 | %! end of file 75 | -------------------------------------------------------------------------------- /rbpci119/80861250.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80861250.PCI = Vendor 8086h, Device 1250h -- Intel 82439HX 4 | %! Last Edit 1/18/97 by Ralf Brown 5 | %! 6 | 7 | Everything preceding a line beginning with the six characters "!begin" is 8 | a comment and will be ignored (with the proviso that the total file size 9 | not exceed 64K). Everything from the !begin line to a line starting with 10 | the four characters "!end" forms part of the device description, in a 11 | format similar to that used for printf(). 12 | 13 | [See file BLANK.PCI for description of formatting specification and how 14 | to create your own device descriptions.] 15 | 16 | 17 | !begin 18 | Intel 82439HX registers in detail: 19 | PCI Control: NewFeaturesEnabled:%[50:0]y Port92 shutdown:%[50:5]y 2-processor NA#: %[50:4]y 20 | %[50:7]|ECC;Parity| memory SERR# %[50:2]|floats;driven| high %[50:6]/ECC Test/ %[50:3]/PCI concurrency/ 21 | Programmable Attribute Map\t(Readable/Writeable/Cacheable) 22 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 23 | \tF000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 24 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 25 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 26 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 27 | DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM %[63]3dM %[64]3dM %[65]3dM %[66]3dM %[67]3dM 28 | DRAM Type: %[68:0]/EDO/ %[68:1]/EDO/ %[68:2]/EDO/ %[68:3]/EDO/ %[68:4]/EDO/ %[68:5]/EDO/ %[68:6]/EDO/ %[68:7]/EDO/ 29 | DRAM Control: refresh = %[57:2-0]|disabled;50MHz;60MHz;66MHz;reserved| 30 | DRAM hole = %[57:7-6]|none;512K-640K;reserved| 31 | EDO Detect mode is %[57:3]ed; 64M SIMM support is %[56:0]ed 32 | Speculative Leadoff %[56:4]Ed 33 | Insert %[56:3]d clocks fo turnaround time after MWE# asserted 34 | Memory Address drive strength is %[56:2-1]|8;8/12;12/8;12|mA 35 | DRAM Timing: read burst = %[58:6-5]|x444/x444;x333/x444;x222/x333;x322/x333| 36 | write burst = %[58:4-3]|x444;x333;x222;reserved| 37 | RAS-to-CAS = %[58:2]|3;2| clocks 38 | DRAM leadoff = %[58:1-0]|7/6/3;6/5/3;7/6/4;6/5/4| (read/write/precharge) 39 | Turbo Read Leadoff is %[58:7]ed 40 | Cache Control: cache size %[52:7-6]|0K;256K;512K;reserved| 41 | L2 RAM type %[52:5-4]|p.burst;reserved;reserved;two banks p.burst| 42 | NA disable %[52:3]y cache memory up to %[52:2]|64;512|M 43 | Force L2 miss %[52:1]y L1 cache %[52:0]Ed 44 | SMRAM Control: SMM Space at segment %[72:2-0+8]1x000 is %[72:6]/open/ %[72:5]/closed/ %[72:4]/locked/ 45 | Error Command: %[90:7]/SERR# until cleared/ %[90:2]/force bad parity/ 46 | %[90:1]/SERR# on multi-bit errors/ %[90:0]/SERR# on single-bit errors/ 47 | Error Status: multi-bit error: %[91:4]y (in DRAM row %[91:7-5]d) 48 | single-bit error: %[91:0]y (in DRAM row %[91:3-1]d) 49 | Error Syndrome: %[92]2x 50 | Undocumented registers: 51 | F0h = %[F0]2x 52 | F1h = %[F1]2x 53 | !end 54 | 55 | ; everything between the above !end line and a following !enum line (not 56 | ; yet implemented) is also a comment 57 | 58 | !enum ToBeImplemented 59 | 60 | %! end of file 61 | -------------------------------------------------------------------------------- /rbpci119/80867000.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867000.PCI = Vendor 8086h, Device 7000h -- Intel 82371SB ISA Br. 4 | %! Last Edit 10jan99 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | Intel 82371FB/SB ISA Controller registers in detail: 12 | I/O Recovery Time: 8-bit: %[4C:6]y - %[4C:3-5]1d SYSCLK 16-bit: %[4C:2]y - %[4C:0-1]1d SYSCLK 13 | X-Bus Chip Select: BIOS enabled at %[4E:7]/FFF80000/ %[4E:6]/E000/ 14 | %[4E:6]|do not;| trigger IRQ13 on FERR# 15 | %[4E:5]e IRQ12 mouse function 16 | BIOS memory is %[4E:2]|not;| write protected 17 | keyboard controller I/O ports are %[4E:1]ed 18 | Real-Time Clock I/O ports are %[4E:0]ed 19 | I/O APIC %[4F:0]ed 20 | IRQ0# Route Control: %[60:0-3]2x (%[60:7]Ed) 21 | IRQ1# Route Control: %[61:0-3]2x (%[61:7]Ed) 22 | IRQ2# Route Control: %[62:0-3]2x (%[62:7]Ed) 23 | IRQ3# Route Control: %[63:0-3]2x (%[63:7]Ed) 24 | ISA Top Of Memory: %[69:7-4+1]2dM 25 | ISA/DMA lower BIOS: %[69:3]|not;| forwarded to PCI 26 | A000/B000 segment: %[69:2]|not;| forwarded to PCI 27 | 8000-A000 segment: %[69:1]|not;| forwarded to PCI 28 | Miscell. Status: enable SERR# on delayed transaction: %[6A:15]y 29 | NB Retry %[6A:7]ed 30 | EXTSMI# mode with PCI bridge %[6A:6]ed 31 | USB %[6A:4]ed 32 | PCI multifunction bit %[6A:2]ed 33 | internal DMA mode: %[6A:1]y 34 | SYSCLK divisor is %[6A:0+3]d 35 | Motherboard IRQ0#: IRQ%[70:0-3]d (%[70:7]Ed) 36 | MIRQ0/IRQ0 sharing %[70:6]ed 37 | IRQ0 output %[70:5]ed 38 | Motherboard IRQ1#: IRQ%[71:0-3]d (%[71:7]Ed) 39 | MIRQ1/IRQ1 sharing %[71:6]ed 40 | IRQ1 output %[71:5]ed 41 | Motherboard DMA0: Type F and DMA buffer %[76:7]ed 42 | DMA channel %[76:2-0]d (%[76:3]Ed) 43 | Motherboard DMA1: Type F and DMA buffer %[77:7]ed 44 | DMA channel %[77:2-0]d (%[77:3]Ed) 45 | Prog. Chip Select: %[78:1-0]|four;eight;no;sixteen| bytes at I/O address %[78:15-2<2]4x 46 | APIC Base Address: FEC0%[80:5-0<10]4x (A12 %[80:6]|ho;ig|nored) 47 | Determistic Latency: SERR# on delayed transation timeout is %[82:3]ed 48 | USB passive release is %[82:2]ed 49 | passive release is %[82:1]ed 50 | delayed transactions are %[82:0]ed 51 | SMI Control: STPCLK# signal %[A0:1]ed, scaling %[A0:2]ed 52 | SMI# on system management interrupt is %[A0:0]ed 53 | SMI Enable: %[A2:8]/USB/ %[A2:7]/APMCwrite/ %[A2:6]/EXTSMI/ %[A2:5]/FastOff/ %[A2:4]/IRQ12/ %[A2:3]/IRQ8/ %[A2:2]/IRQ4/ %[A2:1]/IRQ3/ %[A2:0]/IRQ1/ 54 | System Event Enable: Fast-Off: %[A4:31]/SMI/ %[A4:30]/INTR/ %[A4:28]/APIC/ %[A4:29]/NMI/ 55 | reset Fast-Off on IRQ%[A4:0]/0/ %[A4:1]/1/ %[A4:3]/3/ %[A4:4]/4/ %[A4:5]/5/ %[A4:6]/6/ %[A4:7]/7/ %[A4:8]/8/ %[A4:9]/9/ %[A4:10]/10/ %[A4:10]/11/ %[A4:10]/12/ %[A4:10]/13/ %[A4:10]/14/ %[A4:15]/15/ 56 | SMI Request: due to %[AA:8]/legacy USB/ %[AA:7]/APM/ %[AA:6]/EXTSMI#/ %[AA:5]/Fast-Off/ IRQ: %[AA:4]/12/ %[AA:3]/8/ %[AA:2]/4/ %[AA:1]/3/ %[AA:0]/0/ 57 | Fast-Off Timer: %[A8+1]2d %[A0:4-3]|minutes;stopped;PCICLKs;milliseconds| 58 | !end 59 | 60 | %! end of file 61 | -------------------------------------------------------------------------------- /rbpci119/80867010.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867010.PCI = Vendor 8086h, Device 7010h -- Intel 82371 IDE Ctrlr 4 | %! Last Edit 10jan99 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | Intel 82371FB/SB IDE Controller registers in detail: 12 | Bus Master Interface Base Address: %[20:31-0]8x 13 | IDE timing modes 14 | primary channel: 15 | %[40:15]|dis;en|abled 16 | slave timing register %[40:14]|dis;en|abled 17 | IORDY sampled %[40:13-12]{5432} clocks after DIOx# 18 | recovery time after IORDY is %[40:9-8]{4321} clock(s) 19 | drive 0 enable: %[40:7]/DMA/ %[40:6]/prefetch,post/ %[40:5]/IORDY sampling/ %[40:4]/fast-timing/ 20 | drive 1 enable: %[40:3]/DMA/ %[40:2]/prefetch,post/ %[40:1]/IORDY sampling/ %[40:0]/fast-timing/ 21 | secondary channel: 22 | %[42:15]|dis;en|abled 23 | slave timing register %[42:14]|dis;en|abled 24 | IORDY sampled %[42:13-12]{5432} clocks after DIOx# 25 | recovery time after IORDY is %[42:9-8]{4321} clock(s) 26 | drive 0 enable: %[42:7]/DMA/ %[42:6]/prefetch,post/ %[42:5]/IORDY sampling/ %[42:4]/fast-timing/ 27 | drive 1 enable: %[42:3]/DMA/ %[42:2]/prefetch,post/ %[42:1]/IORDY sampling/ %[42:0]/fast-timing/ 28 | Slave IDE timing: %[44]2x 29 | primary drive 1: 30 | IORDY sampled %[44:3-2]{5432} clocks after DIOx# 31 | recovery time after IORDY is %[44:1-0]{4321} clock(s) 32 | secondary drive 1: 33 | IORDY sampled %[44:7-6]{5432} clocks after DIOx# 34 | recovery time after IORDY is %[44:4-4]{4321} clock(s) 35 | !end 36 | 37 | %! end of file 38 | -------------------------------------------------------------------------------- /rbpci119/80867020.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867020.PCI = Vendor 8086h, Device 7020h -- Intel 82371SB USB 4 | %! Last Edit 9/27/97 by Ralf Brown 5 | %! 6 | 7 | [See file BLANK.PCI for description of formatting specification and how 8 | to create your own device descriptions.] 9 | 10 | !begin 11 | Intel 82371SB USB registers in detail: 12 | I/O space base: %[20:31-0] 13 | USB Specification: %[60:7-4]d.%[60:3-0]d 14 | Misc Status: %[6A]2x (USB clock=%[6A:0]|24;48|MHz) 15 | Legacy Support: A20GATE pass-thru: %[C0:15]|;seq. ended| %[C0:6]|;in progress| (%[C0:5]ed) 16 | USB PIRQ %[C0:13]ed IRQ status: %[C0:12]d 17 | enable SMI: %[C0:7]/A20GATE/ %[C0:4]/USB IRQ/ %[C0:3]/0064 write/ %[C0:2]/0064 read/ %[C0:1]/0060 write/ %[C0:0]/0060 read/ 18 | trap caused by: %[C0:11]/0064 write/ %[C0:10]/0064 read/ %[C0:9]/0060 write/ %[C0:8]/0060 read/ 19 | !end 20 | 21 | %! end of file 22 | -------------------------------------------------------------------------------- /rbpci119/80867030.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867030.PCI = Vendor 8086h, Device 7030h -- Intel 82437VX 4 | %! Last Edit 10jan99 by Ralf Brown 5 | %! 6 | 7 | !begin 8 | 82437VX registers in detail: 9 | Programmable Attribute Map 10 | C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 11 | F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 12 | C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 13 | C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 14 | CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 15 | DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM %[63]3dM 16 | DRAM Row Type: %[68:4]b%[68:0]b %[68:5]b%[68:1]b %[68:6]b%[68:2]b %[68:7]b%[68:3]b 17 | DRAM control: refresh = %[57:2-0]|disabled;50MHz;60MHz;66MHz;reserved| 18 | DRAM hole = %[57:7-6]|none;512K-640K;15M-16M;14M-16M| 19 | EDO Detect mode is %[57:3]ed; Symmetry Detect mode is %[56:0]ed 20 | Fast EDO Path %[56:5]|not;| selected 21 | RAS# asserted for %[56:6+4] clocks on refresh 22 | Speculative Leadoff %[56:4]Ed 23 | Memory Address drive strength is %[56:2-1]|reserved;10mA;16mA;reserved| 24 | DRAM timing: read burst = %[58:6-5]|x444/x444;x333/x444;x222/x333;x322/x333| 25 | write burst = %[58:4-3]|x444;x333;x222;reserved| 26 | RAS-to-CAS = %[58:2]|3;2| clocks 27 | DRAM leadoff = %[58:1-0]|11/7/3;10/6/3;11/7/4;10/6/4| (read/write/precharge) 28 | MA-to-RAS# delay is %[58:7]|one clock;two clocks| 29 | 30 | %! insert rest of device description here 31 | 32 | !end 33 | 34 | %! end of file 35 | -------------------------------------------------------------------------------- /rbpci119/80867100.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867100.PCI = Vendor 8086h, Device 7100h 4 | %! Intel 82439TX System Controller 5 | %! Created 31 Dec 97 by Andy Sawyer 6 | %! Last edit 10jan99 by Ralf Brown 7 | %! 8 | %! Reference : Intel document 29055901.PDF 9 | %! "Intel 430TX PCISET : 82439TX System Controller (MTXC)" 10 | %! 11 | 12 | !begin 13 | 82439TX System Controller registers in detail: [by Andy Sawyer] 14 | 15 | Extended CPU-to-PIIX4 PHLDA# Signalling: %[4F:7]ed 16 | PCI Concurrency Enable: %[50:3]ed 17 | ACPI Control Register: %[79:6]ed 18 | Suspend Refresh Type : %[79:5]|CBR Refresh;Self Refresh| 19 | Normal Refresh Enable: %[79:4]y 20 | Internal Clock Control: %[79:2]ed 21 | 22 | Cache Control: 23 | Seconday Cache Size: %[52:7-6]|Not Populated;256K;512K;Reserved| 24 | L2 SRAM Type: %[52:5-4]|Pipelined Burst SRAM;Reserved;Reserved;Two banks of pipelined burst SRAM| 25 | NA Disable: NA is %[52:3]Ed 26 | Secondary Cache Force Miss: %[52:1]y 27 | First Level Cache Enable: %[52:0]ed 28 | DRAM Cache L2 present: %[53:5]y 29 | DRAM Cache L2 refresh timer: %[53:4-0]d 30 | 31 | SDRAM Control: 32 | Special SDRAM mode select: %[54:8-6](SDMS) 33 | RAS# to CAS# Override: %[54:5]ed 34 | CAS# Latency: %[54:4]{23} 35 | RAS# Timing: %[54:3]|3/5/8;3/4/7| 36 | 64-MBit Technology Enable: %[54:1]y 37 | 38 | DRAM Control: 39 | Refresh RAS# Assertion: %[56:6]{45} Clocks 40 | Fast EDO Lead Off: %[56:5]ed 41 | Speculative Lead Off: %[56:4]Ed 42 | Memory Address Drive Strength: %[56:2]|10;16|ma %[56:1]|10;16|ma 43 | Memory Hole: %[57:7-6]|none;512K-640K;15M-16M;14M-16M| 44 | Enhanced Paging: %[57:4]ed 45 | Detect Mode: %[57:3]ed 46 | Refresh Rate: %[57:2-0]|disabled;15.6;31.2;64.4;125;256;Reserved| 47 | DRAM Timing: 48 | Read Burst Timing: %[58:6-5]|x444/x444;x333/x444;x222/x333;Reserved| 49 | Write Burst Timing: %[58:4-3]|x444;x333;x222;Reserved| 50 | Leadoff Timing: Read %[58:0]|11;10| Write %[58:0]{76} 51 | RAS# Precharge %[58:1]{34} 52 | RAS-to-CAS Delay %[58:0]{43} 53 | DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM 54 | %[63]3dM %[64]3dM %[65]3dM 55 | DRAM Row Type: 56 | Host Frequency: %[67:7]|60;66|MHz 57 | DRAM Row Type: Row 0: %[68:4]b%[68:0]b Row 3: %[68:7]b%[68:3]b 58 | 00=SPM 01=EDO Row 1: %[68:5]b%[68:1]b Row 4: %[67:4]b%[67:0]b 59 | 10=SDRAM Row 2: %[68:6]b%[68:2]b Row 5: %[67:5]b%[67:1]b 60 | 11=Reserved 61 | Memory Address Select Enable: %[67:2]d 62 | %! Note: Intel don't document leadoff timing as the above in as many words, 63 | %! but the answers are still the same :-) 64 | 65 | Programmable Attribute Map 66 | 0F000-0FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R}\t0C000-0C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R} 67 | 0C400-0C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\t0C800-0CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R} 68 | 0CC00-0CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\t0D000-0D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R} 69 | 0D400-0D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\t0D800-0DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R} 70 | 0DC00-0DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\t0E000-0E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R} 71 | 0E400-0E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R}\t0E800-0EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 72 | 0EC00-0EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R} 73 | 74 | Multi-Transaction Timer: %[70:7-2]d 75 | System Management RAM Control: 76 | SMM Space Open: %[73:6]y 77 | SMM Space Closed: %[73:5]y 78 | SMM Space Locked: %[73:4]y 79 | Global SMRAM Enble: %[73:3]y 80 | Compatible SMM Space base Seg: %[73:2-0](C_BASE_SEG) 81 | High SMRAM Enable: %[71:7]e 82 | Extended SMRAM Error: %[71:6]y 83 | SMRAM Cache Strategy: %[71:5]|WriteBack;WriteThru| 84 | SMRAM L1 Cache Enable: %[71:4]e 85 | SMRAM L2 Cache Enable: %[71:3]e 86 | TSEG Size: %[72:2-1](TSEG_SZ) 87 | TSEG Enable: %[72:0]y 88 | !end 89 | 90 | !enum SDMS 91 | Normal SDRAM mode 92 | NOP Command Enable 93 | All Banks Precharge Command Enable 94 | Mode Register Command Enable 95 | CBR Cycle Enable 96 | Reserved 97 | Reserved 98 | Reserved 99 | Reserved 100 | !end 101 | 102 | !enum TSEG_SZ 103 | (TOM-128k) to TOM 104 | (TOM-256k) to TOM 105 | (TOM-512k) to TOM 106 | (TOM-1MB) to TOM 107 | !end 108 | 109 | !enum C_BASE_SEG 110 | Reserved 111 | Reserved 112 | A0000-BFFFFh 113 | Reserved 114 | Reserved 115 | Reserved 116 | Reserved 117 | Reserved 118 | !end 119 | 120 | %! end of file 121 | 122 | -------------------------------------------------------------------------------- /rbpci119/80867110.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867110.PCI = Vendor 8086h, Device 7110h 4 | %! Intel 82731AB PIIX4 PCI-to-ISA Bridge 5 | %! Last Edit 31 Dec 1997 by Andy Sawyer 6 | %! 7 | %! Reference : Intel document 29056201.PDF 8 | %! "82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)" 9 | %! 10 | %! Since the 82371AB indicates that it is a "single function" device 11 | %! for all functions except function 0, version 1,0 of PCICFG.EXE 12 | %! does not correctly display all functions. 13 | %! 14 | %! See also: 15 | %! 80867111.PCI 16 | %! 80867112.PCI 17 | %! 80867113.PCI 18 | !begin 19 | 20 | Intel 82371AB PIIX4 PCI-to-ISA Bridge registers in detail: [by Andy Sawyer] 21 | ISA I/O Recovery Time 22 | DMA Reserved Page Register Aliasing %[4C:7]Ed 23 | 8-bit I/O Recovery %[4C:6]ed - %[4C:5-3]{81234567} SYSCLK 24 | 16-bit I/O Recovery %[4C:2]ed - %[4C:1-0]{3124} SYSCLK 25 | 26 | X-Bus Chip Select 27 | 28 | Microcontroler Location Enable %[4E:10]ed 29 | 1-Meg Extended BIOS Enable %[4E:9]ed 30 | I/O APIC %[4E:8]ed 31 | Extended BIOS Enable %[4E:7]ed 32 | Lower BIOS Enable %[4E:6]ed 33 | Coprocessor Error Fucntion Enable %[4E:5]ed 34 | IRQ12/Mouse Control %[4E:4]|IRQ12;Mouse| 35 | Port 61h Alias Enable %[4E:3]ed 36 | BIOSCS# Write Protect Control %[4E:2]|Read Only;Read Write| 37 | Keyboard Controller I/O Ports %[4E:1]ed 38 | Real-Time Clock I/O ports %[4E:0]ed 39 | 40 | PIRQRC Route Control 41 | PIRCQA Routing %[60:7]Ed - %[60:3-0](PIRQCRRoute) 42 | PIRCQB Routing %[61:7]Ed - %[61:3-0](PIRQCRRoute) 43 | PIRCQC Routing %[62:7]Ed - %[62:3-0](PIRQCRRoute) 44 | PIRCQD Routing %[63:7]Ed - %[63:3-0](PIRQCRRoute) 45 | 46 | Serial IRQ Control 47 | Serial IRQ Enable %[64:7]ed 48 | Serial IRQ Mode %[64:6]|Quiet;Continuous| 49 | Serial IRQ Frame Size %[64:5-2+17]d 50 | Start Frame Pulse Width %[64:1-0]|4;6;8;Reserved| 51 | 52 | Top of Memory Register 53 | Top of Memory %[69:7-4+1]d Mbyte 54 | ISA/DMA Lower BIOS %[69:3]|not ;|forwarded to PCI 55 | 640k-768k Memory Region %[69:2]|not ;|forwarded to PCI 56 | ISA/DMA 512k-640k Region %[69:1]|not ;|forwarded to PCI 57 | 58 | Misc. Status Register 59 | SERR# Generation %[6A:15]d 60 | Host-to-PCI Bridge Retry enable %[6A:7]ed 61 | 62 | Motherboard Device DMA Control 0 63 | Type F DMA Buffer Enabled %[76:7]ed 64 | Type F DMA Channel Routing %[76:2-0](MBDMA) 65 | Motherboard Device DMA Control 1 66 | Type F DMA Buffer Enabled %[77:7]ed 67 | Type F DMA Channel Routing %[77:2-0](MBDMA) 68 | 69 | APIC Base Address Relocation Register 70 | A12 Mask %[80:6]d 71 | Base Address FEC0%[80:5-2]x%[80:1-0]x00h 72 | 73 | Detrministic Latency Control Register 74 | SERR# on delayed transaction timeout %[82:3]ed 75 | USB Passive Release %[82:2]ed 76 | Passive Release %[82:1]ed 77 | Delayed Transactions %[82:0]ed 78 | 79 | PCI DMA Configuration 80 | DMA Channel 7 %[90:15-14](DMAType) 81 | DMA Channel 6 %[90:13-12](DMAType) 82 | DMA Channel 5 %[90:11-10](DMAType) 83 | DMA Channel 3 %[90:7-6](DMAType) 84 | DMA Channel 2 %[90:5-4](DMAType) 85 | DMA Channel 1 %[90:3-2](DMAType) 86 | DMA Channel 0 %[90:1-0](DMAType) 87 | 88 | Distributed DMA Slave Base Pointer Registers 89 | Channel 0-3 %[92:15-6<6]4x 90 | Channel 5-7 %[94:15-6<6]4x 91 | 92 | General Configuration Register 93 | KBCCS# %[B0:31]|KBCCS#;GPO26| 94 | RTCALE %[B0:30]|RTCALE;GPO25| 95 | RTCCS# %[B0:29]|RTCCS#;GPO24| 96 | XOE#/XDIR# %[B0:28]|XOE#/XDIR#;GPO22/GPO23| 97 | RI# %[B0:27]|RI#;GPI12| 98 | LID %[B0:25]|LID;GPI10| 99 | BATLOW# %[B0:24]|BATLOW#;GPI9| 100 | THRM# %[B0:23]|THRM#;GPI8| 101 | SUS_STAT2# %[B0:22]|SUS_STAT2#;GPO21| 102 | SUS_STAT1# %[B0:21]|SUS_STAT1#;GPO20| 103 | ZZ %[B0:20]|ZZ;GPO19| 104 | PCI_STP# %[B0:19]|PCI_STP#;GPO18| 105 | CPU_STP# %[B0:18]|CPU_STP#;GPO17| 106 | SUSB#/SUSC# %[B0:17]|SUSB#/SUSC#;GPO15/16| 107 | SERIRQ %[B0:16]|GPI7;SERIRQ| 108 | SMBALERT# %[B0:15]|SMBALERT#;GPI11| 109 | IRQ8# %[B0:14]|GPI6;IRQ8#| 110 | PC/PCI REQC/GNTC %[B0:10]|GPI4/GPO11;REQC/GNTC| 111 | PC/PCI REQB/GNTB %[B0:9]|GPI3/GPO10;REQB/GNTB| 112 | PC/PCI REQA/GNTA %[B0:8]|GPI2/GPO9;REQA/GNTA| 113 | 114 | Decode configuration %[B0:1]|Subtractive;Positive| 115 | PnP Address Decode %[B0:6]ed 116 | Alternate Access Mode %[B0:5]ed 117 | IDE Secondary Interface %[B0:4]Ed 118 | 119 | Secondary IDE Signal Interface %[B0:12]|Enabled;Tri-State| 120 | Primary IDE Signal Interface %[B0:11]|Enabled;Tri-State| 121 | 122 | CONFIG2 Status %[B0:3]d 123 | CONFIG1 Status %[B0:2]d (%[B0:2]|Pentium;Pentium II|) 124 | ISA/EIO Select %[B0:0]|EIO;ISA| 125 | 126 | Real Time Clock Configuration 127 | RTC Positive Decode %[CB:5]ed 128 | Lock Upper RAM Bytes %[CB:4]ed 129 | Lock Lower RAM Bytes %[CB:3]ed 130 | Upper RAM Enable %[CB:2]ed 131 | RTC Enable %[CB:0]ed 132 | 133 | !end 134 | 135 | !enum PIRQCRRoute 136 | Reserved 137 | Reserved 138 | Reserved 139 | IRQ 3 140 | IRQ 4 141 | IRQ 5 142 | IRQ 6 143 | IRQ 7 144 | Reserved 145 | IRQ 9 146 | IRQ 10 147 | IRQ 11 148 | IRQ 12 149 | Reserved 150 | IRQ 14 151 | IRQ 15 152 | !end 153 | 154 | !enum MBDMA 155 | DMA Channel 0 156 | DMA Channel 1 157 | DMA Channel 2 158 | DMA Channel 3 159 | Disabled 160 | DMA Channel 5 161 | DMA Channel 6 162 | DMA Channel 7 163 | !end 164 | 165 | !enum DMAType 166 | Normal ISA DMA 167 | PC/PCI DMA 168 | Distributed DMA 169 | Reserved 170 | !end 171 | 172 | %! end of file 173 | -------------------------------------------------------------------------------- /rbpci119/80867111.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867111.PCI = Vendor 8086h, Device 7111h 4 | %! Intel 82731AB PIIX4 Ultra DMA/33 IDE Controller 5 | %! Last Edit 31 Dec 1997 by Andy Sawyer 6 | %! 7 | %! Reference : Intel document 29056201.PDF 8 | %! "82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)" 9 | %! 10 | %! See also : 80867110.PCI,80867112.PCI,80867113.PCI 11 | %! 12 | %! Note, the entry listed below as "Fast Timing" is rather confusingly 13 | %! described by intel as "DMA Timing Enable Only", although it doesn't 14 | %! actually affect the timing for DMA operations... 15 | %! 16 | 17 | !begin 18 | Intel 82371AB PIIX4 IDE Controller registers in detail: [by Andy Sawyer] 19 | IDE Timing Modes 20 | Primary Channel %[40:15]ed 21 | Slave Timing Register %[40:14]ed 22 | IORDY Sample Point %[40:13-12]{5432} clocks after DIOx# 23 | Recovery Time after IORDY %[40:9-8]{4321} clock(s) 24 | Drive 0: 25 | Fast Timing %[40:3](FastTiming) 26 | Prefetch and Posting %[40:2]ed 27 | IORDY Sample Point Drive Select %[40:1]ed 28 | Fast Timing Bank Drive Select %[40:0]ed 29 | Drive 1: 30 | Fast timing %[40:7](FastTiming) 31 | Prefetch and Posting %[40:6]ed 32 | IORDY Sample Point Drive Select %[40:5]ed 33 | Fast Timing Bank Drive Select %[40:4]ed 34 | 35 | Secondary Channel %[42:15]ed 36 | Slave Timing Register %[42:14]ed 37 | IORDY Sample Point %[42:13-12]{5432} clocks after DIOx# 38 | Recovery Time after IORDY %[42:9-8]{4321} clock(s) 39 | Drive 0: 40 | Fast timing %[42:3](FastTiming) 41 | Prefetch and Posting %[42:2]ed 42 | IORDY Sample Point Drive Select %[42:1]ed 43 | Fast Timing Bank Drive Select %[42:0]ed 44 | Drive 1: 45 | Fast timing %[42:7](FastTiming) 46 | Prefetch and Posting %[42:6]ed 47 | IORDY Sample Point Drive Select %[42:5]ed 48 | Fast Timing Bank Drive Select %[42:4]ed 49 | 50 | Slave IDE Timing Register 51 | Primary Drive 1: 52 | IORDY Sample Point %[44:3-2]{5432} clocks after DIOx# 53 | Recovery Time %[44:1-0]{4321} clock(s) 54 | Secondary Drive 1: 55 | IORDY Sample Point %[44:7-6]{5432} clocks after DIOx# 56 | Recovery Time %[44:5-4]{4321} clock(s) 57 | 58 | Ultra DMA/33 Control Register 59 | Primary Drive 0 UDMA %[48:0]ed 60 | Primary Drive 1 UDMA %[48:1]ed 61 | Secondary Drive 0 UDMA %[48:2]ed 62 | Secondary Drive 1 UDMA %[48:3]ed 63 | 64 | Ultra DMA/33 Timing Register 65 | Primary Drive 0 Cycle Time %[4A:1-0](UDMATiming) 66 | Primary Drive 1 Cycle Time %[4A:5-4](UDMATiming) 67 | Secondary Drive 0 Cycle Time %[4A:9-8](UDMATiming) 68 | Secondary Drive 1 Cycle Time %[4A:13-12](UDMATiming) 69 | !end 70 | 71 | !enum FastTiming 72 | DMA & PIO Modes 73 | DMA mode only 74 | !end 75 | 76 | !enum UDMATiming 77 | 4/6 78 | 3/5 79 | 2/4 80 | Reserved 81 | !end 82 | 83 | %! end of file 84 | -------------------------------------------------------------------------------- /rbpci119/80867112.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867112.PCI = Vendor 8086h, Device 7112h 4 | %! Intel 82731AB PIIX4 USB Host Controller 5 | %! Last Edit 31 Dec 1997 by Andy Sawyer 6 | %! 7 | %! Reference : Intel document 29056201.PDF 8 | %! "82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)" 9 | %! 10 | %! See also : 80867110.PCI,80867111.PCI,80867113.PCI 11 | %! 12 | 13 | !begin 14 | Intel 82371AB PIIX4 USB Host Controller registers in detail: [by Andy Sawyer] 15 | 16 | USB Specification: %[60:7-4]d.%[60:3-0]d 17 | Legacy Support: 18 | A20GATE Pass-through: %[C0:5]ed %[C0:15]|;seq. ended| %[C0:6]|;in progress| 19 | USB PIRQ %[C0:13]ed 20 | USB IRQ Status %[C0:12]|in;|active 21 | Trap caused by: %[C0:11]|;0064 write| %[C0:10]|;0064 read| %[C0:9]|;0060 write| %[C0:8]|;0060 read| 22 | SMI Enable: %[C0:7]|;A20GATE| %[C0:4]|;USB IRQ| %[C0:3]|;0064 write| %[C0:2]|;0064 read| %[C0:1]|;0060 write| %[C0:0]|;0060 read| 23 | 24 | Misc. Status: 25 | RTC Index Read is %[FF:4]ed 26 | 27 | !end 28 | 29 | %! end of file 30 | 31 | -------------------------------------------------------------------------------- /rbpci119/80867113.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867113.PCI = Vendor 8086h, Device 7113h 4 | %! Intel 82731AB PIIX4 Power Management Controller 5 | %! Last Edit 31 Dec 1997 by Andy Sawyer 6 | %! 7 | %! Reference : Intel document 29056201.PDF 8 | %! "82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)" 9 | %! 10 | %! See also : 80867110.PCI,80867111.PCI,80867113.PCI 11 | %! 12 | 13 | !begin 14 | Intel 82371AB PIIX4 Power Management Controller in detail: [by Andy Sawyer] 15 | 16 | Power Management I/O Space is %[80:0]ed, Base Address is %[40:15-6<6]4x 17 | 18 | Count A/B 19 | Fast Burst Timer Count %[48:4-0]d 20 | Slow Burst Timer Count: %[44:31-28]d 21 | Bus Master Timer Count: %[48:22-18]d 22 | Software Idle Timer Count: %[44:11-8]d 23 | Idle Timer Count A: %[44:3-0]d 24 | Idle Timer Count B: %[44:16-12]d 25 | Idle Timer Count C: %[44:21-17]d 26 | Idle Timer Count D: %[44:27-23]d 27 | Device 0 Idle Timer Resolution: %[44:4]|8 seconds;1 second| 28 | Device 1 Idle Timer Resolution: %[44:5]|8 seconds;1 second| 29 | Device 2 Idle Timer Resolution: %[44:6]|8 seconds;1 second| 30 | Device 3 Idle Timer Resolution: %[44:7]|8 seconds;1 ms| 31 | Device 8 Idle Timer Resolution: %[48:15]|1 second;1 ms| 32 | Device 11 Idle Timer Resolution: %[44:22]|1 second;1 minute| 33 | Video Status: %[48:24]d 34 | ZZ Enable %[48:14]ed 35 | Thermal Duty Cycle %[48:11-13](DutyCycle) 36 | Processor PLL Lock Count %[48:10-6]d 37 | Processor PLL Lock Resolution %[48:5]|1 ms;1 microsecond| 38 | 39 | General Purpose Input Control 40 | Device 13 GPI is %[4C:12]ed - asserted %[4C:25](HiLo), %[4C:27](LE) sensitive 41 | Device 12 GPI is %[4C:11]ed - asserted %[4C:24](HiLo), %[4C:26](LE) sensitive 42 | Device 11 GPI is %[4C:10]ed - asserted %[4C:23](HiLo) 43 | Device 10 GPI is %[4C:9]ed - asserted %[4C:22](HiLo) 44 | Device 9 GPI is %[4C:8]ed - asserted %[4C:21](HiLo) 45 | Device 8 GPI is %[4C:7]ed - asserted %[4C:20](HiLo) 46 | Device 7 GPI is %[4C:6]ed - asserted %[4C:19](HiLo) 47 | Device 6 GPI is %[4C:5]ed - asserted %[4C:18](HiLo) 48 | Device 5 GPI is %[4C:4]ed - asserted %[4C:17](HiLo) 49 | Device 4 GPI is %[4C:3]ed - asserted %[4C:16](HiLo) 50 | Device 3 GPI is %[4C:2]ed - asserted %[4C:15](HiLo) 51 | Device 2 GPI is %[4C:1]ed - asserted %[4C:14](HiLo) 52 | Device 1 GPI is %[4C:0]ed - asserted %[4C:13](HiLo) 53 | 54 | Device Activity A 55 | Device 1 event reloads %[54:28]|slow;fast| burst timer 56 | Device 2 event reloads %[54:29]|slow;fast| burst timer 57 | Device 3 event reloads %[54:30]|slow;fast| burst timer 58 | Device 5 event reloads %[54:31]|slow;fast| burst timer 59 | 60 | Device 0 Burst Timer Reload %[54:14]ed, Global Timer Reload %[54:0]ed 61 | Device 1 Burst Timer Reload %[54:15]ed, Global Timer Reload %[54:1]ed 62 | Device 2 Burst Timer Reload %[54:16]ed, Global Timer Reload %[54:2]ed 63 | Device 3 Burst Timer Reload %[54:17]ed, Global Timer Reload %[54:3]ed 64 | Device 4 Burst Timer Reload %[54:18]ed, Global Timer Reload %[54:4]ed 65 | Device 5 Burst Timer Reload %[54:19]ed, Global Timer Reload %[54:5]ed 66 | Device 6 Burst Timer Reload %[54:20]ed, Global Timer Reload %[54:6]ed 67 | Device 7 Burst Timer Reload %[54:21]ed, Global Timer Reload %[54:7]ed 68 | Device 8 Burst Timer Reload %[54:22]ed, Global Timer Reload %[54:8]ed 69 | Device 9 Burst Timer Reload %[54:23]ed, Global Timer Reload %[54:9]ed 70 | Device 10 Burst Timer Reload %[54:24]ed, Global Timer Reload %[54:10]ed 71 | Device 11 Burst Timer Reload %[54:25]ed, Global Timer Reload %[54:11]ed 72 | Device 12 Burst Timer Reload %[54:26]ed, Global Timer Reload %[54:12]ed 73 | Device 13 Burst Timer Reload %[54:27]ed, Global Timer Reload %[54:13]ed 74 | 75 | Device Activity B 76 | SMI# Generation on APMC Read %[58:25]ed 77 | Video detect generates reload on Device 11 %[58:24]ed 78 | Percentage Bus Utilisation Threshold %[58:23-16]d 79 | Bus Utilisation Threshold %[58:15-8]d 80 | IRQ Global Reload event %[58:6]ed 81 | IRQ Clock event %[58:1]ed 82 | IRQ0 Clock event %[58:0]ed 83 | IRQ8 Clock event %[58:5]ed 84 | PME Clock event %[58:4]ed 85 | Keyboard/Mouse global read event %[58:2]ed 86 | 87 | Device Resources 88 | LPT DMA Select %[50:21-22](LPTDMA) 89 | LPT Port Enable %[50:18]ed 90 | LPT DMA Monitor Enable %[50:17]ed 91 | LPT Decode Select %[60:26-25](LPTDecode) 92 | 93 | Serial Port B Monitor Enable %[50:16]ed 94 | Serial Port A Monitor Enable %[50:14]ed 95 | 96 | FDC Monitor Enable %[50:12]ed 97 | FDC DMA Monitor Enable %[50:11]ed 98 | FDC Decode Select %[60:28](FDCDecode) 99 | 100 | DACK7 Enable %[50:5]ed 101 | DACK6 Enable %[50:4]ed 102 | DACK5 Enable %[50:3]ed 103 | DACK3 Enable %[50:2]ed 104 | DACK1 Enable %[50:1]ed 105 | DACK0 Enable %[50:0]ed 106 | 107 | Graphics A/B Segment Enable %[5C:27]ed 108 | Graphics I/O Enable %[5C:26]ed 109 | Linear Frame Buffer Decode Enable %[5C:24]ed 110 | Base Address: %[5C:21-10<20]8x Decode Mask: %[5C:23-22<20]8x 111 | 112 | SoundBlaster EIO Enable %[5C:25]ed 113 | SoundBlaster 8/16-bit Decode Enable %[5C:3]ed 114 | SoundBlaster Decode Select %[5C:6-5](SBDecode) 115 | 116 | Microsoft Sound System EIO Enable %[60:24]ed 117 | Microsoft Sound System Decode enable %[5C:7]ed 118 | Microsoft Sound System Decode Select %[5C:9-8](MSSDecode) 119 | 120 | MIDI EIO enable %[60:20]ed 121 | MIDI Enable %[5C:0]ed 122 | MIDI Decode Select %[5C:2-1](MIDIDecode) 123 | 124 | Game Port enable %[5C:4]ed 125 | Game Port EIO enable %[60:31]ed 126 | 127 | Keyboard EIO enable %[60:30]ed 128 | Serial Port B Decode Select %[64:30-28](COMDecode) 129 | Serial Port A Decode Select %[64:26-24](COMDecode) 130 | Device 5 EIO enable %[60:29]ed 131 | Device 6 EIO Enable %[64:27]ed 132 | Device 7 EIO Enable %[64:31]ed 133 | Device 8 EIO Enable %[5C:31]ed 134 | Device 9 EIO enable %[60:22]ed 135 | Device 9 Generic Decode Chip Select %[60:23]ed 136 | Device 9 Generic Decode Monitor Enable %[60:21]ed 137 | Device 9 Generic Decode Mask %[60:19-16]4x 138 | Device 9 Generic Decode Base Address %[60:15-0]4x 139 | Device 10 EIO Enable %[64:22]ed 140 | Device 10 Generic Decode Chip Select %[64:23]ed 141 | Device 10 Generic Decode Monitor Enable %[64:21]ed 142 | Device 10 Generic Decode Mask %[64:19-16]4x 143 | Device 10 Generic Decode Base Address %[64:15-0]4x 144 | Device 11 EIO Enable %[5C:28]ed 145 | Device 11 IRQ12 (Mouse) Enable %[50:20]ed 146 | Device 11 IRQ1 (Keyboard) Enable %[50:19]ed 147 | Device 12 EIO Enable %[5C:29]ed 148 | Device 13 EIO Enable %[5C:30]ed 149 | 150 | Device 12 I/O Monitor %[68:20]ed 151 | Base Address: %[68:15-0]4x Decode Mask : %[68:19-16]4x 152 | 153 | Device 12 Memory Monitor %[6C:7]ed 154 | Base Address: %[6C:31-15<15]8x Decode Mask : %[6C:6-0<15]8x 155 | 156 | Device 13 I/O Monitor %[70:20]ed 157 | Base Address: %[70:15-0]4x Decode Mask : %[70:19-16]4x 158 | 159 | Device 13 Memory Monitor %[74:7]ed 160 | Base Address: %[74:31-15<15]8x Decode Mask : %[74:6-0<15]8x 161 | 162 | Generic I/O Montior 0 %[78:20]ed 163 | Base Address: %[78:15-0]4x Decode Mask : %[78:19-16]4x 164 | 165 | Generic I/O Monitor 1 %[7C:20]ed 166 | Base Address: %[7C:15-0]4x Decode Mask : %[7C:19-16]4x 167 | 168 | 169 | SMBUS Configuration 170 | Revision ID: %[D6]2x 171 | Base Address: %[90:15-4<4]4x 172 | Interrupt Select: %[D2:3-1](SMBInt) 173 | Controller Host Interface: %[D2:0]ed 174 | Slave Command: %[D3]2x 175 | Slave Shadow Port 1 Address: %[D4:7-1]2x R/W: %[D4:0]|Write;Read| (**CHECK THIS**) 176 | Slave Shadow Port 2 Address: %[D5:7-1]2x R/W: %[D5:0]|Write;Read| (**CHECK THIS**) 177 | 178 | !end 179 | 180 | 181 | !enum DutyCycle 182 | Reserved 183 | 12.5% 184 | 25% 185 | 37.5% 186 | 50% 187 | 62.5% 188 | 75% 189 | 87.5% 190 | !end 191 | 192 | !enum HiLo 193 | high 194 | low 195 | !end 196 | 197 | !enum LE 198 | level 199 | edge 200 | !end 201 | 202 | !enum MSSDecode 203 | 530h-537h 204 | 604h-60Bh 205 | E80h-E87h 206 | F40h-F47h 207 | !end 208 | 209 | !enum SBDecode 210 | 220-22Fh, 230-233h 211 | 240-24Fh, 250-253h 212 | 260-26Fh, 270-273h 213 | 280-28Fh, 290-293h 214 | !end 215 | 216 | !enum MIDIDecode 217 | 300-303h 218 | 310-313h 219 | 320-323h 220 | 330-333h 221 | !end 222 | 223 | !enum FDCDecode 224 | Primary (3F0h-3F5h,3F7h) 225 | Secondary (370h-375h,377h) 226 | !end 227 | 228 | !enum LPTDMA 229 | DACK0 230 | DACK1 231 | DACK3 232 | Reserved 233 | !end 234 | 235 | !enum LPTDecode 236 | 3BCh-3BFh, 7BCh-7BEh 237 | 378h-37Fh, 778h-77Ah 238 | 278h-27Fh, 678h-67Ah 239 | Reserved 240 | !end 241 | 242 | 243 | !enum COMDecode 244 | 3F8h-3FFh (COM1) 245 | 2F8h-2FFh (COM2) 246 | 220h-227h 247 | 228h-22Fh 248 | 238h-23Fh 249 | 2E8h-2EFh (COM4) 250 | 338h-33Fh 251 | 3E8h-3EFh (COM3) 252 | !end 253 | 254 | !enum SMBInt 255 | SMI# 256 | Reserved 257 | Reserved 258 | Reserved 259 | IRQ9 260 | Reserved 261 | Reserved 262 | Reserved 263 | !end 264 | 265 | %! end of file 266 | 267 | -------------------------------------------------------------------------------- /rbpci119/80867190.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867190.PCI = Vendor 8086h, Device 7190h (Intel 440BX PCI-Host) 4 | %! Last Edit 18jun98 by Ralf Brown 5 | %! 6 | 7 | !begin 8 | 82443BX%[08](Rev) Registers in detail: 9 | 10 | Programmable Attribute Map 11 | \tC000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 12 | \tF000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 13 | \tC400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 14 | \tC800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 15 | \tCC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}% 16 | \t8000-9FFF: %[59:2]{-C}%[59:1]{-W}%[59:0]{-R} 17 | 18 | DRAM type: %[57:4-3]|EDO;SDRAM;registered SDRAM;reserved|\t\trefresh rate: %[57:2-0](refresh) 19 | DRAM Row Boundaries: %[60*8]4dM %[61*8]4dM %[62*8]4dM %[63*8]4dM %[64*8]4dM %[65*8]4dM %[66*8]4dM %[67*8]4dM 20 | SDRAM Type: %[50:24](ECC) %[50:25](ECC) %[50:26](ECC) %[50:27](ECC) %[50:28](ECC) %[50:29](ECC) %[50:30](ECC) %[50:31](ECC) 21 | Row Page Size: %[74:1-0](PS) %[74:3-2](PS) %[74:5-4](PS) %[74:7-6](PS) %[74:9-8](PS) %[74:11-10](PS) %[74:13-12](PS) %[74:15-14](PS) 22 | Banks per Row: %[78:8](BpR) %[78:9](BpR) %[78:10](BpR) %[78:11](BpR) %[78:12](BpR) %[78:13](BpR) %[78:14](BpR) %[78:15](BpR) 23 | EDO DRAM timing: add one RASx# wait = %[58:1]y, add one wait to first CASx# = %[58:0]y 24 | SDRAM timing (clks): Leadoff=%[76:3]|4;3|, CAS# latency=%[76:2]|3;2|, RAS-to-CAS=%[76:1]|3;2|, RAS# prechg=%[76:0]|3;2| 25 | SDRAM mode select: %[76:7-5](MS)\tDRAM Idle Timer: %[78:3-0](DIT) 26 | DRAM data asserted: %[50:18]|one clock after;on same clock as| snoop 27 | Fixed DRAM Hole: %[68:7-6]|none ;512K-640K;15M-16M;reserved|\tModuleMode: %[57:5|76:4](MM) 28 | WSC# handshake: %[50:15]Ed\t\tECC signals always driven for EDO: %[50:17]y 29 | IDSEL redirection: %[50:16]|IDSEL1/AD12;IDSEL7/AD18|\tHost/DRAM frequency: %[50:13-12]|100 MHz;reserved;66 MHz;reserved| 30 | AGP-to-PCI access: %[50:11]ed \tPCI-agent access to aperture: %[50:10]Ed 31 | Graphics Aperture: %[50:9]ed \tDRAM integrity mode: %[50:8-7](integ) 32 | ECC diagnostics mode: %[50:6]ed \tMDA on PCI/ISA: %[50:5]|absent;present| 33 | Posting Host USWC: %[50:3]ed \tIn-Order Queue depth: %[50:2]|1;maximum| 34 | 35 | SMRAM Control: SMM Space %[72:6]/Open/ %[72:5]/Closed/ %[72:4]/Locked/ %[72:3]/Enabled/ at %[72:2-0<12+32768]4x 36 | Ext. SMRAM Control: Using %[73:7]|compatible;high| SMRAM; TSEG (%[73:0]ed) is %[73:2-1]|128K;256K;512K;1M| 37 | SMRAM cacheable: %[73:5]/globally/ %[73:4]/L1/ %[73:3]/L2/ 38 | have %[73:6]|not ;|detected non-SMM access to closed SMRAM 39 | Power Management: enable %[7A:7]/SDRAM powerdown,/ %[7A:6]/ACPI ctrl reg,/ %[7A:4]/normal refresh/ 40 | quick-start %[7A:3]ed, dynamic clock gating %[7A:2]ed 41 | AGP %[7A:1]Ed, CPU reset w/o PCIRST %[7A:0]ed 42 | suspend refresh type is %[7A:5]|self-refresh;CBR| 43 | Suspend CBR Refresh: automatic rate adjustment %[7B:12]ed, rate = %[7B:11-0]d 44 | 45 | Error Address: error address %[80:31-12<12]8x, %[80:1]/multi-bit//%[80:0]/single-bit/ error 46 | Error Command: enable SERR# on: %[90:7]/AGP outs. aperture/ %[90:6]/inv AGP DRAM access/ 47 | %[90:5]/invalid GATT/ %[90:4]/Target Abort/ %[90:3]/Thermal Throttle/ 48 | %[90:1]/multi-bit error/ %[90:0]/single-bit error/ 49 | SERR# mode: %[90:2]|single PCI clock;level mode| 50 | Error Status: detected %[91:12]/Read//%[91:11]/Write/ thermal throttle 51 | %[91:10]/AGP outside aperture/ %[91:9]/inv AGP DRAM access/ %[91:8]/invalid GATT/ 52 | %[91:4]/multi-bit error/ (row %[91:7-5]d), %[91:0]/single-bit error/ (row %[91:3-1]d) 53 | 54 | AGP Control: AGP %[A8:8]ed, sideband addr %[A8:9]ed, %[A8:1-0](AGPxfer) xfer rate 55 | forced ordering of snoop-writes/AGP reads is %[B0:15]Ed 56 | Graphics Aperture write/AGP read sync is %[B0:13]ed 57 | Graphics Translation Lookaside Buffer is %[B0:7]ed 58 | Aperture Size Mask (bits 27-22) = %[B4:5-0]6b 59 | Graphics Aperture Translation Table at %[B8:31-12<12]8x 60 | AGP Jam Latch: %[F0:8]/weak//%[F0:9]/strng/ pull-up, %[F0:6]/weak//%[F0:7]/strng/ pull-down 61 | 62 | DRAM Write Thermal Throttling Control: Read Write 63 | Global DRAM Write Sampling Window (ms): %[E8:13-6<2]d\t\t%[E4:13-6<2]d 64 | Global QWORD Threshold: %[E8:37-26*215]d\t\t%[E0:37-26*215]d 65 | Throttle Time (* sampling window length): %[E8:25-20]d\t\t%[E0:25-20]d 66 | Throttle Monitoring Window (DRAM CLKs): %[E8:19-13<4]d\t\t%[E0:19-13<4]d 67 | Throttle QWORD Maximum: %[E8:12-3]d\t\t%[E0:12-3]d 68 | DRAM Throttle Mode: %[E8:2-0](throt)\t\t%[E0:2-0](throt) 69 | lock: %[E4:31]Y 70 | 71 | Memory Buffers (Speed x Strength): 72 | MAA[13:0],WEA#,SRASA#,SCASA# %[CA:22](Spd)x%[69:39-38](Str1) 73 | MAB[12:11,9:0],MAB[13,10],WEB#,SRASB#,SCABS# %[CA:21](Spd)x%[69:37-36](Str1) 74 | MD[63:0] control 1 %[CA:19](Spd)x%[69:33-32](Str2) 75 | MD[63:0] control 2 %[CA:20](Spd)x%[69:35-34](Str2) 76 | MECC[7:0] control 1 %[CA:17](Spd)x%[69:29-28](Str2) 77 | MECC[7:0] control 2 %[CA:18](Spd)x%[69:31-30](Str2) 78 | CSB7#/CKE5 %[CA:16](Spd)x%[69:27-26](Str1) 79 | CSA7#/CKE3 %[CA:15](Spd)x%[69:25-24](Str1) 80 | CSB6#/CKE4 %[CA:14](Spd)x%[69:23-22](Str1) 81 | CSA6#/CKE2 %[CA:13](Spd)x%[69:21-20](Str1) 82 | CSA5#/RASA5#, CSB5#/RASB5# %[CA:12](Spd)x%[69:19](Str3) 83 | CSA4#/RASA4#, CSB4#/RASB4# %[CA:11](Spd)x%[69:18](Str3) 84 | CSA3#/RASA3#, CSB3#/RASB3# %[CA:10](Spd)x%[69:17](Str3) 85 | CSA2#/RASA2#, CSB2#/RASB2# %[CA:9](Spd)x%[69:16](Str3) 86 | CSA1#/RASA1#, CSB1#/RASB1# %[CA:8](Spd)x%[69:15](Str3) 87 | CSA0#/RASA0#, CSB0#/RASB0# %[CA:7](Spd)x%[69:14](Str3) 88 | DQMA5/CASA5# %[CA:6](Spd)x%[69:13-12](Str4) 89 | DQMA1/CASA1# %[CA:5](Spd)x%[69:11-10](Str1) 90 | DQMB5/CASB5# %[CA:4](Spd)x%[69:9-8](Str4) 91 | DQMB1/CASB1# %[CA:3](Spd)x%[69:7-6](Str4) 92 | DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# %[CA:2](Spd)x%[69:5-4](Str1) 93 | CKE1/GCKE %[CA:1](Spd)x%[69:3-2](Str1) 94 | CKE0/FENA %[CA:0](Spd)x%[69:1-0](Str1) 95 | !end 96 | 97 | !enum Rev 98 | \ 99 | \ 100 | \ step B-1 101 | \ 102 | !end 103 | 104 | !enum refresh 105 | disabled 106 | 15.6 us 107 | 31.2 us 108 | 62.4 us 109 | 124.8 us 110 | 249.6 us 111 | reserved 112 | !end 113 | 114 | !enum ECC 115 | \ ECC 116 | noECC 117 | !end 118 | 119 | !enum PS 120 | \ 2 KB 121 | \ 4 KB 122 | \ 8 KB 123 | \ rsvd 124 | !end 125 | 126 | !enum BpR 127 | \ two \ 128 | \ four 129 | !end 130 | 131 | !enum integ 132 | non-ECC 133 | parity 134 | ECC 135 | ECC w/ hw scrubbing 136 | !end 137 | 138 | !enum MS 139 | normal operation 140 | issue NOP commands 141 | All-Banks-Precharge 142 | mode register set 143 | CBR cycles 144 | reserved 145 | !end 146 | 147 | !enum MM 148 | 3 DIMMs, powerdown enabled 149 | 4 DIMMs, no power-down 150 | 3 DIMMs, no power-down 151 | 3 DIMMs, no power-down 152 | !end 153 | 154 | !enum DIT 155 | 0 clocks 156 | 2 clocks 157 | 4 clocks 158 | 8 clocks 159 | 10 clocks 160 | 12 clocks 161 | 16 clocks 162 | 32 clocks 163 | infinite 164 | !end 165 | 166 | !enum throt 167 | rsvd 168 | rsvd 169 | rsvd 170 | rsvd 171 | normal 172 | rsvd 173 | !end 174 | 175 | !enum Spd 176 | \ 66 MHz \ 177 | 100 MHz \ 178 | !end 179 | 180 | !enum Str1 181 | 1 (66/100) 182 | rsvd 183 | 2 (66/100) 184 | 3 (66/100) 185 | !end 186 | 187 | !enum Str2 188 | 1 (66/100) 189 | rsvd 190 | 2 (66/100) 191 | 3 (100 only) 192 | !end 193 | 194 | !enum Str3 195 | 1 (66/100) 196 | 2 (66/100) 197 | !end 198 | 199 | !enum Str4 200 | 1 (66/100) 201 | rsvd 202 | 2 (66/100) 203 | 3 (66 only) 204 | !end 205 | 206 | !enum AGPxfer 207 | default 208 | 1x 209 | 2x 210 | illegal 211 | !end 212 | -------------------------------------------------------------------------------- /rbpci119/80867192.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename 80867190.PCI = Vendor 8086h, Device 7190h (Intel 440BX PCI-Host) 4 | %! Last Edit 18jun98 by Ralf Brown 5 | %! 6 | 7 | !begin 8 | 82443BX Registers in detail: 9 | 10 | Programmable Attribute Map 11 | \tC000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}% 12 | \tF000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R} 13 | \tC400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R} 14 | \tC800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R} 15 | \tCC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}% 16 | \t8000-9FFF: %[59:2]{-C}%[59:1]{-W}%[59:0]{-R} 17 | 18 | DRAM type: %[57:4-3]|EDO;SDRAM;registered SDRAM;reserved|\t\trefresh rate: %[57:2-0](refresh) 19 | DRAM Row Boundaries: %[60*8]4dM %[61*8]4dM %[62*8]4dM %[63*8]4dM %[64*8]4dM %[65*8]4dM %[66*8]4dM %[67*8]4dM 20 | SDRAM Type: %[50:24](ECC) %[50:25](ECC) %[50:26](ECC) %[50:27](ECC) %[50:28](ECC) %[50:29](ECC) %[50:30](ECC) %[50:31](ECC) 21 | Row Page Size: %[74:1-0](PS) %[74:3-2](PS) %[74:5-4](PS) %[74:7-6](PS) %[74:9-8](PS) %[74:11-10](PS) %[74:13-12](PS) %[74:15-14](PS) 22 | Banks per Row: %[78:8](BpR) %[78:9](BpR) %[78:10](BpR) %[78:11](BpR) %[78:12](BpR) %[78:13](BpR) %[78:14](BpR) %[78:15](BpR) 23 | EDO DRAM timing: add one RASx# wait = %[58:1]y, add one wait to first CASx# = %[58:0]y 24 | SDRAM timing (clks): Leadoff=%[76:3]|4;3|, CAS# latency=%[76:2]|3;2|, RAS-to-CAS=%[76:1]|3;2|, RAS# prechg=%[76:0]|3;2| 25 | SDRAM mode select: %[76:7-5](MS)\tDRAM Idle Timer: %[78:3-0](DIT) 26 | DRAM data asserted: %[50:18]|one clock after;on same clock as| snoop 27 | Fixed DRAM Hole: %[68:7-6]|none ;512K-640K;15M-16M;reserved|\tModuleMode: %[57:5|76:4](MM) 28 | WSC# handshake: %[50:15]Ed\t\tECC signals always driven for EDO: %[50:17]y 29 | IDSEL redirection: %[50:16]|IDSEL1/AD12;IDSEL7/AD18|\tHost/DRAM frequency: %[50:13-12]|100 MHz;reserved;66 MHz;reserved| 30 | AGP-to-PCI access: %[50:11]ed \tPCI-agent access to aperture: %[50:10]Ed 31 | Graphics Aperture: %[50:9]ed \tDRAM integrity mode: %[50:8-7](integ) 32 | ECC diagnostics mode: %[50:6]ed \tMDA on PCI/ISA: %[50:5]|absent;present| 33 | Posting Host USWC: %[50:3]ed \tIn-Order Queue depth: %[50:2]|1;maximum| 34 | 35 | SMRAM Control: SMM Space %[72:6]/Open/ %[72:5]/Closed/ %[72:4]/Locked/ %[72:3]/Enabled/ at %[72:2-0<12+32768]4x 36 | Ext. SMRAM Control: Using %[73:7]|compatible;high| SMRAM; TSEG (%[73:0]ed) is %[73:2-1]|128K;256K;512K;1M| 37 | SMRAM cacheable: %[73:5]/globally/ %[73:4]/L1/ %[73:3]/L2/ 38 | have %[73:6]|not ;|detected non-SMM access to closed SMRAM 39 | Power Management: enable %[7A:7]/SDRAM powerdown,/ %[7A:6]/ACPI ctrl reg,/ %[7A:4]/normal refresh/ 40 | quick-start %[7A:3]ed, dynamic clock gating %[7A:2]ed 41 | AGP %[7A:1]Ed, CPU reset w/o PCIRST %[7A:0]ed 42 | suspend refresh type is %[7A:5]|self-refresh;CBR| 43 | Suspend CBR Refresh: automatic rate adjustment %[7B:12]ed, rate = %[7B:11-0]d 44 | 45 | Error Address: error address %[80:31-12<12]8x, %[80:1]/multi-bit//%[80:0]/single-bit/ error 46 | Error Command: enable SERR# on: %[90:7]/AGP outs. aperture/ %[90:6]/inv AGP DRAM access/ 47 | %[90:5]/invalid GATT/ %[90:4]/Target Abort/ %[90:3]/Thermal Throttle/ 48 | %[90:1]/multi-bit error/ %[90:0]/single-bit error/ 49 | SERR# mode: %[90:2]|single PCI clock;level mode| 50 | Error Status: detected %[91:12]/Read//%[91:11]/Write/ thermal throttle 51 | %[91:10]/AGP outside aperture/ %[91:9]/inv AGP DRAM access/ %[91:8]/invalid GATT/ 52 | %[91:4]/multi-bit error/ (row %[91:7-5]d), %[91:0]/single-bit error/ (row %[91:3-1]d) 53 | 54 | AGP Control: AGP %[A8:8]ed, sideband addr %[A8:9]ed, %[A8:1-0](AGPxfer) xfer rate 55 | forced ordering of snoop-writes/AGP reads is %[B0:15]Ed 56 | Graphics Aperture write/AGP read sync is %[B0:13]ed 57 | Graphics Translation Lookaside Buffer is %[B0:7]ed 58 | Aperture Size Mask (bits 27-22) = %[B4:5-0]6b 59 | Graphics Aperture Translation Table at %[B8:31-12<12]8x 60 | AGP Jam Latch: %[F0:8]/weak//%[F0:9]/strng/ pull-up, %[F0:6]/weak//%[F0:7]/strng/ pull-down 61 | 62 | DRAM Write Thermal Throttling Control: Read Write 63 | Global DRAM Write Sampling Window (ms): %[E8:13-6<2]d\t\t%[E4:13-6<2]d 64 | Global QWORD Threshold: %[E8:37-26*215]d\t\t%[E0:37-26*215]d 65 | Throttle Time (* sampling window length): %[E8:25-20]d\t\t%[E0:25-20]d 66 | Throttle Monitoring Window (DRAM CLKs): %[E8:19-13<4]d\t\t%[E0:19-13<4]d 67 | Throttle QWORD Maximum: %[E8:12-3]d\t\t%[E0:12-3]d 68 | DRAM Throttle Mode: %[E8:2-0](throt)\t\t%[E0:2-0](throt) 69 | lock: %[E4:31]Y 70 | 71 | Memory Buffers (Speed x Strength): 72 | MAA[13:0],WEA#,SRASA#,SCASA# %[CA:22](Spd)x%[69:39-38](Str1) 73 | MAB[12:11,9:0],MAB[13,10],WEB#,SRASB#,SCABS# %[CA:21](Spd)x%[69:37-36](Str1) 74 | MD[63:0] control 1 %[CA:19](Spd)x%[69:33-32](Str2) 75 | MD[63:0] control 2 %[CA:20](Spd)x%[69:35-34](Str2) 76 | MECC[7:0] control 1 %[CA:17](Spd)x%[69:29-28](Str2) 77 | MECC[7:0] control 2 %[CA:18](Spd)x%[69:31-30](Str2) 78 | CSB7#/CKE5 %[CA:16](Spd)x%[69:27-26](Str1) 79 | CSA7#/CKE3 %[CA:15](Spd)x%[69:25-24](Str1) 80 | CSB6#/CKE4 %[CA:14](Spd)x%[69:23-22](Str1) 81 | CSA6#/CKE2 %[CA:13](Spd)x%[69:21-20](Str1) 82 | CSA5#/RASA5#, CSB5#/RASB5# %[CA:12](Spd)x%[69:19](Str3) 83 | CSA4#/RASA4#, CSB4#/RASB4# %[CA:11](Spd)x%[69:18](Str3) 84 | CSA3#/RASA3#, CSB3#/RASB3# %[CA:10](Spd)x%[69:17](Str3) 85 | CSA2#/RASA2#, CSB2#/RASB2# %[CA:9](Spd)x%[69:16](Str3) 86 | CSA1#/RASA1#, CSB1#/RASB1# %[CA:8](Spd)x%[69:15](Str3) 87 | CSA0#/RASA0#, CSB0#/RASB0# %[CA:7](Spd)x%[69:14](Str3) 88 | DQMA5/CASA5# %[CA:6](Spd)x%[69:13-12](Str4) 89 | DQMA1/CASA1# %[CA:5](Spd)x%[69:11-10](Str1) 90 | DQMB5/CASB5# %[CA:4](Spd)x%[69:9-8](Str4) 91 | DQMB1/CASB1# %[CA:3](Spd)x%[69:7-6](Str4) 92 | DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# %[CA:2](Spd)x%[69:5-4](Str1) 93 | CKE1/GCKE %[CA:1](Spd)x%[69:3-2](Str1) 94 | CKE0/FENA %[CA:0](Spd)x%[69:1-0](Str1) 95 | !end 96 | 97 | !enum refresh 98 | disabled 99 | 15.6 us 100 | 31.2 us 101 | 62.4 us 102 | 124.8 us 103 | 249.6 us 104 | reserved 105 | !end 106 | 107 | !enum ECC 108 | \ ECC 109 | noECC 110 | !end 111 | 112 | !enum PS 113 | \ 2 KB 114 | \ 4 KB 115 | \ 8 KB 116 | \ rsvd 117 | !end 118 | 119 | !enum BpR 120 | \ two \ 121 | \ four 122 | !end 123 | 124 | !enum integ 125 | non-ECC 126 | parity 127 | ECC 128 | ECC w/ hw scrubbing 129 | !end 130 | 131 | !enum MS 132 | normal operation 133 | issue NOP commands 134 | All-Banks-Precharge 135 | mode register set 136 | CBR cycles 137 | reserved 138 | !end 139 | 140 | !enum MM 141 | 3 DIMMs, powerdown enabled 142 | 4 DIMMs, no power-down 143 | 3 DIMMs, no power-down 144 | 3 DIMMs, no power-down 145 | !end 146 | 147 | !enum DIT 148 | 0 clocks 149 | 2 clocks 150 | 4 clocks 151 | 8 clocks 152 | 10 clocks 153 | 12 clocks 154 | 16 clocks 155 | 32 clocks 156 | infinite 157 | !end 158 | 159 | !enum throt 160 | rsvd 161 | rsvd 162 | rsvd 163 | rsvd 164 | normal 165 | rsvd 166 | !end 167 | 168 | !enum Spd 169 | \ 66 MHz \ 170 | 100 MHz \ 171 | !end 172 | 173 | !enum Str1 174 | 1 (66/100) 175 | rsvd 176 | 2 (66/100) 177 | 3 (66/100) 178 | !end 179 | 180 | !enum Str2 181 | 1 (66/100) 182 | rsvd 183 | 2 (66/100) 184 | 3 (100 only) 185 | !end 186 | 187 | !enum Str3 188 | 1 (66/100) 189 | 2 (66/100) 190 | !end 191 | 192 | !enum Str4 193 | 1 (66/100) 194 | rsvd 195 | 2 (66/100) 196 | 3 (66 only) 197 | !end 198 | 199 | !enum AGPxfer 200 | default 201 | 1x 202 | 2x 203 | illegal 204 | !end 205 | -------------------------------------------------------------------------------- /rbpci119/BLANK.PCI: -------------------------------------------------------------------------------- 1 | %! Detailed register description file for PCICFG.EXE by Ralf Brown 2 | %! 3 | %! Filename VVVVDDDD.PCI = Vendor VVVVh, Device DDDDh 4 | %! Last Edit 27jun98 by Ralf Brown 5 | %! 6 | 7 | Everything preceding a line beginning with the six characters "!begin" is 8 | a comment and will be ignored (with the proviso that the total file size 9 | not exceed 64K). Everything from the !begin line to a line starting with 10 | the four characters "!end" forms part of the device description, in a 11 | format similar to that used for printf(). 12 | 13 | To create your own device description file for PCICFG, copy this file to 14 | a file in the same directory containing PCICFG.EXE called VVVVDDDD.PCI, 15 | where VVVV are the four hexadecimal digits of the PCI vendor ID reported 16 | by PCICFG, and DDDD are the four hexadecimal digits of the PCI device 17 | ID. Then, place the appropriate formatting directives between the 18 | "!begin" and "!end" lines below. 19 | 20 | 21 | format spec: 22 | everything is literal except backslashes and conversion ops 23 | introduced by a percent sign; the percent-sign is followed by 24 | PCI field specifier, an optional print width, and the conversion 25 | character 26 | 27 | conversion characters: 28 | ignore the newline and paste together the two lines 29 | % literal percent sign 30 | ! rest of line is a comment and is skipped 31 | b print number in binary 32 | o print number in octal 33 | d print number in decimal 34 | x print number in hexadecimal 35 | e print boolean value as "disable" (false) or "enable" (true) 36 | E print boolean value as "enable" (false) or "disable" (true) 37 | f print boolean value as dash (false) or check mark (true) 38 | n print boolean value as Y (false) or N (true), i.e. inverted 39 | N print boolean as Yes (false) or No (true), i.e. inverted 40 | y print boolean value as N (false) or Y (true) 41 | Y print boolean value as No (false) or Yes (true) 42 | (name) print enumerated value given by enum spec "name" 43 | {xyz} print Nth character in "xyz" (prints last if N > # chars) 44 | /lit/ print literal string if boolean is true, dashes otherwise 45 | |a1;a2;a3;a4| select among 2-4 alternate values (index 0-3), prints 46 | last alternative given if N > # alternatives 47 | 48 | backslash conversions supported: 49 | \t tab character 50 | \\ literal backslash 51 | \X (any X not listed above:) literal X 52 | 53 | PCI field specifier: 54 | '[' hex-address ']' entire byte at offset 'hex-address' 55 | '[' addr ':' bitnum ']' bit 'bitnum' of byte at offset 'addr' 56 | '[' addr ':' bit1 '-' bit2 ']' 57 | bits 'bit1' to 'bit2' of byte at 'addr' 58 | '[' bitfield-spec '|' bitfield-spec ... ']' 59 | concatenate multiple bitfields (MS first) 60 | any of the above may also add the following modifiers just prior to 61 | the closing bracket or a separating vertical bar: 62 | '<' shift shift the field left 'shift' bits 63 | '*' mult multiply the field's value by 'mult' 64 | '+' offset add 'offset' to the field value 65 | '<' shift '+' offset 66 | shift left and then add 67 | '*' mult '+' offset multiply and then add 68 | bit numbers up to 31 are fully supported, and address the appropriate 69 | byte beginning at the specified address; all fields are treated as 70 | 32-bit values internally. Bit numbers above 31 are supported 71 | provided that the indicated field does not occupy more than four 72 | bytes (i.e. if the low bit is not a multiple of 8, the maximum field 73 | size is less than 32 bits). 74 | Note: addresses are in hex, all other values are decimal (unsigned except 75 | for 'offset', which may include a leading minus sign after the plus 76 | sign introducing it) 77 | 78 | When printing, an explicit width greater than the item's actual width 79 | causes the addition of padding on the left to ensure the desired 80 | width; the padding uses blanks for all formats except binary (b), 81 | octal (o), and hexadecimal (x) numbers, which use zeros. 82 | 83 | 84 | !begin 85 | 86 | %! insert device description here 87 | 88 | !end 89 | 90 | ; everything between the above !end line and a following !enum line is also 91 | ; a comment 92 | 93 | !enum enum-name 94 | Value0 95 | Value1 96 | Value2 97 | ... 98 | ValueN (also used for any values > N) 99 | !end 100 | 101 | ; enums are matched by name; first, an exact match is attempted, then the 102 | ; first named enum starting with the string in the (enum) is selected 103 | ; name matches are case-sensitive! 104 | ; 105 | ; leading and trailing whitespace is ignored, allowing you to indent the 106 | ; value strings without forcing the space to appear in the output; if you 107 | ; really do need to retain leading or trailing whitespace, add a backslash 108 | ; to the beginning or end of the line 109 | 110 | 111 | %! end of file 112 | -------------------------------------------------------------------------------- /rbpci119/FILE_ID.DIZ: -------------------------------------------------------------------------------- 1 | RB-PCI v1.19 2 | This archive contains Ralf Brown's 3 | PCICFG, a program to tell you more 4 | than you ever cared to know about 5 | the PCI-bus devices in your 6 | computer. 7 | -------------------------------------------------------------------------------- /rbpci119/PCICFG.CPP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/rbpci119/PCICFG.CPP -------------------------------------------------------------------------------- /rbpci119/PCICFG.DAT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/rbpci119/PCICFG.DAT -------------------------------------------------------------------------------- /rbpci119/PCICFG.EXE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/rbpci119/PCICFG.EXE -------------------------------------------------------------------------------- /rbpci119/PCICFG.TXT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/rbpci119/PCICFG.TXT -------------------------------------------------------------------------------- /rbpci119/PGP-SIGS.ZIP: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/rbpci119/PGP-SIGS.ZIP -------------------------------------------------------------------------------- /rbpci119/RBROWN.TXT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cirosantilli/ralf-brown-interrupt-list/fde1a5ac1b7e8a45ff4255ee275ee77c7fe7e256/rbpci119/RBROWN.TXT --------------------------------------------------------------------------------