├── LICENSE ├── README.md ├── at89.conf ├── blink ├── Makefile ├── config_n76e003.json ├── config_n76e616.json ├── config_n76e885.json └── main.c ├── difference-between-c51-and-sdcc.md ├── headers ├── ch552.h ├── ch554.h ├── ch559.h ├── ds89c4xx.h ├── fx2regs.h ├── n76e003.h ├── n76e616.h ├── n76e885.h ├── softdelay.h ├── stc10fxx.h ├── stc12c20xx.h ├── stc12c54xx.h ├── stc12c56xx.h ├── stc12h.h ├── stc15f104e.h ├── stc15fxx.h ├── stc16fxx.h ├── stc51.h ├── stc89xx.h ├── stc8a8k64d4.h ├── stc8cxx.h ├── stc8fxx.h ├── stc8gxx.h ├── stc8hxx.h └── stc90c5xad.h ├── naken_asm-headers ├── README.headers ├── c8051f000.inc ├── c8051f018.inc ├── c8051f020.inc ├── c8051f040.inc ├── c8051f060.inc ├── c8051f120.inc ├── c8051f200.inc ├── c8051f300.inc ├── c8051f310.inc ├── c8051f320.inc ├── c8051f326.inc ├── c8051f330.inc ├── c8051f336.inc ├── c8051f340.inc ├── c8051f350.inc ├── c8051f360.inc ├── c8051f410.inc ├── c8051f520.inc ├── c8051f920.inc ├── c8051t600.inc ├── c8051t610.inc ├── c8051t630.inc ├── ch552.inc ├── ch554.inc ├── ds89c4xx.inc ├── n76e003.inc ├── n76e616.inc ├── n76e885.inc ├── stc10fxx.inc ├── stc12c20xx.inc ├── stc12c54xx.inc ├── stc12h.inc ├── stc15f104e.inc ├── stc15fxx.inc ├── stc16fxx.inc ├── stc32g.inc ├── stc89xx.inc ├── stc8a8k64d4.inc ├── stc8cxx.inc ├── stc8fxx.inc ├── stc8gxx.inc ├── stc8hxx.inc └── stc90c5xad.inc └── stc-nameing-schema.md /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 cjacker 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /at89.conf: -------------------------------------------------------------------------------- 1 | 2 | #------------------------------------------------------------ 3 | # AT89S51 4 | #------------------------------------------------------------ 5 | part 6 | id = "8051"; 7 | desc = "AT89S51"; 8 | signature = 0x1E 0x51 0x06; 9 | chip_erase_delay = 500000; 10 | pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", 11 | "x x x x x x x x x x x x x x x x"; 12 | 13 | chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", 14 | "x x x x x x x x x x x x x x x x"; 15 | 16 | timeout = 200; 17 | stabdelay = 100; 18 | cmdexedelay = 25; 19 | synchloops = 32; 20 | bytedelay = 0; 21 | pollindex = 3; 22 | pollvalue = 0x53; 23 | predelay = 1; 24 | postdelay = 1; 25 | pollmethod = 0; 26 | 27 | memory "flash" 28 | size = 4096; 29 | paged = no; 30 | min_write_delay = 4000; 31 | max_write_delay = 9000; 32 | readback_p1 = 0xff; 33 | readback_p2 = 0xff; 34 | read = " 0 0 1 0 0 0 0 0", 35 | " x x x a12 a11 a10 a9 a8", 36 | " a7 a6 a5 a4 a3 a2 a1 a0", 37 | " o o o o o o o o"; 38 | 39 | write = " 0 1 0 0 0 0 0 0", 40 | " x x x a12 a11 a10 a9 a8", 41 | " a7 a6 a5 a4 a3 a2 a1 a0", 42 | " i i i i i i i i"; 43 | mode = 0x21; 44 | delay = 12; 45 | ; 46 | 47 | memory "signature" 48 | size = 3; 49 | read = "0 0 1 0 1 0 0 0 x x x 0 0 0 a1 a0", 50 | "0 0 0 0 0 0 0 0 o o o o o o o o"; 51 | ; 52 | ; 53 | #------------------------------------------------------------ 54 | # AT89S52 55 | #------------------------------------------------------------ 56 | part 57 | id = "8052"; 58 | desc = "AT89S52"; 59 | signature = 0x1E 0x52 0x06; 60 | chip_erase_delay = 500000; 61 | pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", 62 | "x x x x x x x x x x x x x x x x"; 63 | 64 | chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", 65 | "x x x x x x x x x x x x x x x x"; 66 | 67 | timeout = 200; 68 | stabdelay = 100; 69 | cmdexedelay = 25; 70 | synchloops = 32; 71 | bytedelay = 0; 72 | pollindex = 3; 73 | pollvalue = 0x53; 74 | predelay = 1; 75 | postdelay = 1; 76 | pollmethod = 0; 77 | 78 | memory "flash" 79 | size = 8192; 80 | paged = no; 81 | min_write_delay = 4000; 82 | max_write_delay = 9000; 83 | readback_p1 = 0xff; 84 | readback_p2 = 0xff; 85 | read = " 0 0 1 0 0 0 0 0", 86 | " x x x a12 a11 a10 a9 a8", 87 | " a7 a6 a5 a4 a3 a2 a1 a0", 88 | " o o o o o o o o"; 89 | 90 | write = " 0 1 0 0 0 0 0 0", 91 | " x x x a12 a11 a10 a9 a8", 92 | " a7 a6 a5 a4 a3 a2 a1 a0", 93 | " i i i i i i i i"; 94 | mode = 0x21; 95 | delay = 12; 96 | ; 97 | 98 | memory "signature" 99 | size = 3; 100 | read = "0 0 1 0 1 0 0 0 x x x 0 0 0 a1 a0", 101 | "0 0 0 0 0 0 0 0 o o o o o o o o"; 102 | ; 103 | ; 104 | #------------------------------------------------------------ 105 | # AT89S8253 106 | #------------------------------------------------------------ 107 | part 108 | id = "8253"; 109 | desc = "AT89S8253"; 110 | chip_erase_delay = 20000; 111 | pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", 112 | "x x x x x x x x x x x x x x x x"; 113 | 114 | chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", 115 | "x x x x x x x x x x x x x x x x"; 116 | 117 | timeout = 200; 118 | stabdelay = 100; 119 | cmdexedelay = 25; 120 | synchloops = 32; 121 | bytedelay = 0; 122 | pollindex = 3; 123 | pollvalue = 0x53; 124 | predelay = 1; 125 | postdelay = 1; 126 | pollmethod = 0; 127 | 128 | memory "flash" 129 | size = 12288; 130 | paged = no; 131 | min_write_delay = 4000; 132 | max_write_delay = 9000; 133 | readback_p1 = 0xff; 134 | readback_p2 = 0xff; 135 | read = " 0 0 1 0 0 0 0 0", 136 | " x x a13 a12 a11 a10 a9 a8", 137 | " a7 a6 a5 a4 a3 a2 a1 a0", 138 | " o o o o o o o o"; 139 | 140 | write = " 0 1 0 0 0 0 0 0", 141 | " x x a13 a12 a11 a10 a9 a8", 142 | " a7 a6 a5 a4 a3 a2 a1 a0", 143 | " i i i i i i i i"; 144 | mode = 0x21; 145 | delay = 12; 146 | ; 147 | 148 | memory "signature" 149 | size = 2; 150 | readback_p1 = 0x1E; 151 | readback_p2 = 0x73; 152 | read = "0 0 1 0 1 0 0 0 x x x x x x x x", 153 | "x x 1 1 0 0 0 a0 o o o o o o o o"; 154 | ; 155 | ; 156 | -------------------------------------------------------------------------------- /blink/Makefile: -------------------------------------------------------------------------------- 1 | # compiler and utilities to build and flash 2 | sdcc := sdcc 3 | packihx := packihx 4 | makebin := makebin 5 | # for STC MCU below STC8x 6 | stcgal := stcgal 7 | # for STC MCU 8x and above 8 | stcflash := stcflash 9 | # for WCH CH55x 10 | ch55x-isptool := ch55x-isptool 11 | # for Nuvoton N76Exxx 12 | nuvoprog := nuvoprog 13 | # for Cypress CY7C63013/A 14 | cycfx2prog := cycfx2prog 15 | # for Silicon Labs C8051 and EFM8 16 | # opensource ec2-new 17 | ec2writeflash := ec2writeflash 18 | # c8051/efm8 with usb debug adapter 19 | flash8051 := flash8051 20 | # efm8 with jlink 21 | flashefm8 := flashefm8 22 | # efm8 with uart bootloader 23 | efm8load := efm8load 24 | 25 | # sdcc flags 26 | # notes ： Please adjust '--iram-size'/'--xram-size'/'--code-size' according to your chip ） 27 | # for stc89/90 28 | sdcc_flags := -mmcs51 29 | # for stc15 sop8 30 | # sdcc_flags := -mmcs51 --iram-size 128 --xram-size 0 --code-size 4096 --nooverlay --noinduction --model-small 31 | # for stc8h 32 | # sdcc_flags := -mmcs51 --iram-size 256 --xram-size 8192 --code-size 65536 --stack-auto 33 | 34 | debug_flags := --debug 35 | 36 | # source files 37 | SRCS = main.c 38 | 39 | # include path, since include dir at parent dir. 40 | mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) 41 | current_dir := $(dir $(mkfile_path)) 42 | 43 | INCS = -I$(current_dir)/../headers 44 | 45 | # Specify the output hex File path and file name 46 | outname = firmware 47 | 48 | #default target 49 | all: $(outname).bin $(outname).hex 50 | 51 | # all .c->.rel, Deposit in OBJECT 52 | OBJECTS = $(notdir $(SRCS:.c=.rel)) 53 | vpath %.c $(sort $(dir $(SRCS))) 54 | 55 | %.rel: %.c Makefile 56 | $(sdcc) $(sdcc_flags) $(debug_flags) -c $(INCS) $< -o $@ 57 | 58 | $(outname).ihx: $(OBJECTS) 59 | $(sdcc) $(sdcc_flags) $(debug_flags) $^ -o $(outname).ihx 60 | 61 | %.hex: %.ihx 62 | $(packihx) $< > $(outname).hex 63 | 64 | %.bin: %.hex 65 | $(makebin) -p $(outname).hex $(outname).bin 66 | 67 | flash_stc: $(outname).bin 68 | sudo $(stcgal) $(outname).bin 69 | 70 | flash_stc8x: $(outname).bin 71 | sudo $(stcflash) $(outname).bin 72 | 73 | flash_ch55x: $(outname).bin 74 | sudo $(ch55x-isptool) $(outname).bin 75 | 76 | flash_c8051f_with_ec2new: $(outname).hex 77 | sudo $(ec2writeflash) --port USB --hex $(outname).hex --run 78 | 79 | flash_c8051f_with_flash8051: $(outname).hex 80 | # modify the sn and tif according to your adapter and target board. 81 | sudo $(flash8051) -sn EC60000B878 -tif c2 -erasemode full -upload $(outname).hex 82 | 83 | flash_efm8_with_flashefm8: $(outname).hex 84 | # modify the sn, part and tif according to your adapter and target board. 85 | sudo $(flashefm8) -sn 000440033272 -tif c2 -part efm8sb10f8g -erasemode full -upload $(outname).hex 86 | 87 | flash_efm8_with_uart_bootloader: $(outname).hex 88 | hex2boot $(outname).hex -o $(outname).efm8 89 | efm8load -p /dev/ttyUSB0 -b 115200 -t $(outname).efm8 90 | 91 | flash_n76e003: $(outname).ihx 92 | sudo $(nuvoprog) program -t n76e003 -i $(outname).ihx -c @config_n76e003.json 93 | 94 | flash_n76e616: $(outname).ihx 95 | sudo $(nuvoprog) program -t n76e616 -i $(outname).ihx -c @config_n76e616.json 96 | 97 | flash_n76e885: $(outname).ihx 98 | sudo $(nuvoprog) program -t n76e885 -i $(outname).ihx -c @config_n76e885.json 99 | 100 | flash_fx2: $(outname).ihx 101 | sudo $(cycfx2prog) prg:$(outname).ihx run 102 | 103 | 104 | # clean project 105 | .PHONY : clean 106 | clean : 107 | rm -f $(SRCS:.c=.rel) $(SRCS:.c=.lst) $(SRCS:.c=.rst) $(SRCS:.c=.sym) $(SRCS:.c=.asm) $(SRCS:.c=.adb) 108 | rm -f $(outname).* 109 | -------------------------------------------------------------------------------- /blink/config_n76e003.json: -------------------------------------------------------------------------------- 1 | { 2 | "boot_select": "aprom", 3 | "pwm_enabled_during_ocd": false, 4 | "ocd_enabled": true, 5 | "reset_pin_disabled": false, 6 | "locked": false, 7 | "ldrom_size": "0kb", 8 | "bod_disabled": false, 9 | "bod_voltage": "2v2", 10 | "iap_enabled_in_brownout": false, 11 | "bod_reset_disabled": false, 12 | "wdt": "disabled" 13 | } 14 | -------------------------------------------------------------------------------- /blink/config_n76e616.json: -------------------------------------------------------------------------------- 1 | { 2 | "boot_select": "aprom", 3 | "ocd_enabled": true, 4 | "reset_pin_disabled": false, 5 | "locked": false, 6 | "ldrom_size": "0kb", 7 | "bod_disabled": false, 8 | "bod_voltage": "2v2", 9 | "iap_enabled_in_brownout": false, 10 | "bod_reset_disabled": false, 11 | "wdt": "disabled" 12 | } 13 | -------------------------------------------------------------------------------- /blink/config_n76e885.json: -------------------------------------------------------------------------------- 1 | { 2 | "boot_select": "aprom", 3 | "ocd_enabled": true, 4 | "reset_pin_disabled": false, 5 | "locked": false, 6 | "ldrom_size": "0kb", 7 | "bod_disabled": false, 8 | "bod_voltage": "1v7", 9 | "iap_enabled_in_brownout": false, 10 | "bod_reset_disabled": false, 11 | "wdt": "disabled" 12 | } 13 | -------------------------------------------------------------------------------- /blink/main.c: -------------------------------------------------------------------------------- 1 | // blink led, Pin->Resistor->LED->GND 2 | 3 | #define STC89 4 | 5 | #if defined(STC89) 6 | #include 7 | #define LED P34 8 | 9 | #elif defined(STC8H) 10 | #include 11 | #define LED P34 12 | 13 | #elif defined(C8051F120) 14 | #include 15 | #define LED P3_3 16 | 17 | #elif defined(C8051F300) 18 | #include 19 | #define LED P0_0 //on-board LED 20 | 21 | #elif defined(C8051F320) 22 | #include 23 | #define LED P2_0 //CJMCU F320 on-board LED 24 | 25 | #elif defined(C8051F330) 26 | #include 27 | #define LED P1_0 //on-board LED 28 | 29 | #elif defined(C8051F990) 30 | __sfr __at(0xA5) P1MDOUT; 31 | __sfr __at(0xD9) PCA0MD; 32 | __sfr __at(0xE3) XBR2; 33 | __sbit __at(0x90+0) P10; 34 | #define LED P10 35 | #elif defined(EFM8BB1) || defined(EFM8BB2) || defined(C8051F850) 36 | __sfr __at(0x97) WDTCN; 37 | __sfr __at(0xA5) P1MDOUT; 38 | __sfr __at(0xD5) P1SKIP; 39 | __sfr __at(0xE3) XBR2; 40 | __sbit __at(0x90+0) P10; 41 | __sbit __at(0x90+1) P11; 42 | __sbit __at(0x90+3) P13; 43 | __sbit __at(0x90+4) P14; 44 | #if defined(EFM8BB1) 45 | #define LED P14 46 | #elif defined(EFM8BB2) // my EFM8BB21F16G breakout board has LED to P13 47 | #define LED P13 48 | #elif defined(C8051F850) 49 | #define LED P10 // official toolstick dev platform 50 | #endif 51 | 52 | #elif defined(N76E003) 53 | #include 54 | #define LED P12 55 | 56 | #elif defined(N76E616) 57 | // my 616 dev board have 2 leds on board. 58 | #include 59 | #define LED P21 60 | #define LED1 P22 61 | 62 | #elif defined(N76E885) 63 | // NuTiny board have 2 les. 64 | #include 65 | #define LED P03 66 | #define LED1 P04 67 | 68 | #elif defined(CH552) 69 | #include 70 | #define LED P32 71 | 72 | #elif defined(FX2) 73 | #include 74 | #define LED PA0 75 | #endif 76 | 77 | // not accurate since different MCU/different Clock 78 | // just delay for some time. 79 | void delay(unsigned int z) 80 | { 81 | unsigned int x, y; 82 | for(x = 0; x < z; x++) 83 | for(y = 0; y < 255; y++); 84 | } 85 | 86 | void main() 87 | { 88 | #if defined(STC8H) 89 | // set P34 to Push_Pull 90 | P3M0 = 0x10; 91 | P3M1 = 0x00; 92 | 93 | #elif defined(C8051F120) 94 | // disable watchdog 95 | EA = 0; 96 | WDTCN = 0xde; 97 | WDTCN = 0xad; 98 | EA = 1; 99 | 100 | // set to 0xf for XBR2 and P3MDOUT 101 | SFRPAGE = CONFIG_PAGE; 102 | 103 | // enable Crossbar 104 | XBR2 = 0x40; 105 | P3MDOUT = 0xff; 106 | 107 | #elif defined(C8051F300) 108 | // disable watchdog 109 | PCA0MD = 0x00; 110 | // eanble Crossbar 111 | XBR2 = 0x40; 112 | // set P0 to Push-Pull 113 | P0MDOUT = 0xff; 114 | 115 | #elif defined(C8051F320) 116 | // disable watchdog 117 | PCA0MD = 0x00; 118 | // eanble Crossbar 119 | XBR1 = 0x40; 120 | // set P2 to Push-Pull 121 | P2MDOUT = 0xff; 122 | 123 | #elif defined(C8051F330) 124 | // disable watchdog 125 | PCA0MD = 0x00; 126 | // eanble Crossbar 127 | XBR1 = 0x40; 128 | // set P1 to Push-Pull 129 | P1MDOUT = 0xff; 130 | 131 | #elif defined(C8051F990) 132 | PCA0MD = 0x00; 133 | XBR2 = 0x40; 134 | P1MDOUT = 0xff; 135 | 136 | #elif defined(EFM8BB1) || defined(EFM8BB2) || defined(C8051F850) 137 | // disable watchdog 138 | WDTCN = 0xDE; //First key 139 | WDTCN = 0xAD; //Second key 140 | // enable crossbar 141 | XBR2 = 0x40; 142 | // p1 to push-pull 143 | P1MDOUT = 0xff; 144 | // P1 pin is skipped by the crossbar 145 | P1SKIP = 0xff; 146 | #elif defined(N76E003) 147 | P1M1 = 0x00; 148 | P1M2 = 0x00; 149 | #elif defined(N76E616) 150 | P2M1 = 0x00; 151 | P2M2 = 0x00; 152 | #elif defined(N76E885) 153 | P0M1 = 0x00; 154 | P0M2 = 0x00; 155 | #elif defined(FX2) 156 | OEA = 0x01; 157 | #endif 158 | 159 | while(1) { 160 | LED = !LED; 161 | #if defined(N76E616) || defined(N76E885) 162 | LED1 = !LED1; 163 | #endif 164 | delay(1000); 165 | } 166 | } 167 | -------------------------------------------------------------------------------- /difference-between-c51-and-sdcc.md: -------------------------------------------------------------------------------- 1 | # The difference between Keil C51 and SDCC 2 | 3 | ## Register definitions and name conventions 4 | * Keil C51 use `sbit` to declare special registers and use form like `P2^1` to indicate the P2.1 IO pin register.(actually it's a XOR operator), 5 | for example: `sfr P2 = 0xA0; sbit P2_1 = P2 ^ 1;` 6 | * SDCC use `__sbit` to declare special registers and '8051.h' shipped with SDCC prefer `P2_1` form. 7 | for example: `__sfr __at (0xA0) P2; __sbit __at (0xA0+1) P21;` 8 | * Official STC headers prefer 'P21' form. all headers provided with this repo follow this style name convention. 9 | 10 | And all registers already defined in headers, you should not need to care about this difference. 11 | 12 | ## Large constants storage 13 | * Put lange constants such as a big array in Keil C51 is done with `code` keyworld after type declaration, for example: `unsigned char code table[] = {...}`. 14 | * With SDCC, you should use `__code unsigned char table[] = {...}` 15 | 16 | ## Interrupt service routine declaration 17 | * Keil use, for example: `void isr() interrupt 1` to declare a ISR. 18 | * With SDCC, you should use `void isr() __interrupt(1)`, and it **MUST** have a prototype declaration 19 | within the source file of `main` function if the ISR implemented in a sperate C source file. 20 | 21 | ## data types 22 | * Keil has 1 bit data type `bit` 23 | * SDCC has 1 bit data type `__bit` and `__Bool`. 24 | 25 | You can use `typedef` to re-define it. 26 | 27 | ## pre-defined functions and libraries 28 | * Keil has some pre-defined functions, such as: `_nop_()`, `cror()`, etc. you should include 'intrins.h' header. 29 | * With SDCC, there are also some pre-defined functions, such as: `NOP()`, but you should include 'compiler.h' header. 30 | 31 | ## C function headers. 32 | * Keil C51 support old-style function parameter declaration as `void a(int a, b, c)`, the following type declaration can be omitted. 33 | * SDCC does **NOT** support this form. 34 | -------------------------------------------------------------------------------- /headers/ds89c4xx.h: -------------------------------------------------------------------------------- 1 | /*-------------------------------------------------------------------------- 2 | Registers definition for Dallas Semiconductors DS89C420/430/440/450 3 | -------------------------------------------------------------------------- */ 4 | 5 | /* Byte Addresses */ 6 | __sfr __at (0x80) P0; 7 | __sfr __at (0x81) SP; 8 | __sfr __at (0x82) DPL; 9 | __sfr __at (0x83) DPH; 10 | __sfr __at (0x84) DPL1; 11 | __sfr __at (0x85) DPH1; 12 | __sfr __at (0x86) DPS; 13 | __sfr __at (0x87) PCON; 14 | __sfr __at (0x88) TCON; 15 | __sfr __at (0x89) TMOD; 16 | __sfr __at (0x8A) TL0; 17 | __sfr __at (0x8B) TL1; 18 | __sfr __at (0x8C) TH0; 19 | __sfr __at (0x8D) TH1; 20 | __sfr __at (0x8E) CKCON; 21 | __sfr __at (0x90) P1; 22 | __sfr __at (0x91) EXIF; 23 | __sfr __at (0x96) CKMOD; 24 | __sfr __at (0x98) SCON0; 25 | __sfr __at (0x99) SBUF0; 26 | __sfr __at (0x9D) ACON; 27 | __sfr __at (0xA0) P2; 28 | __sfr __at (0xA8) IE; 29 | __sfr __at (0xA9) SADDR0; 30 | __sfr __at (0xAA) SADDR1; 31 | __sfr __at (0xB0) P3; 32 | __sfr __at (0xB1) IP1; 33 | __sfr __at (0xB8) IP0; 34 | __sfr __at (0xB9) SADEN0; 35 | __sfr __at (0xBA) SADEN1; 36 | __sfr __at (0xC0) SCON1; 37 | __sfr __at (0xC1) SBUF1; 38 | __sfr __at (0xC2) ROMSIZE; 39 | __sfr __at (0xC4) PMR; 40 | __sfr __at (0xC5) STATUS; 41 | __sfr __at (0xC7) TA; 42 | __sfr __at (0xC8) T2CON; 43 | __sfr __at (0xC9) T2MOD; 44 | __sfr __at (0xCA) RCAP2L; 45 | __sfr __at (0xCB) RCAP2H; 46 | __sfr __at (0xCC) TL2; 47 | __sfr __at (0xCD) TH2; 48 | __sfr __at (0xD0) PSW; 49 | __sfr __at (0xD5) FCNTL; 50 | __sfr __at (0xD6) FDATA; 51 | __sfr __at (0xD8) WDCON; 52 | __sfr __at (0xE0) ACC; 53 | __sfr __at (0xE8) EIE; 54 | __sfr __at (0xF0) B; 55 | __sfr __at (0xF1) EIP1; 56 | __sfr __at (0xF8) EIP0; 57 | 58 | /* Bit Addresses */ 59 | 60 | /* TCON */ 61 | __sbit __at (0x88+0) IT0; 62 | __sbit __at (0x88+1) IE0; 63 | __sbit __at (0x88+2) IT1; 64 | __sbit __at (0x88+3) IE1; 65 | __sbit __at (0x88+4) TR0; 66 | __sbit __at (0x88+5) TF0; 67 | __sbit __at (0x88+6) TR1; 68 | __sbit __at (0x88+7) TF1; 69 | 70 | /* SCON0 */ 71 | __sbit __at (0x98+0) RI_0; 72 | __sbit __at (0x98+1) TI_0; 73 | __sbit __at (0x98+2) RB8_0; 74 | __sbit __at (0x98+3) TB8_0; 75 | __sbit __at (0x98+4) REN_0; 76 | __sbit __at (0x98+5) SM2_0; 77 | __sbit __at (0x98+6) SM1_0; 78 | __sbit __at (0x98+7) FE_0; 79 | 80 | /* IE */ 81 | __sbit __at (0xA8+0) EX0; 82 | __sbit __at (0xA8+1) ET0; 83 | __sbit __at (0xA8+2) EX1; 84 | __sbit __at (0xA8+3) ET1; 85 | __sbit __at (0xA8+4) ES0; 86 | __sbit __at (0xA8+5) ET2; 87 | __sbit __at (0xA8+6) ES1; 88 | __sbit __at (0xA8+7) EA; 89 | 90 | /* IP0 */ 91 | __sbit __at (0xB8+0) PX0; 92 | __sbit __at (0xB8+1) PT0; 93 | __sbit __at (0xB8+2) PX1; 94 | __sbit __at (0xB8+3) PT1; 95 | __sbit __at (0xB8+4) PS; 96 | 97 | /* SCON1 */ 98 | __sbit __at (0xC0+0) RI_1; 99 | __sbit __at (0xC0+1) TI_1; 100 | __sbit __at (0xC0+2) RB8_1; 101 | __sbit __at (0xC0+3) TB8_1; 102 | __sbit __at (0xC0+4) REN_1; 103 | __sbit __at (0xC0+5) SM2_1; 104 | __sbit __at (0xC0+6) SM1_1; 105 | __sbit __at (0xC0+7) FE_1; 106 | 107 | /* T2CON */ 108 | __sbit __at (0xC8+0) CP; 109 | 110 | __sbit __at (0xC8+2) TR2; 111 | __sbit __at (0xC8+3) EXEN2; 112 | __sbit __at (0xC8+4) TCLK; 113 | __sbit __at (0xC8+5) RCLK; 114 | __sbit __at (0xC8+6) EXF2; 115 | __sbit __at (0xC8+7) TF2; 116 | 117 | /* PSW */ 118 | __sbit __at (0xD0+0) P; 119 | __sbit __at (0xD0+1) F1; 120 | __sbit __at (0xD0+2) OV; 121 | __sbit __at (0xD0+3) RS0; 122 | __sbit __at (0xD0+4) RS1; 123 | __sbit __at (0xD0+5) F0; 124 | __sbit __at (0xD0+6) AC; 125 | __sbit __at (0xD0+7) CY; 126 | 127 | /* WDCON */ 128 | __sbit __at (0xD8+0) RWT; 129 | __sbit __at (0xD8+1) EWT; 130 | __sbit __at (0xD8+2) WTRF; 131 | __sbit __at (0xD8+3) WDIF; 132 | __sbit __at (0xD8+4) PFI; 133 | __sbit __at (0xD8+5) EPFI; 134 | __sbit __at (0xD8+6) POR; 135 | __sbit __at (0xD8+7) SMOD_1; 136 | 137 | /* EIE */ 138 | __sbit __at (0xE8+0) EX2; 139 | __sbit __at (0xE8+1) EX3; 140 | __sbit __at (0xE8+2) EX4; 141 | __sbit __at (0xE8+3) EX5; 142 | __sbit __at (0xE8+4) EWDI; 143 | 144 | /* EIP0 */ 145 | __sbit __at (0xF8+0) LPX2; 146 | __sbit __at (0xF8+1) LPX3; 147 | __sbit __at (0xF8+2) LPX4; 148 | __sbit __at (0xF8+3) LPX5; 149 | __sbit __at (0xF8+4) LPXWDI; 150 | -------------------------------------------------------------------------------- /headers/n76e003.h: -------------------------------------------------------------------------------- 1 | /*-------------------------------------------------------------------------- 2 | N76E003.H 3 | 4 | Header file for Nuvoton N76E003 5 | --------------------------------------------------------------------------*/ 6 | 7 | __sfr __at (0x80) P0; 8 | __sfr __at (0x81) SP; 9 | __sfr __at (0x82) DPL; 10 | __sfr __at (0x83) DPH; 11 | __sfr __at (0x86) RWK; 12 | __sfr __at (0x87) PCON; 13 | 14 | __sfr __at (0x88) TCON; 15 | __sfr __at (0x89) TMOD; 16 | __sfr __at (0x8A) TL0; 17 | __sfr __at (0x8B) TL1; 18 | __sfr __at (0x8C) TH0; 19 | __sfr __at (0x8D) TH1; 20 | __sfr __at (0x8E) CKCON; 21 | __sfr __at (0x8F) WKCON; 22 | 23 | __sfr __at (0x90) P1; 24 | __sfr __at (0x91) SFRS;//TA Protection 25 | __sfr __at (0x92) CAPCON0; 26 | __sfr __at (0x93) CAPCON1; 27 | __sfr __at (0x94) CAPCON2; 28 | __sfr __at (0x95) CKDIV; 29 | __sfr __at (0x96) CKSWT;//TA Protection 30 | __sfr __at (0x97) CKEN;//TA Protection 31 | 32 | __sfr __at (0x98) SCON; 33 | __sfr __at (0x99) SBUF; 34 | __sfr __at (0x9A) SBUF_1; 35 | __sfr __at (0x9B) EIE; 36 | __sfr __at (0x9C) EIE1; 37 | __sfr __at (0x9F) CHPCON;//TA Protection 38 | 39 | __sfr __at (0xA0) P2; 40 | __sfr __at (0xA2) AUXR1; 41 | __sfr __at (0xA3) BODCON0;//TA Protection 42 | __sfr __at (0xA4) IAPTRG;//TA Protection 43 | __sfr __at (0xA5) IAPUEN;//TA Protection 44 | __sfr __at (0xA6) IAPAL; 45 | __sfr __at (0xA7) IAPAH; 46 | 47 | __sfr __at (0xA8) IE; 48 | __sfr __at (0xA9) SADDR; 49 | __sfr __at (0xAA) WDCON;//TA Protection 50 | __sfr __at (0xAB) BODCON1;//TA Protection 51 | __sfr __at (0xAC) P3M1; 52 | __sfr __at (0xAC) P3S;//Page1 53 | __sfr __at (0xAD) P3M2; 54 | __sfr __at (0xAD) P3SR;//Page1 55 | __sfr __at (0xAE) IAPFD; 56 | __sfr __at (0xAF) IAPCN; 57 | 58 | __sfr __at (0xB0) P3; 59 | __sfr __at (0xB1) P0M1; 60 | __sfr __at (0xB1) P0S;//Page1 61 | __sfr __at (0xB2) P0M2; 62 | __sfr __at (0xB2) P0SR;//Page1 63 | __sfr __at (0xB3) P1M1; 64 | __sfr __at (0xB3) P1S;//Page1 65 | __sfr __at (0xB4) P1M2; 66 | __sfr __at (0xB4) P1SR;//Page1 67 | __sfr __at (0xB5) P2S; 68 | __sfr __at (0xB7) IPH; 69 | __sfr __at (0xB7) PWMINTC;//Page1 70 | 71 | __sfr __at (0xB8) IP; 72 | __sfr __at (0xB9) SADEN; 73 | __sfr __at (0xBA) SADEN_1; 74 | __sfr __at (0xBB) SADDR_1; 75 | __sfr __at (0xBC) I2DAT; 76 | __sfr __at (0xBD) I2STAT; 77 | __sfr __at (0xBE) I2CLK; 78 | __sfr __at (0xBF) I2TOC; 79 | 80 | __sfr __at (0xC0) I2CON; 81 | __sfr __at (0xC1) I2ADDR; 82 | __sfr __at (0xC2) ADCRL; 83 | __sfr __at (0xC3) ADCRH; 84 | __sfr __at (0xC4) T3CON; 85 | __sfr __at (0xC4) PWM4H;//Page1 86 | __sfr __at (0xC5) RL3; 87 | __sfr __at (0xC5) PWM5H;//Page1 88 | __sfr __at (0xC6) RH3; 89 | __sfr __at (0xC6) PIOCON1;//Page1 90 | __sfr __at (0xC7) TA; 91 | 92 | __sfr __at (0xC8) T2CON; 93 | __sfr __at (0xC9) T2MOD; 94 | __sfr __at (0xCA) RCMP2L; 95 | __sfr __at (0xCB) RCMP2H; 96 | __sfr __at (0xCC) TL2; 97 | __sfr __at (0xCC) PWM4L;//Page1 98 | __sfr __at (0xCD) TH2; 99 | __sfr __at (0xCD) PWM5L;//Page1 100 | __sfr __at (0xCE) ADCMPL; 101 | __sfr __at (0xCF) ADCMPH; 102 | 103 | __sfr __at (0xD0) PSW; 104 | __sfr __at (0xD1) PWMPH; 105 | __sfr __at (0xD2) PWM0H; 106 | __sfr __at (0xD3) PWM1H; 107 | __sfr __at (0xD4) PWM2H; 108 | __sfr __at (0xD5) PWM3H; 109 | __sfr __at (0xD6) PNP; 110 | __sfr __at (0xD7) FBD; 111 | 112 | __sfr __at (0xD8) PWMCON0; 113 | __sfr __at (0xD9) PWMPL; 114 | __sfr __at (0xDA) PWM0L; 115 | __sfr __at (0xDB) PWM1L; 116 | __sfr __at (0xDC) PWM2L; 117 | __sfr __at (0xDD) PWM3L; 118 | __sfr __at (0xDE) PIOCON0; 119 | __sfr __at (0xDF) PWMCON1; 120 | 121 | __sfr __at (0xE0) ACC; 122 | __sfr __at (0xE1) ADCCON1; 123 | __sfr __at (0xE2) ADCCON2; 124 | __sfr __at (0xE3) ADCDLY; 125 | __sfr __at (0xE4) C0L; 126 | __sfr __at (0xE5) C0H; 127 | __sfr __at (0xE6) C1L; 128 | __sfr __at (0xE7) C1H; 129 | 130 | __sfr __at (0xE8) ADCCON0; 131 | __sfr __at (0xE9) PICON; 132 | __sfr __at (0xEA) PINEN; 133 | __sfr __at (0xEB) PIPEN; 134 | __sfr __at (0xEC) PIF; 135 | __sfr __at (0xED) C2L; 136 | __sfr __at (0xEE) C2H; 137 | __sfr __at (0xEF) EIP; 138 | 139 | __sfr __at (0xF0) B; 140 | __sfr __at (0xF1) CAPCON3; 141 | __sfr __at (0xF2) CAPCON4; 142 | __sfr __at (0xF3) SPCR; 143 | __sfr __at (0xF3) SPCR2;//Page1 144 | __sfr __at (0xF4) SPSR; 145 | __sfr __at (0xF5) SPDR; 146 | __sfr __at (0xF6) AINDIDS; 147 | __sfr __at (0xF7) EIPH; 148 | 149 | __sfr __at (0xF8) SCON_1; 150 | __sfr __at (0xF9) PDTEN;//TA Protection 151 | __sfr __at (0xFA) PDTCNT;//TA Protection 152 | __sfr __at (0xFB) PMEN; 153 | __sfr __at (0xFC) PMD; 154 | __sfr __at (0xFE) EIP1; 155 | __sfr __at (0xFF) EIPH1; 156 | 157 | /******* BIT addressable Registers **********/ 158 | 159 | /* P0 80H */ 160 | __sbit __at (0x80+0) P00; 161 | __sbit __at (0x80+1) P01; 162 | __sbit __at (0x80+2) P02; 163 | __sbit __at (0x80+3) P03; 164 | __sbit __at (0x80+4) P04; 165 | __sbit __at (0x80+5) P05; 166 | __sbit __at (0x80+6) P06; 167 | __sbit __at (0x80+7) P07; 168 | 169 | /* TCON 88H */ 170 | __sbit __at (0x88+7) TF1; 171 | __sbit __at (0x88+6) TR1; 172 | __sbit __at (0x88+5) TF0; 173 | __sbit __at (0x88+4) TR0; 174 | __sbit __at (0x88+3) IE1; 175 | __sbit __at (0x88+2) IT1; 176 | __sbit __at (0x88+1) IE0; 177 | __sbit __at (0x88+0) IT0; 178 | 179 | /* P1 90H */ 180 | __sbit __at (0x90+0) P10; 181 | __sbit __at (0x90+1) P11; 182 | __sbit __at (0x90+2) P12; 183 | __sbit __at (0x90+3) P13; 184 | __sbit __at (0x90+3) SCL; 185 | __sbit __at (0x90+4) P14; 186 | __sbit __at (0x90+4) SDA; 187 | __sbit __at (0x90+7) P17; 188 | 189 | 190 | /* SCON 98H */ 191 | __sbit __at (0x98+7) SM0; 192 | __sbit __at (0x98+7) FE; 193 | __sbit __at (0x98+6) SM1; 194 | __sbit __at (0x98+5) SM2; 195 | __sbit __at (0x98+4) REN; 196 | __sbit __at (0x98+3) TB8; 197 | __sbit __at (0x98+2) RB8; 198 | __sbit __at (0x98+1) TI; 199 | __sbit __at (0x98+0) RI; 200 | 201 | /* P2 A0H */ 202 | __sbit __at (0xA0+0) P20; 203 | 204 | /* IE A8H */ 205 | __sbit __at (0xA8+7) EA; 206 | __sbit __at (0xA8+6) EADC; 207 | __sbit __at (0xA8+5) EBOD; 208 | __sbit __at (0xA8+4) ES; 209 | __sbit __at (0xA8+3) ET1; 210 | __sbit __at (0xA8+2) EX1; 211 | __sbit __at (0xA8+1) ET0; 212 | __sbit __at (0xA8+0) EX0; 213 | 214 | /* P3 B0H */ 215 | __sbit __at (0xB0+0) P30; 216 | __sbit __at (0xB0+0) INT0; 217 | 218 | /* IP B8H */ 219 | __sbit __at (0xB8+6) PADC; 220 | __sbit __at (0xB8+5) PBOD; 221 | __sbit __at (0xB8+4) PS; 222 | __sbit __at (0xB8+3) PT1; 223 | __sbit __at (0xB8+2) PX1; 224 | __sbit __at (0xB8+1) PT0; 225 | __sbit __at (0xB8+0) PX0; 226 | 227 | /* I2CON C0H */ 228 | __sbit __at (0xC0+6) I2CEN; 229 | __sbit __at (0xC0+5) STA; 230 | __sbit __at (0xC0+4) STO; 231 | __sbit __at (0xC0+3) SI; 232 | __sbit __at (0xC0+2) AA; 233 | __sbit __at (0xC0+0) I2CPX; 234 | 235 | /* T2CON C8H */ 236 | __sbit __at (0xC8+7) TF2; 237 | __sbit __at (0xC8+2) TR2; 238 | __sbit __at (0xC8+0) CM_RL2; 239 | 240 | /* PSW D0H */ 241 | __sbit __at (0xD0+7) CY; 242 | __sbit __at (0xD0+6) AC; 243 | __sbit __at (0xD0+5) F0; 244 | __sbit __at (0xD0+4) RS1; 245 | __sbit __at (0xD0+3) RS0; 246 | __sbit __at (0xD0+2) OV; 247 | __sbit __at (0xD0+0) P; 248 | 249 | /* PWMCON0 D8H */ 250 | __sbit __at (0xD8+7) PWMRUN; 251 | __sbit __at (0xD8+6) LOAD; 252 | __sbit __at (0xD8+5) PWMF; 253 | __sbit __at (0xD8+4) CLRPWM; 254 | 255 | /* ADCCON0 E8H */ 256 | __sbit __at (0xE8+7) ADCF; 257 | __sbit __at (0xE8+6) ADCS; 258 | __sbit __at (0xE8+5) ETGSEL1; 259 | __sbit __at (0xE8+4) ETGSEL0; 260 | __sbit __at (0xE8+3) ADCHS3; 261 | __sbit __at (0xE8+2) ADCHS2; 262 | __sbit __at (0xE8+1) ADCHS1; 263 | __sbit __at (0xE8+0) ADCHS0; 264 | 265 | /* SCON_1 */ 266 | __sbit __at (0xF8+7) SM0_1; 267 | __sbit __at (0xF8+7) FE_1; 268 | __sbit __at (0xF8+6) SM1_1; 269 | __sbit __at (0xF8+5) SM2_1; 270 | __sbit __at (0xF8+4) REN_1; 271 | __sbit __at (0xF8+3) TB8_1; 272 | __sbit __at (0xF8+2) RB8_1; 273 | __sbit __at (0xF8+1) TI_1; 274 | __sbit __at (0xF8+0) RI_1; 275 | -------------------------------------------------------------------------------- /headers/n76e616.h: -------------------------------------------------------------------------------- 1 | /*-------------------------------------------------------------------------- 2 | N76E616.H 3 | 4 | Header file for Nuvoton N76E616 5 | --------------------------------------------------------------------------*/ 6 | /* BYTE Registers */ 7 | __sfr __at (0x80) P0; 8 | __sfr __at (0x81) SP; 9 | __sfr __at (0x82) DPL; 10 | __sfr __at (0x83) DPH; 11 | __sfr __at (0x86) RWK; 12 | __sfr __at (0x87) PCON; 13 | 14 | __sfr __at (0x88) TCON; 15 | __sfr __at (0x89) TMOD; 16 | __sfr __at (0x8A) TL0; 17 | __sfr __at (0x8B) TL1; 18 | __sfr __at (0x8C) TH0; 19 | __sfr __at (0x8D) TH1; 20 | __sfr __at (0x8E) CKCON; 21 | __sfr __at (0x8F) WKCON; 22 | 23 | __sfr __at (0x90) P1; 24 | __sfr __at (0x95) CKDIV; 25 | __sfr __at (0x96) CKSWT; 26 | __sfr __at (0x97) CKEN; 27 | 28 | __sfr __at (0x98) SCON; 29 | __sfr __at (0x99) SBUF; 30 | __sfr __at (0x9A) SBUF_1; 31 | __sfr __at (0x9B) EIE; 32 | __sfr __at (0x9C) EIE1; 33 | __sfr __at (0x9F) CHPCON; 34 | 35 | __sfr __at (0xA0) P2; 36 | __sfr __at (0xA2) AUXR1; 37 | __sfr __at (0xA3) BODCON0; 38 | __sfr __at (0xA4) IAPTRG; 39 | __sfr __at (0xA5) IAPUEN; 40 | __sfr __at (0xA6) IAPAL; 41 | __sfr __at (0xA7) IAPAH; 42 | 43 | __sfr __at (0xA8) IE; 44 | __sfr __at (0xA9) SADDR; 45 | __sfr __at (0xAA) WDCON; 46 | __sfr __at (0xAB) BODCON1; 47 | __sfr __at (0xAC) P3M1; 48 | __sfr __at (0xAC) P3S; 49 | __sfr __at (0xAD) P3M2; 50 | __sfr __at (0xAE) IAPFD; 51 | __sfr __at (0xAF) IAPCN; 52 | 53 | __sfr __at (0xB0) P3; 54 | __sfr __at (0xB1) P0M1; 55 | __sfr __at (0xB1) P0S; 56 | __sfr __at (0xB2) P0M2; 57 | __sfr __at (0xB3) P1M1; 58 | __sfr __at (0xB3) P1S; 59 | __sfr __at (0xB4) P1M2; 60 | __sfr __at (0xB5) P2M1; 61 | __sfr __at (0xB5) P2S; 62 | __sfr __at (0xB6) P2M2; 63 | __sfr __at (0xB7) IPH; 64 | 65 | __sfr __at (0xB8) IP; 66 | __sfr __at (0xB9) SADEN; 67 | __sfr __at (0xBA) SADEN_1; 68 | __sfr __at (0xBB) SADDR_1; 69 | __sfr __at (0xBC) I2DAT; 70 | __sfr __at (0xBD) I2STAT; 71 | __sfr __at (0xBE) I2CLK; 72 | __sfr __at (0xBF) I2TOC; 73 | 74 | __sfr __at (0xC0) I2CON; 75 | __sfr __at (0xC1) I2ADDR; 76 | __sfr __at (0xC2) ADCRL; 77 | __sfr __at (0xC3) ADCRH; 78 | __sfr __at (0xC4) T3CON; 79 | __sfr __at (0xC5) R3L; 80 | __sfr __at (0xC6) R3H; 81 | __sfr __at (0xC7) TA; 82 | 83 | __sfr __at (0xC8) T2CON; 84 | __sfr __at (0xC9) T2MOD0; 85 | __sfr __at (0xCA) T2MOD1; 86 | __sfr __at (0xCB) T2OE; 87 | __sfr __at (0xCC) R2AL; 88 | __sfr __at (0xCD) R2AH; 89 | __sfr __at (0xCE) R2BL; 90 | __sfr __at (0xCF) R2BH; 91 | 92 | __sfr __at (0xD0) PSW; 93 | __sfr __at (0xD4) R2CL; 94 | __sfr __at (0xD5) R2CH; 95 | __sfr __at (0xD6) R2DL; 96 | __sfr __at (0xD7) R2DH; 97 | 98 | __sfr __at (0xD8) P5; 99 | __sfr __at (0xD9) P4; 100 | __sfr __at (0xDA) P4M1; 101 | __sfr __at (0xDA) P4S; 102 | __sfr __at (0xDB) P4M2; 103 | __sfr __at (0xDC) P5M1; 104 | __sfr __at (0xDC) P5S; 105 | __sfr __at (0xDD) P5M2; 106 | 107 | __sfr __at (0xE0) ACC; 108 | __sfr __at (0xE1) ADCCON1; 109 | __sfr __at (0xE2) ADCCON2; 110 | __sfr __at (0xE3) ADCMPL; 111 | __sfr __at (0xE4) ADCMPH; 112 | __sfr __at (0xE5) LCDSEG0; 113 | __sfr __at (0xE6) LCDSEG1; 114 | __sfr __at (0xE7) LCDSEG2; 115 | 116 | __sfr __at (0xE8) ADCCON0; 117 | __sfr __at (0xE9) PICON; 118 | __sfr __at (0xEA) PINEN; 119 | __sfr __at (0xEB) PIPEN; 120 | __sfr __at (0xEC) PIF; 121 | __sfr __at (0xED) PITYP; 122 | __sfr __at (0xEE) LCDSEG3; 123 | __sfr __at (0xEF) EIP; 124 | 125 | __sfr __at (0xF0) B; 126 | __sfr __at (0xF2) ADCAQT; 127 | __sfr __at (0xF6) P0DIDS; 128 | __sfr __at (0xF7) EIPH; 129 | 130 | __sfr __at (0xF8) SCON_1; 131 | __sfr __at (0xF9) LCDCON; 132 | __sfr __at (0xFA) LCDCLK; 133 | __sfr __at (0xFB) LCDPTR; 134 | __sfr __at (0xFC) LCDDAT; 135 | __sfr __at (0xFE) EIP1; 136 | __sfr __at (0xFF) EIPH1; 137 | 138 | /* BIT Registers */ 139 | /* TCON */ 140 | __sbit __at (0x88+7) TF1; 141 | __sbit __at (0x88+6) TR1; 142 | __sbit __at (0x88+5) TF0; 143 | __sbit __at (0x88+4) TR0; 144 | __sbit __at (0x88+3) IE1; 145 | __sbit __at (0x88+2) IT1; 146 | __sbit __at (0x88+1) IE0; 147 | __sbit __at (0x88+0) IT0; 148 | 149 | /* SCON */ 150 | __sbit __at (0x98+7) SM0; 151 | __sbit __at (0x98+7) FE; 152 | __sbit __at (0x98+6) SM1; 153 | __sbit __at (0x98+5) SM2; 154 | __sbit __at (0x98+4) REN; 155 | __sbit __at (0x98+3) TB8; 156 | __sbit __at (0x98+2) RB8; 157 | __sbit __at (0x98+1) TI; 158 | __sbit __at (0x98+0) RI; 159 | 160 | /* IE */ 161 | __sbit __at (0xA8+7) EA; 162 | __sbit __at (0xA8+6) EADC; 163 | __sbit __at (0xA8+5) EBOD; 164 | __sbit __at (0xA8+4) ES; 165 | __sbit __at (0xA8+3) ET1; 166 | __sbit __at (0xA8+2) EX1; 167 | __sbit __at (0xA8+1) ET0; 168 | __sbit __at (0xA8+0) EX0; 169 | 170 | /* IP */ 171 | __sbit __at (0xB8+6) PADC; 172 | __sbit __at (0xB8+5) PBOD; 173 | __sbit __at (0xB8+4) PS; 174 | __sbit __at (0xB8+3) PT1; 175 | __sbit __at (0xB8+2) PX1; 176 | __sbit __at (0xB8+1) PT0; 177 | __sbit __at (0xB8+0) PX0; 178 | 179 | /* I2CON */ 180 | __sbit __at (0xC0+6) I2CEN; 181 | __sbit __at (0xC0+5) STA; 182 | __sbit __at (0xC0+4) STO; 183 | __sbit __at (0xC0+3) SI; 184 | __sbit __at (0xC0+2) AA; 185 | 186 | /* T2CON */ 187 | __sbit __at (0xC8+7) TF2D; 188 | __sbit __at (0xC8+6) TF2C; 189 | __sbit __at (0xC8+5) TF2B; 190 | __sbit __at (0xC8+4) TF2A; 191 | __sbit __at (0xC8+3) TR2D; 192 | __sbit __at (0xC8+2) TR2C; 193 | __sbit __at (0xC8+1) TR2B; 194 | __sbit __at (0xC8+0) TR2A; 195 | 196 | /* PSW */ 197 | __sbit __at (0xD0+7) CY; 198 | __sbit __at (0xD0+6) AC; 199 | __sbit __at (0xD0+5) F0; 200 | __sbit __at (0xD0+4) RS1; 201 | __sbit __at (0xD0+3) RS0; 202 | __sbit __at (0xD0+2) OV; 203 | __sbit __at (0xD0+0) P; 204 | 205 | /* ADCCON0 */ 206 | __sbit __at (0xE8+7) ADCF; 207 | __sbit __at (0xE8+6) ADCS; 208 | __sbit __at (0xE8+3) ADCHS3; 209 | __sbit __at (0xE8+2) ADCHS2; 210 | __sbit __at (0xE8+1) ADCHS1; 211 | __sbit __at (0xE8+0) ADCHS0; 212 | 213 | /* SCON_1 */ 214 | __sbit __at (0xF8+7) SM0_1; 215 | __sbit __at (0xF8+7) FE_1; 216 | __sbit __at (0xF8+6) SM1_1; 217 | __sbit __at (0xF8+5) SM2_1; 218 | __sbit __at (0xF8+4) REN_1; 219 | __sbit __at (0xF8+3) TB8_1; 220 | __sbit __at (0xF8+2) RB8_1; 221 | __sbit __at (0xF8+1) TI_1; 222 | __sbit __at (0xF8+0) RI_1; 223 | 224 | 225 | /* P0 */ 226 | __sbit __at (0x80+0) P00; 227 | __sbit __at (0x80+0) AIN0; 228 | __sbit __at (0x80+0) T0; 229 | __sbit __at (0x80+1) P01; 230 | __sbit __at (0x80+1) AIN1; 231 | __sbit __at (0x80+1) INT0; 232 | __sbit __at (0x80+2) P02; 233 | __sbit __at (0x80+2) AIN2; 234 | __sbit __at (0x80+3) P03; 235 | __sbit __at (0x80+3) AIN3; 236 | __sbit __at (0x80+4) P04; 237 | __sbit __at (0x80+4) AIN4; 238 | __sbit __at (0x80+5) P05; 239 | __sbit __at (0x80+5) AIN5; 240 | __sbit __at (0x80+6) P06; 241 | __sbit __at (0x80+6) AIN6; 242 | __sbit __at (0x80+7) P07; 243 | __sbit __at (0x80+7) AIN7; 244 | __sbit __at (0x80+7) CLO; 245 | 246 | /* P1 */ 247 | __sbit __at (0x90+0) P10; 248 | __sbit __at (0x90+1) P11; 249 | __sbit __at (0x90+2) P12; 250 | __sbit __at (0x90+3) P13; 251 | __sbit __at (0x90+3) INT1; 252 | __sbit __at (0x90+4) P14; 253 | __sbit __at (0x90+4) T1; 254 | __sbit __at (0x90+5) P15; 255 | __sbit __at (0x90+5) T2AO1; 256 | __sbit __at (0x90+6) P16; 257 | __sbit __at (0x90+6) T2AO2; 258 | __sbit __at (0x90+7) P17; 259 | __sbit __at (0x90+7) T2BO1; 260 | 261 | /* P2 */ 262 | __sbit __at (0xA0+0) P20; 263 | __sbit __at (0xA0+0) T2BO2; 264 | __sbit __at (0xA0+1) P21; 265 | __sbit __at (0xA0+1) RXD; 266 | __sbit __at (0xA0+2) P22; 267 | __sbit __at (0xA0+2) TXD; 268 | __sbit __at (0xA0+3) P23; 269 | __sbit __at (0xA0+3) SDA; 270 | __sbit __at (0xA0+4) P24; 271 | __sbit __at (0xA0+4) SCL; 272 | __sbit __at (0xA0+5) P25; 273 | __sbit __at (0xA0+6) P26; 274 | __sbit __at (0xA0+6) T2CO1; 275 | __sbit __at (0xA0+7) P27; 276 | __sbit __at (0xA0+7) T2CO2; 277 | 278 | /* P3 */ 279 | __sbit __at (0xB0+0) P30; 280 | __sbit __at (0xB0+0) T2DO1; 281 | __sbit __at (0xB0+1) P31; 282 | __sbit __at (0xB0+1) T2DO2; 283 | __sbit __at (0xB0+2) P32; 284 | __sbit __at (0xB0+3) P33; 285 | __sbit __at (0xB0+4) P34; 286 | __sbit __at (0xB0+5) P35; 287 | __sbit __at (0xB0+6) P36; 288 | __sbit __at (0xB0+7) P37; 289 | 290 | /* P5 */ 291 | __sbit __at (0xD8+0) P50; 292 | __sbit __at (0xD8+0) STADC; 293 | __sbit __at (0xD8+1) P51; 294 | __sbit __at (0xD8+2) P52; 295 | __sbit __at (0xD8+3) P53; 296 | __sbit __at (0xD8+4) P54; 297 | __sbit __at (0xD8+5) P55; 298 | __sbit __at (0xD8+6) P56; 299 | __sbit __at (0xD8+6) RXD_1; 300 | __sbit __at (0xD8+7) P57; 301 | __sbit __at (0xD8+7) TXD_1; 302 | -------------------------------------------------------------------------------- /headers/n76e885.h: -------------------------------------------------------------------------------- 1 | /*-------------------------------------------------------------------------- 2 | N76E885.H 3 | 4 | Header file for Nuvoton N76E885 5 | --------------------------------------------------------------------------*/ 6 | 7 | #ifndef __N76E885_H__ 8 | #define __N76E885_H__ 9 | 10 | __sfr __at (0x80) P0; 11 | __sfr __at (0x81) SP; 12 | __sfr __at (0x82) DPL; 13 | __sfr __at (0x83) DPH; 14 | __sfr __at (0x86) RWK; 15 | __sfr __at (0x87) PCON; 16 | 17 | __sfr __at (0x88) TCON; 18 | __sfr __at (0x89) TMOD; 19 | __sfr __at (0x8A) TL0; 20 | __sfr __at (0x8B) TL1; 21 | __sfr __at (0x8C) TH0; 22 | __sfr __at (0x8D) TH1; 23 | __sfr __at (0x8E) CKCON; 24 | __sfr __at (0x8F) WKCON; 25 | 26 | __sfr __at (0x90) P1; 27 | __sfr __at (0x91) SFRS;//TA Protection 28 | __sfr __at (0x92) CAPCON0; 29 | __sfr __at (0x93) CAPCON1; 30 | __sfr __at (0x94) CAPCON2; 31 | __sfr __at (0x95) CKDIV; 32 | __sfr __at (0x96) CKSWT;//TA Protection 33 | __sfr __at (0x97) CKEN;//TA Protection 34 | 35 | __sfr __at (0x98) SCON; 36 | __sfr __at (0x99) SBUF; 37 | __sfr __at (0x9A) SBUF_1; 38 | __sfr __at (0x9B) EIE; 39 | __sfr __at (0x9C) EIE1; 40 | __sfr __at (0x9F) CHPCON;//TA Protection 41 | 42 | __sfr __at (0xA0) P2; 43 | __sfr __at (0xA2) AUXR1; 44 | __sfr __at (0xA3) BODCON0;//TA Protection 45 | __sfr __at (0xA4) IAPTRG;//TA Protection 46 | __sfr __at (0xA5) IAPUEN; 47 | __sfr __at (0xA6) IAPAL; 48 | __sfr __at (0xA7) IAPAH; 49 | 50 | __sfr __at (0xA8) IE; 51 | __sfr __at (0xA9) SADDR; 52 | __sfr __at (0xAA) WDCON;//TA Protection 53 | __sfr __at (0xAB) BODCON1;//TA Protection 54 | __sfr __at (0xAC) P3M1; 55 | __sfr __at (0xAC) P3S;//Page1 56 | __sfr __at (0xAD) P3M2; 57 | __sfr __at (0xAD) P3SR;//Page1 58 | __sfr __at (0xAE) IAPFD; 59 | __sfr __at (0xAF) IAPCN; 60 | 61 | __sfr __at (0xB0) P3; 62 | __sfr __at (0xB1) P0M1; 63 | __sfr __at (0xB1) P0S;//Page1 64 | __sfr __at (0xB2) P0M2; 65 | __sfr __at (0xB2) P0SR;//Page1 66 | __sfr __at (0xB3) P1M1; 67 | __sfr __at (0xB3) P1S;//Page1 68 | __sfr __at (0xB4) P1M2; 69 | __sfr __at (0xB4) P1SR;//Page1 70 | __sfr __at (0xB5) P2M1; 71 | __sfr __at (0xB5) P2S;//Page1 72 | __sfr __at (0xB6) P2M2; 73 | __sfr __at (0xB6) P2SR;//Page1 74 | __sfr __at (0xB7) IPH; 75 | 76 | __sfr __at (0xB8) IP; 77 | __sfr __at (0xB9) SADEN; 78 | __sfr __at (0xBA) SADEN_1; 79 | __sfr __at (0xBB) SADDR_1; 80 | __sfr __at (0xBC) I2DAT; 81 | __sfr __at (0xBD) I2STAT; 82 | __sfr __at (0xBE) I2CLK; 83 | __sfr __at (0xBF) I2TOC; 84 | 85 | __sfr __at (0xC0) I2CON; 86 | __sfr __at (0xC1) I2ADDR; 87 | __sfr __at (0xC2) ADCRL; 88 | __sfr __at (0xC3) ADCRH; 89 | __sfr __at (0xC4) T3CON; 90 | __sfr __at (0xC5) RL3; 91 | __sfr __at (0xC6) RH3; 92 | __sfr __at (0xC7) TA; 93 | 94 | __sfr __at (0xC8) T2CON; 95 | __sfr __at (0xC9) T2MOD; 96 | __sfr __at (0xCA) RCMP2L; 97 | __sfr __at (0xCB) RCMP2H; 98 | __sfr __at (0xCC) TL2; 99 | __sfr __at (0xCD) TH2; 100 | __sfr __at (0xCE) ADCMPL; 101 | __sfr __at (0xCF) ADCMPH; 102 | 103 | __sfr __at (0xD0) PSW; 104 | __sfr __at (0xD1) PWMPH; 105 | __sfr __at (0xD2) PWM01H; 106 | __sfr __at (0xD3) PWM23H; 107 | __sfr __at (0xD4) PWM67H; 108 | __sfr __at (0xD5) PWM45H; 109 | __sfr __at (0xD6) PNP; 110 | __sfr __at (0xD7) FBD; 111 | 112 | __sfr __at (0xD8) PWMCON0; 113 | __sfr __at (0xD9) PWMPL; 114 | __sfr __at (0xDA) PWM01L; 115 | __sfr __at (0xDB) PWM23L; 116 | __sfr __at (0xDC) PWM67L; 117 | __sfr __at (0xDD) PWM45L; 118 | __sfr __at (0xDE) PIO; 119 | __sfr __at (0xDF) PWMCON1; 120 | 121 | __sfr __at (0xE0) ACC; 122 | __sfr __at (0xE1) ADCCON1; 123 | __sfr __at (0xE2) ADCCON2; 124 | __sfr __at (0xE3) ADCDLY; 125 | __sfr __at (0xE4) C0L; 126 | __sfr __at (0xE5) C0H; 127 | __sfr __at (0xE6) C1L; 128 | __sfr __at (0xE7) C1H; 129 | 130 | __sfr __at (0xE8) ADCCON0; 131 | __sfr __at (0xE9) PICON; 132 | __sfr __at (0xEA) PINEN; 133 | __sfr __at (0xEB) PIPEN; 134 | __sfr __at (0xEC) PIF; 135 | __sfr __at (0xED) C2L; 136 | __sfr __at (0xEE) C2H; 137 | __sfr __at (0xEF) EIP; 138 | 139 | __sfr __at (0xF0) B; 140 | __sfr __at (0xF2) ADCAQT; 141 | __sfr __at (0xF3) SPCR; 142 | __sfr __at (0xF4) SPSR; 143 | __sfr __at (0xF5) SPDR; 144 | __sfr __at (0xF6) P0DIDS; 145 | __sfr __at (0xF7) EIPH; 146 | 147 | __sfr __at (0xF8) SCON_1; 148 | __sfr __at (0xF9) PDTEN;//TA Protection 149 | __sfr __at (0xFA) PDTCNT;//TA Protection 150 | __sfr __at (0xFB) PMEN; 151 | __sfr __at (0xFC) PMD; 152 | __sfr __at (0xFE) EIP1; 153 | __sfr __at (0xFF) EIPH1; 154 | 155 | /* BIT Registers */ 156 | /* SCON_1 */ 157 | __sbit __at (0xF8+7) SM0_1; 158 | __sbit __at (0xF8+7) FE_1; 159 | __sbit __at (0xF8+6) SM1_1; 160 | __sbit __at (0xF8+5) SM2_1; 161 | __sbit __at (0xF8+4) REN_1; 162 | __sbit __at (0xF8+3) TB8_1; 163 | __sbit __at (0xF8+2) RB8_1; 164 | __sbit __at (0xF8+1) TI_1; 165 | __sbit __at (0xF8+0) RI_1; 166 | 167 | /* ADCCON0 */ 168 | __sbit __at (0xE8+7) ADCF; 169 | __sbit __at (0xE8+6) ADCS; 170 | __sbit __at (0xE8+5) ETGSEL1; 171 | __sbit __at (0xE8+4) ETGSEL0; 172 | __sbit __at (0xE8+3) ADCHS3; 173 | __sbit __at (0xE8+2) ADCHS2; 174 | __sbit __at (0xE8+1) ADCHS1; 175 | __sbit __at (0xE8+0) ADCHS0; 176 | 177 | /* PWMCON0 */ 178 | __sbit __at (0xD8+7) PWMRUN; 179 | __sbit __at (0xD8+6) LOAD; 180 | __sbit __at (0xD8+5) PWMF; 181 | __sbit __at (0xD8+4) CLRPWM; 182 | __sbit __at (0xD8+3) INTTYP1; 183 | __sbit __at (0xD8+2) INTTYP0; 184 | __sbit __at (0xD8+1) INTSEL1; 185 | __sbit __at (0xD8+0) INTSEL0; 186 | 187 | /* PSW */ 188 | __sbit __at (0xD0+7) CY; 189 | __sbit __at (0xD0+6) AC; 190 | __sbit __at (0xD0+5) F0; 191 | __sbit __at (0xD0+4) RS1; 192 | __sbit __at (0xD0+3) RS0; 193 | __sbit __at (0xD0+2) OV; 194 | __sbit __at (0xD0+0) P; 195 | 196 | /* T2CON */ 197 | __sbit __at (0xC8+7) TF2; 198 | __sbit __at (0xC8+2) TR2; 199 | __sbit __at (0xC8+0) CM_CR2; 200 | 201 | /* I2CON */ 202 | __sbit __at (0xC0+6) I2CEN; 203 | __sbit __at (0xC0+5) STA; 204 | __sbit __at (0xC0+4) STO; 205 | __sbit __at (0xC0+3) SI; 206 | __sbit __at (0xC0+2) AA; 207 | 208 | /* IP */ 209 | __sbit __at (0xB8+6) PADC; 210 | __sbit __at (0xB8+5) PBOD; 211 | __sbit __at (0xB8+4) PS; 212 | __sbit __at (0xB8+3) PT1; 213 | __sbit __at (0xB8+2) PX1; 214 | __sbit __at (0xB8+1) PT0; 215 | __sbit __at (0xB8+0) PX0; 216 | 217 | /* P3 */ 218 | __sbit __at (0xB0+0) P30; 219 | __sbit __at (0xB0+1) P31; 220 | __sbit __at (0xB0+2) P32; 221 | __sbit __at (0xB0+3) P33; 222 | __sbit __at (0xB0+4) P34; 223 | __sbit __at (0xB0+5) P35; 224 | __sbit __at (0xB0+6) P36; 225 | __sbit __at (0xB0+7) P37; 226 | 227 | /* IE */ 228 | __sbit __at (0xA8+7) EA; 229 | __sbit __at (0xA8+6) EADC; 230 | __sbit __at (0xA8+5) EBOD; 231 | __sbit __at (0xA8+4) ES; 232 | __sbit __at (0xA8+3) ET1; 233 | __sbit __at (0xA8+2) EX1; 234 | __sbit __at (0xA8+1) ET0; 235 | __sbit __at (0xA8+0) EX0; 236 | 237 | /* P2 */ 238 | __sbit __at (0xA0+0) P20; 239 | __sbit __at (0xA0+0) RXD; 240 | __sbit __at (0xA0+0) T0; 241 | __sbit __at (0xA0+0) IC0; 242 | __sbit __at (0xA0+0) AIN9; 243 | 244 | __sbit __at (0xA0+1) P21; 245 | __sbit __at (0xA0+1) MOSI; 246 | __sbit __at (0xA0+1) T1; 247 | __sbit __at (0xA0+1) IC1; 248 | 249 | __sbit __at (0xA0+2) P22; 250 | __sbit __at (0xA0+2) MISO; 251 | __sbit __at (0xA0+2) IC2; 252 | 253 | __sbit __at (0xA0+3) P23; 254 | __sbit __at (0xA0+3) SDA; 255 | __sbit __at (0xA0+3) FB; 256 | __sbit __at (0xA0+3) STADC; 257 | 258 | __sbit __at (0xA0+4) P24; 259 | __sbit __at (0xA0+4) RXD_1; 260 | 261 | __sbit __at (0xA0+5) P25; 262 | __sbit __at (0xA0+5) TXD_1; 263 | 264 | __sbit __at (0xA0+6) P26; 265 | __sbit __at (0xA0+6) CLO; 266 | __sbit __at (0xA0+6) AIN8; 267 | __sbit __at (0xA0+6) PWM7; 268 | 269 | /* SCON */ 270 | __sbit __at (0x98+7) SM0; 271 | __sbit __at (0x98+7) FE; 272 | __sbit __at (0x98+6) SM1; 273 | __sbit __at (0x98+5) SM2; 274 | __sbit __at (0x98+4) REN; 275 | __sbit __at (0x98+3) TB8; 276 | __sbit __at (0x98+2) RB8; 277 | __sbit __at (0x98+1) TI; 278 | __sbit __at (0x98+0) RI; 279 | 280 | /* P1 */ 281 | __sbit __at (0x90+0) P10; 282 | __sbit __at (0x90+0) PWM0; 283 | __sbit __at (0x90+1) P11; 284 | __sbit __at (0x90+1) PWM1; 285 | __sbit __at (0x90+2) P12; 286 | 287 | /* TCON */ 288 | __sbit __at (0x88+7) TF1; 289 | __sbit __at (0x88+6) TR1; 290 | __sbit __at (0x88+5) TF0; 291 | __sbit __at (0x88+4) TR0; 292 | __sbit __at (0x88+3) IE1; 293 | __sbit __at (0x88+2) IT1; 294 | __sbit __at (0x88+1) IE0; 295 | __sbit __at (0x88+0) IT0; 296 | 297 | /* P0 */ 298 | __sbit __at (0x80+0) P00; 299 | __sbit __at (0x80+0) INT0; 300 | __sbit __at (0x80+0) AIN0; 301 | __sbit __at (0x80+0) VREF; 302 | 303 | __sbit __at (0x80+1) P01; 304 | __sbit __at (0x80+1) INT1; 305 | __sbit __at (0x80+1) AIN1; 306 | 307 | __sbit __at (0x80+2) P02; 308 | __sbit __at (0x80+2) PWM2; 309 | __sbit __at (0x80+2) AIN2; 310 | 311 | __sbit __at (0x80+3) P03; 312 | __sbit __at (0x80+3) PWM3; 313 | __sbit __at (0x80+3) TXD; 314 | __sbit __at (0x80+3) AIN3; 315 | 316 | __sbit __at (0x80+4) P04; 317 | __sbit __at (0x80+4) SS; 318 | __sbit __at (0x80+4) AIN4; 319 | 320 | __sbit __at (0x80+5) P05; 321 | __sbit __at (0x80+5) PWM4; 322 | __sbit __at (0x80+5) SPICK; 323 | __sbit __at (0x80+5) AIN5; 324 | 325 | __sbit __at (0x80+6) P06; 326 | __sbit __at (0x80+6) SCL; 327 | __sbit __at (0x80+6) AIN6; 328 | __sbit __at (0x80+6) PWM5; 329 | 330 | __sbit __at (0x80+7) P07; 331 | __sbit __at (0x80+7) AIN7; 332 | __sbit __at (0x80+7) PWM6; 333 | 334 | 335 | #endif 336 | -------------------------------------------------------------------------------- /headers/stc12c20xx.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC12C2052AD_H__ 2 | #define __STC12C2052AD_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | /* The following is STC additional SFR or change */ 7 | 8 | /* sfr AUXR = 0x8e; */ 9 | /* sfr IPH = 0xb7; */ 10 | 11 | /* Watchdog Timer Register */ 12 | __sfr __at (0xe1) WDT_CONTR; 13 | 14 | /* ISP_IAP_EEPROM Register */ 15 | __sfr __at (0xe2) ISP_DATA; 16 | __sfr __at (0xe3) ISP_ADDRH; 17 | __sfr __at (0xe4) ISP_ADDRL; 18 | __sfr __at (0xe5) ISP_CMD; 19 | __sfr __at (0xe6) ISP_TRIG; 20 | __sfr __at (0xe7) ISP_CONTR; 21 | 22 | /* IDLE, Clock Divider */ 23 | __sfr __at (0xc7) IDLE_CLK; 24 | __sfr __at (0x8F) WAKE_CLKO; 25 | 26 | /* I_O Port Mode Set Register */ 27 | __sfr __at (0x93) P0M0; 28 | __sfr __at (0x94) P0M1; 29 | __sfr __at (0x91) P1M0; 30 | __sfr __at (0x92) P1M1; 31 | __sfr __at (0x95) P2M0; 32 | __sfr __at (0x96) P2M1; 33 | __sfr __at (0xb1) P3M0; 34 | __sfr __at (0xb2) P3M1; 35 | 36 | /* SPI Register */ 37 | __sfr __at (0x84) SPSTAT; 38 | __sfr __at (0x85) SPCTL; 39 | __sfr __at (0x86) SPDAT; 40 | 41 | /* ADC Register */ 42 | __sfr __at (0xc5) ADC_CONTR; 43 | __sfr __at (0xc6) ADC_DATA; 44 | __sfr __at (0xbe) ADC_LOW2; 45 | 46 | /* PCA SFR */ 47 | __sfr __at (0xD8) CCON; 48 | __sfr __at (0xD9) CMOD; 49 | __sfr __at (0xDA) CCAPM0; 50 | __sfr __at (0xDB) CCAPM1; 51 | __sfr __at (0xDC) CCAPM2; 52 | __sfr __at (0xDD) CCAPM3; 53 | __sfr __at (0xDE) CCAPM4; 54 | __sfr __at (0xDF) CCAPM5; 55 | 56 | __sfr __at (0xE9) CL; 57 | __sfr __at (0xEA) CCAP0L; 58 | __sfr __at (0xEB) CCAP1L; 59 | __sfr __at (0xEC) CCAP2L; 60 | __sfr __at (0xED) CCAP3L; 61 | __sfr __at (0xEE) CCAP4L; 62 | __sfr __at (0xEF) CCAP5L; 63 | 64 | __sfr __at (0xF9) CH; 65 | __sfr __at (0xFA) CCAP0H; 66 | __sfr __at (0xFB) CCAP1H; 67 | __sfr __at (0xFC) CCAP2H; 68 | __sfr __at (0xFD) CCAP3H; 69 | __sfr __at (0xFE) CCAP4H; 70 | __sfr __at (0xFF) CCAP5H; 71 | 72 | __sfr __at (0xF2) PCA_PWM0; 73 | __sfr __at (0xF3) PCA_PWM1; 74 | __sfr __at (0xF4) PCA_PWM2; 75 | __sfr __at (0xF5) PCA_PWM3; 76 | __sfr __at (0xF6) PCA_PWM4; 77 | __sfr __at (0xF7) PCA_PWM5; 78 | 79 | /* CCON */ 80 | __sbit __at (0xD8+7) CF; 81 | __sbit __at (0xD8+6) CR; 82 | __sbit __at (0xD8+5) CCF5; 83 | __sbit __at (0xD8+4) CCF4; 84 | __sbit __at (0xD8+3) CCF3; 85 | __sbit __at (0xD8+2) CCF2; 86 | __sbit __at (0xD8+1) CCF1; 87 | __sbit __at (0xD8+0) CCF0; 88 | 89 | /* Above is STC additional SFR or change */ 90 | 91 | /*-------------------------------------------------------------------------- 92 | REG51F.H 93 | 94 | Header file for 8xC31/51, 80C51Fx, 80C51Rx+ 95 | Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. 96 | All rights reserved. 97 | 98 | Modification according to DataSheet from April 1999 99 | - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives 100 | --------------------------------------------------------------------------*/ 101 | 102 | /* BYTE Registers */ 103 | __sfr __at (0x80) P0; 104 | __sbit __at (0x80+0) P00; 105 | __sbit __at (0x80+1) P01; 106 | __sbit __at (0x80+2) P02; 107 | __sbit __at (0x80+3) P03; 108 | __sbit __at (0x80+4) P04; 109 | __sbit __at (0x80+5) P05; 110 | __sbit __at (0x80+6) P06; 111 | __sbit __at (0x80+7) P07; 112 | __sfr __at (0x90) P1; 113 | __sbit __at (0x90+0) P10; 114 | __sbit __at (0x90+1) P11; 115 | __sbit __at (0x90+2) P12; 116 | __sbit __at (0x90+3) P13; 117 | __sbit __at (0x90+4) P14; 118 | __sbit __at (0x90+5) P15; 119 | __sbit __at (0x90+6) P16; 120 | __sbit __at (0x90+7) P17; 121 | __sfr __at (0xA0) P2; 122 | __sbit __at (0xA0+0) P20; 123 | __sbit __at (0xA0+1) P21; 124 | __sbit __at (0xA0+2) P22; 125 | __sbit __at (0xA0+3) P23; 126 | __sbit __at (0xA0+4) P24; 127 | __sbit __at (0xA0+5) P25; 128 | __sbit __at (0xA0+6) P26; 129 | __sbit __at (0xA0+7) P27; 130 | __sfr __at (0xB0) P3; 131 | __sbit __at (0xB0+0) P30; 132 | __sbit __at (0xB0+1) P31; 133 | __sbit __at (0xB0+2) P32; 134 | __sbit __at (0xB0+3) P33; 135 | __sbit __at (0xB0+4) P34; 136 | __sbit __at (0xB0+5) P35; 137 | __sbit __at (0xB0+6) P36; 138 | __sbit __at (0xB0+7) P37; 139 | __sfr __at (0xD0) PSW; 140 | __sfr __at (0xE0) ACC; 141 | __sfr __at (0xF0) B; 142 | __sfr __at (0x81) SP; 143 | __sfr __at (0x82) DPL; 144 | __sfr __at (0x83) DPH; 145 | __sfr __at (0x87) PCON; 146 | __sfr __at (0x88) TCON; 147 | __sfr __at (0x89) TMOD; 148 | __sfr __at (0x8A) TL0; 149 | __sfr __at (0x8B) TL1; 150 | __sfr __at (0x8C) TH0; 151 | __sfr __at (0x8D) TH1; 152 | __sfr __at (0xA8) IE; 153 | __sfr __at (0xB8) IP; 154 | __sfr __at (0x98) SCON; 155 | __sfr __at (0x99) SBUF; 156 | 157 | /* 80C51Fx/Rx Extensions */ 158 | __sfr __at (0x8E) AUXR; 159 | /* sfr AUXR1 = 0xA2; */ 160 | __sfr __at (0xA9) SADDR; 161 | __sfr __at (0xB7) IPH; 162 | __sfr __at (0xB9) SADEN; 163 | __sfr __at (0xC8) T2CON; 164 | __sfr __at (0xC9) T2MOD; 165 | __sfr __at (0xCA) RCAP2L; 166 | __sfr __at (0xCB) RCAP2H; 167 | __sfr __at (0xCC) TL2; 168 | __sfr __at (0xCD) TH2; 169 | 170 | 171 | /* BIT Registers */ 172 | /* PSW */ 173 | __sbit __at (0xD0+7) CY; 174 | __sbit __at (0xD0+6) AC; 175 | __sbit __at (0xD0+5) F0; 176 | __sbit __at (0xD0+4) RS1; 177 | __sbit __at (0xD0+3) RS0; 178 | __sbit __at (0xD0+2) OV; 179 | __sbit __at (0xD0+1) F1; 180 | __sbit __at (0xD0+0) P; 181 | 182 | /* TCON */ 183 | __sbit __at (0x88+7) TF1; 184 | __sbit __at (0x88+6) TR1; 185 | __sbit __at (0x88+5) TF0; 186 | __sbit __at (0x88+4) TR0; 187 | __sbit __at (0x88+3) IE1; 188 | __sbit __at (0x88+2) IT1; 189 | __sbit __at (0x88+1) IE0; 190 | __sbit __at (0x88+0) IT0; 191 | 192 | /* P3 */ 193 | __sbit __at (0xB0+7) RD; 194 | __sbit __at (0xB0+6) WR; 195 | __sbit __at (0xB0+5) T1; 196 | __sbit __at (0xB0+4) T0; 197 | __sbit __at (0xB0+3) INT1; 198 | __sbit __at (0xB0+2) INT0; 199 | __sbit __at (0xB0+1) TXD; 200 | __sbit __at (0xB0+0) RXD; 201 | 202 | /* SCON */ 203 | __sbit __at (0x98+7) SM0;// alternatively "FE" 204 | __sbit __at (0x98+7) FE; 205 | __sbit __at (0x98+6) SM1; 206 | __sbit __at (0x98+5) SM2; 207 | __sbit __at (0x98+4) REN; 208 | __sbit __at (0x98+3) TB8; 209 | __sbit __at (0x98+2) RB8; 210 | __sbit __at (0x98+1) TI; 211 | __sbit __at (0x98+0) RI; 212 | 213 | 214 | __sbit __at (0x90+1) T2EX; 215 | __sbit __at (0x90+0) T2; 216 | 217 | /* T2CON */ 218 | __sbit __at (0xC8+7) TF2; 219 | __sbit __at (0xC8+6) EXF2; 220 | __sbit __at (0xC8+5) RCLK; 221 | __sbit __at (0xC8+4) TCLK; 222 | __sbit __at (0xC8+3) EXEN2; 223 | __sbit __at (0xC8+2) TR2; 224 | __sbit __at (0xC8+1) C_T2; 225 | __sbit __at (0xC8+0) CP_RL2; 226 | 227 | /* PCA Pin */ 228 | 229 | __sbit __at (0xA0+4) CEX3; 230 | __sbit __at (0xA0+0) CEX2; 231 | __sbit __at (0xB0+5) CEX1; 232 | __sbit __at (0xB0+7) CEX0; 233 | __sbit __at (0xB0+4) ECI; 234 | 235 | /* IE */ 236 | __sbit __at (0xA8+7) EA; 237 | __sbit __at (0xA8+6) EPCA_LVD; 238 | __sbit __at (0xA8+5) EADC_SPI; 239 | __sbit __at (0xA8+4) ES; 240 | __sbit __at (0xA8+3) ET1; 241 | __sbit __at (0xA8+2) EX1; 242 | __sbit __at (0xA8+1) ET0; 243 | __sbit __at (0xA8+0) EX0; 244 | 245 | /* IP */ 246 | __sbit __at (0xB8+6) PPCA_LVD; 247 | __sbit __at (0xB8+5) PADC_SPI; 248 | __sbit __at (0xB8+4) PS; 249 | __sbit __at (0xB8+3) PT1; 250 | __sbit __at (0xB8+2) PX1; 251 | __sbit __at (0xB8+1) PT0; 252 | __sbit __at (0xB8+0) PX0; 253 | 254 | ///////////////////////////////////////////////// 255 | 256 | #endif 257 | 258 | -------------------------------------------------------------------------------- /headers/stc12c54xx.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC12C5410AD_H__ 2 | #define __STC12C5410AD_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | /* The following is STC additional SFR or change */ 7 | 8 | /* sfr AUXR = 0x8e; */ 9 | /* sfr IPH = 0xb7; */ 10 | 11 | /* Watchdog Timer Register */ 12 | __sfr __at (0xe1) WDT_CONTR; 13 | 14 | /* ISP_IAP_EEPROM Register */ 15 | __sfr __at (0xe2) ISP_DATA; 16 | __sfr __at (0xe3) ISP_ADDRH; 17 | __sfr __at (0xe4) ISP_ADDRL; 18 | __sfr __at (0xe5) ISP_CMD; 19 | __sfr __at (0xe6) ISP_TRIG; 20 | __sfr __at (0xe7) ISP_CONTR; 21 | 22 | /* System Clock Divider */ 23 | __sfr __at (0xc7) CLK_DIV; 24 | 25 | /* I_O Port Mode Set Register */ 26 | __sfr __at (0x93) P0M0; 27 | __sfr __at (0x94) P0M1; 28 | __sfr __at (0x91) P1M0; 29 | __sfr __at (0x92) P1M1; 30 | __sfr __at (0x95) P2M0; 31 | __sfr __at (0x96) P2M1; 32 | __sfr __at (0xb1) P3M0; 33 | __sfr __at (0xb2) P3M1; 34 | 35 | /* SPI Register */ 36 | __sfr __at (0x84) SPSTAT; 37 | __sfr __at (0x85) SPCTL; 38 | __sfr __at (0x86) SPDAT; 39 | 40 | /* ADC Register */ 41 | __sfr __at (0xc5) ADC_CONTR; 42 | __sfr __at (0xc6) ADC_DATA; 43 | __sfr __at (0xbe) ADC_LOW2; 44 | 45 | /* PCA SFR */ 46 | __sfr __at (0xD8) CCON; 47 | __sfr __at (0xD9) CMOD; 48 | __sfr __at (0xDA) CCAPM0; 49 | __sfr __at (0xDB) CCAPM1; 50 | __sfr __at (0xDC) CCAPM2; 51 | __sfr __at (0xDD) CCAPM3; 52 | __sfr __at (0xDE) CCAPM4; 53 | __sfr __at (0xDF) CCAPM5; 54 | 55 | __sfr __at (0xE9) CL; 56 | __sfr __at (0xEA) CCAP0L; 57 | __sfr __at (0xEB) CCAP1L; 58 | __sfr __at (0xEC) CCAP2L; 59 | __sfr __at (0xED) CCAP3L; 60 | __sfr __at (0xEE) CCAP4L; 61 | __sfr __at (0xEF) CCAP5L; 62 | 63 | __sfr __at (0xF9) CH; 64 | __sfr __at (0xFA) CCAP0H; 65 | __sfr __at (0xFB) CCAP1H; 66 | __sfr __at (0xFC) CCAP2H; 67 | __sfr __at (0xFD) CCAP3H; 68 | __sfr __at (0xFE) CCAP4H; 69 | __sfr __at (0xFF) CCAP5H; 70 | 71 | __sfr __at (0xF2) PCA_PWM0; 72 | __sfr __at (0xF3) PCA_PWM1; 73 | __sfr __at (0xF4) PCA_PWM2; 74 | __sfr __at (0xF5) PCA_PWM3; 75 | __sfr __at (0xF6) PCA_PWM4; 76 | __sfr __at (0xF7) PCA_PWM5; 77 | 78 | /* CCON */ 79 | __sbit __at (0xD8+7) CF; 80 | __sbit __at (0xD8+6) CR; 81 | __sbit __at (0xD8+5) CCF5; 82 | __sbit __at (0xD8+4) CCF4; 83 | __sbit __at (0xD8+3) CCF3; 84 | __sbit __at (0xD8+2) CCF2; 85 | __sbit __at (0xD8+1) CCF1; 86 | __sbit __at (0xD8+0) CCF0; 87 | 88 | 89 | /* Above is STC additional SFR or change */ 90 | 91 | /*-------------------------------------------------------------------------- 92 | REG51F.H 93 | 94 | Header file for 8xC31/51, 80C51Fx, 80C51Rx+ 95 | Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. 96 | All rights reserved. 97 | 98 | Modification according to DataSheet from April 1999 99 | - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives 100 | --------------------------------------------------------------------------*/ 101 | 102 | /* BYTE Registers */ 103 | __sfr __at (0x80) P0; 104 | __sbit __at (0x80+0) P00; 105 | __sbit __at (0x80+1) P01; 106 | __sbit __at (0x80+2) P02; 107 | __sbit __at (0x80+3) P03; 108 | __sbit __at (0x80+4) P04; 109 | __sbit __at (0x80+5) P05; 110 | __sbit __at (0x80+6) P06; 111 | __sbit __at (0x80+7) P07; 112 | __sfr __at (0x90) P1; 113 | __sbit __at (0x90+0) P10; 114 | __sbit __at (0x90+1) P11; 115 | __sbit __at (0x90+2) P12; 116 | __sbit __at (0x90+3) P13; 117 | __sbit __at (0x90+4) P14; 118 | __sbit __at (0x90+5) P15; 119 | __sbit __at (0x90+6) P16; 120 | __sbit __at (0x90+7) P17; 121 | __sfr __at (0xA0) P2; 122 | __sbit __at (0xA0+0) P20; 123 | __sbit __at (0xA0+1) P21; 124 | __sbit __at (0xA0+2) P22; 125 | __sbit __at (0xA0+3) P23; 126 | __sbit __at (0xA0+4) P24; 127 | __sbit __at (0xA0+5) P25; 128 | __sbit __at (0xA0+6) P26; 129 | __sbit __at (0xA0+7) P27; 130 | __sfr __at (0xB0) P3; 131 | __sbit __at (0xB0+0) P30; 132 | __sbit __at (0xB0+1) P31; 133 | __sbit __at (0xB0+2) P32; 134 | __sbit __at (0xB0+3) P33; 135 | __sbit __at (0xB0+4) P34; 136 | __sbit __at (0xB0+5) P35; 137 | __sbit __at (0xB0+6) P36; 138 | __sbit __at (0xB0+7) P37; 139 | __sfr __at (0xD0) PSW; 140 | __sfr __at (0xE0) ACC; 141 | __sfr __at (0xF0) B; 142 | __sfr __at (0x81) SP; 143 | __sfr __at (0x82) DPL; 144 | __sfr __at (0x83) DPH; 145 | __sfr __at (0x87) PCON; 146 | __sfr __at (0x88) TCON; 147 | __sfr __at (0x89) TMOD; 148 | __sfr __at (0x8A) TL0; 149 | __sfr __at (0x8B) TL1; 150 | __sfr __at (0x8C) TH0; 151 | __sfr __at (0x8D) TH1; 152 | __sfr __at (0xA8) IE; 153 | __sfr __at (0xB8) IP; 154 | __sfr __at (0x98) SCON; 155 | __sfr __at (0x99) SBUF; 156 | 157 | /* 80C51Fx/Rx Extensions */ 158 | __sfr __at (0x8E) AUXR; 159 | /* sfr AUXR1 = 0xA2; */ 160 | __sfr __at (0xA9) SADDR; 161 | __sfr __at (0xB7) IPH; 162 | __sfr __at (0xB9) SADEN; 163 | __sfr __at (0xC8) T2CON; 164 | __sfr __at (0xC9) T2MOD; 165 | __sfr __at (0xCA) RCAP2L; 166 | __sfr __at (0xCB) RCAP2H; 167 | __sfr __at (0xCC) TL2; 168 | __sfr __at (0xCD) TH2; 169 | 170 | 171 | /* BIT Registers */ 172 | /* PSW */ 173 | __sbit __at (0xD0+7) CY; 174 | __sbit __at (0xD0+6) AC; 175 | __sbit __at (0xD0+5) F0; 176 | __sbit __at (0xD0+4) RS1; 177 | __sbit __at (0xD0+3) RS0; 178 | __sbit __at (0xD0+2) OV; 179 | __sbit __at (0xD0+1) F1; 180 | __sbit __at (0xD0+0) P; 181 | 182 | /* TCON */ 183 | __sbit __at (0x88+7) TF1; 184 | __sbit __at (0x88+6) TR1; 185 | __sbit __at (0x88+5) TF0; 186 | __sbit __at (0x88+4) TR0; 187 | __sbit __at (0x88+3) IE1; 188 | __sbit __at (0x88+2) IT1; 189 | __sbit __at (0x88+1) IE0; 190 | __sbit __at (0x88+0) IT0; 191 | 192 | /* P3 */ 193 | __sbit __at (0xB0+7) RD; 194 | __sbit __at (0xB0+6) WR; 195 | __sbit __at (0xB0+5) T1; 196 | __sbit __at (0xB0+4) T0; 197 | __sbit __at (0xB0+3) INT1; 198 | __sbit __at (0xB0+2) INT0; 199 | __sbit __at (0xB0+1) TXD; 200 | __sbit __at (0xB0+0) RXD; 201 | 202 | /* SCON */ 203 | __sbit __at (0x98+7) SM0;// alternatively "FE" 204 | __sbit __at (0x98+7) FE; 205 | __sbit __at (0x98+6) SM1; 206 | __sbit __at (0x98+5) SM2; 207 | __sbit __at (0x98+4) REN; 208 | __sbit __at (0x98+3) TB8; 209 | __sbit __at (0x98+2) RB8; 210 | __sbit __at (0x98+1) TI; 211 | __sbit __at (0x98+0) RI; 212 | 213 | 214 | __sbit __at (0x90+1) T2EX; 215 | __sbit __at (0x90+0) T2; 216 | 217 | /* T2CON */ 218 | __sbit __at (0xC8+7) TF2; 219 | __sbit __at (0xC8+6) EXF2; 220 | __sbit __at (0xC8+5) RCLK; 221 | __sbit __at (0xC8+4) TCLK; 222 | __sbit __at (0xC8+3) EXEN2; 223 | __sbit __at (0xC8+2) TR2; 224 | __sbit __at (0xC8+1) C_T2; 225 | __sbit __at (0xC8+0) CP_RL2; 226 | 227 | /* PCA Pin */ 228 | 229 | __sbit __at (0xA0+4) CEX3; 230 | __sbit __at (0xA0+0) CEX2; 231 | __sbit __at (0xB0+5) CEX1; 232 | __sbit __at (0xB0+7) CEX0; 233 | __sbit __at (0xB0+4) ECI; 234 | 235 | /* IE */ 236 | __sbit __at (0xA8+7) EA; 237 | __sbit __at (0xA8+6) EPCA_LVD; 238 | __sbit __at (0xA8+5) EADC_SPI; 239 | __sbit __at (0xA8+4) ES; 240 | __sbit __at (0xA8+3) ET1; 241 | __sbit __at (0xA8+2) EX1; 242 | __sbit __at (0xA8+1) ET0; 243 | __sbit __at (0xA8+0) EX0; 244 | 245 | /* IP */ 246 | __sbit __at (0xB8+6) PPCA_LVD; 247 | __sbit __at (0xB8+5) PADC_SPI; 248 | __sbit __at (0xB8+4) PS; 249 | __sbit __at (0xB8+3) PT1; 250 | __sbit __at (0xB8+2) PX1; 251 | __sbit __at (0xB8+1) PT0; 252 | __sbit __at (0xB8+0) PX0; 253 | 254 | ///////////////////////////////////////////////// 255 | 256 | #endif 257 | 258 | -------------------------------------------------------------------------------- /headers/stc12c56xx.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC12C5630AD_H__ 2 | #define __STC12C5630AD_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | /* The following is STC additional SFR or change */ 7 | 8 | /* sfr AUXR = 0x8e; */ 9 | /* sfr IPH = 0xb7; */ 10 | 11 | /* Watchdog Timer Register */ 12 | __sfr __at (0xe1) WDT_CONTR; 13 | 14 | /* ISP_IAP_EEPROM Register */ 15 | __sfr __at (0xe2) ISP_DATA; 16 | __sfr __at (0xe3) ISP_ADDRH; 17 | __sfr __at (0xe4) ISP_ADDRL; 18 | __sfr __at (0xe5) ISP_CMD; 19 | __sfr __at (0xe6) ISP_TRIG; 20 | __sfr __at (0xe7) ISP_CONTR; 21 | 22 | /* System Clock Divider */ 23 | __sfr __at (0xc7) CLK_DIV; 24 | 25 | /* I_O Port Mode Set Register */ 26 | __sfr __at (0x93) P0M0; 27 | __sfr __at (0x94) P0M1; 28 | __sfr __at (0x91) P1M0; 29 | __sfr __at (0x92) P1M1; 30 | __sfr __at (0x95) P2M0; 31 | __sfr __at (0x96) P2M1; 32 | __sfr __at (0xb1) P3M0; 33 | __sfr __at (0xb2) P3M1; 34 | 35 | /* SPI Register */ 36 | __sfr __at (0x84) SPSTAT; 37 | __sfr __at (0x85) SPCTL; 38 | __sfr __at (0x86) SPDAT; 39 | 40 | /* ADC Register */ 41 | __sfr __at (0xc5) ADC_CONTR; 42 | __sfr __at (0xc6) ADC_DATA; 43 | __sfr __at (0xbe) ADC_LOW2; 44 | 45 | /* PCA SFR */ 46 | __sfr __at (0xD8) CCON; 47 | __sfr __at (0xD9) CMOD; 48 | __sfr __at (0xDA) CCAPM0; 49 | __sfr __at (0xDB) CCAPM1; 50 | __sfr __at (0xDC) CCAPM2; 51 | __sfr __at (0xDD) CCAPM3; 52 | __sfr __at (0xDE) CCAPM4; 53 | __sfr __at (0xDF) CCAPM5; 54 | 55 | __sfr __at (0xE9) CL; 56 | __sfr __at (0xEA) CCAP0L; 57 | __sfr __at (0xEB) CCAP1L; 58 | __sfr __at (0xEC) CCAP2L; 59 | __sfr __at (0xED) CCAP3L; 60 | __sfr __at (0xEE) CCAP4L; 61 | __sfr __at (0xEF) CCAP5L; 62 | 63 | __sfr __at (0xF9) CH; 64 | __sfr __at (0xFA) CCAP0H; 65 | __sfr __at (0xFB) CCAP1H; 66 | __sfr __at (0xFC) CCAP2H; 67 | __sfr __at (0xFD) CCAP3H; 68 | __sfr __at (0xFE) CCAP4H; 69 | __sfr __at (0xFF) CCAP5H; 70 | 71 | __sfr __at (0xF2) PCA_PWM0; 72 | __sfr __at (0xF3) PCA_PWM1; 73 | __sfr __at (0xF4) PCA_PWM2; 74 | __sfr __at (0xF5) PCA_PWM3; 75 | __sfr __at (0xF6) PCA_PWM4; 76 | __sfr __at (0xF7) PCA_PWM5; 77 | 78 | /* CCON */ 79 | __sbit __at (0xD8+7) CF; 80 | __sbit __at (0xD8+6) CR; 81 | __sbit __at (0xD8+5) CCF5; 82 | __sbit __at (0xD8+4) CCF4; 83 | __sbit __at (0xD8+3) CCF3; 84 | __sbit __at (0xD8+2) CCF2; 85 | __sbit __at (0xD8+1) CCF1; 86 | __sbit __at (0xD8+0) CCF0; 87 | 88 | 89 | /* Above is STC additional SFR or change */ 90 | 91 | /*-------------------------------------------------------------------------- 92 | REG51F.H 93 | 94 | Header file for 8xC31/51, 80C51Fx, 80C51Rx+ 95 | Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. 96 | All rights reserved. 97 | 98 | Modification according to DataSheet from April 1999 99 | - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives 100 | --------------------------------------------------------------------------*/ 101 | 102 | /* BYTE Registers */ 103 | __sfr __at (0x80) P0; 104 | __sbit __at (0x80+0) P00; 105 | __sbit __at (0x80+1) P01; 106 | __sbit __at (0x80+2) P02; 107 | __sbit __at (0x80+3) P03; 108 | __sbit __at (0x80+4) P04; 109 | __sbit __at (0x80+5) P05; 110 | __sbit __at (0x80+6) P06; 111 | __sbit __at (0x80+7) P07; 112 | __sfr __at (0x90) P1; 113 | __sbit __at (0x90+0) P10; 114 | __sbit __at (0x90+1) P11; 115 | __sbit __at (0x90+2) P12; 116 | __sbit __at (0x90+3) P13; 117 | __sbit __at (0x90+4) P14; 118 | __sbit __at (0x90+5) P15; 119 | __sbit __at (0x90+6) P16; 120 | __sbit __at (0x90+7) P17; 121 | __sfr __at (0xA0) P2; 122 | __sbit __at (0xA0+0) P20; 123 | __sbit __at (0xA0+1) P21; 124 | __sbit __at (0xA0+2) P22; 125 | __sbit __at (0xA0+3) P23; 126 | __sbit __at (0xA0+4) P24; 127 | __sbit __at (0xA0+5) P25; 128 | __sbit __at (0xA0+6) P26; 129 | __sbit __at (0xA0+7) P27; 130 | __sfr __at (0xB0) P3; 131 | __sbit __at (0xB0+0) P30; 132 | __sbit __at (0xB0+1) P31; 133 | __sbit __at (0xB0+2) P32; 134 | __sbit __at (0xB0+3) P33; 135 | __sbit __at (0xB0+4) P34; 136 | __sbit __at (0xB0+5) P35; 137 | __sbit __at (0xB0+6) P36; 138 | __sbit __at (0xB0+7) P37; 139 | __sfr __at (0xD0) PSW; 140 | __sfr __at (0xE0) ACC; 141 | __sfr __at (0xF0) B; 142 | __sfr __at (0x81) SP; 143 | __sfr __at (0x82) DPL; 144 | __sfr __at (0x83) DPH; 145 | __sfr __at (0x87) PCON; 146 | __sfr __at (0x88) TCON; 147 | __sfr __at (0x89) TMOD; 148 | __sfr __at (0x8A) TL0; 149 | __sfr __at (0x8B) TL1; 150 | __sfr __at (0x8C) TH0; 151 | __sfr __at (0x8D) TH1; 152 | __sfr __at (0xA8) IE; 153 | __sfr __at (0xB8) IP; 154 | __sfr __at (0x98) SCON; 155 | __sfr __at (0x99) SBUF; 156 | 157 | /* 80C51Fx/Rx Extensions */ 158 | __sfr __at (0x8E) AUXR; 159 | /* sfr AUXR1 = 0xA2; */ 160 | __sfr __at (0xA9) SADDR; 161 | __sfr __at (0xB7) IPH; 162 | __sfr __at (0xB9) SADEN; 163 | __sfr __at (0xC8) T2CON; 164 | __sfr __at (0xC9) T2MOD; 165 | __sfr __at (0xCA) RCAP2L; 166 | __sfr __at (0xCB) RCAP2H; 167 | __sfr __at (0xCC) TL2; 168 | __sfr __at (0xCD) TH2; 169 | 170 | 171 | /* BIT Registers */ 172 | /* PSW */ 173 | __sbit __at (0xD0+7) CY; 174 | __sbit __at (0xD0+6) AC; 175 | __sbit __at (0xD0+5) F0; 176 | __sbit __at (0xD0+4) RS1; 177 | __sbit __at (0xD0+3) RS0; 178 | __sbit __at (0xD0+2) OV; 179 | __sbit __at (0xD0+1) F1; 180 | __sbit __at (0xD0+0) P; 181 | 182 | /* TCON */ 183 | __sbit __at (0x88+7) TF1; 184 | __sbit __at (0x88+6) TR1; 185 | __sbit __at (0x88+5) TF0; 186 | __sbit __at (0x88+4) TR0; 187 | __sbit __at (0x88+3) IE1; 188 | __sbit __at (0x88+2) IT1; 189 | __sbit __at (0x88+1) IE0; 190 | __sbit __at (0x88+0) IT0; 191 | 192 | /* P3 */ 193 | __sbit __at (0xB0+7) RD; 194 | __sbit __at (0xB0+6) WR; 195 | __sbit __at (0xB0+5) T1; 196 | __sbit __at (0xB0+4) T0; 197 | __sbit __at (0xB0+3) INT1; 198 | __sbit __at (0xB0+2) INT0; 199 | __sbit __at (0xB0+1) TXD; 200 | __sbit __at (0xB0+0) RXD; 201 | 202 | /* SCON */ 203 | __sbit __at (0x98+7) SM0;// alternatively "FE" 204 | __sbit __at (0x98+7) FE; 205 | __sbit __at (0x98+6) SM1; 206 | __sbit __at (0x98+5) SM2; 207 | __sbit __at (0x98+4) REN; 208 | __sbit __at (0x98+3) TB8; 209 | __sbit __at (0x98+2) RB8; 210 | __sbit __at (0x98+1) TI; 211 | __sbit __at (0x98+0) RI; 212 | 213 | 214 | __sbit __at (0x90+1) T2EX; 215 | __sbit __at (0x90+0) T2; 216 | 217 | /* T2CON */ 218 | __sbit __at (0xC8+7) TF2; 219 | __sbit __at (0xC8+6) EXF2; 220 | __sbit __at (0xC8+5) RCLK; 221 | __sbit __at (0xC8+4) TCLK; 222 | __sbit __at (0xC8+3) EXEN2; 223 | __sbit __at (0xC8+2) TR2; 224 | __sbit __at (0xC8+1) C_T2; 225 | __sbit __at (0xC8+0) CP_RL2; 226 | 227 | /* PCA Pin */ 228 | 229 | __sbit __at (0xA0+4) CEX3; 230 | __sbit __at (0xA0+0) CEX2; 231 | __sbit __at (0xB0+5) CEX1; 232 | __sbit __at (0xB0+7) CEX0; 233 | __sbit __at (0xB0+4) ECI; 234 | 235 | /* IE */ 236 | __sbit __at (0xA8+7) EA; 237 | __sbit __at (0xA8+6) EPCA_LVD; 238 | __sbit __at (0xA8+5) EADC_SPI; 239 | __sbit __at (0xA8+4) ES; 240 | __sbit __at (0xA8+3) ET1; 241 | __sbit __at (0xA8+2) EX1; 242 | __sbit __at (0xA8+1) ET0; 243 | __sbit __at (0xA8+0) EX0; 244 | 245 | /* IP */ 246 | __sbit __at (0xB8+6) PPCA_LVD; 247 | __sbit __at (0xB8+5) PADC_SPI; 248 | __sbit __at (0xB8+4) PS; 249 | __sbit __at (0xB8+3) PT1; 250 | __sbit __at (0xB8+2) PX1; 251 | __sbit __at (0xB8+1) PT0; 252 | __sbit __at (0xB8+0) PX0; 253 | 254 | ///////////////////////////////////////////////// 255 | 256 | #endif 257 | 258 | -------------------------------------------------------------------------------- /headers/stc15f104e.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC15F104E_H__ 2 | #define __STC15F104E_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | //包含本头文件后,不用另外再包含"REG51.H" 7 | 8 | //内核特殊功能寄存器 // 复位值 描述 9 | __sfr __at (0xE0) ACC;//0000,0000 累加器Accumulator 10 | __sfr __at (0xF0) B;//0000,0000 B寄存器 11 | __sfr __at (0xD0) PSW;//0000,0000 程序状态字 12 | __sbit __at (0xD0+7) CY; 13 | __sbit __at (0xD0+6) AC; 14 | __sbit __at (0xD0+5) F0; 15 | __sbit __at (0xD0+4) RS1; 16 | __sbit __at (0xD0+3) RS0; 17 | __sbit __at (0xD0+2) OV; 18 | __sbit __at (0xD0+1) F1; 19 | __sbit __at (0xD0+0) P; 20 | __sfr __at (0x81) SP;//0000,0111 堆栈指针 21 | __sfr __at (0x82) DPL;//0000,0000 数据指针低字节 22 | __sfr __at (0x83) DPH;//0000,0000 数据指针高字节 23 | 24 | //I/O 口特殊功能寄存器 25 | __sfr __at (0x80) P0;//1111,1111 端口0 26 | __sbit __at (0x80+0) P00; 27 | __sbit __at (0x80+1) P01; 28 | __sbit __at (0x80+2) P02; 29 | __sbit __at (0x80+3) P03; 30 | __sbit __at (0x80+4) P04; 31 | __sbit __at (0x80+5) P05; 32 | __sbit __at (0x80+6) P06; 33 | __sbit __at (0x80+7) P07; 34 | __sfr __at (0x90) P1;//1111,1111 端口1 35 | __sbit __at (0x90+0) P10; 36 | __sbit __at (0x90+1) P11; 37 | __sbit __at (0x90+2) P12; 38 | __sbit __at (0x90+3) P13; 39 | __sbit __at (0x90+4) P14; 40 | __sbit __at (0x90+5) P15; 41 | __sbit __at (0x90+6) P16; 42 | __sbit __at (0x90+7) P17; 43 | __sfr __at (0xA0) P2;//1111,1111 端口2 44 | __sbit __at (0xA0+0) P20; 45 | __sbit __at (0xA0+1) P21; 46 | __sbit __at (0xA0+2) P22; 47 | __sbit __at (0xA0+3) P23; 48 | __sbit __at (0xA0+4) P24; 49 | __sbit __at (0xA0+5) P25; 50 | __sbit __at (0xA0+6) P26; 51 | __sbit __at (0xA0+7) P27; 52 | __sfr __at (0xB0) P3;//1111,1111 端口3 53 | __sbit __at (0xB0+0) P30; 54 | __sbit __at (0xB0+1) P31; 55 | __sbit __at (0xB0+2) P32; 56 | __sbit __at (0xB0+3) P33; 57 | __sbit __at (0xB0+4) P34; 58 | __sbit __at (0xB0+5) P35; 59 | __sbit __at (0xB0+6) P36; 60 | __sbit __at (0xB0+7) P37; 61 | __sfr __at (0xC0) P4;//1111,1111 端口4 62 | __sbit __at (0xC0+0) P40; 63 | __sbit __at (0xC0+1) P41; 64 | __sbit __at (0xC0+2) P42; 65 | __sbit __at (0xC0+3) P43; 66 | __sbit __at (0xC0+4) P44; 67 | __sbit __at (0xC0+5) P45; 68 | __sbit __at (0xC0+6) P46; 69 | __sbit __at (0xC0+7) P47; 70 | __sfr __at (0xC8) P5;//xxxx,1111 端口5 71 | __sbit __at (0xC8+0) P50; 72 | __sbit __at (0xC8+1) P51; 73 | __sbit __at (0xC8+2) P52; 74 | __sbit __at (0xC8+3) P53; 75 | __sbit __at (0xC8+4) P54; 76 | __sbit __at (0xC8+5) P55; 77 | __sbit __at (0xC8+6) P56; 78 | __sbit __at (0xC8+7) P57; 79 | __sfr __at (0xE8) P6;//0000,0000 端口6 80 | __sbit __at (0xE8+0) P60; 81 | __sbit __at (0xE8+1) P61; 82 | __sbit __at (0xE8+2) P62; 83 | __sbit __at (0xE8+3) P63; 84 | __sbit __at (0xE8+4) P64; 85 | __sbit __at (0xE8+5) P65; 86 | __sbit __at (0xE8+6) P66; 87 | __sbit __at (0xE8+7) P67; 88 | __sfr __at (0xF8) P7;//0000,0000 端口7 89 | __sbit __at (0xF8+0) P70; 90 | __sbit __at (0xF8+1) P71; 91 | __sbit __at (0xF8+2) P72; 92 | __sbit __at (0xF8+3) P73; 93 | __sbit __at (0xF8+4) P74; 94 | __sbit __at (0xF8+5) P75; 95 | __sbit __at (0xF8+6) P76; 96 | __sbit __at (0xF8+7) P77; 97 | __sfr __at (0x94) P0M0;//0000,0000 端口0模式寄存器0 98 | __sfr __at (0x93) P0M1;//0000,0000 端口0模式寄存器1 99 | __sfr __at (0x92) P1M0;//0000,0000 端口1模式寄存器0 100 | __sfr __at (0x91) P1M1;//0000,0000 端口1模式寄存器1 101 | __sfr __at (0x96) P2M0;//0000,0000 端口2模式寄存器0 102 | __sfr __at (0x95) P2M1;//0000,0000 端口2模式寄存器1 103 | __sfr __at (0xB2) P3M0;//0000,0000 端口3模式寄存器0 104 | __sfr __at (0xB1) P3M1;//0000,0000 端口3模式寄存器1 105 | __sfr __at (0xB4) P4M0;//0000,0000 端口4模式寄存器0 106 | __sfr __at (0xB3) P4M1;//0000,0000 端口4模式寄存器1 107 | __sfr __at (0xCA) P5M0;//0000,0000 端口5模式寄存器0 108 | __sfr __at (0xC9) P5M1;//0000,0000 端口5模式寄存器1 109 | __sfr __at (0xCC) P6M0;//0000,0000 端口6模式寄存器0 110 | __sfr __at (0xCB) P6M1;//0000,0000 端口6模式寄存器1 111 | __sfr __at (0xE2) P7M0;//0000,0000 端口7模式寄存器0 112 | __sfr __at (0xE1) P7M1;//0000,0000 端口7模式寄存器1 113 | 114 | //系统管理特殊功能寄存器 115 | __sfr __at (0x87) PCON;//0001,0000 电源控制寄存器 116 | __sfr __at (0x8E) AUXR;//0000,0000 辅助寄存器 117 | __sfr __at (0xA2) AUXR1;//0000,0000 辅助寄存器1 118 | __sfr __at (0xA2) P_SW1;//0000,0000 外设端口切换寄存器1 119 | __sfr __at (0x97) CLK_DIV;//xxxx,x000 时钟分频控制寄存器 120 | __sfr __at (0xA1) BUS_SPEED;//xx10,x011 总线速度控制寄存器 121 | __sfr __at (0x9D) P1ASF;//0000,0000 端口1模拟功能配置寄存器 122 | __sfr __at (0xBA) P_SW2;//0000,0000 外设端口切换寄存器 123 | __sfr __at (0xBB) IRC_CLKO;//0000,0000 内部振荡器时钟输出控制寄存器 124 | 125 | //中断特殊功能寄存器 126 | __sfr __at (0xA8) IE;//0000,0000 中断控制寄存器 127 | __sbit __at (0xA8+7) EA; 128 | __sbit __at (0xA8+6) ELVD; 129 | __sbit __at (0xA8+5) EADC; 130 | __sbit __at (0xA8+4) ES; 131 | __sbit __at (0xA8+3) ET1; 132 | __sbit __at (0xA8+2) EX1; 133 | __sbit __at (0xA8+1) ET0; 134 | __sbit __at (0xA8+0) EX0; 135 | __sfr __at (0xB8) IP;//0000,0000 中断优先级寄存器 136 | __sbit __at (0xB8+7) PPCA; 137 | __sbit __at (0xB8+6) PLVD; 138 | __sbit __at (0xB8+5) PADC; 139 | __sbit __at (0xB8+4) PS; 140 | __sbit __at (0xB8+3) PT1; 141 | __sbit __at (0xB8+2) PX1; 142 | __sbit __at (0xB8+1) PT0; 143 | __sbit __at (0xB8+0) PX0; 144 | __sfr __at (0xAF) IE2;//0000,0000 中断控制寄存器2 145 | __sfr __at (0xB5) IP2;//xxxx,xx00 中断优先级寄存器2 146 | __sfr __at (0x8F) INT_CLKO;//0000,0000 外部中断与时钟输出控制寄存器 147 | 148 | //定时器特殊功能寄存器 149 | __sfr __at (0x88) TCON;//0000,0000 T0/T1控制寄存器 150 | __sbit __at (0x88+7) TF1; 151 | __sbit __at (0x88+6) TR1; 152 | __sbit __at (0x88+5) TF0; 153 | __sbit __at (0x88+4) TR0; 154 | __sbit __at (0x88+3) IE1; 155 | __sbit __at (0x88+2) IT1; 156 | __sbit __at (0x88+1) IE0; 157 | __sbit __at (0x88+0) IT0; 158 | __sfr __at (0x89) TMOD;//0000,0000 T0/T1模式寄存器 159 | __sfr __at (0x8A) TL0;//0000,0000 T0低字节 160 | __sfr __at (0x8B) TL1;//0000,0000 T1低字节 161 | __sfr __at (0x8C) TH0;//0000,0000 T0高字节 162 | __sfr __at (0x8D) TH1;//0000,0000 T1高字节 163 | __sfr __at (0xD1) T4T3M;//0000,0000 T3/T4模式寄存器 164 | __sfr __at (0xD1) T3T4M;//0000,0000 T3/T4模式寄存器 165 | __sfr __at (0xD2) T4H;//0000,0000 T4高字节 166 | __sfr __at (0xD3) T4L;//0000,0000 T4低字节 167 | __sfr __at (0xD4) T3H;//0000,0000 T3高字节 168 | __sfr __at (0xD5) T3L;//0000,0000 T3低字节 169 | __sfr __at (0xD6) T2H;//0000,0000 T2高字节 170 | __sfr __at (0xD7) T2L;//0000,0000 T2低字节 171 | __sfr __at (0xAA) WKTCL;//0000,0000 掉电唤醒定时器低字节 172 | __sfr __at (0xAB) WKTCH;//0000,0000 掉电唤醒定时器高字节 173 | __sfr __at (0xC1) WDT_CONTR;//0000,0000 看门狗控制寄存器 174 | 175 | //串行口特殊功能寄存器 176 | __sfr __at (0x98) SCON;//0000,0000 串口1控制寄存器 177 | __sbit __at (0x98+7) SM0; 178 | __sbit __at (0x98+6) SM1; 179 | __sbit __at (0x98+5) SM2; 180 | __sbit __at (0x98+4) REN; 181 | __sbit __at (0x98+3) TB8; 182 | __sbit __at (0x98+2) RB8; 183 | __sbit __at (0x98+1) TI; 184 | __sbit __at (0x98+0) RI; 185 | __sfr __at (0x99) SBUF;//xxxx,xxxx 串口1数据寄存器 186 | __sfr __at (0x9A) S2CON;//0000,0000 串口2控制寄存器 187 | __sfr __at (0x9B) S2BUF;//xxxx,xxxx 串口2数据寄存器 188 | __sfr __at (0xAC) S3CON;//0000,0000 串口3控制寄存器 189 | __sfr __at (0xAD) S3BUF;//xxxx,xxxx 串口3数据寄存器 190 | __sfr __at (0x84) S4CON;//0000,0000 串口4控制寄存器 191 | __sfr __at (0x85) S4BUF;//xxxx,xxxx 串口4数据寄存器 192 | __sfr __at (0xA9) SADDR;//0000,0000 从机地址寄存器 193 | __sfr __at (0xB9) SADEN;//0000,0000 从机地址屏蔽寄存器 194 | 195 | //ADC 特殊功能寄存器 196 | __sfr __at (0xBC) ADC_CONTR;//0000,0000 A/D转换控制寄存器 197 | __sfr __at (0xBD) ADC_RES;//0000,0000 A/D转换结果高8位 198 | __sfr __at (0xBE) ADC_RESL;//0000,0000 A/D转换结果低2位 199 | 200 | //SPI 特殊功能寄存器 201 | __sfr __at (0xCD) SPSTAT;//00xx,xxxx SPI状态寄存器 202 | __sfr __at (0xCE) SPCTL;//0000,0100 SPI控制寄存器 203 | __sfr __at (0xCF) SPDAT;//0000,0000 SPI数据寄存器 204 | 205 | //IAP/ISP 特殊功能寄存器 206 | __sfr __at (0xC2) IAP_DATA;//0000,0000 EEPROM数据寄存器 207 | __sfr __at (0xC3) IAP_ADDRH;//0000,0000 EEPROM地址高字节 208 | __sfr __at (0xC4) IAP_ADDRL;//0000,0000 EEPROM地址第字节 209 | __sfr __at (0xC5) IAP_CMD;//xxxx,xx00 EEPROM命令寄存器 210 | __sfr __at (0xC6) IAP_TRIG;//0000,0000 EEPRPM命令触发寄存器 211 | __sfr __at (0xC7) IAP_CONTR;//0000,x000 EEPROM控制寄存器 212 | 213 | //PCA/PWM 特殊功能寄存器 214 | __sfr __at (0xD8) CCON;//00xx,xx00 PCA控制寄存器 215 | __sbit __at (0xD8+7) CF; 216 | __sbit __at (0xD8+6) CR; 217 | __sbit __at (0xD8+2) CCF2; 218 | __sbit __at (0xD8+1) CCF1; 219 | __sbit __at (0xD8+0) CCF0; 220 | __sfr __at (0xD9) CMOD;//0xxx,x000 PCA 工作模式寄存器 221 | __sfr __at (0xE9) CL;//0000,0000 PCA计数器低字节 222 | __sfr __at (0xF9) CH;//0000,0000 PCA计数器高字节 223 | __sfr __at (0xDA) CCAPM0;//0000,0000 PCA模块0的PWM寄存器 224 | __sfr __at (0xDB) CCAPM1;//0000,0000 PCA模块1的PWM寄存器 225 | __sfr __at (0xDC) CCAPM2;//0000,0000 PCA模块2的PWM 寄存器 226 | __sfr __at (0xEA) CCAP0L;//0000,0000 PCA模块0的捕捉/比较寄存器低字节 227 | __sfr __at (0xEB) CCAP1L;//0000,0000 PCA模块1的捕捉/比较寄存器低字节 228 | __sfr __at (0xEC) CCAP2L;//0000,0000 PCA模块2的捕捉/比较寄存器低字节 229 | __sfr __at (0xF2) PCA_PWM0;//xxxx,xx00 PCA模块0的PWM寄存器 230 | __sfr __at (0xF3) PCA_PWM1;//xxxx,xx00 PCA模块1的PWM寄存器 231 | __sfr __at (0xF4) PCA_PWM2;//xxxx,xx00 PCA模块1的PWM寄存器 232 | __sfr __at (0xFA) CCAP0H;//0000,0000 PCA模块0的捕捉/比较寄存器高字节 233 | __sfr __at (0xFB) CCAP1H;//0000,0000 PCA模块1的捕捉/比较寄存器高字节 234 | __sfr __at (0xFC) CCAP2H;//0000,0000 PCA模块2的捕捉/比较寄存器高字节 235 | 236 | ///////////////////////////////////////////////// 237 | 238 | #endif 239 | 240 | -------------------------------------------------------------------------------- /headers/stc15fxx.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC15_H__ 2 | #define __STC15_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | //注意: STC15W4K32S4系列的芯片,上电后所有与PWM相关的IO口均为 6 | // 高阻态,需将这些口设置为准双向口或强推挽模式方可正常使用 7 | //相关IO: P0.6/P0.7/P1.6/P1.7/P2.1/P2.2 8 | // P2.3/P2.7/P3.7/P4.2/P4.4/P4.5 9 | ///////////////////////////////////////////////// 10 | 11 | ///////////////////////////////////////////////// 12 | 13 | //包含本头文件后,不用另外再包含"REG51.H" 14 | 15 | //内核特殊功能寄存器 // 复位值 描述 16 | __sfr __at (0xE0) ACC;//0000,0000 累加器Accumulator 17 | __sfr __at (0xF0) B;//0000,0000 B寄存器 18 | __sfr __at (0xD0) PSW;//0000,0000 程序状态字 19 | __sbit __at (0xD0+7) CY; 20 | __sbit __at (0xD0+6) AC; 21 | __sbit __at (0xD0+5) F0; 22 | __sbit __at (0xD0+4) RS1; 23 | __sbit __at (0xD0+3) RS0; 24 | __sbit __at (0xD0+2) OV; 25 | __sbit __at (0xD0+1) F1; 26 | __sbit __at (0xD0+0) P; 27 | __sfr __at (0x81) SP;//0000,0111 堆栈指针 28 | __sfr __at (0x82) DPL;//0000,0000 数据指针低字节 29 | __sfr __at (0x83) DPH;//0000,0000 数据指针高字节 30 | 31 | //I/O 口特殊功能寄存器 32 | __sfr __at (0x80) P0;//1111,1111 端口0 33 | __sbit __at (0x80+0) P00; 34 | __sbit __at (0x80+1) P01; 35 | __sbit __at (0x80+2) P02; 36 | __sbit __at (0x80+3) P03; 37 | __sbit __at (0x80+4) P04; 38 | __sbit __at (0x80+5) P05; 39 | __sbit __at (0x80+6) P06; 40 | __sbit __at (0x80+7) P07; 41 | __sfr __at (0x90) P1;//1111,1111 端口1 42 | __sbit __at (0x90+0) P10; 43 | __sbit __at (0x90+1) P11; 44 | __sbit __at (0x90+2) P12; 45 | __sbit __at (0x90+3) P13; 46 | __sbit __at (0x90+4) P14; 47 | __sbit __at (0x90+5) P15; 48 | __sbit __at (0x90+6) P16; 49 | __sbit __at (0x90+7) P17; 50 | __sfr __at (0xA0) P2;//1111,1111 端口2 51 | __sbit __at (0xA0+0) P20; 52 | __sbit __at (0xA0+1) P21; 53 | __sbit __at (0xA0+2) P22; 54 | __sbit __at (0xA0+3) P23; 55 | __sbit __at (0xA0+4) P24; 56 | __sbit __at (0xA0+5) P25; 57 | __sbit __at (0xA0+6) P26; 58 | __sbit __at (0xA0+7) P27; 59 | __sfr __at (0xB0) P3;//1111,1111 端口3 60 | __sbit __at (0xB0+0) P30; 61 | __sbit __at (0xB0+1) P31; 62 | __sbit __at (0xB0+2) P32; 63 | __sbit __at (0xB0+3) P33; 64 | __sbit __at (0xB0+4) P34; 65 | __sbit __at (0xB0+5) P35; 66 | __sbit __at (0xB0+6) P36; 67 | __sbit __at (0xB0+7) P37; 68 | __sfr __at (0xC0) P4;//1111,1111 端口4 69 | __sbit __at (0xC0+0) P40; 70 | __sbit __at (0xC0+1) P41; 71 | __sbit __at (0xC0+2) P42; 72 | __sbit __at (0xC0+3) P43; 73 | __sbit __at (0xC0+4) P44; 74 | __sbit __at (0xC0+5) P45; 75 | __sbit __at (0xC0+6) P46; 76 | __sbit __at (0xC0+7) P47; 77 | __sfr __at (0xC8) P5;//xxxx,1111 端口5 78 | __sbit __at (0xC8+0) P50; 79 | __sbit __at (0xC8+1) P51; 80 | __sbit __at (0xC8+2) P52; 81 | __sbit __at (0xC8+3) P53; 82 | __sbit __at (0xC8+4) P54; 83 | __sbit __at (0xC8+5) P55; 84 | __sbit __at (0xC8+6) P56; 85 | __sbit __at (0xC8+7) P57; 86 | __sfr __at (0xE8) P6;//0000,0000 端口6 87 | __sbit __at (0xE8+0) P60; 88 | __sbit __at (0xE8+1) P61; 89 | __sbit __at (0xE8+2) P62; 90 | __sbit __at (0xE8+3) P63; 91 | __sbit __at (0xE8+4) P64; 92 | __sbit __at (0xE8+5) P65; 93 | __sbit __at (0xE8+6) P66; 94 | __sbit __at (0xE8+7) P67; 95 | __sfr __at (0xF8) P7;//0000,0000 端口7 96 | __sbit __at (0xF8+0) P70; 97 | __sbit __at (0xF8+1) P71; 98 | __sbit __at (0xF8+2) P72; 99 | __sbit __at (0xF8+3) P73; 100 | __sbit __at (0xF8+4) P74; 101 | __sbit __at (0xF8+5) P75; 102 | __sbit __at (0xF8+6) P76; 103 | __sbit __at (0xF8+7) P77; 104 | __sfr __at (0x94) P0M0;//0000,0000 端口0模式寄存器0 105 | __sfr __at (0x93) P0M1;//0000,0000 端口0模式寄存器1 106 | __sfr __at (0x92) P1M0;//0000,0000 端口1模式寄存器0 107 | __sfr __at (0x91) P1M1;//0000,0000 端口1模式寄存器1 108 | __sfr __at (0x96) P2M0;//0000,0000 端口2模式寄存器0 109 | __sfr __at (0x95) P2M1;//0000,0000 端口2模式寄存器1 110 | __sfr __at (0xB2) P3M0;//0000,0000 端口3模式寄存器0 111 | __sfr __at (0xB1) P3M1;//0000,0000 端口3模式寄存器1 112 | __sfr __at (0xB4) P4M0;//0000,0000 端口4模式寄存器0 113 | __sfr __at (0xB3) P4M1;//0000,0000 端口4模式寄存器1 114 | __sfr __at (0xCA) P5M0;//0000,0000 端口5模式寄存器0 115 | __sfr __at (0xC9) P5M1;//0000,0000 端口5模式寄存器1 116 | __sfr __at (0xCC) P6M0;//0000,0000 端口6模式寄存器0 117 | __sfr __at (0xCB) P6M1;//0000,0000 端口6模式寄存器1 118 | __sfr __at (0xE2) P7M0;//0000,0000 端口7模式寄存器0 119 | __sfr __at (0xE1) P7M1;//0000,0000 端口7模式寄存器1 120 | 121 | //系统管理特殊功能寄存器 122 | __sfr __at (0x87) PCON;//0001,0000 电源控制寄存器 123 | __sfr __at (0x8E) AUXR;//0000,0000 辅助寄存器 124 | __sfr __at (0xA2) AUXR1;//0000,0000 辅助寄存器1 125 | __sfr __at (0xA2) P_SW1;//0000,0000 外设端口切换寄存器1 126 | __sfr __at (0x97) CLK_DIV;//0000,0000 时钟分频控制寄存器 127 | __sfr __at (0xA1) BUS_SPEED;//xx10,x011 总线速度控制寄存器 128 | __sfr __at (0x9D) P1ASF;//0000,0000 端口1模拟功能配置寄存器 129 | __sfr __at (0xBA) P_SW2;//0xxx,x000 外设端口切换寄存器 130 | 131 | //中断特殊功能寄存器 132 | __sfr __at (0xA8) IE;//0000,0000 中断控制寄存器 133 | __sbit __at (0xA8+7) EA; 134 | __sbit __at (0xA8+6) ELVD; 135 | __sbit __at (0xA8+5) EADC; 136 | __sbit __at (0xA8+4) ES; 137 | __sbit __at (0xA8+3) ET1; 138 | __sbit __at (0xA8+2) EX1; 139 | __sbit __at (0xA8+1) ET0; 140 | __sbit __at (0xA8+0) EX0; 141 | __sfr __at (0xB8) IP;//0000,0000 中断优先级寄存器 142 | __sbit __at (0xB8+7) PPCA; 143 | __sbit __at (0xB8+6) PLVD; 144 | __sbit __at (0xB8+5) PADC; 145 | __sbit __at (0xB8+4) PS; 146 | __sbit __at (0xB8+3) PT1; 147 | __sbit __at (0xB8+2) PX1; 148 | __sbit __at (0xB8+1) PT0; 149 | __sbit __at (0xB8+0) PX0; 150 | __sfr __at (0xAF) IE2;//0000,0000 中断控制寄存器2 151 | __sfr __at (0xB5) IP2;//xxxx,xx00 中断优先级寄存器2 152 | __sfr __at (0x8F) INT_CLKO;//0000,0000 外部中断与时钟输出控制寄存器 153 | 154 | //定时器特殊功能寄存器 155 | __sfr __at (0x88) TCON;//0000,0000 T0/T1控制寄存器 156 | __sbit __at (0x88+7) TF1; 157 | __sbit __at (0x88+6) TR1; 158 | __sbit __at (0x88+5) TF0; 159 | __sbit __at (0x88+4) TR0; 160 | __sbit __at (0x88+3) IE1; 161 | __sbit __at (0x88+2) IT1; 162 | __sbit __at (0x88+1) IE0; 163 | __sbit __at (0x88+0) IT0; 164 | __sfr __at (0x89) TMOD;//0000,0000 T0/T1模式寄存器 165 | __sfr __at (0x8A) TL0;//0000,0000 T0低字节 166 | __sfr __at (0x8B) TL1;//0000,0000 T1低字节 167 | __sfr __at (0x8C) TH0;//0000,0000 T0高字节 168 | __sfr __at (0x8D) TH1;//0000,0000 T1高字节 169 | __sfr __at (0xD1) T4T3M;//0000,0000 T3/T4模式寄存器 170 | __sfr __at (0xD1) T3T4M;//0000,0000 T3/T4模式寄存器 171 | __sfr __at (0xD2) T4H;//0000,0000 T4高字节 172 | __sfr __at (0xD3) T4L;//0000,0000 T4低字节 173 | __sfr __at (0xD4) T3H;//0000,0000 T3高字节 174 | __sfr __at (0xD5) T3L;//0000,0000 T3低字节 175 | __sfr __at (0xD6) T2H;//0000,0000 T2高字节 176 | __sfr __at (0xD7) T2L;//0000,0000 T2低字节 177 | __sfr __at (0xAA) WKTCL;//0000,0000 掉电唤醒定时器低字节 178 | __sfr __at (0xAB) WKTCH;//0000,0000 掉电唤醒定时器高字节 179 | __sfr __at (0xC1) WDT_CONTR;//0000,0000 看门狗控制寄存器 180 | 181 | //串行口特殊功能寄存器 182 | __sfr __at (0x98) SCON;//0000,0000 串口1控制寄存器 183 | __sbit __at (0x98+7) SM0; 184 | __sbit __at (0x98+6) SM1; 185 | __sbit __at (0x98+5) SM2; 186 | __sbit __at (0x98+4) REN; 187 | __sbit __at (0x98+3) TB8; 188 | __sbit __at (0x98+2) RB8; 189 | __sbit __at (0x98+1) TI; 190 | __sbit __at (0x98+0) RI; 191 | __sfr __at (0x99) SBUF;//xxxx,xxxx 串口1数据寄存器 192 | __sfr __at (0x9A) S2CON;//0000,0000 串口2控制寄存器 193 | __sfr __at (0x9B) S2BUF;//xxxx,xxxx 串口2数据寄存器 194 | __sfr __at (0xAC) S3CON;//0000,0000 串口3控制寄存器 195 | __sfr __at (0xAD) S3BUF;//xxxx,xxxx 串口3数据寄存器 196 | __sfr __at (0x84) S4CON;//0000,0000 串口4控制寄存器 197 | __sfr __at (0x85) S4BUF;//xxxx,xxxx 串口4数据寄存器 198 | __sfr __at (0xA9) SADDR;//0000,0000 从机地址寄存器 199 | __sfr __at (0xB9) SADEN;//0000,0000 从机地址屏蔽寄存器 200 | 201 | //ADC 特殊功能寄存器 202 | __sfr __at (0xBC) ADC_CONTR;//0000,0000 A/D转换控制寄存器 203 | __sfr __at (0xBD) ADC_RES;//0000,0000 A/D转换结果高8位 204 | __sfr __at (0xBE) ADC_RESL;//0000,0000 A/D转换结果低2位 205 | 206 | //SPI 特殊功能寄存器 207 | __sfr __at (0xCD) SPSTAT;//00xx,xxxx SPI状态寄存器 208 | __sfr __at (0xCE) SPCTL;//0000,0100 SPI控制寄存器 209 | __sfr __at (0xCF) SPDAT;//0000,0000 SPI数据寄存器 210 | 211 | //IAP/ISP 特殊功能寄存器 212 | __sfr __at (0xC2) IAP_DATA;//0000,0000 EEPROM数据寄存器 213 | __sfr __at (0xC3) IAP_ADDRH;//0000,0000 EEPROM地址高字节 214 | __sfr __at (0xC4) IAP_ADDRL;//0000,0000 EEPROM地址第字节 215 | __sfr __at (0xC5) IAP_CMD;//xxxx,xx00 EEPROM命令寄存器 216 | __sfr __at (0xC6) IAP_TRIG;//0000,0000 EEPRPM命令触发寄存器 217 | __sfr __at (0xC7) IAP_CONTR;//0000,x000 EEPROM控制寄存器 218 | 219 | //PCA/PWM 特殊功能寄存器 220 | __sfr __at (0xD8) CCON;//00xx,xx00 PCA控制寄存器 221 | __sbit __at (0xD8+7) CF; 222 | __sbit __at (0xD8+6) CR; 223 | __sbit __at (0xD8+2) CCF2; 224 | __sbit __at (0xD8+1) CCF1; 225 | __sbit __at (0xD8+0) CCF0; 226 | __sfr __at (0xD9) CMOD;//0xxx,x000 PCA 工作模式寄存器 227 | __sfr __at (0xE9) CL;//0000,0000 PCA计数器低字节 228 | __sfr __at (0xF9) CH;//0000,0000 PCA计数器高字节 229 | __sfr __at (0xDA) CCAPM0;//0000,0000 PCA模块0的PWM寄存器 230 | __sfr __at (0xDB) CCAPM1;//0000,0000 PCA模块1的PWM寄存器 231 | __sfr __at (0xDC) CCAPM2;//0000,0000 PCA模块2的PWM 寄存器 232 | __sfr __at (0xEA) CCAP0L;//0000,0000 PCA模块0的捕捉/比较寄存器低字节 233 | __sfr __at (0xEB) CCAP1L;//0000,0000 PCA模块1的捕捉/比较寄存器低字节 234 | __sfr __at (0xEC) CCAP2L;//0000,0000 PCA模块2的捕捉/比较寄存器低字节 235 | __sfr __at (0xF2) PCA_PWM0;//xxxx,xx00 PCA模块0的PWM寄存器 236 | __sfr __at (0xF3) PCA_PWM1;//xxxx,xx00 PCA模块1的PWM寄存器 237 | __sfr __at (0xF4) PCA_PWM2;//xxxx,xx00 PCA模块1的PWM寄存器 238 | __sfr __at (0xFA) CCAP0H;//0000,0000 PCA模块0的捕捉/比较寄存器高字节 239 | __sfr __at (0xFB) CCAP1H;//0000,0000 PCA模块1的捕捉/比较寄存器高字节 240 | __sfr __at (0xFC) CCAP2H;//0000,0000 PCA模块2的捕捉/比较寄存器高字节 241 | 242 | //比较器特殊功能寄存器 243 | __sfr __at (0xE6) CMPCR1;//0000,0000 比较器控制寄存器1 244 | __sfr __at (0xE7) CMPCR2;//0000,0000 比较器控制寄存器2 245 | 246 | //增强型PWM波形发生器特殊功能寄存器 247 | __sfr __at (0xf1) PWMCFG;//x000,0000 PWM配置寄存器 248 | __sfr __at (0xf5) PWMCR;//0000,0000 PWM控制寄存器 249 | __sfr __at (0xf6) PWMIF;//x000,0000 PWM中断标志寄存器 250 | __sfr __at (0xf7) PWMFDCR;//xx00,0000 PWM外部异常检测控制寄存器 251 | 252 | //如下特殊功能寄存器位于扩展RAM区域 253 | //访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 254 | #define PWMC (*(unsigned int volatile __xdata *)0xfff0) 255 | #define PWMCH (*(unsigned char volatile __xdata *)0xfff0) 256 | #define PWMCL (*(unsigned char volatile __xdata *)0xfff1) 257 | #define PWMCKS (*(unsigned char volatile __xdata *)0xfff2) 258 | #define PWM2T1 (*(unsigned int volatile __xdata *)0xff00) 259 | #define PWM2T1H (*(unsigned char volatile __xdata *)0xff00) 260 | #define PWM2T1L (*(unsigned char volatile __xdata *)0xff01) 261 | #define PWM2T2 (*(unsigned int volatile __xdata *)0xff02) 262 | #define PWM2T2H (*(unsigned char volatile __xdata *)0xff02) 263 | #define PWM2T2L (*(unsigned char volatile __xdata *)0xff03) 264 | #define PWM2CR (*(unsigned char volatile __xdata *)0xff04) 265 | #define PWM3T1 (*(unsigned int volatile __xdata *)0xff10) 266 | #define PWM3T1H (*(unsigned char volatile __xdata *)0xff10) 267 | #define PWM3T1L (*(unsigned char volatile __xdata *)0xff11) 268 | #define PWM3T2 (*(unsigned int volatile __xdata *)0xff12) 269 | #define PWM3T2H (*(unsigned char volatile __xdata *)0xff12) 270 | #define PWM3T2L (*(unsigned char volatile __xdata *)0xff13) 271 | #define PWM3CR (*(unsigned char volatile __xdata *)0xff14) 272 | #define PWM4T1 (*(unsigned int volatile __xdata *)0xff20) 273 | #define PWM4T1H (*(unsigned char volatile __xdata *)0xff20) 274 | #define PWM4T1L (*(unsigned char volatile __xdata *)0xff21) 275 | #define PWM4T2 (*(unsigned int volatile __xdata *)0xff22) 276 | #define PWM4T2H (*(unsigned char volatile __xdata *)0xff22) 277 | #define PWM4T2L (*(unsigned char volatile __xdata *)0xff23) 278 | #define PWM4CR (*(unsigned char volatile __xdata *)0xff24) 279 | #define PWM5T1 (*(unsigned int volatile __xdata *)0xff30) 280 | #define PWM5T1H (*(unsigned char volatile __xdata *)0xff30) 281 | #define PWM5T1L (*(unsigned char volatile __xdata *)0xff31) 282 | #define PWM5T2 (*(unsigned int volatile __xdata *)0xff32) 283 | #define PWM5T2H (*(unsigned char volatile __xdata *)0xff32) 284 | #define PWM5T2L (*(unsigned char volatile __xdata *)0xff33) 285 | #define PWM5CR (*(unsigned char volatile __xdata *)0xff34) 286 | #define PWM6T1 (*(unsigned int volatile __xdata *)0xff40) 287 | #define PWM6T1H (*(unsigned char volatile __xdata *)0xff40) 288 | #define PWM6T1L (*(unsigned char volatile __xdata *)0xff41) 289 | #define PWM6T2 (*(unsigned int volatile __xdata *)0xff42) 290 | #define PWM6T2H (*(unsigned char volatile __xdata *)0xff42) 291 | #define PWM6T2L (*(unsigned char volatile __xdata *)0xff43) 292 | #define PWM6CR (*(unsigned char volatile __xdata *)0xff44) 293 | #define PWM7T1 (*(unsigned int volatile __xdata *)0xff50) 294 | #define PWM7T1H (*(unsigned char volatile __xdata *)0xff50) 295 | #define PWM7T1L (*(unsigned char volatile __xdata *)0xff51) 296 | #define PWM7T2 (*(unsigned int volatile __xdata *)0xff52) 297 | #define PWM7T2H (*(unsigned char volatile __xdata *)0xff52) 298 | #define PWM7T2L (*(unsigned char volatile __xdata *)0xff53) 299 | #define PWM7CR (*(unsigned char volatile __xdata *)0xff54) 300 | 301 | ///////////////////////////////////////////////// 302 | 303 | #endif 304 | 305 | -------------------------------------------------------------------------------- /headers/stc51.h: -------------------------------------------------------------------------------- 1 | #ifndef _STC51_H 2 | #define _STC51_H 3 | typedef unsigned char uint8; 4 | typedef unsigned short uint16; 5 | typedef unsigned int uint32; 6 | typedef __bit bit; 7 | typedef _Bool bool; 8 | 9 | #if defined(STC89) || defined(STC90) 10 | #include 11 | #elif defined(STC90AD) 12 | #include 13 | #elif defined(STC10) || defined(STC11) || defined(STC12C52) || defined(STC12C5A) 14 | #include 15 | #elif defined(STC12C20) 16 | #include 17 | #elif defined(STC12C54) || defined(STC12C56) 18 | #include 19 | #elif defined(STC12H) 20 | #include 21 | #elif defined(STC15F104E) || defined(STC15F204EA) 22 | #include 23 | #elif defined(STC15) 24 | #include 25 | #elif defined(STC8A) || defined(STC8F) 26 | #include 27 | #elif defined(STC8C) 28 | #include 29 | #elif defined(STC8G) 30 | #include 31 | #elif defined(STC8H) 32 | #include 33 | #elif defined(STC8A8K64D4) 34 | #include 35 | #else /* by default, include the earliest stc89/90 series header */ 36 | #include 37 | #endif 38 | 39 | #endif /* _STC51_H */ 40 | -------------------------------------------------------------------------------- /headers/stc89xx.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC89C5xRC_RDP_H__ 2 | #define __STC89C5xRC_RDP_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | /* The following is STC additional SFR */ 7 | 8 | /* sfr AUXR = 0x8e; */ 9 | /* sfr AUXR1 = 0xa2; */ 10 | /* sfr IPH = 0xb7; */ 11 | 12 | __sfr __at (0xe8) P4; 13 | __sbit __at (0xe8+6) P46; 14 | __sbit __at (0xe8+5) P45;//ISP下载需勾选"ALE脚用作P4.5口" 15 | __sbit __at (0xe8+4) P44; 16 | __sbit __at (0xe8+3) P43; 17 | __sbit __at (0xe8+2) P42; 18 | __sbit __at (0xe8+1) P41; 19 | __sbit __at (0xe8+0) P40; 20 | 21 | __sfr __at (0xc0) XICON; 22 | 23 | __sfr __at (0xe1) WDT_CONTR; 24 | 25 | __sfr __at (0xe2) ISP_DATA; 26 | __sfr __at (0xe3) ISP_ADDRH; 27 | __sfr __at (0xe4) ISP_ADDRL; 28 | __sfr __at (0xe5) ISP_CMD; 29 | __sfr __at (0xe6) ISP_TRIG; 30 | __sfr __at (0xe7) ISP_CONTR; 31 | 32 | /* Above is STC additional SFR */ 33 | 34 | /*-------------------------------------------------------------------------- 35 | REG51F.H 36 | 37 | Header file for 8xC31/51, 80C51Fx, 80C51Rx+ 38 | Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. 39 | All rights reserved. 40 | 41 | Modification according to DataSheet from April 1999 42 | - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives 43 | --------------------------------------------------------------------------*/ 44 | 45 | /* BYTE Registers */ 46 | __sfr __at (0x80) P0; 47 | __sbit __at (0x80+0) P00; 48 | __sbit __at (0x80+1) P01; 49 | __sbit __at (0x80+2) P02; 50 | __sbit __at (0x80+3) P03; 51 | __sbit __at (0x80+4) P04; 52 | __sbit __at (0x80+5) P05; 53 | __sbit __at (0x80+6) P06; 54 | __sbit __at (0x80+7) P07; 55 | __sfr __at (0x90) P1; 56 | __sbit __at (0x90+0) P10; 57 | __sbit __at (0x90+1) P11; 58 | __sbit __at (0x90+2) P12; 59 | __sbit __at (0x90+3) P13; 60 | __sbit __at (0x90+4) P14; 61 | __sbit __at (0x90+5) P15; 62 | __sbit __at (0x90+6) P16; 63 | __sbit __at (0x90+7) P17; 64 | __sfr __at (0xA0) P2; 65 | __sbit __at (0xA0+0) P20; 66 | __sbit __at (0xA0+1) P21; 67 | __sbit __at (0xA0+2) P22; 68 | __sbit __at (0xA0+3) P23; 69 | __sbit __at (0xA0+4) P24; 70 | __sbit __at (0xA0+5) P25; 71 | __sbit __at (0xA0+6) P26; 72 | __sbit __at (0xA0+7) P27; 73 | __sfr __at (0xB0) P3; 74 | __sbit __at (0xB0+0) P30; 75 | __sbit __at (0xB0+1) P31; 76 | __sbit __at (0xB0+2) P32; 77 | __sbit __at (0xB0+3) P33; 78 | __sbit __at (0xB0+4) P34; 79 | __sbit __at (0xB0+5) P35; 80 | __sbit __at (0xB0+6) P36; 81 | __sbit __at (0xB0+7) P37; 82 | __sfr __at (0xD0) PSW; 83 | __sfr __at (0xE0) ACC; 84 | __sfr __at (0xF0) B; 85 | __sfr __at (0x81) SP; 86 | __sfr __at (0x82) DPL; 87 | __sfr __at (0x83) DPH; 88 | __sfr __at (0x87) PCON; 89 | __sfr __at (0x88) TCON; 90 | __sfr __at (0x89) TMOD; 91 | __sfr __at (0x8A) TL0; 92 | __sfr __at (0x8B) TL1; 93 | __sfr __at (0x8C) TH0; 94 | __sfr __at (0x8D) TH1; 95 | __sfr __at (0xA8) IE; 96 | __sfr __at (0xB8) IP; 97 | __sfr __at (0x98) SCON; 98 | __sfr __at (0x99) SBUF; 99 | 100 | /* 80C51Fx/Rx Extensions */ 101 | __sfr __at (0x8E) AUXR; 102 | __sfr __at (0xA2) AUXR1; 103 | __sfr __at (0xA9) SADDR; 104 | __sfr __at (0xB7) IPH; 105 | __sfr __at (0xB9) SADEN; 106 | __sfr __at (0xC8) T2CON; 107 | __sfr __at (0xC9) T2MOD; 108 | __sfr __at (0xCA) RCAP2L; 109 | __sfr __at (0xCB) RCAP2H; 110 | __sfr __at (0xCC) TL2; 111 | __sfr __at (0xCD) TH2; 112 | 113 | /* PCA SFR 114 | sfr CCON = 0xD8; 115 | sfr CMOD = 0xD9; 116 | sfr CCAPM0 = 0xDA; 117 | sfr CCAPM1 = 0xDB; 118 | sfr CCAPM2 = 0xDC; 119 | sfr CCAPM3 = 0xDD; 120 | sfr CCAPM4 = 0xDE; 121 | sfr CL = 0xE9; 122 | sfr CCAP0L = 0xEA; 123 | sfr CCAP1L = 0xEB; 124 | sfr CCAP2L = 0xEC; 125 | sfr CCAP3L = 0xED; 126 | sfr CCAP4L = 0xEE; 127 | sfr CH = 0xF9; 128 | sfr CCAP0H = 0xFA; 129 | sfr CCAP1H = 0xFB; 130 | sfr CCAP2H = 0xFC; 131 | sfr CCAP3H = 0xFD; 132 | sfr CCAP4H = 0xFE; 133 | */ 134 | 135 | /* BIT Registers */ 136 | /* PSW */ 137 | __sbit __at (0xD0+7) CY; 138 | __sbit __at (0xD0+6) AC; 139 | __sbit __at (0xD0+5) F0; 140 | __sbit __at (0xD0+4) RS1; 141 | __sbit __at (0xD0+3) RS0; 142 | __sbit __at (0xD0+2) OV; 143 | __sbit __at (0xD0+1) F1; 144 | __sbit __at (0xD0+0) P; 145 | 146 | /* TCON */ 147 | __sbit __at (0x88+7) TF1; 148 | __sbit __at (0x88+6) TR1; 149 | __sbit __at (0x88+5) TF0; 150 | __sbit __at (0x88+4) TR0; 151 | __sbit __at (0x88+3) IE1; 152 | __sbit __at (0x88+2) IT1; 153 | __sbit __at (0x88+1) IE0; 154 | __sbit __at (0x88+0) IT0; 155 | 156 | /* IE */ 157 | __sbit __at (0xA8+7) EA; 158 | __sbit __at (0xA8+6) EC; 159 | __sbit __at (0xA8+5) ET2; 160 | __sbit __at (0xA8+4) ES; 161 | __sbit __at (0xA8+3) ET1; 162 | __sbit __at (0xA8+2) EX1; 163 | __sbit __at (0xA8+1) ET0; 164 | __sbit __at (0xA8+0) EX0; 165 | 166 | /* IP */ 167 | /* sbit PPC = IP^6;*/ 168 | __sbit __at (0xB8+5) PT2; 169 | __sbit __at (0xB8+4) PS; 170 | __sbit __at (0xB8+3) PT1; 171 | __sbit __at (0xB8+2) PX1; 172 | __sbit __at (0xB8+1) PT0; 173 | __sbit __at (0xB8+0) PX0; 174 | 175 | /* P3 */ 176 | __sbit __at (0xB0+7) RD; 177 | __sbit __at (0xB0+6) WR; 178 | __sbit __at (0xB0+5) T1; 179 | __sbit __at (0xB0+4) T0; 180 | __sbit __at (0xB0+3) INT1; 181 | __sbit __at (0xB0+2) INT0; 182 | __sbit __at (0xB0+1) TXD; 183 | __sbit __at (0xB0+0) RXD; 184 | 185 | /* SCON */ 186 | __sbit __at (0x98+7) SM0;// alternatively "FE" 187 | __sbit __at (0x98+7) FE; 188 | __sbit __at (0x98+6) SM1; 189 | __sbit __at (0x98+5) SM2; 190 | __sbit __at (0x98+4) REN; 191 | __sbit __at (0x98+3) TB8; 192 | __sbit __at (0x98+2) RB8; 193 | __sbit __at (0x98+1) TI; 194 | __sbit __at (0x98+0) RI; 195 | 196 | /* P1 */ 197 | /* PCA 198 | sbit CEX4 = P1^7; 199 | sbit CEX3 = P1^6; 200 | sbit CEX2 = P1^5; 201 | sbit CEX1 = P1^4; 202 | sbit CEX0 = P1^3; 203 | sbit ECI = P1^2; 204 | */ 205 | 206 | __sbit __at (0x90+1) T2EX; 207 | __sbit __at (0x90+0) T2; 208 | 209 | /* T2CON */ 210 | __sbit __at (0xC8+7) TF2; 211 | __sbit __at (0xC8+6) EXF2; 212 | __sbit __at (0xC8+5) RCLK; 213 | __sbit __at (0xC8+4) TCLK; 214 | __sbit __at (0xC8+3) EXEN2; 215 | __sbit __at (0xC8+2) TR2; 216 | __sbit __at (0xC8+1) C_T2; 217 | __sbit __at (0xC8+0) CP_RL2; 218 | 219 | /* CCON */ 220 | /* PCA 221 | sbit CF = CCON^7; 222 | sbit CR = CCON^6; 223 | 224 | sbit CCF4 = CCON^4; 225 | sbit CCF3 = CCON^3; 226 | sbit CCF2 = CCON^2; 227 | sbit CCF1 = CCON^1; 228 | sbit CCF0 = CCON^0; 229 | */ 230 | 231 | ///////////////////////////////////////////////// 232 | 233 | #endif 234 | 235 | -------------------------------------------------------------------------------- /headers/stc8cxx.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC8C_H__ 2 | #define __STC8C_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | //包含本头文件后,不用另外再包含"REG51.H" 7 | 8 | __sfr __at (0x80) P0; 9 | __sbit __at (0x80+0) P00; 10 | __sbit __at (0x80+1) P01; 11 | __sbit __at (0x80+2) P02; 12 | __sbit __at (0x80+3) P03; 13 | __sbit __at (0x80+4) P04; 14 | __sbit __at (0x80+5) P05; 15 | __sbit __at (0x80+6) P06; 16 | __sbit __at (0x80+7) P07; 17 | __sfr __at (0x81) SP; 18 | __sfr __at (0x82) DPL; 19 | __sfr __at (0x83) DPH; 20 | __sfr __at (0x87) PCON; 21 | __sfr __at (0x88) TCON; 22 | __sbit __at (0x88+7) TF1; 23 | __sbit __at (0x88+6) TR1; 24 | __sbit __at (0x88+5) TF0; 25 | __sbit __at (0x88+4) TR0; 26 | __sbit __at (0x88+3) IE1; 27 | __sbit __at (0x88+2) IT1; 28 | __sbit __at (0x88+1) IE0; 29 | __sbit __at (0x88+0) IT0; 30 | __sfr __at (0x89) TMOD; 31 | __sfr __at (0x8A) TL0; 32 | __sfr __at (0x8B) TL1; 33 | __sfr __at (0x8C) TH0; 34 | __sfr __at (0x8D) TH1; 35 | __sfr __at (0x8E) AUXR; 36 | __sfr __at (0x8F) INTCLKO; 37 | __sfr __at (0x90) P1; 38 | __sbit __at (0x90+0) P10; 39 | __sbit __at (0x90+1) P11; 40 | __sbit __at (0x90+2) P12; 41 | __sbit __at (0x90+3) P13; 42 | __sbit __at (0x90+4) P14; 43 | __sbit __at (0x90+5) P15; 44 | __sbit __at (0x90+6) P16; 45 | __sbit __at (0x90+7) P17; 46 | __sfr __at (0x91) P1M1; 47 | __sfr __at (0x92) P1M0; 48 | __sfr __at (0x93) P0M1; 49 | __sfr __at (0x94) P0M0; 50 | __sfr __at (0x95) P2M1; 51 | __sfr __at (0x96) P2M0; 52 | __sfr __at (0x98) SCON; 53 | __sbit __at (0x98+7) SM0; 54 | __sbit __at (0x98+6) SM1; 55 | __sbit __at (0x98+5) SM2; 56 | __sbit __at (0x98+4) REN; 57 | __sbit __at (0x98+3) TB8; 58 | __sbit __at (0x98+2) RB8; 59 | __sbit __at (0x98+1) TI; 60 | __sbit __at (0x98+0) RI; 61 | __sfr __at (0x99) SBUF; 62 | __sfr __at (0x9A) S2CON; 63 | __sfr __at (0x9B) S2BUF; 64 | __sfr __at (0x9D) IRCBAND; 65 | __sfr __at (0x9E) LIRTRIM; 66 | __sfr __at (0x9F) IRTRIM; 67 | __sfr __at (0xA0) P2; 68 | __sbit __at (0xA0+0) P20; 69 | __sbit __at (0xA0+1) P21; 70 | __sbit __at (0xA0+2) P22; 71 | __sbit __at (0xA0+3) P23; 72 | __sbit __at (0xA0+4) P24; 73 | __sbit __at (0xA0+5) P25; 74 | __sbit __at (0xA0+6) P26; 75 | __sbit __at (0xA0+7) P27; 76 | __sfr __at (0xA1) BUS_SPEED; 77 | __sfr __at (0xA2) P_SW1; 78 | __sfr __at (0xA8) IE; 79 | __sbit __at (0xA8+7) EA; 80 | __sbit __at (0xA8+6) ELVD; 81 | __sbit __at (0xA8+5) EADC; 82 | __sbit __at (0xA8+4) ES; 83 | __sbit __at (0xA8+3) ET1; 84 | __sbit __at (0xA8+2) EX1; 85 | __sbit __at (0xA8+1) ET0; 86 | __sbit __at (0xA8+0) EX0; 87 | __sfr __at (0xA9) SADDR; 88 | __sfr __at (0xAA) WKTCL; 89 | __sfr __at (0xAB) WKTCH; 90 | __sfr __at (0xAE) TA; 91 | __sfr __at (0xAF) IE2; 92 | __sfr __at (0xB0) P3; 93 | __sbit __at (0xB0+0) P30; 94 | __sbit __at (0xB0+1) P31; 95 | __sbit __at (0xB0+2) P32; 96 | __sbit __at (0xB0+3) P33; 97 | __sbit __at (0xB0+4) P34; 98 | __sbit __at (0xB0+5) P35; 99 | __sbit __at (0xB0+6) P36; 100 | __sbit __at (0xB0+7) P37; 101 | __sfr __at (0xB1) P3M1; 102 | __sfr __at (0xB2) P3M0; 103 | __sfr __at (0xB3) P4M1; 104 | __sfr __at (0xB4) P4M0; 105 | __sfr __at (0xB5) IP2; 106 | __sfr __at (0xB6) IP2H; 107 | __sfr __at (0xB7) IPH; 108 | __sfr __at (0xB8) IP; 109 | __sbit __at (0xB8+6) PLVD; 110 | __sbit __at (0xB8+4) PS; 111 | __sbit __at (0xB8+3) PT1; 112 | __sbit __at (0xB8+2) PX1; 113 | __sbit __at (0xB8+1) PT0; 114 | __sbit __at (0xB8+0) PX0; 115 | __sfr __at (0xB9) SADEN; 116 | __sfr __at (0xBA) P_SW2; 117 | __sfr __at (0xC0) P4; 118 | __sbit __at (0xC0+0) P40; 119 | __sbit __at (0xC0+1) P41; 120 | __sbit __at (0xC0+2) P42; 121 | __sbit __at (0xC0+3) P43; 122 | __sbit __at (0xC0+4) P44; 123 | __sbit __at (0xC0+5) P45; 124 | __sbit __at (0xC0+6) P46; 125 | __sbit __at (0xC0+7) P47; 126 | __sfr __at (0xC1) WDT_CONTR; 127 | __sfr __at (0xC2) IAP_DATA; 128 | __sfr __at (0xC3) IAP_ADDRH; 129 | __sfr __at (0xC4) IAP_ADDRL; 130 | __sfr __at (0xC5) IAP_CMD; 131 | __sfr __at (0xC6) IAP_TRIG; 132 | __sfr __at (0xC7) IAP_CONTR; 133 | __sfr __at (0xC8) P5; 134 | __sbit __at (0xC8+0) P50; 135 | __sbit __at (0xC8+1) P51; 136 | __sbit __at (0xC8+2) P52; 137 | __sbit __at (0xC8+3) P53; 138 | __sbit __at (0xC8+4) P54; 139 | __sbit __at (0xC8+5) P55; 140 | __sbit __at (0xC8+6) P56; 141 | __sbit __at (0xC8+7) P57; 142 | __sfr __at (0xC9) P5M1; 143 | __sfr __at (0xCA) P5M0; 144 | __sfr __at (0xCD) SPSTAT; 145 | __sfr __at (0xCE) SPCTL; 146 | __sfr __at (0xCF) SPDAT; 147 | __sfr __at (0xD0) PSW; 148 | __sbit __at (0xD0+7) CY; 149 | __sbit __at (0xD0+6) AC; 150 | __sbit __at (0xD0+5) F0; 151 | __sbit __at (0xD0+4) RS1; 152 | __sbit __at (0xD0+3) RS0; 153 | __sbit __at (0xD0+2) OV; 154 | __sbit __at (0xD0+1) F1; 155 | __sbit __at (0xD0+0) P; 156 | __sfr __at (0xD1) T4T3M; 157 | __sfr __at (0xD2) T4H; 158 | __sfr __at (0xD3) T4L; 159 | __sfr __at (0xD4) T3H; 160 | __sfr __at (0xD5) T3L; 161 | __sfr __at (0xD6) T2H; 162 | __sfr __at (0xDF) IP3; 163 | __sfr __at (0xE0) ACC; 164 | __sfr __at (0xE3) DPS; 165 | __sfr __at (0xE4) DPL1; 166 | __sfr __at (0xE5) DPH1; 167 | __sfr __at (0xE6) CMPCR1; 168 | __sfr __at (0xE7) CMPCR2; 169 | __sfr __at (0xEE) IP3H; 170 | __sfr __at (0xEF) AUXINTIF; 171 | __sfr __at (0xF0) B; 172 | __sfr __at (0xF5) IAP_TPS; 173 | __sfr __at (0xFF) RSTCFG; 174 | 175 | //如下特殊功能寄存器位于扩展RAM区域 176 | //访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 177 | 178 | ///////////////////////////////////////////////// 179 | //FF00H-FFFFH 180 | ///////////////////////////////////////////////// 181 | 182 | 183 | ///////////////////////////////////////////////// 184 | //FE00H-FEFFH 185 | ///////////////////////////////////////////////// 186 | 187 | #define CKSEL (*(unsigned char volatile __xdata *)0xfe00) 188 | #define CLKDIV (*(unsigned char volatile __xdata *)0xfe01) 189 | #define HIRCCR (*(unsigned char volatile __xdata *)0xfe02) 190 | #define XOSCCR (*(unsigned char volatile __xdata *)0xfe03) 191 | #define IRC32KCR (*(unsigned char volatile __xdata *)0xfe04) 192 | #define MCLKOCR (*(unsigned char volatile __xdata *)0xfe05) 193 | #define IRCDB (*(unsigned char volatile __xdata *)0xfe06) 194 | 195 | #define P0PU (*(unsigned char volatile __xdata *)0xfe10) 196 | #define P1PU (*(unsigned char volatile __xdata *)0xfe11) 197 | #define P2PU (*(unsigned char volatile __xdata *)0xfe12) 198 | #define P3PU (*(unsigned char volatile __xdata *)0xfe13) 199 | #define P4PU (*(unsigned char volatile __xdata *)0xfe14) 200 | #define P5PU (*(unsigned char volatile __xdata *)0xfe15) 201 | #define P0NCS (*(unsigned char volatile __xdata *)0xfe18) 202 | #define P1NCS (*(unsigned char volatile __xdata *)0xfe19) 203 | #define P2NCS (*(unsigned char volatile __xdata *)0xfe1a) 204 | #define P3NCS (*(unsigned char volatile __xdata *)0xfe1b) 205 | #define P4NCS (*(unsigned char volatile __xdata *)0xfe1c) 206 | #define P5NCS (*(unsigned char volatile __xdata *)0xfe1d) 207 | #define P0SR (*(unsigned char volatile __xdata *)0xfe20) 208 | #define P1SR (*(unsigned char volatile __xdata *)0xfe21) 209 | #define P2SR (*(unsigned char volatile __xdata *)0xfe22) 210 | #define P3SR (*(unsigned char volatile __xdata *)0xfe23) 211 | #define P4SR (*(unsigned char volatile __xdata *)0xfe24) 212 | #define P5SR (*(unsigned char volatile __xdata *)0xfe25) 213 | #define P0DR (*(unsigned char volatile __xdata *)0xfe28) 214 | #define P1DR (*(unsigned char volatile __xdata *)0xfe29) 215 | #define P2DR (*(unsigned char volatile __xdata *)0xfe2a) 216 | #define P3DR (*(unsigned char volatile __xdata *)0xfe2b) 217 | #define P4DR (*(unsigned char volatile __xdata *)0xfe2c) 218 | #define P5DR (*(unsigned char volatile __xdata *)0xfe2d) 219 | #define P0IE (*(unsigned char volatile __xdata *)0xfe30) 220 | #define P1IE (*(unsigned char volatile __xdata *)0xfe31) 221 | 222 | #define I2CCFG (*(unsigned char volatile __xdata *)0xfe80) 223 | #define I2CMSCR (*(unsigned char volatile __xdata *)0xfe81) 224 | #define I2CMSST (*(unsigned char volatile __xdata *)0xfe82) 225 | #define I2CSLCR (*(unsigned char volatile __xdata *)0xfe83) 226 | #define I2CSLST (*(unsigned char volatile __xdata *)0xfe84) 227 | #define I2CSLADR (*(unsigned char volatile __xdata *)0xfe85) 228 | #define I2CTXD (*(unsigned char volatile __xdata *)0xfe86) 229 | #define I2CRXD (*(unsigned char volatile __xdata *)0xfe87) 230 | #define I2CMSAUX (*(unsigned char volatile __xdata *)0xfe88) 231 | 232 | #define TM2PS (*(unsigned char volatile __xdata *)0xfea2) 233 | #define TM3PS (*(unsigned char volatile __xdata *)0xfea3) 234 | #define TM4PS (*(unsigned char volatile __xdata *)0xfea4) 235 | 236 | ///////////////////////////////////////////////// 237 | //FD00H-FDFFH 238 | ///////////////////////////////////////////////// 239 | 240 | #define P0INTE (*(unsigned char volatile __xdata *)0xfd00) 241 | #define P1INTE (*(unsigned char volatile __xdata *)0xfd01) 242 | #define P2INTE (*(unsigned char volatile __xdata *)0xfd02) 243 | #define P3INTE (*(unsigned char volatile __xdata *)0xfd03) 244 | #define P4INTE (*(unsigned char volatile __xdata *)0xfd04) 245 | #define P5INTE (*(unsigned char volatile __xdata *)0xfd05) 246 | #define P0INTF (*(unsigned char volatile __xdata *)0xfd10) 247 | #define P1INTF (*(unsigned char volatile __xdata *)0xfd11) 248 | #define P2INTF (*(unsigned char volatile __xdata *)0xfd12) 249 | #define P3INTF (*(unsigned char volatile __xdata *)0xfd13) 250 | #define P4INTF (*(unsigned char volatile __xdata *)0xfd14) 251 | #define P5INTF (*(unsigned char volatile __xdata *)0xfd15) 252 | #define P0IM0 (*(unsigned char volatile __xdata *)0xfd20) 253 | #define P1IM0 (*(unsigned char volatile __xdata *)0xfd21) 254 | #define P2IM0 (*(unsigned char volatile __xdata *)0xfd22) 255 | #define P3IM0 (*(unsigned char volatile __xdata *)0xfd23) 256 | #define P4IM0 (*(unsigned char volatile __xdata *)0xfd24) 257 | #define P5IM0 (*(unsigned char volatile __xdata *)0xfd25) 258 | #define P0IM1 (*(unsigned char volatile __xdata *)0xfd30) 259 | #define P1IM1 (*(unsigned char volatile __xdata *)0xfd31) 260 | #define P2IM1 (*(unsigned char volatile __xdata *)0xfd32) 261 | #define P3IM1 (*(unsigned char volatile __xdata *)0xfd33) 262 | #define P4IM1 (*(unsigned char volatile __xdata *)0xfd34) 263 | #define P5IM1 (*(unsigned char volatile __xdata *)0xfd35) 264 | 265 | ///////////////////////////////////////////////// 266 | //FC00H-FCFFH 267 | ///////////////////////////////////////////////// 268 | 269 | #define MD3 (*(unsigned char volatile __xdata *)0xfcf0) 270 | #define MD2 (*(unsigned char volatile __xdata *)0xfcf1) 271 | #define MD1 (*(unsigned char volatile __xdata *)0xfcf2) 272 | #define MD0 (*(unsigned char volatile __xdata *)0xfcf3) 273 | #define MD5 (*(unsigned char volatile __xdata *)0xfcf4) 274 | #define MD4 (*(unsigned char volatile __xdata *)0xfcf5) 275 | #define ARCON (*(unsigned char volatile __xdata *)0xfcf6) 276 | #define OPCON (*(unsigned char volatile __xdata *)0xfcf7) 277 | 278 | ///////////////////////////////////////////////// 279 | //FB00H-FBFFH 280 | ///////////////////////////////////////////////// 281 | 282 | 283 | ///////////////////////////////////////////////// 284 | //FA00H-FAFFH 285 | ///////////////////////////////////////////////// 286 | 287 | 288 | ///////////////////////////////////////////////// 289 | 290 | #endif 291 | 292 | -------------------------------------------------------------------------------- /headers/stc90c5xad.h: -------------------------------------------------------------------------------- 1 | #ifndef __STC90C5xAD_H__ 2 | #define __STC90C5xAD_H__ 3 | 4 | ///////////////////////////////////////////////// 5 | 6 | /* The following is STC additional SFR */ 7 | 8 | /* sfr AUXR = 0x8e; */ 9 | /* sfr AUXR1 = 0xa2; */ 10 | /* sfr IPH = 0xb7; */ 11 | 12 | __sfr __at (0xc0) P4; 13 | __sbit __at (0xc0+6) P46; 14 | __sbit __at (0xc0+5) P45;//ISP下载需勾选"ALE脚用作P4.5口" 15 | __sbit __at (0xc0+4) P44; 16 | __sbit __at (0xc0+3) P43; 17 | __sbit __at (0xc0+2) P42; 18 | __sbit __at (0xc0+1) P41; 19 | __sbit __at (0xc0+0) P40; 20 | 21 | __sfr __at (0xe8) XICON; 22 | 23 | __sfr __at (0xe1) WDT_CONTR; 24 | 25 | __sfr __at (0xe2) ISP_DATA; 26 | __sfr __at (0xe3) ISP_ADDRH; 27 | __sfr __at (0xe4) ISP_ADDRL; 28 | __sfr __at (0xe5) ISP_CMD; 29 | __sfr __at (0xe6) ISP_TRIG; 30 | __sfr __at (0xe7) ISP_CONTR; 31 | 32 | /* Above is STC additional SFR */ 33 | 34 | /*-------------------------------------------------------------------------- 35 | REG51F.H 36 | 37 | Header file for 8xC31/51, 80C51Fx, 80C51Rx+ 38 | Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. 39 | All rights reserved. 40 | 41 | Modification according to DataSheet from April 1999 42 | - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives 43 | --------------------------------------------------------------------------*/ 44 | 45 | /* BYTE Registers */ 46 | __sfr __at (0x80) P0; 47 | __sbit __at (0x80+0) P00; 48 | __sbit __at (0x80+1) P01; 49 | __sbit __at (0x80+2) P02; 50 | __sbit __at (0x80+3) P03; 51 | __sbit __at (0x80+4) P04; 52 | __sbit __at (0x80+5) P05; 53 | __sbit __at (0x80+6) P06; 54 | __sbit __at (0x80+7) P07; 55 | __sfr __at (0x90) P1; 56 | __sbit __at (0x90+0) P10; 57 | __sbit __at (0x90+1) P11; 58 | __sbit __at (0x90+2) P12; 59 | __sbit __at (0x90+3) P13; 60 | __sbit __at (0x90+4) P14; 61 | __sbit __at (0x90+5) P15; 62 | __sbit __at (0x90+6) P16; 63 | __sbit __at (0x90+7) P17; 64 | __sfr __at (0xA0) P2; 65 | __sbit __at (0xA0+0) P20; 66 | __sbit __at (0xA0+1) P21; 67 | __sbit __at (0xA0+2) P22; 68 | __sbit __at (0xA0+3) P23; 69 | __sbit __at (0xA0+4) P24; 70 | __sbit __at (0xA0+5) P25; 71 | __sbit __at (0xA0+6) P26; 72 | __sbit __at (0xA0+7) P27; 73 | __sfr __at (0xB0) P3; 74 | __sbit __at (0xB0+0) P30; 75 | __sbit __at (0xB0+1) P31; 76 | __sbit __at (0xB0+2) P32; 77 | __sbit __at (0xB0+3) P33; 78 | __sbit __at (0xB0+4) P34; 79 | __sbit __at (0xB0+5) P35; 80 | __sbit __at (0xB0+6) P36; 81 | __sbit __at (0xB0+7) P37; 82 | __sfr __at (0xD0) PSW; 83 | __sfr __at (0xE0) ACC; 84 | __sfr __at (0xF0) B; 85 | __sfr __at (0x81) SP; 86 | __sfr __at (0x82) DPL; 87 | __sfr __at (0x83) DPH; 88 | __sfr __at (0x87) PCON; 89 | __sfr __at (0x88) TCON; 90 | __sfr __at (0x89) TMOD; 91 | __sfr __at (0x8A) TL0; 92 | __sfr __at (0x8B) TL1; 93 | __sfr __at (0x8C) TH0; 94 | __sfr __at (0x8D) TH1; 95 | __sfr __at (0xA8) IE; 96 | __sfr __at (0xB8) IP; 97 | __sfr __at (0x98) SCON; 98 | __sfr __at (0x99) SBUF; 99 | 100 | /* 80C51Fx/Rx Extensions */ 101 | __sfr __at (0x8E) AUXR; 102 | __sfr __at (0xA2) AUXR1; 103 | __sfr __at (0xA9) SADDR; 104 | __sfr __at (0xB7) IPH; 105 | __sfr __at (0xB9) SADEN; 106 | __sfr __at (0xC8) T2CON; 107 | __sfr __at (0xC9) T2MOD; 108 | __sfr __at (0xCA) RCAP2L; 109 | __sfr __at (0xCB) RCAP2H; 110 | __sfr __at (0xCC) TL2; 111 | __sfr __at (0xCD) TH2; 112 | 113 | /* PCA SFR 114 | sfr CCON = 0xD8; 115 | sfr CMOD = 0xD9; 116 | sfr CCAPM0 = 0xDA; 117 | sfr CCAPM1 = 0xDB; 118 | sfr CCAPM2 = 0xDC; 119 | sfr CCAPM3 = 0xDD; 120 | sfr CCAPM4 = 0xDE; 121 | sfr CL = 0xE9; 122 | sfr CCAP0L = 0xEA; 123 | sfr CCAP1L = 0xEB; 124 | sfr CCAP2L = 0xEC; 125 | sfr CCAP3L = 0xED; 126 | sfr CCAP4L = 0xEE; 127 | sfr CH = 0xF9; 128 | sfr CCAP0H = 0xFA; 129 | sfr CCAP1H = 0xFB; 130 | sfr CCAP2H = 0xFC; 131 | sfr CCAP3H = 0xFD; 132 | sfr CCAP4H = 0xFE; 133 | */ 134 | 135 | /* BIT Registers */ 136 | /* PSW */ 137 | __sbit __at (0xD0+7) CY; 138 | __sbit __at (0xD0+6) AC; 139 | __sbit __at (0xD0+5) F0; 140 | __sbit __at (0xD0+4) RS1; 141 | __sbit __at (0xD0+3) RS0; 142 | __sbit __at (0xD0+2) OV; 143 | __sbit __at (0xD0+1) F1; 144 | __sbit __at (0xD0+0) P; 145 | 146 | /* TCON */ 147 | __sbit __at (0x88+7) TF1; 148 | __sbit __at (0x88+6) TR1; 149 | __sbit __at (0x88+5) TF0; 150 | __sbit __at (0x88+4) TR0; 151 | __sbit __at (0x88+3) IE1; 152 | __sbit __at (0x88+2) IT1; 153 | __sbit __at (0x88+1) IE0; 154 | __sbit __at (0x88+0) IT0; 155 | 156 | /* IE */ 157 | __sbit __at (0xA8+7) EA; 158 | __sbit __at (0xA8+6) EC; 159 | __sbit __at (0xA8+5) ET2; 160 | __sbit __at (0xA8+4) ES; 161 | __sbit __at (0xA8+3) ET1; 162 | __sbit __at (0xA8+2) EX1; 163 | __sbit __at (0xA8+1) ET0; 164 | __sbit __at (0xA8+0) EX0; 165 | 166 | /* IP */ 167 | /* sbit PPC = IP^6;*/ 168 | __sbit __at (0xB8+5) PT2; 169 | __sbit __at (0xB8+4) PS; 170 | __sbit __at (0xB8+3) PT1; 171 | __sbit __at (0xB8+2) PX1; 172 | __sbit __at (0xB8+1) PT0; 173 | __sbit __at (0xB8+0) PX0; 174 | 175 | /* P3 */ 176 | __sbit __at (0xB0+7) RD; 177 | __sbit __at (0xB0+6) WR; 178 | __sbit __at (0xB0+5) T1; 179 | __sbit __at (0xB0+4) T0; 180 | __sbit __at (0xB0+3) INT1; 181 | __sbit __at (0xB0+2) INT0; 182 | __sbit __at (0xB0+1) TXD; 183 | __sbit __at (0xB0+0) RXD; 184 | 185 | /* SCON */ 186 | __sbit __at (0x98+7) SM0;// alternatively "FE" 187 | __sbit __at (0x98+7) FE; 188 | __sbit __at (0x98+6) SM1; 189 | __sbit __at (0x98+5) SM2; 190 | __sbit __at (0x98+4) REN; 191 | __sbit __at (0x98+3) TB8; 192 | __sbit __at (0x98+2) RB8; 193 | __sbit __at (0x98+1) TI; 194 | __sbit __at (0x98+0) RI; 195 | 196 | /* P1 */ 197 | /* PCA 198 | sbit CEX4 = P1^7; 199 | sbit CEX3 = P1^6; 200 | sbit CEX2 = P1^5; 201 | sbit CEX1 = P1^4; 202 | sbit CEX0 = P1^3; 203 | sbit ECI = P1^2; 204 | */ 205 | 206 | __sbit __at (0x90+1) T2EX; 207 | __sbit __at (0x90+0) T2; 208 | 209 | /* T2CON */ 210 | __sbit __at (0xC8+7) TF2; 211 | __sbit __at (0xC8+6) EXF2; 212 | __sbit __at (0xC8+5) RCLK; 213 | __sbit __at (0xC8+4) TCLK; 214 | __sbit __at (0xC8+3) EXEN2; 215 | __sbit __at (0xC8+2) TR2; 216 | __sbit __at (0xC8+1) C_T2; 217 | __sbit __at (0xC8+0) CP_RL2; 218 | 219 | /* CCON */ 220 | /* PCA 221 | sbit CF = CCON^7; 222 | sbit CR = CCON^6; 223 | 224 | sbit CCF4 = CCON^4; 225 | sbit CCF3 = CCON^3; 226 | sbit CCF2 = CCON^2; 227 | sbit CCF1 = CCON^1; 228 | sbit CCF0 = CCON^0; 229 | */ 230 | 231 | ///////////////////////////////////////////////// 232 | 233 | #endif 234 | 235 | -------------------------------------------------------------------------------- /naken_asm-headers/README.headers: -------------------------------------------------------------------------------- 1 | cf headers converted from SDCC. 2 | stc headers converted from official opensource headers. 3 | nuvoton headers converted from official demo packages. 4 | 5 | -------------------------------------------------------------------------------- /naken_asm-headers/c8051f200.inc: -------------------------------------------------------------------------------- 1 | ; C8051F200.h - Register Declarations for the Cygnal/SiLabs C8051F2xx 2 | ; Processor Range 3 | ; 4 | ; Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl 5 | ; 6 | ; This library is free software; you can redistribute it and/or modify it 7 | ; under the terms of the GNU General Public License as published by the 8 | ; Free Software Foundation; either version 2, or (at your option) any 9 | ; later version. 10 | ; 11 | ; This library is distributed in the hope that it will be useful, 12 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | ; GNU General Public License for more details. 15 | ; 16 | ; You should have received a copy of the GNU General Public License 17 | ; along with this library; see the file COPYING. If not, write to the 18 | ; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19 | ; MA 02110-1301, USA. 20 | ; 21 | ; As a special exception, if you link this library with other files, 22 | ; some of which are compiled with SDCC, to produce an executable, 23 | ; this library does not by itself cause the resulting executable to 24 | ; be covered by the GNU General Public License. This exception does 25 | ; not however invalidate any other reasons why the executable file 26 | ; might be covered by the GNU General Public License. 27 | 28 | ; BYTE Registers 29 | P0 equ 0x80 ; PORT 0 30 | SP equ 0x81 ; STACK POINTER 31 | DPL equ 0x82 ; DATA POINTER - LOW BYTE 32 | DPH equ 0x83 ; DATA POINTER - HIGH BYTE 33 | PCON equ 0x87 ; POWER Control 34 | TCON equ 0x88 ; TIMER Control 35 | TMOD equ 0x89 ; TIMER MODE 36 | TL0 equ 0x8A ; TIMER 0 - LOW BYTE 37 | TL1 equ 0x8B ; TIMER 1 - LOW BYTE 38 | TH0 equ 0x8C ; TIMER 0 - HIGH BYTE 39 | TH1 equ 0x8D ; TIMER 1 - HIGH BYTE 40 | CKCON equ 0x8E ; CLOCK Control 41 | PSCTL equ 0x8F ; PROGRAM STORE R/W Control 42 | P1 equ 0x90 ; PORT 1 43 | SCON equ 0x98 ; SERIAL PORT Control 44 | SBUF equ 0x99 ; SERIAL PORT BUFFER 45 | SPI0CFG equ 0x9A ; SERIAL PERIPHERAL INTERFACE 0 Configuration 46 | SPI0DAT equ 0x9B ; SERIAL PERIPHERAL INTERFACE 0 DATA 47 | SPI0CKR equ 0x9D ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE Control 48 | CPT0CN equ 0x9E ; COMPARATOR 0 Control 49 | CPT1CN equ 0x9F ; COMPARATOR 1 Control 50 | P2 equ 0xA0 ; PORT 2 51 | PRT0CF equ 0xA4 ; PORT 0 OUTPUT MODE Configuration 52 | PRT1CF equ 0xA5 ; PORT 1 OUTPUT MODE Configuration 53 | PRT2CF equ 0xA6 ; PORT 2 OUTPUT MODE Configuration 54 | PRT3CF equ 0xA7 ; PORT 3 OUTPUT MODE Configuration 55 | IE equ 0xA8 ; Interrupt Enable 56 | SWCINT equ 0xAD ; SOFTWARE-Controlled Interrupt FLAGS 57 | PRT1IF equ 0xAD ; SOFTWARE-Controlled Interrupt FLAGS (LEGACY NAME equ 58 | EMI0CN equ 0xAF ; EXTERNAL MEMORY INTERFACE Control (F206/F226/F236 equ 59 | _XPAGE equ 0xAF ; XDATA/PDATA PAGE 60 | P3 equ 0xB0 ; PORT 3 61 | OSCXCN equ 0xB1 ; EXTERNAL OSCILLATOR Control 62 | OSCICN equ 0xB2 ; INTERNAL OSCILLATOR Control 63 | FLSCL equ 0xB6 ; FLASH MEMORY TIMING PRESCALER 64 | FLACL equ 0xB7 ; FLASH ACESS LIMIT 65 | IP equ 0xB8 ; Interrupt Priority 66 | AMX0SL equ 0xBB ; ADC 0 MUX CHANNEL SELECTION (Not on F230/1/6 equ 67 | ADC0CF equ 0xBC ; ADC 0 Configuration (Not on F230/1/6 equ 68 | ADC0L equ 0xBE ; ADC 0 Data LOW ( F206 only equ 69 | ADC0H equ 0xBF ; ADC 0 Data High 70 | ADC0GTL equ 0xC4 ; ADC 0 GREATER-THAN Register LOW( F206 only equ 71 | ADC0GTH equ 0xC5 ; ADC 0 GREATER-THAN Register (Not on F230/1/6 equ 72 | ADC0LTL equ 0xC6 ; ADC 0 LESS-THAN Register LOW ( F206 only equ 73 | ADC0LTH equ 0xC7 ; ADC 0 LESS-THAN Register (Not on F230/1/6 equ 74 | T2CON equ 0xC8 ; TIMER 2 Control 75 | RCAP2L equ 0xCA ; TIMER 2 CAPTURE Register - LOW BYTE 76 | RCAP2H equ 0xCB ; TIMER 2 CAPTURE Register - HIGH BYTE 77 | TL2 equ 0xCC ; TIMER 2 - LOW BYTE 78 | TH2 equ 0xCD ; TIMER 2 - HIGH BYTE 79 | PSW equ 0xD0 ; PROGRAM STATUS WORD 80 | REF0CN equ 0xD1 ; VOLTAGE REFERENCE 0 Control 81 | ACC equ 0xE0 ; ACCUMULATOR 82 | PRT0MX equ 0xE1 ; PORT MUX Configuration Register 0 83 | PRT1MX equ 0xE2 ; PORT MUX Configuration Register 1 84 | PRT2MX equ 0xE3 ; PORT MUX Configuration Register 2 85 | EIE1 equ 0xE6 ; EXTERNAL Interrupt Enable 1 86 | EIE2 equ 0xE7 ; EXTERNAL Interrupt Enable 2 87 | ADC0CN equ 0xE8 ; ADC 0 Control (Not on F230/1/6 equ 88 | RSTSRC equ 0xEF ; RESET SOURCE 89 | B equ 0xF0 ; B Register 90 | P0MODE equ 0xF1 ; PORT 0 INPUT MODE Configuration 91 | P1MODE equ 0xF2 ; PORT 1 INPUT MODE Configuration 92 | P2MODE equ 0xF3 ; PORT 2 INPUT MODE Configuration 93 | P3MODE equ 0xF4 ; PORT 3 INPUT MODE Configuration (Not on F221/F231 equ 94 | EIP1 equ 0xF6 ; EXTERNAL Interrupt Priority Register 1 95 | EIP2 equ 0xF7 ; EXTERNAL Interrupt Priority Register 2 96 | SPI0CN equ 0xF8 ; SERIAL PERIPHERAL INTERFACE 0 Control 97 | WDTCN equ 0xFF ; WATCHDOG TIMER Control 98 | 99 | ; WORD/DWORD Registers 100 | TMR0 equ 0x8C8A ; TIMER 0 COUNTER 101 | TMR1 equ 0x8D8B ; TIMER 1 COUNTER 102 | TMR2 equ 0xCDCC ; TIMER 2 COUNTER 103 | RCAP2 equ 0xCBCA ; TIMER 2 CAPTURE REGISTER WORD 104 | ADC0 equ 0xBFBE ; ADC 0 DATA WORD 105 | ADC0GT equ 0xC5C4 ; ADC 0 GREATER-THAN REGISTER WORD 106 | ADC0LT equ 0xC7C6 ; ADC 0 LESS-THAN REGISTER WORD 107 | 108 | ; BIT Registers 109 | 110 | ; TCON 0x88 111 | IT0 equ 0x88 ; EXT. Interrupt 0 TYPE 112 | IE0 equ 0x89 ; EXT. Interrupt 0 EDGE FLAG 113 | IT1 equ 0x8A ; EXT. Interrupt 1 TYPE 114 | IE1 equ 0x8B ; EXT. Interrupt 1 EDGE FLAG 115 | TR0 equ 0x8C ; TIMER 0 ON/OFF Control 116 | TF0 equ 0x8D ; TIMER 0 Overflow FLAG 117 | TR1 equ 0x8E ; TIMER 1 ON/OFF Control 118 | TF1 equ 0x8F ; TIMER 1 Overflow FLAG 119 | 120 | ; SCON 0x98 121 | RI equ 0x98 ; RECEIVE Interrupt FLAG 122 | TI equ 0x99 ; TRANSMIT Interrupt FLAG 123 | RB8 equ 0x9A ; RECEIVE BIT 8 124 | TB8 equ 0x9B ; TRANSMIT BIT 8 125 | REN equ 0x9C ; RECEIVE Enable 126 | SM2 equ 0x9D ; MULTIPROCESSOR COMMUNICATION Enable 127 | SM1 equ 0x9E ; SERIAL MODE Control BIT 1 128 | SM0 equ 0x9F ; SERIAL MODE Control BIT 0 129 | 130 | ; IE 0xA8 131 | EX0 equ 0xA8 ; EXTERNAL Interrupt 0 Enable 132 | ET0 equ 0xA9 ; TIMER 0 Interrupt Enable 133 | EX1 equ 0xAA ; EXTERNAL Interrupt 1 Enable 134 | ET1 equ 0xAB ; TIMER 1 Interrupt Enable 135 | ES equ 0xAC ; SERIAL PORT Interrupt Enable 136 | ET2 equ 0xAD ; TIMER 2 Interrupt Enable 137 | EA equ 0xAF ; GLOBAL Interrupt Enable 138 | 139 | ; IP 0xB8 140 | PX0 equ 0xB8 ; EXTERNAL Interrupt 0 Priority 141 | PT0 equ 0xB9 ; TIMER 0 Priority 142 | PX1 equ 0xBA ; EXTERNAL Interrupt 1 Priority 143 | PT1 equ 0xBB ; TIMER 1 Priority 144 | PS equ 0xBC ; SERIAL PORT Priority 145 | PT2 equ 0xBD ; TIMER 2 Priority 146 | 147 | ; T2CON 0xC8 148 | CPRL2 equ 0xC8 ; CAPTURE OR RELOAD SELECT 149 | CT2 equ 0xC9 ; TIMER OR COUNTER SELECT 150 | TR2 equ 0xCA ; TIMER 2 ON/OFF Control 151 | EXEN2 equ 0xCB ; TIMER 2 EXTERNAL Enable FLAG 152 | TCLK equ 0xCC ; TRANSMIT CLOCK FLAG 153 | RCLK equ 0xCD ; RECEIVE CLOCK FLAG 154 | EXF2 equ 0xCE ; EXTERNAL FLAG 155 | TF2 equ 0xCF ; TIMER 2 Overflow FLAG 156 | 157 | ; PSW 0xD0 158 | P equ 0xD0 ; ACCUMULATOR PARITY FLAG 159 | F1 equ 0xD1 ; USER FLAG 1 160 | OV equ 0xD2 ; Overflow FLAG 161 | RS0 equ 0xD3 ; Register BANK SELECT 0 162 | RS1 equ 0xD4 ; Register BANK SELECT 1 163 | F0 equ 0xD5 ; USER FLAG 0 164 | AC equ 0xD6 ; AUXILIARY CARRY FLAG 165 | CY equ 0xD7 ; CARRY FLAG 166 | 167 | ; ADC0CN 0xE8 168 | ADLJST equ 0xE8 ; Left Justify Data (F206 only equ 169 | ADWINT equ 0xE9 ; WINDOW COMPARE Interrupt FLAG 170 | ADSTM0 equ 0xEA ; START OF CONVERSION MODE BIT 0 171 | ADSTM1 equ 0xEB ; START OF CONVERSION MODE BIT 1 172 | ADBUSY equ 0xEC ; BUSY FLAG 173 | ADCINT equ 0xED ; CONVERISION COMPLETE Interrupt FLAG 174 | ADCTM equ 0xEE ; TRACK MODE 175 | ADCEN equ 0xEF ; Enable 176 | 177 | ; SPI0CN 0xF8 178 | SPIEN equ 0xF8 ; SPI Enable 179 | MSTEN equ 0xF9 ; MASTER Enable 180 | SLVSEL equ 0xFA ; SLAVE SELECT 181 | TXBSY equ 0xFB ; TX BUSY FLAG 182 | RXOVRN equ 0xFC ; RX OVERRUN FLAG 183 | MODF equ 0xFD ; MODE FAULT FLAG 184 | WCOL equ 0xFE ; WRITE COLLISION FLAG 185 | SPIF equ 0xFF ; Interrupt FLAG 186 | -------------------------------------------------------------------------------- /naken_asm-headers/c8051f326.inc: -------------------------------------------------------------------------------- 1 | ; C8051F326.h - Register Declarations for the Cygnal/SiLabs C8051F326/7 2 | ; Processor Range 3 | ; 4 | ; Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl 5 | ; 6 | ; This library is free software; you can redistribute it and/or modify it 7 | ; under the terms of the GNU General Public License as published by the 8 | ; Free Software Foundation; either version 2, or (at your option) any 9 | ; later version. 10 | ; 11 | ; This library is distributed in the hope that it will be useful, 12 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | ; GNU General Public License for more details. 15 | ; 16 | ; You should have received a copy of the GNU General Public License 17 | ; along with this library; see the file COPYING. If not, write to the 18 | ; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19 | ; MA 02110-1301, USA. 20 | ; 21 | ; As a special exception, if you link this library with other files, 22 | ; some of which are compiled with SDCC, to produce an executable, 23 | ; this library does not by itself cause the resulting executable to 24 | ; be covered by the GNU General Public License. This exception does 25 | ; not however invalidate any other reasons why the executable file 26 | ; might be covered by the GNU General Public License. 27 | 28 | ; BYTE Registers 29 | P0 equ 0x80 ; PORT 0 30 | SP equ 0x81 ; STACK POINTER 31 | DPL equ 0x82 ; DATA POINTER - LOW BYTE 32 | DPH equ 0x83 ; DATA POINTER - HIGH BYTE 33 | PCON equ 0x87 ; POWER CONTROL 34 | TCON equ 0x88 ; TIMER CONTROL 35 | TMOD equ 0x89 ; TIMER MODE 36 | TL0 equ 0x8A ; TIMER 0 - LOW BYTE 37 | TL1 equ 0x8B ; TIMER 1 - LOW BYTE 38 | TH0 equ 0x8C ; TIMER 0 - HIGH BYTE 39 | TH1 equ 0x8D ; TIMER 1 - HIGH BYTE 40 | CKCON equ 0x8E ; CLOCK CONTROL 41 | PSCTL equ 0x8F ; PROGRAM STORE R/W CONTROL 42 | SBCON0 equ 0x91 ; BAUDRATE GENERATOR 0 CONTROL 43 | SBRLL0 equ 0x93 ; BAUDRATE GENERATOR 0 RELOAD VALUE - LOW BYTE 44 | SBRLH0 equ 0x94 ; BAUDRATE GENERATOR 0 RELOAD VALUE - HIGH BYTE 45 | USB0ADR equ 0x96 ; USB0 INDIRECT ADDRESS REGISTER 46 | USB0DAT equ 0x97 ; USB0 DATA REGISTER 47 | SCON equ 0x98 ; UART0 CONTROL 48 | SCON0 equ 0x98 ; UART0 CONTROL 49 | SBUF equ 0x99 ; UART0 BUFFER 50 | SBUF0 equ 0x99 ; UART0 BUFFER 51 | SMOD0 equ 0x9A ; UART0 MODE 52 | P2 equ 0xA0 ; PORT 2 53 | P0MDOUT equ 0xA4 ; PORT 0 OUTPUT MODE CONFIGURATION 54 | P2MDOUT equ 0xA6 ; PORT 2 OUTPUT MODE CONFIGURATION 55 | P3MDOUT equ 0xA7 ; PORT 3 OUTPUT MODE CONFIGURATION 56 | IE equ 0xA8 ; INTERRUPT ENABLE 57 | CLKSEL equ 0xA9 ; SYSTEM CLOCK SELECT 58 | EMI0CN equ 0xAA ; EXTERNAL MEMORY INTERFACE CONTROL 59 | _XPAGE equ 0xAA ; XDATA/PDATA PAGE 60 | P3 equ 0xB0 ; PORT 3 61 | OSCICN equ 0xB2 ; INTERNAL OSCILLATOR CONTROL 62 | OSCICL equ 0xB3 ; INTERNAL OSCILLATOR CALIBRATION 63 | FLSCL equ 0xB6 ; FLASH MEMORY TIMING PRESCALER 64 | FLKEY equ 0xB7 ; FLASH ACESS LIMIT 65 | IP equ 0xB8 ; INTERRUPT PRIORITY 66 | CLKMUL equ 0xB9 ; CLOCK MULTIPLIER CONTROL REGISTER 67 | REG0CN equ 0xC9 ; VOLTAGE REGULATOR CONTROL 68 | PSW equ 0xD0 ; PROGRAM STATUS WORD 69 | USB0XCN equ 0xD7 ; USB0 TRANSCEIVER CONTROL 70 | ACC equ 0xE0 ; ACCUMULATOR 71 | GPIOCN equ 0xE2 ; GLOBAL PORT I/O CONTROL 72 | OSCLCN equ 0xE3 ; LOW-FREQUENCY OSCILLATOR CONTROL 73 | EIE1 equ 0xE6 ; EXTERNAL INTERRUPT ENABLE 1 74 | EIE2 equ 0xE7 ; EXTERNAL INTERRUPT ENABLE 2 75 | RSTSRC equ 0xEF ; RESET SOURCE 76 | B equ 0xF0 ; B REGISTER 77 | EIP1 equ 0xF6 ; EXTERNAL INTERRUPT PRIORITY REGISTER 1 78 | EIP2 equ 0xF7 ; EXTERNAL INTERRUPT PRIORITY REGISTER 2 79 | VDM0CN equ 0xFF ; VDD MONITOR CONTROL 80 | 81 | ; WORD/DWORD Registers 82 | TMR0 equ 0x8C8A ; TIMER 0 COUNTER 83 | TMR1 equ 0x8D8B ; TIMER 1 COUNTER 84 | SBRL0 equ 0x9493 ; BAUDRATE GENERATOR 0 RELOAD VALUE WORD 85 | 86 | ; BIT Registers 87 | 88 | ; TCON 0x88 89 | IT0 equ 0x88 ; TCON.0 - EXT. INTERRUPT 0 TYPE 90 | IE0 equ 0x89 ; TCON.1 - EXT. INTERRUPT 0 EDGE FLAG 91 | IT1 equ 0x8A ; TCON.2 - EXT. INTERRUPT 1 TYPE 92 | IE1 equ 0x8B ; TCON.3 - EXT. INTERRUPT 1 EDGE FLAG 93 | TR0 equ 0x8C ; TCON.4 - TIMER 0 ON/OFF CONTROL 94 | TF0 equ 0x8D ; TCON.5 - TIMER 0 OVERFLOW FLAG 95 | TR1 equ 0x8E ; TCON.6 - TIMER 1 ON/OFF CONTROL 96 | TF1 equ 0x8F ; TCON.7 - TIMER 1 OVERFLOW FLAG 97 | 98 | ; SCON 0x98 99 | RI equ 0x98 ; SCON.0 - RECEIVE INTERRUPT FLAG 100 | RI0 equ 0x98 ; SCON.0 - RECEIVE INTERRUPT FLAG 101 | TI equ 0x99 ; SCON.1 - TRANSMIT INTERRUPT FLAG 102 | TI0 equ 0x99 ; SCON.1 - TRANSMIT INTERRUPT FLAG 103 | RB8 equ 0x9A ; SCON.2 - RECEIVE BIT 8 104 | RBX0 equ 0x9A ; SCON.2 - EXTRA RECEIVE BIT 105 | TB8 equ 0x9B ; SCON.3 - TRANSMIT BIT 8 106 | TBX0 equ 0x9B ; SCON.3 - EXTRA TRANSMIT BIT 107 | REN equ 0x9C ; SCON.4 - RECEIVE ENABLE 108 | REN0 equ 0x9C ; SCON.4 - RECEIVE ENABLE 109 | PERR0 equ 0x9E ; SCON.6 - PARITY ERROR FLAG 110 | OVR0 equ 0x9F ; SCON.7 - RECEIVE FIFO OVERRUN FLAG 111 | 112 | ; IE 0xA8 113 | EX0 equ 0xA8 ; IE.0 - EXTERNAL INTERRUPT 0 ENABLE 114 | ET0 equ 0xA9 ; IE.1 - TIMER 0 INTERRUPT ENABLE 115 | EX1 equ 0xAA ; IE.2 - EXTERNAL INTERRUPT 1 ENABLE 116 | ET1 equ 0xAB ; IE.3 - TIMER 1 INTERRUPT ENABLE 117 | ES equ 0xAC ; IE.4 - SERIAL PORT INTERRUPT ENABLE 118 | ES0 equ 0xAC ; IE.4 - SERIAL PORT INTERRUPT ENABLE 119 | EA equ 0xAF ; IE.7 - GLOBAL INTERRUPT ENABLE 120 | 121 | ; IP 0xB8 122 | PX0 equ 0xB8 ; IP.0 - EXTERNAL INTERRUPT 0 PRIORITY 123 | PT0 equ 0xB9 ; IP.1 - TIMER 0 PRIORITY 124 | PX1 equ 0xBA ; IP.2 - EXTERNAL INTERRUPT 1 PRIORITY 125 | PT1 equ 0xBB ; IP.3 - TIMER 1 PRIORITY 126 | PS equ 0xBC ; IP.4 - SERIAL PORT PRIORITY 127 | PS0 equ 0xBC ; IP.4 - SERIAL PORT PRIORITY 128 | 129 | ; PSW 0xD0 130 | PARITY equ 0xD0 ; PSW.0 - ACCUMULATOR PARITY FLAG 131 | F1 equ 0xD1 ; PSW.1 - FLAG 1 132 | OV equ 0xD2 ; PSW.2 - OVERFLOW FLAG 133 | RS0 equ 0xD3 ; PSW.3 - REGISTER BANK SELECT 0 134 | RS1 equ 0xD4 ; PSW.4 - REGISTER BANK SELECT 1 135 | F0 equ 0xD5 ; PSW.5 - FLAG 0 136 | AC equ 0xD6 ; PSW.6 - AUXILIARY CARRY FLAG 137 | CY equ 0xD7 ; PSW.7 - CARRY FLAG 138 | 139 | ; Predefined SFR Bit Masks 140 | PCON_IDLE equ 0x01 ; PCON 141 | PCON_STOP equ 0x02 ; PCON 142 | T0M equ 0x04 ; CKCON 143 | T1M equ 0x08 ; CKCON 144 | PSWE equ 0x01 ; PSCTL 145 | PSEE equ 0x02 ; PSCTL 146 | EUSB0 equ 0x02 ; EIE1 147 | EVBUS equ 0x01 ; EIE2 148 | PORSF equ 0x02 ; RSTSRC 149 | SWRSF equ 0x10 ; RSTSRC 150 | -------------------------------------------------------------------------------- /naken_asm-headers/c8051f520.inc: -------------------------------------------------------------------------------- 1 | ; C8051F520.h - Register Declarations for the SiLabs C8051F52x-F53x 2 | ; Processor Range 3 | ; 4 | ; Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl 5 | ; 6 | ; This library is free software; you can redistribute it and/or modify it 7 | ; under the terms of the GNU General Public License as published by the 8 | ; Free Software Foundation; either version 2, or (at your option) any 9 | ; later version. 10 | ; 11 | ; This library is distributed in the hope that it will be useful, 12 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | ; GNU General Public License for more details. 15 | ; 16 | ; You should have received a copy of the GNU General Public License 17 | ; along with this library; see the file COPYING. If not, write to the 18 | ; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19 | ; MA 02110-1301, USA. 20 | ; 21 | ; As a special exception, if you link this library with other files, 22 | ; some of which are compiled with SDCC, to produce an executable, 23 | ; this library does not by itself cause the resulting executable to 24 | ; be covered by the GNU General Public License. This exception does 25 | ; not however invalidate any other reasons why the executable file 26 | ; might be covered by the GNU General Public License. 27 | P0 equ 0x80 ; Port 0 28 | SP equ 0x81 ; Stack Pointer 29 | DPL equ 0x82 ; Data Pointer Low Byte 30 | DPH equ 0x83 ; Data Pointer High Byte 31 | PCON equ 0x87 ; Power Mode Control 32 | TCON equ 0x88 ; Timer Control 33 | IT0 equ 0x88.0 ; Ext. Interrupt 0 Type Select 34 | IE0 equ 0x88.1 ; Ext. Interrupt 0 Flag 35 | IT1 equ 0x88.2 ; Ext. Interrupt 1 Type Select 36 | IE1 equ 0x88.3 ; Ext. Interrupt 1 Flag 37 | TR0 equ 0x88.4 ; Timer 0 Run Control 38 | TF0 equ 0x88.5 ; Timer 0 Overflow Flag 39 | TR1 equ 0x88.6 ; Timer 1 Run Control 40 | TF1 equ 0x88.7 ; Timer 1 Overflow Flag 41 | TMOD equ 0x89 ; Timer Mode 42 | TMR0 equ 0x8C8A ; Timer/Counter 0 Word 43 | TL0 equ 0x8A ; Timer/Counter 0 Low Byte 44 | TH0 equ 0x8C ; Timer/Counter 0 High Byte 45 | TMR1 equ 0x8D8B ; Timer/Counter 1 Word 46 | TL1 equ 0x8B ; Timer/Counter 1 Low Byte 47 | TH1 equ 0x8D ; Timer/Counter 1 High Byte 48 | CKCON equ 0x8E ; Clock Control 49 | PSCTL equ 0x8F ; Program Store R/W Control 50 | P1 equ 0x90 ; Port 1 51 | LINADDR equ 0x92 ; LIN Indirect Address Pointer 52 | LINDATA equ 0x93 ; LIN Indirect Data Buffer 53 | LINCF equ 0x95 ; LIN Control Mode 54 | SCON0 equ 0x98 ; Serial Port 0 Control 55 | RI0 equ 0x98.0 ; Receive Interrupt Flag 56 | TI0 equ 0x98.1 ; Transmit Interrupt Flag 57 | RB80 equ 0x98.2 ; Ninth Receive Bit 58 | TB80 equ 0x98.3 ; Ninth Transmission Bit 59 | REN0 equ 0x98.4 ; Receive Enable 60 | MCE0 equ 0x98.5 ; Multiprocessor Communication Enable 61 | S0MODE equ 0x98.7 ; Serial Port 0 Operation Mode 62 | SBUF0 equ 0x99 ; Serial Port 0 Data Buffer 63 | CPT0CN equ 0x9B ; Comparator 0 Control 64 | CPT0MD equ 0x9D ; Comparator 0 Mode Selection 65 | CPT0MX equ 0x9F ; Comparator 0 MUX Selection 66 | SPI0CFG equ 0xA1 ; SPI Configuration 67 | SPI0CKR equ 0xA2 ; SPI Clock Rate Control 68 | SPI0DAT equ 0xA3 ; SPI Data 69 | P0MDOUT equ 0xA4 ; Port 0 Output Mode Configuration 70 | P1MDOUT equ 0xA5 ; Port 1 Output Mode Configuration 71 | IE equ 0xA8 ; Interrupt Enable 72 | EX0 equ 0xA8.0 ; Enable External Interrupt 0 73 | ET0 equ 0xA8.1 ; Enable Timer 0 Interrupt 74 | EX1 equ 0xA8.2 ; Enable External Interrupt 1 75 | ET1 equ 0xA8.3 ; Enable Timer 1 Interrupt 76 | ES0 equ 0xA8.4 ; Enable Serial Port Interrupt 77 | ET2 equ 0xA8.5 ; Enable Timer 2 Interrupt 78 | ESPI0 equ 0xA8.6 ; Enable SPI0 Interrupt 79 | EA equ 0xA8.7 ; Global Interrupt Enable 80 | CLKSEL equ 0xA9 ; Clock Select 81 | OSCIFIN equ 0xB0 ; Internal Oscillator Fine Calibration 82 | OSCXCN equ 0xB1 ; External Oscillator Control 83 | OSCICN equ 0xB2 ; Internal Oscillator Control 84 | OSCICL equ 0xB3 ; Internal Oscillator Calibration 85 | FLKEY equ 0xB7 ; Flash Lock and Key 86 | IP equ 0xB8 ; Interrupt Priority 87 | PX0 equ 0xB8.0 ; External Interrupt 0 Priority 88 | PT0 equ 0xB8.1 ; Timer 0 Interrupt Priority 89 | PX1 equ 0xB8.2 ; External Interrupt 1 Priority 90 | PT1 equ 0xB8.3 ; Timer 1 Interrupt Priority 91 | PS0 equ 0xB8.4 ; Serial Port Interrupt Priority 92 | PT2 equ 0xB8.5 ; Timer 2 Interrupt Priority 93 | PSPI0 equ 0xB8.6 ; SPI0 Interrupt Priority 94 | ADC0TK equ 0xBA ; ADC0 Tracking Mode Select 95 | ADC0MX equ 0xBB ; ADC0 Channel Select 96 | ADC0CF equ 0xBC ; ADC0 Configuration 97 | ADC0 equ 0xBD ; ADC0 Word 98 | ADC0L equ 0xBD ; ADC0 Low Byte 99 | ADC0H equ 0xBE ; ADC0 High Byte 100 | P1MASK equ 0xBF ; Port 1 Mask 101 | ADC0GT equ 0xC3 ; ADC0 Greater-Than Data Word 102 | ADC0GTL equ 0xC3 ; ADC0 Greater-Than Data Low Byte 103 | ADC0GTH equ 0xC4 ; ADC0 Greater-Than Data High Byte 104 | ADC0LT equ 0xC5 ; ADC0 Less-Than Data Word 105 | ADC0LTL equ 0xC5 ; ADC0 Less-Than Data Low Byte 106 | ADC0LTH equ 0xC6 ; ADC0 Less-Than Data High Byte 107 | P0MASK equ 0xC7 ; Port 0 Mask 108 | TMR2CN equ 0xC8 ; Timer/Counter 2 Control 109 | REG0CN equ 0xC9 ; Voltage Regulator Control 110 | TMR2RL equ 0xCA ; Timer/Counter 2 Reload Word 111 | TMR2RLL equ 0xCA ; Timer/Counter 2 Reload Low Byte 112 | TMR2RLH equ 0xCB ; Timer/Counter 2 Reload High Byte 113 | TMR2 equ 0xCC ; Timer/Counter 2 Word 114 | TMR2L equ 0xCC ; Timer/Counter 2 Low Byte 115 | TMR2H equ 0xCD ; Timer/Counter 2 High Byte 116 | P1MAT equ 0xCF ; Port 1 Match 117 | PSW equ 0xD0 ; Program Status Word 118 | P equ 0xD0.0 ; Parity Flag 119 | F1 equ 0xD0.1 ; User-Defined Flag 120 | OV equ 0xD0.2 ; Overflow Flag 121 | RS0 equ 0xD0.3 ; Register Bank Select 0 122 | RS1 equ 0xD0.4 ; Register Bank Select 1 123 | F0 equ 0xD0.5 ; User-Defined Flag 124 | AC equ 0xD0.6 ; Auxiliary Carry Flag 125 | CY equ 0xD0.7 ; Carry Flag 126 | REF0CN equ 0xD1 ; Voltage Reference Control 127 | P0SKIP equ 0xD4 ; Port 0 Skip 128 | P1SKIP equ 0xD5 ; Port 1 Skip 129 | P0MAT equ 0xD7 ; Port 0 Match 130 | PCA0CN equ 0xD8 ; PCA Control 131 | CCF0 equ 0xD8.0 ; PCA Module 0 Capture/Compare Flag 132 | CCF1 equ 0xD8.1 ; PCA Module 1 Capture/Compare Flag 133 | CCF2 equ 0xD8.2 ; PCA Module 2 Capture/Compare Flag 134 | CR equ 0xD8.6 ; PCA Counter/Timer Run Control 135 | CF equ 0xD8.7 ; PCA Counter/Timer Overflow Flag 136 | PCA0MD equ 0xD9 ; PCA Mode 137 | PCA0CPM0 equ 0xDA ; PCA Module 0 Mode 138 | PCA0CPM1 equ 0xDB ; PCA Module 1 Mode 139 | PCA0CPM2 equ 0xDC ; PCA Module 2 Mode 140 | ACC equ 0xE0 ; Accumulator 141 | XBR0 equ 0xE1 ; Port I/O Crossbar Control 0 142 | XBR1 equ 0xE2 ; Port I/O Crossbar Control 1 143 | IT01CF equ 0xE4 ; INT0/INT1 Configuration 144 | EIE1 equ 0xE6 ; Extended Interrupt Enable 1 145 | ADC0CN equ 0xE8 ; ADC0 Control 146 | AD0CM0 equ 0xE8.0 ; ADC0 Conversion Start Mode Select Bit 0 147 | AD0CM1 equ 0xE8.1 ; ADC0 Conversion Start Mode Select Bit 1 148 | AD0LJST equ 0xE8.2 ; ADC0 Left Justify Select 149 | AD0WINT equ 0xE8.3 ; ADC0 Window Compare Interrupt Flag 150 | AD0BUSY equ 0xE8.4 ; ADC0 Busy Bit 151 | AD0INT equ 0xE8.5 ; ADC0 Conversion Complete Interrupt Flag 152 | BURSTEN equ 0xE8.6 ; ADC0 Burst Mode Enable Bit 153 | AD0EN equ 0xE8.7 ; ADC0 Enable Bit 154 | PCA0CP1 equ 0xE9 ; PCA Capture 1 Word 155 | PCA0CPL1 equ 0xE9 ; PCA Capture 1 Low Byte 156 | PCA0CPH1 equ 0xEA ; PCA Capture 1 High Byte 157 | PCA0CP2 equ 0xEB ; PCA Capture 2 Word 158 | PCA0CPL2 equ 0xEB ; PCA Capture 2 Low Byte 159 | PCA0CPH2 equ 0xEC ; PCA Capture 2 High Byte 160 | RSTSRC equ 0xEF ; Reset Source Configuration/Status 161 | B equ 0xF0 ; B Register 162 | P0MDIN equ 0xF1 ; Port 0 Input Mode Configuration 163 | P1MDIN equ 0xF2 ; Port 1 Input Mode Configuration 164 | EIP1 equ 0xF6 ; Extended Interrupt Priority 1 165 | SPI0CN equ 0xF8 ; SPI0 Control 166 | SPIEN equ 0xF8.0 ; SPI0 Enable 167 | TXBMT equ 0xF8.1 ; SPI0 Transmit Buffer Empty 168 | NSSMD0 equ 0xF8.2 ; SPI0 Slave Select Mode Bit 0 169 | NSSMD1 equ 0xF8.3 ; SPI0 Slave Select Mode Bit 1 170 | RXOVRN equ 0xF8.4 ; SPI0 Receive Overrun Flag 171 | MODF equ 0xF8.5 ; SPI0 Mode Fault Flag 172 | WCOL equ 0xF8.6 ; SPI0 Write Collision Flag 173 | SPIF equ 0xF8.7 ; SPI0 Interrupt Flag 174 | PCA0 equ 0xF9 ; PCA Counter Word 175 | PCA0L equ 0xF9 ; PCA Counter Low Byte 176 | PCA0H equ 0xFA ; PCA Counter High Byte 177 | PCA0CP0 equ 0xFB ; PCA Capture 0 Word 178 | PCA0CPL0 equ 0xFB ; PCA Capture 0 Low Byte 179 | PCA0CPH0 equ 0xFC ; PCA Capture 0 High Byte 180 | VDDMON equ 0xFF ; VDD Control 181 | 182 | ; Predefined SFR Bit Masks 183 | PCON_IDLE equ 0x01 ; PCON 184 | PCON_STOP equ 0x02 ; PCON 185 | T1M equ 0x08 ; CKCON 186 | PSWE equ 0x01 ; PSCTL 187 | PSEE equ 0x02 ; PSCTL 188 | PORSF equ 0x02 ; RSTSRC 189 | SWRSF equ 0x10 ; RSTSRC 190 | ECCF equ 0x01 ; PCA0CPMn 191 | PWM equ 0x02 ; PCA0CPMn 192 | TOG equ 0x04 ; PCA0CPMn 193 | MAT equ 0x08 ; PCA0CPMn 194 | CAPN equ 0x10 ; PCA0CPMn 195 | CAPP equ 0x20 ; PCA0CPMn 196 | ECOM equ 0x40 ; PCA0CPMn 197 | PWM16 equ 0x80 ; PCA0CPMn 198 | CP0E equ 0x10 ; XBR0 199 | CP0AE equ 0x20 ; XBR0 200 | 201 | ; Interrupts 202 | INT_EXT0 equ 0 ; External Interrupt 0 203 | INT_TIMER0 equ 1 ; Timer0 Overflow 204 | INT_EXT1 equ 2 ; External Interrupt 1 205 | INT_TIMER1 equ 3 ; Timer1 Overflow 206 | INT_UART0 equ 4 ; Serial Port 0 207 | INT_TIMER2 equ 5 ; Timer2 Overflow 208 | INT_SPI0 equ 6 ; Serial Peripheral Interface 0 209 | INT_ADC0_WINDOW equ 7 ; ADC0 Window Comparison 210 | INT_ADC0_EOC equ 8 ; ADC0 End Of Conversion 211 | INT_PCA0 equ 9 ; PCA0 Peripheral 212 | INT_COMP_FALLING equ 10 ; Comparator0 Falling 213 | INT_COMP_RISING equ 11 ; Comparator0 Rising 214 | INT_LIN equ 12 ; LIN 215 | INT_VREG_DROPOUT equ 13 ; VREG dropout 216 | INT_PORT_MATCH equ 14 ; Port Match 217 | -------------------------------------------------------------------------------- /naken_asm-headers/ch552.inc: -------------------------------------------------------------------------------- 1 | PSW equ 0xD0 2 | ACC equ 0xE0 3 | B equ 0xF0 4 | SP equ 0x81 5 | DPL equ 0x82 6 | DPH equ 0x83 7 | SAFE_MOD equ 0xA1 8 | GLOBAL_CFG equ 0xB1 9 | PCON equ 0x87 10 | CLOCK_CFG equ 0xB9 11 | WAKE_CTRL equ 0xA9 12 | RESET_KEEP equ 0xFE 13 | WDOG_COUNT equ 0xFF 14 | IE equ 0xA8 15 | IP equ 0xB8 16 | IE_EX equ 0xE8 17 | IP_EX equ 0xE9 18 | GPIO_IE equ 0xC7 19 | ROM_ADDR_L equ 0x84 20 | ROM_ADDR_H equ 0x85 21 | ROM_DATA_L equ 0x8E 22 | ROM_DATA_H equ 0x8F 23 | ROM_CTRL equ 0x86 24 | P1 equ 0x90 25 | P1_MOD_OC equ 0x92 26 | P1_DIR_PU equ 0x93 27 | P2 equ 0xA0 28 | P3 equ 0xB0 29 | P3_MOD_OC equ 0x96 30 | P3_DIR_PU equ 0x97 31 | PIN_FUNC equ 0xC6 32 | XBUS_AUX equ 0xA2 33 | TCON equ 0x88 34 | TMOD equ 0x89 35 | TL0 equ 0x8A 36 | TL1 equ 0x8B 37 | TH0 equ 0x8C 38 | TH1 equ 0x8D 39 | SCON equ 0x98 40 | SBUF equ 0x99 41 | T2CON equ 0xC8 42 | T2MOD equ 0xC9 43 | RCAP2L equ 0xCA 44 | RCAP2H equ 0xCB 45 | TL2 equ 0xCC 46 | TH2 equ 0xCD 47 | T2CAP1L equ 0xCE 48 | T2CAP1H equ 0xCF 49 | PWM_DATA2 equ 0x9B 50 | PWM_DATA1 equ 0x9C 51 | PWM_CTRL equ 0x9D 52 | PWM_CK_SE equ 0x9E 53 | SPI0_STAT equ 0xF8 54 | SPI0_DATA equ 0xF9 55 | SPI0_CTRL equ 0xFA 56 | SPI0_CK_SE equ 0xFB 57 | SPI0_SETUP equ 0xFC 58 | SCON1 equ 0xC0 59 | SBUF1 equ 0xC1 60 | SBAUD1 equ 0xC2 61 | ADC_CTRL equ 0x80 62 | ADC_CFG equ 0x9A 63 | ADC_DATA equ 0x9F 64 | TKEY_CTRL equ 0xC3 65 | TKEY_DATL equ 0xC4 66 | TKEY_DATH equ 0xC5 67 | USB_C_CTRL equ 0x91 68 | UDEV_CTRL equ 0xD1 69 | UEP1_CTRL equ 0xD2 70 | UEP1_T_LEN equ 0xD3 71 | UEP2_CTRL equ 0xD4 72 | UEP2_T_LEN equ 0xD5 73 | UEP3_CTRL equ 0xD6 74 | UEP3_T_LEN equ 0xD7 75 | USB_INT_FG equ 0xD8 76 | USB_INT_ST equ 0xD9 77 | USB_MIS_ST equ 0xDA 78 | USB_RX_LEN equ 0xDB 79 | UEP0_CTRL equ 0xDC 80 | UEP0_T_LEN equ 0xDD 81 | UEP4_CTRL equ 0xDE 82 | UEP4_T_LEN equ 0xDF 83 | USB_INT_EN equ 0xE1 84 | USB_CTRL equ 0xE2 85 | USB_DEV_AD equ 0xE3 86 | UEP2_DMA_L equ 0xE4 87 | UEP2_DMA_H equ 0xE5 88 | UEP3_DMA_L equ 0xE6 89 | UEP3_DMA_H equ 0xE7 90 | UEP4_1_MOD equ 0xEA 91 | UEP2_3_MOD equ 0xEB 92 | UEP0_DMA_L equ 0xEC 93 | UEP0_DMA_H equ 0xED 94 | UEP1_DMA_L equ 0xEE 95 | UEP1_DMA_H equ 0xEF 96 | 97 | ; bit aliases 98 | 99 | 100 | ; xdata 101 | 102 | -------------------------------------------------------------------------------- /naken_asm-headers/ch554.inc: -------------------------------------------------------------------------------- 1 | PSW equ 0xD0 2 | ACC equ 0xE0 3 | B equ 0xF0 4 | SP equ 0x81 5 | DPL equ 0x82 6 | DPH equ 0x83 7 | SAFE_MOD equ 0xA1 8 | GLOBAL_CFG equ 0xB1 9 | PCON equ 0x87 10 | CLOCK_CFG equ 0xB9 11 | WAKE_CTRL equ 0xA9 12 | RESET_KEEP equ 0xFE 13 | WDOG_COUNT equ 0xFF 14 | IE equ 0xA8 15 | IP equ 0xB8 16 | IE_EX equ 0xE8 17 | IP_EX equ 0xE9 18 | GPIO_IE equ 0xC7 19 | ROM_ADDR_L equ 0x84 20 | ROM_ADDR_H equ 0x85 21 | ROM_DATA_L equ 0x8E 22 | ROM_DATA_H equ 0x8F 23 | ROM_CTRL equ 0x86 24 | P1 equ 0x90 25 | P1_MOD_OC equ 0x92 26 | P1_DIR_PU equ 0x93 27 | P2 equ 0xA0 28 | P3 equ 0xB0 29 | P3_MOD_OC equ 0x96 30 | P3_DIR_PU equ 0x97 31 | PIN_FUNC equ 0xC6 32 | XBUS_AUX equ 0xA2 33 | TCON equ 0x88 34 | TMOD equ 0x89 35 | TL0 equ 0x8A 36 | TL1 equ 0x8B 37 | TH0 equ 0x8C 38 | TH1 equ 0x8D 39 | SCON equ 0x98 40 | SBUF equ 0x99 41 | T2CON equ 0xC8 42 | T2MOD equ 0xC9 43 | RCAP2L equ 0xCA 44 | RCAP2H equ 0xCB 45 | TL2 equ 0xCC 46 | TH2 equ 0xCD 47 | T2CAP1L equ 0xCE 48 | T2CAP1H equ 0xCF 49 | PWM_DATA2 equ 0x9B 50 | PWM_DATA1 equ 0x9C 51 | PWM_CTRL equ 0x9D 52 | PWM_CK_SE equ 0x9E 53 | SPI0_STAT equ 0xF8 54 | SPI0_DATA equ 0xF9 55 | SPI0_CTRL equ 0xFA 56 | SPI0_CK_SE equ 0xFB 57 | SPI0_SETUP equ 0xFC 58 | SCON1 equ 0xC0 59 | SBUF1 equ 0xC1 60 | SBAUD1 equ 0xC2 61 | ADC_CTRL equ 0x80 62 | ADC_CFG equ 0x9A 63 | ADC_DATA equ 0x9F 64 | TKEY_CTRL equ 0xC3 65 | TKEY_DATL equ 0xC4 66 | TKEY_DATH equ 0xC5 67 | USB_C_CTRL equ 0x91 68 | UDEV_CTRL equ 0xD1 69 | UEP1_CTRL equ 0xD2 70 | UEP1_T_LEN equ 0xD3 71 | UEP2_CTRL equ 0xD4 72 | UEP2_T_LEN equ 0xD5 73 | UEP3_CTRL equ 0xD6 74 | UEP3_T_LEN equ 0xD7 75 | USB_INT_FG equ 0xD8 76 | USB_INT_ST equ 0xD9 77 | USB_MIS_ST equ 0xDA 78 | USB_RX_LEN equ 0xDB 79 | UEP0_CTRL equ 0xDC 80 | UEP0_T_LEN equ 0xDD 81 | UEP4_CTRL equ 0xDE 82 | UEP4_T_LEN equ 0xDF 83 | USB_INT_EN equ 0xE1 84 | USB_CTRL equ 0xE2 85 | USB_DEV_AD equ 0xE3 86 | UEP2_DMA_L equ 0xE4 87 | UEP2_DMA_H equ 0xE5 88 | UEP3_DMA_L equ 0xE6 89 | UEP3_DMA_H equ 0xE7 90 | UEP4_1_MOD equ 0xEA 91 | UEP2_3_MOD equ 0xEB 92 | UEP0_DMA_L equ 0xEC 93 | UEP0_DMA_H equ 0xED 94 | UEP1_DMA_L equ 0xEE 95 | UEP1_DMA_H equ 0xEF 96 | 97 | ; bit aliases 98 | 99 | 100 | ; xdata 101 | 102 | -------------------------------------------------------------------------------- /naken_asm-headers/ds89c4xx.inc: -------------------------------------------------------------------------------- 1 | P0 equ 0x80 2 | SP equ 0x81 3 | DPL equ 0x82 4 | DPH equ 0x83 5 | DPL1 equ 0x84 6 | DPH1 equ 0x85 7 | DPS equ 0x86 8 | PCON equ 0x87 9 | TCON equ 0x88 10 | TMOD equ 0x89 11 | TL0 equ 0x8A 12 | TL1 equ 0x8B 13 | TH0 equ 0x8C 14 | TH1 equ 0x8D 15 | CKCON equ 0x8E 16 | P1 equ 0x90 17 | EXIF equ 0x91 18 | CKMOD equ 0x96 19 | SCON0 equ 0x98 20 | SBUF0 equ 0x99 21 | ACON equ 0x9D 22 | P2 equ 0xA0 23 | IE equ 0xA8 24 | SADDR0 equ 0xA9 25 | SADDR1 equ 0xAA 26 | P3 equ 0xB0 27 | IP1 equ 0xB1 28 | IP0 equ 0xB8 29 | SADEN0 equ 0xB9 30 | SADEN1 equ 0xBA 31 | SCON1 equ 0xC0 32 | SBUF1 equ 0xC1 33 | ROMSIZE equ 0xC2 34 | PMR equ 0xC4 35 | STATUS equ 0xC5 36 | TA equ 0xC7 37 | T2CON equ 0xC8 38 | T2MOD equ 0xC9 39 | RCAP2L equ 0xCA 40 | RCAP2H equ 0xCB 41 | TL2 equ 0xCC 42 | TH2 equ 0xCD 43 | PSW equ 0xD0 44 | FCNTL equ 0xD5 45 | FDATA equ 0xD6 46 | WDCON equ 0xD8 47 | ACC equ 0xE0 48 | EIE equ 0xE8 49 | B equ 0xF0 50 | EIP1 equ 0xF1 51 | EIP0 equ 0xF8 52 | 53 | ; bit aliases 54 | 55 | IT0 equ 0x88.0 56 | IE0 equ 0x88.1 57 | IT1 equ 0x88.2 58 | IE1 equ 0x88.3 59 | TR0 equ 0x88.4 60 | TF0 equ 0x88.5 61 | TR1 equ 0x88.6 62 | TF1 equ 0x88.7 63 | RI_0 equ 0x98.0 64 | TI_0 equ 0x98.1 65 | RB8_0 equ 0x98.2 66 | TB8_0 equ 0x98.3 67 | REN_0 equ 0x98.4 68 | SM2_0 equ 0x98.5 69 | SM1_0 equ 0x98.6 70 | FE_0 equ 0x98.7 71 | EX0 equ 0xA8.0 72 | ET0 equ 0xA8.1 73 | EX1 equ 0xA8.2 74 | ET1 equ 0xA8.3 75 | ES0 equ 0xA8.4 76 | ET2 equ 0xA8.5 77 | ES1 equ 0xA8.6 78 | EA equ 0xA8.7 79 | PX0 equ 0xB8.0 80 | PT0 equ 0xB8.1 81 | PX1 equ 0xB8.2 82 | PT1 equ 0xB8.3 83 | PS equ 0xB8.4 84 | RI_1 equ 0xC0.0 85 | TI_1 equ 0xC0.1 86 | RB8_1 equ 0xC0.2 87 | TB8_1 equ 0xC0.3 88 | REN_1 equ 0xC0.4 89 | SM2_1 equ 0xC0.5 90 | SM1_1 equ 0xC0.6 91 | FE_1 equ 0xC0.7 92 | CP equ 0xC8.0 93 | TR2 equ 0xC8.2 94 | EXEN2 equ 0xC8.3 95 | TCLK equ 0xC8.4 96 | RCLK equ 0xC8.5 97 | EXF2 equ 0xC8.6 98 | TF2 equ 0xC8.7 99 | P equ 0xD0.0 100 | F1 equ 0xD0.1 101 | OV equ 0xD0.2 102 | RS0 equ 0xD0.3 103 | RS1 equ 0xD0.4 104 | F0 equ 0xD0.5 105 | AC equ 0xD0.6 106 | CY equ 0xD0.7 107 | RWT equ 0xD8.0 108 | EWT equ 0xD8.1 109 | WTRF equ 0xD8.2 110 | WDIF equ 0xD8.3 111 | PFI equ 0xD8.4 112 | EPFI equ 0xD8.5 113 | POR equ 0xD8.6 114 | SMOD_1 equ 0xD8.7 115 | EX2 equ 0xE8.0 116 | EX3 equ 0xE8.1 117 | EX4 equ 0xE8.2 118 | EX5 equ 0xE8.3 119 | EWDI equ 0xE8.4 120 | LPX2 equ 0xF8.0 121 | LPX3 equ 0xF8.1 122 | LPX4 equ 0xF8.2 123 | LPX5 equ 0xF8.3 124 | LPXWDI equ 0xF8.4 125 | 126 | ; xdata 127 | 128 | -------------------------------------------------------------------------------- /naken_asm-headers/n76e003.inc: -------------------------------------------------------------------------------- 1 | P0 equ 0x80 2 | SP equ 0x81 3 | DPL equ 0x82 4 | DPH equ 0x83 5 | RWK equ 0x86 6 | PCON equ 0x87 7 | TCON equ 0x88 8 | TMOD equ 0x89 9 | TL0 equ 0x8A 10 | TL1 equ 0x8B 11 | TH0 equ 0x8C 12 | TH1 equ 0x8D 13 | CKCON equ 0x8E 14 | WKCON equ 0x8F 15 | P1 equ 0x90 16 | SFRS equ 0x91 17 | CAPCON0 equ 0x92 18 | CAPCON1 equ 0x93 19 | CAPCON2 equ 0x94 20 | CKDIV equ 0x95 21 | CKSWT equ 0x96 22 | CKEN equ 0x97 23 | SCON equ 0x98 24 | SBUF equ 0x99 25 | SBUF_1 equ 0x9A 26 | EIE equ 0x9B 27 | EIE1 equ 0x9C 28 | CHPCON equ 0x9F 29 | P2 equ 0xA0 30 | AUXR1 equ 0xA2 31 | BODCON0 equ 0xA3 32 | IAPTRG equ 0xA4 33 | IAPUEN equ 0xA5 34 | IAPAL equ 0xA6 35 | IAPAH equ 0xA7 36 | IE equ 0xA8 37 | SADDR equ 0xA9 38 | WDCON equ 0xAA 39 | BODCON1 equ 0xAB 40 | P3M1 equ 0xAC 41 | P3S equ 0xAC 42 | P3M2 equ 0xAD 43 | P3SR equ 0xAD 44 | IAPFD equ 0xAE 45 | IAPCN equ 0xAF 46 | P3 equ 0xB0 47 | P0M1 equ 0xB1 48 | P0S equ 0xB1 49 | P0M2 equ 0xB2 50 | P0SR equ 0xB2 51 | P1M1 equ 0xB3 52 | P1S equ 0xB3 53 | P1M2 equ 0xB4 54 | P1SR equ 0xB4 55 | P2S equ 0xB5 56 | IPH equ 0xB7 57 | PWMINTC equ 0xB7 58 | IP equ 0xB8 59 | SADEN equ 0xB9 60 | SADEN_1 equ 0xBA 61 | SADDR_1 equ 0xBB 62 | I2DAT equ 0xBC 63 | I2STAT equ 0xBD 64 | I2CLK equ 0xBE 65 | I2TOC equ 0xBF 66 | I2CON equ 0xC0 67 | I2ADDR equ 0xC1 68 | ADCRL equ 0xC2 69 | ADCRH equ 0xC3 70 | T3CON equ 0xC4 71 | PWM4H equ 0xC4 72 | RL3 equ 0xC5 73 | PWM5H equ 0xC5 74 | RH3 equ 0xC6 75 | PIOCON1 equ 0xC6 76 | TA equ 0xC7 77 | T2CON equ 0xC8 78 | T2MOD equ 0xC9 79 | RCMP2L equ 0xCA 80 | RCMP2H equ 0xCB 81 | TL2 equ 0xCC 82 | PWM4L equ 0xCC 83 | TH2 equ 0xCD 84 | PWM5L equ 0xCD 85 | ADCMPL equ 0xCE 86 | ADCMPH equ 0xCF 87 | PSW equ 0xD0 88 | PWMPH equ 0xD1 89 | PWM0H equ 0xD2 90 | PWM1H equ 0xD3 91 | PWM2H equ 0xD4 92 | PWM3H equ 0xD5 93 | PNP equ 0xD6 94 | FBD equ 0xD7 95 | PWMCON0 equ 0xD8 96 | PWMPL equ 0xD9 97 | PWM0L equ 0xDA 98 | PWM1L equ 0xDB 99 | PWM2L equ 0xDC 100 | PWM3L equ 0xDD 101 | PIOCON0 equ 0xDE 102 | PWMCON1 equ 0xDF 103 | ACC equ 0xE0 104 | ADCCON1 equ 0xE1 105 | ADCCON2 equ 0xE2 106 | ADCDLY equ 0xE3 107 | C0L equ 0xE4 108 | C0H equ 0xE5 109 | C1L equ 0xE6 110 | C1H equ 0xE7 111 | ADCCON0 equ 0xE8 112 | PICON equ 0xE9 113 | PINEN equ 0xEA 114 | PIPEN equ 0xEB 115 | PIF equ 0xEC 116 | C2L equ 0xED 117 | C2H equ 0xEE 118 | EIP equ 0xEF 119 | B equ 0xF0 120 | CAPCON3 equ 0xF1 121 | CAPCON4 equ 0xF2 122 | SPCR equ 0xF3 123 | SPCR2 equ 0xF3 124 | SPSR equ 0xF4 125 | SPDR equ 0xF5 126 | AINDIDS equ 0xF6 127 | EIPH equ 0xF7 128 | SCON_1 equ 0xF8 129 | PDTEN equ 0xF9 130 | PDTCNT equ 0xFA 131 | PMEN equ 0xFB 132 | PMD equ 0xFC 133 | EIP1 equ 0xFE 134 | EIPH1 equ 0xFF 135 | 136 | ; bit aliases 137 | 138 | TF1 equ 0x88.7 139 | TR1 equ 0x88.6 140 | TF0 equ 0x88.5 141 | TR0 equ 0x88.4 142 | IE1 equ 0x88.3 143 | IT1 equ 0x88.2 144 | IE0 equ 0x88.1 145 | IT0 equ 0x88.0 146 | SCL equ 0x90.3 147 | SDA equ 0x90.4 148 | SM0 equ 0x98.7 149 | FE equ 0x98.7 150 | SM1 equ 0x98.6 151 | SM2 equ 0x98.5 152 | REN equ 0x98.4 153 | TB8 equ 0x98.3 154 | RB8 equ 0x98.2 155 | TI equ 0x98.1 156 | RI equ 0x98.0 157 | EA equ 0xA8.7 158 | EADC equ 0xA8.6 159 | EBOD equ 0xA8.5 160 | ES equ 0xA8.4 161 | ET1 equ 0xA8.3 162 | EX1 equ 0xA8.2 163 | ET0 equ 0xA8.1 164 | EX0 equ 0xA8.0 165 | INT0 equ 0xB0.0 166 | PADC equ 0xB8.6 167 | PBOD equ 0xB8.5 168 | PS equ 0xB8.4 169 | PT1 equ 0xB8.3 170 | PX1 equ 0xB8.2 171 | PT0 equ 0xB8.1 172 | PX0 equ 0xB8.0 173 | I2CEN equ 0xC0.6 174 | STA equ 0xC0.5 175 | STO equ 0xC0.4 176 | SI equ 0xC0.3 177 | AA equ 0xC0.2 178 | I2CPX equ 0xC0.0 179 | TF2 equ 0xC8.7 180 | TR2 equ 0xC8.2 181 | CM_RL2 equ 0xC8.0 182 | CY equ 0xD0.7 183 | AC equ 0xD0.6 184 | F0 equ 0xD0.5 185 | RS1 equ 0xD0.4 186 | RS0 equ 0xD0.3 187 | OV equ 0xD0.2 188 | P equ 0xD0.0 189 | PWMRUN equ 0xD8.7 190 | LOAD equ 0xD8.6 191 | PWMF equ 0xD8.5 192 | CLRPWM equ 0xD8.4 193 | ADCF equ 0xE8.7 194 | ADCS equ 0xE8.6 195 | ETGSEL1 equ 0xE8.5 196 | ETGSEL0 equ 0xE8.4 197 | ADCHS3 equ 0xE8.3 198 | ADCHS2 equ 0xE8.2 199 | ADCHS1 equ 0xE8.1 200 | ADCHS0 equ 0xE8.0 201 | SM0_1 equ 0xF8.7 202 | FE_1 equ 0xF8.7 203 | SM1_1 equ 0xF8.6 204 | SM2_1 equ 0xF8.5 205 | REN_1 equ 0xF8.4 206 | TB8_1 equ 0xF8.3 207 | RB8_1 equ 0xF8.2 208 | TI_1 equ 0xF8.1 209 | RI_1 equ 0xF8.0 210 | 211 | ; xdata 212 | 213 | -------------------------------------------------------------------------------- /naken_asm-headers/n76e616.inc: -------------------------------------------------------------------------------- 1 | P0 equ 0x80 2 | SP equ 0x81 3 | DPL equ 0x82 4 | DPH equ 0x83 5 | RWK equ 0x86 6 | PCON equ 0x87 7 | TCON equ 0x88 8 | TMOD equ 0x89 9 | TL0 equ 0x8A 10 | TL1 equ 0x8B 11 | TH0 equ 0x8C 12 | TH1 equ 0x8D 13 | CKCON equ 0x8E 14 | WKCON equ 0x8F 15 | P1 equ 0x90 16 | CKDIV equ 0x95 17 | CKSWT equ 0x96 18 | CKEN equ 0x97 19 | SCON equ 0x98 20 | SBUF equ 0x99 21 | SBUF_1 equ 0x9A 22 | EIE equ 0x9B 23 | EIE1 equ 0x9C 24 | CHPCON equ 0x9F 25 | P2 equ 0xA0 26 | AUXR1 equ 0xA2 27 | BODCON0 equ 0xA3 28 | IAPTRG equ 0xA4 29 | IAPUEN equ 0xA5 30 | IAPAL equ 0xA6 31 | IAPAH equ 0xA7 32 | IE equ 0xA8 33 | SADDR equ 0xA9 34 | WDCON equ 0xAA 35 | BODCON1 equ 0xAB 36 | P3M1 equ 0xAC 37 | P3S equ 0xAC 38 | P3M2 equ 0xAD 39 | IAPFD equ 0xAE 40 | IAPCN equ 0xAF 41 | P3 equ 0xB0 42 | P0M1 equ 0xB1 43 | P0S equ 0xB1 44 | P0M2 equ 0xB2 45 | P1M1 equ 0xB3 46 | P1S equ 0xB3 47 | P1M2 equ 0xB4 48 | P2M1 equ 0xB5 49 | P2S equ 0xB5 50 | P2M2 equ 0xB6 51 | IPH equ 0xB7 52 | IP equ 0xB8 53 | SADEN equ 0xB9 54 | SADEN_1 equ 0xBA 55 | SADDR_1 equ 0xBB 56 | I2DAT equ 0xBC 57 | I2STAT equ 0xBD 58 | I2CLK equ 0xBE 59 | I2TOC equ 0xBF 60 | I2CON equ 0xC0 61 | I2ADDR equ 0xC1 62 | ADCRL equ 0xC2 63 | ADCRH equ 0xC3 64 | T3CON equ 0xC4 65 | R3L equ 0xC5 66 | R3H equ 0xC6 67 | TA equ 0xC7 68 | T2CON equ 0xC8 69 | T2MOD0 equ 0xC9 70 | T2MOD1 equ 0xCA 71 | T2OE equ 0xCB 72 | R2AL equ 0xCC 73 | R2AH equ 0xCD 74 | R2BL equ 0xCE 75 | R2BH equ 0xCF 76 | PSW equ 0xD0 77 | R2CL equ 0xD4 78 | R2CH equ 0xD5 79 | R2DL equ 0xD6 80 | R2DH equ 0xD7 81 | P5 equ 0xD8 82 | P4 equ 0xD9 83 | P4M1 equ 0xDA 84 | P4S equ 0xDA 85 | P4M2 equ 0xDB 86 | P5M1 equ 0xDC 87 | P5S equ 0xDC 88 | P5M2 equ 0xDD 89 | ACC equ 0xE0 90 | ADCCON1 equ 0xE1 91 | ADCCON2 equ 0xE2 92 | ADCMPL equ 0xE3 93 | ADCMPH equ 0xE4 94 | LCDSEG0 equ 0xE5 95 | LCDSEG1 equ 0xE6 96 | LCDSEG2 equ 0xE7 97 | ADCCON0 equ 0xE8 98 | PICON equ 0xE9 99 | PINEN equ 0xEA 100 | PIPEN equ 0xEB 101 | PIF equ 0xEC 102 | PITYP equ 0xED 103 | LCDSEG3 equ 0xEE 104 | EIP equ 0xEF 105 | B equ 0xF0 106 | ADCAQT equ 0xF2 107 | P0DIDS equ 0xF6 108 | EIPH equ 0xF7 109 | SCON_1 equ 0xF8 110 | LCDCON equ 0xF9 111 | LCDCLK equ 0xFA 112 | LCDPTR equ 0xFB 113 | LCDDAT equ 0xFC 114 | EIP1 equ 0xFE 115 | EIPH1 equ 0xFF 116 | 117 | ; bit aliases 118 | 119 | TF1 equ 0x88.7 120 | TR1 equ 0x88.6 121 | TF0 equ 0x88.5 122 | TR0 equ 0x88.4 123 | IE1 equ 0x88.3 124 | IT1 equ 0x88.2 125 | IE0 equ 0x88.1 126 | IT0 equ 0x88.0 127 | SM0 equ 0x98.7 128 | FE equ 0x98.7 129 | SM1 equ 0x98.6 130 | SM2 equ 0x98.5 131 | REN equ 0x98.4 132 | TB8 equ 0x98.3 133 | RB8 equ 0x98.2 134 | TI equ 0x98.1 135 | RI equ 0x98.0 136 | EA equ 0xA8.7 137 | EADC equ 0xA8.6 138 | EBOD equ 0xA8.5 139 | ES equ 0xA8.4 140 | ET1 equ 0xA8.3 141 | EX1 equ 0xA8.2 142 | ET0 equ 0xA8.1 143 | EX0 equ 0xA8.0 144 | PADC equ 0xB8.6 145 | PBOD equ 0xB8.5 146 | PS equ 0xB8.4 147 | PT1 equ 0xB8.3 148 | PX1 equ 0xB8.2 149 | PT0 equ 0xB8.1 150 | PX0 equ 0xB8.0 151 | I2CEN equ 0xC0.6 152 | STA equ 0xC0.5 153 | STO equ 0xC0.4 154 | SI equ 0xC0.3 155 | AA equ 0xC0.2 156 | TF2D equ 0xC8.7 157 | TF2C equ 0xC8.6 158 | TF2B equ 0xC8.5 159 | TF2A equ 0xC8.4 160 | TR2D equ 0xC8.3 161 | TR2C equ 0xC8.2 162 | TR2B equ 0xC8.1 163 | TR2A equ 0xC8.0 164 | CY equ 0xD0.7 165 | AC equ 0xD0.6 166 | F0 equ 0xD0.5 167 | RS1 equ 0xD0.4 168 | RS0 equ 0xD0.3 169 | OV equ 0xD0.2 170 | P equ 0xD0.0 171 | ADCF equ 0xE8.7 172 | ADCS equ 0xE8.6 173 | ADCHS3 equ 0xE8.3 174 | ADCHS2 equ 0xE8.2 175 | ADCHS1 equ 0xE8.1 176 | ADCHS0 equ 0xE8.0 177 | SM0_1 equ 0xF8.7 178 | FE_1 equ 0xF8.7 179 | SM1_1 equ 0xF8.6 180 | SM2_1 equ 0xF8.5 181 | REN_1 equ 0xF8.4 182 | TB8_1 equ 0xF8.3 183 | RB8_1 equ 0xF8.2 184 | TI_1 equ 0xF8.1 185 | RI_1 equ 0xF8.0 186 | AIN0 equ 0x80.0 187 | T0 equ 0x80.0 188 | AIN1 equ 0x80.1 189 | INT0 equ 0x80.1 190 | AIN2 equ 0x80.2 191 | AIN3 equ 0x80.3 192 | AIN4 equ 0x80.4 193 | AIN5 equ 0x80.5 194 | AIN6 equ 0x80.6 195 | AIN7 equ 0x80.7 196 | CLO equ 0x80.7 197 | INT1 equ 0x90.3 198 | T1 equ 0x90.4 199 | T2AO1 equ 0x90.5 200 | T2AO2 equ 0x90.6 201 | T2BO1 equ 0x90.7 202 | T2BO2 equ 0xA0.0 203 | RXD equ 0xA0.1 204 | TXD equ 0xA0.2 205 | SDA equ 0xA0.3 206 | SCL equ 0xA0.4 207 | T2CO1 equ 0xA0.6 208 | T2CO2 equ 0xA0.7 209 | T2DO1 equ 0xB0.0 210 | T2DO2 equ 0xB0.1 211 | STADC equ 0xD8.0 212 | RXD_1 equ 0xD8.6 213 | TXD_1 equ 0xD8.7 214 | 215 | ; xdata 216 | 217 | -------------------------------------------------------------------------------- /naken_asm-headers/n76e885.inc: -------------------------------------------------------------------------------- 1 | P0 equ 0x80 2 | SP equ 0x81 3 | DPL equ 0x82 4 | DPH equ 0x83 5 | RWK equ 0x86 6 | PCON equ 0x87 7 | TCON equ 0x88 8 | TMOD equ 0x89 9 | TL0 equ 0x8A 10 | TL1 equ 0x8B 11 | TH0 equ 0x8C 12 | TH1 equ 0x8D 13 | CKCON equ 0x8E 14 | WKCON equ 0x8F 15 | P1 equ 0x90 16 | SFRS equ 0x91 17 | CAPCON0 equ 0x92 18 | CAPCON1 equ 0x93 19 | CAPCON2 equ 0x94 20 | CKDIV equ 0x95 21 | CKSWT equ 0x96 22 | CKEN equ 0x97 23 | SCON equ 0x98 24 | SBUF equ 0x99 25 | SBUF_1 equ 0x9A 26 | EIE equ 0x9B 27 | EIE1 equ 0x9C 28 | CHPCON equ 0x9F 29 | P2 equ 0xA0 30 | AUXR1 equ 0xA2 31 | BODCON0 equ 0xA3 32 | IAPTRG equ 0xA4 33 | IAPUEN equ 0xA5 34 | IAPAL equ 0xA6 35 | IAPAH equ 0xA7 36 | IE equ 0xA8 37 | SADDR equ 0xA9 38 | WDCON equ 0xAA 39 | BODCON1 equ 0xAB 40 | P3M1 equ 0xAC 41 | P3S equ 0xAC 42 | P3M2 equ 0xAD 43 | P3SR equ 0xAD 44 | IAPFD equ 0xAE 45 | IAPCN equ 0xAF 46 | P3 equ 0xB0 47 | P0M1 equ 0xB1 48 | P0S equ 0xB1 49 | P0M2 equ 0xB2 50 | P0SR equ 0xB2 51 | P1M1 equ 0xB3 52 | P1S equ 0xB3 53 | P1M2 equ 0xB4 54 | P1SR equ 0xB4 55 | P2M1 equ 0xB5 56 | P2S equ 0xB5 57 | P2M2 equ 0xB6 58 | P2SR equ 0xB6 59 | IPH equ 0xB7 60 | IP equ 0xB8 61 | SADEN equ 0xB9 62 | SADEN_1 equ 0xBA 63 | SADDR_1 equ 0xBB 64 | I2DAT equ 0xBC 65 | I2STAT equ 0xBD 66 | I2CLK equ 0xBE 67 | I2TOC equ 0xBF 68 | I2CON equ 0xC0 69 | I2ADDR equ 0xC1 70 | ADCRL equ 0xC2 71 | ADCRH equ 0xC3 72 | T3CON equ 0xC4 73 | RL3 equ 0xC5 74 | RH3 equ 0xC6 75 | TA equ 0xC7 76 | T2CON equ 0xC8 77 | T2MOD equ 0xC9 78 | RCMP2L equ 0xCA 79 | RCMP2H equ 0xCB 80 | TL2 equ 0xCC 81 | TH2 equ 0xCD 82 | ADCMPL equ 0xCE 83 | ADCMPH equ 0xCF 84 | PSW equ 0xD0 85 | PWMPH equ 0xD1 86 | PWM01H equ 0xD2 87 | PWM23H equ 0xD3 88 | PWM67H equ 0xD4 89 | PWM45H equ 0xD5 90 | PNP equ 0xD6 91 | FBD equ 0xD7 92 | PWMCON0 equ 0xD8 93 | PWMPL equ 0xD9 94 | PWM01L equ 0xDA 95 | PWM23L equ 0xDB 96 | PWM67L equ 0xDC 97 | PWM45L equ 0xDD 98 | PIO equ 0xDE 99 | PWMCON1 equ 0xDF 100 | ACC equ 0xE0 101 | ADCCON1 equ 0xE1 102 | ADCCON2 equ 0xE2 103 | ADCDLY equ 0xE3 104 | C0L equ 0xE4 105 | C0H equ 0xE5 106 | C1L equ 0xE6 107 | C1H equ 0xE7 108 | ADCCON0 equ 0xE8 109 | PICON equ 0xE9 110 | PINEN equ 0xEA 111 | PIPEN equ 0xEB 112 | PIF equ 0xEC 113 | C2L equ 0xED 114 | C2H equ 0xEE 115 | EIP equ 0xEF 116 | B equ 0xF0 117 | ADCAQT equ 0xF2 118 | SPCR equ 0xF3 119 | SPSR equ 0xF4 120 | SPDR equ 0xF5 121 | P0DIDS equ 0xF6 122 | EIPH equ 0xF7 123 | SCON_1 equ 0xF8 124 | PDTEN equ 0xF9 125 | PDTCNT equ 0xFA 126 | PMEN equ 0xFB 127 | PMD equ 0xFC 128 | EIP1 equ 0xFE 129 | EIPH1 equ 0xFF 130 | 131 | ; bit aliases 132 | 133 | SM0_1 equ 0xF8.7 134 | FE_1 equ 0xF8.7 135 | SM1_1 equ 0xF8.6 136 | SM2_1 equ 0xF8.5 137 | REN_1 equ 0xF8.4 138 | TB8_1 equ 0xF8.3 139 | RB8_1 equ 0xF8.2 140 | TI_1 equ 0xF8.1 141 | RI_1 equ 0xF8.0 142 | ADCF equ 0xE8.7 143 | ADCS equ 0xE8.6 144 | ETGSEL1 equ 0xE8.5 145 | ETGSEL0 equ 0xE8.4 146 | ADCHS3 equ 0xE8.3 147 | ADCHS2 equ 0xE8.2 148 | ADCHS1 equ 0xE8.1 149 | ADCHS0 equ 0xE8.0 150 | PWMRUN equ 0xD8.7 151 | LOAD equ 0xD8.6 152 | PWMF equ 0xD8.5 153 | CLRPWM equ 0xD8.4 154 | INTTYP1 equ 0xD8.3 155 | INTTYP0 equ 0xD8.2 156 | INTSEL1 equ 0xD8.1 157 | INTSEL0 equ 0xD8.0 158 | CY equ 0xD0.7 159 | AC equ 0xD0.6 160 | F0 equ 0xD0.5 161 | RS1 equ 0xD0.4 162 | RS0 equ 0xD0.3 163 | OV equ 0xD0.2 164 | P equ 0xD0.0 165 | TF2 equ 0xC8.7 166 | TR2 equ 0xC8.2 167 | CM_CR2 equ 0xC8.0 168 | I2CEN equ 0xC0.6 169 | STA equ 0xC0.5 170 | STO equ 0xC0.4 171 | SI equ 0xC0.3 172 | AA equ 0xC0.2 173 | PADC equ 0xB8.6 174 | PBOD equ 0xB8.5 175 | PS equ 0xB8.4 176 | PT1 equ 0xB8.3 177 | PX1 equ 0xB8.2 178 | PT0 equ 0xB8.1 179 | PX0 equ 0xB8.0 180 | EA equ 0xA8.7 181 | EADC equ 0xA8.6 182 | EBOD equ 0xA8.5 183 | ES equ 0xA8.4 184 | ET1 equ 0xA8.3 185 | EX1 equ 0xA8.2 186 | ET0 equ 0xA8.1 187 | EX0 equ 0xA8.0 188 | RXD equ 0xA0.0 189 | T0 equ 0xA0.0 190 | IC0 equ 0xA0.0 191 | AIN9 equ 0xA0.0 192 | MOSI equ 0xA0.1 193 | T1 equ 0xA0.1 194 | IC1 equ 0xA0.1 195 | MISO equ 0xA0.2 196 | IC2 equ 0xA0.2 197 | SDA equ 0xA0.3 198 | FB equ 0xA0.3 199 | STADC equ 0xA0.3 200 | RXD_1 equ 0xA0.4 201 | TXD_1 equ 0xA0.5 202 | CLO equ 0xA0.6 203 | AIN8 equ 0xA0.6 204 | PWM7 equ 0xA0.6 205 | SM0 equ 0x98.7 206 | FE equ 0x98.7 207 | SM1 equ 0x98.6 208 | SM2 equ 0x98.5 209 | REN equ 0x98.4 210 | TB8 equ 0x98.3 211 | RB8 equ 0x98.2 212 | TI equ 0x98.1 213 | RI equ 0x98.0 214 | PWM0 equ 0x90.0 215 | PWM1 equ 0x90.1 216 | TF1 equ 0x88.7 217 | TR1 equ 0x88.6 218 | TF0 equ 0x88.5 219 | TR0 equ 0x88.4 220 | IE1 equ 0x88.3 221 | IT1 equ 0x88.2 222 | IE0 equ 0x88.1 223 | IT0 equ 0x88.0 224 | INT0 equ 0x80.0 225 | AIN0 equ 0x80.0 226 | VREF equ 0x80.0 227 | INT1 equ 0x80.1 228 | AIN1 equ 0x80.1 229 | PWM2 equ 0x80.2 230 | AIN2 equ 0x80.2 231 | PWM3 equ 0x80.3 232 | TXD equ 0x80.3 233 | AIN3 equ 0x80.3 234 | SS equ 0x80.4 235 | AIN4 equ 0x80.4 236 | PWM4 equ 0x80.5 237 | SPICK equ 0x80.5 238 | AIN5 equ 0x80.5 239 | SCL equ 0x80.6 240 | AIN6 equ 0x80.6 241 | PWM5 equ 0x80.6 242 | AIN7 equ 0x80.7 243 | PWM6 equ 0x80.7 244 | 245 | ; xdata 246 | 247 | -------------------------------------------------------------------------------- /naken_asm-headers/stc10fxx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC10Fxx/STC11Fxx/STC12C52xx/STC12C5Axx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC10Fxx / STC11Fxx / STC12C52xx / STC12C5Axx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | ACC equ 0xE0 13 | B equ 0xF0 14 | PSW equ 0xD0 15 | SP equ 0x81 16 | DPL equ 0x82 17 | DPH equ 0x83 18 | PCON equ 0x87 19 | AUXR equ 0x8E 20 | AUXR1 equ 0xA2 21 | WAKE_CLKO equ 0x8F 22 | CLK_DIV equ 0x97 23 | BUS_SPEED equ 0xA1 24 | IE equ 0xA8 25 | IE2 equ 0xAF 26 | IP equ 0xB8 27 | IPH equ 0xB7 28 | IP2 equ 0xB5 29 | IPH2 equ 0xB6 30 | P0 equ 0x80 31 | P0M0 equ 0x94 32 | P0M1 equ 0x93 33 | P1 equ 0x90 34 | P1M0 equ 0x92 35 | P1M1 equ 0x91 36 | P1ASF equ 0x9D 37 | P2 equ 0xA0 38 | P2M0 equ 0x96 39 | P2M1 equ 0x95 40 | P3 equ 0xB0 41 | P3M0 equ 0xB2 42 | P3M1 equ 0xB1 43 | P4 equ 0xC0 44 | P4M0 equ 0xB4 45 | P4M1 equ 0xB3 46 | P4SW equ 0xBB 47 | P5 equ 0xC8 48 | P5M0 equ 0xCA 49 | P5M1 equ 0xC9 50 | TCON equ 0x88 51 | TMOD equ 0x89 52 | TL0 equ 0x8A 53 | TH0 equ 0x8C 54 | TL1 equ 0x8B 55 | TH1 equ 0x8D 56 | SCON equ 0x98 57 | SBUF equ 0x99 58 | SADEN equ 0xB9 59 | SADDR equ 0xA9 60 | S2CON equ 0x9A 61 | S2BUF equ 0x9B 62 | BRT equ 0x9C 63 | WDT_CONTR equ 0xC1 64 | CCON equ 0xD8 65 | CMOD equ 0xD9 66 | CL equ 0xE9 67 | CH equ 0xF9 68 | CCAPM0 equ 0xDA 69 | CCAPM1 equ 0xDB 70 | CCAP0L equ 0xEA 71 | CCAP0H equ 0xFA 72 | CCAP1L equ 0xEB 73 | CCAP1H equ 0xFB 74 | PCA_PWM0 equ 0xF2 75 | PCA_PWM1 equ 0xF3 76 | ADC_CONTR equ 0xBC 77 | ADC_RES equ 0xBD 78 | ADC_RESL equ 0xBE 79 | SPCTL equ 0xCE 80 | SPSTAT equ 0xCD 81 | SPDAT equ 0xCF 82 | IAP_DATA equ 0xC2 83 | IAP_ADDRH equ 0xC3 84 | IAP_ADDRL equ 0xC4 85 | IAP_CMD equ 0xC5 86 | IAP_TRIG equ 0xC6 87 | IAP_CONTR equ 0xC7 88 | 89 | ; bit aliases 90 | 91 | CY equ 0xD0.7 92 | AC equ 0xD0.6 93 | F0 equ 0xD0.5 94 | RS1 equ 0xD0.4 95 | RS0 equ 0xD0.3 96 | OV equ 0xD0.2 97 | F1 equ 0xD0.1 98 | P equ 0xD0.0 99 | EA equ 0xA8.7 100 | ELVD equ 0xA8.6 101 | EADC equ 0xA8.5 102 | ES equ 0xA8.4 103 | ET1 equ 0xA8.3 104 | EX1 equ 0xA8.2 105 | ET0 equ 0xA8.1 106 | EX0 equ 0xA8.0 107 | PPCA equ 0xB8.7 108 | PLVD equ 0xB8.6 109 | PADC equ 0xB8.5 110 | PS equ 0xB8.4 111 | PT1 equ 0xB8.3 112 | PX1 equ 0xB8.2 113 | PT0 equ 0xB8.1 114 | PX0 equ 0xB8.0 115 | TF1 equ 0x88.7 116 | TR1 equ 0x88.6 117 | TF0 equ 0x88.5 118 | TR0 equ 0x88.4 119 | IE1 equ 0x88.3 120 | IT1 equ 0x88.2 121 | IE0 equ 0x88.1 122 | IT0 equ 0x88.0 123 | SM0 equ 0x98.7 124 | SM1 equ 0x98.6 125 | SM2 equ 0x98.5 126 | REN equ 0x98.4 127 | TB8 equ 0x98.3 128 | RB8 equ 0x98.2 129 | TI equ 0x98.1 130 | RI equ 0x98.0 131 | CF equ 0xD8.7 132 | CR equ 0xD8.6 133 | CCF1 equ 0xD8.1 134 | CCF0 equ 0xD8.0 135 | 136 | ; xdata 137 | 138 | -------------------------------------------------------------------------------- /naken_asm-headers/stc12c20xx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC12C20xx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC12C20xx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | WDT_CONTR equ 0xe1 13 | ISP_DATA equ 0xe2 14 | ISP_ADDRH equ 0xe3 15 | ISP_ADDRL equ 0xe4 16 | ISP_CMD equ 0xe5 17 | ISP_TRIG equ 0xe6 18 | ISP_CONTR equ 0xe7 19 | IDLE_CLK equ 0xc7 20 | WAKE_CLKO equ 0x8F 21 | P0M0 equ 0x93 22 | P0M1 equ 0x94 23 | P1M0 equ 0x91 24 | P1M1 equ 0x92 25 | P2M0 equ 0x95 26 | P2M1 equ 0x96 27 | P3M0 equ 0xb1 28 | P3M1 equ 0xb2 29 | SPSTAT equ 0x84 30 | SPCTL equ 0x85 31 | SPDAT equ 0x86 32 | ADC_CONTR equ 0xc5 33 | ADC_DATA equ 0xc6 34 | ADC_LOW2 equ 0xbe 35 | CCON equ 0xD8 36 | CMOD equ 0xD9 37 | CCAPM0 equ 0xDA 38 | CCAPM1 equ 0xDB 39 | CCAPM2 equ 0xDC 40 | CCAPM3 equ 0xDD 41 | CCAPM4 equ 0xDE 42 | CCAPM5 equ 0xDF 43 | CL equ 0xE9 44 | CCAP0L equ 0xEA 45 | CCAP1L equ 0xEB 46 | CCAP2L equ 0xEC 47 | CCAP3L equ 0xED 48 | CCAP4L equ 0xEE 49 | CCAP5L equ 0xEF 50 | CH equ 0xF9 51 | CCAP0H equ 0xFA 52 | CCAP1H equ 0xFB 53 | CCAP2H equ 0xFC 54 | CCAP3H equ 0xFD 55 | CCAP4H equ 0xFE 56 | CCAP5H equ 0xFF 57 | PCA_PWM0 equ 0xF2 58 | PCA_PWM1 equ 0xF3 59 | PCA_PWM2 equ 0xF4 60 | PCA_PWM3 equ 0xF5 61 | PCA_PWM4 equ 0xF6 62 | PCA_PWM5 equ 0xF7 63 | P0 equ 0x80 64 | P1 equ 0x90 65 | P2 equ 0xA0 66 | P3 equ 0xB0 67 | PSW equ 0xD0 68 | ACC equ 0xE0 69 | B equ 0xF0 70 | SP equ 0x81 71 | DPL equ 0x82 72 | DPH equ 0x83 73 | PCON equ 0x87 74 | TCON equ 0x88 75 | TMOD equ 0x89 76 | TL0 equ 0x8A 77 | TL1 equ 0x8B 78 | TH0 equ 0x8C 79 | TH1 equ 0x8D 80 | IE equ 0xA8 81 | IP equ 0xB8 82 | SCON equ 0x98 83 | SBUF equ 0x99 84 | AUXR equ 0x8E 85 | SADDR equ 0xA9 86 | IPH equ 0xB7 87 | SADEN equ 0xB9 88 | T2CON equ 0xC8 89 | T2MOD equ 0xC9 90 | RCAP2L equ 0xCA 91 | RCAP2H equ 0xCB 92 | TL2 equ 0xCC 93 | TH2 equ 0xCD 94 | 95 | ; bit aliases 96 | 97 | CF equ 0xD8.7 98 | CR equ 0xD8.6 99 | CCF5 equ 0xD8.5 100 | CCF4 equ 0xD8.4 101 | CCF3 equ 0xD8.3 102 | CCF2 equ 0xD8.2 103 | CCF1 equ 0xD8.1 104 | CCF0 equ 0xD8.0 105 | CY equ 0xD0.7 106 | AC equ 0xD0.6 107 | F0 equ 0xD0.5 108 | RS1 equ 0xD0.4 109 | RS0 equ 0xD0.3 110 | OV equ 0xD0.2 111 | F1 equ 0xD0.1 112 | P equ 0xD0.0 113 | TF1 equ 0x88.7 114 | TR1 equ 0x88.6 115 | TF0 equ 0x88.5 116 | TR0 equ 0x88.4 117 | IE1 equ 0x88.3 118 | IT1 equ 0x88.2 119 | IE0 equ 0x88.1 120 | IT0 equ 0x88.0 121 | RD equ 0xB0.7 122 | WR equ 0xB0.6 123 | T1 equ 0xB0.5 124 | T0 equ 0xB0.4 125 | INT1 equ 0xB0.3 126 | INT0 equ 0xB0.2 127 | TXD equ 0xB0.1 128 | RXD equ 0xB0.0 129 | SM0 equ 0x98.7 130 | FE equ 0x98.7 131 | SM1 equ 0x98.6 132 | SM2 equ 0x98.5 133 | REN equ 0x98.4 134 | TB8 equ 0x98.3 135 | RB8 equ 0x98.2 136 | TI equ 0x98.1 137 | RI equ 0x98.0 138 | T2EX equ 0x90.1 139 | T2 equ 0x90.0 140 | TF2 equ 0xC8.7 141 | EXF2 equ 0xC8.6 142 | RCLK equ 0xC8.5 143 | TCLK equ 0xC8.4 144 | EXEN2 equ 0xC8.3 145 | TR2 equ 0xC8.2 146 | C_T2 equ 0xC8.1 147 | CP_RL2 equ 0xC8.0 148 | CEX3 equ 0xA0.4 149 | CEX2 equ 0xA0.0 150 | CEX1 equ 0xB0.5 151 | CEX0 equ 0xB0.7 152 | ECI equ 0xB0.4 153 | EA equ 0xA8.7 154 | EPCA_LVD equ 0xA8.6 155 | EADC_SPI equ 0xA8.5 156 | ES equ 0xA8.4 157 | ET1 equ 0xA8.3 158 | EX1 equ 0xA8.2 159 | ET0 equ 0xA8.1 160 | EX0 equ 0xA8.0 161 | PPCA_LVD equ 0xB8.6 162 | PADC_SPI equ 0xB8.5 163 | PS equ 0xB8.4 164 | PT1 equ 0xB8.3 165 | PX1 equ 0xB8.2 166 | PT0 equ 0xB8.1 167 | PX0 equ 0xB8.0 168 | 169 | ; xdata 170 | 171 | -------------------------------------------------------------------------------- /naken_asm-headers/stc12c54xx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC12C54xx/STC12C56xx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC12C54xx / STC12C56xx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | WDT_CONTR equ 0xe1 13 | ISP_DATA equ 0xe2 14 | ISP_ADDRH equ 0xe3 15 | ISP_ADDRL equ 0xe4 16 | ISP_CMD equ 0xe5 17 | ISP_TRIG equ 0xe6 18 | ISP_CONTR equ 0xe7 19 | CLK_DIV equ 0xc7 20 | P0M0 equ 0x93 21 | P0M1 equ 0x94 22 | P1M0 equ 0x91 23 | P1M1 equ 0x92 24 | P2M0 equ 0x95 25 | P2M1 equ 0x96 26 | P3M0 equ 0xb1 27 | P3M1 equ 0xb2 28 | SPSTAT equ 0x84 29 | SPCTL equ 0x85 30 | SPDAT equ 0x86 31 | ADC_CONTR equ 0xc5 32 | ADC_DATA equ 0xc6 33 | ADC_LOW2 equ 0xbe 34 | CCON equ 0xD8 35 | CMOD equ 0xD9 36 | CCAPM0 equ 0xDA 37 | CCAPM1 equ 0xDB 38 | CCAPM2 equ 0xDC 39 | CCAPM3 equ 0xDD 40 | CCAPM4 equ 0xDE 41 | CCAPM5 equ 0xDF 42 | CL equ 0xE9 43 | CCAP0L equ 0xEA 44 | CCAP1L equ 0xEB 45 | CCAP2L equ 0xEC 46 | CCAP3L equ 0xED 47 | CCAP4L equ 0xEE 48 | CCAP5L equ 0xEF 49 | CH equ 0xF9 50 | CCAP0H equ 0xFA 51 | CCAP1H equ 0xFB 52 | CCAP2H equ 0xFC 53 | CCAP3H equ 0xFD 54 | CCAP4H equ 0xFE 55 | CCAP5H equ 0xFF 56 | PCA_PWM0 equ 0xF2 57 | PCA_PWM1 equ 0xF3 58 | PCA_PWM2 equ 0xF4 59 | PCA_PWM3 equ 0xF5 60 | PCA_PWM4 equ 0xF6 61 | PCA_PWM5 equ 0xF7 62 | P0 equ 0x80 63 | P1 equ 0x90 64 | P2 equ 0xA0 65 | P3 equ 0xB0 66 | PSW equ 0xD0 67 | ACC equ 0xE0 68 | B equ 0xF0 69 | SP equ 0x81 70 | DPL equ 0x82 71 | DPH equ 0x83 72 | PCON equ 0x87 73 | TCON equ 0x88 74 | TMOD equ 0x89 75 | TL0 equ 0x8A 76 | TL1 equ 0x8B 77 | TH0 equ 0x8C 78 | TH1 equ 0x8D 79 | IE equ 0xA8 80 | IP equ 0xB8 81 | SCON equ 0x98 82 | SBUF equ 0x99 83 | AUXR equ 0x8E 84 | SADDR equ 0xA9 85 | IPH equ 0xB7 86 | SADEN equ 0xB9 87 | T2CON equ 0xC8 88 | T2MOD equ 0xC9 89 | RCAP2L equ 0xCA 90 | RCAP2H equ 0xCB 91 | TL2 equ 0xCC 92 | TH2 equ 0xCD 93 | 94 | ; bit aliases 95 | 96 | CF equ 0xD8.7 97 | CR equ 0xD8.6 98 | CCF5 equ 0xD8.5 99 | CCF4 equ 0xD8.4 100 | CCF3 equ 0xD8.3 101 | CCF2 equ 0xD8.2 102 | CCF1 equ 0xD8.1 103 | CCF0 equ 0xD8.0 104 | CY equ 0xD0.7 105 | AC equ 0xD0.6 106 | F0 equ 0xD0.5 107 | RS1 equ 0xD0.4 108 | RS0 equ 0xD0.3 109 | OV equ 0xD0.2 110 | F1 equ 0xD0.1 111 | P equ 0xD0.0 112 | TF1 equ 0x88.7 113 | TR1 equ 0x88.6 114 | TF0 equ 0x88.5 115 | TR0 equ 0x88.4 116 | IE1 equ 0x88.3 117 | IT1 equ 0x88.2 118 | IE0 equ 0x88.1 119 | IT0 equ 0x88.0 120 | RD equ 0xB0.7 121 | WR equ 0xB0.6 122 | T1 equ 0xB0.5 123 | T0 equ 0xB0.4 124 | INT1 equ 0xB0.3 125 | INT0 equ 0xB0.2 126 | TXD equ 0xB0.1 127 | RXD equ 0xB0.0 128 | SM0 equ 0x98.7 129 | FE equ 0x98.7 130 | SM1 equ 0x98.6 131 | SM2 equ 0x98.5 132 | REN equ 0x98.4 133 | TB8 equ 0x98.3 134 | RB8 equ 0x98.2 135 | TI equ 0x98.1 136 | RI equ 0x98.0 137 | T2EX equ 0x90.1 138 | T2 equ 0x90.0 139 | TF2 equ 0xC8.7 140 | EXF2 equ 0xC8.6 141 | RCLK equ 0xC8.5 142 | TCLK equ 0xC8.4 143 | EXEN2 equ 0xC8.3 144 | TR2 equ 0xC8.2 145 | C_T2 equ 0xC8.1 146 | CP_RL2 equ 0xC8.0 147 | CEX3 equ 0xA0.4 148 | CEX2 equ 0xA0.0 149 | CEX1 equ 0xB0.5 150 | CEX0 equ 0xB0.7 151 | ECI equ 0xB0.4 152 | EA equ 0xA8.7 153 | EPCA_LVD equ 0xA8.6 154 | EADC_SPI equ 0xA8.5 155 | ES equ 0xA8.4 156 | ET1 equ 0xA8.3 157 | EX1 equ 0xA8.2 158 | ET0 equ 0xA8.1 159 | EX0 equ 0xA8.0 160 | PPCA_LVD equ 0xB8.6 161 | PADC_SPI equ 0xB8.5 162 | PS equ 0xB8.4 163 | PT1 equ 0xB8.3 164 | PX1 equ 0xB8.2 165 | PT0 equ 0xB8.1 166 | PX0 equ 0xB8.0 167 | 168 | ; xdata 169 | 170 | -------------------------------------------------------------------------------- /naken_asm-headers/stc12h.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC12H include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC12H 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | P0 equ 0x80 13 | SP equ 0x81 14 | DPL equ 0x82 15 | DPH equ 0x83 16 | S4CON equ 0x84 17 | S4BUF equ 0x85 18 | PCON equ 0x87 19 | TCON equ 0x88 20 | TMOD equ 0x89 21 | TL0 equ 0x8a 22 | TL1 equ 0x8b 23 | TH0 equ 0x8c 24 | TH1 equ 0x8d 25 | AUXR equ 0x8e 26 | INTCLKO equ 0x8f 27 | P1 equ 0x90 28 | P1M1 equ 0x91 29 | P1M0 equ 0x92 30 | P0M1 equ 0x93 31 | P0M0 equ 0x94 32 | P2M1 equ 0x95 33 | P2M0 equ 0x96 34 | SCON equ 0x98 35 | SBUF equ 0x99 36 | S2CON equ 0x9a 37 | S2BUF equ 0x9b 38 | IRCBAND equ 0x9d 39 | LIRTRIM equ 0x9e 40 | IRTRIM equ 0x9f 41 | P2 equ 0xa0 42 | P_SW1 equ 0xa2 43 | IE equ 0xa8 44 | SADDR equ 0xa9 45 | WKTCL equ 0xaa 46 | WKTCH equ 0xab 47 | S3CON equ 0xac 48 | S3BUF equ 0xad 49 | TA equ 0xae 50 | IE2 equ 0xaf 51 | P3 equ 0xb0 52 | P3M1 equ 0xb1 53 | P3M0 equ 0xb2 54 | P4M1 equ 0xb3 55 | P4M0 equ 0xb4 56 | IP2 equ 0xb5 57 | IP2H equ 0xb6 58 | IPH equ 0xb7 59 | IP equ 0xb8 60 | SADEN equ 0xb9 61 | P_SW2 equ 0xba 62 | VOCTRL equ 0xbb 63 | ADC_CONTR equ 0xbc 64 | ADC_RES equ 0xbd 65 | ADC_RESL equ 0xbe 66 | P4 equ 0xc0 67 | WDT_CONTR equ 0xc1 68 | IAP_DATA equ 0xc2 69 | IAP_ADDRH equ 0xc3 70 | IAP_ADDRL equ 0xc4 71 | IAP_CMD equ 0xc5 72 | IAP_TRIG equ 0xc6 73 | IAP_CONTR equ 0xc7 74 | P5 equ 0xc8 75 | P5M1 equ 0xc9 76 | P5M0 equ 0xca 77 | P6M1 equ 0xcb 78 | P6M0 equ 0xcc 79 | SPSTAT equ 0xcd 80 | SPCTL equ 0xce 81 | SPDAT equ 0xcf 82 | PSW equ 0xd0 83 | T4T3M equ 0xd1 84 | T4H equ 0xd2 85 | T4L equ 0xd3 86 | T3H equ 0xd4 87 | T3L equ 0xd5 88 | T2H equ 0xd6 89 | T2L equ 0xd7 90 | CCON equ 0xd8 91 | CMOD equ 0xd9 92 | CCAPM0 equ 0xda 93 | CCAPM1 equ 0xdb 94 | CCAPM2 equ 0xdc 95 | ADCCFG equ 0xde 96 | IP3 equ 0xdf 97 | ACC equ 0xe0 98 | P7M1 equ 0xe1 99 | P7M0 equ 0xe2 100 | DPS equ 0xe3 101 | DPL1 equ 0xe4 102 | DPH1 equ 0xe5 103 | CMPCR1 equ 0xe6 104 | CMPCR2 equ 0xe7 105 | P6 equ 0xe8 106 | CL equ 0xe9 107 | CCAP0L equ 0xea 108 | CCAP1L equ 0xeb 109 | CCAP2L equ 0xec 110 | IP3H equ 0xee 111 | AUXINTIF equ 0xef 112 | B equ 0xf0 113 | PCA_PWM0 equ 0xf2 114 | PCA_PWM1 equ 0xf3 115 | PCA_PWM2 equ 0xf4 116 | IAP_TPS equ 0xf5 117 | P7 equ 0xf8 118 | CH equ 0xf9 119 | CCAP0H equ 0xfa 120 | CCAP1H equ 0xfb 121 | CCAP2H equ 0xfc 122 | RSTCFG equ 0xff 123 | USBCLK equ 0xdc 124 | USBDAT equ 0xec 125 | USBCON equ 0xf4 126 | USBADR equ 0xfc 127 | 128 | ; bit aliases 129 | 130 | TF1 equ 0x88.7 131 | TR1 equ 0x88.6 132 | TF0 equ 0x88.5 133 | TR0 equ 0x88.4 134 | IE1 equ 0x88.3 135 | IT1 equ 0x88.2 136 | IE0 equ 0x88.1 137 | IT0 equ 0x88.0 138 | SM0 equ 0x98.7 139 | SM1 equ 0x98.6 140 | SM2 equ 0x98.5 141 | REN equ 0x98.4 142 | TB8 equ 0x98.3 143 | RB8 equ 0x98.2 144 | TI equ 0x98.1 145 | RI equ 0x98.0 146 | EA equ 0xa8.7 147 | ELVD equ 0xa8.6 148 | EADC equ 0xa8.5 149 | ES equ 0xa8.4 150 | ET1 equ 0xa8.3 151 | EX1 equ 0xa8.2 152 | ET0 equ 0xa8.1 153 | EX0 equ 0xa8.0 154 | PPCA equ 0xb8.7 155 | PLVD equ 0xb8.6 156 | PADC equ 0xb8.5 157 | PS equ 0xb8.4 158 | PT1 equ 0xb8.3 159 | PX1 equ 0xb8.2 160 | PT0 equ 0xb8.1 161 | PX0 equ 0xb8.0 162 | CY equ 0xd0.7 163 | AC equ 0xd0.6 164 | F0 equ 0xd0.5 165 | RS1 equ 0xd0.4 166 | RS0 equ 0xd0.3 167 | OV equ 0xd0.2 168 | P equ 0xd0.0 169 | CF equ 0xd8.7 170 | CR equ 0xd8.6 171 | CCF3 equ 0xd8.3 172 | CCF2 equ 0xd8.2 173 | CCF1 equ 0xd8.1 174 | CCF0 equ 0xd8.0 175 | 176 | ; xdata 177 | 178 | CCAPM3 equ 0xfd54 179 | CCAP3L equ 0xfd55 180 | CCAP3H equ 0xfd56 181 | PCA_PWM3 equ 0xfd57 182 | CKSEL equ 0xfe00 183 | CLKDIV equ 0xfe01 184 | IRC24MCR equ 0xfe02 185 | XOSCCR equ 0xfe03 186 | IRC32KCR equ 0xfe04 187 | MCLKOCR equ 0xfe05 188 | IRC48MCR equ 0xfe07 189 | P0PU equ 0xfe10 190 | P1PU equ 0xfe11 191 | P2PU equ 0xfe12 192 | P3PU equ 0xfe13 193 | P4PU equ 0xfe14 194 | P5PU equ 0xfe15 195 | P6PU equ 0xfe16 196 | P7PU equ 0xfe17 197 | P0NCS equ 0xfe18 198 | P1NCS equ 0xfe19 199 | P2NCS equ 0xfe1a 200 | P3NCS equ 0xfe1b 201 | P4NCS equ 0xfe1c 202 | P5NCS equ 0xfe1d 203 | P6NCS equ 0xfe1e 204 | P7NCS equ 0xfe1f 205 | P0SR equ 0xfe20 206 | P1SR equ 0xfe21 207 | P2SR equ 0xfe22 208 | P3SR equ 0xfe23 209 | P4SR equ 0xfe24 210 | P5SR equ 0xfe25 211 | P6SR equ 0xfe26 212 | P7SR equ 0xfe27 213 | P0DR equ 0xfe28 214 | P1DR equ 0xfe29 215 | P2DR equ 0xfe2a 216 | P3DR equ 0xfe2b 217 | P4DR equ 0xfe2c 218 | P5DR equ 0xfe2d 219 | P6DR equ 0xfe2e 220 | P7DR equ 0xfe2f 221 | P0IE equ 0xfe30 222 | P1IE equ 0xfe31 223 | P2IE equ 0xfe32 224 | P3IE equ 0xfe33 225 | P4IE equ 0xfe34 226 | P5IE equ 0xfe35 227 | P6IE equ 0xfe36 228 | P7IE equ 0xfe37 229 | I2CCFG equ 0xfe80 230 | I2CMSCR equ 0xfe81 231 | I2CMSST equ 0xfe82 232 | I2CSLCR equ 0xfe83 233 | I2CSLST equ 0xfe84 234 | I2CSLADR equ 0xfe85 235 | I2CTXD equ 0xfe86 236 | I2CRXD equ 0xfe87 237 | I2CMSAUX equ 0xfe88 238 | TM2PS equ 0xfea2 239 | TM3PS equ 0xfea3 240 | TM4PS equ 0xfea4 241 | ADCTIM equ 0xfea8 242 | T3T4PIN equ 0xfeac 243 | PWM1_ETRPS equ 0xfeb0 244 | PWM1_ENO equ 0xfeb1 245 | PWM1_PS equ 0xfeb2 246 | PWM1_IOAUX equ 0xfeb3 247 | PWM2_ETRPS equ 0xfeb4 248 | PWM2_ENO equ 0xfeb5 249 | PWM2_PS equ 0xfeb6 250 | PWM2_IOAUX equ 0xfeb7 251 | PWM1_CR1 equ 0xfec0 252 | PWM1_CR2 equ 0xfec1 253 | PWM1_SMCR equ 0xfec2 254 | PWM1_ETR equ 0xfec3 255 | PWM1_IER equ 0xfec4 256 | PWM1_SR1 equ 0xfec5 257 | PWM1_SR2 equ 0xfec6 258 | PWM1_EGR equ 0xfec7 259 | PWM1_CCMR1 equ 0xfec8 260 | PWM1_CCMR2 equ 0xfec9 261 | PWM1_CCMR3 equ 0xfeca 262 | PWM1_CCMR4 equ 0xfecb 263 | PWM1_CCER1 equ 0xfecc 264 | PWM1_CCER2 equ 0xfecd 265 | PWM1_CNTR equ 0xfece 266 | PWM1_CNTRH equ 0xfece 267 | PWM1_CNTRL equ 0xfecf 268 | PWM1_PSCR equ 0xfed0 269 | PWM1_PSCRH equ 0xfed0 270 | PWM1_PSCRL equ 0xfed1 271 | PWM1_ARR equ 0xfed2 272 | PWM1_ARRH equ 0xfed2 273 | PWM1_ARRL equ 0xfed3 274 | PWM1_RCR equ 0xfed4 275 | PWM1_CCR1 equ 0xfed5 276 | PWM1_CCR1H equ 0xfed5 277 | PWM1_CCR1L equ 0xfed6 278 | PWM1_CCR2 equ 0xfed7 279 | PWM1_CCR2H equ 0xfed7 280 | PWM1_CCR2L equ 0xfed8 281 | PWM1_CCR3 equ 0xfed9 282 | PWM1_CCR3H equ 0xfed9 283 | PWM1_CCR3L equ 0xfeda 284 | PWM1_CCR4 equ 0xfedb 285 | PWM1_CCR4H equ 0xfedb 286 | PWM1_CCR4L equ 0xfedc 287 | PWM1_BKR equ 0xfedd 288 | PWM1_DTR equ 0xfede 289 | PWM1_OISR equ 0xfedf 290 | PWM2_CR1 equ 0xfee0 291 | PWM2_CR2 equ 0xfee1 292 | PWM2_SMCR equ 0xfee2 293 | PWM2_ETR equ 0xfee3 294 | PWM2_IER equ 0xfee4 295 | PWM2_SR1 equ 0xfee5 296 | PWM2_SR2 equ 0xfee6 297 | PWM2_EGR equ 0xfee7 298 | PWM2_CCMR1 equ 0xfee8 299 | PWM2_CCMR2 equ 0xfee9 300 | PWM2_CCMR3 equ 0xfeea 301 | PWM2_CCMR4 equ 0xfeeb 302 | PWM2_CCER1 equ 0xfeec 303 | PWM2_CCER2 equ 0xfeed 304 | PWM2_CNTR equ 0xfeee 305 | PWM2_CNTRH equ 0xfeee 306 | PWM2_CNTRL equ 0xfeef 307 | PWM2_PSCR equ 0xfef0 308 | PWM2_PSCRH equ 0xfef0 309 | PWM2_PSCRL equ 0xfef1 310 | PWM2_ARR equ 0xfef2 311 | PWM2_ARRH equ 0xfef2 312 | PWM2_ARRL equ 0xfef3 313 | PWM2_RCR equ 0xfef4 314 | PWM2_CCR1 equ 0xfef5 315 | PWM2_CCR1H equ 0xfef5 316 | PWM2_CCR1L equ 0xfef6 317 | PWM2_CCR2 equ 0xfef7 318 | PWM2_CCR2H equ 0xfef7 319 | PWM2_CCR2L equ 0xfef8 320 | PWM2_CCR3 equ 0xfef9 321 | PWM2_CCR3H equ 0xfef9 322 | PWM2_CCR3L equ 0xfefa 323 | PWM2_CCR4 equ 0xfefb 324 | PWM2_CCR4H equ 0xfefb 325 | PWM2_CCR4L equ 0xfefc 326 | PWM2_BKR equ 0xfefd 327 | PWM2_DTR equ 0xfefe 328 | PWM2_OISR equ 0xfeff 329 | P0INTE equ 0xfd00 330 | P1INTE equ 0xfd01 331 | P2INTE equ 0xfd02 332 | P3INTE equ 0xfd03 333 | P4INTE equ 0xfd04 334 | P5INTE equ 0xfd05 335 | P6INTE equ 0xfd06 336 | P7INTE equ 0xfd07 337 | P0INTF equ 0xfd10 338 | P1INTF equ 0xfd11 339 | P2INTF equ 0xfd12 340 | P3INTF equ 0xfd13 341 | P4INTF equ 0xfd14 342 | P5INTF equ 0xfd15 343 | P6INTF equ 0xfd16 344 | P7INTF equ 0xfd17 345 | P0IM0 equ 0xfd20 346 | P1IM0 equ 0xfd21 347 | P2IM0 equ 0xfd22 348 | P3IM0 equ 0xfd23 349 | P4IM0 equ 0xfd24 350 | P5IM0 equ 0xfd25 351 | P6IM0 equ 0xfd26 352 | P7IM0 equ 0xfd27 353 | P0IM1 equ 0xfd30 354 | P1IM1 equ 0xfd31 355 | P2IM1 equ 0xfd32 356 | P3IM1 equ 0xfd33 357 | P4IM1 equ 0xfd34 358 | P5IM1 equ 0xfd35 359 | P6IM1 equ 0xfd36 360 | P7IM1 equ 0xfd37 361 | MD3 equ 0xfcf0 362 | MD2 equ 0xfcf1 363 | MD1 equ 0xfcf2 364 | MD0 equ 0xfcf3 365 | MD5 equ 0xfcf4 366 | MD4 equ 0xfcf5 367 | dwOP1 equ 0xfcf0 368 | wOP1 equ 0xfcf2 369 | wOP2 equ 0xfcf4 370 | ARCON equ 0xfcf6 371 | OPCON equ 0xfcf7 372 | PWM1 equ 0xfec0 373 | PWM2 equ 0xfee0 374 | -------------------------------------------------------------------------------- /naken_asm-headers/stc15f104e.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC15F104E/STC15F204EA include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC15F104E / STC15F204EA 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | ACC equ 0xE0 13 | B equ 0xF0 14 | PSW equ 0xD0 15 | SP equ 0x81 16 | DPL equ 0x82 17 | DPH equ 0x83 18 | P0 equ 0x80 19 | P1 equ 0x90 20 | P2 equ 0xA0 21 | P3 equ 0xB0 22 | P4 equ 0xC0 23 | P5 equ 0xC8 24 | P6 equ 0xE8 25 | P7 equ 0xF8 26 | P0M0 equ 0x94 27 | P0M1 equ 0x93 28 | P1M0 equ 0x92 29 | P1M1 equ 0x91 30 | P2M0 equ 0x96 31 | P2M1 equ 0x95 32 | P3M0 equ 0xB2 33 | P3M1 equ 0xB1 34 | P4M0 equ 0xB4 35 | P4M1 equ 0xB3 36 | P5M0 equ 0xCA 37 | P5M1 equ 0xC9 38 | P6M0 equ 0xCC 39 | P6M1 equ 0xCB 40 | P7M0 equ 0xE2 41 | P7M1 equ 0xE1 42 | PCON equ 0x87 43 | AUXR equ 0x8E 44 | AUXR1 equ 0xA2 45 | P_SW1 equ 0xA2 46 | CLK_DIV equ 0x97 47 | BUS_SPEED equ 0xA1 48 | P1ASF equ 0x9D 49 | P_SW2 equ 0xBA 50 | IRC_CLKO equ 0xBB 51 | IE equ 0xA8 52 | IP equ 0xB8 53 | IE2 equ 0xAF 54 | IP2 equ 0xB5 55 | INT_CLKO equ 0x8F 56 | TCON equ 0x88 57 | TMOD equ 0x89 58 | TL0 equ 0x8A 59 | TL1 equ 0x8B 60 | TH0 equ 0x8C 61 | TH1 equ 0x8D 62 | T4T3M equ 0xD1 63 | T3T4M equ 0xD1 64 | T4H equ 0xD2 65 | T4L equ 0xD3 66 | T3H equ 0xD4 67 | T3L equ 0xD5 68 | T2H equ 0xD6 69 | T2L equ 0xD7 70 | WKTCL equ 0xAA 71 | WKTCH equ 0xAB 72 | WDT_CONTR equ 0xC1 73 | SCON equ 0x98 74 | SBUF equ 0x99 75 | S2CON equ 0x9A 76 | S2BUF equ 0x9B 77 | S3CON equ 0xAC 78 | S3BUF equ 0xAD 79 | S4CON equ 0x84 80 | S4BUF equ 0x85 81 | SADDR equ 0xA9 82 | SADEN equ 0xB9 83 | ADC_CONTR equ 0xBC 84 | ADC_RES equ 0xBD 85 | ADC_RESL equ 0xBE 86 | SPSTAT equ 0xCD 87 | SPCTL equ 0xCE 88 | SPDAT equ 0xCF 89 | IAP_DATA equ 0xC2 90 | IAP_ADDRH equ 0xC3 91 | IAP_ADDRL equ 0xC4 92 | IAP_CMD equ 0xC5 93 | IAP_TRIG equ 0xC6 94 | IAP_CONTR equ 0xC7 95 | CCON equ 0xD8 96 | CMOD equ 0xD9 97 | CL equ 0xE9 98 | CH equ 0xF9 99 | CCAPM0 equ 0xDA 100 | CCAPM1 equ 0xDB 101 | CCAPM2 equ 0xDC 102 | CCAP0L equ 0xEA 103 | CCAP1L equ 0xEB 104 | CCAP2L equ 0xEC 105 | PCA_PWM0 equ 0xF2 106 | PCA_PWM1 equ 0xF3 107 | PCA_PWM2 equ 0xF4 108 | CCAP0H equ 0xFA 109 | CCAP1H equ 0xFB 110 | CCAP2H equ 0xFC 111 | 112 | ; bit aliases 113 | 114 | CY equ 0xD0.7 115 | AC equ 0xD0.6 116 | F0 equ 0xD0.5 117 | RS1 equ 0xD0.4 118 | RS0 equ 0xD0.3 119 | OV equ 0xD0.2 120 | F1 equ 0xD0.1 121 | P equ 0xD0.0 122 | EA equ 0xA8.7 123 | ELVD equ 0xA8.6 124 | EADC equ 0xA8.5 125 | ES equ 0xA8.4 126 | ET1 equ 0xA8.3 127 | EX1 equ 0xA8.2 128 | ET0 equ 0xA8.1 129 | EX0 equ 0xA8.0 130 | PPCA equ 0xB8.7 131 | PLVD equ 0xB8.6 132 | PADC equ 0xB8.5 133 | PS equ 0xB8.4 134 | PT1 equ 0xB8.3 135 | PX1 equ 0xB8.2 136 | PT0 equ 0xB8.1 137 | PX0 equ 0xB8.0 138 | TF1 equ 0x88.7 139 | TR1 equ 0x88.6 140 | TF0 equ 0x88.5 141 | TR0 equ 0x88.4 142 | IE1 equ 0x88.3 143 | IT1 equ 0x88.2 144 | IE0 equ 0x88.1 145 | IT0 equ 0x88.0 146 | SM0 equ 0x98.7 147 | SM1 equ 0x98.6 148 | SM2 equ 0x98.5 149 | REN equ 0x98.4 150 | TB8 equ 0x98.3 151 | RB8 equ 0x98.2 152 | TI equ 0x98.1 153 | RI equ 0x98.0 154 | CF equ 0xD8.7 155 | CR equ 0xD8.6 156 | CCF2 equ 0xD8.2 157 | CCF1 equ 0xD8.1 158 | CCF0 equ 0xD8.0 159 | 160 | ; xdata 161 | 162 | -------------------------------------------------------------------------------- /naken_asm-headers/stc15fxx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC15Fxx/STC15Wxx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC15Fxx / STC15Wxx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | ACC equ 0xE0 13 | B equ 0xF0 14 | PSW equ 0xD0 15 | SP equ 0x81 16 | DPL equ 0x82 17 | DPH equ 0x83 18 | P0 equ 0x80 19 | P1 equ 0x90 20 | P2 equ 0xA0 21 | P3 equ 0xB0 22 | P4 equ 0xC0 23 | P5 equ 0xC8 24 | P6 equ 0xE8 25 | P7 equ 0xF8 26 | P0M0 equ 0x94 27 | P0M1 equ 0x93 28 | P1M0 equ 0x92 29 | P1M1 equ 0x91 30 | P2M0 equ 0x96 31 | P2M1 equ 0x95 32 | P3M0 equ 0xB2 33 | P3M1 equ 0xB1 34 | P4M0 equ 0xB4 35 | P4M1 equ 0xB3 36 | P5M0 equ 0xCA 37 | P5M1 equ 0xC9 38 | P6M0 equ 0xCC 39 | P6M1 equ 0xCB 40 | P7M0 equ 0xE2 41 | P7M1 equ 0xE1 42 | PCON equ 0x87 43 | AUXR equ 0x8E 44 | AUXR1 equ 0xA2 45 | P_SW1 equ 0xA2 46 | CLK_DIV equ 0x97 47 | BUS_SPEED equ 0xA1 48 | P1ASF equ 0x9D 49 | P_SW2 equ 0xBA 50 | IE equ 0xA8 51 | IP equ 0xB8 52 | IE2 equ 0xAF 53 | IP2 equ 0xB5 54 | INT_CLKO equ 0x8F 55 | TCON equ 0x88 56 | TMOD equ 0x89 57 | TL0 equ 0x8A 58 | TL1 equ 0x8B 59 | TH0 equ 0x8C 60 | TH1 equ 0x8D 61 | T4T3M equ 0xD1 62 | T3T4M equ 0xD1 63 | T4H equ 0xD2 64 | T4L equ 0xD3 65 | T3H equ 0xD4 66 | T3L equ 0xD5 67 | T2H equ 0xD6 68 | T2L equ 0xD7 69 | WKTCL equ 0xAA 70 | WKTCH equ 0xAB 71 | WDT_CONTR equ 0xC1 72 | SCON equ 0x98 73 | SBUF equ 0x99 74 | S2CON equ 0x9A 75 | S2BUF equ 0x9B 76 | S3CON equ 0xAC 77 | S3BUF equ 0xAD 78 | S4CON equ 0x84 79 | S4BUF equ 0x85 80 | SADDR equ 0xA9 81 | SADEN equ 0xB9 82 | ADC_CONTR equ 0xBC 83 | ADC_RES equ 0xBD 84 | ADC_RESL equ 0xBE 85 | SPSTAT equ 0xCD 86 | SPCTL equ 0xCE 87 | SPDAT equ 0xCF 88 | IAP_DATA equ 0xC2 89 | IAP_ADDRH equ 0xC3 90 | IAP_ADDRL equ 0xC4 91 | IAP_CMD equ 0xC5 92 | IAP_TRIG equ 0xC6 93 | IAP_CONTR equ 0xC7 94 | CCON equ 0xD8 95 | CMOD equ 0xD9 96 | CL equ 0xE9 97 | CH equ 0xF9 98 | CCAPM0 equ 0xDA 99 | CCAPM1 equ 0xDB 100 | CCAPM2 equ 0xDC 101 | CCAP0L equ 0xEA 102 | CCAP1L equ 0xEB 103 | CCAP2L equ 0xEC 104 | PCA_PWM0 equ 0xF2 105 | PCA_PWM1 equ 0xF3 106 | PCA_PWM2 equ 0xF4 107 | CCAP0H equ 0xFA 108 | CCAP1H equ 0xFB 109 | CCAP2H equ 0xFC 110 | CMPCR1 equ 0xE6 111 | CMPCR2 equ 0xE7 112 | PWMCFG equ 0xf1 113 | PWMCR equ 0xf5 114 | PWMIF equ 0xf6 115 | PWMFDCR equ 0xf7 116 | 117 | ; bit aliases 118 | 119 | CY equ 0xD0.7 120 | AC equ 0xD0.6 121 | F0 equ 0xD0.5 122 | RS1 equ 0xD0.4 123 | RS0 equ 0xD0.3 124 | OV equ 0xD0.2 125 | F1 equ 0xD0.1 126 | P equ 0xD0.0 127 | EA equ 0xA8.7 128 | ELVD equ 0xA8.6 129 | EADC equ 0xA8.5 130 | ES equ 0xA8.4 131 | ET1 equ 0xA8.3 132 | EX1 equ 0xA8.2 133 | ET0 equ 0xA8.1 134 | EX0 equ 0xA8.0 135 | PPCA equ 0xB8.7 136 | PLVD equ 0xB8.6 137 | PADC equ 0xB8.5 138 | PS equ 0xB8.4 139 | PT1 equ 0xB8.3 140 | PX1 equ 0xB8.2 141 | PT0 equ 0xB8.1 142 | PX0 equ 0xB8.0 143 | TF1 equ 0x88.7 144 | TR1 equ 0x88.6 145 | TF0 equ 0x88.5 146 | TR0 equ 0x88.4 147 | IE1 equ 0x88.3 148 | IT1 equ 0x88.2 149 | IE0 equ 0x88.1 150 | IT0 equ 0x88.0 151 | SM0 equ 0x98.7 152 | SM1 equ 0x98.6 153 | SM2 equ 0x98.5 154 | REN equ 0x98.4 155 | TB8 equ 0x98.3 156 | RB8 equ 0x98.2 157 | TI equ 0x98.1 158 | RI equ 0x98.0 159 | CF equ 0xD8.7 160 | CR equ 0xD8.6 161 | CCF2 equ 0xD8.2 162 | CCF1 equ 0xD8.1 163 | CCF0 equ 0xD8.0 164 | 165 | ; xdata 166 | 167 | PWMC equ 0xfff0 168 | PWMCH equ 0xfff0 169 | PWMCL equ 0xfff1 170 | PWMCKS equ 0xfff2 171 | PWM2T1 equ 0xff00 172 | PWM2T1H equ 0xff00 173 | PWM2T1L equ 0xff01 174 | PWM2T2 equ 0xff02 175 | PWM2T2H equ 0xff02 176 | PWM2T2L equ 0xff03 177 | PWM2CR equ 0xff04 178 | PWM3T1 equ 0xff10 179 | PWM3T1H equ 0xff10 180 | PWM3T1L equ 0xff11 181 | PWM3T2 equ 0xff12 182 | PWM3T2H equ 0xff12 183 | PWM3T2L equ 0xff13 184 | PWM3CR equ 0xff14 185 | PWM4T1 equ 0xff20 186 | PWM4T1H equ 0xff20 187 | PWM4T1L equ 0xff21 188 | PWM4T2 equ 0xff22 189 | PWM4T2H equ 0xff22 190 | PWM4T2L equ 0xff23 191 | PWM4CR equ 0xff24 192 | PWM5T1 equ 0xff30 193 | PWM5T1H equ 0xff30 194 | PWM5T1L equ 0xff31 195 | PWM5T2 equ 0xff32 196 | PWM5T2H equ 0xff32 197 | PWM5T2L equ 0xff33 198 | PWM5CR equ 0xff34 199 | PWM6T1 equ 0xff40 200 | PWM6T1H equ 0xff40 201 | PWM6T1L equ 0xff41 202 | PWM6T2 equ 0xff42 203 | PWM6T2H equ 0xff42 204 | PWM6T2L equ 0xff43 205 | PWM6CR equ 0xff44 206 | PWM7T1 equ 0xff50 207 | PWM7T1H equ 0xff50 208 | PWM7T1L equ 0xff51 209 | PWM7T2 equ 0xff52 210 | PWM7T2H equ 0xff52 211 | PWM7T2L equ 0xff53 212 | PWM7CR equ 0xff54 213 | -------------------------------------------------------------------------------- /naken_asm-headers/stc16fxx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC16Fxx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC16Fxx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | P0 equ 0x80 13 | SP equ 0x81 14 | DPL equ 0x82 15 | DPH equ 0x83 16 | DPXL equ 0x84 17 | USBCLK equ 0x85 18 | DPS equ 0x86 19 | PCON equ 0x87 20 | TCON equ 0x88 21 | TMOD equ 0x89 22 | TL0 equ 0x8a 23 | TL1 equ 0x8b 24 | TH0 equ 0x8c 25 | TH1 equ 0x8d 26 | CKCON equ 0x8e 27 | DMAIR equ 0x8f 28 | P1 equ 0x90 29 | USBCON equ 0x91 30 | WTST equ 0x92 31 | AUXR equ 0x93 32 | AUXR2 equ 0x94 33 | INTCLKO equ 0x95 34 | USBADR equ 0x96 35 | USBDAT equ 0x97 36 | SCON equ 0x98 37 | SBUF equ 0x99 38 | P_SW1 equ 0x9a 39 | P_SW2 equ 0x9b 40 | BGTRIM equ 0x9c 41 | VRTRIM equ 0x9d 42 | LIRTRIM equ 0x9e 43 | IRTRIM equ 0x9f 44 | P2 equ 0xa0 45 | CANICR equ 0xa1 46 | CANAR equ 0xa2 47 | CANDR equ 0xa3 48 | IE equ 0xa8 49 | IRCBAND equ 0xa9 50 | WKTCL equ 0xaa 51 | WKTCH equ 0xab 52 | VOCTRL equ 0xac 53 | VOSEL equ 0xad 54 | P3 equ 0xb0 55 | LINICR equ 0xb1 56 | LINAR equ 0xb2 57 | LINDR equ 0xb3 58 | CMPCR1 equ 0xb4 59 | CMPCR2 equ 0xb5 60 | IP2H equ 0xb6 61 | IPH equ 0xb7 62 | IP equ 0xb8 63 | SPSTAT equ 0xb9 64 | SPCTL equ 0xba 65 | SPDAT equ 0xbb 66 | S4CON equ 0xbc 67 | S4BUF equ 0xbd 68 | SPH equ 0xbe 69 | BUSSPD equ 0xbf 70 | P4 equ 0xc0 71 | DID equ 0xc1 72 | IAP_DATA equ 0xc2 73 | IAP_ADDRH equ 0xc3 74 | IAP_ADDRL equ 0xc4 75 | IAP_CMD equ 0xc5 76 | IAP_TRIG equ 0xc6 77 | IAP_CONTR equ 0xc7 78 | P5 equ 0xc8 79 | T4H equ 0xc9 80 | T4L equ 0xca 81 | T3H equ 0xcb 82 | T3L equ 0xcc 83 | T2H equ 0xcd 84 | T2L equ 0xce 85 | PSW equ 0xd0 86 | PSW1 equ 0xd1 87 | P7M1 equ 0xd2 88 | P7M0 equ 0xd3 89 | RSTIF equ 0xd8 90 | AUXINTIF equ 0xda 91 | T4T3M equ 0xdb 92 | ADC_CONTR equ 0xdc 93 | ADC_RES equ 0xdd 94 | ADC_RESL equ 0xde 95 | ADCCFG equ 0xdf 96 | ACC equ 0xe0 97 | SADDR equ 0xe1 98 | SADEN equ 0xe2 99 | S2CON equ 0xe3 100 | S2BUF equ 0xe4 101 | S3CON equ 0xe5 102 | S3BUF equ 0xe6 103 | IE2 equ 0xe7 104 | P6 equ 0xe8 105 | MXAX equ 0xea 106 | TA equ 0xeb 107 | P5M1 equ 0xec 108 | P5M0 equ 0xed 109 | P6M1 equ 0xee 110 | P6M0 equ 0xef 111 | B equ 0xf0 112 | P0M1 equ 0xf1 113 | P0M0 equ 0xf2 114 | P1M1 equ 0xf3 115 | P1M0 equ 0xf4 116 | P2M1 equ 0xf5 117 | P2M0 equ 0xf6 118 | IAP_TPS equ 0xf7 119 | P7 equ 0xf8 120 | P3M1 equ 0xf9 121 | P3M0 equ 0xfa 122 | P4M1 equ 0xfb 123 | P4M0 equ 0xfc 124 | WDT_CONTR equ 0xfd 125 | IP2 equ 0xfe 126 | RSTCFG equ 0xff 127 | 128 | ; bit aliases 129 | 130 | IT0 equ 0x88.0 131 | IE0 equ 0x88.1 132 | IT1 equ 0x88.2 133 | IE1 equ 0x88.3 134 | TR0 equ 0x88.4 135 | TF0 equ 0x88.5 136 | TR1 equ 0x88.6 137 | TF1 equ 0x88.7 138 | RI equ 0x98.0 139 | TI equ 0x98.1 140 | RB8 equ 0x98.2 141 | TB8 equ 0x98.3 142 | REN equ 0x98.4 143 | SM2 equ 0x98.5 144 | SM1 equ 0x98.6 145 | SM0 equ 0x98.7 146 | EX0 equ 0xa8.0 147 | ET0 equ 0xa8.1 148 | EX1 equ 0xa8.2 149 | ET1 equ 0xa8.3 150 | ES equ 0xa8.4 151 | EADC equ 0xa8.5 152 | ELVD equ 0xa8.6 153 | EA equ 0xa8.7 154 | PX0 equ 0xb8.0 155 | PT0 equ 0xb8.1 156 | PX1 equ 0xb8.2 157 | PT1 equ 0xb8.3 158 | PS0 equ 0xb8.4 159 | PS equ 0xb8.4 160 | PADC equ 0xb8.5 161 | PLVD equ 0xb8.6 162 | PPWM1 equ 0xb8.7 163 | P equ 0xd0.0 164 | F1 equ 0xd0.1 165 | OV equ 0xd0.2 166 | RS0 equ 0xd0.3 167 | RS1 equ 0xd0.4 168 | F0 equ 0xd0.5 169 | AC equ 0xd0.6 170 | CY equ 0xd0.7 171 | 172 | ; xdata 173 | 174 | CLKSEL equ 0x7efe00 175 | CLKDIV equ 0x7efe01 176 | IRC24MCR equ 0x7efe02 177 | XOSCCR equ 0x7efe03 178 | IRC32KCR equ 0x7efe04 179 | PLLCR equ 0x7efe05 180 | USBCON1 equ 0x7efe06 181 | MCLKOCR equ 0x7efe07 182 | IRC48MCR equ 0x7efe08 183 | IRC48ATRIM equ 0x7efe09 184 | IRC48BTRIM equ 0x7efe0a 185 | IRCDB equ 0x7efe0b 186 | P0PU equ 0x7efe10 187 | P1PU equ 0x7efe11 188 | P2PU equ 0x7efe12 189 | P3PU equ 0x7efe13 190 | P4PU equ 0x7efe14 191 | P5PU equ 0x7efe15 192 | P6PU equ 0x7efe16 193 | P7PU equ 0x7efe17 194 | P0NCS equ 0x7efe18 195 | P1NCS equ 0x7efe19 196 | P2NCS equ 0x7efe1a 197 | P3NCS equ 0x7efe1b 198 | P4NCS equ 0x7efe1c 199 | P5NCS equ 0x7efe1d 200 | P6NCS equ 0x7efe1e 201 | P7NCS equ 0x7efe1f 202 | P0SR equ 0x7efe20 203 | P1SR equ 0x7efe21 204 | P2SR equ 0x7efe22 205 | P3SR equ 0x7efe23 206 | P4SR equ 0x7efe24 207 | P5SR equ 0x7efe25 208 | P6SR equ 0x7efe26 209 | P7SR equ 0x7efe27 210 | P0DR equ 0x7efe28 211 | P1DR equ 0x7efe29 212 | P2DR equ 0x7efe2a 213 | P3DR equ 0x7efe2b 214 | P4DR equ 0x7efe2c 215 | P5DR equ 0x7efe2d 216 | P6DR equ 0x7efe2e 217 | P7DR equ 0x7efe2f 218 | P0IE equ 0x7efe30 219 | P1IE equ 0x7efe31 220 | I2CCFG equ 0x7efe80 221 | I2CMSCR equ 0x7efe81 222 | I2CMSST equ 0x7efe82 223 | I2CSLCR equ 0x7efe83 224 | I2CSLST equ 0x7efe84 225 | I2CSLADR equ 0x7efe85 226 | I2CTXD equ 0x7efe86 227 | I2CRXD equ 0x7efe87 228 | I2CMSAUX equ 0x7efe88 229 | TIMER2PS equ 0x7efea2 230 | TIMER3PS equ 0x7efea3 231 | TIMER4PS equ 0x7efea4 232 | ADCTIM equ 0x7efeab 233 | T3T4PS equ 0x7efeac 234 | PWM1_ETRPS equ 0x7efeb0 235 | PWM1_ENO equ 0x7efeb1 236 | PWM1_PS equ 0x7efeb2 237 | PWM1_IOAUX equ 0x7efeb3 238 | PWM2_ETRPS equ 0x7efeb4 239 | PWM2_ENO equ 0x7efeb5 240 | PWM2_PS equ 0x7efeb6 241 | PWM2_IOAUX equ 0x7efeb7 242 | PWMA_ETRPS equ 0x7efeb0 243 | PWMA_ENO equ 0x7efeb1 244 | PWMA_PS equ 0x7efeb2 245 | PWMA_IOAUX equ 0x7efeb3 246 | PWMB_ETRPS equ 0x7efeb4 247 | PWMB_ENO equ 0x7efeb5 248 | PWMB_PS equ 0x7efeb6 249 | PWMB_IOAUX equ 0x7efeb7 250 | PWM1_CR1 equ 0x7efec0 251 | PWM1_CR2 equ 0x7efec1 252 | PWM1_SMCR equ 0x7efec2 253 | PWM1_ETR equ 0x7efec3 254 | PWM1_IER equ 0x7efec4 255 | PWM1_SR1 equ 0x7efec5 256 | PWM1_SR2 equ 0x7efec6 257 | PWM1_EGR equ 0x7efec7 258 | PWM1_CCMR1 equ 0x7efec8 259 | PWM1_CCMR2 equ 0x7efec9 260 | PWM1_CCMR3 equ 0x7efeca 261 | PWM1_CCMR4 equ 0x7efecb 262 | PWM1_CCER1 equ 0x7efecc 263 | PWM1_CCER2 equ 0x7efecd 264 | PWM1_CNTRH equ 0x7efece 265 | PWM1_CNTRL equ 0x7efecf 266 | PWM1_PSCRH equ 0x7efed0 267 | PWM1_PSCRL equ 0x7efed1 268 | PWM1_ARRH equ 0x7efed2 269 | PWM1_ARRL equ 0x7efed3 270 | PWM1_RCR equ 0x7efed4 271 | PWM1_CCR1H equ 0x7efed5 272 | PWM1_CCR1L equ 0x7efed6 273 | PWM1_CCR2H equ 0x7efed7 274 | PWM1_CCR2L equ 0x7efed8 275 | PWM1_CCR3H equ 0x7efed9 276 | PWM1_CCR3L equ 0x7efeda 277 | PWM1_CCR4H equ 0x7efedb 278 | PWM1_CCR4L equ 0x7efedc 279 | PWM1_BKR equ 0x7efedd 280 | PWM1_DTR equ 0x7efede 281 | PWM1_OISR equ 0x7efedf 282 | PWM2_CR1 equ 0x7efee0 283 | PWM2_CR2 equ 0x7efee1 284 | PWM2_SMCR equ 0x7efee2 285 | PWM2_ETR equ 0x7efee3 286 | PWM2_IER equ 0x7efee4 287 | PWM2_SR1 equ 0x7efee5 288 | PWM2_SR2 equ 0x7efee6 289 | PWM2_EGR equ 0x7efee7 290 | PWM2_CCMR1 equ 0x7efee8 291 | PWM2_CCMR2 equ 0x7efee9 292 | PWM2_CCMR3 equ 0x7efeea 293 | PWM2_CCMR4 equ 0x7efeeb 294 | PWM2_CCER1 equ 0x7efeec 295 | PWM2_CCER2 equ 0x7efeed 296 | PWM2_CNTRH equ 0x7efeee 297 | PWM2_CNTRL equ 0x7efeef 298 | PWM2_PSCRH equ 0x7efef0 299 | PWM2_PSCRL equ 0x7efef1 300 | PWM2_ARRH equ 0x7efef2 301 | PWM2_ARRL equ 0x7efef3 302 | PWM2_RCR equ 0x7efef4 303 | PWM2_CCR1H equ 0x7efef5 304 | PWM2_CCR1L equ 0x7efef6 305 | PWM2_CCR2H equ 0x7efef7 306 | PWM2_CCR2L equ 0x7efef8 307 | PWM2_CCR3H equ 0x7efef9 308 | PWM2_CCR3L equ 0x7efefa 309 | PWM2_CCR4H equ 0x7efefb 310 | PWM2_CCR4L equ 0x7efefc 311 | PWM2_BKR equ 0x7efefd 312 | PWM2_DTR equ 0x7efefe 313 | PWM2_OISR equ 0x7efeff 314 | PWMA_CR1 equ 0x7efec0 315 | PWMA_CR2 equ 0x7efec1 316 | PWMA_SMCR equ 0x7efec2 317 | PWMA_ETR equ 0x7efec3 318 | PWMA_IER equ 0x7efec4 319 | PWMA_SR1 equ 0x7efec5 320 | PWMA_SR2 equ 0x7efec6 321 | PWMA_EGR equ 0x7efec7 322 | PWMA_CCMR1 equ 0x7efec8 323 | PWMA_CCMR2 equ 0x7efec9 324 | PWMA_CCMR3 equ 0x7efeca 325 | PWMA_CCMR4 equ 0x7efecb 326 | PWMA_CCER1 equ 0x7efecc 327 | PWMA_CCER2 equ 0x7efecd 328 | PWMA_CNTRH equ 0x7efece 329 | PWMA_CNTRL equ 0x7efecf 330 | PWMA_PSCRH equ 0x7efed0 331 | PWMA_PSCRL equ 0x7efed1 332 | PWMA_ARRH equ 0x7efed2 333 | PWMA_ARRL equ 0x7efed3 334 | PWMA_RCR equ 0x7efed4 335 | PWMA_CCR1H equ 0x7efed5 336 | PWMA_CCR1L equ 0x7efed6 337 | PWMA_CCR2H equ 0x7efed7 338 | PWMA_CCR2L equ 0x7efed8 339 | PWMA_CCR3H equ 0x7efed9 340 | PWMA_CCR3L equ 0x7efeda 341 | PWMA_CCR4H equ 0x7efedb 342 | PWMA_CCR4L equ 0x7efedc 343 | PWMA_BKR equ 0x7efedd 344 | PWMA_DTR equ 0x7efede 345 | PWMA_OISR equ 0x7efedf 346 | PWMB_CR1 equ 0x7efee0 347 | PWMB_CR2 equ 0x7efee1 348 | PWMB_SMCR equ 0x7efee2 349 | PWMB_ETR equ 0x7efee3 350 | PWMB_IER equ 0x7efee4 351 | PWMB_SR1 equ 0x7efee5 352 | PWMB_SR2 equ 0x7efee6 353 | PWMB_EGR equ 0x7efee7 354 | PWMB_CCMR1 equ 0x7efee8 355 | PWMB_CCMR2 equ 0x7efee9 356 | PWMB_CCMR3 equ 0x7efeea 357 | PWMB_CCMR4 equ 0x7efeeb 358 | PWMB_CCER1 equ 0x7efeec 359 | PWMB_CCER2 equ 0x7efeed 360 | PWMB_CNTRH equ 0x7efeee 361 | PWMB_CNTRL equ 0x7efeef 362 | PWMB_PSCRH equ 0x7efef0 363 | PWMB_PSCRL equ 0x7efef1 364 | PWMB_ARRH equ 0x7efef2 365 | PWMB_ARRL equ 0x7efef3 366 | PWMB_RCR equ 0x7efef4 367 | PWMB_CCR1H equ 0x7efef5 368 | PWMB_CCR1L equ 0x7efef6 369 | PWMB_CCR2H equ 0x7efef7 370 | PWMB_CCR2L equ 0x7efef8 371 | PWMB_CCR3H equ 0x7efef9 372 | PWMB_CCR3L equ 0x7efefa 373 | PWMB_CCR4H equ 0x7efefb 374 | PWMB_CCR4L equ 0x7efefc 375 | PWMB_BKR equ 0x7efefd 376 | PWMB_DTR equ 0x7efefe 377 | PWMB_OISR equ 0x7efeff 378 | -------------------------------------------------------------------------------- /naken_asm-headers/stc89xx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC89xx/STC90xx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC89xx / STC90xx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | P4 equ 0xe8 13 | XICON equ 0xc0 14 | WDT_CONTR equ 0xe1 15 | ISP_DATA equ 0xe2 16 | ISP_ADDRH equ 0xe3 17 | ISP_ADDRL equ 0xe4 18 | ISP_CMD equ 0xe5 19 | ISP_TRIG equ 0xe6 20 | ISP_CONTR equ 0xe7 21 | P0 equ 0x80 22 | P1 equ 0x90 23 | P2 equ 0xA0 24 | P3 equ 0xB0 25 | PSW equ 0xD0 26 | ACC equ 0xE0 27 | B equ 0xF0 28 | SP equ 0x81 29 | DPL equ 0x82 30 | DPH equ 0x83 31 | PCON equ 0x87 32 | TCON equ 0x88 33 | TMOD equ 0x89 34 | TL0 equ 0x8A 35 | TL1 equ 0x8B 36 | TH0 equ 0x8C 37 | TH1 equ 0x8D 38 | IE equ 0xA8 39 | IP equ 0xB8 40 | SCON equ 0x98 41 | SBUF equ 0x99 42 | AUXR equ 0x8E 43 | AUXR1 equ 0xA2 44 | SADDR equ 0xA9 45 | IPH equ 0xB7 46 | SADEN equ 0xB9 47 | T2CON equ 0xC8 48 | T2MOD equ 0xC9 49 | RCAP2L equ 0xCA 50 | RCAP2H equ 0xCB 51 | TL2 equ 0xCC 52 | TH2 equ 0xCD 53 | 54 | ; bit aliases 55 | 56 | CY equ 0xD0.7 57 | AC equ 0xD0.6 58 | F0 equ 0xD0.5 59 | RS1 equ 0xD0.4 60 | RS0 equ 0xD0.3 61 | OV equ 0xD0.2 62 | F1 equ 0xD0.1 63 | P equ 0xD0.0 64 | TF1 equ 0x88.7 65 | TR1 equ 0x88.6 66 | TF0 equ 0x88.5 67 | TR0 equ 0x88.4 68 | IE1 equ 0x88.3 69 | IT1 equ 0x88.2 70 | IE0 equ 0x88.1 71 | IT0 equ 0x88.0 72 | EA equ 0xA8.7 73 | EC equ 0xA8.6 74 | ET2 equ 0xA8.5 75 | ES equ 0xA8.4 76 | ET1 equ 0xA8.3 77 | EX1 equ 0xA8.2 78 | ET0 equ 0xA8.1 79 | EX0 equ 0xA8.0 80 | PT2 equ 0xB8.5 81 | PS equ 0xB8.4 82 | PT1 equ 0xB8.3 83 | PX1 equ 0xB8.2 84 | PT0 equ 0xB8.1 85 | PX0 equ 0xB8.0 86 | RD equ 0xB0.7 87 | WR equ 0xB0.6 88 | T1 equ 0xB0.5 89 | T0 equ 0xB0.4 90 | INT1 equ 0xB0.3 91 | INT0 equ 0xB0.2 92 | TXD equ 0xB0.1 93 | RXD equ 0xB0.0 94 | SM0 equ 0x98.7 95 | FE equ 0x98.7 96 | SM1 equ 0x98.6 97 | SM2 equ 0x98.5 98 | REN equ 0x98.4 99 | TB8 equ 0x98.3 100 | RB8 equ 0x98.2 101 | TI equ 0x98.1 102 | RI equ 0x98.0 103 | T2EX equ 0x90.1 104 | T2 equ 0x90.0 105 | TF2 equ 0xC8.7 106 | EXF2 equ 0xC8.6 107 | RCLK equ 0xC8.5 108 | TCLK equ 0xC8.4 109 | EXEN2 equ 0xC8.3 110 | TR2 equ 0xC8.2 111 | C_T2 equ 0xC8.1 112 | CP_RL2 equ 0xC8.0 113 | 114 | ; xdata 115 | 116 | -------------------------------------------------------------------------------- /naken_asm-headers/stc8a8k64d4.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC8A8K64D4 include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC8A8K64D4 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | P0 equ 0x80 13 | SP equ 0x81 14 | DPL equ 0x82 15 | DPH equ 0x83 16 | S4CON equ 0x84 17 | S4BUF equ 0x85 18 | PCON equ 0x87 19 | TCON equ 0x88 20 | TMOD equ 0x89 21 | TL0 equ 0x8a 22 | TL1 equ 0x8b 23 | TH0 equ 0x8c 24 | TH1 equ 0x8d 25 | AUXR equ 0x8e 26 | INTCLKO equ 0x8f 27 | P1 equ 0x90 28 | P1M1 equ 0x91 29 | P1M0 equ 0x92 30 | P0M1 equ 0x93 31 | P0M0 equ 0x94 32 | P2M1 equ 0x95 33 | P2M0 equ 0x96 34 | SCON equ 0x98 35 | SBUF equ 0x99 36 | S2CON equ 0x9a 37 | S2BUF equ 0x9b 38 | IRCBAND equ 0x9d 39 | LIRTRIM equ 0x9e 40 | IRTRIM equ 0x9f 41 | P2 equ 0xa0 42 | BUS_SPEED equ 0xa1 43 | P_SW1 equ 0xa2 44 | IE equ 0xa8 45 | SADDR equ 0xa9 46 | WKTCL equ 0xaa 47 | WKTCH equ 0xab 48 | S3CON equ 0xac 49 | S3BUF equ 0xad 50 | TA equ 0xae 51 | IE2 equ 0xaf 52 | P3 equ 0xb0 53 | P3M1 equ 0xb1 54 | P3M0 equ 0xb2 55 | P4M1 equ 0xb3 56 | P4M0 equ 0xb4 57 | IP2 equ 0xb5 58 | IP2H equ 0xb6 59 | IPH equ 0xb7 60 | IP equ 0xb8 61 | SADEN equ 0xb9 62 | P_SW2 equ 0xba 63 | ADC_CONTR equ 0xbc 64 | ADC_RES equ 0xbd 65 | ADC_RESL equ 0xbe 66 | P4 equ 0xc0 67 | WDT_CONTR equ 0xc1 68 | IAP_DATA equ 0xc2 69 | IAP_ADDRH equ 0xc3 70 | IAP_ADDRL equ 0xc4 71 | IAP_CMD equ 0xc5 72 | IAP_TRIG equ 0xc6 73 | IAP_CONTR equ 0xc7 74 | P5 equ 0xc8 75 | P5M1 equ 0xc9 76 | P5M0 equ 0xca 77 | P6M1 equ 0xcb 78 | P6M0 equ 0xcc 79 | SPSTAT equ 0xcd 80 | SPCTL equ 0xce 81 | SPDAT equ 0xcf 82 | PSW equ 0xd0 83 | T4T3M equ 0xd1 84 | T4H equ 0xd2 85 | T4L equ 0xd3 86 | T3H equ 0xd4 87 | T3L equ 0xd5 88 | T2H equ 0xd6 89 | T2L equ 0xd7 90 | CCON equ 0xd8 91 | CMOD equ 0xd9 92 | CCAPM0 equ 0xda 93 | CCAPM1 equ 0xdb 94 | CCAPM2 equ 0xdc 95 | ADCCFG equ 0xde 96 | IP3 equ 0xdf 97 | ACC equ 0xe0 98 | P7M1 equ 0xe1 99 | P7M0 equ 0xe2 100 | DPS equ 0xe3 101 | DPL1 equ 0xe4 102 | DPH1 equ 0xe5 103 | CMPCR1 equ 0xe6 104 | CMPCR2 equ 0xe7 105 | P6 equ 0xe8 106 | CL equ 0xe9 107 | CCAP0L equ 0xea 108 | CCAP1L equ 0xeb 109 | CCAP2L equ 0xec 110 | IP3H equ 0xee 111 | AUXINTIF equ 0xef 112 | B equ 0xf0 113 | PWMSET equ 0xf1 114 | PCA_PWM0 equ 0xf2 115 | PCA_PWM1 equ 0xf3 116 | PCA_PWM2 equ 0xf4 117 | IAP_TPS equ 0xf5 118 | PWMCFG equ 0xf6 119 | P7 equ 0xf8 120 | CH equ 0xf9 121 | CCAP0H equ 0xfa 122 | CCAP1H equ 0xfb 123 | CCAP2H equ 0xfc 124 | RSTCFG equ 0xff 125 | 126 | ; bit aliases 127 | 128 | TF1 equ 0x88.7 129 | TR1 equ 0x88.6 130 | TF0 equ 0x88.5 131 | TR0 equ 0x88.4 132 | IE1 equ 0x88.3 133 | IT1 equ 0x88.2 134 | IE0 equ 0x88.1 135 | IT0 equ 0x88.0 136 | SM0 equ 0x98.7 137 | SM1 equ 0x98.6 138 | SM2 equ 0x98.5 139 | REN equ 0x98.4 140 | TB8 equ 0x98.3 141 | RB8 equ 0x98.2 142 | TI equ 0x98.1 143 | RI equ 0x98.0 144 | EA equ 0xa8.7 145 | ELVD equ 0xa8.6 146 | EADC equ 0xa8.5 147 | ES equ 0xa8.4 148 | ET1 equ 0xa8.3 149 | EX1 equ 0xa8.2 150 | ET0 equ 0xa8.1 151 | EX0 equ 0xa8.0 152 | PPCA equ 0xb8.7 153 | PLVD equ 0xb8.6 154 | PADC equ 0xb8.5 155 | PS equ 0xb8.4 156 | PT1 equ 0xb8.3 157 | PX1 equ 0xb8.2 158 | PT0 equ 0xb8.1 159 | PX0 equ 0xb8.0 160 | CY equ 0xd0.7 161 | AC equ 0xd0.6 162 | F0 equ 0xd0.5 163 | RS1 equ 0xd0.4 164 | RS0 equ 0xd0.3 165 | OV equ 0xd0.2 166 | P equ 0xd0.0 167 | CF equ 0xd8.7 168 | CR equ 0xd8.6 169 | CCF3 equ 0xd8.3 170 | CCF2 equ 0xd8.2 171 | CCF1 equ 0xd8.1 172 | CCF0 equ 0xd8.0 173 | 174 | ; xdata 175 | 176 | PWMC equ 0xff00 177 | PWMCH equ 0xff00 178 | PWMCL equ 0xff01 179 | PWMCKS equ 0xff02 180 | PWMTADC equ 0xff03 181 | PWMTADCH equ 0xff03 182 | PWMTADCL equ 0xff04 183 | PWMIF equ 0xff05 184 | PWMFDCR equ 0xff06 185 | PWMDELSEL equ 0xff07 186 | PWM0T1 equ 0xff10 187 | PWM0T1H equ 0xff10 188 | PWM0T1L equ 0xff11 189 | PWM0T2 equ 0xff12 190 | PWM0T2H equ 0xff12 191 | PWM0T2L equ 0xff13 192 | PWM0CR equ 0xff14 193 | PWM0HLD equ 0xff15 194 | PWM1T1 equ 0xff18 195 | PWM1T1H equ 0xff18 196 | PWM1T1L equ 0xff19 197 | PWM1T2 equ 0xff1a 198 | PWM1T2H equ 0xff1a 199 | PWM1T2L equ 0xff1b 200 | PWM1CR equ 0xff1c 201 | PWM1HLD equ 0xff1d 202 | PWM2T1 equ 0xff20 203 | PWM2T1H equ 0xff20 204 | PWM2T1L equ 0xff21 205 | PWM2T2 equ 0xff22 206 | PWM2T2H equ 0xff22 207 | PWM2T2L equ 0xff23 208 | PWM2CR equ 0xff24 209 | PWM2HLD equ 0xff25 210 | PWM3T1 equ 0xff28 211 | PWM3T1H equ 0xff28 212 | PWM3T1L equ 0xff29 213 | PWM3T2 equ 0xff2a 214 | PWM3T2H equ 0xff2a 215 | PWM3T2L equ 0xff2b 216 | PWM3CR equ 0xff2c 217 | PWM3HLD equ 0xff2d 218 | PWM4T1 equ 0xff30 219 | PWM4T1H equ 0xff30 220 | PWM4T1L equ 0xff31 221 | PWM4T2 equ 0xff32 222 | PWM4T2H equ 0xff32 223 | PWM4T2L equ 0xff33 224 | PWM4CR equ 0xff34 225 | PWM4HLD equ 0xff35 226 | PWM5T1 equ 0xff38 227 | PWM5T1H equ 0xff38 228 | PWM5T1L equ 0xff39 229 | PWM5T2 equ 0xff3a 230 | PWM5T2H equ 0xff3a 231 | PWM5T2L equ 0xff3b 232 | PWM5CR equ 0xff3c 233 | PWM5HLD equ 0xff3d 234 | PWM6T1 equ 0xff40 235 | PWM6T1H equ 0xff40 236 | PWM6T1L equ 0xff41 237 | PWM6T2 equ 0xff42 238 | PWM6T2H equ 0xff42 239 | PWM6T2L equ 0xff43 240 | PWM6CR equ 0xff44 241 | PWM6HLD equ 0xff45 242 | PWM7T1 equ 0xff48 243 | PWM7T1H equ 0xff48 244 | PWM7T1L equ 0xff49 245 | PWM7T2 equ 0xff4a 246 | PWM7T2H equ 0xff4a 247 | PWM7T2L equ 0xff4b 248 | PWM7CR equ 0xff4c 249 | PWM7HLD equ 0xff4d 250 | CKSEL equ 0xfe00 251 | CLKDIV equ 0xfe01 252 | IRC24MCR equ 0xfe02 253 | XOSCCR equ 0xfe03 254 | IRC32KCR equ 0xfe04 255 | MCLKOCR equ 0xfe05 256 | IRCDB equ 0xfe06 257 | P0PU equ 0xfe10 258 | P1PU equ 0xfe11 259 | P2PU equ 0xfe12 260 | P3PU equ 0xfe13 261 | P4PU equ 0xfe14 262 | P5PU equ 0xfe15 263 | P6PU equ 0xfe16 264 | P7PU equ 0xfe17 265 | P0NCS equ 0xfe18 266 | P1NCS equ 0xfe19 267 | P2NCS equ 0xfe1a 268 | P3NCS equ 0xfe1b 269 | P4NCS equ 0xfe1c 270 | P5NCS equ 0xfe1d 271 | P6NCS equ 0xfe1e 272 | P7NCS equ 0xfe1f 273 | P0SR equ 0xfe20 274 | P1SR equ 0xfe21 275 | P2SR equ 0xfe22 276 | P3SR equ 0xfe23 277 | P4SR equ 0xfe24 278 | P5SR equ 0xfe25 279 | P6SR equ 0xfe26 280 | P7SR equ 0xfe27 281 | P0DR equ 0xfe28 282 | P1DR equ 0xfe29 283 | P2DR equ 0xfe2a 284 | P3DR equ 0xfe2b 285 | P4DR equ 0xfe2c 286 | P5DR equ 0xfe2d 287 | P6DR equ 0xfe2e 288 | P7DR equ 0xfe2f 289 | P0IE equ 0xfe30 290 | P1IE equ 0xfe31 291 | P2IE equ 0xfe32 292 | P3IE equ 0xfe33 293 | P4IE equ 0xfe34 294 | P5IE equ 0xfe35 295 | P6IE equ 0xfe36 296 | P7IE equ 0xfe37 297 | LCMIFCFG equ 0xfe50 298 | LCMIFCFG2 equ 0xfe51 299 | LCMIFCR equ 0xfe52 300 | LCMIFSTA equ 0xfe53 301 | LCMIFDATL equ 0xfe54 302 | LCMIFDATH equ 0xfe55 303 | I2CCFG equ 0xfe80 304 | I2CMSCR equ 0xfe81 305 | I2CMSST equ 0xfe82 306 | I2CSLCR equ 0xfe83 307 | I2CSLST equ 0xfe84 308 | I2CSLADR equ 0xfe85 309 | I2CTXD equ 0xfe86 310 | I2CRXD equ 0xfe87 311 | I2CMSAUX equ 0xfe88 312 | TM2PS equ 0xfea2 313 | TM3PS equ 0xfea3 314 | TM4PS equ 0xfea4 315 | ADCTIM equ 0xfea8 316 | ADCEXCFG equ 0xfead 317 | CMPEXCFG equ 0xfeae 318 | P0INTE equ 0xfd00 319 | P1INTE equ 0xfd01 320 | P2INTE equ 0xfd02 321 | P3INTE equ 0xfd03 322 | P4INTE equ 0xfd04 323 | P5INTE equ 0xfd05 324 | P6INTE equ 0xfd06 325 | P7INTE equ 0xfd07 326 | P0INTF equ 0xfd10 327 | P1INTF equ 0xfd11 328 | P2INTF equ 0xfd12 329 | P3INTF equ 0xfd13 330 | P4INTF equ 0xfd14 331 | P5INTF equ 0xfd15 332 | P6INTF equ 0xfd16 333 | P7INTF equ 0xfd17 334 | P0IM0 equ 0xfd20 335 | P1IM0 equ 0xfd21 336 | P2IM0 equ 0xfd22 337 | P3IM0 equ 0xfd23 338 | P4IM0 equ 0xfd24 339 | P5IM0 equ 0xfd25 340 | P6IM0 equ 0xfd26 341 | P7IM0 equ 0xfd27 342 | P0IM1 equ 0xfd30 343 | P1IM1 equ 0xfd31 344 | P2IM1 equ 0xfd32 345 | P3IM1 equ 0xfd33 346 | P4IM1 equ 0xfd34 347 | P5IM1 equ 0xfd35 348 | P6IM1 equ 0xfd36 349 | P7IM1 equ 0xfd37 350 | P0WKUE equ 0xfd40 351 | P1WKUE equ 0xfd41 352 | P2WKUE equ 0xfd42 353 | P3WKUE equ 0xfd43 354 | P4WKUE equ 0xfd44 355 | P5WKUE equ 0xfd45 356 | P6WKUE equ 0xfd46 357 | P7WKUE equ 0xfd47 358 | CCAPM3 equ 0xfd54 359 | CCAP3L equ 0xfd55 360 | CCAP3H equ 0xfd56 361 | PCA_PWM3 equ 0xfd57 362 | PIN_IP equ 0xfd60 363 | PIN_IPH equ 0xfd61 364 | CHIPID0 equ 0xfde0 365 | CHIPID1 equ 0xfde1 366 | CHIPID2 equ 0xfde2 367 | CHIPID3 equ 0xfde3 368 | CHIPID4 equ 0xfde4 369 | CHIPID5 equ 0xfde5 370 | CHIPID6 equ 0xfde6 371 | CHIPID7 equ 0xfde7 372 | CHIPID8 equ 0xfde8 373 | CHIPID9 equ 0xfde9 374 | CHIPID10 equ 0xfdea 375 | CHIPID11 equ 0xfdeb 376 | CHIPID12 equ 0xfdec 377 | CHIPID13 equ 0xfded 378 | CHIPID14 equ 0xfdee 379 | CHIPID15 equ 0xfdef 380 | CHIPID16 equ 0xfdf0 381 | CHIPID17 equ 0xfdf1 382 | CHIPID18 equ 0xfdf2 383 | CHIPID19 equ 0xfdf3 384 | CHIPID20 equ 0xfdf4 385 | CHIPID21 equ 0xfdf5 386 | CHIPID22 equ 0xfdf6 387 | CHIPID23 equ 0xfdf7 388 | CHIPID24 equ 0xfdf8 389 | CHIPID25 equ 0xfdf9 390 | CHIPID26 equ 0xfdfa 391 | CHIPID27 equ 0xfdfb 392 | CHIPID28 equ 0xfdfc 393 | CHIPID29 equ 0xfdfd 394 | CHIPID30 equ 0xfdfe 395 | CHIPID31 equ 0xfdff 396 | MD3 equ 0xfcf0 397 | MD2 equ 0xfcf1 398 | MD1 equ 0xfcf2 399 | MD0 equ 0xfcf3 400 | MD5 equ 0xfcf4 401 | MD4 equ 0xfcf5 402 | dwOP1 equ 0xfcf0 403 | wOP1 equ 0xfcf2 404 | wOP2 equ 0xfcf4 405 | ARCON equ 0xfcf6 406 | OPCON equ 0xfcf7 407 | DMA_ADC_CFG equ 0xfa10 408 | DMA_ADC_CR equ 0xfa11 409 | DMA_ADC_STA equ 0xfa12 410 | DMA_ADC_RXA equ 0xfa17 411 | DMA_ADC_RXAH equ 0xfa17 412 | DMA_ADC_RXAL equ 0xfa18 413 | DMA_ADC_CFG2 equ 0xfa19 414 | DMA_ADC_CHSW0 equ 0xfa1a 415 | DMA_ADC_CHSW1 equ 0xfa1b 416 | DMA_SPI_CFG equ 0xfa20 417 | DMA_SPI_CR equ 0xfa21 418 | DMA_SPI_STA equ 0xfa22 419 | DMA_SPI_AMT equ 0xfa23 420 | DMA_SPI_DONE equ 0xfa24 421 | DMA_SPI_TXA equ 0xfa25 422 | DMA_SPI_TXAH equ 0xfa25 423 | DMA_SPI_TXAL equ 0xfa26 424 | DMA_SPI_RXA equ 0xfa27 425 | DMA_SPI_RXAH equ 0xfa27 426 | DMA_SPI_RXAL equ 0xfa28 427 | DMA_SPI_CFG2 equ 0xfa29 428 | DMA_UR1T_CFG equ 0xfa30 429 | DMA_UR1T_CR equ 0xfa31 430 | DMA_UR1T_STA equ 0xfa32 431 | DMA_UR1T_AMT equ 0xfa33 432 | DMA_UR1T_DONE equ 0xfa34 433 | DMA_UR1T_TXA equ 0xfa35 434 | DMA_UR1T_TXAH equ 0xfa35 435 | DMA_UR1T_TXAL equ 0xfa36 436 | DMA_UR1R_CFG equ 0xfa38 437 | DMA_UR1R_CR equ 0xfa39 438 | DMA_UR1R_STA equ 0xfa3a 439 | DMA_UR1R_AMT equ 0xfa3b 440 | DMA_UR1R_DONE equ 0xfa3c 441 | DMA_UR1R_RXA equ 0xfa3d 442 | DMA_UR1R_RXAH equ 0xfa3d 443 | DMA_UR1R_RXAL equ 0xfa3e 444 | DMA_UR2T_CFG equ 0xfa40 445 | DMA_UR2T_CR equ 0xfa41 446 | DMA_UR2T_STA equ 0xfa42 447 | DMA_UR2T_AMT equ 0xfa43 448 | DMA_UR2T_DONE equ 0xfa44 449 | DMA_UR2T_TXA equ 0xfa45 450 | DMA_UR2T_TXAH equ 0xfa45 451 | DMA_UR2T_TXAL equ 0xfa46 452 | DMA_UR2R_CFG equ 0xfa48 453 | DMA_UR2R_CR equ 0xfa49 454 | DMA_UR2R_STA equ 0xfa4a 455 | DMA_UR2R_AMT equ 0xfa4b 456 | DMA_UR2R_DONE equ 0xfa4c 457 | DMA_UR2R_RXA equ 0xfa4d 458 | DMA_UR2R_RXAH equ 0xfa4d 459 | DMA_UR2R_RXAL equ 0xfa4e 460 | DMA_UR3T_CFG equ 0xfa50 461 | DMA_UR3T_CR equ 0xfa51 462 | DMA_UR3T_STA equ 0xfa52 463 | DMA_UR3T_AMT equ 0xfa53 464 | DMA_UR3T_DONE equ 0xfa54 465 | DMA_UR3T_TXA equ 0xfa55 466 | DMA_UR3T_TXAH equ 0xfa55 467 | DMA_UR3T_TXAL equ 0xfa56 468 | DMA_UR3R_CFG equ 0xfa58 469 | DMA_UR3R_CR equ 0xfa59 470 | DMA_UR3R_STA equ 0xfa5a 471 | DMA_UR3R_AMT equ 0xfa5b 472 | DMA_UR3R_DONE equ 0xfa5c 473 | DMA_UR3R_RXA equ 0xfa5d 474 | DMA_UR3R_RXAH equ 0xfa5d 475 | DMA_UR3R_RXAL equ 0xfa5e 476 | DMA_UR4T_CFG equ 0xfa60 477 | DMA_UR4T_CR equ 0xfa61 478 | DMA_UR4T_STA equ 0xfa62 479 | DMA_UR4T_AMT equ 0xfa63 480 | DMA_UR4T_DONE equ 0xfa64 481 | DMA_UR4T_TXA equ 0xfa65 482 | DMA_UR4T_TXAH equ 0xfa65 483 | DMA_UR4T_TXAL equ 0xfa66 484 | DMA_UR4R_CFG equ 0xfa68 485 | DMA_UR4R_CR equ 0xfa69 486 | DMA_UR4R_STA equ 0xfa6a 487 | DMA_UR4R_AMT equ 0xfa6b 488 | DMA_UR4R_DONE equ 0xfa6c 489 | DMA_UR4R_RXA equ 0xfa6d 490 | DMA_UR4R_RXAH equ 0xfa6d 491 | DMA_UR4R_RXAL equ 0xfa6e 492 | DMA_LCM_CFG equ 0xfa70 493 | DMA_LCM_CR equ 0xfa71 494 | DMA_LCM_STA equ 0xfa72 495 | DMA_LCM_AMT equ 0xfa73 496 | DMA_LCM_DONE equ 0xfa74 497 | DMA_LCM_TXA equ 0xfa75 498 | DMA_LCM_TXAH equ 0xfa75 499 | DMA_LCM_TXAL equ 0xfa76 500 | DMA_LCM_RXA equ 0xfa77 501 | DMA_LCM_RXAH equ 0xfa77 502 | DMA_LCM_RXAL equ 0xfa78 503 | -------------------------------------------------------------------------------- /naken_asm-headers/stc8cxx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC8Cxx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC8Cxx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | P0 equ 0x80 13 | SP equ 0x81 14 | DPL equ 0x82 15 | DPH equ 0x83 16 | PCON equ 0x87 17 | TCON equ 0x88 18 | TMOD equ 0x89 19 | TL0 equ 0x8A 20 | TL1 equ 0x8B 21 | TH0 equ 0x8C 22 | TH1 equ 0x8D 23 | AUXR equ 0x8E 24 | INTCLKO equ 0x8F 25 | P1 equ 0x90 26 | P1M1 equ 0x91 27 | P1M0 equ 0x92 28 | P0M1 equ 0x93 29 | P0M0 equ 0x94 30 | P2M1 equ 0x95 31 | P2M0 equ 0x96 32 | SCON equ 0x98 33 | SBUF equ 0x99 34 | S2CON equ 0x9A 35 | S2BUF equ 0x9B 36 | IRCBAND equ 0x9D 37 | LIRTRIM equ 0x9E 38 | IRTRIM equ 0x9F 39 | P2 equ 0xA0 40 | BUS_SPEED equ 0xA1 41 | P_SW1 equ 0xA2 42 | IE equ 0xA8 43 | SADDR equ 0xA9 44 | WKTCL equ 0xAA 45 | WKTCH equ 0xAB 46 | TA equ 0xAE 47 | IE2 equ 0xAF 48 | P3 equ 0xB0 49 | P3M1 equ 0xB1 50 | P3M0 equ 0xB2 51 | P4M1 equ 0xB3 52 | P4M0 equ 0xB4 53 | IP2 equ 0xB5 54 | IP2H equ 0xB6 55 | IPH equ 0xB7 56 | IP equ 0xB8 57 | SADEN equ 0xB9 58 | P_SW2 equ 0xBA 59 | P4 equ 0xC0 60 | WDT_CONTR equ 0xC1 61 | IAP_DATA equ 0xC2 62 | IAP_ADDRH equ 0xC3 63 | IAP_ADDRL equ 0xC4 64 | IAP_CMD equ 0xC5 65 | IAP_TRIG equ 0xC6 66 | IAP_CONTR equ 0xC7 67 | P5 equ 0xC8 68 | P5M1 equ 0xC9 69 | P5M0 equ 0xCA 70 | SPSTAT equ 0xCD 71 | SPCTL equ 0xCE 72 | SPDAT equ 0xCF 73 | PSW equ 0xD0 74 | T4T3M equ 0xD1 75 | T4H equ 0xD2 76 | T4L equ 0xD3 77 | T3H equ 0xD4 78 | T3L equ 0xD5 79 | T2H equ 0xD6 80 | IP3 equ 0xDF 81 | ACC equ 0xE0 82 | DPS equ 0xE3 83 | DPL1 equ 0xE4 84 | DPH1 equ 0xE5 85 | CMPCR1 equ 0xE6 86 | CMPCR2 equ 0xE7 87 | IP3H equ 0xEE 88 | AUXINTIF equ 0xEF 89 | B equ 0xF0 90 | IAP_TPS equ 0xF5 91 | RSTCFG equ 0xFF 92 | 93 | ; bit aliases 94 | 95 | TF1 equ 0x88.7 96 | TR1 equ 0x88.6 97 | TF0 equ 0x88.5 98 | TR0 equ 0x88.4 99 | IE1 equ 0x88.3 100 | IT1 equ 0x88.2 101 | IE0 equ 0x88.1 102 | IT0 equ 0x88.0 103 | SM0 equ 0x98.7 104 | SM1 equ 0x98.6 105 | SM2 equ 0x98.5 106 | REN equ 0x98.4 107 | TB8 equ 0x98.3 108 | RB8 equ 0x98.2 109 | TI equ 0x98.1 110 | RI equ 0x98.0 111 | EA equ 0xA8.7 112 | ELVD equ 0xA8.6 113 | EADC equ 0xA8.5 114 | ES equ 0xA8.4 115 | ET1 equ 0xA8.3 116 | EX1 equ 0xA8.2 117 | ET0 equ 0xA8.1 118 | EX0 equ 0xA8.0 119 | PLVD equ 0xB8.6 120 | PS equ 0xB8.4 121 | PT1 equ 0xB8.3 122 | PX1 equ 0xB8.2 123 | PT0 equ 0xB8.1 124 | PX0 equ 0xB8.0 125 | CY equ 0xD0.7 126 | AC equ 0xD0.6 127 | F0 equ 0xD0.5 128 | RS1 equ 0xD0.4 129 | RS0 equ 0xD0.3 130 | OV equ 0xD0.2 131 | F1 equ 0xD0.1 132 | P equ 0xD0.0 133 | 134 | ; xdata 135 | 136 | CKSEL equ 0xfe00 137 | CLKDIV equ 0xfe01 138 | HIRCCR equ 0xfe02 139 | XOSCCR equ 0xfe03 140 | IRC32KCR equ 0xfe04 141 | MCLKOCR equ 0xfe05 142 | IRCDB equ 0xfe06 143 | P0PU equ 0xfe10 144 | P1PU equ 0xfe11 145 | P2PU equ 0xfe12 146 | P3PU equ 0xfe13 147 | P4PU equ 0xfe14 148 | P5PU equ 0xfe15 149 | P0NCS equ 0xfe18 150 | P1NCS equ 0xfe19 151 | P2NCS equ 0xfe1a 152 | P3NCS equ 0xfe1b 153 | P4NCS equ 0xfe1c 154 | P5NCS equ 0xfe1d 155 | P0SR equ 0xfe20 156 | P1SR equ 0xfe21 157 | P2SR equ 0xfe22 158 | P3SR equ 0xfe23 159 | P4SR equ 0xfe24 160 | P5SR equ 0xfe25 161 | P0DR equ 0xfe28 162 | P1DR equ 0xfe29 163 | P2DR equ 0xfe2a 164 | P3DR equ 0xfe2b 165 | P4DR equ 0xfe2c 166 | P5DR equ 0xfe2d 167 | P0IE equ 0xfe30 168 | P1IE equ 0xfe31 169 | I2CCFG equ 0xfe80 170 | I2CMSCR equ 0xfe81 171 | I2CMSST equ 0xfe82 172 | I2CSLCR equ 0xfe83 173 | I2CSLST equ 0xfe84 174 | I2CSLADR equ 0xfe85 175 | I2CTXD equ 0xfe86 176 | I2CRXD equ 0xfe87 177 | I2CMSAUX equ 0xfe88 178 | TM2PS equ 0xfea2 179 | TM3PS equ 0xfea3 180 | TM4PS equ 0xfea4 181 | P0INTE equ 0xfd00 182 | P1INTE equ 0xfd01 183 | P2INTE equ 0xfd02 184 | P3INTE equ 0xfd03 185 | P4INTE equ 0xfd04 186 | P5INTE equ 0xfd05 187 | P0INTF equ 0xfd10 188 | P1INTF equ 0xfd11 189 | P2INTF equ 0xfd12 190 | P3INTF equ 0xfd13 191 | P4INTF equ 0xfd14 192 | P5INTF equ 0xfd15 193 | P0IM0 equ 0xfd20 194 | P1IM0 equ 0xfd21 195 | P2IM0 equ 0xfd22 196 | P3IM0 equ 0xfd23 197 | P4IM0 equ 0xfd24 198 | P5IM0 equ 0xfd25 199 | P0IM1 equ 0xfd30 200 | P1IM1 equ 0xfd31 201 | P2IM1 equ 0xfd32 202 | P3IM1 equ 0xfd33 203 | P4IM1 equ 0xfd34 204 | P5IM1 equ 0xfd35 205 | MD3 equ 0xfcf0 206 | MD2 equ 0xfcf1 207 | MD1 equ 0xfcf2 208 | MD0 equ 0xfcf3 209 | MD5 equ 0xfcf4 210 | MD4 equ 0xfcf5 211 | ARCON equ 0xfcf6 212 | OPCON equ 0xfcf7 213 | -------------------------------------------------------------------------------- /naken_asm-headers/stc8fxx.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC8Axx/STC8Fxx include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC8Axx / STC8Fxx 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | ACC equ 0xe0 13 | B equ 0xf0 14 | PSW equ 0xd0 15 | SP equ 0x81 16 | DPL equ 0x82 17 | DPH equ 0x83 18 | TA equ 0xae 19 | DPS equ 0xe3 20 | DPL1 equ 0xe4 21 | DPH1 equ 0xe5 22 | P0 equ 0x80 23 | P1 equ 0x90 24 | P2 equ 0xa0 25 | P3 equ 0xb0 26 | P4 equ 0xc0 27 | P5 equ 0xc8 28 | P6 equ 0xe8 29 | P7 equ 0xf8 30 | P0M0 equ 0x94 31 | P0M1 equ 0x93 32 | P1M0 equ 0x92 33 | P1M1 equ 0x91 34 | P2M0 equ 0x96 35 | P2M1 equ 0x95 36 | P3M0 equ 0xb2 37 | P3M1 equ 0xb1 38 | P4M0 equ 0xb4 39 | P4M1 equ 0xb3 40 | P5M0 equ 0xca 41 | P5M1 equ 0xc9 42 | P6M0 equ 0xcc 43 | P6M1 equ 0xcb 44 | P7M0 equ 0xe2 45 | P7M1 equ 0xe1 46 | PCON equ 0x87 47 | AUXR equ 0x8e 48 | AUXR2 equ 0x97 49 | BUS_SPEED equ 0xa1 50 | P_SW1 equ 0xa2 51 | P_SW2 equ 0xba 52 | VOCTRL equ 0xbb 53 | RSTCFG equ 0xff 54 | IE equ 0xa8 55 | IE2 equ 0xaf 56 | IP equ 0xb8 57 | IP2 equ 0xb5 58 | IPH equ 0xb7 59 | IP2H equ 0xb6 60 | INTCLKO equ 0x8f 61 | AUXINTIF equ 0xef 62 | TCON equ 0x88 63 | TMOD equ 0x89 64 | TL0 equ 0x8a 65 | TL1 equ 0x8b 66 | TH0 equ 0x8c 67 | TH1 equ 0x8d 68 | T4T3M equ 0xd1 69 | T4H equ 0xd2 70 | T4L equ 0xd3 71 | T3H equ 0xd4 72 | T3L equ 0xd5 73 | T2H equ 0xd6 74 | T2L equ 0xd7 75 | TH4 equ 0xd2 76 | TL4 equ 0xd3 77 | TH3 equ 0xd4 78 | TL3 equ 0xd5 79 | TH2 equ 0xd6 80 | TL2 equ 0xd7 81 | WKTCL equ 0xaa 82 | WKTCH equ 0xab 83 | WDT_CONTR equ 0xc1 84 | SCON equ 0x98 85 | SBUF equ 0x99 86 | S2CON equ 0x9a 87 | S2BUF equ 0x9b 88 | S3CON equ 0xac 89 | S3BUF equ 0xad 90 | S4CON equ 0x84 91 | S4BUF equ 0x85 92 | SADDR equ 0xa9 93 | SADEN equ 0xb9 94 | ADC_CONTR equ 0xbc 95 | ADC_RES equ 0xbd 96 | ADC_RESL equ 0xbe 97 | ADCCFG equ 0xde 98 | SPSTAT equ 0xcd 99 | SPCTL equ 0xce 100 | SPDAT equ 0xcf 101 | IAP_DATA equ 0xc2 102 | IAP_ADDRH equ 0xc3 103 | IAP_ADDRL equ 0xc4 104 | IAP_CMD equ 0xc5 105 | IAP_TRIG equ 0xc6 106 | IAP_CONTR equ 0xc7 107 | ISP_DATA equ 0xc2 108 | ISP_ADDRH equ 0xc3 109 | ISP_ADDRL equ 0xc4 110 | ISP_CMD equ 0xc5 111 | ISP_TRIG equ 0xc6 112 | ISP_CONTR equ 0xc7 113 | CMPCR1 equ 0xe6 114 | CMPCR2 equ 0xe7 115 | CCON equ 0xd8 116 | CMOD equ 0xd9 117 | CL equ 0xe9 118 | CH equ 0xf9 119 | CCAPM0 equ 0xda 120 | CCAPM1 equ 0xdb 121 | CCAPM2 equ 0xdc 122 | CCAPM3 equ 0xdd 123 | CCAP0L equ 0xea 124 | CCAP1L equ 0xeb 125 | CCAP2L equ 0xec 126 | CCAP3L equ 0xed 127 | CCAP0H equ 0xfa 128 | CCAP1H equ 0xfb 129 | CCAP2H equ 0xfc 130 | CCAP3H equ 0xfd 131 | PCA_PWM0 equ 0xf2 132 | PCA_PWM1 equ 0xf3 133 | PCA_PWM2 equ 0xf4 134 | PCA_PWM3 equ 0xf5 135 | PWMCFG equ 0xf1 136 | PWMIF equ 0xf6 137 | PWMFDCR equ 0xf7 138 | PWMCR equ 0xfe 139 | 140 | ; bit aliases 141 | 142 | CY equ 0xd0.7 143 | AC equ 0xd0.6 144 | F0 equ 0xd0.5 145 | RS1 equ 0xd0.4 146 | RS0 equ 0xd0.3 147 | OV equ 0xd0.2 148 | F1 equ 0xd0.1 149 | P equ 0xd0.0 150 | EA equ 0xa8.7 151 | ELVD equ 0xa8.6 152 | EADC equ 0xa8.5 153 | ES equ 0xa8.4 154 | ET1 equ 0xa8.3 155 | EX1 equ 0xa8.2 156 | ET0 equ 0xa8.1 157 | EX0 equ 0xa8.0 158 | PPCA equ 0xb8.7 159 | PLVD equ 0xb8.6 160 | PADC equ 0xb8.5 161 | PS equ 0xb8.4 162 | PT1 equ 0xb8.3 163 | PX1 equ 0xb8.2 164 | PT0 equ 0xb8.1 165 | PX0 equ 0xb8.0 166 | TF1 equ 0x88.7 167 | TR1 equ 0x88.6 168 | TF0 equ 0x88.5 169 | TR0 equ 0x88.4 170 | IE1 equ 0x88.3 171 | IT1 equ 0x88.2 172 | IE0 equ 0x88.1 173 | IT0 equ 0x88.0 174 | SM0 equ 0x98.7 175 | SM1 equ 0x98.6 176 | SM2 equ 0x98.5 177 | REN equ 0x98.4 178 | TB8 equ 0x98.3 179 | RB8 equ 0x98.2 180 | TI equ 0x98.1 181 | RI equ 0x98.0 182 | CF equ 0xd8.7 183 | CR equ 0xd8.6 184 | CCF3 equ 0xd8.3 185 | CCF2 equ 0xd8.2 186 | CCF1 equ 0xd8.1 187 | CCF0 equ 0xd8.0 188 | 189 | ; xdata 190 | 191 | P0PU equ 0xfe10 192 | P1PU equ 0xfe11 193 | P2PU equ 0xfe12 194 | P3PU equ 0xfe13 195 | P4PU equ 0xfe14 196 | P5PU equ 0xfe15 197 | P6PU equ 0xfe16 198 | P7PU equ 0xfe17 199 | P0NCS equ 0xfe18 200 | P1NCS equ 0xfe19 201 | P2NCS equ 0xfe1a 202 | P3NCS equ 0xfe1b 203 | P4NCS equ 0xfe1c 204 | P5NCS equ 0xfe1d 205 | P6NCS equ 0xfe1e 206 | P7NCS equ 0xfe1f 207 | CKSEL equ 0xfe00 208 | CLKDIV equ 0xfe01 209 | IRC24MCR equ 0xfe02 210 | XOSCCR equ 0xfe03 211 | IRC32KCR equ 0xfe04 212 | PWMC equ 0xfff0 213 | PWMCH equ 0xfff0 214 | PWMCL equ 0xfff1 215 | PWMCKS equ 0xfff2 216 | TADCP equ 0xfff3 217 | TADCPH equ 0xfff3 218 | TADCPL equ 0xfff4 219 | PWM0T1 equ 0xff00 220 | PWM0T1H equ 0xff00 221 | PWM0T1L equ 0xff01 222 | PWM0T2 equ 0xff02 223 | PWM0T2H equ 0xff02 224 | PWM0T2L equ 0xff03 225 | PWM0CR equ 0xff04 226 | PWM0HLD equ 0xff05 227 | PWM1T1 equ 0xff10 228 | PWM1T1H equ 0xff10 229 | PWM1T1L equ 0xff11 230 | PWM1T2 equ 0xff12 231 | PWM1T2H equ 0xff12 232 | PWM1T2L equ 0xff13 233 | PWM1CR equ 0xff14 234 | PWM1HLD equ 0xff15 235 | PWM2T1 equ 0xff20 236 | PWM2T1H equ 0xff20 237 | PWM2T1L equ 0xff21 238 | PWM2T2 equ 0xff22 239 | PWM2T2H equ 0xff22 240 | PWM2T2L equ 0xff23 241 | PWM2CR equ 0xff24 242 | PWM2HLD equ 0xff25 243 | PWM3T1 equ 0xff30 244 | PWM3T1H equ 0xff30 245 | PWM3T1L equ 0xff31 246 | PWM3T2 equ 0xff32 247 | PWM3T2H equ 0xff32 248 | PWM3T2L equ 0xff33 249 | PWM3CR equ 0xff34 250 | PWM3HLD equ 0xff35 251 | PWM4T1 equ 0xff40 252 | PWM4T1H equ 0xff40 253 | PWM4T1L equ 0xff41 254 | PWM4T2 equ 0xff42 255 | PWM4T2H equ 0xff42 256 | PWM4T2L equ 0xff43 257 | PWM4CR equ 0xff44 258 | PWM4HLD equ 0xff45 259 | PWM5T1 equ 0xff50 260 | PWM5T1H equ 0xff50 261 | PWM5T1L equ 0xff51 262 | PWM5T2 equ 0xff52 263 | PWM5T2H equ 0xff52 264 | PWM5T2L equ 0xff53 265 | PWM5CR equ 0xff54 266 | PWM5HLD equ 0xff55 267 | PWM6T1 equ 0xff60 268 | PWM6T1H equ 0xff60 269 | PWM6T1L equ 0xff61 270 | PWM6T2 equ 0xff62 271 | PWM6T2H equ 0xff62 272 | PWM6T2L equ 0xff63 273 | PWM6CR equ 0xff64 274 | PWM6HLD equ 0xff65 275 | PWM7T1 equ 0xff70 276 | PWM7T1H equ 0xff70 277 | PWM7T1L equ 0xff71 278 | PWM7T2 equ 0xff72 279 | PWM7T2H equ 0xff72 280 | PWM7T2L equ 0xff73 281 | PWM7CR equ 0xff74 282 | PWM7HLD equ 0xff75 283 | I2CCFG equ 0xfe80 284 | I2CMSCR equ 0xfe81 285 | I2CMSST equ 0xfe82 286 | I2CSLCR equ 0xfe83 287 | I2CSLST equ 0xfe84 288 | I2CSLADR equ 0xfe85 289 | I2CTXD equ 0xfe86 290 | I2CRXD equ 0xfe87 291 | -------------------------------------------------------------------------------- /naken_asm-headers/stc90c5xad.inc: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; STC90C5xAD include 4 | ;; part of the naken_asm assembler 5 | ;; 6 | ;; Generated by: Cjacker Huang (cjacker@gmail.com) 7 | ;; Date: 2022-05-21 8 | ;; Parts: STC90C5xAD 9 | ;; 10 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 11 | 12 | P4 equ 0xc0 13 | XICON equ 0xe8 14 | WDT_CONTR equ 0xe1 15 | ISP_DATA equ 0xe2 16 | ISP_ADDRH equ 0xe3 17 | ISP_ADDRL equ 0xe4 18 | ISP_CMD equ 0xe5 19 | ISP_TRIG equ 0xe6 20 | ISP_CONTR equ 0xe7 21 | P0 equ 0x80 22 | P1 equ 0x90 23 | P2 equ 0xA0 24 | P3 equ 0xB0 25 | PSW equ 0xD0 26 | ACC equ 0xE0 27 | B equ 0xF0 28 | SP equ 0x81 29 | DPL equ 0x82 30 | DPH equ 0x83 31 | PCON equ 0x87 32 | TCON equ 0x88 33 | TMOD equ 0x89 34 | TL0 equ 0x8A 35 | TL1 equ 0x8B 36 | TH0 equ 0x8C 37 | TH1 equ 0x8D 38 | IE equ 0xA8 39 | IP equ 0xB8 40 | SCON equ 0x98 41 | SBUF equ 0x99 42 | AUXR equ 0x8E 43 | AUXR1 equ 0xA2 44 | SADDR equ 0xA9 45 | IPH equ 0xB7 46 | SADEN equ 0xB9 47 | T2CON equ 0xC8 48 | T2MOD equ 0xC9 49 | RCAP2L equ 0xCA 50 | RCAP2H equ 0xCB 51 | TL2 equ 0xCC 52 | TH2 equ 0xCD 53 | 54 | ; bit aliases 55 | 56 | CY equ 0xD0.7 57 | AC equ 0xD0.6 58 | F0 equ 0xD0.5 59 | RS1 equ 0xD0.4 60 | RS0 equ 0xD0.3 61 | OV equ 0xD0.2 62 | F1 equ 0xD0.1 63 | P equ 0xD0.0 64 | TF1 equ 0x88.7 65 | TR1 equ 0x88.6 66 | TF0 equ 0x88.5 67 | TR0 equ 0x88.4 68 | IE1 equ 0x88.3 69 | IT1 equ 0x88.2 70 | IE0 equ 0x88.1 71 | IT0 equ 0x88.0 72 | EA equ 0xA8.7 73 | EC equ 0xA8.6 74 | ET2 equ 0xA8.5 75 | ES equ 0xA8.4 76 | ET1 equ 0xA8.3 77 | EX1 equ 0xA8.2 78 | ET0 equ 0xA8.1 79 | EX0 equ 0xA8.0 80 | PT2 equ 0xB8.5 81 | PS equ 0xB8.4 82 | PT1 equ 0xB8.3 83 | PX1 equ 0xB8.2 84 | PT0 equ 0xB8.1 85 | PX0 equ 0xB8.0 86 | RD equ 0xB0.7 87 | WR equ 0xB0.6 88 | T1 equ 0xB0.5 89 | T0 equ 0xB0.4 90 | INT1 equ 0xB0.3 91 | INT0 equ 0xB0.2 92 | TXD equ 0xB0.1 93 | RXD equ 0xB0.0 94 | SM0 equ 0x98.7 95 | FE equ 0x98.7 96 | SM1 equ 0x98.6 97 | SM2 equ 0x98.5 98 | REN equ 0x98.4 99 | TB8 equ 0x98.3 100 | RB8 equ 0x98.2 101 | TI equ 0x98.1 102 | RI equ 0x98.0 103 | T2EX equ 0x90.1 104 | T2 equ 0x90.0 105 | TF2 equ 0xC8.7 106 | EXF2 equ 0xC8.6 107 | RCLK equ 0xC8.5 108 | TCLK equ 0xC8.4 109 | EXEN2 equ 0xC8.3 110 | TR2 equ 0xC8.2 111 | C_T2 equ 0xC8.1 112 | CP_RL2 equ 0xC8.0 113 | 114 | ; xdata 115 | 116 | -------------------------------------------------------------------------------- /stc-nameing-schema.md: -------------------------------------------------------------------------------- 1 | # STC 8051 MCU 2 | 3 | STC is a Chinese semiconductor manufacturer, it took the model of 8051 and upgraded it to new levels by implementing some vital upgrades, enhancements and additions. It also manufactures standard 8051s which are designed to fit in place of any other 8051s from any manufacturer. At present STC has several different variants of 8051s, ranging from standard 40 pin regular DIP 8051s to tiny 8-pin variants. 4 | 5 | There are some STC microcontrollers like STC89C52RC that are same as the standard ones while others like STC8H8K64U are more robust with many advanced features. you should refer to corresponding datasheet of the chip for details. 6 | 7 | The model name conventions of STC 8051 is different for every different generation, it is not well-regulated, but still have some rules, usually the model name of STC8051 consist of: 8 | 9 | `STC[generation] [one or two letters for voltage range] [some numbers for ram/rom size descriptions] [a suffix to describe special features]` 10 | 11 | The generation of STC 8051 include 89/90/10/11/12/15 and 8[A|C|F|G|H]. 12 | 13 | The voltage range usually is 'c' or 'f' for 3.5-5.5v voltage range, 'l' or 'le' for 2.0-3.6v voltage range and 'w' for 2.0-5.5 wide voltage range. but the latest STC 8[A|C|F|G|H] series and some special modules does NOT follow these rules. 14 | 15 | The ram/rom size descriptions and the suffix are not same meanings for different generation, but it follow the same rule for different models of same generation. Again, please refer to corresponding datasheet for details. 16 | 17 | For example, STC89C516AD, the '89' means STC 89 series, 'C' means 3.5-5.5v voltage range, '16' means 64k rom size(5 of 516 has no meaning, 16 means 16x4k rom size), with 'AD' support, it's a ['12T'](https://en.wikipedia.org/wiki/Instruction_cycle) 8051 MCU. STC also provide 6T and 1T MCU. 18 | 19 | Since STC 8051 is the most famous and popular 8051 MCU in China, this tutorial will mostly focus on STC 8051. there is not so much different between 8051 MCUs from different vendors, so you can also refer to this tutorial even use chips from other vendors. 20 | 21 | By the way, STCmcu also have STC16/STC32 80251 series MCU, and without opensource toolchain support up to this tutorial written. But you still can use 8051 opensource toolchains with such 80251 MCU, it's binary compatible. 22 | --------------------------------------------------------------------------------