├── LICENSE
├── Makefile
├── STM32F30x_StdPeriph_Driver
├── Release_Notes.html
├── inc
│ ├── stm32f30x_adc.h
│ ├── stm32f30x_can.h
│ ├── stm32f30x_comp.h
│ ├── stm32f30x_crc.h
│ ├── stm32f30x_dac.h
│ ├── stm32f30x_dbgmcu.h
│ ├── stm32f30x_dma.h
│ ├── stm32f30x_exti.h
│ ├── stm32f30x_flash.h
│ ├── stm32f30x_gpio.h
│ ├── stm32f30x_i2c.h
│ ├── stm32f30x_iwdg.h
│ ├── stm32f30x_misc.h
│ ├── stm32f30x_opamp.h
│ ├── stm32f30x_pwr.h
│ ├── stm32f30x_rcc.h
│ ├── stm32f30x_rtc.h
│ ├── stm32f30x_spi.h
│ ├── stm32f30x_syscfg.h
│ ├── stm32f30x_tim.h
│ ├── stm32f30x_usart.h
│ └── stm32f30x_wwdg.h
└── src
│ ├── stm32f30x_adc.c
│ ├── stm32f30x_can.c
│ ├── stm32f30x_comp.c
│ ├── stm32f30x_crc.c
│ ├── stm32f30x_dac.c
│ ├── stm32f30x_dbgmcu.c
│ ├── stm32f30x_dma.c
│ ├── stm32f30x_exti.c
│ ├── stm32f30x_flash.c
│ ├── stm32f30x_gpio.c
│ ├── stm32f30x_i2c.c
│ ├── stm32f30x_iwdg.c
│ ├── stm32f30x_misc.c
│ ├── stm32f30x_opamp.c
│ ├── stm32f30x_pwr.c
│ ├── stm32f30x_rcc.c
│ ├── stm32f30x_rtc.c
│ ├── stm32f30x_spi.c
│ ├── stm32f30x_syscfg.c
│ ├── stm32f30x_tim.c
│ ├── stm32f30x_usart.c
│ └── stm32f30x_wwdg.c
├── flash.cfg
├── lib
├── core_cm4.h
├── core_cm4_simd.h
├── core_cmFunc.h
├── core_cmInstr.h
├── startup_stm32f30x.s
├── stm32f303.ld
├── stm32f30x.h
├── stm32f30x_conf.h
├── system_stm32f30x.c
├── system_stm32f30x.h
├── systems.c
└── systems.h
├── main.c
├── stm32f30x_it.c
├── stm32f30x_it.h
└── terminal.cfg
/LICENSE:
--------------------------------------------------------------------------------
1 | STM32F303-based ColorChord 2.0 Build
2 |
3 | Copyright (c) 2015 Charles Lohr
4 |
5 | Roughly based off of: https://github.com/devthrash/0xWS2812
6 |
7 | Permission is hereby granted, free of charge, to any person obtaining a copy
8 | of this software and associated documentation files (the "Software"), to deal
9 | in the Software without restriction, including without limitation the rights
10 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 | copies of the Software, and to permit persons to whom the Software is
12 | furnished to do so, subject to the following conditions:
13 |
14 | The above copyright notice and this permission notice shall be included in
15 | all copies or substantial portions of the Software.
16 |
17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 | THE SOFTWARE.
24 |
25 |
26 |
--------------------------------------------------------------------------------
/Makefile:
--------------------------------------------------------------------------------
1 | TARGET=main
2 | all: burn
3 |
4 | PREFIX=arm-none-eabi
5 |
6 | CC=$(PREFIX)-gcc
7 | LD=$(PREFIX)-gcc
8 | AS=$(PREFIX)-as
9 | CP=$(PREFIX)-objcopy
10 | OD=$(PREFIX)-objdump
11 |
12 |
13 | OBJCOPYFLAGS = -O binary
14 |
15 | BIN=$(CP) -O ihex
16 |
17 | DEFS = -DSTM32F30X -DHSE_VALUE=25000000
18 | STARTUP = lib/startup_stm32f30x.s
19 |
20 | MCU = cortex-m3
21 | MCFLAGS = -mcpu=$(MCU) -mthumb -mlittle-endian -mthumb-interwork
22 |
23 | STM32_INCLUDES = -Ilib -I. -ISTM32F30x_StdPeriph_Driver/inc
24 |
25 |
26 | OPTIMIZE = -Os
27 |
28 | CFLAGS = $(MCFLAGS) $(OPTIMIZE) $(DEFS) -I. -I./ $(STM32_INCLUDES) -Wl,-T,lib/stm32f303.ld
29 | CFLAGS+=-DDEBUG
30 |
31 | AFLAGS = $(MCFLAGS)
32 |
33 | SRC = main.c \
34 | stm32f30x_it.c \
35 | lib/system_stm32f30x.c \
36 | lib/systems.c \
37 | STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c \
38 | STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c
39 |
40 |
41 | burn : $(TARGET).bin
42 | openocd -f flash.cfg #-d3
43 | terminal :
44 | openocd -f terminal.cfg
45 |
46 | $(TARGET).bin : $(TARGET).out
47 | $(CP) $(OBJCOPYFLAGS) $< $@
48 |
49 | $(TARGET).hex: $(EXECUTABLE)
50 | $(CP) -O ihex $^ $@
51 |
52 | $(TARGET).out : $(SRC) $(STARTUP)
53 | $(CC) $(CFLAGS) $^ -lm -lc -lnosys -o $@
54 |
55 | clean:
56 | rm -f $(TARGET).lst $(TARGET).out $(TARGET).hex $(TARGET).bin $(TARGET).map $(EXECUTABLE)
57 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/Release_Notes.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/cnlohr/minimal_stm32f303/656a71af8d555689b5c54676564156c271d734c0/STM32F30x_StdPeriph_Driver/Release_Notes.html
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_crc.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_CRC_H
31 | #define __STM32F30x_CRC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /*!< Includes ----------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup CRC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup CRC_ReverseInputData
52 | * @{
53 | */
54 | #define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
55 | #define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
56 | #define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
57 | #define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
58 |
59 | #define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
60 | ((DATA) == CRC_ReverseInputData_8bits) || \
61 | ((DATA) == CRC_ReverseInputData_16bits) || \
62 | ((DATA) == CRC_ReverseInputData_32bits))
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup CRC_PolynomialSize
69 | * @{
70 | */
71 | #define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
72 | #define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
73 | #define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
74 | #define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
75 |
76 | #define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
77 | ((SIZE) == CRC_PolSize_8) || \
78 | ((SIZE) == CRC_PolSize_16) || \
79 | ((SIZE) == CRC_PolSize_32))
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /* Exported macro ------------------------------------------------------------*/
86 | /* Exported functions ------------------------------------------------------- */
87 | /* Configuration of the CRC computation unit **********************************/
88 | void CRC_DeInit(void);
89 | void CRC_ResetDR(void);
90 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /* Select or Config, which one is the best */
91 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
92 | void CRC_ReverseOutputDataCmd(FunctionalState NewState);
93 | void CRC_SetInitRegister(uint32_t CRC_InitValue); /* change the function proto to SetInitRemainder() ??? */
94 | void CRC_SetPolynomial(uint32_t CRC_Pol);
95 |
96 | /* CRC computation ************************************************************/
97 | uint32_t CRC_CalcCRC(uint32_t CRC_Data);
98 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
99 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
100 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
101 | uint32_t CRC_GetCRC(void);
102 |
103 | /* Independent register (IDR) access (write/read) *****************************/
104 | void CRC_SetIDRegister(uint8_t CRC_IDValue);
105 | uint8_t CRC_GetIDRegister(void);
106 |
107 | #ifdef __cplusplus
108 | }
109 | #endif
110 |
111 | #endif /* __STM32F30x_CRC_H */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
122 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2012 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F30x_DBGMCU_H
30 | #define __STM32F30x_DBGMCU_H
31 |
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 |
36 | /* Includes ------------------------------------------------------------------*/
37 | #include "stm32f30x.h"
38 |
39 | /** @addtogroup STM32F30x_StdPeriph_Driver
40 | * @{
41 | */
42 |
43 | /** @addtogroup DBGMCU
44 | * @{
45 | */
46 |
47 | /* Exported types ------------------------------------------------------------*/
48 | /* Exported constants --------------------------------------------------------*/
49 |
50 | /** @defgroup DBGMCU_Exported_Constants
51 | * @{
52 | */
53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
54 | #define DBGMCU_STOP ((uint32_t)0x00000002)
55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
56 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
57 |
58 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
59 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
60 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
61 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
62 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
63 | #define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
64 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
65 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
66 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
67 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
68 | #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
69 |
70 | #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
71 |
72 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
73 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
74 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
75 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
76 | #define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
77 | #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /* Exported macro ------------------------------------------------------------*/
84 | /* Exported functions --------------------------------------------------------*/
85 | /* Device and Revision ID management functions ********************************/
86 | uint32_t DBGMCU_GetREVID(void);
87 | uint32_t DBGMCU_GetDEVID(void);
88 |
89 | /* Peripherals Configuration functions ****************************************/
90 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
91 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
92 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
93 |
94 | #ifdef __cplusplus
95 | }
96 | #endif
97 |
98 | #endif /* __STM32F30x_DBGMCU_H */
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | /**
105 | * @}
106 | */
107 |
108 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
109 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_exti.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the EXTI
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_EXTI_H
31 | #define __STM32F30x_EXTI_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup EXTI
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief EXTI mode enumeration
52 | */
53 |
54 | typedef enum
55 | {
56 | EXTI_Mode_Interrupt = 0x00,
57 | EXTI_Mode_Event = 0x04
58 | }EXTIMode_TypeDef;
59 |
60 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
61 |
62 | /**
63 | * @brief EXTI Trigger enumeration
64 | */
65 |
66 | typedef enum
67 | {
68 | EXTI_Trigger_Rising = 0x08,
69 | EXTI_Trigger_Falling = 0x0C,
70 | EXTI_Trigger_Rising_Falling = 0x10
71 | }EXTITrigger_TypeDef;
72 |
73 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
74 | ((TRIGGER) == EXTI_Trigger_Falling) || \
75 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
76 | /**
77 | * @brief EXTI Init Structure definition
78 | */
79 |
80 | typedef struct
81 | {
82 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
83 | This parameter can be any combination of @ref EXTI_Lines */
84 |
85 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
86 | This parameter can be a value of @ref EXTIMode_TypeDef */
87 |
88 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
89 | This parameter can be a value of @ref EXTITrigger_TypeDef */
90 |
91 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
92 | This parameter can be set either to ENABLE or DISABLE */
93 | }EXTI_InitTypeDef;
94 |
95 | /* Exported constants --------------------------------------------------------*/
96 |
97 | /** @defgroup EXTI_Exported_Constants
98 | * @{
99 | */
100 | /** @defgroup EXTI_Lines
101 | * @{
102 | */
103 |
104 | #define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
105 | #define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
106 | #define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
107 | #define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
108 | #define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
109 | #define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
110 | #define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
111 | #define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
112 | #define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
113 | #define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
114 | #define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
115 | #define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
116 | #define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
117 | #define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
118 | #define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
119 | #define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
120 | #define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
121 | Connected to the PVD Output */
122 | #define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
123 | Connected to the RTC Alarm
124 | event */
125 | #define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
126 | Connected to the USB Device
127 | Wakeup from suspend event */
128 | #define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
129 | Connected to the RTC Tamper
130 | and Time Stamp events */
131 | #define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
132 | Connected to the RTC wakeup
133 | event */
134 | #define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
135 | Connected to the Comparator 1
136 | event */
137 | #define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
138 | Connected to the Comparator 2
139 | event */
140 | #define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
141 | Connected to the I2C1 wakeup
142 | event */
143 | #define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
144 | Connected to the I2C2 wakeup
145 | event */
146 | #define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
147 | Connected to the USART1 wakeup
148 | event */
149 | #define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
150 | Connected to the USART2 wakeup
151 | event */
152 | #define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
153 | reserved */
154 | #define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
155 | Connected to the USART3 wakeup
156 | event */
157 | #define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
158 | Connected to the Comparator 3
159 | event */
160 | #define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
161 | Connected to the Comparator 4
162 | event */
163 | #define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
164 | Connected to the Comparator 5
165 | event */
166 | #define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
167 | Connected to the Comparator 6
168 | event */
169 | #define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
170 | Connected to the Comparator 7
171 | event */
172 | #define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
173 | Connected to the USART4 wakeup
174 | event */
175 | #define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
176 | Connected to the USART5 wakeup
177 | event */
178 |
179 | #define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
180 | #define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
181 | ((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
182 |
183 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
184 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
185 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
186 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
187 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
188 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
189 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
190 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
191 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
192 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
193 | ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
194 | ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
195 | ((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
196 | ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
197 | /**
198 | * @}
199 | */
200 |
201 | /**
202 | * @}
203 | */
204 |
205 | /* Exported macro ------------------------------------------------------------*/
206 | /* Exported functions ------------------------------------------------------- */
207 | /* Function used to set the EXTI configuration to the default reset state *****/
208 | void EXTI_DeInit(void);
209 |
210 | /* Initialization and Configuration functions *********************************/
211 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
212 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
213 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
214 |
215 | /* Interrupts and flags management functions **********************************/
216 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
217 | void EXTI_ClearFlag(uint32_t EXTI_Line);
218 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
219 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
220 |
221 | #ifdef __cplusplus
222 | }
223 | #endif
224 |
225 | #endif /* __STM32F30x_EXTI_H */
226 | /**
227 | * @}
228 | */
229 |
230 | /**
231 | * @}
232 | */
233 |
234 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
235 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_flash.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_flash.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the FLASH
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_FLASH_H
31 | #define __STM32F30x_FLASH_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup FLASH
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /**
50 | * @brief FLASH Status
51 | */
52 | typedef enum
53 | {
54 | FLASH_BUSY = 1,
55 | FLASH_ERROR_WRP,
56 | FLASH_ERROR_PROGRAM,
57 | FLASH_COMPLETE,
58 | FLASH_TIMEOUT
59 | }FLASH_Status;
60 |
61 | /* Exported constants --------------------------------------------------------*/
62 |
63 | /** @defgroup FLASH_Exported_Constants
64 | * @{
65 | */
66 |
67 | /** @defgroup Flash_Latency
68 | * @{
69 | */
70 | #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
71 | #define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
72 | #define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
73 |
74 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
75 | ((LATENCY) == FLASH_Latency_1) || \
76 | ((LATENCY) == FLASH_Latency_2))
77 | /**
78 | * @}
79 | */
80 |
81 | /** @defgroup FLASH_Interrupts
82 | * @{
83 | */
84 |
85 | #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
86 | #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
87 | #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
88 | /**
89 | * @}
90 | */
91 | /** @defgroup FLASH_Address
92 | * @{
93 | */
94 |
95 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /** @defgroup FLASH_OB_DATA_ADDRESS
102 | * @{
103 | */
104 | #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
105 |
106 | /**
107 | * @}
108 | */
109 |
110 | /** @defgroup Option_Bytes_Write_Protection
111 | * @{
112 | */
113 |
114 | #define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
115 | #define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
116 | #define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
117 | #define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
118 | #define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
119 | #define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
120 | #define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
121 | #define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
122 | #define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
123 | #define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
124 | #define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
125 | #define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
126 | #define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
127 | #define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
128 | #define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
129 | #define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
130 | #define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
131 | #define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
132 | #define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
133 | #define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
134 | #define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
135 | #define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
136 | #define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
137 | #define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
138 | #define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
139 | #define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
140 | #define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
141 | #define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
142 | #define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
143 | #define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
144 | #define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
145 | #define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
146 |
147 | #define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
148 |
149 | #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
150 |
151 | /**
152 | * @}
153 | */
154 |
155 | /** @defgroup Option_Bytes_Read_Protection
156 | * @{
157 | */
158 |
159 | /**
160 | * @brief Read Protection Level
161 | */
162 | #define OB_RDP_Level_0 ((uint8_t)0xAA)
163 | #define OB_RDP_Level_1 ((uint8_t)0xBB)
164 | /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
165 | it's no more possible to go back to level 1 or 0 */
166 |
167 | #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
168 | ((LEVEL) == OB_RDP_Level_1))/*||\
169 | ((LEVEL) == OB_RDP_Level_2))*/
170 | /**
171 | * @}
172 | */
173 |
174 | /** @defgroup Option_Bytes_IWatchdog
175 | * @{
176 | */
177 |
178 | #define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
179 | #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
180 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
181 |
182 | /**
183 | * @}
184 | */
185 |
186 | /** @defgroup Option_Bytes_nRST_STOP
187 | * @{
188 | */
189 |
190 | #define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
191 | #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
192 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
193 |
194 | /**
195 | * @}
196 | */
197 |
198 | /** @defgroup Option_Bytes_nRST_STDBY
199 | * @{
200 | */
201 |
202 | #define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
203 | #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
204 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
205 |
206 | /**
207 | * @}
208 | */
209 | /** @defgroup Option_Bytes_BOOT1
210 | * @{
211 | */
212 |
213 | #define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
214 | #define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
215 | #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
216 |
217 | /**
218 | * @}
219 | */
220 | /** @defgroup Option_Bytes_VDDA_Analog_Monitoring
221 | * @{
222 | */
223 |
224 | #define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
225 | #define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
226 |
227 | #define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
228 |
229 | /**
230 | * @}
231 | */
232 |
233 | /** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
234 | * @{
235 | */
236 |
237 | #define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
238 | #define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
239 |
240 | #define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
241 |
242 | /**
243 | * @}
244 | */
245 |
246 | /** @defgroup FLASH_Flags
247 | * @{
248 | */
249 |
250 | #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
251 | #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
252 | #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
253 | #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
254 |
255 | #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
256 |
257 | #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
258 | ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
259 | /**
260 | * @}
261 | */
262 | /** @defgroup Timeout_definition
263 | * @{
264 | */
265 | #define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
266 |
267 | /**
268 | * @}
269 | */
270 |
271 | /**
272 | * @}
273 | */
274 |
275 | /* Exported macro ------------------------------------------------------------*/
276 | /* Exported functions --------------------------------------------------------*/
277 |
278 | /* FLASH Interface configuration functions ************************************/
279 | void FLASH_SetLatency(uint32_t FLASH_Latency);
280 | void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
281 | void FLASH_PrefetchBufferCmd(FunctionalState NewState);
282 |
283 | /* FLASH Memory Programming functions *****************************************/
284 | void FLASH_Unlock(void);
285 | void FLASH_Lock(void);
286 | FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
287 | FLASH_Status FLASH_EraseAllPages(void);
288 | FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
289 | FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
290 |
291 | /* Option Bytes Programming functions *****************************************/
292 | void FLASH_OB_Unlock(void);
293 | void FLASH_OB_Lock(void);
294 | void FLASH_OB_Launch(void);
295 | FLASH_Status FLASH_OB_Erase(void);
296 | FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
297 | FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
298 | FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
299 | FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
300 | FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
301 | FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
302 | FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
303 | FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
304 | uint8_t FLASH_OB_GetUser(void);
305 | uint32_t FLASH_OB_GetWRP(void);
306 | FlagStatus FLASH_OB_GetRDP(void);
307 |
308 | /* Interrupts and flags management functions **********************************/
309 | void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
310 | FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
311 | void FLASH_ClearFlag(uint32_t FLASH_FLAG);
312 | FLASH_Status FLASH_GetStatus(void);
313 | FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
314 |
315 | #ifdef __cplusplus
316 | }
317 | #endif
318 |
319 | #endif /* __STM32F30x_FLASH_H */
320 |
321 | /**
322 | * @}
323 | */
324 |
325 | /**
326 | * @}
327 | */
328 |
329 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
330 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_iwdg.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30X_IWDG_H
31 | #define __STM32F30X_IWDG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup IWDG
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup IWDG_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup IWDG_WriteAccess
56 | * @{
57 | */
58 |
59 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
60 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
61 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
62 | ((ACCESS) == IWDG_WriteAccess_Disable))
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup IWDG_prescaler
68 | * @{
69 | */
70 |
71 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
72 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
73 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
74 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
75 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
76 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
77 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
78 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
79 | ((PRESCALER) == IWDG_Prescaler_8) || \
80 | ((PRESCALER) == IWDG_Prescaler_16) || \
81 | ((PRESCALER) == IWDG_Prescaler_32) || \
82 | ((PRESCALER) == IWDG_Prescaler_64) || \
83 | ((PRESCALER) == IWDG_Prescaler_128)|| \
84 | ((PRESCALER) == IWDG_Prescaler_256))
85 | /**
86 | * @}
87 | */
88 |
89 | /** @defgroup IWDG_Flag
90 | * @{
91 | */
92 |
93 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
94 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
95 | #define IWDG_FLAG_WVU ((uint16_t)0x0002)
96 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
97 | ((FLAG) == IWDG_FLAG_WVU))
98 | /**
99 | * @}
100 | */
101 |
102 | /** @defgroup IWDG_Reload_Value
103 | * @{
104 | */
105 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /** @defgroup IWDG_CounterWindow_Value
112 | * @{
113 | */
114 | #define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
115 | /**
116 | * @}
117 | */
118 |
119 | /**
120 | * @}
121 | */
122 |
123 | /* Exported macro ------------------------------------------------------------*/
124 | /* Exported functions --------------------------------------------------------*/
125 |
126 | /* Prescaler and Counter configuration functions ******************************/
127 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
128 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
129 | void IWDG_SetReload(uint16_t Reload);
130 | void IWDG_ReloadCounter(void);
131 | void IWDG_SetWindowValue(uint16_t WindowValue);
132 |
133 | /* IWDG activation function ***************************************************/
134 | void IWDG_Enable(void);
135 |
136 | /* Flag management function ***************************************************/
137 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
138 |
139 | #ifdef __cplusplus
140 | }
141 | #endif
142 |
143 | #endif /* __STM32F30X_IWDG_H */
144 |
145 | /**
146 | * @}
147 | */
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
154 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_misc.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the miscellaneous
8 | * firmware library functions (add-on to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_MISC_H
31 | #define __STM32F30x_MISC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup MISC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief NVIC Init Structure definition
52 | */
53 |
54 | typedef struct
55 | {
56 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
57 | This parameter can be a value of @ref IRQn_Type (For
58 | the complete STM32 Devices IRQ Channels list, please
59 | refer to stm32f30x.h file) */
60 |
61 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
62 | specified in NVIC_IRQChannel. This parameter can be a value
63 | between 0 and 15.
64 | A lower priority value indicates a higher priority */
65 |
66 |
67 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
68 | in NVIC_IRQChannel. This parameter can be a value
69 | between 0 and 15.
70 | A lower priority value indicates a higher priority */
71 |
72 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
73 | will be enabled or disabled.
74 | This parameter can be set either to ENABLE or DISABLE */
75 | } NVIC_InitTypeDef;
76 |
77 | /**
78 | *
79 | @verbatim
80 | The table below gives the allowed values of the pre-emption priority and subpriority according
81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
82 | ============================================================================================================================
83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
84 | ============================================================================================================================
85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
86 | | | | 4 bits for subpriority
87 | ----------------------------------------------------------------------------------------------------------------------------
88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
89 | | | | 3 bits for subpriority
90 | ----------------------------------------------------------------------------------------------------------------------------
91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
92 | | | | 2 bits for subpriority
93 | ----------------------------------------------------------------------------------------------------------------------------
94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
95 | | | | 1 bits for subpriority
96 | ----------------------------------------------------------------------------------------------------------------------------
97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
98 | | | | 0 bits for subpriority
99 | ============================================================================================================================
100 | @endverbatim
101 | */
102 |
103 | /* Exported constants --------------------------------------------------------*/
104 |
105 | /** @defgroup MISC_Exported_Constants
106 | * @{
107 | */
108 |
109 | /** @defgroup MISC_Vector_Table_Base
110 | * @{
111 | */
112 |
113 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
114 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
115 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
116 | ((VECTTAB) == NVIC_VectTab_FLASH))
117 | /**
118 | * @}
119 | */
120 |
121 | /** @defgroup MISC_System_Low_Power
122 | * @{
123 | */
124 |
125 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
126 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
127 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
128 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
129 | ((LP) == NVIC_LP_SLEEPDEEP) || \
130 | ((LP) == NVIC_LP_SLEEPONEXIT))
131 | /**
132 | * @}
133 | */
134 |
135 | /** @defgroup MISC_Preemption_Priority_Group
136 | * @{
137 | */
138 |
139 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
140 | 4 bits for subpriority */
141 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
142 | 3 bits for subpriority */
143 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
144 | 2 bits for subpriority */
145 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
146 | 1 bits for subpriority */
147 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
148 | 0 bits for subpriority */
149 |
150 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
151 | ((GROUP) == NVIC_PriorityGroup_1) || \
152 | ((GROUP) == NVIC_PriorityGroup_2) || \
153 | ((GROUP) == NVIC_PriorityGroup_3) || \
154 | ((GROUP) == NVIC_PriorityGroup_4))
155 |
156 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
157 |
158 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
159 |
160 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /** @defgroup MISC_SysTick_clock_source
167 | */
168 |
169 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
170 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
171 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
172 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
173 | /**
174 | * @}
175 | */
176 |
177 | /**
178 | * @}
179 | */
180 |
181 | /* Exported macro ------------------------------------------------------------*/
182 | /* Exported functions --------------------------------------------------------*/
183 |
184 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
185 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
186 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
187 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
188 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
189 |
190 | #ifdef __cplusplus
191 | }
192 | #endif
193 |
194 | #endif /* __STM32F30x_MISC_H */
195 |
196 | /**
197 | * @}
198 | */
199 |
200 | /**
201 | * @}
202 | */
203 |
204 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
205 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_opamp.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_opamp.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the operational
8 | * amplifiers (OPAMP) firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_OPAMP_H
31 | #define __STM32F30x_OPAMP_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup OPAMP
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief OPAMP Init structure definition
52 | */
53 |
54 | typedef struct
55 | {
56 |
57 | uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
58 | This parameter can be a value of @ref OPAMP_InvertingInput */
59 |
60 | uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
61 | This parameter can be a value of @ref OPAMP_NonInvertingInput */
62 |
63 | }OPAMP_InitTypeDef;
64 |
65 | /* Exported constants --------------------------------------------------------*/
66 |
67 | /** @defgroup OPAMP_Exported_Constants
68 | * @{
69 | */
70 |
71 | /** @defgroup OPAMP_Selection
72 | * @{
73 | */
74 |
75 | #define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
76 | #define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
77 | #define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
78 | #define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
79 |
80 | #define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
81 | ((PERIPH) == OPAMP_Selection_OPAMP2) || \
82 | ((PERIPH) == OPAMP_Selection_OPAMP3) || \
83 | ((PERIPH) == OPAMP_Selection_OPAMP4))
84 |
85 | /**
86 | * @}
87 | */
88 |
89 | /** @defgroup OPAMP_InvertingInput
90 | * @{
91 | */
92 |
93 | #define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
94 | connected to OPAMPx inverting input */
95 | #define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
96 | connected to OPAMPx inverting input */
97 | #define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
98 | #define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
99 |
100 | #define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
101 | ((INPUT) == OPAMP_InvertingInput_IO2) || \
102 | ((INPUT) == OPAMP_InvertingInput_PGA) || \
103 | ((INPUT) == OPAMP_InvertingInput_Vout))
104 | /**
105 | * @}
106 | */
107 |
108 | /** @defgroup OPAMP_NonInvertingInput
109 | * @{
110 | */
111 |
112 | #define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
113 | connected to OPAMPx non inverting input */
114 | #define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
115 | connected to OPAMPx non inverting input */
116 | #define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
117 | connected to OPAMPx non inverting input */
118 | #define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
119 | connected to OPAMPx non inverting input */
120 |
121 | #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
122 | ((INPUT) == OPAMP_NonInvertingInput_IO2) || \
123 | ((INPUT) == OPAMP_NonInvertingInput_IO3) || \
124 | ((INPUT) == OPAMP_NonInvertingInput_IO4))
125 | /**
126 | * @}
127 | */
128 |
129 | /** @defgroup OPAMP_PGAGain_Config
130 | * @{
131 | */
132 |
133 | #define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
134 | #define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
135 | #define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
136 | #define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
137 |
138 | #define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
139 | ((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
140 | ((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
141 | ((GAIN) == OPAMP_OPAMP_PGAGain_16))
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup OPAMP_PGAConnect_Config
147 | * @{
148 | */
149 |
150 | #define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
151 | #define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
152 | #define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
153 |
154 | #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
155 | ((CONNECT) == OPAMP_PGAConnect_IO1) || \
156 | ((CONNECT) == OPAMP_PGAConnect_IO2))
157 | /**
158 | * @}
159 | */
160 |
161 | /** @defgroup OPAMP_SecondaryInvertingInput
162 | * @{
163 | */
164 |
165 | #define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
166 | ((INVINPUT) == OPAMP_InvertingInput_IO2))
167 | /**
168 | * @}
169 | */
170 |
171 | /** @defgroup OPAMP_Input
172 | * @{
173 | */
174 |
175 | #define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
176 | #define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
177 |
178 | #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
179 | ((INPUT) == OPAMP_Input_NonInverting))
180 |
181 | /**
182 | * @}
183 | */
184 |
185 | /** @defgroup OPAMP_Vref
186 | * @{
187 | */
188 |
189 | #define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
190 | #define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
191 | #define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
192 | #define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
193 |
194 | #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
195 | ((VREF) == OPAMP_Vref_10VDDA) || \
196 | ((VREF) == OPAMP_Vref_50VDDA) || \
197 | ((VREF) == OPAMP_Vref_90VDDA))
198 |
199 | /**
200 | * @}
201 | */
202 |
203 | /** @defgroup OPAMP_Trimming
204 | */
205 |
206 | #define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
207 | #define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
208 |
209 | #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
210 | ((TRIMMING) == OPAMP_Trimming_User))
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /** @defgroup OPAMP_TrimValue
217 | * @{
218 | */
219 |
220 | #define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
221 |
222 | /**
223 | * @}
224 | */
225 |
226 | /** @defgroup OPAMP_OutputLevel
227 | * @{
228 | */
229 |
230 | #define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
231 | #define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
232 |
233 | /**
234 | * @}
235 | */
236 |
237 | /* Exported macro ------------------------------------------------------------*/
238 | /* Exported functions ------------------------------------------------------- */
239 |
240 | /* Function used to set the OPAMP configuration to the default reset state ***/
241 | void OPAMP_DeInit(uint32_t OPAMP_Selection);
242 |
243 | /* Initialization and Configuration functions *********************************/
244 | void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
245 | void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
246 | void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
247 | void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
248 | void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
249 | void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
250 | void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
251 | void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
252 | uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
253 |
254 | /* Calibration functions ******************************************************/
255 | void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
256 | void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
257 | void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
258 | void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
259 |
260 | /* OPAMP configuration locking function ***************************************/
261 | void OPAMP_LockConfig(uint32_t OPAMP_Selection);
262 |
263 | #ifdef __cplusplus
264 | }
265 | #endif
266 |
267 | #endif /*__STM32F30x_OPAMP_H */
268 |
269 | /**
270 | * @}
271 | */
272 |
273 | /**
274 | * @}
275 | */
276 |
277 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
278 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_pwr.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_PWR_H
31 | #define __STM32F30x_PWR_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup PWR
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup PWR_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup PWR_PVD_detection_level
56 | * @{
57 | */
58 |
59 | #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
60 | #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
61 | #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
62 | #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
63 | #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
64 | #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
65 | #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
66 | #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
67 |
68 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
69 | ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
70 | ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
71 | ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup PWR_WakeUp_Pins
77 | * @{
78 | */
79 |
80 | #define PWR_WakeUpPin_1 PWR_CSR_EWUP1
81 | #define PWR_WakeUpPin_2 PWR_CSR_EWUP2
82 | #define PWR_WakeUpPin_3 PWR_CSR_EWUP3
83 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
84 | ((PIN) == PWR_WakeUpPin_2) || \
85 | ((PIN) == PWR_WakeUpPin_3))
86 | /**
87 | * @}
88 | */
89 |
90 |
91 | /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
92 | * @{
93 | */
94 |
95 | #define PWR_Regulator_ON ((uint32_t)0x00000000)
96 | #define PWR_Regulator_LowPower PWR_CR_LPSDSR
97 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
98 | ((REGULATOR) == PWR_Regulator_LowPower))
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup PWR_SLEEP_mode_entry
104 | * @{
105 | */
106 |
107 | #define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
108 | #define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
109 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /** @defgroup PWR_STOP_mode_entry
116 | * @{
117 | */
118 |
119 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
120 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
121 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | /** @defgroup PWR_Flag
128 | * @{
129 | */
130 |
131 | #define PWR_FLAG_WU PWR_CSR_WUF
132 | #define PWR_FLAG_SB PWR_CSR_SBF
133 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
134 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
135 |
136 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
137 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
138 |
139 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
140 | /**
141 | * @}
142 | */
143 |
144 | /**
145 | * @}
146 | */
147 |
148 | /* Exported macro ------------------------------------------------------------*/
149 | /* Exported functions ------------------------------------------------------- */
150 |
151 | /* Function used to set the PWR configuration to the default reset state ******/
152 | void PWR_DeInit(void);
153 |
154 | /* Backup Domain Access function **********************************************/
155 | void PWR_BackupAccessCmd(FunctionalState NewState);
156 |
157 | /* PVD configuration functions ************************************************/
158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
159 | void PWR_PVDCmd(FunctionalState NewState);
160 |
161 | /* WakeUp pins configuration functions ****************************************/
162 | void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
163 |
164 | /* Low Power modes configuration functions ************************************/
165 | void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
166 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
167 | void PWR_EnterSTANDBYMode(void);
168 |
169 | /* Flags management functions *************************************************/
170 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
171 | void PWR_ClearFlag(uint32_t PWR_FLAG);
172 |
173 | #ifdef __cplusplus
174 | }
175 | #endif
176 |
177 | #endif /* __STM32F30x_PWR_H */
178 |
179 | /**
180 | * @}
181 | */
182 |
183 | /**
184 | * @}
185 | */
186 |
187 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
188 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_syscfg.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the SYSCFG firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /*!< Define to prevent recursive inclusion -----------------------------------*/
30 | #ifndef __STM32F30x_SYSCFG_H
31 | #define __STM32F30x_SYSCFG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /*!< Includes ----------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup SYSCFG
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup SYSCFG_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup SYSCFG_EXTI_Port_Sources
56 | * @{
57 | */
58 | #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
59 | #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
60 | #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
61 | #define EXTI_PortSourceGPIOD ((uint8_t)0x03)
62 | #define EXTI_PortSourceGPIOE ((uint8_t)0x04)
63 | #define EXTI_PortSourceGPIOF ((uint8_t)0x05)
64 |
65 | #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
66 | ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
67 | ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
68 | ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
69 | ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
70 | ((PORTSOURCE) == EXTI_PortSourceGPIOF))
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup SYSCFG_EXTI_Pin_sources
76 | * @{
77 | */
78 | #define EXTI_PinSource0 ((uint8_t)0x00)
79 | #define EXTI_PinSource1 ((uint8_t)0x01)
80 | #define EXTI_PinSource2 ((uint8_t)0x02)
81 | #define EXTI_PinSource3 ((uint8_t)0x03)
82 | #define EXTI_PinSource4 ((uint8_t)0x04)
83 | #define EXTI_PinSource5 ((uint8_t)0x05)
84 | #define EXTI_PinSource6 ((uint8_t)0x06)
85 | #define EXTI_PinSource7 ((uint8_t)0x07)
86 | #define EXTI_PinSource8 ((uint8_t)0x08)
87 | #define EXTI_PinSource9 ((uint8_t)0x09)
88 | #define EXTI_PinSource10 ((uint8_t)0x0A)
89 | #define EXTI_PinSource11 ((uint8_t)0x0B)
90 | #define EXTI_PinSource12 ((uint8_t)0x0C)
91 | #define EXTI_PinSource13 ((uint8_t)0x0D)
92 | #define EXTI_PinSource14 ((uint8_t)0x0E)
93 | #define EXTI_PinSource15 ((uint8_t)0x0F)
94 |
95 | #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
96 | ((PINSOURCE) == EXTI_PinSource1) || \
97 | ((PINSOURCE) == EXTI_PinSource2) || \
98 | ((PINSOURCE) == EXTI_PinSource3) || \
99 | ((PINSOURCE) == EXTI_PinSource4) || \
100 | ((PINSOURCE) == EXTI_PinSource5) || \
101 | ((PINSOURCE) == EXTI_PinSource6) || \
102 | ((PINSOURCE) == EXTI_PinSource7) || \
103 | ((PINSOURCE) == EXTI_PinSource8) || \
104 | ((PINSOURCE) == EXTI_PinSource9) || \
105 | ((PINSOURCE) == EXTI_PinSource10) || \
106 | ((PINSOURCE) == EXTI_PinSource11) || \
107 | ((PINSOURCE) == EXTI_PinSource12) || \
108 | ((PINSOURCE) == EXTI_PinSource13) || \
109 | ((PINSOURCE) == EXTI_PinSource14) || \
110 | ((PINSOURCE) == EXTI_PinSource15))
111 | /**
112 | * @}
113 | */
114 |
115 | /** @defgroup SYSCFG_Memory_Remap_Config
116 | * @{
117 | */
118 | #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
119 | #define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
120 | #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
121 |
122 |
123 | #define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
124 | ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
125 | ((REMAP) == SYSCFG_MemoryRemap_SRAM))
126 |
127 | /**
128 | * @}
129 | */
130 |
131 | /** @defgroup SYSCFG_DMA_Remap_Config
132 | * @{
133 | */
134 | #define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
135 | #define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
136 | #define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1_DMA_RMP /*!< Remap TIM6/DAC1 DMA requests from DMA2 channel3 to DMA1 channel3 */
137 | #define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC2_DMA_RMP /*!< Remap TIM7/DAC2 DMA requests from DMA2 channel4 to DMA1 channel4 */
138 | #define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4 */
139 |
140 | #define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
141 | ((REMAP) == SYSCFG_DMARemap_TIM16) || \
142 | ((REMAP) == SYSCFG_DMARemap_TIM6DAC1) || \
143 | ((REMAP) == SYSCFG_DMARemap_TIM7DAC2) || \
144 | ((REMAP) == SYSCFG_DMARemap_ADC2ADC4))
145 |
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup SYSCFG_Trigger_Remap_Config
151 | * @{
152 | */
153 | #define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC_TRIG_RMP /*!< Remap DAC trigger to TIM3 */
154 | #define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
155 |
156 | #define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
157 | ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
158 |
159 | /**
160 | * @}
161 | */
162 |
163 | /** @defgroup SYSCFG_EncoderRemap_Config
164 | * @{
165 | */
166 | #define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
167 | #define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
168 | #define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
169 | #define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
170 |
171 | #define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
172 | ((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
173 | ((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
174 | ((REMAP) == SYSCFG_EncoderRemap_TIM4))
175 |
176 | /**
177 | * @}
178 | */
179 |
180 | /** @defgroup SYSCFG_I2C_FastModePlus_Config
181 | * @{
182 | */
183 | #define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
184 | #define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
185 | #define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
186 | #define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
187 | #define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
188 | #define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
189 |
190 | #define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
191 | ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
192 | ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
193 | ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
194 | ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
195 | ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
196 |
197 | /**
198 | * @}
199 | */
200 |
201 | /** @defgroup SYSCFG_FPU_Interrupt_Config
202 | * @{
203 | */
204 | #define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
205 | #define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
206 | #define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
207 | #define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
208 | #define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
209 | #define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
210 |
211 | #define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
212 |
213 | /**
214 | * @}
215 | */
216 |
217 | /** @defgroup SYSCFG_Lock_Config
218 | * @{
219 | */
220 | #define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
221 | #define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
222 | #define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM0 with Break Input of TIM1/8/15/16/17 */
223 |
224 | #define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
225 | ((CONFIG) == SYSCFG_Break_SRAMParity) || \
226 | ((CONFIG) == SYSCFG_Break_Lockup))
227 |
228 | /**
229 | * @}
230 | */
231 |
232 | /** @defgroup SYSCFG_SRAMWRP_Config
233 | * @{
234 | */
235 | #define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
236 | #define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
237 | #define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
238 | #define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
239 | #define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
240 | #define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
241 | #define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
242 | #define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
243 |
244 | #define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
245 |
246 | /**
247 | * @}
248 | */
249 |
250 | /** @defgroup SYSCFG_flags_definition
251 | * @{
252 | */
253 |
254 | #define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
255 |
256 | #define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
257 |
258 | /**
259 | * @}
260 | */
261 |
262 | /**
263 | * @}
264 | */
265 |
266 | /* Exported macro ------------------------------------------------------------*/
267 | /* Exported functions ------------------------------------------------------- */
268 |
269 | /* Function used to set the SYSCFG configuration to the default reset state **/
270 | void SYSCFG_DeInit(void);
271 |
272 | /* SYSCFG configuration functions *********************************************/
273 | void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
274 | void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
275 | void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
276 | void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
277 | void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
278 | void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
279 | void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
280 | void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
281 | void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
282 | void SYSCFG_BypassParityCheckDisable(void);
283 | void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
284 | FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
285 | void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
286 |
287 | #ifdef __cplusplus
288 | }
289 | #endif
290 |
291 | #endif /*__STM32F30x_SYSCFG_H */
292 |
293 | /**
294 | * @}
295 | */
296 |
297 | /**
298 | * @}
299 | */
300 |
301 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
302 |
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/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_wwdg.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file contains all the functions prototypes for the WWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2012 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30X_WWDG_H
31 | #define __STM32F30X_WWDG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup WWDG
45 | * @{
46 | */
47 | /* Exported types ------------------------------------------------------------*/
48 | /* Exported constants --------------------------------------------------------*/
49 |
50 | /** @defgroup WWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup WWDG_Prescaler
55 | * @{
56 | */
57 |
58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
63 | ((PRESCALER) == WWDG_Prescaler_2) || \
64 | ((PRESCALER) == WWDG_Prescaler_4) || \
65 | ((PRESCALER) == WWDG_Prescaler_8))
66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /* Exported macro ------------------------------------------------------------*/
78 | /* Exported functions ------------------------------------------------------- */
79 | /* Function used to set the WWDG configuration to the default reset state ****/
80 | void WWDG_DeInit(void);
81 |
82 | /* Prescaler, Refresh window and Counter configuration functions **************/
83 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
84 | void WWDG_SetWindowValue(uint8_t WindowValue);
85 | void WWDG_EnableIT(void);
86 | void WWDG_SetCounter(uint8_t Counter);
87 |
88 | /* WWDG activation functions **************************************************/
89 | void WWDG_Enable(uint8_t Counter);
90 |
91 | /* Interrupts and flags management functions **********************************/
92 | FlagStatus WWDG_GetFlagStatus(void);
93 | void WWDG_ClearFlag(void);
94 |
95 | #ifdef __cplusplus
96 | }
97 | #endif
98 |
99 | #endif /* __STM32F30X_WWDG_H */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
110 |
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/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_crc.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of CRC computation unit peripheral:
9 | * + Configuration of the CRC computation unit
10 | * + CRC computation of one/many 32-bit data
11 | * + CRC Independent register (IDR) access
12 | *
13 | @verbatim
14 |
15 | ===============================================================================
16 | ##### How to use this driver #####
17 | ===============================================================================
18 | [..]
19 | (#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
20 | function.
21 | (#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
22 | (#) Set the polynomial coefficients using CRC_SetPolynomial();
23 | (#) If required, select the reverse operation on input data
24 | using CRC_ReverseInputDataSelect();
25 | (#) If required, enable the reverse operation on output data
26 | using CRC_ReverseOutputDataCmd(Enable);
27 | (#) If required, set the initialization remainder value using
28 | CRC_SetInitRegister();
29 | (#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
30 | or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
31 | data buffer.
32 |
33 | @endverbatim
34 |
35 | ******************************************************************************
36 | * @attention
37 | *
38 | * © COPYRIGHT 2012 STMicroelectronics
39 | *
40 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
41 | * You may not use this file except in compliance with the License.
42 | * You may obtain a copy of the License at:
43 | *
44 | * http://www.st.com/software_license_agreement_liberty_v2
45 | *
46 | * Unless required by applicable law or agreed to in writing, software
47 | * distributed under the License is distributed on an "AS IS" BASIS,
48 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
49 | * See the License for the specific language governing permissions and
50 | * limitations under the License.
51 | *
52 | ******************************************************************************
53 | */
54 |
55 | /* Includes ------------------------------------------------------------------*/
56 | #include "stm32f30x_crc.h"
57 |
58 | /** @addtogroup STM32F30x_StdPeriph_Driver
59 | * @{
60 | */
61 |
62 | /** @defgroup CRC
63 | * @brief CRC driver modules
64 | * @{
65 | */
66 |
67 | /* Private typedef -----------------------------------------------------------*/
68 | /* Private define ------------------------------------------------------------*/
69 | /* Private macro -------------------------------------------------------------*/
70 | /* Private variables ---------------------------------------------------------*/
71 | /* Private function prototypes -----------------------------------------------*/
72 | /* Private functions ---------------------------------------------------------*/
73 |
74 | /** @defgroup CRC_Private_Functions
75 | * @{
76 | */
77 |
78 | /** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
79 | * @brief Configuration of the CRC computation unit functions
80 | *
81 | @verbatim
82 | ===============================================================================
83 | ##### CRC configuration functions #####
84 | ===============================================================================
85 |
86 | @endverbatim
87 | * @{
88 | */
89 |
90 | /**
91 | * @brief Deinitializes CRC peripheral registers to their default reset values.
92 | * @param None
93 | * @retval None
94 | */
95 | void CRC_DeInit(void)
96 | {
97 | /* Set DR register to reset value */
98 | CRC->DR = 0xFFFFFFFF;
99 | /* Set the POL register to the reset value: 0x04C11DB7 */
100 | CRC->POL = 0x04C11DB7;
101 | /* Reset IDR register */
102 | CRC->IDR = 0x00;
103 | /* Set INIT register to reset value */
104 | CRC->INIT = 0xFFFFFFFF;
105 | /* Reset the CRC calculation unit */
106 | CRC->CR = CRC_CR_RESET;
107 | }
108 |
109 | /**
110 | * @brief Resets the CRC calculation unit and sets INIT register content in DR register.
111 | * @param None
112 | * @retval None
113 | */
114 | void CRC_ResetDR(void)
115 | {
116 | /* Reset CRC generator */
117 | CRC->CR |= CRC_CR_RESET;
118 | }
119 |
120 | /**
121 | * @brief Selects the polynomial size.
122 | * @param CRC_PolSize: Specifies the polynomial size.
123 | * This parameter can be:
124 | * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
125 | * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
126 | * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
127 | * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
128 | * @retval None
129 | */
130 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
131 | {
132 | uint32_t tmpcr = 0;
133 |
134 | /* Check the parameter */
135 | assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
136 |
137 | /* Get CR register value */
138 | tmpcr = CRC->CR;
139 |
140 | /* Reset POL_SIZE bits */
141 | tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
142 | /* Set the polynomial size */
143 | tmpcr |= (uint32_t)CRC_PolSize;
144 |
145 | /* Write to CR register */
146 | CRC->CR = (uint32_t)tmpcr;
147 | }
148 |
149 | /**
150 | * @brief Selects the reverse operation to be performed on input data.
151 | * @param CRC_ReverseInputData: Specifies the reverse operation on input data.
152 | * This parameter can be:
153 | * @arg CRC_ReverseInputData_No: No reverse operation is performed
154 | * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
155 | * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
156 | * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
157 | * @retval None
158 | */
159 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
160 | {
161 | uint32_t tmpcr = 0;
162 |
163 | /* Check the parameter */
164 | assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
165 |
166 | /* Get CR register value */
167 | tmpcr = CRC->CR;
168 |
169 | /* Reset REV_IN bits */
170 | tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
171 | /* Set the reverse operation */
172 | tmpcr |= (uint32_t)CRC_ReverseInputData;
173 |
174 | /* Write to CR register */
175 | CRC->CR = (uint32_t)tmpcr;
176 | }
177 |
178 | /**
179 | * @brief Enables or disable the reverse operation on output data.
180 | * The reverse operation on output data is performed on 32-bit.
181 | * @param NewState: new state of the reverse operation on output data.
182 | * This parameter can be: ENABLE or DISABLE.
183 | * @retval None
184 | */
185 | void CRC_ReverseOutputDataCmd(FunctionalState NewState)
186 | {
187 | /* Check the parameters */
188 | assert_param(IS_FUNCTIONAL_STATE(NewState));
189 |
190 | if (NewState != DISABLE)
191 | {
192 | /* Enable reverse operation on output data */
193 | CRC->CR |= CRC_CR_REV_OUT;
194 | }
195 | else
196 | {
197 | /* Disable reverse operation on output data */
198 | CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
199 | }
200 | }
201 |
202 | /**
203 | * @brief Initializes the INIT register.
204 | * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
205 | * @param CRC_InitValue: Programmable initial CRC value
206 | * @retval None
207 | */
208 | void CRC_SetInitRegister(uint32_t CRC_InitValue)
209 | {
210 | CRC->INIT = CRC_InitValue;
211 | }
212 |
213 | /**
214 | * @brief Initializes the polynomail coefficients.
215 | * @param CRC_Pol: Polynomial to be used for CRC calculation.
216 | * @retval None
217 | */
218 | void CRC_SetPolynomial(uint32_t CRC_Pol)
219 | {
220 | CRC->POL = CRC_Pol;
221 | }
222 |
223 | /**
224 | * @}
225 | */
226 |
227 | /** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
228 | * @brief CRC computation of one/many 32-bit data functions
229 | *
230 | @verbatim
231 | ===============================================================================
232 | ##### CRC computation functions #####
233 | ===============================================================================
234 |
235 | @endverbatim
236 | * @{
237 | */
238 |
239 | /**
240 | * @brief Computes the 32-bit CRC of a given data word(32-bit).
241 | * @param CRC_Data: data word(32-bit) to compute its CRC
242 | * @retval 32-bit CRC
243 | */
244 | uint32_t CRC_CalcCRC(uint32_t CRC_Data)
245 | {
246 | CRC->DR = CRC_Data;
247 |
248 | return (CRC->DR);
249 | }
250 |
251 | /**
252 | * @brief Computes the 16-bit CRC of a given 16-bit data.
253 | * @param CRC_Data: data half-word(16-bit) to compute its CRC
254 | * @retval 16-bit CRC
255 | */
256 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
257 | {
258 | *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
259 |
260 | return (CRC->DR);
261 | }
262 |
263 | /**
264 | * @brief Computes the 8-bit CRC of a given 8-bit data.
265 | * @param CRC_Data: 8-bit data to compute its CRC
266 | * @retval 8-bit CRC
267 | */
268 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
269 | {
270 | *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
271 |
272 | return (CRC->DR);
273 | }
274 |
275 | /**
276 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
277 | * @param pBuffer: pointer to the buffer containing the data to be computed
278 | * @param BufferLength: length of the buffer to be computed
279 | * @retval 32-bit CRC
280 | */
281 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
282 | {
283 | uint32_t index = 0;
284 |
285 | for(index = 0; index < BufferLength; index++)
286 | {
287 | CRC->DR = pBuffer[index];
288 | }
289 | return (CRC->DR);
290 | }
291 |
292 | /**
293 | * @brief Returns the current CRC value.
294 | * @param None
295 | * @retval 32-bit CRC
296 | */
297 | uint32_t CRC_GetCRC(void)
298 | {
299 | return (CRC->DR);
300 | }
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | /** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
307 | * @brief CRC Independent Register (IDR) access (write/read) functions
308 | *
309 | @verbatim
310 | ===============================================================================
311 | ##### CRC Independent Register (IDR) access functions #####
312 | ===============================================================================
313 |
314 | @endverbatim
315 | * @{
316 | */
317 |
318 | /**
319 | * @brief Stores an 8-bit data in the Independent Data(ID) register.
320 | * @param CRC_IDValue: 8-bit value to be stored in the ID register
321 | * @retval None
322 | */
323 | void CRC_SetIDRegister(uint8_t CRC_IDValue)
324 | {
325 | CRC->IDR = CRC_IDValue;
326 | }
327 |
328 | /**
329 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register
330 | * @param None
331 | * @retval 8-bit value of the ID register
332 | */
333 | uint8_t CRC_GetIDRegister(void)
334 | {
335 | return (CRC->IDR);
336 | }
337 |
338 | /**
339 | * @}
340 | */
341 |
342 | /**
343 | * @}
344 | */
345 |
346 | /**
347 | * @}
348 | */
349 |
350 | /**
351 | * @}
352 | */
353 |
354 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
355 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_dbgmcu.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Debug MCU (DBGMCU) peripheral:
9 | * + Device and Revision ID management
10 | * + Peripherals Configuration
11 | ******************************************************************************
12 | * @attention
13 | *
14 | * © COPYRIGHT 2012 STMicroelectronics
15 | *
16 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
17 | * You may not use this file except in compliance with the License.
18 | * You may obtain a copy of the License at:
19 | *
20 | * http://www.st.com/software_license_agreement_liberty_v2
21 | *
22 | * Unless required by applicable law or agreed to in writing, software
23 | * distributed under the License is distributed on an "AS IS" BASIS,
24 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 | * See the License for the specific language governing permissions and
26 | * limitations under the License.
27 | *
28 | ******************************************************************************
29 | */
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f30x_dbgmcu.h"
33 |
34 | /** @addtogroup STM32F30x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @defgroup DBGMCU
39 | * @brief DBGMCU driver modules
40 | * @{
41 | */
42 |
43 | /* Private typedef -----------------------------------------------------------*/
44 | /* Private define ------------------------------------------------------------*/
45 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
46 |
47 | /* Private macro -------------------------------------------------------------*/
48 | /* Private variables ---------------------------------------------------------*/
49 | /* Private function prototypes -----------------------------------------------*/
50 | /* Private functions ---------------------------------------------------------*/
51 |
52 | /** @defgroup DBGMCU_Private_Functions
53 | * @{
54 | */
55 |
56 | /** @defgroup DBGMCU_Group1 Device and Revision ID management functions
57 | * @brief Device and Revision ID management functions
58 | *
59 | @verbatim
60 | ==============================================================================
61 | ##### Device and Revision ID management functions #####
62 | ==============================================================================
63 |
64 | @endverbatim
65 | * @{
66 | */
67 |
68 | /**
69 | * @brief Returns the device revision identifier.
70 | * @param None
71 | * @retval Device revision identifier
72 | */
73 | uint32_t DBGMCU_GetREVID(void)
74 | {
75 | return(DBGMCU->IDCODE >> 16);
76 | }
77 |
78 | /**
79 | * @brief Returns the device identifier.
80 | * @param None
81 | * @retval Device identifier
82 | */
83 | uint32_t DBGMCU_GetDEVID(void)
84 | {
85 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
86 | }
87 |
88 | /**
89 | * @}
90 | */
91 |
92 | /** @defgroup DBGMCU_Group2 Peripherals Configuration functions
93 | * @brief Peripherals Configuration
94 | *
95 | @verbatim
96 | ==============================================================================
97 | ##### Peripherals Configuration functions #####
98 | ==============================================================================
99 |
100 | @endverbatim
101 | * @{
102 | */
103 |
104 | /**
105 | * @brief Configures low power mode behavior when the MCU is in Debug mode.
106 | * @param DBGMCU_Periph: specifies the low power mode.
107 | * This parameter can be any combination of the following values:
108 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
109 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
110 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
111 | * @param NewState: new state of the specified low power mode in Debug mode.
112 | * This parameter can be: ENABLE or DISABLE.
113 | * @retval None
114 | */
115 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
116 | {
117 | /* Check the parameters */
118 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
119 | assert_param(IS_FUNCTIONAL_STATE(NewState));
120 | if (NewState != DISABLE)
121 | {
122 | DBGMCU->CR |= DBGMCU_Periph;
123 | }
124 | else
125 | {
126 | DBGMCU->CR &= ~DBGMCU_Periph;
127 | }
128 | }
129 |
130 | /**
131 | * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
132 | * @param DBGMCU_Periph: specifies the APB1 peripheral.
133 | * This parameter can be any combination of the following values:
134 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
135 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
136 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
137 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
138 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
139 | * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
140 | * Core is halted.
141 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
142 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
143 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
144 | * Core is halted.
145 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
146 | * Core is halted.
147 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
148 | * @param NewState: new state of the specified APB1 peripheral in Debug mode.
149 | * This parameter can be: ENABLE or DISABLE.
150 | * @retval None
151 | */
152 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
153 | {
154 | /* Check the parameters */
155 | assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
156 | assert_param(IS_FUNCTIONAL_STATE(NewState));
157 |
158 | if (NewState != DISABLE)
159 | {
160 | DBGMCU->APB1FZ |= DBGMCU_Periph;
161 | }
162 | else
163 | {
164 | DBGMCU->APB1FZ &= ~DBGMCU_Periph;
165 | }
166 | }
167 |
168 | /**
169 | * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
170 | * @param DBGMCU_Periph: specifies the APB2 peripheral.
171 | * This parameter can be any combination of the following values:
172 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
173 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
174 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
175 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
176 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
177 | * @param NewState: new state of the specified APB2 peripheral in Debug mode.
178 | * This parameter can be: ENABLE or DISABLE.
179 | * @retval None
180 | */
181 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
182 | {
183 | /* Check the parameters */
184 | assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
185 | assert_param(IS_FUNCTIONAL_STATE(NewState));
186 |
187 | if (NewState != DISABLE)
188 | {
189 | DBGMCU->APB2FZ |= DBGMCU_Periph;
190 | }
191 | else
192 | {
193 | DBGMCU->APB2FZ &= ~DBGMCU_Periph;
194 | }
195 | }
196 |
197 | /**
198 | * @}
199 | */
200 |
201 | /**
202 | * @}
203 | */
204 |
205 | /**
206 | * @}
207 | */
208 |
209 | /**
210 | * @}
211 | */
212 |
213 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
214 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_exti.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the EXTI peripheral:
9 | * + Initialization and Configuration
10 | * + Interrupts and flags management
11 | *
12 | @verbatim
13 | ===============================================================================
14 | ##### EXTI features #####
15 | ===============================================================================
16 | [..] External interrupt/event lines are mapped as following:
17 | (#) All available GPIO pins are connected to the 16 external
18 | interrupt/event lines from EXTI0 to EXTI15.
19 | (#) EXTI line 16 is connected to the PVD output
20 | (#) EXTI line 17 is connected to the RTC Alarm event
21 | (#) EXTI line 18 is connected to USB Device wakeup event
22 | (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
23 | (#) EXTI line 20 is connected to the RTC wakeup event
24 | (#) EXTI line 21 is connected to the Comparator 1 wakeup event
25 | (#) EXTI line 22 is connected to the Comparator 2 wakeup event
26 | (#) EXTI line 23 is connected to the I2C1 wakeup event
27 | (#) EXTI line 24 is connected to the I2C2 wakeup event
28 | (#) EXTI line 25 is connected to the USART1 wakeup event
29 | (#) EXTI line 26 is connected to the USART2 wakeup event
30 | (#) EXTI line 27 is reserved
31 | (#) EXTI line 28 is connected to the USART3 wakeup event
32 | (#) EXTI line 29 is connected to the Comparator 3 event
33 | (#) EXTI line 30 is connected to the Comparator 4 event
34 | (#) EXTI line 31 is connected to the Comparator 5 event
35 | (#) EXTI line 32 is connected to the Comparator 6 event
36 | (#) EXTI line 33 is connected to the Comparator 7 event
37 | (#) EXTI line 34 is connected for thr UART4 wakeup event
38 | (#) EXTI line 35 is connected for the UART5 wakeup event
39 |
40 | ##### How to use this driver #####
41 | ===============================================================================
42 | [..] In order to use an I/O pin as an external interrupt source,
43 | follow steps below:
44 | (#) Configure the I/O in input mode using GPIO_Init().
45 | (#) Select the input source pin for the EXTI line using
46 | SYSCFG_EXTILineConfig().
47 | (#) Select the mode(interrupt, event) and configure the trigger
48 | selection (Rising, falling or both) using EXTI_Init(). For the
49 | internal interrupt, the trigger selection is not needed
50 | (the active edge is always the rising one).
51 | (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
52 | (#) Optionally, you can generate a software interrupt using the function
53 | EXTI_GenerateSWInterrupt().
54 | [..]
55 | (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
56 | registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
57 |
58 | @endverbatim
59 |
60 | ******************************************************************************
61 | * @attention
62 | *
63 | * © COPYRIGHT 2012 STMicroelectronics
64 | *
65 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
66 | * You may not use this file except in compliance with the License.
67 | * You may obtain a copy of the License at:
68 | *
69 | * http://www.st.com/software_license_agreement_liberty_v2
70 | *
71 | * Unless required by applicable law or agreed to in writing, software
72 | * distributed under the License is distributed on an "AS IS" BASIS,
73 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
74 | * See the License for the specific language governing permissions and
75 | * limitations under the License.
76 | *
77 | ******************************************************************************
78 | */
79 |
80 | /* Includes ------------------------------------------------------------------*/
81 | #include "stm32f30x_exti.h"
82 |
83 | /** @addtogroup STM32F30x_StdPeriph_Driver
84 | * @{
85 | */
86 |
87 | /** @defgroup EXTI
88 | * @brief EXTI driver modules
89 | * @{
90 | */
91 |
92 |
93 | /* Private typedef -----------------------------------------------------------*/
94 | /* Private define ------------------------------------------------------------*/
95 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
96 |
97 | /* Private macro -------------------------------------------------------------*/
98 | /* Private variables ---------------------------------------------------------*/
99 | /* Private function prototypes -----------------------------------------------*/
100 | /* Private functions ---------------------------------------------------------*/
101 |
102 | /** @defgroup EXTI_Private_Functions
103 | * @{
104 | */
105 |
106 | /** @defgroup EXTI_Group1 Initialization and Configuration functions
107 | * @brief Initialization and Configuration functions
108 | *
109 | @verbatim
110 | ===============================================================================
111 | ##### Initialization and Configuration functions #####
112 | ===============================================================================
113 |
114 | @endverbatim
115 | * @{
116 | */
117 |
118 | /**
119 | * @brief Deinitializes the EXTI peripheral registers to their default reset
120 | * values.
121 | * @param None
122 | * @retval None
123 | */
124 | void EXTI_DeInit(void)
125 | {
126 | EXTI->IMR = 0x1F800000;
127 | EXTI->EMR = 0x00000000;
128 | EXTI->RTSR = 0x00000000;
129 | EXTI->FTSR = 0x00000000;
130 | EXTI->SWIER = 0x00000000;
131 | EXTI->PR = 0xE07FFFFF;
132 | EXTI->IMR2 = 0x0000000C;
133 | EXTI->EMR2 = 0x00000000;
134 | EXTI->RTSR2 = 0x00000000;
135 | EXTI->FTSR2 = 0x00000000;
136 | EXTI->SWIER2 = 0x00000000;
137 | EXTI->PR2 = 0x00000003;
138 | }
139 |
140 | /**
141 | * @brief Initializes the EXTI peripheral according to the specified
142 | * parameters in the EXTI_InitStruct.
143 | * EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
144 | * EXTI_Mode specifies which EXTI line is used as interrupt or an event.
145 | * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
146 | * pending bit will be set.
147 | * EXTI_LineCmd controls (Enable/Disable) the EXTI line.
148 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
149 | * contains the configuration information for the EXTI peripheral.
150 | * @retval None
151 | */
152 |
153 |
154 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
155 | {
156 | uint32_t tmp = 0;
157 |
158 | /* Check the parameters */
159 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
160 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
161 | assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
162 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
163 |
164 | tmp = (uint32_t)EXTI_BASE;
165 |
166 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
167 | {
168 | /* Clear EXTI line configuration */
169 | *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
170 | *(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
171 |
172 | tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
173 |
174 | *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
175 |
176 | tmp = (uint32_t)EXTI_BASE;
177 |
178 | /* Clear Rising Falling edge configuration */
179 | *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
180 | *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
181 |
182 | /* Select the trigger for the selected interrupts */
183 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
184 | {
185 | /* Rising Falling edge */
186 | *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
187 | *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
188 | }
189 | else
190 | {
191 | tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
192 |
193 | *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
194 | }
195 | }
196 |
197 | else
198 | {
199 | tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
200 |
201 | /* Disable the selected external lines */
202 | *(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
203 | }
204 |
205 | }
206 |
207 | /**
208 | * @brief Fills each EXTI_InitStruct member with its reset value.
209 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
210 | * be initialized.
211 | * @retval None
212 | */
213 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
214 | {
215 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
216 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
217 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
218 | EXTI_InitStruct->EXTI_LineCmd = DISABLE;
219 | }
220 |
221 | /**
222 | * @brief Generates a Software interrupt on selected EXTI line.
223 | * @param EXTI_Line: specifies the EXTI line on which the software interrupt
224 | * will be generated.
225 | * This parameter can be any combination of EXTI_Linex where x can be (0..20).
226 | * @retval None
227 | */
228 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
229 | {
230 | /* Check the parameters */
231 | assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
232 |
233 | *(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
234 |
235 | }
236 |
237 | /**
238 | * @}
239 | */
240 |
241 | /** @defgroup EXTI_Group2 Interrupts and flags management functions
242 | * @brief EXTI Interrupts and flags management functions
243 | *
244 | @verbatim
245 | ===============================================================================
246 | ##### Interrupts and flags management functions #####
247 | ===============================================================================
248 | [..]
249 | This section provides functions allowing to configure the EXTI Interrupts
250 | sources and check or clear the flags or pending bits status.
251 |
252 | @endverbatim
253 | * @{
254 | */
255 |
256 | /**
257 | * @brief Checks whether the specified EXTI line flag is set or not.
258 | * @param EXTI_Line: specifies the EXTI line flag to check.
259 | * This parameter can be any combination of EXTI_Linex where x can be (0..20).
260 | * @retval The new state of EXTI_Line (SET or RESET).
261 | */
262 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
263 | {
264 | FlagStatus bitstatus = RESET;
265 |
266 | /* Check the parameters */
267 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
268 |
269 | if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
270 | {
271 | bitstatus = SET;
272 | }
273 | else
274 | {
275 | bitstatus = RESET;
276 | }
277 | return bitstatus;
278 | }
279 |
280 | /**
281 | * @brief Clears the EXTI's line pending flags.
282 | * @param EXTI_Line: specifies the EXTI lines flags to clear.
283 | * This parameter can be any combination of EXTI_Linex where x can be (0..20).
284 | * @retval None
285 | */
286 | void EXTI_ClearFlag(uint32_t EXTI_Line)
287 | {
288 | /* Check the parameters */
289 | assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
290 |
291 | *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
292 | }
293 |
294 | /**
295 | * @brief Checks whether the specified EXTI line is asserted or not.
296 | * @param EXTI_Line: specifies the EXTI line to check.
297 | * This parameter can be any combination of EXTI_Linex where x can be (0..20).
298 | * @retval The new state of EXTI_Line (SET or RESET).
299 | */
300 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
301 | {
302 | ITStatus bitstatus = RESET;
303 | uint32_t enablestatus = 0;
304 |
305 | /* Check the parameters */
306 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
307 |
308 | enablestatus = *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_Line) >> 5 ) * 0x20) & (uint32_t)(1 << (EXTI_Line & 0x1F));
309 |
310 | if ( (((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + (((EXTI_Line) >> 5 ) * 0x20) )) & (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
311 | {
312 | bitstatus = SET;
313 | }
314 | else
315 | {
316 | bitstatus = RESET;
317 | }
318 | return bitstatus;
319 |
320 | }
321 |
322 | /**
323 | * @brief Clears the EXTI's line pending bits.
324 | * @param EXTI_Line: specifies the EXTI lines to clear.
325 | * This parameter can be any combination of EXTI_Linex where x can be (0..20).
326 | * @retval None
327 | */
328 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
329 | {
330 | /* Check the parameters */
331 | assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
332 |
333 | *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
334 | }
335 |
336 | /**
337 | * @}
338 | */
339 |
340 | /**
341 | * @}
342 | */
343 |
344 | /**
345 | * @}
346 | */
347 |
348 | /**
349 | * @}
350 | */
351 |
352 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
353 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_iwdg.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Independent watchdog (IWDG) peripheral:
9 | * + Prescaler and Counter configuration
10 | * + IWDG activation
11 | * + Flag management
12 | *
13 | @verbatim
14 |
15 | ===============================================================================
16 | ##### IWDG features #####
17 | ===============================================================================
18 | [..] The IWDG can be started by either software or hardware (configurable
19 | through option byte).
20 | [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
21 | thus stays active even if the main clock fails.
22 | Once the IWDG is started, the LSI is forced ON and cannot be disabled
23 | (LSI cannot be disabled too), and the counter starts counting down from
24 | the reset value of 0xFFF. When it reaches the end of count value (0x000)
25 | a system reset is generated.
26 | The IWDG counter should be reloaded at regular intervals to prevent
27 | an MCU reset.
28 | [..] The IWDG is implemented in the VDD voltage domain that is still functional
29 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
30 | [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
31 | reset occurs.
32 | [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
33 | The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
34 | devices provide the capability to measure the LSI frequency (LSI clock
35 | connected internally to TIM16 CH1 input capture). The measured value
36 | can be used to have an IWDG timeout with an acceptable accuracy.
37 | For more information, please refer to the STM32F30x Reference manual.
38 |
39 | ##### How to use this driver #####
40 | ===============================================================================
41 | [..] This driver allows to use IWDG peripheral with either window option enabled
42 | or disabled. To do so follow one of the two procedures below.
43 | (#) Window option is enabled:
44 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
45 | in software mode (no need to enable the LSI, it will be enabled
46 | by hardware).
47 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using
48 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
49 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
50 | (++) Configure the IWDG counter value using IWDG_SetReload() function.
51 | This value will be loaded in the IWDG counter each time the counter
52 | is reloaded, then the IWDG will start counting down from this value.
53 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
54 | (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
55 |
56 | (#) Window option is disabled:
57 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using
58 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
59 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
60 | (++) Configure the IWDG counter value using IWDG_SetReload() function.
61 | This value will be loaded in the IWDG counter each time the counter
62 | is reloaded, then the IWDG will start counting down from this value.
63 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
64 | (++) reload the IWDG counter at regular intervals during normal operation
65 | to prevent an MCU reset, using IWDG_ReloadCounter() function.
66 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
67 | in software mode (no need to enable the LSI, it will be enabled
68 | by hardware).
69 |
70 | @endverbatim
71 |
72 | ******************************************************************************
73 | * @attention
74 | *
75 | * © COPYRIGHT 2012 STMicroelectronics
76 | *
77 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
78 | * You may not use this file except in compliance with the License.
79 | * You may obtain a copy of the License at:
80 | *
81 | * http://www.st.com/software_license_agreement_liberty_v2
82 | *
83 | * Unless required by applicable law or agreed to in writing, software
84 | * distributed under the License is distributed on an "AS IS" BASIS,
85 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
86 | * See the License for the specific language governing permissions and
87 | * limitations under the License.
88 | *
89 | ******************************************************************************
90 | */
91 |
92 | /* Includes ------------------------------------------------------------------*/
93 | #include "stm32f30x_iwdg.h"
94 |
95 | /** @addtogroup STM32F30x_StdPeriph_Driver
96 | * @{
97 | */
98 |
99 | /** @defgroup IWDG
100 | * @brief IWDG driver modules
101 | * @{
102 | */
103 |
104 | /* Private typedef -----------------------------------------------------------*/
105 | /* Private define ------------------------------------------------------------*/
106 | /* ---------------------- IWDG registers bit mask ----------------------------*/
107 | /* KR register bit mask */
108 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA)
109 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC)
110 |
111 | /* Private macro -------------------------------------------------------------*/
112 | /* Private variables ---------------------------------------------------------*/
113 | /* Private function prototypes -----------------------------------------------*/
114 | /* Private functions ---------------------------------------------------------*/
115 |
116 | /** @defgroup IWDG_Private_Functions
117 | * @{
118 | */
119 |
120 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
121 | * @brief Prescaler and Counter configuration functions
122 | *
123 | @verbatim
124 | ===============================================================================
125 | ##### Prescaler and Counter configuration functions #####
126 | ===============================================================================
127 |
128 | @endverbatim
129 | * @{
130 | */
131 |
132 | /**
133 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
134 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
135 | * This parameter can be one of the following values:
136 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
137 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
138 | * @retval None
139 | */
140 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
141 | {
142 | /* Check the parameters */
143 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
144 | IWDG->KR = IWDG_WriteAccess;
145 | }
146 |
147 | /**
148 | * @brief Sets IWDG Prescaler value.
149 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
150 | * This parameter can be one of the following values:
151 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
152 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
153 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
154 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
155 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
156 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
157 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
158 | * @retval None
159 | */
160 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
161 | {
162 | /* Check the parameters */
163 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
164 | IWDG->PR = IWDG_Prescaler;
165 | }
166 |
167 | /**
168 | * @brief Sets IWDG Reload value.
169 | * @param Reload: specifies the IWDG Reload value.
170 | * This parameter must be a number between 0 and 0x0FFF.
171 | * @retval None
172 | */
173 | void IWDG_SetReload(uint16_t Reload)
174 | {
175 | /* Check the parameters */
176 | assert_param(IS_IWDG_RELOAD(Reload));
177 | IWDG->RLR = Reload;
178 | }
179 |
180 | /**
181 | * @brief Reloads IWDG counter with value defined in the reload register
182 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
183 | * @param None
184 | * @retval None
185 | */
186 | void IWDG_ReloadCounter(void)
187 | {
188 | IWDG->KR = KR_KEY_RELOAD;
189 | }
190 |
191 |
192 | /**
193 | * @brief Sets the IWDG window value.
194 | * @param WindowValue: specifies the window value to be compared to the downcounter.
195 | * @retval None
196 | */
197 | void IWDG_SetWindowValue(uint16_t WindowValue)
198 | {
199 | /* Check the parameters */
200 | assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
201 | IWDG->WINR = WindowValue;
202 | }
203 |
204 | /**
205 | * @}
206 | */
207 |
208 | /** @defgroup IWDG_Group2 IWDG activation function
209 | * @brief IWDG activation function
210 | *
211 | @verbatim
212 | ===============================================================================
213 | ##### IWDG activation function #####
214 | ===============================================================================
215 |
216 | @endverbatim
217 | * @{
218 | */
219 |
220 | /**
221 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
222 | * @param None
223 | * @retval None
224 | */
225 | void IWDG_Enable(void)
226 | {
227 | IWDG->KR = KR_KEY_ENABLE;
228 | }
229 |
230 | /**
231 | * @}
232 | */
233 |
234 | /** @defgroup IWDG_Group3 Flag management function
235 | * @brief Flag management function
236 | *
237 | @verbatim
238 | ===============================================================================
239 | ##### Flag management function #####
240 | ===============================================================================
241 |
242 | @endverbatim
243 | * @{
244 | */
245 |
246 | /**
247 | * @brief Checks whether the specified IWDG flag is set or not.
248 | * @param IWDG_FLAG: specifies the flag to check.
249 | * This parameter can be one of the following values:
250 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
251 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
252 | * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
253 | * @retval The new state of IWDG_FLAG (SET or RESET).
254 | */
255 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
256 | {
257 | FlagStatus bitstatus = RESET;
258 | /* Check the parameters */
259 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
260 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
261 | {
262 | bitstatus = SET;
263 | }
264 | else
265 | {
266 | bitstatus = RESET;
267 | }
268 | /* Return the flag status */
269 | return bitstatus;
270 | }
271 |
272 | /**
273 | * @}
274 | */
275 |
276 | /**
277 | * @}
278 | */
279 |
280 | /**
281 | * @}
282 | */
283 |
284 | /**
285 | * @}
286 | */
287 |
288 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
289 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_misc.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file provides all the miscellaneous firmware functions (add-on
8 | * to CMSIS functions).
9 | *
10 | @verbatim
11 |
12 | ===============================================================================
13 | ##### How to configure Interrupts using driver #####
14 | ===============================================================================
15 | [..] This section provide functions allowing to configure the NVIC interrupts
16 | (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
17 | (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
18 | function according to the following table.
19 | The table below gives the allowed values of the pre-emption priority
20 | and subpriority according to the Priority Grouping configuration
21 | performed by NVIC_PriorityGroupConfig function.
22 |
23 | (#) Enable and Configure the priority of the selected IRQ Channels.
24 | [..]
25 | (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
26 | the IRQ priority will be managed only by subpriority.
27 | The sub-priority is only used to sort pending exception priorities,
28 | and does not affect active exceptions.
29 | (@) Lower priority values gives higher priority.
30 | (@) Priority Order:
31 | (#@) Lowest Preemption priority.
32 | (#@) Lowest Subpriority.
33 | (#@) Lowest hardware priority (IRQn position).
34 |
35 | @endverbatim
36 |
37 | ******************************************************************************
38 | * @attention
39 | *
40 | * © COPYRIGHT 2012 STMicroelectronics
41 | *
42 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
43 | * You may not use this file except in compliance with the License.
44 | * You may obtain a copy of the License at:
45 | *
46 | * http://www.st.com/software_license_agreement_liberty_v2
47 | *
48 | * Unless required by applicable law or agreed to in writing, software
49 | * distributed under the License is distributed on an "AS IS" BASIS,
50 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
51 | * See the License for the specific language governing permissions and
52 | * limitations under the License.
53 | *
54 | ******************************************************************************
55 | */
56 |
57 | /* Includes ------------------------------------------------------------------*/
58 | #include "stm32f30x_misc.h"
59 |
60 | /** @addtogroup STM32F30x_StdPeriph_Driver
61 | * @{
62 | */
63 |
64 | /** @defgroup MISC
65 | * @brief MISC driver modules
66 | * @{
67 | */
68 |
69 | /* Private typedef -----------------------------------------------------------*/
70 | /* Private define ------------------------------------------------------------*/
71 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
72 |
73 | /* Private macro -------------------------------------------------------------*/
74 | /* Private variables ---------------------------------------------------------*/
75 | /* Private function prototypes -----------------------------------------------*/
76 | /* Private functions ---------------------------------------------------------*/
77 |
78 | /** @defgroup MISC_Private_Functions
79 | * @{
80 | */
81 |
82 | /**
83 | * @brief Configures the priority grouping: pre-emption priority and subpriority.
84 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
85 | * This parameter can be one of the following values:
86 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
87 | * 4 bits for subpriority.
88 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
89 | * 3 bits for subpriority.
90 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
91 | * 2 bits for subpriority.
92 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
93 | * 1 bits for subpriority.
94 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
95 | * 0 bits for subpriority.
96 | * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
97 | * interrupt. This interrupts priority is managed only with subpriority.
98 | * @retval None
99 | */
100 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
101 | {
102 | /* Check the parameters */
103 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
104 |
105 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
106 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
107 | }
108 |
109 | /**
110 | * @brief Initializes the NVIC peripheral according to the specified
111 | * parameters in the NVIC_InitStruct.
112 | * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
113 | * function should be called before.
114 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
115 | * the configuration information for the specified NVIC peripheral.
116 | * @retval None
117 | */
118 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
119 | {
120 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
121 |
122 | /* Check the parameters */
123 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
124 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
125 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
126 |
127 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
128 | {
129 | /* Compute the Corresponding IRQ Priority --------------------------------*/
130 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
131 | tmppre = (0x4 - tmppriority);
132 | tmpsub = tmpsub >> tmppriority;
133 |
134 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
135 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
136 | tmppriority = tmppriority << 0x04;
137 |
138 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
139 |
140 | /* Enable the Selected IRQ Channels --------------------------------------*/
141 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
143 | }
144 | else
145 | {
146 | /* Disable the Selected IRQ Channels -------------------------------------*/
147 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
148 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
149 | }
150 | }
151 |
152 | /**
153 | * @brief Sets the vector table location and Offset.
154 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
155 | * This parameter can be one of the following values:
156 | * @arg NVIC_VectTab_RAM
157 | * @arg NVIC_VectTab_FLASH
158 | * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
159 | * @retval None
160 | */
161 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
162 | {
163 | /* Check the parameters */
164 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
165 | assert_param(IS_NVIC_OFFSET(Offset));
166 |
167 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
168 | }
169 |
170 | /**
171 | * @brief Selects the condition for the system to enter low power mode.
172 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
173 | * This parameter can be one of the following values:
174 | * @arg NVIC_LP_SEVONPEND
175 | * @arg NVIC_LP_SLEEPDEEP
176 | * @arg NVIC_LP_SLEEPONEXIT
177 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
178 | * @retval None
179 | */
180 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
181 | {
182 | /* Check the parameters */
183 | assert_param(IS_NVIC_LP(LowPowerMode));
184 | assert_param(IS_FUNCTIONAL_STATE(NewState));
185 |
186 | if (NewState != DISABLE)
187 | {
188 | SCB->SCR |= LowPowerMode;
189 | }
190 | else
191 | {
192 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
193 | }
194 | }
195 |
196 | /**
197 | * @brief Configures the SysTick clock source.
198 | * @param SysTick_CLKSource: specifies the SysTick clock source.
199 | * This parameter can be one of the following values:
200 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
201 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
202 | * @retval None
203 | */
204 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
205 | {
206 | /* Check the parameters */
207 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
208 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
209 | {
210 | SysTick->CTRL |= SysTick_CLKSource_HCLK;
211 | }
212 | else
213 | {
214 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
215 | }
216 | }
217 |
218 | /**
219 | * @}
220 | */
221 |
222 | /**
223 | * @}
224 | */
225 |
226 | /**
227 | * @}
228 | */
229 |
230 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
231 |
--------------------------------------------------------------------------------
/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_wwdg.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Window watchdog (WWDG) peripheral:
9 | * + Prescaler, Refresh window and Counter configuration
10 | * + WWDG activation
11 | * + Interrupts and flags management
12 | *
13 | * @verbatim
14 | *
15 | ==============================================================================
16 | ##### WWDG features #####
17 | ==============================================================================
18 |
19 | [..] Once enabled the WWDG generates a system reset on expiry of a programmed
20 | time period, unless the program refreshes the counter (downcounter)
21 | before to reach 0x3F value (i.e. a reset is generated when the counter
22 | value rolls over from 0x40 to 0x3F).
23 | [..] An MCU reset is also generated if the counter value is refreshed
24 | before the counter has reached the refresh window value. This
25 | implies that the counter must be refreshed in a limited window.
26 |
27 | [..] Once enabled the WWDG cannot be disabled except by a system reset.
28 |
29 | [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
30 | reset occurs.
31 |
32 | [..] The WWDG counter input clock is derived from the APB clock divided
33 | by a programmable prescaler.
34 |
35 | [..] WWDG counter clock = PCLK1 / Prescaler.
36 | [..] WWDG timeout = (WWDG counter clock) * (counter value).
37 |
38 | [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
39 |
40 | ##### How to use this driver #####
41 | ==============================================================================
42 | [..]
43 | (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
44 | function.
45 |
46 | (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
47 |
48 | (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
49 |
50 | (#) Set the WWDG counter value and start it using WWDG_Enable() function.
51 | When the WWDG is enabled the counter value should be configured to
52 | a value greater than 0x40 to prevent generating an immediate reset.
53 |
54 | (#) Optionally you can enable the Early wakeup interrupt which is
55 | generated when the counter reach 0x40.
56 | Once enabled this interrupt cannot be disabled except by a system reset.
57 |
58 | (#) Then the application program must refresh the WWDG counter at regular
59 | intervals during normal operation to prevent an MCU reset, using
60 | WWDG_SetCounter() function. This operation must occur only when
61 | the counter value is lower than the refresh window value,
62 | programmed using WWDG_SetWindowValue().
63 |
64 | @endverbatim
65 |
66 | ******************************************************************************
67 | * @attention
68 | *
69 | * © COPYRIGHT 2012 STMicroelectronics
70 | *
71 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
72 | * You may not use this file except in compliance with the License.
73 | * You may obtain a copy of the License at:
74 | *
75 | * http://www.st.com/software_license_agreement_liberty_v2
76 | *
77 | * Unless required by applicable law or agreed to in writing, software
78 | * distributed under the License is distributed on an "AS IS" BASIS,
79 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
80 | * See the License for the specific language governing permissions and
81 | * limitations under the License.
82 | *
83 | ******************************************************************************
84 | */
85 |
86 | /* Includes ------------------------------------------------------------------*/
87 | #include "stm32f30x_wwdg.h"
88 | #include "stm32f30x_rcc.h"
89 |
90 | /** @addtogroup STM32F30x_StdPeriph_Driver
91 | * @{
92 | */
93 |
94 | /** @defgroup WWDG
95 | * @brief WWDG driver modules
96 | * @{
97 | */
98 |
99 | /* Private typedef -----------------------------------------------------------*/
100 | /* Private define ------------------------------------------------------------*/
101 | /* --------------------- WWDG registers bit mask ---------------------------- */
102 | /* CFR register bit mask */
103 | #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
104 | #define CFR_W_MASK ((uint32_t)0xFFFFFF80)
105 | #define BIT_MASK ((uint8_t)0x7F)
106 |
107 | /* Private macro -------------------------------------------------------------*/
108 | /* Private variables ---------------------------------------------------------*/
109 | /* Private function prototypes -----------------------------------------------*/
110 | /* Private functions ---------------------------------------------------------*/
111 |
112 | /** @defgroup WWDG_Private_Functions
113 | * @{
114 | */
115 |
116 | /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
117 | * @brief Prescaler, Refresh window and Counter configuration functions
118 | *
119 | @verbatim
120 | ==============================================================================
121 | ##### Prescaler, Refresh window and Counter configuration functions #####
122 | ==============================================================================
123 |
124 | @endverbatim
125 | * @{
126 | */
127 |
128 | /**
129 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
130 | * @param None
131 | * @retval None
132 | */
133 | void WWDG_DeInit(void)
134 | {
135 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
136 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
137 | }
138 |
139 | /**
140 | * @brief Sets the WWDG Prescaler.
141 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
142 | * This parameter can be one of the following values:
143 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
144 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
145 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
146 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
147 | * @retval None
148 | */
149 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
150 | {
151 | uint32_t tmpreg = 0;
152 | /* Check the parameters */
153 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
154 | /* Clear WDGTB[1:0] bits */
155 | tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
156 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
157 | tmpreg |= WWDG_Prescaler;
158 | /* Store the new value */
159 | WWDG->CFR = tmpreg;
160 | }
161 |
162 | /**
163 | * @brief Sets the WWDG window value.
164 | * @param WindowValue: specifies the window value to be compared to the downcounter.
165 | * This parameter value must be lower than 0x80.
166 | * @retval None
167 | */
168 | void WWDG_SetWindowValue(uint8_t WindowValue)
169 | {
170 | __IO uint32_t tmpreg = 0;
171 |
172 | /* Check the parameters */
173 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
174 | /* Clear W[6:0] bits */
175 |
176 | tmpreg = WWDG->CFR & CFR_W_MASK;
177 |
178 | /* Set W[6:0] bits according to WindowValue value */
179 | tmpreg |= WindowValue & (uint32_t) BIT_MASK;
180 |
181 | /* Store the new value */
182 | WWDG->CFR = tmpreg;
183 | }
184 |
185 | /**
186 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
187 | * @note Once enabled this interrupt cannot be disabled except by a system reset.
188 | * @param None
189 | * @retval None
190 | */
191 | void WWDG_EnableIT(void)
192 | {
193 | WWDG->CFR |= WWDG_CFR_EWI;
194 | }
195 |
196 | /**
197 | * @brief Sets the WWDG counter value.
198 | * @param Counter: specifies the watchdog counter value.
199 | * This parameter must be a number between 0x40 and 0x7F (to prevent generating
200 | * an immediate reset).
201 | * @retval None
202 | */
203 | void WWDG_SetCounter(uint8_t Counter)
204 | {
205 | /* Check the parameters */
206 | assert_param(IS_WWDG_COUNTER(Counter));
207 | /* Write to T[6:0] bits to configure the counter value, no need to do
208 | a read-modify-write; writing a 0 to WDGA bit does nothing */
209 | WWDG->CR = Counter & BIT_MASK;
210 | }
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /** @defgroup WWDG_Group2 WWDG activation functions
217 | * @brief WWDG activation functions
218 | *
219 | @verbatim
220 | ==============================================================================
221 | ##### WWDG activation function #####
222 | ==============================================================================
223 |
224 | @endverbatim
225 | * @{
226 | */
227 |
228 | /**
229 | * @brief Enables WWDG and load the counter value.
230 | * @param Counter: specifies the watchdog counter value.
231 | * This parameter must be a number between 0x40 and 0x7F (to prevent generating
232 | * an immediate reset).
233 | * @retval None
234 | */
235 | void WWDG_Enable(uint8_t Counter)
236 | {
237 | /* Check the parameters */
238 | assert_param(IS_WWDG_COUNTER(Counter));
239 | WWDG->CR = WWDG_CR_WDGA | Counter;
240 | }
241 |
242 | /**
243 | * @}
244 | */
245 |
246 | /** @defgroup WWDG_Group3 Interrupts and flags management functions
247 | * @brief Interrupts and flags management functions
248 | *
249 | @verbatim
250 | ==============================================================================
251 | ##### Interrupts and flags management functions #####
252 | ==============================================================================
253 |
254 | @endverbatim
255 | * @{
256 | */
257 |
258 | /**
259 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
260 | * @param None
261 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
262 | */
263 | FlagStatus WWDG_GetFlagStatus(void)
264 | {
265 | FlagStatus bitstatus = RESET;
266 |
267 | if ((WWDG->SR) != (uint32_t)RESET)
268 | {
269 | bitstatus = SET;
270 | }
271 | else
272 | {
273 | bitstatus = RESET;
274 | }
275 | return bitstatus;
276 | }
277 |
278 | /**
279 | * @brief Clears Early Wakeup interrupt flag.
280 | * @param None
281 | * @retval None
282 | */
283 | void WWDG_ClearFlag(void)
284 | {
285 | WWDG->SR = (uint32_t)RESET;
286 | }
287 |
288 | /**
289 | * @}
290 | */
291 |
292 | /**
293 | * @}
294 | */
295 |
296 | /**
297 | * @}
298 | */
299 |
300 | /**
301 | * @}
302 | */
303 |
304 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
305 |
--------------------------------------------------------------------------------
/flash.cfg:
--------------------------------------------------------------------------------
1 | set TRANSPORT hla_swd
2 |
3 | source [find interface/stlink-v2.cfg]
4 | source [find target/stm32f3x_stlink.cfg]
5 |
6 | #reset_config none separate
7 | #reset_config srst_push_pull
8 | #separate trst_push_pull
9 |
10 | reset_config srst_nogate
11 |
12 | init
13 |
14 | reset halt
15 | halt 200
16 | reset
17 | sleep 10
18 | halt 200
19 | flash write_image erase main.bin 0x08000000
20 | sleep 10
21 | reset
22 | sleep 10
23 | arm semihosting enable
24 | reset run
25 | sleep 10
26 | #shutdown
27 |
--------------------------------------------------------------------------------
/lib/startup_stm32f30x.s:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file startup_stm32f30x.s
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
8 | * This module performs:
9 | * - Set the initial SP
10 | * - Set the initial PC == Reset_Handler,
11 | * - Set the vector table entries with the exceptions ISR address,
12 | * - Configure the clock system
13 | * - Branches to main in the C library (which eventually
14 | * calls main()).
15 | * After Reset the Cortex-M4 processor is in Thread mode,
16 | * priority is Privileged, and the Stack is set to Main.
17 | ******************************************************************************
18 | * @attention
19 | *
20 | * © COPYRIGHT 2012 STMicroelectronics
21 | *
22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
23 | * You may not use this file except in compliance with the License.
24 | * You may obtain a copy of the License at:
25 | *
26 | * http://www.st.com/software_license_agreement_liberty_v2
27 | *
28 | * Unless required by applicable law or agreed to in writing, software
29 | * distributed under the License is distributed on an "AS IS" BASIS,
30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31 | * See the License for the specific language governing permissions and
32 | * limitations under the License.
33 | *
34 | ******************************************************************************
35 | */
36 |
37 | .syntax unified
38 | .cpu cortex-m4
39 | .fpu softvfp
40 | .thumb
41 |
42 | .global g_pfnVectors
43 | .global Default_Handler
44 |
45 | /* start address for the initialization values of the .data section.
46 | defined in linker script */
47 | .word _sidata
48 | /* start address for the .data section. defined in linker script */
49 | .word _sdata
50 | /* end address for the .data section. defined in linker script */
51 | .word _edata
52 | /* start address for the .bss section. defined in linker script */
53 | .word _sbss
54 | /* end address for the .bss section. defined in linker script */
55 | .word _ebss
56 |
57 | .equ BootRAM, 0xF1E0F85F
58 | /**
59 | * @brief This is the code that gets called when the processor first
60 | * starts execution following a reset event. Only the absolutely
61 | * necessary set is performed, after which the application
62 | * supplied main() routine is called.
63 | * @param None
64 | * @retval : None
65 | */
66 |
67 | .section .text.Reset_Handler
68 | .weak Reset_Handler
69 | .type Reset_Handler, %function
70 | Reset_Handler:
71 |
72 | /* Copy the data segment initializers from flash to SRAM */
73 | movs r1, #0
74 | b LoopCopyDataInit
75 |
76 | CopyDataInit:
77 |
78 | ldr r3, =_sidata
79 | ldr r3, [r3, r1]
80 | str r3, [r0, r1]
81 | adds r1, r1, #4
82 |
83 | LoopCopyDataInit:
84 | ldr r0, =_sdata
85 | ldr r3, =_edata
86 | adds r2, r0, r1
87 | cmp r2, r3
88 | bcc CopyDataInit
89 | ldr r2, =_sbss
90 | b LoopFillZerobss
91 | /* Zero fill the bss segment. */
92 | FillZerobss:
93 | movs r3, #0
94 | str r3, [r2], #4
95 |
96 | LoopFillZerobss:
97 | ldr r3, = _ebss
98 | cmp r2, r3
99 | bcc FillZerobss
100 |
101 | /* Call the clock system intitialization function.*/
102 | bl SystemInit
103 |
104 | /* Call static constructors */
105 | bl __libc_init_array
106 | /* Call the application's entry point.*/
107 |
108 | bl main
109 |
110 | LoopForever:
111 | b LoopForever
112 |
113 | .size Reset_Handler, .-Reset_Handler
114 |
115 | /**
116 | * @brief This is the code that gets called when the processor receives an
117 | * unexpected interrupt. This simply enters an infinite loop, preserving
118 | * the system state for examination by a debugger.
119 | *
120 | * @param None
121 | * @retval : None
122 | */
123 | .section .text.Default_Handler,"ax",%progbits
124 | Default_Handler:
125 | Infinite_Loop:
126 | b Infinite_Loop
127 | .size Default_Handler, .-Default_Handler
128 | /******************************************************************************
129 | *
130 | * The minimal vector table for a Cortex-M4. Note that the proper constructs
131 | * must be placed on this to ensure that it ends up at physical address
132 | * 0x0000.0000.
133 | *
134 | ******************************************************************************/
135 | .section .isr_vector,"a",%progbits
136 | .type g_pfnVectors, %object
137 | .size g_pfnVectors, .-g_pfnVectors
138 |
139 |
140 | g_pfnVectors:
141 | .word _estack
142 | .word Reset_Handler
143 | .word NMI_Handler
144 | .word HardFault_Handler
145 | .word MemManage_Handler
146 | .word BusFault_Handler
147 | .word UsageFault_Handler
148 | .word 0
149 | .word 0
150 | .word 0
151 | .word 0
152 | .word SVC_Handler
153 | .word DebugMon_Handler
154 | .word 0
155 | .word PendSV_Handler
156 | .word SysTick_Handler
157 | .word WWDG_IRQHandler
158 | .word PVD_IRQHandler
159 | .word TAMPER_STAMP_IRQHandler
160 | .word RTC_WKUP_IRQHandler
161 | .word FLASH_IRQHandler
162 | .word RCC_IRQHandler
163 | .word EXTI0_IRQHandler
164 | .word EXTI1_IRQHandler
165 | .word EXTI2_TS_IRQHandler
166 | .word EXTI3_IRQHandler
167 | .word EXTI4_IRQHandler
168 | .word DMA1_Channel1_IRQHandler
169 | .word DMA1_Channel2_IRQHandler
170 | .word DMA1_Channel3_IRQHandler
171 | .word DMA1_Channel4_IRQHandler
172 | .word DMA1_Channel5_IRQHandler
173 | .word DMA1_Channel6_IRQHandler
174 | .word DMA1_Channel7_IRQHandler
175 | .word ADC1_2_IRQHandler
176 | .word USB_HP_CAN1_TX_IRQHandler
177 | .word USB_LP_CAN1_RX0_IRQHandler
178 | .word CAN1_RX1_IRQHandler
179 | .word CAN1_SCE_IRQHandler
180 | .word EXTI9_5_IRQHandler
181 | .word TIM1_BRK_TIM15_IRQHandler
182 | .word TIM1_UP_TIM16_IRQHandler
183 | .word TIM1_TRG_COM_TIM17_IRQHandler
184 | .word TIM1_CC_IRQHandler
185 | .word TIM2_IRQHandler
186 | .word TIM3_IRQHandler
187 | .word TIM4_IRQHandler
188 | .word I2C1_EV_IRQHandler
189 | .word I2C1_ER_IRQHandler
190 | .word I2C2_EV_IRQHandler
191 | .word I2C2_ER_IRQHandler
192 | .word SPI1_IRQHandler
193 | .word SPI2_IRQHandler
194 | .word USART1_IRQHandler
195 | .word USART2_IRQHandler
196 | .word USART3_IRQHandler
197 | .word EXTI15_10_IRQHandler
198 | .word RTC_Alarm_IRQHandler
199 | .word USBWakeUp_IRQHandler
200 | .word TIM8_BRK_IRQHandler
201 | .word TIM8_UP_IRQHandler
202 | .word TIM8_TRG_COM_IRQHandler
203 | .word TIM8_CC_IRQHandler
204 | .word ADC3_IRQHandler
205 | .word 0
206 | .word 0
207 | .word 0
208 | .word SPI3_IRQHandler
209 | .word UART4_IRQHandler
210 | .word UART5_IRQHandler
211 | .word TIM6_DAC_IRQHandler
212 | .word TIM7_IRQHandler
213 | .word DMA2_Channel1_IRQHandler
214 | .word DMA2_Channel2_IRQHandler
215 | .word DMA2_Channel3_IRQHandler
216 | .word DMA2_Channel4_IRQHandler
217 | .word DMA2_Channel5_IRQHandler
218 | .word ADC4_IRQHandler
219 | .word 0
220 | .word 0
221 | .word COMP1_2_3_IRQHandler
222 | .word COMP4_5_6_IRQHandler
223 | .word COMP7_IRQHandler
224 | .word 0
225 | .word 0
226 | .word 0
227 | .word 0
228 | .word 0
229 | .word 0
230 | .word 0
231 | .word USB_HP_IRQHandler
232 | .word USB_LP_IRQHandler
233 | .word USBWakeUp_RMP_IRQHandler
234 | .word 0
235 | .word 0
236 | .word 0
237 | .word 0
238 | .word FPU_IRQHandler
239 |
240 | /*******************************************************************************
241 | *
242 | * Provide weak aliases for each Exception handler to the Default_Handler.
243 | * As they are weak aliases, any function with the same name will override
244 | * this definition.
245 | *
246 | *******************************************************************************/
247 |
248 | .weak NMI_Handler
249 | .thumb_set NMI_Handler,Default_Handler
250 |
251 | .weak HardFault_Handler
252 | .thumb_set HardFault_Handler,Default_Handler
253 |
254 | .weak MemManage_Handler
255 | .thumb_set MemManage_Handler,Default_Handler
256 |
257 | .weak BusFault_Handler
258 | .thumb_set BusFault_Handler,Default_Handler
259 |
260 | .weak UsageFault_Handler
261 | .thumb_set UsageFault_Handler,Default_Handler
262 |
263 | .weak SVC_Handler
264 | .thumb_set SVC_Handler,Default_Handler
265 |
266 | .weak DebugMon_Handler
267 | .thumb_set DebugMon_Handler,Default_Handler
268 |
269 | .weak PendSV_Handler
270 | .thumb_set PendSV_Handler,Default_Handler
271 |
272 | .weak SysTick_Handler
273 | .thumb_set SysTick_Handler,Default_Handler
274 |
275 | .weak WWDG_IRQHandler
276 | .thumb_set WWDG_IRQHandler,Default_Handler
277 |
278 | .weak PVD_IRQHandler
279 | .thumb_set PVD_IRQHandler,Default_Handler
280 |
281 | .weak TAMPER_STAMP_IRQHandler
282 | .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
283 |
284 | .weak RTC_WKUP_IRQHandler
285 | .thumb_set RTC_WKUP_IRQHandler,Default_Handler
286 |
287 | .weak FLASH_IRQHandler
288 | .thumb_set FLASH_IRQHandler,Default_Handler
289 |
290 | .weak RCC_IRQHandler
291 | .thumb_set RCC_IRQHandler,Default_Handler
292 |
293 | .weak EXTI0_IRQHandler
294 | .thumb_set EXTI0_IRQHandler,Default_Handler
295 |
296 | .weak EXTI1_IRQHandler
297 | .thumb_set EXTI1_IRQHandler,Default_Handler
298 |
299 | .weak EXTI2_TS_IRQHandler
300 | .thumb_set EXTI2_TS_IRQHandler,Default_Handler
301 |
302 | .weak EXTI3_IRQHandler
303 | .thumb_set EXTI3_IRQHandler,Default_Handler
304 |
305 | .weak EXTI4_IRQHandler
306 | .thumb_set EXTI4_IRQHandler,Default_Handler
307 |
308 | .weak DMA1_Channel1_IRQHandler
309 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
310 |
311 | .weak DMA1_Channel2_IRQHandler
312 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
313 |
314 | .weak DMA1_Channel3_IRQHandler
315 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
316 |
317 | .weak DMA1_Channel4_IRQHandler
318 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
319 |
320 | .weak DMA1_Channel5_IRQHandler
321 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
322 |
323 | .weak DMA1_Channel6_IRQHandler
324 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
325 |
326 | .weak DMA1_Channel7_IRQHandler
327 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
328 |
329 | .weak ADC1_2_IRQHandler
330 | .thumb_set ADC1_2_IRQHandler,Default_Handler
331 |
332 | .weak USB_HP_CAN1_TX_IRQHandler
333 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
334 |
335 | .weak USB_LP_CAN1_RX0_IRQHandler
336 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
337 |
338 | .weak CAN1_RX1_IRQHandler
339 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler
340 |
341 | .weak CAN1_SCE_IRQHandler
342 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler
343 |
344 | .weak EXTI9_5_IRQHandler
345 | .thumb_set EXTI9_5_IRQHandler,Default_Handler
346 |
347 | .weak TIM1_BRK_TIM15_IRQHandler
348 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
349 |
350 | .weak TIM1_UP_TIM16_IRQHandler
351 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
352 |
353 | .weak TIM1_TRG_COM_TIM17_IRQHandler
354 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
355 |
356 | .weak TIM1_CC_IRQHandler
357 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
358 |
359 | .weak TIM2_IRQHandler
360 | .thumb_set TIM2_IRQHandler,Default_Handler
361 |
362 | .weak TIM3_IRQHandler
363 | .thumb_set TIM3_IRQHandler,Default_Handler
364 |
365 | .weak TIM4_IRQHandler
366 | .thumb_set TIM4_IRQHandler,Default_Handler
367 |
368 | .weak I2C1_EV_IRQHandler
369 | .thumb_set I2C1_EV_IRQHandler,Default_Handler
370 |
371 | .weak I2C1_ER_IRQHandler
372 | .thumb_set I2C1_ER_IRQHandler,Default_Handler
373 |
374 | .weak I2C2_EV_IRQHandler
375 | .thumb_set I2C2_EV_IRQHandler,Default_Handler
376 |
377 | .weak I2C2_ER_IRQHandler
378 | .thumb_set I2C2_ER_IRQHandler,Default_Handler
379 |
380 | .weak SPI1_IRQHandler
381 | .thumb_set SPI1_IRQHandler,Default_Handler
382 |
383 | .weak SPI2_IRQHandler
384 | .thumb_set SPI2_IRQHandler,Default_Handler
385 |
386 | .weak USART1_IRQHandler
387 | .thumb_set USART1_IRQHandler,Default_Handler
388 |
389 | .weak USART2_IRQHandler
390 | .thumb_set USART2_IRQHandler,Default_Handler
391 |
392 | .weak USART3_IRQHandler
393 | .thumb_set USART3_IRQHandler,Default_Handler
394 |
395 | .weak EXTI15_10_IRQHandler
396 | .thumb_set EXTI15_10_IRQHandler,Default_Handler
397 |
398 | .weak RTC_Alarm_IRQHandler
399 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler
400 |
401 | .weak USBWakeUp_IRQHandler
402 | .thumb_set USBWakeUp_IRQHandler,Default_Handler
403 |
404 | .weak TIM8_BRK_IRQHandler
405 | .thumb_set TIM8_BRK_IRQHandler,Default_Handler
406 |
407 | .weak TIM8_UP_IRQHandler
408 | .thumb_set TIM8_UP_IRQHandler,Default_Handler
409 |
410 | .weak TIM8_TRG_COM_IRQHandler
411 | .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
412 |
413 | .weak TIM8_CC_IRQHandler
414 | .thumb_set TIM8_CC_IRQHandler,Default_Handler
415 |
416 | .weak ADC3_IRQHandler
417 | .thumb_set ADC3_IRQHandler,Default_Handler
418 |
419 | .weak SPI3_IRQHandler
420 | .thumb_set SPI3_IRQHandler,Default_Handler
421 |
422 | .weak UART4_IRQHandler
423 | .thumb_set UART4_IRQHandler,Default_Handler
424 |
425 | .weak UART5_IRQHandler
426 | .thumb_set UART5_IRQHandler,Default_Handler
427 |
428 | .weak TIM6_DAC_IRQHandler
429 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler
430 |
431 | .weak TIM7_IRQHandler
432 | .thumb_set TIM7_IRQHandler,Default_Handler
433 |
434 | .weak DMA2_Channel1_IRQHandler
435 | .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
436 |
437 | .weak DMA2_Channel2_IRQHandler
438 | .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
439 |
440 | .weak DMA2_Channel3_IRQHandler
441 | .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
442 |
443 | .weak DMA2_Channel4_IRQHandler
444 | .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
445 |
446 | .weak DMA2_Channel5_IRQHandler
447 | .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
448 |
449 | .weak ADC4_IRQHandler
450 | .thumb_set ADC4_IRQHandler,Default_Handler
451 |
452 | .weak COMP1_2_3_IRQHandler
453 | .thumb_set COMP1_2_3_IRQHandler,Default_Handler
454 |
455 | .weak COMP4_5_6_IRQHandler
456 | .thumb_set COMP4_5_6_IRQHandler,Default_Handler
457 |
458 | .weak COMP7_IRQHandler
459 | .thumb_set COMP7_IRQHandler,Default_Handler
460 |
461 | .weak USB_HP_IRQHandler
462 | .thumb_set USB_HP_IRQHandler,Default_Handler
463 |
464 | .weak USB_LP_IRQHandler
465 | .thumb_set USB_LP_IRQHandler,Default_Handler
466 |
467 | .weak USBWakeUp_RMP_IRQHandler
468 | .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
469 |
470 | .weak FPU_IRQHandler
471 | .thumb_set FPU_IRQHandler,Default_Handler
472 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
473 |
474 |
475 |
--------------------------------------------------------------------------------
/lib/stm32f303.ld:
--------------------------------------------------------------------------------
1 | /*. Entry Point *./
2 | ENTRY( Reset_Handler )
3 |
4 | /* Highest address of the user mode stack .*/
5 |
6 | _estack = 0x2000a000; /* end of 40K RAM */
7 |
8 | /* Generate a link error if heap and s tack dont fit int o RAM */
9 |
10 | _Min_Heap_Size = 0; /* required amount of heap .*/
11 | _Min_Stack_Size = 0x200; /* required amount of stack .*/
12 |
13 | MEMORY
14 | {
15 | FLASH ( rx ) : ORIGIN = 0x08000000 , LENGTH = 256K
16 | RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 40K
17 | CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 8K
18 | }
19 |
20 | SECTIONS
21 | {
22 |
23 | /* The startup code goes first into FLASH */
24 | .isr_vector :
25 | {
26 | . = ALIGN(4);
27 | KEEP(*(.isr_vector)) /* Startup code */
28 | . = ALIGN(4);
29 | } >FLASH
30 |
31 | /* The program code and other data goes into FLASH */
32 | .text :
33 | {
34 | . = ALIGN(4);
35 | *(.text) /* .text sections (code) */
36 | *(.text*) /* .text* sections (code) */
37 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
38 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
39 | *(.glue_7) /* glue arm to thumb code */
40 | *(.glue_7t) /* glue thumb to arm code */
41 | *(.eh_frame)
42 |
43 | KEEP (*(.init))
44 | KEEP (*(.fini))
45 |
46 | . = ALIGN(4);
47 | _etext = .; /* define a global symbols at end of code */
48 | } >FLASH
49 |
50 |
51 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
52 |
53 | .ARM : {
54 | __exidx_start = .;
55 | *(.ARM.exidx*)
56 | __exidx_end = .;
57 | } >FLASH
58 |
59 | .preinit_array :
60 | {
61 | PROVIDE_HIDDEN (__preinit_array_start = .);
62 | KEEP (*(.preinit_array*))
63 | PROVIDE_HIDDEN (__preinit_array_end = .);
64 | } >FLASH
65 |
66 | .init_array :
67 | {
68 | PROVIDE_HIDDEN (__init_array_start = .);
69 | KEEP (*(SORT(.init_array.*)))
70 | KEEP (*(.init_array*))
71 | PROVIDE_HIDDEN (__init_array_end = .);
72 | } >FLASH
73 |
74 | .fini_array :
75 | {
76 | PROVIDE_HIDDEN (__fini_array_start = .);
77 | KEEP (*(SORT(.fini_array.*)))
78 | KEEP (*(.fini_array*))
79 | PROVIDE_HIDDEN (__fini_array_end = .);
80 | } >FLASH
81 |
82 | /* used by the startup to initialize data */
83 | _sidata = LOADADDR(.data);
84 |
85 | /* Initialized data sections goes into RAM, load LMA copy after code */
86 | .data :
87 | {
88 | . = ALIGN(4);
89 | _sdata = .;
90 | *(.data)
91 | *(.data*)
92 |
93 | . = ALIGN(4);
94 | _edata = .;
95 | } >RAM AT> FLASH
96 |
97 | .ccmram :
98 | {
99 | . = ALIGN(4);
100 | _sccmram = .;
101 | *(.ccmram)
102 | *(.ccmram*)
103 |
104 | . = ALIGN(4);
105 | _eccmram = .;
106 | } >CCMRAM AT> FLASH
107 |
108 | /* Uninitialized data section */
109 | . = ALIGN(4);
110 | .bss :
111 | {
112 | _sbss = .;
113 | __bss_start__ = _sbss;
114 | *(.bss)
115 | *(.bss*)
116 | *(COMMON)
117 |
118 | . = ALIGN(4);
119 | _ebss = .;
120 | __bss_end__ = _ebss;
121 | } >RAM
122 | }
123 |
124 |
125 |
--------------------------------------------------------------------------------
/lib/stm32f30x.h:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/cnlohr/minimal_stm32f303/656a71af8d555689b5c54676564156c271d734c0/lib/stm32f30x.h
--------------------------------------------------------------------------------
/lib/stm32f30x_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file STM32F3xx_EEPROM_Emulation/inc/stm32f30x_conf.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 02-October-2012
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2012 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F30X_CONF_H
30 | #define __STM32F30X_CONF_H
31 |
32 | #ifndef __STM32F30x_H
33 | /* Includes ------------------------------------------------------------------*/
34 | /* Comment the line below to disable peripheral header file inclusion */
35 | #include "stm32f30x_adc.h"
36 | #include "stm32f30x_can.h"
37 | #include "stm32f30x_crc.h"
38 | #include "stm32f30x_comp.h"
39 | #include "stm32f30x_dac.h"
40 | #include "stm32f30x_dbgmcu.h"
41 | #include "stm32f30x_dma.h"
42 | #include "stm32f30x_exti.h"
43 | #include "stm32f30x_flash.h"
44 | #include "stm32f30x_gpio.h"
45 | #include "stm32f30x_syscfg.h"
46 | #include "stm32f30x_i2c.h"
47 | #include "stm32f30x_iwdg.h"
48 | #include "stm32f30x_opamp.h"
49 | #include "stm32f30x_pwr.h"
50 | #include "stm32f30x_rcc.h"
51 | #include "stm32f30x_rtc.h"
52 | #include "stm32f30x_spi.h"
53 | #include "stm32f30x_tim.h"
54 | #include "stm32f30x_usart.h"
55 | #include "stm32f30x_wwdg.h"
56 | #include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
57 |
58 | #include "stm32f30x.h"
59 | #endif
60 | /* Exported types ------------------------------------------------------------*/
61 | /* Exported constants --------------------------------------------------------*/
62 | /* Uncomment the line below to expanse the "assert_param" macro in the
63 | Standard Peripheral Library drivers code */
64 | /* #define USE_FULL_ASSERT 1 */
65 |
66 | /* Exported macro ------------------------------------------------------------*/
67 | #ifdef USE_FULL_ASSERT
68 |
69 | /**
70 | * @brief The assert_param macro is used for function's parameters check.
71 | * @param expr: If expr is false, it calls assert_failed function which reports
72 | * the name of the source file and the source line number of the call
73 | * that failed. If expr is true, it returns no value.
74 | * @retval None
75 | */
76 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
77 | /* Exported functions ------------------------------------------------------- */
78 | void assert_failed(uint8_t* file, uint32_t line);
79 | #else
80 | #define assert_param(expr) ((void)0)
81 | #endif /* USE_FULL_ASSERT */
82 |
83 | #endif /* __STM32F30X_CONF_H */
84 |
85 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
86 |
--------------------------------------------------------------------------------
/lib/system_stm32f30x.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f30x.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 | * This file contains the system clock configuration for STM32F30x devices,
9 | * and is generated by the clock configuration tool
10 | * stm32f30x_Clock_Configuration_V1.0.0.xls
11 | *
12 | * 1. This file provides two functions and one global variable to be called from
13 | * user application:
14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
15 | * and Divider factors, AHB/APBx prescalers and Flash settings),
16 | * depending on the configuration made in the clock xls tool.
17 | * This function is called at startup just after reset and
18 | * before branch to main program. This call is made inside
19 | * the "startup_stm32f30x.s" file.
20 | *
21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
22 | * by the user application to setup the SysTick
23 | * timer or configure other parameters.
24 | *
25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
26 | * be called whenever the core clock is changed
27 | * during program execution.
28 | *
29 | * 2. After each device reset the HSI (8 MHz) is used as system clock source.
30 | * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
31 | * configure the system clock before to branch to main program.
32 | *
33 | * 3. If the system clock source selected by user fails to startup, the SystemInit()
34 | * function will do nothing and HSI still used as system clock source. User can
35 | * add some code to deal with this issue inside the SetSysClock() function.
36 | *
37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
38 | * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
39 | * through PLL, and you are using different crystal you have to adapt the HSE
40 | * value to your own configuration.
41 | *
42 | * 5. This file configures the system clock as follows:
43 | *=============================================================================
44 | * Supported STM32F30x device
45 | *-----------------------------------------------------------------------------
46 | * System Clock source | PLL (HSE)
47 | *-----------------------------------------------------------------------------
48 | * SYSCLK(Hz) | 72000000
49 | *-----------------------------------------------------------------------------
50 | * HCLK(Hz) | 72000000
51 | *-----------------------------------------------------------------------------
52 | * AHB Prescaler | 1
53 | *-----------------------------------------------------------------------------
54 | * APB2 Prescaler | 1
55 | *-----------------------------------------------------------------------------
56 | * APB1 Prescaler | 2
57 | *-----------------------------------------------------------------------------
58 | * HSE Frequency(Hz) | 8000000
59 | *----------------------------------------------------------------------------
60 | * PLLMUL | 9
61 | *-----------------------------------------------------------------------------
62 | * PREDIV | 1
63 | *-----------------------------------------------------------------------------
64 | * USB Clock | DISABLE
65 | *-----------------------------------------------------------------------------
66 | * Flash Latency(WS) | 2
67 | *-----------------------------------------------------------------------------
68 | * Prefetch Buffer | ON
69 | *-----------------------------------------------------------------------------
70 | *=============================================================================
71 | ******************************************************************************
72 | * @attention
73 | *
74 | * © COPYRIGHT 2012 STMicroelectronics
75 | *
76 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
77 | * You may not use this file except in compliance with the License.
78 | * You may obtain a copy of the License at:
79 | *
80 | * http://www.st.com/software_license_agreement_liberty_v2
81 | *
82 | * Unless required by applicable law or agreed to in writing, software
83 | * distributed under the License is distributed on an "AS IS" BASIS,
84 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
85 | * See the License for the specific language governing permissions and
86 | * limitations under the License.
87 | *
88 | ******************************************************************************
89 | */
90 | /** @addtogroup CMSIS
91 | * @{
92 | */
93 |
94 | /** @addtogroup stm32f30x_system
95 | * @{
96 | */
97 |
98 | /** @addtogroup STM32F30x_System_Private_Includes
99 | * @{
100 | */
101 |
102 | #include "stm32f30x.h"
103 |
104 | /**
105 | * @}
106 | */
107 |
108 | /** @addtogroup STM32F30x_System_Private_TypesDefinitions
109 | * @{
110 | */
111 |
112 | /**
113 | * @}
114 | */
115 |
116 | /** @addtogroup STM32F30x_System_Private_Defines
117 | * @{
118 | */
119 | /*!< Uncomment the following line if you need to relocate your vector Table in
120 | Internal SRAM. */
121 | /* #define VECT_TAB_SRAM */
122 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
123 | This value must be a multiple of 0x200. */
124 | /**
125 | * @}
126 | */
127 |
128 | /** @addtogroup STM32F30x_System_Private_Macros
129 | * @{
130 | */
131 |
132 | /**
133 | * @}
134 | */
135 |
136 | /** @addtogroup STM32F30x_System_Private_Variables
137 | * @{
138 | */
139 |
140 | uint32_t SystemCoreClock = 72000000;
141 |
142 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
143 |
144 | /**
145 | * @}
146 | */
147 |
148 | /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
149 | * @{
150 | */
151 |
152 | static void SetSysClock(void);
153 |
154 | /**
155 | * @}
156 | */
157 |
158 | /** @addtogroup STM32F30x_System_Private_Functions
159 | * @{
160 | */
161 |
162 | /**
163 | * @brief Setup the microcontroller system
164 | * Initialize the Embedded Flash Interface, the PLL and update the
165 | * SystemFrequency variable.
166 | * @param None
167 | * @retval None
168 | */
169 | void SystemInit(void)
170 | {
171 | /* FPU settings ------------------------------------------------------------*/
172 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
173 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
174 | #endif
175 |
176 | /* Reset the RCC clock configuration to the default reset state ------------*/
177 | /* Set HSION bit */
178 | RCC->CR |= (uint32_t)0x00000001;
179 |
180 | /* Reset CFGR register */
181 | RCC->CFGR &= 0xF87FC00C;
182 |
183 | /* Reset HSEON, CSSON and PLLON bits */
184 | RCC->CR &= (uint32_t)0xFEF6FFFF;
185 |
186 | /* Reset HSEBYP bit */
187 | RCC->CR &= (uint32_t)0xFFFBFFFF;
188 |
189 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
190 | RCC->CFGR &= (uint32_t)0xFF80FFFF;
191 |
192 | /* Reset PREDIV1[3:0] bits */
193 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
194 |
195 | /* Reset USARTSW[1:0], I2CSW and TIMs bits */
196 | RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
197 |
198 | /* Disable all interrupts */
199 | RCC->CIR = 0x00000000;
200 |
201 | /* Configure the System clock source, PLL Multiplier and Divider factors,
202 | AHB/APBx prescalers and Flash settings ----------------------------------*/
203 | SetSysClock();
204 |
205 | #ifdef VECT_TAB_SRAM
206 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
207 | #else
208 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
209 | #endif
210 | }
211 |
212 | /**
213 | * @brief Update SystemCoreClock variable according to Clock Register Values.
214 | * The SystemCoreClock variable contains the core clock (HCLK), it can
215 | * be used by the user application to setup the SysTick timer or configure
216 | * other parameters.
217 | *
218 | * @note Each time the core clock (HCLK) changes, this function must be called
219 | * to update SystemCoreClock variable value. Otherwise, any configuration
220 | * based on this variable will be incorrect.
221 | *
222 | * @note - The system frequency computed by this function is not the real
223 | * frequency in the chip. It is calculated based on the predefined
224 | * constant and the selected clock source:
225 | *
226 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
227 | *
228 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
229 | *
230 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
231 | * or HSI_VALUE(*) multiplied/divided by the PLL factors.
232 | *
233 | * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
234 | * 8 MHz) but the real value may vary depending on the variations
235 | * in voltage and temperature.
236 | *
237 | * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
238 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real
239 | * frequency of the crystal used. Otherwise, this function may
240 | * have wrong result.
241 | *
242 | * - The result of this function could be not correct when using fractional
243 | * value for HSE crystal.
244 | *
245 | * @param None
246 | * @retval None
247 | */
248 | void SystemCoreClockUpdate (void)
249 | {
250 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
251 |
252 | /* Get SYSCLK source -------------------------------------------------------*/
253 | tmp = RCC->CFGR & RCC_CFGR_SWS;
254 |
255 | switch (tmp)
256 | {
257 | case 0x00: /* HSI used as system clock */
258 | SystemCoreClock = HSI_VALUE;
259 | break;
260 | case 0x04: /* HSE used as system clock */
261 | SystemCoreClock = HSE_VALUE;
262 | break;
263 | case 0x08: /* PLL used as system clock */
264 | /* Get PLL clock source and multiplication factor ----------------------*/
265 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
266 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
267 | pllmull = ( pllmull >> 18) + 2;
268 |
269 | if (pllsource == 0x00)
270 | {
271 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
272 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
273 | }
274 | else
275 | {
276 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
277 | /* HSE oscillator clock selected as PREDIV1 clock entry */
278 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
279 | }
280 | break;
281 | default: /* HSI used as system clock */
282 | SystemCoreClock = HSI_VALUE;
283 | break;
284 | }
285 | /* Compute HCLK clock frequency ----------------*/
286 | /* Get HCLK prescaler */
287 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
288 | /* HCLK clock frequency */
289 | SystemCoreClock >>= tmp;
290 | }
291 |
292 | /**
293 | * @brief Configures the System clock source, PLL Multiplier and Divider factors,
294 | * AHB/APBx prescalers and Flash settings
295 | * @note This function should be called only once the RCC clock configuration
296 | * is reset to the default reset state (done in SystemInit() function).
297 | * @param None
298 | * @retval None
299 | */
300 | static void SetSysClock(void)
301 | {
302 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
303 |
304 | /******************************************************************************/
305 | /* PLL (clocked by HSE) used as System clock source */
306 | /******************************************************************************/
307 |
308 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
309 | /* Enable HSE */
310 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
311 |
312 | /* Wait till HSE is ready and if Time out is reached exit */
313 | do
314 | {
315 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
316 | StartUpCounter++;
317 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
318 |
319 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
320 | {
321 | HSEStatus = (uint32_t)0x01;
322 | }
323 | else
324 | {
325 | HSEStatus = (uint32_t)0x00;
326 | }
327 |
328 | if (HSEStatus == (uint32_t)0x01)
329 | {
330 | /* Enable Prefetch Buffer and set Flash Latency */
331 | FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
332 |
333 | /* HCLK = SYSCLK / 1 */
334 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
335 |
336 | /* PCLK2 = HCLK / 1 */
337 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
338 |
339 | /* PCLK1 = HCLK / 2 */
340 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
341 |
342 | /* PLL configuration */
343 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
344 | // RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
345 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL2); //25MHz*2 = 50 MHz
346 |
347 | /* Enable PLL */
348 | RCC->CR |= RCC_CR_PLLON;
349 |
350 | /* Wait till PLL is ready */
351 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
352 | {
353 | }
354 |
355 | /* Select PLL as system clock source */
356 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
357 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
358 |
359 | /* Wait till PLL is used as system clock source */
360 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
361 | {
362 | }
363 | }
364 | else
365 | { /* If HSE fails to start-up, the application will have wrong clock
366 | configuration. User can add here some code to deal with this error */
367 | }
368 | }
369 |
370 | /**
371 | * @}
372 | */
373 |
374 | /**
375 | * @}
376 | */
377 |
378 | /**
379 | * @}
380 | */
381 |
382 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
383 |
384 |
--------------------------------------------------------------------------------
/lib/system_stm32f30x.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f30x.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 04-September-2012
7 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2012 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /** @addtogroup CMSIS
29 | * @{
30 | */
31 |
32 | /** @addtogroup stm32f30x_system
33 | * @{
34 | */
35 |
36 | /**
37 | * @brief Define to prevent recursive inclusion
38 | */
39 | #ifndef __SYSTEM_STM32F30X_H
40 | #define __SYSTEM_STM32F30X_H
41 |
42 | #ifdef __cplusplus
43 | extern "C" {
44 | #endif
45 |
46 | /** @addtogroup STM32F30x_System_Includes
47 | * @{
48 | */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 |
55 | /** @addtogroup STM32F30x_System_Exported_types
56 | * @{
57 | */
58 |
59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
60 |
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @addtogroup STM32F30x_System_Exported_Constants
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @addtogroup STM32F30x_System_Exported_Macros
75 | * @{
76 | */
77 |
78 | /**
79 | * @}
80 | */
81 |
82 | /** @addtogroup STM32F30x_System_Exported_Functions
83 | * @{
84 | */
85 |
86 | extern void SystemInit(void);
87 | extern void SystemCoreClockUpdate(void);
88 | /**
89 | * @}
90 | */
91 |
92 | #ifdef __cplusplus
93 | }
94 | #endif
95 |
96 | #endif /*__SYSTEM_STM32F30X_H */
97 |
98 | /**
99 | * @}
100 | */
101 |
102 | /**
103 | * @}
104 | */
105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
106 |
--------------------------------------------------------------------------------
/lib/systems.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include "systems.h"
3 | #include
4 | #ifdef STM32F30X
5 | #include
6 | #include
7 | #include
8 | #elif defined( STM32F40_41xxx )
9 | #include
10 | #include
11 | #include
12 | #endif
13 | #include
14 | #include
15 |
16 | extern RCC_ClocksTypeDef RCC_Clocks;
17 |
18 | //For precise timing.
19 | volatile unsigned int *DWT_CYCCNT = (volatile unsigned int *)0xE0001004; //address of the register
20 | volatile unsigned int *SCB_DEMCR = (volatile unsigned int *)0xE000EDFC; //address of the register
21 | volatile unsigned int *DWT_CONTROL = (volatile unsigned int *)0xE0001000; //address of the register
22 |
23 | void send_openocd_command(int command, void *message)
24 | {
25 | #ifdef DEBUG
26 | asm("mov r0, %[cmd];"
27 | "mov r1, %[msg];"
28 | "bkpt #0xAB"
29 | :
30 | : [cmd] "r" (command), [msg] "r" (message)
31 | : "r0", "r1", "memory");
32 | #endif
33 | }
34 |
35 |
36 | void send_text( const char * text )
37 | {
38 | uint32_t m[] = { 2, (uint32_t)text, strlen(text) };
39 | send_openocd_command(0x05, m);
40 | }
41 |
42 | int __attribute__((used)) _write (int fd, const void *buf, size_t count)
43 | {
44 | uint32_t m[] = { 2, (uint32_t)buf, count };
45 | send_openocd_command(0x05, m);
46 | }
47 |
48 | void __attribute__((used)) * _sbrk(int incr) {
49 | extern char _ebss; // Defined by the linker
50 | static char *heap_end;
51 | char *prev_heap_end;
52 |
53 |
54 | if (heap_end == 0) {
55 | heap_end = &_ebss;
56 | }
57 | prev_heap_end = heap_end;
58 |
59 | char * stack = (char*) __get_MSP();
60 | if (heap_end + incr > stack)
61 | {
62 | return (void*)(-1);
63 | }
64 |
65 | heap_end += incr;
66 |
67 | return (void*) prev_heap_end;
68 | }
69 |
70 | void _delay_us(uint32_t us) {
71 | if( us ) us--; //Approximate extra overhead time.
72 | us *= RCC_Clocks.HCLK_Frequency/1000000;
73 | *SCB_DEMCR = *SCB_DEMCR | 0x01000000;
74 | *DWT_CYCCNT = 0; // reset the counter
75 | *DWT_CONTROL = *DWT_CONTROL | 1 ; // enable the counter
76 | while( *DWT_CYCCNT < us );
77 | }
78 |
79 | void ConfigureLED()
80 | {
81 | ConfigureGPIO( LEDPIN, INOUT_OUT );
82 | }
83 |
84 | uint8_t GetGPIOFromString( const char * str )
85 | {
86 | int mode = 0;
87 | int port = -1;
88 | int pin = -1;
89 | const char * st = str;
90 | for( ; *st; st++ )
91 | {
92 | char c = *st;
93 | if( mode == 0 )
94 | {
95 | if( c >= 'A' && c <= 'F' )
96 | {
97 | port = c - 'A';
98 | mode = 2;
99 | }
100 | else if( c >= 'a' && c <= 'f' )
101 | {
102 | port = c - 'a';
103 | mode = 2;
104 | }
105 | }
106 | else if( mode == 2 )
107 | {
108 | if( c >= '0' && c <= '9' )
109 | {
110 | pin = 0;
111 | mode = 3;
112 | }
113 | }
114 |
115 | if( mode == 3 )
116 | {
117 | if( c >= '0' && c <= '9' )
118 | {
119 | pin = pin * 10;
120 | pin+= c - '0';
121 | }
122 | else
123 | {
124 | break;
125 | }
126 | }
127 | }
128 |
129 | if( port > 0 && pin > 0 && port <= 6 && pin <= 15)
130 | {
131 | return (port<<4)|pin;
132 | }
133 | else
134 | {
135 | return 0xff;
136 | }
137 | }
138 |
139 |
140 | void ConfigureGPIO( uint8_t gpio, int parameters )
141 | {
142 | GPIO_InitTypeDef GPIO_InitStructure;
143 |
144 | /* Enable the GPIO_LED Clock */
145 | #ifdef STM32F30X
146 | RCC_AHBPeriphClockCmd( 1<<(17+(gpio>>4)), ENABLE);
147 | #elif defined( STM32F40_41xxx )
148 | RCC_AHB1PeriphClockCmd( 1<<((gpio>>4)), ENABLE);
149 | #endif
150 |
151 | if( parameters & DEFAULT_VALUE_FLAG )
152 | {
153 | GPIOOn( gpio );
154 | }
155 | else
156 | {
157 | GPIOOff( gpio );
158 | }
159 |
160 | /* Configure the GPIO_LED pin */
161 | GPIO_InitStructure.GPIO_Pin = 1<<(gpio&0xf);
162 | GPIO_InitStructure.GPIO_Mode = (parameters&INOUT_FLAG)?GPIO_Mode_OUT:GPIO_Mode_IN;
163 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
164 | GPIO_InitStructure.GPIO_PuPd = (parameters&PUPD_FLAG)?( (parameters&PUPD_UP)?GPIO_PuPd_UP:GPIO_PuPd_DOWN ):GPIO_PuPd_NOPULL;
165 |
166 | #ifdef STM32F30X
167 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
168 | #elif defined( STM32F40_41xxx )
169 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
170 | #endif
171 |
172 | GPIO_Init(GPIOOf(gpio), &GPIO_InitStructure);
173 | }
174 |
175 |
--------------------------------------------------------------------------------
/lib/systems.h:
--------------------------------------------------------------------------------
1 | #ifndef _SYSTEMS_H
2 | #define _SYSTEMS_H
3 |
4 | void send_openocd_command(int command, void *message);
5 | void send_text( const char * text );
6 | void _delay_us(uint32_t us);
7 |
8 |
9 | typedef uint8_t gpio;
10 |
11 | gpio GetGPIOFromString( const char * str );
12 |
13 |
14 | #define DEFAULT_VALUE_FLAG 0x00000001
15 | #define DEFAULT_ON 0x00000001
16 | #define DEFAULT_OFF 0x00000000
17 |
18 | #define INOUT_FLAG 0x00000002
19 | #define INOUT_OUT 0x00000002
20 | #define INOUT_IN 0x00000000
21 |
22 | #define PUPD_FLAG 0x0000000C
23 | #define PUPD_NONE 0x00000000
24 | #define PUPD_UP 0x00000004
25 | #define PUPD_DOWN 0x00000008
26 |
27 | void ConfigureGPIO( gpio gpio, int parameters );
28 |
29 |
30 |
31 | #ifdef STM32F30X
32 | #define GPIOOf(x) ((GPIO_TypeDef *) ((((x)>>4)<=6)?(AHB2PERIPH_BASE+0x400*((x)>>4)):0x60000000) )
33 | #elif defined( STM32F40_41xxx )
34 | #define GPIOOf(x) ((GPIO_TypeDef *) ((((x)>>4)<=6)?(AHB1PERIPH_BASE+0x400*((x)>>4)):0x60000000) )
35 | #endif
36 |
37 | #define GPIOPin(x) ((1<<((x)&0x0f)))
38 | #define GPIOLatch(x) GPIOOf(x)->ODR
39 |
40 | #ifdef STM32F30X
41 | #define GPIOOn(x) GPIOOf(x)->BSRR = (1<<((x)&0x0f));
42 | #define GPIOOff(x) GPIOOf(x)->BRR = (1<<((x)&0x0f));
43 | #elif defined( STM32F40_41xxx )
44 | #define GPIOOn(x) GPIOOf(x)->BSRRH = (1<<((x)&0x0f));
45 | #define GPIOOff(x) GPIOOf(x)->BSRRL = (1<<((x)&0x0f));
46 | #endif
47 |
48 |
49 |
50 | #ifdef STM32F30X
51 | //#define LEDPIN 0x18
52 | #define LEDPIN 0x05 //PA05 (From Nucleo board)
53 | #elif defined( STM32F40_41xxx )
54 | #define LEDPIN 0x3f
55 | #endif
56 |
57 | void ConfigureLED();
58 | #define LED_TOGGLE {GPIOOf(LEDPIN)->ODR^=(1<<((LEDPIN)&0x0f));}
59 | #define LED_ON GPIOOn(LEDPIN)
60 | #define LED_OFF GPIOOff(LEDPIN)
61 |
62 |
63 | #endif
64 |
65 |
--------------------------------------------------------------------------------
/main.c:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 | #include
5 | #include
6 | #include
7 |
8 | RCC_ClocksTypeDef RCC_Clocks;
9 |
10 | int main(void)
11 | {
12 | uint32_t i = 0;
13 |
14 | RCC_GetClocksFreq( &RCC_Clocks );
15 |
16 | ConfigureLED(); LED_ON;
17 |
18 | /* SysTick end of count event each 10ms */
19 | // SysTick_Config( RCC_Clocks.HCLK_Frequency / 100);
20 |
21 | // printf( "Operating at %dHz\n", RCC_Clocks.HCLK_Frequency );
22 | while(1)
23 | {
24 | }
25 | }
26 |
27 | void TimingDelay_Decrement()
28 | {
29 | }
30 |
31 |
32 |
--------------------------------------------------------------------------------
/stm32f30x_it.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_it.c
4 | * @author MCD Application Team
5 | * @version V1.1.0
6 | * @date 20-September-2012
7 | * @brief Main Interrupt Service Routines.
8 | * This file provides template for all exceptions handler and
9 | * peripherals interrupt service routine.
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © COPYRIGHT 2012 STMicroelectronics
14 | *
15 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
16 | * You may not use this file except in compliance with the License.
17 | * You may obtain a copy of the License at:
18 | *
19 | * http://www.st.com/software_license_agreement_liberty_v2
20 | *
21 | * Unless required by applicable law or agreed to in writing, software
22 | * distributed under the License is distributed on an "AS IS" BASIS,
23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 | * See the License for the specific language governing permissions and
25 | * limitations under the License.
26 | *
27 | ******************************************************************************
28 | */
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f30x_it.h"
32 |
33 | /** @addtogroup STM32F3-Discovery_Demo
34 | * @{
35 | */
36 |
37 | /* Private typedef -----------------------------------------------------------*/
38 | /* Private define ------------------------------------------------------------*/
39 | /* Private macro -------------------------------------------------------------*/
40 | /* Private variables ---------------------------------------------------------*/
41 | /* Private function prototypes -----------------------------------------------*/
42 | /* Private functions ---------------------------------------------------------*/
43 |
44 | /******************************************************************************/
45 | /* Cortex-M4 Processor Exceptions Handlers */
46 | /******************************************************************************/
47 |
48 | /**
49 | * @brief This function handles NMI exception.
50 | * @param None
51 | * @retval None
52 | */
53 | void NMI_Handler(void)
54 | {
55 | }
56 |
57 | /**
58 | * @brief This function handles Hard Fault exception.
59 | * @param None
60 | * @retval None
61 | */
62 | void HardFault_Handler(void)
63 | {
64 | /* Go to infinite loop when Hard Fault exception occurs */
65 | while (1)
66 | {
67 | }
68 | }
69 |
70 | /**
71 | * @brief This function handles Memory Manage exception.
72 | * @param None
73 | * @retval None
74 | */
75 | void MemManage_Handler(void)
76 | {
77 | /* Go to infinite loop when Memory Manage exception occurs */
78 | while (1)
79 | {
80 | }
81 | }
82 |
83 | /**
84 | * @brief This function handles Bus Fault exception.
85 | * @param None
86 | * @retval None
87 | */
88 | void BusFault_Handler(void)
89 | {
90 | /* Go to infinite loop when Bus Fault exception occurs */
91 | while (1)
92 | {
93 | }
94 | }
95 |
96 | /**
97 | * @brief This function handles Usage Fault exception.
98 | * @param None
99 | * @retval None
100 | */
101 | void UsageFault_Handler(void)
102 | {
103 | /* Go to infinite loop when Usage Fault exception occurs */
104 | while (1)
105 | {
106 | }
107 | }
108 |
109 | /**
110 | * @brief This function handles SVCall exception.
111 | * @param None
112 | * @retval None
113 | */
114 | void SVC_Handler(void)
115 | {
116 | }
117 |
118 | /**
119 | * @brief This function handles Debug Monitor exception.
120 | * @param None
121 | * @retval None
122 | */
123 | void DebugMon_Handler(void)
124 | {
125 | }
126 |
127 | /**
128 | * @brief This function handles PendSVC exception.
129 | * @param None
130 | * @retval None
131 | */
132 | void PendSV_Handler(void)
133 | {
134 | }
135 |
136 | /**
137 | * @brief This function handles SysTick Handler.
138 | * @param None
139 | * @retval None
140 | */
141 | void SysTick_Handler(void)
142 | {
143 | TimingDelay_Decrement();
144 | }
145 |
146 | /******************************************************************************/
147 | /* STM32F30x Peripherals Interrupt Handlers */
148 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
149 | /* available peripheral interrupt handler's name please refer to the startup */
150 | /* file (startup_stm32f30x.s). */
151 | /******************************************************************************/
152 | /**
153 | * @brief This function handles EXTI0_IRQ Handler.
154 | * @param None
155 | * @retval None
156 | */
157 | //void EXTI0_IRQHandler(void)
158 | //{
159 | //}
160 |
161 | /**
162 | * @brief This function handles PPP interrupt request.
163 | * @param None
164 | * @retval None
165 | */
166 | /*void PPP_IRQHandler(void)
167 | {
168 | }*/
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
175 |
176 |
--------------------------------------------------------------------------------
/stm32f30x_it.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_it.h
4 | * @author MCD Application Team
5 | * @version V1.1.0
6 | * @date 20-September-2012
7 | * @brief This file contains the headers of the interrupt handlers.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2012 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F30X_IT_H
30 | #define __STM32F30X_IT_H
31 |
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 |
36 | /* Includes ------------------------------------------------------------------*/
37 | #include "stm32f30x_conf.h"
38 | #include "stm32f30x.h"
39 |
40 | /* Imported functions ------------------------------------------------------- */
41 | void TimingDelay_Decrement();
42 |
43 | /* Exported types ------------------------------------------------------------*/
44 | /* Exported constants --------------------------------------------------------*/
45 | /* Exported macro ------------------------------------------------------------*/
46 | /* Exported functions ------------------------------------------------------- */
47 |
48 | void NMI_Handler(void);
49 | void HardFault_Handler(void);
50 | void MemManage_Handler(void);
51 | void BusFault_Handler(void);
52 | void UsageFault_Handler(void);
53 | void SVC_Handler(void);
54 | void DebugMon_Handler(void);
55 | void PendSV_Handler(void);
56 | void SysTick_Handler(void);
57 | void EXTI0_IRQHandler(void);
58 |
59 | void USB_LP_CAN1_RX0_IRQHandler(void);
60 | void USB_LP_IRQHandler(void);
61 | void USBWakeUp_IRQHandler(void);
62 | void USBWakeUp_RMP_IRQHandler(void);
63 |
64 | #ifdef __cplusplus
65 | }
66 | #endif
67 |
68 | #endif /* __STM32F30X_IT_H */
69 |
70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
71 |
--------------------------------------------------------------------------------
/terminal.cfg:
--------------------------------------------------------------------------------
1 | set TRANSPORT hla_swd
2 |
3 | source [find interface/stlink-v2.cfg]
4 | source [find target/stm32f3x_stlink.cfg]
5 |
6 | #reset_config none separate
7 | #reset_config srst_push_pull
8 | #separate trst_push_pull
9 |
10 | reset_config srst_nogate
11 | init
12 |
13 | #to manually recover, unplug, connect reset hard to ground.
14 | # replug.
15 | # 'reset halt'.
16 | # unplug reset, plug into programmer's reset.
17 |
18 | # flash erase_sector 0 0 100
19 | # flash write_image erase main.bin 0x08000000
20 |
21 |
--------------------------------------------------------------------------------