├── HDLC Protocol FPGA Implementation ├── Modules │ ├── clock divider self │ │ ├── clkdiv.ucf │ │ ├── clkdiv.bit │ │ ├── clkdiv.vhd │ │ └── tb_clkdiv.vhd │ ├── clk flag │ │ ├── clkdiv.bit │ │ ├── clkflag.vhd │ │ └── tb_clkflag.vhd │ ├── piso │ │ ├── new piso │ │ │ └── piso.vhd │ │ ├── piso.vhd │ │ └── tb_piso.vhd │ ├── Shift reg │ │ ├── shifreg.vhd │ │ └── tb_shifreg.vhd │ ├── sipo │ │ ├── sipo.vhd │ │ └── tb_sipo.vhd │ ├── Bit stuffing │ │ └── BITSTFNG.vhd │ ├── flag gen │ │ ├── flagen.vhd │ │ └── tb_flagen.vhd │ ├── Unstuffing │ │ └── unstf.vhd │ ├── Flag abort │ │ ├── tb_flagab.vhd │ │ └── flagab.vhd │ └── Zero Insert │ │ └── zeroo.vhd ├── Xilinx ISE - Component tests │ ├── loc.JPG │ ├── bitgen.JPG │ ├── crcdet.JPG │ ├── crcgen.JPG │ ├── bitremov.JPG │ └── flaggen.JPG └── Main │ ├── clkdiv.vhd │ ├── transmit.vhd │ └── receive.vhd ├── README.md └── LICENSE /HDLC Protocol FPGA Implementation/Modules/clock divider self/clkdiv.ucf: -------------------------------------------------------------------------------- 1 | net clk loc = p122; 2 | net reset loc = p6; 3 | net ckout loc = p2; -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/clk flag/clkdiv.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Modules/clk flag/clkdiv.bit -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/loc.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/loc.JPG -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/clock divider self/clkdiv.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Modules/clock divider self/clkdiv.bit -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/bitgen.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/bitgen.JPG -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/crcdet.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/crcdet.JPG -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/crcgen.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/crcgen.JPG -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/bitremov.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/bitremov.JPG -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/flaggen.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/codeshaa/16-bit-HDLC-using-VHDL/HEAD/HDLC Protocol FPGA Implementation/Xilinx ISE - Component tests/flaggen.JPG -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | HDLC 3 | 4 | HDLC (High-level Data Link Control) is a group of protocols for transmitting synchronous data packets between point to point nodes. 5 | In this controller, data is organized into frames. 6 | HDLC protocol resides with Layer 2 of the OSI model, the data link layer. 7 | It make use of zero insertion/deletion process (bit stuffing) to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. 8 | HDLC controller is designed to permit both synchronous and code transparent data transmission this control information reduces the possibility of errors. 9 | 10 | 16-bit address. 11 | 8 bit data 12 | And 16 bit CRC Check. 13 | 14 | simulation result for final output at the receiver end for 8-bit data16-bit address and 16-bit CRC, with bit stuffing and removal of error in HDLC. 15 | 16 | Use Xilinx ISE design suite to work on the program. 17 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 Sharun John 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/piso/new piso/piso.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17:28:42 11/27/2013 6 | -- Design Name: 7 | -- Module Name: piso - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.all; 22 | 23 | entity piso is 24 | port( 25 | clk : in STD_LOGIC; 26 | reset : in STD_LOGIC; 27 | load : in STD_LOGIC; 28 | din : in STD_LOGIC_VECTOR(3 downto 0); 29 | dout : out STD_LOGIC 30 | ); 31 | end piso; 32 | 33 | 34 | architecture piso_arc of piso is 35 | begin 36 | 37 | process (clk,reset,load,din) is 38 | variable temp : std_logic_vector (din'range); 39 | begin 40 | if (reset='1') then 41 | temp := (others=>'0'); 42 | elsif (load='1') then 43 | temp := din ; 44 | elsif (rising_edge (clk)) then 45 | dout <= temp(3); 46 | temp := temp(2 downto 0) & '0'; 47 | end if; 48 | end process; 49 | 50 | end piso_arc; 51 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/piso/piso.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:14:17 09/20/2013 6 | -- Design Name: 7 | -- Module Name: piso - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity piso is 33 | port(clk,reset:in std_logic; 34 | x:in std_logic_vector(0 to 7); 35 | sout: out std_logic); 36 | end piso; 37 | 38 | architecture Behavioral of piso is 39 | 40 | signal i:integer:=0; 41 | begin 42 | process(clk,reset) 43 | begin 44 | if reset='1' then 45 | sout<='0'; 46 | i<=0; 47 | else 48 | if i<=8 then 49 | sout<=x(i); 50 | i<=i+1; 51 | 52 | 53 | end if; 54 | end if; 55 | end process; 56 | 57 | 58 | end Behavioral; 59 | 60 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Shift reg/shifreg.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12:36:07 11/25/2013 6 | -- Design Name: 7 | -- Module Name: shifreg - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity shifreg is 33 | port(clk,reset,sin: in std_logic; 34 | sout:out std_logic); 35 | end shifreg; 36 | 37 | architecture Behavioral of shifreg is 38 | signal q:std_logic_vector(1 to 8):="00000000"; 39 | begin 40 | process(clk,sin,reset) 41 | begin 42 | if reset='1' then 43 | sout<='0'; 44 | else 45 | 46 | if clk='1' and clk'event then 47 | 48 | q<=sin & q(2 to 8); 49 | end if; 50 | end if; 51 | sout<=q(1); 52 | end process; 53 | 54 | end Behavioral; 55 | 56 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/clock divider self/clkdiv.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 09:34:55 11/27/2013 6 | -- Design Name: 7 | -- Module Name: clkdiv - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_arith.all; 23 | use ieee.std_logic_unsigned.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity 35 | architecture Behavioral of clkdiv is 36 | signal count:integer; 37 | begin 38 | process(clk,reset) 39 | -- variable count:integer; 40 | begin 41 | if reset='0' then 42 | count<=0; 43 | ckout<='1'; 44 | elsif 45 | clk='1' and clk'event then 46 | count<=count+1; 47 | if count=25 then 48 | ckout<=not ckout; 49 | count<=0; 50 | end if; 51 | end if; 52 | end process; 53 | 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/sipo/sipo.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 09:53:34 11/25/2013 6 | -- Design Name: 7 | -- Module Name: sipo - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity sipo is 33 | port(clk,reset:in std_logic; 34 | sin:in std_logic; 35 | pout:inout std_logic_vector(7 downto 0)); 36 | end sipo; 37 | 38 | architecture Behavioral of sipo is 39 | --signal i:std_logic_vector(7 downto 0):="00000000"; 40 | begin 41 | process(clk,reset) 42 | 43 | begin 44 | if reset='1' then 45 | pout<="XXXXXXXX"; 46 | else 47 | if clk='1' and clk'event then 48 | pout<=(sin & pout(7 downto 1)); 49 | 50 | end if; 51 | 52 | end if; 53 | --pout<=i; 54 | 55 | end process; 56 | 57 | end Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/clk flag/clkflag.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17:31:52 11/27/2013 6 | -- Design Name: 7 | -- Module Name: clkflag - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity clkflag is 33 | port(clk,a,reset:in std_logic; 34 | cko:inout std_logic; 35 | y:out std_logic); 36 | end clkflag; 37 | 38 | architecture Behavioral of clkflag is 39 | component clkdiv is 40 | port( clk_in: in std_logic; 41 | reset : in std_logic; 42 | clk_1hz :out std_logic); 43 | 44 | end component; 45 | 46 | component flagen is 47 | port(clk,a:in std_logic; 48 | z:out std_logic); 49 | end component; 50 | 51 | begin 52 | ck: clkdiv port map(clk,reset,cko); 53 | flg: flagen port map(cko,a,y); 54 | 55 | 56 | end Behavioral; 57 | 58 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Main/clkdiv.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12:55:24 01/03/2013 6 | -- Design Name: 7 | -- Module Name: clkdiv - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity clkdiv is 34 | generic (D : natural := 10); 35 | port( clk_in: in std_logic; 36 | reset : in std_logic; 37 | clk_1hz :out std_logic); 38 | 39 | end clkdiv; 40 | 41 | architecture Behavioral of clkdiv is 42 | signal q : std_logic_vector(D-1 downto 0); 43 | begin 44 | process(clk_in,reset) is 45 | begin 46 | if(reset = '1')then 47 | q <= (others => '0'); 48 | elsif(reset = '0')then --rising_edge(clk_in)then 49 | q <= q+1; 50 | end if; 51 | end process; 52 | clk_1hz <= not q(D-1); 53 | 54 | end Behavioral; 55 | 56 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Bit stuffing/BITSTFNG.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:44:09 11/28/2013 6 | -- Design Name: 7 | -- Module Name: BITSTFNG - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity BITSTFNG is 33 | port(a,clk,reset:in std_logic; 34 | z:out std_logic); 35 | 36 | end BITSTFNG; 37 | 38 | architecture Behavioral of BITSTFNG is 39 | type state is(s1,s2,s3,s4,s5); 40 | signal fm:state; 41 | 42 | 43 | begin 44 | process(clk,reset,a) 45 | begin 46 | if reset<='1' then 47 | z<='0'; 48 | else 49 | if clk='1' and clk'event then 50 | case fm is 51 | when s1=> 52 | z<='0'; 53 | if a='1' then 54 | fm<=s2; 55 | else 56 | fm<=s1; 57 | end if; 58 | when s2=> 59 | z<='0'; 60 | if a='1' then 61 | fm<=s3; 62 | else 63 | fm<=s1; 64 | end if; 65 | 66 | when s3=> 67 | z<='0'; 68 | if a='1' then 69 | fm<=s4; 70 | else 71 | fm<=s1; 72 | end if; 73 | 74 | when s4=> 75 | z<='0'; 76 | if a='1' then 77 | fm<=s5; 78 | else 79 | fm<=s1; 80 | end if; 81 | 82 | when s5=> 83 | fm<=s1; 84 | if a='1' then 85 | z<='1'; 86 | else 87 | z<='0'; 88 | end if; 89 | -- when s6=> if det='1' then 90 | -- y<='0'; 91 | -- end if; 92 | -- k<=x; 93 | -- pstate<=s7; 94 | -- 95 | -- 96 | -- when s7=> y<=k; 97 | -- pstate<=s1; 98 | 99 | end case; 100 | end if; 101 | end if; 102 | end process; 103 | 104 | end Behavioral; 105 | 106 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/clock divider self/tb_clkdiv.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 09:42:09 11/27/2013 6 | -- Design Name: 7 | -- Module Name: D:/Students/VLSI/CET/clkdiv/tb_clkdiv.vhd 8 | -- Project Name: clkdiv 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: clkdiv 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_clkdiv IS 36 | END tb_clkdiv; 37 | 38 | ARCHITECTURE behavior OF tb_clkdiv IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT clkdiv 43 | PORT( 44 | clk : IN std_logic; 45 | reset : IN std_logic; 46 | ckout : INOUT std_logic 47 | ); 48 | END COMPONENT; 49 | 50 | 51 | --Inputs 52 | signal clk : std_logic := '0'; 53 | signal reset : std_logic := '0'; 54 | 55 | --BiDirs 56 | signal ckout : std_logic; 57 | 58 | -- Clock period definitions 59 | constant clk_period : time := 0.02 us; 60 | 61 | BEGIN 62 | 63 | -- Instantiate the Unit Under Test (UUT) 64 | uut: clkdiv PORT MAP ( 65 | clk => clk, 66 | reset => reset, 67 | ckout => ckout 68 | ); 69 | 70 | -- Clock process definitions 71 | clk_process :process 72 | begin 73 | clk <= '0'; 74 | wait for clk_period/2; 75 | clk <= '1'; 76 | wait for clk_period/2; 77 | end process; 78 | 79 | 80 | -- Stimulus process 81 | stim_proc: process 82 | begin 83 | reset<='1'; 84 | -- hold reset state for 100 ns. 85 | wait for 100 ns; 86 | 87 | 88 | wait for clk_period*10; 89 | 90 | -- insert stimulus here 91 | 92 | wait; 93 | end process; 94 | 95 | END; 96 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/flag gen/flagen.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:29:32 11/26/2013 6 | -- Design Name: 7 | -- Module Name: flagen - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity flagen is 33 | port(clk,reset:in std_logic; 34 | a:in std_logic; 35 | z:out std_logic); 36 | end flagen; 37 | 38 | architecture Behavioral of flagen is 39 | type state is(s0,s1,s2,s3,s4,s5,s6,s7); 40 | signal flagstate:state; 41 | begin 42 | 43 | process(clk,reset) 44 | begin 45 | if reset='1' then 46 | z<='0'; 47 | else 48 | if clk='1' and clk'event then 49 | case flagstate is 50 | when s0=> z<='0'; 51 | if a='1' then 52 | flagstate<=s1; 53 | end if; 54 | when s1=> z<='1'; 55 | if a='1' then 56 | flagstate<=s2; 57 | else 58 | flagstate<=s0; 59 | end if; 60 | when s2=> z<='1'; 61 | if a='1' then 62 | flagstate<=s3; 63 | else 64 | flagstate<=s0; 65 | end if; 66 | when s3=> z<='1'; 67 | if a='1' then 68 | flagstate<=s4; 69 | else 70 | flagstate<=s0; 71 | end if; 72 | when s4=> z<='1'; 73 | if a='1' then 74 | flagstate<=s5; 75 | else 76 | flagstate<=s0; 77 | end if; 78 | when s5=> z<='1'; 79 | if a='1' then 80 | flagstate<=s6; 81 | else 82 | flagstate<=s0; 83 | end if; 84 | when s6=> z<='0'; 85 | if a='1' then 86 | flagstate<=s7; 87 | else 88 | flagstate<=s0; 89 | end if; 90 | when s7=> z<='0'; 91 | if a='1' then 92 | flagstate<=s0; 93 | 94 | else 95 | flagstate<=s0; 96 | end if; 97 | 98 | end case; 99 | end if; 100 | end if; 101 | end process; 102 | end behavioral; -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Unstuffing/unstf.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 09:58:22 11/30/2013 6 | -- Design Name: 7 | -- Module Name: unstf - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity unstf is 33 | port(clk,reset,data:in std_logic; 34 | det:inout std_logic; 35 | y:out std_logic); 36 | end unstf; 37 | 38 | architecture Behavioral of unstf is 39 | type statetype is(s1,s2,s3,s4,s5,s6); 40 | signal n_state:statetype; 41 | 42 | begin 43 | process(clk,reset,data) 44 | variable k: std_logic; 45 | begin 46 | 47 | if reset='1' then 48 | det<='0'; 49 | y<=data; 50 | 51 | else 52 | if clk'event and clk='1' then 53 | case n_state is 54 | when s1=> 55 | det<='0'; 56 | if data='1' then 57 | n_state<=s2; 58 | y<=data; 59 | else 60 | y<=data; 61 | n_state<=s1; 62 | end if; 63 | 64 | when s2=> 65 | det<='0'; 66 | if data='1' then 67 | y<=data; 68 | n_state<=s3; 69 | else 70 | y<=data; 71 | n_state<=s1; 72 | end if; 73 | 74 | when s3=> 75 | det<='0'; 76 | if data='1' then 77 | y<=data; 78 | n_state<=s4; 79 | else 80 | y<=data; 81 | n_state<=s1; 82 | end if; 83 | 84 | when s4=> 85 | det<='0'; 86 | if data='1' then 87 | y<=data; 88 | n_state<=s5; 89 | else 90 | y<=data; 91 | n_state<=s1; 92 | end if; 93 | 94 | when s5=> 95 | if data='1' then 96 | y<=data; 97 | det<='1'; 98 | n_state<=s6; 99 | else 100 | y<=data; 101 | det<='0'; 102 | n_state<=s1; 103 | end if; 104 | 105 | 106 | when s6=> 107 | if det='1' then 108 | n_state<=s1; 109 | det<='0'; 110 | else 111 | y<=data; 112 | n_state<=s1; 113 | 114 | end if; 115 | end case; 116 | end if; 117 | end if; 118 | end process; 119 | end Behavioral; 120 | 121 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/flag gen/tb_flagen.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:55:15 11/26/2013 6 | -- Design Name: 7 | -- Module Name: D:/Students/VLSI/CET/flagen/tb_flagen.vhd 8 | -- Project Name: flagen 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: flagen 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_flagen IS 36 | END tb_flagen; 37 | 38 | ARCHITECTURE behavior OF tb_flagen IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT flagen 43 | PORT( 44 | clk : IN std_logic; 45 | reset : IN std_logic; 46 | a : IN std_logic; 47 | z : OUT std_logic 48 | ); 49 | END COMPONENT; 50 | 51 | 52 | --Inputs 53 | signal clk : std_logic := '0'; 54 | signal reset : std_logic:= '0'; 55 | signal a : std_logic := '0'; 56 | --Bidirs 57 | 58 | 59 | --Outputs 60 | signal z : std_logic; 61 | 62 | -- Clock period definitions 63 | constant clk_period : time := 100 ns; 64 | 65 | BEGIN 66 | 67 | -- Instantiate the Unit Under Test (UUT) 68 | uut: flagen PORT MAP ( 69 | clk => clk, 70 | reset => reset, 71 | a => a, 72 | z => z 73 | ); 74 | 75 | -- Clock process definitions 76 | clk_process :process 77 | begin 78 | clk <= '0'; 79 | wait for clk_period/2; 80 | clk <= '1'; 81 | wait for clk_period/2; 82 | end process; 83 | 84 | 85 | -- Stimulus process 86 | stim_proc: process 87 | begin 88 | reset<='1'; 89 | a<='0'; 90 | wait for 100 ns; 91 | reset<='0'; 92 | a<='1'; 93 | wait for 800 ns; 94 | a<='0'; 95 | wait for 300 ns; 96 | a<='1'; 97 | wait for 800 ns; 98 | 99 | 100 | -- hold reset state for 100 ns. 101 | 102 | 103 | wait for clk_period*10; 104 | 105 | -- insert stimulus here 106 | 107 | wait; 108 | end process; 109 | 110 | END; 111 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/clk flag/tb_clkflag.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:03:50 11/27/2013 6 | -- Design Name: 7 | -- Module Name: D:/Students/VLSI/CET/clkflag/tb_clkflag.vhd 8 | -- Project Name: clkflag 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: clkflag 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_clkflag IS 36 | END tb_clkflag; 37 | 38 | ARCHITECTURE behavior OF tb_clkflag IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT clkflag 43 | PORT( 44 | clk : IN std_logic; 45 | a : IN std_logic; 46 | reset : IN std_logic; 47 | cko : INOUT std_logic; 48 | y : OUT std_logic 49 | ); 50 | END COMPONENT; 51 | 52 | 53 | --Inputs 54 | signal clk : std_logic := '0'; 55 | signal a : std_logic := '0'; 56 | signal reset : std_logic := '0'; 57 | 58 | --BiDirs 59 | signal cko : std_logic; 60 | 61 | --Outputs 62 | signal y : std_logic; 63 | 64 | -- Clock period definitions 65 | constant clk_period : time := 100 ns; 66 | 67 | BEGIN 68 | 69 | -- Instantiate the Unit Under Test (UUT) 70 | uut: clkflag PORT MAP ( 71 | clk => clk, 72 | a => a, 73 | reset => reset, 74 | cko => cko, 75 | y => y 76 | ); 77 | 78 | -- Clock process definitions 79 | clk_process :process 80 | begin 81 | clk <= '0'; 82 | wait for clk_period/2; 83 | clk <= '1'; 84 | wait for clk_period/2; 85 | end process; 86 | 87 | 88 | -- Stimulus process 89 | stim_proc: process 90 | begin 91 | reset<='1'; 92 | 93 | wait for 2000 ns; 94 | reset<='0'; 95 | a<='1'; 96 | wait for 8000000 us; 97 | 98 | -- hold reset state for 100 ns. 99 | wait for 100 ns; 100 | 101 | wait for clk_period*10; 102 | 103 | -- insert stimulus here 104 | 105 | wait; 106 | end process; 107 | 108 | END; 109 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/piso/tb_piso.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:39:14 09/20/2013 6 | -- Design Name: 7 | -- Module Name: D:/Students/VLSI/CET/piso/tb_piso.vhd 8 | -- Project Name: piso 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: piso 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_piso IS 36 | END tb_piso; 37 | 38 | ARCHITECTURE behavior OF tb_piso IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT piso 43 | PORT( 44 | clk : IN std_logic; 45 | reset : IN std_logic; 46 | load : IN std_logic; 47 | x : IN std_logic_vector(0 to 7); 48 | sout : OUT std_logic 49 | ); 50 | END COMPONENT; 51 | 52 | 53 | --Inputs 54 | signal clk : std_logic := '0'; 55 | signal reset : std_logic := '0'; 56 | signal load : std_logic := '0'; 57 | signal x : std_logic_vector(0 to 7) := (others => '0'); 58 | 59 | --Outputs 60 | signal sout : std_logic; 61 | 62 | -- Clock period definitions 63 | constant clk_period : time := 100 ns; 64 | 65 | BEGIN 66 | 67 | -- Instantiate the Unit Under Test (UUT) 68 | uut: piso PORT MAP ( 69 | clk => clk, 70 | reset => reset, 71 | load => load, 72 | x => x, 73 | sout => sout 74 | ); 75 | 76 | -- Clock process definitions 77 | clk_process :process 78 | begin 79 | clk <= '0'; 80 | wait for clk_period/2; 81 | clk <= '1'; 82 | wait for clk_period/2; 83 | end process; 84 | 85 | 86 | -- Stimulus process 87 | stim_proc: process 88 | begin 89 | x<="10110101"; 90 | reset<='1'; 91 | load<='1'; 92 | -- hold reset state for 100 ns. 93 | wait for 200 ns; 94 | reset<='0'; 95 | load<='0'; 96 | 97 | wait for 200 ns; 98 | reset<='0'; 99 | load<='1'; 100 | 101 | wait for clk_period*10; 102 | 103 | -- insert stimulus here 104 | 105 | wait; 106 | end process; 107 | 108 | END; 109 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Flag abort/tb_flagab.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 23:32:34 11/27/2013 6 | -- Design Name: 7 | -- Module Name: D:/PROJ MAIN/PRO-WORK/flagab/tb_flagab.vhd 8 | -- Project Name: flagab 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: flagab 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_flagab IS 36 | END tb_flagab; 37 | 38 | ARCHITECTURE behavior OF tb_flagab IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT flagab 43 | PORT( 44 | clk : IN std_logic; 45 | reset : IN std_logic; 46 | a : IN std_logic; 47 | z : OUT std_logic; 48 | about:out std_logic; 49 | idlout:out std_logic 50 | ); 51 | END COMPONENT; 52 | 53 | 54 | --Inputs 55 | signal clk : std_logic := '0'; 56 | signal reset : std_logic := '0'; 57 | signal a : std_logic := '0'; 58 | 59 | --Outputs 60 | signal z : std_logic; 61 | signal about:std_logic; 62 | signal idlout:std_logic; 63 | 64 | -- Clock period definitions 65 | constant clk_period : time := 100 ns; 66 | 67 | BEGIN 68 | 69 | -- Instantiate the Unit Under Test (UUT) 70 | uut: flagab PORT MAP ( 71 | clk => clk, 72 | reset => reset, 73 | a => a, 74 | z => z, 75 | about => about, 76 | idlout => idlout 77 | ); 78 | 79 | -- Clock process definitions 80 | clk_process :process 81 | begin 82 | clk <= '0'; 83 | wait for clk_period/2; 84 | clk <= '1'; 85 | wait for clk_period/2; 86 | end process; 87 | 88 | 89 | -- Stimulus process 90 | stim_proc: process 91 | begin 92 | reset<='1'; 93 | a<='1'; 94 | wait for 100 ns; 95 | reset<='0'; 96 | a<='0'; 97 | wait for 100 ns; 98 | a<='1'; 99 | wait for 700 ns; 100 | --a<='1'; 101 | --wait for 500 ns; 102 | --a<='0'; 103 | --wait for 100 ns; 104 | -- a<='1'; 105 | -- wait for 800 ns; 106 | -- a<='0'; 107 | -- wait for 100 ns; 108 | -- a<='1'; 109 | -- wait for 700 ns; 110 | -- hold reset state for 100 ns. 111 | 112 | 113 | wait for clk_period*10; 114 | 115 | -- insert stimulus here 116 | 117 | wait; 118 | end process; 119 | 120 | END; 121 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/sipo/tb_sipo.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 10:03:49 11/25/2013 6 | -- Design Name: 7 | -- Module Name: D:/Students/VLSI/CET/sipo/tb_sipo.vhd 8 | -- Project Name: sipo 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: sipo 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_sipo IS 36 | END tb_sipo; 37 | 38 | ARCHITECTURE behavior OF tb_sipo IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT sipo 43 | PORT( 44 | clk : IN std_logic; 45 | reset : IN std_logic; 46 | 47 | x : IN std_logic; 48 | pout : INOUT std_logic_vector(7 downto 0) 49 | ); 50 | END COMPONENT; 51 | 52 | 53 | --Inputs 54 | signal clk : std_logic := '0'; 55 | signal reset : std_logic := '0'; 56 | 57 | signal x : std_logic := '0'; 58 | 59 | --Outputs 60 | signal pout : std_logic_vector(7 downto 0); 61 | 62 | -- Clock period definitions 63 | constant clk_period : time := 100 ns; 64 | 65 | BEGIN 66 | 67 | -- Instantiate the Unit Under Test (UUT) 68 | uut: sipo PORT MAP ( 69 | clk => clk, 70 | reset => reset, 71 | 72 | x => x, 73 | pout => pout 74 | ); 75 | 76 | -- Clock process definitions 77 | clk_process :process 78 | begin 79 | clk <= '0'; 80 | wait for clk_period/2; 81 | clk <= '1'; 82 | wait for clk_period/2; 83 | end process; 84 | 85 | 86 | -- Stimulus process 87 | stim_proc: process 88 | begin 89 | reset<='1'; 90 | x<='1'; 91 | 92 | wait for 100 ns; 93 | 94 | reset<='0'; 95 | x<='1'; 96 | wait for 100 ns; 97 | 98 | x<='0'; 99 | 100 | wait for 100 ns; 101 | 102 | x<='1'; 103 | 104 | wait for 100 ns; 105 | 106 | x<='0'; 107 | 108 | wait for 100 ns; 109 | 110 | x<='1'; 111 | 112 | wait for 100 ns; 113 | 114 | x<='1'; 115 | 116 | wait for 100 ns; 117 | 118 | x<='0'; 119 | 120 | wait for 100 ns; 121 | 122 | x<='1'; 123 | 124 | wait for 100 ns; 125 | 126 | wait for clk_period*10; 127 | 128 | -- insert stimulus here 129 | 130 | wait; 131 | end process; 132 | 133 | END; 134 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Shift reg/tb_shifreg.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:44:27 11/25/2013 6 | -- Design Name: 7 | -- Module Name: D:/Students/VLSI/CET/shifreg/tb_shifreg.vhd 8 | -- Project Name: shifreg 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: shifreg 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY tb_shifreg IS 36 | END tb_shifreg; 37 | 38 | ARCHITECTURE behavior OF tb_shifreg IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT shifreg 43 | PORT( 44 | clk : IN std_logic; 45 | reset : IN std_logic; 46 | sin : IN std_logic; 47 | sout : OUT std_logic 48 | ); 49 | END COMPONENT; 50 | 51 | 52 | --Inputs 53 | signal clk : std_logic := '0'; 54 | signal reset : std_logic := '0'; 55 | signal sin : std_logic := '0'; 56 | 57 | --Outputs 58 | signal sout : std_logic; 59 | 60 | -- Clock period definitions 61 | constant clk_period : time := 1000 ns; 62 | 63 | BEGIN 64 | 65 | -- Instantiate the Unit Under Test (UUT) 66 | uut: shifreg PORT MAP ( 67 | clk => clk, 68 | reset => reset, 69 | sin => sin, 70 | sout => sout 71 | ); 72 | 73 | -- Clock process definitions 74 | clk_process :process 75 | begin 76 | clk <= '0'; 77 | wait for clk_period/2; 78 | clk <= '1'; 79 | wait for clk_period/2; 80 | end process; 81 | 82 | 83 | -- Stimulus process 84 | stim_proc: process 85 | begin 86 | reset<='1'; 87 | sin<='1'; 88 | -- hold reset state for 100 ns. 89 | wait for 100 ns; 90 | reset<='0'; 91 | sin<='1'; 92 | wait for 100 ns; 93 | 94 | reset<='0'; 95 | sin<='1'; 96 | wait for 100 ns; 97 | 98 | reset<='0'; 99 | sin<='0'; 100 | wait for 100 ns; 101 | 102 | reset<='0'; 103 | sin<='0'; 104 | wait for 100 ns; 105 | 106 | reset<='0'; 107 | sin<='1'; 108 | wait for 100 ns; 109 | 110 | reset<='0'; 111 | sin<='1'; 112 | wait for 100 ns; 113 | 114 | reset<='0'; 115 | sin<='0'; 116 | wait for 100 ns; 117 | 118 | reset<='0'; 119 | sin<='0'; 120 | wait for 100 ns; 121 | 122 | wait for clk_period*10; 123 | 124 | -- insert stimulus here 125 | 126 | wait; 127 | end process; 128 | 129 | END; 130 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Zero Insert/zeroo.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 10:51:33 11/28/2013 6 | -- Design Name: 7 | -- Module Name: zeroin - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity zeroin is 33 | port(clk,reset,data:in std_logic; 34 | det:inout std_logic; 35 | y:out std_logic); 36 | end zeroin; 37 | 38 | architecture Behavioral of zeroin is 39 | type statetype is(s1,s2,s3,s4,s5,s6,s7); 40 | signal n_state:statetype; 41 | 42 | 43 | begin 44 | process(clk,reset,data) 45 | variable k: std_logic; 46 | begin 47 | 48 | if reset='1' then 49 | 50 | det<='0'; 51 | y<=data; 52 | 53 | else 54 | if clk'event and clk='1' then 55 | 56 | 57 | case n_state is 58 | 59 | 60 | when s1=> 61 | det<='0'; 62 | if data='1' then 63 | y<=data; 64 | 65 | n_state<=s2; 66 | 67 | else 68 | y<=data; 69 | 70 | n_state<=s1; 71 | 72 | end if; 73 | 74 | when s2=> 75 | det<='0'; 76 | if data='1' then 77 | 78 | y<=data; 79 | n_state<=s3; 80 | 81 | else 82 | 83 | y<=data; 84 | 85 | n_state<=s1; 86 | 87 | end if; 88 | 89 | when s3=> 90 | det<='0'; 91 | if data='1' then 92 | 93 | y<=data; 94 | 95 | n_state<=s4; 96 | 97 | 98 | else 99 | 100 | y<=data; 101 | 102 | n_state<=s1; 103 | 104 | end if; 105 | 106 | when s4=> 107 | det<='0'; 108 | if data='1' then 109 | 110 | y<=data; 111 | 112 | n_state<=s5; 113 | 114 | else 115 | 116 | y<=data; 117 | 118 | n_state<=s1; 119 | 120 | end if; 121 | 122 | when s5=> 123 | if data='1' then 124 | 125 | y<=data; 126 | det<='1'; 127 | n_state<=s6; 128 | 129 | else 130 | 131 | y<=data; 132 | det<='0'; 133 | n_state<=s1; 134 | 135 | end if; 136 | 137 | when s6=> 138 | 139 | 140 | if det='1' then 141 | 142 | y<='0'; 143 | k:=data; 144 | n_state<=s7; 145 | det<='0'; 146 | else 147 | y<=data; 148 | n_state<=s1; 149 | 150 | end if; 151 | 152 | 153 | 154 | when s7=> 155 | y<=k; 156 | 157 | 158 | n_state<=s2; 159 | 160 | 161 | 162 | end case; 163 | 164 | end if; 165 | end if; 166 | 167 | end process; 168 | 169 | 170 | 171 | 172 | 173 | end Behavioral; 174 | 175 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Modules/Flag abort/flagab.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 22:18:22 11/27/2013 6 | -- Design Name: 7 | -- Module Name: flagab - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity flagab is 33 | port(clk,reset,a:in std_logic; 34 | z,about,idlout:out std_logic); 35 | 36 | end flagab; 37 | 38 | architecture Behavioral of flagab is 39 | type state is(s1,s2,s3,s4,s5,s6,s7,s8); 40 | signal fm,idl,ab:state; 41 | begin 42 | process(clk,reset) 43 | begin 44 | if reset='1' then 45 | z<='0'; 46 | else 47 | if clk='1' and clk'event then 48 | case fm is 49 | when s1=> 50 | z<='0'; 51 | if a='0' then 52 | fm<=s2; 53 | else 54 | fm<=s1; 55 | 56 | end if; 57 | when s2=> 58 | z<='0'; 59 | if a='1' then 60 | fm<=s3; 61 | else 62 | fm<=s1; 63 | end if; 64 | 65 | when s3=> 66 | z<='0'; 67 | if a='1' then 68 | fm<=s4; 69 | else 70 | fm<=s1; 71 | end if; 72 | 73 | when s4=> 74 | z<='0'; 75 | if a='1' then 76 | fm<=s5; 77 | else 78 | fm<=s1; 79 | end if; 80 | 81 | when s5=> 82 | z<='0'; 83 | if a='1' then 84 | fm<=s6; 85 | else 86 | fm<=s1; 87 | end if; 88 | 89 | when s6=> 90 | z<='0'; 91 | if a='1' then 92 | fm<=s7; 93 | else 94 | fm<=s1; 95 | end if; 96 | 97 | when s7=> 98 | z<='0'; 99 | if a='1' then 100 | fm<=s8; 101 | else 102 | fm<=s1; 103 | end if; 104 | 105 | when s8=> 106 | fm<=s1; 107 | if a='0' then 108 | z<='1'; 109 | else 110 | z<='0'; 111 | 112 | end if; 113 | end case; 114 | 115 | case idl is 116 | when s1=> 117 | idlout<='0'; 118 | if a='1' then 119 | idl<=s2; 120 | else 121 | idl<=s1; 122 | end if; 123 | when s2=> 124 | idlout<='0'; 125 | if a='1' then 126 | idl<=s3; 127 | else 128 | idl<=s1; 129 | end if; 130 | 131 | when s3=> 132 | idlout<='0'; 133 | if a='1' then 134 | idl<=s4; 135 | else 136 | idl<=s1; 137 | end if; 138 | 139 | when s4=> 140 | idlout<='0'; 141 | if a='1' then 142 | idl<=s5; 143 | else 144 | idl<=s1; 145 | end if; 146 | 147 | when s5=> 148 | idlout<='0'; 149 | if a='1' then 150 | idl<=s6; 151 | else 152 | idl<=s1; 153 | end if; 154 | 155 | when s6=> 156 | idlout<='0'; 157 | if a='1' then 158 | idl<=s7; 159 | else 160 | idl<=s1; 161 | end if; 162 | 163 | when s7=> 164 | idlout<='0'; 165 | if a='1' then 166 | idl<=s8; 167 | else 168 | idl<=s1; 169 | end if; 170 | 171 | when s8=> 172 | idl<=s1; 173 | if a='0' then 174 | idlout<='0'; 175 | else 176 | idlout<='1'; 177 | end if; 178 | end case; 179 | 180 | case ab is 181 | when s1=> 182 | about<='0'; 183 | if a='0' then 184 | ab<=s2; 185 | else 186 | ab<=s1; 187 | 188 | end if; 189 | when s2=> 190 | about<='0'; 191 | if a='1' then 192 | ab<=s3; 193 | else 194 | ab<=s1; 195 | end if; 196 | 197 | when s3=> 198 | about<='0'; 199 | if a='1' then 200 | ab<=s4; 201 | else 202 | ab<=s1; 203 | end if; 204 | 205 | when s4=> 206 | about<='0'; 207 | if a='1' then 208 | ab<=s5; 209 | else 210 | ab<=s1; 211 | end if; 212 | 213 | when s5=> 214 | about<='0'; 215 | if a='1' then 216 | ab<=s6; 217 | else 218 | ab<=s1; 219 | end if; 220 | 221 | when s6=> 222 | about<='0'; 223 | if a='1' then 224 | ab<=s7; 225 | else 226 | ab<=s1; 227 | end if; 228 | 229 | when s7=> 230 | about<='0'; 231 | if a='1' then 232 | ab<=s8; 233 | else 234 | ab<=s1; 235 | end if; 236 | 237 | when s8=> 238 | ab<=s1; 239 | if a='0' then 240 | about<='0'; 241 | else 242 | about<='1'; 243 | end if; 244 | end case; 245 | 246 | end if; 247 | end if; 248 | end process; 249 | 250 | end Behavioral; 251 | 252 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Main/transmit.vhd: -------------------------------------------------------------------------------- 1 | 2 | 3 | library IEEE; 4 | library work; 5 | use IEEE.std_logic_1164.all; 6 | use IEEE.std_logic_Unsigned.all; 7 | use work.hdlc_package.all; 8 | 9 | entity HDLC_TRANSMIT is 10 | port ( 11 | -- Global Reset 12 | Reset : in std_logic; -- Master reset 13 | 14 | -- HDLC Transmit Serial Interface 15 | TxC : in std_logic; -- Transmit Serial Clock 16 | TxD : out std_logic; -- Transmit Serial Data 17 | 18 | -- HDLC Transmit External Memory Interface 19 | TxInputData_B0 : in std_logic; -- Transmit Data Input Bit 0 20 | TxInputData_B1 : in std_logic; -- Transmit Data Input Bit 1 21 | TxInputData_B2 : in std_logic; -- Transmit Data Input Bit 2 22 | TxInputData_B3 : in std_logic; -- Transmit Data Input Bit 3 23 | TxInputData_B4 : in std_logic; -- Transmit Data Input Bit 4 24 | TxInputData_B5 : in std_logic; -- Transmit Data Input Bit 5 25 | TxInputData_B6 : in std_logic; -- Transmit Data Input Bit 6 26 | TxInputData_B7 : in std_logic; -- Transmit Data Input Bit 7 27 | TxRead_n : out std_logic; -- Transmit Data Read 28 | TxEmpty_n : in std_logic; -- Transmit Data Empty 29 | 30 | TxStart : in std_logic; -- Transmit Start 31 | TxAbort : in std_logic; -- Transmit Abort 32 | 33 | TxEnable : in std_logic -- Transmit Enable 34 | ); 35 | end HDLC_TRANSMIT; 36 | 37 | architecture HDLC_TRANSMIT_a of HDLC_TRANSMIT is 38 | 39 | -- State Machine Type Definition 40 | type F_INSERT_state_Typ is (FI0, FI1, FI2, FI3, FI4, FI5, FI6, FI7, NF); 41 | type Z_STUFF_state_Typ is (ZS0, ZS1, ZS2, ZS3, ZS4, ZS5, Stuff); 42 | 43 | -- F_INSERT Signal Declaration 44 | signal FI_State : F_INSERT_state_Typ; 45 | 46 | -- Z_STUFF Signal Declaration 47 | signal ZS_State : Z_STUFF_state_Typ; 48 | signal ZS_Out : std_logic; 49 | 50 | -- T_BUFFER Signal Declaration 51 | signal T_BUFFER : std_logic_vector(7 downto 0); 52 | 53 | -- T_SHIFT Signal Declaration 54 | signal T_SHIFT : std_logic_vector(7 downto 0); 55 | 56 | -- CRC_GEN Signal Declaration 57 | signal ZS_In : std_logic; 58 | signal CRC_feedback : std_logic; 59 | signal FCS : std_logic_vector(FCS_size-1 downto 0); 60 | 61 | -- A_INSERT Signal Declaration 62 | signal AbortLatch : std_logic; 63 | signal Abort : std_logic; 64 | signal Aborting : std_logic; 65 | 66 | -- T_CONTROL Signal Declaration 67 | signal StartLatch : std_logic; 68 | signal Start : std_logic; 69 | signal StartAck : std_logic; 70 | signal Read_n : std_logic; 71 | signal RstZS : std_logic; 72 | signal Latch : std_logic; 73 | signal NonFlagFields : std_logic; 74 | signal NotLastByte : std_logic; 75 | signal NotLastByteD : std_logic; 76 | signal Load : std_logic; 77 | signal EnCrcGen : std_logic; 78 | signal CRC_CNT : std_logic_vector(2 downto 0); 79 | signal TS_CNT : std_logic_vector(2 downto 0); 80 | 81 | -- TxInputData_int Signal Declaration 82 | signal TxInputData_int : std_logic_vector(7 downto 0); 83 | 84 | begin 85 | 86 | TxInputData_int <= TxInputData_B7 & TxInputData_B6 & 87 | TxInputData_B5 & TxInputData_B4 & 88 | TxInputData_B3 & TxInputData_B2 & 89 | TxInputData_B1 & TxInputData_B0; 90 | 91 | -------------------------------------------------------------------------------- 92 | -- F_INSERT 93 | -------------------------------------------------------------------------------- 94 | 95 | -- F_INSERT State Machine 96 | -- State Type : (FI0, FI1, FI2, FI3, FI4, FI5, FI6, FI7, NF); 97 | F_INSERT_FSM: process(TxC, Reset) 98 | begin 99 | if (Reset='1') then 100 | FI_State <= FI0; 101 | elsif rising_edge(TxC) then 102 | if (TxEnable='1') then 103 | case FI_State is 104 | when FI0 => 105 | FI_State <= FI1; 106 | when FI1 => 107 | FI_State <= FI2; 108 | when FI2 => 109 | FI_State <= FI3; 110 | when FI3 => 111 | FI_State <= FI4; 112 | when FI4 => 113 | FI_State <= FI5; 114 | when FI5 => 115 | FI_State <= FI6; 116 | when FI6 => 117 | FI_State <= FI7; 118 | when FI7 => 119 | if (NonFlagFields='0') then 120 | FI_State <= FI0; 121 | else 122 | FI_State <= NF; 123 | end if; 124 | when NF => 125 | if (NonFlagFields='0') then 126 | FI_State <= FI0; 127 | end if; 128 | when others => 129 | FI_State <= FI0; 130 | end case; 131 | end if; 132 | end if; 133 | end process F_INSERT_FSM; 134 | 135 | -- TxD 136 | TxD_Proc: process (TxC, Reset) 137 | begin 138 | if (Reset='1') then 139 | TxD <= '1'; 140 | elsif rising_edge(TxC) then 141 | if (TxEnable='1') then 142 | case FI_State is 143 | when FI0 => 144 | TxD <= '0'; 145 | when FI7 => 146 | TxD <= '0'; 147 | when NF => 148 | TxD <= ZS_Out or Aborting; 149 | when others => 150 | TxD <= '1'; 151 | end case; 152 | end if; 153 | end if; 154 | end process TxD_Proc; 155 | 156 | -------------------------------------------------------------------------------- 157 | -- Z_STUFF 158 | -------------------------------------------------------------------------------- 159 | 160 | -- Z_STUFF State Machine 161 | -- State Type : (ZS0, ZS1, ZS2, ZS3, ZS4, ZS5, Stuff); 162 | Z_STUFF_FSM: process(TxC, RstZS) 163 | begin 164 | if (RstZS='1') then 165 | ZS_State <= ZS0; 166 | elsif rising_edge(TxC) then 167 | if (TxEnable='1') then 168 | case ZS_State is 169 | when ZS0 => 170 | if (ZS_In='1') then 171 | ZS_State <= ZS1; 172 | end if; 173 | when ZS1 => 174 | if (ZS_In='1') then 175 | ZS_State <= ZS2; 176 | else 177 | ZS_State <= ZS0; 178 | end if; 179 | when ZS2 => 180 | if (ZS_In='1') then 181 | ZS_State <= ZS3; 182 | else 183 | ZS_State <= ZS0; 184 | end if; 185 | when ZS3 => 186 | if (ZS_In='1') then 187 | ZS_State <= ZS4; 188 | else 189 | ZS_State <= ZS0; 190 | end if; 191 | when ZS4 => 192 | if (ZS_In='1') then 193 | ZS_State <= ZS5; 194 | else 195 | ZS_State <= ZS0; 196 | end if; 197 | when ZS5 => 198 | ZS_State <= Stuff; 199 | when Stuff => 200 | if (ZS_In='1') then 201 | ZS_State <= ZS1; 202 | else 203 | ZS_State <= ZS0; 204 | end if; 205 | when others => 206 | ZS_State <= ZS0; 207 | end case; 208 | end if; 209 | end if; 210 | end process Z_STUFF_FSM; 211 | 212 | -- ZS_In 213 | ZS_In <= T_SHIFT(0) when (EnCrcGen='0') else 214 | not FCS(FCS_size-1); 215 | 216 | -- ZS_Out 217 | ZS_Out <= '1' when (ZS_State = ZS1) else 218 | '1' when (ZS_State = ZS2) else 219 | '1' when (ZS_State = ZS3) else 220 | '1' when (ZS_State = ZS4) else 221 | '1' when (ZS_State = ZS5) else 222 | '0'; 223 | 224 | -------------------------------------------------------------------------------- 225 | -- T_BUFFER 226 | -------------------------------------------------------------------------------- 227 | 228 | T_BUFFER_Proc: process (TxC, Reset) 229 | begin 230 | if (Reset='1') then 231 | T_BUFFER <= (others => '0'); 232 | elsif rising_edge(TxC) then 233 | if (TxEnable='1') and (Latch='1') then 234 | T_BUFFER <= TxInputData_int(7 downto 0); 235 | end if; 236 | end if; 237 | end process T_BUFFER_Proc; 238 | 239 | -------------------------------------------------------------------------------- 240 | -- T_SHIFT 241 | -------------------------------------------------------------------------------- 242 | 243 | T_SHIFT_Proc: process (TxC, Reset) 244 | begin 245 | if (Reset='1') then 246 | T_SHIFT <= (others => '0'); 247 | elsif rising_edge(TxC) then 248 | if (TxEnable='1') and (ZS_State/=ZS5) then 249 | if (Load='1') then 250 | T_SHIFT <= T_BUFFER; 251 | else 252 | T_SHIFT <= '0' & T_SHIFT(7 downto 1); 253 | end if; 254 | end if; 255 | end if; 256 | end process T_SHIFT_Proc; 257 | 258 | -------------------------------------------------------------------------------- 259 | -- CRC_GEN 260 | -------------------------------------------------------------------------------- 261 | 262 | -- CRC generation 263 | -- 264 | CRC_feedback <= (FCS(FCS_size-1) xor T_SHIFT(0)) and not EnCrcGen; 265 | 266 | CRC_Proc: process (TxC, RstZS) 267 | begin 268 | if (RstZS='1') then 269 | FCS <= (others => '1'); 270 | elsif rising_edge(TxC) then 271 | if (TxEnable='1') and (ZS_State/=ZS5) then 272 | for i in FCS_size-1 downto 1 loop 273 | if (CRC_Polynomial(i) = '1') then 274 | FCS(i) <= FCS(i-1) xor CRC_feedback; 275 | else 276 | FCS(i) <= FCS(i-1); 277 | end if; 278 | end loop; 279 | FCS(0) <= CRC_feedback; 280 | end if; 281 | end if; 282 | end process CRC_Proc; 283 | 284 | -------------------------------------------------------------------------------- 285 | -- A_INSERT 286 | -------------------------------------------------------------------------------- 287 | 288 | -- AbortLatch 289 | AbortLatch_Proc: process (TxC, Reset) 290 | begin 291 | if (Reset='1') then 292 | AbortLatch <= '0'; 293 | elsif rising_edge(TxC) then 294 | if (Abort='1') then 295 | AbortLatch <= '0'; 296 | elsif (TxAbort='1') then 297 | AbortLatch <= '1'; 298 | end if; 299 | end if; 300 | end process AbortLatch_Proc; 301 | 302 | -- Abort 303 | Abort_Proc: process (TxC, Reset) 304 | begin 305 | if (Reset='1') then 306 | Abort <= '0'; 307 | elsif rising_edge(TxC) then 308 | if (TxEnable='1') then 309 | Abort <= AbortLatch; 310 | end if; 311 | end if; 312 | end process Abort_Proc; 313 | 314 | -- Aborting 315 | Aborting_Proc: process (TxC, Reset) 316 | begin 317 | if (Reset='1') then 318 | Aborting <= '0'; 319 | elsif rising_edge(TxC) then 320 | if (TxEnable='1') then 321 | if (NonFlagFields='0') then 322 | Aborting <= '0'; 323 | elsif (Abort='1') then 324 | Aborting <= '1'; 325 | end if; 326 | end if; 327 | end if; 328 | end process Aborting_Proc; 329 | 330 | -------------------------------------------------------------------------------- 331 | -- T_CONTROL 332 | -------------------------------------------------------------------------------- 333 | 334 | -- StartLatch 335 | StartLatch_Proc: process (TxC, Reset) 336 | begin 337 | if (Reset='1') then 338 | StartLatch <= '0'; 339 | elsif rising_edge(TxC) then 340 | if (Start='1') or (NonFlagFields='1') then 341 | StartLatch <= '0'; 342 | elsif (TxStart='1') then 343 | StartLatch <= '1'; 344 | end if; 345 | end if; 346 | end process StartLatch_Proc; 347 | 348 | -- Start 349 | Start_Proc: process (TxC, Reset) 350 | begin 351 | if (Reset='1') then 352 | Start <= '0'; 353 | elsif rising_edge(TxC) then 354 | if (TxEnable='1') then 355 | Start <= StartLatch; 356 | end if; 357 | end if; 358 | end process Start_Proc; 359 | 360 | -- StartAck 361 | StartAck_Proc: process (TxC, Reset) 362 | begin 363 | if (Reset='1') then 364 | StartAck <= '0'; 365 | elsif rising_edge(TxC) then 366 | if (TxEnable='1') then 367 | if (NonFlagFields='1') then 368 | StartAck <= '0'; 369 | elsif (Start='1') and (TxEmpty_n='1') then 370 | StartAck <= '1'; 371 | end if; 372 | end if; 373 | end if; 374 | end process StartAck_Proc; 375 | 376 | -- Read_n 377 | Read_n_Proc: process (TxC, Reset) 378 | begin 379 | if (Reset='1') then 380 | Read_n <= '1'; 381 | elsif rising_edge(TxC) then 382 | if (TxEnable='1') then 383 | if (StartAck='1') and (FI_State=FI3) then 384 | Read_n <= '0'; 385 | elsif (ZS_State=ZS5) then 386 | Read_n <= '1'; 387 | elsif (TS_CNT="101") and (NotLastByte='1') then 388 | Read_n <= '0'; 389 | elsif (TS_CNT="101") and (NotLastByteD='1') then 390 | Read_n <= '0'; 391 | else 392 | Read_n <= '1'; 393 | end if; 394 | end if; 395 | end if; 396 | end process Read_n_Proc; 397 | 398 | -- TxRead_n 399 | TxRead_n_Proc: process (TxC, Reset) 400 | begin 401 | if (Reset='1') then 402 | TxRead_n <= '1'; 403 | elsif rising_edge(TxC) then 404 | if (TxEnable='0') then 405 | TxRead_n <= '1'; 406 | elsif (StartAck='1') and (FI_State=FI3) then 407 | TxRead_n <= '0'; 408 | elsif (ZS_State=ZS5) then 409 | TxRead_n <= '1'; 410 | elsif (TS_CNT="101") and (NotLastByte='1') then 411 | TxRead_n <= '0'; 412 | elsif (TS_CNT="101") and (NotLastByteD='1') then 413 | TxRead_n <= '0'; 414 | else 415 | TxRead_n <= '1'; 416 | end if; 417 | end if; 418 | end process TxRead_n_Proc; 419 | 420 | -- RstZS 421 | RstZS_Proc: process (TxC, Reset) 422 | begin 423 | if (Reset='1') then 424 | RstZS <= '1'; 425 | elsif rising_edge(TxC) then 426 | if (TxEnable='1') then 427 | RstZS <= not NonFlagFields; 428 | end if; 429 | end if; 430 | end process RstZS_Proc; 431 | 432 | -- Latch 433 | Latch_Proc: process (TxC, Reset) 434 | begin 435 | if (Reset='1') then 436 | Latch <= '0'; 437 | elsif rising_edge(TxC) then 438 | if (TxEnable='1') then 439 | Latch <= not Read_n; 440 | end if; 441 | end if; 442 | end process Latch_Proc; 443 | 444 | -- CRC_CNT 445 | CRC_CNT_Proc: process (TxC, Reset) 446 | begin 447 | if (Reset='1') then 448 | CRC_CNT <= (others => '0'); 449 | elsif rising_edge(TxC) then 450 | if (TxEnable='1') and (ZS_State/=ZS5) then 451 | if (EnCrcGen='0') then 452 | CRC_CNT <= (others => '0'); 453 | elsif (TS_CNT="111") then 454 | CRC_CNT <= CRC_CNT + 1; 455 | end if; 456 | end if; 457 | end if; 458 | end process CRC_CNT_Proc; 459 | 460 | -- NonFlagFields 461 | NonFlagFields_Proc: process (TxC, Reset) 462 | begin 463 | if (Reset='1') then 464 | NonFlagFields <= '0'; 465 | elsif rising_edge(TxC) then 466 | if (TxEnable='1') and (ZS_State/=ZS5) then 467 | if (Aborting='1') and (TS_CNT="111") then 468 | NonFlagFields <= '0'; 469 | elsif (FCS_size=16) and (CRC_CNT(1)='1') then 470 | NonFlagFields <= '0'; 471 | elsif (FCS_size=32) and (CRC_CNT(2)='1') then 472 | NonFlagFields <= '0'; 473 | elsif (Latch='1') then 474 | NonFlagFields <= '1'; 475 | end if; 476 | end if; 477 | end if; 478 | end process NonFlagFields_Proc; 479 | 480 | -- NotLastByte 481 | NotLastByte_Proc: process (TxC, FI_State) 482 | begin 483 | if (FI_State=FI0) then 484 | NotLastByte <= '1'; 485 | elsif rising_edge(TxC) then 486 | if (TxEnable='1') and (Latch='1') then 487 | NotLastByte <= TxEmpty_n; 488 | end if; 489 | end if; 490 | end process NotLastByte_Proc; 491 | 492 | -- NotLastByteD 493 | NotLastByteD_Proc: process (TxC, Reset) 494 | begin 495 | if (Reset='1') then 496 | NotLastByteD <= '1'; 497 | elsif rising_edge(TxC) then 498 | if (TxEnable='1') and (ZS_State/=ZS5) and (Load='1') then 499 | NotLastByteD <= NotLastByte; 500 | end if; 501 | end if; 502 | end process NotLastByteD_Proc; 503 | 504 | -- Load 505 | Load <= '0' when (NotLastByte = '0') and (NotLastByteD = '0') else 506 | '0' when (TS_CNT /= "000") else 507 | '1'; 508 | 509 | -- TS_CNT 510 | TS_CNT_Proc: process (TxC, Reset) 511 | begin 512 | if (Reset='1') then 513 | TS_CNT <= (others => '0'); 514 | elsif rising_edge(TxC) then 515 | if (TxEnable='1') then 516 | if (Abort='1') or (NonFlagFields='0') then 517 | TS_CNT <= (others => '0'); 518 | elsif (Aborting='1') or (ZS_State/=ZS5) then 519 | TS_CNT <= TS_CNT + 1; 520 | end if; 521 | end if; 522 | end if; 523 | end process TS_CNT_Proc; 524 | 525 | -- EnCrcGen 526 | EnCrcGen_Proc: process (TxC, Reset) 527 | begin 528 | if (Reset='1') then 529 | EnCrcGen <= '0'; 530 | elsif rising_edge(TxC) then 531 | if (TxEnable='1') and (ZS_State/=ZS5) then 532 | if (FI_State=FI7) or (Aborting='1') then 533 | EnCrcGen <= '0'; 534 | elsif (NonFlagFields='1') and (NotLastByte='0') and (NotLastByteD='0') 535 | and (TS_CNT="000") then 536 | EnCrcGen <= '1'; 537 | end if; 538 | end if; 539 | end if; 540 | end process EnCrcGen_Proc; 541 | 542 | end HDLC_TRANSMIT_a; 543 | 544 | -------------------------------------------------------------------------------- /HDLC Protocol FPGA Implementation/Main/receive.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | ---------------------------------Receive Module------------------------------------------ 3 | ----------------------------------------------------------------------------------------- 4 | 5 | library IEEE; 6 | library work; 7 | use IEEE.std_logic_1164.all; 8 | use IEEE.std_logic_Unsigned.all; 9 | use work.hdlc_package.all; 10 | 11 | entity HDLC_RECEIVE is 12 | port ( 13 | -- Global Reset 14 | Reset : in std_logic; -- Master reset 15 | 16 | -- HDLC Receive Serial Interface 17 | RxC : in std_logic; -- Receive Serial Clock 18 | RxD : in std_logic; -- Receive Serial Data 19 | 20 | -- HDLC Receive External Memory Interface 21 | RxOutputData_B0 : out std_logic; -- Receive Data Output Bit 0 22 | RxOutputData_B1 : out std_logic; -- Receive Data Output Bit 1 23 | RxOutputData_B2 : out std_logic; -- Receive Data Output Bit 2 24 | RxOutputData_B3 : out std_logic; -- Receive Data Output Bit 3 25 | RxOutputData_B4 : out std_logic; -- Receive Data Output Bit 4 26 | RxOutputData_B5 : out std_logic; -- Receive Data Output Bit 5 27 | RxOutputData_B6 : out std_logic; -- Receive Data Output Bit 6 28 | RxOutputData_B7 : out std_logic; -- Receive Data Output Bit 7 29 | RxDataWrite_n : out std_logic; -- Receive Data Valid 30 | RxStatusWrite_n : out std_logic; -- Receive Status Valid 31 | 32 | RxEnable : in std_logic -- Receive Enable 33 | ); 34 | end HDLC_RECEIVE; 35 | 36 | architecture HDLC_RECEIVE_a of HDLC_RECEIVE is 37 | 38 | -- Function CRC_Remainder 39 | function CRC_Remainder(numBits: in integer) return std_logic_vector is 40 | variable R : std_logic_vector(numBits-1 downto 0); 41 | variable feedback : std_logic; 42 | begin 43 | R := (others => '1'); 44 | for i in 0 to numBits-1 loop 45 | feedback := R(numBits-1); 46 | for j in numBits-1 downto 1 loop 47 | if (CRC_Polynomial(j) = '1') then 48 | R(j) := R(j-1) xor feedback; 49 | else 50 | R(j) := R(j-1); 51 | end if; 52 | end loop; 53 | R(0) := feedback; 54 | end loop; 55 | return R; 56 | end function CRC_Remainder; 57 | 58 | -- State Machine Type Definition 59 | type F_DETECT_state_Typ is (FD0, FD1, FD2, FD3, FD4, FD5, FD6, Flag, Idle); 60 | type Z_UNSTUFF_state_Typ is (ZU0, ZU1, ZU2, ZU3, ZU4, ZU5, Unstuff); 61 | 62 | -- CRC_CHK Signal Declaration 63 | signal CRC_feedback : std_logic; 64 | signal FCS : std_logic_vector(FCS_size-1 downto 0); 65 | signal CRC_err : std_logic; 66 | --HD 230410 add sample signal 67 | signal CRC_err_sample : std_logic; 68 | 69 | -- F_DETECT Signal Declaration 70 | signal F_State : F_DETECT_state_Typ; 71 | signal FDT : std_logic; 72 | signal OctetDetected : std_logic; 73 | signal OD_CNT : std_logic_vector(3 downto 0); 74 | signal RstStatus : std_logic; 75 | 76 | -- Z_UNSTUFF Signal Declaration 77 | signal Z_State : Z_UNSTUFF_state_Typ; 78 | signal EnShift : std_logic; 79 | 80 | -- A_DETECT Signal Declaration 81 | signal Abort : std_logic; 82 | --HD 230410 add sample signal 83 | signal Abort_sample : std_logic; 84 | 85 | -- BIT_CNT Signal Declaration 86 | signal BIT_CNT : std_logic_vector(2 downto 0); 87 | signal Octet_err : std_logic; 88 | --HD 230410 add sample signal 89 | signal Octet_err_sample : std_logic; 90 | 91 | 92 | -- R_BUFFER Signal Declaration 93 | signal R_BUFFER : std_logic_vector(7 downto 0); 94 | 95 | -- R_SHIFT Signal Declaration 96 | signal R_SHIFT : std_logic_vector(7 downto 0); 97 | 98 | -- R_CONTROL Signal Declaration 99 | signal DataValid : std_logic; 100 | signal StatusValid : std_logic_vector(6 downto 0); 101 | signal OctetDetectedD : std_logic; 102 | 103 | -- RxOutputData_int Signal Declaration 104 | signal RxOutputData_int : std_logic_vector(7 downto 0); 105 | 106 | -- Attributes for ispMACH5000VG to get higher performance 107 | -- These can be removed when the UART design is targeted to other devices. 108 | -- ATTRIBUTE SYN_KEEP : integer; 109 | -- ATTRIBUTE SYN_KEEP OF BIT_CNT : SIGNAL IS 1; 110 | -- ATTRIBUTE OPT : string; 111 | -- ATTRIBUTE OPT OF BIT_CNT : SIGNAL IS "KEEP"; 112 | 113 | begin 114 | 115 | RxOutputData_B0 <= RxOutputData_int(0); 116 | RxOutputData_B1 <= RxOutputData_int(1); 117 | RxOutputData_B2 <= RxOutputData_int(2); 118 | RxOutputData_B3 <= RxOutputData_int(3); 119 | RxOutputData_B4 <= RxOutputData_int(4); 120 | RxOutputData_B5 <= RxOutputData_int(5); 121 | RxOutputData_B6 <= RxOutputData_int(6); 122 | RxOutputData_B7 <= RxOutputData_int(7); 123 | 124 | -------------------------------------------------------------------------------- 125 | -- F_DETECT 126 | -------------------------------------------------------------------------------- 127 | 128 | -- F_DETECT State Machine 129 | -- State Type : (FD0, FD1, FD2, FD3, FD4, FD5, FD6, Flag, Idle); 130 | F_DETECT_FSM: process(RxC, Reset) 131 | begin 132 | if (Reset='1') then 133 | F_State <= FD0; 134 | elsif rising_edge(RxC) then 135 | if (RxEnable='1') then 136 | case F_State is 137 | when FD0 => 138 | if (RxD='1') then 139 | F_State <= FD1; 140 | end if; 141 | when FD1 => 142 | if (RxD='1') then 143 | F_State <= FD2; 144 | else 145 | F_State <= FD0; 146 | end if; 147 | when FD2 => 148 | if (RxD='1') then 149 | F_State <= FD3; 150 | else 151 | F_State <= FD0; 152 | end if; 153 | when FD3 => 154 | if (RxD='1') then 155 | F_State <= FD4; 156 | else 157 | F_State <= FD0; 158 | end if; 159 | when FD4 => 160 | if (RxD='1') then 161 | F_State <= FD5; 162 | else 163 | F_State <= FD0; 164 | end if; 165 | when FD5 => 166 | if (RxD='1') then 167 | F_State <= FD6; 168 | else 169 | F_State <= FD0; 170 | end if; 171 | when FD6 => 172 | if (RxD='1') then 173 | F_State <= Idle; 174 | else 175 | F_State <= Flag; 176 | end if; 177 | when Flag => 178 | if (RxD='1') then 179 | F_State <= FD1; 180 | else 181 | F_State <= FD0; 182 | end if; 183 | when Idle => 184 | if (RxD='0') then 185 | F_State <= FD0; 186 | end if; 187 | when others => 188 | F_State <= FD0; 189 | end case; 190 | end if; 191 | end if; 192 | end process F_DETECT_FSM; 193 | 194 | -- FDT : will be '1' when Flag is detected 195 | -- : will be '0' when the first Octet is received 196 | FDT_Proc: process (RxC, Reset) 197 | begin 198 | if (Reset='1') then 199 | FDT <= '0'; 200 | elsif rising_edge(RxC) then 201 | if (RxEnable='1') then 202 | if (OctetDetected='1') then 203 | FDT <= '0'; 204 | elsif (F_State=FD6) and (RxD='1') then 205 | FDT <= '0'; 206 | elsif (F_State=Flag) then 207 | FDT <= '1'; 208 | end if; 209 | end if; 210 | end if; 211 | end process FDT_Proc; 212 | 213 | -- OctetDetected : will be '1' when the first Octet is received 214 | -- : will be '0' when six consecutive 1's are received 215 | OctetDetected <= OD_CNT(3); 216 | 217 | OD_CNT_Proc: process (RxC, Reset) 218 | begin 219 | if (Reset='1') then 220 | OD_CNT <= (others => '0'); 221 | elsif rising_edge(RxC) then 222 | if (RxEnable='1') then 223 | if (F_State=FD6) then 224 | OD_CNT <= (others => '0'); 225 | elsif (F_State=Flag) or (FDT='1') then 226 | OD_CNT <= OD_CNT + 1; 227 | end if; 228 | end if; 229 | end if; 230 | end process OD_CNT_Proc; 231 | 232 | -- RstStatus : will be '1' one clock before OctetDetected turnes high 233 | -- : used to reset "Abort" and initialize "FCS" 234 | RstStatus <= '1' when (Reset='1') else 235 | '1' when (OD_CNT=B"0111") and (FDT='1') and (F_State/=FD6) else 236 | '0'; 237 | 238 | -------------------------------------------------------------------------------- 239 | -- Z_UNSTUFF 240 | -------------------------------------------------------------------------------- 241 | 242 | -- Z_UNSTUFF State Machine 243 | -- State Type : (ZU0, ZU1, ZU2, ZU3, ZU4, ZU5, Unstuff); 244 | Z_UNSTUFF_FSM: process(RxC, OctetDetected) 245 | begin 246 | if (OctetDetected='0') then 247 | Z_State <= ZU0; 248 | elsif rising_edge(RxC) then 249 | if (RxEnable='1') then 250 | case Z_State is 251 | when ZU0 => 252 | if (R_BUFFER(0)='1') then 253 | Z_State <= ZU1; 254 | end if; 255 | when ZU1 => 256 | if (R_BUFFER(0)='1') then 257 | Z_State <= ZU2; 258 | else 259 | Z_State <= ZU0; 260 | end if; 261 | when ZU2 => 262 | if (R_BUFFER(0)='1') then 263 | Z_State <= ZU3; 264 | else 265 | Z_State <= ZU0; 266 | end if; 267 | when ZU3 => 268 | if (R_BUFFER(0)='1') then 269 | Z_State <= ZU4; 270 | else 271 | Z_State <= ZU0; 272 | end if; 273 | when ZU4 => 274 | if (R_BUFFER(0)='1') then 275 | Z_State <= ZU5; 276 | else 277 | Z_State <= ZU0; 278 | end if; 279 | when ZU5 => 280 | if (R_BUFFER(0)='1') then 281 | Z_State <= ZU0; 282 | else 283 | Z_State <= Unstuff; 284 | end if; 285 | when Unstuff => 286 | if (R_BUFFER(0)='1') then 287 | Z_State <= ZU1; 288 | else 289 | Z_State <= ZU0; 290 | end if; 291 | when others => 292 | Z_State <= ZU0; 293 | end case; 294 | end if; 295 | end if; 296 | end process Z_UNSTUFF_FSM; 297 | 298 | -- EnShift : will be '1' during the (data + FCS) transition period 299 | -- except the zero unstuffing clock 300 | EnShift <= '0' when (Z_State = ZU5) and (R_BUFFER(0) = '0') else 301 | OctetDetected; 302 | 303 | -------------------------------------------------------------------------------- 304 | -- A_DETECT 305 | -------------------------------------------------------------------------------- 306 | 307 | -- Abort : will be '1' when seven or more consecutive 1's are received 308 | -- : will be '0' when Flag is detected 309 | Abort_Proc: process (RxC, RstStatus) 310 | begin 311 | if (RstStatus='1') then 312 | Abort <= '0'; 313 | elsif rising_edge(RxC) then 314 | if (RxEnable='1') then 315 | if (F_State=Flag) then 316 | Abort <= '0'; 317 | elsif (F_State=FD6) then 318 | Abort <= OctetDetected and RxD; 319 | end if; 320 | end if; 321 | end if; 322 | end process Abort_Proc; 323 | 324 | -------------------------------------------------------------------------------- 325 | -- BIT_CNT 326 | -------------------------------------------------------------------------------- 327 | 328 | -- Octet_err : will be '1' when receiving a non-integer number of Octets 329 | -- : will be '0' when Flag is detected 330 | Octet_err <= BIT_CNT(0) or BIT_CNT(1) or BIT_CNT(2); 331 | 332 | BIT_CNT_Proc: process (RxC, Reset) 333 | begin 334 | if (Reset='1') then 335 | BIT_CNT <= (others => '0'); 336 | elsif rising_edge(RxC) then 337 | if (RxEnable='1') then 338 | if (F_State=Flag) or (Abort='1') then 339 | BIT_CNT <= (others => '0'); 340 | elsif (EnShift='1') then 341 | BIT_CNT <= BIT_CNT + 1; 342 | end if; 343 | end if; 344 | -- if (F_State=Flag) or (Abort='1') then 345 | -- BIT_CNT <= (others => '0'); 346 | -- elsif (RxEnable='1') and (EnShift='1') then 347 | -- BIT_CNT <= BIT_CNT + 1; 348 | -- end if; 349 | end if; 350 | end process BIT_CNT_Proc; 351 | 352 | -------------------------------------------------------------------------------- 353 | -- CRC_CHK 354 | -------------------------------------------------------------------------------- 355 | 356 | -- CRC checking 357 | -- 358 | CRC_feedback <= FCS(FCS_size-1) xor R_BUFFER(0); 359 | 360 | CRC_Proc: process (RxC, RstStatus) 361 | begin 362 | if (RstStatus='1') then 363 | FCS <= (others => '1'); 364 | elsif rising_edge(RxC) then 365 | if (RxEnable='1') and (EnShift='1') then 366 | for i in FCS_size-1 downto 1 loop 367 | if (CRC_Polynomial(i) = '1') then 368 | FCS(i) <= FCS(i-1) xor CRC_feedback; 369 | else 370 | FCS(i) <= FCS(i-1); 371 | end if; 372 | end loop; 373 | FCS(0) <= CRC_feedback; 374 | end if; 375 | end if; 376 | end process CRC_Proc; 377 | 378 | -- CRC_err 379 | CRC_err_Proc: process (RxC, Reset) 380 | begin 381 | if (Reset='1') then 382 | CRC_err <= '0'; 383 | elsif rising_edge(RxC) then 384 | if (RxEnable='1') then 385 | if (FCS = CRC_Remainder(FCS_size)) then 386 | CRC_err <= '0'; 387 | else 388 | CRC_err <= '1'; 389 | end if; 390 | end if; 391 | end if; 392 | end process CRC_err_Proc; 393 | 394 | -------------------------------------------------------------------------------- 395 | -- R_BUFFER 396 | -------------------------------------------------------------------------------- 397 | 398 | R_BUFFER_Proc: process (RxC, Reset) 399 | begin 400 | if (Reset='1') then 401 | R_BUFFER <= (others => '0'); 402 | elsif rising_edge(RxC) then 403 | if (RxEnable='1') then 404 | R_BUFFER <= RxD & R_BUFFER(7 downto 1); 405 | end if; 406 | end if; 407 | end process R_BUFFER_Proc; 408 | 409 | -------------------------------------------------------------------------------- 410 | -- R_SHIFT 411 | -------------------------------------------------------------------------------- 412 | 413 | R_SHIFT_Proc: process (RxC, Reset) 414 | begin 415 | if (Reset='1') then 416 | R_SHIFT <= (others => '0'); 417 | elsif rising_edge(RxC) then 418 | if (RxEnable='1') and (EnShift='1') then 419 | R_SHIFT <= R_BUFFER(0) & R_SHIFT(7 downto 1); 420 | end if; 421 | end if; 422 | end process R_SHIFT_Proc; 423 | 424 | -------------------------------------------------------------------------------- 425 | -- R_CONTROL 426 | -------------------------------------------------------------------------------- 427 | 428 | -- DataValid 429 | DataValid_Proc: process (RxC, Reset) 430 | begin 431 | if (Reset='1') then 432 | DataValid <= '0'; 433 | elsif rising_edge(RxC) then 434 | if (RxEnable='1') then 435 | if (Z_State = ZU5) and (R_BUFFER(0) = '0') then 436 | DataValid <= '0'; 437 | elsif (BIT_CNT="111") then 438 | DataValid <= '1'; 439 | else 440 | DataValid <= '0'; 441 | end if; 442 | end if; 443 | end if; 444 | end process DataValid_Proc; 445 | 446 | -- RxDataWrite_n 447 | RxDataWrite_n_Proc: process (RxC, Reset) 448 | begin 449 | if (Reset='1') then 450 | RxDataWrite_n <= '1'; 451 | elsif rising_edge(RxC) then 452 | RxDataWrite_n <= not (RxEnable and DataValid and not Abort); 453 | end if; 454 | end process RxDataWrite_n_Proc; 455 | 456 | -- OctetDetectedD 457 | OctetDetectedD_Proc: process (RxC, Reset) 458 | begin 459 | if (Reset='1') then 460 | OctetDetectedD <= '0'; 461 | elsif rising_edge(RxC) then 462 | if (RxEnable='1') then 463 | OctetDetectedD <= OctetDetected; 464 | end if; 465 | end if; 466 | end process OctetDetectedD_Proc; 467 | 468 | -- StatusValid 469 | StatusValid_Proc: process (RxC, Reset) 470 | begin 471 | if (Reset='1') then 472 | StatusValid <= (others => '0'); 473 | elsif rising_edge(RxC) then 474 | if (RxEnable='1') then 475 | StatusValid(0) <= OctetDetectedD and not OctetDetected; 476 | for i in 1 to 6 loop 477 | StatusValid(i) <= StatusValid(i-1); 478 | end loop; 479 | end if; 480 | end if; 481 | end process StatusValid_Proc; 482 | 483 | -- RxStatusWrite_n 484 | RxStatusWrite_n_Proc: process (RxC, Reset) 485 | begin 486 | if (Reset='1') then 487 | RxStatusWrite_n <= '1'; 488 | elsif rising_edge(RxC) then 489 | RxStatusWrite_n <= not (RxEnable and StatusValid(6)); 490 | end if; 491 | end process RxStatusWrite_n_Proc; 492 | 493 | -------------------------------------------------------------------------------- 494 | -- R_DATA 495 | -------------------------------------------------------------------------------- 496 | 497 | -- Added new process RXOUTPUTSAMPLE_PROC 498 | --Since the output of the Abort, Octet_err and CRC_err is delayed by 7 clock cycles 499 | --we need to sample the values at the right point. 500 | 501 | RxOutputsample_Proc: process (RxC, Reset) 502 | begin 503 | if (Reset='1') then 504 | Abort_sample <= '0'; 505 | Octet_err_sample <='0'; 506 | CRC_err_sample <= '0'; 507 | elsif rising_edge(RxC) then 508 | if (RxEnable='1') then 509 | if (Statusvalid(0)='1') then 510 | Abort_sample <= Abort; 511 | Octet_err_sample <=Octet_err; 512 | CRC_err_sample <= CRC_err; 513 | 514 | else 515 | Abort_sample <= Abort_sample; 516 | Octet_err_sample <=Octet_err_sample; 517 | CRC_err_sample <= CRC_err_sample; 518 | end if; 519 | end if; 520 | end if; 521 | end process RxOutputsample_Proc; 522 | 523 | 524 | -- Modified RXOutputData_proc to use the sample Error signals 525 | RxOutputData_Proc: process (RxC, Reset) 526 | begin 527 | if (Reset='1') then 528 | RxOutputData_int <= (others => '0'); 529 | elsif rising_edge(RxC) then 530 | if (RxEnable='1') then 531 | if (DataValid='1') then 532 | RxOutputData_int <= R_SHIFT; 533 | elsif (StatusValid(6)='1') then 534 | --HD RxOutputData_int <= "11111" & Abort & Octet_err & CRC_err; 535 | RxOutputData_int <= "11111" & Abort_Sample & Octet_err_sample & CRC_err_sample; 536 | end if; 537 | end if; 538 | end if; 539 | end process RxOutputData_Proc; 540 | 541 | end HDLC_RECEIVE_a; 542 | 543 | --------------------------------------------------------------------------------