├── .gitignore ├── LANGS.md ├── README.md ├── book.json ├── en ├── README.md ├── SUMMARY.md ├── about_this_manual.md ├── chapter_d4 │ ├── README.md │ ├── d41_1_address_tagging_in_aarch64_state.md │ ├── d41_about_the_virtual_memory_system_architecture_v_.md │ ├── d42_10_pseudocode_description_of_vmsav8-64_address_translation.md │ ├── d42_11_address_translation_instructions.md │ ├── d42_1_about_the_vmsav8-64_address_translation_syste.md │ ├── d42_2_controlling_address_translation_stages.md │ ├── d42_3_memory_translation_granule_size.md │ ├── d42_4_translation_tables_and_the_translation_proces.md │ ├── d42_5_overview_of_the_vmsav8-64_address_translation.md │ ├── d42_6_the_vmsav8-64_translation_table_format.md │ ├── d42_7_the_algorithm_for_finding_the_translation_table_entries.md │ ├── d42_8_the_effects_of_disabling_a_stage_of_address_translation.md │ ├── d42_9_the_implemented_exception_levels_and_the_resulting_translation_stages_and_regimes.md │ ├── d42_the_vmsav8-64_address_translation_system.md │ ├── d43_1_vmsav8-64_translation_table_descriptor_formats.md │ ├── d43_2_armv8_translation_table_level_3_descriptor_formats.md │ ├── d43_3_memory_attribute_fields_in_the_vmsav8-64_translation_table_formats_descriptors.md │ ├── d43_4_control_of_secure_or_non-secure_memory_access.md │ ├── d43_vmsav8-64_translation_table_format_descriptors.md │ ├── d44_1_memory_access_control.md │ ├── d44_access_controls_and_memory_region_attributes.md │ ├── d45_mmu_faults.md │ ├── d46_translation_lookaside_buffers_tlbs.md │ ├── d47_tlb_maintenance_requirements_and_the_tlb_maint.md │ ├── d48_caches_in_a_vmsa_implementation.md │ ├── d4_the_aarch64_virtual_memory_system_archi.md │ ├── figure_d4_1.png │ ├── figure_d4_10.png │ ├── figure_d4_11.png │ ├── figure_d4_12.png │ ├── figure_d4_13.png │ ├── figure_d4_14.png │ ├── figure_d4_15.png │ ├── figure_d4_16.png │ ├── figure_d4_17.1.png │ ├── figure_d4_17.2.png │ ├── figure_d4_17.3.png │ ├── figure_d4_17.png │ ├── figure_d4_18.png │ ├── figure_d4_2.png │ ├── figure_d4_3.png │ ├── figure_d4_4.png │ ├── figure_d4_5.png │ ├── figure_d4_6.png │ ├── figure_d4_7.png │ ├── figure_d4_8.png │ ├── figure_d4_9.png │ ├── table_d4_1.png │ ├── table_d4_10.png │ ├── table_d4_11.png │ ├── table_d4_12.png │ ├── table_d4_13.png │ ├── table_d4_14.png │ ├── table_d4_15.png │ ├── table_d4_16.png │ ├── table_d4_17.png │ ├── table_d4_18.png │ ├── table_d4_19.png │ ├── table_d4_2.png │ ├── table_d4_20.png │ ├── table_d4_21_1.png │ ├── table_d4_21_2.png │ ├── table_d4_22.png │ ├── table_d4_23.png │ ├── table_d4_24.png │ ├── table_d4_25.png │ ├── table_d4_26.png │ ├── table_d4_27.png │ ├── table_d4_28.png │ ├── table_d4_29.png │ ├── table_d4_3.png │ ├── table_d4_30.png │ ├── table_d4_31.png │ ├── table_d4_32_1.png │ ├── table_d4_32_2.png │ ├── table_d4_33_1.png │ ├── table_d4_33_2.png │ ├── table_d4_34.png │ ├── table_d4_35.png │ ├── table_d4_36.png │ ├── table_d4_37.png │ ├── table_d4_38.png │ ├── table_d4_39.png │ ├── table_d4_40.png │ ├── table_d4_41.png │ ├── table_d4_42.png │ ├── table_d4_43.png │ ├── table_d4_4_1.png │ ├── table_d4_4_2.png │ ├── table_d4_5.png │ ├── table_d4_6.png │ ├── table_d4_7.png │ ├── table_d4_8.png │ ├── table_d4_9.png │ └── todo.md ├── css │ └── custom.css ├── js │ └── custom.js └── preface.md └── zh ├── README.md ├── SUMMARY.md ├── about_this_manual.md ├── chapter_d4 ├── README.md ├── d41_1_address_tagging_in_aarch64_state.md ├── d41_about_the_virtual_memory_system_architecture_v_.md ├── d428_the_effects_of_disabling_a_stage_of_address_translation.md ├── d42_10_pseudocode_description_of_vmsav8-64_address_translation.md ├── d42_11_address_translation_instructions.md ├── d42_1_about_the_vmsav8-64_address_translation_syste.md ├── d42_2_controlling_address_translation_stages.md ├── d42_3_memory_translation_granule_size.md ├── d42_4_translation_tables_and_the_translation_proces.md ├── d42_5_overview_of_the_vmsav8-64_address_translation.md ├── d42_6_the_vmsav8-64_translation_table_format.md ├── d42_7_the_algorithm_for_finding_the_translation_table_entries.md ├── d42_9_the_implemented_exception_levels_and_the_resulting_translation_stages_and_regimes.md ├── d42_the_vmsav8-64_address_translation_system.md ├── d43_1_vmsav8-64_translation_table_descriptor_formats.md ├── d43_2_armv8_translation_table_level_3_descriptor_formats.md ├── d43_3_memory_attribute_fields_in_the_vmsav8-64_translation_table_formats_descriptors.md ├── d43_4_control_of_secure_or_non-secure_memory_access.md ├── d43_vmsav8-64_translation_table_format_descriptors.md ├── d44_1_memory_access_control.md ├── d44_access_controls_and_memory_region_attributes.md ├── d45_mmu_faults.md ├── d46_translation_lookaside_buffers_tlbs.md ├── d47_tlb_maintenance_requirements_and_the_tlb_maint.md ├── d48_caches_in_a_vmsa_implementation.md ├── d4_the_aarch64_virtual_memory_system_archi.md ├── figure_d4_1.png ├── figure_d4_10.png ├── figure_d4_11.png ├── figure_d4_12.png ├── figure_d4_13.png ├── figure_d4_14.png ├── figure_d4_15.png ├── figure_d4_16.png ├── figure_d4_17.1.png ├── figure_d4_17.2.png ├── figure_d4_17.3.png ├── figure_d4_17.png ├── figure_d4_18.png ├── figure_d4_2.png ├── figure_d4_3.png ├── figure_d4_4.png ├── figure_d4_5.png ├── figure_d4_6.png ├── figure_d4_7.png ├── figure_d4_8.png ├── figure_d4_9.png ├── table_d4_1.png ├── table_d4_10.png ├── table_d4_11.png ├── table_d4_12.png ├── table_d4_13.png ├── table_d4_14.png ├── table_d4_15.png ├── table_d4_16.png ├── table_d4_17.png ├── table_d4_18.png ├── table_d4_19.png ├── table_d4_2.png ├── table_d4_20.png ├── table_d4_21_1.png ├── table_d4_21_2.png ├── table_d4_22.png ├── table_d4_23.png ├── table_d4_24.png ├── table_d4_25.png ├── table_d4_26.png ├── table_d4_27.png ├── table_d4_28.png ├── table_d4_29.png ├── table_d4_3.png ├── table_d4_30.png ├── table_d4_31.png ├── table_d4_32_1.png ├── table_d4_32_2.png ├── table_d4_33_1.png ├── table_d4_33_2.png ├── table_d4_34.png ├── table_d4_35.png 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