├── .clang-format ├── .dockerignore ├── .editorconfig ├── .gitattributes ├── .gitcommit ├── .github ├── ISSUE_TEMPLATE │ ├── bug_report.yml │ ├── config.yml │ ├── docs_report.yml │ └── feature_request.yml ├── PULL_REQUEST_TEMPLATE.md ├── actions │ └── setup-build-env │ │ └── action.yml └── workflows │ ├── codeql.yml │ ├── extra-builds.yml │ ├── prepare-docs.yml │ ├── source-vendor.yml │ ├── test-build.yml │ ├── test-compile.yml │ ├── test-verific.yml │ ├── update-flake-lock.yml │ ├── version.yml │ ├── wheels.yml │ └── wheels │ ├── _run_cibw_linux.py │ ├── cibw_before_all.sh │ └── cibw_before_build.sh ├── .gitignore ├── .gitmodules ├── .mailmap ├── .readthedocs.yaml ├── Brewfile ├── CHANGELOG ├── CODEOWNERS ├── CODE_OF_CONDUCT.md ├── COPYING ├── Dockerfile ├── Makefile ├── README-ift.md ├── README.md ├── backends ├── aiger │ ├── Makefile.inc │ ├── aiger.cc │ └── xaiger.cc ├── aiger2 │ ├── Makefile.inc │ └── aiger.cc ├── blif │ ├── Makefile.inc │ └── blif.cc ├── btor │ ├── .gitignore │ ├── Makefile.inc │ ├── btor.cc │ └── test_cells.sh ├── cxxrtl │ ├── Makefile.inc │ ├── cxxrtl_backend.cc │ └── runtime │ │ ├── README.txt │ │ └── cxxrtl │ │ ├── capi │ │ ├── cxxrtl_capi.cc │ │ ├── cxxrtl_capi.h │ │ ├── cxxrtl_capi_vcd.cc │ │ └── cxxrtl_capi_vcd.h │ │ ├── cxxrtl.h │ │ ├── cxxrtl_replay.h │ │ ├── cxxrtl_time.h │ │ └── cxxrtl_vcd.h ├── edif │ ├── Makefile.inc │ ├── edif.cc │ └── runtest.py ├── firrtl │ ├── .gitignore │ ├── Makefile.inc │ ├── firrtl.cc │ ├── test.sh │ └── test.v ├── functional │ ├── Makefile.inc │ ├── cxx.cc │ ├── cxx_runtime │ │ └── sim.h │ ├── smtlib.cc │ ├── smtlib_rosette.cc │ └── test_generic.cc ├── intersynth │ ├── Makefile.inc │ └── intersynth.cc ├── jny │ ├── Makefile.inc │ └── jny.cc ├── json │ ├── Makefile.inc │ └── json.cc ├── rtlil │ ├── Makefile.inc │ ├── rtlil_backend.cc │ └── rtlil_backend.h ├── simplec │ ├── .gitignore │ ├── Makefile.inc │ ├── simplec.cc │ ├── test00.sh │ ├── test00_tb.c │ └── test00_uut.v ├── smt2 │ ├── .gitignore │ ├── Makefile.inc │ ├── example.v │ ├── example.ys │ ├── smt2.cc │ ├── smtbmc.py │ ├── smtbmc_incremental.py │ ├── smtio.py │ ├── test_cells.sh │ ├── witness.py │ └── ywio.py ├── smv │ ├── .gitignore │ ├── Makefile.inc │ ├── smv.cc │ └── test_cells.sh ├── spice │ ├── Makefile.inc │ └── spice.cc ├── table │ ├── Makefile.inc │ └── table.cc └── verilog │ ├── Makefile.inc │ └── verilog_backend.cc ├── docs ├── .gitignore ├── Makefile ├── source │ ├── _downloads │ │ ├── APPNOTE_010_Verilog_to_BLIF.pdf │ │ └── APPNOTE_012_Verilog_to_BTOR.pdf │ ├── _images │ │ ├── Makefile │ │ ├── internals │ │ │ ├── approach_flow.tex │ │ │ ├── overview_flow.tex │ │ │ ├── overview_rtlil.tex │ │ │ ├── simplified_rtlil.tex │ │ │ └── verilog_flow.tex │ │ └── primer │ │ │ ├── basics_abstractions.tex │ │ │ ├── basics_ast.tex │ │ │ ├── basics_flow.tex │ │ │ ├── basics_parsetree.tex │ │ │ └── levels_of_abstraction.tex │ ├── _static │ │ ├── custom.css │ │ └── logo.png │ ├── appendix │ │ ├── APPNOTE_010_Verilog_to_BLIF.rst │ │ ├── APPNOTE_012_Verilog_to_BTOR.rst │ │ ├── auxlibs.rst │ │ ├── auxprogs.rst │ │ ├── env_vars.rst │ │ ├── primer.rst │ │ └── rtlil_text.rst │ ├── bib.rst │ ├── cell │ │ ├── gate_comb_combined.rst │ │ ├── gate_comb_simple.rst │ │ ├── gate_other.rst │ │ ├── gate_reg_ff.rst │ │ ├── gate_reg_latch.rst │ │ ├── index_gate.rst │ │ ├── index_word.rst │ │ ├── properties.rst │ │ ├── word_arith.rst │ │ ├── word_binary.rst │ │ ├── word_debug.rst │ │ ├── word_formal.rst │ │ ├── word_fsm.rst │ │ ├── word_logic.rst │ │ ├── word_mem.rst │ │ ├── word_mux.rst │ │ ├── word_reg.rst │ │ ├── word_spec.rst │ │ ├── word_unary.rst │ │ └── word_wire.rst │ ├── cell_index.rst │ ├── cmd_ref.rst │ ├── code_examples │ │ ├── .gitignore │ │ ├── axis │ │ │ ├── axis_master.v │ │ │ ├── axis_test.v │ │ │ └── axis_test.ys │ │ ├── extensions │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── absval_ref.v │ │ │ ├── my_cmd.cc │ │ │ └── sigmap_test.v │ │ ├── fifo │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── fifo.libmap │ │ │ ├── fifo.v │ │ │ ├── fifo.ys │ │ │ └── fifo_map.ys │ │ ├── intro │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── counter.v │ │ │ ├── counter.ys │ │ │ ├── mycells.lib │ │ │ └── mycells.v │ │ ├── macc │ │ │ ├── Makefile │ │ │ ├── macc_simple_test.v │ │ │ ├── macc_simple_test.ys │ │ │ ├── macc_simple_test_01.v │ │ │ ├── macc_simple_test_02.v │ │ │ ├── macc_simple_xmap.v │ │ │ ├── macc_xilinx_swap_map.v │ │ │ ├── macc_xilinx_test.v │ │ │ ├── macc_xilinx_test.ys │ │ │ ├── macc_xilinx_unwrap_map.v │ │ │ ├── macc_xilinx_wrap_map.v │ │ │ └── macc_xilinx_xmap.v │ │ ├── macro_commands │ │ │ ├── fsm.ys │ │ │ ├── memory.ys │ │ │ ├── opt.ys │ │ │ ├── proc.ys │ │ │ └── synth_ice40.ys │ │ ├── opt │ │ │ ├── Makefile │ │ │ ├── opt_expr.ys │ │ │ ├── opt_merge.ys │ │ │ ├── opt_muxtree.ys │ │ │ └── opt_share.ys │ │ ├── primetest.v │ │ ├── scrambler │ │ │ ├── Makefile │ │ │ ├── scrambler.v │ │ │ └── scrambler.ys │ │ ├── selections │ │ │ ├── Makefile │ │ │ ├── foobaraddsub.v │ │ │ ├── memdemo.v │ │ │ ├── memdemo.ys │ │ │ ├── select.v │ │ │ ├── select.ys │ │ │ ├── submod.ys │ │ │ ├── sumprod.v │ │ │ └── sumprod.ys │ │ ├── show │ │ │ ├── Makefile │ │ │ ├── cmos.v │ │ │ ├── cmos.ys │ │ │ ├── example.v │ │ │ ├── example.ys │ │ │ ├── example_lscd.ys │ │ │ ├── example_show.ys │ │ │ └── splice.v │ │ ├── stubnets │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── stubnets.cc │ │ │ └── test.v │ │ ├── synth_flow │ │ │ ├── Makefile │ │ │ ├── memory_01.v │ │ │ ├── memory_01.ys │ │ │ ├── memory_02.v │ │ │ ├── memory_02.ys │ │ │ ├── proc_01.v │ │ │ ├── proc_01.ys │ │ │ ├── proc_02.v │ │ │ ├── proc_02.ys │ │ │ ├── proc_03.v │ │ │ ├── proc_03.ys │ │ │ ├── techmap_01.v │ │ │ ├── techmap_01.ys │ │ │ └── techmap_01_map.v │ │ └── techmap │ │ │ ├── Makefile │ │ │ ├── addshift_map.v │ │ │ ├── addshift_test.v │ │ │ ├── addshift_test.ys │ │ │ ├── mulshift_map.v │ │ │ ├── mulshift_test.v │ │ │ ├── mulshift_test.ys │ │ │ ├── mymul_map.v │ │ │ ├── mymul_test.v │ │ │ ├── mymul_test.ys │ │ │ ├── red_or3x1_cells.v │ │ │ ├── red_or3x1_map.v │ │ │ ├── red_or3x1_test.v │ │ │ ├── red_or3x1_test.ys │ │ │ ├── sym_mul_cells.v │ │ │ ├── sym_mul_map.v │ │ │ ├── sym_mul_test.v │ │ │ └── sym_mul_test.ys │ ├── conf.py │ ├── getting_started │ │ ├── example_synth.rst │ │ ├── index.rst │ │ ├── installation.rst │ │ └── scripting_intro.rst │ ├── index.rst │ ├── introduction.rst │ ├── literature.bib │ ├── requirements.txt │ ├── using_yosys │ │ ├── index.rst │ │ ├── more_scripting │ │ │ ├── index.rst │ │ │ ├── interactive_investigation.rst │ │ │ ├── load_design.rst │ │ │ ├── model_checking.rst │ │ │ └── selections.rst │ │ └── synthesis │ │ │ ├── abc.rst │ │ │ ├── cell_libs.rst │ │ │ ├── extract.rst │ │ │ ├── fsm.rst │ │ │ ├── index.rst │ │ │ ├── memory.rst │ │ │ ├── opt.rst │ │ │ ├── proc.rst │ │ │ ├── synth.rst │ │ │ └── techmap_synth.rst │ └── yosys_internals │ │ ├── extending_yosys │ │ ├── build_verific.rst │ │ ├── contributing.rst │ │ ├── extensions.rst │ │ ├── functional_ir.rst │ │ ├── index.rst │ │ └── test_suites.rst │ │ ├── flow │ │ ├── control_and_data.rst │ │ ├── index.rst │ │ ├── overview.rst │ │ └── verilog_frontend.rst │ │ ├── formats │ │ ├── index.rst │ │ └── rtlil_rep.rst │ │ ├── hashing.rst │ │ ├── index.rst │ │ ├── techmap.rst │ │ └── verilog.rst ├── tests │ └── macro_commands.py └── util │ ├── RtlilLexer.py │ ├── __init__.py │ ├── cellref.py │ └── cmdref.py ├── examples ├── aiger │ ├── .gitignore │ ├── README │ ├── demo.sh │ └── demo.v ├── anlogic │ ├── .gitignore │ ├── README │ ├── build.sh │ ├── build.tcl │ ├── demo.adc │ ├── demo.v │ └── demo.ys ├── basys3 │ ├── README │ ├── example.v │ ├── example.xdc │ ├── run.sh │ ├── run_prog.tcl │ ├── run_vivado.tcl │ └── run_yosys.ys ├── cmos │ ├── .gitignore │ ├── README │ ├── cmos_cells.lib │ ├── cmos_cells.sp │ ├── cmos_cells.v │ ├── cmos_cells_digital.sp │ ├── counter.v │ ├── counter.ys │ ├── counter_digital.ys │ ├── counter_tb.gtkw │ ├── counter_tb.v │ ├── testbench.sh │ ├── testbench.sp │ ├── testbench_digital.sh │ └── testbench_digital.sp ├── cxx-api │ ├── demomain.cc │ ├── evaldemo.cc │ └── scopeinfo_example.cc ├── gowin │ ├── .gitignore │ ├── README │ ├── demo.cst │ ├── demo.sdc │ ├── demo.v │ ├── device.cfg │ ├── pnr.cfg │ ├── run.sh │ ├── run.tcl │ └── testbench.v ├── igloo2 │ ├── .gitignore │ ├── example.pdc │ ├── example.sdc │ ├── example.v │ ├── libero.tcl │ └── runme.sh ├── intel │ ├── DE2i-150 │ │ ├── quartus_compile │ │ │ ├── de2i.qpf │ │ │ ├── de2i.qsf │ │ │ └── runme_quartus │ │ ├── run_cycloneiv │ │ ├── sevenseg.v │ │ └── top.v │ ├── MAX10 │ │ ├── run_max10 │ │ ├── runme_postsynth │ │ ├── sevenseg.v │ │ └── top.v │ └── asicworld_lfsr │ │ ├── README │ │ ├── lfsr_updown.v │ │ ├── lfsr_updown_tb.v │ │ ├── run_cycloneiv │ │ ├── run_max10 │ │ ├── runme_postsynth │ │ └── runme_presynth ├── mimas2 │ ├── README │ ├── example.ucf │ ├── example.v │ ├── run.sh │ └── run_yosys.ys ├── osu035 │ ├── .gitignore │ ├── Makefile │ ├── example.constr │ ├── example.v │ └── example.ys ├── python-api │ ├── .gitignore │ ├── pass.py │ └── script.py └── smtbmc │ ├── .gitignore │ ├── Makefile │ ├── demo1.v │ ├── demo2.v │ ├── demo3.smtc │ ├── demo3.v │ ├── demo4.smtc │ ├── demo4.v │ ├── demo5.v │ ├── demo6.v │ ├── demo7.v │ ├── demo8.v │ ├── demo9.v │ └── glift │ ├── C7552.v │ ├── C7552.ys │ ├── C880.v │ ├── C880.ys │ ├── alu2.v │ ├── alu2.ys │ ├── alu4.v │ ├── alu4.ys │ ├── mux2.ys │ ├── t481.v │ ├── t481.ys │ ├── too_large.v │ ├── too_large.ys │ ├── ttt2.v │ ├── ttt2.ys │ ├── x1.v │ └── x1.ys ├── flake.lock ├── flake.nix ├── frontends ├── aiger │ ├── Makefile.inc │ ├── aigerparse.cc │ └── aigerparse.h ├── aiger2 │ ├── Makefile.inc │ └── xaiger.cc ├── ast │ ├── Makefile.inc │ ├── ast.cc │ ├── ast.h │ ├── ast_binding.cc │ ├── ast_binding.h │ ├── dpicall.cc │ ├── genrtlil.cc │ └── simplify.cc ├── blif │ ├── Makefile.inc │ ├── blifparse.cc │ └── blifparse.h ├── json │ ├── Makefile.inc │ └── jsonparse.cc ├── liberty │ ├── Makefile.inc │ └── liberty.cc ├── rpc │ ├── Makefile.inc │ └── rpc_frontend.cc ├── rtlil │ ├── .gitignore │ ├── Makefile.inc │ ├── rtlil_frontend.cc │ ├── rtlil_frontend.h │ ├── rtlil_lexer.l │ └── rtlil_parser.y ├── verific │ ├── Makefile.inc │ ├── README │ ├── example.sby │ ├── example.sv │ ├── verific.cc │ ├── verific.h │ └── verificsva.cc └── verilog │ ├── .gitignore │ ├── Makefile.inc │ ├── const2ast.cc │ ├── preproc.cc │ ├── preproc.h │ ├── verilog_frontend.cc │ ├── verilog_frontend.h │ ├── verilog_lexer.l │ └── verilog_parser.y ├── guidelines └── GettingStarted ├── kernel ├── binding.cc ├── binding.h ├── bitpattern.h ├── calc.cc ├── cellaigs.cc ├── cellaigs.h ├── celledges.cc ├── celledges.h ├── celltypes.h ├── compute_graph.h ├── consteval.h ├── constids.inc ├── cost.cc ├── cost.h ├── driver.cc ├── drivertools.cc ├── drivertools.h ├── ff.cc ├── ff.h ├── ffinit.h ├── ffmerge.cc ├── ffmerge.h ├── fmt.cc ├── fmt.h ├── fstdata.cc ├── fstdata.h ├── functional.cc ├── functional.h ├── hashlib.h ├── json.cc ├── json.h ├── log.cc ├── log.h ├── macc.h ├── mem.cc ├── mem.h ├── modtools.h ├── qcsat.cc ├── qcsat.h ├── register.cc ├── register.h ├── rtlil.cc ├── rtlil.h ├── satgen.cc ├── satgen.h ├── scopeinfo.cc ├── scopeinfo.h ├── sexpr.cc ├── sexpr.h ├── sigtools.h ├── tclapi.cc ├── timinginfo.h ├── topo_scc.h ├── utils.h ├── yosys.cc ├── yosys.h ├── yosys_common.h ├── yw.cc └── yw.h ├── libs ├── bigint │ ├── .gitignore │ ├── BigInteger.cc │ ├── BigInteger.hh │ ├── BigIntegerAlgorithms.cc │ ├── BigIntegerAlgorithms.hh │ ├── BigIntegerLibrary.hh │ ├── BigIntegerUtils.cc │ ├── BigIntegerUtils.hh │ ├── BigUnsigned.cc │ ├── BigUnsigned.hh │ ├── BigUnsignedInABase.cc │ ├── BigUnsignedInABase.hh │ ├── ChangeLog │ ├── Makefile │ ├── NumberlikeArray.hh │ ├── README │ ├── run-testsuite │ ├── sample.cc │ └── testsuite.cc ├── dlfcn-win32 │ ├── dlfcn.cc │ └── dlfcn.h ├── ezsat │ ├── .gitignore │ ├── Makefile │ ├── README │ ├── demo_bit.cc │ ├── demo_cmp.cc │ ├── demo_vec.cc │ ├── ezminisat.cc │ ├── ezminisat.h │ ├── ezsat.cc │ ├── ezsat.h │ ├── puzzle3d.cc │ ├── puzzle3d.scad │ └── testbench.cc ├── fst │ ├── 00_PATCH_win_io.patch │ ├── 00_PATCH_win_zlib.patch │ ├── 00_UPDATE.sh │ ├── block_format.txt │ ├── config.h │ ├── fastlz.cc │ ├── fastlz.h │ ├── fst_win_unistd.h │ ├── fstapi.cc │ ├── fstapi.h │ ├── lz4.cc │ └── lz4.h ├── json11 │ ├── json11.cpp │ └── json11.hpp ├── minisat │ ├── 00_PATCH_mkLit_default_arg.patch │ ├── 00_PATCH_no_fpu_control.patch │ ├── 00_PATCH_remove_zlib.patch │ ├── 00_PATCH_typofixes.patch │ ├── 00_PATCH_warnings.patch │ ├── 00_PATCH_wasm.patch │ ├── 00_UPDATE.sh │ ├── Alg.h │ ├── Alloc.h │ ├── Dimacs.h │ ├── Heap.h │ ├── IntMap.h │ ├── IntTypes.h │ ├── LICENSE │ ├── Map.h │ ├── Options.cc │ ├── Options.h │ ├── ParseUtils.h │ ├── Queue.h │ ├── Rnd.h │ ├── SimpSolver.cc │ ├── SimpSolver.h │ ├── Solver.cc │ ├── Solver.h │ ├── SolverTypes.h │ ├── Sort.h │ ├── System.cc │ ├── System.h │ ├── Vec.h │ └── XAlloc.h ├── sha1 │ ├── sha1.cpp │ └── sha1.h └── subcircuit │ ├── .gitignore │ ├── Makefile │ ├── README │ ├── demo.cc │ ├── scshell.cc │ ├── subcircuit.cc │ ├── subcircuit.h │ ├── test_large.spl │ ├── test_macc22.txt │ ├── test_mine.txt │ ├── test_perm.pl │ └── test_shorts.spl ├── misc ├── __init__.py ├── create_vcxsrc.sh ├── jny.schema.json ├── launcher.c ├── py_wrap_generator.py ├── yosys-config.in └── yosysjs │ ├── demo01.html │ ├── demo02.html │ ├── demo03.html │ ├── yosysjs.js │ └── yosyswrk.js ├── passes ├── cellift │ ├── Makefile.inc │ ├── cellift.cc │ ├── cellift_util.cc │ └── cells │ │ ├── add.cc │ │ ├── and.cc │ │ ├── bmux.cc │ │ ├── bwmux.cc │ │ ├── conjunctive │ │ ├── one_input.cc │ │ ├── three_inputs.cc │ │ └── two_inputs.cc │ │ ├── demux.cc │ │ ├── eq_ne.cc │ │ ├── ge.cc │ │ ├── gt.cc │ │ ├── le.cc │ │ ├── logic_and.cc │ │ ├── logic_not.cc │ │ ├── logic_or.cc │ │ ├── lt.cc │ │ ├── mod.cc │ │ ├── mul.cc │ │ ├── mux.cc │ │ ├── neg.cc │ │ ├── not.cc │ │ ├── or.cc │ │ ├── pmux.cc │ │ ├── pow.cc │ │ ├── reduce_and.cc │ │ ├── reduce_xor.cc │ │ ├── rtlift │ │ └── add.cc │ │ ├── shift_imprecise.cc │ │ ├── shift_shiftx_precise.cc │ │ ├── shiftx_imprecise.cc │ │ ├── shl_sshl_imprecise.cc │ │ ├── shl_sshl_precise.cc │ │ ├── shr.cc │ │ ├── shr_sshr_imprecise.cc │ │ ├── sshr.cc │ │ ├── stateful │ │ ├── adff.cc │ │ ├── adffe.cc │ │ ├── aldff.cc │ │ ├── dff.cc │ │ ├── dff_simple_techmap.cc │ │ ├── dff_techmap.cc │ │ ├── dffe.cc │ │ ├── dffe_rst_techmap.cc │ │ ├── dffe_techmap.cc │ │ ├── dlatch.cc │ │ ├── dlatch_en.cc │ │ ├── sdff.cc │ │ ├── sdff_techmap.cc │ │ ├── sdffce.cc │ │ ├── sdffce_techmap.cc │ │ ├── sdffe.cc │ │ └── sdffe_techmap.cc │ │ ├── sub.cc │ │ └── xor.cc ├── cmds │ ├── Makefile.inc │ ├── add.cc │ ├── add_attrs_to_state_elems.cc │ ├── autoname.cc │ ├── blackbox.cc │ ├── box_derive.cc │ ├── breakdown_glift.cc │ ├── bugpoint.cc │ ├── check.cc │ ├── chformal.cc │ ├── chtype.cc │ ├── clean_zerowidth.cc │ ├── clear_all_attrs.cc │ ├── connect.cc │ ├── connwrappers.cc │ ├── copy.cc │ ├── cover.cc │ ├── delete.cc │ ├── design.cc │ ├── dft_tag.cc │ ├── edgetypes.cc │ ├── example_dt.cc │ ├── exec.cc │ ├── future.cc │ ├── glift.cc │ ├── insert_bmux_cell.cc │ ├── insert_bwmux_cell.cc │ ├── insert_demux_cell.cc │ ├── insert_dff_cell.cc │ ├── insert_pmux_cell.cc │ ├── insert_shift_cell.cc │ ├── insert_shiftx_cell.cc │ ├── internal_stats.cc │ ├── list_state_elements.cc │ ├── logcmd.cc │ ├── logger.cc │ ├── ltp.cc │ ├── meta_reset.cc │ ├── mul_to_adds.cc │ ├── plugin.cc │ ├── pmux_statistics.cc │ ├── portarcs.cc │ ├── portlist.cc │ ├── pre_cellift.cc │ ├── printattrs.cc │ ├── regroup_mux_by_sel.cc │ ├── rename.cc │ ├── scatter.cc │ ├── scc.cc │ ├── scratchpad.cc │ ├── select.cc │ ├── setattr.cc │ ├── setenv.cc │ ├── setundef.cc │ ├── show.cc │ ├── splice.cc │ ├── splitcells.cc │ ├── splitnets.cc │ ├── sta.cc │ ├── stat.cc │ ├── stat_pre_cellift.cc │ ├── stat_shift_offsets.cc │ ├── taint_probes.cc │ ├── tee.cc │ ├── timestamp.cc │ ├── torder.cc │ ├── trace.cc │ ├── viz.cc │ ├── wrapcell.cc │ ├── write_file.cc │ └── xprop.cc ├── equiv │ ├── Makefile.inc │ ├── equiv_add.cc │ ├── equiv_induct.cc │ ├── equiv_make.cc │ ├── equiv_mark.cc │ ├── equiv_miter.cc │ ├── equiv_opt.cc │ ├── equiv_purge.cc │ ├── equiv_remove.cc │ ├── equiv_simple.cc │ ├── equiv_status.cc │ └── equiv_struct.cc ├── fsm │ ├── Makefile.inc │ ├── fsm.cc │ ├── fsm_detect.cc │ ├── fsm_expand.cc │ ├── fsm_export.cc │ ├── fsm_extract.cc │ ├── fsm_info.cc │ ├── fsm_map.cc │ ├── fsm_opt.cc │ ├── fsm_recode.cc │ └── fsmdata.h ├── hierarchy │ ├── Makefile.inc │ ├── hierarchy.cc │ ├── keep_hierarchy.cc │ ├── submod.cc │ └── uniquify.cc ├── memory │ ├── Makefile.inc │ ├── memlib.cc │ ├── memlib.h │ ├── memlib.md │ ├── memory.cc │ ├── memory_bmux2rom.cc │ ├── memory_bram.cc │ ├── memory_collect.cc │ ├── memory_dff.cc │ ├── memory_libmap.cc │ ├── memory_map.cc │ ├── memory_memx.cc │ ├── memory_narrow.cc │ ├── memory_nordff.cc │ ├── memory_share.cc │ └── memory_unpack.cc ├── opt │ ├── Makefile.inc │ ├── muxpack.cc │ ├── opt.cc │ ├── opt_clean.cc │ ├── opt_demorgan.cc │ ├── opt_dff.cc │ ├── opt_expr.cc │ ├── opt_ffinv.cc │ ├── opt_lut.cc │ ├── opt_lut_ins.cc │ ├── opt_mem.cc │ ├── opt_mem_feedback.cc │ ├── opt_mem_priority.cc │ ├── opt_mem_widen.cc │ ├── opt_merge.cc │ ├── opt_muxtree.cc │ ├── opt_reduce.cc │ ├── opt_share.cc │ ├── pmux2shiftx.cc │ ├── rmports.cc │ ├── share.cc │ └── wreduce.cc ├── pmgen │ ├── .gitignore │ ├── Makefile.inc │ ├── README.md │ ├── generate.h │ ├── ice40_dsp.cc │ ├── ice40_dsp.pmg │ ├── ice40_wrapcarry.cc │ ├── ice40_wrapcarry.pmg │ ├── microchip_dsp.cc │ ├── microchip_dsp.pmg │ ├── microchip_dsp_CREG.pmg │ ├── microchip_dsp_cascade.pmg │ ├── peepopt.cc │ ├── peepopt_formal_clockgateff.pmg │ ├── peepopt_muldiv.pmg │ ├── peepopt_shiftadd.pmg │ ├── peepopt_shiftmul_left.pmg │ ├── peepopt_shiftmul_right.pmg │ ├── pmgen.py │ ├── test_pmgen.cc │ ├── test_pmgen.pmg │ ├── xilinx_dsp.cc │ ├── xilinx_dsp.pmg │ ├── xilinx_dsp48a.pmg │ ├── xilinx_dsp_CREG.pmg │ ├── xilinx_dsp_cascade.pmg │ ├── xilinx_srl.cc │ └── xilinx_srl.pmg ├── proc │ ├── Makefile.inc │ ├── proc.cc │ ├── proc_arst.cc │ ├── proc_clean.cc │ ├── proc_dff.cc │ ├── proc_dlatch.cc │ ├── proc_init.cc │ ├── proc_memwr.cc │ ├── proc_mux.cc │ ├── proc_prune.cc │ ├── proc_rmdead.cc │ └── proc_rom.cc ├── sat │ ├── Makefile.inc │ ├── assertpmux.cc │ ├── async2sync.cc │ ├── clk2fflogic.cc │ ├── cutpoint.cc │ ├── eval.cc │ ├── example.v │ ├── example.ys │ ├── expose.cc │ ├── fmcombine.cc │ ├── fminit.cc │ ├── formalff.cc │ ├── freduce.cc │ ├── miter.cc │ ├── mutate.cc │ ├── qbfsat.cc │ ├── qbfsat.h │ ├── recover_names.cc │ ├── sat.cc │ ├── sim.cc │ ├── supercover.cc │ └── synthprop.cc ├── techmap │ ├── Makefile.inc │ ├── abc.cc │ ├── abc9.cc │ ├── abc9_exe.cc │ ├── abc9_ops.cc │ ├── abc_new.cc │ ├── aigmap.cc │ ├── alumacc.cc │ ├── attrmap.cc │ ├── attrmvcp.cc │ ├── bmuxmap.cc │ ├── booth.cc │ ├── bufnorm.cc │ ├── bwmuxmap.cc │ ├── cellmatch.cc │ ├── clkbufmap.cc │ ├── clockgate.cc │ ├── deminout.cc │ ├── demuxmap.cc │ ├── dffinit.cc │ ├── dfflegalize.cc │ ├── dfflibmap.cc │ ├── dffunmap.cc │ ├── extract.cc │ ├── extract_counter.cc │ ├── extract_fa.cc │ ├── extract_reduce.cc │ ├── extractinv.cc │ ├── filterlib.cc │ ├── flatten.cc │ ├── flowmap.cc │ ├── hilomap.cc │ ├── insbuf.cc │ ├── iopadmap.cc │ ├── libparse.cc │ ├── libparse.h │ ├── lut2mux.cc │ ├── maccmap.cc │ ├── muxcover.cc │ ├── nlutmap.cc │ ├── pmuxtree.cc │ ├── shregmap.cc │ ├── simplemap.cc │ ├── simplemap.h │ ├── techmap.cc │ ├── tribuf.cc │ └── zinit.cc └── tests │ ├── Makefile.inc │ ├── flowmap │ ├── flow.v │ ├── flowp.v │ ├── pack1.v │ ├── pack1p.v │ ├── pack2.v │ ├── pack2p.v │ ├── pack3.v │ └── pack3p.v │ ├── test_abcloop.cc │ ├── test_autotb.cc │ └── test_cell.cc ├── setup.py ├── techlibs ├── .gitignore ├── achronix │ ├── Makefile.inc │ ├── speedster22i │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ └── synth_achronix.cc ├── anlogic │ ├── Makefile.inc │ ├── anlogic_eqn.cc │ ├── anlogic_fixcarry.cc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── eagle_bb.v │ ├── lutrams.txt │ ├── lutrams_map.v │ └── synth_anlogic.cc ├── common │ ├── .gitignore │ ├── Makefile.inc │ ├── abc9_map.v │ ├── abc9_model.v │ ├── abc9_unmap.v │ ├── adff2dff.v │ ├── cellhelp.py │ ├── cells.lib │ ├── choices │ │ ├── han-carlson.v │ │ ├── kogge-stone.v │ │ └── sklansky.v │ ├── cmp2lcu.v │ ├── cmp2lut.v │ ├── cmp2softlogic.v │ ├── dff2ff.v │ ├── gate2lut.v │ ├── gen_fine_ffs.py │ ├── mul2dsp.v │ ├── pmux2mux.v │ ├── prep.cc │ ├── simcells.v │ ├── simlib.v │ ├── smtmap.v │ ├── synth.cc │ └── techmap.v ├── coolrunner2 │ ├── Makefile.inc │ ├── cells_counter_map.v │ ├── cells_latch.v │ ├── cells_sim.v │ ├── coolrunner2_fixup.cc │ ├── coolrunner2_sop.cc │ ├── synth_coolrunner2.cc │ ├── tff_extract.v │ └── xc2_dff.lib ├── easic │ ├── Makefile.inc │ └── synth_easic.cc ├── ecp5 │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_bb.v │ ├── cells_ff.vh │ ├── cells_io.vh │ ├── cells_map.v │ ├── cells_sim.v │ ├── dsp_map.v │ ├── latches_map.v │ ├── lutrams.txt │ ├── lutrams_map.v │ ├── synth_ecp5.cc │ └── tests │ │ ├── .gitignore │ │ └── test_diamond_ffs.py ├── efinix │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── efinix_fixcarry.cc │ ├── gbuf_map.v │ └── synth_efinix.cc ├── fabulous │ ├── Makefile.inc │ ├── arith_map.v │ ├── cells_map.v │ ├── ff_map.v │ ├── io_map.v │ ├── latches_map.v │ ├── prims.v │ ├── ram_regfile.txt │ ├── regfile_map.v │ └── synth_fabulous.cc ├── gatemate │ ├── .gitignore │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_init_20.vh │ ├── brams_init_40.vh │ ├── brams_map.v │ ├── cells_bb.v │ ├── cells_sim.v │ ├── gatemate_foldinv.cc │ ├── inv_map.v │ ├── lut_map.v │ ├── make_lut_tree_lib.py │ ├── mul_map.v │ ├── mux_map.v │ ├── reg_map.v │ └── synth_gatemate.cc ├── gowin │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_xtra.py │ ├── cells_xtra_gw1n.v │ ├── cells_xtra_gw2a.v │ ├── cells_xtra_gw5a.v │ ├── lutrams.txt │ ├── lutrams_map.v │ └── synth_gowin.cc ├── greenpak4 │ ├── Makefile.inc │ ├── cells_blackbox.v │ ├── cells_latch.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_sim_ams.v │ ├── cells_sim_digital.v │ ├── cells_sim_wip.v │ ├── gp_dff.lib │ ├── greenpak4_dffinv.cc │ └── synth_greenpak4.cc ├── ice40 │ ├── Makefile.inc │ ├── abc9_model.v │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── dsp_map.v │ ├── ff_map.v │ ├── ice40_braminit.cc │ ├── ice40_opt.cc │ ├── latches_map.v │ ├── spram.txt │ ├── spram_map.v │ ├── synth_ice40.cc │ └── tests │ │ ├── .gitignore │ │ ├── test_arith.v │ │ ├── test_arith.ys │ │ ├── test_bram.sh │ │ ├── test_bram.v │ │ ├── test_bram_tb.v │ │ ├── test_dsp_map.sh │ │ ├── test_dsp_model.sh │ │ ├── test_dsp_model.v │ │ ├── test_ffs.sh │ │ └── test_ffs.v ├── intel │ ├── Makefile.inc │ ├── common │ │ ├── altpll_bb.v │ │ ├── brams_m9k.txt │ │ ├── brams_map_m9k.v │ │ ├── ff_map.v │ │ └── m9k_bb.v │ ├── cyclone10lp │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ ├── cycloneiv │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ ├── cycloneive │ │ ├── arith_map.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ ├── max10 │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ └── synth_intel.cc ├── intel_alm │ ├── Makefile.inc │ ├── common │ │ ├── abc9_map.v │ │ ├── abc9_model.v │ │ ├── abc9_unmap.v │ │ ├── alm_map.v │ │ ├── alm_sim.v │ │ ├── arith_alm_map.v │ │ ├── bram_m10k.txt │ │ ├── bram_m10k_map.v │ │ ├── dff_map.v │ │ ├── dff_sim.v │ │ ├── dsp_map.v │ │ ├── dsp_sim.v │ │ ├── lutram_mlab.txt │ │ ├── megafunction_bb.v │ │ ├── mem_sim.v │ │ └── misc_sim.v │ ├── cyclonev │ │ └── cells_sim.v │ └── synth_intel_alm.cc ├── lattice │ ├── Makefile.inc │ ├── arith_map_ccu2c.v │ ├── arith_map_ccu2d.v │ ├── brams_16kd.txt │ ├── brams_8kc.txt │ ├── brams_map_16kd.v │ ├── brams_map_8kc.v │ ├── ccu2c_sim.vh │ ├── ccu2d_sim.vh │ ├── cells_bb_ecp5.v │ ├── cells_bb_xo2.v │ ├── cells_bb_xo3.v │ ├── cells_bb_xo3d.v │ ├── cells_ff.vh │ ├── cells_io.vh │ ├── cells_map.v │ ├── cells_sim_ecp5.v │ ├── cells_sim_xo2.v │ ├── cells_sim_xo3.v │ ├── cells_sim_xo3d.v │ ├── cells_xtra.py │ ├── common_sim.vh │ ├── dsp_map_18x18.v │ ├── latches_map.v │ ├── lattice_gsr.cc │ ├── lutrams.txt │ ├── lutrams_map.v │ └── synth_lattice.cc ├── microchip │ ├── LSRAM.txt │ ├── LSRAM_map.v │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams_defs.vh │ ├── cells_map.v │ ├── cells_sim.v │ ├── microchip_dffopt.cc │ ├── polarfire_dsp_map.v │ ├── synth_microchip.cc │ ├── uSRAM.txt │ └── uSRAM_map.v ├── nanoxplore │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_init.vh │ ├── brams_map.v │ ├── cells_bb.v │ ├── cells_bb_l.v │ ├── cells_bb_m.v │ ├── cells_bb_u.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_sim_l.v │ ├── cells_sim_m.v │ ├── cells_sim_u.v │ ├── cells_wrap.v │ ├── cells_wrap_l.v │ ├── cells_wrap_m.v │ ├── cells_wrap_u.v │ ├── io_map.v │ ├── latches_map.v │ ├── nx_carry.cc │ ├── rf_init.vh │ ├── rf_rams_l.txt │ ├── rf_rams_m.txt │ ├── rf_rams_map_l.v │ ├── rf_rams_map_m.v │ ├── rf_rams_map_u.v │ ├── rf_rams_u.txt │ └── synth_nanoxplore.cc ├── nexus │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_xtra.py │ ├── cells_xtra.v │ ├── dsp_map.v │ ├── latches_map.v │ ├── lrams.txt │ ├── lrams_map.v │ ├── lutrams.txt │ ├── lutrams_map.v │ ├── parse_init.vh │ └── synth_nexus.cc ├── quicklogic │ ├── .gitignore │ ├── Makefile.inc │ ├── common │ │ └── cells_sim.v │ ├── pp3 │ │ ├── abc9_map.v │ │ ├── abc9_model.v │ │ ├── abc9_unmap.v │ │ ├── cells_map.v │ │ ├── cells_sim.v │ │ ├── ffs_map.v │ │ ├── latches_map.v │ │ └── lut_map.v │ ├── ql_bram_merge.cc │ ├── ql_bram_types.cc │ ├── ql_dsp_io_regs.cc │ ├── ql_dsp_macc.cc │ ├── ql_dsp_macc.pmg │ ├── ql_dsp_simd.cc │ ├── qlf_k6n10f │ │ ├── .gitignore │ │ ├── TDP18K_FIFO.v │ │ ├── arith_map.v │ │ ├── brams_map.v │ │ ├── brams_sim.v │ │ ├── cells_sim.v │ │ ├── dsp_final_map.v │ │ ├── dsp_map.v │ │ ├── dsp_sim.v │ │ ├── ffs_map.v │ │ ├── generate_bram_types_sim.py │ │ ├── libmap_brams.txt │ │ ├── libmap_brams_map.v │ │ ├── sram1024x18_mem.v │ │ └── ufifo_ctl.v │ └── synth_quicklogic.cc ├── sf2 │ ├── Makefile.inc │ ├── NOTES.txt │ ├── arith_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── synth_sf2.cc │ └── tests │ │ └── test_arith.ys └── xilinx │ ├── Makefile.inc │ ├── abc9_model.v │ ├── arith_map.v │ ├── brams_defs.vh │ ├── brams_xc2v.txt │ ├── brams_xc2v_map.v │ ├── brams_xc3sda.txt │ ├── brams_xc3sda_map.v │ ├── brams_xc4v.txt │ ├── brams_xc4v_map.v │ ├── brams_xc5v_map.v │ ├── brams_xc6v_map.v │ ├── brams_xcu_map.v │ ├── brams_xcv.txt │ ├── brams_xcv_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_xtra.py │ ├── cells_xtra.v │ ├── ff_map.v │ ├── lut_map.v │ ├── lutrams_xc5v.txt │ ├── lutrams_xc5v_map.v │ ├── lutrams_xcu.txt │ ├── lutrams_xcv.txt │ ├── lutrams_xcv_map.v │ ├── mux_map.v │ ├── synth_xilinx.cc │ ├── tests │ ├── .gitignore │ ├── bram1.sh │ ├── bram1.v │ ├── bram1_tb.v │ ├── bram2.sh │ ├── bram2.v │ ├── bram2_tb.v │ ├── test_dsp48_model.sh │ ├── test_dsp48_model.v │ ├── test_dsp48a1_model.sh │ ├── test_dsp48a1_model.v │ ├── test_dsp_model.sh │ └── test_dsp_model.v │ ├── urams.txt │ ├── urams_map.v │ ├── xc3s_mult_map.v │ ├── xc3sda_dsp_map.v │ ├── xc4v_dsp_map.v │ ├── xc5v_dsp_map.v │ ├── xc6s_dsp_map.v │ ├── xc7_dsp_map.v │ ├── xcu_dsp_map.v │ └── xilinx_dffopt.cc ├── test └── tests ├── aiger ├── .gitignore ├── and_.aag ├── and_.aig ├── and_to_bad_out.aag ├── and_to_bad_out.aig ├── buffer.aag ├── buffer.aig ├── cnt1.aag ├── cnt1.aig ├── cnt1e.aag ├── cnt1e.aig ├── empty.aag ├── empty.aig ├── false.aag ├── false.aig ├── halfadder.aag ├── halfadder.aig ├── inverter.aag ├── inverter.aig ├── neg.ys ├── notcnt1.aag ├── notcnt1.aig ├── notcnt1e.aag ├── notcnt1e.aig ├── or_.aag ├── or_.aig ├── run-test.sh ├── symbols.aag ├── symbols.aig ├── toggle-re.aag ├── toggle-re.aig ├── toggle.aag ├── toggle.aig ├── true.aag └── true.aig ├── alumacc ├── macc_b_port_compat.ys └── run-test.sh ├── arch ├── anlogic │ ├── .gitignore │ ├── add_sub.ys │ ├── blockram.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── common │ ├── add_sub.v │ ├── adffs.v │ ├── blockram.v │ ├── blockrom.v │ ├── counter.v │ ├── dffs.v │ ├── fsm.v │ ├── latches.v │ ├── logic.v │ ├── lutram.v │ ├── memory_attributes │ │ └── attributes_test.v │ ├── mul.v │ ├── mux.v │ ├── shifter.v │ └── tribuf.v ├── ecp5 │ ├── .gitignore │ ├── add_sub.py │ ├── add_sub.ys │ ├── adffs.ys │ ├── bug1459.ys │ ├── bug1598.ys │ ├── bug1630.il.gz │ ├── bug1630.ys │ ├── bug1836.mem │ ├── bug1836.ys │ ├── bug2409.ys │ ├── bug2731.ys │ ├── counter.ys │ ├── dffs.ys │ ├── dpram.v │ ├── dpram.ys │ ├── fsm.ys │ ├── latches.ys │ ├── latches_abc9.ys │ ├── logic.ys │ ├── lutram.ys │ ├── macc.v │ ├── macc.ys │ ├── memories.ys │ ├── mul.ys │ ├── mux.ys │ ├── opt_lut_ins.ys │ ├── rom.v │ ├── rom.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── efinix │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── fabulous │ ├── .gitignore │ ├── carry.ys │ ├── complexflop.ys │ ├── counter.ys │ ├── custom_map.v │ ├── custom_prims.v │ ├── customisation.ys │ ├── fsm.ys │ ├── logic.ys │ ├── regfile.ys │ └── tribuf.ys ├── gatemate │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── gen_luttrees.py │ ├── latches.ys │ ├── logic.ys │ ├── luttrees.v │ ├── luttrees.ys │ ├── memory.ys │ ├── mul.v │ ├── mul.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── gowin │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── compare.v │ ├── compare.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── init-error.ys │ ├── init.v │ ├── init.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── ice40 │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── bug1597.ys │ ├── bug1598.ys │ ├── bug1626.ys │ ├── bug1644.il.gz │ ├── bug1644.ys │ ├── bug2061.ys │ ├── counter.ys │ ├── dffs.ys │ ├── dpram.v │ ├── dpram.ys │ ├── fsm.ys │ ├── ice40_dsp.ys │ ├── ice40_opt.ys │ ├── ice40_wrapcarry.ys │ ├── latches.ys │ ├── logic.ys │ ├── macc.v │ ├── macc.ys │ ├── memories.ys │ ├── mul.ys │ ├── mux.ys │ ├── rom.v │ ├── rom.ys │ ├── run-test.sh │ ├── shifter.ys │ ├── spram.v │ ├── spram.ys │ └── tribuf.ys ├── intel_alm │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── blockram.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mul.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── machxo2 │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── microchip │ ├── .gitignore │ ├── dff.ys │ ├── dff_opt.ys │ ├── dsp.ys │ ├── mult.ys │ ├── ram_SDP.ys │ ├── ram_TDP.ys │ ├── reduce.ys │ ├── run-test.sh │ ├── simple_ram.ys │ ├── uram_ar.ys │ ├── uram_sr.ys │ └── widemux.ys ├── nanoxplore │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── meminit.v │ ├── meminit.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── nexus │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── blockram.ys │ ├── blockram_dc.v │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mul.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── quicklogic │ ├── .gitignore │ ├── pp3 │ │ ├── add_sub.ys │ │ ├── adffs.ys │ │ ├── counter.ys │ │ ├── dffs.ys │ │ ├── fsm.ys │ │ ├── latches.ys │ │ ├── logic.ys │ │ ├── mux.ys │ │ ├── run-test.sh │ │ └── tribuf.ys │ └── qlf_k6n10f │ │ ├── .gitignore │ │ ├── add_sub.ys │ │ ├── adffs.ys │ │ ├── counter.ys │ │ ├── dffs.ys │ │ ├── div.ys │ │ ├── dsp.ys │ │ ├── fsm.ys │ │ ├── latches.ys │ │ ├── logic.ys │ │ ├── mem_gen.py │ │ ├── mem_tb.v │ │ ├── meminit.v │ │ ├── meminit.ys │ │ ├── mux.ys │ │ └── run-test.sh ├── run-test.sh └── xilinx │ ├── .gitignore │ ├── abc9_dff.ys │ ├── add_sub.ys │ ├── adffs.ys │ ├── asym_ram_sdp.ys │ ├── asym_ram_sdp_read_wider.v │ ├── asym_ram_sdp_write_wider.v │ ├── attributes_test.ys │ ├── blockram.ys │ ├── bug1460.ys │ ├── bug1462.ys │ ├── bug1480.ys │ ├── bug1598.ys │ ├── bug1605.ys │ ├── bug3670.v │ ├── bug3670.ys │ ├── counter.ys │ ├── dffs.ys │ ├── dsp_abc9.ys │ ├── dsp_cascade.ys │ ├── dsp_fastfir.ys │ ├── dsp_simd.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── macc.sh │ ├── macc.v │ ├── macc.ys │ ├── macc_tb.v │ ├── mul.ys │ ├── mul_unsigned.v │ ├── mul_unsigned.ys │ ├── mux.ys │ ├── mux_lut4.ys │ ├── nosrl.ys │ ├── opt_lut_ins.ys │ ├── pmgen_xilinx_srl.ys │ ├── priority_memory.v │ ├── priority_memory.ys │ ├── run-test.sh │ ├── shifter.ys │ ├── tribuf.sh │ ├── tribuf.ys │ ├── xilinx_dffopt.ys │ ├── xilinx_dffopt_blacklist.txt │ ├── xilinx_dsp.ys │ ├── xilinx_srl.v │ └── xilinx_srl.ys ├── asicworld ├── .gitignore ├── README ├── code_hdl_models_GrayCounter.v ├── code_hdl_models_arbiter.v ├── code_hdl_models_arbiter_tb.v ├── code_hdl_models_cam.v ├── code_hdl_models_clk_div.v ├── code_hdl_models_clk_div_45.v ├── code_hdl_models_d_ff_gates.v ├── code_hdl_models_d_latch_gates.v ├── code_hdl_models_decoder_2to4_gates.v ├── code_hdl_models_decoder_using_assign.v ├── code_hdl_models_decoder_using_case.v ├── code_hdl_models_dff_async_reset.v ├── code_hdl_models_dff_sync_reset.v ├── code_hdl_models_encoder_4to2_gates.v ├── code_hdl_models_encoder_using_case.v ├── code_hdl_models_encoder_using_if.v ├── code_hdl_models_full_adder_gates.v ├── code_hdl_models_full_subtracter_gates.v ├── code_hdl_models_gray_counter.v ├── code_hdl_models_half_adder_gates.v ├── code_hdl_models_lfsr.v ├── code_hdl_models_lfsr_updown.v ├── code_hdl_models_mux_2to1_gates.v ├── code_hdl_models_mux_using_assign.v ├── code_hdl_models_mux_using_case.v ├── code_hdl_models_mux_using_if.v ├── code_hdl_models_one_hot_cnt.v ├── code_hdl_models_parallel_crc.v ├── code_hdl_models_parity_using_assign.v ├── code_hdl_models_parity_using_bitwise.v ├── code_hdl_models_parity_using_function.v ├── code_hdl_models_pri_encoder_using_assign.v ├── code_hdl_models_rom_using_case.v ├── code_hdl_models_serial_crc.v ├── code_hdl_models_tff_async_reset.v ├── code_hdl_models_tff_sync_reset.v ├── code_hdl_models_uart.v ├── code_hdl_models_up_counter.v ├── code_hdl_models_up_counter_load.v ├── code_hdl_models_up_down_counter.v ├── code_specman_switch_fabric.v ├── code_tidbits_asyn_reset.v ├── code_tidbits_blocking.v ├── code_tidbits_fsm_using_always.v ├── code_tidbits_fsm_using_function.v ├── code_tidbits_fsm_using_single_always.v ├── code_tidbits_nonblocking.v ├── code_tidbits_reg_combo_example.v ├── code_tidbits_reg_seq_example.v ├── code_tidbits_syn_reset.v ├── code_tidbits_wire_example.v ├── code_verilog_tutorial_addbit.v ├── code_verilog_tutorial_always_example.v ├── code_verilog_tutorial_bus_con.v ├── code_verilog_tutorial_comment.v ├── code_verilog_tutorial_counter.v ├── code_verilog_tutorial_counter_tb.v ├── code_verilog_tutorial_d_ff.v ├── code_verilog_tutorial_decoder.v ├── code_verilog_tutorial_decoder_always.v ├── code_verilog_tutorial_escape_id.v ├── code_verilog_tutorial_explicit.v ├── code_verilog_tutorial_first_counter.v ├── code_verilog_tutorial_first_counter_tb.v ├── code_verilog_tutorial_flip_flop.v ├── code_verilog_tutorial_fsm_full.v ├── code_verilog_tutorial_fsm_full_tb.v ├── code_verilog_tutorial_good_code.v ├── code_verilog_tutorial_if_else.v ├── code_verilog_tutorial_multiply.v ├── code_verilog_tutorial_mux_21.v ├── code_verilog_tutorial_n_out_primitive.v ├── code_verilog_tutorial_parallel_if.v ├── code_verilog_tutorial_parity.v ├── code_verilog_tutorial_simple_function.v ├── code_verilog_tutorial_simple_if.v ├── code_verilog_tutorial_task_global.v ├── code_verilog_tutorial_tri_buf.v ├── code_verilog_tutorial_v2k_reg.v ├── code_verilog_tutorial_which_clock.v ├── run-test.sh └── xfirrtl ├── bind ├── .gitignore ├── basic.sv ├── basic.ys ├── cell_list.sv ├── cell_list.ys ├── hier.sv ├── hier.ys ├── inst_list.sv ├── inst_list.ys ├── param.sv ├── param.ys ├── run-test.sh ├── toplevel.sv └── toplevel.ys ├── blif ├── .gitignore ├── bug2729.ys ├── bug3374.ys ├── bug3385.ys └── run-test.sh ├── bram ├── .gitignore ├── generate.py ├── run-single.sh └── run-test.sh ├── cxxrtl ├── .gitignore ├── run-test.sh ├── test_unconnected_output.v ├── test_value.cc └── test_value_fuzz.cc ├── errors ├── syntax_err01.v ├── syntax_err02.v ├── syntax_err03.v ├── syntax_err04.v ├── syntax_err05.v ├── syntax_err06.v ├── syntax_err07.v ├── syntax_err08.v ├── syntax_err09.v ├── syntax_err10.v ├── syntax_err11.v ├── syntax_err12.v └── syntax_err13.v ├── fmt ├── .gitignore ├── always_comb.v ├── always_comb_tb.cc ├── always_comb_tb.v ├── always_display.v ├── always_full.v ├── always_full_tb.cc ├── always_full_tb.v ├── display_lm.v ├── display_lm_tb.cc ├── fuzz │ ├── .gitignore │ ├── CMakeLists.txt │ └── x_test.cc ├── initial_display.v ├── roundtrip.v ├── roundtrip_tb.v └── run-test.sh ├── fsm ├── .gitignore ├── generate.py └── run-test.sh ├── functional ├── .gitignore ├── README.md ├── conftest.py ├── picorv32.v ├── picorv32_tb.v ├── rkt_vcd.py ├── rtlil_cells.py ├── run-test.sh ├── smt_vcd.py ├── smtio.py ├── test_functional.py └── vcd_harness.cc ├── gen-tests-makefile.sh ├── hana ├── .gitignore ├── README ├── hana_vlib.v ├── run-test.sh ├── test_intermout.v ├── test_parse2synthtrans.v ├── test_parser.v ├── test_simulation_always.v ├── test_simulation_and.v ├── test_simulation_buffer.v ├── test_simulation_decoder.v ├── test_simulation_inc.v ├── test_simulation_mux.v ├── test_simulation_nand.v ├── test_simulation_nor.v ├── test_simulation_or.v ├── test_simulation_seq.v ├── test_simulation_shifter.v ├── test_simulation_sop.v ├── test_simulation_techmap.v ├── test_simulation_techmap_tech.v ├── test_simulation_vlib.v ├── test_simulation_xnor.v └── test_simulation_xor.v ├── liberty ├── .gitignore ├── XNOR2X1.lib ├── XNOR2X1.lib.filtered.ok ├── XNOR2X1.lib.verilogsim.ok ├── busdef.lib ├── busdef.lib.filtered.ok ├── busdef.lib.verilogsim.ok ├── foundry_data │ ├── .gitignore │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz │ ├── rules.txt │ └── sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz ├── issue3498_bad.lib ├── issue3498_bad.lib.filtered.ok ├── issue3498_bad.lib.verilogsim.ok ├── normal.lib ├── normal.lib.filtered.ok ├── normal.lib.verilogsim.ok ├── normal.verilogsim.ok ├── options_test.ys ├── processdefs.lib ├── processdefs.lib.filtered.ok ├── processdefs.lib.verilogsim.ok ├── run-test.sh ├── semicolextra.lib ├── semicolextra.lib.filtered.ok ├── semicolextra.lib.verilogsim.ok ├── semicolmissing.lib ├── semicolmissing.lib.filtered.ok ├── semicolmissing.lib.verilogsim.ok └── small.v ├── lut ├── .gitignore ├── check_map.ys ├── check_map_lut6.ys ├── map_and.v ├── map_cmp.v ├── map_mux.v ├── map_not.v ├── map_or.v ├── map_xor.v └── run-test.sh ├── memfile ├── .gitignore ├── content1.dat ├── memory.v └── run-test.sh ├── memlib ├── .gitignore ├── generate.py ├── memlib_9b1B.txt ├── memlib_9b1B.v ├── memlib_block_sdp.txt ├── memlib_block_sdp.v ├── memlib_block_sdp_1clk.txt ├── memlib_block_sdp_1clk.v ├── memlib_block_sp.txt ├── memlib_block_sp.v ├── memlib_block_sp_full.txt ├── memlib_block_sp_full.v ├── memlib_block_tdp.txt ├── memlib_block_tdp.v ├── memlib_clock_sdp.txt ├── memlib_clock_sdp.v ├── memlib_lut.txt ├── memlib_lut.v ├── memlib_multilut.txt ├── memlib_multilut.v ├── memlib_wide_read.txt ├── memlib_wide_read.v ├── memlib_wide_sdp.txt ├── memlib_wide_sdp.v ├── memlib_wide_sp.txt ├── memlib_wide_sp.v ├── memlib_wide_write.txt ├── memlib_wide_write.v ├── memlib_wren.txt ├── memlib_wren.v └── run-test.sh ├── memories ├── .gitignore ├── amber23_sram_byte_en.v ├── firrtl_938.v ├── implicit_en.v ├── issue00335.v ├── issue00710.v ├── no_implicit_en.v ├── nordports.ys ├── read_arst.v ├── read_two_mux.v ├── run-test.sh ├── shared_ports.v ├── simple_sram_byte_en.v ├── trans_addr_enable.v ├── trans_sdp.v ├── trans_sp.v ├── wide_all.v ├── wide_read_async.v ├── wide_read_mixed.v ├── wide_read_sync.v ├── wide_read_trans.v ├── wide_thru_priority.v └── wide_write.v ├── opt ├── .gitignore ├── bug1525.ys ├── bug1758.ys ├── bug1854.ys ├── bug2010.ys ├── bug2221.ys ├── bug2311.ys ├── bug2318.ys ├── bug2623.ys ├── bug2765.ys ├── bug2766.ys ├── bug2824.ys ├── bug2920.ys ├── bug3047.ys ├── bug3117.ys ├── bug3848.ys ├── bug3867.ys ├── bug4413.ys ├── bug4610.ys ├── memory_bmux2rom.ys ├── memory_dff_trans.ys ├── memory_map_offset.ys ├── opt_clean_init.ys ├── opt_clean_mem.ys ├── opt_dff_arst.ys ├── opt_dff_clk.ys ├── opt_dff_const.ys ├── opt_dff_dffmux.ys ├── opt_dff_en.ys ├── opt_dff_mux.ys ├── opt_dff_qd.ys ├── opt_dff_sr.ys ├── opt_dff_srst.ys ├── opt_expr.ys ├── opt_expr_alu.ys ├── opt_expr_and.ys ├── opt_expr_cmp.v ├── opt_expr_cmp.ys ├── opt_expr_combined_assign.ys ├── opt_expr_constconn.v ├── opt_expr_constconn.ys ├── opt_expr_consumex.ys ├── opt_expr_or.ys ├── opt_expr_xnor.ys ├── opt_expr_xor.ys ├── opt_lut.v ├── opt_lut.ys ├── opt_lut_elim.il ├── opt_lut_elim.ys ├── opt_lut_ins.ys ├── opt_lut_port.il ├── opt_lut_port.ys ├── opt_mem_feedback.ys ├── opt_mem_priority.ys ├── opt_merge_init.ys ├── opt_merge_keep.ys ├── opt_reduce_andor.ys ├── opt_reduce_bmux.ys ├── opt_reduce_demux.ys ├── opt_rmdff.v ├── opt_rmdff.ys ├── opt_rmdff_sat.v ├── opt_rmdff_sat.ys ├── opt_share_add_sub.v ├── opt_share_add_sub.ys ├── opt_share_bug2334.ys ├── opt_share_bug2335.ys ├── opt_share_bug2336.ys ├── opt_share_bug2538.ys ├── opt_share_cat.v ├── opt_share_cat.ys ├── opt_share_cat_multiuser.v ├── opt_share_cat_multiuser.ys ├── opt_share_diff_port_widths.v ├── opt_share_diff_port_widths.ys ├── opt_share_extend.v ├── opt_share_extend.ys ├── opt_share_large_pmux_cat.v ├── opt_share_large_pmux_cat.ys ├── opt_share_large_pmux_cat_multipart.v ├── opt_share_large_pmux_cat_multipart.ys ├── opt_share_large_pmux_multipart.v ├── opt_share_large_pmux_multipart.ys ├── opt_share_large_pmux_part.v ├── opt_share_large_pmux_part.ys ├── opt_share_mux_tree.v ├── opt_share_mux_tree.ys └── run-test.sh ├── opt_share ├── .gitignore ├── generate.py └── run-test.sh ├── proc ├── .gitignore ├── bug2619.ys ├── bug2656.ys ├── bug2962.ys ├── bug4712.ys ├── bug_1268.v ├── bug_1268.ys ├── clean_undef_case.ys ├── proc_dff.ys ├── proc_rom.ys ├── rmdead.v ├── rmdead.ys └── run-test.sh ├── realmath ├── .gitignore ├── generate.py └── run-test.sh ├── rpc ├── .gitignore ├── design.v ├── exec.ys ├── frontend.py └── run-test.sh ├── sat ├── .gitignore ├── alu.v ├── asserts.v ├── asserts.ys ├── asserts_seq.v ├── asserts_seq.ys ├── bug2595.ys ├── clk2fflogic.ys ├── counters-repeat.v ├── counters-repeat.ys ├── counters.v ├── counters.ys ├── dff.ys ├── expose_dff.v ├── expose_dff.ys ├── grom.ys ├── grom_computer.v ├── grom_cpu.v ├── initval.v ├── initval.ys ├── ram_memory.v ├── run-test.sh ├── share.v ├── share.ys ├── sim_counter.ys ├── sizebits.sv ├── sizebits.ys ├── splice.v └── splice.ys ├── select ├── .gitignore ├── blackboxes.ys ├── list_mod.ys ├── mod-attribute.ys ├── no_warn_assert.ys ├── no_warn_prefixed_arg_memb.ys ├── no_warn_prefixed_empty_select_arg.ys ├── run-test.sh ├── unset.ys ├── unset2.ys └── warn_empty_select_arg.ys ├── share ├── .gitignore ├── generate.py └── run-test.sh ├── sim ├── .gitignore ├── adff.v ├── adffe.v ├── adlatch.v ├── aldff.v ├── aldffe.v ├── assume_x_first_step.ys ├── dff.v ├── dffe.v ├── dffsr.v ├── dlatch.v ├── dlatchsr.v ├── run-test.sh ├── sdff.v ├── sdffce.v ├── sdffe.v ├── sim_adff.ys ├── sim_adffe.ys ├── sim_adlatch.ys ├── sim_aldff.ys ├── sim_aldffe.ys ├── sim_dff.ys ├── sim_dffe.ys ├── sim_dffsr.ys ├── sim_dlatch.ys ├── sim_dlatchsr.ys ├── sim_sdff.ys ├── sim_sdffce.ys ├── sim_sdffe.ys ├── simple_assign.v ├── simple_assign.vcd ├── tb │ ├── tb_adff.v │ ├── tb_adffe.v │ ├── tb_adlatch.v │ ├── tb_aldff.v │ ├── tb_aldffe.v │ ├── tb_dff.v │ ├── tb_dffe.v │ ├── tb_dffsr.v │ ├── tb_dlatch.v │ ├── tb_dlatchsr.v │ ├── tb_sdff.v │ ├── tb_sdffce.v │ └── tb_sdffe.v ├── var_reference_with_whitespace.vcd ├── var_reference_without_whitespace.vcd ├── vcd_var_reference_whitespace.ys └── vector_assign.il ├── simple ├── .gitignore ├── aes_kexp128.v ├── always01.v ├── always02.v ├── always03.v ├── arraycells.v ├── arrays01.v ├── arrays02.sv ├── arrays03.sv ├── asgn_binop.sv ├── attrib01_module.v ├── attrib02_port_decl.v ├── attrib03_parameter.v ├── attrib04_net_var.v ├── attrib05_port_conn.v.DISABLED ├── attrib06_operator_suffix.v ├── attrib07_func_call.v.DISABLED ├── attrib08_mod_inst.v ├── attrib09_case.v ├── carryadd.v ├── case_expr_const.v ├── case_expr_extend.sv ├── case_expr_non_const.v ├── case_expr_query.sv ├── case_large.v ├── const_branch_finish.v ├── const_fold_func.v ├── const_func_shadow.v ├── constmuldivmod.v ├── constpower.v ├── defvalue.sv ├── dff_different_styles.v ├── dff_init.v ├── dynslice.v ├── fiedler-cooley.v ├── forgen01.v ├── forgen02.v ├── forloops.v ├── fsm.v ├── func_block.v ├── func_recurse.v ├── func_width_scope.v ├── genblk_collide.v ├── genblk_dive.v ├── genblk_order.v ├── genblk_port_shadow.v ├── generate.v ├── graphtest.v ├── hierarchy.v ├── hierdefparam.v ├── i2c_master_tests.v ├── ifdef_1.v ├── ifdef_2.v ├── implicit_ports.sv ├── lesser_size_cast.sv ├── local_loop_var.sv ├── localparam_attr.v ├── loop_prefix_case.v ├── loop_var_shadow.v ├── loops.v ├── macro_arg_spaces.sv ├── macro_arg_surrounding_spaces.v ├── macros.v ├── matching_end_labels.sv ├── mem2reg.v ├── mem2reg_bounds_tern.v ├── mem_arst.v ├── memory.v ├── memwr_port_connection.sv ├── module_scope.v ├── module_scope_case.v ├── module_scope_func.v ├── multiplier.v ├── muxtree.v ├── named_genblk.v ├── nested_genblk_resolve.v ├── omsp_dbg_uart.v ├── operators.v ├── param_attr.v ├── paramods.v ├── partsel.v ├── process.v ├── realexpr.v ├── repwhile.v ├── retime.v ├── rotate.v ├── run-test.sh ├── scopes.v ├── sign_part_assign.v ├── signed_full_slice.v ├── signedexpr.v ├── sincos.v ├── specify.v ├── string_format.v ├── subbytes.v ├── task_func.v ├── undef_eqx_nex.v ├── unnamed_block_decl.sv ├── usb_phy_tests.v ├── values.v ├── verilog_primitives.v ├── vloghammer.v ├── wandwor.v ├── wreduce.v └── xfirrtl ├── simple_abc9 ├── .gitignore ├── abc9.v └── run-test.sh ├── smv ├── .gitignore ├── run-single.sh └── run-test.sh ├── sva ├── .gitignore ├── Makefile ├── basic00.sv ├── basic01.sv ├── basic02.sv ├── basic03.sv ├── basic04.sv ├── basic04.vhd ├── basic05.sv ├── basic05.vhd ├── counter.sv ├── extnets.sv ├── nested_clk_else.sv ├── runtest.sh ├── sva_not.sv ├── sva_range.sv ├── sva_throughout.sv ├── sva_value_change_changed.sv ├── sva_value_change_changed_wide.sv ├── sva_value_change_rose.sv ├── sva_value_change_sim.sv └── sva_value_change_sim.ys ├── svinterfaces ├── .gitignore ├── load_and_derive.sv ├── load_and_derive.ys ├── ondemand.sv ├── resolve_types.sv ├── resolve_types.ys ├── run-test.sh ├── run_simple.sh ├── runone.sh ├── svinterface1.sv ├── svinterface1_ref.v ├── svinterface1_tb.v ├── svinterface_at_top.sv ├── svinterface_at_top_ref.v ├── svinterface_at_top_tb.v ├── svinterface_at_top_tb_wrapper.v └── svinterface_at_top_wrapper.v ├── svtypes ├── .gitignore ├── enum_simple.sv ├── enum_simple.ys ├── logic_rom.sv ├── logic_rom.ys ├── multirange_array.sv ├── multirange_subarray_access.ys ├── run-test.sh ├── static_cast_negative.ys ├── static_cast_nonconst.ys ├── static_cast_simple.sv ├── static_cast_verilog.ys ├── static_cast_zero.ys ├── struct_array.sv ├── struct_dynamic_range.sv ├── struct_dynamic_range.ys ├── struct_simple.sv ├── struct_sizebits.sv ├── typedef_initial_and_assign.sv ├── typedef_initial_and_assign.ys ├── typedef_memory.sv ├── typedef_memory.ys ├── typedef_memory_2.sv ├── typedef_memory_2.ys ├── typedef_package.sv ├── typedef_param.sv ├── typedef_scopes.sv ├── typedef_simple.sv ├── typedef_struct.sv ├── typedef_struct_port.sv ├── typedef_struct_port.ys └── union_simple.sv ├── techmap ├── .gitignore ├── abc9.ys ├── adff2dff.ys ├── aigmap.ys ├── autopurge.ys ├── bmuxmap_pmux.ys ├── booth.ys ├── booth_map_script.ys_ ├── bufnorm.ys ├── bug2183.ys ├── bug2321.ys ├── bug2332.ys ├── bug2759.ys ├── bug2972.ys ├── cellmatch.ys ├── cellname.ys ├── clkbufmap.ys ├── clockgate.lib ├── clockgate.ys ├── clockgate_neg.lib ├── clockgate_pos.lib ├── cmp2lcu.ys ├── dff2ff.ys ├── dffinit.ys ├── dfflegalize_adff.ys ├── dfflegalize_adff_init.ys ├── dfflegalize_adlatch.ys ├── dfflegalize_adlatch_init.ys ├── dfflegalize_aldff.ys ├── dfflegalize_aldff_init.ys ├── dfflegalize_dff.ys ├── dfflegalize_dff_init.ys ├── dfflegalize_dffsr.ys ├── dfflegalize_dffsr_init.ys ├── dfflegalize_dlatch.ys ├── dfflegalize_dlatch_const.ys ├── dfflegalize_dlatch_init.ys ├── dfflegalize_dlatchsr.ys ├── dfflegalize_dlatchsr_init.ys ├── dfflegalize_inv.ys ├── dfflegalize_mince.ys ├── dfflegalize_minsrst.ys ├── dfflegalize_sr.ys ├── dfflegalize_sr_init.ys ├── dfflibmap-sim.v ├── dfflibmap.lib ├── dfflibmap.ys ├── dfflibmap_dffn_dffe.lib ├── dfflibmap_dffsr.lib ├── dffunmap.ys ├── extractinv.ys ├── han-carlson.tcl ├── iopadmap.ys ├── kogge-stone.tcl ├── lcu_refined.v ├── mem_simple_4x1_cells.v ├── mem_simple_4x1_map.v ├── mem_simple_4x1_runtest.sh ├── mem_simple_4x1_tb.v ├── mem_simple_4x1_uut.v ├── pmux2mux.ys ├── recursive.v ├── recursive_map.v ├── recursive_runtest.sh ├── run-test.sh ├── shiftx2mux.ys ├── sklansky.tcl ├── techmap_chtype.ys ├── techmap_replace.ys ├── wireinit.ys └── zinit.ys ├── tools ├── .gitignore ├── autotest.mk ├── autotest.sh ├── cmp_tbdata.c ├── profiler.pl ├── txt2tikztiming.py ├── vcd2txt.pl └── vcdcd.pl ├── unit ├── Makefile └── kernel │ ├── logTest.cc │ └── rtlilTest.cc ├── various ├── .gitignore ├── abc9.v ├── abc9.ys ├── aiger2.ys ├── aiger_dff.ys ├── async.sh ├── async.v ├── attrib05_port_conn.v ├── attrib05_port_conn.ys ├── attrib07_func_call.v ├── attrib07_func_call.ys ├── autoname.ys ├── blackbox_wb.ys ├── box_derive.ys ├── bug1496.ys ├── bug1531.ys ├── bug1614.ys ├── bug1710.ys ├── bug1745.ys ├── bug1781.ys ├── bug1876.ys ├── bug2014.ys ├── bug3462.ys ├── bug4082.ys ├── cellarray_array_connections.ys ├── celledges_shift.ys ├── check.ys ├── check_2.ys ├── check_3.ys ├── check_4.ys ├── chformal_check.ys ├── chformal_coverenable.ys ├── chparam.sh ├── clk2fflogic_effects.sh ├── clk2fflogic_effects.sv ├── const_arg_loop.sv ├── const_arg_loop.ys ├── const_func.sv ├── const_func.ys ├── const_func_block_var.v ├── const_func_block_var.ys ├── constant_drive_conflict.ys ├── constcomment.ys ├── constmsk_test.v ├── constmsk_test.ys ├── constmsk_testmap.v ├── countbits.sv ├── countbits.ys ├── deminout_unused.ys ├── design.ys ├── design1.ys ├── design2.ys ├── dynamic_part_select.ys ├── dynamic_part_select │ ├── forloop_select.v │ ├── forloop_select_gate.v │ ├── forloop_select_nowrshmsk.v │ ├── latch_002.v │ ├── latch_002_gate.v │ ├── latch_002_gate_good.v │ ├── latch_1990.v │ ├── latch_1990_gate.v │ ├── multiple_blocking.v │ ├── multiple_blocking_gate.v │ ├── nonblocking.v │ ├── nonblocking_gate.v │ ├── original.v │ ├── original_gate.v │ ├── reset_test.v │ ├── reset_test_gate.v │ ├── reversed.v │ └── reversed_gate.v ├── elab_sys_tasks.sv ├── elab_sys_tasks.ys ├── equiv_make_make_assert.ys ├── equiv_opt_multiclock.ys ├── equiv_opt_undef.ys ├── exec.ys ├── fib.v ├── fib.ys ├── fib_tern.v ├── fib_tern.ys ├── func_port_implied_dir.sv ├── func_port_implied_dir.ys ├── gen_if_null.v ├── gen_if_null.ys ├── global_scope.ys ├── gzip_verilog.v.gz ├── gzip_verilog.ys ├── help.ys ├── hierarchy.sh ├── hierarchy_defer.ys ├── hierarchy_generate.ys ├── hierarchy_param.ys ├── ice40_mince_abc9.ys ├── integer_range_bad_syntax.ys ├── integer_real_bad_syntax.ys ├── json_escape_chars.ys ├── json_scopeinfo.ys ├── keep_hierarchy.ys ├── logger_cmd_error.sh ├── logger_error.ys ├── logger_fail.sh ├── logger_nowarning.ys ├── logger_warn.ys ├── logger_warning.ys ├── logic_param_simple.ys ├── mem2reg.ys ├── memory_word_as_index.data ├── memory_word_as_index.v ├── memory_word_as_index.ys ├── muxcover.ys ├── muxpack.v ├── muxpack.ys ├── param_struct.ys ├── peepopt.ys ├── peepopt_formal.ys ├── plugin.cc ├── plugin.sh ├── pmgen_reduce.ys ├── pmux2shiftx.v ├── pmux2shiftx.ys ├── port_sign_extend.v ├── port_sign_extend.ys ├── primitives.ys ├── printattr.ys ├── rand_const.sv ├── rand_const.ys ├── reg_wire_error.sv ├── reg_wire_error.ys ├── rename_scramble_name.ys ├── rtlil_signed_attribute.ys ├── rtlil_z_bits.ys ├── run-test.sh ├── scopeinfo.ys ├── scratchpad.ys ├── script.ys ├── sformatf.ys ├── shregmap.v ├── shregmap.ys ├── signed.ys ├── signext.ys ├── sim_const.ys ├── specify.v ├── specify.ys ├── src.ys ├── sta.ys ├── struct_access.sv ├── struct_access.ys ├── sub.v ├── submod.ys ├── submod_extract.ys ├── sv_defines.ys ├── sv_defines_dup.ys ├── sv_defines_mismatch.ys ├── sv_defines_too_few.ys ├── sv_implicit_ports.sh ├── svalways.sh ├── tcl_apis.tcl ├── tcl_apis.v ├── tcl_apis.ys ├── wrapcell.ys ├── wreduce.ys ├── wreduce2.ys ├── write_gzip.ys └── xaiger.ys ├── verific ├── .gitignore ├── blackbox.ys ├── blackbox_empty.ys ├── blackbox_ql.ys ├── bounds.sv ├── bounds.vhd ├── bounds.ys ├── case.sv ├── case.ys ├── clocking.ys ├── enum_values.sv ├── enum_values.ys ├── memory_semantics.ys ├── range_case.sv ├── range_case.ys ├── rom_case.ys ├── run-test.sh ├── setenv.flist └── setenv.ys ├── verilog ├── .gitignore ├── absurd_width.ys ├── absurd_width_const.ys ├── always_comb_latch_1.ys ├── always_comb_latch_2.ys ├── always_comb_latch_3.ys ├── always_comb_latch_4.ys ├── always_comb_nolatch_1.ys ├── always_comb_nolatch_2.ys ├── always_comb_nolatch_3.ys ├── always_comb_nolatch_4.ys ├── always_comb_nolatch_5.ys ├── always_comb_nolatch_6.ys ├── asgn_expr.sv ├── asgn_expr.ys ├── asgn_expr_not_proc_1.ys ├── asgn_expr_not_proc_2.ys ├── asgn_expr_not_proc_3.ys ├── asgn_expr_not_proc_4.ys ├── asgn_expr_not_proc_5.ys ├── asgn_expr_not_sv_1.ys ├── asgn_expr_not_sv_2.ys ├── asgn_expr_not_sv_3.ys ├── asgn_expr_not_sv_4.ys ├── assign_to_reg.ys ├── atom_type_signedness.ys ├── block_end_label_only.ys ├── block_end_label_wrong.ys ├── block_labels.ys ├── bug2037.ys ├── bug2042-sv.ys ├── bug2042.ys ├── bug2493.ys ├── bug656.v ├── bug656.ys ├── conflict_assert.ys ├── conflict_cell_memory.ys ├── conflict_interface_port.ys ├── conflict_memory_wire.ys ├── conflict_pwire.ys ├── conflict_wire_memory.ys ├── const_arst.ys ├── const_sr.ys ├── delay_mintypmax.ys ├── delay_risefall.ys ├── delay_time_scale.ys ├── doubleslash.ys ├── dynamic_range_lhs.sh ├── dynamic_range_lhs.v ├── for_decl_no_init.ys ├── for_decl_no_sv.ys ├── for_decl_shadow.sv ├── for_decl_shadow.ys ├── func_arg_mismatch_1.ys ├── func_arg_mismatch_2.ys ├── func_arg_mismatch_3.ys ├── func_arg_mismatch_4.ys ├── func_tern_hint.sv ├── func_tern_hint.ys ├── func_typename_ret.sv ├── func_typename_ret.ys ├── func_upto.sv ├── func_upto.ys ├── gen_block_end_label_only.ys ├── gen_block_end_label_wrong.ys ├── genblk_case.v ├── genblk_case.ys ├── genblk_port_decl.ys ├── genfor_decl_no_init.ys ├── genfor_decl_no_sv.ys ├── genvar_loop_decl_1.sv ├── genvar_loop_decl_1.ys ├── genvar_loop_decl_2.sv ├── genvar_loop_decl_2.ys ├── genvar_loop_decl_3.sv ├── genvar_loop_decl_3.ys ├── global_parameter.ys ├── hidden_decl.ys ├── ifdef_nest.ys ├── ifdef_unterminated.ys ├── include_self.v ├── include_self.ys ├── int_types.sv ├── int_types.ys ├── localparam_no_default_1.ys ├── localparam_no_default_2.ys ├── macro_arg_tromp.sv ├── macro_arg_tromp.ys ├── macro_unapplied.ys ├── macro_unapplied_newline.ys ├── mem_bounds.sv ├── mem_bounds.ys ├── module_end_label.ys ├── net_types.sv ├── net_types.ys ├── package_end_label.ys ├── package_task_func.sv ├── package_task_func.ys ├── param_int_types.sv ├── param_int_types.ys ├── param_no_default.sv ├── param_no_default.ys ├── param_no_default_not_svmode.ys ├── param_no_default_unbound_1.ys ├── param_no_default_unbound_2.ys ├── param_no_default_unbound_3.ys ├── param_no_default_unbound_4.ys ├── param_no_default_unbound_5.ys ├── parameters_across_files.ys ├── past_signedness.ys ├── port_int_types.sv ├── port_int_types.ys ├── prefix.sv ├── prefix.ys ├── roundtrip_proc.ys ├── run-test.sh ├── sign_array_query.ys ├── size_cast.sv ├── size_cast.ys ├── struct_access.sv ├── struct_access.ys ├── task_attr.ys ├── typedef_across_files.ys ├── typedef_const_shadow.sv ├── typedef_const_shadow.ys ├── typedef_legacy_conflict.ys ├── unbased_unsized.sv ├── unbased_unsized.ys ├── unbased_unsized_shift.sv ├── unbased_unsized_shift.ys ├── unbased_unsized_tern.sv ├── unbased_unsized_tern.ys ├── unmatched_else.ys ├── unmatched_elsif.ys ├── unmatched_endif.ys ├── unmatched_endif_2.ys ├── unnamed_block.ys ├── unnamed_genblk.sv ├── unnamed_genblk.ys ├── unreachable_case_sign.ys ├── upto.ys ├── void_func.ys ├── wire_and_var.sv └── wire_and_var.ys ├── vloghtb ├── .gitignore ├── common.sh ├── run-test.sh ├── test_febe.sh ├── test_makefile ├── test_mapopt.sh └── test_share.sh └── xprop ├── .gitignore ├── generate.py ├── run-test.sh └── test.py /.clang-format: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/comsec-group/cellift-yosys/HEAD/.clang-format -------------------------------------------------------------------------------- /.dockerignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/comsec-group/cellift-yosys/HEAD/.dockerignore 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