├── README.md ├── cpu ├── amd │ ├── family_10h-family_14h │ │ └── microcode_amd.bin │ └── family_15h │ │ └── microcode_amd_fam15h.bin ├── intel │ ├── LICENSE │ ├── microcode │ │ ├── microcode2bin.sh │ │ └── update-microcodes.sh │ ├── model_1066x │ │ └── microcode.bin │ ├── model_1067x │ │ └── microcode.bin │ ├── model_106ax │ │ └── microcode.bin │ ├── model_106cx │ │ └── microcode.bin │ ├── model_106dx │ │ └── microcode.bin │ ├── model_106ex │ │ └── microcode.bin │ ├── model_2065x │ │ └── microcode.bin │ ├── model_2066x │ │ └── microcode.bin │ ├── model_206ax │ │ └── microcode.bin │ ├── model_206cx │ │ └── microcode.bin │ ├── model_206dx │ │ └── microcode.bin │ ├── model_206ex │ │ └── microcode.bin │ ├── model_206fx │ │ └── microcode.bin │ ├── model_306ax │ │ └── microcode.bin │ ├── model_306cx │ │ └── microcode.bin │ ├── model_306dx │ │ └── microcode.bin │ ├── model_306ex │ │ └── microcode.bin │ ├── model_306fx │ │ └── microcode.bin │ ├── model_4065x │ │ └── microcode.bin │ ├── model_4066x │ │ └── microcode.bin │ ├── model_4067x │ │ └── microcode.bin │ ├── model_406ex │ │ └── microcode.bin │ ├── model_5065x │ │ └── microcode.bin │ ├── model_5066x │ │ └── microcode.bin │ ├── model_506cx │ │ └── microcode.bin │ ├── model_506ex │ │ └── microcode.bin │ ├── model_506fx │ │ └── microcode.bin │ ├── model_63x │ │ └── microcode.bin │ ├── model_65x │ │ └── microcode.bin │ ├── model_66x │ │ └── microcode.bin │ ├── model_67x │ │ └── microcode.bin │ ├── model_68x │ │ └── microcode.bin │ ├── model_69x │ │ └── microcode.bin │ ├── model_6ax │ │ └── microcode.bin │ ├── model_6bx │ │ └── microcode.bin │ ├── model_6dx │ │ └── microcode.bin │ ├── model_6ex │ │ └── microcode.bin │ ├── model_6fx │ │ └── microcode.bin │ ├── model_706ax │ │ └── microcode.bin │ ├── model_806ex │ │ └── microcode.bin │ ├── model_906ex │ │ └── microcode.bin │ ├── model_f0x │ │ └── microcode.bin │ ├── model_f1x │ │ └── microcode.bin │ ├── model_f2x │ │ └── microcode.bin │ ├── model_f3x │ │ └── microcode.bin │ ├── model_f4x │ │ └── microcode.bin │ ├── model_f6x │ │ └── microcode.bin │ └── stm │ │ ├── README.md │ │ ├── license.txt │ │ └── stm.bin ├── qualcomm │ ├── ipq40xx │ │ ├── cdt-AP.DK01.1-C1.bin │ │ ├── cdt.mbn │ │ ├── ddr.mbn │ │ ├── rpm.mbn │ │ ├── sbl.elf │ │ ├── tz.mbn │ │ └── tzbsp_no_xpu.mbn │ ├── ipq8064 │ │ ├── README │ │ └── sbls.bin │ └── ipq806x │ │ ├── README │ │ ├── cdt.mbn │ │ ├── ddr.mbn │ │ ├── rpm.mbn │ │ ├── tz.mbn │ │ └── uber-sbl.mbn ├── samsung │ ├── exynos5250 │ │ ├── bl1.bin │ │ └── update-bl1.sh │ └── exynos5420 │ │ └── bl1.bin └── via │ └── nano │ ├── microcode.bin │ └── microcode.h ├── mainboard ├── amd │ ├── bilby │ │ └── APCB_bilby.bin │ ├── majolica │ │ ├── APCB_CZN_D4.bin │ │ └── APCB_CZN_D4_DefaultRecovery.bin │ └── mandolin │ │ ├── APCB_cereme.bin │ │ └── APCB_mandolin.bin ├── facebook │ └── fbg1701 │ │ ├── descriptor.bin │ │ ├── license.txt │ │ └── me.bin ├── google │ ├── butterfly │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2130_coreboot.bin │ ├── guybrush │ │ ├── APCB_CZN_D4.bin │ │ ├── Release.txt │ │ └── TypeId0x55_SplTable_Prod_CZN_Chrome.sbin │ ├── kahlee │ │ ├── VBIOS_015_049_000_017.bin │ │ ├── VBIOS_015_049_000_018.bin │ │ ├── VBIOS_Release_Notes.txt │ │ ├── aleena │ │ │ ├── VBIOS_015_049_000_018.bin │ │ │ └── VBIOS_Release_Notes.txt │ │ ├── liara │ │ │ ├── VBIOS BRT39865 release note.txt │ │ │ └── VBIOS_BRT39865.001.bin │ │ └── license.txt │ ├── link │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2137.dat │ ├── parrot │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2130_coreboot.bin │ ├── skyrim │ │ ├── APCB_MDN_D5.bin │ │ ├── Release.txt │ │ ├── TypeId0x55_SplTableBl_MDN_CHROME.sbin │ │ └── TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin │ ├── stout │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2137.dat │ └── utils │ │ └── prepare_verstage_to_sign.sh ├── intel │ └── emeraldlake2 │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2120.dat ├── ocp │ └── tiogapass │ │ └── descriptor.bin ├── pcengines │ └── apu2 │ │ └── AGESA.bin ├── samsung │ ├── lumpy │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2130_coreboot.bin │ └── stumpy │ │ ├── descriptor.bin │ │ ├── me.bin │ │ └── snm_2124_coreboot.bin └── starlabs │ ├── Logo.bmp │ ├── MIT.md │ ├── README.md │ ├── cezanne │ └── starbook │ │ ├── README.md │ │ └── ec.bin │ └── starbook │ ├── adl │ ├── README.md │ └── ec.bin │ ├── cml │ ├── README.md │ └── ec.bin │ └── tgl │ ├── README.md │ └── ec.bin ├── northbridge ├── amd │ ├── 00630F01 │ │ ├── VBIOS.bin │ │ ├── VBIOS_Release_Notes.txt │ │ └── license.txt │ ├── 00660F01 │ │ ├── VBIOS.bin │ │ ├── VBIOS_Release_Notes.txt │ │ └── license.txt │ └── 00730F01 │ │ ├── VBIOS.bin │ │ ├── VBIOS_Release_Notes.txt │ │ └── license.txt └── intel │ └── sandybridge │ └── systemagent-r6.bin ├── pi └── amd │ ├── 00630F01 │ └── FP3 │ │ ├── AGESA.bin │ │ ├── AGESA_Release_Notes.txt │ │ └── license.txt │ ├── 00660F01 │ └── FP4 │ │ ├── AGESA.bin │ │ ├── AGESA_Release_Notes.txt │ │ └── license.txt │ ├── 00670F00 │ ├── FP4 │ │ ├── AGESA.bin │ │ ├── AGESA_Release_Notes.txt │ │ └── license.txt │ └── FT4 │ │ ├── AGESA.bin │ │ ├── AGESA_Release_Notes.txt │ │ └── license.txt │ └── 00730F01 │ └── FT3b │ ├── AGESA.bin │ ├── AGESA_Release_Notes.txt │ └── license.txt ├── soc ├── amd │ └── stoneyridge │ │ ├── PSP │ │ ├── AmdPubKeyST.bin │ │ ├── PspAgesaS3Resume_prod_ST.csbin │ │ ├── PspBootLoader_prod_ST.sbin │ │ ├── PspNvramS3_ST.bin │ │ ├── PspNvramST.bin │ │ ├── PspRecoveryBootLoader_prod_ST.sbin │ │ ├── PspSecureDebugST.Key │ │ ├── PspSecureOs_prod_ST.csbin │ │ ├── PspTrustlets_TPMver137_prod_ST.cbin │ │ ├── PspTrustlets_prod_ST.cbin │ │ ├── ReleaseNote.txt │ │ ├── RtmPubSignedST.key │ │ ├── SmuFirmware2_prod_ST.csbin │ │ ├── SmuFirmware2_prod_ST.sbin │ │ ├── SmuFirmware2_prod_ST_FN.csbin │ │ ├── SmuFirmware2_prod_ST_FN.sbin │ │ ├── SmuFirmwareST.sbin │ │ ├── SmuFirmwareST_FN.sbin │ │ ├── SmuFirmware_ST.csbin │ │ ├── SmuFirmware_ST_FN.csbin │ │ ├── SmuReleaseNotes.txt │ │ ├── SmuReleaseNotesST.txt │ │ ├── SmuReleaseNotesST_FN.txt │ │ ├── SmuScsST.bin │ │ ├── TrustletKey_prod_ST.sbin │ │ └── license.txt │ │ ├── VBIOS.bin │ │ ├── VBIOS_Release_Notes.txt │ │ ├── imc.bin │ │ ├── license.txt │ │ ├── vbios_license.txt │ │ └── xhci.bin ├── cavium │ └── cn81xx │ │ ├── LICENSE │ │ ├── README │ │ ├── VERSION │ │ └── bl31.elf ├── intel │ ├── baytrail │ │ ├── M0C3067_0000031E.h │ │ ├── microcode.bin │ │ └── microcode_blob.h │ ├── broadwell │ │ ├── microcode-M7240651_0000001C.h │ │ ├── microcode-MC0306D3_FFFF0010.h │ │ ├── microcode-MC0306D4_0000001F.h │ │ ├── microcode-MF2306D2_FFFF0009.h │ │ ├── microcode.bin │ │ └── microcode_blob.h │ └── quark │ │ ├── Fsp2_0 │ │ ├── DEBUG │ │ │ ├── FSP_M.fd │ │ │ ├── FSP_S.fd │ │ │ ├── FSP_T.fd │ │ │ └── QUARK.fd │ │ ├── Fsp.bsf │ │ ├── Include │ │ │ ├── FspUpd.h │ │ │ ├── FspmUpd.h │ │ │ ├── FspsUpd.h │ │ │ └── FsptUpd.h │ │ └── RELEASE │ │ │ ├── FSP_M.fd │ │ │ ├── FSP_S.fd │ │ │ ├── FSP_T.fd │ │ │ └── QUARK.fd │ │ ├── Fsp2_0Pei │ │ ├── DEBUG │ │ │ ├── FSP_M.fd │ │ │ ├── FSP_S.fd │ │ │ ├── FSP_T.fd │ │ │ └── QUARK.fd │ │ ├── Fsp.bsf │ │ ├── Include │ │ │ ├── FspUpd.h │ │ │ ├── FspmUpd.h │ │ │ ├── FspsUpd.h │ │ │ └── FsptUpd.h │ │ └── RELEASE │ │ │ ├── FSP_M.fd │ │ │ ├── FSP_S.fd │ │ │ ├── FSP_T.fd │ │ │ └── QUARK.fd │ │ ├── QuarkFsp.patch │ │ └── README.txt └── mediatek │ ├── mt8183 │ ├── README.md │ ├── dram.elf │ ├── dram.elf.md5 │ ├── dram_release_notes.txt │ ├── license.txt │ ├── pcm_allinone_lp4_3200.bin │ ├── pcm_allinone_lp4_3733.bin │ ├── spm_release_notes.txt │ ├── sspm.bin │ └── sspm_release_notes.txt │ ├── mt8186 │ ├── README.md │ ├── dram.elf │ ├── dram.elf.md5 │ ├── dram_release_notes.txt │ ├── license.txt │ ├── spm_firmware.bin │ ├── spm_firmware.bin.md5 │ ├── spm_release_notes.txt │ ├── sspm.bin │ ├── sspm.bin.md5 │ └── sspm_release_notes.txt │ ├── mt8188 │ ├── README.md │ ├── dpm.dm │ ├── dpm.dm.md5 │ ├── dpm.pm │ ├── dpm.pm.md5 │ ├── dpm_release_notes.txt │ ├── dram.elf │ ├── dram.elf.md5 │ ├── dram_release_notes.txt │ ├── license.txt │ ├── mcupm.bin │ ├── mcupm.bin.md5 │ ├── mcupm_release_notes.txt │ ├── spm_firmware.bin │ ├── spm_firmware.bin.md5 │ ├── spm_release_notes.txt │ ├── sspm.bin │ ├── sspm.bin.md5 │ └── sspm_release_notes.txt │ ├── mt8192 │ ├── README.md │ ├── dpm.dm │ ├── dpm.md5 │ ├── dpm.pm │ ├── dpm_release_notes.txt │ ├── dram.elf │ ├── dram.elf.md5 │ ├── dram_release_notes.txt │ ├── license.txt │ ├── mcupm.bin │ ├── mcupm.bin.md5 │ ├── mcupm_release_notes.txt │ ├── spm_firmware.bin │ ├── spm_firmware.bin.md5 │ ├── spm_release_notes.txt │ ├── sspm.bin │ ├── sspm.bin.md5 │ └── sspm_release_notes.txt │ └── mt8195 │ ├── README.md │ ├── dpm.dm │ ├── dpm.dm.md5 │ ├── dpm.pm │ ├── dpm.pm.md5 │ ├── dpm_release_notes.txt │ ├── dram.elf │ ├── dram.elf.md5 │ ├── dram_release_notes.txt │ ├── license.txt │ ├── mcupm.bin │ ├── mcupm.bin.md5 │ ├── mcupm_release_notes.txt │ ├── spm_firmware.bin │ ├── spm_firmware.bin.md5 │ ├── spm_release_notes.txt │ ├── sspm.bin │ ├── sspm.bin.md5 │ └── sspm_release_notes.txt └── southbridge └── amd ├── avalon ├── PSP │ ├── AmdPubKey.bin │ ├── PspBootLoader.Bypass.sbin │ ├── PspEarlyUnlock.sbin │ ├── PspNvram.bin │ ├── PspRecovery.sbin │ ├── PspReleaseNote.txt │ ├── PspSecureDebug.Key │ ├── PspSecureOs.sbin │ ├── RtmPubSigned.key │ ├── SmuFirmware.sbin │ ├── SmuScs.bin │ ├── Trustlet.tkn.cert │ ├── license.txt │ └── trustlets.bin ├── Release_AvalonXHC.txt ├── Release_IMC_Mullins.txt ├── imc.bin ├── license.txt └── xhci.bin ├── bolton ├── License.rtf ├── Release_IMC_Hudson2.txt ├── XHCI_Release_Notes.txt ├── imc.bin └── xhci.bin ├── hudson ├── License.rtf ├── Release_Hudson2XHC.txt ├── Release_IMC_Hudson2.txt ├── imc.bin └── xhci.bin ├── kern ├── PSP │ ├── AmdPubKeyCZ.bin │ ├── PspAgesaS3Resume_prod_CZ.csbin │ ├── PspBootLoader_prod_CZ.sbin │ ├── PspNvramCZ.bin │ ├── PspNvramS3_CZ.bin │ ├── PspRecoveryBootLoader_prod_CZ.sbin │ ├── PspSecureDebugCZ.Key │ ├── PspSecureOs_prod_CZ.csbin │ ├── PspTrustlets_prod_CZ.cbin │ ├── ReleaseNote.txt │ ├── RtmPubSignedCZ.key │ ├── SmuFirmware2_prod_CZ.sbin │ ├── SmuFirmwareCZ.sbin │ ├── SmuReleaseNotes.txt │ ├── SmuScsCZ.bin │ ├── TrustletKey_prod_CZ.sbin │ └── license.txt ├── imc.bin ├── license.txt └── xhci.bin └── yangtze ├── imc.bin └── xhci.bin /README.md: -------------------------------------------------------------------------------- 1 | # coreboot binary policy v1.0 2 | 3 | While coreboot attempts to be binary free, some coreboot mainboards require 4 | vendor binaries to support silicon and features. It is an unfortunate fact, 5 | as silicon has become more complicated, vendors are using more binaries to 6 | support their silicon. The coreboot community can not control the vendors, 7 | nor completely eliminate binaries, but it can set standards and expectations 8 | for vendor participation. coreboot needs policies and guidelines to meet GPL 9 | licence requirements and to organize and maintain standards within coreboot. 10 | 11 | To accept binaries in coreboot 3rdparty/blobs repository, **the binary 12 | must meet the following**: 13 | 14 | ## 1. A publicly available (published) ABI 15 | 16 | * In case of non-ISA binary, documented usage conventions are required 17 | * Examples: 18 | 19 | * The Intel® Firmware Support Package: External Architecture 20 | Specification v.1.0 21 | * The PCI firmware specification is the ABI for a standard PCI video BIOS. 22 | * Vendor microcode loading and placement instructions 23 | 24 | ## 2. Appropriate license (redistributable) 25 | 26 | The binary must be accompanied by a distribution license. The license 27 | must allow unlimited redistribution to allow coreboot contributors to 28 | create coreboot images for third parties which contain this and other blobs. 29 | 30 | ## 3. Linking 31 | 32 | Source code linked into coreboot may not be committed to the binary 33 | repository. Such source code and header files must be committed to the 34 | coreboot repository instead. 35 | 36 | ## 4. Binary version 37 | 38 | The binary must contain the version and how to extract the version must 39 | be published in the ABI 40 | 41 | ## 5. Release notes - updated with each version 42 | 43 | Each binary release must be accompanied by a release note that contains 44 | all of the following (if a field is unknown or unavailable, mark it as 45 | unknown or N/A): 46 | 47 | * version 48 | * release date 49 | * supported silicon 50 | * instructions, requirements, and dependencies 51 | * changes since the last version 52 | * errata, known issues 53 | * toolchain version(s), if applicable 54 | * ABI version and link to the published ABI (in the binary repository) 55 | 56 | ## 6. Good commit message 57 | 58 | The commit message should summarize the release note and contain 59 | any additional information that might be specific to coreboot. It is 60 | helpful to indicate how the binary was tested within coreboot and list 61 | any known exceptions or errata. 62 | -------------------------------------------------------------------------------- /cpu/amd/family_10h-family_14h/microcode_amd.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/cpu/amd/family_10h-family_14h/microcode_amd.bin -------------------------------------------------------------------------------- /cpu/amd/family_15h/microcode_amd_fam15h.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/cpu/amd/family_15h/microcode_amd_fam15h.bin -------------------------------------------------------------------------------- /cpu/intel/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2018 Intel Corporation. 2 | All rights reserved. 3 | 4 | Redistribution. 5 | 6 | Redistribution and use in binary form, without modification, are permitted, 7 | provided that the following conditions are met: 8 | 9 | 1. Redistributions must reproduce the above copyright notice and the 10 | following disclaimer in the documentation and/or other materials provided 11 | with the distribution. 12 | 13 | 2. Neither the name of Intel Corporation nor the names of its suppliers may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | 3. No reverse engineering, decompilation, or disassembly of this software 18 | is permitted. 19 | 20 | 21 | "Binary form" includes any format that is commonly used for electronic 22 | conveyance that is a reversible, bit-exact translation of binary 23 | representation to ASCII or ISO text, for example "uuencode". 24 | 25 | DISCLAIMER. 26 | 27 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 31 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 | POSSIBILITY OF SUCH DAMAGE. 38 | -------------------------------------------------------------------------------- /cpu/intel/microcode/microcode2bin.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # This file is part of the coreboot project. 4 | # 5 | # Copyright (C) 2015 Google Inc. 6 | # 7 | # All rights reserved. 8 | # 9 | # Redistribution and use in source and binary forms, with or without 10 | # modification, are permitted provided that the following conditions are met: 11 | # 12 | # 1. Redistributions of source code must retain the above copyright notice, 13 | # this list of conditions and the following disclaimer. 14 | # 15 | # 2. Redistributions in binary form must reproduce the above copyright notice, 16 | # this list of conditions and the following disclaimer in the documentation 17 | # and/or other materials provided with the distribution. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | # POSSIBILITY OF SUCH DAMAGE. 30 | # 31 | 32 | OLD=$(pwd) 33 | 34 | for UCODE in ../*/microcode.h 35 | do 36 | cd $(dirname $UCODE) 37 | cat > microcode.c << EOF 38 | #include 39 | unsigned int microcode[] = { 40 | #include "microcode.h" 41 | }; 42 | int main(void) 43 | { 44 | FILE *f = fopen("microcode.bin", "wb"); 45 | fwrite(microcode, sizeof(microcode), 1, f); 46 | fclose(f); 47 | return 0; 48 | 49 | } 50 | EOF 51 | gcc -o microcode microcode.c 52 | ./microcode 53 | rm microcode microcode.c 54 | cd $OLD 55 | done 56 | -------------------------------------------------------------------------------- /cpu/intel/microcode/update-microcodes.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # This file is part of the coreboot project. 4 | # 5 | # Copyright (C) 2007-2010 coresystems GmbH 6 | # 7 | # This program is free software; you can redistribute it and/or modify 8 | # it under the terms of the GNU General Public License as published by 9 | # the Free Software Foundation; version 2 of the License. 10 | # 11 | # This program is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with this program; if not, write to the Free Software 18 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 | # 20 | 21 | MICROCODE_VERSION=20180312 22 | MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz 23 | MICROCODE_FILE=microcode.dat 24 | INTEL_MICROCODE=http://downloadmirror.intel.com/27591/eng/$MICROCODE_ARCHIVE 25 | 26 | # 27 | # Getting Intel(R) Microcode 28 | # 29 | 30 | get_microcode() { 31 | printf "Getting microcode...\n" 32 | wget -nv $INTEL_MICROCODE 33 | tar xzf $MICROCODE_ARCHIVE 34 | } 35 | 36 | # 37 | # Creating separate files per microcode 38 | # 39 | 40 | separate_microcode() { 41 | printf "Separating microcode...\n" 42 | csplit -s -n4 -k $MICROCODE_FILE '/^\/\*.*\.inc.*\*\//' '{500}' 2> /dev/null 43 | mv xx0000 header.inc 44 | perl -pi -e 's,\ \ \ \ \ \ \ ,\ ,' header.inc 45 | perl -pi -e 's,^,/,g' header.inc 46 | perl -pi -e 's,^//\*,/\*,' header.inc 47 | for i in xx????; do 48 | name="`head -1 $i`" 49 | name=${name%??} 50 | name=${name:2} 51 | name=$( echo $name ) 52 | name=microcode-${name%.inc}.h 53 | cat header.inc $i > $name 54 | done 55 | rm -f xx???? header.inc 56 | } 57 | 58 | # 59 | # Dump CPUIDs from all separated files 60 | # 61 | 62 | dump_cpuids() { 63 | ls -1 microcode-*.h | while read F; do 64 | CPUID="$( echo $( head -36 $F |tail -1|cut -d, -f4|sed s,0x,, ) | sed 's/0*//')" 65 | echo "$CPUID:$F" 66 | done 67 | } 68 | 69 | # 70 | # Move microcode to target positions 71 | # 72 | 73 | move_microcode() { 74 | printf "Moving microcode...\n" 75 | 76 | # Empty out the microcode include headers 77 | for x in ../model_*/microcode.h; do echo > "$x"; done 78 | 79 | dump_cpuids | sort | while read N; do 80 | ID=$( echo $N | cut -d: -f1 ) 81 | F=$( echo $N | cut -d: -f2 ) 82 | 83 | if [ -d ../model_$ID ]; then 84 | echo "Model: $ID Microcode: $F" 85 | mv $F ../model_$ID/$F 86 | echo "#include \"$F\"" >> ../model_$ID/microcode.h 87 | else 88 | ID2=${ID%?}x 89 | if [ -d ../model_$ID2 ]; then 90 | echo "Model: $ID($ID2) Microcode: $F (copied)" 91 | mv $F ../model_$ID2/$F 92 | echo "#include \"$F\"" >> ../model_$ID2/microcode.h 93 | else 94 | ID1=${ID%??}xx 95 | if [ -d ../model_$ID1 ]; then 96 | echo "Model: $ID($ID1) Microcode: $F (copied)" 97 | mv $F ../model_$ID1/$F 98 | echo "#include \"$F\"" >> ../model_$ID1/microcode.h 99 | else 100 | echo "Model: $ID Microcode: $F (erased)" 101 | rm -f $F 102 | fi 103 | fi 104 | fi 105 | done 106 | } 107 | 108 | get_microcode 109 | separate_microcode 110 | move_microcode 111 | 112 | rm -f $MICROCODE_ARCHIVE 113 | rm -f $MICROCODE_FILE 114 | 115 | -------------------------------------------------------------------------------- /cpu/intel/model_1066x/microcode.bin: -------------------------------------------------------------------------------- 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17 | 18 | ## Instructions: 19 | 20 | This folder serves as the location for the stm.bin file. The developer 21 | can use the default stm.bin provided or replace it with one that has 22 | been custom built. The coreboot build system will look here for the 23 | STM binary when the STM has been configured. 24 | 25 | The default STM requires a MSEG of 4MB. If a smaller MSEG is used 26 | then the STM has to be custom built. Also, if a larger MSEG is 27 | configured, then the STM has to be custom built to take advantage 28 | of the additional memory. 29 | 30 | For version changes, issues, etc see the git repository. 31 | 32 | ## Toolchains: 33 | 34 | The STM can be built with either Microsoft Visual Studio or with CMAKE/GNU. 35 | 36 | ## ABI: 37 | 38 | This document defines both the firmware interface and the operating system 39 | interface with the STM: 40 | 41 | SMI Transfer Monitor (STM) User Guide, August 2015 42 | 43 | The above document can be obtained from firmware.intel.com. 44 | 45 | The STM-PE interface is defined in the Readme.STMPE file found on 46 | the stmpe branch of review.coreboot.org/STM. 47 | 48 | -------------------------------------------------------------------------------- /cpu/intel/stm/license.txt: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012, Intel Corporation. All rights reserved. 2 | 3 | Redistribution and use in source and binary forms, with or without 4 | modification, are permitted provided that the following conditions 5 | are met: 6 | 7 | * Redistributions of source code must retain the above copyright 8 | notice, this list of conditions and the following disclaimer. 9 | * Redistributions in binary form must reproduce the above copyright 10 | notice, this list of conditions and the following disclaimer in 11 | the documentation and/or other materials provided with the 12 | distribution. 13 | 14 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 15 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 16 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 17 | FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 18 | COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 19 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 | BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 | LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 | ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | POSSIBILITY OF SUCH DAMAGE. 26 | -------------------------------------------------------------------------------- /cpu/intel/stm/stm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/cpu/intel/stm/stm.bin -------------------------------------------------------------------------------- /cpu/qualcomm/ipq40xx/cdt-AP.DK01.1-C1.bin: -------------------------------------------------------------------------------- 1 | dummy 2 | -------------------------------------------------------------------------------- /cpu/qualcomm/ipq40xx/cdt.mbn: -------------------------------------------------------------------------------- 1 | dummy 2 | -------------------------------------------------------------------------------- /cpu/qualcomm/ipq40xx/ddr.mbn: -------------------------------------------------------------------------------- 1 | dummy 2 | -------------------------------------------------------------------------------- /cpu/qualcomm/ipq40xx/rpm.mbn: -------------------------------------------------------------------------------- 1 | dummy 2 | -------------------------------------------------------------------------------- /cpu/qualcomm/ipq40xx/sbl.elf: -------------------------------------------------------------------------------- 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the flash device and be 6 | * sure to back it up prior to overwriting it with a coreboot image. 7 | ******************************************************************************* 8 | 9 | -------------------------------------------------------------------------------- /cpu/qualcomm/ipq806x/README: -------------------------------------------------------------------------------- 1 | ******************************************************************************* 2 | * ATTENTION: The MBN files in cpu/qualcomm/ipq806x/*.mbn are placeholders. 3 | * These are NOT working IPQ806x binaries. 4 | * 5 | * Developers should maintain the IPQ806x files on the flash device and be 6 | * sure to back it up prior to overwriting it with a coreboot image. 7 | ******************************************************************************* 8 | 9 | -------------------------------------------------------------------------------- /cpu/qualcomm/ipq806x/cdt.mbn: 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GET THE ARCHIVE CONTAINING THIS FILE FROM http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r7.tbz2 2 | -------------------------------------------------------------------------------- /cpu/samsung/exynos5250/update-bl1.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | BL1_NAME="E5250.nbl1.bin" 4 | BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/" 5 | BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2" 6 | 7 | get_bl1() { 8 | mkdir -p "${BL1_PATH}" 9 | cd "${BL1_PATH}" 10 | wget "${BL1_URL}" -O bl1.tbz2 11 | tar jxvf bl1.tbz2 12 | mv "exynos-pre-boot/firmware/${BL1_NAME}" . 13 | rm -rf exynos-pre-boot 14 | if [ ! -e "${BL1_NAME}" ]; then 15 | echo "Error getting BL1" 16 | fi 17 | } 18 | 19 | main() { 20 | if [ ! -e ${BL1_PATH}/${BL1_NAME} ]; then 21 | get_bl1 22 | fi 23 | } 24 | 25 | set -e 26 | main "$@" 27 | -------------------------------------------------------------------------------- /cpu/samsung/exynos5420/bl1.bin: -------------------------------------------------------------------------------- 1 | Fake BL1. Get the current version (as of July 9 2013) from http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/peach_exynos-pre-boot-0.0.1-r3.tbz2 -------------------------------------------------------------------------------- /cpu/via/nano/microcode.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/cpu/via/nano/microcode.bin -------------------------------------------------------------------------------- /mainboard/amd/bilby/APCB_bilby.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/amd/bilby/APCB_bilby.bin -------------------------------------------------------------------------------- /mainboard/amd/majolica/APCB_CZN_D4.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/amd/majolica/APCB_CZN_D4.bin -------------------------------------------------------------------------------- /mainboard/amd/majolica/APCB_CZN_D4_DefaultRecovery.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/amd/majolica/APCB_CZN_D4_DefaultRecovery.bin -------------------------------------------------------------------------------- /mainboard/amd/mandolin/APCB_cereme.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/amd/mandolin/APCB_cereme.bin -------------------------------------------------------------------------------- /mainboard/amd/mandolin/APCB_mandolin.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/amd/mandolin/APCB_mandolin.bin -------------------------------------------------------------------------------- /mainboard/facebook/fbg1701/descriptor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/facebook/fbg1701/descriptor.bin -------------------------------------------------------------------------------- /mainboard/facebook/fbg1701/license.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/facebook/fbg1701/license.txt -------------------------------------------------------------------------------- /mainboard/facebook/fbg1701/me.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/facebook/fbg1701/me.bin -------------------------------------------------------------------------------- /mainboard/google/butterfly/descriptor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/butterfly/descriptor.bin -------------------------------------------------------------------------------- /mainboard/google/butterfly/me.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/butterfly/me.bin -------------------------------------------------------------------------------- /mainboard/google/butterfly/snm_2130_coreboot.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/butterfly/snm_2130_coreboot.bin -------------------------------------------------------------------------------- /mainboard/google/guybrush/APCB_CZN_D4.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/guybrush/APCB_CZN_D4.bin -------------------------------------------------------------------------------- /mainboard/google/guybrush/Release.txt: -------------------------------------------------------------------------------- 1 | Files: 2 | TypeId0x55_SplTable_Prod_CZN_Chrome.sbin - SPL for Guybrush 3 | 4 | Files: 5 | APCB_CZN_D4.bin - Data only - No license, ABI or Version # 6 | 7 | 2022-03-21: 8 | - Increase the number of SPD slots in APCB_CZN_D4.bin from 4 to 16 9 | Slots 0 - 3: 10 | lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A 11 | lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F 12 | lp4x-spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 13 | lp4x-spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B 14 | 15 | Slots 4 - 15: 16 | Place holder SPDs from Majolica 17 | 18 | 2021-04-05: 19 | - Fix UMAmode 20 | - Enable VBL/PSP to control eDP VDD. 21 | 22 | 2021-03-19: 23 | - Remove all debug output 24 | 25 | 2021-03-18: 26 | - Update DRQ routing 27 | 28 | 2021-03-11: Initial drop: 29 | - Add APCB_CZN_D4.bin 30 | This is a data file that gives configuration data to AMD's ABL, 31 | the PSP AGESA Bootloader. As there is no code, there is no ABI, 32 | license, or version number. 33 | 34 | Specified contents describing memory initialization: 35 | Memory is 2 channel, LPDDR4x 36 | 37 | The GPIOs to use for the SPD identifiers: 38 | Bit 0: GPIO 109 39 | Bit 1: GPIO 87 40 | Bit 2: GPIO 75 41 | Bit 3: GPIO 88 42 | 43 | SPDs from the guybrush platform: 44 | lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A 45 | lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F 46 | lp4x-spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 47 | All other GPIO IDs are unused. 48 | -------------------------------------------------------------------------------- /mainboard/google/guybrush/TypeId0x55_SplTable_Prod_CZN_Chrome.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/guybrush/TypeId0x55_SplTable_Prod_CZN_Chrome.sbin -------------------------------------------------------------------------------- /mainboard/google/kahlee/VBIOS_015_049_000_017.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/kahlee/VBIOS_015_049_000_017.bin -------------------------------------------------------------------------------- /mainboard/google/kahlee/VBIOS_015_049_000_018.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/kahlee/VBIOS_015_049_000_018.bin -------------------------------------------------------------------------------- /mainboard/google/kahlee/VBIOS_Release_Notes.txt: -------------------------------------------------------------------------------- 1 | ============================ ST 015.049.000.018 VBIOS release ======================================== 2 | Stoney generic Baseline VBIOS 015.049.000.018 3 | release date : 10/25/2018 4 | supported silicon : Stoney 5 | 6 | Changes: 7 | - Production release version (113-C91400-010) instead of debug version (113-C91400-X09) 8 | - No functional changes from 017 9 | 10 | ============================ ST 015.049.000.017 VBIOS release ======================================== 11 | Stoney generic Baseline VBIOS 015.049.000.017 12 | release date : 7/4/2018 13 | supported silicon : Stoney 14 | 15 | Major Changes included: 16 | 1. eDP HBR: Pre-emphasis increment=1,Swing increment = 8 17 | 2. DP RBR/HBR: Pre-emphasis increment=3,Swing increment = 1; 18 | 19 | errata, known issues : To pass the careena eDP compliance test 20 | ============================ Version information ======================================== 21 | To get the Version number, search the string “ATOMBIOSBK-AMD” from the binary, after that is the binary version number. 22 | Example: 23 | % strings VBIOS_*.bin | grep ATOMBIOSBK-AMD 24 | ATOMBIOSBK-AMD VER015.049.000.017.000000 25 | ATOMBIOSBK-AMD VER015.049.000.018.000000 26 | -------------------------------------------------------------------------------- /mainboard/google/kahlee/aleena/VBIOS_015_049_000_018.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/kahlee/aleena/VBIOS_015_049_000_018.bin -------------------------------------------------------------------------------- /mainboard/google/kahlee/aleena/VBIOS_Release_Notes.txt: -------------------------------------------------------------------------------- 1 | =========================== Aleena Stoney VBIOS BRT39459 release ====================================== 2 | Aleena Stoney VBIOS BRT39459 3 | BRT39459.001 11/27/18,03:10:27 CL#1712289 @ 15.49.0.18 ATOMBuild#435785 4 | 5 | Major Changes included: 6 | 1. Change register UNIPHY_TMDP_REG3_TMDP_EDP_HIGH_VDIFF_CLK2_AND_PL0_VL0_VAL to 0x250d8001 7 | 2. Change register UNIPHY_TX_CONTROL3_TMDP_EDP_HIGH_VDIFF_CLK2_AND_PL0_VL0_VAL to 0x09000000 8 | 9 | =========================== Aleena Stoney VBIOS BRT39201 release ====================================== 10 | Aleena Stoney VBIOS BRT39201 11 | BRT39201.001 11/21/18,03:43:46 CL#1709986 @ 15.49.0.18 ATOMBuild#435327 12 | 13 | Major Changes included: 14 | 1. First Stoney VBIOS released to Aleena w/ eDP SI tuning result. 15 | -------------------------------------------------------------------------------- /mainboard/google/kahlee/liara/ VBIOS BRT39865 release note.txt: -------------------------------------------------------------------------------- 1 | =========================== Liara Chromebook Stoney VBIOS BRT39865 release ====================================== 2 | Liara Chromebook Stoney VBIOS BRT39865 3 | BRT39865.001 12/05/18,01:13:54 CL#1716128 @ 15.49.0.18 ATOMBuild#436504 4 | 5 | Major Changes included: 6 | 1. First Stoney VBIOS released to Liara update eDP power up sequence. -------------------------------------------------------------------------------- /mainboard/google/kahlee/liara/VBIOS_BRT39865.001.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/kahlee/liara/VBIOS_BRT39865.001.bin -------------------------------------------------------------------------------- /mainboard/google/link/descriptor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/link/descriptor.bin -------------------------------------------------------------------------------- /mainboard/google/link/me.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/link/me.bin -------------------------------------------------------------------------------- /mainboard/google/link/snm_2137.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/link/snm_2137.dat -------------------------------------------------------------------------------- /mainboard/google/parrot/descriptor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/parrot/descriptor.bin -------------------------------------------------------------------------------- /mainboard/google/parrot/me.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/parrot/me.bin -------------------------------------------------------------------------------- /mainboard/google/parrot/snm_2130_coreboot.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/parrot/snm_2130_coreboot.bin -------------------------------------------------------------------------------- /mainboard/google/skyrim/APCB_MDN_D5.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/skyrim/APCB_MDN_D5.bin -------------------------------------------------------------------------------- /mainboard/google/skyrim/Release.txt: -------------------------------------------------------------------------------- 1 | Files: 2 | APCB_MDN_D5.bin - Data only - No license, ABI or Version # 3 | TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin - Data only, no license 4 | TypeId0x55_SplTableBl_MDN_CHROME.sbin - Data only, no license 5 | 6 | 2022-12-12: Initial release of the ChromeOS RO SPL table 7 | 8 | SPL/SVN - Security Patch level / Security Version Number 9 | A version number used to prevent Rollback attacks. 10 | Software updates with an SVN lower than the currently installed SVN 11 | are not permitted. 12 | 13 | * Version: 3c.03.12 14 | * Release Date: 2022-09-25 15 | * Supported Silicon: AMD Mendocino 16 | * Requirements/dependencies: None 17 | * Errata: None 18 | 19 | Versioned Chip Endorsement Key (VCEK) Certificate and KDS Interface 20 | Specification 21 | Document # 57230 Rev. 0.50 October 2021 22 | https://web.archive.org/web/20221213033802/https://www.amd.com/system/files/TechDocs/57230.pdf 23 | 24 | 25 | 2022-09-27: Initial release of the ChromeOS RW SPL table 26 | 27 | * Version: 3c.03.12 28 | * Release Date: 2022-09-25 29 | * Supported Silicon: AMD Mendocino 30 | * Requirements/dependencies: None 31 | * Errata: None 32 | 33 | 2022-09-02: Initial public release: 34 | - Add APCB_MDN_D5.bin 35 | This is a data file that gives configuration data to AMD's ABL, 36 | the PSP AGESA Bootloader. As there is no code, there is no ABI, 37 | license, or version number. 38 | 39 | Specified contents describing memory initialization: 40 | Memory is 2 channel, LPDDR5/LPDDR5x 41 | 42 | The GPIOs to use for the SPD identifiers: 43 | Bit 0: GPIO 144 44 | Bit 1: GPIO 85 45 | Bit 2: GPIO 79 46 | Bit 3: GPIO 91 47 | 48 | Contains 16 slots for possible SPD entries. 49 | UMA size is set to 64MB. 50 | eSPI I/O range address and size configuration. 51 | MEMRESTORECTL is enabled to leverage MRC Cache. 52 | 53 | sha1sum: 54 | a91237472d662b8035450e19f118adaece4748f4 APCB_MDN_D5.bin 55 | e66c4ace7fa13913d2147016a7a0544b9f52de61 TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin 56 | c761d0c9386f302ea50fefd8762b1b4c85df117b TypeId0x55_SplTableBl_MDN_CHROME.sbin 57 | -------------------------------------------------------------------------------- /mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME.sbin -------------------------------------------------------------------------------- /mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/skyrim/TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin -------------------------------------------------------------------------------- /mainboard/google/stout/descriptor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/stout/descriptor.bin -------------------------------------------------------------------------------- /mainboard/google/stout/me.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/stout/me.bin -------------------------------------------------------------------------------- /mainboard/google/stout/snm_2137.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/google/stout/snm_2137.dat -------------------------------------------------------------------------------- /mainboard/google/utils/prepare_verstage_to_sign.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Copyright 2023 The Chromium OS Authors. All rights reserved. 3 | # Use of this source code is governed by a BSD-style license that can be 4 | # found in the LICENSE file. 5 | 6 | # Abort on error. 7 | set -eu -o pipefail 8 | 9 | # Extract program name for usage instructions. 10 | PROG="$(basename "$0")" 11 | 12 | usage() { 13 | cat < 15 | 16 | For detail, reference the AMD documentation titled "OEM PSP VERSTAGE BL FW Signing 17 | Key Pair Generation and Certificate Request Process" - 18 | http://dr/corp/drive/folders/1ySJyDgbH73W1lqrhxMvM9UYl5TtJt_mw. This document 19 | is Google internal only and is under NDA. This document is loosely based on the 20 | "AMD BIOS Signing Key Pair Generation and Certificate Request Process Document 21 | (id: 56535)" from AMD devhub. 22 | 23 | EOF 24 | 25 | if [[ $# -ne 0 ]]; then 26 | echo "$*" >&2 27 | exit 1 28 | else 29 | exit 0 30 | fi 31 | } 32 | 33 | die() { 34 | echo "$*" >&2 35 | exit 1 36 | } 37 | 38 | # Check the arguments to make sure we have the correct number. 39 | if [[ $# -ne 3 ]]; then 40 | usage "Error: Incorrect number of arguments" 41 | fi 42 | 43 | write_byte() { 44 | local position="$1" 45 | local value="$2" 46 | local file="$3" 47 | 48 | echo -n -e "\x${value}" | 49 | dd of="${file}" bs=1 count=1 seek="${position}" conv=notrunc status=none 50 | } 51 | 52 | write_dword_le() { 53 | local -i position="$1" 54 | local value 55 | value="$(printf "%08x" "$2")" 56 | local file="$3" 57 | 58 | write_byte $((position)) "${value:6:2}" "${file}" 59 | write_byte $((position + 1)) "${value:4:2}" "${file}" 60 | write_byte $((position + 2)) "${value:2:2}" "${file}" 61 | write_byte $((position + 3)) "${value:0:2}" "${file}" 62 | } 63 | 64 | copy_key_id() { 65 | local input_file="$1" 66 | local -i input_offset="$2" 67 | local output_file="$3" 68 | local -i output_offset="$4" 69 | local -i id_size=16 70 | 71 | dd if="${input_file}" skip="${input_offset}" \ 72 | of="${output_file}" seek="${output_offset}" \ 73 | bs=1 count="${id_size}" conv=notrunc status=none 74 | } 75 | 76 | main() { 77 | local input_firmware="$1" 78 | local amd_key="$2" 79 | local output_firmware="$3" 80 | 81 | if [[ "${input_firmware}" == "${output_firmware}" ]]; then 82 | usage "Error: input and output files must not be the same" 83 | fi 84 | 85 | if [[ ! -e "${input_firmware}" || ! -e "${amd_key}" ]]; then 86 | usage "Error: either input or amd_key does not exist" 87 | fi 88 | 89 | local -i sig_size=256 # RSA2048 signature size 90 | local -i fw_size 91 | local -i image_size 92 | local -i header_size=256 # AMDFW header size 93 | local -i signed_fw_size 94 | local -i unsigned_fw_size 95 | local -i signed_fw_minus_header_size 96 | 97 | fw_size="$(stat -c %s "${input_firmware}")" 98 | image_size="$((fw_size + sig_size))" 99 | # Search for PSP_FOOTER_DATA in psp_verstage binary. On boards with CBFS_VERIFICATION 100 | # enabled, metadata hash anchor follows PSP_FOOTER_DATA and is excluded from signing. 101 | local -a psp_footer_matches 102 | readarray -t psp_footer_matches < <( 103 | od -v --address-radix=d -t x4 --width=64 "${input_firmware}" | \ 104 | awk '/[[:digit:]]+( 9{8}){16}$/ {print ($1 + 64)}' 105 | ) 106 | if [[ "${#psp_footer_matches[@]}" -ne 1 ]]; then 107 | die "Multiple PSP Footer matches" 108 | fi 109 | signed_fw_size="${psp_footer_matches[0]}" 110 | if [[ "${signed_fw_size}" -le "${header_size}" ]]; then 111 | die "PSP Footer Data unexpectedly inside header!!!" 112 | fi 113 | signed_fw_minus_header_size="$((signed_fw_size - header_size))" 114 | unsigned_fw_size="$((fw_size - signed_fw_size))" 115 | 116 | dd if="${input_firmware}" of="${output_firmware}" bs=1 count="${signed_fw_size}" status=none 117 | 118 | # Since the header is also part of the signed binary, update the required fields before 119 | # signing. Refer to Appendix D in the AMD BIOS Signing Key Pair and Certification Process 120 | # document for what needs to be changed in the psp_verstage header. 121 | write_dword_le "0x14" "${signed_fw_minus_header_size}" "${output_firmware}" 122 | # Set the signed flag in the header 123 | write_dword_le "0x30" "1" "${output_firmware}" 124 | write_dword_le "0x6c" "${image_size}" "${output_firmware}" 125 | write_dword_le "0x70" "${unsigned_fw_size}" "${output_firmware}" 126 | copy_key_id "${amd_key}" "0x04" "${output_firmware}" "0x38" 127 | 128 | echo "Finished preparing PSP Verstage for signing" 129 | } 130 | 131 | main "$@" 132 | -------------------------------------------------------------------------------- /mainboard/intel/emeraldlake2/descriptor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/intel/emeraldlake2/descriptor.bin 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associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 4 | 5 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 8 | -------------------------------------------------------------------------------- /mainboard/starlabs/README.md: -------------------------------------------------------------------------------- 1 | This project has mixed licencing. You are free to copy, redistribute and/or modify aspects of this work under the terms of each licence accordingly (unless otherwise specified). 2 | 3 | Graphical assets (any and all source `.svg` files or rendered `.png` or `.bmp` files) are licensed under the terms of the [Creative Commons Attribution-ShareAlike 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/). 4 | 5 | Any and all `ec.bin` files are licensed under the terms of the [MIT License](MIT.md). This applies only to the firmware binary. The source code is proprietary and not available for customer use. 6 | 7 | -------------------------------------------------------------------------------- /mainboard/starlabs/cezanne/starbook/README.md: -------------------------------------------------------------------------------- 1 | This is the firmware binary for the ITE embedded controller used in the StarBook Mk VI. The embedded controller 2 | controls all the low level function in the laptop like switches, keyboard and power. 3 | 4 | It is licensed under the [MIT License](../../MIT.md), and as such, the source code is not available. 5 | 6 | ## **StarBook**[MkVI-AMD](https://github.com/StarLabsLtd/firmware/tree/master/StarBook/MkVI-AMD) 7 | #### ITE128: [1.02](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkVI-AMD/ITE128/1.02/efi-B6-A.zip) (2022-10-28) 8 | > Modified the F10 scan code for better compatibility 9 | > Modified the F12 scan code for better compatibility 10 | > Initialised the Keyboard Backlight from the EC to avoid problems when switching branch 11 | 12 | #### ITE128: [1.01](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkVI-AMD/ITE128/1.01/efi-B6-A.zip) (2022-10-28) 13 | > Fix the backlight helper to remember the last state 14 | > Modified the scan code of the sysreq key 15 | 16 | #### ITE128: [1.00](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkVI-AMD/ITE128/1.00/efi-B6-A.zip) (2022-10-28) 17 | > Initial release EC firmware for the StarBook Mk VI 18 | 19 | -------------------------------------------------------------------------------- /mainboard/starlabs/cezanne/starbook/ec.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/starlabs/cezanne/starbook/ec.bin -------------------------------------------------------------------------------- /mainboard/starlabs/starbook/adl/README.md: -------------------------------------------------------------------------------- 1 | This is the firmware binary for the ITE embedded controller used in the StarBook Mk VI. The embedded controller 2 | controls all the low level function in the laptop like switches, keyboard and power. 3 | 4 | It is licensed under the [MIT License](../../MIT.md), and as such, the source code is not available. 5 | 6 | #### ITE128: [1.01](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkVI-Intel/ITE128/1.01/efi-B6-I.zip) (2022-10-28) 7 | > Enabled hybrid power; when using a charger that doesn't supply enough power, 8 | > the battery will also power the laptop. This will only happen if the battery 9 | > is charged to 15% or more. 10 | 11 | #### ITE128: [1.00](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkV/ITE128/1.00/efi-B5.zip) (2021-10-08) 12 | > Initial release firmware for the StarBook Mk VI 13 | -------------------------------------------------------------------------------- /mainboard/starlabs/starbook/adl/ec.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/starlabs/starbook/adl/ec.bin -------------------------------------------------------------------------------- /mainboard/starlabs/starbook/cml/README.md: -------------------------------------------------------------------------------- 1 | This is the firmware binary for the ITE embedded controller used in the StarLabTop Mk IV. The embedded controller 2 | controls all the low level function in the laptop like switches, keyboard and power. 3 | 4 | It is licensed under the [MIT License](../../MIT.md), and as such, the source code is not available. 5 | 6 | #### ITE: [1.07](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.07/efi-L4.zip) (2021-09-29) 7 | > Add support to set the maximum charge level of the battery 8 | 9 | #### ITE: [1.06](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.06/efi-L4.zip) (2021-09-22) 10 | > Add Q Event for Touchpad State which allows it to be saved on reboot 11 | 12 | #### ITE: [1.05](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.05/efi-L4.zip) (2021-09-22) 13 | > Updated power configuration 14 | > Use battery power when charger doesn't supply enough 15 | 16 | #### ITE: [1.04](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.04/efi-L4.zip) (2021-09-22) 17 | > Function lock state remembered between reboots 18 | 19 | #### ITE: [1.03](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.03/efi-L4.zip) (2021-09-22) 20 | > Updated fan curve 21 | 22 | #### ITE: [1.02](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.02/efi-L4.zip) (2021-09-22) 23 | > Updated fan curve 24 | 25 | #### ITE: [1.01](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.01/efi-L4.zip) (2021-09-22) 26 | > Updated fan curve 27 | > Updated Fn binding at post 28 | 29 | #### ITE: [1.00](https://github.com/StarLabsLtd/firmware/raw/master/StarLabTop/MkIV/ITE/1.00/efi-L4.zip) (2021-09-22) 30 | > Initial release firmware for the StarLabTop Mk IV 31 | -------------------------------------------------------------------------------- /mainboard/starlabs/starbook/cml/ec.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/starlabs/starbook/cml/ec.bin -------------------------------------------------------------------------------- /mainboard/starlabs/starbook/tgl/README.md: -------------------------------------------------------------------------------- 1 | This is the firmware binary for the ITE embedded controller used in the StarBook Mk V. The embedded controller 2 | controls all the low level function in the laptop like switches, keyboard and power. 3 | 4 | It is licensed under the [MIT License](../../MIT.md), and as such, the source code is not available. 5 | 6 | #### ITE128: [1.03](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkV/ITE128/1.03/efi-B5.zip) (2021-12-22) 7 | > Fixed issue where keyboard backlight wouldn't turn off when entering S3 or turning off 8 | 9 | #### ITE128: [1.02](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkV/ITE128/1.02/efi-B5.zip) (2021-12-10) 10 | > Update Normal and Quiet fan curves to delay start until 65 degree's. Performance mode is unchanged. 11 | 12 | #### ITE128: [1.01](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkV/ITE128/1.01/efi-B5.zip) (2021-10-08) 13 | > Added support to select maximum charge percentage 14 | 15 | #### ITE128: [1.00](https://github.com/StarLabsLtd/firmware/raw/master/StarBook/MkV/ITE128/1.00/efi-B5.zip) (2021-10-08) 16 | > Initial release firmware for the StarBook Mk V 17 | -------------------------------------------------------------------------------- /mainboard/starlabs/starbook/tgl/ec.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/mainboard/starlabs/starbook/tgl/ec.bin -------------------------------------------------------------------------------- /northbridge/amd/00630F01/VBIOS.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/northbridge/amd/00630F01/VBIOS.bin -------------------------------------------------------------------------------- /northbridge/amd/00630F01/VBIOS_Release_Notes.txt: -------------------------------------------------------------------------------- 1 | ============================ 102 VBIOS release ======================================== 2 | 3 | Kaveri generic Baseline VBIOS 102 4 | Spectre A11 0x1304 105-c45300-000 AMDSpectreGenericVbios.102 02/03/14,12:14:55 1003805@VER015.041.000.002.000000 ATOMBuild #285239 5 | 6 | Changes include: 7 | CL1003465 - EPR #392854 - [KV][Realtek][Kaveri Mobile] Triggering a TDR on LVDS REALTEK causes screen to go blank. 8 | 9 | ============================ 101 VBIOS release ======================================== 10 | 11 | Kaveri generic Baseline VBIOS 101 12 | Spectre A11 0x1304 105-c45300-000 AMDSpectreGenericVbios.101 01/03/14,17:42:37 993494@VER015.041.000.001.000000 ATOMBuild #282316 13 | 14 | Changes include: 15 | CL993491 - OBS428719 - eDP backlight sequence T15&T16 issue. 16 | 17 | ============================ 100 VBIOS release ======================================== 18 | 19 | Kaveri generic Baseline VBIOS 100 20 | Spectre A11 0x1304 105-c45300-000 AMDSpectreGenericVbios.100 12/05/13,16:27:24 984074@15.41.0.0 ATOMBuild #279841 21 | 22 | Changes include: 23 | no change, update the Vbios bring up revisio number 0xx to production revision number 100. 24 | 25 | -------------------------------------------------------------------------------- /northbridge/amd/00660F01/VBIOS.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/northbridge/amd/00660F01/VBIOS.bin -------------------------------------------------------------------------------- /northbridge/amd/00730F01/VBIOS.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/northbridge/amd/00730F01/VBIOS.bin -------------------------------------------------------------------------------- /northbridge/amd/00730F01/VBIOS_Release_Notes.txt: -------------------------------------------------------------------------------- 1 | 2 | Release Notes for Mullins VBIOS 3 | ------------------------------- 4 | Ref board: Discovery 105-C69300-00, Asic: Godavari 5 | 6 | 7 | ==================================================================================== 8 | Version : V100 Release Date: Jan 7 2014 9 | File :MullinsGenericVbios.bin 10 | Code rev: 15.42.0.2 ATOMBuild #282578 11 | ------------------------------------------------------------------------------------ 12 | 1.Rev up to V100 to indicate it is start of production version 13 | 2.EPR#010003 : OBS428719 - eDP backlight sequence T15&T16 issue 14 | 15 | -------------------------------------------------------------------------------- /northbridge/intel/sandybridge/systemagent-r6.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/northbridge/intel/sandybridge/systemagent-r6.bin -------------------------------------------------------------------------------- /pi/amd/00630F01/FP3/AGESA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/pi/amd/00630F01/FP3/AGESA.bin -------------------------------------------------------------------------------- /pi/amd/00660F01/FP4/AGESA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/pi/amd/00660F01/FP4/AGESA.bin -------------------------------------------------------------------------------- /pi/amd/00660F01/FP4/AGESA_Release_Notes.txt: -------------------------------------------------------------------------------- 1 |  Binary PI Release Notes for 2 | ----------------- 3 | Merlin Falcon (Carrizo) Platform Initialization (CarrizoPI) 4 | 5 | 6 | ============================================================================= 7 | AGESA PI Version: 1.1.0.1 Test Board: Bettong Alfa, Beta 8 | Binary PI version: 1.5 Binary PI Build Date: Aug. 5 2015 9 | ============================================================================= 10 | 1. Update CarrizoPI to Version 1.1.0.1 11 | 12 | ============================================================================= 13 | AGESA PI Version: 1.1.0.0 Test Board: Bettong Alfa, Beta 14 | Binary PI version: 1.4 Binary PI Build Date: Jul. 10 2015 15 | ============================================================================= 16 | 1. Update CarrizoPI to Version 1.1.0.0 17 | 2. CarrizoPI 1.1.0.0 support DDR4 18 | 19 | ============================================================================= 20 | AGESA PI Version: 1.0.0.7 Test Board: Bettong Alfa 21 | Binary PI version: 1.3 Binary PI Build Date: Jun. 26 2015 22 | ============================================================================= 23 | 1. Add NB PState support 24 | 1) Add two macros in buildOpts.c 25 | BLDCFG_PLATFORM_CPB_MODE and BLDCFG_NB_PSTATES_SUPPORTED 26 | 2) Add GnbSmuServiceRequestV8 27 | This function is commented out before. This is necessary for NB PState, 28 | so add it back. 29 | 2. Add FchSetSpi back 30 | 3. Skip CF9 warm reset in FchInitResetHwAcpiP 31 | Bug found (18Jun15) with ZE880PAAY4382 OPN, 50% hang rate in early POST 32 | due to "unnecessary reset" too close to power-on (<90ms). 33 | Resolution: "Remove unnecessary reset to fix the hang" 34 | 35 | ============================================================================= 36 | AGESA PI Version: 1.0.0.7 Test Board: Bettong Alfa 37 | Binary PI version: 1.2 Binary PI Build Date: May 29 2015 38 | ============================================================================= 39 | 1. Update header files. 40 | Update header files according commit d82006ea 41 | 2. The AGESA.bin is the same as Binary PI version 1.1 42 | 43 | ============================================================================= 44 | AGESA PI Version: 1.0.0.7 Test Board: Bettong Alfa 45 | Binary PI version: 1.1 Binary PI Build Date: May 29 2015 46 | ============================================================================= 47 | 1. Update to CarrizoPI version 1.0.0.7 48 | 49 | ============================================================================= 50 | AGESA PI Version: 1.0.0.2 Test Board: Bettong Alfa 51 | Binary PI version: 1.0 Binary PI Build Date: May 19 2015 52 | ============================================================================= 53 | 1. Support 2133MHz dimm and enable 35W TDP 54 | Add two macros in buildOpts.c 55 | #define BLDCFG_SYSTEM_CONFIGURATION 2 56 | #define BLDCFG_AMD_TDP_LIMIT 35000 57 | 2. Enable HDMI audio 58 | Add a macro in buildOpts.c 59 | #define BLDCFG_CFG_GNB_HD_AUDIO TRUE 60 | 3. Add PSP initialization code 61 | Add PspMboxBiosCmdDramInfo in AmdInitEnv 62 | Add PspMboxBiosCmdExitBootServices in AmdInitLate 63 | 4. Pull up GPIO86 (use SSD) and GPIO64 (enable network adapter) 64 | add a gpio array "merlin_falcon_gpio" to pull up GPIO86 and GPIO64, 65 | then add a macro in buildOpts.c 66 | #define BLDCFG_FCH_GPIO_CONTROL_LIST (&merlin_falcon_gpio[0]) 67 | This can be override by oem_bettong_gpio in src/mainboard/amd/bettong/BiosCallOuts.c 68 | -------------------------------------------------------------------------------- /pi/amd/00670F00/FP4/AGESA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/pi/amd/00670F00/FP4/AGESA.bin -------------------------------------------------------------------------------- /pi/amd/00670F00/FT4/AGESA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/pi/amd/00670F00/FT4/AGESA.bin -------------------------------------------------------------------------------- /pi/amd/00730F01/FT3b/AGESA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/pi/amd/00730F01/FT3b/AGESA.bin -------------------------------------------------------------------------------- /pi/amd/00730F01/FT3b/AGESA_Release_Notes.txt: -------------------------------------------------------------------------------- 1 | 2 | Release Notes for 3 | ----------------- 4 | Mullins Platform Initialization (MullinsPI) 5 | 6 | ============================================================================= 7 | 8 | coreboot usage information: 9 | 10 | AGESA source (binary PI) ---> 11 | (3rdparty/pi/amd/00730F01) AGESA PI directory path 12 | (FT3b/AGESA.bin) AGESA PI binary file name 13 | (0xFFE00000) AGESA PI binary address in ROM 14 | 15 | config MMCONF_BASE_ADDRESS 16 | hex 17 | default 0xF8000000 18 | 19 | config MMCONF_BUS_NUMBER 20 | int 21 | default 64 22 | 23 | ============================================================================= 24 | 25 | MullinsPI Version: 1.0.0.A Release Date: July 2015 26 | BinaryPI Version: 1.1 Build date: Aug. 25 2015 27 | Built by coreboot toolchain v1.27 March 8th, 2015 28 | Test Board: Olive Hill Plus 29 | 30 | ============================================================================= 31 | - Update to MullinsPI 1.0.0.A 32 | - BUG465142: ECC error injection fails 33 | 34 | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.9: 35 | 36 | - BUG466307: PSP Trustlets is not updated properly 37 | 38 | 39 | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.8: 40 | 41 | - ENH466202: PSP FW stack version D.1.1.4D 42 | - ENH460470: Remove the PSP DEBUG info to fix system hanging issue 43 | - PLAT-986: Initial iTpmControlArea to avoid potential exception 44 | - ENH465927: Enable MMIO decode in iTpmGetResponse 45 | 46 | 47 | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.7: 48 | 49 | - ENH465438: Add SMBIOS support for Sempron part 50 | - ENH465709: PSP FW stack version D.1.1.4A 51 | - ENH465474: SMU_Firmware_14_33 52 | 53 | 54 | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.6: 55 | 56 | - ENH465011: PSP FW stack version D.1.1.47 57 | - BUG463002: SATA hardware revision ID gets overwritten 58 | - ENH463253: LAN performance data(Auto negotiation/1000M) 59 | 60 | 61 | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.5: 62 | 63 | - ENH464327: PSP FW stack version D.1.1.42 64 | - ENH463121: AGESA Memory Option for JEDEC DDR3/DDR4 SPD MAC 65 | - BUG455965: System hangs at PC02FF when GFX card(Asic type: Topaz) plugged in 66 | - ENH462603: Enable SRT only when the platform really needs to run > 85C 67 | 68 | 69 | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.4: 70 | 71 | - ENH462390: PSP FW stack version D.1.1.36 72 | - ENH457952: Publish PSP fTPM ready PPI 73 | - BUG460543: ECC lane fails training 74 | - BUG458825: Typo in dec file 75 | - ENH455439: Save & Restore PSP Bar3 related register for S3 76 | - BUG458331: Correct Size mismatch of create the recovery guid Hob 77 | - ENH455923: Update ALIB to support Windows XP 78 | - ENH454744: Save Restore FakeSMI related registers for S3 79 | 80 | ============================================================================= 81 | 82 | ============================================================================= 83 | 84 | MullinsPI Version: 1.0.0.4 Release Date: Jun. 25 2015 85 | BinaryPI Version: 1.0 86 | 87 | ============================================================================= 88 | From this commit we use two version numbers to identify binary PI: 89 | MullinsPI Version is the AGESA version. This is the same as original 90 | MullinsPI. 91 | BinaryPI Version is the AGESA.bin version. We will change this version when 92 | we upload new AGESA.bin. 93 | 94 | - Add PspMboxBiosCmdDramInfo and PspMboxBiosCmdExitBootServices to fix 95 | Windows 7 hang after graphics driver installed. 96 | 97 | ============================================================================= 98 | -------------------------------------------------------------------------------- /soc/amd/stoneyridge/PSP/AmdPubKeyST.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin -------------------------------------------------------------------------------- /soc/amd/stoneyridge/PSP/PspAgesaS3Resume_prod_ST.csbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/amd/stoneyridge/PSP/PspAgesaS3Resume_prod_ST.csbin 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VBIOS 006 3 | Stoney A11 0x98E0 109-C91420-00A StoneyGenericVbios.006 02/22/16,01:31:08 CL#1239056 @15.49.0.12 ATOMBuild #339175 4 | 5 | Major Changes included: 6 | 1. Update TMDP_DP golden setting refert to STONEY_TMDP_DP_new(requested by Connie). 7 | 8 | ============================ ST 005 VBIOS release ======================================== 9 | Stoney generic Baseline VBIOS 005 10 | Stoney A11 0x98E0 109-C91420-00A StoneyGenericVbios.005 12/21/15,12:48:54 CL#1222685 @15.49.0.11 ATOMBuild #335602 11 | 12 | Major Changes included: 13 | 1. To align with the GOP driver behavior that just turn on one available display device when POST, 14 | if no available display device, use default available devices as DOS request devices (DFP1). 15 | 16 | ============================ ST 004 VBIOS release ======================================== 17 | Stoney generic Baseline VBIOS 004 18 | Stoney A11 0x98E0 109-C91420-00A StoneyGenericVbios.004 11/02/15,02:58:13 CL#1206328 @15.49.0.09 ATOMBuild #331092 19 | 20 | Major Changes included: 21 | 1. By pass programming PS175 via I2C if Parade PS175 reported by SBIOS 22 | 2. Update to release branch 15.49 23 | 24 | ============================ ST 003 VBIOS release ======================================== 25 | Stoney generic Baseline VBIOS 003 26 | Stoney A11 0x98E0 109-C91420-00A StoneyGenericVbios.003 10/02/15,03:22:47 CL#1196473 @15.48.0.68 ATOMBuild #329408 27 | 28 | Major Changes included: 29 | 1. Correct the miss in 002 for Parade PS175 DPToHDMI w/ HDCP2.2 recoverter chip support 30 | 31 | ============================ ST 002 VBIOS release ======================================== 32 | Stoney generic Baseline VBIOS 002 33 | Stoney A11 0x98E0 109-C91420-00A StoneyGenericVbios.002 09/25/15,05:42:02 CL#1194488 @15.48.0.68 ATOMBuild #329237 34 | 35 | Major Changes included: 36 | 1. Add Parade PS175 DPToHDMI w/ HDCP2.2 recoverter chip support 37 | 38 | ============================ ST 001 VBIOS release ======================================== 39 | Stoney generic Baseline VBIOS 001 40 | Stoney A11 0x98E0 109-C91420-00A StoneyGenericVbios.001 08/11/15,05:49:23 CL#1179088 @15.48.0.66 ATOMBuild #326744 41 | 42 | Vbios includes: 43 | 1. sync to the latest change in 15.48.(Same as Carrizo generic VBIOS v028) 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /soc/amd/stoneyridge/imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/amd/stoneyridge/imc.bin -------------------------------------------------------------------------------- /soc/amd/stoneyridge/xhci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/amd/stoneyridge/xhci.bin -------------------------------------------------------------------------------- /soc/cavium/cn81xx/LICENSE: -------------------------------------------------------------------------------- 1 | License Agreement 2 | For Open Source Computer Vision Library 3 | (3-clause BSD License) 4 | 5 | Copyright 2018 Facebook, Inc. 6 | Copyright 2003-2017 Cavium Inc. 7 | 8 | Redistribution and use in source and binary forms, with or without modification, 9 | are permitted provided that the following conditions are met: 10 | 11 | * Redistributions of source code must retain the above copyright notice, 12 | this list of conditions and the following disclaimer. 13 | 14 | * Redistributions in binary form must reproduce the above copyright notice, 15 | this list of conditions and the following disclaimer in the documentation 16 | and/or other materials provided with the distribution. 17 | 18 | * Neither the names of the copyright holders nor the names of the contributors 19 | may be used to endorse or promote products derived from this software 20 | without specific prior written permission. 21 | 22 | This software is provided by the copyright holders and contributors "as is" and 23 | any express or implied warranties, including, but not limited to, the implied 24 | warranties of merchantability and fitness for a particular purpose are disclaimed. 25 | In no event shall copyright holders or contributors be liable for any direct, 26 | indirect, incidental, special, exemplary, or consequential damages 27 | (including, but not limited to, procurement of substitute goods or services; 28 | loss of use, data, or profits; or business interruption) however caused 29 | and on any theory of liability, whether in contract, strict liability, 30 | or tort (including negligence or otherwise) arising in any way out of 31 | the use of this software, even if advised of the possibility of such damage. 32 | -------------------------------------------------------------------------------- /soc/cavium/cn81xx/README: -------------------------------------------------------------------------------- 1 | Fork of https://github.com/ARM-software/arm-trusted-firmware 2 | Version 1.5 based on commit d48f193d11b4d4dca2675646ad76147f2d4765f2 3 | Source is available at: 4 | https://github.com/9elements/arm-trusted-firmware/commits/coreboot_bl31_blob 5 | -------------------------------------------------------------------------------- /soc/cavium/cn81xx/VERSION: -------------------------------------------------------------------------------- 1 | version : ATF 1.5-117f85dd 2 | release date : 07-19-2018 3 | supported silicon: Cavium CN81XX 4 | ERRATA : - 5 | toolchain version: GCC 6.3.0 6 | ABI version : 1.5 7 | arch : aarch64 8 | instruction : Include into coreboot's CBFS and build with 9 | CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE 10 | -------------------------------------------------------------------------------- /soc/cavium/cn81xx/bl31.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/cavium/cn81xx/bl31.elf -------------------------------------------------------------------------------- /soc/intel/baytrail/microcode.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/baytrail/microcode.bin -------------------------------------------------------------------------------- /soc/intel/baytrail/microcode_blob.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the coreboot project. 3 | * 4 | * Copyright (C) 2014 Google Inc. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; version 2 of the License. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | */ 19 | 20 | #include "M0C3067_0000031E.h" 21 | -------------------------------------------------------------------------------- /soc/intel/broadwell/microcode.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/broadwell/microcode.bin -------------------------------------------------------------------------------- /soc/intel/broadwell/microcode_blob.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the coreboot project. 3 | * 4 | * Copyright (C) 2014 Google Inc. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; version 2 of the License. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | */ 19 | 20 | #include "microcode-M7240651_0000001C.h" /* Haswell ULT C0 or D0 */ 21 | #include "microcode-MF2306D2_FFFF0009.h" /* Broadwell C0 */ 22 | #include "microcode-MC0306D3_FFFF0010.h" /* Broadwell D0 */ 23 | #include "microcode-MC0306D4_0000001F.h" /* Broadwell E0/F0 */ 24 | 25 | /* Dummy terminator */ 26 | 0x0, 0x0, 0x0, 0x0, 27 | 0x0, 0x0, 0x0, 0x0, 28 | 0x0, 0x0, 0x0, 0x0, 29 | 0x0, 0x0, 0x0, 0x0, 30 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/DEBUG/FSP_M.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/DEBUG/FSP_M.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/DEBUG/FSP_S.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/DEBUG/FSP_S.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/DEBUG/FSP_T.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/DEBUG/FSP_T.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/DEBUG/QUARK.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/DEBUG/QUARK.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/Include/FspUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPUPD_H__ 34 | #define __FSPUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | #define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ 41 | 42 | #define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ 43 | 44 | #define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ 45 | 46 | #pragma pack() 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/Include/FspmUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPMUPD_H__ 34 | #define __FSPMUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | 41 | /** Fsp M Configuration 42 | **/ 43 | typedef struct { 44 | 45 | /** Offset 0x0040 - RmuBaseAddress 46 | RMU microcode binary base address in SPI flash' 47 | **/ 48 | UINT32 RmuBaseAddress; 49 | 50 | /** Offset 0x0044 - RmuLength 51 | RMU microcode binary length in bytes 52 | **/ 53 | UINT32 RmuLength; 54 | 55 | /** Offset 0x0048 - SerialPortBaseAddress 56 | Debug serial port base address set by BIOS. Zero disables debug serial output. 57 | **/ 58 | UINT32 Reserved_48; 59 | 60 | /** Offset 0x004C - tRAS 61 | ACT to PRE command period in picoseconds. 62 | **/ 63 | UINT32 tRAS; 64 | 65 | /** Offset 0x0050 - tWTR 66 | Delay from start of internal write transaction to internal read command in picoseconds. 67 | **/ 68 | UINT32 tWTR; 69 | 70 | /** Offset 0x0054 - tRRD 71 | ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. 72 | **/ 73 | UINT32 tRRD; 74 | 75 | /** Offset 0x0058 - tFAW 76 | Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. 77 | **/ 78 | UINT32 tFAW; 79 | 80 | /** Offset 0x005C - Flags 81 | Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN 82 | BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" 83 | topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices 84 | on writes. 85 | **/ 86 | UINT32 Flags; 87 | 88 | /** Offset 0x0060 - DramWidth 89 | 0=x8, 1=x16, others=RESERVED. 90 | **/ 91 | UINT8 DramWidth; 92 | 93 | /** Offset 0x0061 - DramSpeed 94 | 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. 95 | **/ 96 | UINT8 DramSpeed; 97 | 98 | /** Offset 0x0062 - DramType 99 | 0=DDR3, 1=DDR3L, others=RESERVED. 100 | **/ 101 | UINT8 DramType; 102 | 103 | /** Offset 0x0063 - RankMask 104 | bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. 105 | **/ 106 | UINT8 RankMask; 107 | 108 | /** Offset 0x0064 - ChanMask 109 | bit[0] CHAN0_EN, others=RESERVED. 110 | **/ 111 | UINT8 ChanMask; 112 | 113 | /** Offset 0x0065 - ChanWidth 114 | 1=x16, others=RESERVED. 115 | **/ 116 | UINT8 ChanWidth; 117 | 118 | /** Offset 0x0066 - AddrMode 119 | 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. 120 | **/ 121 | UINT8 AddrMode; 122 | 123 | /** Offset 0x0067 - SrInt 124 | 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. 125 | **/ 126 | UINT8 SrInt; 127 | 128 | /** Offset 0x0068 - SrTemp 129 | 0=normal, 1=extended, others=RESERVED. 130 | **/ 131 | UINT8 SrTemp; 132 | 133 | /** Offset 0x0069 - DramRonVal 134 | 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. 135 | **/ 136 | UINT8 DramRonVal; 137 | 138 | /** Offset 0x006A - DramRttNomVal 139 | 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. 140 | **/ 141 | UINT8 DramRttNomVal; 142 | 143 | /** Offset 0x006B - DramRttWrVal 144 | 0=off others=RESERVED. 145 | **/ 146 | UINT8 DramRttWrVal; 147 | 148 | /** Offset 0x006C - SocRdOdtVal 149 | 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. 150 | **/ 151 | UINT8 SocRdOdtVal; 152 | 153 | /** Offset 0x006D - SocWrRonVal 154 | 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. 155 | **/ 156 | UINT8 SocWrRonVal; 157 | 158 | /** Offset 0x006E - SocWrSlewRate 159 | 0=2.5V/ns, 1=4V/ns, others=RESERVED. 160 | **/ 161 | UINT8 SocWrSlewRate; 162 | 163 | /** Offset 0x006F - DramDensity 164 | 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. 165 | **/ 166 | UINT8 DramDensity; 167 | 168 | /** Offset 0x0070 - tCL 169 | DRAM CAS Latency in clocks 170 | **/ 171 | UINT8 tCL; 172 | 173 | /** Offset 0x0071 - EccScrubInterval 174 | ECC scrub interval in miliseconds 1..255 (0 works as feature disable 175 | **/ 176 | UINT8 EccScrubInterval; 177 | 178 | /** Offset 0x0072 - EccScrubBlkSize 179 | Number of 32B blocks read for ECC scrub 2..16 180 | **/ 181 | UINT8 EccScrubBlkSize; 182 | 183 | /** Offset 0x0073 - SmmTsegSize 184 | Size of the SMM region in 1 MiB chunks 185 | **/ 186 | UINT8 SmmTsegSize; 187 | 188 | /** Offset 0x0074 - FspReservedMemoryLength 189 | FSP reserved memory length in bytes 190 | **/ 191 | UINT32 FspReservedMemoryLength; 192 | 193 | /** Offset 0x0078 - MrcDataPtr 194 | Pointer to saved MRC data 195 | **/ 196 | UINT32 MrcDataPtr; 197 | 198 | /** Offset 0x007C - MrcDataLength 199 | Length of saved MRC data 200 | **/ 201 | UINT32 MrcDataLength; 202 | 203 | /** Offset 0x0080 204 | **/ 205 | UINT32 SerialPortPollForChar; 206 | 207 | /** Offset 0x0084 208 | **/ 209 | UINT32 SerialPortReadChar; 210 | 211 | /** Offset 0x0088 212 | **/ 213 | UINT32 SerialPortWriteChar; 214 | 215 | /** Offset 0x008C 216 | **/ 217 | UINT16 UpdTerminator; 218 | } FSP_M_CONFIG; 219 | 220 | /** Fsp M UPD Configuration 221 | **/ 222 | typedef struct { 223 | 224 | /** Offset 0x0000 225 | **/ 226 | FSP_UPD_HEADER FspUpdHeader; 227 | 228 | /** Offset 0x0020 229 | **/ 230 | FSPM_ARCH_UPD FspmArchUpd; 231 | 232 | /** Offset 0x0040 233 | **/ 234 | FSP_M_CONFIG FspmConfig; 235 | } FSPM_UPD; 236 | 237 | #pragma pack() 238 | 239 | #endif 240 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/Include/FspsUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPSUPD_H__ 34 | #define __FSPSUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | 41 | /** Fsp S UPD Configuration 42 | **/ 43 | typedef struct { 44 | 45 | /** Offset 0x0000 46 | **/ 47 | FSP_UPD_HEADER FspUpdHeader; 48 | 49 | /** Offset 0x0020 50 | **/ 51 | UINT16 UpdTerminator; 52 | } FSPS_UPD; 53 | 54 | #pragma pack() 55 | 56 | #endif 57 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/Include/FsptUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPTUPD_H__ 34 | #define __FSPTUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | 41 | /** Fsp T Common UPD 42 | **/ 43 | typedef struct { 44 | 45 | /** Offset 0x0020 46 | **/ 47 | UINT8 Revision; 48 | 49 | /** Offset 0x0021 50 | **/ 51 | UINT8 Reserved[3]; 52 | 53 | /** Offset 0x0024 54 | **/ 55 | UINT32 MicrocodeRegionBase; 56 | 57 | /** Offset 0x0028 58 | **/ 59 | UINT32 MicrocodeRegionLength; 60 | 61 | /** Offset 0x002C 62 | **/ 63 | UINT32 CodeRegionBase; 64 | 65 | /** Offset 0x0030 66 | **/ 67 | UINT32 CodeRegionLength; 68 | 69 | /** Offset 0x0034 70 | **/ 71 | UINT8 Reserved1[12]; 72 | } FSPT_COMMON_UPD; 73 | 74 | /** Fsp T UPD Configuration 75 | **/ 76 | typedef struct { 77 | 78 | /** Offset 0x0000 79 | **/ 80 | FSP_UPD_HEADER FspUpdHeader; 81 | 82 | /** Offset 0x0020 83 | **/ 84 | FSPT_COMMON_UPD FsptCommonUpd; 85 | 86 | /** Offset 0x0040 87 | **/ 88 | UINT16 UpdTerminator; 89 | } FSPT_UPD; 90 | 91 | #pragma pack() 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/RELEASE/FSP_M.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/RELEASE/FSP_M.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/RELEASE/FSP_S.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/RELEASE/FSP_S.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/RELEASE/FSP_T.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/RELEASE/FSP_T.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0/RELEASE/QUARK.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0/RELEASE/QUARK.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/DEBUG/FSP_M.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/DEBUG/FSP_M.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/DEBUG/FSP_S.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/DEBUG/FSP_S.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/DEBUG/FSP_T.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/DEBUG/FSP_T.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/DEBUG/QUARK.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/DEBUG/QUARK.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/Include/FspUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPUPD_H__ 34 | #define __FSPUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | #define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ 41 | 42 | #define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ 43 | 44 | #define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ 45 | 46 | #pragma pack() 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/Include/FspmUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPMUPD_H__ 34 | #define __FSPMUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | 41 | /** Fsp M Configuration 42 | **/ 43 | typedef struct { 44 | 45 | /** Offset 0x0040 - RmuBaseAddress 46 | RMU microcode binary base address in SPI flash' 47 | **/ 48 | UINT32 RmuBaseAddress; 49 | 50 | /** Offset 0x0044 - RmuLength 51 | RMU microcode binary length in bytes 52 | **/ 53 | UINT32 RmuLength; 54 | 55 | /** Offset 0x0048 - SerialPortBaseAddress 56 | Debug serial port base address set by BIOS. Zero disables debug serial output. 57 | **/ 58 | UINT32 Reserved_48; 59 | 60 | /** Offset 0x004C - tRAS 61 | ACT to PRE command period in picoseconds. 62 | **/ 63 | UINT32 tRAS; 64 | 65 | /** Offset 0x0050 - tWTR 66 | Delay from start of internal write transaction to internal read command in picoseconds. 67 | **/ 68 | UINT32 tWTR; 69 | 70 | /** Offset 0x0054 - tRRD 71 | ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. 72 | **/ 73 | UINT32 tRRD; 74 | 75 | /** Offset 0x0058 - tFAW 76 | Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. 77 | **/ 78 | UINT32 tFAW; 79 | 80 | /** Offset 0x005C - Flags 81 | Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN 82 | BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" 83 | topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices 84 | on writes. 85 | **/ 86 | UINT32 Flags; 87 | 88 | /** Offset 0x0060 - DramWidth 89 | 0=x8, 1=x16, others=RESERVED. 90 | **/ 91 | UINT8 DramWidth; 92 | 93 | /** Offset 0x0061 - DramSpeed 94 | 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. 95 | **/ 96 | UINT8 DramSpeed; 97 | 98 | /** Offset 0x0062 - DramType 99 | 0=DDR3, 1=DDR3L, others=RESERVED. 100 | **/ 101 | UINT8 DramType; 102 | 103 | /** Offset 0x0063 - RankMask 104 | bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. 105 | **/ 106 | UINT8 RankMask; 107 | 108 | /** Offset 0x0064 - ChanMask 109 | bit[0] CHAN0_EN, others=RESERVED. 110 | **/ 111 | UINT8 ChanMask; 112 | 113 | /** Offset 0x0065 - ChanWidth 114 | 1=x16, others=RESERVED. 115 | **/ 116 | UINT8 ChanWidth; 117 | 118 | /** Offset 0x0066 - AddrMode 119 | 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. 120 | **/ 121 | UINT8 AddrMode; 122 | 123 | /** Offset 0x0067 - SrInt 124 | 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. 125 | **/ 126 | UINT8 SrInt; 127 | 128 | /** Offset 0x0068 - SrTemp 129 | 0=normal, 1=extended, others=RESERVED. 130 | **/ 131 | UINT8 SrTemp; 132 | 133 | /** Offset 0x0069 - DramRonVal 134 | 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. 135 | **/ 136 | UINT8 DramRonVal; 137 | 138 | /** Offset 0x006A - DramRttNomVal 139 | 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. 140 | **/ 141 | UINT8 DramRttNomVal; 142 | 143 | /** Offset 0x006B - DramRttWrVal 144 | 0=off others=RESERVED. 145 | **/ 146 | UINT8 DramRttWrVal; 147 | 148 | /** Offset 0x006C - SocRdOdtVal 149 | 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. 150 | **/ 151 | UINT8 SocRdOdtVal; 152 | 153 | /** Offset 0x006D - SocWrRonVal 154 | 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. 155 | **/ 156 | UINT8 SocWrRonVal; 157 | 158 | /** Offset 0x006E - SocWrSlewRate 159 | 0=2.5V/ns, 1=4V/ns, others=RESERVED. 160 | **/ 161 | UINT8 SocWrSlewRate; 162 | 163 | /** Offset 0x006F - DramDensity 164 | 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. 165 | **/ 166 | UINT8 DramDensity; 167 | 168 | /** Offset 0x0070 - tCL 169 | DRAM CAS Latency in clocks 170 | **/ 171 | UINT8 tCL; 172 | 173 | /** Offset 0x0071 - EccScrubInterval 174 | ECC scrub interval in miliseconds 1..255 (0 works as feature disable 175 | **/ 176 | UINT8 EccScrubInterval; 177 | 178 | /** Offset 0x0072 - EccScrubBlkSize 179 | Number of 32B blocks read for ECC scrub 2..16 180 | **/ 181 | UINT8 EccScrubBlkSize; 182 | 183 | /** Offset 0x0073 - SmmTsegSize 184 | Size of the SMM region in 1 MiB chunks 185 | **/ 186 | UINT8 SmmTsegSize; 187 | 188 | /** Offset 0x0074 - FspReservedMemoryLength 189 | FSP reserved memory length in bytes 190 | **/ 191 | UINT32 FspReservedMemoryLength; 192 | 193 | /** Offset 0x0078 - MrcDataPtr 194 | Pointer to saved MRC data 195 | **/ 196 | UINT32 MrcDataPtr; 197 | 198 | /** Offset 0x007C - MrcDataLength 199 | Length of saved MRC data 200 | **/ 201 | UINT32 MrcDataLength; 202 | 203 | /** Offset 0x0080 204 | **/ 205 | UINT32 SerialPortPollForChar; 206 | 207 | /** Offset 0x0084 208 | **/ 209 | UINT32 SerialPortReadChar; 210 | 211 | /** Offset 0x0088 212 | **/ 213 | UINT32 SerialPortWriteChar; 214 | 215 | /** Offset 0x008C 216 | **/ 217 | UINT16 UpdTerminator; 218 | } FSP_M_CONFIG; 219 | 220 | /** Fsp M UPD Configuration 221 | **/ 222 | typedef struct { 223 | 224 | /** Offset 0x0000 225 | **/ 226 | FSP_UPD_HEADER FspUpdHeader; 227 | 228 | /** Offset 0x0020 229 | **/ 230 | FSPM_ARCH_UPD FspmArchUpd; 231 | 232 | /** Offset 0x0040 233 | **/ 234 | FSP_M_CONFIG FspmConfig; 235 | } FSPM_UPD; 236 | 237 | #pragma pack() 238 | 239 | #endif 240 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/Include/FspsUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPSUPD_H__ 34 | #define __FSPSUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | 41 | /** Fsp S UPD Configuration 42 | **/ 43 | typedef struct { 44 | 45 | /** Offset 0x0000 46 | **/ 47 | FSP_UPD_HEADER FspUpdHeader; 48 | 49 | /** Offset 0x0020 50 | **/ 51 | UINT16 UpdTerminator; 52 | } FSPS_UPD; 53 | 54 | #pragma pack() 55 | 56 | #endif 57 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/Include/FsptUpd.h: -------------------------------------------------------------------------------- 1 | /** @file 2 | 3 | Copyright (c) 2018, Intel Corporation. All rights reserved.
4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | * Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | * Redistributions in binary form must reproduce the above copyright notice, this 11 | list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | * Neither the name of Intel Corporation nor the names of its contributors may 14 | be used to endorse or promote products derived from this software without 15 | specific prior written permission. 16 | 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 | THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | This file is automatically generated. Please do NOT modify !!! 30 | 31 | **/ 32 | 33 | #ifndef __FSPTUPD_H__ 34 | #define __FSPTUPD_H__ 35 | 36 | #include 37 | 38 | #pragma pack(1) 39 | 40 | 41 | /** Fsp T Common UPD 42 | **/ 43 | typedef struct { 44 | 45 | /** Offset 0x0020 46 | **/ 47 | UINT8 Revision; 48 | 49 | /** Offset 0x0021 50 | **/ 51 | UINT8 Reserved[3]; 52 | 53 | /** Offset 0x0024 54 | **/ 55 | UINT32 MicrocodeRegionBase; 56 | 57 | /** Offset 0x0028 58 | **/ 59 | UINT32 MicrocodeRegionLength; 60 | 61 | /** Offset 0x002C 62 | **/ 63 | UINT32 CodeRegionBase; 64 | 65 | /** Offset 0x0030 66 | **/ 67 | UINT32 CodeRegionLength; 68 | 69 | /** Offset 0x0034 70 | **/ 71 | UINT8 Reserved1[12]; 72 | } FSPT_COMMON_UPD; 73 | 74 | /** Fsp T UPD Configuration 75 | **/ 76 | typedef struct { 77 | 78 | /** Offset 0x0000 79 | **/ 80 | FSP_UPD_HEADER FspUpdHeader; 81 | 82 | /** Offset 0x0020 83 | **/ 84 | FSPT_COMMON_UPD FsptCommonUpd; 85 | 86 | /** Offset 0x0040 87 | **/ 88 | UINT16 UpdTerminator; 89 | } FSPT_UPD; 90 | 91 | #pragma pack() 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/RELEASE/FSP_M.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/RELEASE/FSP_M.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/RELEASE/FSP_S.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/RELEASE/FSP_S.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/RELEASE/FSP_T.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/RELEASE/FSP_T.fd -------------------------------------------------------------------------------- /soc/intel/quark/Fsp2_0Pei/RELEASE/QUARK.fd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/intel/quark/Fsp2_0Pei/RELEASE/QUARK.fd -------------------------------------------------------------------------------- /soc/intel/quark/QuarkFsp.patch: -------------------------------------------------------------------------------- 1 | diff --git a/BuildFsp2_0.sh b/BuildFsp2_0.sh 2 | index 8910928..ca96446 100755 3 | --- a/BuildFsp2_0.sh 4 | +++ b/BuildFsp2_0.sh 5 | @@ -22,7 +22,7 @@ PLATFORM_NAME=QuarkFsp2_0 6 | BIN_SUB_DIR=Fsp2_0 7 | FSP_PKG_CONF_NAME=QuarkFspPkgConfig 8 | FSP_PKG_EXT_CONF_NAME=QuarkFspPkgExtConfig 9 | -TOOL_CHAIN=GCC48 10 | +TOOL_CHAIN=COREBOOT 11 | Edksetup=edksetup.sh 12 | FSP_T_UPD_GUID=34686CA3-34F9-4901-B82A-BA630F0714C6 13 | FSP_M_UPD_GUID=39A250DB-E465-4DD1-A2AC-E2BD3C0E2385 14 | diff --git a/BuildFsp2_0Pei.sh b/BuildFsp2_0Pei.sh 15 | index 3f447e1..f266572 100755 16 | --- a/BuildFsp2_0Pei.sh 17 | +++ b/BuildFsp2_0Pei.sh 18 | @@ -22,7 +22,7 @@ PLATFORM_NAME=QuarkFsp2_0Pei 19 | BIN_SUB_DIR=Fsp2_0Pei 20 | FSP_PKG_CONF_NAME=QuarkFspPkgConfig 21 | FSP_PKG_EXT_CONF_NAME=QuarkFspPkgExtConfig 22 | -TOOL_CHAIN=GCC48 23 | +TOOL_CHAIN=COREBOOT 24 | Edksetup=edksetup.sh 25 | FSP_T_UPD_GUID=34686CA3-34F9-4901-B82A-BA630F0714C6 26 | FSP_M_UPD_GUID=39A250DB-E465-4DD1-A2AC-E2BD3C0E2385 27 | diff --git a/Library/Fsp2_0Lib/Peim.c b/Library/Fsp2_0Lib/Peim.c 28 | index 14d0f99..c9a531a 100644 29 | --- a/Library/Fsp2_0Lib/Peim.c 30 | +++ b/Library/Fsp2_0Lib/Peim.c 31 | @@ -13,6 +13,7 @@ 32 | **/ 33 | 34 | #include 35 | +#include 36 | #include 37 | #include 38 | #include 39 | @@ -53,3 +54,17 @@ VOID FspInstallPeiMemory(EFI_PHYSICAL_ADDRESS FspReservedArea, 40 | Status = PeiServicesInstallPeiMemory (FspReservedArea, ReservedBytes); 41 | ASSERT_EFI_ERROR (Status); 42 | } 43 | + 44 | +#if !((defined(MDE_CPU_ARM) || defined(MDE_CPU_AARCH64)) && defined(__GNUC__)) 45 | +/** The memset function copies the value of c (converted to an unsigned char) 46 | + into each of the first n characters of the object pointed to by s. 47 | + 48 | + @return The memset function returns the value of s. 49 | +**/ 50 | +void * 51 | +memset(void *s, int c, size_t n) 52 | +{ 53 | + return SetMem( s, (UINTN)n, (UINT8)c); 54 | +} 55 | +#endif 56 | + 57 | -------------------------------------------------------------------------------- /soc/intel/quark/README.txt: -------------------------------------------------------------------------------- 1 | These binaries are the result of compiling the QuarkFsp sources and 2 | provided as a convenience since not everybody wants to setup a working 3 | edk2 tree. 4 | Since the sources, as well as the edk2 sources, are BSD-licensed, 5 | redistribution is not an issue. 6 | 7 | These binaries are untested and come with no warranty! 8 | 9 | Instructions to build your own binaries, using the coreboot toolchain: 10 | 11 | $ git clone http://github.com/tianocore/edk2 12 | $ cd edk2 13 | $ git checkout a5cd3bb037cf87ecda0a5c8cd8a3eda722591b70 14 | $ git clone https://review.gerrithub.io/LeeLeahy/quarkfsp QuarkFspPkg 15 | $ (cd QuarkFspPkg; patch -p1 -i $path/to/this/directory/QuarkFsp.patch) 16 | $ . edksetup.sh 17 | $ cat $path/to/your/coreboot/toolchain/share/edk2config/tools_def.txt >> Conf/tools_def.txt 18 | 19 | $ # builds the debug images 20 | $ QuarkFspPkg/BuildFsp2_0.sh -d32 21 | $ QuarkFspPkg/BuildFsp2_0Pei.sh -d32 22 | 23 | $ # builds the release images 24 | $ QuarkFspPkg/BuildFsp2_0.sh -r32 25 | $ QuarkFspPkg/BuildFsp2_0Pei.sh -r32 26 | -------------------------------------------------------------------------------- /soc/mediatek/mt8183/README.md: -------------------------------------------------------------------------------- 1 | # Firmware list 2 | 3 | - drame.elf 4 | 5 | # `dram.elf` Introduction 6 | 7 | `dram.elf` is one ELF format file which is used for calibration. 8 | The `dram.elf` is loaded at the first bootup. It will do DRAM 9 | full calibration, and save calibration parameters to NAND/NOR (or EMMC) 10 | for faster bootup after the first bootup. 11 | 12 | ## Who uses it 13 | 14 | coreboot loads `dram.elf` at the first time bootup if no DRAM parameters have 15 | been cached. 16 | 17 | 18 | ## How to load `dram.elf` 19 | 20 | coreboot locates `dram.elf` file, and locates the entry point `_start`, 21 | then it passes DRAM struct `param`, and calls `_start(¶m)` to execute 22 | `dram.elf` flow. 23 | 24 | ## Parameters 25 | 26 | ``` 27 | struct dramc_param { 28 | struct dramc_param_header header; // see below 29 | void (*do_putc)(unsigned char c); 30 | struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; // see below 31 | }; 32 | ``` 33 | 34 | Below shows the internal structure of `dramc_param`: 35 | 36 | ``` 37 | struct dramc_param_header { 38 | u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ 39 | u32 magic; /* DRAMC_PARAM_HEADER_MAGIC */ 40 | u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ 41 | u16 size; /* size of whole dramc_param, update in the coreboot */ 42 | I u16 config; /* DRAMC_PARAM_CONFIG, used for blob */ 43 | u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ 44 | u32 checksum; /* checksum of dramc_datas, update in the coreboot */ 45 | }; 46 | 47 | struct sdram_params { 48 | u16 source; 49 | u16 frequency; /* DRAM frequency */ 50 | u8 rank_num; /* DRAM rank number */ 51 | u16 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ 52 | u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 53 | 54 | /* DUTY */ 55 | s8 duty_clk_delay[CHANNEL_MAX]; 56 | s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 57 | 58 | /* CBT */ 59 | u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; 60 | u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; 61 | u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; 62 | u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; 63 | u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; 64 | 65 | /* Gating */ 66 | u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 67 | u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 68 | u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 69 | u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 70 | 71 | /* TX perbit */ 72 | u8 tx_vref[CHANNEL_MAX][RANK_MAX]; 73 | u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 74 | u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 75 | u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 76 | u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 77 | u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 78 | 79 | /* datlat */ 80 | u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; 81 | 82 | /* RX perbit */ 83 | u8 rx_vref[CHANNEL_MAX]; 84 | s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 85 | u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 86 | 87 | u32 emi_cona_val; 88 | u32 emi_conh_val; 89 | u32 emi_conf_val; 90 | u32 chn_emi_cona_val[CHANNEL_MAX]; 91 | u32 cbt_mode_extern; 92 | u32 delay_cell_unit; 93 | }; 94 | ``` 95 | 96 | ## Output of `dram.elf` 97 | 98 | `dram.elf` will set suitable dramc settings, and save the DRAM parameters 99 | to NAND/NOR (or EMMC) in the specified section: `RW_DDR_TRAINING`. 100 | 101 | ## Return Values 102 | 103 | - 0 : means successful. 104 | - < 0 : means failed. 105 | 106 | ## Version 107 | 108 | ``` 109 | $ strings dram.elf | grep "firmware version" 110 | MediaTek DRAM firmware version: 1.5.0 111 | ``` 112 | -------------------------------------------------------------------------------- /soc/mediatek/mt8183/dram.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8183/dram.elf -------------------------------------------------------------------------------- /soc/mediatek/mt8183/dram.elf.md5: -------------------------------------------------------------------------------- 1 | c2261728217c9e3ca21cb511724dde5d *dram.elf 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8183/dram_release_notes.txt: -------------------------------------------------------------------------------- 1 | # 2021.04.06 2 | 1. Build from Chrome OS 12573.224.0, compatible with previous versions. 3 | Header version = 5. 4 | 5 | 2. Include changes: 6 | 7 | CL:*3724354 dramc: Do not print if serial console is disabled 8 | CL:*3724353 dramc: mt8183: Add blob version 9 | 10 | # 2021.01.20 11 | 1. Build from Chrome OS 12573.197.0, incompatible with previous versions. 12 | Header version = 5. 13 | 14 | 2. Include changes: 15 | 16 | CL:*3531920 dramc: mt8183: add 8GB dram byte mode setting 17 | 18 | # 2020.09.29 19 | 1. Build from Chrome OS 12573.136.0, incompatible with previous versions. 20 | Header version = 4. 21 | 2. Included changes: 22 | 23 | CL:*3222235 dramc: MT8183: Enable CA perbit mechanism 24 | 25 | # 2020.08.12 26 | 27 | 1. Build from Chrome OS 12573.132.0, incompatible with previous versions. 28 | Header version = 3. 29 | 2. Included changes: 30 | 31 | CL:*3208271 dramc: MT8183: Add ddr geometry to support 6GB, 8GB DDR bootup 32 | 33 | # 2019.11.20 34 | 35 | 1. Build from Chrome OS 12573.28.0 36 | 2. Included changes: 37 | 38 | CL:*2173841 dramc: fast-k: save TX window param result with correct type 39 | 40 | # 2019.11.18 41 | 42 | 1. Build from Chrome OS 12573.25.0 43 | 2. Included changes: 44 | 45 | CL:*2150073 dramc: reduce the default DRAM calibration log 46 | 47 | # 2019.11.14 48 | 49 | 1. Built from Chrome OS 12573.20.0 50 | 2. Included changes: 51 | 52 | CL:*2134550 driver: Do not add \r when printing logs to external console 53 | 54 | # 2019.10.31 55 | 56 | 1. Built from Chrome OS 12573.16.0 57 | 2. Included changes: 58 | 59 | CL:*2067070 dramc: Control DVFS from config 60 | CL:*2026388 driver: Add udelay after setting voltages 61 | 62 | # 2019.10.23 63 | 64 | 1. Built from Chrome OS 12617.0.0 65 | 2. Included changes: 66 | 67 | fdaa670 driver: Add pmic_wrap for adjusting voltages 68 | 5178528 dramc: Redirect console output to provided callback 69 | b5636b4 dramc: Remove start and end patterns from sdram_params 70 | ae64f23 dramc: Add 'dramc_param' for sharing configs in a better way 71 | aa556fb dramc: Minimal effort to support both eMCP and discrete in same blob 72 | 79e9bb5 dramc: Save DRAM calibration result to coreboot for fast calibration 73 | ae95839 dramc: Loader of the blob should support ELF format 74 | 1a9ce1a porting DRAM full calibration driver 75 | -------------------------------------------------------------------------------- /soc/mediatek/mt8183/license.txt: -------------------------------------------------------------------------------- 1 | MediaTek Inc. grants permission to use and redistribute aforementioned firmware 2 | files for the use with devices containing MediaTek chipsets, but not as part of 3 | the Linux kernel or in any other form which would require these files themselves 4 | to be covered by the terms of the GNU General Public License or the GNU Lesser 5 | General Public License. 6 | 7 | These firmware files are distributed in the hope that they will be useful, but 8 | are provided WITHOUT ANY WARRANTY, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTY 9 | OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 10 | -------------------------------------------------------------------------------- /soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8183/pcm_allinone_lp4_3733.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8183/pcm_allinone_lp4_3733.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8183/spm_release_notes.txt: -------------------------------------------------------------------------------- 1 | =============== spm release 201907============= 2 | 1. support spm suspend at the end of system suspend 3 | -------------------------------------------------------------------------------- /soc/mediatek/mt8183/sspm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8183/sspm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8183/sspm_release_notes.txt: -------------------------------------------------------------------------------- 1 | =============== sspm release 201907============= 2 | 1. support basic environment 3 | 2. support SSPM_IDLE and SPM_COMMON 4 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/README.md: -------------------------------------------------------------------------------- 1 | # Firmware list 2 | - `spm_firmware.bin` 3 | - `sspm.bin` 4 | - `dram.elf` 5 | 6 | -------------------------------------------------------------------------------- 7 | # SPM introduction 8 | SPM is able to turn off more power such as DRAM self-refresh mode and 26M clock off 9 | when system is in suspend. Also, SPM helps support Vcore DVFS feature. 10 | 11 | ## Who uses it 12 | Linux kernel system suspend and Vcore DVFS. 13 | 14 | ## How to load `spm_fimware.bin` 15 | Use CBFS to load `spm_fimware.bin` to DRAM and SPM DMA loads it from dram to SPM SRAM. 16 | 17 | ## Return values 18 | No return value. 19 | 20 | ## Version 21 | `$ strings spm_firmware.bin | grep pcm_suspend` 22 | 23 | -------------------------------------------------------------------------------- 24 | # SSPM introduction 25 | SSPM is "Secure System Power Manager" that provides power control in secure domain. 26 | SSPM provides power related features, e.g. CPU DVFS, thermal control, to offload 27 | application processor for security reason. 28 | 29 | SSPM firmware is loaded into SSPM SRAM at system initialization. 30 | 31 | ## Who uses it 32 | coreboot will load sspm.bin to SSPM SRAM at ramstage. 33 | 34 | ## How to load `sspm.bin` 35 | Use CBFS to load `sspm.bin`. 36 | No need to pass other parameters to SSPM. 37 | 38 | ## Return value 39 | No return value. 40 | 41 | ## Version 42 | `$ strings sspm.bin | grep "SSPM firmware"` 43 | 44 | -------------------------------------------------------------------------------- 45 | # `dram.elf` introduction 46 | `dram.elf` is an ELF format file, which performs DRAM full calibration, DRAM 47 | fast calibration and returns the trained calibration parameters to the caller. 48 | The caller may store the parameters on NOR/NAND or eMMC for faster subsequent 49 | bootups. 50 | 51 | ## Who uses it 52 | coreboot loads `dram.elf` during the first bootup if no valid DRAM parameters 53 | are found on NOR/NAND or eMMC. 54 | 55 | ## How to load `dram.elf` 56 | coreboot locates `dram.elf` file, locates the entry point `_start`, 57 | passes a `dramc_param` struct argument `dparam` to it, and calls 58 | `_start(&dparam)` to execute `dram.elf`. 59 | 60 | ## Parameters 61 | ``` 62 | struct dramc_param { 63 | struct dramc_param_header header; // see below 64 | void (*do_putc)(unsigned char c); 65 | struct dramc_data dramc_datas; // see below 66 | }; 67 | ``` 68 | 69 | Below shows the internal structure of `dramc_param`: 70 | ``` 71 | struct dramc_param_header { 72 | u16 version; /* DRAMC_PARAM_HEADER_VERSION, set in coreboot */ 73 | u16 size; /* size of whole dramc_param, set in coreboot */ 74 | u16 status; /* DRAMC_PARAM_STATUS_CODES, set in dram blob */ 75 | u16 flags; /* DRAMC_PARAM_FLAG, set in dram blob */ 76 | u16 config; /* DRAMC_PARAM_CONFIG, set in coreboot */ 77 | }; 78 | 79 | struct sdram_info { 80 | u32 ddr_type; /* SDRAM_DDR_TYPE */ 81 | u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ 82 | }; 83 | 84 | struct sdram_params { 85 | u32 rank_num; 86 | u16 num_dlycell_perT; 87 | u16 delay_cell_timex100; 88 | 89 | /* duty */ 90 | s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; 91 | s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 92 | s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 93 | ....... 94 | ....... 95 | }; 96 | 97 | struct emi_mdl { 98 | u32 cona_val; 99 | u32 conh_val; 100 | u32 conf_val; 101 | u32 chn_cona_val; 102 | }; 103 | 104 | struct ddr_mrr_info { 105 | u16 mr5_vendor_id; 106 | u16 mr6_revision_id; 107 | u16 mr7_revision_id; 108 | u64 mr8_density[RANK_MAX]; 109 | u32 rank_nums; 110 | u8 die_num[RANK_MAX]; 111 | }; 112 | 113 | struct ddr_base_info { 114 | u32 config_dvfs; /* SDRAM_DVFS_FLAG */ 115 | struct sdram_info sdram; 116 | u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ 117 | u32 support_ranks; 118 | u64 rank_size[RANK_MAX]; 119 | struct emi_mdl emi_config; 120 | DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; 121 | struct ddr_mrr_info mrr_info; 122 | u32 data_rate; 123 | }; 124 | 125 | struct dramc_data { 126 | struct ddr_base_info ddr_info; 127 | struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; 128 | }; 129 | ``` 130 | 131 | ## The output of `dram.elf` 132 | `dram.elf` configures suitable dramc settings and returns the DRAM parameters. 133 | Then, coreboot saves the parameters on the specified firmware flash section: 134 | `"RW_MRC_CACHE"`. 135 | 136 | ## Return values 137 | 0 on success; < 0 on failure. 138 | 139 | ## Version 140 | `$ strings dram.elf | grep "firmware version"` 141 | 142 | -------------------------------------------------------------------------------- 143 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/dram.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8186/dram.elf -------------------------------------------------------------------------------- /soc/mediatek/mt8186/dram.elf.md5: -------------------------------------------------------------------------------- 1 | 5c7f96716ec681544803301184a33f4b *dram.elf 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/dram_release_notes.txt: -------------------------------------------------------------------------------- 1 | # 0.1.0 2 | 3 | 1. A local build. 4 | Protocol (params header) version: 1 5 | 6 | 2. Included changes: 7 | 8 | - CL:*4389197 mtk-dramk/mt8186,8192,8195: Extract dramc_param_header to common header 9 | - CL:*4357516 mtk-dramk/mt8186: Add fast-k support 10 | - CL:*4392248 mtk-dramk/mt8186: Add cros folder for mtk-dramk 11 | - CL:*4043272 mtk-dramk/mt8186: Initial drop for memory calibration 12 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/license.txt: -------------------------------------------------------------------------------- 1 | MediaTek Inc. grants permission to use and redistribute aforementioned firmware 2 | files for the use with devices containing MediaTek chipsets, but not as part of 3 | the Linux kernel or in any other form which would require these files themselves 4 | to be covered by the terms of the GNU General Public License or the GNU Lesser 5 | General Public License. 6 | 7 | These firmware files are distributed in the hope that they will be useful, but 8 | are provided WITHOUT ANY WARRANTY, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTY 9 | OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 10 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/spm_firmware.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8186/spm_firmware.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8186/spm_firmware.bin.md5: -------------------------------------------------------------------------------- 1 | 7db456c2374b3a76daa9e6f0f2b4fd71 *spm_firmware.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/spm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # pcm_suspend_mp_v1109 4 | 1. SPM suspend can turn 26M clock off when system goes into suspend. 5 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/sspm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8186/sspm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8186/sspm.bin.md5: -------------------------------------------------------------------------------- 1 | 634e532d6acb98e4b1807944233b8f81 *sspm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8186/sspm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # v2.0.1 4 | 1. Fix PMIC MT6315 regulator issue. 5 | 6 | # v2.0.0 7 | 1. Add PMIC MT6315 support for SSPM. 8 | 9 | # v1.0.0 10 | 1. Add sspm.bin v1.0.0. 11 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/README.md: -------------------------------------------------------------------------------- 1 | # Firmware list 2 | - mcupm.bin 3 | - sspm.bin 4 | - dpm.dm 5 | - dpm.pm 6 | - spm_firmware.bin 7 | - dram.elf 8 | 9 | -------------------------------------------------------------------------------- 10 | # MCUPM introduction 11 | MCUPM is a hardware module which is used for MCUSYS Power Management. 12 | MCUPM firmware (`mcupm.bin`) is loaded into MCUPM SRAM at system initialization. 13 | 14 | ## Who uses it 15 | Coreboot will load MCUPM at ramstage. It will copy mcupm.bin to MCUPM SRAM. 16 | 17 | ## How to load `mcupm.bin` 18 | Use CBFS to load `mcupm.bin`, then set normal boot flag and release software reset pin of MCUPM. 19 | 20 | ## Return values 21 | No return value. 22 | 23 | ## Version 24 | `$ strings mcupm.bin | grep "MCUPM firmware"` 25 | 26 | -------------------------------------------------------------------------------- 27 | # SSPM introduction 28 | SSPM is "Secure System Power Manager" that provides power control in secure domain. 29 | SSPM provides power related features, e.g. CPU DVFS, thermal control, to offload 30 | application processor for security reason. 31 | 32 | SSPM firmware is loaded into SSPM SRAM at system initialization. 33 | 34 | ## Who uses it 35 | Coreboot will load sspm.bin to SSPM SRAM at ramstage. 36 | 37 | ## How to load `sspm.bin` 38 | Use CBFS to load `sspm.bin`. 39 | No need to pass other parameters to SSPM. 40 | 41 | ## Return value 42 | No return value. 43 | 44 | ## Version 45 | `$ strings sspm.bin | grep "SSPM firmware"` 46 | 47 | -------------------------------------------------------------------------------- 48 | # DPM introduction 49 | DPM is a hardware module for DRAM Power Management, which is used for DRAM low power. 50 | For example: self refresh, disable PLL/DLL when not in use. 51 | 52 | DPM includes two parts of images: data part (`dpm.dm`) and program part (`dpm.pm`). 53 | 54 | ## Who uses it 55 | Coreboot loads dpm at ramstage, and copies `dpm.dm` & `dpm.pm` to DPM SRAM. 56 | 57 | ## How to load DPM 58 | Use CBFS to load `dpm.dm` and `dpm.pm`. 59 | No need to pass other parameters to DPM. 60 | 61 | ## Return values 62 | No return value. 63 | 64 | ## Add version 65 | ``` 66 | $ echo -n 'DPMD Firmware version: x.x' >> dpm.dm 67 | $ echo -n 'DPMP Firmware version: x.x' >> dpm.pm 68 | ``` 69 | 70 | ## Version 71 | ``` 72 | $ strings dpm.dm | grep version 73 | $ strings dpm.pm | grep version 74 | ``` 75 | 76 | -------------------------------------------------------------------------------- 77 | # SPM introduction 78 | SPM is able to turn off more power such as DRAM self-refresh mode and 26M clock off 79 | when system is in suspend. Also, SPM helps support Vcore DVFS feature. 80 | 81 | ## Who uses it 82 | Linux kernel system suspend and Vcore DVFS. 83 | 84 | ## How to load `spm_fimware.bin` 85 | Use CBFS to load `spm_fimware.bin` to DRAM and SPM DMA loads it from dram to SPM SRAM. 86 | 87 | ## Return values 88 | No return value. 89 | 90 | ## Version 91 | `$ strings spm_firmware.bin | grep pcm_suspend` 92 | 93 | -------------------------------------------------------------------------------- 94 | # `dram.elf` introduction 95 | `dram.elf` is an ELF format file, which performs DRAM full calibration, DRAM 96 | fast calibration and returns the trained calibration parameters to the caller. 97 | The caller may store the parameters on NOR/NAND or eMMC for faster subsequent 98 | bootups. 99 | 100 | ## Who uses it 101 | Coreboot loads `dram.elf` during the first bootup if no valid DRAM parameters 102 | are found on NOR/NAND or eMMC. 103 | 104 | ## How to load `dram.elf` 105 | Coreboot locates `dram.elf` file, locates the entry point `_start`, 106 | passes a `dramc_param` struct argument `dparam` to it, and calls 107 | `_start(&dparam)` to execute `dram.elf`. 108 | 109 | ## Parameters 110 | ``` 111 | struct dramc_param { 112 | struct dramc_param_header header; 113 | void (*do_putc)(unsigned char c); 114 | struct dramc_data dramc_datas; 115 | }; 116 | ``` 117 | 118 | Below shows the internal structure of `dramc_param`: 119 | ``` 120 | struct dramc_param_header { 121 | u16 version; /* DRAMC_PARAM_HEADER_VERSION, set in coreboot */ 122 | u16 size; /* size of whole dramc_param, set in coreboot */ 123 | u16 status; /* DRAMC_PARAM_STATUS_CODES, set in dram blob */ 124 | u16 flags; /* DRAMC_PARAM_FLAG, set in dram blob */ 125 | u16 config; /* DRAMC_PARAM_CONFIG, set in coreboot */ 126 | }; 127 | 128 | struct sdram_params { 129 | /* rank, cbt */ 130 | u32 rank_num; 131 | u32 dram_cbt_mode; 132 | u16 delay_cell_timex100; 133 | u8 u18ph_dly; 134 | 135 | /* duty */ 136 | s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; 137 | s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 138 | s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 139 | ....... 140 | ....... 141 | }; 142 | 143 | struct ddr_mrr_info { 144 | u16 mr5_vendor_id; 145 | u16 mr6_revision_id; 146 | u16 mr7_revision_id; 147 | u64 mr8_density[RANK_MAX]; 148 | u32 rank_nums; 149 | u8 die_num[RANK_MAX]; 150 | }; 151 | 152 | struct emi_mdl { 153 | u32 cona_val; 154 | u32 conh_val; 155 | u32 conf_val; 156 | u32 chn_cona_val; 157 | }; 158 | 159 | struct sdram_info { 160 | u32 ddr_type; /* SDRAM_DDR_TYPE */ 161 | u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ 162 | }; 163 | 164 | struct ddr_base_info { 165 | u32 config_dvfs; /* SDRAM_DVFS_FLAG */ 166 | struct sdram_info sdram; 167 | u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ 168 | u32 support_ranks; 169 | u64 rank_size[RANK_MAX]; 170 | struct emi_mdl emi_config; 171 | DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; 172 | struct ddr_mrr_info mrr_info; 173 | u32 data_rate; 174 | }; 175 | 176 | struct dramc_data { 177 | struct ddr_base_info ddr_info; 178 | struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; 179 | }; 180 | ``` 181 | 182 | ## The output of `dram.elf` 183 | `dram.elf` configures suitable dramc settings and returns the DRAM parameters. 184 | Then, Coreboot saves the parameters on the specified firmware flash section: 185 | `"RW_MRC_CACHE"`. 186 | 187 | ## Return values 188 | 0 on success; < 0 on failure. 189 | 190 | ## Version 191 | `$ strings dram.elf | grep "firmware version"` 192 | 193 | -------------------------------------------------------------------------------- 194 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dpm.dm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8188/dpm.dm -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dpm.dm.md5: -------------------------------------------------------------------------------- 1 | c5fccdf936b3c85bebfa010313890aac *dpm.dm 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dpm.pm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8188/dpm.pm -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dpm.pm.md5: -------------------------------------------------------------------------------- 1 | a4953cf61e566d02b23cd43abc565d0a *dpm.pm 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dpm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | # Version 0.2 3 | 1. Add scramble switch support. 4 | 5 | # Version 0.1 6 | 1. Add DRAM suspend/DVFS support. 7 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dram.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8188/dram.elf -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dram.elf.md5: -------------------------------------------------------------------------------- 1 | 2f1c79839e0a78d16c19b039d05a650a *dram.elf 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/dram_release_notes.txt: -------------------------------------------------------------------------------- 1 | # 0.1.1 2 | 3 | 1. Add scramble switch for production build and serial build compatiblity. 4 | Fix fast-k single rank wrong register bit. 5 | 6 | 2. Included changes: 7 | 8 | - CL:*5498291 mtk-dramk/common: Add scramble switch 9 | - CL:*5504769 mtk-dramk/common: Copy soc/emi.h to dramk/common from coreboot 10 | - CL:*5533692 mtk-dramk/mt8188: Fix fast-k single rank wrong register bit 11 | 12 | 13 | # 0.1.0 14 | 15 | 1. A local build. 16 | Protocol (params header) version: 1 17 | 18 | 2. Included changes: 19 | 20 | - CL:*4911803 mtk-dramk/mt8188: Add fast-k support 21 | - CL:*4911802 mtk-dramk/mt8188: Make source code compilable and runable 22 | - CL:*4933742 mtk-dramk: Move typedefs.h to common folder 23 | - CL:*4933741 mtk-dramk: Refactor emi files 24 | - CL:*4916640 mtk-dramk: Enable checkpatch_check 25 | - CL:*4916639 COIL: Add unblocked_terms.txt 26 | - CL:*4911800 mtk-dramk/mt8188: First code drop from MT8188 internal DRAM preloader 27 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/license.txt: -------------------------------------------------------------------------------- 1 | MediaTek Inc. grants permission to use and redistribute aforementioned firmware 2 | files for the use with devices containing MediaTek chipsets, but not as part of 3 | the Linux kernel or in any other form which would require these files themselves 4 | to be covered by the terms of the GNU General Public License or the GNU Lesser 5 | General Public License. 6 | 7 | These firmware files are distributed in the hope that they will be useful, but 8 | are provided WITHOUT ANY WARRANTY, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTY 9 | OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 10 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/mcupm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8188/mcupm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8188/mcupm.bin.md5: -------------------------------------------------------------------------------- 1 | 05b8c9b38d790a3480a5d79a01a47d5b *mcupm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/mcupm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | # v1.01.04 3 | 1. Update CPU DVFS OPP table to enhance power saving. 4 | 5 | # v1.01.03 6 | 1. The efuse memory address is wrong for MCUPM to access. Add the 7 | offset to revise the efuse memory address. 8 | 9 | # v1.01.02 10 | 1. Remove mtk header. 11 | 12 | # v1.01.01 13 | 1. Revise the latency offset in SYSRAM for CPUFreq to be consistent with MT8195. 14 | 15 | # v1.01.00 16 | 1. Initial release. 17 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/spm_firmware.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8188/spm_firmware.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8188/spm_firmware.bin.md5: -------------------------------------------------------------------------------- 1 | e5f3d221be6b549368c7aee91fcad274 *spm_firmware.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/spm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # pcm_suspend_20220705_v2_MP 4 | 1. SPM suspend can turn 26M clock off when system goes into suspend. 5 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/sspm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8188/sspm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8188/sspm.bin.md5: -------------------------------------------------------------------------------- 1 | e5b2c28a74bbb4bf93f8cb04a88a1a72 *sspm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8188/sspm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | # 1.88.01 3 | 1. Add error checking for last_emi to avoid null pointer issue. 4 | 5 | # 1.88.00 6 | 1. Add sspm.bin v1.88.00. 7 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/README.md: -------------------------------------------------------------------------------- 1 | # Firmware list 2 | - drame.elf 3 | - dpm.dm 4 | - dpm.pm 5 | - spm_firmware.bin 6 | - sspm.bin 7 | - mcupm.bin 8 | 9 | -------------------------------------------------------------------------------- 10 | # `dram.elf` Introduction 11 | 12 | `dram.elf` is one ELF format file which is used for calibration. 13 | The dram.elf is loaded at the first time bootup, it will do DRAM 14 | full calibration, and save calibration parameters to NAND (or EMMC) 15 | for faster bootup after the frist bootup. 16 | 17 | ## Who uses it 18 | - coreboot loads `dram.elf` at the first time bootup if no DRAM parameters exist. 19 | 20 | ## How to load `dram.elf` 21 | - coreboot locates `dram.elf` file, and locates the entry point "_start", 22 | then it passes DRAM struct "param", and call _start(¶m) to execute `dram.elf` 23 | flow. 24 | 25 | ## Parameters 26 | ``` 27 | struct dramc_param { 28 | struct dramc_param_header header; // see below 29 | void (*do_putc)(unsigned char c); 30 | struct dramc_data dramc_datas; // see below 31 | }; 32 | ``` 33 | Below shows the internal structure of dramc_param: 34 | ``` 35 | struct dramc_param_header { 36 | u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ 37 | u16 size; /* size of whole dramc_param, update in the coreboot */ 38 | u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ 39 | u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ 40 | }; 41 | 42 | struct dramc_data { 43 | struct ddr_base_info ddr_info; 44 | struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; 45 | }; 46 | 47 | struct ddr_base_info { 48 | u16 config_dvfs; /* DRAMC_PARAM_DVFS_FLAG */ 49 | u16 ddr_type; /* DRAMC_PARAM_DDR_TYPE */ 50 | u16 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ 51 | u16 voltage_type; /* DRAM_PARAM_VOLTAGE_TYPE */ 52 | u32 support_ranks; 53 | u64 rank_size[RANK_MAX]; 54 | struct emi_mdl emi_config; 55 | dram_cbt_mode cbt_mode[RANK_MAX]; 56 | }; 57 | 58 | struct sdram_params { 59 | u32 rank_num; 60 | u16 num_dlycell_perT; 61 | u16 delay_cell_timex100; 62 | 63 | /* duty */ 64 | s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; 65 | s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 66 | s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 67 | ....... 68 | ....... 69 | }; 70 | ``` 71 | 72 | ## The output of `dram.elf` 73 | - `dram.elf` will set the suitable dramc settings, also save the DRAM parameters 74 | to NOR/NAND (or EMMC) on the specified section: "RW_MRC_CACHE". 75 | 76 | ## Return Values 77 | - 0 : means successful. 78 | - < 0 : means failed. 79 | 80 | ## Version 81 | - $ strings dram.elf | grep "firmware version" 82 | MediaTek DRAM firmware version: 1.6.3 83 | 84 | -------------------------------------------------------------------------------- 85 | # DPM Introduction 86 | 87 | DPM is hardware module which is used for DRAM Power Management, which 88 | is used for DRAM low power. 89 | For example: self refresh, disable PLL/DLL when not in used. 90 | 91 | DPM includes two parts of images: data part (`dpm.dm`) and program part (`dpm.pm`). 92 | They are loaded into DPM SRAM when system inits. 93 | 94 | ## Who uses it 95 | - coreboot will load dpm at ramstage. It will copy `dpm.dm` & `dpm.pm` to DPM SRAM. 96 | 97 | ## How to load DPM 98 | - Use CBFS to load `dpm.dm` and `dpm.pm`. 99 | - No need to pass other parameters to DPM. 100 | 101 | ## Return Values 102 | - 0 : means successful; 103 | - -1 : means failed; 104 | 105 | ## Version 106 | - No version yet. 107 | 108 | -------------------------------------------------------------------------------- 109 | # SPM Introduction 110 | 111 | SPM is able to turn off more power such as DRAM self-refresh mode and 26M clock off 112 | when system is in suspend. Also, SPM helps support Vcore DVFS feature. 113 | 114 | ## Who uses it 115 | - Linux kernel system suspend and Vcore DVFS. 116 | 117 | ## How to load `spm_fimware.bin` 118 | - Use CBFS to load "spm_fimware.bin" to DRAM and SPM DMA loads it from dram to SPM SRAM. 119 | 120 | ## Return Values 121 | SPM driver in coreboot checks if pmem_words/dmem_words are 16-byte aligned in `spm_fimware.bin` 122 | - yes : SPM DMA can load `spm_fimware.bin` to SPM SRAM correctly. 123 | - no : assert(0) 124 | 125 | ## Version 126 | Search "spmfw (version" will show log like below 127 | - spmfw (version pcm_suspend_v1.43_no_GPU_WAYEN) 128 | 129 | -------------------------------------------------------------------------------- 130 | # SSPM Introduction 131 | 132 | SSPM is "Secure System Power Manager" that provides power control in secure domain. 133 | SSPM provides power related features, e.g. CPU DVFS, thermal control, to offload 134 | application processor for security reason. 135 | 136 | SSPM firmware is loaded into SSPM SRAM at system initialization. 137 | 138 | ## Who uses it 139 | - coreboot will load sspm.bin to SSPM SRAM at ramstage. 140 | 141 | ## How to load `sspm.bin` 142 | - Use CBFS to load `sspm.bin`. 143 | - No need to pass other parameters to SSPM. 144 | 145 | ## Return Value 146 | - No return value. 147 | 148 | ## Version 149 | - $ strings sspm.bin | grep version 150 | MediaTek SSPM firmware: version 1.0.0 151 | 152 | -------------------------------------------------------------------------------- 153 | # MCUPM Introduction 154 | 155 | MCUPM is a hardware module which is used for MCUSYS Power Management, 156 | for example: core/cluster on/off. MCUPM firmware (`mcupm.bin`) is loaded into 157 | MCUPM SRAM at system initialization. 158 | 159 | ## Who uses it 160 | - coreboot will load MCUPM at ramstage. It will copy mcupm.bin to MCUPM SRAM. 161 | 162 | ## How to load `mcupm.bin` 163 | - Use CBFS to load `mcupm.bin`, then set normal boot flag and release software reset pin of MCUPM. 164 | 165 | ## Return Values 166 | - No return value. 167 | 168 | ## Version 169 | - $ strings mcupm.bin | grep MCUPM 170 | MediaTek MCUPM firmware: version 1.00.07 171 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dpm.dm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8192/dpm.dm -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dpm.md5: -------------------------------------------------------------------------------- 1 | e267f2e23aecfc848ef404dd9dc0f7f6 *dpm.dm 2 | 40a1756efa1e034f868d5ff91a05e89d *dpm.pm 3 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dpm.pm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8192/dpm.pm -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dpm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # 2020.11.05 4 | 1. Add 4266Mbps suspend/resume support. 5 | 6 | # 2020.08.01 7 | 1. Add DRAM suspend/DVFS support. 8 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dram.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8192/dram.elf -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dram.elf.md5: -------------------------------------------------------------------------------- 1 | b0873be4ce5cecc432b21977022ae852 *dram.elf 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/dram_release_notes.txt: -------------------------------------------------------------------------------- 1 | # 1.6.3 2 | 3 | 1. Chrome OS build from 13885.22.0. 4 | Protocol (params header) version: 6 5 | 6 | 2. Include changes: 7 | 8 | CL:*3814555 Revert "dramc: mt8192: set max freq 3200 for discrete DDR" 9 | 10 | # 1.6.2 11 | 12 | 1. Chrome OS build from 13885.15.0. 13 | Protocol (params header) version: 6 14 | 15 | 2. Include changes: 16 | 17 | CL:*3785326 dramc: mt8192: fix emi settings count 18 | CL:*3787636 dramc: mt8192: Include sdram_info in ddr_base_info 19 | CL:*3787637 dramc: mt8192: Update version to 1.6.2 20 | 21 | # 1.6.0 22 | 23 | 1. Chrome OS build from 13869.0.0. 24 | Protocol (params header) version: 6 25 | 26 | 2. Include changes: 27 | 28 | CL:*3674585 dramc: mt8192: Update dramc_param.h for mrc_cache 29 | CL:*3655431 dramc: mt8192: improve discrete DRAM stability 30 | CL:*3693609 dramc: mt8192: Move memory address to 0x00220000 31 | CL:*3678607 dramc: mt8192: fix fast-k gating PI P1 initialization 32 | CL:*3704751 dramc: mt8192: Move memory address to 0x00210000 33 | 34 | # 1.5.1 35 | 36 | 1. A local build from 71629f0 (CL:*3639823), incompatible with previous versions. 37 | Protocol (params header) version: 5 38 | 39 | 2. Include changes: 40 | 41 | CL:*3475447 dramc: mt8192: enable per-bank refresh 42 | CL:*3531917 dramc: mt8192: Add ddr_type for struct sdram_info 43 | CL:*3517916 dramc: mt8192: Add EMI Settings of 8GB normal mode 44 | CL:*3568265 dramc: mt8192: Move memory address to 0x00250000 (Depends: CB:50017) 45 | CL:*3574468 dramc: mt8192: Add blob version 46 | CL:*3596349 dramc: mt8192: set max freq 3200 for discrete DDR 47 | CL:*3639823 dramc: mt8192: fix blob version issue 48 | 49 | # 2020.12.01 50 | 51 | 1. A local build and incompatible with previous versions. 52 | Header version = 5. 53 | 2. Include changes: 54 | 55 | CL:*3438249 dramc: MT8192: Add discrete DDR support 56 | 57 | # 2020.11.05 58 | 59 | 1. A local build and incompatible with previous versions. 60 | Header version = 4. 61 | 2. Include changes: 62 | 63 | CL:*3398084 dramc: MT8192: add max freq flag 64 | 65 | # 2020.09.16 66 | 67 | 1. Built from Chrome OS 13473.0.2020_09_16_2253. 68 | 2. Include changes: 69 | 70 | eed9075 dramc: MT8192: Use clear data rate log format 71 | c57d520 dramc: MT8192: Adjust vcore voltage to correct value for DDR calibration 72 | a3651f6 pmic: MT6359: Allow to modify VGPU11 voltage 73 | bdff3f3 dramc: MT8192: Update the output message for easy debug 74 | 824f1e0 dramc: MT8192: Load correct emi setting by the ddr geometry 75 | f488694 dramc: MT8192: Save the dramc params result after calibration 76 | adab87d dramc: MT8192: Update the dramc param struct 77 | 3a1c53e dramc: MT8192: Update the dram control drivers 78 | a87ece6 dramc: MT8192: Add RX gating fast calibration flow 79 | c112bf9 dramc: MT8192: Add DRAM full calibration blob source code 80 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/license.txt: -------------------------------------------------------------------------------- 1 | MediaTek Inc. grants permission to use and redistribute aforementioned firmware 2 | files for the use with devices containing MediaTek chipsets, but not as part of 3 | the Linux kernel or in any other form which would require these files themselves 4 | to be covered by the terms of the GNU General Public License or the GNU Lesser 5 | General Public License. 6 | 7 | These firmware files are distributed in the hope that they will be useful, but 8 | are provided WITHOUT ANY WARRANTY, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTY 9 | OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 10 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/mcupm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8192/mcupm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8192/mcupm.bin.md5: -------------------------------------------------------------------------------- 1 | 59de2352b53f52c6edf176f02ceca3ee mcupm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/mcupm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # 1.00.07 4 | 1. Add 2.6G CPU DVFS segment 5 | 6 | # 1.00.06 7 | 1. Add version number 8 | 2. Modify SRAM layout for CPU DVFS 9 | 10 | # 2020.11.12 11 | 1. Update mcupm.bin to v1.0.5 12 | 2. Add EM table into mcupm 13 | 3. Add SVS CPU 14 | 15 | # 2020.09.11 16 | 1. Update mcupm.bin to v1.0.4 17 | 2. Add cpufreq opp table into MCUPM 18 | 19 | # 2020.08.27 20 | 1. Update mcupm.bin to v1.0.3 21 | 2. Change private table setting for chrome book 22 | 23 | # 2020.08.19 24 | 1. Update mcupm.bin to v1.0.2 25 | 2. Fix build/release flow bug 26 | 27 | # 2020.08.19 28 | 1. Update mcupm.bin to v1.0.1 29 | 2. Initialize private table in MCUPM 30 | 31 | # 2020.08 32 | 1. Launch MCUPM as mcusys control interface 33 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/spm_firmware.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8192/spm_firmware.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8192/spm_firmware.bin.md5: -------------------------------------------------------------------------------- 1 | 7da2cadcb7051dc8fa91495f99cda851 *spm_firmware.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/spm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # 2020.11.11 4 | 1. SPM suspend can turn 26M clock off when system goes into suspend. 5 | 6 | # 2020.07 7 | 1. Support SPM suspend at the end of system suspend. 8 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/sspm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8192/sspm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8192/sspm.bin.md5: -------------------------------------------------------------------------------- 1 | 8d6d154ccde77ba7a618505f7ab66daa *sspm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8192/sspm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # 1.0.0 4 | 1. Add version number. 5 | 2. Disable boot log 6 | 7 | # 2020.11.19 (no version) 8 | 1. Add SSPM firmware. 9 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/README.md: -------------------------------------------------------------------------------- 1 | # Firmware list 2 | - mcupm.bin 3 | - sspm.bin 4 | - spm_firmware.bin 5 | - dram.elf 6 | - dpm.dm 7 | - dpm.pm 8 | 9 | -------------------------------------------------------------------------------- 10 | # MCUPM introduction 11 | MCUPM is a hardware module which is used for MCUSYS Power Management. 12 | MCUPM firmware (`mcupm.bin`) is loaded into MCUPM SRAM at system initialization. 13 | 14 | ## Who uses it 15 | coreboot will load MCUPM at ramstage. It will copy mcupm.bin to MCUPM SRAM. 16 | 17 | ## How to load `mcupm.bin` 18 | Use CBFS to load `mcupm.bin`, then set normal boot flag and release software reset pin of MCUPM. 19 | 20 | ## Return values 21 | No return value. 22 | 23 | ## Version 24 | `$ strings mcupm.bin | grep "MCUPM firmware"` 25 | 26 | -------------------------------------------------------------------------------- 27 | # SSPM introduction 28 | SSPM is "Secure System Power Manager" that provides power control in secure domain. 29 | SSPM provides power related features, e.g. CPU DVFS, thermal control, to offload 30 | application processor for security reason. 31 | 32 | SSPM firmware is loaded into SSPM SRAM at system initialization. 33 | 34 | ## Who uses it 35 | coreboot will load sspm.bin to SSPM SRAM at ramstage. 36 | 37 | ## How to load `sspm.bin` 38 | Use CBFS to load `sspm.bin`. 39 | No need to pass other parameters to SSPM. 40 | 41 | ## Return value 42 | No return value. 43 | 44 | ## Version 45 | `$ strings sspm.bin | grep "SSPM firmware"` 46 | 47 | -------------------------------------------------------------------------------- 48 | # SPM introduction 49 | SPM is able to turn off more power such as DRAM self-refresh mode and 26M clock off 50 | when system is in suspend. Also, SPM helps support Vcore DVFS feature. 51 | 52 | ## Who uses it 53 | Linux kernel system suspend and Vcore DVFS. 54 | 55 | ## How to load `spm_fimware.bin` 56 | Use CBFS to load `spm_fimware.bin` to DRAM and SPM DMA loads it from dram to SPM SRAM. 57 | 58 | ## Return values 59 | No return value. 60 | 61 | ## Version 62 | `$ strings spm_firmware.bin | grep pcm_suspend` 63 | 64 | -------------------------------------------------------------------------------- 65 | # `dram.elf` introduction 66 | `dram.elf` is an ELF format file, which performs DRAM full calibration and 67 | returns the trained calibration parameters to the caller. 68 | The caller may store the parameters on NOR/NAND or eMMC for faster subsequent 69 | bootups. 70 | 71 | ## Who uses it 72 | coreboot loads `dram.elf` during the first bootup if no valid DRAM parameters 73 | are found on NOR/NAND or eMMC. 74 | 75 | ## How to load `dram.elf` 76 | coreboot locates `dram.elf` file, locates the entry point `_start`, 77 | passes a `dramc_param` struct argument `dparam` to it, and calls 78 | `_start(&dparam)` to execute `dram.elf`. 79 | 80 | ## Parameters 81 | ``` 82 | struct dramc_param { 83 | struct dramc_param_header header; // see below 84 | void (*do_putc)(unsigned char c); 85 | struct dramc_data dramc_datas; // see below 86 | }; 87 | ``` 88 | 89 | Below shows the internal structure of `dramc_param`: 90 | ``` 91 | struct dramc_param_header { 92 | u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ 93 | u16 size; /* size of whole dramc_param, update in the coreboot */ 94 | u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ 95 | u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ 96 | }; 97 | 98 | struct sdram_info { 99 | u32 ddr_type; /* SDRAM_DDR_TYPE */ 100 | u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ 101 | }; 102 | 103 | struct sdram_params { 104 | u32 rank_num; 105 | u16 num_dlycell_perT; 106 | u16 delay_cell_timex100; 107 | 108 | /* duty */ 109 | s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; 110 | s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 111 | s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; 112 | ....... 113 | ....... 114 | }; 115 | 116 | struct emi_mdl { 117 | u32 cona_val; 118 | u32 conh_val; 119 | u32 conf_val; 120 | u32 chn_cona_val; 121 | }; 122 | 123 | struct ddr_base_info { 124 | u32 config_dvfs; /* SDRAM_DVFS_FLAG */ 125 | struct sdram_info sdram; 126 | u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ 127 | u32 support_ranks; 128 | u64 rank_size[RANK_MAX]; 129 | struct emi_mdl emi_config; 130 | DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; 131 | }; 132 | 133 | struct dramc_data { 134 | struct ddr_base_info ddr_info; 135 | struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; 136 | }; 137 | ``` 138 | 139 | ## The output of `dram.elf` 140 | `dram.elf` configures suitable dramc settings and returns the DRAM parameters. 141 | Then, coreboot saves the parameters on the specified firmware flash section: 142 | `"RW_MRC_CACHE"`. 143 | 144 | ## Return values 145 | 0 on success; < 0 on failure. 146 | 147 | ## Version 148 | `$ strings dram.elf | grep "firmware version"` 149 | 150 | -------------------------------------------------------------------------------- 151 | # DPM introduction 152 | DPM is a hardware module for DRAM Power Management, which is used for DRAM low power. 153 | For example: self refresh, disable PLL/DLL when not in use. 154 | 155 | DPM includes two parts of images: data part (`dpm.dm`) and program part (`dpm.pm`). 156 | 157 | ## Who uses it 158 | Coreboot loads dpm at ramstage, and copies `dpm.dm` & `dpm.pm` to DPM SRAM. 159 | 160 | ## How to load DPM 161 | Use CBFS to load `dpm.dm` and `dpm.pm`. 162 | No need to pass other parameters to DPM. 163 | 164 | ## Return values 165 | No return value. 166 | 167 | ## Add version 168 | ``` 169 | $ echo -n 'DPMD Firmware version: x.x' >> dpm.dm 170 | $ echo -n 'DPMP Firmware version: x.x' >> dpm.pm 171 | ``` 172 | 173 | ## Version 174 | ``` 175 | $ strings dpm.dm | grep version 176 | $ strings dpm.pm | grep version 177 | ``` 178 | 179 | -------------------------------------------------------------------------------- 180 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dpm.dm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8195/dpm.dm -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dpm.dm.md5: -------------------------------------------------------------------------------- 1 | fabc06d8e697fcbda135576997b5d86c *dpm.dm 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dpm.pm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8195/dpm.pm -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dpm.pm.md5: -------------------------------------------------------------------------------- 1 | 8806d7a7ee847e04ff9996b39d746829 *dpm.pm 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dpm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # Version 1.0 4 | 1. Add DRAM suspend/DVFS support. 5 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dram.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8195/dram.elf -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dram.elf.md5: -------------------------------------------------------------------------------- 1 | 7c42083cf2cc78c1f16e3a0f8fd00054 *dram.elf 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/dram_release_notes.txt: -------------------------------------------------------------------------------- 1 | # 1.9.1 2 | 1. Chrome OS build from 14545.0.0. 3 | Protocol (params header) version: 9 4 | 5 | 2. Included changes: 6 | 7 | CL:*4585853: mtk-dramk/mt8186,8192,8195: Refactor dramc_param to share more structures 8 | 9 | # 1.8.1 10 | 11 | 1. Chrome OS build from 14507.0.0. 12 | Protocol (params header) version: 8 13 | 14 | 2. Included changes: 15 | 16 | CL:*4389197: mtk-dramk/mt8186,8192,8195: Extract dramc_param_header to common header 17 | 18 | # 1.7.1 19 | 20 | Protocol (params header) version: 7 21 | 22 | Include changes: 23 | 24 | CL:*3960396 mtk-dramk/mt8195: DRAMC: Update the DRAMC_PARAM_HEADER_VERSION to '7' 25 | CL:*3960395 mtk-dramk/mt8195: Add version information 26 | CL:*3960394 mtk-dramk/mt8195: Add pmic driver to get Vcore 27 | CL:*3960393 mtk-dramk/mt8195: DRAMC: Add unsigned define value. 28 | CL:*3960392 mtk-dramk/mt8195: DRAMC: Enable vref calibration at DDR3200 for enter/exit S0 stability. 29 | CL:*3960391 mtk-dramk/mt8195: DRAMC: Duty calibration criteira is not proper, redefine the criteria value. 30 | CL:*3960390 mtk-dramk/mt8195: DRAMC: Duty Last K global variables use channel to save last K values. 31 | CL:*3960389 mtk-dramk/mt8195: Chrome fast k flow porting 32 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/license.txt: -------------------------------------------------------------------------------- 1 | MediaTek Inc. grants permission to use and redistribute aforementioned firmware 2 | files for the use with devices containing MediaTek chipsets, but not as part of 3 | the Linux kernel or in any other form which would require these files themselves 4 | to be covered by the terms of the GNU General Public License or the GNU Lesser 5 | General Public License. 6 | 7 | These firmware files are distributed in the hope that they will be useful, but 8 | are provided WITHOUT ANY WARRANTY, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTY 9 | OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 10 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/mcupm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8195/mcupm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8195/mcupm.bin.md5: -------------------------------------------------------------------------------- 1 | 8a0641145c57bcb223f27e3cca9f0572 *mcupm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/mcupm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # v1.02.00 4 | 1. Support CPU frequency for both 3.0G and 2.6G. 5 | 6 | # v1.01.00 7 | 1. Add mcupm thermal features. 8 | 9 | # v1.00.00 10 | 1. Initial release. 11 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/spm_firmware.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8195/spm_firmware.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8195/spm_firmware.bin.md5: -------------------------------------------------------------------------------- 1 | 8f22ddf9d2ca7a780c2d7cf33727f2a6 *spm_firmware.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/spm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | # pcm_suspend_v1.0_20210519 4 | 1. SPM suspend can turn 26M clock off when system goes into suspend. 5 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/sspm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/soc/mediatek/mt8195/sspm.bin -------------------------------------------------------------------------------- /soc/mediatek/mt8195/sspm.bin.md5: -------------------------------------------------------------------------------- 1 | 2695108b761bc3e55b7eb27358248059 *sspm.bin 2 | -------------------------------------------------------------------------------- /soc/mediatek/mt8195/sspm_release_notes.txt: -------------------------------------------------------------------------------- 1 | ** Build from MediaTek Internal ** 2 | 3 | read version string via this command 4 | $ strings sspm.bin | grep "version" 5 | 6 | # v1.0.0 7 | 1. Add sspm.bin v1.0.0. 8 | -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/AmdPubKey.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/AmdPubKey.bin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspBootLoader.Bypass.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/PspBootLoader.Bypass.sbin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspEarlyUnlock.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/PspEarlyUnlock.sbin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspNvram.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/PspNvram.bin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspRecovery.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/PspRecovery.sbin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspReleaseNote.txt: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // PSP FW Delivery Release Note 3 | // 4 | // Copyright 2014, Advanced Micro Devices, Inc. 5 | // Image Version number: PSP BootLoader: D.1.1.4D, PSP SecureOS: D.1.1.4D 6 | // Date: 07/06/2015 7 | //---------------------------------------------------------------------------- 8 | 9 | Files: 10 | PspBootLoader.Bypass.sbin - PSP bootloader with HVB bypass enabled 11 | PspRecovery.sbin - PSP Recovery boot loader 12 | PspSecureOs.sbin - PSP secure OS, signed with production key version 13 | PspNvram.bin - NV storage pattern used to populate the SPI-ROM. 14 | PspTrustlets.bin - PSP Trustlet binaries 15 | 16 | 17 | Features and fixes: 18 | - Rollback //depot/psp/stg/fw/1.0/fw/mars/src/bios_mailbox.c to revision 4 to avoid timing issue; 19 | - Code base updated to CL#30102; 20 | -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspSecureDebug.Key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/PspSecureDebug.Key -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/PspSecureOs.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/PspSecureOs.sbin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/RtmPubSigned.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/RtmPubSigned.key -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/SmuFirmware.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/SmuFirmware.sbin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/SmuScs.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/SmuScs.bin -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/Trustlet.tkn.cert: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/Trustlet.tkn.cert -------------------------------------------------------------------------------- /southbridge/amd/avalon/PSP/trustlets.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/PSP/trustlets.bin -------------------------------------------------------------------------------- /southbridge/amd/avalon/Release_AvalonXHC.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/Release_AvalonXHC.txt -------------------------------------------------------------------------------- /southbridge/amd/avalon/Release_IMC_Mullins.txt: -------------------------------------------------------------------------------- 1 | Release 1.0.1 2 | 3 | Dec 20, 2013 4 | 5 | Change log: 6 | 7 | Update SMBus port address register location for Avalon IMC 8 | 9 | Known issues: 10 | 11 | None 12 | 13 | =============================================================================== 14 | Release 1.0.0 15 | 16 | Jun 10, 2013 17 | 18 | Change log: 19 | 20 | Initial release 21 | 22 | Known issues: 23 | 24 | None 25 | -------------------------------------------------------------------------------- /southbridge/amd/avalon/imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/imc.bin -------------------------------------------------------------------------------- /southbridge/amd/avalon/xhci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/avalon/xhci.bin -------------------------------------------------------------------------------- /southbridge/amd/bolton/XHCI_Release_Notes.txt: -------------------------------------------------------------------------------- 1 | Release Notes 2 | ============= 3 | xHC FW 4 | 5 | -------------------------------------------- 6 | Version 1.1.0.0059 7 | -------------------------------------------- 8 | Enhancements: 9 | ============= 10 | 1. Add a workaround to prevent controller from STOP in run mode. Otherwise the compliance test will fail. 11 | 12 | -------------------------------------------- 13 | Version 1.1.0.0055 14 | -------------------------------------------- 15 | Enhancements: 16 | ============= 17 | 1. Removed SBD and FSE bits. 18 | 19 | -------------------------------------------- 20 | Version 1.1.0.0049 21 | -------------------------------------------- 22 | Enhancements: 23 | ============= 24 | 1. The release supports Bolton series chipsets. 25 | 26 | 27 | -------------------------------------------------------------------------------- /southbridge/amd/bolton/imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/bolton/imc.bin -------------------------------------------------------------------------------- /southbridge/amd/bolton/xhci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/bolton/xhci.bin -------------------------------------------------------------------------------- /southbridge/amd/hudson/Release_Hudson2XHC.txt: -------------------------------------------------------------------------------- 1 | Release Notes 2 | ============= 3 | xHC FW 4 | 5 | -------------------------------------------- 6 | Version 1.0.0.48 7 | -------------------------------------------- 8 | Enhancements: 9 | ============= 10 | 1. The release corrects an issue where the system would hang when unplugging a USB mouse and plugging in a USB 3.0 storage device while in the S3 state. 11 | 12 | -------------------------------------------- 13 | Version 1.0.0.44 14 | -------------------------------------------- 15 | Enhancements: 16 | ============= 17 | 1. The release supports Hudson-3 series chipsets. 18 | -------------------------------------------------------------------------------- /southbridge/amd/hudson/imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/hudson/imc.bin -------------------------------------------------------------------------------- /southbridge/amd/hudson/xhci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/hudson/xhci.bin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/AmdPubKeyCZ.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspAgesaS3Resume_prod_CZ.csbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspAgesaS3Resume_prod_CZ.csbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspBootLoader_prod_CZ.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspBootLoader_prod_CZ.sbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspNvramCZ.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspNvramCZ.bin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspNvramS3_CZ.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspNvramS3_CZ.bin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspRecoveryBootLoader_prod_CZ.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspRecoveryBootLoader_prod_CZ.sbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspSecureDebugCZ.Key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspSecureDebugCZ.Key -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspSecureOs_prod_CZ.csbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspSecureOs_prod_CZ.csbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/PspTrustlets_prod_CZ.cbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/PspTrustlets_prod_CZ.cbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/ReleaseNote.txt: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // PSP FW Delivery Release Note 3 | // 4 | // Copyright 2015, Advanced Micro Devices, Inc. 5 | // Image Version number: PSP BootLoader: 0.2.0.35, PSP SecureOS: 0.2.0.35 6 | // Date: July 15, 2015 7 | //---------------------------------------------------------------------------- 8 | 9 | Content: 10 | PSP FW Deliverables for Carrizo Bring Up. 11 | This Build is compiled using the ARM license from the AMD license server. 12 | 13 | Files: 14 | PspBootLoader_prod_CZ.sbin - PSP offchip BootLoader, signed with production key version 15 | PspRecoveryBootLoader_prod_CZ.sbin - PSP offchip Recovery BootLoader, signed with production key version 16 | PspAgesaS3Resume_prod_CZ.csbin - PSP Agesa S3 resume, signed with production key version and compressed 17 | PspSecureOs_prod_CZ.csbin - PSP secure OS, signed with production key version and compressed 18 | PspTrustlets_prod_CZ.cbin - PSP secure OS system trustlets, not signed but compressed 19 | 20 | Features and fixes: 21 | 1. ENH466357: Reduce PSP/SMN clock back to 300 MHz as a temporarily workaround for eCZ B10/A10 fused parts. 22 | 2. Code base updated up to CL#30190. 23 | -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/RtmPubSignedCZ.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/RtmPubSignedCZ.key -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/SmuFirmware2_prod_CZ.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/SmuFirmware2_prod_CZ.sbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/SmuFirmwareCZ.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/SmuFirmwareCZ.sbin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/SmuScsCZ.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/SmuScsCZ.bin -------------------------------------------------------------------------------- /southbridge/amd/kern/PSP/TrustletKey_prod_CZ.sbin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/PSP/TrustletKey_prod_CZ.sbin -------------------------------------------------------------------------------- /southbridge/amd/kern/imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/imc.bin -------------------------------------------------------------------------------- /southbridge/amd/kern/xhci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/kern/xhci.bin -------------------------------------------------------------------------------- /southbridge/amd/yangtze/imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/yangtze/imc.bin -------------------------------------------------------------------------------- /southbridge/amd/yangtze/xhci.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/coreboot/blobs/475dce449451c2a10bd8b7b056f12e6b56ef5fdc/southbridge/amd/yangtze/xhci.bin --------------------------------------------------------------------------------