├── .gitignore
├── LICENSE
├── Makefile.in
├── README.md
├── configure
├── configure.ac
├── conftest.py
├── dataset
├── Prob01p01_comb_const_zero_prompt.txt
├── Prob01p01_comb_const_zero_test.py
├── Prob01p01_comb_const_zero_test.v
├── Prob01p02_comb_const_one_prompt.txt
├── Prob01p02_comb_const_one_test.py
├── Prob01p02_comb_const_one_test.v
├── Prob01p03_comb_const_lohi_prompt.txt
├── Prob01p03_comb_const_lohi_test.py
├── Prob01p03_comb_const_lohi_test.v
├── Prob01p04_comb_const_32b_value_prompt.txt
├── Prob01p04_comb_const_32b_value_test.py
├── Prob01p04_comb_const_32b_value_test.v
├── Prob02p01_comb_wires_8b_passthru_prompt.txt
├── Prob02p01_comb_wires_8b_passthru_test.py
├── Prob02p01_comb_wires_8b_passthru_test.v
├── Prob02p02_comb_wires_16b_split_prompt.txt
├── Prob02p02_comb_wires_16b_split_test.py
├── Prob02p02_comb_wires_16b_split_test.v
├── Prob02p03_comb_wires_8b_bit_rev_prompt.txt
├── Prob02p03_comb_wires_8b_bit_rev_test.py
├── Prob02p03_comb_wires_8b_bit_rev_test.v
├── Prob02p04_comb_wires_100b_bit_rev_prompt.txt
├── Prob02p04_comb_wires_100b_bit_rev_test.py
├── Prob02p04_comb_wires_100b_bit_rev_test.v
├── Prob02p05_comb_wires_64b_byte_rev_prompt.txt
├── Prob02p05_comb_wires_64b_byte_rev_test.py
├── Prob02p05_comb_wires_64b_byte_rev_test.v
├── Prob02p06_comb_wires_4x2b_passthru_prompt.txt
├── Prob02p06_comb_wires_4x2b_passthru_test.py
├── Prob02p06_comb_wires_4x2b_passthru_test.v
├── Prob02p07_comb_wires_5x3b_to_4x4b_prompt.txt
├── Prob02p07_comb_wires_5x3b_to_4x4b_test.py
├── Prob02p07_comb_wires_5x3b_to_4x4b_test.v
├── Prob02p08_comb_wires_sext_prompt.txt
├── Prob02p08_comb_wires_sext_test.py
├── Prob02p08_comb_wires_sext_test.v
├── Prob03p01_comb_gates_and_prompt.txt
├── Prob03p01_comb_gates_and_test.py
├── Prob03p01_comb_gates_and_test.v
├── Prob03p02_comb_gates_nor_prompt.txt
├── Prob03p02_comb_gates_nor_test.py
├── Prob03p02_comb_gates_nor_test.v
├── Prob03p03_comb_gates_aoi21_prompt.txt
├── Prob03p03_comb_gates_aoi21_test.py
├── Prob03p03_comb_gates_aoi21_test.v
├── Prob03p04_comb_gates_oai22_prompt.txt
├── Prob03p04_comb_gates_oai22_test.py
├── Prob03p04_comb_gates_oai22_test.v
├── Prob03p05_comb_gates_hadd_prompt.txt
├── Prob03p05_comb_gates_hadd_test.py
├── Prob03p05_comb_gates_hadd_test.v
├── Prob03p06_comb_gates_fadd_prompt.txt
├── Prob03p06_comb_gates_fadd_test.py
├── Prob03p06_comb_gates_fadd_test.v
├── Prob03p07_comb_gates_4_input_prompt.txt
├── Prob03p07_comb_gates_4_input_test.py
├── Prob03p07_comb_gates_4_input_test.v
├── Prob03p08_comb_gates_100_input_prompt.txt
├── Prob03p08_comb_gates_100_input_test.py
├── Prob03p08_comb_gates_100_input_test.v
├── Prob03p09_comb_gates_bitwise_prompt.txt
├── Prob03p09_comb_gates_bitwise_test.py
├── Prob03p09_comb_gates_bitwise_test.v
├── Prob03p10_comb_gates_4b_pairwise_prompt.txt
├── Prob03p10_comb_gates_4b_pairwise_test.py
├── Prob03p10_comb_gates_4b_pairwise_test.v
├── Prob03p11_comb_gates_100b_pairwise_prompt.txt
├── Prob03p11_comb_gates_100b_pairwise_test.py
├── Prob03p11_comb_gates_100b_pairwise_test.v
├── Prob03p12_comb_gates_nl0_prompt.txt
├── Prob03p12_comb_gates_nl0_test.py
├── Prob03p12_comb_gates_nl0_test.v
├── Prob03p13_comb_gates_nl1_prompt.txt
├── Prob03p13_comb_gates_nl1_test.py
├── Prob03p13_comb_gates_nl1_test.v
├── Prob04p01_comb_bool_logic_eq0_prompt.txt
├── Prob04p01_comb_bool_logic_eq0_test.py
├── Prob04p01_comb_bool_logic_eq0_test.v
├── Prob04p02_comb_bool_logic_eq1_prompt.txt
├── Prob04p02_comb_bool_logic_eq1_test.py
├── Prob04p02_comb_bool_logic_eq1_test.v
├── Prob04p03_comb_bool_logic_eq2_prompt.txt
├── Prob04p03_comb_bool_logic_eq2_test.py
├── Prob04p03_comb_bool_logic_eq2_test.v
├── Prob04p04_comb_bool_truth_tbl0_prompt.txt
├── Prob04p04_comb_bool_truth_tbl0_test.py
├── Prob04p04_comb_bool_truth_tbl0_test.v
├── Prob04p05_comb_bool_truth_tbl1_prompt.txt
├── Prob04p05_comb_bool_truth_tbl1_test.py
├── Prob04p05_comb_bool_truth_tbl1_test.v
├── Prob04p06_comb_bool_truth_tbl2_prompt.txt
├── Prob04p06_comb_bool_truth_tbl2_test.py
├── Prob04p06_comb_bool_truth_tbl2_test.v
├── Prob04p07_comb_bool_kmap0_prompt.txt
├── Prob04p07_comb_bool_kmap0_test.py
├── Prob04p07_comb_bool_kmap0_test.v
├── Prob04p08_comb_bool_kmap1_prompt.txt
├── Prob04p08_comb_bool_kmap1_test.py
├── Prob04p08_comb_bool_kmap1_test.v
├── Prob04p09_comb_bool_kmap2_prompt.txt
├── Prob04p09_comb_bool_kmap2_test.py
├── Prob04p09_comb_bool_kmap2_test.v
├── Prob04p10_comb_bool_waveform0_prompt.txt
├── Prob04p10_comb_bool_waveform0_test.py
├── Prob04p10_comb_bool_waveform0_test.v
├── Prob04p11_comb_bool_waveform1_prompt.txt
├── Prob04p11_comb_bool_waveform1_test.py
├── Prob04p11_comb_bool_waveform1_test.v
├── Prob04p12_comb_bool_waveform2_prompt.txt
├── Prob04p12_comb_bool_waveform2_test.py
├── Prob04p12_comb_bool_waveform2_test.v
├── Prob04p13_comb_bool_nl_lights_prompt.txt
├── Prob04p13_comb_bool_nl_lights_test.py
├── Prob04p13_comb_bool_nl_lights_test.v
├── Prob04p14_comb_bool_nl_ringer_prompt.txt
├── Prob04p14_comb_bool_nl_ringer_test.py
├── Prob04p14_comb_bool_nl_ringer_test.v
├── Prob04p15_comb_bool_nl_thermostat_prompt.txt
├── Prob04p15_comb_bool_nl_thermostat_test.py
├── Prob04p15_comb_bool_nl_thermostat_test.v
├── Prob05p01_comb_mux_1b_2to1_prompt.txt
├── Prob05p01_comb_mux_1b_2to1_test.py
├── Prob05p01_comb_mux_1b_2to1_test.v
├── Prob05p02_comb_mux_1b_8to1_prompt.txt
├── Prob05p02_comb_mux_1b_8to1_test.py
├── Prob05p02_comb_mux_1b_8to1_test.v
├── Prob05p03_comb_mux_1b_1to8_prompt.txt
├── Prob05p03_comb_mux_1b_1to8_test.py
├── Prob05p03_comb_mux_1b_1to8_test.v
├── Prob05p04_comb_mux_4b_8to1_prompt.txt
├── Prob05p04_comb_mux_4b_8to1_test.py
├── Prob05p04_comb_mux_4b_8to1_test.v
├── Prob05p05_comb_mux_4b_1to8_prompt.txt
├── Prob05p05_comb_mux_4b_1to8_test.py
├── Prob05p05_comb_mux_4b_1to8_test.v
├── Prob05p06_comb_mux_4b_5to1_prompt.txt
├── Prob05p06_comb_mux_4b_5to1_test.py
├── Prob05p06_comb_mux_4b_5to1_test.v
├── Prob05p07_comb_mux_4b_1to5_prompt.txt
├── Prob05p07_comb_mux_4b_1to5_test.py
├── Prob05p07_comb_mux_4b_1to5_test.v
├── Prob05p08_comb_mux_1b_128to1_prompt.txt
├── Prob05p08_comb_mux_1b_128to1_test.py
├── Prob05p08_comb_mux_1b_128to1_test.v
├── Prob05p09_comb_mux_1b_1to128_prompt.txt
├── Prob05p09_comb_mux_1b_1to128_test.py
├── Prob05p09_comb_mux_1b_1to128_test.v
├── Prob06p01_comb_codes_enc_4to2_prompt.txt
├── Prob06p01_comb_codes_enc_4to2_test.py
├── Prob06p01_comb_codes_enc_4to2_test.v
├── Prob06p02_comb_codes_enc_16to4_prompt.txt
├── Prob06p02_comb_codes_enc_16to4_test.py
├── Prob06p02_comb_codes_enc_16to4_test.v
├── Prob06p03_comb_codes_dec_2to4_prompt.txt
├── Prob06p03_comb_codes_dec_2to4_test.py
├── Prob06p03_comb_codes_dec_2to4_test.v
├── Prob06p04_comb_codes_dec_4to16_prompt.txt
├── Prob06p04_comb_codes_dec_4to16_test.py
├── Prob06p04_comb_codes_dec_4to16_test.v
├── Prob06p05_comb_codes_penc_4to2_prompt.txt
├── Prob06p05_comb_codes_penc_4to2_test.py
├── Prob06p05_comb_codes_penc_4to2_test.v
├── Prob06p06_comb_codes_penc_16to4_prompt.txt
├── Prob06p06_comb_codes_penc_16to4_test.py
├── Prob06p06_comb_codes_penc_16to4_test.v
├── Prob06p07_comb_codes_bin2gcode_prompt.txt
├── Prob06p07_comb_codes_bin2gcode_test.py
├── Prob06p07_comb_codes_bin2gcode_test.v
├── Prob06p08_comb_codes_gcode2bin_prompt.txt
├── Prob06p08_comb_codes_gcode2bin_test.py
├── Prob06p08_comb_codes_gcode2bin_test.v
├── Prob06p09_comb_codes_bin2bcd_prompt.txt
├── Prob06p09_comb_codes_bin2bcd_test.py
├── Prob06p09_comb_codes_bin2bcd_test.v
├── Prob06p10_comb_codes_bcd2bin_prompt.txt
├── Prob06p10_comb_codes_bcd2bin_test.py
├── Prob06p10_comb_codes_bcd2bin_test.v
├── Prob06p11_comb_codes_bin2ascii_prompt.txt
├── Prob06p11_comb_codes_bin2ascii_test.py
├── Prob06p11_comb_codes_bin2ascii_test.v
├── Prob06p12_comb_codes_ascii2bin_prompt.txt
├── Prob06p12_comb_codes_ascii2bin_test.py
├── Prob06p12_comb_codes_ascii2bin_test.v
├── Prob06p13_comb_codes_8b_parity_prompt.txt
├── Prob06p13_comb_codes_8b_parity_test.py
├── Prob06p13_comb_codes_8b_parity_test.v
├── Prob06p14_comb_codes_100b_parity_prompt.txt
├── Prob06p14_comb_codes_100b_parity_test.py
├── Prob06p14_comb_codes_100b_parity_test.v
├── Prob07p01_comb_arith_8b_add_prompt.txt
├── Prob07p01_comb_arith_8b_add_test.py
├── Prob07p01_comb_arith_8b_add_test.v
├── Prob07p02_comb_arith_8b_add_carry_prompt.txt
├── Prob07p02_comb_arith_8b_add_carry_test.py
├── Prob07p02_comb_arith_8b_add_carry_test.v
├── Prob07p03_comb_arith_8b_sub_prompt.txt
├── Prob07p03_comb_arith_8b_sub_test.py
├── Prob07p03_comb_arith_8b_sub_test.v
├── Prob07p04_comb_arith_8b_popcount_prompt.txt
├── Prob07p04_comb_arith_8b_popcount_test.py
├── Prob07p04_comb_arith_8b_popcount_test.v
├── Prob07p05_comb_arith_100b_popcount_prompt.txt
├── Prob07p05_comb_arith_100b_popcount_test.py
├── Prob07p05_comb_arith_100b_popcount_test.v
├── Prob07p06_comb_arith_8b_shifter_prompt.txt
├── Prob07p06_comb_arith_8b_shifter_test.py
├── Prob07p06_comb_arith_8b_shifter_test.v
├── Prob07p07_comb_arith_8b_sra_prompt.txt
├── Prob07p07_comb_arith_8b_sra_test.py
├── Prob07p07_comb_arith_8b_sra_test.v
├── Prob07p08_comb_arith_8b_rotator_prompt.txt
├── Prob07p08_comb_arith_8b_rotator_test.py
├── Prob07p08_comb_arith_8b_rotator_test.v
├── Prob07p09_comb_arith_8b_umul_prompt.txt
├── Prob07p09_comb_arith_8b_umul_test.py
├── Prob07p09_comb_arith_8b_umul_test.v
├── Prob07p10_comb_arith_8b_smul_prompt.txt
├── Prob07p10_comb_arith_8b_smul_test.py
├── Prob07p10_comb_arith_8b_smul_test.v
├── Prob07p11_comb_arith_8b_fxp_umul_prompt.txt
├── Prob07p11_comb_arith_8b_fxp_umul_test.py
├── Prob07p11_comb_arith_8b_fxp_umul_test.v
├── Prob07p12_comb_arith_8b_madd_prompt.txt
├── Prob07p12_comb_arith_8b_madd_test.py
├── Prob07p12_comb_arith_8b_madd_test.v
├── Prob07p13_comb_arith_8b_ucmp_prompt.txt
├── Prob07p13_comb_arith_8b_ucmp_test.py
├── Prob07p13_comb_arith_8b_ucmp_test.v
├── Prob07p14_comb_arith_8b_scmp_prompt.txt
├── Prob07p14_comb_arith_8b_scmp_test.py
├── Prob07p14_comb_arith_8b_scmp_test.v
├── Prob07p15_comb_arith_8b_alu_prompt.txt
├── Prob07p15_comb_arith_8b_alu_test.py
├── Prob07p15_comb_arith_8b_alu_test.v
├── Prob07p16_comb_arith_2x8b_minmax_prompt.txt
├── Prob07p16_comb_arith_2x8b_minmax_test.py
├── Prob07p16_comb_arith_2x8b_minmax_test.v
├── Prob07p17_comb_arith_4x8b_sorter_prompt.txt
├── Prob07p17_comb_arith_4x8b_sorter_test.py
├── Prob07p17_comb_arith_4x8b_sorter_test.v
├── Prob08p01_comb_fsm_4s1i1o_mo_tbl0_prompt.txt
├── Prob08p01_comb_fsm_4s1i1o_mo_tbl0_test.py
├── Prob08p01_comb_fsm_4s1i1o_mo_tbl0_test.v
├── Prob08p02_comb_fsm_4s1i1o_mo_tbl1_prompt.txt
├── Prob08p02_comb_fsm_4s1i1o_mo_tbl1_test.py
├── Prob08p02_comb_fsm_4s1i1o_mo_tbl1_test.v
├── Prob08p03_comb_fsm_4s1i1o_me_tbl_prompt.txt
├── Prob08p03_comb_fsm_4s1i1o_me_tbl_test.py
├── Prob08p03_comb_fsm_4s1i1o_me_tbl_test.v
├── Prob08p04_comb_fsm_4s1i2o_mo_tbl_prompt.txt
├── Prob08p04_comb_fsm_4s1i2o_mo_tbl_test.py
├── Prob08p04_comb_fsm_4s1i2o_mo_tbl_test.v
├── Prob08p05_comb_fsm_4s2i1o_mo_tbl_prompt.txt
├── Prob08p05_comb_fsm_4s2i1o_mo_tbl_test.py
├── Prob08p05_comb_fsm_4s2i1o_mo_tbl_test.v
├── Prob08p06_comb_fsm_6s2i2o_mo_tbl_prompt.txt
├── Prob08p06_comb_fsm_6s2i2o_mo_tbl_test.py
├── Prob08p06_comb_fsm_6s2i2o_mo_tbl_test.v
├── Prob08p07_comb_fsm_4s1i1o_mo_dia_prompt.txt
├── Prob08p07_comb_fsm_4s1i1o_mo_dia_test.py
├── Prob08p07_comb_fsm_4s1i1o_mo_dia_test.v
├── Prob08p08_comb_fsm_4s1i1o_me_dia_prompt.txt
├── Prob08p08_comb_fsm_4s1i1o_me_dia_test.py
├── Prob08p08_comb_fsm_4s1i1o_me_dia_test.v
├── Prob08p09_comb_fsm_6s2i2o_mo_dia_prompt.txt
├── Prob08p09_comb_fsm_6s2i2o_mo_dia_test.py
├── Prob08p09_comb_fsm_6s2i2o_mo_dia_test.v
├── Prob09p01_comb_param_const_prompt.txt
├── Prob09p01_comb_param_const_test.py
├── Prob09p01_comb_param_const_test.v
├── Prob09p02_comb_param_bit_rev_prompt.txt
├── Prob09p02_comb_param_bit_rev_test.py
├── Prob09p02_comb_param_bit_rev_test.v
├── Prob09p03_comb_param_nor_prompt.txt
├── Prob09p03_comb_param_nor_test.py
├── Prob09p03_comb_param_nor_test.v
├── Prob09p04_comb_param_2to1_mux_prompt.txt
├── Prob09p04_comb_param_2to1_mux_test.py
├── Prob09p04_comb_param_2to1_mux_test.v
├── Prob09p05_comb_param_enc_prompt.txt
├── Prob09p05_comb_param_enc_test.py
├── Prob09p05_comb_param_enc_test.v
├── Prob09p06_comb_param_dec_prompt.txt
├── Prob09p06_comb_param_dec_test.py
├── Prob09p06_comb_param_dec_test.v
├── Prob09p07_comb_param_penc_prompt.txt
├── Prob09p07_comb_param_penc_test.py
├── Prob09p07_comb_param_penc_test.v
├── Prob09p08_comb_param_rotator_prompt.txt
├── Prob09p08_comb_param_rotator_test.py
├── Prob09p08_comb_param_rotator_test.v
├── Prob10p01_seq_gates_1b_dff_prompt.txt
├── Prob10p01_seq_gates_1b_dff_test.py
├── Prob10p01_seq_gates_1b_dff_test.v
├── Prob10p02_seq_gates_1b_dffe_prompt.txt
├── Prob10p02_seq_gates_1b_dffe_test.py
├── Prob10p02_seq_gates_1b_dffe_test.v
├── Prob10p03_seq_gates_1b_dffr_prompt.txt
├── Prob10p03_seq_gates_1b_dffr_test.py
├── Prob10p03_seq_gates_1b_dffr_test.v
├── Prob10p04_seq_gates_8b_dff_prompt.txt
├── Prob10p04_seq_gates_8b_dff_test.py
├── Prob10p04_seq_gates_8b_dff_test.v
├── Prob10p05_seq_gates_8b_dffre_prompt.txt
├── Prob10p05_seq_gates_8b_dffre_test.py
├── Prob10p05_seq_gates_8b_dffre_test.v
├── Prob10p06_seq_gates_8b_dff_byte_prompt.txt
├── Prob10p06_seq_gates_8b_dff_byte_test.py
├── Prob10p06_seq_gates_8b_dff_byte_test.v
├── Prob10p07_seq_gates_nl0_prompt.txt
├── Prob10p07_seq_gates_nl0_test.py
├── Prob10p07_seq_gates_nl0_test.v
├── Prob10p08_seq_gates_nl1_prompt.txt
├── Prob10p08_seq_gates_nl1_test.py
├── Prob10p08_seq_gates_nl1_test.v
├── Prob10p09_seq_gates_nl2_prompt.txt
├── Prob10p09_seq_gates_nl2_test.py
├── Prob10p09_seq_gates_nl2_test.v
├── Prob11p01_seq_bool_truth_dff_prompt.txt
├── Prob11p01_seq_bool_truth_dff_test.py
├── Prob11p01_seq_bool_truth_dff_test.v
├── Prob11p02_seq_bool_truth_tff_prompt.txt
├── Prob11p02_seq_bool_truth_tff_test.py
├── Prob11p02_seq_bool_truth_tff_test.v
├── Prob11p03_seq_bool_truth_jkff_prompt.txt
├── Prob11p03_seq_bool_truth_jkff_test.py
├── Prob11p03_seq_bool_truth_jkff_test.v
├── Prob11p04_seq_bool_waveform0_prompt.txt
├── Prob11p04_seq_bool_waveform0_test.py
├── Prob11p04_seq_bool_waveform0_test.v
├── Prob11p05_seq_bool_waveform1_prompt.txt
├── Prob11p05_seq_bool_waveform1_test.py
├── Prob11p05_seq_bool_waveform1_test.v
├── Prob12p01_seq_sreg_8b_siso_prompt.txt
├── Prob12p01_seq_sreg_8b_siso_test.py
├── Prob12p01_seq_sreg_8b_siso_test.v
├── Prob12p02_seq_sreg_8b_piso_prompt.txt
├── Prob12p02_seq_sreg_8b_piso_test.py
├── Prob12p02_seq_sreg_8b_piso_test.v
├── Prob12p03_seq_sreg_8b_sipo_prompt.txt
├── Prob12p03_seq_sreg_8b_sipo_test.py
├── Prob12p03_seq_sreg_8b_sipo_test.v
├── Prob12p04_seq_sreg_8b_universal_prompt.txt
├── Prob12p04_seq_sreg_8b_universal_test.py
├── Prob12p04_seq_sreg_8b_universal_test.v
├── Prob12p05_seq_sreg_8b_bidir_prompt.txt
├── Prob12p05_seq_sreg_8b_bidir_test.py
├── Prob12p05_seq_sreg_8b_bidir_test.v
├── Prob12p06_seq_sreg_5b_lfsr_prompt.txt
├── Prob12p06_seq_sreg_5b_lfsr_test.py
├── Prob12p06_seq_sreg_5b_lfsr_test.v
├── Prob12p07_seq_sreg_7b_lfsr_prompt.txt
├── Prob12p07_seq_sreg_7b_lfsr_test.py
├── Prob12p07_seq_sreg_7b_lfsr_test.v
├── Prob13p01_seq_count_3b_bin_up_prompt.txt
├── Prob13p01_seq_count_3b_bin_up_test.py
├── Prob13p01_seq_count_3b_bin_up_test.v
├── Prob13p02_seq_count_3b_bin_up_en_prompt.txt
├── Prob13p02_seq_count_3b_bin_up_en_test.py
├── Prob13p02_seq_count_3b_bin_up_en_test.v
├── Prob13p03_seq_count_3b_bin_dn_prompt.txt
├── Prob13p03_seq_count_3b_bin_dn_test.py
├── Prob13p03_seq_count_3b_bin_dn_test.v
├── Prob13p04_seq_count_3b_bin_up_dn_prompt.txt
├── Prob13p04_seq_count_3b_bin_up_dn_test.py
├── Prob13p04_seq_count_3b_bin_up_dn_test.v
├── Prob13p05_seq_count_2b_bin_sat_prompt.txt
├── Prob13p05_seq_count_2b_bin_sat_test.py
├── Prob13p05_seq_count_2b_bin_sat_test.v
├── Prob13p06_seq_count_3b_bin_var_dn_prompt.txt
├── Prob13p06_seq_count_3b_bin_var_dn_test.py
├── Prob13p06_seq_count_3b_bin_var_dn_test.v
├── Prob13p07_seq_count_4b_dec_up_prompt.txt
├── Prob13p07_seq_count_4b_dec_up_test.py
├── Prob13p07_seq_count_4b_dec_up_test.v
├── Prob13p08_seq_count_timer_prompt.txt
├── Prob13p08_seq_count_timer_test.py
├── Prob13p08_seq_count_timer_test.v
├── Prob13p09_seq_count_clock_prompt.txt
├── Prob13p09_seq_count_clock_test.py
├── Prob13p09_seq_count_clock_test.v
├── Prob14p01_seq_edge_8b_any_detect_prompt.txt
├── Prob14p01_seq_edge_8b_any_detect_test.py
├── Prob14p01_seq_edge_8b_any_detect_test.v
├── Prob14p02_seq_edge_8b_pos_detect_prompt.txt
├── Prob14p02_seq_edge_8b_pos_detect_test.py
├── Prob14p02_seq_edge_8b_pos_detect_test.v
├── Prob14p03_seq_edge_8b_capture_prompt.txt
├── Prob14p03_seq_edge_8b_capture_test.py
├── Prob14p03_seq_edge_8b_capture_test.v
├── Prob14p04_seq_edge_8b_any_count_prompt.txt
├── Prob14p04_seq_edge_8b_any_count_test.py
├── Prob14p04_seq_edge_8b_any_count_test.v
├── Prob14p05_seq_edge_8b_max_switch_prompt.txt
├── Prob14p05_seq_edge_8b_max_switch_test.py
├── Prob14p05_seq_edge_8b_max_switch_test.v
├── Prob15p01_seq_arb_4in_variable_prompt.txt
├── Prob15p01_seq_arb_4in_variable_test.py
├── Prob15p01_seq_arb_4in_variable_test.v
├── Prob15p02_seq_arb_4in_rotating_prompt.txt
├── Prob15p02_seq_arb_4in_rotating_test.py
├── Prob15p02_seq_arb_4in_rotating_test.v
├── Prob15p03_seq_arb_4in_roundrobin_prompt.txt
├── Prob15p03_seq_arb_4in_roundrobin_test.py
├── Prob15p03_seq_arb_4in_roundrobin_test.v
├── Prob15p04_seq_arb_4in_granthold_prompt.txt
├── Prob15p04_seq_arb_4in_granthold_test.py
├── Prob15p04_seq_arb_4in_granthold_test.v
├── Prob15p05_seq_arb_4in_weighted_prompt.txt
├── Prob15p05_seq_arb_4in_weighted_test.py
├── Prob15p05_seq_arb_4in_weighted_test.v
├── Prob16p01_seq_fsm_4s1i1o_mo_tbl0_prompt.txt
├── Prob16p01_seq_fsm_4s1i1o_mo_tbl0_test.py
├── Prob16p01_seq_fsm_4s1i1o_mo_tbl0_test.v
├── Prob16p02_seq_fsm_4s1i1o_mo_tbl1_prompt.txt
├── Prob16p02_seq_fsm_4s1i1o_mo_tbl1_test.py
├── Prob16p02_seq_fsm_4s1i1o_mo_tbl1_test.v
├── Prob16p03_seq_fsm_4s1i1o_me_tbl_prompt.txt
├── Prob16p03_seq_fsm_4s1i1o_me_tbl_test.py
├── Prob16p03_seq_fsm_4s1i1o_me_tbl_test.v
├── Prob16p04_seq_fsm_4s1i2o_mo_tbl_prompt.txt
├── Prob16p04_seq_fsm_4s1i2o_mo_tbl_test.py
├── Prob16p04_seq_fsm_4s1i2o_mo_tbl_test.v
├── Prob16p05_seq_fsm_4s2i1o_mo_tbl_prompt.txt
├── Prob16p05_seq_fsm_4s2i1o_mo_tbl_test.py
├── Prob16p05_seq_fsm_4s2i1o_mo_tbl_test.v
├── Prob16p06_seq_fsm_6s2i2o_mo_tbl_prompt.txt
├── Prob16p06_seq_fsm_6s2i2o_mo_tbl_test.py
├── Prob16p06_seq_fsm_6s2i2o_mo_tbl_test.v
├── Prob16p07_seq_fsm_4s1i1o_mo_dia_prompt.txt
├── Prob16p07_seq_fsm_4s1i1o_mo_dia_test.py
├── Prob16p07_seq_fsm_4s1i1o_mo_dia_test.v
├── Prob16p08_seq_fsm_4s1i1o_me_dia_prompt.txt
├── Prob16p08_seq_fsm_4s1i1o_me_dia_test.py
├── Prob16p08_seq_fsm_4s1i1o_me_dia_test.v
├── Prob16p09_seq_fsm_6s2i2o_mo_dia_prompt.txt
├── Prob16p09_seq_fsm_6s2i2o_mo_dia_test.py
├── Prob16p09_seq_fsm_6s2i2o_mo_dia_test.v
├── Prob16p10_seq_fsm_pattern1_prompt.txt
├── Prob16p10_seq_fsm_pattern1_test.py
├── Prob16p10_seq_fsm_pattern1_test.v
├── Prob16p11_seq_fsm_pattern2_prompt.txt
├── Prob16p11_seq_fsm_pattern2_test.py
├── Prob16p11_seq_fsm_pattern2_test.v
├── Prob16p12_seq_fsm_stop_light_prompt.txt
├── Prob16p12_seq_fsm_stop_light_test.py
├── Prob16p12_seq_fsm_stop_light_test.v
├── Prob16p13_seq_fsm_ps2_prompt.txt
├── Prob16p13_seq_fsm_ps2_test.py
├── Prob16p13_seq_fsm_ps2_test.v
├── Prob17p01_seq_mem_8x8b_1r1w_rf_prompt.txt
├── Prob17p01_seq_mem_8x8b_1r1w_rf_test.py
├── Prob17p01_seq_mem_8x8b_1r1w_rf_test.v
├── Prob17p02_seq_mem_8x8b_1r1w_rf_fw_prompt.txt
├── Prob17p02_seq_mem_8x8b_1r1w_rf_fw_test.py
├── Prob17p02_seq_mem_8x8b_1r1w_rf_fw_test.v
├── Prob17p03_seq_mem_8x8b_1r1w_rf_z_prompt.txt
├── Prob17p03_seq_mem_8x8b_1r1w_rf_z_test.py
├── Prob17p03_seq_mem_8x8b_1r1w_rf_z_test.v
├── Prob17p04_seq_mem_8x8b_1r1w_rf_pw_prompt.txt
├── Prob17p04_seq_mem_8x8b_1r1w_rf_pw_test.py
├── Prob17p04_seq_mem_8x8b_1r1w_rf_pw_test.v
├── Prob17p05_seq_mem_8x8b_2r1w_rf_fwz_prompt.txt
├── Prob17p05_seq_mem_8x8b_2r1w_rf_fwz_test.py
├── Prob17p05_seq_mem_8x8b_2r1w_rf_fwz_test.v
├── Prob17p06_seq_mem_8x8b_1s1w_cam_prompt.txt
├── Prob17p06_seq_mem_8x8b_1s1w_cam_test.py
├── Prob17p06_seq_mem_8x8b_1s1w_cam_test.v
├── Prob18p01_seq_arith_4x1b_incr_prompt.txt
├── Prob18p01_seq_arith_4x1b_incr_test.py
├── Prob18p01_seq_arith_4x1b_incr_test.v
├── Prob18p02_seq_arith_4x1b_add_prompt.txt
├── Prob18p02_seq_arith_4x1b_add_test.py
├── Prob18p02_seq_arith_4x1b_add_test.v
├── Prob18p03_seq_arith_2x4b_add_prompt.txt
├── Prob18p03_seq_arith_2x4b_add_test.py
├── Prob18p03_seq_arith_2x4b_add_test.v
├── Prob18p04_seq_arith_8b_accum_prompt.txt
├── Prob18p04_seq_arith_8b_accum_test.py
├── Prob18p04_seq_arith_8b_accum_test.v
├── Prob19p01_seq_pipe_delay_1stage_prompt.txt
├── Prob19p01_seq_pipe_delay_1stage_test.py
├── Prob19p01_seq_pipe_delay_1stage_test.v
├── Prob19p02_seq_pipe_delay_2stage_prompt.txt
├── Prob19p02_seq_pipe_delay_2stage_test.py
├── Prob19p02_seq_pipe_delay_2stage_test.v
├── Prob19p03_seq_pipe_delay_3stage_prompt.txt
├── Prob19p03_seq_pipe_delay_3stage_test.py
├── Prob19p03_seq_pipe_delay_3stage_test.v
├── Prob19p04_seq_pipe_add2_1stage_prompt.txt
├── Prob19p04_seq_pipe_add2_1stage_test.py
├── Prob19p04_seq_pipe_add2_1stage_test.v
├── Prob19p05_seq_pipe_add2_2stage_prompt.txt
├── Prob19p05_seq_pipe_add2_2stage_test.py
├── Prob19p05_seq_pipe_add2_2stage_test.v
├── Prob19p06_seq_pipe_add3_2stage_prompt.txt
├── Prob19p06_seq_pipe_add3_2stage_test.py
├── Prob19p06_seq_pipe_add3_2stage_test.v
├── Prob19p07_seq_pipe_add4_2stage_prompt.txt
├── Prob19p07_seq_pipe_add4_2stage_test.py
├── Prob19p07_seq_pipe_add4_2stage_test.v
├── Prob19p08_seq_pipe_minmax4_2stage_prompt.txt
├── Prob19p08_seq_pipe_minmax4_2stage_test.py
├── Prob19p08_seq_pipe_minmax4_2stage_test.v
├── problems.txt
└── test_utils.v
├── examples
├── amaranth-ex1.txt
├── amaranth-ex2.txt
├── amaranth-ex3.txt
├── amaranth-ex4.txt
├── migen-ex1.txt
├── migen-ex2.txt
├── migen-ex3.txt
├── migen-ex4.txt
├── myhdl-ex1.txt
├── myhdl-ex2.txt
├── myhdl-ex3.txt
├── myhdl-ex4.txt
├── pymtl-ex1.txt
├── pymtl-ex2.txt
├── pymtl-ex3.txt
├── pymtl-ex4.txt
├── pyrtl-ex1.txt
├── pyrtl-ex2.txt
├── pyrtl-ex3.txt
├── pyrtl-ex4.txt
├── verilog-ex1.txt
├── verilog-ex2.txt
├── verilog-ex3.txt
└── verilog-ex4.txt
├── pyhdl_eval
├── __init__.py
├── amaranth.py
├── bits.py
├── cfg.py
├── core.py
├── migen.py
├── myhdl.py
├── pymtl.py
├── pyrtl.py
├── strategies.py
├── test
│ ├── bits_test.py
│ ├── comb_incr_amaranth.py
│ ├── comb_incr_migen.py
│ ├── comb_incr_myhdl.py
│ ├── comb_incr_pymtl.py
│ ├── comb_incr_pyrtl.py
│ ├── comb_incr_ref.v
│ ├── comb_incr_test.py
│ ├── comb_incr_verilog.v
│ ├── const_amaranth.py
│ ├── const_migen.py
│ ├── const_myhdl.py
│ ├── const_pymtl.py
│ ├── const_pyrtl.py
│ ├── const_ref.v
│ ├── const_test.py
│ ├── const_verilog.v
│ ├── count_incr_amaranth.py
│ ├── count_incr_migen.py
│ ├── count_incr_myhdl.py
│ ├── count_incr_pymtl.py
│ ├── count_incr_pyrtl.py
│ ├── count_incr_ref.v
│ ├── count_incr_test.py
│ ├── count_incr_verilog.v
│ ├── param_incr_amaranth.py
│ ├── param_incr_migen.py
│ ├── param_incr_myhdl.py
│ ├── param_incr_pymtl.py
│ ├── param_incr_pyrtl.py
│ ├── param_incr_ref.v
│ ├── param_incr_test.py
│ ├── param_incr_verilog.v
│ ├── pipe_incr_amaranth.py
│ ├── pipe_incr_migen.py
│ ├── pipe_incr_myhdl.py
│ ├── pipe_incr_pymtl.py
│ ├── pipe_incr_pyrtl.py
│ ├── pipe_incr_ref.v
│ ├── pipe_incr_test.py
│ ├── pipe_incr_verilog.v
│ ├── reg_incr_amaranth.py
│ ├── reg_incr_migen.py
│ ├── reg_incr_myhdl.py
│ ├── reg_incr_pymtl.py
│ ├── reg_incr_pyrtl.py
│ ├── reg_incr_ref.v
│ ├── reg_incr_test.py
│ └── reg_incr_verilog.v
└── verilog.py
├── pytest.ini
└── scripts
├── analyze-amaranth
├── analyze-migen
├── analyze-myhdl
├── analyze-pymtl
├── analyze-pyrtl
├── analyze-verilog
├── collect-summaries
├── echo-progress
└── generate
/.gitignore:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Git Ignore Files
3 | #=========================================================================
4 | # We explicitly ignore a default build directory and the autoconf
5 | # generated autom4te.cache directory. This makes it easy to do a clean
6 | # build under the source directory and still have it appear clean to git.
7 |
8 | build*/
9 | autom4te.cache/
10 |
11 | .pytest_cache/
12 | __pycache__/
13 |
14 | run.sh
15 | dataset/copy.sh
16 |
--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
1 |
2 | MIT License
3 |
4 | Copyright (c) 2024 NVIDIA Research Projects
5 |
6 | Permission is hereby granted, free of charge, to any person obtaining
7 | a copy of this software and associated documentation files (the
8 | "Software"), to deal in the Software without restriction, including
9 | without limitation the rights to use, copy, modify, merge, publish,
10 | distribute, sublicense, and/or sell copies of the Software, and to
11 | permit persons to whom the Software is furnished to do so, subject to
12 | the following conditions:
13 |
14 | The above copyright notice and this permission notice shall be
15 | included in all copies or substantial portions of the Software.
16 |
17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 | IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
21 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 |
25 |
--------------------------------------------------------------------------------
/dataset/Prob01p01_comb_const_zero_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - output zero
6 |
7 | The module implementation should always output a logic zero.
8 |
9 |
--------------------------------------------------------------------------------
/dataset/Prob01p01_comb_const_zero_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob01p01_comb_const_zero_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "zero", OutputPort(1) ),
18 | ],
19 | )
20 |
21 | #-------------------------------------------------------------------------
22 | # test_case_directed
23 | #-------------------------------------------------------------------------
24 |
25 | def test_case_directed( pytestconfig ):
26 | run_sim( pytestconfig, __file__, config )
27 |
28 |
--------------------------------------------------------------------------------
/dataset/Prob01p02_comb_const_one_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - output out
6 |
7 | The module implementation should always output a logic one.
8 |
9 |
--------------------------------------------------------------------------------
/dataset/Prob01p02_comb_const_one_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob01p02_comb_const_one_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "out", OutputPort(1) ),
18 | ],
19 | )
20 |
21 | #-------------------------------------------------------------------------
22 | # test_case_directed
23 | #-------------------------------------------------------------------------
24 |
25 | def test_case_directed( pytestconfig ):
26 | run_sim( pytestconfig, __file__, config )
27 |
28 |
--------------------------------------------------------------------------------
/dataset/Prob01p03_comb_const_lohi_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - output lo
6 | - output hi
7 |
8 | The module implementation should always output a logic LOW and a logic
9 | HIGH on the appropriate output ports. A logic LOW should always be output
10 | on output port lo and a logic HIGH should always be output on output port
11 | hi.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob01p03_comb_const_lohi_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob01p03_comb_const_lohi_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "lo", OutputPort(1) ),
18 | ( "hi", OutputPort(1) ),
19 | ],
20 | )
21 |
22 | #-------------------------------------------------------------------------
23 | # test_case_directed
24 | #-------------------------------------------------------------------------
25 |
26 | def test_case_directed( pytestconfig ):
27 | run_sim( pytestconfig, __file__, config )
28 |
29 |
--------------------------------------------------------------------------------
/dataset/Prob01p04_comb_const_32b_value_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - output out (32 bits)
6 |
7 | The module implementation should always output the constant 0xdeadbeef.
8 |
9 |
--------------------------------------------------------------------------------
/dataset/Prob01p04_comb_const_32b_value_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob01p04_comb_const_32b_value_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "out", OutputPort(32) ),
18 | ],
19 | )
20 |
21 | #-------------------------------------------------------------------------
22 | # test_case_directed
23 | #-------------------------------------------------------------------------
24 |
25 | def test_case_directed( pytestconfig ):
26 | run_sim( pytestconfig, __file__, config )
27 |
28 |
--------------------------------------------------------------------------------
/dataset/Prob02p01_comb_wires_8b_passthru_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output out (8 bits)
7 |
8 | The module implementation should directly connect the input port to the
9 | output port.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob02p02_comb_wires_16b_split_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output lo (4 bits)
7 | - output hi (4 bits)
8 |
9 | The module implementation should split the input into two four-bit
10 | fields. The least-significant four bits (i.e., in_[3:0]) should be
11 | connected to the output lo port, while the most-significant four bits
12 | (i.e., in_[7:4]) should be connected to the output hi port.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob02p03_comb_wires_8b_bit_rev_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output out (8 bits)
7 |
8 | The module implementation should connect the input port to the output
9 | port but with the bits in reversed order. In other words, in_[0] should
10 | be connected to out[7], in_[1] should be connected to out[6], and so on.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob02p04_comb_wires_100b_bit_rev_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (100 bits)
6 | - output out (100 bits)
7 |
8 | The module implementation should connect the input port to the output
9 | port but with the bits in reversed order. In other words, in_[0] should
10 | be connected to out[99], in_[1] should be connected to out[98], and so on.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob02p05_comb_wires_64b_byte_rev_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (64 bits)
6 | - output out (64 bits)
7 |
8 | The module implementation should connect the input port to the output
9 | port but with the bytes in reversed order. In other words, the least
10 | significant byte of the input should be written to the most significant
11 | byte of the output, the most significant byte of the input should be
12 | written to the least significant byte of the output, and so on.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob02p06_comb_wires_4x2b_passthru_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (2 bits)
6 | - input in1 (2 bits)
7 | - input in2 (2 bits)
8 | - input in3 (2 bits)
9 | - output out0 (2 bits)
10 | - output out1 (2 bits)
11 | - output out2 (2 bits)
12 | - output out3 (2 bits)
13 |
14 | The module implementation should directly connect each the input port to
15 | the corresponding output port. So input port in0 should be connected to
16 | output port out0, input port in1 should be connected to output port out1,
17 | and so on.
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob02p07_comb_wires_5x3b_to_4x4b_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (3 bits)
6 | - input in1 (3 bits)
7 | - input in2 (3 bits)
8 | - input in3 (3 bits)
9 | - input in4 (3 bits)
10 | - output out0 (4 bits)
11 | - output out1 (4 bits)
12 | - output out2 (4 bits)
13 | - output out3 (4 bits)
14 |
15 | The module implementation should concatenate the input ports together
16 | into a single wide signal, and then split this wide signal across the
17 | output ports. The input port in0 should be connected to the
18 | least-significant three bits of output port out0, the input port in1
19 | should be split across output ports out0 and out1, the input port in2
20 | should be split across output ports out1 and out2, and so on. There are
21 | five 3-bit input ports for a total of 15 bits, and there are four 4-bit
22 | output ports for a total of 16 bits. So there is one more bit in the
23 | output compared to the input. Wire the most significant bit of output
24 | port out3 to be a constant logic one.
25 |
26 |
--------------------------------------------------------------------------------
/dataset/Prob02p08_comb_wires_sext_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output out (32 bits)
7 |
8 | The module implementation should connect the input port to the output
9 | port using sign extension. Sign extension involves taking the
10 | most-significant bit of the input and replicating it to fill the
11 | most-significant bits of the output.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob03p01_comb_gates_and_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - output out
8 |
9 | The module should implement an AND gate.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob03p01_comb_gates_and_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob03p01_comb_gates_and_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in0", InputPort (1) ),
18 | ( "in1", InputPort (1) ),
19 | ( "out", OutputPort(1) ),
20 | ],
21 | )
22 |
23 | #-------------------------------------------------------------------------
24 | # test_case_directed
25 | #-------------------------------------------------------------------------
26 |
27 | def test_case_directed( pytestconfig ):
28 | run_sim( pytestconfig, __file__, config,
29 | [
30 | (0,0),
31 | (0,1),
32 | (1,0),
33 | (1,1)
34 | ])
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob03p02_comb_gates_nor_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - output out
8 |
9 | The module should implement a NOR gate.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob03p02_comb_gates_nor_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob03p02_comb_gates_nor_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in0", InputPort (1) ),
18 | ( "in1", InputPort (1) ),
19 | ( "out", OutputPort(1) ),
20 | ],
21 | )
22 |
23 | #-------------------------------------------------------------------------
24 | # test_case_directed
25 | #-------------------------------------------------------------------------
26 |
27 | def test_case_directed( pytestconfig ):
28 | run_sim( pytestconfig, __file__, config,
29 | [
30 | (0,0),
31 | (0,1),
32 | (1,0),
33 | (1,1)
34 | ])
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob03p03_comb_gates_aoi21_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input in2
8 | - output out
9 |
10 | The module should implement a 2-1 AND-OR-inverting (AOI) compound gate.
11 | Inputs in0 and in1 should connect to the AND gate and input in2 should
12 | connect to the remaining input of the OR gate.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob03p03_comb_gates_aoi21_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob03p03_comb_gates_aoi21_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in0", InputPort (1) ),
18 | ( "in1", InputPort (1) ),
19 | ( "in2", InputPort (1) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob03p04_comb_gates_oai22_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input in2
8 | - input in3
9 | - output out
10 |
11 | The module should implement a 2-2 OR-AND-inverting (OAI) compound gate.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob03p05_comb_gates_hadd_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - output sum
8 | - output cout
9 |
10 | The module should implement a one-bit half adder.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob03p05_comb_gates_hadd_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob03p05_comb_gates_hadd_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "sum", OutputPort(1) ),
20 | ( "cout", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0),
32 | (0,1),
33 | (1,0),
34 | (1,1)
35 | ])
36 |
37 |
--------------------------------------------------------------------------------
/dataset/Prob03p06_comb_gates_fadd_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input cin
8 | - output sum
9 | - output cout
10 |
11 | The module should implement a one-bit full adder.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob03p06_comb_gates_fadd_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob03p06_comb_gates_fadd_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "cin", InputPort (1) ),
20 | ( "sum", OutputPort(1) ),
21 | ( "cout", OutputPort(1) ),
22 | ],
23 | )
24 |
25 | #-------------------------------------------------------------------------
26 | # test_case_directed
27 | #-------------------------------------------------------------------------
28 |
29 | def test_case_directed( pytestconfig ):
30 | run_sim( pytestconfig, __file__, config,
31 | [
32 | (0,0,0),
33 | (0,0,1),
34 | (0,1,0),
35 | (0,1,1),
36 | (1,0,0),
37 | (1,0,1),
38 | (1,1,0),
39 | (1,1,1),
40 | ])
41 |
42 |
--------------------------------------------------------------------------------
/dataset/Prob03p07_comb_gates_4_input_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input in2
8 | - input in3
9 | - output out_and
10 | - output out_nand
11 | - output out_or
12 | - output out_nor
13 |
14 | The module should implement four logic gates: a four-input AND gate, a
15 | four-input NAND gate, a four-input OR gate, and a four-input NOR gate.
16 | The output of each gate should be connected to the appropriate output
17 | port.
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob03p08_comb_gates_100_input_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (100 bits)
6 | - output out_and
7 | - output out_nand
8 | - output out_or
9 | - output out_nor
10 |
11 | The module should implement four logic gates: a 100-input AND gate, a
12 | 100-input NAND gate, a 100-input OR gate, and a 100-input NOR gate.
13 | The output of each gate should be connected to the appropriate output
14 | port.
15 |
16 |
--------------------------------------------------------------------------------
/dataset/Prob03p09_comb_gates_bitwise_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (4 bits)
6 | - input in1 (4 bits)
7 | - output out_and (4 bits)
8 | - output out_nand (4 bits)
9 | - output out_or (4 bits)
10 | - output out_nor (4 bits)
11 |
12 | The module should implement a total of 16 logic gates. It should
13 | implement four two-input AND gates that calculate the bitwise AND of the
14 | two inputs and connect the output of these four AND gates to the four
15 | bits of the out_and output port. It should similarly calculate the
16 | bitwise NAND, OR, and NOR and connect the outputs to the appropriate
17 | output port.
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob03p10_comb_gates_4b_pairwise_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out_and (3 bits)
7 | - output out_or (3 bits)
8 | - output out_xnor (3 bits)
9 |
10 | The module should use a variety of logic gates to analyze consecutive
11 | pairs of bits of the four-bit input: use three AND gates to determine if
12 | a given input bit and its neighbor are both one; use three OR gates to
13 | determine if either the given input bit or its neighbor are one; and use
14 | three XNOR gates to determine if a given input bit and its neighbor are
15 | the same. The outputs of these gates should be connected to the
16 | appropriate output port. Logic gates analyzing bits 0 and 1 of the input
17 | should be connected to bit 0 of the output port, logic gates analyzing
18 | bits 1 and 2 of the input should be connected to bit 1 of the output
19 | port, and so on.
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob03p11_comb_gates_100b_pairwise_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (100 bits)
6 | - output out_and ( 99 bits)
7 | - output out_or ( 99 bits)
8 | - output out_xnor ( 99 bits)
9 |
10 | The module should use a variety of logic gates to analyze consecutive
11 | pairs of bits of the 100-bit input: use 99 AND gates to determine if a
12 | given input bit and its neighbor are both one; use 99 OR gates to
13 | determine if either the given input bit or its neighbor are one; and use
14 | 99 XNOR gates to determine if a given input bit and its neighbor are
15 | the same. The outputs of these gates should be connected to the
16 | appropriate output port. Logic gates analyzing bits 0 and 1 of the input
17 | should be connected to bit 0 of the output port, logic gates analyzing
18 | bits 1 and 2 of the input should be connected to bit 1 of the output
19 | port, and so on.
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob03p12_comb_gates_nl0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input in2
8 | - output out
9 |
10 | The module should implement the following circuit: inputs in0 and in1
11 | should be connected to a two-input XOR gate; the output of the XOR gate
12 | should be conneectd to a NOT gate; the output of the NOT gate should be
13 | connected to the first input of a two-input AND gate; input in2 should be
14 | connected to the second input of the two-input AND gate; the output of
15 | the AND gate should be connected to the output port.
16 |
17 |
--------------------------------------------------------------------------------
/dataset/Prob03p12_comb_gates_nl0_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob03p12_comb_gates_nl0_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in0", InputPort (1) ),
18 | ( "in1", InputPort (1) ),
19 | ( "in2", InputPort (1) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob03p13_comb_gates_nl1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input in2
8 | - input in3
9 | - output out
10 |
11 | The module should implement the following circuit: input in0 should be
12 | connected to a NOT gate and the output of this NOT gate should be
13 | connected to the first input of a two-input OR gate; input in1 should be
14 | connected to the second input of this two-input OR gate; input in2 should
15 | be connected to the first input of another two-input OR gate; input in3
16 | should be connected to a NOT gate and the output of this NOT gate should
17 | be connected to the second input of the two-input OR gate; the output of
18 | both two-input OR gates should be connected to a two-input AND gate; the
19 | output of the AND gate should be connected to the output port.
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob04p01_comb_bool_logic_eq0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - output f
9 |
10 | The module should implement the following boolean logic equation.
11 |
12 | f = (~a & b & ~c) | (a & b & c)
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob04p01_comb_bool_logic_eq0_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p01_comb_bool_logic_eq0_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "c", InputPort (1) ),
20 | ( "f", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p02_comb_bool_logic_eq1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - output f
9 |
10 | The module should implement the following boolean logic equation.
11 |
12 | f = ((NOT a) AND b AND (NOT c)) OR (a AND b AND c)
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob04p02_comb_bool_logic_eq1_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p02_comb_bool_logic_eq1_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "c", InputPort (1) ),
20 | ( "f", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p03_comb_bool_logic_eq2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - output f
9 |
10 | The module should implement the following boolean logic equation.
11 |
12 | f = a'bc' + abc
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob04p03_comb_bool_logic_eq2_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p03_comb_bool_logic_eq2_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "c", InputPort (1) ),
20 | ( "f", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p04_comb_bool_truth_tbl0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - output f
8 |
9 | The module should implement a combinational circuit described by the
10 | following truth table.
11 |
12 | a b | f
13 | -----+---
14 | 0 0 | 1
15 | 0 1 | 1
16 | 1 0 | 1
17 | 1 1 | 0
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob04p04_comb_bool_truth_tbl0_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p04_comb_bool_truth_tbl0_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "f", OutputPort(1) ),
20 | ],
21 | )
22 |
23 | #-------------------------------------------------------------------------
24 | # test_case_directed
25 | #-------------------------------------------------------------------------
26 |
27 | def test_case_directed( pytestconfig ):
28 | run_sim( pytestconfig, __file__, config,
29 | [
30 | (0,0),
31 | (0,1),
32 | (1,0),
33 | (1,1),
34 | ])
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob04p05_comb_bool_truth_tbl1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - output f
9 |
10 | The module should implement a combinational circuit described by the
11 | following truth table:
12 |
13 | a b c | f
14 | -------+---
15 | 0 0 0 | 1
16 | 0 0 1 | 1
17 | 0 1 0 | 1
18 | 0 1 1 | 0
19 | 1 0 0 | 1
20 | 1 0 1 | 0
21 | 1 1 0 | 0
22 | 1 1 1 | 1
23 |
24 |
--------------------------------------------------------------------------------
/dataset/Prob04p05_comb_bool_truth_tbl1_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p05_comb_bool_truth_tbl1_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "c", InputPort (1) ),
20 | ( "f", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p06_comb_bool_truth_tbl2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - input d
9 | - output f
10 |
11 | The module should implement a combinational circuit described by the
12 | following truth table:
13 |
14 | a b c d | f
15 | ---------+---
16 | 0 0 0 0 | 1
17 | 0 0 0 1 | 1
18 | 0 0 1 0 | 0
19 | 0 0 1 1 | 0
20 | 0 1 0 0 | 1
21 | 0 1 0 1 | 1
22 | 0 1 1 0 | 0
23 | 0 1 1 1 | 0
24 | 1 0 0 0 | 1
25 | 1 0 0 1 | 0
26 | 1 0 1 0 | 1
27 | 1 0 1 1 | 0
28 | 1 1 0 0 | 0
29 | 1 1 0 1 | 1
30 | 1 1 1 0 | 0
31 | 1 1 1 1 | 1
32 |
33 |
--------------------------------------------------------------------------------
/dataset/Prob04p07_comb_bool_kmap0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - output f
8 |
9 | The module should implement a combinational circuit described by the
10 | following Karnaugh map. Note that a is the column variable and b is the
11 | row variable.
12 |
13 | b\a | 0 1
14 | -----+-----
15 | 0 | 1 1
16 | 1 | 1 0
17 |
18 |
--------------------------------------------------------------------------------
/dataset/Prob04p07_comb_bool_kmap0_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p07_comb_bool_kmap0_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "f", OutputPort(1) ),
20 | ],
21 | )
22 |
23 | #-------------------------------------------------------------------------
24 | # test_case_directed
25 | #-------------------------------------------------------------------------
26 |
27 | def test_case_directed( pytestconfig ):
28 | run_sim( pytestconfig, __file__, config,
29 | [
30 | (0,0),
31 | (0,1),
32 | (1,0),
33 | (1,1),
34 | ])
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob04p08_comb_bool_kmap1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - output f
9 |
10 | The module should implement a combinational circuit described by the
11 | following Karnaugh map. Note that a and b are column variables, and c is
12 | the row variable.
13 |
14 | c\ab | 00 01 11 10
15 | ------+-------------
16 | 0 | 1 1 0 1
17 | 1 | 1 0 1 0
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob04p08_comb_bool_kmap1_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p08_comb_bool_kmap1_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "c", InputPort (1) ),
20 | ( "f", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p09_comb_bool_kmap2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - input d
9 | - output f
10 |
11 | The module should implement a combinational circuit described by the
12 | following Karnaugh map. Note that a and b are column variables, and c and
13 | d are row variables.
14 |
15 | cd\ab | 00 01 11 10
16 | -------+-------------
17 | 00 | 1 1 0 1
18 | 01 | 1 1 1 0
19 | 10 | 0 0 0 1
20 | 11 | 0 0 1 0
21 |
22 |
--------------------------------------------------------------------------------
/dataset/Prob04p10_comb_bool_waveform0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - output f
8 |
9 | The module should implement a combinational circuit described by the
10 | following simulation waveform. The waveform shows the input values and
11 | the desired output values on every cycle of the simulation.
12 |
13 | cycle | a b f
14 | -------+-------
15 | 0 | 1 0 1
16 | 1 | 0 1 1
17 | 2 | 0 0 1
18 | 3 | 0 1 1
19 | 4 | 0 1 1
20 | 5 | 1 1 0
21 | 6 | 1 1 0
22 | 7 | 0 1 1
23 | 8 | 1 0 1
24 | 9 | 0 1 1
25 | 10 | 0 0 1
26 | 11 | 1 0 1
27 | 12 | 1 1 0
28 | 13 | 0 0 1
29 | 14 | 1 0 1
30 | 15 | 0 0 1
31 | 16 | 1 0 1
32 | 17 | 1 0 1
33 | 18 | 0 1 1
34 | 19 | 1 0 1
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob04p10_comb_bool_waveform0_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p10_comb_bool_waveform0_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "f", OutputPort(1) ),
20 | ],
21 | )
22 |
23 | #-------------------------------------------------------------------------
24 | # test_case_directed
25 | #-------------------------------------------------------------------------
26 |
27 | def test_case_directed( pytestconfig ):
28 | run_sim( pytestconfig, __file__, config,
29 | [
30 | (0,0),
31 | (0,1),
32 | (1,0),
33 | (1,1),
34 | ])
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob04p11_comb_bool_waveform1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input a
6 | - input b
7 | - input c
8 | - output f
9 |
10 | The module should implement a combinational circuit described by the
11 | following simulation waveform. The waveform shows the input values and
12 | the desired output values on every cycle of the simulation.
13 |
14 | cycle | a b c f
15 | -------+---------
16 | 0 | 1 0 0 1
17 | 1 | 0 0 1 1
18 | 2 | 1 0 1 0
19 | 3 | 1 1 1 1
20 | 4 | 0 1 1 0
21 | 5 | 0 0 0 1
22 | 6 | 0 1 1 0
23 | 7 | 0 0 1 1
24 | 8 | 0 0 1 1
25 | 9 | 0 1 0 1
26 | 10 | 1 1 0 0
27 | 11 | 0 0 1 1
28 | 12 | 0 1 0 1
29 | 13 | 1 1 0 0
30 | 14 | 0 1 1 0
31 | 15 | 1 0 1 0
32 | 16 | 1 1 0 0
33 | 17 | 0 0 0 1
34 | 18 | 0 1 0 1
35 | 19 | 1 1 1 1
36 | 20 | 0 1 1 0
37 | 21 | 1 1 1 1
38 | 22 | 1 0 1 0
39 | 23 | 1 1 0 0
40 | 24 | 0 0 1 1
41 | 25 | 0 1 1 0
42 | 26 | 0 1 0 1
43 | 27 | 1 0 0 1
44 | 28 | 1 0 0 1
45 | 29 | 1 0 0 1
46 |
47 |
--------------------------------------------------------------------------------
/dataset/Prob04p11_comb_bool_waveform1_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p11_comb_bool_waveform1_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "a", InputPort (1) ),
18 | ( "b", InputPort (1) ),
19 | ( "c", InputPort (1) ),
20 | ( "f", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p13_comb_bool_nl_lights_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input dark
6 | - input movement
7 | - input force_on
8 | - output turn_on_lights
9 |
10 | The module should implement a controller for a home lighting system.
11 | There are three inputs: input dark is one if it is dark outside and zero
12 | if it is light outside; input movement is one if the security system has
13 | detected movement and is otherwise zero; and input force_on is one if a
14 | manual override switch is activated. The lights should be turned on if it
15 | is dark outside and the security system has detected movement. The lights
16 | should always be turned off if it is light outside regardless of whether
17 | the security system has detected movement. The lights should always be
18 | turned on if the manual override switch is activated.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob04p13_comb_bool_nl_lights_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p13_comb_bool_nl_lights_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "dark", InputPort (1) ),
18 | ( "movement", InputPort (1) ),
19 | ( "force_on", InputPort (1) ),
20 | ( "turn_on_lights", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob04p14_comb_bool_nl_ringer_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input vibrate_mode
6 | - input ring
7 | - output turn_on_ringer
8 | - output turn_on_motor
9 |
10 | The module should implement a circuit to control a cellphone's ringer and
11 | vibration motor. Whenever the phone needs to ring from an incoming call
12 | (i.e., input ring is one), the circuit must either turn on the ringer
13 | (i.e., set the turn_on_ringer output to one) or the vibration motor
14 | (i.e., set the turn_on_motor output to one), but not both. If the phone
15 | is in vibrate mode (i.e., input vibrate_mode is one), turn on the motor.
16 | Otherwise, turn on the ringer.
17 |
18 |
--------------------------------------------------------------------------------
/dataset/Prob04p14_comb_bool_nl_ringer_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob04p14_comb_bool_nl_ringer_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "vibrate_mode", InputPort (1) ),
18 | ( "ring", InputPort (1) ),
19 | ( "turn_on_ringer", OutputPort(1) ),
20 | ( "turn_on_motor", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0),
32 | (0,1),
33 | (1,0),
34 | (1,1),
35 | ])
36 |
37 |
--------------------------------------------------------------------------------
/dataset/Prob04p15_comb_bool_nl_thermostat_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input mode
6 | - input too_cold
7 | - input too_hot
8 | - input fan_on
9 | - output heater
10 | - output aircon
11 | - output fan
12 |
13 | The module should implement a heating/cooling thermostat controller which
14 | controls a heater (during the winter), an air conditioner (during the
15 | summer), and a blower fan (during both the winter and summer). The
16 | thermostat can be in one of two modes: heating mode (mode = 1) or cooling
17 | model (mode = 0). In heating mode, turn the heater on when it is too cold
18 | (too_cold = 1) but do not use the air conditioner. In cooling mode, turn
19 | the air conditioner on when it is too hot (too_hot = 1), but do not turn
20 | on the heater. When the heater or air conditioner are on, also turn on
21 | the blower fan to circulate the air. In addition, the user can also
22 | request the fan to turn on (fan_on = 1), even if the heater and air
23 | conditioner are off.
24 |
25 |
--------------------------------------------------------------------------------
/dataset/Prob05p01_comb_mux_1b_2to1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input sel
8 | - output out
9 |
10 | The module should implement a 1-bit 2-to-1 multiplexer. The input sel
11 | should select which of the two inputs is used to write the output. If sel
12 | equals 0 then in0 should be selected and if sel equals 1 then then in1
13 | should be selected.
14 |
15 |
--------------------------------------------------------------------------------
/dataset/Prob05p01_comb_mux_1b_2to1_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob05p01_comb_mux_1b_2to1_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in0", InputPort (1) ),
18 | ( "in1", InputPort (1) ),
19 | ( "sel", InputPort (1) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | (0,0,0),
32 | (0,0,1),
33 | (0,1,0),
34 | (0,1,1),
35 | (1,0,0),
36 | (1,0,1),
37 | (1,1,0),
38 | (1,1,1),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob05p02_comb_mux_1b_8to1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0
6 | - input in1
7 | - input in2
8 | - input in3
9 | - input in4
10 | - input in5
11 | - input in6
12 | - input in7
13 | - input sel (3 bits)
14 | - output out
15 |
16 | The module should implement a 1-bit 8-to-1 multiplexer. The input sel
17 | should select which of the eight inputs is used to write the output. If
18 | sel equals 0 then in0 should be selected, if sel equals 1 then in1 should
19 | be selected, and so on.
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob05p03_comb_mux_1b_1to8_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_
6 | - input sel (3 bits)
7 | - output out0
8 | - output out1
9 | - output out2
10 | - output out3
11 | - output out4
12 | - output out5
13 | - output out6
14 | - output out7
15 |
16 | The module should implement a 1-bit 1-to-8 demultiplexer. The input sel
17 | should select which of the outputs is written with the value of the input
18 | port in_. Unselected output ports should be set to all zeros. If sel
19 | equals 0 then out0 should be selected, if sel equals 1 then then out1
20 | should be selected, and so on.
21 |
22 |
--------------------------------------------------------------------------------
/dataset/Prob05p04_comb_mux_4b_8to1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (4 bits)
6 | - input in1 (4 bits)
7 | - input in2 (4 bits)
8 | - input in3 (4 bits)
9 | - input in4 (4 bits)
10 | - input in5 (4 bits)
11 | - input in6 (4 bits)
12 | - input in7 (4 bits)
13 | - input sel (3 bits)
14 | - output out (4 bits)
15 |
16 | The module should implement a 4-bit 8-to-1 multiplexer. The input sel
17 | should select which of the inputs is used to write the output. If sel
18 | equals 0 then in0 should be selected, if sel equals 1 then in1 should be
19 | selected, and so on.
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob05p05_comb_mux_4b_1to8_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - input sel (3 bits)
7 | - output out0 (4 bits)
8 | - output out1 (4 bits)
9 | - output out2 (4 bits)
10 | - output out3 (4 bits)
11 | - output out4 (4 bits)
12 | - output out5 (4 bits)
13 | - output out6 (4 bits)
14 | - output out7 (4 bits)
15 |
16 | The module should implement a 4-bit 1-to-8 demultiplexer. The input sel
17 | should select which of the outputs is written with the value of the input
18 | port in_. Unselected output ports should be set to all zeros. If sel
19 | equals 0 then out0 should be selected, if sel equals 1 then then out1
20 | should be selected, and so on.
21 |
22 |
--------------------------------------------------------------------------------
/dataset/Prob05p06_comb_mux_4b_5to1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (4 bits)
6 | - input in1 (4 bits)
7 | - input in2 (4 bits)
8 | - input in3 (4 bits)
9 | - input in4 (4 bits)
10 | - input sel (3 bits)
11 | - output out (4 bits)
12 |
13 | The module should implement a 4-bit 5-to-1 multiplexer. The input sel
14 | should select which of the inputs is used to write the output. If sel
15 | equals 0 then in0 should be selected, if sel equals 1 then in1 should be
16 | selected, and so on. If the sel signal is invalid then the output should
17 | be set to all zeros.
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob05p07_comb_mux_4b_1to5_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - input sel (3 bits)
7 | - output out0 (4 bits)
8 | - output out1 (4 bits)
9 | - output out2 (4 bits)
10 | - output out3 (4 bits)
11 | - output out4 (4 bits)
12 |
13 | The module should implement a 4-bit 1-to-5 demultiplexer. The input sel
14 | should select which of the outputs is written with the value of the input
15 | port in_. Unselected output ports should be set to all zeros. If sel
16 | equals 0 then out0 should be selected, if sel equals 1 then out1 should
17 | be selected, and so on. If the sel signal is invalid then all outputs
18 | should be set to all zeros.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob05p08_comb_mux_1b_128to1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (128 bits)
6 | - input sel ( 7 bits)
7 | - output out
8 |
9 | The module should implement a 1-bit 128-to-1 multiplexer. The input sel
10 | should select which bit of the input in_ is used to write the output. If
11 | sel equals 0 then bit 0 of in_ should be selected, if sel equals 1 then
12 | bit 1 of in_ should be selected, and so on.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob05p09_comb_mux_1b_1to128_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_
6 | - input sel ( 7 bits)
7 | - output out (128 bits)
8 |
9 | The module should implement a 1-bit 1-to-128. The input sel
10 | should select which bit of the output is written with the value of the
11 | input port in_. Unselected output bits should be set to zero. If sel
12 | equals 0 then bit 0 of out should be selected, if sel equals 1 then bit 1
13 | of out should be selected, and so on.
14 |
15 |
--------------------------------------------------------------------------------
/dataset/Prob06p01_comb_codes_enc_4to2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out (2 bits)
7 |
8 | The module should implement a 4-to-2 encoder. The input is a one-hot
9 | signal (i.e., exactly one bit is one) and the output is a binary encoded
10 | value indicating the index of the input bit which is set to one. If the
11 | input is an invalid one-hot encoding then the output should be zero.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob06p02_comb_codes_enc_16to4_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (16 bits)
6 | - output out (4 bits)
7 |
8 | The module should implement a 16-to-4 encoder. The input is a one-hot
9 | signal (i.e., exactly one bit is one) and the output is a binary encoded
10 | value indicating the index of the input bit which is set to one. If the
11 | input is an invalid one-hot encoding then the output should be zero.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob06p03_comb_codes_dec_2to4_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (2 bits)
6 | - output out (4 bits)
7 |
8 | The module should implement a 2-to-4 decoder. The output is a one-hot
9 | signal (i.e., exactly one bit is one) and the input is a binary encoded
10 | value indicating which bit of the output should be set to one.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob06p03_comb_codes_dec_2to4_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob06p03_comb_codes_dec_2to4_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in_", InputPort (2) ),
18 | ( "out", OutputPort(4) ),
19 | ],
20 | )
21 |
22 | #-------------------------------------------------------------------------
23 | # test_case_directed
24 | #-------------------------------------------------------------------------
25 |
26 | def test_case_directed( pytestconfig ):
27 | run_sim( pytestconfig, __file__, config,
28 | [
29 | 0b00,
30 | 0b01,
31 | 0b10,
32 | 0b11,
33 | ])
34 |
35 |
--------------------------------------------------------------------------------
/dataset/Prob06p04_comb_codes_dec_4to16_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out (16 bits)
7 |
8 | The module should implement a 4-to-16 decoder. The output is a one-hot
9 | signal (i.e., exactly one bit is one) and the input is a binary encoded
10 | value indicating which bit of the output should be set to one.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob06p04_comb_codes_dec_4to16_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob06p04_comb_codes_dec_4to16_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in_", InputPort ( 4) ),
18 | ( "out", OutputPort(16) ),
19 | ],
20 | )
21 |
22 | #-------------------------------------------------------------------------
23 | # test_case_directed
24 | #-------------------------------------------------------------------------
25 |
26 | def test_case_directed( pytestconfig ):
27 | run_sim( pytestconfig, __file__, config,
28 | [
29 | 0b0000,
30 | 0b0001,
31 | 0b0010,
32 | 0b0011,
33 | 0b0100,
34 | 0b0101,
35 | 0b0110,
36 | 0b0111,
37 |
38 | 0b1000,
39 | 0b1001,
40 | 0b1010,
41 | 0b1011,
42 | 0b1100,
43 | 0b1101,
44 | 0b1110,
45 | 0b1111,
46 | ])
47 |
48 |
--------------------------------------------------------------------------------
/dataset/Prob06p05_comb_codes_penc_4to2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out (2 bits)
7 |
8 | The module should implement a 4-to-2 priority encoder. The output is a
9 | binary encoded value indicating the index of the input bit which is set
10 | to one. If more than one bit of the input is set to one, then the module
11 | should choose the "highest priority" bit (i.e., the bit with the lowest
12 | index). If no bits are set in the input, then the output should be zero.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob06p05_comb_codes_penc_4to2_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob06p05_comb_codes_penc_4to2_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in_", InputPort (4) ),
18 | ( "out", OutputPort(2) ),
19 | ],
20 | )
21 |
22 | #-------------------------------------------------------------------------
23 | # test_case_directed
24 | #-------------------------------------------------------------------------
25 |
26 | def test_case_directed( pytestconfig ):
27 | run_sim( pytestconfig, __file__, config,
28 | [
29 | 0b0000,
30 | 0b0001,
31 | 0b0010,
32 | 0b0011,
33 | 0b0100,
34 | 0b0101,
35 | 0b0110,
36 | 0b0111,
37 |
38 | 0b1000,
39 | 0b1001,
40 | 0b1010,
41 | 0b1011,
42 | 0b1100,
43 | 0b1101,
44 | 0b1110,
45 | 0b1111,
46 | ])
47 |
48 |
--------------------------------------------------------------------------------
/dataset/Prob06p06_comb_codes_penc_16to4_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (16 bits)
6 | - output out ( 4 bits)
7 |
8 | The module should implement a 16-to-4 priority encoder. The output is a
9 | binary encoded value indicating the index of the input bit which is set
10 | to one. If more than one bit of the input is set to one, then the module
11 | should choose the "highest priority" bit (i.e., the bit with the lowest
12 | index). If no bits are set in the input, then the output should be zero.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob06p07_comb_codes_bin2gcode_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out (4 bits)
7 |
8 | The module should convert a 4-bit binary encoded value into a 4-bit gray
9 | code encoded value.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob06p08_comb_codes_gcode2bin_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out (4 bits)
7 |
8 | The module should convert a 4-bit gray code encoded value into a 4-bit
9 | binary encoded value.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob06p09_comb_codes_bin2bcd_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (4 bits)
6 | - output out (8 bits)
7 |
8 | The module should convert a 4-bit binary encoded value into a 2-digit
9 | natural binary coded decimal (BCD) value. In an natural BCD encoding
10 | (also called an 8421 encoding), each decimal digital is represented by it
11 | corresponding 4-bit binary value.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob06p09_comb_codes_bin2bcd_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob06p09_comb_codes_bin2bcd_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in_", InputPort (4) ),
18 | ( "out", OutputPort(8) ),
19 | ],
20 | )
21 |
22 | #-------------------------------------------------------------------------
23 | # test_case_directed
24 | #-------------------------------------------------------------------------
25 |
26 | def test_case_directed( pytestconfig ):
27 | run_sim( pytestconfig, __file__, config,
28 | [
29 | 0b0000,
30 | 0b0001,
31 | 0b0010,
32 | 0b0011,
33 |
34 | 0b0100,
35 | 0b0101,
36 | 0b0110,
37 | 0b0111,
38 |
39 | 0b1000,
40 | 0b1001,
41 | 0b1010,
42 | 0b1011,
43 |
44 | 0b1100,
45 | 0b1101,
46 | 0b1110,
47 | 0b1111,
48 | ])
49 |
50 |
--------------------------------------------------------------------------------
/dataset/Prob06p10_comb_codes_bcd2bin_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output out (4 bits)
7 |
8 | The module should convert a 2-digit natural binary coded decimal (BCD)
9 | value to a 4-bit binary encoded value. In an natural BCD encoding (also
10 | called an 8421 encoding), each decimal digital is represented by it
11 | corresponding 4-bit binary value. If the input is an invalid BCD encoding
12 | then the output should be zero. If the BCD encoded value cannot be
13 | represented using a 4-bit binary encoded value then the output should be
14 | zero.
15 |
16 |
--------------------------------------------------------------------------------
/dataset/Prob06p11_comb_codes_bin2ascii_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ ( 4 bits)
6 | - output out (16 bits)
7 |
8 | The module should convert a 4-bit binary encoded value to a 2-digit ASCII
9 | encoded value (using a decimal representation). For example, if the input
10 | is 0b0010, then the output should be the ASCII encoding for "02" and if
11 | the input is 0b1000, then the output should be the ASCII encoding for
12 | "10".
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob06p11_comb_codes_bin2ascii_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob06p11_comb_codes_bin2ascii_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "in_", InputPort ( 4) ),
18 | ( "out", OutputPort(16) ),
19 | ],
20 | )
21 |
22 | #-------------------------------------------------------------------------
23 | # test_case_directed
24 | #-------------------------------------------------------------------------
25 |
26 | def test_case_directed( pytestconfig ):
27 | run_sim( pytestconfig, __file__, config,
28 | [
29 | 0b0000,
30 | 0b0001,
31 | 0b0010,
32 | 0b0011,
33 |
34 | 0b0100,
35 | 0b0101,
36 | 0b0110,
37 | 0b0111,
38 |
39 | 0b1000,
40 | 0b1001,
41 | 0b1010,
42 | 0b1011,
43 |
44 | 0b1100,
45 | 0b1101,
46 | 0b1110,
47 | 0b1111,
48 | ])
49 |
50 |
--------------------------------------------------------------------------------
/dataset/Prob06p12_comb_codes_ascii2bin_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (16 bits)
6 | - output out ( 4 bits)
7 |
8 | The module should convert a 2-digit ASCII encoded value (using a decimal
9 | representation) to a 4-bit binary encoded value. For example, if the
10 | input is "02" then the output should be 0b0010 and if the input is "10"
11 | then the output should be 0b1000. If the input value cannot be
12 | represented as a 4-bit binary encoded value then the output should be set
13 | to zero.
14 |
15 |
--------------------------------------------------------------------------------
/dataset/Prob06p13_comb_codes_8b_parity_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output out
7 |
8 | The module should set the output to the even parity of the given 8-bit
9 | input value.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob06p14_comb_codes_100b_parity_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (100 bits)
6 | - output out
7 |
8 | The module should set the output to the even parity of the given 100-bit
9 | input value.
10 |
11 |
--------------------------------------------------------------------------------
/dataset/Prob07p01_comb_arith_8b_add_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an adder which adds the two given inputs and
10 | writes the result to the output. Assume all values are encoded as two's
11 | complement binary numbers.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob07p02_comb_arith_8b_add_carry_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - input cin
8 | - output out (8 bits)
9 | - output cout
10 |
11 | The module should implement an adder which adds the two given inputs and
12 | writes the result to the output. The adder should also include the carry
13 | input (i.e., the cin port) as part of the addition, and should write the
14 | final carry output to the cout port. Assume all values are encoded as
15 | two's complement binary numbers.
16 |
17 |
--------------------------------------------------------------------------------
/dataset/Prob07p03_comb_arith_8b_sub_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement a subtractor which subtracts in1 from in0 and
10 | writes the result to the output. Assume all values are encoded as two's
11 | complement binary numbers.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob07p04_comb_arith_8b_popcount_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - output out (4 bits)
7 |
8 | The module should implement a popcount unit which calculates the
9 | population count (i.e., the number of ones) of the input and writes the
10 | result to the output.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob07p05_comb_arith_100b_popcount_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (100 bits)
6 | - output out ( 7 bits)
7 |
8 | The module should implement a popcount unit which calculates the
9 | population count (i.e., the number of ones) of the input and writes the
10 | result to the output.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob07p06_comb_arith_8b_shifter_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - input amt (3 bits)
7 | - input op
8 | - output out (8 bits)
9 |
10 | The module should implement a variable shifter which takes as input a
11 | value to shift (in_) and the shift amount (amt) and writes the shifted
12 | result to the output (out). The input op specifies what kind of shift to
13 | perform using the following encoding:
14 |
15 | - 0 : shift left logical (shift in zeros)
16 | - 1 : shift right logical (shift in zeros)
17 |
18 |
--------------------------------------------------------------------------------
/dataset/Prob07p07_comb_arith_8b_sra_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - input amt (3 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement a variable right arithmetic shifter which
10 | takes as input a value to shift (in_) and the shift amount (amt) and
11 | writes the shifted result to the output (out).
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob07p08_comb_arith_8b_rotator_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in_ (8 bits)
6 | - input amt (3 bits)
7 | - input op
8 | - output out (8 bits)
9 |
10 | The module should implement a variable rotator which takes as input a
11 | value to rotate (in_) and the rotation amount (amt) and writes the
12 | rotated result to the output (out). The input op specifies what kind of
13 | rotate to perform using the following encoding:
14 |
15 | - 0 : rotate left
16 | - 1 : rotate right
17 |
18 |
--------------------------------------------------------------------------------
/dataset/Prob07p09_comb_arith_8b_umul_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 ( 8 bits)
6 | - input in1 ( 8 bits)
7 | - output out (16 bits)
8 |
9 | The module should implement an unsigned multiplier which multiplies the
10 | two given inputs and writes the result to the output. Assume all values
11 | are encoded as unsigned binary numbers.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob07p10_comb_arith_8b_smul_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 ( 8 bits)
6 | - input in1 ( 8 bits)
7 | - output out (16 bits)
8 |
9 | The module should implement a signed multiplier which multiplies the two
10 | given inputs and writes the result to the output. Assume all values are
11 | encoded as two's complement binary numbers.
12 |
13 |
--------------------------------------------------------------------------------
/dataset/Prob07p11_comb_arith_8b_fxp_umul_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - output out (8 bits)
8 | - output overflow
9 |
10 | The module should implement an unsigned fixed-point multiplier which
11 | multiplies the two given inputs and writes the result to the output.
12 | Assume all values are encoded as UQ4.4 fixed point (i.e., the most
13 | significant four bits represent the integer part and the least
14 | significant four bits represent the fraction part). Because the output is
15 | only 8 bits there is a chance of overflow (the full-precision output is
16 | too large to represent using UQ4.4). In the case of overflow, set the
17 | overflow signal high and the output to zero.
18 |
19 |
--------------------------------------------------------------------------------
/dataset/Prob07p12_comb_arith_8b_madd_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 ( 8 bits)
6 | - input in1 ( 8 bits)
7 | - input in2 (16 bits)
8 | - output out (16 bits)
9 |
10 | The module should implement an unsigned multiply-add unit which
11 | multiplies the the inputs in0 and in1, adds the corresponding product to
12 | the input in2, and writes the result to the output. Assume all values are
13 | encoded as unsigned binary numbers.
14 |
15 |
--------------------------------------------------------------------------------
/dataset/Prob07p13_comb_arith_8b_ucmp_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 ( 8 bits)
6 | - input in1 ( 8 bits)
7 | - output lt
8 | - output eq
9 | - output gt
10 |
11 | The module should implement an unsigned comparator which compares the two
12 | given inputs and updates all three outputs as follows:
13 |
14 | - lt should be one if in0 is less than in1
15 | - eq should be one if in0 is equal to in1
16 | - gt should be one if in0 is greater than in1
17 |
18 | Assume all values are encoded as unsigned binary numbers.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob07p14_comb_arith_8b_scmp_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 ( 8 bits)
6 | - input in1 ( 8 bits)
7 | - output lt
8 | - output eq
9 | - output gt
10 |
11 | The module should implement a signed comparator which compares the two
12 | given inputs and updates all three outputs as follows:
13 |
14 | - lt should be one if in0 is less than in1
15 | - eq should be one if in0 is equal to in1
16 | - gt should be one if in0 is greater than in1
17 |
18 | Assume all values are encoded as two's complement binary numbers.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob07p15_comb_arith_8b_alu_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - input op (3 bits)
8 | - output out (8 bits)
9 |
10 | The module should implement an arithmetic logic unit (ALU) which performs
11 | a specific operation on the in0 and in1 inputs based on the op input and
12 | writes the result to the output. The op input encoding is as follows:
13 |
14 | - 0 : addition (out = in0 + in1)
15 | - 1 : subtraction (out = in0 - in1)
16 | - 2 : shift left logical (out = in0 << in1)
17 | - 3 : shift right logical (out = in0 >> in1)
18 | - 4 : less than (out = in0 < in1)
19 | - 5 : equal (out = in0 == in1)
20 | - 6 : greater than (out = in0 > in1)
21 |
22 | Assume all values are encoded as unsigned binary numbers. Note that for
23 | the shift operations, only the least-significant three bits of the shift
24 | amount (i.e., in1) should be used, the remaining bits should be ignored.
25 | The output should be set to zero for any invalid op input encoding.
26 |
27 |
--------------------------------------------------------------------------------
/dataset/Prob07p16_comb_arith_2x8b_minmax_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - output min (8 bits)
8 | - output max (8 bits)
9 |
10 | The module should implement a min/max unit which compares the two inputs
11 | and writes the minimum value to the min output and the maximum value to
12 | the max output. Assume all values are encoded as unsigned binary numbers.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob07p17_comb_arith_4x8b_sorter_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input in0 (8 bits)
6 | - input in1 (8 bits)
7 | - input in2 (8 bits)
8 | - input in3 (8 bits)
9 | - output out0 (8 bits)
10 | - output out1 (8 bits)
11 | - output out2 (8 bits)
12 | - output out3 (8 bits)
13 |
14 | The module should implement a sorter unit which writes the smallest input
15 | value to out0, the second smallest input value to out1, and so on. Assume
16 | all values are encoded as unsigned binary numbers.
17 |
18 |
--------------------------------------------------------------------------------
/dataset/Prob08p01_comb_fsm_4s1i1o_mo_tbl0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (4 bits)
6 | - input in_
7 | - output state_next (4 bits)
8 | - output out
9 |
10 | The module should implement the state transition and output logic for the
11 | Moore finite-state machine (FSM) described by the following table.
12 |
13 | Current | Next State Next State |
14 | State | if in_=0 if in_=1 | Output
15 | ---------+------------------------+--------
16 | A | A B | 0
17 | B | C B | 0
18 | C | A D | 0
19 | D | C B | 1
20 |
21 | The state machine should use the following one-hot state encoding.
22 |
23 | - A : 0b0001
24 | - B : 0b0010
25 | - C : 0b0100
26 | - D : 0b1000
27 |
28 | If the input state is not a valid one-hot encoding then the outputs
29 | should all be zero. The module should only implement the combinational
30 | state transition logic and output logic and should not include any
31 | sequential state.
32 |
33 |
--------------------------------------------------------------------------------
/dataset/Prob08p02_comb_fsm_4s1i1o_mo_tbl1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (2 bits)
6 | - input in_
7 | - output state_next (2 bits)
8 | - output out
9 |
10 | The module should implement the state transition and output logic for the
11 | Moore finite-state machine (FSM) described by the following table.
12 |
13 | Current | Next State Next State |
14 | State | if in_=0 if in_=1 | Output
15 | ---------+------------------------+--------
16 | A | A B | 0
17 | B | C B | 0
18 | C | A D | 0
19 | D | C B | 1
20 |
21 | The state machine should use the following state encoding.
22 |
23 | - A : 0
24 | - B : 1
25 | - C : 2
26 | - D : 3
27 |
28 | The module should only implement the combinational state transition logic
29 | and output logic and should not include any sequential state.
30 |
31 |
--------------------------------------------------------------------------------
/dataset/Prob08p02_comb_fsm_4s1i1o_mo_tbl1_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob08p02_comb_fsm_4s1i1o_mo_tbl1_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "state", InputPort (2) ),
18 | ( "in_", InputPort (1) ),
19 | ( "state_next", OutputPort(2) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | ( 0, 0 ),
32 | ( 0, 1 ),
33 | ( 1, 0 ),
34 | ( 1, 1 ),
35 | ( 2, 0 ),
36 | ( 2, 1 ),
37 | ( 3, 0 ),
38 | ( 3, 1 ),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob08p03_comb_fsm_4s1i1o_me_tbl_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (2 bits)
6 | - input in_
7 | - output state_next (2 bits)
8 | - output out
9 |
10 | The module should implement the state transition and output logic for the
11 | Mealy finite-state machine (FSM) described by the following table. Each
12 | next state entry in the table is of the format X/Y where X is the next
13 | state and Y is the output.
14 |
15 | Current | Next State/Output
16 | State | if in_=0 if in_=1
17 | ---------+----------------------
18 | A | A/0 B/1
19 | B | C/1 B/0
20 | C | A/0 D/1
21 | D | C/0 B/0
22 |
23 | The state machine should use the following state encoding.
24 |
25 | - A : 0
26 | - B : 1
27 | - C : 2
28 | - D : 3
29 |
30 | The module should only implement the combinational state transition logic
31 | and output logic and should not include any sequential state.
32 |
33 |
--------------------------------------------------------------------------------
/dataset/Prob08p03_comb_fsm_4s1i1o_me_tbl_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob08p03_comb_fsm_4s1i1o_me_tbl_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "state", InputPort (2) ),
18 | ( "in_", InputPort (1) ),
19 | ( "state_next", OutputPort(2) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | ( 0, 0 ),
32 | ( 0, 1 ),
33 | ( 1, 0 ),
34 | ( 1, 1 ),
35 | ( 2, 0 ),
36 | ( 2, 1 ),
37 | ( 3, 0 ),
38 | ( 3, 1 ),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob08p04_comb_fsm_4s1i2o_mo_tbl_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (2 bits)
6 | - input in_
7 | - output state_next (2 bits)
8 | - output out0
9 | - output out1
10 |
11 | The module should implement the state transition and output logic for the
12 | Moore finite-state machine (FSM) described by the following table.
13 |
14 | Current | Next State Next State | Output Output
15 | State | if in_=0 if in_=1 | 0 1
16 | ---------+------------------------+----------------
17 | A | A B | 0 0
18 | B | C B | 0 1
19 | C | A D | 0 1
20 | D | C B | 1 0
21 |
22 | The state machine should use the following state encoding.
23 |
24 | - A : 0
25 | - B : 1
26 | - C : 2
27 | - D : 3
28 |
29 | The module should only implement the combinational state transition logic
30 | and output logic and should not include any sequential state.
31 |
32 |
--------------------------------------------------------------------------------
/dataset/Prob08p04_comb_fsm_4s1i2o_mo_tbl_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob08p04_comb_fsm_4s1i2o_mo_tbl_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "state", InputPort (2) ),
18 | ( "in_", InputPort (1) ),
19 | ( "state_next", OutputPort(2) ),
20 | ( "out0", OutputPort(1) ),
21 | ( "out1", OutputPort(1) ),
22 | ],
23 | )
24 |
25 | #-------------------------------------------------------------------------
26 | # test_case_directed
27 | #-------------------------------------------------------------------------
28 |
29 | def test_case_directed( pytestconfig ):
30 | run_sim( pytestconfig, __file__, config,
31 | [
32 | ( 0, 0 ),
33 | ( 0, 1 ),
34 | ( 1, 0 ),
35 | ( 1, 1 ),
36 | ( 2, 0 ),
37 | ( 2, 1 ),
38 | ( 3, 0 ),
39 | ( 3, 1 ),
40 | ])
41 |
42 |
--------------------------------------------------------------------------------
/dataset/Prob08p05_comb_fsm_4s2i1o_mo_tbl_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (2 bits)
6 | - input in_ (2 bits)
7 | - output state_next (2 bits)
8 | - output out
9 |
10 | The module should implement the state transition and output logic for the
11 | Moore finite-state machine (FSM) described by the following table.
12 |
13 | Current | Next State Next State Next State Next State | Output
14 | State | if in_=00 if in_=01 if in_=10 if in_=11 | 0
15 | ---------+------------------------------------------------+--------
16 | A | A B A D | 0
17 | B | C B A D | 0
18 | C | A D A D | 0
19 | D | C B A D | 1
20 |
21 | The state machine should use the following state encoding.
22 |
23 | - A : 0
24 | - B : 1
25 | - C : 2
26 | - D : 3
27 |
28 | The module should only implement the combinational state transition logic
29 | and output logic and should not include any sequential state.
30 |
31 |
--------------------------------------------------------------------------------
/dataset/Prob08p07_comb_fsm_4s1i1o_mo_dia_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (2 bits)
6 | - input in_
7 | - output state_next (2 bits)
8 | - output out
9 |
10 | The module should implement the state transition and output logic for a
11 | Moore finite-state machine (FSM) with four states. The FSM will be
12 | described as a set of FSM transitions with each transition specified
13 | using the following format.
14 |
15 | X (0) --1--> Y
16 |
17 | In this example, the FSM transitions from state X to state Y when the
18 | input is 1 and the output of the FSM should be 0 during this transition.
19 | Implement the FSM with the following transitions.
20 |
21 | A (0) --0--> A
22 | A (0) --1--> B
23 | B (0) --0--> C
24 | B (0) --1--> B
25 | C (0) --0--> A
26 | C (0) --1--> D
27 | D (1) --0--> C
28 | D (1) --1--> B
29 |
30 | The state machine should use the following state encoding.
31 |
32 | - A : 0
33 | - B : 1
34 | - C : 2
35 | - D : 3
36 |
37 | The module should only implement the combinational state transition logic
38 | and output logic and should not include any sequential state.
39 |
40 |
--------------------------------------------------------------------------------
/dataset/Prob08p07_comb_fsm_4s1i1o_mo_dia_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob08p07_comb_fsm_4s1i1o_mo_dia_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "state", InputPort (2) ),
18 | ( "in_", InputPort (1) ),
19 | ( "state_next", OutputPort(2) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | ( 0, 0 ),
32 | ( 0, 1 ),
33 | ( 1, 0 ),
34 | ( 1, 1 ),
35 | ( 2, 0 ),
36 | ( 2, 1 ),
37 | ( 3, 0 ),
38 | ( 3, 1 ),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob08p08_comb_fsm_4s1i1o_me_dia_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input state (2 bits)
6 | - input in_
7 | - output state_next (2 bits)
8 | - output out
9 |
10 | The module should implement the state transition and output logic for the
11 | Mealy finite-state machine (FSM) with four states. The FSM will be
12 | described as a set of FSM transitions with each transition specified
13 | using the following format.
14 |
15 | X (0) --1--> Y
16 |
17 | In this example, the FSM transitions from state X to state Y when the
18 | input is 1 and the output of the FSM should be 0 during this transition.
19 | Implement the FSM with the following transitions.
20 |
21 | A (0) --0--> A
22 | A (1) --1--> B
23 | B (1) --0--> C
24 | B (0) --1--> B
25 | C (0) --0--> A
26 | C (1) --1--> D
27 | D (0) --0--> C
28 | D (0) --1--> B
29 |
30 | The state machine should use the following state encoding.
31 |
32 | - A : 0
33 | - B : 1
34 | - C : 2
35 | - D : 3
36 |
37 | The module should only implement the combinational state transition logic
38 | and output logic and should not include any sequential state.
39 |
40 |
--------------------------------------------------------------------------------
/dataset/Prob08p08_comb_fsm_4s1i1o_me_dia_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob08p08_comb_fsm_4s1i1o_me_dia_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "state", InputPort (2) ),
18 | ( "in_", InputPort (1) ),
19 | ( "state_next", OutputPort(2) ),
20 | ( "out", OutputPort(1) ),
21 | ],
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | ( 0, 0 ),
32 | ( 0, 1 ),
33 | ( 1, 0 ),
34 | ( 1, 1 ),
35 | ( 2, 0 ),
36 | ( 2, 1 ),
37 | ( 3, 0 ),
38 | ( 3, 1 ),
39 | ])
40 |
41 |
--------------------------------------------------------------------------------
/dataset/Prob09p01_comb_param_const_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - parameter value
7 | - output out (nbits)
8 |
9 | The module implementation should always output the constant given by the
10 | parameter value.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob09p02_comb_param_bit_rev_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in_ (nbits)
7 | - output out (nbits)
8 |
9 | The module implementation should connect the input port to the output
10 | port but with the bits in reversed order. The module is pararmeterized by
11 | bitwidth of each port (nbits). In other words, in_[0] should be connected
12 | to out[nbits-1], in_[1] should be connected to out[nbits-2], and so on.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob09p03_comb_param_nor_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in_ (nbits)
7 | - output out
8 |
9 | The module should implement a NOR gate that is parameterized by the
10 | number of inputs to the logic gate.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob09p04_comb_param_2to1_mux_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in0 (nbits)
7 | - input in1 (nbits)
8 | - input sel
9 | - output out (nbits)
10 |
11 | The module should implement a 2-to-1 multiplexer that is parameterized by
12 | the bitwidth of the input and output ports. The input sel should select
13 | which of the two inputs is used to write the output. If sel equals 0 then
14 | input in0 should be selected and if sel equals 1 then then input in1
15 | should be selected.
16 |
17 |
--------------------------------------------------------------------------------
/dataset/Prob09p05_comb_param_enc_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in_ (nbits)
7 | - output out (log2(nbits))
8 |
9 | The module should implement an N-to-M encoder. The input is a one-hot
10 | signal (i.e., exactly one bit is one) and the output is a binary encoded
11 | value indicating the index of the input bit which is set to one. The
12 | input is nbits wide and the output is log2(nbits) wide. If the input is
13 | an invalid one-hot encoding then the output should be zero.
14 |
15 |
--------------------------------------------------------------------------------
/dataset/Prob09p06_comb_param_dec_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in_ (log2(bits))
7 | - output out (nbits)
8 |
9 | The module should implement an M-to-N decoder. The output is a one-hot
10 | signal (i.e., exactly one bit is one) and the input is a binary encoded
11 | value indicating which bit of the output should be set to one. The output
12 | is nbits wide and the input is log2(nbits) wide. If nbits is not a power
13 | of two, then it might be possible for the input to be too large for the
14 | given number of bits in the output; in this situation set the output to
15 | be zero.
16 |
17 |
--------------------------------------------------------------------------------
/dataset/Prob09p07_comb_param_penc_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in_ (nbits)
7 | - output out (log2(nbits))
8 |
9 | The module should implement an N-to-M priority encoder. The output is a
10 | binary encoded value indicating the index of the input bit which is set
11 | to one. If more than one bit of the input is set to one, then the module
12 | should choose the "highest priority" bit (i.e., the bit with the lowest
13 | index). The input is nbits wide and the output is log2(nbits) wide. If no
14 | bits are set in the input, then the output should be zero.
15 |
16 |
--------------------------------------------------------------------------------
/dataset/Prob09p08_comb_param_rotator_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - parameter nbits
6 | - input in_ (nbits)
7 | - input amt (log2(nbits))
8 | - input op
9 | - output out (nbits)
10 |
11 | The module should implement a variable rotator which takes as input a
12 | value to rotate (in_) and the rotation amount (amt) and writes the
13 | rotated result to the output (out). The module should be parameterized by
14 | the bitwidth (nbits) of the input and output ports; nbits can be assumed
15 | to be a power of two. The input op specifies what kind of rotate to
16 | perform using the following encoding:
17 |
18 | - 0 : rotate left
19 | - 1 : rotate right
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob10p01_seq_gates_1b_dff_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input d
7 | - output q
8 |
9 | The module should implement a D flip-flop. Assume all sequential logic is
10 | triggered on the positive edge of the clock.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob10p01_seq_gates_1b_dff_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob10p01_seq_gates_1b_dff_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "clk", InputPort (1) ),
18 | ( "d", InputPort (1) ),
19 | ( "q", OutputPort(1) ),
20 | ],
21 | dead_cycles=1,
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | 0,
32 | 0, # prev: 0 -> 0 0
33 | 1, # prev: 0 -> 1 0
34 | 1, # prev: 1 -> 1 1
35 | 0, # prev: 1 -> 0 1
36 | 0,
37 | ])
38 |
39 |
--------------------------------------------------------------------------------
/dataset/Prob10p02_seq_gates_1b_dffe_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input en
7 | - input d
8 | - output q
9 |
10 | The module should implement a D flip-flop with an enable. The input
11 | should only be sampled when the enable (en) input is one. Assume all
12 | sequential logic is triggered on the positive edge of the clock.
13 |
14 |
--------------------------------------------------------------------------------
/dataset/Prob10p03_seq_gates_1b_dffr_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input d
8 | - output q
9 |
10 | The module should implement a D flip-flop with an active-high synchronous
11 | reset. The internal state should be reset to zero when the reset input is
12 | one. Assume all sequential logic is triggered on the positive edge of the
13 | clock.
14 |
15 |
--------------------------------------------------------------------------------
/dataset/Prob10p04_seq_gates_8b_dff_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input d (8 bits)
7 | - output q (8 bits)
8 |
9 | The module should implement eight D flip-flops. Assume all sequential
10 | logic is triggered on the positive edge of the clock.
11 |
12 |
--------------------------------------------------------------------------------
/dataset/Prob10p05_seq_gates_8b_dffre_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input d (8 bits)
9 | - output q (8 bits)
10 |
11 | The module should implement eight D flip-flops with an active-high
12 | synchronous reset and an enable. The internal state should be reset to
13 | the value 0xff when the reset input is one. The input should only be
14 | sampled when the enable (en) input is one. Assume all sequential logic is
15 | triggered on the positive edge of the clock.
16 |
17 |
--------------------------------------------------------------------------------
/dataset/Prob10p06_seq_gates_8b_dff_byte_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input en ( 2 bits)
7 | - input d (16 bits)
8 | - output q (16 bits)
9 |
10 | The module should implement 16 D flip-flops with byte write enables. The
11 | en input is used to indicate which bytes to write using the following
12 | encoding:
13 |
14 | - 00 : do not write either byte
15 | - 01 : write the least signficant byte
16 | - 10 : write the most significant byte
17 | - 11 : write both bytes
18 |
19 | Assume all sequential logic is triggered on the positive edge of the
20 | clock.
21 |
22 |
--------------------------------------------------------------------------------
/dataset/Prob10p07_seq_gates_nl0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in0
7 | - input in1
8 | - output out
9 |
10 | The module should implement the following circuit: input in0 should be
11 | connected to a D flip-flop; input in1 should be connected to a separate D
12 | flip-flop; the outputs of both D flip-flops should be connected to the
13 | inputs of a two-input AND gate. The output of the AND gate should be
14 | connected to the output port. Assume all sequential logic is triggered on
15 | the positive edge of the clock.
16 |
17 |
--------------------------------------------------------------------------------
/dataset/Prob10p08_seq_gates_nl1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in0
7 | - input in1
8 | - input in2
9 | - output out
10 |
11 | The module should implement the following circuit: input in0 should be
12 | connected to a D flip-flop (let's call this DFF0); input in1 should be
13 | connected to a second D flip-flop (let's call this DFF1); input in2
14 | should be connected to a third D flip-flop (let's call this DFF2); the
15 | outputs of DFF0 an DFF1 should be connected to a two-input XOR gate; the
16 | output of the XOR gate should be conneectd to a NOT gate; the output of
17 | the NOT gate should be connected to the first input of a two-input AND
18 | gate; the output of DFF2 should be connected to the second input of the
19 | two-input AND gate; the output of the AND gate should be connected to the
20 | output port. Assume all sequential logic is triggered on the positive
21 | edge of the clock.
22 |
23 |
--------------------------------------------------------------------------------
/dataset/Prob10p09_seq_gates_nl2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in0
7 | - input in1
8 | - input in2
9 | - input in3
10 | - output out
11 |
12 | The module should implement the following circuit: input in0 should be
13 | connected to a D flip-flop (let's call this DFF0); input in1 should be
14 | connected to a second D flip-flop (let's call this DFF1); input in2
15 | should be connected to a third D flip-flop (let's call this DFF2); input
16 | in3 should be connected to a fourth D flip-flop (let's call this DFF3);
17 | the output of DFF0 should be connected to a NOT gate and the output of
18 | this NOT gate should be connected to the first input of a two-input OR
19 | gate; the output of DFF1 should be connected to the second input of this
20 | two-input OR gate; the output of DFF2 should be connected to the first
21 | input of another two-input OR gate; the output of DFF3 should be
22 | connected to a NOT gate and the output of this NOT gate should be
23 | connected to the second input of the two-input OR gate; the output of
24 | both two-input OR gates should be connected to a two-input AND gate; the
25 | output of the AND gate should be connected to the output port.
26 |
27 |
--------------------------------------------------------------------------------
/dataset/Prob11p01_seq_bool_truth_dff_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input a
7 | - output q
8 |
9 | The module should implement a sequential circuit triggered by the
10 | positive edge of the clock. The module is described by the following
11 | truth table where q indicates the previous value of the state holding
12 | element before the rising edge of the clock and q_next indicates the next
13 | value of the state holding element after the rising edge of the clock.
14 |
15 | a q_prev | q_next
16 | ----------+--------
17 | 0 0 | 0
18 | 0 1 | 0
19 | 1 0 | 1
20 | 1 1 | 1
21 |
22 |
--------------------------------------------------------------------------------
/dataset/Prob11p01_seq_bool_truth_dff_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # Prob11p01_seq_bool_truth_dff_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyhdl_eval.cfg import Config, InputPort, OutputPort
9 | from pyhdl_eval.core import run_sim
10 |
11 | #-------------------------------------------------------------------------
12 | # Configuration
13 | #-------------------------------------------------------------------------
14 |
15 | config = Config(
16 | ports = [
17 | ( "clk", InputPort (1) ),
18 | ( "a", InputPort (1) ),
19 | ( "q", OutputPort(1) ),
20 | ],
21 | dead_cycles=1,
22 | )
23 |
24 | #-------------------------------------------------------------------------
25 | # test_case_directed
26 | #-------------------------------------------------------------------------
27 |
28 | def test_case_directed( pytestconfig ):
29 | run_sim( pytestconfig, __file__, config,
30 | [
31 | 0,
32 | 0, # prev: 0 -> 0 0
33 | 1, # prev: 0 -> 1 0
34 | 1, # prev: 1 -> 1 1
35 | 0, # prev: 1 -> 0 1
36 | 0,
37 | ])
38 |
39 |
--------------------------------------------------------------------------------
/dataset/Prob11p02_seq_bool_truth_tff_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input a
7 | - input b
8 | - output q
9 |
10 | The module should implement a sequential circuit triggered by the
11 | positive edge of the clock. The module is described by the following
12 | truth table where q indicates the previous value of the state holding
13 | element before the rising edge of the clock and q_next indicates the next
14 | value of the state holding element after the rising edge of the clock.
15 |
16 | a b q_prev | q_next
17 | ------------+--------
18 | 0 0 0 | 0
19 | 0 0 1 | 1
20 | 0 1 0 | 1
21 | 0 1 1 | 0
22 | 1 0 0 | 0
23 | 1 0 1 | 0
24 | 1 1 0 | 0
25 | 1 1 1 | 0
26 |
27 |
--------------------------------------------------------------------------------
/dataset/Prob11p03_seq_bool_truth_jkff_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input a
7 | - input b
8 | - output q
9 |
10 | The module should implement a sequential circuit triggered by the
11 | positive edge of the clock. The module is described by the following
12 | truth table where q indicates the previous value of the state holding
13 | element before the rising edge of the clock and q_next indicates the next
14 | value of the state holding element after the rising edge of the clock.
15 |
16 | a b q_prev | q_next
17 | ------------+--------
18 | 0 0 0 | 0
19 | 0 0 1 | 1
20 | 0 1 0 | 0
21 | 0 1 1 | 0
22 | 1 0 0 | 1
23 | 1 0 1 | 1
24 | 1 1 0 | 1
25 | 1 1 1 | 0
26 |
27 |
--------------------------------------------------------------------------------
/dataset/Prob11p04_seq_bool_waveform0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input a
7 | - output f
8 |
9 | The module should implement a sequential circuit with a single bit of
10 | state described by the following simulation waveform. The waveform shows
11 | the input values and the desired output values on every cycle of the
12 | simulation. An X indicates that the output is undefined because there is
13 | no reset signal for this sequential circuit.
14 |
15 | cycle | a f
16 | -------+-----
17 | 0 | 1 X
18 | 1 | 0 1
19 | 2 | 0 0
20 | 3 | 0 0
21 | 4 | 0 0
22 | 5 | 1 0
23 | 6 | 1 1
24 | 7 | 0 1
25 | 8 | 1 0
26 | 9 | 0 1
27 | 10 | 0 0
28 | 11 | 1 0
29 | 12 | 1 1
30 | 13 | 0 1
31 | 14 | 1 0
32 | 15 | 0 1
33 | 16 | 1 0
34 | 17 | 1 1
35 | 18 | 0 1
36 | 19 | 1 0
37 |
38 |
--------------------------------------------------------------------------------
/dataset/Prob11p05_seq_bool_waveform1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input a
7 | - output f
8 |
9 | The module should implement a sequential circuit with a single bit of
10 | state described by the following simulation waveform. The waveform shows
11 | the input values and the desired output values on every cycle of the
12 | simulation. An X indicates that the output is undefined because there is
13 | no reset signal for this sequential circuit.
14 |
15 | cycle | a f
16 | -------+-----
17 | 0 | 1 X
18 | 1 | 0 0
19 | 2 | 0 1
20 | 3 | 0 1
21 | 4 | 0 1
22 | 5 | 1 1
23 | 6 | 1 0
24 | 7 | 0 0
25 | 8 | 1 1
26 | 9 | 0 0
27 | 10 | 0 1
28 | 11 | 1 1
29 | 12 | 1 0
30 | 13 | 0 0
31 | 14 | 1 1
32 | 15 | 0 0
33 | 16 | 1 1
34 | 17 | 1 0
35 | 18 | 0 0
36 | 19 | 1 1
37 |
38 |
--------------------------------------------------------------------------------
/dataset/Prob12p01_seq_sreg_8b_siso_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input sin
9 | - output sout
10 |
11 | The module should implement an 8-bit, serial-input, serial-output shift
12 | register with an active-high synchronous reset and an enable. When the
13 | input en is high, then the shift register should shift all of its values
14 | by one bit to the left and use the input sin as the new least-significant
15 | bit of the shift register. The most-significant bit of the shift register
16 | should connected to the output sout. The shift register should be reset
17 | to zero when the reset input is one. Assume all sequential logic is
18 | triggered on the positive edge of the clock.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob12p02_seq_sreg_8b_piso_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input ld
9 | - input pin (8 bits)
10 | - output sout
11 |
12 | The module should implement an 8-bit, parallel-input, serial-output shift
13 | register with an active-high synchronous reset and an enable. When the
14 | input ld is high (regardless of the value of the input en), then the
15 | parallel input (pin) should be loaded into the shift register. When the
16 | input en is high, then the shift register should shift all of its values
17 | by one bit to the left and shift a zero into the least-significant bit of
18 | the shift register. The most-significant bit of the shift register should
19 | be connected to the output sout. The shift register should be reset to
20 | zero when the reset input is one. Assume all sequential logic is
21 | triggered on the positive edge of the clock.
22 |
23 |
--------------------------------------------------------------------------------
/dataset/Prob12p03_seq_sreg_8b_sipo_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input sin
9 | - output pout
10 |
11 | The module should implement an 8-bit, serial-input, parallel-output shift
12 | register with an active-high synchronous reset and an enable. When the
13 | input en is high, then the shift register should shift all of its values
14 | by one bit to the left and use the input sin as the new the
15 | least-significant bit of the shift register. All eight bits of the shift
16 | register should be connected to the output pout. The shift register
17 | should be reset to zero when the reset input is one. Assume all
18 | sequential logic is triggered on the positive edge of the clock.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob12p04_seq_sreg_8b_universal_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input ld
9 | - input pin (8 bits)
10 | - input sin
11 | - output pout (8bits)
12 | - output sout
13 |
14 | The module should implement an 8-bit universal shift register that
15 | supports parallel-input, serial-input, parallel-output, and
16 | serial-output. The shift register should also include an active-high
17 | synchronous reset and an enable. When the input ld is high (regardless of
18 | the value of the input en and sin), then the parallel input (pin) should
19 | be loaded into the shift register. When the input en is high, then the
20 | shift register should shift all of its values by one bit to the left and
21 | use the input sin as the new least-significant bit of the shift register.
22 | All eight bits of the shift register should be connected to the output
23 | pout. The most-significant bit of the shift register should be connected
24 | to the output sout. The shift register should be reset to zero when the
25 | reset input is one. Assume all sequential logic is triggered on the
26 | positive edge of the clock.
27 |
28 |
--------------------------------------------------------------------------------
/dataset/Prob12p05_seq_sreg_8b_bidir_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input ld
9 | - input pin (8 bits)
10 | - input op
11 | - output pout (8 bits)
12 |
13 | The module should implement an 8-bit bi-directional shift register
14 | active-high synchronous reset and an enable. When the input ld is high
15 | (regardless of the value of the input en), then the parallel input (pin)
16 | should be loaded into the shift register. When the input en is high, then
17 | the shift register should shift all of its values by one bit either left
18 | or right always shifting in a zero. The input op specifies what kind of
19 | shift to perform using the following encoding:
20 |
21 | - 0 : shift left logical (shift in zeros)
22 | - 1 : shift right logical (shift in zeros)
23 |
24 | All eight bits of the shift register should be connected to the output
25 | pout. The shift register should be reset to zero when the reset input is
26 | one. Assume all sequential logic is triggered on the positive edge of the
27 | clock.
28 |
29 |
--------------------------------------------------------------------------------
/dataset/Prob13p01_seq_count_3b_bin_up_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - output out (3 bits)
8 |
9 | The module should implement a 3-bit binary up counter with an active-high
10 | synchronous reset. The counter should be reset to zero when the reset
11 | input is one. The counter should then count up by one every cycle; when
12 | the counter reaches the maximum value it should wrap-around. The internal
13 | counter register should be directly connected to the output port. Assume
14 | all sequential logic is triggered on the positive edge of the clock.
15 |
16 |
--------------------------------------------------------------------------------
/dataset/Prob13p02_seq_count_3b_bin_up_en_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - output out (3 bits)
9 |
10 | The module should implement a 3-bit binary up counter with an active-high
11 | synchronous reset and an enable. The counter should be reset to zero when
12 | the reset input is one. The counter should then count up by one every
13 | cycle as long as the input en is one; when the counter reaches the
14 | maximum value it should wrap-around. The internal counter register should
15 | be directly connected to the output port. Assume all sequential logic is
16 | triggered on the positive edge of the clock.
17 |
18 |
--------------------------------------------------------------------------------
/dataset/Prob13p03_seq_count_3b_bin_dn_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - output out (3 bits)
8 |
9 | The module should implement a 3-bit binary down counter with an
10 | active-high synchronous reset. The counter should be reset to seven when
11 | the reset input is one. The counter should then count down by one every
12 | cycle; when the counter reaches zero it should wrap-around. The internal
13 | counter register should be directly connected to the output port. Assume
14 | all sequential logic is triggered on the positive edge of the clock.
15 |
16 |
--------------------------------------------------------------------------------
/dataset/Prob13p04_seq_count_3b_bin_up_dn_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input op
8 | - output out (3 bits)
9 |
10 | The module should implement a 3-bit binary up/down counter with an
11 | active-high synchronous reset. The counter should be reset to zero when
12 | the reset input is one. The counter should then count either up or down
13 | by one every cycle; when the counter reaches either zero or the maximum
14 | value it should wrap-around. The input op specifies whether to count up
15 | or down using the following encoding:
16 |
17 | - 0 : count up
18 | - 1 : count down
19 |
20 | The internal counter register should be directly connected to the output
21 | port. Assume all sequential logic is triggered on the positive edge of
22 | the clock.
23 |
24 |
--------------------------------------------------------------------------------
/dataset/Prob13p05_seq_count_2b_bin_sat_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input en
8 | - input op
9 | - output out (2 bits)
10 |
11 | The module should implement a 2-bit binary up/down saturating counter
12 | with an active-high synchronous reset. The counter should be reset to two
13 | when the reset input is one. The counter should then count either up or
14 | down by one every cycle as long as the input en is one; when the counter
15 | reaches either zero or the maximum value it should saturate (i.e,
16 | continue to hold the current value and not wrap-around). The input op
17 | specifies whether to count up or down using the following encoding:
18 |
19 | - 0 : count up
20 | - 1 : count down
21 |
22 | The internal counter register should be directly connected to the output
23 | port. Assume all sequential logic is triggered on the positive edge of
24 | the clock.
25 |
26 |
--------------------------------------------------------------------------------
/dataset/Prob13p06_seq_count_3b_bin_var_dn_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input ld
7 | - input in_ (3 bits)
8 | - output out (3 bits)
9 | - output done
10 |
11 | The module should implement a 3-bit binary down counter. When the input
12 | ld is high, then the input (in_) should be loaded into the counter. The
13 | counter should then count down by one every cycle; when the counter
14 | reaches zero it stop counting and remain at zero until a new value is
15 | loaded into the counter. The internal counter register should be directly
16 | connected to the output port. The output done should be (combinationally)
17 | set to one when the counter is zero. Assume all sequential logic is
18 | triggered on the positive edge of the clock.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob13p07_seq_count_4b_dec_up_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - output out (4 bits)
8 |
9 | The module should implement a single-digit decade up counter with an
10 | active-high synchronous reset. The counter should be reset to zero when
11 | the reset input is one. The counter should then count up by one every
12 | cycle; when the counter reaches nine it should wrap-around. The internal
13 | counter register should be directly connected to the output port. Assume
14 | all sequential logic is triggered on the positive edge of the clock.
15 |
16 |
--------------------------------------------------------------------------------
/dataset/Prob13p08_seq_count_timer_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input restart
8 | - input tick
9 | - input run
10 | - output mins (6 bits)
11 | - output secs (6 bits)
12 |
13 | The module should implement a timer with an active-high synchronous
14 | reset. The timer's input clk runs much faster than one Hertz, so the
15 | input tick is used to indicate when the timer should increment. The
16 | module can assume the input tick is asserted for one cycle once a second.
17 |
18 | When the input restart is high, the timer should be cleared to zero. When
19 | both the run and tick signals are high the timer should be incremented.
20 | When the run signal is low, the timer should hold its current value. The
21 | outputs mins and secs should be binary encoded values indicating the
22 | amount of time the timer has been running. If the timer reaches 59
23 | xminutes and 59 seconds it should stop with an output of 59:59.
24 |
25 | The outputs should be reset to zero when the reset input is one. Assume
26 | all sequential logic is triggered on the positive edge of the clock.
27 |
28 |
--------------------------------------------------------------------------------
/dataset/Prob14p01_seq_edge_8b_any_detect_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an 8-bit edge detector that will detect when
10 | an input bit changes from one clock cycle to the next. The module should
11 | detect both positive edges (0 to 1 transitions) and negative edges (1 to
12 | 0 transitions). Output out[i] should be (combinationally) set to zero if
13 | in_[i] has not changed from the previous to the current cycle; output
14 | out[i] should be (combinationally) set to one if in_[i] has changed from
15 | the previous to the current cycle. Here is an example execution trace. An
16 | x indicates that the output bit is undefined because it is the first
17 | cycle and thus there is no previous cycle.
18 |
19 | cycle | in_ out
20 | -------+---------------------
21 | 0 | 0000_0000 xxxx_xxxx
22 | 1 | 0000_0000 0000_0000
23 | 2 | 0001_0001 0001_0001
24 | 3 | 0101_0101 0100_0100
25 | 4 | 0001_0001 0100_0100
26 | 5 | 0100_0100 0101_0101
27 | 6 | 0000_0000 0100_0100
28 | 7 | 0000_0000 0000_0000
29 |
30 | Assume all sequential logic is triggered on the positive edge of the
31 | clock.
32 |
33 |
--------------------------------------------------------------------------------
/dataset/Prob14p02_seq_edge_8b_pos_detect_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an 8-bit edge detector that will detect
10 | positive edges (0 to 1 transitions). Output out[i] should be
11 | (combinationally) set to one if in_[i] was zero on the previous cycle and
12 | is now one on the current cycle; output out[i] should be
13 | (combinationally) set to zero otherwise. Here is an example execution
14 | trace. An x indicates that the output bit is undefined because it is the
15 | first cycle and thus there is no previous cycle.
16 |
17 | cycle | in_ out
18 | -------+---------------------
19 | 0 | 0000_0000 xxxx_xxxx
20 | 1 | 0000_0000 0000_0000
21 | 2 | 0001_0001 0001_0001
22 | 3 | 0101_0101 0100_0100
23 | 4 | 0001_0001 0000_0000
24 | 5 | 0100_0100 0100_0100
25 | 6 | 0000_0000 0000_0000
26 | 7 | 0000_0000 0000_0000
27 |
28 | Assume all sequential logic is triggered on the positive edge of the
29 | clock.
30 |
31 |
--------------------------------------------------------------------------------
/dataset/Prob14p03_seq_edge_8b_capture_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input clear
7 | - input in_ (8 bits)
8 | - output out (8 bits)
9 |
10 | The module should implement an 8-bit edge capture that will capture
11 | positive edges (0 to 1 transitions). Output out[i] should then be
12 | (combinationally) set to one if in_[i] was zero on the previous cycle and
13 | is now one on the current cycle; output out[i] should then remain one
14 | until cleared using the input clear. Here is an example execution trace.
15 | An x indicates that the output bit is undefined because it is the first
16 | cycle and thus there is no previous cycle.
17 |
18 | cycle | in_ out
19 | -------+---------------------
20 | 0 | 0000_0000 xxxx_xxxx
21 | 1 | 0000_0000 0000_0000
22 | 2 | 0001_0001 0001_0001
23 | 3 | 0101_0101 0101_0101
24 | 4 | 0001_0001 0101_0101
25 | 5 | 0100_0100 0101_0101
26 | 6 | 0000_0000 0101_0101
27 | 7 | 0000_0000 0101_0101
28 |
29 | All internal state should be set to zero when the clear input is one.
30 | Assume all sequential logic is triggered on the positive edge of the
31 | clock.
32 |
33 |
--------------------------------------------------------------------------------
/dataset/Prob14p05_seq_edge_8b_max_switch_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in_ (8 bits)
7 | - output max_switching
8 |
9 | The module should detect a "worst case switching event" (i.e., when
10 | adjacent bits switch in opposite directions simultaneously). In other
11 | words, the module should detect when the input switches from 01010101 to
12 | 10101010 or when the input switches from 10101010 to 01010101. On the
13 | cycle a worst case switching event is detected, the output max_switching
14 | should be (combinationally) set to one and set to zero otherwise. Here is
15 | an example execution trace. An X indicates that the output bit is
16 | undefined because it is the first cycle and thus there is no previous
17 | cycle.
18 |
19 | cycle | in_ detected
20 | -------+---------------------
21 | 0 | 0000_0000 X
22 | 1 | 0000_0000 0
23 | 2 | 0001_0001 0
24 | 3 | 0101_0101 0
25 | 4 | 1010_1010 1
26 | 5 | 1010_1010 0
27 | 6 | 0001_0001 0
28 | 7 | 1010_1010 0
29 | 8 | 0101_0101 1
30 | 9 | 1010_1010 1
31 | 10 | 0000_0000 0
32 |
33 | Assume all sequential logic is triggered on the positive edge of the
34 | clock.
35 |
36 |
--------------------------------------------------------------------------------
/dataset/Prob16p01_seq_fsm_4s1i1o_mo_tbl0_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output state (4 bits)
9 | - output out
10 |
11 | The module should implement a Moore finite-state machine (FSM) described
12 | by the following table.
13 |
14 | Current | Next State Next State |
15 | State | if in_=0 if in_=1 | Output
16 | ---------+------------------------+--------
17 | A | A B | 0
18 | B | C B | 0
19 | C | A D | 0
20 | D | C B | 1
21 |
22 | The state machine should use the following one-hot state encoding.
23 |
24 | - A : 0b0001
25 | - B : 0b0010
26 | - C : 0b0100
27 | - D : 0b1000
28 |
29 | The FSM should reset to state A when the reset input is one. The internal
30 | state register should be directly connected to the output port state so
31 | that this output always reflects the current state of the FSM. Assume all
32 | sequential logic is triggered on the positive edge of the clock.
33 |
34 |
--------------------------------------------------------------------------------
/dataset/Prob16p02_seq_fsm_4s1i1o_mo_tbl1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output state (2 bits)
9 | - output out
10 |
11 | The module should implement a Moore finite-state machine (FSM) described
12 | by the following table.
13 |
14 | Current | Next State Next State |
15 | State | if in_=0 if in_=1 | Output
16 | ---------+------------------------+--------
17 | A | A B | 0
18 | B | C B | 0
19 | C | A D | 0
20 | D | C B | 1
21 |
22 | The state machine should use the following state encoding.
23 |
24 | - A : 0
25 | - B : 1
26 | - C : 2
27 | - D : 3
28 |
29 | The FSM should reset to state A when the reset input is one. The internal
30 | state register should be directly connected to the output port state so
31 | that this output always reflects the current state of the FSM. Assume all
32 | sequential logic is triggered on the positive edge of the clock.
33 |
34 |
--------------------------------------------------------------------------------
/dataset/Prob16p03_seq_fsm_4s1i1o_me_tbl_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output state (2 bits)
9 | - output out
10 |
11 | The module should implement a Mealy finite-state machine (FSM) described
12 | by the following table. Each next state entry in the table is of the
13 | format X/Y where X is the next state and Y is the output.
14 |
15 | Current | Next State/Output
16 | State | if in_=0 if in_=1
17 | ---------+----------------------
18 | A | A/0 B/1
19 | B | C/1 B/0
20 | C | A/0 D/1
21 | D | C/0 B/0
22 |
23 | The state machine should use the following state encoding.
24 |
25 | - A : 0
26 | - B : 1
27 | - C : 2
28 | - D : 3
29 |
30 | The FSM should reset to state A when the reset input is one. The internal
31 | state register should be directly connected to the output port state so
32 | that this output always reflects the current state of the FSM. Assume all
33 | sequential logic is triggered on the positive edge of the clock.
34 |
35 |
--------------------------------------------------------------------------------
/dataset/Prob16p04_seq_fsm_4s1i2o_mo_tbl_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output state (2 bits)
9 | - output out0
10 | - output out1
11 |
12 | The module should implement a Moore finite-state machine (FSM) described
13 | by the following table.
14 |
15 | Current | Next State Next State | Output Output
16 | State | if in_=0 if in_=1 | 0 1
17 | ---------+------------------------+----------------
18 | A | A B | 0 0
19 | B | C B | 0 1
20 | C | A D | 0 1
21 | D | C B | 1 0
22 |
23 | The state machine should use the following state encoding.
24 |
25 | - A : 0
26 | - B : 1
27 | - C : 2
28 | - D : 3
29 |
30 | The FSM should reset to state A when the reset input is one. The internal
31 | state register should be directly connected to the output port state so
32 | that this output always reflects the current state of the FSM. Assume all
33 | sequential logic is triggered on the positive edge of the clock.
34 |
35 |
--------------------------------------------------------------------------------
/dataset/Prob16p05_seq_fsm_4s2i1o_mo_tbl_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_ (2 bits)
8 | - output state (2 bits)
9 | - output out
10 |
11 | The module should implement a Moore finite-state machine (FSM) described
12 | by the following table.
13 |
14 | Current | Next State Next State Next State Next State | Output
15 | State | if in_=00 if in_=01 if in_=10 if in_=11 | 0
16 | ---------+------------------------------------------------+--------
17 | A | A B A D | 0
18 | B | C B A D | 0
19 | C | A D A D | 0
20 | D | C B A D | 1
21 |
22 | The state machine should use the following state encoding.
23 |
24 | - A : 0
25 | - B : 1
26 | - C : 2
27 | - D : 3
28 |
29 | The FSM should reset to state A when the reset input is one. The internal
30 | state register should be directly connected to the output port state so
31 | that this output always reflects the current state of the FSM. Assume all
32 | sequential logic is triggered on the positive edge of the clock.
33 |
34 |
--------------------------------------------------------------------------------
/dataset/Prob16p07_seq_fsm_4s1i1o_mo_dia_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output state (2 bits)
9 | - output out
10 |
11 | The module should implement a Moore finite-state machine (FSM) with four
12 | states. The FSM will be described as a set of FSM transitions with each
13 | transition specified using the following format.
14 |
15 | X (0) --1--> Y
16 |
17 | In this example, the FSM transitions from state X to state Y when the
18 | input is 1 and the output of the FSM should be 0 during this transition.
19 | Implement the FSM with the following transitions.
20 |
21 | A (0) --0--> A
22 | A (0) --1--> B
23 | B (0) --0--> C
24 | B (0) --1--> B
25 | C (0) --0--> A
26 | C (0) --1--> D
27 | D (1) --0--> C
28 | D (1) --1--> B
29 |
30 | The state machine should use the following state encoding.
31 |
32 | - A : 0
33 | - B : 1
34 | - C : 2
35 | - D : 3
36 |
37 | The FSM should reset to state A when the reset input is one. The internal
38 | state register should be directly connected to the output port state so
39 | that this output always reflects the current state of the FSM. Assume all
40 | sequential logic is triggered on the positive edge of the clock.
41 |
42 |
--------------------------------------------------------------------------------
/dataset/Prob16p08_seq_fsm_4s1i1o_me_dia_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output state (2 bits)
9 | - output out
10 |
11 | The module should implement a Mealy finite-state machine (FSM) with four
12 | states. The FSM will be described as a set of FSM transitions with each
13 | transition specified using the following format.
14 |
15 | X (0) --1--> Y
16 |
17 | In this example, the FSM transitions from state X to state Y when the
18 | input is 1 and the output of the FSM should be 0 during this transition.
19 | Implement the FSM with the following transitions.
20 |
21 | A (0) --0--> A
22 | A (1) --1--> B
23 | B (1) --0--> C
24 | B (0) --1--> B
25 | C (0) --0--> A
26 | C (1) --1--> D
27 | D (0) --0--> C
28 | D (0) --1--> B
29 |
30 | The state machine should use the following state encoding.
31 |
32 | - A : 0
33 | - B : 1
34 | - C : 2
35 | - D : 3
36 |
37 | The FSM should reset to state A when the reset input is one. The internal
38 | state register should be directly connected to the output port state so
39 | that this output always reflects the current state of the FSM. Assume all
40 | sequential logic is triggered on the positive edge of the clock.
41 |
42 |
--------------------------------------------------------------------------------
/dataset/Prob16p10_seq_fsm_pattern1_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output out
9 |
10 | The module should implement a Mealy finite-state machine (FSM) with an
11 | active-high synchronous reset. The FSM should recognize the target
12 | pattern 101 in the binary sequence sampled at the input one bit per
13 | cycle. When the FSM detects the target pattern 101, it should
14 | (combinationally) set the output to one on the same cycle it sees the
15 | final bit of the target pattern. The FSM should detect overlapping target
16 | patterns. Here is an example execution trace.
17 |
18 | cycle | in_ out
19 | -------+-------------
20 | 0 | 0 0
21 | 1 | 0 0
22 | 2 | 1 0
23 | 3 | 0 0
24 | 4 | 1 1
25 | 5 | 0 0
26 | 6 | 1 1
27 | 7 | 0 0
28 |
29 | Assume all sequential logic is triggered on the positive edge of the
30 | clock.
31 |
32 |
--------------------------------------------------------------------------------
/dataset/Prob16p11_seq_fsm_pattern2_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_
8 | - output out
9 |
10 | The module should implement a Mealy finite-state machine (FSM) with an
11 | active-high synchronous reset. The FSM should recognize the target
12 | pattern 1110 in the binary sequence sampled at the input one bit per
13 | cycle. When the FSM detects the target pattern 1110, it should
14 | (combinationally) set the output to one on the same cycle it sees the
15 | final bit of the target pattern. The FSM should detect overlapping target
16 | patterns. Here is an example execution trace.
17 |
18 | cycle | in_ out
19 | -------+-------------
20 | 0 | 0 0
21 | 1 | 1 0
22 | 2 | 1 0
23 | 3 | 1 0
24 | 4 | 1 0
25 | 5 | 0 1
26 | 6 | 1 0
27 | 7 | 0 0
28 |
29 | Assume all sequential logic is triggered on the positive edge of the
30 | clock.
31 |
32 |
--------------------------------------------------------------------------------
/dataset/Prob16p12_seq_fsm_stop_light_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input starting_yellow
8 | - input change
9 | - output green_on
10 | - output yellow_on
11 | - output red_on
12 |
13 | The module should implement a Moore finite-state machine (FSM) for a
14 | traffic light controller with an active-high synchronous reset. The three
15 | outputs are used to turn on one of the three traffic lights. Only one
16 | light should be on at a time. The FSM should reset to the state which
17 | turns on the green light. The input change is used to move between the
18 | states of the FSM in one of two orders depending on whether the input
19 | starting_yellow is high or low. If starting_yellow is high, then the FSM
20 | should change from green, to yellow, to red, to yellow, and back to
21 | green. If starting_yellow is low, then the FSM should change from green,
22 | to yellow, to red, and back to green. Assume that the starting_yellow
23 | signal will only switch when the traffic light is in the state which
24 | turns on the green light. Assume all sequential logic is triggered on the
25 | positive edge of the clock.
26 |
27 |
--------------------------------------------------------------------------------
/dataset/Prob17p01_seq_mem_8x8b_1r1w_rf_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input read_addr (3 bits)
7 | - output read_data (8 bits)
8 | - input write_en
9 | - input write_addr (3 bits)
10 | - input write_data (8 bits)
11 |
12 | The module should implement an 8-entry 8-bit register file with one read
13 | port and one write port. The read port should be combinational (i.e., the
14 | read data corresponds to the input read address on that cycle) and writes
15 | should only occur when the write enable is high. The register file should
16 | always read the value currently stored in the register file even if the
17 | write address equals the read address. Assume all sequential logic is
18 | triggered on the positive edge of the clock.
19 |
20 |
--------------------------------------------------------------------------------
/dataset/Prob17p02_seq_mem_8x8b_1r1w_rf_fw_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input read_addr (3 bits)
7 | - output read_data (8 bits)
8 | - input write_en
9 | - input write_addr (3 bits)
10 | - input write_data (8 bits)
11 |
12 | The module should implement an 8-entry 8-bit register file with one read
13 | port and one write port. The read port should be combinational (i.e., the
14 | read data corresponds to the input read address on that cycle) and writes
15 | should only occur when the write enable is high. If the write enable is
16 | high and write address and the read address are equal, then the read data
17 | should be combinationally set to the write data (i.e., the data should be
18 | forwarded from the write port to the read port). Assume all sequential
19 | logic is triggered on the positive edge of the clock.
20 |
21 |
--------------------------------------------------------------------------------
/dataset/Prob17p03_seq_mem_8x8b_1r1w_rf_z_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input read_addr (3 bits)
7 | - output read_data (8 bits)
8 | - input write_en
9 | - input write_addr (3 bits)
10 | - input write_data (8 bits)
11 |
12 | The module should implement an 8-entry 8-bit register file with one read
13 | port and one write port. The read port should be combinational (i.e., the
14 | read data corresponds to the input read address on that cycle) and writes
15 | should only occur when the write enable is high. The register file should
16 | always read the value currently stored in the register file even if the
17 | write address equals the read address. The register file should treat
18 | register zero specially; reading register zero should always return the
19 | value zero. Writing register zero is valid but should have no observable
20 | effect. Assume all sequential logic is triggered on the positive edge of
21 | the clock.
22 |
23 |
--------------------------------------------------------------------------------
/dataset/Prob17p04_seq_mem_8x8b_1r1w_rf_pw_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input read_addr (3 bits)
7 | - output read_data (8 bits)
8 | - input write_nibble_en (2 bits)
9 | - input write_addr (3 bits)
10 | - input write_data (8 bits)
11 |
12 | The module should implement an 8-entry 8-bit register file with one read
13 | port and one write port. The read port should be combinational (i.e., the
14 | read data corresponds to the input read address on that cycle). The input
15 | write_nibble_en is used to specify a "partial write", i.e., which nibble
16 | should be written into the register file as follows:
17 |
18 | - 00 : do not write any data
19 | - 01 : write least significant four bits
20 | - 10 : write most significant four bits
21 | - 11 : write all eight bits
22 |
23 | The register file should always read the value currently stored in the
24 | register file even if the write address equals the read address. Assume
25 | all sequential logic is triggered on the positive edge of the clock.
26 |
27 |
--------------------------------------------------------------------------------
/dataset/Prob18p04_seq_arith_8b_accum_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input reset
7 | - input in_ (8 bits)
8 | - output out (8 bits)
9 |
10 | The module should implement an 8-bit accumulator with an internal 8-bit
11 | accumulator register and an active-high synchronous reset. The internal
12 | accumulator register should be reset to zero when the reset input is one.
13 | There should be no latency through the accumulator (i.e., the output
14 | should be a combinational function of the inputs). The accumulator should
15 | be able to achieve full throughput, i.e., it should be able to accept a
16 | new input every cycle and produce a valid output every cycle. Here is an
17 | example execution trace.
18 |
19 | cycle | in_ out
20 | -------+-----------
21 | 0 | 00 00
22 | 1 | 01 01
23 | 1 | 02 03
24 | 1 | 04 07
25 | 1 | 04 0b
26 |
27 | Assume all sequential logic is triggered on the positive edge of the
28 | clock. Assume all values are encoded as two's complement binary numbers.
29 |
30 |
--------------------------------------------------------------------------------
/dataset/Prob19p01_seq_pipe_delay_1stage_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement a one-stage pipelined channel where the input
10 | data is passed unchanged through one stage of pipeline registers. Here
11 | is an example execution trace. An X indicates that the output is
12 | undefined because there is no reset signal for the pipeline registers.
13 |
14 | cycle | in_ out
15 | -------+---------
16 | 0 | 00 XX
17 | 1 | 0a 00
18 | 2 | 0b 0a
19 | 3 | 0c 0b
20 | 4 | 0d 0c
21 | 5 | 0e 0d
22 | 6 | 0f 0e
23 | 7 | 00 0f
24 |
25 | Assume all sequential logic is triggered on the positive edge of the
26 | clock.
27 |
28 |
--------------------------------------------------------------------------------
/dataset/Prob19p02_seq_pipe_delay_2stage_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement a two-stage pipelined channel where the input
10 | data is passed unchanged through two stages of pipeline registers. Here
11 | is an example execution trace. An X indicates that the output is
12 | undefined because there is no reset signal for the pipeline registers.
13 |
14 | cycle | in_ out
15 | -------+---------
16 | 0 | 00 XX
17 | 1 | 0a XX
18 | 2 | 0b 00
19 | 3 | 0c 0a
20 | 4 | 0d 0b
21 | 5 | 0e 0c
22 | 6 | 0f 0d
23 | 7 | 00 0e
24 | 8 | 00 0f
25 |
26 | Assume all sequential logic is triggered on the positive edge of the
27 | clock.
28 |
29 |
--------------------------------------------------------------------------------
/dataset/Prob19p03_seq_pipe_delay_3stage_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement a three-stage pipelined channel where the
10 | input data is passed unchanged through three stages of pipeline
11 | registers. Here is an example execution trace. An X indicates that the
12 | output is undefined because there is no reset signal for the pipeline
13 | registers.
14 |
15 | cycle | in_ out
16 | -------+---------
17 | 0 | 00 XX
18 | 1 | 0a XX
19 | 2 | 0b XX
20 | 3 | 0c 00
21 | 4 | 0d 0a
22 | 5 | 0e 0b
23 | 6 | 0f 0c
24 | 7 | 00 0d
25 | 8 | 00 0e
26 | 9 | 00 0f
27 |
28 | Assume all sequential logic is triggered on the positive edge of the
29 | clock.
30 |
31 |
--------------------------------------------------------------------------------
/dataset/Prob19p04_seq_pipe_add2_1stage_prompt.txt:
--------------------------------------------------------------------------------
1 |
2 | Implement a hardware module named TopModule with the following interface.
3 | All input and output ports are one bit unless otherwise specified.
4 |
5 | - input clk
6 | - input in0 (8 bits)
7 | - input in1 (8 bits)
8 | - output out (8 bits)
9 |
10 | The module should implement a one-stage pipelined two-input adder. All
11 | transactions should have a one cycle latency (i.e., inputs on cycle i
12 | will produce the corresponding sum on cycle i+1). Here is an example
13 | execution trace. An X indicates that the output is undefined because
14 | there is no reset signal for the pipeline registers.
15 |
16 | cycle | in0 in1 out
17 | -------+-------------
18 | 0 | 00 00 XX
19 | 1 | 01 01 00
20 | 2 | 02 03 02
21 | 3 | 03 04 05
22 | 4 | 00 00 07
23 |
24 | Assume all sequential logic is triggered on the positive edge of the
25 | clock.
26 |
27 |
--------------------------------------------------------------------------------
/examples/amaranth-ex1.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an incrementer which increments the input by
10 | one and writes the result to the output. Assume all values are encoded as
11 | two's complement binary numbers.
12 |
13 | Enclose your code with and
. Only output the code snippet
14 | and do NOT output anything else.
15 |
16 | Answer:
17 |
18 | from amaranth import *
19 |
20 | class TopModule( Elaboratable ):
21 |
22 | def __init__( s ):
23 |
24 | # Port-based interface
25 |
26 | s.in_ = Signal(8)
27 | s.out = Signal(8)
28 |
29 | def elaborate( s, platform ):
30 |
31 | # Create module
32 |
33 | m = Module()
34 |
35 | # Combinational logic
36 |
37 | m.d.comb += s.out.eq( s.in_ + 1 )
38 |
39 | # Return module
40 |
41 | return m
42 |
43 |
44 |
--------------------------------------------------------------------------------
/examples/migen-ex1.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an incrementer which increments the input by
10 | one and writes the result to the output. Assume all values are encoded as
11 | two's complement binary numbers.
12 |
13 | Enclose your code with and
. Only output the code snippet
14 | and do NOT output anything else.
15 |
16 | Answer:
17 |
18 | from migen import *
19 |
20 | class TopModule( Module ):
21 |
22 | def __init__( s ):
23 |
24 | # Port-based interface
25 |
26 | s.in_ = Signal(8)
27 | s.out = Signal(8)
28 |
29 | # Combinational logic
30 |
31 | s.comb += s.out.eq( s.in_ + 1 )
32 |
33 |
34 |
--------------------------------------------------------------------------------
/examples/myhdl-ex1.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an incrementer which increments the input by
10 | one and writes the result to the output. Assume all values are encoded as
11 | two's complement binary numbers.
12 |
13 | Enclose your code with and
. Only output the code snippet
14 | and do NOT output anything else.
15 |
16 | Answer:
17 |
18 | from myhdl import *
19 |
20 | @block
21 | def TopModule( in_, out ):
22 |
23 | # Combinational logic
24 |
25 | @always_comb
26 | def comb():
27 | out.next = in_ + 1
28 |
29 | return comb
30 |
31 |
32 |
--------------------------------------------------------------------------------
/examples/pymtl-ex1.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an incrementer which increments the input by
10 | one and writes the result to the output. Assume all values are encoded as
11 | two's complement binary numbers.
12 |
13 | Enclose your code with and
. Only output the code snippet
14 | and do NOT output anything else.
15 |
16 | Answer:
17 |
18 | from pymtl3 import *
19 |
20 | class TopModule( Component ):
21 |
22 | def construct( s ):
23 |
24 | # Port-based interface
25 |
26 | s.in_ = InPort (8)
27 | s.out = OutPort(8)
28 |
29 | # Combinational logic
30 |
31 | @update
32 | def up():
33 | s.out @= s.in_ + 1
34 |
35 |
36 |
--------------------------------------------------------------------------------
/examples/pyrtl-ex1.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an incrementer which increments the input by
10 | one and writes the result to the output. Assume all values are encoded as
11 | two's complement binary numbers.
12 |
13 | Enclose your code with and
. Only output the code snippet
14 | and do NOT output anything else.
15 |
16 | Answer:
17 |
18 | from pyrtl import *
19 |
20 | def TopModule( in_ ):
21 |
22 | # Declare outputs
23 |
24 | out = WireVector(8)
25 |
26 | # Combinational logic
27 |
28 | out <<= in_ + 1
29 |
30 | # Return outputs
31 |
32 | return out
33 |
34 |
35 |
--------------------------------------------------------------------------------
/examples/pyrtl-ex2.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input clk
7 | - input reset
8 | - input in_ (8 bits)
9 | - output out (8 bits)
10 |
11 | The module should implement an 8-bit registered incrementer with an
12 | active-high synchronous reset. The 8-bit input is first registered and
13 | then incremented by one on the next cycle. The internal state should be
14 | reset to zero when the reset input is one. Assume all values are encoded
15 | as two's complement binary numbers. Assume all sequential logic is
16 | triggered on the positive edge of the clock.
17 |
18 | Enclose your code with and
. Only output the code snippet
19 | and do NOT output anything else.
20 |
21 | Answer:
22 |
23 | from pyrtl import *
24 |
25 | def TopModule( in_ ):
26 |
27 | # Declare outputs
28 |
29 | out = WireVector(8)
30 |
31 | # Sequential logic
32 |
33 | reg_out = Register( 8, reset_value=0 )
34 | reg_out.next <<= in_
35 |
36 | # Combinational logic
37 |
38 | temp_wire = WireVector(8)
39 | temp_wire <<= reg_out + 1
40 |
41 | # Structural connections
42 |
43 | out <<= temp_wire
44 |
45 | # Return outputs
46 |
47 | return out
48 |
49 |
50 |
--------------------------------------------------------------------------------
/examples/verilog-ex1.txt:
--------------------------------------------------------------------------------
1 |
2 | Question:
3 | Implement a hardware module named TopModule with the following interface.
4 | All input and output ports are one bit unless otherwise specified.
5 |
6 | - input in_ (8 bits)
7 | - output out (8 bits)
8 |
9 | The module should implement an incrementer which increments the input by
10 | one and writes the result to the output. Assume all values are encoded as
11 | two's complement binary numbers.
12 |
13 | Enclose your code with and
. Only output the code snippet
14 | and do NOT output anything else.
15 |
16 | Answer:
17 |
18 | module TopModule
19 | (
20 | input logic [7:0] in_,
21 | output logic [7:0] out
22 | );
23 |
24 | // Combinational logic
25 |
26 | assign out = in_ + 1;
27 |
28 | endmodule
29 |
30 |
31 |
--------------------------------------------------------------------------------
/pyhdl_eval/__init__.py:
--------------------------------------------------------------------------------
1 |
2 |
--------------------------------------------------------------------------------
/pyhdl_eval/cfg.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pyhdl_eval.cfg
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 | #
8 |
9 | from dataclasses import dataclass, field
10 | from enum import Enum
11 |
12 | # Interface Configuration
13 |
14 | class Port():
15 | pass
16 |
17 | class InputPort(Port):
18 | def __init__( s, nbits ):
19 | s._nbits = nbits
20 | def nbits( s ):
21 | return s._nbits
22 |
23 | class OutputPort(Port):
24 | def __init__( s, nbits ):
25 | s._nbits = nbits
26 | def nbits( s ):
27 | return s._nbits
28 |
29 | # Trace Configuration
30 |
31 | class TraceFormat(Enum):
32 | HEX = 1
33 | BIN = 2
34 | INT = 3
35 | UINT = 4
36 |
37 | # Config Dataclass
38 |
39 | @dataclass
40 | class Config:
41 | parameters : list[ tuple[str,int] ] = field(default_factory=dict)
42 | ports : list[ tuple[str,Port] ] = field(default_factory=list)
43 | trace_format : TraceFormat = TraceFormat.HEX
44 | dead_cycles : int = 0
45 | dead_cycle_inputs : int = None
46 |
47 |
--------------------------------------------------------------------------------
/pyhdl_eval/strategies.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pyhdl_eval.stragegies
3 | #=========================================================================
4 | # Hypothesis strategies for random testing.
5 | #
6 | # SPDX-License-Identifier: MIT
7 | # Author : Christopher Batten, NVIDIA
8 | # Date : May 20, 2024
9 |
10 | from hypothesis import strategies as st
11 | from pyhdl_eval.bits import Bits
12 |
13 | #-------------------------------------------------------------------------
14 | # bits
15 | #-------------------------------------------------------------------------
16 | # Return a Hypothesis search stategy for Bits
17 |
18 | @st.composite
19 | def bits( draw, nbits, min_value=None, max_value=None ):
20 |
21 | if min_value == None:
22 | min_value = 0
23 | if max_value == None:
24 | max_value = 2**nbits-1
25 |
26 | if nbits == 1:
27 | return Bits( nbits, draw( st.booleans() ) )
28 | else:
29 | return Bits( nbits, draw( st.integers(min_value,max_value) ) )
30 |
31 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_amaranth.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # incr_amaranth
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from amaranth import *
9 |
10 | class TopModule( Elaboratable ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = Signal(8)
17 | s.out = Signal(8)
18 |
19 | def elaborate( s, platform ):
20 |
21 | # Create module
22 |
23 | m = Module()
24 |
25 | # Combinational logic
26 |
27 | m.d.comb += s.out.eq( s.in_ + 1 )
28 |
29 | # Return module
30 |
31 | return m
32 |
33 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_migen.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # incr_migen
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from migen import *
9 |
10 | class TopModule( Module ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = Signal(8)
17 | s.out = Signal(8)
18 |
19 | # Combinational logic
20 |
21 | s.comb += s.out.eq( s.in_ + 1 )
22 |
23 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_myhdl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # comb_incr_myhdl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from myhdl import *
9 |
10 | @block
11 | def TopModule( in_, out ):
12 |
13 | # Combinational logic
14 |
15 | @always_comb
16 | def comb():
17 | out.next = in_ + 1
18 |
19 | return comb
20 |
21 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_pymtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # comb_incr_pymtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pymtl3 import *
9 |
10 | class TopModule( Component ):
11 |
12 | def construct( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = InPort ( Bits8 )
17 | s.out = OutPort( Bits8 )
18 |
19 | # Combinational logic
20 |
21 | @update
22 | def comb():
23 | s.out @= s.in_ + 1
24 |
25 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_pyrtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # comb_incr_pyrtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyrtl import *
9 |
10 | def TopModule( in_ ):
11 |
12 | # Declare outputs
13 |
14 | out = WireVector(8)
15 |
16 | # Combinational logic
17 |
18 | out <<= in_ + 1
19 |
20 | # Return outputs
21 |
22 | return out
23 |
24 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_ref.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // comb_incr_ref
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module RefModule
9 | (
10 | input logic [7:0] in_,
11 | output logic [7:0] out
12 | );
13 |
14 | assign out = in_ + 1;
15 |
16 | endmodule
17 |
18 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/comb_incr_verilog.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // comb_incr_verilog
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module TopModule
9 | (
10 | input logic [7:0] in_,
11 | output logic [7:0] out
12 | );
13 |
14 | assign out = in_ + 1;
15 |
16 | endmodule
17 |
18 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_amaranth.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # const_amaranth
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from amaranth import *
9 |
10 | class TopModule( Elaboratable ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.out = Signal(8)
17 |
18 | def elaborate( s, platform ):
19 |
20 | # Create module
21 |
22 | m = Module()
23 |
24 | # Combinational logic
25 |
26 | m.d.comb += s.out.eq( 1 )
27 |
28 | # Return module
29 |
30 | return m
31 |
32 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_migen.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # const_migen
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from migen import *
9 |
10 | class TopModule( Module ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.out = Signal(8)
17 |
18 | # Combinational logic
19 |
20 | s.comb += s.out.eq( 1 )
21 |
22 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_myhdl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # const_myhdl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from myhdl import *
9 |
10 | @block
11 | def TopModule( out ):
12 |
13 | # Combinational logic
14 |
15 | const_value = Signal(1)
16 |
17 | @always_comb
18 | def logic():
19 | out.next = const_value
20 |
21 | return logic
22 |
23 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_pymtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # const_pymtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pymtl3 import *
9 |
10 | class TopModule( Component ):
11 |
12 | def construct( s ):
13 |
14 | # Port-based interface
15 |
16 | s.out = OutPort( Bits8 )
17 |
18 | # Connect to constant
19 |
20 | connect( s.out, 1 )
21 |
22 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_pyrtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # const_pyrtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyrtl import *
9 |
10 | def TopModule():
11 |
12 | # Declare outputs
13 |
14 | out = WireVector(8)
15 |
16 | # Combinational logic
17 |
18 | out <<= 1
19 |
20 | # Return outputs
21 |
22 | return out
23 |
24 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_ref.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // const_ref
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module RefModule
9 | (
10 | output logic [7:0] out
11 | );
12 |
13 | assign out = 1;
14 |
15 | endmodule
16 |
17 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_test.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # const_test
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | import pytest
9 |
10 | from pyhdl_eval.cfg import Config, OutputPort
11 | from pyhdl_eval.core import run_sim, dsls
12 |
13 | #-------------------------------------------------------------------------
14 | # Configuration
15 | #-------------------------------------------------------------------------
16 |
17 | config = Config(
18 | ports = [
19 | ( "out", OutputPort(8) ),
20 | ],
21 | )
22 |
23 | #-------------------------------------------------------------------------
24 | # test_case_small
25 | #-------------------------------------------------------------------------
26 |
27 | @pytest.mark.parametrize( "dslstr", dsls.keys() )
28 | def test_case_small( dslstr ):
29 | run_sim( dslstr, __file__, config )
30 |
31 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/const_verilog.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // const_verilog
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module TopModule
9 | (
10 | output logic [7:0] out
11 | );
12 |
13 | assign out = 1;
14 |
15 | endmodule
16 |
17 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_amaranth.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # count_incr_amaranth
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from amaranth import *
9 |
10 | class TopModule( Elaboratable ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.en = Signal()
17 | s.ld = Signal()
18 | s.in_ = Signal(8)
19 | s.out = Signal(8)
20 |
21 | def elaborate( s, platform ):
22 |
23 | # Create module
24 |
25 | m = Module()
26 |
27 | # Sequential logic
28 |
29 | reg_next = Signal( 8 )
30 | reg_out = Signal( 8 )
31 |
32 | with m.If( s.ld ):
33 | m.d.sync += reg_out.eq( s.in_ )
34 | with m.Elif( s.en ):
35 | m.d.sync += reg_out.eq( reg_next )
36 |
37 | # Combinational logic
38 |
39 | m.d.comb += reg_next.eq( reg_out + 1 )
40 |
41 | # Structural connections
42 |
43 | m.d.comb += s.out.eq( reg_out )
44 |
45 | # Return module
46 |
47 | return m
48 |
49 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_migen.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # count_incr_migen
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from migen import *
9 |
10 | class TopModule( Module ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.en = Signal()
17 | s.ld = Signal()
18 | s.in_ = Signal(8)
19 | s.out = Signal(8)
20 |
21 | # Sequential logic
22 |
23 | reg_next = Signal( 8 )
24 | reg_out = Signal( 8 )
25 |
26 | s.sync += \
27 | If ( s.ld, reg_out.eq( s.in_ ) ). \
28 | Elif( s.en, reg_out.eq( reg_next ) )
29 |
30 | # Combinational logic
31 |
32 | s.comb += reg_next.eq( reg_out + 1 )
33 |
34 | # Structural connections
35 |
36 | s.comb += s.out.eq( reg_out )
37 |
38 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_myhdl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # count_incr_myhdl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from myhdl import *
9 |
10 | @block
11 | def TopModule( clk, en, ld, in_, out ):
12 |
13 | # Sequential logic
14 |
15 | reg_next = Signal( modbv(0)[8:] )
16 | reg_out = Signal( modbv(0)[8:] )
17 |
18 | @always( clk.posedge )
19 | def seq():
20 | if ld:
21 | reg_out.next = in_
22 | elif en:
23 | reg_out.next = reg_next
24 |
25 | # Combinational logic
26 |
27 | @always_comb
28 | def comb0():
29 | reg_next.next = reg_out + 1
30 |
31 | # Structural connections
32 |
33 | @always_comb
34 | def comb1():
35 | out.next = reg_out
36 |
37 | # Return blocks
38 |
39 | return seq, comb0, comb1
40 |
41 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_pymtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # count_incr_pymtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pymtl3 import *
9 |
10 | class TopModule( Component ):
11 |
12 | def construct( s ):
13 |
14 | # Port-based interface
15 |
16 | s.en = InPort ()
17 | s.ld = InPort ()
18 | s.in_ = InPort ( Bits8 )
19 | s.out = OutPort( Bits8 )
20 |
21 | # Sequential logic
22 |
23 | s.reg_next = Wire( Bits8 )
24 | s.reg_out = Wire( Bits8 )
25 |
26 | @update_ff
27 | def seq():
28 | if s.ld:
29 | s.reg_out <<= s.in_
30 | elif s.en:
31 | s.reg_out <<= s.reg_next
32 |
33 | # Combinational logic
34 |
35 | @update
36 | def comb():
37 | s.reg_next @= s.reg_out + 1
38 |
39 | # Structural connections
40 |
41 | s.out //= s.reg_out
42 |
43 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_pyrtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # count_incr_pyrtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyrtl import *
9 |
10 | def TopModule( en, ld, in_ ):
11 |
12 | # Declare outputs
13 |
14 | out = WireVector(8)
15 |
16 | # Sequential logic
17 |
18 | reg_next = WireVector(8)
19 | reg_out = Register(8)
20 |
21 | with conditional_assignment:
22 | with ld:
23 | reg_out.next |= in_
24 | with en:
25 | reg_out.next |= reg_next
26 |
27 | # Combinational logic
28 |
29 | reg_next <<= reg_out + 1
30 |
31 | # Structural connections
32 |
33 | out <<= reg_out
34 |
35 | # Return outputs
36 |
37 | return out
38 |
39 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_ref.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // count_incr_ref
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module RefModule
9 | (
10 | input logic clk,
11 | input logic ld,
12 | input logic en,
13 | input logic [7:0] in_,
14 | output logic [7:0] out
15 | );
16 |
17 | // Sequential logic
18 |
19 | logic [7:0] reg_next;
20 | logic [7:0] reg_out;
21 |
22 | always @( posedge clk ) begin
23 | if ( ld )
24 | reg_out <= in_;
25 | else if ( en )
26 | reg_out <= reg_next;
27 | end
28 |
29 | // Combinational logic
30 |
31 | always @(*) begin
32 | reg_next = reg_out + 1;
33 | end
34 |
35 | // Structural connections
36 |
37 | assign out = reg_out;
38 |
39 | endmodule
40 |
41 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/count_incr_verilog.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // count_incr_verilog
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module TopModule
9 | (
10 | input logic clk,
11 | input logic en,
12 | input logic ld,
13 | input logic [7:0] in_,
14 | output logic [7:0] out
15 | );
16 |
17 | // Sequential logic
18 |
19 | logic [7:0] reg_next;
20 | logic [7:0] reg_out;
21 |
22 | always @( posedge clk ) begin
23 | if ( ld )
24 | reg_out <= in_;
25 | else if ( en )
26 | reg_out <= reg_next;
27 | end
28 |
29 | // Combinational logic
30 |
31 | always @(*) begin
32 | reg_next = reg_out + 1;
33 | end
34 |
35 | // Structural connections
36 |
37 | assign out = reg_out;
38 |
39 | endmodule
40 |
41 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_amaranth.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # param_incr_amaranth
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from amaranth import *
9 |
10 | class TopModule( Elaboratable ):
11 |
12 | def __init__( s, nbits ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = Signal( nbits )
17 | s.out = Signal( nbits )
18 |
19 | # Save parameters
20 |
21 | s.nbits = nbits
22 |
23 | def elaborate( s, platform ):
24 |
25 | # Create module
26 |
27 | m = Module()
28 |
29 | # Sequential logic
30 |
31 | reg_out = Signal( s.nbits, reset=0 )
32 |
33 | m.d.sync += reg_out.eq( s.in_ )
34 |
35 | # Combinational logic
36 |
37 | temp_wire = Signal( s.nbits )
38 |
39 | m.d.comb += temp_wire.eq( reg_out + 1 )
40 |
41 | # Structural connections
42 |
43 | m.d.comb += s.out.eq( temp_wire )
44 |
45 | # Return module
46 |
47 | return m
48 |
49 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_migen.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # param_incr_migen
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from migen import *
9 |
10 | @ResetInserter()
11 | class TopModule( Module ):
12 |
13 | def __init__( s, nbits ):
14 |
15 | # Port-based interface
16 |
17 | s.in_ = Signal( nbits )
18 | s.out = Signal( nbits )
19 |
20 | # Sequential logic
21 |
22 | reg_out = Signal( nbits, reset=0 )
23 |
24 | s.sync += reg_out.eq( s.in_ )
25 |
26 | # Combinational logic
27 |
28 | temp_wire = Signal( nbits )
29 |
30 | s.comb += temp_wire.eq( reg_out + 1 )
31 |
32 | # Structural connections
33 |
34 | s.comb += s.out.eq( temp_wire )
35 |
36 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_myhdl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # param_incr_myhdl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from myhdl import *
9 |
10 | @block
11 | def TopModule( clk, reset, in_, out, nbits ):
12 |
13 | # Sequential logic
14 |
15 | reg_out = Signal( modbv(0)[nbits:] )
16 |
17 | @always( clk.posedge )
18 | def seq():
19 | if reset:
20 | reg_out.next = 0
21 | else:
22 | reg_out.next = in_
23 |
24 | # Combinational logic
25 |
26 | temp_wire = Signal( modbv(0)[nbits:] )
27 |
28 | @always_comb
29 | def comb0():
30 | temp_wire.next = reg_out + 1
31 |
32 | # Structural connections
33 |
34 | @always_comb
35 | def comb1():
36 | out.next = temp_wire
37 |
38 | # Return blocks
39 |
40 | return seq, comb0, comb1
41 |
42 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_pymtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # param_incr_pymtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pymtl3 import *
9 |
10 | class TopModule( Component ):
11 |
12 | def construct( s, nbits ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = InPort ( nbits )
17 | s.out = OutPort( nbits )
18 |
19 | # Sequential logic
20 |
21 | s.reg_out = Wire( nbits )
22 |
23 | @update_ff
24 | def block1():
25 | if s.reset:
26 | s.reg_out <<= 0
27 | else:
28 | s.reg_out <<= s.in_
29 |
30 | # Combinational logic
31 |
32 | s.temp_wire = Wire( nbits )
33 |
34 | @update
35 | def block2():
36 | s.temp_wire @= s.reg_out + 1
37 |
38 | # Structural connections
39 |
40 | s.out //= s.temp_wire
41 |
42 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_pyrtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # param_incr_pyrtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyrtl import *
9 |
10 | def TopModule( in_, nbits ):
11 |
12 | # Declare outputs
13 |
14 | out = WireVector( nbits )
15 |
16 | # Sequential logic
17 |
18 | reg_out = Register( nbits, reset_value=0 )
19 | reg_out.next <<= in_
20 |
21 | # Combinational logic
22 |
23 | temp_wire = WireVector( nbits )
24 | temp_wire <<= reg_out + 1
25 |
26 | # Structural connections
27 |
28 | out <<= temp_wire
29 |
30 | # Return outputs
31 |
32 | return out
33 |
34 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_ref.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // param_incr_ref
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module RefModule
9 | #(
10 | parameter nbits
11 | )(
12 | input logic clk,
13 | input logic reset,
14 | input logic [nbits-1:0] in_,
15 | output logic [nbits-1:0] out
16 | );
17 |
18 | // Sequential logic
19 |
20 | logic [nbits-1:0] reg_out;
21 |
22 | always @( posedge clk ) begin
23 | if ( reset )
24 | reg_out <= 0;
25 | else
26 | reg_out <= in_;
27 | end
28 |
29 | // Combinational logic
30 |
31 | logic [nbits-1:0] temp_wire;
32 |
33 | always @(*) begin
34 | temp_wire = reg_out + 1;
35 | end
36 |
37 | // Structural connections
38 |
39 | assign out = temp_wire;
40 |
41 | endmodule
42 |
43 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/param_incr_verilog.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // param_incr_verilog
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module TopModule
9 | #(
10 | parameter nbits
11 | )(
12 | input logic clk,
13 | input logic reset,
14 | input logic [nbits-1:0] in_,
15 | output logic [nbits-1:0] out
16 | );
17 |
18 | // Sequential logic
19 |
20 | logic [nbits-1:0] reg_out;
21 |
22 | always @( posedge clk ) begin
23 | if ( reset )
24 | reg_out <= 0;
25 | else
26 | reg_out <= in_;
27 | end
28 |
29 | // Combinational logic
30 |
31 | logic [nbits-1:0] temp_wire;
32 |
33 | always @(*) begin
34 | temp_wire = reg_out + 1;
35 | end
36 |
37 | // Structural connections
38 |
39 | assign out = temp_wire;
40 |
41 | endmodule
42 |
43 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_amaranth.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pipe_incr_amaranth
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from amaranth import *
9 |
10 | class TopModule( Elaboratable ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in0 = Signal(8)
17 | s.in1 = Signal(8)
18 | s.out = Signal(8)
19 |
20 | def elaborate( s, platform ):
21 |
22 | # Create module
23 |
24 | m = Module()
25 |
26 | # Stage 0
27 |
28 | in0_X0 = Signal( 8 )
29 | in1_X0 = Signal( 8 )
30 |
31 | m.d.sync += [
32 | in0_X0.eq( s.in0 ),
33 | in1_X0.eq( s.in1 ),
34 | ]
35 |
36 | incr0_X0 = Signal( 8 )
37 | incr1_X0 = Signal( 8 )
38 |
39 | m.d.comb += [
40 | incr0_X0.eq( in0_X0 + 1 ),
41 | incr1_X0.eq( in1_X0 + 1 ),
42 | ]
43 |
44 | # Stage 1
45 |
46 | incr0_X1 = Signal( 8 )
47 | incr1_X1 = Signal( 8 )
48 |
49 | m.d.sync += [
50 | incr0_X1.eq( incr0_X0 ),
51 | incr1_X1.eq( incr1_X0 ),
52 | ]
53 |
54 | m.d.comb += [
55 | s.out.eq( incr0_X1 + incr1_X1 ),
56 | ]
57 |
58 | # Return module
59 |
60 | return m
61 |
62 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_migen.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pipe_incr_migen
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from migen import *
9 |
10 | class TopModule( Module ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in0 = Signal(8)
17 | s.in1 = Signal(8)
18 | s.out = Signal(8)
19 |
20 | # Stage 0
21 |
22 | in0_X0 = Signal( 8 )
23 | in1_X0 = Signal( 8 )
24 |
25 | s.sync += [
26 | in0_X0.eq( s.in0 ),
27 | in1_X0.eq( s.in1 ),
28 | ]
29 |
30 | incr0_X0 = Signal( 8 )
31 | incr1_X0 = Signal( 8 )
32 |
33 | s.comb += [
34 | incr0_X0.eq( in0_X0 + 1 ),
35 | incr1_X0.eq( in1_X0 + 1 ),
36 | ]
37 |
38 | # Stage 1
39 |
40 | incr0_X1 = Signal( 8 )
41 | incr1_X1 = Signal( 8 )
42 |
43 | s.sync += [
44 | incr0_X1.eq( incr0_X0 ),
45 | incr1_X1.eq( incr1_X0 ),
46 | ]
47 |
48 | s.comb += [
49 | s.out.eq( incr0_X1 + incr1_X1 ),
50 | ]
51 |
52 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_myhdl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pipe_incr_myhdl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from myhdl import *
9 |
10 | @block
11 | def TopModule( clk, in0, in1, out ):
12 |
13 | # Stage 0
14 |
15 | in0_X0 = Signal( modbv(0)[8:] )
16 | in1_X0 = Signal( modbv(0)[8:] )
17 |
18 | @always( clk.posedge )
19 | def stage0_seq():
20 | in0_X0.next = in0
21 | in1_X0.next = in1
22 |
23 | incr0_X0 = Signal( modbv(0)[8:] )
24 | incr1_X0 = Signal( modbv(0)[8:] )
25 |
26 | @always_comb
27 | def stage0_comb():
28 | incr0_X0.next = in0_X0 + 1
29 | incr1_X0.next = in1_X0 + 1
30 |
31 | # Stage 0
32 |
33 | incr0_X1 = Signal( modbv(0)[8:] )
34 | incr1_X1 = Signal( modbv(0)[8:] )
35 |
36 | @always( clk.posedge )
37 | def stage1_seq():
38 | incr0_X1.next = incr0_X0
39 | incr1_X1.next = incr1_X0
40 |
41 | @always_comb
42 | def stage1_comb():
43 | out.next = incr0_X1 + incr1_X1
44 |
45 | return stage0_seq, stage0_comb, stage1_seq, stage1_comb
46 |
47 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_pymtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pipe_incr_pymtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pymtl3 import *
9 |
10 | class TopModule( Component ):
11 |
12 | def construct( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in0 = InPort ( Bits8 )
17 | s.in1 = InPort ( Bits8 )
18 | s.out = OutPort( Bits8 )
19 |
20 | # Stage 0
21 |
22 | s.in0_X0 = Wire( Bits8 )
23 | s.in1_X0 = Wire( Bits8 )
24 |
25 | @update_ff
26 | def stage0_pipe():
27 | s.in0_X0 <<= s.in0
28 | s.in1_X0 <<= s.in1
29 |
30 | s.incr0_X0 = Wire( Bits8 )
31 | s.incr1_X0 = Wire( Bits8 )
32 |
33 | @update
34 | def stage0_comb():
35 | s.incr0_X0 @= s.in0_X0 + 1
36 | s.incr1_X0 @= s.in1_X0 + 1
37 |
38 | # Stage 1
39 |
40 | s.incr0_X1 = Wire( Bits8 )
41 | s.incr1_X1 = Wire( Bits8 )
42 |
43 | @update_ff
44 | def stage1_pipe():
45 | s.incr0_X1 <<= s.incr0_X0
46 | s.incr1_X1 <<= s.incr1_X0
47 |
48 | @update
49 | def stage1_comb():
50 | s.out @= s.incr0_X1 + s.incr1_X1
51 |
52 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_pyrtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pipe_incr_pyrtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyrtl import *
9 |
10 | def TopModule( in0, in1 ):
11 |
12 | # Declare outputs
13 |
14 | out = WireVector(8)
15 |
16 | # Stage 0
17 |
18 | in0_X0 = Register( 8 )
19 | in1_X0 = Register( 8 )
20 |
21 | in0_X0.next <<= in0
22 | in1_X0.next <<= in1
23 |
24 | incr0_X0 = WireVector(8)
25 | incr1_X0 = WireVector(8)
26 |
27 | incr0_X0 <<= in0_X0 + 1
28 | incr1_X0 <<= in1_X0 + 1
29 |
30 | # Stage 1
31 |
32 | incr0_X1 = Register( 8 )
33 | incr1_X1 = Register( 8 )
34 |
35 | incr0_X1.next <<= incr0_X0
36 | incr1_X1.next <<= incr1_X0
37 |
38 | out <<= incr0_X1 + incr1_X1
39 |
40 | # Return outputs
41 |
42 | return out
43 |
44 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_ref.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // pipe_incr_ref
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module RefModule
9 | (
10 | input logic clk,
11 | input logic [7:0] in0,
12 | input logic [7:0] in1,
13 | output logic [7:0] out
14 | );
15 |
16 | // Stage 0
17 |
18 | logic [7:0] in0_X0;
19 | logic [7:0] in1_X0;
20 |
21 | always @( posedge clk ) begin
22 | in0_X0 <= in0;
23 | in1_X0 <= in1;
24 | end
25 |
26 | logic [7:0] incr0_X0;
27 | logic [7:0] incr1_X0;
28 |
29 | assign incr0_X0 = in0_X0 + 1;
30 | assign incr1_X0 = in1_X0 + 1;
31 |
32 | // Stage 1
33 |
34 | logic [7:0] incr0_X1;
35 | logic [7:0] incr1_X1;
36 |
37 | always @( posedge clk ) begin
38 | incr0_X1 <= incr0_X0;
39 | incr1_X1 <= incr1_X0;
40 | end
41 |
42 | assign out = incr0_X1 + incr1_X1;
43 |
44 | endmodule
45 |
46 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/pipe_incr_verilog.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // pipe_incr_verilog
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module TopModule
9 | (
10 | input logic clk,
11 | input logic [7:0] in0,
12 | input logic [7:0] in1,
13 | output logic [7:0] out
14 | );
15 |
16 | // Stage 0
17 |
18 | logic [7:0] in0_X0;
19 | logic [7:0] in1_X0;
20 |
21 | always @( posedge clk ) begin
22 | in0_X0 <= in0;
23 | in1_X0 <= in1;
24 | end
25 |
26 | logic [7:0] incr0_X0;
27 | logic [7:0] incr1_X0;
28 |
29 | assign incr0_X0 = in0_X0 + 1;
30 | assign incr1_X0 = in1_X0 + 1;
31 |
32 | // Stage 1
33 |
34 | logic [7:0] incr0_X1;
35 | logic [7:0] incr1_X1;
36 |
37 | always @( posedge clk ) begin
38 | incr0_X1 <= incr0_X0;
39 | incr1_X1 <= incr1_X0;
40 | end
41 |
42 | assign out = incr0_X1 + incr1_X1;
43 |
44 | endmodule
45 |
46 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_amaranth.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # reg_incr_amaranth
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from amaranth import *
9 |
10 | class TopModule( Elaboratable ):
11 |
12 | def __init__( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = Signal(8)
17 | s.out = Signal(8)
18 |
19 | def elaborate( s, platform ):
20 |
21 | # Create module
22 |
23 | m = Module()
24 |
25 | # Sequential logic
26 |
27 | reg_out = Signal( 8, reset=0 )
28 |
29 | m.d.sync += reg_out.eq( s.in_ )
30 |
31 | # Combinational logic
32 |
33 | temp_wire = Signal(8)
34 |
35 | m.d.comb += temp_wire.eq( reg_out + 1 )
36 |
37 | # Structural connections
38 |
39 | m.d.comb += s.out.eq( temp_wire )
40 |
41 | # Return module
42 |
43 | return m
44 |
45 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_migen.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # reg_incr_migen
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from migen import *
9 |
10 | @ResetInserter()
11 | class TopModule( Module ):
12 |
13 | def __init__( s ):
14 |
15 | # Port-based interface
16 |
17 | s.in_ = Signal(8)
18 | s.out = Signal(8)
19 |
20 | # Sequential logic
21 |
22 | reg_out = Signal( 8, reset=0 )
23 |
24 | s.sync += reg_out.eq( s.in_ )
25 |
26 | # Combinational logic
27 |
28 | temp_wire = Signal(8)
29 |
30 | s.comb += temp_wire.eq( reg_out + 1 )
31 |
32 | # Structural connections
33 |
34 | s.comb += s.out.eq( temp_wire )
35 |
36 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_myhdl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # reg_incr_myhdl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from myhdl import *
9 |
10 | @block
11 | def TopModule( clk, reset, in_, out ):
12 |
13 | # Sequential logic
14 |
15 | reg_out = Signal( modbv(0)[8:] )
16 |
17 | @always( clk.posedge )
18 | def seq():
19 | if reset:
20 | reg_out.next = 0
21 | else:
22 | reg_out.next = in_
23 |
24 | # Combinational logic
25 |
26 | temp_wire = Signal( modbv(0)[8:] )
27 |
28 | @always_comb
29 | def comb0():
30 | temp_wire.next = reg_out + 1
31 |
32 | # Structural connections
33 |
34 | @always_comb
35 | def comb1():
36 | out.next = temp_wire
37 |
38 | # Return blocks
39 |
40 | return seq, comb0, comb1
41 |
42 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_pymtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # reg_incr_pymtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pymtl3 import *
9 |
10 | class TopModule( Component ):
11 |
12 | def construct( s ):
13 |
14 | # Port-based interface
15 |
16 | s.in_ = InPort ( Bits8 )
17 | s.out = OutPort( Bits8 )
18 |
19 | # Sequential logic
20 |
21 | s.reg_out = Wire( Bits8 )
22 |
23 | @update_ff
24 | def seq():
25 | if s.reset:
26 | s.reg_out <<= 0
27 | else:
28 | s.reg_out <<= s.in_
29 |
30 | # Combinational logic
31 |
32 | s.temp_wire = Wire( Bits8 )
33 |
34 | @update
35 | def comb():
36 | s.temp_wire @= s.reg_out + 1
37 |
38 | # Structural connections
39 |
40 | s.out //= s.temp_wire
41 |
42 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_pyrtl.py:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # reg_incr_pyrtl
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | from pyrtl import *
9 |
10 | def TopModule( in_ ):
11 |
12 | # Declare outputs
13 |
14 | out = WireVector(8)
15 |
16 | # Sequential logic
17 |
18 | reg_out = Register( 8, reset_value=0 )
19 | reg_out.next <<= in_
20 |
21 | # Combinational logic
22 |
23 | temp_wire = WireVector(8)
24 | temp_wire <<= reg_out + 1
25 |
26 | # Structural connections
27 |
28 | out <<= temp_wire
29 |
30 | # Return outputs
31 |
32 | return out
33 |
34 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_ref.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // reg_incr_ref
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module RefModule
9 | (
10 | input logic clk,
11 | input logic reset,
12 | input logic [7:0] in_,
13 | output logic [7:0] out
14 | );
15 |
16 | // Sequential logic
17 |
18 | logic [7:0] reg_out;
19 |
20 | always @( posedge clk ) begin
21 | if ( reset )
22 | reg_out <= 0;
23 | else
24 | reg_out <= in_;
25 | end
26 |
27 | // Combinational logic
28 |
29 | logic [7:0] temp_wire;
30 |
31 | always @(*) begin
32 | temp_wire = reg_out + 1;
33 | end
34 |
35 | // Structural connections
36 |
37 | assign out = temp_wire;
38 |
39 | endmodule
40 |
41 |
--------------------------------------------------------------------------------
/pyhdl_eval/test/reg_incr_verilog.v:
--------------------------------------------------------------------------------
1 | //========================================================================
2 | // reg_incr_verilog
3 | //========================================================================
4 | // SPDX-License-Identifier: MIT
5 | // Author : Christopher Batten, NVIDIA
6 | // Date : May 20, 2024
7 |
8 | module TopModule
9 | (
10 | input logic clk,
11 | input logic reset,
12 | input logic [7:0] in_,
13 | output logic [7:0] out
14 | );
15 |
16 | // Sequential logic
17 |
18 | logic [7:0] reg_out;
19 |
20 | always @( posedge clk ) begin
21 | if ( reset )
22 | reg_out <= 0;
23 | else
24 | reg_out <= in_;
25 | end
26 |
27 | // Combinational logic
28 |
29 | logic [7:0] temp_wire;
30 |
31 | always @(*) begin
32 | temp_wire = reg_out + 1;
33 | end
34 |
35 | // Structural connections
36 |
37 | assign out = temp_wire;
38 |
39 | endmodule
40 |
41 |
--------------------------------------------------------------------------------
/pytest.ini:
--------------------------------------------------------------------------------
1 | #=========================================================================
2 | # pytest.ini
3 | #=========================================================================
4 | # SPDX-License-Identifier: MIT
5 | # Author : Christopher Batten, NVIDIA
6 | # Date : May 20, 2024
7 |
8 | [pytest]
9 |
10 | #-------------------------------------------------------------------------
11 | # default commandline arguments
12 | #-------------------------------------------------------------------------
13 | # By default do not show any traceback. This means by deafult py.test
14 | # gives an overview of the results but not any details. Users can use
15 | # --tb=long to get more information on a failing test. We also display
16 | # error/warnings at the end; otherwise syntax errors won't really show
17 | # up.
18 |
19 | addopts = --tb=no -r Ew
20 |
21 |
--------------------------------------------------------------------------------