├── .gitattributes ├── .github └── workflows │ ├── docs.yml │ └── rust.yml ├── .gitignore ├── .vscode └── settings.json ├── Cargo.lock ├── Cargo.toml ├── LICENSE ├── README.md ├── bin ├── eqmap ├── eqmap_vivado ├── fam ├── lvv ├── lvv-vivado ├── msynth ├── opt-verilog └── resynth ├── clippy.toml ├── src ├── analysis.rs ├── asic.rs ├── bin │ ├── emit-verilog.rs │ ├── eqmap_asic.rs │ ├── eqmap_fpga.rs │ ├── opt.rs │ ├── optcell.rs │ └── parse-verilog.rs ├── check.rs ├── cost.rs ├── driver.rs ├── lib.rs ├── logic.rs ├── lut.rs ├── netlist.rs ├── rewrite.rs ├── serialize.rs └── verilog.rs ├── tests ├── asic │ ├── cla.txt │ ├── cla.v │ └── filter.v ├── disassemble │ ├── full_adder.v │ └── mux_l4.v ├── driver │ ├── add_synth.v │ ├── big_decimal.v │ ├── gate_test.v │ ├── mk_rpt.v │ ├── mux_reg.v │ └── unused_input.v ├── emitter │ ├── comparator.txt │ ├── idempotent.txt │ ├── mux_4_1.txt │ └── parity_checker.txt ├── lutlang │ ├── bus.txt │ ├── examples.txt │ ├── gate_compare.txt │ ├── hard_examples.txt │ ├── invariance.txt │ ├── invariance_no_greedy.txt │ └── proofs.txt ├── reg │ ├── cycles.txt │ └── mux_retime.txt └── verilog │ ├── add_synth.v │ ├── big_decimal.v │ ├── fdre.v │ ├── fdre_roundtrip.v │ ├── gate_test.v │ ├── gnd.v │ ├── mux_4_1_k3.v │ ├── mux_4_1_synth.v │ ├── mux_decimal.v │ ├── mux_reg.v │ ├── muxf.v │ ├── roundtrip.v │ ├── top_5xp1_y0_synth.v │ ├── top_5xp1_y1_synth.v │ └── two_outputs.v ├── utils ├── append.py ├── cat.py ├── min-coverage.py ├── paths.py ├── recordTime.sh ├── runTests.sh ├── setup.sh ├── setup.zsh └── test-runner.py └── verilog ├── Makefile ├── README.md ├── celllang.v ├── check-cells.sh ├── equiv.sh ├── lutlang.v ├── multPipe_n4.v ├── mux_4_1 ├── Makefile ├── mux_2_1.v └── mux_4_1.v ├── simlib.v └── stdcells.v /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cornell-zhang/eqmap/HEAD/.gitattributes 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