├── LICENSE ├── README.md ├── handlers ├── cortexm.cpp ├── stack.cpp └── stm32 │ └── f0.cpp ├── ld ├── _common │ ├── flash.ld │ └── sram.ld └── stm32 │ └── f0 │ ├── 3xx4.ld │ ├── 3xx6.ld │ ├── 3xx8.ld │ ├── 3xxc.ld │ ├── 4xx4.ld │ ├── 4xx6.ld │ ├── 5xx4.ld │ ├── 5xx6.ld │ ├── 5xx8.ld │ ├── 7xx6.ld │ ├── 7xx8.ld │ ├── 7xxb.ld │ ├── 9xxb.ld │ └── 9xxc.ld ├── lib ├── io_def.hpp └── main_app.hpp ├── reg ├── cortexm │ ├── nvic.hpp │ ├── scb.hpp │ └── systick.hpp ├── reg_generator.py └── stm32 │ ├── _common │ ├── adc_v2.hpp │ ├── dma_v1.hpp │ ├── exti.hpp │ ├── gpio_v2.hpp │ ├── i2c_v2.hpp │ ├── iwdg_v1.hpp │ ├── iwdg_v2.hpp │ ├── rtc_v2.hpp │ ├── spi_v1.hpp │ ├── spi_v2.hpp │ ├── timer.hpp │ ├── usart_v2.hpp │ └── wwdg.hpp │ ├── f0 │ ├── adc.hpp │ ├── comp.hpp │ ├── crc.hpp │ ├── crs.hpp │ ├── dac.hpp │ ├── dma.hpp │ ├── exti.hpp │ ├── flash.hpp │ ├── gpio.hpp │ ├── i2c.hpp │ ├── isr.hpp │ ├── iwdg.hpp │ ├── pwr.hpp │ ├── rcc.hpp │ ├── rtc.hpp │ ├── spi.hpp │ ├── syscfg.hpp │ ├── sysmem.hpp │ ├── timer.hpp │ ├── usart.hpp │ └── wwdg.hpp │ ├── f1 │ └── wwdg.hpp │ ├── f2 │ ├── gpio.hpp │ └── wwdg.hpp │ ├── f3 │ ├── gpio.hpp │ ├── iwdg.hpp │ ├── rtc.hpp │ ├── usart.hpp │ └── wwdg.hpp │ ├── f4 │ ├── gpio.hpp │ └── wwdg.hpp │ ├── f7 │ ├── gpio.hpp │ ├── iwdg.hpp │ ├── usart.hpp │ └── wwdg.hpp │ ├── h7 │ ├── gpio.hpp │ └── iwdg.hpp │ ├── l0 │ ├── adc.hpp │ ├── dma.hpp │ ├── gpio.hpp │ ├── i2c.hpp │ ├── iwdg.hpp │ ├── spi.hpp │ ├── usart.hpp │ └── wwdg.hpp │ ├── l1 │ ├── gpio.hpp │ └── wwdg.hpp │ └── l4 │ ├── gpio.hpp │ ├── iwdg.hpp │ ├── usart.hpp │ └── wwdg.hpp └── startup ├── _common ├── bss.hpp ├── data.hpp ├── fini.hpp ├── heap.hpp └── init.hpp └── stm32 └── f0.cpp /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Pavel Revak 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # C++ IO library for ARM Cortex-M micro-controllers 2 | 3 | ## Goal 4 | 5 | - Is experimental project to replace CMSIS. 6 | - C++ support only (actually GCC) 7 | - Objective access to MCU peripherals and registers. 8 | - Avoid usage of `#define` or other C mess. 9 | - Include some basic startup code 10 | 11 | ## Notice 12 | 13 | This project is under active development and sometimes unstable, there are supported only some peripherals and MCUs. 14 | 15 | Actually most supported and tested is STM32F0xx series. 16 | 17 | If you want to help me with development, or you have any ideas please contact me. 18 | 19 | ## License 20 | 21 | MIT 22 | -------------------------------------------------------------------------------- /handlers/cortexm.cpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Handlers setup code for Cortex-M. 3 | */ 4 | 5 | #include "io/lib/io_def.hpp" 6 | 7 | // Undefined handler is pointing to this function, this stop MCU. 8 | // This function name must by not mangled, so must be C, 9 | // because alias("..") is working only with C code 10 | extern "C" void __stop() { while (true); } 11 | 12 | // Handlers for Cortex-M core. 13 | // These handler are with attribute 'weak' and can be overwritten 14 | // by non-week function, default is __stop() function 15 | __attribute__((weak, alias("__stop"))) void RESET_handler(); 16 | __attribute__((weak, alias("__stop"))) void NMI_handler(); 17 | __attribute__((weak, alias("__stop"))) void HARDFAULT_handler(); 18 | __attribute__((weak, alias("__stop"))) void MEMMANAGE_handler(); 19 | __attribute__((weak, alias("__stop"))) void BUSFAULT_handler(); 20 | __attribute__((weak, alias("__stop"))) void USAGEFAULT_handler(); 21 | __attribute__((weak, alias("__stop"))) void SVCALL_handler(); 22 | __attribute__((weak, alias("__stop"))) void DEBUGMONITOR_handler(); 23 | __attribute__((weak, alias("__stop"))) void PENDSV_handler(); 24 | __attribute__((weak, alias("__stop"))) void SYSTICK_handler(); 25 | 26 | // Dummy handler (for unused vectors) 27 | __attribute__((weak, alias("__stop"))) void DUMMY_handler(); 28 | 29 | // Vector table for handlers 30 | // This array will be placed in ".vectors" section defined in linker script. 31 | __attribute__((section(".vectors"), used)) ptr_func_t __isr_vectors[] = { 32 | RESET_handler, 33 | NMI_handler, 34 | HARDFAULT_handler, 35 | MEMMANAGE_handler, 36 | BUSFAULT_handler, 37 | USAGEFAULT_handler, 38 | DUMMY_handler, 39 | DUMMY_handler, 40 | DUMMY_handler, 41 | DUMMY_handler, 42 | SVCALL_handler, 43 | DEBUGMONITOR_handler, 44 | DUMMY_handler, 45 | PENDSV_handler, 46 | SYSTICK_handler, 47 | }; 48 | -------------------------------------------------------------------------------- /handlers/stack.cpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Stack setup 3 | */ 4 | 5 | // top of stack 6 | extern unsigned __stacktop; 7 | 8 | // put top of stack into ".stack" section 9 | __attribute__((section(".stack"), used)) unsigned *__stack_init = &__stacktop; 10 | -------------------------------------------------------------------------------- /handlers/stm32/f0.cpp: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * Handlers setup code for STM32F0xxxx MCUs. 4 | */ 5 | 6 | #include "io/lib/io_def.hpp" 7 | 8 | // Undefined handler is pointing to this function, this stop MCU. 9 | // This function name must by not mangled, so must be C, 10 | // because alias("..") is working only with C code 11 | extern "C" void __stop_stm32() { while (true); } 12 | 13 | // Handlers for Cortex-M core. 14 | // These handler are with attribute 'weak' and can be overwritten 15 | // by non-week function, default is __stop() function 16 | __attribute__((weak, alias("__stop_stm32"))) void WWDG_handler(); 17 | __attribute__((weak, alias("__stop_stm32"))) void PVD_handler(); 18 | __attribute__((weak, alias("__stop_stm32"))) void RTC_handler(); 19 | __attribute__((weak, alias("__stop_stm32"))) void FLASH_handler(); 20 | __attribute__((weak, alias("__stop_stm32"))) void RCC_CRS_handler(); 21 | __attribute__((weak, alias("__stop_stm32"))) void EXTI0_1_handler(); 22 | __attribute__((weak, alias("__stop_stm32"))) void EXTI2_3_handler(); 23 | __attribute__((weak, alias("__stop_stm32"))) void EXTI4_15_handler(); 24 | __attribute__((weak, alias("__stop_stm32"))) void TSC_handler(); 25 | __attribute__((weak, alias("__stop_stm32"))) void DMA1_CH1_handler(); 26 | __attribute__((weak, alias("__stop_stm32"))) void DMA1_CH2_3_DMA2_CH1_2_handler(); 27 | __attribute__((weak, alias("__stop_stm32"))) void DMA1_CH4_5_6_7_DMA2_CH3_4_5_handler(); 28 | __attribute__((weak, alias("__stop_stm32"))) void ADC_COMP_handler(); 29 | __attribute__((weak, alias("__stop_stm32"))) void TIM1_BRK_UP_TRG_COM_handler(); 30 | __attribute__((weak, alias("__stop_stm32"))) void TIM1_CC_handler(); 31 | __attribute__((weak, alias("__stop_stm32"))) void TIM2_handler(); 32 | __attribute__((weak, alias("__stop_stm32"))) void TIM3_handler(); 33 | __attribute__((weak, alias("__stop_stm32"))) void TIM6_DAC_handler(); 34 | __attribute__((weak, alias("__stop_stm32"))) void TIM7_handler(); 35 | __attribute__((weak, alias("__stop_stm32"))) void TIM14_handler(); 36 | __attribute__((weak, alias("__stop_stm32"))) void TIM15_handler(); 37 | __attribute__((weak, alias("__stop_stm32"))) void TIM16_handler(); 38 | __attribute__((weak, alias("__stop_stm32"))) void TIM17_handler(); 39 | __attribute__((weak, alias("__stop_stm32"))) void I2C1_handler(); 40 | __attribute__((weak, alias("__stop_stm32"))) void I2C2_handler(); 41 | __attribute__((weak, alias("__stop_stm32"))) void SPI1_handler(); 42 | __attribute__((weak, alias("__stop_stm32"))) void SPI2_handler(); 43 | __attribute__((weak, alias("__stop_stm32"))) void USART1_handler(); 44 | __attribute__((weak, alias("__stop_stm32"))) void USART2_handler(); 45 | __attribute__((weak, alias("__stop_stm32"))) void USART3_4_5_6_7_8_handler(); 46 | __attribute__((weak, alias("__stop_stm32"))) void CEC_CAN_handler(); 47 | __attribute__((weak, alias("__stop_stm32"))) void USB_handler(); 48 | 49 | // Dummy handler (for unused vectors) 50 | extern void DUMMY_handler(); 51 | 52 | // Vector table for handlers 53 | // This array will be placed in ".vectors" section defined in linker script. 54 | __attribute__((section(".vectors_stm32"), used)) ptr_func_t __isr_vectors_stm32[] = { 55 | WWDG_handler, 56 | PVD_handler, 57 | RTC_handler, 58 | FLASH_handler, 59 | RCC_CRS_handler, 60 | EXTI0_1_handler, 61 | EXTI2_3_handler, 62 | EXTI4_15_handler, 63 | TSC_handler, 64 | DMA1_CH1_handler, 65 | DMA1_CH2_3_DMA2_CH1_2_handler, 66 | DMA1_CH4_5_6_7_DMA2_CH3_4_5_handler, 67 | ADC_COMP_handler, 68 | TIM1_BRK_UP_TRG_COM_handler, 69 | TIM1_CC_handler, 70 | TIM2_handler, 71 | TIM3_handler, 72 | TIM6_DAC_handler, 73 | TIM7_handler, 74 | TIM14_handler, 75 | TIM15_handler, 76 | TIM16_handler, 77 | TIM17_handler, 78 | I2C1_handler, 79 | I2C2_handler, 80 | SPI1_handler, 81 | SPI2_handler, 82 | USART1_handler, 83 | USART2_handler, 84 | USART3_4_5_6_7_8_handler, 85 | CEC_CAN_handler, 86 | USB_handler, 87 | }; 88 | -------------------------------------------------------------------------------- /ld/_common/flash.ld: -------------------------------------------------------------------------------- 1 | SECTIONS { 2 | . = ORIGIN(FLASH); 3 | .stack : { 4 | KEEP(*(.stack)) 5 | } >FLASH 6 | 7 | .vectors : { 8 | KEEP(*(.vectors)) 9 | KEEP(*(.vectors*)) 10 | } >FLASH 11 | 12 | .text ALIGN(4) : { 13 | KEEP(*(.text)) 14 | *(.text*) 15 | } >FLASH 16 | 17 | .rodata ALIGN(4) : { 18 | KEEP(*(.rodata)) 19 | *(.rodata*) 20 | . = ALIGN(4); 21 | } >FLASH 22 | 23 | .preinit_array ALIGN(4): { 24 | __preinit_array_start = .; 25 | KEEP(*(.preinit_array)) 26 | __preinit_array_end = .; 27 | } >FLASH 28 | 29 | .init_array ALIGN(4): { 30 | __init_array_start = .; 31 | KEEP(*(.init_array)) 32 | __init_array_end = .; 33 | } >FLASH 34 | 35 | .fini_array ALIGN(4): { 36 | __fini_array_start = .; 37 | KEEP(*(.fini_array)) 38 | __fini_array_end = .; 39 | } >FLASH 40 | 41 | /DISCARD/ : { 42 | *(.ARM.exidx*) 43 | *(.gnu.linkonce.armexidx.*) 44 | *(.ARM.attributes) 45 | *(.debug_frame) 46 | *(.comment) 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /ld/_common/sram.ld: -------------------------------------------------------------------------------- 1 | SECTIONS { 2 | __stacktop = ORIGIN(SRAM) + LENGTH(SRAM); 3 | __data_load = LOADADDR(.data); 4 | . = ORIGIN(SRAM); 5 | 6 | .data ALIGN(4) : { 7 | __data_start = .; 8 | *(.data) 9 | *(.data*) 10 | . = ALIGN(4); 11 | __data_end = .; 12 | } >SRAM AT >FLASH 13 | 14 | .bss ALIGN(4) (NOLOAD) : { 15 | __bss_start = .; 16 | *(.bss) 17 | *(.bss*) 18 | . = ALIGN(4); 19 | __bss_end = .; 20 | *(.noinit) 21 | *(.noinit*) 22 | } >SRAM 23 | 24 | . = ALIGN(4); 25 | __heap_start = .; 26 | } 27 | -------------------------------------------------------------------------------- /ld/stm32/f0/3xx4.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 16K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 4K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/3xx6.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 32K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 4K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/3xx8.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 64K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 8K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/3xxc.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 256K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/4xx4.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 16K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 6K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/4xx6.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 32K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 6K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/5xx4.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 16K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 8K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/5xx6.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 32K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 8K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/5xx8.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 64K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 8K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/7xx6.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 32K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 6K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/7xx8.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 64K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/7xxb.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 128K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/9xxb.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 128K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /ld/stm32/f0/9xxc.ld: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 256K 3 | SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K 4 | } 5 | 6 | INCLUDE "io/ld/_common/flash.ld" 7 | INCLUDE "io/ld/_common/sram.ld" 8 | -------------------------------------------------------------------------------- /lib/io_def.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * io library definitions 3 | */ 4 | 5 | #pragma once 6 | 7 | typedef void (*ptr_func_t)(); 8 | -------------------------------------------------------------------------------- /lib/main_app.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * main_app function definition 3 | */ 4 | 5 | #pragma once 6 | 7 | extern void main_app(); 8 | -------------------------------------------------------------------------------- /reg/cortexm/nvic.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * NVIC - Nested Vector Interrupt Controller 5 | * 6 | * MCUs containing this peripheral: 7 | * - Cortex-M0 8 | * - Cortex-M0plus 9 | * - Cortex-M3 10 | * - Cortex-M4 11 | * - Cortex-M7 12 | */ 13 | 14 | #pragma once 15 | 16 | #include 17 | #include 18 | 19 | namespace io { 20 | 21 | struct Nvic { 22 | /** Software trigger interrupt register 23 | * This register is on Cortex-M3, M4 and M7 24 | */ 25 | struct Stir { 26 | Stir(const uint32_t raw=0) { r = raw; } 27 | 28 | struct Bits { 29 | uint32_t INTID : 9; // Software generated interrupt ID 30 | uint32_t : 23; 31 | }; 32 | 33 | union { 34 | uint32_t r; 35 | Bits b; 36 | uint32_t INTID; // direct 32 bit access to INTID 37 | }; 38 | }; 39 | 40 | volatile uint32_t ISER[8]; // Interrupt set-enable registers 41 | uint32_t __res0[24]; 42 | volatile uint32_t ICER[8]; // Interrupt clear-enable registers 43 | uint32_t __res1[24]; 44 | volatile uint32_t ISPR[8]; // Interrupt set-pending registers 45 | uint32_t __res2[24]; 46 | volatile uint32_t ICPR[8]; // Interrupt clear-pending registers 47 | uint32_t __res3[24]; 48 | volatile const uint32_t IABR[8]; // Interrupt active bit registers (M3, M4, M7) 49 | uint32_t __res4[56]; 50 | volatile uint8_t IPR[240]; // Interrupt priority registers 51 | uint32_t __res5[644]; 52 | volatile Stir STIR; // Software trigger interrupt register (M3, M4, M7) 53 | 54 | /** Enable interrupt 55 | * @param isr interrupt ID 56 | */ 57 | inline void iser(uint32_t isr) { 58 | ISER[isr >> 5] = static_cast(1 << (isr & 0x1f)); 59 | } 60 | 61 | /** Disable interrupt 62 | * @param isr interrupt ID 63 | */ 64 | inline void icer(uint32_t isr) { 65 | ICER[isr >> 5] = static_cast(1 << (isr & 0x1f)); 66 | } 67 | 68 | /** Is interrupt enabled 69 | * @param isr interrupt ID 70 | * @return True if interrupt is enabled 71 | */ 72 | inline bool ier(uint32_t isr) const { 73 | return ISER[isr >> 5] & static_cast(1 << (isr & 0x1f)); 74 | } 75 | 76 | /** Enable pending interrupt 77 | * @param isr interrupt ID 78 | */ 79 | inline void ispr(uint32_t isr) { 80 | ISPR[isr >> 5] = static_cast(1 << (isr & 0x1f)); 81 | } 82 | 83 | /** Disable pending interrupt 84 | * @param isr interrupt ID 85 | */ 86 | inline void icpr(uint32_t isr) { 87 | ICPR[isr >> 5] = static_cast(1 << (isr & 0x1f)); 88 | } 89 | 90 | /** Is pending interrupt 91 | * @param isr interrupt ID 92 | * @return True if interrupt is enabled 93 | */ 94 | inline bool ipr(uint32_t isr) const { 95 | return ISPR[isr >> 5] & static_cast(1 << (isr & 0x1f)); 96 | } 97 | 98 | /** Is interrupt active 99 | * @param isr interrupt ID 100 | * @return True if interrupt is active 101 | */ 102 | inline bool iabr(uint32_t isr) const { 103 | return IABR[isr >> 5] & static_cast(1 << (isr & 0x1f)); 104 | } 105 | 106 | /** Enable global interrupt 107 | */ 108 | static inline void isr_enable() { 109 | __asm volatile ("cpsie i" : : : "memory"); 110 | } 111 | 112 | /** 113 | * disable global interrupt 114 | */ 115 | static inline void isr_disable() { 116 | __asm volatile ("cpsid i" : : : "memory"); 117 | } 118 | 119 | static const size_t BASE = 0xe000e100; 120 | }; 121 | 122 | static Nvic &NVIC = *reinterpret_cast(Nvic::BASE); 123 | 124 | } 125 | -------------------------------------------------------------------------------- /reg/cortexm/scb.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SCB - System Control Block 5 | * 6 | * MCUs containing this peripheral: 7 | * - Cortex M0 8 | * - Cortex M0plus 9 | * - Cortex M3 10 | * - Cortex M4 11 | * - Cortex M7 12 | */ 13 | 14 | #pragma once 15 | 16 | #include 17 | #include 18 | 19 | namespace io { 20 | 21 | struct Scb { 22 | /** CPUID Register 23 | */ 24 | struct Cpuid { 25 | Cpuid(const uint32_t raw=0) { r = raw; } 26 | 27 | struct Bits { 28 | const uint32_t REVISION : 4; // Revision number 29 | const uint32_t PARTNO : 12; // Part number of the processor 30 | const uint32_t ARCHITECTURE : 4; // Architecture 31 | const uint32_t VARIANT : 4; // Part Number 32 | const uint32_t IMPLEMENTER : 8; // Revision number 33 | }; 34 | 35 | struct Partno { 36 | static const uint32_t CORTEX_M0 = 0xc20; 37 | static const uint32_t CORTEX_M0P = 0xc60; 38 | static const uint32_t CORTEX_M3 = 0xc23; 39 | static const uint32_t CORTEX_M4 = 0xc24; 40 | static const uint32_t CORTEX_M7 = 0xc27; 41 | }; 42 | 43 | struct Architecture { 44 | static const uint32_t ARMV6M = 0xc; // M0, M0+ 45 | static const uint32_t ARMV7M = 0xf; // M3, M4, M7 46 | }; 47 | 48 | struct Implementer { 49 | static const uint32_t ARM = 0x41; 50 | }; 51 | 52 | union { 53 | uint32_t r; 54 | Bits b; 55 | }; 56 | }; 57 | 58 | /** Interrupt control and state register 59 | */ 60 | struct Icsr { 61 | Icsr(const uint32_t raw=0) { r = raw; } 62 | 63 | struct Bits { 64 | uint32_t VECTACTIVE : 9; // Active vector 65 | uint32_t : 2; 66 | const uint32_t RETOBASE : 1; // Return to base level (M0+, M3, M4, M7) 67 | const uint32_t VECTPENDING : 9; // Pending vector 68 | uint32_t : 1; 69 | const uint32_t ISRPENDING : 1; // Interrupt pending flag 70 | uint32_t : 2; 71 | uint32_t PENDSTCLR : 1; // SysTick exception clear-pending bit 72 | uint32_t PENDSTSET : 1; // SysTick exception set-pending bit 73 | uint32_t PENDSVCLR : 1; // PendSV clear-pending bit 74 | uint32_t PENDSVSET : 1; // PendSV set-pending bit 75 | uint32_t : 2; 76 | uint32_t NMIPENDSET : 1; // NMI set-pending bit 77 | }; 78 | 79 | union { 80 | uint32_t r; 81 | Bits b; 82 | }; 83 | }; 84 | 85 | /** Vector Table Offset Register 86 | */ 87 | struct Vtor { 88 | union { 89 | uint32_t r; 90 | uint32_t TBLOFF; // Vector table base offset field 91 | }; 92 | }; 93 | 94 | /** Application Interrupt and Reset Control Register 95 | */ 96 | struct Aircr { 97 | Aircr(const uint32_t raw=0) { r = raw; } 98 | 99 | struct Bits { 100 | uint32_t VECTRESET : 1; // Reserved for Debug use 101 | uint32_t VECTCLRACTIVE : 1; // Reserved for Debug use 102 | uint32_t SYSRESETREQ : 1; // System reset request 103 | uint32_t : 5; 104 | uint32_t PRIGROUP : 3; // Interrupt priority grouping field (M3, M4, M7) 105 | uint32_t : 4; 106 | const uint32_t ENDIANESS : 1; // Data endianness bit 107 | uint32_t VECTKEY : 16; // Register key 108 | }; 109 | 110 | struct Endianess { 111 | static const uint32_t LITTLE_ENDIAN = 0; 112 | }; 113 | 114 | union { 115 | uint32_t r; 116 | Bits b; 117 | }; 118 | }; 119 | 120 | /** System control registe 121 | */ 122 | struct Scr { 123 | Scr(const uint32_t raw=0) { r = raw; } 124 | 125 | struct Bits { 126 | uint32_t : 1; 127 | uint32_t SLEEPONEXIT : 1; // Seep on return from interrupt 128 | uint32_t SLEEPDEEP : 1; // Use deep sleep mode 129 | uint32_t : 1; 130 | uint32_t SEVONPEND : 1; // Send Event on Pending bit 131 | uint32_t : 27; 132 | }; 133 | 134 | union { 135 | uint32_t r; 136 | Bits b; 137 | }; 138 | }; 139 | 140 | /** Configuration and control register 141 | */ 142 | struct Ccr { 143 | Ccr(const uint32_t raw=0) { r = raw; } 144 | 145 | struct Bits { 146 | uint32_t NONBASETHRDENA : 1; // Configures how the processor enters Thread mode (M3, M4, M7) 147 | uint32_t USERSETMPEND : 1; // Enables unprivileged software access to the STIR (M3, M4, M7) 148 | uint32_t : 1; 149 | uint32_t UNALIGN_TRP : 1; // Enables unaligned access traps 150 | uint32_t DIV_0_TRP : 1; // Trap on SDIV or UDIV with a divisor of 0 (M3, M4, M7) 151 | uint32_t : 3; 152 | uint32_t BFHFNMIGN : 1; // Enables handlers with priority -1 or -2 (M3, M4, M7) 153 | uint32_t STKALIGN : 1; // Configures stack alignment on exception entry 154 | uint32_t : 22; 155 | }; 156 | 157 | union { 158 | uint32_t r; 159 | Bits b; 160 | }; 161 | }; 162 | 163 | /** System handler priority register 164 | */ 165 | struct Shpr { 166 | Shpr(const uint32_t raw0=0, const uint32_t raw1=0, const uint32_t raw2=0) { r[0] = raw0; r[1] = raw1; r[2] = raw2; } 167 | 168 | struct Bits { 169 | uint8_t PRI_4; // MEMMANAGE handler priority (M3, M4, M7) 170 | uint8_t PRI_5; // BUSFAULT handler priority (M3, M4, M7) 171 | uint8_t PRI_6; // USAGEFAULT handler priority (M3, M4, M7) 172 | uint8_t __res7; 173 | uint8_t __res8; 174 | uint8_t __res9; 175 | uint8_t __res10; 176 | uint8_t PRI_11; // SVCALL handler priority 177 | uint8_t __res12; // DEBUGMONITOR handler priority 178 | uint8_t __res13; 179 | uint8_t PRI_14; // PENDSV handler priority 180 | uint8_t PRI_15; // SYSTICK handler priority 181 | }; 182 | 183 | union { 184 | uint32_t r[3]; 185 | Bits b; 186 | }; 187 | }; 188 | 189 | /** System handler control and state register (M3, M4, M7) 190 | */ 191 | struct Shcsr { 192 | Shcsr(const uint32_t raw=0) { r = raw; } 193 | 194 | struct Bits { 195 | uint32_t MEMFAULTACT : 1; // Memory management fault exception active bit 196 | uint32_t BUSFAULTACT : 1; // Bus fault exception active bit 197 | uint32_t : 1; 198 | uint32_t USGFAULTACT : 1; // Usage fault exception active bit 199 | uint32_t : 3; 200 | uint32_t SVCALLACT : 1; // SVC call active bit 201 | uint32_t MONITORACT : 1; // Debug monitor active bit 202 | uint32_t : 1; 203 | uint32_t PENDSVACT : 1; // PendSV exception active bit 204 | uint32_t SYSTICKACT : 1; // SysTick exception active bit 205 | uint32_t USGFAULTPENDED : 1; // Usage fault exception pending bit 206 | uint32_t MEMFAULTPENDED : 1; // Memory management fault exception pending bit 207 | uint32_t BUSFAULTPENDED : 1; // Bus fault exception pending bit 208 | uint32_t SVCALLPENDED : 1; // SVC call pending bit 209 | uint32_t MEMFAULTENA : 1; // Memory management fault enable bit 210 | uint32_t BUSFAULTENA : 1; // Bus fault enable bit 211 | uint32_t USGFAULTENA : 1; // Usage fault enable bit 212 | uint32_t : 13; 213 | }; 214 | 215 | union { 216 | uint32_t r; 217 | Bits b; 218 | }; 219 | }; 220 | 221 | /** Configurable fault status register (M3, M4, M7) 222 | */ 223 | struct Cfsr { 224 | Cfsr(const uint32_t raw=0) { r = raw; } 225 | 226 | struct Bits { 227 | uint32_t IACCVIOL : 1; // Instruction access violation flag 228 | uint32_t DACCVIOL : 1; // Data access violation flag 229 | uint32_t : 1; 230 | uint32_t MUNSTKERR : 1; // Memory manager fault on unstacking for a return from exception 231 | uint32_t MSTKERR : 1; // Memory manager fault on stacking for exception entry 232 | uint32_t MLSPERR : 1; // MemManage fault occurred during floating-point lazy state (M4, M7) 233 | uint32_t : 1; 234 | uint32_t MMARVALID : 1; // Memory Management Fault Address Register (MMAR) valid flag 235 | uint32_t IBUSERR : 1; // Instruction bus error 236 | uint32_t PRECISERR : 1; // Precise data bus error 237 | uint32_t IMPRECISERR : 1; // Imprecise data bus error 238 | uint32_t UNSTKERR : 1; // Bus fault on unstacking for a return from exception 239 | uint32_t STKERR : 1; // Bus fault on stacking for exception entry 240 | uint32_t LSPERR : 1; // Bus fault on floating-point lazy state preservation (M4, M7) 241 | uint32_t : 1; 242 | uint32_t BFARVALID : 1; // Bus Fault Address Register (BFAR) valid flag 243 | uint32_t UNDEFINSTR : 1; // Undefined instruction usage fault 244 | uint32_t INVSTATE : 1; // Invalid state usage fault 245 | uint32_t INVPC : 1; // Invalid PC load usage fault 246 | uint32_t NOCP : 1; // No coprocessor usage fault 247 | uint32_t : 4; 248 | uint32_t UNALIGNED : 1; // Unaligned access usage fault 249 | uint32_t DIVBYZERO : 1; // Divide by zero usage fault 250 | uint32_t : 6; 251 | }; 252 | 253 | union { 254 | uint32_t r; 255 | Bits b; 256 | }; 257 | }; 258 | 259 | /** HardFault status register (M3, M4, M7) 260 | */ 261 | struct Hfsr { 262 | Hfsr(const uint32_t raw=0) { r = raw; } 263 | 264 | struct Bits { 265 | uint32_t : 1; 266 | uint32_t VECTTBL : 1; // Vector table hard fault 267 | uint32_t : 4; 268 | uint32_t FORCED : 1; // Forced hard fault 269 | uint32_t DEBUG_VT : 1; // Reserved for Debug use 270 | uint32_t : 24; 271 | }; 272 | 273 | union { 274 | uint32_t r; 275 | Bits b; 276 | }; 277 | }; 278 | 279 | volatile Cpuid CPUID; // CPUID base register 280 | volatile Icsr ICSR; // Interrupt control and state register 281 | volatile Vtor VTOR; // Vector Table Offset Register (M3, M4, M7) 282 | volatile Aircr AIRCR; // Application Interrupt and Reset Control Register 283 | volatile Scr SCR; // System control registe 284 | volatile Ccr CCR; // Configuration and control register 285 | volatile Shpr SHPR; // System handler priority registers 286 | volatile Shcsr SHCSR; // ystem handler control and state register (M3, M4, M7) 287 | volatile Cfsr CFSR; // Configurable fault status register (M3, M4, M7) 288 | volatile Hfsr HFSR; // HardFault status register (M3, M4, M7) 289 | volatile uint32_t MMFAR; // Memory management fault address register (M3, M4, M7) 290 | volatile uint32_t BFAR; // Bus fault address register (M3, M4, M7) 291 | volatile uint32_t AFSR; // Auxiliary fault status register (M4, M7) 292 | 293 | static const size_t BASE = 0xe000ed00; 294 | }; 295 | 296 | static Scb &SCB = *reinterpret_cast(Scb::BASE); 297 | 298 | } 299 | -------------------------------------------------------------------------------- /reg/cortexm/systick.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SYSTICK - SysTick Timer 5 | * 6 | * MCUs containing this peripheral: 7 | * - Cortex M0 8 | * - Cortex M0plus 9 | * - Cortex M3 10 | * - Cortex M4 11 | * - Cortex M7 12 | */ 13 | 14 | #pragma once 15 | 16 | #include 17 | #include 18 | 19 | namespace io { 20 | 21 | struct Systick { 22 | /** SysTick control and status register 23 | */ 24 | struct Csr { 25 | Csr(const uint32_t raw=0) { r = raw; } 26 | 27 | struct Bits { 28 | uint32_t ENABLE : 1; // Counter enable 29 | uint32_t TICKINT : 1; // SysTick exception request enable 30 | uint32_t CLKSOURCE : 1; // Clock source selection 31 | uint32_t : 13; 32 | uint32_t COUNTFLAG : 1; // Returns 1 if timer counted to 0 since last time this was read. 33 | uint32_t : 15; 34 | }; 35 | 36 | union { 37 | uint32_t r; 38 | Bits b; 39 | }; 40 | 41 | struct Clksource { 42 | static const uint32_t EXTERNAL = 0; 43 | static const uint32_t PROCESSOR = 1; 44 | }; 45 | }; 46 | 47 | /** SysTick reload value register 48 | */ 49 | struct Load { 50 | Load(const uint32_t raw=0) { r = raw; } 51 | 52 | struct Bits { 53 | uint32_t RELOAD : 24; // reload value 54 | uint32_t : 8; 55 | }; 56 | 57 | union { 58 | uint32_t r; 59 | Bits b; 60 | uint32_t RELOAD; // direct 32 bit access to RELOAD 61 | }; 62 | }; 63 | 64 | /** SysTick current value register 65 | */ 66 | struct Val { 67 | Val(const uint32_t raw=0) { r = raw; } 68 | 69 | struct Bits { 70 | uint32_t CURRENT : 24; // current counter value 71 | uint32_t : 8; 72 | }; 73 | 74 | union { 75 | uint32_t r; 76 | Bits b; 77 | uint32_t CURRENT; // direct 32 bit access to COUNTER 78 | }; 79 | }; 80 | 81 | /** SysTick calibration value register 82 | */ 83 | struct Calib { 84 | Calib(const uint32_t raw=0) { r = raw; } 85 | 86 | struct Bits { 87 | const uint32_t TENMS : 24; // Calibration value 88 | uint32_t : 6; 89 | const uint32_t SKEW : 1; // Indicates whether the TENMS value is exact 90 | const uint32_t NOREF : 1; // No reference clock to the processor 91 | }; 92 | 93 | union { 94 | uint32_t r; 95 | Bits b; 96 | }; 97 | }; 98 | 99 | volatile Csr CSR; // SysTick control and status register 100 | volatile Load LOAD; // SysTick reload value register 101 | volatile Val VAL; // SysTick reload value register 102 | volatile Calib CALIB; // SysTick calibration value register 103 | 104 | static const size_t BASE = 0xe000e010; 105 | }; 106 | 107 | static Systick &SYSTICK = *reinterpret_cast(Systick::BASE); 108 | 109 | } 110 | -------------------------------------------------------------------------------- /reg/reg_generator.py: -------------------------------------------------------------------------------- 1 | """io:reg generator""" 2 | 3 | import sys 4 | import swd.svd 5 | 6 | 7 | class RegGeneratorError(Exception): 8 | pass 9 | 10 | 11 | def generate_bits(register): 12 | print(" struct Bits {") 13 | current_offset = 0 14 | for field in register.fields: 15 | if field.offset > current_offset: 16 | offset = field.offset - current_offset 17 | print(f" uint32_t : {offset};") 18 | elif field.offset < current_offset: 19 | raise RegGeneratorError("REPEATING BITS") 20 | current_offset = field.offset + field.width 21 | prefix = '' 22 | if field.allow_read and not field.allow_write: 23 | prefix = 'const ' 24 | print(f" {prefix}uint32_t {field.name} : {field.width}; // {field.description}") 25 | for enumerated_value in field.enumerated_values: 26 | print(f" // {enumerated_value}") 27 | if current_offset < 32: 28 | print(f" uint32_t : {32 - current_offset};") 29 | elif current_offset > 32: 30 | raise RegGeneratorError("Too many bits in register") 31 | print(" };") 32 | 33 | 34 | def generate_registers_definitions(peripheral): 35 | for register in peripheral.registers: 36 | register_class_name = register.name.capitalize() 37 | print(f" /** {register.description}") 38 | print(" */") 39 | print(f" struct {register_class_name} {{") 40 | print(f" {register_class_name}(const uint32_t raw=0) {{ r = raw; }}") 41 | print() 42 | generate_bits(register) 43 | print() 44 | print(" union {") 45 | print(" uint32_t r;") 46 | print(" Bits b;") 47 | print(" };") 48 | print(" };") 49 | print() 50 | 51 | 52 | def generate_registers(peripheral): 53 | registers = [] 54 | current_offset = 0 55 | for register in peripheral.registers: 56 | offset = register.offset - current_offset 57 | if offset % 4 != 0: 58 | raise RegGeneratorError("wrong registers alignment") 59 | offset //= 4 60 | if offset == 0: 61 | registers.append(register) 62 | elif offset > 0: 63 | registers.append(offset) 64 | registers.append(register) 65 | elif offset < 0: 66 | if isinstance(registers[offset], int): 67 | raise RegGeneratorError("Inconsistent registers definition") 68 | if isinstance(registers[offset], swd.svd.Register): 69 | registers[offset] = [registers[offset]] 70 | if isinstance(registers[offset], list): 71 | registers[offset].append(register) 72 | else: 73 | raise RegGeneratorError("Unexpected error") 74 | current_offset = register.offset + 4 75 | res_counter = 0 76 | for register in registers: 77 | # print(register) 78 | if isinstance(register, int): 79 | if register == 1: 80 | print(f" uint32_t _res{res_counter:02d}") 81 | elif register > 1: 82 | print(f" uint32_t _res{res_counter:02d}[{(register)}]") 83 | else: 84 | raise RegGeneratorError("Unexpected error") 85 | res_counter += 1 86 | elif isinstance(register, swd.svd.Register): 87 | register_class_name = register.name.capitalize() 88 | print(f" volatile {register_class_name} {register.name}; // {register.description}") 89 | elif isinstance(register, list): 90 | index = 1 91 | # print(str(registers)) 92 | while len({reg.name[:index] for reg in register}) == 1: 93 | index += 1 94 | index -= 1 95 | print(" union {") 96 | common_name = register[0].name[:index].upper() 97 | 98 | for union_register in register: 99 | register_class_name = union_register.name.capitalize() 100 | print(f" volatile {register_class_name} {union_register.name.removeprefix(common_name)}; // {union_register.description}") 101 | if index > 0: 102 | print(f" }} {common_name.rstrip('_')};") 103 | else: 104 | print(" } FIXME;") 105 | 106 | 107 | def generate_peripheral(peripheral): 108 | peripheral_class_name = peripheral.name.capitalize() 109 | print("/**") 110 | print(" * Peripheral Definition File") 111 | print(" *") 112 | print(f" * {peripheral.name} - {peripheral.description}") 113 | print(" */") 114 | print() 115 | print("#pragma once") 116 | print() 117 | print("#include ") 118 | print("#include ") 119 | print() 120 | print("namespace io {") 121 | print() 122 | print(f"/** {peripheral.description}") 123 | print(" */") 124 | print(f"struct {peripheral_class_name} {{") 125 | generate_registers_definitions(peripheral) 126 | generate_registers(peripheral) 127 | print("};") 128 | print() 129 | print("namespace base {") 130 | print() 131 | print(f"static const size_t {peripheral.name} = 0x{peripheral.base_address:8x};") 132 | print() 133 | print("}") 134 | print() 135 | print(f"static {peripheral_class_name} &{peripheral.name} = *reinterpret_cast<{peripheral_class_name} *>(base::{peripheral.name});") 136 | print() 137 | print("}") 138 | 139 | 140 | def generate_handlers(svd): 141 | print("/**") 142 | print(" * Handlers Setup File") 143 | print(" */") 144 | print('#include "io/lib/io_def.hpp"') 145 | print() 146 | print('// Undefined handler is pointing to this function, this stop MCU.') 147 | print('// This function name must by not mangled, so must be C,') 148 | print('// because alias("..") is working only with C code') 149 | print('extern "C" void __stop_mcu() { while (true); }') 150 | print() 151 | print('// These handler are with attribute "weak" and can be overwritten') 152 | print('// by non-week function, default is __stop_mcu() function') 153 | for interrupt in svd.interrupts: 154 | print(f'__attribute__((weak, alias("__stop_mcu"))) void {interrupt.name}_handler();') 155 | print() 156 | print("// Dummy handler (for unused vectors)") 157 | print("extern void DUMMY_handler();") 158 | print() 159 | print('__attribute__((section(".vectors_mcu"), used)) ptr_func_t __isr_vectors_mcu[] = {') 160 | last_vector = -1 161 | for interrupt in svd.interrupts: 162 | while last_vector + 1 < interrupt.vector: 163 | last_vector += 1 164 | print(" DUMMY_handler,") 165 | last_vector = interrupt.vector 166 | print(f' {interrupt.name}_handler, // {interrupt.vector}') 167 | print("};") 168 | 169 | 170 | def main(svd_file, peripheral_name=None): 171 | svd = swd.svd.Svd() 172 | svd.parse_svd(svd_file) 173 | svd.validate() 174 | if not peripheral_name: 175 | for peripheral in svd.peripherals: 176 | print(f"0x{peripheral.base_address:08x} : {peripheral.name}") 177 | elif peripheral_name == 'handlers': 178 | generate_handlers(svd) 179 | else: 180 | for peripheral in svd.peripherals: 181 | if peripheral_name == peripheral.name: 182 | generate_peripheral(peripheral) 183 | break 184 | 185 | 186 | if __name__ == "__main__": 187 | if len(sys.argv) == 2: 188 | main(sys.argv[1]) 189 | elif len(sys.argv) == 3: 190 | main(sys.argv[1], sys.argv[2]) 191 | else: 192 | print(f'Usage: {sys.argv[0]} path/to/file.svd [PERIPHERAL_NAME|handlers]') 193 | -------------------------------------------------------------------------------- /reg/stm32/_common/adc_v2.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * ADC - Analog Digital Converter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32L0xx 9 | */ 10 | 11 | #pragma once 12 | 13 | #include 14 | #include 15 | 16 | namespace io { 17 | 18 | struct Adc { 19 | /** Interrupt and status register 20 | */ 21 | struct Isr { 22 | Isr(const uint32_t raw=0) { r = raw; } 23 | 24 | struct Bits { 25 | uint32_t ADRDY : 1; // ADC ready 26 | uint32_t EOSMP : 1; // End of sampling flag 27 | uint32_t EOC : 1; // End of conversion flag 28 | uint32_t EOSEQ : 1; // End of sequence flag 29 | uint32_t OVR : 1; // ADC overrun 30 | uint32_t : 2; 31 | uint32_t AWD : 1; // Analog watchdog flag 32 | uint32_t : 3; 33 | uint32_t EOCAL : 1; // End Of Calibration flag (L0) 34 | uint32_t : 20; 35 | }; 36 | 37 | union { 38 | uint32_t r; 39 | Bits b; 40 | }; 41 | }; 42 | 43 | /** Interrupt enable register 44 | */ 45 | struct Ier { 46 | Ier(const uint32_t raw=0) { r = raw; } 47 | 48 | struct Bits { 49 | uint32_t ADRDYIE : 1; // ADC ready interrupt enable 50 | uint32_t EOSMPIE : 1; // End of sampling flag interrupt enable 51 | uint32_t EOCIE : 1; // End of conversion interrupt enable 52 | uint32_t EOSEQIE : 1; // End of conversion sequence interrupt enable 53 | uint32_t OVRIE : 1; // Overrun interrupt enable 54 | uint32_t : 2; 55 | uint32_t AWDIE : 1; // Analog watchdog interrupt enable 56 | uint32_t : 3; 57 | uint32_t EOCALIE : 1; // End Of Calibration flag interrupt enable (L0) 58 | uint32_t : 20; 59 | }; 60 | 61 | union { 62 | uint32_t r; 63 | Bits b; 64 | }; 65 | }; 66 | 67 | /** Control register 68 | */ 69 | struct Cr { 70 | Cr(const uint32_t raw=0) { r = raw; } 71 | 72 | struct Bits { 73 | uint32_t ADEN : 1; // ADC enable command 74 | uint32_t ADDIS : 1; // ADC disable command 75 | uint32_t ADSTART : 1; // ADC start conversion command 76 | uint32_t : 1; 77 | uint32_t ADSTP : 1; // ADC stop conversion command 78 | uint32_t : 23; 79 | uint32_t ADVREGEN : 1; // ADC Voltage Regulator Enable (L0) 80 | uint32_t : 2; 81 | uint32_t ADCAL : 1; // ADC calibration 82 | }; 83 | 84 | union { 85 | uint32_t r; 86 | Bits b; 87 | }; 88 | }; 89 | 90 | /** Configuration register 1 91 | */ 92 | struct Cfgr1 { 93 | Cfgr1(const uint32_t raw=0) { r = raw; } 94 | 95 | struct Bits { 96 | uint32_t DMAEN : 1; // Direct memory access enable 97 | uint32_t DMACFG : 1; // Direct memory access configuration 98 | uint32_t SCANDIR : 1; // Scan sequence direction 99 | uint32_t RES : 2; // Data resolution 100 | uint32_t ALIGN : 1; // Data alignment 101 | uint32_t EXTSEL : 3; // External trigger selection 102 | uint32_t : 1; 103 | uint32_t EXTEN : 2; // External trigger enable and polarity selection 104 | uint32_t OVRMOD : 1; // Overrun management mode 105 | uint32_t CONT : 1; // Single / continuous conversion mode 106 | uint32_t WAIT : 1; // Wait conversion mode 107 | uint32_t AUTOFF : 1; // Auto-off mode 108 | uint32_t DISCEN : 1; // Discontinuous mode 109 | uint32_t : 5; 110 | uint32_t AWDSGL : 1; // Enable the watchdog on a single channel or on all channels 111 | uint32_t AWDEN : 1; // Analog watchdog enable 112 | uint32_t : 2; 113 | uint32_t AWDCH : 5; // Analog watchdog channel selection 114 | uint32_t : 1; 115 | }; 116 | 117 | struct Res { 118 | static const uint32_t RES_12 = 0; 119 | static const uint32_t RES_10 = 1; 120 | static const uint32_t RES_8 = 2; 121 | static const uint32_t RES_6 = 3; 122 | }; 123 | 124 | union { 125 | uint32_t r; 126 | Bits b; 127 | }; 128 | }; 129 | 130 | /** Configuration register 2 131 | */ 132 | struct Cfgr2 { 133 | Cfgr2(const uint32_t raw=0) { r = raw; } 134 | 135 | struct Bits { 136 | uint32_t OVSE : 1; // Oversampler Enable (L0) 137 | uint32_t : 1; 138 | uint32_t OVSR : 3; // Oversampling ratio (L0) 139 | uint32_t OVSS : 4; // Oversampling shift (L0) 140 | uint32_t TOVS : 1; // Triggered Oversampling (L0) 141 | uint32_t : 20; 142 | uint32_t CKMODE : 2; // ADC clock mode 143 | }; 144 | 145 | struct Ovsr { 146 | static const uint32_t OVS_2 = 0; 147 | static const uint32_t OVS_4 = 1; 148 | static const uint32_t OVS_8 = 2; 149 | static const uint32_t OVS_16 = 3; 150 | static const uint32_t OVS_32 = 4; 151 | static const uint32_t OVS_64 = 5; 152 | static const uint32_t OVS_128 = 6; 153 | static const uint32_t OVS_256 = 7; 154 | }; 155 | 156 | struct Ckmode { 157 | static const uint32_t ADCCLK = 0; 158 | static const uint32_t PCLK_DIV2 = 1; 159 | static const uint32_t PCLK_DIV4 = 2; 160 | }; 161 | 162 | union { 163 | uint32_t r; 164 | Bits b; 165 | }; 166 | }; 167 | 168 | /** Sampling time register 169 | */ 170 | struct Smpr { 171 | Smpr(const uint32_t raw=0) { r = raw; } 172 | 173 | struct Bits { 174 | uint32_t SMP : 3; // Sampling time selection 175 | uint32_t : 29; 176 | }; 177 | 178 | struct Smp { 179 | static const uint32_t SMP_1_5 = 0; 180 | static const uint32_t SMP_7_5 = 1; 181 | static const uint32_t SMP_13_5 = 2; 182 | static const uint32_t SMP_28_5 = 3; 183 | static const uint32_t SMP_41_5 = 4; 184 | static const uint32_t SMP_55_5 = 5; 185 | static const uint32_t SMP_71_5 = 6; 186 | static const uint32_t SMP_239_5 = 7; 187 | }; 188 | 189 | union { 190 | uint32_t r; 191 | Bits b; 192 | }; 193 | }; 194 | 195 | /** Watchdog threshold register 196 | */ 197 | struct Tr { 198 | Tr(const uint32_t raw=0) { r = raw; } 199 | 200 | struct Bits { 201 | uint32_t LT : 12; // Analog watchdog lower threshold 202 | uint32_t : 4; 203 | uint32_t HT : 12; // Analog watchdog higher threshold 204 | uint32_t : 4; 205 | }; 206 | 207 | union { 208 | uint32_t r; 209 | Bits b; 210 | }; 211 | }; 212 | 213 | /** Channel selection register 214 | */ 215 | struct Chselr { 216 | Chselr(const uint32_t raw=0) { r = raw; } 217 | 218 | struct Bits { 219 | uint32_t CHSEL0 : 1; // Channel selection 220 | uint32_t CHSEL1 : 1; 221 | uint32_t CHSEL2 : 1; 222 | uint32_t CHSEL3 : 1; 223 | uint32_t CHSEL4 : 1; 224 | uint32_t CHSEL5 : 1; 225 | uint32_t CHSEL6 : 1; 226 | uint32_t CHSEL7 : 1; 227 | uint32_t CHSEL8 : 1; 228 | uint32_t CHSEL9 : 1; 229 | uint32_t CHSEL10 : 1; 230 | uint32_t CHSEL11 : 1; 231 | uint32_t CHSEL12 : 1; 232 | uint32_t CHSEL13 : 1; 233 | uint32_t CHSEL14 : 1; 234 | uint32_t CHSEL15 : 1; 235 | uint32_t CHSEL16 : 1; 236 | uint32_t CHSEL17 : 1; 237 | uint32_t CHSEL18 : 1; 238 | uint32_t : 13; 239 | }; 240 | 241 | union { 242 | uint32_t r; 243 | Bits b; 244 | }; 245 | 246 | inline void set(const uint32_t ch) volatile { 247 | r |= static_cast(1 << ch); 248 | } 249 | 250 | inline void clr(const uint32_t ch) volatile { 251 | r &= ~static_cast(1 << ch); 252 | } 253 | }; 254 | 255 | /** Data register 256 | */ 257 | struct Dr { 258 | union { 259 | uint32_t r; 260 | const uint32_t DATA; // Converted data 261 | }; 262 | }; 263 | 264 | /** Calibration factor register (L0) 265 | */ 266 | struct Calfactr { 267 | Calfactr(const uint32_t raw=0) { r = raw; } 268 | 269 | struct Bits { 270 | uint32_t CALFACT : 7; // Calibration factor 271 | uint32_t : 25; 272 | }; 273 | 274 | union { 275 | uint32_t r; 276 | Bits b; 277 | }; 278 | }; 279 | 280 | /** Common configuration register 281 | */ 282 | struct Ccr { 283 | Ccr(const uint32_t raw=0) { r = raw; } 284 | 285 | struct Bits { 286 | uint32_t : 22; 287 | uint32_t VREFEN : 1; // VREFINT enable 288 | uint32_t TSEN : 1; // Temperature sensor enable 289 | uint32_t VBATEN : 1; // VBAT enable 290 | uint32_t : 7; 291 | }; 292 | 293 | union { 294 | uint32_t r; 295 | Bits b; 296 | }; 297 | }; 298 | 299 | volatile Isr ISR; // Interrupt and status register 300 | volatile Ier IER; // Interrupt enable register 301 | volatile Cr CR; // Control register 302 | volatile Cfgr1 CFGR1; // Configuration register 1 303 | volatile Cfgr2 CFGR2; // Configuration register 2 304 | volatile Smpr SMPR; // Sampling time register 305 | uint32_t __res0[2]; 306 | volatile Tr TR; // Watchdog threshold register 307 | uint32_t __res1; 308 | volatile Chselr CHSELR; // Channel selection register 309 | uint32_t __res2[5]; 310 | volatile Dr DR; // Data register 311 | uint32_t __res3[28]; 312 | volatile Calfactr CALFACTR; // Calibration factor register (L0) 313 | uint32_t __res4[148]; 314 | volatile Ccr CCR; // Commong configuration register 315 | }; 316 | 317 | } 318 | -------------------------------------------------------------------------------- /reg/stm32/_common/dma_v1.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * DMA - Direct Memory Access 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F1xx 9 | * - STM32F3xx 10 | * - STM32L0xx 11 | * - STM32L1xx 12 | * - STM32L4xx 13 | */ 14 | 15 | #pragma once 16 | 17 | #include 18 | #include 19 | 20 | namespace io { 21 | 22 | struct Dma { 23 | /** Interrupt status register 24 | */ 25 | struct Isr { 26 | Isr(const uint32_t raw=0) { r = raw; } 27 | 28 | struct Bits { 29 | const uint32_t GIF1 : 1; // Global Interrupt Flag 30 | const uint32_t TCIF1 : 1; // Transfer Complete Interrupt Flag 31 | const uint32_t HTIF1 : 1; // Half Transfer Interrupt Flag 32 | const uint32_t TEIF1 : 1; // Transfer Error Interrupt Flag 33 | const uint32_t GIF2 : 1; 34 | const uint32_t TCIF2 : 1; 35 | const uint32_t HTIF2 : 1; 36 | const uint32_t TEIF2 : 1; 37 | const uint32_t GIF3 : 1; 38 | const uint32_t TCIF3 : 1; 39 | const uint32_t HTIF3 : 1; 40 | const uint32_t TEIF3 : 1; 41 | const uint32_t GIF4 : 1; 42 | const uint32_t TCIF4 : 1; 43 | const uint32_t HTIF4 : 1; 44 | const uint32_t TEIF4 : 1; 45 | const uint32_t GIF5 : 1; 46 | const uint32_t TCIF5 : 1; 47 | const uint32_t HTIF5 : 1; 48 | const uint32_t TEIF5 : 1; 49 | const uint32_t GIF6 : 1; 50 | const uint32_t TCIF6 : 1; 51 | const uint32_t HTIF6 : 1; 52 | const uint32_t TEIF6 : 1; 53 | const uint32_t GIF7 : 1; 54 | const uint32_t TCIF7 : 1; 55 | const uint32_t HTIF7 : 1; 56 | const uint32_t TEIF7 : 1; 57 | uint32_t : 4; 58 | }; 59 | 60 | union { 61 | uint32_t r; 62 | Bits b; 63 | }; 64 | 65 | inline bool GIF(const unsigned channel) volatile const { 66 | return r & static_cast(1 << ((channel - 1) << 2)); 67 | } 68 | 69 | inline bool TCIF(const unsigned channel) volatile const { 70 | return r & static_cast(2 << ((channel - 1) << 2)); 71 | } 72 | 73 | inline bool HTIF(const unsigned channel) volatile const { 74 | return r & static_cast(4 << ((channel - 1) << 2)); 75 | } 76 | 77 | inline bool TEIF(const unsigned channel) volatile const { 78 | return r & static_cast(8 << ((channel - 1) << 2)); 79 | } 80 | }; 81 | 82 | /** Interrupt flag clear register 83 | */ 84 | struct Ifcr { 85 | Ifcr(const uint32_t raw=0) { r = raw; } 86 | 87 | struct Bits { 88 | uint32_t CGIF1 : 1; // Clear Global Interrupt Flag 89 | uint32_t CTCIF1 : 1; // Clear Transfer Complete Interrupt Flag 90 | uint32_t CHTIF1 : 1; // Clear Half Transfer Interrupt Flag 91 | uint32_t CTEIF1 : 1; // Clear Transfer Error Interrupt Flag 92 | uint32_t CGIF2 : 1; 93 | uint32_t CTCIF2 : 1; 94 | uint32_t CHTIF2 : 1; 95 | uint32_t CTEIF2 : 1; 96 | uint32_t CGIF3 : 1; 97 | uint32_t CTCIF3 : 1; 98 | uint32_t CHTIF3 : 1; 99 | uint32_t CTEIF3 : 1; 100 | uint32_t CGIF4 : 1; 101 | uint32_t CTCIF4 : 1; 102 | uint32_t CHTIF4 : 1; 103 | uint32_t CTEIF4 : 1; 104 | uint32_t CGIF5 : 1; 105 | uint32_t CTCIF5 : 1; 106 | uint32_t CHTIF5 : 1; 107 | uint32_t CTEIF5 : 1; 108 | uint32_t CGIF6 : 1; 109 | uint32_t CTCIF6 : 1; 110 | uint32_t CHTIF6 : 1; 111 | uint32_t CTEIF6 : 1; 112 | uint32_t CGIF7 : 1; 113 | uint32_t CTCIF7 : 1; 114 | uint32_t CHTIF7 : 1; 115 | uint32_t CTEIF7 : 1; 116 | uint32_t : 4; 117 | }; 118 | 119 | static const unsigned GIF = 1; 120 | static const unsigned TCIF = 2; 121 | static const unsigned HTIF = 4; 122 | static const unsigned TEIF = 8; 123 | 124 | union { 125 | uint32_t r; 126 | Bits b; 127 | }; 128 | 129 | inline void clear_flags(const unsigned channel, unsigned val=GIF | TCIF | HTIF | TEIF) volatile { 130 | r = val << ((channel - 1) << 2); 131 | } 132 | 133 | inline void CGIF(const unsigned channel) volatile { 134 | clear_flags(channel, GIF); 135 | } 136 | 137 | inline void CTCIF(const unsigned channel) volatile { 138 | clear_flags(channel, TCIF); 139 | } 140 | 141 | inline void CHTIF(const unsigned channel) volatile { 142 | clear_flags(channel, HTIF); 143 | } 144 | 145 | inline void CTEIF(const unsigned channel) volatile { 146 | clear_flags(channel, TEIF); 147 | } 148 | }; 149 | 150 | /** Channel registers 151 | */ 152 | struct Channel { 153 | /** Configuration register 154 | */ 155 | struct Ccr { 156 | Ccr(const uint32_t raw=0) { r = raw; } 157 | 158 | struct Bits { 159 | uint32_t EN : 1; // Channel Enable 160 | uint32_t TCIE : 1; // Transfer Complete Interrupt Enable 161 | uint32_t HTIE : 1; // Half Transfer Interrupt Enable 162 | uint32_t TEIE : 1; // Transfer Error Interrupt Enable 163 | uint32_t DIR : 1; // Direction (0: from peripheral, 1: from memory) 164 | uint32_t CIRC : 1; // Circular mode enable 165 | uint32_t PINC : 1; // Peripheral Increment mode enable 166 | uint32_t MINC : 1; // Memory Increment mode enable 167 | uint32_t PSIZE : 2; // Peripheral Size 168 | uint32_t MSIZE : 2; // Memory Size 169 | uint32_t PL : 2; // Channel Priority (0 - 3 : low - high) 170 | uint32_t MEM2MEM : 1; // Memory to Memory mode enable 171 | uint32_t : 17; 172 | }; 173 | 174 | enum class Size : uint32_t { 175 | SIZE_8 = 0, 176 | SIZE_16 = 1, 177 | SIZE_32 = 2, 178 | }; 179 | 180 | enum class Pl : uint32_t { 181 | LOW = 0, 182 | MEDIUM = 1, 183 | HIGH = 2, 184 | VERY_HIGH = 3, 185 | }; 186 | 187 | union { 188 | uint32_t r; 189 | Bits b; 190 | }; 191 | 192 | void PSIZE(Size size) { 193 | b.PSIZE = 0x03 & static_cast(size); 194 | } 195 | 196 | Size PSIZE() { 197 | return static_cast(b.PSIZE); 198 | } 199 | 200 | void MSIZE(Size size) { 201 | b.MSIZE = 0x03 & static_cast(size); 202 | } 203 | 204 | Size MSIZE() { 205 | return static_cast(b.MSIZE); 206 | } 207 | 208 | void PL(Pl pl) { 209 | b.PL = 0x03 & static_cast(pl); 210 | } 211 | 212 | Pl PL() { 213 | return static_cast(b.PL); 214 | } 215 | }; 216 | 217 | /** Number of data register 218 | */ 219 | struct Cndtr { 220 | union { 221 | uint32_t r; 222 | uint32_t NDT; // Number of Data to Transfer 223 | }; 224 | }; 225 | 226 | /** Peripheral address register 227 | */ 228 | struct Cpar { 229 | uint32_t r; 230 | 231 | template 232 | void PAR(T *par) volatile { 233 | r = reinterpret_cast(par); 234 | } 235 | }; 236 | 237 | /** Memory address register 238 | */ 239 | struct Cmar { 240 | uint32_t r; 241 | 242 | template 243 | void MAR(T *mar) volatile { 244 | r = reinterpret_cast(mar); 245 | } 246 | }; 247 | 248 | volatile Ccr CCR; // Configuration register 249 | volatile Cndtr CNDTR; // Number of data register 250 | volatile Cpar CPAR; // Peripheral address register 251 | volatile Cmar CMAR; // Memory address register 252 | uint32_t __res0; 253 | }; 254 | 255 | /** Selection Register 256 | */ 257 | struct Cselr { 258 | Cselr(const uint32_t raw=0) { r = raw; } 259 | 260 | struct Bits { 261 | uint32_t C1S : 4; 262 | uint32_t C2S : 4; 263 | uint32_t C3S : 4; 264 | uint32_t C4S : 4; 265 | uint32_t C5S : 4; 266 | uint32_t C6S : 4; 267 | uint32_t C7S : 4; 268 | uint32_t : 4; 269 | }; 270 | 271 | union { 272 | uint32_t r; 273 | Bits b; 274 | }; 275 | 276 | inline void set(const unsigned channel, const unsigned request) volatile { 277 | r &= ~static_cast(0x0f << (channel << 2)); 278 | r |= (request & 0x0f) << (channel << 2); 279 | } 280 | 281 | inline unsigned get(const unsigned channel) volatile const { 282 | return 0x0f & (r >> (channel << 2)); 283 | } 284 | }; 285 | 286 | volatile Isr ISR; // Interrupt status register 287 | volatile Ifcr IFCR; // Interrupt flag clear register 288 | Channel _CHANNEL[7]; // Channel registers 289 | uint32_t __res1[20]; 290 | volatile Cselr CSELR; // Selection Register 291 | 292 | Channel &CHANNEL(const unsigned channel) { 293 | return _CHANNEL[channel - 1]; 294 | } 295 | }; 296 | 297 | static inline constexpr Dma &DMA(const size_t base) { 298 | return *reinterpret_cast(base); 299 | } 300 | 301 | } 302 | -------------------------------------------------------------------------------- /reg/stm32/_common/exti.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * EXTI - External Interrupt 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F1xx 9 | * - STM32F2xx 10 | * - STM32F3xx 11 | * - STM32F4xx 12 | * - STM32F7xx 13 | * - STM32L0xx 14 | * - STM32L1xx 15 | * - STM32L4xx - has two EXTI units, see data-sheet 16 | */ 17 | 18 | #pragma once 19 | 20 | #include 21 | #include 22 | 23 | namespace io { 24 | 25 | struct Exti { 26 | /** Mask register 27 | */ 28 | struct Mr { 29 | Mr(const uint32_t raw=0) { r = raw; } 30 | 31 | struct Bits { 32 | uint32_t MR0 : 1; // Interrupt or Event mask on external/internal line 33 | uint32_t MR1 : 1; 34 | uint32_t MR2 : 1; 35 | uint32_t MR3 : 1; 36 | uint32_t MR4 : 1; 37 | uint32_t MR5 : 1; 38 | uint32_t MR6 : 1; 39 | uint32_t MR7 : 1; 40 | uint32_t MR8 : 1; 41 | uint32_t MR9 : 1; 42 | uint32_t MR10 : 1; 43 | uint32_t MR11 : 1; 44 | uint32_t MR12 : 1; 45 | uint32_t MR13 : 1; 46 | uint32_t MR14 : 1; 47 | uint32_t MR15 : 1; 48 | uint32_t MR16 : 1; 49 | uint32_t MR17 : 1; 50 | uint32_t MR18 : 1; 51 | uint32_t MR19 : 1; 52 | uint32_t MR20 : 1; 53 | uint32_t MR21 : 1; 54 | uint32_t MR22 : 1; 55 | uint32_t MR23 : 1; 56 | uint32_t MR24 : 1; 57 | uint32_t MR25 : 1; 58 | uint32_t MR26 : 1; 59 | uint32_t MR27 : 1; 60 | uint32_t MR28 : 1; 61 | uint32_t MR29 : 1; 62 | uint32_t MR30 : 1; 63 | uint32_t MR31 : 1; 64 | }; 65 | 66 | union { 67 | uint32_t r; 68 | Bits b; 69 | uint32_t MR; 70 | }; 71 | 72 | inline void set(const unsigned bit) volatile { 73 | MR |= 1 << bit; 74 | } 75 | 76 | inline void clr(const unsigned bit) volatile { 77 | MR &= ~(1 << bit); 78 | } 79 | 80 | inline void set(const unsigned bit, const bool val) volatile { 81 | if (val) set(bit); 82 | else clr(bit); 83 | } 84 | }; 85 | 86 | /** Trigger selection register 87 | */ 88 | struct Tr { 89 | Tr(const uint32_t raw=0) { r = raw; } 90 | 91 | struct Bits { 92 | uint32_t TR0 : 1; // Trigger event configuration bit of line 93 | uint32_t TR1 : 1; 94 | uint32_t TR2 : 1; 95 | uint32_t TR3 : 1; 96 | uint32_t TR4 : 1; 97 | uint32_t TR5 : 1; 98 | uint32_t TR6 : 1; 99 | uint32_t TR7 : 1; 100 | uint32_t TR8 : 1; 101 | uint32_t TR9 : 1; 102 | uint32_t TR10 : 1; 103 | uint32_t TR11 : 1; 104 | uint32_t TR12 : 1; 105 | uint32_t TR13 : 1; 106 | uint32_t TR14 : 1; 107 | uint32_t TR15 : 1; 108 | uint32_t TR16 : 1; 109 | uint32_t TR17 : 1; 110 | uint32_t TR18 : 1; 111 | uint32_t TR19 : 1; 112 | uint32_t TR20 : 1; 113 | uint32_t TR21 : 1; 114 | uint32_t TR22 : 1; 115 | uint32_t TR23 : 1; 116 | uint32_t TR24 : 1; 117 | uint32_t TR25 : 1; 118 | uint32_t TR26 : 1; 119 | uint32_t TR27 : 1; 120 | uint32_t TR28 : 1; 121 | uint32_t TR29 : 1; 122 | uint32_t TR30 : 1; 123 | uint32_t TR31 : 1; 124 | }; 125 | 126 | union { 127 | uint32_t r; 128 | Bits b; 129 | uint32_t TR; 130 | }; 131 | 132 | inline void set(const unsigned bit) volatile { 133 | TR |= 1 << bit; 134 | } 135 | 136 | inline void clr(const unsigned bit) volatile { 137 | TR &= ~(1 << bit); 138 | } 139 | 140 | inline void set(const unsigned bit, const bool val) volatile { 141 | if (val) set(bit); 142 | else clr(bit); 143 | } 144 | }; 145 | 146 | /** Software interrupt event register 147 | */ 148 | struct Swier { 149 | Swier(const uint32_t raw=0) { r = raw; } 150 | 151 | struct Bits { 152 | uint32_t SWIER0 : 1; // Software interrupt on line 153 | uint32_t SWIER1 : 1; 154 | uint32_t SWIER2 : 1; 155 | uint32_t SWIER3 : 1; 156 | uint32_t SWIER4 : 1; 157 | uint32_t SWIER5 : 1; 158 | uint32_t SWIER6 : 1; 159 | uint32_t SWIER7 : 1; 160 | uint32_t SWIER8 : 1; 161 | uint32_t SWIER9 : 1; 162 | uint32_t SWIER10 : 1; 163 | uint32_t SWIER11 : 1; 164 | uint32_t SWIER12 : 1; 165 | uint32_t SWIER13 : 1; 166 | uint32_t SWIER14 : 1; 167 | uint32_t SWIER15 : 1; 168 | uint32_t SWIER16 : 1; 169 | uint32_t SWIER17 : 1; 170 | uint32_t SWIER18 : 1; 171 | uint32_t SWIER19 : 1; 172 | uint32_t SWIER20 : 1; 173 | uint32_t SWIER21 : 1; 174 | uint32_t SWIER22 : 1; 175 | uint32_t SWIER23 : 1; 176 | uint32_t SWIER24 : 1; 177 | uint32_t SWIER25 : 1; 178 | uint32_t SWIER26 : 1; 179 | uint32_t SWIER27 : 1; 180 | uint32_t SWIER28 : 1; 181 | uint32_t SWIER29 : 1; 182 | uint32_t SWIER30 : 1; 183 | uint32_t SWIER31 : 1; 184 | }; 185 | 186 | union { 187 | uint32_t r; 188 | Bits b; 189 | uint32_t SWIER; 190 | }; 191 | 192 | inline void set(const unsigned bit) volatile { 193 | SWIER |= 1 << bit; 194 | } 195 | 196 | inline void clr(const unsigned bit) volatile { 197 | SWIER &= ~(1 << bit); 198 | } 199 | 200 | inline void set(const unsigned bit, const bool val) volatile { 201 | if (val) set(bit); 202 | else clr(bit); 203 | } 204 | }; 205 | 206 | /** Pending register 207 | */ 208 | struct Pr { 209 | Pr(const uint32_t raw=0) { r = raw; } 210 | 211 | struct Bits { 212 | uint32_t PR0 : 1; // Pending bit on line 213 | uint32_t PR1 : 1; 214 | uint32_t PR2 : 1; 215 | uint32_t PR3 : 1; 216 | uint32_t PR4 : 1; 217 | uint32_t PR5 : 1; 218 | uint32_t PR6 : 1; 219 | uint32_t PR7 : 1; 220 | uint32_t PR8 : 1; 221 | uint32_t PR9 : 1; 222 | uint32_t PR10 : 1; 223 | uint32_t PR11 : 1; 224 | uint32_t PR12 : 1; 225 | uint32_t PR13 : 1; 226 | uint32_t PR14 : 1; 227 | uint32_t PR15 : 1; 228 | uint32_t PR16 : 1; 229 | uint32_t PR17 : 1; 230 | uint32_t PR18 : 1; 231 | uint32_t PR19 : 1; 232 | uint32_t PR20 : 1; 233 | uint32_t PR21 : 1; 234 | uint32_t PR22 : 1; 235 | uint32_t PR23 : 1; 236 | uint32_t PR24 : 1; 237 | uint32_t PR25 : 1; 238 | uint32_t PR26 : 1; 239 | uint32_t PR27 : 1; 240 | uint32_t PR28 : 1; 241 | uint32_t PR29 : 1; 242 | uint32_t PR30 : 1; 243 | uint32_t PR31 : 1; 244 | }; 245 | 246 | union { 247 | uint32_t r; 248 | Bits b; 249 | uint32_t PR; 250 | }; 251 | 252 | inline void clr(const unsigned bit) volatile { 253 | PR = 1 << bit; 254 | } 255 | 256 | inline bool get(const unsigned pin) volatile const { 257 | return 1 & (PR >> pin); 258 | } 259 | }; 260 | 261 | volatile Mr IMR; // Interrupt mask register 262 | volatile Mr EMR; // Event mask register 263 | volatile Tr RTSR; // Rising trigger selection register 264 | volatile Tr FTSR; // Falling trigger selection register 265 | volatile Swier SWIER; // Software interrupt event register 266 | volatile Pr PR; // Pending register 267 | }; 268 | 269 | } 270 | -------------------------------------------------------------------------------- /reg/stm32/_common/i2c_v2.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * I2C - Inter-integrated circuit interface 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F3xx 9 | * - STM32F7xx 10 | * - STM32H7xx 11 | * - STM32L0xx 12 | * - STM32L4xx 13 | */ 14 | 15 | #pragma once 16 | 17 | #include 18 | #include 19 | 20 | namespace io { 21 | 22 | struct I2c { 23 | /** Control register 1 24 | */ 25 | struct Cr1 { 26 | Cr1(const uint32_t raw=0) { r = raw; } 27 | 28 | struct Bits { 29 | uint32_t PE : 1; // Peripheral enable 30 | uint32_t TXIE : 1; // TX Interrupt enable 31 | uint32_t RXIE : 1; // RX Interrupt enable 32 | uint32_t ADDRIE : 1; // Address match Interrupt enable (slave only) 33 | uint32_t NACKIE : 1; // Not acknowledge received Interrupt enable 34 | uint32_t STOPIE : 1; // STOP detection Interrupt enable 35 | uint32_t TCIE : 1; // Transfer Complete interrupt enable 36 | uint32_t ERRIE : 1; // Error interrupts enable 37 | uint32_t DNF : 4; // Digital noise filter 38 | uint32_t ANF : 1; // Analog noise filter OFF 39 | uint32_t : 1; 40 | uint32_t TXDMAEN : 1; // DMA transmission requests enable 41 | uint32_t RXDMAEN : 1; // DMA reception requests enable 42 | uint32_t SBC : 1; // Slave byte control 43 | uint32_t NOSTRETCH : 1; // Clock stretching disable 44 | uint32_t WUPEN : 1; // Wakeup from Stop mode enable // F0, F3, H7, L0, L4 45 | uint32_t GCEN : 1; // General call enable 46 | uint32_t SMBHEN : 1; // SMBus Host address enable 47 | uint32_t SMBDEN : 1; // SMBus Device Default address enable 48 | uint32_t ALERTEN : 1; // SMBus alert enable 49 | uint32_t PECEN : 1; // PEC enable 50 | uint32_t : 8; 51 | }; 52 | 53 | union { 54 | uint32_t r; 55 | Bits b; 56 | }; 57 | }; 58 | 59 | /** Control register 2 60 | */ 61 | struct Cr2 { 62 | Cr2(const uint32_t raw=0) { r = raw; } 63 | 64 | struct Bits { 65 | uint32_t SADD : 10; // Slave address 66 | uint32_t RD_WRN : 1; // Transfer direction (master mode) 67 | uint32_t ADD10 : 1; // 10-bit addressing mode (master mode) 68 | uint32_t HEAD10R : 1; // 10-bit address header only read direction (master receiver mode) 69 | uint32_t START : 1; // Start generation 70 | uint32_t STOP : 1; // Stop generation (master mode) 71 | uint32_t NACK : 1; // NACK generation (slave mode) 72 | uint32_t NBYTES : 8; // Number of bytes 73 | uint32_t RELOAD : 1; // NBYTES reload mode 74 | uint32_t AUTOEND : 1; // Automatic end mode (master mode) 75 | uint32_t PECBYTE : 1; // Packet error checking byte 76 | uint32_t : 5; 77 | }; 78 | 79 | union { 80 | uint32_t r; 81 | Bits b; 82 | }; 83 | }; 84 | 85 | /** Own address 1 register 86 | */ 87 | struct Oar1 { 88 | Oar1(const uint32_t raw=0) { r = raw; } 89 | 90 | struct Bits { 91 | uint32_t OA1 : 10; // Interface address 92 | uint32_t OA1MODE : 1; // Own Address 1 10-bit mode 93 | uint32_t : 4; 94 | uint32_t OA1EN : 1; // Own Address 1 enable 95 | uint32_t : 16; 96 | }; 97 | 98 | union { 99 | uint32_t r; 100 | Bits b; 101 | }; 102 | }; 103 | 104 | /** Own address 2 register 105 | */ 106 | struct Oar2 { 107 | Oar2(const uint32_t raw=0) { r = raw; } 108 | 109 | struct Bits { 110 | uint32_t : 1; 111 | uint32_t OA2 : 7; // Interface address 112 | uint32_t OA2MASK : 3; // Own Address 2 masks 113 | uint32_t : 4; 114 | uint32_t OA2EN : 1; // Own Address 2 enable 115 | uint32_t : 16; 116 | }; 117 | 118 | union { 119 | uint32_t r; 120 | Bits b; 121 | }; 122 | }; 123 | 124 | /** Timing register 125 | */ 126 | struct Timingr { 127 | Timingr(const uint32_t raw=0) { r = raw; } 128 | 129 | struct Bits { 130 | uint32_t SCLL : 8; // SCL low period (master mode) 131 | uint32_t SCLH : 8; // SCL high period (master mode) 132 | uint32_t SDADEL : 4; // Data hold time 133 | uint32_t SCLDEL : 4; // Data setup time 134 | uint32_t : 4; 135 | uint32_t PRESC : 4; // Timing prescaler 136 | }; 137 | 138 | union { 139 | uint32_t r; 140 | Bits b; 141 | }; 142 | }; 143 | 144 | /** Timeout register 145 | */ 146 | struct Timeoutr { 147 | Timeoutr(const uint32_t raw=0) { r = raw; } 148 | 149 | struct Bits { 150 | uint32_t TIMEOUTA : 12; // Bus Timeout A 151 | uint32_t TIDLE : 1; // Idle clock timeout detection 152 | uint32_t : 2; 153 | uint32_t TIMEOUTEN : 1; // Clock timeout enable 154 | uint32_t TIMEOUTB : 12; // Bus timeout B 155 | uint32_t : 3; 156 | uint32_t TEXTEN : 1; // Extended clock timeout enable 157 | }; 158 | 159 | union { 160 | uint32_t r; 161 | Bits b; 162 | }; 163 | }; 164 | 165 | /** Interrupt and status register 166 | */ 167 | struct Isr { 168 | Isr(const uint32_t raw=0) { r = raw; } 169 | 170 | struct Bits { 171 | uint32_t TXE : 1; // Transmit data register empty (transmitters) 172 | uint32_t TXIS : 1; // Transmit interrupt status (transmitters) 173 | const uint32_t RXNE : 1; // Receive data register not empty (receivers) 174 | const uint32_t ADDR : 1; // Address matched (slave mode) 175 | const uint32_t NACKF : 1; // Not Acknowledge received flag 176 | const uint32_t STOPF : 1; // Stop detection flag 177 | const uint32_t TC : 1; // Transfer Complete (master mode) 178 | const uint32_t TCR : 1; // Transfer Complete Reload 179 | const uint32_t BERR : 1; // Bus error 180 | const uint32_t ARLO : 1; // Arbitration lost 181 | const uint32_t OVR : 1; // Overrun/Underrun (slave mode) 182 | const uint32_t PECERR : 1; // PEC Error in reception 183 | const uint32_t TIMEOUT : 1; // Timeout or tLOW detection flag 184 | const uint32_t ALERT : 1; // SMBus alert 185 | const uint32_t : 1; 186 | const uint32_t BUSY : 1; // Bus busy 187 | const uint32_t DIR : 1; // Transfer direction (Slave mode) 188 | const uint32_t ADDCODE : 7; // Address match code (Slave mode) 189 | uint32_t : 8; 190 | }; 191 | 192 | union { 193 | uint32_t r; 194 | Bits b; 195 | }; 196 | }; 197 | 198 | /** Interrupt clear register 199 | */ 200 | struct Icr { 201 | Icr(const uint32_t raw=0) { r = raw; } 202 | 203 | struct Bits { 204 | uint32_t : 3; 205 | uint32_t ADDRCF : 1; // Address Matched flag clear 206 | uint32_t NACKCF : 1; // Not Acknowledge flag clear 207 | uint32_t STOPCF : 1; // Stop detection flag clear 208 | uint32_t : 2; 209 | uint32_t BERRCF : 1; // Bus error flag clear 210 | uint32_t ARLOCF : 1; // Arbitration Lost flag clea 211 | uint32_t OVRCF : 1; // Overrun/Underrun flag clear 212 | uint32_t PECCF : 1; // PEC Error flag clear 213 | uint32_t TIMOUTCF : 1; // Timeout detection flag clear 214 | uint32_t ALERTCF : 1; // Alert flag clear 215 | uint32_t : 18; 216 | }; 217 | 218 | union { 219 | uint32_t r; 220 | Bits b; 221 | }; 222 | }; 223 | 224 | /** Packet error checking register 225 | */ 226 | struct Pecr { 227 | union { 228 | uint32_t r; 229 | uint32_t PEC; // Packet error checking register (8-bit used) 230 | }; 231 | }; 232 | 233 | /** Receive data register 234 | */ 235 | struct Rxdr { 236 | union { 237 | uint32_t r; 238 | uint32_t RXDATA; // 8-bit receive data 239 | }; 240 | }; 241 | 242 | /** Transmit data register 243 | */ 244 | struct Txdr { 245 | union { 246 | uint32_t r; 247 | uint32_t TXDATA; // 8-bit transmit data 248 | }; 249 | }; 250 | 251 | volatile Cr1 CR1; // Control register 1 252 | volatile Cr2 CR2; // Control register 2 253 | volatile Oar1 OAR1; // Own address 1 register 254 | volatile Oar2 OAR2; // Own address 2 register 255 | volatile Timingr TIMINGR; // Timing register 256 | volatile Timeoutr TIMEOUTR; // Timeout register 257 | volatile Isr ISR; // Interrupt and status register 258 | volatile Icr ICR; // Interrupt clear register 259 | volatile Pecr PECR; // Packet error checking register 260 | volatile Rxdr RXDR; // Receive data register 261 | volatile Txdr TXDR; // Transmit data register 262 | }; 263 | 264 | static inline constexpr I2c &I2C(const size_t base) { 265 | return *reinterpret_cast(base); 266 | } 267 | 268 | } 269 | -------------------------------------------------------------------------------- /reg/stm32/_common/iwdg_v1.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F1xx 8 | * - STM32F2xx 9 | * - STM32F4xx 10 | * - STM32L1xx 11 | */ 12 | 13 | #pragma once 14 | 15 | #include 16 | #include 17 | 18 | namespace io { 19 | 20 | struct Iwdg { 21 | /** Key register 22 | */ 23 | struct Kr { 24 | Kr(const uint32_t raw=0) { r = raw; } 25 | 26 | static const uint32_t WRITE_ACCESS = 0x00005555; 27 | static const uint32_t REFRESH = 0x0000aaaa; 28 | static const uint32_t START = 0x0000cccc; 29 | 30 | union { 31 | uint32_t r; 32 | uint32_t KEY; // Key value 33 | uint16_t KEY16; // 16 bit access 34 | }; 35 | }; 36 | 37 | /** Prescaler register 38 | */ 39 | struct Pr { 40 | Pr(const uint32_t raw=0) { r = raw; } 41 | 42 | struct Bits { 43 | uint32_t PRE : 3; // prescaler divider 44 | uint32_t : 29; 45 | }; 46 | 47 | struct Pre { 48 | static const uint32_t DIV_4 = 0; 49 | static const uint32_t DIV_8 = 1; 50 | static const uint32_t DIV_16 = 2; 51 | static const uint32_t DIV_32 = 3; 52 | static const uint32_t DIV_64 = 4; 53 | static const uint32_t DIV_128 = 5; 54 | static const uint32_t DIV_256 = 6; 55 | }; 56 | 57 | union { 58 | uint32_t r; 59 | uint32_t PRE; // 32 bit access 60 | uint16_t PRE16; // 16 bit access 61 | Bits b; 62 | }; 63 | }; 64 | 65 | /** Reload register 66 | */ 67 | struct Rlr { 68 | Rlr(const uint32_t raw=0) { r = raw; } 69 | 70 | struct Bits { 71 | uint32_t RL : 12; // Watchdog counter reload value 72 | uint32_t : 20; 73 | }; 74 | 75 | union { 76 | uint32_t r; 77 | uint32_t RL; // 32 bit access 78 | uint16_t RL16; // 16 bit access 79 | Bits b; 80 | }; 81 | }; 82 | 83 | /** Status register 84 | */ 85 | struct Sr { 86 | Sr(const uint32_t raw=0) { r = raw; } 87 | 88 | struct Bits { 89 | const uint32_t PVU : 1; // Watchdog prescaler value update 90 | const uint32_t RVU : 1; // Watchdog counter reload value update 91 | uint32_t : 30; 92 | }; 93 | 94 | union { 95 | uint32_t r; 96 | Bits b; 97 | }; 98 | }; 99 | 100 | volatile Kr KR; // Key register 101 | volatile Pr PR; // Prescaler register 102 | volatile Rlr RLR; // Reload register 103 | volatile Sr SR; // Status register 104 | }; 105 | 106 | } 107 | -------------------------------------------------------------------------------- /reg/stm32/_common/iwdg_v2.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F3xx 9 | * - STM32F7xx 10 | * - STM32H7xx 11 | * - STM32L0xx 12 | * - STM32L4xx 13 | */ 14 | 15 | #pragma once 16 | 17 | #include 18 | #include 19 | 20 | namespace io { 21 | 22 | struct Iwdg { 23 | /** Key register 24 | */ 25 | struct Kr { 26 | Kr(const uint32_t raw=0) { r = raw; } 27 | 28 | static const uint32_t WRITE_ACCESS = 0x00005555; 29 | static const uint32_t REFRESH = 0x0000aaaa; 30 | static const uint32_t START = 0x0000cccc; 31 | 32 | union { 33 | uint32_t r; 34 | uint32_t KEY; // Key value 35 | uint16_t KEY16; // 16 bit access 36 | }; 37 | }; 38 | 39 | /** Prescaler register 40 | */ 41 | struct Pr { 42 | Pr(const uint32_t raw=0) { r = raw; } 43 | 44 | struct Bits { 45 | uint32_t PRE : 3; // prescaler divider 46 | uint32_t : 29; 47 | }; 48 | 49 | struct Pre { 50 | static const uint32_t DIV_4 = 0; 51 | static const uint32_t DIV_8 = 1; 52 | static const uint32_t DIV_16 = 2; 53 | static const uint32_t DIV_32 = 3; 54 | static const uint32_t DIV_64 = 4; 55 | static const uint32_t DIV_128 = 5; 56 | static const uint32_t DIV_256 = 6; 57 | }; 58 | 59 | union { 60 | uint32_t r; 61 | uint32_t PRE; // 32 bit access 62 | uint16_t PRE16; // 16 bit access 63 | Bits b; 64 | }; 65 | }; 66 | 67 | /** Reload register 68 | */ 69 | struct Rlr { 70 | Rlr(const uint32_t raw=0) { r = raw; } 71 | 72 | struct Bits { 73 | uint32_t RL : 12; // Watchdog counter reload value 74 | uint32_t : 20; 75 | }; 76 | 77 | struct Rl { 78 | static const uint32_t MAX = 0x00000fff; 79 | }; 80 | 81 | union { 82 | uint32_t r; 83 | uint32_t RL; // 32 bit access 84 | uint16_t RL16; // 16 bit access 85 | Bits b; 86 | }; 87 | }; 88 | 89 | /** Status register 90 | */ 91 | struct Sr { 92 | Sr(const uint32_t raw=0) { r = raw; } 93 | 94 | struct Bits { 95 | const uint32_t PVU : 1; // Watchdog prescaler value update 96 | const uint32_t RVU : 1; // Watchdog counter reload value update 97 | const uint32_t WVU : 1; // Watchdog counter window value update 98 | uint32_t : 29; 99 | }; 100 | 101 | union { 102 | uint32_t r; 103 | Bits b; 104 | }; 105 | }; 106 | 107 | /** Window register 108 | */ 109 | struct Winr { 110 | Winr(const uint32_t raw=0) { r = raw; } 111 | 112 | struct Bits { 113 | uint32_t WIN : 12; // Watchdog counter reload value 114 | uint32_t : 20; 115 | }; 116 | 117 | union { 118 | uint32_t r; 119 | uint32_t WIN; // Key value 120 | uint16_t WIN16; // 16 bit access 121 | Bits b; 122 | }; 123 | }; 124 | 125 | volatile Kr KR; // Key register 126 | volatile Pr PR; // Prescaler register 127 | volatile Rlr RLR; // Reload register 128 | volatile Sr SR; // Status register 129 | volatile Winr WINR; // Window register 130 | }; 131 | 132 | } 133 | -------------------------------------------------------------------------------- /reg/stm32/_common/rtc_v2.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * RTC - Real-time clock 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F2xx (partial support) 9 | * - STM32F3xx 10 | * - STM32F4xx (partial support) 11 | * - STM32F46+ 12 | * - STM32F7xx (partial support) 13 | * - STM32H7xx (partial support) 14 | * - STM32L0xx (partial support) 15 | * - STM32L1xx (partial support) 16 | * - STM32L4xx (partial support) 17 | */ 18 | 19 | #pragma once 20 | 21 | #include 22 | #include 23 | 24 | namespace io { 25 | 26 | struct Rtc { 27 | /** Time register 28 | */ 29 | struct Tr { 30 | Tr(const uint32_t raw=0) { r = raw; } 31 | 32 | struct Bits { 33 | uint32_t SU : 4; // Second units in BCD format 34 | uint32_t ST : 3; // Second tens in BCD format 35 | uint32_t : 1; 36 | uint32_t MNU : 4; // Minute units in BCD format 37 | uint32_t MNT : 3; // Minute tens in BCD format 38 | uint32_t : 1; 39 | uint32_t HU : 4; // Hour units in BCD format 40 | uint32_t HT : 2; // Hour tens in BCD format 41 | uint32_t PM : 1; // AM/PM notation 42 | uint32_t : 9; 43 | }; 44 | 45 | union { 46 | uint32_t r; 47 | Bits b; 48 | }; 49 | }; 50 | 51 | /** Date register 52 | */ 53 | struct Dr { 54 | Dr(const uint32_t raw=0) { r = raw; } 55 | 56 | struct Bits { 57 | uint32_t DU : 4; // Date units in BCD format 58 | uint32_t DT : 2; // Date tens in BCD format 59 | uint32_t : 2; 60 | uint32_t MU : 4; // Month units in BCD format 61 | uint32_t MT : 1; // Month tens in BCD format 62 | uint32_t WDU : 3; // Week day units 63 | uint32_t YU : 4; // Year units in BCD format 64 | uint32_t YT : 4; // Year tens in BCD format 65 | uint32_t : 8; 66 | }; 67 | 68 | union { 69 | uint32_t r; 70 | Bits b; 71 | }; 72 | }; 73 | 74 | /** Control register 75 | */ 76 | struct Cr { 77 | Cr(const uint32_t raw=0) { r = raw; } 78 | 79 | struct Bits { 80 | uint32_t WUCKSEL : 3; // Wakeup clock selection 81 | uint32_t TSEDGE : 1; // Time-stamp event active edge 82 | uint32_t REFCKON : 1; // RTC_REFIN reference clock detection enable 83 | uint32_t BYPSHAD : 1; // Bypass the shadow register (F0, F3, F4, F7, H7, L0, L1, L4) 84 | uint32_t FMT : 1; // Hour format 85 | uint32_t DCE : 1; // Coarse digital calibration enable (F2, F4, L1) 86 | uint32_t ALRAE : 1; // Alarm A enable 87 | uint32_t ALRBE : 1; // Alarm B enable (F2, F3, F4, F7, H7, L0, L1, L4) 88 | uint32_t WUTE : 1; // Wakeup timer enable 89 | uint32_t TSE : 1; // Time-stamp enable 90 | uint32_t ALRAIE : 1; // Alarm A interrupt enable 91 | uint32_t ALRBIE : 1; // Alarm B interrupt enable (F2, F3, F4, F7, H7, L0, L1, L4) 92 | uint32_t WUTIE : 1; // Wakeup timer interrupt enable 93 | uint32_t TSIE : 1; // Time-stamp interrupt enable 94 | uint32_t ADD1H : 1; // Add one hour 95 | uint32_t SUB1H : 1; // Subtract 1 hour 96 | uint32_t BKP : 1; // Backup 97 | uint32_t COSEL : 1; // Calibration output selection (F0, F4, F7, H7, L0, L1, L4) 98 | uint32_t POL : 1; // Output polarity 99 | uint32_t OSEL : 2; // Output selection 100 | uint32_t COE : 1; // Calibration output enable 101 | uint32_t ITSE : 1; // Time-stamp on internal event enable (F7, H7, L4) 102 | uint32_t : 7; 103 | }; 104 | 105 | union { 106 | uint32_t r; 107 | Bits b; 108 | }; 109 | struct Fmt { 110 | static const uint32_t HF24 = 0; 111 | static const uint32_t HF12 = 1; 112 | }; 113 | struct Wucksel { 114 | static const uint32_t RTC_16 = 0; 115 | static const uint32_t RTC_8 = 1; 116 | static const uint32_t RTC_4 = 2; 117 | static const uint32_t RTC_2 = 3; 118 | static const uint32_t CK_SPRE = 4; 119 | static const uint32_t CK_SPRE_2_16 = 6; 120 | }; 121 | }; 122 | 123 | /** Initialization and status register 124 | */ 125 | struct Isr { 126 | Isr(const uint32_t raw=0) { r = raw; } 127 | 128 | struct Bits { 129 | const uint32_t ALRAWF : 1; // Alarm A write flag 130 | const uint32_t ALRBWF : 1; // Alarm B write flag (F2, F3, F4, F7, H7, L0, L1, L4) 131 | const uint32_t WUTWF : 1; // Wakeup timer write flag 132 | const uint32_t SHPF : 1; // Shift operation pending (F0, F3, F4, F7, H7, L0, L1, L4) 133 | const uint32_t INITS : 1; // Initialization status flag 134 | uint32_t RSF : 1; // Registers synchronization flag 135 | const uint32_t INITF : 1; // Initialization flag 136 | uint32_t INIT : 1; // Initialization mode 137 | uint32_t ALRAF : 1; // Alarm A flag 138 | uint32_t ALRBF : 1; // Alarm B flag (F2, F3, F4, F7, H7, L0, L1, L4) 139 | uint32_t WUTF : 1; // Wakeup timer flag 140 | uint32_t TSF : 1; // Time-stamp flag 141 | uint32_t TSOVF : 1; // Time-stamp overflow flag 142 | uint32_t TAMP1F : 1; // RTC_TAMP1 detection flag 143 | uint32_t TAMP2F : 1; // RTC_TAMP2 detection flag (F0, F3, F4, F7, H7, L0, L1, L4) 144 | uint32_t TAMP3F : 1; // RTC_TAMP3 detection flag (F0, F3, F4, F7, H7, L0, L1, L4) 145 | const uint32_t RECALPF : 1; // Recalibration pending Flag (F0, F3, F4, F7, H7, L0, L1, L4) 146 | uint32_t ITSF : 1; // Internal Time-stamp flag (F7, H7, L4) 147 | uint32_t : 14; 148 | }; 149 | 150 | union { 151 | uint32_t r; 152 | Bits b; 153 | }; 154 | }; 155 | 156 | /** Prescaler register 157 | */ 158 | struct Prer { 159 | Prer(const uint32_t raw=0) { r = raw; } 160 | 161 | struct Bits { 162 | uint32_t PREDIV_S : 15; // Asynchronous prescaler factor 163 | uint32_t : 1; 164 | uint32_t PREDIV_A : 7; // Synchronous prescaler factor 165 | uint32_t : 9; 166 | }; 167 | 168 | union { 169 | uint32_t r; 170 | Bits b; 171 | }; 172 | }; 173 | 174 | /** Wakeup timer register 175 | */ 176 | struct Wutr { 177 | Wutr(const uint32_t raw=0) { r = raw; } 178 | 179 | struct Bits { 180 | uint32_t WUT : 16; // Wakeup auto-reload value 181 | uint32_t : 16; 182 | }; 183 | 184 | union { 185 | uint32_t r; 186 | uint32_t WUT; 187 | Bits b; 188 | }; 189 | }; 190 | 191 | /** Calibration register (F2, F4, L1) 192 | */ 193 | struct Calibr { 194 | Calibr(const uint32_t raw=0) { r = raw; } 195 | 196 | struct Bits { 197 | uint32_t DC : 5; // Digital calibration 198 | uint32_t : 2; 199 | uint32_t DCS : 1; // Digital calibration sign 200 | uint32_t : 24; 201 | }; 202 | 203 | union { 204 | uint32_t r; 205 | Bits b; 206 | }; 207 | }; 208 | 209 | /** Alarm register 210 | */ 211 | struct Alarmr { 212 | Alarmr(const uint32_t raw=0) { r = raw; } 213 | 214 | struct Bits { 215 | uint32_t SU : 4; // Second units in BCD format 216 | uint32_t ST : 3; // Second tens in BCD format 217 | uint32_t MSK1 : 1; // Alarm A seconds mask 218 | uint32_t MNU : 4; // Minute units in BCD format 219 | uint32_t MNT : 3; // Minute tens in BCD format 220 | uint32_t MSK2 : 1; // Alarm A minutes mask 221 | uint32_t HU : 4; // Hour units in BCD format 222 | uint32_t HT : 2; // Hour tens in BCD format 223 | uint32_t PM : 1; // AM/PM notation 224 | uint32_t MSK3 : 1; // Alarm A hour mask 225 | uint32_t DU : 4; // Date units in BCD format 226 | uint32_t DT : 2; // Date tens in BCD format 227 | uint32_t WDSEL : 1; // Week day selection 228 | uint32_t MSK4 : 1; // Alarm A date mask 229 | }; 230 | 231 | union { 232 | uint32_t r; 233 | Bits b; 234 | }; 235 | }; 236 | 237 | /** Write protection register 238 | */ 239 | struct Wpr { 240 | Wpr(const uint32_t raw=0) { r = raw; } 241 | 242 | struct Bits { 243 | uint32_t KEY : 8; // Write protection key 244 | uint32_t : 24; 245 | }; 246 | 247 | union { 248 | uint32_t r; 249 | uint32_t KEY; 250 | Bits b; 251 | }; 252 | }; 253 | 254 | /** Sub second register (F0, F3, F4, F7, H7, L0, L1, L4) 255 | */ 256 | struct Ssr { 257 | Ssr(const uint32_t raw=0) { r = raw; } 258 | 259 | struct Bits { 260 | const uint32_t SS : 16; // sub seconds 261 | uint32_t : 16; 262 | }; 263 | 264 | union { 265 | uint32_t r; 266 | Bits b; 267 | }; 268 | }; 269 | 270 | /** Shift control register (F0, F3, F4, F7, H7, L0, L1, L4) 271 | */ 272 | struct Shiftr { 273 | Shiftr(const uint32_t raw=0) { r = raw; } 274 | 275 | struct Bits { 276 | uint32_t SUBFS : 15; // Subtract a fraction of a second 277 | uint32_t : 16; 278 | uint32_t ADD1S : 1; // Add one second 279 | }; 280 | 281 | union { 282 | uint32_t r; 283 | Bits b; 284 | }; 285 | }; 286 | 287 | /** Time-stamp time register 288 | */ 289 | struct Tstr { 290 | Tstr(const uint32_t raw=0) { r = raw; } 291 | 292 | struct Bits { 293 | const uint32_t SU : 4; // Second units in BCD format 294 | const uint32_t ST : 3; // Second tens in BCD format 295 | uint32_t : 1; 296 | const uint32_t MNU : 4; // Minute units in BCD format 297 | const uint32_t MNT : 3; // Minute tens in BCD format 298 | uint32_t : 1; 299 | const uint32_t HU : 4; // Hour units in BCD format 300 | const uint32_t HT : 2; // Hour tens in BCD format 301 | const uint32_t PM : 1; // AM/PM notation 302 | uint32_t : 9; 303 | }; 304 | 305 | union { 306 | uint32_t r; 307 | Bits b; 308 | }; 309 | }; 310 | 311 | /** Time-stamp date register 312 | */ 313 | struct Tsdr { 314 | Tsdr(const uint32_t raw=0) { r = raw; } 315 | 316 | struct Bits { 317 | const uint32_t DU : 4; // Date units in BCD format 318 | const uint32_t DT : 2; // Date tens in BCD format 319 | uint32_t : 2; 320 | const uint32_t MU : 4; // Month units in BCD format 321 | const uint32_t MT : 1; // Month tens in BCD format 322 | const uint32_t WDU : 3; // Week day units 323 | uint32_t : 16; 324 | }; 325 | 326 | union { 327 | uint32_t r; 328 | Bits b; 329 | }; 330 | }; 331 | 332 | /** Time-stamp sub second register (F0, F3, F4, F7, H7, L0, L1, L4) 333 | */ 334 | struct Tsssr { 335 | Tsssr(const uint32_t raw=0) { r = raw; } 336 | 337 | struct Bits { 338 | const uint32_t SS : 16; // sub seconds 339 | uint32_t : 16; 340 | }; 341 | 342 | union { 343 | uint32_t r; 344 | Bits b; 345 | }; 346 | }; 347 | 348 | /** Calibration register (F0, F3, F4, F7, H7, L0, L1, L4) 349 | */ 350 | struct Calr { 351 | Calr(const uint32_t raw=0) { r = raw; } 352 | 353 | struct Bits { 354 | uint32_t CALM : 9; // calibration minus 355 | uint32_t : 4; 356 | uint32_t CALW16 : 1; // Use a 16-second calibration cycle period 357 | uint32_t CALW8 : 1; // Use an 8-second calibration cycle period 358 | uint32_t CALP : 1; // Increase frequency of RTC by 488.5 ppm 359 | uint32_t : 16; 360 | }; 361 | 362 | union { 363 | uint32_t r; 364 | Bits b; 365 | }; 366 | }; 367 | 368 | /** Tamper and alternate function configuration register (F0, F3, F46+, ) 369 | */ 370 | struct Tafcr { 371 | Tafcr(const uint32_t raw=0) { r = raw; } 372 | 373 | struct Bits { 374 | uint32_t TAMP1E : 1; // RTC_TAMP1 input detection enable 375 | uint32_t TAMP1TRG : 1; // Active level for RTC_TAMP1 input 376 | uint32_t TAMPIE : 1; // Tamper interrupt enable 377 | uint32_t TAMP2E : 1; // RTC_TAMP2 input detection enable 378 | uint32_t TAMP2TRG : 1; // Active level for RTC_TAMP2 input 379 | uint32_t TAMP3E : 1; // RTC_TAMP3 detection enable 380 | uint32_t TAMP3TRG : 1; // Active level for RTC_TAMP3 input 381 | uint32_t TAMPTS : 1; // Activate time-stamp on tamper detection event 382 | uint32_t TAMPFREQ : 3; // Tamper sampling frequency 383 | uint32_t TAMPFLT : 2; // RTC_TAMPx filter count 384 | uint32_t TAMPPRCH : 2; // RTC_TAMPx precharge duration 385 | uint32_t TAMPPUDIS : 1; // RTC_TAMPx pull-up disable 386 | uint32_t : 2; 387 | uint32_t PC13VALUE : 1; // RTC_ALARM output type/PC13 value 388 | uint32_t PC13MODE : 1; // PC13 mode 389 | uint32_t PC14VALUE : 1; // PC14 value 390 | uint32_t PC14MODE : 1; // PC14 mode 391 | uint32_t PC15VALUE : 1; // PC15 value 392 | uint32_t PC15MODE : 1; // PC15 mode 393 | uint32_t : 8; 394 | }; 395 | 396 | union { 397 | uint32_t r; 398 | Bits b; 399 | }; 400 | }; 401 | 402 | /** Alarm A sSub second register 403 | */ 404 | struct Alrmssr { 405 | Alrmssr(const uint32_t raw=0) { r = raw; } 406 | 407 | struct Bits { 408 | const uint32_t SS : 15; // sub seconds 409 | uint32_t : 9; 410 | uint32_t MASKSS : 4; // Mask the most-significant bits starting at this bit 411 | uint32_t : 4; 412 | }; 413 | 414 | union { 415 | uint32_t r; 416 | Bits b; 417 | }; 418 | }; 419 | 420 | volatile Tr TR; // Time register 421 | volatile Dr DR; // Date register 422 | volatile Cr CR; // Control register 423 | volatile Isr ISR; // Initialization and status register 424 | volatile Prer PRER; // Prescaler register 425 | volatile Wutr WUTR; // Wakeup timer register 426 | volatile Calibr CALIBR; // Calibration register (F2, F4, L1) 427 | volatile Alarmr ALARMAR; // Alarm A register 428 | volatile Alarmr ALARMBR; // Alarm B register (F2, F3, F4, F7, H7, L0, L1, L4) 429 | volatile Wpr WPR; // Write protection register 430 | volatile Ssr SSR; // Sub second register (F0, F3, F4, F7, H7, L0, L1, L4) 431 | volatile Shiftr SHIFTR; // Shift control register (F0, F3, F4, F7, H7, L0, L1, L4) 432 | volatile Tstr TSTR; // Time-stamp time register 433 | volatile Tsdr TSDR; // Time-stamp date register 434 | volatile Tsssr TSSSR; // Time-stamp sub second register (F0, F3, F4, F7, H7, L0, L1, L4) 435 | volatile Calr CALR; // Calibration register (F0, F3, F4, F7, H7, L0, L1, L4) 436 | volatile Tafcr TAFCR; // Tamper and alternate function configuration register 437 | volatile Alrmssr ALRMASSR; // Alarm A sSub second register 438 | volatile Alrmssr ALRMBSSR; // Alarm A sSub second register 439 | uint32_t __res1; 440 | volatile uint32_t BKP[32]; // (F0:5, F2:20, F3:32, F4:20, F7:32, L0:5, L1:32, L4:32, H7:32) 441 | }; 442 | 443 | } 444 | -------------------------------------------------------------------------------- /reg/stm32/_common/spi_v1.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SPI - Serial peripheral interface / inter-IC sound 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F1xx 8 | * - STM32F2xx 9 | * - STM32F4xx 10 | * - STM32L0xx 11 | * - STM32L1xx 12 | */ 13 | 14 | #pragma once 15 | 16 | #include 17 | #include 18 | 19 | namespace io { 20 | 21 | struct Spi { 22 | /** Control register 1 23 | */ 24 | struct Cr1 { 25 | Cr1(const uint32_t raw=0) { r = raw; } 26 | 27 | struct Bits { 28 | uint32_t CPHA : 1; // Clock Phase 29 | uint32_t CPOL : 1; // Clock Polarity 30 | uint32_t MSTR : 1; // Master enable 31 | uint32_t BR : 3; // Baud Rate control 32 | uint32_t SPE : 1; // SPI Enable 33 | uint32_t LSBFIRST : 1; // LSB First frame format 34 | uint32_t SSI : 1; // Internal Slave Select 35 | uint32_t SSM : 1; // Software Slave Management enable 36 | uint32_t RXONLY : 1; // Receiver Only mode enable 37 | uint32_t DFF : 1; // Data frame format (0: 8 bit, 1: 16 bit) 38 | uint32_t CRCNEXT : 1; // Transmit CRC Next 39 | uint32_t CRCEN : 1; // CRC enable 40 | uint32_t BIDIOE : 1; // Output Enable in Bidirectional Mode 41 | uint32_t BIDIMODE : 1; // Bidirectional data Mode enabled 42 | uint32_t : 16; 43 | }; 44 | 45 | struct Br { 46 | static const uint32_t DIV_2 = 0; 47 | static const uint32_t DIV_4 = 1; 48 | static const uint32_t DIV_8 = 2; 49 | static const uint32_t DIV_16 = 3; 50 | static const uint32_t DIV_32 = 4; 51 | static const uint32_t DIV_64 = 5; 52 | static const uint32_t DIV_128 = 6; 53 | static const uint32_t DIV_256 = 7; 54 | }; 55 | 56 | union { 57 | uint32_t r; 58 | Bits b; 59 | }; 60 | }; 61 | 62 | /** Control register 2 63 | */ 64 | struct Cr2 { 65 | Cr2(const uint32_t raw=0) { r = raw; } 66 | 67 | struct Bits { 68 | uint32_t RXDMAEN : 1; // RX buffer DMA Enable 69 | uint32_t TXDMAEN : 1; // TX buffer DMA Enable 70 | uint32_t SSOE : 1; // Slave Select Output Enable 71 | uint32_t NSSP : 1; // NSS Pulse management enable 72 | uint32_t FRF : 1; // Frame Format mode (0: Motorola, 1: TI) 73 | uint32_t ERRIE : 1; // Error Interrupt Enable 74 | uint32_t RXNEIE : 1; // RX buffer Not Empty Interrupt Enable 75 | uint32_t TXEIE : 1; // TX buffer Empty Interrupt Enable 76 | uint32_t DS : 4; // Data Size 77 | uint32_t FRXTH : 1; // FiFo Reception Threshold 78 | uint32_t LDMA_RX : 1; // Last DMA transfer for Reception 79 | uint32_t LDMA_TX : 1; // Last DMA transfer for transmission 80 | uint32_t : 17; 81 | }; 82 | 83 | struct Ds { 84 | static const uint32_t DS_4 = 3; 85 | static const uint32_t DS_5 = 4; 86 | static const uint32_t DS_6 = 5; 87 | static const uint32_t DS_7 = 6; 88 | static const uint32_t DS_8 = 7; 89 | static const uint32_t DS_9 = 8; 90 | static const uint32_t DS_10 = 9; 91 | static const uint32_t DS_11 = 10; 92 | static const uint32_t DS_12 = 11; 93 | static const uint32_t DS_13 = 12; 94 | static const uint32_t DS_14 = 13; 95 | static const uint32_t DS_15 = 14; 96 | static const uint32_t DS_16 = 15; 97 | }; 98 | 99 | union { 100 | uint32_t r; 101 | Bits b; 102 | }; 103 | }; 104 | 105 | /** Status register 106 | */ 107 | struct Sr { 108 | Sr(const uint32_t raw=0) { r = raw; } 109 | 110 | struct Bits { 111 | const uint32_t RXNE : 1; // RX buffer not empty 112 | const uint32_t TXE : 1; // TX buffer empty 113 | const uint32_t CHSIDE : 1; // I2S Channel side (0: left, 1: right) 114 | const uint32_t UDR : 1; // I2S Under run flag 115 | uint32_t CRCERR : 1; // CRC Error flag 116 | const uint32_t MODF : 1; // Mode Fault 117 | const uint32_t OVR : 1; // Overrun Flag 118 | const uint32_t BSY : 1; // Busy Flag 119 | const uint32_t FRE : 1; // Frame format Error 120 | const uint32_t FRLVL : 2; // FiFo Reception Level 121 | const uint32_t FTLVL : 2; // FiFo Transmission Level 122 | uint32_t : 19; 123 | }; 124 | 125 | union { 126 | uint32_t r; 127 | Bits b; 128 | }; 129 | struct Flvl { 130 | static const uint32_t EMPTY = 0; 131 | static const uint32_t QUART = 1; 132 | static const uint32_t HALF = 2; 133 | static const uint32_t FULL = 3; 134 | }; 135 | }; 136 | 137 | /** data register 138 | */ 139 | struct Dr { 140 | union { 141 | uint32_t r; 142 | uint32_t DR; // Data Register 16 bit access (using 32 bits) 143 | uint16_t DR16; // Data Register 16 bit access 144 | uint8_t DR8; // Data Register 8 bit access 145 | }; 146 | }; 147 | 148 | /** CRC polynomial register 149 | */ 150 | struct Crcpr { 151 | union { 152 | uint32_t r; 153 | uint16_t CRCPOLY; // CRC Polynomial 154 | }; 155 | }; 156 | 157 | /** Rx CRC register 158 | */ 159 | struct Rxcrcr { 160 | union { 161 | uint32_t r; 162 | const uint16_t RXCRC; // RX CRC 16 bit 163 | }; 164 | }; 165 | 166 | /** Tx CRC register 167 | */ 168 | struct Txcrcr { 169 | union { 170 | uint32_t r; 171 | const uint16_t TXCRC; // TX CRC 16 bit 172 | }; 173 | }; 174 | 175 | /** I2S configuration register 176 | */ 177 | struct I2scfgr { 178 | I2scfgr(const uint32_t raw=0) { r = raw; } 179 | 180 | struct Bits { 181 | uint32_t CHLEN : 1; // Channel Length (0: 16 bit, 1: 32 bit) 182 | uint32_t DATLEN : 2; // Data Length 183 | uint32_t CKPOL : 1; // steady state Clock Polarity 184 | uint32_t I2SSTD : 2; // I2S Standard selection 185 | uint32_t : 1; 186 | uint32_t PCMSYNC : 1; // PCM frame Synchronization 187 | uint32_t I2SCFG : 2; // I2S Configuration mode 188 | uint32_t I2SE : 1; // I2S Enable 189 | uint32_t I2SMOD : 1; // I2S Mode selected 190 | uint32_t : 20; 191 | }; 192 | 193 | struct Datalen { 194 | static const uint32_t DATALEN_16 = 0; 195 | static const uint32_t DATALEN_24 = 1; 196 | static const uint32_t DATALEN_32 = 2; 197 | }; 198 | 199 | struct I2sstd { 200 | static const uint32_t I2S_PHILLIPS = 0; 201 | static const uint32_t MSB_JUSTIFIED = 1; 202 | static const uint32_t LSB_JUSTIFIED = 2; 203 | static const uint32_t PCM_STANDARD = 3; 204 | }; 205 | 206 | struct I2scfg { 207 | static const uint32_t SLAVE_TX = 0; 208 | static const uint32_t SLAVE_RX = 1; 209 | static const uint32_t MASTER_TX = 2; 210 | static const uint32_t MASTER_RX = 3; 211 | }; 212 | 213 | union { 214 | uint32_t r; 215 | Bits b; 216 | }; 217 | }; 218 | 219 | /** I2S prescaler register 220 | */ 221 | struct I2spr { 222 | I2spr(const uint32_t raw=0) { r = raw; } 223 | 224 | struct Bits { 225 | uint32_t I2SDIV : 8; // I2S linear prescaler 226 | uint32_t ODD : 1; // Odd factor for the prescaler 227 | uint32_t MCKOE : 1; // Master Clock Output Enable 228 | uint32_t : 22; 229 | }; 230 | 231 | union { 232 | uint32_t r; 233 | Bits b; 234 | }; 235 | }; 236 | 237 | volatile Cr1 CR1; // Control register 1 238 | volatile Cr2 CR2; // Control register 2 239 | volatile Sr SR; // Status register 240 | volatile Dr DR; // data register 241 | volatile Crcpr CRCPR; // CRC polynomial register 242 | volatile Rxcrcr RXCRCR; // Rx CRC register 243 | volatile Txcrcr TXCRCR; // Tx CRC register 244 | volatile I2scfgr I2SCFGR; // I2S configuration register 245 | volatile I2spr I2SPR; // I2S prescaler register 246 | }; 247 | 248 | static inline constexpr Spi &SPI(const size_t base) { 249 | return *reinterpret_cast(base); 250 | } 251 | 252 | } 253 | -------------------------------------------------------------------------------- /reg/stm32/_common/spi_v2.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SPI - Serial peripheral interface / inter-IC sound 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F3xx 9 | * - STM32F7xx 10 | * - STM32L4xx 11 | */ 12 | 13 | #pragma once 14 | 15 | #include 16 | #include 17 | 18 | namespace io { 19 | 20 | struct Spi { 21 | /** Control register 1 22 | */ 23 | struct Cr1 { 24 | Cr1(const uint32_t raw=0) { r = raw; } 25 | 26 | struct Bits { 27 | uint32_t CPHA : 1; // Clock Phase 28 | uint32_t CPOL : 1; // Clock Polarity 29 | uint32_t MSTR : 1; // Master enable 30 | uint32_t BR : 3; // Baud Rate control 31 | uint32_t SPE : 1; // SPI Enable 32 | uint32_t LSBFIRST : 1; // LSB First frame format 33 | uint32_t SSI : 1; // Internal Slave Select 34 | uint32_t SSM : 1; // Software Slave Management enable 35 | uint32_t RXONLY : 1; // Receiver Only mode enable 36 | uint32_t CRCL : 1; // CRC Length 37 | uint32_t CRCNEXT : 1; // Transmit CRC Next 38 | uint32_t CRCEN : 1; // CRC enable 39 | uint32_t BIDIOE : 1; // Output Enable in Bidirectional Mode 40 | uint32_t BIDIMODE : 1; // Bidirectional data Mode enabled 41 | uint32_t : 16; 42 | }; 43 | 44 | struct Br { 45 | static const uint32_t DIV_2 = 0; 46 | static const uint32_t DIV_4 = 1; 47 | static const uint32_t DIV_8 = 2; 48 | static const uint32_t DIV_16 = 3; 49 | static const uint32_t DIV_32 = 4; 50 | static const uint32_t DIV_64 = 5; 51 | static const uint32_t DIV_128 = 6; 52 | static const uint32_t DIV_256 = 7; 53 | }; 54 | 55 | union { 56 | uint32_t r; 57 | Bits b; 58 | }; 59 | }; 60 | 61 | /** Control register 2 62 | */ 63 | struct Cr2 { 64 | Cr2(const uint32_t raw=0) { r = raw; } 65 | 66 | struct Bits { 67 | uint32_t RXDMAEN : 1; // RX buffer DMA Enable 68 | uint32_t TXDMAEN : 1; // TX buffer DMA Enable 69 | uint32_t SSOE : 1; // Slave Select Output Enable 70 | uint32_t NSSP : 1; // NSS Pulse management enable 71 | uint32_t FRF : 1; // Frame Format mode (0: Motorola, 1: TI) 72 | uint32_t ERRIE : 1; // Error Interrupt Enable 73 | uint32_t RXNEIE : 1; // RX buffer Not Empty Interrupt Enable 74 | uint32_t TXEIE : 1; // TX buffer Empty Interrupt Enable 75 | uint32_t DS : 4; // Data Size 76 | uint32_t FRXTH : 1; // FiFo Reception Threshold 77 | uint32_t LDMA_RX : 1; // Last DMA transfer for Reception 78 | uint32_t LDMA_TX : 1; // Last DMA transfer for transmission 79 | uint32_t : 17; 80 | }; 81 | 82 | struct Ds { 83 | static const uint32_t DS_4 = 3; 84 | static const uint32_t DS_5 = 4; 85 | static const uint32_t DS_6 = 5; 86 | static const uint32_t DS_7 = 6; 87 | static const uint32_t DS_8 = 7; 88 | static const uint32_t DS_9 = 8; 89 | static const uint32_t DS_10 = 9; 90 | static const uint32_t DS_11 = 10; 91 | static const uint32_t DS_12 = 11; 92 | static const uint32_t DS_13 = 12; 93 | static const uint32_t DS_14 = 13; 94 | static const uint32_t DS_15 = 14; 95 | static const uint32_t DS_16 = 15; 96 | }; 97 | 98 | union { 99 | uint32_t r; 100 | Bits b; 101 | }; 102 | }; 103 | 104 | /** Status register 105 | */ 106 | struct Sr { 107 | Sr(const uint32_t raw=0) { r = raw; } 108 | 109 | struct Bits { 110 | const uint32_t RXNE : 1; // RX buffer not empty 111 | const uint32_t TXE : 1; // TX buffer empty 112 | const uint32_t CHSIDE : 1; // I2S Channel side (0: left, 1: right) 113 | const uint32_t UDR : 1; // I2S Under run flag 114 | uint32_t CRCERR : 1; // CRC Error flag 115 | const uint32_t MODF : 1; // Mode Fault 116 | const uint32_t OVR : 1; // Overrun Flag 117 | const uint32_t BSY : 1; // Busy Flag 118 | const uint32_t FRE : 1; // Frame format Error 119 | const uint32_t FRLVL : 2; // FiFo Reception Level 120 | const uint32_t FTLVL : 2; // FiFo Transmission Level 121 | uint32_t : 19; 122 | }; 123 | 124 | struct Flvl { 125 | static const uint32_t EMPTY = 0; 126 | static const uint32_t QUART = 1; 127 | static const uint32_t HALF = 2; 128 | static const uint32_t FULL = 3; 129 | }; 130 | 131 | union { 132 | uint32_t r; 133 | Bits b; 134 | }; 135 | }; 136 | 137 | /** data register 138 | */ 139 | struct Dr { 140 | union { 141 | uint32_t r; 142 | uint32_t DR; // Data Register 16 bit access (using 32 bits) 143 | uint16_t DR16; // Data Register 16 bit access 144 | uint8_t DR8; // Data Register 8 bit access 145 | }; 146 | }; 147 | 148 | /** CRC polynomial register 149 | */ 150 | struct Crcpr { 151 | union { 152 | uint32_t r; 153 | uint16_t CRCPOLY; // CRC Polynomial 154 | }; 155 | }; 156 | 157 | /** Rx CRC register 158 | */ 159 | struct Rxcrcr { 160 | union { 161 | uint32_t r; 162 | const uint16_t RXCRC; // RX CRC 16 bit 163 | }; 164 | }; 165 | 166 | /** Tx CRC register 167 | */ 168 | struct Txcrcr { 169 | union { 170 | uint32_t r; 171 | const uint16_t TXCRC; // TX CRC 16 bit 172 | }; 173 | }; 174 | 175 | /** I2S configuration register 176 | */ 177 | struct I2scfgr { 178 | I2scfgr(const uint32_t raw=0) { r = raw; } 179 | 180 | struct Bits { 181 | uint32_t CHLEN : 1; // Channel Length (0: 16 bit, 1: 32 bit) 182 | uint32_t DATLEN : 2; // Data Length 183 | uint32_t CKPOL : 1; // steady state Clock Polarity 184 | uint32_t I2SSTD : 2; // I2S Standard selection 185 | uint32_t : 1; 186 | uint32_t PCMSYNC : 1; // PCM frame Synchronization 187 | uint32_t I2SCFG : 2; // I2S Configuration mode 188 | uint32_t I2SE : 1; // I2S Enable 189 | uint32_t I2SMOD : 1; // I2S Mode selected 190 | uint32_t : 20; 191 | }; 192 | 193 | struct Datalen { 194 | static const uint32_t DATALEN_16 = 0; 195 | static const uint32_t DATALEN_24 = 1; 196 | static const uint32_t DATALEN_32 = 2; 197 | }; 198 | 199 | struct i2sstd { 200 | static const uint32_t I2S_PHILLIPS = 0; 201 | static const uint32_t MSB_JUSTIFIED = 1; 202 | static const uint32_t LSB_JUSTIFIED = 2; 203 | static const uint32_t PCM_STANDARD = 3; 204 | }; 205 | 206 | struct i2scfg { 207 | static const uint32_t SLAVE_TX = 0; 208 | static const uint32_t SLAVE_RX = 1; 209 | static const uint32_t MASTER_TX = 2; 210 | static const uint32_t MASTER_RX = 3; 211 | }; 212 | 213 | union { 214 | uint32_t r; 215 | Bits b; 216 | }; 217 | }; 218 | 219 | /** I2S prescaler register 220 | */ 221 | struct I2spr { 222 | I2spr(const uint32_t raw=0) { r = raw; } 223 | 224 | struct Bits { 225 | uint32_t I2SDIV : 8; // I2S linear prescaler 226 | uint32_t ODD : 1; // Odd factor for the prescaler 227 | uint32_t MCKOE : 1; // Master Clock Output Enable 228 | uint32_t : 22; 229 | }; 230 | 231 | union { 232 | uint32_t r; 233 | Bits b; 234 | }; 235 | }; 236 | 237 | volatile Cr1 CR1; // Control register 1 238 | volatile Cr2 CR2; // Control register 2 239 | volatile Sr SR; // Status register 240 | volatile Dr DR; // data register 241 | volatile Crcpr CRCPR; // CRC polynomial register 242 | volatile Rxcrcr RXCRCR; // Rx CRC register 243 | volatile Txcrcr TXCRCR; // Tx CRC register 244 | volatile I2scfgr I2SCFGR; // I2S configuration register 245 | volatile I2spr I2SPR; // I2S prescaler register 246 | }; 247 | 248 | static inline constexpr Spi &SPI(const size_t base) { 249 | return *reinterpret_cast(base); 250 | } 251 | 252 | } 253 | -------------------------------------------------------------------------------- /reg/stm32/_common/timer.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * TIMER - Timers 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F1xx 9 | * - STM32F2xx 10 | * - STM32F4xx 11 | * - STM32L0xx 12 | * - STM32L1xx 13 | */ 14 | 15 | #pragma once 16 | 17 | #include 18 | #include 19 | 20 | namespace io { 21 | 22 | struct Timer { 23 | /** Control register 1 24 | */ 25 | struct Cr1 { 26 | Cr1(const uint32_t raw=0) { r = raw; } 27 | 28 | struct Bits { 29 | uint32_t CEN : 1; // Counter enable 30 | uint32_t UDIS : 1; // Update disable 31 | uint32_t URS : 1; // Update request source 32 | uint32_t OPM : 1; // One pulse mode 33 | uint32_t DIR : 1; // Direction 34 | uint32_t CMS : 2; // Center-aligned mode selection 35 | uint32_t ARPE : 1; // Auto-reload preload enable 36 | uint32_t CKD : 2; // Clock division 37 | uint32_t : 22; 38 | }; 39 | 40 | union { 41 | uint32_t r; 42 | Bits b; 43 | }; 44 | }; 45 | 46 | /** Control register 2 47 | */ 48 | struct Cr2 { 49 | Cr2(const uint32_t raw=0) { r = raw; } 50 | 51 | struct Bits { 52 | uint32_t CCPC : 1; // Capture/compare preloaded control 53 | uint32_t : 1; 54 | uint32_t CCUS : 1; // Capture/compare control update selection 55 | uint32_t CCDS : 1; // Capture/compare DMA selection 56 | uint32_t MMS : 3; // Master mode selection 57 | uint32_t TI1S : 1; // TI1 selection 58 | uint32_t OIS1 : 1; // Output Idle state 1 (OC1 output) 59 | uint32_t OIS1N : 1; // Output Idle state 1 (OC1N output) 60 | uint32_t OIS2 : 1; // Output Idle state 2 (OC2 output) 61 | uint32_t OIS2N : 1; // Output Idle state 2 (OC2N output) 62 | uint32_t OIS3 : 1; // Output Idle state 3 (OC3 output) 63 | uint32_t OIS3N : 1; // Output Idle state 3 (OC3N output) 64 | uint32_t OIS4 : 1; // Output Idle state 4 (OC4 output) 65 | uint32_t : 17; 66 | }; 67 | 68 | union { 69 | uint32_t r; 70 | Bits b; 71 | }; 72 | }; 73 | 74 | /** Slave mode control register 75 | */ 76 | struct Smcr { 77 | Smcr(const uint32_t raw=0) { r = raw; } 78 | 79 | struct Bits { 80 | uint32_t SMS : 3; // Slave mode selection 81 | uint32_t OCCS : 1; // OCREF clear selection 82 | uint32_t TS : 3; // Trigger selection 83 | uint32_t MSM : 1; // Master/slave mode 84 | uint32_t ETF : 4; // External trigger filter 85 | uint32_t ETPS : 2; // External trigger prescaler 86 | uint32_t ECE : 1; // External clock enable 87 | uint32_t ETP : 1; // External trigger polarity 88 | uint32_t : 16; 89 | }; 90 | 91 | struct Sms { 92 | uint32_t SLAVE_MODE_DISABLED = 0; 93 | uint32_t ENCODER_MODE1 = 1; 94 | uint32_t ENCODER_MODE2 = 2; 95 | uint32_t ENCODER_MODE3 = 3; 96 | uint32_t RESET_MODE = 4; 97 | uint32_t GATED_MODE = 5; 98 | uint32_t TRIGGER_MODE = 6; 99 | uint32_t EXTERNAL_CLOCK_MODE = 7; 100 | }; 101 | 102 | struct Ts { 103 | uint32_t ITR0 = 0; 104 | uint32_t ITR1 = 1; 105 | uint32_t ITR2 = 2; 106 | uint32_t ITR3 = 3; 107 | uint32_t TI1FED = 4; 108 | uint32_t TI1FP1 = 5; 109 | uint32_t TI1FP2 = 6; 110 | uint32_t ETRF = 7; 111 | }; 112 | 113 | union { 114 | uint32_t r; 115 | Bits b; 116 | }; 117 | }; 118 | 119 | /** DMA/interrupt enable register 120 | */ 121 | struct Dier { 122 | Dier(const uint32_t raw=0) { r = raw; } 123 | 124 | struct Bits { 125 | uint32_t UIE : 1; // Update interrupt enable 126 | uint32_t CC1IE : 1; // Capture/Compare 1 interrupt enable 127 | uint32_t CC2IE : 1; // Capture/Compare 2 interrupt enable 128 | uint32_t CC3IE : 1; // Capture/Compare 3 interrupt enable 129 | uint32_t CC4IE : 1; // Capture/Compare 4 interrupt enable 130 | uint32_t COMIE : 1; // COM interrupt enable 131 | uint32_t TIE : 1; // Trigger interrupt enable 132 | uint32_t BIE : 1; // Break interrupt enable 133 | uint32_t UDE : 1; // Update DMA request enable 134 | uint32_t CC1DE : 1; // Capture/Compare 1 DMA request enable 135 | uint32_t CC2DE : 1; // Capture/Compare 2 DMA request enable 136 | uint32_t CC3DE : 1; // Capture/Compare 3 DMA request enable 137 | uint32_t CC4DE : 1; // Capture/Compare 4 DMA request enable 138 | uint32_t COMDE : 1; // COM DMA request enable 139 | uint32_t TDE : 1; // Trigger DMA request enable 140 | uint32_t : 17; 141 | }; 142 | 143 | union { 144 | uint32_t r; 145 | Bits b; 146 | }; 147 | }; 148 | 149 | /** Status register 150 | */ 151 | struct Sr { 152 | Sr(const uint32_t raw=0) { r = raw; } 153 | 154 | struct Bits { 155 | uint32_t UIF : 1; // Update interrupt flag 156 | uint32_t CC1IF : 1; // Capture/Compare 1 interrupt flag 157 | uint32_t CC2IF : 1; // Capture/Compare 2 interrupt flag 158 | uint32_t CC3IF : 1; // Capture/Compare 3 interrupt flag 159 | uint32_t CC4IF : 1; // Capture/Compare 4 interrupt flag 160 | uint32_t COMIF : 1; // COM interrupt flag 161 | uint32_t TIF : 1; // Trigger interrupt flag 162 | uint32_t BIF : 1; // Break interrupt flag 163 | uint32_t : 1; 164 | uint32_t CC1OF : 1; // Capture/Compare 1 overcapture flag 165 | uint32_t CC2OF : 1; // Capture/Compare 2 overcapture flag 166 | uint32_t CC3OF : 1; // Capture/Compare 3 overcapture flag 167 | uint32_t CC4OF : 1; // Capture/Compare 4 overcapture flag 168 | uint32_t : 19; 169 | }; 170 | 171 | union { 172 | uint32_t r; 173 | Bits b; 174 | }; 175 | }; 176 | 177 | /** Event generation register 178 | */ 179 | struct Egr { 180 | Egr(const uint32_t raw=0) { r = raw; } 181 | 182 | struct Bits { 183 | uint32_t UG : 1; // Update generation 184 | uint32_t CC1G : 1; // Capture/Compare 1 generation 185 | uint32_t CC2G : 1; // Capture/Compare 2 generation 186 | uint32_t CC3G : 1; // Capture/Compare 3 generation 187 | uint32_t CC4G : 1; // Capture/Compare 4 generation 188 | uint32_t COMG : 1; // Capture/Compare control update generation 189 | uint32_t TG : 1; // Trigger generation 190 | uint32_t BG : 1; // Break generation 191 | uint32_t : 24; 192 | }; 193 | 194 | union { 195 | uint32_t r; 196 | Bits b; 197 | }; 198 | }; 199 | 200 | /** Capture/compare mode register - output capture mode 201 | */ 202 | struct CcmrOc { 203 | CcmrOc() {} 204 | 205 | struct Bits { 206 | uint32_t CC1S : 2; // Capture/Compare 1 selection 207 | uint32_t OC1FE : 1; // Output Compare 1 fast enable 208 | uint32_t OC1PE : 1; // Output Compare 1 preload enable 209 | uint32_t OC1M : 3; // Output Compare 1 mode 210 | uint32_t OC1CE : 1; // Output Compare 1 clear enable 211 | uint32_t CC2S : 2; // Capture/Compare 2 selection 212 | uint32_t OC2FE : 1; // Output Compare 2 fast enable 213 | uint32_t OC2PE : 1; // Output Compare 2 preload enable 214 | uint32_t OC2M : 3; // Output Compare 2 mode 215 | uint32_t OC2CE : 1; // Output Compare 2 clear enable 216 | uint32_t : 16; 217 | uint32_t CC3S : 2; // Capture/Compare 3 selection 218 | uint32_t OC3FE : 1; // Output Compare 3 fast enable 219 | uint32_t OC3PE : 1; // Output Compare 3 preload enable 220 | uint32_t OC3M : 3; // Output Compare 3 mode 221 | uint32_t OC3CE : 1; // Output Compare 3 clear enable 222 | uint32_t CC4S : 2; // Capture/Compare 4 selection 223 | uint32_t OC4FE : 1; // Output Compare 4 fast enable 224 | uint32_t OC4PE : 1; // Output Compare 4 preload enable 225 | uint32_t OC4M : 3; // Output Compare 4 mode 226 | uint32_t OC4CE : 1; // Output Compare 4 clear enable 227 | uint32_t : 16; 228 | }; 229 | 230 | struct Ccs { 231 | uint32_t OUTPUT = 0; 232 | uint32_t INPUT_TI2 = 1; 233 | uint32_t INPUT_TI1 = 2; 234 | uint32_t INPUT_TRC = 3; 235 | }; 236 | 237 | struct Ocm { 238 | uint32_t FROZEN = 0; 239 | uint32_t SET_ACTIVE = 1; 240 | uint32_t SET_INACTIVE = 2; 241 | uint32_t TOGGLE = 3; 242 | uint32_t FORCE_INACTIVE = 4; 243 | uint32_t FORCE_ACTIVE = 5; 244 | uint32_t PWM_MODE1 = 6; 245 | uint32_t PWM_MODE2 = 7; 246 | }; 247 | 248 | union { 249 | uint32_t r[2]; 250 | Bits b; 251 | }; 252 | }; 253 | 254 | /** Capture/compare mode register input capture mode 255 | */ 256 | struct CcmrIc { 257 | CcmrIc() {} 258 | 259 | struct Bits { 260 | uint32_t : 2; 261 | uint32_t IC1PSC : 2; // Input capture 1 prescaler 262 | uint32_t IC1F : 4; // Input capture 1 filter 263 | uint32_t : 2; 264 | uint32_t IC2PSC : 2; // Input capture 2 prescaler 265 | uint32_t IC2F : 4; // Input capture 2 filter 266 | uint32_t : 16; 267 | uint32_t : 2; 268 | uint32_t IC3PSC : 2; // Input capture 3 prescaler 269 | uint32_t IC3F : 4; // Input capture 3 filter 270 | uint32_t : 2; 271 | uint32_t IC4PSC : 2; // Input capture 4 prescaler 272 | uint32_t IC4F : 4; // Input capture 4 filter 273 | uint32_t : 16; 274 | }; 275 | 276 | union { 277 | uint32_t r[2]; 278 | Bits b; 279 | }; 280 | }; 281 | 282 | /** Capture/compare enable register 283 | */ 284 | struct Ccer { 285 | Ccer(const uint32_t raw=0) { r = raw; } 286 | 287 | struct Bits { 288 | uint32_t CC1E : 1; // Capture/Compare 1 output enable 289 | uint32_t CC1P : 1; // Capture/Compare 1 output polarity 290 | uint32_t CC1NE : 1; // Capture/Compare 1 complementary output enable 291 | uint32_t CC1NP : 1; // Capture/Compare 1 complementary output polarity 292 | uint32_t CC2E : 1; // Capture/Compare 2 output enable 293 | uint32_t CC2P : 1; // Capture/Compare 2 output polarity 294 | uint32_t CC2NE : 1; // Capture/Compare 2 complementary output enable 295 | uint32_t CC2NP : 1; // Capture/Compare 2 complementary output polarity 296 | uint32_t CC3E : 1; // Capture/Compare 3 output enable 297 | uint32_t CC3P : 1; // Capture/Compare 3 output polarity 298 | uint32_t CC3NE : 1; // Capture/Compare 3 complementary output enable 299 | uint32_t CC3NP : 1; // Capture/Compare 3 complementary output polarity 300 | uint32_t CC4E : 1; // Capture/Compare 4 output enable 301 | uint32_t CC4P : 1; // Capture/Compare 4 output polarity 302 | uint32_t : 18; 303 | }; 304 | 305 | union { 306 | uint32_t r; 307 | Bits b; 308 | }; 309 | }; 310 | 311 | /** Counter value 312 | */ 313 | struct Cnt { 314 | union { 315 | uint32_t r; 316 | uint32_t CNT; // 32 bit access 317 | uint16_t CNT16; // 16 bit access 318 | }; 319 | }; 320 | 321 | /** Prescaler value 322 | */ 323 | struct Psc { 324 | union { 325 | uint32_t r; 326 | uint32_t PSC; // 32 bit access 327 | uint16_t PSC16; // 16 bit access 328 | }; 329 | }; 330 | 331 | /** Auto-reload value 332 | */ 333 | struct Arr { 334 | union { 335 | uint32_t r; 336 | uint32_t ARR; // 32 bit access 337 | uint16_t ARR16; // 16 bit access 338 | }; 339 | }; 340 | 341 | /** Repetition counter value 342 | */ 343 | struct Rcr { 344 | union { 345 | uint32_t r; 346 | uint32_t RCR; // 32 bit access 347 | uint16_t RCR16; // 16 bit access 348 | }; 349 | }; 350 | 351 | /** Capture/compare register 352 | */ 353 | struct Ccr { 354 | union { 355 | uint32_t r[4]; 356 | uint32_t CCR[4]; 357 | }; 358 | }; 359 | 360 | /** Break and dead-time register 361 | */ 362 | struct Bdtr { 363 | Bdtr(const uint32_t raw=0) { r = raw; } 364 | 365 | struct Bits { 366 | uint32_t DTG : 8; // Dead-time generator setup 367 | uint32_t LOCK : 2; // Lock configuration 368 | uint32_t OSSI : 1; // Off-state selection for Idle mode 369 | uint32_t OSSR : 1; // Off-state selection for Run mode 370 | uint32_t BKE : 1; // Break enable 371 | uint32_t BKP : 1; // Break polarity 372 | uint32_t AOE : 1; // Automatic output enable 373 | uint32_t MOE : 1; // Main output enable 374 | uint32_t : 16; 375 | }; 376 | 377 | union { 378 | uint32_t r; 379 | Bits b; 380 | }; 381 | }; 382 | 383 | /** DMA control register 384 | */ 385 | struct Dcr { 386 | Dcr(const uint32_t raw=0) { r = raw; } 387 | 388 | struct Bits { 389 | uint32_t DBA : 5; // DMA base address 390 | uint32_t : 3; 391 | uint32_t DBL : 5; // DMA burst length 392 | uint32_t : 19; 393 | }; 394 | 395 | union { 396 | uint32_t r; 397 | Bits b; 398 | }; 399 | }; 400 | 401 | /** DMA address for full transfer 402 | */ 403 | struct Dmar { 404 | union { 405 | uint32_t r; 406 | uint32_t DMAB; // DMA register for burst accesses 407 | uint16_t DMAB16; // 16 bit access 408 | }; 409 | }; 410 | 411 | volatile Cr1 CR1; // Control register 1 412 | volatile Cr2 CR2; // Control register 2 413 | volatile Smcr SMCR; // Slave mode control register 414 | volatile Dier DIER; // DMA/interrupt enable register 415 | volatile Sr SR; // Status register 416 | volatile Egr EGR; // Event generation register 417 | union { 418 | volatile CcmrOc OC; // Capture/compare mode register - output capture mode 419 | volatile CcmrIc IC; // Capture/compare mode register - input capture mode 420 | } CCMR; 421 | volatile Ccer CCER; // Capture/compare enable register 422 | volatile Cnt CNT; // Counter value 423 | volatile Psc PSC; // Prescaler value 424 | volatile Arr ARR; // Auto-reload value 425 | volatile Rcr RCR; // Repetition counter value 426 | volatile Ccr CCR; // Capture/compare register 427 | volatile Bdtr BDTR; // Break and dead-time register 428 | volatile Dcr DCR; // DMA control register 429 | volatile Dmar DMAR; // DMA address for full transfer 430 | }; 431 | 432 | static inline constexpr Timer &TIMER(const size_t base) { 433 | return *reinterpret_cast(base); 434 | } 435 | 436 | } 437 | -------------------------------------------------------------------------------- /reg/stm32/_common/usart_v2.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * USART - Universal synchronous asynchronous receiver transmitter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F3xx 9 | * - STM32F7xx 10 | * - STM32L0xx 11 | * - STM32L4xx 12 | */ 13 | 14 | #pragma once 15 | 16 | #include 17 | #include 18 | 19 | namespace io { 20 | 21 | struct Usart { 22 | /** Control register 1 23 | */ 24 | struct Cr1 { 25 | Cr1(const uint32_t raw=0) { r = raw; } 26 | 27 | struct Bits { 28 | uint32_t UE : 1; // USART enable 29 | uint32_t UESM : 1; // USART enable in Stop mode 30 | uint32_t RE : 1; // Receiver enable 31 | uint32_t TE : 1; // Transmitter enable 32 | uint32_t IDLEIE : 1; // IDLE interrupt enable 33 | uint32_t RXNEIE : 1; // RXNE interrupt enable 34 | uint32_t TCIE : 1; // Transmission complete interrupt enable 35 | uint32_t TXEIE : 1; // interrupt enable 36 | uint32_t PEIE : 1; // PE interrupt enable 37 | uint32_t PS : 1; // Parity selection 38 | uint32_t PCE : 1; // Parity control enable 39 | uint32_t WAKE : 1; // Receiver wakeup method 40 | uint32_t M0 : 1; // Word length 0 41 | uint32_t MME : 1; // Mute mode enable 42 | uint32_t CMIE : 1; // Character match interrupt enable 43 | uint32_t OVER8 : 1; // Oversampling mode 44 | uint32_t DEDT : 5; // Driver Enable de-assertion time 45 | uint32_t DEAT : 5; // Driver Enable assertion time 46 | uint32_t RTOIE : 1; // Receiver timeout interrupt enable 47 | uint32_t EOBIE : 1; // End of Block interrupt enable 48 | uint32_t M1 : 1; // Word length 1 49 | uint32_t : 3; 50 | }; 51 | 52 | union { 53 | uint32_t r; 54 | Bits b; 55 | }; 56 | }; 57 | 58 | /** Control register 2 59 | */ 60 | struct Cr2 { 61 | Cr2(const uint32_t raw=0) { r = raw; } 62 | 63 | struct Bits { 64 | uint32_t : 4; 65 | uint32_t ADDM7 : 1; // 7-bit Address Detection/4-bit Address Detection 66 | uint32_t LBDL : 1; // LIN break detection length 67 | uint32_t LBDIE : 1; // LIN break detection interrupt enable 68 | uint32_t : 1; 69 | uint32_t LBCL : 1; // Last bit clock pulse 70 | uint32_t CPHA : 1; // Clock phase 71 | uint32_t CPOL : 1; // Clock polarity 72 | uint32_t CLKEN : 1; // Clock enable 73 | uint32_t STOP: 2; // STOP bits 74 | uint32_t LINEN : 1; // LIN mode enable 75 | uint32_t SWAP : 1; // Swap TX/RX pins 76 | uint32_t RXINV : 1; // RX pin active level inversion 77 | uint32_t TXINV : 1; // TX pin active level inversion 78 | uint32_t DATAINV : 1; // Binary data inversion 79 | uint32_t MSBFIRST : 1; // Most significant bit first 80 | uint32_t ABREN : 1; // Auto baud rate enable 81 | uint32_t ABRMOD : 2; // Auto baud rate mode 82 | uint32_t RTOEN : 1; // Receiver timeout enable 83 | uint32_t ADD : 8; // Address of the USART node 84 | }; 85 | 86 | union { 87 | uint32_t r; 88 | Bits b; 89 | }; 90 | }; 91 | 92 | /** Control register 3 93 | */ 94 | struct Cr3 { 95 | Cr3(const uint32_t raw=0) { r = raw; } 96 | 97 | struct Bits { 98 | uint32_t EIE : 1; // Error interrupt enable 99 | uint32_t IREN : 1; // IrDA mode enable 100 | uint32_t IRLP : 1; // IrDA low-power 101 | uint32_t HDSEL : 1; // Half-duplex selection 102 | uint32_t NACK : 1; // Smartcard NACK enable 103 | uint32_t SCEN : 1; // Smartcard mode enable 104 | uint32_t DMAR : 1; // DMA enable receiver 105 | uint32_t DMAT : 1; // DMA enable transmitter 106 | uint32_t RTSE : 1; // RTS enable 107 | uint32_t CTSE : 1; // CTS enable 108 | uint32_t CTSIE : 1; // CTS interrupt enable 109 | uint32_t ONEBIT : 1; // One sample bit method enable 110 | uint32_t OVRDIS : 1; // Overrun Disable 111 | uint32_t DDRE : 1; // DMA Disable on Reception Erro 112 | uint32_t DEM : 1; // Driver enable mode 113 | uint32_t DEP : 1; // Driver enable polarity selection 114 | uint32_t : 1; 115 | uint32_t SCARCNT : 3; // Smartcard auto-retry count 116 | uint32_t WUS : 2; // Wakeup from Stop mode interrupt flag selection (F0, L0) 117 | uint32_t WUFIE : 1; // Wakeup from Stop mode interrupt enable (F0, L0) 118 | uint32_t UCESM : 1; // USART Clock Enable in Stop mode (L0) 119 | uint32_t TCBGTIE : 1; // Transmission complete before guard time interrupt enable (L4) 120 | uint32_t : 7; 121 | }; 122 | 123 | union { 124 | uint32_t r; 125 | Bits b; 126 | }; 127 | }; 128 | 129 | /** Baud rate register 130 | */ 131 | struct Brr { 132 | Brr(const uint32_t raw=0) { r = raw; } 133 | 134 | struct Bits { 135 | uint32_t DIV_FRACTION : 4; 136 | uint32_t DIV_MANTIS : 12; 137 | uint32_t : 16; 138 | }; 139 | 140 | union { 141 | uint32_t r; 142 | Bits b; 143 | }; 144 | }; 145 | 146 | /** Guard time and prescaler register 147 | */ 148 | struct Gtpr { 149 | Gtpr(const uint32_t raw=0) { r = raw; } 150 | 151 | struct Bits { 152 | uint32_t PSC : 8; // Prescaler value 153 | uint32_t GT : 8; // Guard time value 154 | uint32_t : 16; 155 | }; 156 | 157 | union { 158 | uint32_t r; 159 | Bits b; 160 | }; 161 | }; 162 | 163 | /** Receiver timeout register 164 | */ 165 | struct Rtor { 166 | Rtor(const uint32_t raw=0) { r = raw; } 167 | 168 | struct Bits { 169 | uint32_t RTO : 24; // Receiver timeout value 170 | uint32_t BLEN : 8; // Block Length 171 | }; 172 | 173 | union { 174 | uint32_t r; 175 | Bits b; 176 | }; 177 | }; 178 | 179 | /** Request register 180 | */ 181 | struct Rqr { 182 | Rqr(const uint32_t raw=0) { r = raw; } 183 | 184 | struct Bits { 185 | uint32_t ABRRQ : 1; // Auto baud rate reques 186 | uint32_t SBKRQ : 1; // Send break request 187 | uint32_t MMRQ : 1; // Mute mode request 188 | uint32_t RXFRQ : 1; // Receive data flush request 189 | uint32_t TXFRQ : 1; // Transmit data flush request 190 | uint32_t : 27; 191 | }; 192 | 193 | union { 194 | uint32_t r; 195 | Bits b; 196 | }; 197 | }; 198 | 199 | /** Interrupt and status register 200 | */ 201 | struct Isr { 202 | Isr(const uint32_t raw=0) { r = raw; } 203 | 204 | struct Bits { 205 | const uint32_t PE : 1; // Parity error 206 | const uint32_t FE : 1; // Framing error 207 | const uint32_t NF : 1; // START bit Noise detection flag 208 | const uint32_t ORE : 1; // Overrun error 209 | const uint32_t IDLE : 1; // Idle line detected 210 | const uint32_t RXNE : 1; // Read data register not empty 211 | const uint32_t TC : 1; // Transmission complete 212 | const uint32_t TXE : 1; // Transmit data register empty 213 | const uint32_t LBDF : 1; // LIN break detection flag 214 | const uint32_t CTSIF : 1; // CTS interrupt flag 215 | const uint32_t CTS : 1; // CTS flag 216 | const uint32_t RTOF : 1; // Receiver timeout 217 | const uint32_t EOBF : 1; // End of block flag 218 | uint32_t : 1; 219 | const uint32_t ABRE : 1; // Auto baud rate error 220 | const uint32_t ABRF : 1; // Auto baud rate flag 221 | const uint32_t BUSY : 1; // Busy flag 222 | const uint32_t CMF : 1; // Character match flag 223 | const uint32_t SBKF : 1; // Send break flag 224 | const uint32_t RWU : 1; // Receiver wakeup from Mute mode 225 | const uint32_t WUF : 1; // Wakeup from Stop mode flag (F0, L0) 226 | const uint32_t TEACK : 1; // Transmit enable acknowledge flag 227 | const uint32_t REACK : 1; // Receive enable acknowledge flag (F0, L0) 228 | uint32_t : 2; 229 | const uint32_t TCBGT : 1; // Transmission complete before guard time completion (L4) 230 | uint32_t : 6; 231 | }; 232 | 233 | union { 234 | uint32_t r; 235 | Bits b; 236 | }; 237 | }; 238 | 239 | /** Interrupt flag clear register 240 | */ 241 | struct Icr { 242 | Icr(const uint32_t raw=0) { r = raw; } 243 | 244 | struct Bits { 245 | uint32_t PECF : 1; // Parity error clear flag 246 | uint32_t FECF : 1; // Framing error clear flag 247 | uint32_t NCF : 1; // Noise detected clear flag 248 | uint32_t ORECF : 1; // Overrun error clear flag 249 | uint32_t IDLECF : 1; // Idle line detected clear flag 250 | uint32_t : 1; 251 | uint32_t TCCF : 1; // Transmission complete clear flag 252 | uint32_t : 1; 253 | uint32_t LBDFCF : 1; // LIN break detection clear flag 254 | uint32_t CTSCF : 1; // CTS clear flag 255 | uint32_t : 1; 256 | uint32_t RTOCF : 1; // Receiver timeout clear flag 257 | uint32_t EOBFCF : 1; // End of block clear flag 258 | uint32_t : 4; 259 | uint32_t CMCF : 1; // Character match clear flag 260 | uint32_t : 2; 261 | uint32_t WUCF : 1; // Wakeup from Stop mode clear flag (F0, L0) 262 | uint32_t : 11; 263 | }; 264 | union { 265 | uint32_t r; 266 | Bits b; 267 | }; 268 | }; 269 | 270 | /** Receiver data register 271 | */ 272 | struct Rdr { 273 | union { 274 | uint32_t r; 275 | const uint32_t DR; // Data register 276 | const uint16_t DR16; // 16 bit access 277 | }; 278 | }; 279 | 280 | /** Transceiver data register 281 | */ 282 | struct Tdr { 283 | union { 284 | uint32_t r; 285 | uint32_t DR; // Data register 286 | uint16_t DR16; // 16 bit access 287 | }; 288 | }; 289 | 290 | volatile Cr1 CR1; // Control register 1 291 | volatile Cr2 CR2; // Control register 2 292 | volatile Cr3 CR3; // Control register 1 293 | volatile Brr BRR; // Baud rate register 294 | volatile Gtpr GTPR; // Guard time and prescaler register 295 | volatile Rtor RTOR; // Receiver timeout register 296 | volatile Rqr RQR; // Request register 297 | volatile Isr ISR; // Interrupt and status register 298 | volatile Icr ICR; // Interrupt flag clear register 299 | volatile Rdr RDR; // Receiver data register 300 | volatile Tdr TDR; // Transceiver data register 301 | }; 302 | 303 | static inline constexpr Usart &USART(const size_t base) { 304 | return *reinterpret_cast(base); 305 | } 306 | 307 | } 308 | -------------------------------------------------------------------------------- /reg/stm32/_common/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Window watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | * - STM32F1xx 9 | * - STM32F2xx 10 | * - STM32F3xx 11 | * - STM32F4xx 12 | * - STM32F7xx 13 | * - STM32L0xx 14 | * - STM32L1xx 15 | * - STM32L4xx 16 | */ 17 | 18 | #pragma once 19 | 20 | #include 21 | #include 22 | 23 | namespace io { 24 | 25 | struct Wwdg { 26 | /** Control register 27 | */ 28 | struct Cr { 29 | Cr(const uint32_t raw=0) { r = raw; } 30 | 31 | struct Bits { 32 | uint32_t T : 7; // 7-bit counter (MSB to LSB) 33 | uint32_t WDGA : 1; // Activation bit 34 | uint32_t : 24; 35 | }; 36 | 37 | union { 38 | uint32_t r; 39 | Bits b; 40 | }; 41 | }; 42 | 43 | /** Configuration register 44 | */ 45 | struct Cfr { 46 | Cfr(const uint32_t raw=0) { r = raw; } 47 | 48 | struct Bits { 49 | uint32_t T : 7; // 7-bit window value 50 | uint32_t WDGTB : 2; // Timer base 51 | uint32_t EWI : 1; // Early wakeup interrupt 52 | uint32_t : 22; 53 | }; 54 | 55 | struct Wdgtb { 56 | static const uint32_t DIV_1 = 0; 57 | static const uint32_t DIV_2 = 1; 58 | static const uint32_t DIV_4 = 2; 59 | static const uint32_t DIV_8 = 3; 60 | }; 61 | 62 | union { 63 | uint32_t r; 64 | Bits b; 65 | }; 66 | }; 67 | 68 | /** Status register 69 | */ 70 | struct Sr { 71 | Sr(const uint32_t raw=0) { r = raw; } 72 | 73 | struct Bits { 74 | uint32_t EWIF : 1; // Early wakeup interrupt flag 75 | uint32_t : 31; 76 | }; 77 | 78 | union { 79 | uint32_t r; 80 | Bits b; 81 | }; 82 | }; 83 | 84 | volatile Cr CR; // Control register 85 | volatile Cfr CFR; // Configuration register 86 | volatile Sr SR; // Status register 87 | }; 88 | 89 | } 90 | -------------------------------------------------------------------------------- /reg/stm32/f0/adc.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * ADC - Analog Digital Converter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/adc_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t ADC = 0x40012400; 22 | 23 | } 24 | 25 | static Adc &ADC = *reinterpret_cast(base::ADC); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f0/comp.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * COMP - Comparator 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | namespace io { 16 | 17 | struct Comp { 18 | /** Control and status register 19 | */ 20 | struct Csr { 21 | struct Bits { 22 | uint32_t COMP1EN : 1; // Comparator 1 enable 23 | uint32_t COMP1SW1 : 1; // Comparator 1 non inverting input DAC switch 24 | uint32_t COMP1MODE : 2; // Comparator 1 mode 25 | uint32_t COMP1INSEL : 3; // Comparator 1 inverting input selection 26 | uint32_t : 1; 27 | uint32_t COMP1OUTSEL : 3; // Comparator 1 output selection 28 | uint32_t COMP1POL : 1; // Comparator 1 output polarity 29 | uint32_t COMP1HYST : 2; // Comparator 1 hysteresis 30 | const uint32_t COMP1OUT : 1; // Comparator 1 output 31 | uint32_t COMP1LOCK : 1; // Comparator 1 lock 32 | uint32_t COMP2EN : 1; // Comparator 2 enable 33 | uint32_t : 1; 34 | uint32_t COMP2MODE : 2; // Comparator 2 mode 35 | uint32_t COMP2INSEL : 3; // Comparator 2 inverting input selection 36 | uint32_t WNDWEN : 1; // Window mode enable 37 | uint32_t COMP2OUTSEL : 3; // Comparator 2 output selection 38 | uint32_t COMP2POL : 1; // Comparator 2 output polarity 39 | uint32_t COMP2HYST : 2; // Comparator 2 hysteresis 40 | const uint32_t COMP2OUT : 1; // Comparator 2 output 41 | uint32_t COMP2LOCK : 1; // Comparator 2 lock 42 | }; 43 | 44 | union { 45 | uint32_t r; 46 | Bits b; 47 | }; 48 | 49 | struct Compmode { 50 | static const uint32_t HIGH_SPEED = 0; // full power 51 | static const uint32_t MEDIUM_SPEED = 1; // mediaum power 52 | static const uint32_t LOW_SPEED = 2; // low power 53 | static const uint32_t VERY_LOW_SPEED = 3; // ultra-low power 54 | }; 55 | 56 | struct Compoutsel { 57 | static const uint32_t NO_SELECTION = 0; // No selection 58 | static const uint32_t TIM1_BREAK = 1; // Timer 1 break input 59 | static const uint32_t TIM1_INPUT_CAPTURE1 = 2; // Timer 1 input capture 1 60 | static const uint32_t TIM1_OC_REF_CLEAR = 3; // Timer 1 OC ref clear input 61 | static const uint32_t TIM2_INPUT_CAPTURE4 = 4; // Timer 2 input capture 4 62 | static const uint32_t TIM2_OC_REF_CLEAR = 5; // Timer 2 OC ref clear input 63 | static const uint32_t TIM3_INPUT_CAPTURE1 = 6; // Timer 3 input capture 1 64 | static const uint32_t TIM3_OC_REF_CLEAR = 7; // Timer 3 OC ref clear input 65 | }; 66 | 67 | struct Comphyst { 68 | static const uint32_t NO_HYSTERESIS = 0; // No hysteresis 69 | static const uint32_t LOW_HYSTERESIS = 1; // Low hysteresis 70 | static const uint32_t MEDIUM_HYSTERESIS = 2; // Medium hysteresis 71 | static const uint32_t HIGH_HYSTERESIS = 3; // High hysteresis 72 | }; 73 | 74 | struct Comp1insel { 75 | static const uint32_t VREF_1_4 = 0; // 1/4 Vrefint 76 | static const uint32_t VREF_1_2 = 1; // 1/2 Vrefint 77 | static const uint32_t VREF_3_4 = 2; // 3/4 Vrefint 78 | static const uint32_t VREF = 3; // Vrefint 79 | static const uint32_t PA4 = 4; // PA4 (DAC_OUT1) 80 | static const uint32_t PA5 = 5; // PA5 (DAC_OUT2) 81 | static const uint32_t PA0 = 6; // PA0 82 | }; 83 | 84 | struct Comp2insel { 85 | static const uint32_t VREF_1_4 = 0; // 1/4 Vrefint 86 | static const uint32_t VREF_1_2 = 1; // 1/2 Vrefint 87 | static const uint32_t VREF_3_4 = 2; // 3/4 Vrefint 88 | static const uint32_t VREF = 3; // Vrefint 89 | static const uint32_t PA4 = 4; // PA4 (DAC_OUT1) 90 | static const uint32_t PA5 = 5; // PA5 (DAC_OUT2) 91 | static const uint32_t PA2 = 6; // PA2 92 | }; 93 | }; 94 | 95 | volatile Csr CSR; // Control and status register 96 | }; 97 | 98 | namespace base { 99 | 100 | static constexpr size_t COMP = 0x40010000; 101 | 102 | } 103 | 104 | static Comp &COMP = *reinterpret_cast(base::COMP); 105 | 106 | } 107 | -------------------------------------------------------------------------------- /reg/stm32/f0/crc.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * CRC - Cyclic redundancy check calculation unit 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | namespace io { 16 | 17 | struct Crc { 18 | /** Data register 19 | */ 20 | struct Dr { 21 | union { 22 | uint32_t r; 23 | uint32_t DR; // Data register (32-bit) 24 | uint32_t DR32; // Data register (32-bit) 25 | uint16_t DR16; // Data register (16-bit) 26 | uint8_t DR8; // Data register (8-bit) 27 | }; 28 | }; 29 | 30 | /** Independent data register 31 | */ 32 | struct Idr { 33 | struct Bits { 34 | uint32_t IDR : 8; // General-purpose 8-bit data register bits 35 | uint32_t : 24; 36 | }; 37 | 38 | union { 39 | uint32_t r; 40 | Bits b; 41 | uint32_t IDR; // Data register 42 | }; 43 | }; 44 | 45 | /** Control register 46 | */ 47 | struct Cr { 48 | Cr(const uint32_t raw=0) { r = raw; } 49 | 50 | struct Bits { 51 | uint32_t RESET : 1; // RESET bit 52 | uint32_t : 2; 53 | uint32_t POLYSIZE: 2; // Polynomial size (STM32F07x and STM32F09x) 54 | uint32_t REVIN : 2; // Reverse input data 55 | uint32_t REVOUT: 1; // Reverse output data 56 | }; 57 | 58 | struct Polysize { 59 | static const uint32_t POLY_7 = 0; // 7-bit polynomial 60 | static const uint32_t POLY_8 = 1; // 8-bit polynomial 61 | static const uint32_t POLY_16 = 2; // 16-bit polynomial 62 | static const uint32_t POLY_32 = 3; // 32-bit polynomial 63 | }; 64 | 65 | struct Revin { 66 | static const uint32_t NO = 0; // bit order not affected 67 | static const uint32_t REV_8 = 1; // Bit reversal done by word 68 | static const uint32_t REV_16 = 2; // Bit reversal done by half-word 69 | static const uint32_t REV_32 = 3; // Bit reversal done by word 70 | }; 71 | 72 | struct Revout { 73 | static const uint32_t NO = 0; // 7-bit polynomial 74 | static const uint32_t REVERSE = 1; // Bit-reversed output format 75 | }; 76 | 77 | union { 78 | uint32_t r; 79 | Bits b; 80 | }; 81 | }; 82 | 83 | /** Initial CRC value 84 | */ 85 | struct Init { 86 | union { 87 | uint32_t r; 88 | uint32_t INIT; // Programmable initial CRC value 89 | }; 90 | }; 91 | 92 | /** CRC polynomial 93 | */ 94 | struct Pol { 95 | union { 96 | uint32_t r; 97 | uint32_t POL; // Programmable polynomial (RW for: STM32F07x and STM32F09x) 98 | }; 99 | }; 100 | 101 | volatile Dr DR; // Data register 102 | volatile Idr IDR; // Independent data register 103 | volatile Cr CR; // Control register 104 | volatile Init INIT; // Initial CRC value 105 | volatile Pol POL; // CRC polynomial 106 | }; 107 | 108 | namespace base { 109 | 110 | static constexpr size_t CRC = 0x40023000; 111 | 112 | } 113 | 114 | static Crc &CRC = *reinterpret_cast(base::CRC); 115 | 116 | } 117 | -------------------------------------------------------------------------------- /reg/stm32/f0/crs.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * CRS - Clock recovery system 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F04x 8 | * - STM32F07x 9 | * - STM32F09x 10 | */ 11 | 12 | #pragma once 13 | 14 | #include 15 | #include 16 | 17 | namespace io { 18 | 19 | struct Crs { 20 | /** Control register 21 | */ 22 | struct Cr { 23 | Cr(const uint32_t raw=0) { r = raw; } 24 | 25 | struct Bits { 26 | uint32_t SYNCOKIE : 1; // SYNC event OK interrupt enable 27 | uint32_t SYNCWARNIE: 1; // SYNC warning interrupt enable 28 | uint32_t ERRIE : 1; // Synchronization or trimming error interrupt enable 29 | uint32_t ESYNCIE: 1; // Expected SYNC interrupt enable 30 | uint32_t : 1; 31 | uint32_t CEN : 1; // Frequency error counter enable 32 | uint32_t AUTOTRIMEN : 1; // Automatic trimming enable 33 | uint32_t SWSYNC : 1; // Generate software SYNC event 34 | uint32_t TRIM : 6; // HSI48 oscillator smooth trimming 35 | uint32_t : 18; 36 | }; 37 | 38 | union { 39 | uint32_t r; 40 | Bits b; 41 | }; 42 | }; 43 | 44 | /** Configuration register 45 | */ 46 | struct Cfgr { 47 | Cfgr(const uint32_t raw=0) { r = raw; } 48 | 49 | struct Bits { 50 | uint32_t RELOAD : 16; // Counter reload value 51 | uint32_t FELIM: 8; // Frequency error limit 52 | uint32_t SYNCDIV : 3; // SYNC divider 53 | uint32_t : 1; 54 | uint32_t SYNCSRC : 2; // SYNC signal source selection 55 | uint32_t : 1; 56 | uint32_t SYNCPOL: 1; // SYNC polarity selection 57 | }; 58 | 59 | union { 60 | uint32_t r; 61 | Bits b; 62 | }; 63 | }; 64 | 65 | /** Interrupt and status register 66 | */ 67 | struct Isr { 68 | Isr(const uint32_t raw=0) { r = raw; } 69 | 70 | struct Bits { 71 | const uint32_t SYNCOKF : 1; // SYNC event OK flag 72 | const uint32_t SYNCWARNF : 1; // SYNC warning flag 73 | const uint32_t ERRF : 1; // Error flag 74 | const uint32_t ESYNCF : 1; // SYNC flag 75 | const uint32_t : 4; 76 | const uint32_t SYNCERR : 1; // SYNC error 77 | const uint32_t SYNCMISS : 1; // SYNC missed 78 | const uint32_t TRIMOVF : 1; // Trimming overflow or underflow 79 | const uint32_t : 4; 80 | const uint32_t FEDIR : 1; // Frequency error direction 81 | const uint32_t FECAP : 16; // Frequency error capture 82 | }; 83 | 84 | union { 85 | uint32_t r; 86 | Bits b; 87 | }; 88 | }; 89 | 90 | /** Interrupt flag clear register 91 | */ 92 | struct Icr { 93 | Icr(const uint32_t raw=0) { r = raw; } 94 | 95 | struct Bits { 96 | const uint32_t SYNCOKC : 1; // SYNC event OK clear flag 97 | const uint32_t SYNCWARNC : 1; // SYNC warning clear flag 98 | const uint32_t ERRC : 1; // Error clear flag 99 | const uint32_t ESYNCC : 1; // SYNC clear flag 100 | const uint32_t : 28; 101 | }; 102 | 103 | union { 104 | uint32_t r; 105 | Bits b; 106 | }; 107 | }; 108 | 109 | volatile Cr CR; // Control register 110 | volatile Cfgr CFGR; // Configuration register 111 | volatile Isr ISR; // Interrupt and status register 112 | volatile Icr ICR; // Interrupt flag clear register 113 | }; 114 | 115 | namespace base { 116 | 117 | static constexpr size_t CRS = 0x40006c00; 118 | 119 | } 120 | 121 | static Crs &CRS = *reinterpret_cast(base::CRS); 122 | 123 | } 124 | -------------------------------------------------------------------------------- /reg/stm32/f0/dac.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * DAC - Digital-to-analog converter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F05x (single channel) 8 | * - STM32F07x (dual channel) 9 | * - STM32F09x (dual channel) 10 | */ 11 | 12 | #pragma once 13 | 14 | #include 15 | #include 16 | 17 | namespace io { 18 | 19 | struct Dac { 20 | /** Control register 21 | */ 22 | struct Cr { 23 | Cr(const uint32_t raw=0) { r = raw; } 24 | 25 | struct Bits { 26 | uint32_t EN1 : 1; // DAC channel 1 enable 27 | uint32_t BOFF1 : 1; // DAC channel 1 output buffer disable 28 | uint32_t TEN1 : 1; // DAC channel 1 trigger enable 29 | uint32_t TSEL1 : 3; // DAC channel 1 trigger selection 30 | uint32_t WAVE1 : 2; // DAC channel 1 noise / triangle wave generation enable 31 | uint32_t MAMP1 : 4; // DAC channel 1 mask / amplitude selector 32 | uint32_t DMAEN1 : 1; // DAC channel 1 DMAenable 33 | uint32_t DMAUDRIE1 : 1; // DAC channel 1 DMA Under run Interrupt enable 34 | uint32_t : 2; 35 | uint32_t EN2 : 1; // DAC channel 2 enable 36 | uint32_t BOFF2 : 1; // DAC channel 2 output buffer disable 37 | uint32_t TEN2 : 1; // DAC channel 2 trigger enable 38 | uint32_t TSEL2 : 3; // DAC channel 2 trigger selection 39 | uint32_t WAVE2 : 2; // DAC channel 2 noise / triangle wave generation enable 40 | uint32_t MAMP2 : 4; // DAC channel 2 mask / amplitude selector 41 | uint32_t DMAEN2 : 1; // DAC channel 2 DMAenable 42 | uint32_t DMAUDRIE2 : 1; // DAC channel 2 DMA Under run Interrupt enable 43 | uint32_t : 2; 44 | }; 45 | 46 | struct Tsel { 47 | static const uint32_t TIMER_3 = 0; // 48 | static const uint32_t TIMER_6 = 1; // 49 | static const uint32_t TIMER_7 = 2; // 50 | static const uint32_t TIMER_15 = 3; // 51 | static const uint32_t TIMER_2 = 4; // 52 | static const uint32_t EXTI = 6; // 53 | static const uint32_t SW = 7; // 54 | }; 55 | 56 | struct Wave { 57 | static const uint32_t DISABLED = 0; // bit order not affected 58 | static const uint32_t NOISE = 1; // Bit reversal done by word 59 | static const uint32_t TRIANGLE = 2; // Bit reversal done by half-word 60 | }; 61 | 62 | struct Mamp { 63 | static const uint32_t AMP_1 = 0; // Unmask bit 0 of LFSR / triangle amplitude equal to 1 64 | static const uint32_t AMP_3 = 1; // Unmask bits [1:0] of LFSR / triangle amplitude equal to 3 65 | static const uint32_t AMP_7 = 2; // Unmask bits [2:0] of LFSR / triangle amplitude equal to 7 66 | static const uint32_t AMP_15 = 3; // Unmask bits [3:0] of LFSR / triangle amplitude equal to 15 67 | static const uint32_t AMP_31 = 4; // Unmask bits [4:0] of LFSR / triangle amplitude equal to 31 68 | static const uint32_t AMP_63 = 5; // Unmask bits [5:0] of LFSR / triangle amplitude equal to 63 69 | static const uint32_t AMP_127 = 6; // Unmask bits [6:0] of LFSR / triangle amplitude equal to 127 70 | static const uint32_t AMP_255 = 7; // Unmask bits [7:0] of LFSR / triangle amplitude equal to 255 71 | static const uint32_t AMP_511 = 8; // Unmask bits [8:0] of LFSR / triangle amplitude equal to 511 72 | static const uint32_t AMP_1023 = 9; // Unmask bits [9:0] of LFSR / triangle amplitude equal to 1023 73 | static const uint32_t AMP_2047 = 10; // Unmask bits [10:0] of LFSR / triangle amplitude equal to 2047 74 | static const uint32_t AMP_4095 = 11; // Unmask bits [11:0] of LFSR / triangle amplitude equal to 4095 75 | }; 76 | 77 | union { 78 | uint32_t r; 79 | Bits b; 80 | }; 81 | }; 82 | 83 | /** DAC software trigger register 84 | */ 85 | struct Swtrigr { 86 | Swtrigr(const uint32_t raw=0) { r = raw; } 87 | 88 | struct Bits { 89 | uint32_t SWTRIG1 : 1; // DAC channel 1 software trigger 90 | uint32_t SWTRIG2 : 1; // DAC channel 1 software trigger 91 | uint32_t : 30; 92 | }; 93 | 94 | union { 95 | uint32_t r; 96 | Bits b; 97 | }; 98 | }; 99 | 100 | /** DAC channel 1 12-bit right-aligned data holding register 101 | */ 102 | struct Dhr12r1 { 103 | Dhr12r1(const uint32_t raw=0) { r = raw; } 104 | 105 | union { 106 | uint32_t r; 107 | uint32_t DACC1DHR; // DAC channel 1 12-bit right-aligned data 108 | }; 109 | 110 | void set(uint16_t val1) volatile { 111 | DACC1DHR = static_cast(val1); 112 | } 113 | }; 114 | 115 | /** DAC channel 1 12-bit left-aligned data holding register 116 | */ 117 | struct Dhr12l1 { 118 | Dhr12l1(const uint32_t raw=0) { r = raw; } 119 | 120 | union { 121 | uint32_t r; 122 | uint32_t DACC1DHR; // DAC channel 1 12-bit left-aligned data 123 | }; 124 | 125 | void set(uint16_t val1) volatile { 126 | DACC1DHR = static_cast(val1); 127 | } 128 | }; 129 | 130 | /** DAC channel 1 8-bit right-aligned data holding register 131 | */ 132 | struct Dhr8r1 { 133 | Dhr8r1(const uint32_t raw=0) { r = raw; } 134 | 135 | union { 136 | uint32_t r; 137 | uint32_t DACC1DHR; // DAC channel 1 8-bit right-aligned data 138 | }; 139 | 140 | void set(uint8_t val1) volatile { 141 | DACC1DHR = static_cast(val1); 142 | } 143 | }; 144 | 145 | /** DAC channel 2 12-bit right-aligned data holding register 146 | */ 147 | struct Dhr12r2 { 148 | Dhr12r2(const uint32_t raw=0) { r = raw; } 149 | 150 | union { 151 | uint32_t r; 152 | uint32_t DACC2DHR; // DAC channel 2 12-bit right-aligned data 153 | }; 154 | 155 | void set(uint16_t val2) volatile { 156 | DACC2DHR = static_cast(val2); 157 | } 158 | }; 159 | 160 | /** DAC channel 2 12-bit left-aligned data holding register 161 | */ 162 | struct Dhr12l2 { 163 | Dhr12l2(const uint32_t raw=0) { r = raw; } 164 | 165 | union { 166 | uint32_t r; 167 | uint32_t DACC2DHR; // DAC channel 2 12-bit left-aligned data 168 | }; 169 | 170 | void set(uint16_t val2) volatile { 171 | DACC2DHR = static_cast(val2); 172 | } 173 | }; 174 | 175 | /** DAC channel 2 8-bit right-aligned data holding register 176 | */ 177 | struct Dhr8r2 { 178 | Dhr8r2(const uint32_t raw=0) { r = raw; } 179 | 180 | union { 181 | uint32_t r; 182 | uint32_t DACC2DHR; // DAC channel 2 8-bit right-aligned data 183 | }; 184 | 185 | void set(uint8_t val2) volatile { 186 | DACC2DHR = static_cast(val2); 187 | } 188 | }; 189 | 190 | /** Dual DAC 12-bit right-aligned data holding register 191 | */ 192 | struct Dhr12rd { 193 | Dhr12rd(const uint32_t raw=0) { r = raw; } 194 | 195 | struct Bits { 196 | uint32_t DACC1DHR : 16; // DAC channel 1 right-aligned data 197 | uint32_t DACC2DHR : 16; // DAC channel 2 right-aligned data 198 | }; 199 | 200 | union { 201 | uint32_t r; 202 | Bits b; 203 | }; 204 | 205 | void set(uint16_t val1, uint16_t val2) volatile { 206 | Dhr12rd reg(0); 207 | reg.b.DACC1DHR = val1; 208 | reg.b.DACC2DHR = val2; 209 | r = reg.r; 210 | } 211 | }; 212 | 213 | /** Dual DAC 12-bit left-aligned data holding register 214 | */ 215 | struct Dhr12ld { 216 | Dhr12ld(const uint32_t raw=0) { r = raw; } 217 | 218 | struct Bits { 219 | uint32_t DACC1DHR : 16; // DAC channel 1 left-aligned data 220 | uint32_t DACC2DHR : 16; // DAC channel 2 left-aligned data 221 | }; 222 | 223 | union { 224 | uint32_t r; 225 | Bits b; 226 | }; 227 | 228 | void set(uint16_t val1, uint16_t val2) volatile { 229 | Dhr12ld reg(0); 230 | reg.b.DACC1DHR = val1; 231 | reg.b.DACC2DHR = val2; 232 | r = reg.r; 233 | } 234 | }; 235 | 236 | /** Dual DAC 8-bit right-aligned data holding register 237 | */ 238 | struct Dhr8rd { 239 | Dhr8rd(const uint32_t raw=0) { r = raw; } 240 | 241 | struct Bits { 242 | uint32_t DACC1DHR : 8; // DAC channel 1 right-aligned data 243 | uint32_t DACC2DHR : 8; // DAC channel 2 right-aligned data 244 | uint32_t : 16; 245 | }; 246 | 247 | union { 248 | uint32_t r; 249 | Bits b; 250 | }; 251 | 252 | void set(uint8_t val1, uint8_t val2) volatile { 253 | Dhr8rd reg(0); 254 | reg.b.DACC1DHR = val1; 255 | reg.b.DACC2DHR = val2; 256 | r = reg.r; 257 | } 258 | }; 259 | 260 | /** DAC Channel 1 data output register 261 | */ 262 | struct Dhrdor1 { 263 | struct Bits { 264 | const uint32_t DACC1DOR : 16; // DAC channel 1 data output 265 | uint32_t : 16; 266 | }; 267 | 268 | union { 269 | uint32_t r; 270 | Bits b; 271 | }; 272 | }; 273 | 274 | /** DAC Channel 2 data output register 275 | */ 276 | struct Dhrdor2 { 277 | struct Bits { 278 | const uint32_t DACC2DOR : 16; // DAC channel 2 data output 279 | uint32_t : 16; 280 | }; 281 | 282 | union { 283 | uint32_t r; 284 | Bits b; 285 | }; 286 | }; 287 | 288 | /** DAC status register 289 | */ 290 | struct Sr { 291 | struct Bits { 292 | uint32_t : 13; 293 | const uint32_t DMAUDR1 : 1; // DAC channel 2 data output 294 | uint32_t : 15; 295 | const uint32_t DMAUDR2 : 1; // DAC channel 2 data output 296 | uint32_t : 2; 297 | }; 298 | 299 | union { 300 | uint32_t r; 301 | Bits b; 302 | }; 303 | }; 304 | 305 | volatile Cr CR; // Control register 306 | volatile Swtrigr SWTRIGR; // DAC software trigger register 307 | volatile Dhr12r1 DHR12R1; // DAC channel 1 12-bit right-aligned data holding register 308 | volatile Dhr12l1 DHR12L1; // DAC channel 1 12-bit left-aligned data holding register 309 | volatile Dhr8r1 DHR8R1; // DAC channel 1 8-bit right-aligned data holding register 310 | volatile Dhr12r2 DHR12R2; // DAC channel 2 12-bit right-aligned data holding register 311 | volatile Dhr12l2 DHR12L2; // DAC channel 2 12-bit left-aligned data holding register 312 | volatile Dhr8r2 DHR8R2; // DAC channel 2 8-bit right-aligned data holding register 313 | volatile Dhr12rd DHR12RD; // Dual DAC 12-bit right-aligned data holding register 314 | volatile Dhr12ld DHR12LD; // Dual DAC 12-bit left-aligned data holding register 315 | volatile Dhr8rd DHR8RD; // Dual DAC 8-bit right-aligned data holding register 316 | volatile Dhrdor1 DHRDOR1; // DAC Channel 1 data output register 317 | volatile Dhrdor2 DHRDOR2; // DAC Channel 2 data output register 318 | volatile Sr SR; // DAC status register 319 | }; 320 | 321 | namespace base { 322 | 323 | static constexpr size_t DAC = 0x40007400; 324 | 325 | } 326 | 327 | static Dac &DAC = *reinterpret_cast(base::DAC); 328 | 329 | } 330 | -------------------------------------------------------------------------------- /reg/stm32/f0/dma.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * DMA - Direct memory access controller 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/dma_v1.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t DMA1 = 0x40020000; 22 | static const size_t DMA2 = 0x40020400; 23 | 24 | } 25 | 26 | static Dma &DMA1 = *reinterpret_cast(base::DMA1); 27 | static Dma &DMA2 = *reinterpret_cast(base::DMA2); 28 | 29 | } 30 | -------------------------------------------------------------------------------- /reg/stm32/f0/exti.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * EXTI - External interrupt/event controller 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/exti.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t EXTI = 0x40010400; 22 | 23 | } 24 | 25 | static Exti &EXTI = *reinterpret_cast(base::EXTI); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f0/flash.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * FLASH - Flash memory controller 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | namespace io { 16 | 17 | struct Flash { 18 | /** Flash access control register 19 | */ 20 | struct Acr { 21 | Acr(const uint32_t raw=0) { r = raw; } 22 | 23 | struct Bits { 24 | uint32_t LATENCY : 3; // Latency 25 | uint32_t : 1; 26 | uint32_t PRFTBE : 1; // Prefetch buffer enable 27 | const uint32_t PRFTBS : 1; // Prefetch buffer status 28 | uint32_t : 26; 29 | }; 30 | 31 | union { 32 | uint32_t r; 33 | Bits b; 34 | }; 35 | }; 36 | 37 | /** Flash status register 38 | */ 39 | struct Sr { 40 | Sr(const uint32_t raw=0) { r = raw; } 41 | 42 | struct Bits { 43 | const uint32_t BSY : 1; // Busy 44 | uint32_t : 1; 45 | uint32_t PGERR : 1; // Programming error 46 | uint32_t : 1; 47 | uint32_t WRPRTERR : 1; // Write protection error 48 | uint32_t EOP : 1; // End of operation 49 | uint32_t : 26; 50 | }; 51 | 52 | union { 53 | uint32_t r; 54 | Bits b; 55 | }; 56 | }; 57 | 58 | /** Flash control register 59 | */ 60 | struct Cr { 61 | Cr(const uint32_t raw=0) { r = raw; } 62 | 63 | struct Bits { 64 | uint32_t PG : 1; // Programming 65 | uint32_t PER : 1; // Page erase 66 | uint32_t MER : 1; // Mass erase 67 | uint32_t : 1; 68 | uint32_t OPTPG : 1; // Option byte programming 69 | uint32_t OPTER : 1; // Option byte erase 70 | uint32_t STRT : 1; // Start 71 | uint32_t LOCK : 1; // Lock 72 | uint32_t : 1; 73 | uint32_t OPTWRE : 1; // Option byte write enable 74 | uint32_t ERRIE : 1; // Error interrupt enable 75 | uint32_t : 1; 76 | uint32_t EOPIE : 1; // End of operation interrupt enable 77 | uint32_t OBL_LAUNCH : 1; // Force option byte loading 78 | uint32_t : 18; 79 | }; 80 | 81 | union { 82 | uint32_t r; 83 | Bits b; 84 | }; 85 | }; 86 | 87 | /** Flash option byte register 88 | */ 89 | struct Obr { 90 | Obr(const uint32_t raw=0) { r = raw; } 91 | 92 | struct Bits { 93 | const uint32_t OPTERR : 1; // Option byte error 94 | const uint32_t RDPRT : 2; // Read protection level status 95 | uint32_t : 5; 96 | const uint32_t WDG_SW : 1; 97 | const uint32_t RST_STOP : 1; 98 | const uint32_t RST_STDBY : 1; 99 | const uint32_t BOOT0 : 1; 100 | const uint32_t BOOT1 : 1; 101 | const uint32_t VDDA_MONITOR : 1; 102 | const uint32_t RAM_PARITY_CHECK : 1; 103 | const uint32_t BOOT_SEL : 1; 104 | const uint32_t DATA0 : 8; 105 | const uint32_t DATA1 : 8; 106 | }; 107 | 108 | union { 109 | uint32_t r; 110 | Bits b; 111 | }; 112 | }; 113 | 114 | volatile Acr ACR; // Flash access control register 115 | volatile uint32_t KEYR; // Flash key register 116 | volatile uint32_t OPTKEYR; // Flash option key register 117 | volatile Sr SR; // Flash status register 118 | volatile Cr CR; // Flash control register 119 | volatile uint32_t AR; // Flash address register 120 | uint32_t __res0; 121 | volatile Obr OBR; // Flash option byte register 122 | volatile uint32_t WRPR; // Write protection register 123 | 124 | static const size_t BASE = 0x40022000; 125 | }; 126 | 127 | static Flash &FLASH = *reinterpret_cast(Flash::BASE); 128 | 129 | } 130 | -------------------------------------------------------------------------------- /reg/stm32/f0/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x48000000; 22 | static const size_t GPIOB = 0x48000400; 23 | static const size_t GPIOC = 0x48000800; 24 | static const size_t GPIOD = 0x48000c00; 25 | static const size_t GPIOE = 0x48001000; 26 | static const size_t GPIOF = 0x48001400; 27 | 28 | } 29 | 30 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 31 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 32 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 33 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 34 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 35 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 36 | 37 | } 38 | -------------------------------------------------------------------------------- /reg/stm32/f0/i2c.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * I2C - Inter-integrated circuit interface 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/i2c_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t I2C1 = 0x40005400; 22 | static const size_t I2C2 = 0x40005800; 23 | 24 | } 25 | 26 | static I2c &I2C1 = *reinterpret_cast(base::I2C1); 27 | static I2c &I2C2 = *reinterpret_cast(base::I2C2); 28 | 29 | } 30 | -------------------------------------------------------------------------------- /reg/stm32/f0/isr.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * ISR - ISR numbers 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | 14 | namespace io { 15 | 16 | namespace isr { 17 | 18 | static const uint32_t WWDG_isr = 0; 19 | static const uint32_t PVD_isr = 1; 20 | static const uint32_t RTC_isr = 2; 21 | static const uint32_t FLASH_isr = 3; 22 | static const uint32_t RCC_CRS_isr = 4; 23 | static const uint32_t EXTI0_1_isr = 5; 24 | static const uint32_t EXTI2_3_isr = 6; 25 | static const uint32_t EXTI4_15_isr = 7; 26 | static const uint32_t TSC_isr = 8; 27 | static const uint32_t DMA1_CH1_isr = 9; 28 | static const uint32_t DMA1_CH2_3_DMA2_CH1_2_isr = 10; 29 | static const uint32_t DMA1_CH4_5_6_7_DMA2_CH3_4_5_isr = 11; 30 | static const uint32_t ADC_COMP_isr = 12; 31 | static const uint32_t TIM1_BRK_UP_TRG_COM_isr = 13; 32 | static const uint32_t TIM1_CC_isr = 14; 33 | static const uint32_t TIM2_isr = 15; 34 | static const uint32_t TIM3_isr = 16; 35 | static const uint32_t TIM6_DAC_isr = 17; 36 | static const uint32_t TIM7_isr = 18; 37 | static const uint32_t TIM14_isr = 19; 38 | static const uint32_t TIM15_isr = 20; 39 | static const uint32_t TIM16_isr = 21; 40 | static const uint32_t TIM17_isr = 22; 41 | static const uint32_t I2C1_isr = 23; 42 | static const uint32_t I2C2_isr = 24; 43 | static const uint32_t SPI1_isr = 25; 44 | static const uint32_t SPI2_isr = 26; 45 | static const uint32_t USART1_isr = 27; 46 | static const uint32_t USART2_isr = 28; 47 | static const uint32_t USART3_4_5_6_7_8_isr = 29; 48 | static const uint32_t CEC_CAN_isr = 30; 49 | static const uint32_t USB_isr = 31; 50 | 51 | } 52 | 53 | } 54 | -------------------------------------------------------------------------------- /reg/stm32/f0/iwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/iwdg_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t IWDG = 0x40003000; 22 | 23 | } 24 | 25 | static Iwdg &IWDG = *reinterpret_cast(base::IWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f0/pwr.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * PWR - Power control 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | namespace io { 16 | 17 | struct Pwr { 18 | /** Power control register 19 | */ 20 | struct Cr { 21 | Cr(const uint32_t raw=0) { r = raw; } 22 | 23 | struct Bits { 24 | uint32_t LPDS : 1; // Low power deep sleep 25 | uint32_t PDDS : 1; // Power down deep sleep 26 | uint32_t CWUF : 1; // Clear wakeup flag 27 | uint32_t CSBF : 1; // Clear standby flag 28 | uint32_t PVDE : 1; // Power voltage detector enable (F0x1, F0x2, F0x8) 29 | uint32_t PLS : 3; // PVD level selection (F0x1, F0x2, F0x8) 30 | uint32_t DBP : 1; // Disable RTC domain write protection 31 | uint32_t : 23; 32 | }; 33 | 34 | struct Pls { 35 | static const uint32_t PVD_2_2 = 0; 36 | static const uint32_t PVD_2_3 = 1; 37 | static const uint32_t PVD_2_4 = 2; 38 | static const uint32_t PVD_2_5 = 3; 39 | static const uint32_t PVD_2_6 = 4; 40 | static const uint32_t PVD_2_7 = 5; 41 | static const uint32_t PVD_2_8 = 6; 42 | static const uint32_t PVD_2_9 = 7; 43 | }; 44 | 45 | union { 46 | uint32_t r; 47 | Bits b; 48 | }; 49 | }; 50 | 51 | /** Power control status register 52 | */ 53 | struct Csr { 54 | Csr(const uint32_t raw=0) { r = raw; } 55 | 56 | struct Bits { 57 | const uint32_t WUF : 1; // Wakeup flag 58 | const uint32_t SBF : 1; // Standby flag 59 | const uint32_t PVDO : 1; // PVD output (F0x1, F0x2, F0x8) 60 | const uint32_t VREFINTRDY : 1; // VREFINT reference voltage ready (F0x1, F0x2, F0x8) 61 | uint32_t : 4; 62 | uint32_t EWUP1 : 1; // Enable WKUPx pins 63 | uint32_t EWUP2 : 1; 64 | uint32_t EWUP3 : 1; 65 | uint32_t EWUP4 : 1; 66 | uint32_t EWUP5 : 1; 67 | uint32_t EWUP6 : 1; 68 | uint32_t EWUP7 : 1; 69 | uint32_t EWUP8 : 1; 70 | uint32_t : 16; 71 | }; 72 | 73 | union { 74 | uint32_t r; 75 | Bits b; 76 | }; 77 | }; 78 | 79 | volatile Cr CR; // Power control register 80 | volatile Csr CSR; // Power control status register 81 | 82 | }; 83 | 84 | namespace base { 85 | 86 | static const size_t PWR = 0x40007000; 87 | 88 | } 89 | 90 | static Pwr &PWR = *reinterpret_cast(base::PWR); 91 | 92 | } 93 | -------------------------------------------------------------------------------- /reg/stm32/f0/rtc.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * RTC - Real-time clock 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/rtc_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t RTC = 0x40002800; 22 | 23 | } 24 | 25 | static Rtc &RTC = *reinterpret_cast(base::RTC); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f0/spi.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SPI - Serial peripheral interface / inter-IC sound 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/spi_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t SPI1 = 0x40013000; 22 | static const size_t SPI2 = 0x40003800; 23 | 24 | } 25 | 26 | static Spi &SPI1 = *reinterpret_cast(base::SPI1); 27 | static Spi &SPI2 = *reinterpret_cast(base::SPI2); 28 | 29 | } 30 | -------------------------------------------------------------------------------- /reg/stm32/f0/sysmem.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SYSMEM - System memory 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/adc_v2.hpp" 16 | 17 | namespace io { 18 | 19 | struct Sysmem { 20 | 21 | /** Unique device ID 22 | */ 23 | struct Uid { 24 | struct Bits { 25 | const uint16_t X; // x-coordinate 26 | const uint16_t Y; // y-coordinate 27 | const uint8_t WAF; // Wafer number 28 | const uint8_t LOT[7]; // Lot number 29 | }; 30 | 31 | union { 32 | uint32_t r[3]; 33 | Bits b; 34 | }; 35 | }; 36 | 37 | volatile const Uid UID; // Unique device ID (0x1ffff7ac) 38 | volatile const uint16_t TEMP30_CAL; // Temperature sensor ADC raw data at 30 degree C (0x1ffff7b8) 39 | volatile const uint16_t VREFINT_CAL; // Voltage reference ADC raw data at 30 degree C (0x1ffff7ba) 40 | uint16_t __res0[3]; 41 | volatile const uint16_t TEMP110_CAL; // Temperature sensor ADC raw data at 110 degree C (0x1ffff7c2) 42 | uint16_t __res1[4]; 43 | volatile const uint16_t FLASH_SIZE; // Flash memory size in KB (0x1ffff7cc) 44 | 45 | }; 46 | 47 | } 48 | 49 | namespace io { 50 | 51 | namespace base { 52 | 53 | static const size_t SYSMEM = 0x1ffff7ac; 54 | 55 | } 56 | 57 | static Sysmem &SYSMEM = *reinterpret_cast(base::SYSMEM); 58 | 59 | } 60 | -------------------------------------------------------------------------------- /reg/stm32/f0/timer.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * TIMER - Timers 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/timer.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t TIM1 = 0x40012c00; 22 | static const size_t TIM2 = 0x40000000; 23 | static const size_t TIM3 = 0x40000400; 24 | static const size_t TIM6 = 0x40001000; 25 | static const size_t TIM7 = 0x40001400; 26 | static const size_t TIM14 = 0x40002000; 27 | static const size_t TIM15 = 0x40014000; 28 | static const size_t TIM16 = 0x40014400; 29 | static const size_t TIM17 = 0x40014800; 30 | 31 | } 32 | 33 | static Timer &TIM1 = *reinterpret_cast(base::TIM1); 34 | static Timer &TIM2 = *reinterpret_cast(base::TIM2); 35 | static Timer &TIM3 = *reinterpret_cast(base::TIM3); 36 | static Timer &TIM6 = *reinterpret_cast(base::TIM6); 37 | static Timer &TIM7 = *reinterpret_cast(base::TIM7); 38 | static Timer &TIM14 = *reinterpret_cast(base::TIM14); 39 | static Timer &TIM15 = *reinterpret_cast(base::TIM15); 40 | static Timer &TIM16 = *reinterpret_cast(base::TIM16); 41 | static Timer &TIM17 = *reinterpret_cast(base::TIM17); 42 | 43 | } 44 | -------------------------------------------------------------------------------- /reg/stm32/f0/usart.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * USART - Universal synchronous asynchronous receiver transmitter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/usart_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t USART1 = 0x40013800; 22 | static const size_t USART2 = 0x40004400; 23 | static const size_t USART3 = 0x40004800; 24 | static const size_t USART4 = 0x40004c00; 25 | static const size_t USART5 = 0x40005000; 26 | static const size_t USART6 = 0x40011400; 27 | static const size_t USART7 = 0x40011800; 28 | static const size_t USART8 = 0x40011c00; 29 | 30 | } 31 | 32 | static Usart &USART1 = *reinterpret_cast(base::USART1); 33 | static Usart &USART2 = *reinterpret_cast(base::USART2); 34 | static Usart &USART3 = *reinterpret_cast(base::USART3); 35 | static Usart &USART4 = *reinterpret_cast(base::USART4); 36 | static Usart &USART5 = *reinterpret_cast(base::USART5); 37 | static Usart &USART6 = *reinterpret_cast(base::USART6); 38 | static Usart &USART7 = *reinterpret_cast(base::USART7); 39 | static Usart &USART8 = *reinterpret_cast(base::USART8); 40 | 41 | } 42 | -------------------------------------------------------------------------------- /reg/stm32/f0/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f1/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F1xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f2/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F2xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x40020000; 22 | static const size_t GPIOB = 0x40020400; 23 | static const size_t GPIOC = 0x40020800; 24 | static const size_t GPIOD = 0x40020c00; 25 | static const size_t GPIOE = 0x40021000; 26 | static const size_t GPIOF = 0x40021400; 27 | static const size_t GPIOG = 0x40021800; 28 | static const size_t GPIOH = 0x40021c00; 29 | static const size_t GPIOI = 0x40022000; 30 | 31 | } 32 | 33 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 34 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 35 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 36 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 37 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 38 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 39 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 40 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 41 | static Gpio &GPIOI = *reinterpret_cast(base::GPIOI); 42 | 43 | } 44 | -------------------------------------------------------------------------------- /reg/stm32/f2/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F2xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f3/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F3xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x48000000; 22 | static const size_t GPIOB = 0x48000400; 23 | static const size_t GPIOC = 0x48000800; 24 | static const size_t GPIOD = 0x48000c00; 25 | static const size_t GPIOE = 0x48001000; 26 | static const size_t GPIOF = 0x48001400; 27 | static const size_t GPIOG = 0x48001800; 28 | static const size_t GPIOH = 0x48001c00; 29 | 30 | } 31 | 32 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 33 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 34 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 35 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 36 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 37 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 38 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 39 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 40 | 41 | } 42 | -------------------------------------------------------------------------------- /reg/stm32/f3/iwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F3xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/iwdg_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t IWDG = 0x40003000; 22 | 23 | } 24 | 25 | static Iwdg &IWDG = *reinterpret_cast(base::IWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f3/rtc.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * RTC - Real-time clock 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F3xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/rtc_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t RTC = 0x40002800; 22 | 23 | } 24 | 25 | static Rtc &RTC = *reinterpret_cast(base::RTC); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f3/usart.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * USART - Universal synchronous asynchronous receiver transmitter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F3xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/usart_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t USART1 = 0x40013800; 22 | static const size_t USART2 = 0x40004400; 23 | static const size_t USART3 = 0x40004800; 24 | static const size_t UART4 = 0x40004c00; 25 | static const size_t UART5 = 0x40005000; 26 | 27 | } 28 | 29 | static Usart &USART1 = *reinterpret_cast(base::USART1); 30 | static Usart &USART2 = *reinterpret_cast(base::USART2); 31 | static Usart &USART3 = *reinterpret_cast(base::USART3); 32 | static Usart &UART4 = *reinterpret_cast(base::UART4); 33 | static Usart &UART5 = *reinterpret_cast(base::UART5); 34 | 35 | } 36 | -------------------------------------------------------------------------------- /reg/stm32/f3/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F3xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f4/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F4xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x40020000; 22 | static const size_t GPIOB = 0x40020400; 23 | static const size_t GPIOC = 0x40020800; 24 | static const size_t GPIOD = 0x40020c00; 25 | static const size_t GPIOE = 0x40021000; 26 | static const size_t GPIOF = 0x40021400; 27 | static const size_t GPIOG = 0x40021800; 28 | static const size_t GPIOH = 0x40021c00; 29 | static const size_t GPIOI = 0x40022000; 30 | static const size_t GPIOJ = 0x40022400; 31 | static const size_t GPIOK = 0x40022800; 32 | 33 | } 34 | 35 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 36 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 37 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 38 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 39 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 40 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 41 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 42 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 43 | static Gpio &GPIOI = *reinterpret_cast(base::GPIOI); 44 | static Gpio &GPIOJ = *reinterpret_cast(base::GPIOJ); 45 | static Gpio &GPIOK = *reinterpret_cast(base::GPIOK); 46 | 47 | } 48 | -------------------------------------------------------------------------------- /reg/stm32/f4/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F4xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f7/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F7xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x40020000; 22 | static const size_t GPIOB = 0x40020400; 23 | static const size_t GPIOC = 0x40020800; 24 | static const size_t GPIOD = 0x40020c00; 25 | static const size_t GPIOE = 0x40021000; 26 | static const size_t GPIOF = 0x40021400; 27 | static const size_t GPIOG = 0x40021800; 28 | static const size_t GPIOH = 0x40021c00; 29 | static const size_t GPIOI = 0x40022000; 30 | static const size_t GPIOJ = 0x40022400; 31 | static const size_t GPIOK = 0x40022800; 32 | 33 | } 34 | 35 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 36 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 37 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 38 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 39 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 40 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 41 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 42 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 43 | static Gpio &GPIOI = *reinterpret_cast(base::GPIOI); 44 | static Gpio &GPIOJ = *reinterpret_cast(base::GPIOJ); 45 | static Gpio &GPIOK = *reinterpret_cast(base::GPIOK); 46 | 47 | } 48 | -------------------------------------------------------------------------------- /reg/stm32/f7/iwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F7xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/iwdg_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t IWDG = 0x40003000; 22 | 23 | } 24 | 25 | static Iwdg &IWDG = *reinterpret_cast(base::IWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/f7/usart.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * USART - Universal synchronous asynchronous receiver transmitter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F7xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/usart_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t USART1 = 0x40011000; 22 | static const size_t USART2 = 0x40004400; 23 | static const size_t USART3 = 0x40004800; 24 | static const size_t UART4 = 0x40004c00; 25 | static const size_t UART5 = 0x40005000; 26 | static const size_t USART6 = 0x40011400; 27 | static const size_t UART7 = 0x40007800; 28 | static const size_t UART8 = 0x40007C00; 29 | 30 | } 31 | 32 | static Usart &USART1 = *reinterpret_cast(base::USART1); 33 | static Usart &USART2 = *reinterpret_cast(base::USART2); 34 | static Usart &USART3 = *reinterpret_cast(base::USART3); 35 | static Usart &UART4 = *reinterpret_cast(base::UART4); 36 | static Usart &UART5 = *reinterpret_cast(base::UART5); 37 | static Usart &USART6 = *reinterpret_cast(base::USART6); 38 | static Usart &UART7 = *reinterpret_cast(base::UART7); 39 | static Usart &UART8 = *reinterpret_cast(base::UART8); 40 | 41 | } 42 | -------------------------------------------------------------------------------- /reg/stm32/f7/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F7xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/h7/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32H7xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x58020000; 22 | static const size_t GPIOB = 0x58020400; 23 | static const size_t GPIOC = 0x58020800; 24 | static const size_t GPIOD = 0x58020c00; 25 | static const size_t GPIOE = 0x58021000; 26 | static const size_t GPIOF = 0x58021400; 27 | static const size_t GPIOG = 0x58021800; 28 | static const size_t GPIOH = 0x58021c00; 29 | static const size_t GPIOI = 0x58022000; 30 | static const size_t GPIOJ = 0x58022400; 31 | static const size_t GPIOK = 0x58022800; 32 | 33 | } 34 | 35 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 36 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 37 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 38 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 39 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 40 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 41 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 42 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 43 | static Gpio &GPIOI = *reinterpret_cast(base::GPIOI); 44 | static Gpio &GPIOJ = *reinterpret_cast(base::GPIOJ); 45 | static Gpio &GPIOK = *reinterpret_cast(base::GPIOK); 46 | 47 | } 48 | -------------------------------------------------------------------------------- /reg/stm32/h7/iwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32H7xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/iwdg_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t IWDG = 0x58004800; 22 | 23 | } 24 | 25 | static Iwdg &IWDG = *reinterpret_cast(base::IWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/l0/adc.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * ADC - Analog Digital Converter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/adc_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t ADC = 0x40012400; 22 | 23 | } 24 | 25 | static Adc &ADC = *reinterpret_cast(base::ADC); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/l0/dma.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * DMA - Direct memory access controller 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/dma_v1.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t DMA1 = 0x40026000; 22 | static const size_t DMA2 = 0x40026400; 23 | 24 | } 25 | 26 | static Dma &DMA1 = *reinterpret_cast(base::DMA1); 27 | static Dma &DMA2 = *reinterpret_cast(base::DMA2); 28 | 29 | } 30 | -------------------------------------------------------------------------------- /reg/stm32/l0/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x50000000; 22 | static const size_t GPIOB = 0x50000400; 23 | static const size_t GPIOC = 0x50000800; 24 | static const size_t GPIOD = 0x50000c00; 25 | static const size_t GPIOE = 0x50001000; 26 | static const size_t GPIOH = 0x50001c00; 27 | 28 | } 29 | 30 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 31 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 32 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 33 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 34 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 35 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 36 | 37 | } 38 | -------------------------------------------------------------------------------- /reg/stm32/l0/i2c.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * I2C - Inter-integrated circuit interface 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/i2c_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t I2C1 = 0x40005400; 22 | static const size_t I2C2 = 0x40005800; 23 | static const size_t I2C3 = 0x40007800; 24 | 25 | } 26 | 27 | static I2c &I2C1 = *reinterpret_cast(base::I2C1); 28 | static I2c &I2C2 = *reinterpret_cast(base::I2C2); 29 | static I2c &I2C3 = *reinterpret_cast(base::I2C3); 30 | 31 | } 32 | -------------------------------------------------------------------------------- /reg/stm32/l0/iwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/iwdg_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t IWDG = 0x40003000; 22 | 23 | } 24 | 25 | static Iwdg &IWDG = *reinterpret_cast(base::IWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/l0/spi.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * SPI - Serial peripheral interface / inter-IC sound 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/spi_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t SPI1 = 0x40013000; 22 | static const size_t SPI2 = 0x40003800; 23 | 24 | } 25 | 26 | static Spi &SPI1 = *reinterpret_cast(base::SPI1); 27 | static Spi &SPI2 = *reinterpret_cast(base::SPI2); 28 | 29 | } 30 | -------------------------------------------------------------------------------- /reg/stm32/l0/usart.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * USART - Universal synchronous asynchronous receiver transmitter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/usart_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t USART1 = 0x40013800; 22 | static const size_t USART2 = 0x40004400; 23 | static const size_t USART4 = 0x40004c00; 24 | static const size_t USART5 = 0x40005000; 25 | 26 | } 27 | 28 | static Usart &USART1 = *reinterpret_cast(base::USART1); 29 | static Usart &USART2 = *reinterpret_cast(base::USART2); 30 | static Usart &USART4 = *reinterpret_cast(base::USART4); 31 | static Usart &USART5 = *reinterpret_cast(base::USART5); 32 | 33 | } 34 | -------------------------------------------------------------------------------- /reg/stm32/l0/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L0xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/l1/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L1xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x40020000; 22 | static const size_t GPIOB = 0x40020400; 23 | static const size_t GPIOC = 0x40020800; 24 | static const size_t GPIOD = 0x40020c00; 25 | static const size_t GPIOE = 0x40021000; 26 | static const size_t GPIOF = 0x40021400; 27 | static const size_t GPIOG = 0x40021800; 28 | static const size_t GPIOH = 0x40021c00; 29 | 30 | } 31 | 32 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 33 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 34 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 35 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 36 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 37 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 38 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 39 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 40 | 41 | } 42 | -------------------------------------------------------------------------------- /reg/stm32/l1/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L1xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/l4/gpio.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * GPIO - General purpose and alternate function I/Os 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L4xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/gpio_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t GPIOA = 0x48000000; 22 | static const size_t GPIOB = 0x48000400; 23 | static const size_t GPIOC = 0x48000800; 24 | static const size_t GPIOD = 0x48000c00; 25 | static const size_t GPIOE = 0x48001000; 26 | static const size_t GPIOF = 0x48001400; 27 | static const size_t GPIOG = 0x48001800; 28 | static const size_t GPIOH = 0x48001c00; 29 | static const size_t GPIOI = 0x48002000; 30 | 31 | } 32 | 33 | static Gpio &GPIOA = *reinterpret_cast(base::GPIOA); 34 | static Gpio &GPIOB = *reinterpret_cast(base::GPIOB); 35 | static Gpio &GPIOC = *reinterpret_cast(base::GPIOC); 36 | static Gpio &GPIOD = *reinterpret_cast(base::GPIOD); 37 | static Gpio &GPIOE = *reinterpret_cast(base::GPIOE); 38 | static Gpio &GPIOF = *reinterpret_cast(base::GPIOF); 39 | static Gpio &GPIOG = *reinterpret_cast(base::GPIOG); 40 | static Gpio &GPIOH = *reinterpret_cast(base::GPIOH); 41 | static Gpio &GPIOI = *reinterpret_cast(base::GPIOI); 42 | 43 | } 44 | -------------------------------------------------------------------------------- /reg/stm32/l4/iwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * IWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L4xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/iwdg_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t IWDG = 0x40003000; 22 | 23 | } 24 | 25 | static Iwdg &IWDG = *reinterpret_cast(base::IWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /reg/stm32/l4/usart.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * USART - Universal synchronous asynchronous receiver transmitter 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32F3xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/usart_v2.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static const size_t USART1 = 0x40013800; 22 | static const size_t USART2 = 0x40004400; 23 | static const size_t USART3 = 0x40004800; 24 | static const size_t UART4 = 0x40004c00; 25 | static const size_t UART5 = 0x40005000; 26 | 27 | } 28 | 29 | static Usart &USART1 = *reinterpret_cast(base::USART1); 30 | static Usart &USART2 = *reinterpret_cast(base::USART2); 31 | static Usart &USART3 = *reinterpret_cast(base::USART3); 32 | static Usart &UART4 = *reinterpret_cast(base::UART4); 33 | static Usart &UART5 = *reinterpret_cast(base::UART5); 34 | 35 | } 36 | -------------------------------------------------------------------------------- /reg/stm32/l4/wwdg.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Peripheral Definition File 3 | * 4 | * WWDG - Independent watchdog 5 | * 6 | * MCUs containing this peripheral: 7 | * - STM32L4xx 8 | */ 9 | 10 | #pragma once 11 | 12 | #include 13 | #include 14 | 15 | #include "io/reg/stm32/_common/wwdg.hpp" 16 | 17 | namespace io { 18 | 19 | namespace base { 20 | 21 | static constexpr size_t WWDG = 0x40002c00; 22 | 23 | } 24 | 25 | static Wwdg &WWDG = *reinterpret_cast(base::WWDG); 26 | 27 | } 28 | -------------------------------------------------------------------------------- /startup/_common/bss.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Functions for setup BSS memory 3 | * (zero and uninitialized static variables) 4 | */ 5 | 6 | #pragma once 7 | 8 | // bss 9 | extern unsigned __bss_start; 10 | extern unsigned __bss_end; 11 | 12 | /** Zero static variables with zero or undefined value 13 | */ 14 | inline void zero_bss() { 15 | unsigned *dst = &__bss_start; 16 | while (dst < &__bss_end) { 17 | *dst++ = 0; 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /startup/_common/data.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Functions for setup DATA memory 3 | * (non-zero initialized static variables) 4 | */ 5 | 6 | #pragma once 7 | 8 | // data 9 | extern unsigned __data_start; 10 | extern unsigned __data_end; 11 | // data load 12 | extern unsigned __data_load; 13 | 14 | /** Copy statically defined variables 15 | */ 16 | inline void copy_data() { 17 | unsigned *src = &__data_load; 18 | unsigned *dst = &__data_start; 19 | while (dst < &__data_end) { 20 | *dst++ = *src++; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /startup/_common/fini.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Functions for setup static objects 3 | */ 4 | 5 | #pragma once 6 | 7 | #include "io/lib/io_def.hpp" 8 | 9 | // destructors array 10 | extern ptr_func_t __fini_array_start[]; 11 | extern ptr_func_t __fini_array_end[]; 12 | 13 | /** call destructors for static objects 14 | */ 15 | inline void call_fini_array() { 16 | auto array = __fini_array_start; 17 | while (array < __fini_array_end) { 18 | (*array)(); 19 | array++; 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /startup/_common/heap.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Functions for setup HEAP memory 3 | */ 4 | 5 | #pragma once 6 | 7 | // heap start 8 | extern unsigned __heap_start; 9 | 10 | /** Clear/fill with pattern content of HEAP memory 11 | */ 12 | inline void fill_heap(unsigned fill=0x45455246) { 13 | unsigned *dst = &__heap_start; 14 | unsigned *msp_reg; 15 | __asm__("mrs %0, msp\n" : "=r" (msp_reg) ); 16 | while (dst < msp_reg) { 17 | *dst++ = fill; 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /startup/_common/init.hpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Functions for setup static objects 3 | */ 4 | 5 | #pragma once 6 | 7 | #include "io/lib/io_def.hpp" 8 | 9 | // constructors array 10 | extern ptr_func_t __preinit_array_start[]; 11 | extern ptr_func_t __preinit_array_end[]; 12 | extern ptr_func_t __init_array_start[]; 13 | extern ptr_func_t __init_array_end[]; 14 | 15 | /** call constructors for static objects 16 | */ 17 | inline void call_init_array() { 18 | auto array = __preinit_array_start; 19 | while (array < __preinit_array_end) { 20 | (*array)(); 21 | array++; 22 | } 23 | 24 | array = __init_array_start; 25 | while (array < __init_array_end) { 26 | (*array)(); 27 | array++; 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /startup/stm32/f0.cpp: -------------------------------------------------------------------------------- 1 | /** 2 | * Start-up code 3 | */ 4 | 5 | #include "io/lib/main_app.hpp" 6 | #include "io/startup/_common/data.hpp" 7 | #include "io/startup/_common/bss.hpp" 8 | #include "io/startup/_common/heap.hpp" 9 | #include "io/startup/_common/init.hpp" 10 | #include "io/startup/_common/fini.hpp" 11 | 12 | void RESET_handler() { 13 | copy_data(); 14 | zero_bss(); 15 | fill_heap(); 16 | call_init_array(); 17 | // run application 18 | main_app(); 19 | // call destructors for static instances 20 | call_fini_array(); 21 | // stop 22 | while (true); 23 | } 24 | --------------------------------------------------------------------------------